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[binutils, Arm] Add support for shift instructions in MVE
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24 #include <assert.h>
25
26 #include "disassemble.h"
27 #include "opcode/arm.h"
28 #include "opintl.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
32
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
35 #include "libcoff.h"
36 #include "bfd.h"
37 #include "elf-bfd.h"
38 #include "elf/internal.h"
39 #include "elf/arm.h"
40 #include "mach-o.h"
41
42 /* FIXME: Belongs in global header. */
43 #ifndef strneq
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45 #endif
46
47 /* Cached mapping symbol state. */
48 enum map_type
49 {
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53 };
54
55 struct arm_private_data
56 {
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
68 bfd_vma last_mapping_addr;
69 };
70
71 enum mve_instructions
72 {
73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
231 MVE_VMAX,
232 MVE_VMAXA,
233 MVE_VMAXNM_FP,
234 MVE_VMAXNMA_FP,
235 MVE_VMAXNMV_FP,
236 MVE_VMAXNMAV_FP,
237 MVE_VMAXV,
238 MVE_VMAXAV,
239 MVE_VMIN,
240 MVE_VMINA,
241 MVE_VMINNM_FP,
242 MVE_VMINNMA_FP,
243 MVE_VMINNMV_FP,
244 MVE_VMINNMAV_FP,
245 MVE_VMINV,
246 MVE_VMINAV,
247 MVE_VMLA,
248 MVE_VMUL_FP_T1,
249 MVE_VMUL_FP_T2,
250 MVE_VMUL_VEC_T1,
251 MVE_VMUL_VEC_T2,
252 MVE_VMULH,
253 MVE_VRMULH,
254 MVE_VNEG_FP,
255 MVE_VNEG_VEC,
256 MVE_VPNOT,
257 MVE_VPSEL,
258 MVE_VQABS,
259 MVE_VQADD_T1,
260 MVE_VQADD_T2,
261 MVE_VQSUB_T1,
262 MVE_VQSUB_T2,
263 MVE_VQNEG,
264 MVE_VREV16,
265 MVE_VREV32,
266 MVE_VREV64,
267 MVE_LSLL,
268 MVE_LSLLI,
269 MVE_LSRL,
270 MVE_ASRL,
271 MVE_ASRLI,
272 MVE_SQRSHRL,
273 MVE_SQRSHR,
274 MVE_UQRSHL,
275 MVE_UQRSHLL,
276 MVE_UQSHL,
277 MVE_UQSHLL,
278 MVE_URSHRL,
279 MVE_URSHR,
280 MVE_SRSHRL,
281 MVE_SRSHR,
282 MVE_SQSHLL,
283 MVE_SQSHL,
284 MVE_NONE
285 };
286
287 enum mve_unpredictable
288 {
289 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
290 */
291 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
292 fcB = 1 (vpt). */
293 UNPRED_R13, /* Unpredictable because r13 (sp) or
294 r15 (sp) used. */
295 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
296 UNPRED_Q_GT_4, /* Unpredictable because
297 vec reg start > 4 (vld4/st4). */
298 UNPRED_Q_GT_6, /* Unpredictable because
299 vec reg start > 6 (vld2/st2). */
300 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
301 and WB bit = 1. */
302 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
303 equal. */
304 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
305 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
306 same. */
307 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
308 size = 1. */
309 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
310 size = 2. */
311 UNPRED_NONE /* No unpredictable behavior. */
312 };
313
314 enum mve_undefined
315 {
316 UNDEF_SIZE, /* undefined size. */
317 UNDEF_SIZE_0, /* undefined because size == 0. */
318 UNDEF_SIZE_2, /* undefined because size == 2. */
319 UNDEF_SIZE_3, /* undefined because size == 3. */
320 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
321 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
322 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
323 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
324 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
325 size == 0. */
326 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
327 size == 1. */
328 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
329 UNDEF_VCVT_IMM6, /* imm6 < 32. */
330 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
331 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
332 op1 == (0 or 1). */
333 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
334 op2 == 0 and op1 == (0 or 1). */
335 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
336 in {0xx1, x0x1}. */
337 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
338 UNDEF_NONE /* no undefined behavior. */
339 };
340
341 struct opcode32
342 {
343 arm_feature_set arch; /* Architecture defining this insn. */
344 unsigned long value; /* If arch is 0 then value is a sentinel. */
345 unsigned long mask; /* Recognise insn if (op & mask) == value. */
346 const char * assembler; /* How to disassemble this insn. */
347 };
348
349 /* MVE opcodes. */
350
351 struct mopcode32
352 {
353 arm_feature_set arch; /* Architecture defining this insn. */
354 enum mve_instructions mve_op; /* Specific mve instruction for faster
355 decoding. */
356 unsigned long value; /* If arch is 0 then value is a sentinel. */
357 unsigned long mask; /* Recognise insn if (op & mask) == value. */
358 const char * assembler; /* How to disassemble this insn. */
359 };
360
361 enum isa {
362 ANY,
363 T32,
364 ARM
365 };
366
367
368 /* Shared (between Arm and Thumb mode) opcode. */
369 struct sopcode32
370 {
371 enum isa isa; /* Execution mode instruction availability. */
372 arm_feature_set arch; /* Architecture defining this insn. */
373 unsigned long value; /* If arch is 0 then value is a sentinel. */
374 unsigned long mask; /* Recognise insn if (op & mask) == value. */
375 const char * assembler; /* How to disassemble this insn. */
376 };
377
378 struct opcode16
379 {
380 arm_feature_set arch; /* Architecture defining this insn. */
381 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
382 const char *assembler; /* How to disassemble this insn. */
383 };
384
385 /* print_insn_coprocessor recognizes the following format control codes:
386
387 %% %
388
389 %c print condition code (always bits 28-31 in ARM mode)
390 %q print shifter argument
391 %u print condition code (unconditional in ARM mode,
392 UNPREDICTABLE if not AL in Thumb)
393 %A print address for ldc/stc/ldf/stf instruction
394 %B print vstm/vldm register list
395 %C print vscclrm register list
396 %I print cirrus signed shift immediate: bits 0..3|4..6
397 %J print register for VLDR instruction
398 %K print address for VLDR instruction
399 %F print the COUNT field of a LFM/SFM instruction.
400 %P print floating point precision in arithmetic insn
401 %Q print floating point precision in ldf/stf insn
402 %R print floating point rounding mode
403
404 %<bitfield>c print as a condition code (for vsel)
405 %<bitfield>r print as an ARM register
406 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
407 %<bitfield>ru as %<>r but each u register must be unique.
408 %<bitfield>d print the bitfield in decimal
409 %<bitfield>k print immediate for VFPv3 conversion instruction
410 %<bitfield>x print the bitfield in hex
411 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
412 %<bitfield>f print a floating point constant if >7 else a
413 floating point register
414 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
415 %<bitfield>g print as an iWMMXt 64-bit register
416 %<bitfield>G print as an iWMMXt general purpose or control register
417 %<bitfield>D print as a NEON D register
418 %<bitfield>Q print as a NEON Q register
419 %<bitfield>V print as a NEON D or Q register
420 %<bitfield>E print a quarter-float immediate value
421
422 %y<code> print a single precision VFP reg.
423 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
424 %z<code> print a double precision VFP reg
425 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
426
427 %<bitfield>'c print specified char iff bitfield is all ones
428 %<bitfield>`c print specified char iff bitfield is all zeroes
429 %<bitfield>?ab... select from array of values in big endian order
430
431 %L print as an iWMMXt N/M width field.
432 %Z print the Immediate of a WSHUFH instruction.
433 %l like 'A' except use byte offsets for 'B' & 'H'
434 versions.
435 %i print 5-bit immediate in bits 8,3..0
436 (print "32" when 0)
437 %r print register offset address for wldt/wstr instruction. */
438
439 enum opcode_sentinel_enum
440 {
441 SENTINEL_IWMMXT_START = 1,
442 SENTINEL_IWMMXT_END,
443 SENTINEL_GENERIC_START
444 } opcode_sentinels;
445
446 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
447 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
448 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
449 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
450
451 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
452
453 static const struct sopcode32 coprocessor_opcodes[] =
454 {
455 /* XScale instructions. */
456 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
457 0x0e200010, 0x0fff0ff0,
458 "mia%c\tacc0, %0-3r, %12-15r"},
459 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
460 0x0e280010, 0x0fff0ff0,
461 "miaph%c\tacc0, %0-3r, %12-15r"},
462 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
463 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
464 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
465 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
466 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
467 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
468
469 /* Intel Wireless MMX technology instructions. */
470 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
471 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
472 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
473 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
474 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
475 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
476 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
477 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
478 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
479 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
480 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
481 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
482 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
483 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
484 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
485 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
486 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
487 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
488 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
489 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
490 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
491 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
492 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
493 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
494 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
495 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
496 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
497 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
498 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
499 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
500 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
501 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
502 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
503 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
504 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
505 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
506 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
507 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
508 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
509 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
510 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
511 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
512 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
513 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
514 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
515 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
516 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
517 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
518 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
519 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
520 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
521 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
522 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
523 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
524 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
525 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
526 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
527 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
528 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
529 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
530 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
531 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
532 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
533 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
534 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
535 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
536 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
537 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
538 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
539 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
540 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
541 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
542 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
544 0x0e800120, 0x0f800ff0,
545 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
547 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
549 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
551 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
552 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
553 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
554 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
555 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
556 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
557 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
558 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
559 0x0e8000a0, 0x0f800ff0,
560 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
562 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
564 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
566 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
568 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
569 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
570 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
571 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
572 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
573 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
574 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
575 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
576 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
577 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
578 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
579 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
580 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
581 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
582 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
583 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
584 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
585 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
586 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
587 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
588 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
589 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
590 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
591 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
592 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
593 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
594 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
595 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
596 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
597 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
598 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
599 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
600 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
601 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
602 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
603 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
604 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
605 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
606 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
607 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
608 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
609 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
610 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
611 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
612 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
613 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
614 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
615 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
616 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
617 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
618 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
619 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
620 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
621 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
622 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
623 {ANY, ARM_FEATURE_CORE_LOW (0),
624 SENTINEL_IWMMXT_END, 0, "" },
625
626 /* Floating point coprocessor (FPA) instructions. */
627 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
628 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
629 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
630 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
631 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
632 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
633 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
634 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
635 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
636 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
637 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
638 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
639 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
640 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
641 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
642 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
643 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
644 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
645 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
646 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
647 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
648 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
649 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
650 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
651 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
652 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
653 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
654 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
655 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
656 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
657 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
658 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
659 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
660 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
661 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
662 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
663 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
664 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
665 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
666 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
667 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
668 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
669 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
670 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
671 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
672 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
673 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
674 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
675 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
676 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
677 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
678 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
679 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
680 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
681 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
682 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
683 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
684 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
685 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
686 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
687 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
688 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
689 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
690 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
691 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
692 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
693 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
694 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
695 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
696 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
697 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
698 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
699 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
700 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
701 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
702 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
703 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
704 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
705 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
706 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
707 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
708 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
709 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
710 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
711 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
712 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
713
714 /* Armv8.1-M Mainline instructions. */
715 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
716 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
717 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
718 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
719
720 /* ARMv8-M Mainline Security Extensions instructions. */
721 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
722 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
723 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
724 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
725
726 /* Register load/store. */
727 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
728 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
729 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
730 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
731 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
732 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
733 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
734 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
735 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
736 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
737 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
738 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
739 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
740 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
741 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
742 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
743 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
744 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
745 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
746 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
747 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
748 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
749 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
750 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
751 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
752 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
753 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
754 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
755 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
756 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
757 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
758 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
759 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
760 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
761 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
762 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
763
764 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
765 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
766 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
767 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
768 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
769 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
770 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
771 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
772
773 /* Data transfer between ARM and NEON registers. */
774 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
775 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
776 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
777 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
778 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
779 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
780 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
781 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
782 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
783 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
784 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
785 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
786 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
787 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
788 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
789 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
790 /* Half-precision conversion instructions. */
791 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
792 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
793 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
794 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
795 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
796 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
797 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
798 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
799
800 /* Floating point coprocessor (VFP) instructions. */
801 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
802 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
803 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
804 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
805 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
806 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
807 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
808 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
809 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
810 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
812 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
814 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
815 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
816 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
818 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
820 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
822 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
824 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
826 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
828 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
829 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
830 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
831 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
832 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
833 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
834 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
835 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
836 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
838 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
840 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
842 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
843 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
844 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
845 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
846 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
847 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
848 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
849 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
850 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
851 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
852 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
853 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
854 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
855 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
856 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
857 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
858 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
859 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
860 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
861 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
862 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
863 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
864 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
865 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
866 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
867 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
868 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
869 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
870 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
871 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
872 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
873 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
874 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
875 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
876 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
877 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
878 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
879 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
880 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
881 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
882 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
883 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
884 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
885 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
886 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
887 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
888 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
889 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
890 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
891 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
892 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
893 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
894 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
895 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
896 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
897 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
898 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
899 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
900 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
901 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
902 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
903 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
904 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
905 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
906 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
907 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
908 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
909 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
910 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
911 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
912 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
913 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
914 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
915 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
916 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
917 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
918 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
919 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
920 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
921 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
922 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
923 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
924 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
925 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
926 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
927 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
928 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
929 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
930 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
931 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
932 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
933 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
934 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
935 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
936 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
937 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
938 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
939
940 /* Cirrus coprocessor instructions. */
941 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
942 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
943 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
944 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
945 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
946 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
947 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
948 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
949 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
950 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
951 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
952 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
953 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
954 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
955 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
956 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
957 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
958 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
959 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
960 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
961 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
962 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
963 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
964 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
965 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
966 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
967 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
968 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
969 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
970 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
971 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
972 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
973 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
974 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
975 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
976 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
977 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
978 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
979 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
980 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
981 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
982 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
983 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
984 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
985 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
986 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
987 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
988 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
989 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
990 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
991 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
992 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
993 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
994 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
995 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
996 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
997 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
998 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
999 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1000 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
1001 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1002 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
1003 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1004 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
1005 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1006 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
1007 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1008 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
1009 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1010 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
1011 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1012 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
1013 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1014 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
1015 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1016 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
1017 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1018 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
1019 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1020 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
1021 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1022 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
1023 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1024 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
1025 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1026 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
1027 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1028 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1029 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1030 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1031 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1032 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1033 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1034 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1035 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1036 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1037 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1038 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1039 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1040 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1041 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1042 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1043 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1044 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1045 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1046 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1047 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1048 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1049 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1050 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1051 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1052 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1053 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1054 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1055 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1056 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1057 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1058 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1059 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1060 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1061 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1062 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1063 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1064 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1065 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1066 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1067 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1068 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1069 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1070 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1071 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1072 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1073 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1074 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1075 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1076 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1077 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1078 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1079 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1080 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1081 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1082 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1083 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1084 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1085 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1086 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1087 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1088 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1089 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1090 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1091 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1092 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1093 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1094 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1095 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1096 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1097 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1098 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1099 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1100 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1101 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1102 0x0e000600, 0x0ff00f10,
1103 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1104 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1105 0x0e100600, 0x0ff00f10,
1106 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1107 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1108 0x0e200600, 0x0ff00f10,
1109 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1110 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1111 0x0e300600, 0x0ff00f10,
1112 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1113
1114 /* VFP Fused multiply add instructions. */
1115 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1116 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1117 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1118 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1119 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1120 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1121 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1122 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1123 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1124 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1125 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1126 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1127 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1128 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1129 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1130 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1131
1132 /* FP v5. */
1133 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1134 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1135 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1136 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1137 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1138 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1139 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1140 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1141 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1142 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1143 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1144 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1145 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1146 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1147 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1148 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1149 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1150 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1151 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1152 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1153 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1154 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1155 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1156 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1157
1158 /* Generic coprocessor instructions. */
1159 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1160 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1161 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1162 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1163 0x0c500000, 0x0ff00000,
1164 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1165 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1166 0x0e000000, 0x0f000010,
1167 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1168 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1169 0x0e10f010, 0x0f10f010,
1170 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1171 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1172 0x0e100010, 0x0f100010,
1173 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1174 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1175 0x0e000010, 0x0f100010,
1176 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1177 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1178 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1179 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1180 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1181
1182 /* V6 coprocessor instructions. */
1183 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1184 0xfc500000, 0xfff00000,
1185 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1186 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1187 0xfc400000, 0xfff00000,
1188 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1189
1190 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1191 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1192 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1193 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1194 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1195 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1196 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1197 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1198 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1199 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1200 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1201 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1202 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1203 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1204 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1205 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1206 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1207 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1208 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1209 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1210 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1211
1212 /* Dot Product instructions in the space of coprocessor 13. */
1213 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1214 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1215 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1216 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1217
1218 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1219 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1220 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1221 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1222 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1223 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1224 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1225 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1226 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1227 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1228 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1229 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1230 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1231 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1232 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1233 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1234 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1235
1236 /* V5 coprocessor instructions. */
1237 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1238 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1239 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1240 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1241 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1242 0xfe000000, 0xff000010,
1243 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1244 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1245 0xfe000010, 0xff100010,
1246 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1247 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1248 0xfe100010, 0xff100010,
1249 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1250
1251 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1252 cp_num: bit <11:8> == 0b1001.
1253 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1254 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1255 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1256 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1257 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1258 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1259 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1260 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1261 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1262 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1263 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1264 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1265 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1266 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1267 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1268 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1269 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1270 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1271 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1272 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1273 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1274 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1275 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1276 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1277 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1278 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1279 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1280 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1281 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1282 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1283 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1284 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1285 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1286 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1287 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1288 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1289 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1290 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1291 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1292 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1293 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1294 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1295 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1296 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1297 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1298 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1299 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1300 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1301 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1302 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1303 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1304 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1305 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1306 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1307 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1308 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1309 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1310 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1311 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1312 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1313 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1314 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1315 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1316 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1317 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1318 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1319 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1320 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1321 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1322 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1323 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1324
1325 /* ARMv8.3 javascript conversion instruction. */
1326 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1327 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1328
1329 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1330 };
1331
1332 /* Neon opcode table: This does not encode the top byte -- that is
1333 checked by the print_insn_neon routine, as it depends on whether we are
1334 doing thumb32 or arm32 disassembly. */
1335
1336 /* print_insn_neon recognizes the following format control codes:
1337
1338 %% %
1339
1340 %c print condition code
1341 %u print condition code (unconditional in ARM mode,
1342 UNPREDICTABLE if not AL in Thumb)
1343 %A print v{st,ld}[1234] operands
1344 %B print v{st,ld}[1234] any one operands
1345 %C print v{st,ld}[1234] single->all operands
1346 %D print scalar
1347 %E print vmov, vmvn, vorr, vbic encoded constant
1348 %F print vtbl,vtbx register list
1349
1350 %<bitfield>r print as an ARM register
1351 %<bitfield>d print the bitfield in decimal
1352 %<bitfield>e print the 2^N - bitfield in decimal
1353 %<bitfield>D print as a NEON D register
1354 %<bitfield>Q print as a NEON Q register
1355 %<bitfield>R print as a NEON D or Q register
1356 %<bitfield>Sn print byte scaled width limited by n
1357 %<bitfield>Tn print short scaled width limited by n
1358 %<bitfield>Un print long scaled width limited by n
1359
1360 %<bitfield>'c print specified char iff bitfield is all ones
1361 %<bitfield>`c print specified char iff bitfield is all zeroes
1362 %<bitfield>?ab... select from array of values in big endian order. */
1363
1364 static const struct opcode32 neon_opcodes[] =
1365 {
1366 /* Extract. */
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368 0xf2b00840, 0xffb00850,
1369 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf2b00000, 0xffb00810,
1372 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1373
1374 /* Data transfer between ARM and NEON registers. */
1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1376 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1387
1388 /* Move data element to all lanes. */
1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1390 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1394 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1395
1396 /* Table lookup. */
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1400 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1401
1402 /* Half-precision conversions. */
1403 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1404 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1405 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1406 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1407
1408 /* NEON fused multiply add instructions. */
1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1410 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1411 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1412 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1414 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1416 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1417
1418 /* Two registers, miscellaneous. */
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1420 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1422 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1424 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1425 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1426 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1427 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1428 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1429 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1430 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1431 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1432 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1433 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1434 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1435 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1436 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1437 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1438 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1439 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1440 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1460 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1462 0xf3b20300, 0xffb30fd0,
1463 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1466 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1467 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1470 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1471 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1505 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1507 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1509 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1511 0xf3bb0600, 0xffbf0e10,
1512 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1513 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1514 0xf3b70600, 0xffbf0e10,
1515 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1516
1517 /* Three registers of the same length. */
1518 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1519 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1520 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1521 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1522 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1523 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1524 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1525 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1526 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1527 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1528 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1529 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1530 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1531 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1533 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1535 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1537 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1538 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1539 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1540 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1541 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1545 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1546 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1547 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1549 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1551 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1552 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1553 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1559 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1562 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1563 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1564 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1565 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1566 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1567 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1571 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1575 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1576 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1577 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1578 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1579 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1581 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1582 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1583 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1585 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1586 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1587 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1588 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1589 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1590 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1591 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1594 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1595 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1598 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1599 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1602 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1603 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1606 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1607 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1611 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1614 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1615 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1618 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1619 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1622 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1623 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1626 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1627 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1631 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635 0xf2000b00, 0xff800f10,
1636 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf2000b10, 0xff800f10,
1639 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1641 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1643 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1645 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647 0xf3000b00, 0xff800f10,
1648 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf2000000, 0xfe800f10,
1651 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653 0xf2000010, 0xfe800f10,
1654 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656 0xf2000100, 0xfe800f10,
1657 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1659 0xf2000200, 0xfe800f10,
1660 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf2000210, 0xfe800f10,
1663 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1665 0xf2000300, 0xfe800f10,
1666 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668 0xf2000310, 0xfe800f10,
1669 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1671 0xf2000400, 0xfe800f10,
1672 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf2000410, 0xfe800f10,
1675 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1677 0xf2000500, 0xfe800f10,
1678 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680 0xf2000510, 0xfe800f10,
1681 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1683 0xf2000600, 0xfe800f10,
1684 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686 0xf2000610, 0xfe800f10,
1687 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf2000700, 0xfe800f10,
1690 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692 0xf2000710, 0xfe800f10,
1693 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695 0xf2000910, 0xfe800f10,
1696 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698 0xf2000a00, 0xfe800f10,
1699 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701 0xf2000a10, 0xfe800f10,
1702 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1704 0xf3000b10, 0xff800f10,
1705 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1706 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1707 0xf3000c10, 0xff800f10,
1708 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1709
1710 /* One register and an immediate value. */
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1715 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1716 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1720 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1722 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1727 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1728 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1733 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1734 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1737
1738 /* Two registers and a shift amount. */
1739 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1740 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1742 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1745 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1746 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1747 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1748 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1750 0xf2880950, 0xfeb80fd0,
1751 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1755 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1767 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2900950, 0xfeb00fd0,
1774 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1775 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1776 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1778 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1780 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1813 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1814 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1815 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1816 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818 0xf2a00950, 0xfea00fd0,
1819 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1823 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1825 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1829 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1831 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1835 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1841 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1843 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1847 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1848 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1849 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1851 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1853 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1854 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1855 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1856 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1857 0xf2a00e10, 0xfea00e90,
1858 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1859 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1860 0xf2a00c10, 0xfea00e90,
1861 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1862
1863 /* Three registers of different lengths. */
1864 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1865 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1866 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1867 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1868 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1869 0xf2800400, 0xff800f50,
1870 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf2800600, 0xff800f50,
1873 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1874 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1875 0xf2800900, 0xff800f50,
1876 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf2800b00, 0xff800f50,
1879 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1881 0xf2800d00, 0xff800f50,
1882 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884 0xf3800400, 0xff800f50,
1885 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1886 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1887 0xf3800600, 0xff800f50,
1888 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890 0xf2800000, 0xfe800f50,
1891 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1893 0xf2800100, 0xfe800f50,
1894 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1895 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1896 0xf2800200, 0xfe800f50,
1897 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899 0xf2800300, 0xfe800f50,
1900 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1901 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1902 0xf2800500, 0xfe800f50,
1903 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905 0xf2800700, 0xfe800f50,
1906 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1907 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1908 0xf2800800, 0xfe800f50,
1909 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911 0xf2800a00, 0xfe800f50,
1912 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1913 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1914 0xf2800c00, 0xfe800f50,
1915 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1916
1917 /* Two registers and a scalar. */
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1919 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1920 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1921 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1922 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1923 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1925 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1926 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1927 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1928 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1929 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1930 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1931 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1933 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1934 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1935 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1937 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1938 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1939 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1941 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1943 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1945 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1946 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1947 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1949 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1950 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1951 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1952 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1953 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1954 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1955 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1956 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1957 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1958 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1959 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1961 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1962 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1963 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1965 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1967 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1969 0xf2800240, 0xfe800f50,
1970 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1972 0xf2800640, 0xfe800f50,
1973 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1975 0xf2800a40, 0xfe800f50,
1976 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1978 0xf2800e40, 0xff800f50,
1979 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1981 0xf2800f40, 0xff800f50,
1982 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1984 0xf3800e40, 0xff800f50,
1985 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1987 0xf3800f40, 0xff800f50,
1988 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1989 },
1990
1991 /* Element and structure load/store. */
1992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1993 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1995 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1997 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1999 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2001 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2002 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2003 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2004 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2005 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2006 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2007 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2008 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2009 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2010 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2011 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2013 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2014 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2015 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2016 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2017 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2019 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2020 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2021 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2022 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2023 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2025 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2026 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2027 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2028 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2029 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2030
2031 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2032 };
2033
2034 /* mve opcode table. */
2035
2036 /* print_insn_mve recognizes the following format control codes:
2037
2038 %% %
2039
2040 %a print '+' or '-' or imm offset in vldr[bhwd] and
2041 vstr[bhwd]
2042 %c print condition code
2043 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2044 %u print 'U' (unsigned) or 'S' for various mve instructions
2045 %i print MVE predicate(s) for vpt and vpst
2046 %j print a 5-bit immediate from hw2[14:12,7:6]
2047 %m print rounding mode for vcvt and vrint
2048 %n print vector comparison code for predicated instruction
2049 %s print size for various vcvt instructions
2050 %v print vector predicate for instruction in predicated
2051 block
2052 %o print offset scaled for vldr[hwd] and vstr[hwd]
2053 %w print writeback mode for MVE v{st,ld}[24]
2054 %B print v{st,ld}[24] any one operands
2055 %E print vmov, vmvn, vorr, vbic encoded constant
2056 %N print generic index for vmov
2057 %T print bottom ('b') or top ('t') of source register
2058 %X print exchange field in vmla* instructions
2059
2060 %<bitfield>r print as an ARM register
2061 %<bitfield>d print the bitfield in decimal
2062 %<bitfield>A print accumulate or not
2063 %<bitfield>Q print as a MVE Q register
2064 %<bitfield>F print as a MVE S register
2065 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2066 UNPREDICTABLE
2067
2068 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
2069 %<bitfield>s print size for vector predicate & non VMOV instructions
2070 %<bitfield>I print carry flag or not
2071 %<bitfield>i print immediate for vstr/vldr reg +/- imm
2072 %<bitfield>h print high half of 64-bit destination reg
2073 %<bitfield>k print immediate for vector conversion instruction
2074 %<bitfield>l print low half of 64-bit destination reg
2075 %<bitfield>o print rotate value for vcmul
2076 %<bitfield>u print immediate value for vddup/vdwdup
2077 %<bitfield>x print the bitfield in hex.
2078 */
2079
2080 static const struct mopcode32 mve_opcodes[] =
2081 {
2082 /* MVE. */
2083
2084 {ARM_FEATURE_COPROC (FPU_MVE),
2085 MVE_VPST,
2086 0xfe310f4d, 0xffbf1fff,
2087 "vpst%i"
2088 },
2089
2090 /* Floating point VPT T1. */
2091 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2092 MVE_VPT_FP_T1,
2093 0xee310f00, 0xefb10f50,
2094 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2095 /* Floating point VPT T2. */
2096 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2097 MVE_VPT_FP_T2,
2098 0xee310f40, 0xefb10f50,
2099 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2100
2101 /* Vector VPT T1. */
2102 {ARM_FEATURE_COPROC (FPU_MVE),
2103 MVE_VPT_VEC_T1,
2104 0xfe010f00, 0xff811f51,
2105 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2106 /* Vector VPT T2. */
2107 {ARM_FEATURE_COPROC (FPU_MVE),
2108 MVE_VPT_VEC_T2,
2109 0xfe010f01, 0xff811f51,
2110 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2111 /* Vector VPT T3. */
2112 {ARM_FEATURE_COPROC (FPU_MVE),
2113 MVE_VPT_VEC_T3,
2114 0xfe011f00, 0xff811f50,
2115 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2116 /* Vector VPT T4. */
2117 {ARM_FEATURE_COPROC (FPU_MVE),
2118 MVE_VPT_VEC_T4,
2119 0xfe010f40, 0xff811f70,
2120 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2121 /* Vector VPT T5. */
2122 {ARM_FEATURE_COPROC (FPU_MVE),
2123 MVE_VPT_VEC_T5,
2124 0xfe010f60, 0xff811f70,
2125 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2126 /* Vector VPT T6. */
2127 {ARM_FEATURE_COPROC (FPU_MVE),
2128 MVE_VPT_VEC_T6,
2129 0xfe011f40, 0xff811f50,
2130 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2131
2132 /* Vector VBIC immediate. */
2133 {ARM_FEATURE_COPROC (FPU_MVE),
2134 MVE_VBIC_IMM,
2135 0xef800070, 0xefb81070,
2136 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2137
2138 /* Vector VBIC register. */
2139 {ARM_FEATURE_COPROC (FPU_MVE),
2140 MVE_VBIC_REG,
2141 0xef100150, 0xffb11f51,
2142 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2143
2144 /* Vector VABAV. */
2145 {ARM_FEATURE_COPROC (FPU_MVE),
2146 MVE_VABAV,
2147 0xee800f01, 0xefc10f51,
2148 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2149
2150 /* Vector VABD floating point. */
2151 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2152 MVE_VABD_FP,
2153 0xff200d40, 0xffa11f51,
2154 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2155
2156 /* Vector VABD. */
2157 {ARM_FEATURE_COPROC (FPU_MVE),
2158 MVE_VABD_VEC,
2159 0xef000740, 0xef811f51,
2160 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2161
2162 /* Vector VABS floating point. */
2163 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2164 MVE_VABS_FP,
2165 0xFFB10740, 0xFFB31FD1,
2166 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2167 /* Vector VABS. */
2168 {ARM_FEATURE_COPROC (FPU_MVE),
2169 MVE_VABS_VEC,
2170 0xffb10340, 0xffb31fd1,
2171 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2172
2173 /* Vector VADD floating point T1. */
2174 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2175 MVE_VADD_FP_T1,
2176 0xef000d40, 0xffa11f51,
2177 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2178 /* Vector VADD floating point T2. */
2179 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2180 MVE_VADD_FP_T2,
2181 0xee300f40, 0xefb11f70,
2182 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2183 /* Vector VADD T1. */
2184 {ARM_FEATURE_COPROC (FPU_MVE),
2185 MVE_VADD_VEC_T1,
2186 0xef000840, 0xff811f51,
2187 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2188 /* Vector VADD T2. */
2189 {ARM_FEATURE_COPROC (FPU_MVE),
2190 MVE_VADD_VEC_T2,
2191 0xee010f40, 0xff811f70,
2192 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2193
2194 /* Vector VADDLV. */
2195 {ARM_FEATURE_COPROC (FPU_MVE),
2196 MVE_VADDLV,
2197 0xee890f00, 0xef8f1fd1,
2198 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2199
2200 /* Vector VADDV. */
2201 {ARM_FEATURE_COPROC (FPU_MVE),
2202 MVE_VADDV,
2203 0xeef10f00, 0xeff31fd1,
2204 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2205
2206 /* Vector VADC. */
2207 {ARM_FEATURE_COPROC (FPU_MVE),
2208 MVE_VADC,
2209 0xee300f00, 0xffb10f51,
2210 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2211
2212 /* Vector VAND. */
2213 {ARM_FEATURE_COPROC (FPU_MVE),
2214 MVE_VAND,
2215 0xef000150, 0xffb11f51,
2216 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2217
2218 /* Vector VBRSR register. */
2219 {ARM_FEATURE_COPROC (FPU_MVE),
2220 MVE_VBRSR,
2221 0xfe011e60, 0xff811f70,
2222 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2223
2224 /* Vector VCADD floating point. */
2225 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2226 MVE_VCADD_FP,
2227 0xfc800840, 0xfea11f51,
2228 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2229
2230 /* Vector VCADD. */
2231 {ARM_FEATURE_COPROC (FPU_MVE),
2232 MVE_VCADD_VEC,
2233 0xfe000f00, 0xff810f51,
2234 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2235
2236 /* Vector VCLS. */
2237 {ARM_FEATURE_COPROC (FPU_MVE),
2238 MVE_VCLS,
2239 0xffb00440, 0xffb31fd1,
2240 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2241
2242 /* Vector VCLZ. */
2243 {ARM_FEATURE_COPROC (FPU_MVE),
2244 MVE_VCLZ,
2245 0xffb004c0, 0xffb31fd1,
2246 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2247
2248 /* Vector VCMLA. */
2249 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2250 MVE_VCMLA_FP,
2251 0xfc200840, 0xfe211f51,
2252 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2253
2254 /* Vector VCMP floating point T1. */
2255 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2256 MVE_VCMP_FP_T1,
2257 0xee310f00, 0xeff1ef50,
2258 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2259
2260 /* Vector VCMP floating point T2. */
2261 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2262 MVE_VCMP_FP_T2,
2263 0xee310f40, 0xeff1ef50,
2264 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2265
2266 /* Vector VCMP T1. */
2267 {ARM_FEATURE_COPROC (FPU_MVE),
2268 MVE_VCMP_VEC_T1,
2269 0xfe010f00, 0xffc1ff51,
2270 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2271 /* Vector VCMP T2. */
2272 {ARM_FEATURE_COPROC (FPU_MVE),
2273 MVE_VCMP_VEC_T2,
2274 0xfe010f01, 0xffc1ff51,
2275 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2276 /* Vector VCMP T3. */
2277 {ARM_FEATURE_COPROC (FPU_MVE),
2278 MVE_VCMP_VEC_T3,
2279 0xfe011f00, 0xffc1ff50,
2280 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2281 /* Vector VCMP T4. */
2282 {ARM_FEATURE_COPROC (FPU_MVE),
2283 MVE_VCMP_VEC_T4,
2284 0xfe010f40, 0xffc1ff70,
2285 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2286 /* Vector VCMP T5. */
2287 {ARM_FEATURE_COPROC (FPU_MVE),
2288 MVE_VCMP_VEC_T5,
2289 0xfe010f60, 0xffc1ff70,
2290 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2291 /* Vector VCMP T6. */
2292 {ARM_FEATURE_COPROC (FPU_MVE),
2293 MVE_VCMP_VEC_T6,
2294 0xfe011f40, 0xffc1ff50,
2295 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2296
2297 /* Vector VDUP. */
2298 {ARM_FEATURE_COPROC (FPU_MVE),
2299 MVE_VDUP,
2300 0xeea00b10, 0xffb10f5f,
2301 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2302
2303 /* Vector VEOR. */
2304 {ARM_FEATURE_COPROC (FPU_MVE),
2305 MVE_VEOR,
2306 0xff000150, 0xffd11f51,
2307 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2308
2309 /* Vector VFMA, vector * scalar. */
2310 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2311 MVE_VFMA_FP_SCALAR,
2312 0xee310e40, 0xefb11f70,
2313 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2314
2315 /* Vector VFMA floating point. */
2316 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2317 MVE_VFMA_FP,
2318 0xef000c50, 0xffa11f51,
2319 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2320
2321 /* Vector VFMS floating point. */
2322 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2323 MVE_VFMS_FP,
2324 0xef200c50, 0xffa11f51,
2325 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2326
2327 /* Vector VFMAS, vector * scalar. */
2328 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2329 MVE_VFMAS_FP_SCALAR,
2330 0xee311e40, 0xefb11f70,
2331 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2332
2333 /* Vector VHADD T1. */
2334 {ARM_FEATURE_COPROC (FPU_MVE),
2335 MVE_VHADD_T1,
2336 0xef000040, 0xef811f51,
2337 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2338
2339 /* Vector VHADD T2. */
2340 {ARM_FEATURE_COPROC (FPU_MVE),
2341 MVE_VHADD_T2,
2342 0xee000f40, 0xef811f70,
2343 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2344
2345 /* Vector VHSUB T1. */
2346 {ARM_FEATURE_COPROC (FPU_MVE),
2347 MVE_VHSUB_T1,
2348 0xef000240, 0xef811f51,
2349 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2350
2351 /* Vector VHSUB T2. */
2352 {ARM_FEATURE_COPROC (FPU_MVE),
2353 MVE_VHSUB_T2,
2354 0xee001f40, 0xef811f70,
2355 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2356
2357 /* Vector VCMUL. */
2358 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2359 MVE_VCMUL_FP,
2360 0xee300e00, 0xefb10f50,
2361 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2362
2363 /* Vector VCTP. */
2364 {ARM_FEATURE_COPROC (FPU_MVE),
2365 MVE_VCTP,
2366 0xf000e801, 0xffc0ffff,
2367 "vctp%v.%20-21s\t%16-19r"},
2368
2369 /* Vector VDUP. */
2370 {ARM_FEATURE_COPROC (FPU_MVE),
2371 MVE_VDUP,
2372 0xeea00b10, 0xffb10f5f,
2373 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2374
2375 /* Vector VRHADD. */
2376 {ARM_FEATURE_COPROC (FPU_MVE),
2377 MVE_VRHADD,
2378 0xef000140, 0xef811f51,
2379 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2380
2381 /* Vector VCVT. */
2382 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2383 MVE_VCVT_FP_FIX_VEC,
2384 0xef800c50, 0xef801cd1,
2385 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2386
2387 /* Vector VCVT. */
2388 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2389 MVE_VCVT_BETWEEN_FP_INT,
2390 0xffb30640, 0xffb31e51,
2391 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2392
2393 /* Vector VCVT between single and half-precision float, bottom half. */
2394 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2395 MVE_VCVT_FP_HALF_FP,
2396 0xee3f0e01, 0xefbf1fd1,
2397 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2398
2399 /* Vector VCVT between single and half-precision float, top half. */
2400 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2401 MVE_VCVT_FP_HALF_FP,
2402 0xee3f1e01, 0xefbf1fd1,
2403 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2404
2405 /* Vector VCVT. */
2406 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2407 MVE_VCVT_FROM_FP_TO_INT,
2408 0xffb30040, 0xffb31c51,
2409 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2410
2411 /* Vector VDDUP. */
2412 {ARM_FEATURE_COPROC (FPU_MVE),
2413 MVE_VDDUP,
2414 0xee011f6e, 0xff811f7e,
2415 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2416
2417 /* Vector VDWDUP. */
2418 {ARM_FEATURE_COPROC (FPU_MVE),
2419 MVE_VDWDUP,
2420 0xee011f60, 0xff811f70,
2421 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2422
2423 /* Vector VHCADD. */
2424 {ARM_FEATURE_COPROC (FPU_MVE),
2425 MVE_VHCADD,
2426 0xee000f00, 0xff810f51,
2427 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2428
2429 /* Vector VIWDUP. */
2430 {ARM_FEATURE_COPROC (FPU_MVE),
2431 MVE_VIWDUP,
2432 0xee010f60, 0xff811f70,
2433 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2434
2435 /* Vector VIDUP. */
2436 {ARM_FEATURE_COPROC (FPU_MVE),
2437 MVE_VIDUP,
2438 0xee010f6e, 0xff811f7e,
2439 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2440
2441 /* Vector VLD2. */
2442 {ARM_FEATURE_COPROC (FPU_MVE),
2443 MVE_VLD2,
2444 0xfc901e00, 0xff901e5f,
2445 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2446
2447 /* Vector VLD4. */
2448 {ARM_FEATURE_COPROC (FPU_MVE),
2449 MVE_VLD4,
2450 0xfc901e01, 0xff901e1f,
2451 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2452
2453 /* Vector VLDRB gather load. */
2454 {ARM_FEATURE_COPROC (FPU_MVE),
2455 MVE_VLDRB_GATHER_T1,
2456 0xec900e00, 0xefb01e50,
2457 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2458
2459 /* Vector VLDRH gather load. */
2460 {ARM_FEATURE_COPROC (FPU_MVE),
2461 MVE_VLDRH_GATHER_T2,
2462 0xec900e10, 0xefb01e50,
2463 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2464
2465 /* Vector VLDRW gather load. */
2466 {ARM_FEATURE_COPROC (FPU_MVE),
2467 MVE_VLDRW_GATHER_T3,
2468 0xfc900f40, 0xffb01fd0,
2469 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2470
2471 /* Vector VLDRD gather load. */
2472 {ARM_FEATURE_COPROC (FPU_MVE),
2473 MVE_VLDRD_GATHER_T4,
2474 0xec900fd0, 0xefb01fd0,
2475 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2476
2477 /* Vector VLDRW gather load. */
2478 {ARM_FEATURE_COPROC (FPU_MVE),
2479 MVE_VLDRW_GATHER_T5,
2480 0xfd101e00, 0xff111f00,
2481 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2482
2483 /* Vector VLDRD gather load, variant T6. */
2484 {ARM_FEATURE_COPROC (FPU_MVE),
2485 MVE_VLDRD_GATHER_T6,
2486 0xfd101f00, 0xff111f00,
2487 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2488
2489 /* Vector VLDRB. */
2490 {ARM_FEATURE_COPROC (FPU_MVE),
2491 MVE_VLDRB_T1,
2492 0xec100e00, 0xee581e00,
2493 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2494
2495 /* Vector VLDRH. */
2496 {ARM_FEATURE_COPROC (FPU_MVE),
2497 MVE_VLDRH_T2,
2498 0xec180e00, 0xee581e00,
2499 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2500
2501 /* Vector VLDRB unsigned, variant T5. */
2502 {ARM_FEATURE_COPROC (FPU_MVE),
2503 MVE_VLDRB_T5,
2504 0xec101e00, 0xfe101f80,
2505 "vldrb%v.u8\t%13-15,22Q, %d"},
2506
2507 /* Vector VLDRH unsigned, variant T6. */
2508 {ARM_FEATURE_COPROC (FPU_MVE),
2509 MVE_VLDRH_T6,
2510 0xec101e80, 0xfe101f80,
2511 "vldrh%v.u16\t%13-15,22Q, %d"},
2512
2513 /* Vector VLDRW unsigned, variant T7. */
2514 {ARM_FEATURE_COPROC (FPU_MVE),
2515 MVE_VLDRW_T7,
2516 0xec101f00, 0xfe101f80,
2517 "vldrw%v.u32\t%13-15,22Q, %d"},
2518
2519 /* Vector VMAX. */
2520 {ARM_FEATURE_COPROC (FPU_MVE),
2521 MVE_VMAX,
2522 0xef000640, 0xef811f51,
2523 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2524
2525 /* Vector VMAXA. */
2526 {ARM_FEATURE_COPROC (FPU_MVE),
2527 MVE_VMAXA,
2528 0xee330e81, 0xffb31fd1,
2529 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2530
2531 /* Vector VMAXNM floating point. */
2532 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2533 MVE_VMAXNM_FP,
2534 0xff000f50, 0xffa11f51,
2535 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2536
2537 /* Vector VMAXNMA floating point. */
2538 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2539 MVE_VMAXNMA_FP,
2540 0xee3f0e81, 0xefbf1fd1,
2541 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2542
2543 /* Vector VMAXNMV floating point. */
2544 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2545 MVE_VMAXNMV_FP,
2546 0xeeee0f00, 0xefff0fd1,
2547 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2548
2549 /* Vector VMAXNMAV floating point. */
2550 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2551 MVE_VMAXNMAV_FP,
2552 0xeeec0f00, 0xefff0fd1,
2553 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2554
2555 /* Vector VMAXV. */
2556 {ARM_FEATURE_COPROC (FPU_MVE),
2557 MVE_VMAXV,
2558 0xeee20f00, 0xeff30fd1,
2559 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2560
2561 /* Vector VMAXAV. */
2562 {ARM_FEATURE_COPROC (FPU_MVE),
2563 MVE_VMAXAV,
2564 0xeee00f00, 0xfff30fd1,
2565 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2566
2567 /* Vector VMIN. */
2568 {ARM_FEATURE_COPROC (FPU_MVE),
2569 MVE_VMIN,
2570 0xef000650, 0xef811f51,
2571 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2572
2573 /* Vector VMINA. */
2574 {ARM_FEATURE_COPROC (FPU_MVE),
2575 MVE_VMINA,
2576 0xee331e81, 0xffb31fd1,
2577 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2578
2579 /* Vector VMINNM floating point. */
2580 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2581 MVE_VMINNM_FP,
2582 0xff200f50, 0xffa11f51,
2583 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2584
2585 /* Vector VMINNMA floating point. */
2586 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2587 MVE_VMINNMA_FP,
2588 0xee3f1e81, 0xefbf1fd1,
2589 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2590
2591 /* Vector VMINNMV floating point. */
2592 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2593 MVE_VMINNMV_FP,
2594 0xeeee0f80, 0xefff0fd1,
2595 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2596
2597 /* Vector VMINNMAV floating point. */
2598 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2599 MVE_VMINNMAV_FP,
2600 0xeeec0f80, 0xefff0fd1,
2601 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2602
2603 /* Vector VMINV. */
2604 {ARM_FEATURE_COPROC (FPU_MVE),
2605 MVE_VMINV,
2606 0xeee20f80, 0xeff30fd1,
2607 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2608
2609 /* Vector VMINAV. */
2610 {ARM_FEATURE_COPROC (FPU_MVE),
2611 MVE_VMINAV,
2612 0xeee00f80, 0xfff30fd1,
2613 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2614
2615 /* Vector VMLA. */
2616 {ARM_FEATURE_COPROC (FPU_MVE),
2617 MVE_VMLA,
2618 0xee010e40, 0xef811f70,
2619 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2620
2621 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2622 opcode aliasing. */
2623 {ARM_FEATURE_COPROC (FPU_MVE),
2624 MVE_VMLALDAV,
2625 0xee801e00, 0xef801f51,
2626 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2627
2628 {ARM_FEATURE_COPROC (FPU_MVE),
2629 MVE_VMLALDAV,
2630 0xee800e00, 0xef801f51,
2631 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2632
2633 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2634 {ARM_FEATURE_COPROC (FPU_MVE),
2635 MVE_VMLADAV_T1,
2636 0xeef00e00, 0xeff01f51,
2637 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2638
2639 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2640 {ARM_FEATURE_COPROC (FPU_MVE),
2641 MVE_VMLADAV_T2,
2642 0xeef00f00, 0xeff11f51,
2643 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2644
2645 /* Vector VMLADAV T1 variant. */
2646 {ARM_FEATURE_COPROC (FPU_MVE),
2647 MVE_VMLADAV_T1,
2648 0xeef01e00, 0xeff01f51,
2649 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2650
2651 /* Vector VMLADAV T2 variant. */
2652 {ARM_FEATURE_COPROC (FPU_MVE),
2653 MVE_VMLADAV_T2,
2654 0xeef01f00, 0xeff11f51,
2655 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2656
2657 /* Vector VMLAS. */
2658 {ARM_FEATURE_COPROC (FPU_MVE),
2659 MVE_VMLAS,
2660 0xee011e40, 0xef811f70,
2661 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2662
2663 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2664 opcode aliasing. */
2665 {ARM_FEATURE_COPROC (FPU_MVE),
2666 MVE_VRMLSLDAVH,
2667 0xfe800e01, 0xff810f51,
2668 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2669
2670 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2671 opcdoe aliasing. */
2672 {ARM_FEATURE_COPROC (FPU_MVE),
2673 MVE_VMLSLDAV,
2674 0xee800e01, 0xff800f51,
2675 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2676
2677 /* Vector VMLSDAV T1 Variant. */
2678 {ARM_FEATURE_COPROC (FPU_MVE),
2679 MVE_VMLSDAV_T1,
2680 0xeef00e01, 0xfff00f51,
2681 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2682
2683 /* Vector VMLSDAV T2 Variant. */
2684 {ARM_FEATURE_COPROC (FPU_MVE),
2685 MVE_VMLSDAV_T2,
2686 0xfef00e01, 0xfff10f51,
2687 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2688
2689 /* Vector VMOV between gpr and half precision register, op == 0. */
2690 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2691 MVE_VMOV_HFP_TO_GP,
2692 0xee000910, 0xfff00f7f,
2693 "vmov.f16\t%7,16-19F, %12-15r"},
2694
2695 /* Vector VMOV between gpr and half precision register, op == 1. */
2696 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2697 MVE_VMOV_HFP_TO_GP,
2698 0xee100910, 0xfff00f7f,
2699 "vmov.f16\t%12-15r, %7,16-19F"},
2700
2701 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2702 MVE_VMOV_GP_TO_VEC_LANE,
2703 0xee000b10, 0xff900f1f,
2704 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2705
2706 /* Vector VORR immediate to vector.
2707 NOTE: MVE_VORR_IMM must appear in the table
2708 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2709 {ARM_FEATURE_COPROC (FPU_MVE),
2710 MVE_VORR_IMM,
2711 0xef800050, 0xefb810f0,
2712 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2713
2714 /* Vector VQSHL T2 Variant.
2715 NOTE: MVE_VQSHL_T2 must appear in the table before
2716 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2717 {ARM_FEATURE_COPROC (FPU_MVE),
2718 MVE_VQSHL_T2,
2719 0xef800750, 0xef801fd1,
2720 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2721
2722 /* Vector VQSHLU T3 Variant
2723 NOTE: MVE_VQSHL_T2 must appear in the table before
2724 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2725
2726 {ARM_FEATURE_COPROC (FPU_MVE),
2727 MVE_VQSHLU_T3,
2728 0xff800650, 0xff801fd1,
2729 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2730
2731 /* Vector VRSHR
2732 NOTE: MVE_VRSHR must appear in the table before
2733 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2734 {ARM_FEATURE_COPROC (FPU_MVE),
2735 MVE_VRSHR,
2736 0xef800250, 0xef801fd1,
2737 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2738
2739 /* Vector VSHL.
2740 NOTE: MVE_VSHL must appear in the table before
2741 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2742 {ARM_FEATURE_COPROC (FPU_MVE),
2743 MVE_VSHL_T1,
2744 0xef800550, 0xff801fd1,
2745 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2746
2747 /* Vector VSHR
2748 NOTE: MVE_VSHR must appear in the table before
2749 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2750 {ARM_FEATURE_COPROC (FPU_MVE),
2751 MVE_VSHR,
2752 0xef800050, 0xef801fd1,
2753 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2754
2755 /* Vector VSLI
2756 NOTE: MVE_VSLI must appear in the table before
2757 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2758 {ARM_FEATURE_COPROC (FPU_MVE),
2759 MVE_VSLI,
2760 0xff800550, 0xff801fd1,
2761 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2762
2763 /* Vector VSRI
2764 NOTE: MVE_VSRI must appear in the table before
2765 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2766 {ARM_FEATURE_COPROC (FPU_MVE),
2767 MVE_VSRI,
2768 0xff800450, 0xff801fd1,
2769 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2770
2771 /* Vector VMOV immediate to vector,
2772 cmode == 11x1 -> VMVN which is UNDEFINED
2773 for such a cmode. */
2774 {ARM_FEATURE_COPROC (FPU_MVE),
2775 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2776
2777 /* Vector VMOV immediate to vector. */
2778 {ARM_FEATURE_COPROC (FPU_MVE),
2779 MVE_VMOV_IMM_TO_VEC,
2780 0xef800050, 0xefb810d0,
2781 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2782
2783 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2784 {ARM_FEATURE_COPROC (FPU_MVE),
2785 MVE_VMOV2_VEC_LANE_TO_GP,
2786 0xec000f00, 0xffb01ff0,
2787 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2788
2789 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2790 {ARM_FEATURE_COPROC (FPU_MVE),
2791 MVE_VMOV2_VEC_LANE_TO_GP,
2792 0xec000f10, 0xffb01ff0,
2793 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2794
2795 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2796 {ARM_FEATURE_COPROC (FPU_MVE),
2797 MVE_VMOV2_GP_TO_VEC_LANE,
2798 0xec100f00, 0xffb01ff0,
2799 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2800
2801 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2802 {ARM_FEATURE_COPROC (FPU_MVE),
2803 MVE_VMOV2_GP_TO_VEC_LANE,
2804 0xec100f10, 0xffb01ff0,
2805 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2806
2807 /* Vector VMOV Vector lane to gpr. */
2808 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2809 MVE_VMOV_VEC_LANE_TO_GP,
2810 0xee100b10, 0xff100f1f,
2811 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2812
2813 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2814 to instruction opcode aliasing. */
2815 {ARM_FEATURE_COPROC (FPU_MVE),
2816 MVE_VSHLL_T1,
2817 0xeea00f40, 0xefa00fd1,
2818 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2819
2820 /* Vector VMOVL long. */
2821 {ARM_FEATURE_COPROC (FPU_MVE),
2822 MVE_VMOVL,
2823 0xeea00f40, 0xefa70fd1,
2824 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2825
2826 /* Vector VMOV and narrow. */
2827 {ARM_FEATURE_COPROC (FPU_MVE),
2828 MVE_VMOVN,
2829 0xfe310e81, 0xffb30fd1,
2830 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2831
2832 /* Floating point move extract. */
2833 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2834 MVE_VMOVX,
2835 0xfeb00a40, 0xffbf0fd0,
2836 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2837
2838 /* Vector VMUL floating-point T1 variant. */
2839 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2840 MVE_VMUL_FP_T1,
2841 0xff000d50, 0xffa11f51,
2842 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2843
2844 /* Vector VMUL floating-point T2 variant. */
2845 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2846 MVE_VMUL_FP_T2,
2847 0xee310e60, 0xefb11f70,
2848 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2849
2850 /* Vector VMUL T1 variant. */
2851 {ARM_FEATURE_COPROC (FPU_MVE),
2852 MVE_VMUL_VEC_T1,
2853 0xef000950, 0xff811f51,
2854 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2855
2856 /* Vector VMUL T2 variant. */
2857 {ARM_FEATURE_COPROC (FPU_MVE),
2858 MVE_VMUL_VEC_T2,
2859 0xee011e60, 0xff811f70,
2860 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2861
2862 /* Vector VMULH. */
2863 {ARM_FEATURE_COPROC (FPU_MVE),
2864 MVE_VMULH,
2865 0xee010e01, 0xef811f51,
2866 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2867
2868 /* Vector VRMULH. */
2869 {ARM_FEATURE_COPROC (FPU_MVE),
2870 MVE_VRMULH,
2871 0xee011e01, 0xef811f51,
2872 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2873
2874 /* Vector VMULL integer. */
2875 {ARM_FEATURE_COPROC (FPU_MVE),
2876 MVE_VMULL_INT,
2877 0xee010e00, 0xef810f51,
2878 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2879
2880 /* Vector VMULL polynomial. */
2881 {ARM_FEATURE_COPROC (FPU_MVE),
2882 MVE_VMULL_POLY,
2883 0xee310e00, 0xefb10f51,
2884 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2885
2886 /* Vector VMVN immediate to vector. */
2887 {ARM_FEATURE_COPROC (FPU_MVE),
2888 MVE_VMVN_IMM,
2889 0xef800070, 0xefb810f0,
2890 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2891
2892 /* Vector VMVN register. */
2893 {ARM_FEATURE_COPROC (FPU_MVE),
2894 MVE_VMVN_REG,
2895 0xffb005c0, 0xffbf1fd1,
2896 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2897
2898 /* Vector VNEG floating point. */
2899 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2900 MVE_VNEG_FP,
2901 0xffb107c0, 0xffb31fd1,
2902 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2903
2904 /* Vector VNEG. */
2905 {ARM_FEATURE_COPROC (FPU_MVE),
2906 MVE_VNEG_VEC,
2907 0xffb103c0, 0xffb31fd1,
2908 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2909
2910 /* Vector VORN, vector bitwise or not. */
2911 {ARM_FEATURE_COPROC (FPU_MVE),
2912 MVE_VORN,
2913 0xef300150, 0xffb11f51,
2914 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2915
2916 /* Vector VORR register. */
2917 {ARM_FEATURE_COPROC (FPU_MVE),
2918 MVE_VORR_REG,
2919 0xef200150, 0xffb11f51,
2920 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2921
2922 /* Vector VQDMULL T1 variant. */
2923 {ARM_FEATURE_COPROC (FPU_MVE),
2924 MVE_VQDMULL_T1,
2925 0xee300f01, 0xefb10f51,
2926 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2927
2928 /* Vector VPNOT. */
2929 {ARM_FEATURE_COPROC (FPU_MVE),
2930 MVE_VPNOT,
2931 0xfe310f4d, 0xffffffff,
2932 "vpnot%v"},
2933
2934 /* Vector VPSEL. */
2935 {ARM_FEATURE_COPROC (FPU_MVE),
2936 MVE_VPSEL,
2937 0xfe310f01, 0xffb11f51,
2938 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2939
2940 /* Vector VQABS. */
2941 {ARM_FEATURE_COPROC (FPU_MVE),
2942 MVE_VQABS,
2943 0xffb00740, 0xffb31fd1,
2944 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2945
2946 /* Vector VQADD T1 variant. */
2947 {ARM_FEATURE_COPROC (FPU_MVE),
2948 MVE_VQADD_T1,
2949 0xef000050, 0xef811f51,
2950 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2951
2952 /* Vector VQADD T2 variant. */
2953 {ARM_FEATURE_COPROC (FPU_MVE),
2954 MVE_VQADD_T2,
2955 0xee000f60, 0xef811f70,
2956 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2957
2958 /* Vector VQDMULL T2 variant. */
2959 {ARM_FEATURE_COPROC (FPU_MVE),
2960 MVE_VQDMULL_T2,
2961 0xee300f60, 0xefb10f70,
2962 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2963
2964 /* Vector VQMOVN. */
2965 {ARM_FEATURE_COPROC (FPU_MVE),
2966 MVE_VQMOVN,
2967 0xee330e01, 0xefb30fd1,
2968 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2969
2970 /* Vector VQMOVUN. */
2971 {ARM_FEATURE_COPROC (FPU_MVE),
2972 MVE_VQMOVUN,
2973 0xee310e81, 0xffb30fd1,
2974 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2975
2976 /* Vector VQDMLADH. */
2977 {ARM_FEATURE_COPROC (FPU_MVE),
2978 MVE_VQDMLADH,
2979 0xee000e00, 0xff810f51,
2980 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2981
2982 /* Vector VQRDMLADH. */
2983 {ARM_FEATURE_COPROC (FPU_MVE),
2984 MVE_VQRDMLADH,
2985 0xee000e01, 0xff810f51,
2986 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2987
2988 /* Vector VQDMLAH. */
2989 {ARM_FEATURE_COPROC (FPU_MVE),
2990 MVE_VQDMLAH,
2991 0xee000e60, 0xef811f70,
2992 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2993
2994 /* Vector VQRDMLAH. */
2995 {ARM_FEATURE_COPROC (FPU_MVE),
2996 MVE_VQRDMLAH,
2997 0xee000e40, 0xef811f70,
2998 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2999
3000 /* Vector VQDMLASH. */
3001 {ARM_FEATURE_COPROC (FPU_MVE),
3002 MVE_VQDMLASH,
3003 0xee001e60, 0xef811f70,
3004 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3005
3006 /* Vector VQRDMLASH. */
3007 {ARM_FEATURE_COPROC (FPU_MVE),
3008 MVE_VQRDMLASH,
3009 0xee001e40, 0xef811f70,
3010 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3011
3012 /* Vector VQDMLSDH. */
3013 {ARM_FEATURE_COPROC (FPU_MVE),
3014 MVE_VQDMLSDH,
3015 0xfe000e00, 0xff810f51,
3016 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3017
3018 /* Vector VQRDMLSDH. */
3019 {ARM_FEATURE_COPROC (FPU_MVE),
3020 MVE_VQRDMLSDH,
3021 0xfe000e01, 0xff810f51,
3022 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3023
3024 /* Vector VQDMULH T1 variant. */
3025 {ARM_FEATURE_COPROC (FPU_MVE),
3026 MVE_VQDMULH_T1,
3027 0xef000b40, 0xff811f51,
3028 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3029
3030 /* Vector VQRDMULH T2 variant. */
3031 {ARM_FEATURE_COPROC (FPU_MVE),
3032 MVE_VQRDMULH_T2,
3033 0xff000b40, 0xff811f51,
3034 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3035
3036 /* Vector VQDMULH T3 variant. */
3037 {ARM_FEATURE_COPROC (FPU_MVE),
3038 MVE_VQDMULH_T3,
3039 0xee010e60, 0xff811f70,
3040 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3041
3042 /* Vector VQRDMULH T4 variant. */
3043 {ARM_FEATURE_COPROC (FPU_MVE),
3044 MVE_VQRDMULH_T4,
3045 0xfe010e60, 0xff811f70,
3046 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3047
3048 /* Vector VQNEG. */
3049 {ARM_FEATURE_COPROC (FPU_MVE),
3050 MVE_VQNEG,
3051 0xffb007c0, 0xffb31fd1,
3052 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3053
3054 /* Vector VQRSHL T1 variant. */
3055 {ARM_FEATURE_COPROC (FPU_MVE),
3056 MVE_VQRSHL_T1,
3057 0xef000550, 0xef811f51,
3058 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3059
3060 /* Vector VQRSHL T2 variant. */
3061 {ARM_FEATURE_COPROC (FPU_MVE),
3062 MVE_VQRSHL_T2,
3063 0xee331ee0, 0xefb31ff0,
3064 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3065
3066 /* Vector VQRSHRN. */
3067 {ARM_FEATURE_COPROC (FPU_MVE),
3068 MVE_VQRSHRN,
3069 0xee800f41, 0xefa00fd1,
3070 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3071
3072 /* Vector VQRSHRUN. */
3073 {ARM_FEATURE_COPROC (FPU_MVE),
3074 MVE_VQRSHRUN,
3075 0xfe800fc0, 0xffa00fd1,
3076 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3077
3078 /* Vector VQSHL T1 Variant. */
3079 {ARM_FEATURE_COPROC (FPU_MVE),
3080 MVE_VQSHL_T1,
3081 0xee311ee0, 0xefb31ff0,
3082 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3083
3084 /* Vector VQSHL T4 Variant. */
3085 {ARM_FEATURE_COPROC (FPU_MVE),
3086 MVE_VQSHL_T4,
3087 0xef000450, 0xef811f51,
3088 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3089
3090 /* Vector VQSHRN. */
3091 {ARM_FEATURE_COPROC (FPU_MVE),
3092 MVE_VQSHRN,
3093 0xee800f40, 0xefa00fd1,
3094 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3095
3096 /* Vector VQSHRUN. */
3097 {ARM_FEATURE_COPROC (FPU_MVE),
3098 MVE_VQSHRUN,
3099 0xee800fc0, 0xffa00fd1,
3100 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3101
3102 /* Vector VQSUB T1 Variant. */
3103 {ARM_FEATURE_COPROC (FPU_MVE),
3104 MVE_VQSUB_T1,
3105 0xef000250, 0xef811f51,
3106 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3107
3108 /* Vector VQSUB T2 Variant. */
3109 {ARM_FEATURE_COPROC (FPU_MVE),
3110 MVE_VQSUB_T2,
3111 0xee001f60, 0xef811f70,
3112 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3113
3114 /* Vector VREV16. */
3115 {ARM_FEATURE_COPROC (FPU_MVE),
3116 MVE_VREV16,
3117 0xffb00140, 0xffb31fd1,
3118 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3119
3120 /* Vector VREV32. */
3121 {ARM_FEATURE_COPROC (FPU_MVE),
3122 MVE_VREV32,
3123 0xffb000c0, 0xffb31fd1,
3124 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3125
3126 /* Vector VREV64. */
3127 {ARM_FEATURE_COPROC (FPU_MVE),
3128 MVE_VREV64,
3129 0xffb00040, 0xffb31fd1,
3130 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3131
3132 /* Vector VRINT floating point. */
3133 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3134 MVE_VRINT_FP,
3135 0xffb20440, 0xffb31c51,
3136 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3137
3138 /* Vector VRMLALDAVH. */
3139 {ARM_FEATURE_COPROC (FPU_MVE),
3140 MVE_VRMLALDAVH,
3141 0xee800f00, 0xef811f51,
3142 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3143
3144 /* Vector VRMLALDAVH. */
3145 {ARM_FEATURE_COPROC (FPU_MVE),
3146 MVE_VRMLALDAVH,
3147 0xee801f00, 0xef811f51,
3148 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3149
3150 /* Vector VRSHL T1 Variant. */
3151 {ARM_FEATURE_COPROC (FPU_MVE),
3152 MVE_VRSHL_T1,
3153 0xef000540, 0xef811f51,
3154 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3155
3156 /* Vector VRSHL T2 Variant. */
3157 {ARM_FEATURE_COPROC (FPU_MVE),
3158 MVE_VRSHL_T2,
3159 0xee331e60, 0xefb31ff0,
3160 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3161
3162 /* Vector VRSHRN. */
3163 {ARM_FEATURE_COPROC (FPU_MVE),
3164 MVE_VRSHRN,
3165 0xfe800fc1, 0xffa00fd1,
3166 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3167
3168 /* Vector VSBC. */
3169 {ARM_FEATURE_COPROC (FPU_MVE),
3170 MVE_VSBC,
3171 0xfe300f00, 0xffb10f51,
3172 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3173
3174 /* Vector VSHL T2 Variant. */
3175 {ARM_FEATURE_COPROC (FPU_MVE),
3176 MVE_VSHL_T2,
3177 0xee311e60, 0xefb31ff0,
3178 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3179
3180 /* Vector VSHL T3 Variant. */
3181 {ARM_FEATURE_COPROC (FPU_MVE),
3182 MVE_VSHL_T3,
3183 0xef000440, 0xef811f51,
3184 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3185
3186 /* Vector VSHLC. */
3187 {ARM_FEATURE_COPROC (FPU_MVE),
3188 MVE_VSHLC,
3189 0xeea00fc0, 0xffa01ff0,
3190 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3191
3192 /* Vector VSHLL T2 Variant. */
3193 {ARM_FEATURE_COPROC (FPU_MVE),
3194 MVE_VSHLL_T2,
3195 0xee310e01, 0xefb30fd1,
3196 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3197
3198 /* Vector VSHRN. */
3199 {ARM_FEATURE_COPROC (FPU_MVE),
3200 MVE_VSHRN,
3201 0xee800fc1, 0xffa00fd1,
3202 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3203
3204 /* Vector VST2 no writeback. */
3205 {ARM_FEATURE_COPROC (FPU_MVE),
3206 MVE_VST2,
3207 0xfc801e00, 0xffb01e5f,
3208 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3209
3210 /* Vector VST2 writeback. */
3211 {ARM_FEATURE_COPROC (FPU_MVE),
3212 MVE_VST2,
3213 0xfca01e00, 0xffb01e5f,
3214 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3215
3216 /* Vector VST4 no writeback. */
3217 {ARM_FEATURE_COPROC (FPU_MVE),
3218 MVE_VST4,
3219 0xfc801e01, 0xffb01e1f,
3220 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3221
3222 /* Vector VST4 writeback. */
3223 {ARM_FEATURE_COPROC (FPU_MVE),
3224 MVE_VST4,
3225 0xfca01e01, 0xffb01e1f,
3226 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3227
3228 /* Vector VSTRB scatter store, T1 variant. */
3229 {ARM_FEATURE_COPROC (FPU_MVE),
3230 MVE_VSTRB_SCATTER_T1,
3231 0xec800e00, 0xffb01e50,
3232 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3233
3234 /* Vector VSTRH scatter store, T2 variant. */
3235 {ARM_FEATURE_COPROC (FPU_MVE),
3236 MVE_VSTRH_SCATTER_T2,
3237 0xec800e10, 0xffb01e50,
3238 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3239
3240 /* Vector VSTRW scatter store, T3 variant. */
3241 {ARM_FEATURE_COPROC (FPU_MVE),
3242 MVE_VSTRW_SCATTER_T3,
3243 0xec800e40, 0xffb01e50,
3244 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3245
3246 /* Vector VSTRD scatter store, T4 variant. */
3247 {ARM_FEATURE_COPROC (FPU_MVE),
3248 MVE_VSTRD_SCATTER_T4,
3249 0xec800fd0, 0xffb01fd0,
3250 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3251
3252 /* Vector VSTRW scatter store, T5 variant. */
3253 {ARM_FEATURE_COPROC (FPU_MVE),
3254 MVE_VSTRW_SCATTER_T5,
3255 0xfd001e00, 0xff111f00,
3256 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3257
3258 /* Vector VSTRD scatter store, T6 variant. */
3259 {ARM_FEATURE_COPROC (FPU_MVE),
3260 MVE_VSTRD_SCATTER_T6,
3261 0xfd001f00, 0xff111f00,
3262 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3263
3264 /* Vector VSTRB. */
3265 {ARM_FEATURE_COPROC (FPU_MVE),
3266 MVE_VSTRB_T1,
3267 0xec000e00, 0xfe581e00,
3268 "vstrb%v.%7-8s\t%13-15Q, %d"},
3269
3270 /* Vector VSTRH. */
3271 {ARM_FEATURE_COPROC (FPU_MVE),
3272 MVE_VSTRH_T2,
3273 0xec080e00, 0xfe581e00,
3274 "vstrh%v.%7-8s\t%13-15Q, %d"},
3275
3276 /* Vector VSTRB variant T5. */
3277 {ARM_FEATURE_COPROC (FPU_MVE),
3278 MVE_VSTRB_T5,
3279 0xec001e00, 0xfe101f80,
3280 "vstrb%v.8\t%13-15,22Q, %d"},
3281
3282 /* Vector VSTRH variant T6. */
3283 {ARM_FEATURE_COPROC (FPU_MVE),
3284 MVE_VSTRH_T6,
3285 0xec001e80, 0xfe101f80,
3286 "vstrh%v.16\t%13-15,22Q, %d"},
3287
3288 /* Vector VSTRW variant T7. */
3289 {ARM_FEATURE_COPROC (FPU_MVE),
3290 MVE_VSTRW_T7,
3291 0xec001f00, 0xfe101f80,
3292 "vstrw%v.32\t%13-15,22Q, %d"},
3293
3294 /* Vector VSUB floating point T1 variant. */
3295 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3296 MVE_VSUB_FP_T1,
3297 0xef200d40, 0xffa11f51,
3298 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3299
3300 /* Vector VSUB floating point T2 variant. */
3301 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3302 MVE_VSUB_FP_T2,
3303 0xee301f40, 0xefb11f70,
3304 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3305
3306 /* Vector VSUB T1 variant. */
3307 {ARM_FEATURE_COPROC (FPU_MVE),
3308 MVE_VSUB_VEC_T1,
3309 0xff000840, 0xff811f51,
3310 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3311
3312 /* Vector VSUB T2 variant. */
3313 {ARM_FEATURE_COPROC (FPU_MVE),
3314 MVE_VSUB_VEC_T2,
3315 0xee011f40, 0xff811f70,
3316 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3317
3318 {ARM_FEATURE_COPROC (FPU_MVE),
3319 MVE_ASRLI,
3320 0xea50012f, 0xfff1813f,
3321 "asrl%c\t%17-19l, %9-11h, %j"},
3322
3323 {ARM_FEATURE_COPROC (FPU_MVE),
3324 MVE_ASRL,
3325 0xea50012d, 0xfff101ff,
3326 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3327
3328 {ARM_FEATURE_COPROC (FPU_MVE),
3329 MVE_LSLLI,
3330 0xea50010f, 0xfff1813f,
3331 "lsll%c\t%17-19l, %9-11h, %j"},
3332
3333 {ARM_FEATURE_COPROC (FPU_MVE),
3334 MVE_LSLL,
3335 0xea50010d, 0xfff101ff,
3336 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3337
3338 {ARM_FEATURE_COPROC (FPU_MVE),
3339 MVE_LSRL,
3340 0xea50011f, 0xfff1813f,
3341 "lsrl%c\t%17-19l, %9-11h, %j"},
3342
3343 {ARM_FEATURE_COPROC (FPU_MVE),
3344 MVE_SQRSHRL,
3345 0xea51012d, 0xfff101ff,
3346 "sqrshrl%c\t%17-19l, %9-11h, %12-15S"},
3347
3348 {ARM_FEATURE_COPROC (FPU_MVE),
3349 MVE_SQRSHR,
3350 0xea500f2d, 0xfff00fff,
3351 "sqrshr%c\t%16-19S, %12-15S"},
3352
3353 {ARM_FEATURE_COPROC (FPU_MVE),
3354 MVE_SQSHLL,
3355 0xea51013f, 0xfff1813f,
3356 "sqshll%c\t%17-19l, %9-11h, %j"},
3357
3358 {ARM_FEATURE_COPROC (FPU_MVE),
3359 MVE_SQSHL,
3360 0xea500f3f, 0xfff08f3f,
3361 "sqshl%c\t%16-19S, %j"},
3362
3363 {ARM_FEATURE_COPROC (FPU_MVE),
3364 MVE_SRSHRL,
3365 0xea51012f, 0xfff1813f,
3366 "srshrl%c\t%17-19l, %9-11h, %j"},
3367
3368 {ARM_FEATURE_COPROC (FPU_MVE),
3369 MVE_SRSHR,
3370 0xea500f2f, 0xfff08f3f,
3371 "srshr%c\t%16-19S, %j"},
3372
3373 {ARM_FEATURE_COPROC (FPU_MVE),
3374 MVE_UQRSHLL,
3375 0xea51010d, 0xfff101ff,
3376 "uqrshll%c\t%17-19l, %9-11h, %12-15S"},
3377
3378 {ARM_FEATURE_COPROC (FPU_MVE),
3379 MVE_UQRSHL,
3380 0xea500f0d, 0xfff00fff,
3381 "uqrshl%c\t%16-19S, %12-15S"},
3382
3383 {ARM_FEATURE_COPROC (FPU_MVE),
3384 MVE_UQSHLL,
3385 0xea51010f, 0xfff1813f,
3386 "uqshll%c\t%17-19l, %9-11h, %j"},
3387
3388 {ARM_FEATURE_COPROC (FPU_MVE),
3389 MVE_UQSHL,
3390 0xea500f0f, 0xfff08f3f,
3391 "uqshl%c\t%16-19S, %j"},
3392
3393 {ARM_FEATURE_COPROC (FPU_MVE),
3394 MVE_URSHRL,
3395 0xea51011f, 0xfff1813f,
3396 "urshrl%c\t%17-19l, %9-11h, %j"},
3397
3398 {ARM_FEATURE_COPROC (FPU_MVE),
3399 MVE_URSHR,
3400 0xea500f1f, 0xfff08f3f,
3401 "urshr%c\t%16-19S, %j"},
3402
3403 {ARM_FEATURE_CORE_LOW (0),
3404 MVE_NONE,
3405 0x00000000, 0x00000000, 0}
3406 };
3407
3408 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3409 ordered: they must be searched linearly from the top to obtain a correct
3410 match. */
3411
3412 /* print_insn_arm recognizes the following format control codes:
3413
3414 %% %
3415
3416 %a print address for ldr/str instruction
3417 %s print address for ldr/str halfword/signextend instruction
3418 %S like %s but allow UNPREDICTABLE addressing
3419 %b print branch destination
3420 %c print condition code (always bits 28-31)
3421 %m print register mask for ldm/stm instruction
3422 %o print operand2 (immediate or register + shift)
3423 %p print 'p' iff bits 12-15 are 15
3424 %t print 't' iff bit 21 set and bit 24 clear
3425 %B print arm BLX(1) destination
3426 %C print the PSR sub type.
3427 %U print barrier type.
3428 %P print address for pli instruction.
3429
3430 %<bitfield>r print as an ARM register
3431 %<bitfield>T print as an ARM register + 1
3432 %<bitfield>R as %r but r15 is UNPREDICTABLE
3433 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3434 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3435 %<bitfield>d print the bitfield in decimal
3436 %<bitfield>W print the bitfield plus one in decimal
3437 %<bitfield>x print the bitfield in hex
3438 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3439
3440 %<bitfield>'c print specified char iff bitfield is all ones
3441 %<bitfield>`c print specified char iff bitfield is all zeroes
3442 %<bitfield>?ab... select from array of values in big endian order
3443
3444 %e print arm SMI operand (bits 0..7,8..19).
3445 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3446 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3447 %R print the SPSR/CPSR or banked register of an MRS. */
3448
3449 static const struct opcode32 arm_opcodes[] =
3450 {
3451 /* ARM instructions. */
3452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3453 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3455 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3456
3457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3458 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3460 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3462 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3464 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3466 0x00800090, 0x0fa000f0,
3467 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3469 0x00a00090, 0x0fa000f0,
3470 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3471
3472 /* V8.2 RAS extension instructions. */
3473 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3474 0xe320f010, 0xffffffff, "esb"},
3475
3476 /* V8 instructions. */
3477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3478 0x0320f005, 0x0fffffff, "sevl"},
3479 /* Defined in V8 but is in NOP space so available to all arch. */
3480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3481 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3482 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
3483 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3484 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3485 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3487 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3489 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3490 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3491 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3492 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3493 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3494 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3495 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3496 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3497 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3498 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3499 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3500 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3501 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3502 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3503 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3504 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3505 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3506 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3507 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3508 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3509 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3510 /* CRC32 instructions. */
3511 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3512 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3513 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3514 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3515 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3516 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3517 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3518 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3519 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3520 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3521 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3522 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3523
3524 /* Privileged Access Never extension instructions. */
3525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3526 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3527
3528 /* Virtualization Extension instructions. */
3529 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3531
3532 /* Integer Divide Extension instructions. */
3533 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3534 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3535 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3536 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3537
3538 /* MP Extension instructions. */
3539 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3540
3541 /* Speculation Barriers. */
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3545
3546 /* V7 instructions. */
3547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3555 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3556
3557 /* ARM V6T2 instructions. */
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3559 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3561 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3563 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3565 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3566
3567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3568 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3570 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3571
3572 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3573 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3575 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3577 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3579 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3580
3581 /* ARM Security extension instructions. */
3582 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3583 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3584
3585 /* ARM V6K instructions. */
3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3587 0xf57ff01f, 0xffffffff, "clrex"},
3588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3589 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3591 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3593 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3595 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3597 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3599 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3600
3601 /* ARMv8.5-A instructions. */
3602 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3603
3604 /* ARM V6K NOP hints. */
3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3606 0x0320f001, 0x0fffffff, "yield%c"},
3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3608 0x0320f002, 0x0fffffff, "wfe%c"},
3609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3610 0x0320f003, 0x0fffffff, "wfi%c"},
3611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3612 0x0320f004, 0x0fffffff, "sev%c"},
3613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3614 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3615
3616 /* ARM V6 instructions. */
3617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3618 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3620 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3622 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3624 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3626 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3628 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3630 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3632 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3634 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3636 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3638 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3640 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3642 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3644 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3646 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3648 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3650 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3652 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3654 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3656 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3658 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3660 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3662 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3664 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3666 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3668 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3670 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3672 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3674 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3676 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3678 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3680 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3682 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3684 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3686 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3688 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3690 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3692 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3694 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3696 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3698 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3700 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3702 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3704 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3706 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3708 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3710 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3712 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3714 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3716 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3718 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3720 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3722 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3724 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3726 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3728 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3730 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3732 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3734 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3736 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3738 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3740 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3742 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3744 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3746 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3748 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3750 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3752 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3754 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3756 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3758 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3760 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3762 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3764 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3766 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3768 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3770 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3772 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3774 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3776 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3778 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3780 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3782 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3784 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3786 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3788 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3790 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3792 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3794 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3796 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3798 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3800 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3802 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3804 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3806 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3808 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3810 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3812 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3814 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3816 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3818 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3820 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3822 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3824 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3826 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3828 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3830 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3832 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3834 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3836 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3838 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3840 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3842 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3844 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3846 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3848 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3850 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3852 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3854 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3856 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3858 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3860 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3861
3862 /* V5J instruction. */
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3864 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3865
3866 /* V5 Instructions. */
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3868 0xe1200070, 0xfff000f0,
3869 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3871 0xfa000000, 0xfe000000, "blx\t%B"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3873 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3875 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3876
3877 /* V5E "El Segundo" Instructions. */
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3879 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3881 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3883 0xf450f000, 0xfc70f000, "pld\t%a"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3885 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3887 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3889 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3891 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3892
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3894 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3896 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3897
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3899 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3901 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3903 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3905 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3906
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3908 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3910 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3912 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3914 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3915
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3917 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3919 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3920
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3922 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3924 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3926 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3928 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3929
3930 /* ARM Instructions. */
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3932 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3933
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3935 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3937 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3939 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3941 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3943 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3945 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3946
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3948 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3950 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3952 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3954 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3955
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3957 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3959 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3961 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3963 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3964
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3966 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3968 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3970 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3971
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3973 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3975 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3977 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3978
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3980 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3982 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3984 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3985
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3987 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3989 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3991 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3992
3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3994 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3996 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3998 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3999
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4001 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4003 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4005 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4006
4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4008 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4010 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4012 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4013
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4015 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4017 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4019 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4020
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4022 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4024 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4026 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4027
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4029 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4031 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4033 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4034
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4036 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4038 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4040 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4041
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4043 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4045 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4047 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4048
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4050 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4052 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4054 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4055
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4057 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4059 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4061 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4062
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4064 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4066 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4068 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4070 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4072 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4074 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4076 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4077
4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4079 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4081 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4083 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4084
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4086 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4088 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4090 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4091
4092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4093 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4095 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4096
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4098 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4099
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4101 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4103 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4104
4105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4106 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4108 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4110 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4112 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4114 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4116 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4118 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4120 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4122 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4124 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4126 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4128 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4130 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4132 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4134 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4136 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4138 0x092d0000, 0x0fff0000, "push%c\t%m"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4140 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4142 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4143
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4145 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4147 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4149 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4151 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4153 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4155 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4157 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4163 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4165 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4167 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4169 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4171 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4173 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4175 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4177 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4179 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4181 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4182
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4187
4188 /* The rest. */
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4190 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
4191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4192 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4193 {ARM_FEATURE_CORE_LOW (0),
4194 0x00000000, 0x00000000, 0}
4195 };
4196
4197 /* print_insn_thumb16 recognizes the following format control codes:
4198
4199 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4200 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4201 %<bitfield>I print bitfield as a signed decimal
4202 (top bit of range being the sign bit)
4203 %N print Thumb register mask (with LR)
4204 %O print Thumb register mask (with PC)
4205 %M print Thumb register mask
4206 %b print CZB's 6-bit unsigned branch destination
4207 %s print Thumb right-shift immediate (6..10; 0 == 32).
4208 %c print the condition code
4209 %C print the condition code, or "s" if not conditional
4210 %x print warning if conditional an not at end of IT block"
4211 %X print "\t; unpredictable <IT:code>" if conditional
4212 %I print IT instruction suffix and operands
4213 %W print Thumb Writeback indicator for LDMIA
4214 %<bitfield>r print bitfield as an ARM register
4215 %<bitfield>d print bitfield as a decimal
4216 %<bitfield>H print (bitfield * 2) as a decimal
4217 %<bitfield>W print (bitfield * 4) as a decimal
4218 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4219 %<bitfield>B print Thumb branch destination (signed displacement)
4220 %<bitfield>c print bitfield as a condition code
4221 %<bitnum>'c print specified char iff bit is one
4222 %<bitnum>?ab print a if bit is one else print b. */
4223
4224 static const struct opcode16 thumb_opcodes[] =
4225 {
4226 /* Thumb instructions. */
4227
4228 /* ARMv8-M Security Extensions instructions. */
4229 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
4230 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
4231
4232 /* ARM V8 instructions. */
4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
4235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
4236
4237 /* ARM V6K no-argument instructions. */
4238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4244
4245 /* ARM V6T2 instructions. */
4246 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4247 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4248 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4249 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
4251
4252 /* ARM V6. */
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4264
4265 /* ARM V5 ISA extends Thumb. */
4266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4267 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
4268 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4270 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
4271 /* ARM V4T ISA (Thumb v1). */
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4273 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4274 /* Format 4. */
4275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4291 /* format 13 */
4292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4294 /* format 5 */
4295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4299 /* format 14 */
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
4302 /* format 2 */
4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4304 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4306 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4308 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4310 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4311 /* format 8 */
4312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4313 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4315 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4317 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4318 /* format 7 */
4319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4320 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4322 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4323 /* format 1 */
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4326 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4329 /* format 3 */
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4334 /* format 6 */
4335 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4337 0x4800, 0xF800,
4338 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4339 /* format 9 */
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4341 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4343 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4345 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4347 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4348 /* format 10 */
4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4350 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4352 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4353 /* format 11 */
4354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4355 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4357 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4358 /* format 12 */
4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4360 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4362 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4363 /* format 15 */
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4366 /* format 17 */
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4368 /* format 16 */
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4372 /* format 18 */
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4374
4375 /* The E800 .. FFFF range is unconditionally redirected to the
4376 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4377 are processed via that table. Thus, we can never encounter a
4378 bare "second half of BL/BLX(1)" instruction here. */
4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4380 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4381 };
4382
4383 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4384 We adopt the convention that hw1 is the high 16 bits of .value and
4385 .mask, hw2 the low 16 bits.
4386
4387 print_insn_thumb32 recognizes the following format control codes:
4388
4389 %% %
4390
4391 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4392 %M print a modified 12-bit immediate (same location)
4393 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4394 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4395 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
4396 %S print a possibly-shifted Rm
4397
4398 %L print address for a ldrd/strd instruction
4399 %a print the address of a plain load/store
4400 %w print the width and signedness of a core load/store
4401 %m print register mask for ldm/stm
4402 %n print register mask for clrm
4403
4404 %E print the lsb and width fields of a bfc/bfi instruction
4405 %F print the lsb and width fields of a sbfx/ubfx instruction
4406 %G print a fallback offset for Branch Future instructions
4407 %W print an offset for BF instruction
4408 %Y print an offset for BFL instruction
4409 %Z print an offset for BFCSEL instruction
4410 %Q print an offset for Low Overhead Loop instructions
4411 %P print an offset for Low Overhead Loop end instructions
4412 %b print a conditional branch offset
4413 %B print an unconditional branch offset
4414 %s print the shift field of an SSAT instruction
4415 %R print the rotation field of an SXT instruction
4416 %U print barrier type.
4417 %P print address for pli instruction.
4418 %c print the condition code
4419 %x print warning if conditional an not at end of IT block"
4420 %X print "\t; unpredictable <IT:code>" if conditional
4421
4422 %<bitfield>d print bitfield in decimal
4423 %<bitfield>D print bitfield plus one in decimal
4424 %<bitfield>W print bitfield*4 in decimal
4425 %<bitfield>r print bitfield as an ARM register
4426 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4427 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4428 %<bitfield>c print bitfield as a condition code
4429
4430 %<bitfield>'c print specified char iff bitfield is all ones
4431 %<bitfield>`c print specified char iff bitfield is all zeroes
4432 %<bitfield>?ab... select from array of values in big endian order
4433
4434 With one exception at the bottom (done because BL and BLX(1) need
4435 to come dead last), this table was machine-sorted first in
4436 decreasing order of number of bits set in the mask, then in
4437 increasing numeric order of mask, then in increasing numeric order
4438 of opcode. This order is not the clearest for a human reader, but
4439 is guaranteed never to catch a special-case bit pattern with a more
4440 general mask, which is important, because this instruction encoding
4441 makes heavy use of special-case bit patterns. */
4442 static const struct opcode32 thumb32_opcodes[] =
4443 {
4444 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4445 instructions. */
4446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4447 0xf00fe001, 0xffffffff, "lctp%c"},
4448 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4449 0xf02fc001, 0xfffff001, "le\t%P"},
4450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4451 0xf00fc001, 0xfffff001, "le\tlr, %P"},
4452 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4453 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4455 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4456 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4457 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4459 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4460 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4461 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4462
4463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4464 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4466 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4467 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4468 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4470 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4471 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4472 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4473
4474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4475 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4476
4477 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4478 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4480 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4482 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4484 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4486 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4487
4488 /* ARM V8.2 RAS extension instructions. */
4489 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
4490 0xf3af8010, 0xffffffff, "esb"},
4491
4492 /* V8 instructions. */
4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4494 0xf3af8005, 0xffffffff, "sevl%c.w"},
4495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4496 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4498 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4500 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4502 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4504 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4506 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4508 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4510 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4512 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4514 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4516 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4518 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4520 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4522 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4524 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4525
4526 /* CRC32 instructions. */
4527 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4528 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4529 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4530 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4531 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4532 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4533 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4534 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4535 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4536 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4537 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4538 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4539
4540 /* Speculation Barriers. */
4541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4544
4545 /* V7 instructions. */
4546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4553 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4554 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4555 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4556 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4557
4558 /* Virtualization Extension instructions. */
4559 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4560 /* We skip ERET as that is SUBS pc, lr, #0. */
4561
4562 /* MP Extension instructions. */
4563 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4564
4565 /* Security extension instructions. */
4566 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4567
4568 /* ARMv8.5-A instructions. */
4569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4570
4571 /* Instructions defined in the basic V6T2 set. */
4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4578 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4580
4581 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4582 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4584 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4586 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4588 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4590 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4592 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4594 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4596 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4598 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4600 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4602 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4604 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4606 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4608 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4609 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4610 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4612 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4614 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4616 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4618 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4620 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4622 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4624 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4626 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4628 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4629 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4630 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4632 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4634 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4636 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4638 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4640 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4642 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4644 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4646 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4648 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4650 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4652 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4654 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4656 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4658 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4660 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4662 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4664 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4666 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4668 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4670 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4672 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4674 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4676 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4678 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4680 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4682 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4684 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4686 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4688 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4690 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4692 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4694 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4696 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4698 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4700 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4702 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4704 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4706 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4708 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4710 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4712 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4714 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4716 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4718 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4720 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4722 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4724 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4726 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4728 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4730 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4732 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4734 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4736 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4737 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4738 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4740 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4742 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4744 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4746 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4748 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4750 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4752 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4754 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4756 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4758 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4760 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4762 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4764 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4766 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4768 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4770 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4772 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4774 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4776 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4778 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4780 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4782 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4784 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4786 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4788 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4790 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4792 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4794 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4796 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4798 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4800 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4802 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4804 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4806 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4808 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4810 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4812 0xf810f000, 0xff70f000, "pld%c\t%a"},
4813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4814 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4816 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4818 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4822 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4824 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4828 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4830 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4832 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4834 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4836 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4838 0xfb100000, 0xfff000c0,
4839 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4841 0xfbc00080, 0xfff000c0,
4842 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4844 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4846 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4848 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4850 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4852 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4853 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4854 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4857 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4858 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4860 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4862 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4864 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4866 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4868 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4879 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4880 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4896 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4898 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4900 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4906 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4908 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4910 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4912 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4914 0xe9400000, 0xff500000,
4915 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4917 0xe9500000, 0xff500000,
4918 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4920 0xe8600000, 0xff700000,
4921 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4923 0xe8700000, 0xff700000,
4924 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
4929
4930 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4934 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4938 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
4939
4940 /* These have been 32-bit since the invention of Thumb. */
4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4942 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4944 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
4945
4946 /* Fallback. */
4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4948 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4949 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4950 };
4951
4952 static const char *const arm_conditional[] =
4953 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
4954 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
4955
4956 static const char *const arm_fp_const[] =
4957 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4958
4959 static const char *const arm_shift[] =
4960 {"lsl", "lsr", "asr", "ror"};
4961
4962 typedef struct
4963 {
4964 const char *name;
4965 const char *description;
4966 const char *reg_names[16];
4967 }
4968 arm_regname;
4969
4970 static const arm_regname regnames[] =
4971 {
4972 { "reg-names-raw", N_("Select raw register names"),
4973 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
4974 { "reg-names-gcc", N_("Select register names used by GCC"),
4975 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
4976 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
4977 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
4978 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4979 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4980 { "reg-names-apcs", N_("Select register names used in the APCS"),
4981 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
4982 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
4983 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
4984 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4985 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
4986 };
4987
4988 static const char *const iwmmxt_wwnames[] =
4989 {"b", "h", "w", "d"};
4990
4991 static const char *const iwmmxt_wwssnames[] =
4992 {"b", "bus", "bc", "bss",
4993 "h", "hus", "hc", "hss",
4994 "w", "wus", "wc", "wss",
4995 "d", "dus", "dc", "dss"
4996 };
4997
4998 static const char *const iwmmxt_regnames[] =
4999 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5000 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5001 };
5002
5003 static const char *const iwmmxt_cregnames[] =
5004 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5005 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5006 };
5007
5008 static const char *const vec_condnames[] =
5009 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5010 };
5011
5012 static const char *const mve_predicatenames[] =
5013 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5014 "eee", "ee", "eet", "e", "ett", "et", "ete"
5015 };
5016
5017 /* Names for 2-bit size field for mve vector isntructions. */
5018 static const char *const mve_vec_sizename[] =
5019 { "8", "16", "32", "64"};
5020
5021 /* Indicates whether we are processing a then predicate,
5022 else predicate or none at all. */
5023 enum vpt_pred_state
5024 {
5025 PRED_NONE,
5026 PRED_THEN,
5027 PRED_ELSE
5028 };
5029
5030 /* Information used to process a vpt block and subsequent instructions. */
5031 struct vpt_block
5032 {
5033 /* Are we in a vpt block. */
5034 bfd_boolean in_vpt_block;
5035
5036 /* Next predicate state if in vpt block. */
5037 enum vpt_pred_state next_pred_state;
5038
5039 /* Mask from vpt/vpst instruction. */
5040 long predicate_mask;
5041
5042 /* Instruction number in vpt block. */
5043 long current_insn_num;
5044
5045 /* Number of instructions in vpt block.. */
5046 long num_pred_insn;
5047 };
5048
5049 static struct vpt_block vpt_block_state =
5050 {
5051 FALSE,
5052 PRED_NONE,
5053 0,
5054 0,
5055 0
5056 };
5057
5058 /* Default to GCC register name set. */
5059 static unsigned int regname_selected = 1;
5060
5061 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
5062 #define arm_regnames regnames[regname_selected].reg_names
5063
5064 static bfd_boolean force_thumb = FALSE;
5065
5066 /* Current IT instruction state. This contains the same state as the IT
5067 bits in the CPSR. */
5068 static unsigned int ifthen_state;
5069 /* IT state for the next instruction. */
5070 static unsigned int ifthen_next_state;
5071 /* The address of the insn for which the IT state is valid. */
5072 static bfd_vma ifthen_address;
5073 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5074 /* Indicates that the current Conditional state is unconditional or outside
5075 an IT block. */
5076 #define COND_UNCOND 16
5077
5078 \f
5079 /* Functions. */
5080 /* Extract the predicate mask for a VPT or VPST instruction.
5081 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5082
5083 static long
5084 mve_extract_pred_mask (long given)
5085 {
5086 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5087 }
5088
5089 /* Return the number of instructions in a MVE predicate block. */
5090 static long
5091 num_instructions_vpt_block (long given)
5092 {
5093 long mask = mve_extract_pred_mask (given);
5094 if (mask == 0)
5095 return 0;
5096
5097 if (mask == 8)
5098 return 1;
5099
5100 if ((mask & 7) == 4)
5101 return 2;
5102
5103 if ((mask & 3) == 2)
5104 return 3;
5105
5106 if ((mask & 1) == 1)
5107 return 4;
5108
5109 return 0;
5110 }
5111
5112 static void
5113 mark_outside_vpt_block (void)
5114 {
5115 vpt_block_state.in_vpt_block = FALSE;
5116 vpt_block_state.next_pred_state = PRED_NONE;
5117 vpt_block_state.predicate_mask = 0;
5118 vpt_block_state.current_insn_num = 0;
5119 vpt_block_state.num_pred_insn = 0;
5120 }
5121
5122 static void
5123 mark_inside_vpt_block (long given)
5124 {
5125 vpt_block_state.in_vpt_block = TRUE;
5126 vpt_block_state.next_pred_state = PRED_THEN;
5127 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5128 vpt_block_state.current_insn_num = 0;
5129 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5130 assert (vpt_block_state.num_pred_insn >= 1);
5131 }
5132
5133 static enum vpt_pred_state
5134 invert_next_predicate_state (enum vpt_pred_state astate)
5135 {
5136 if (astate == PRED_THEN)
5137 return PRED_ELSE;
5138 else if (astate == PRED_ELSE)
5139 return PRED_THEN;
5140 else
5141 return PRED_NONE;
5142 }
5143
5144 static enum vpt_pred_state
5145 update_next_predicate_state (void)
5146 {
5147 long pred_mask = vpt_block_state.predicate_mask;
5148 long mask_for_insn = 0;
5149
5150 switch (vpt_block_state.current_insn_num)
5151 {
5152 case 1:
5153 mask_for_insn = 8;
5154 break;
5155
5156 case 2:
5157 mask_for_insn = 4;
5158 break;
5159
5160 case 3:
5161 mask_for_insn = 2;
5162 break;
5163
5164 case 4:
5165 return PRED_NONE;
5166 }
5167
5168 if (pred_mask & mask_for_insn)
5169 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5170 else
5171 return vpt_block_state.next_pred_state;
5172 }
5173
5174 static void
5175 update_vpt_block_state (void)
5176 {
5177 vpt_block_state.current_insn_num++;
5178 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5179 {
5180 /* No more instructions to process in vpt block. */
5181 mark_outside_vpt_block ();
5182 return;
5183 }
5184
5185 vpt_block_state.next_pred_state = update_next_predicate_state ();
5186 }
5187
5188 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5189 Returns pointer to following character of the format string and
5190 fills in *VALUEP and *WIDTHP with the extracted value and number of
5191 bits extracted. WIDTHP can be NULL. */
5192
5193 static const char *
5194 arm_decode_bitfield (const char *ptr,
5195 unsigned long insn,
5196 unsigned long *valuep,
5197 int *widthp)
5198 {
5199 unsigned long value = 0;
5200 int width = 0;
5201
5202 do
5203 {
5204 int start, end;
5205 int bits;
5206
5207 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5208 start = start * 10 + *ptr - '0';
5209 if (*ptr == '-')
5210 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5211 end = end * 10 + *ptr - '0';
5212 else
5213 end = start;
5214 bits = end - start;
5215 if (bits < 0)
5216 abort ();
5217 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5218 width += bits + 1;
5219 }
5220 while (*ptr++ == ',');
5221 *valuep = value;
5222 if (widthp)
5223 *widthp = width;
5224 return ptr - 1;
5225 }
5226
5227 static void
5228 arm_decode_shift (long given, fprintf_ftype func, void *stream,
5229 bfd_boolean print_shift)
5230 {
5231 func (stream, "%s", arm_regnames[given & 0xf]);
5232
5233 if ((given & 0xff0) != 0)
5234 {
5235 if ((given & 0x10) == 0)
5236 {
5237 int amount = (given & 0xf80) >> 7;
5238 int shift = (given & 0x60) >> 5;
5239
5240 if (amount == 0)
5241 {
5242 if (shift == 3)
5243 {
5244 func (stream, ", rrx");
5245 return;
5246 }
5247
5248 amount = 32;
5249 }
5250
5251 if (print_shift)
5252 func (stream, ", %s #%d", arm_shift[shift], amount);
5253 else
5254 func (stream, ", #%d", amount);
5255 }
5256 else if ((given & 0x80) == 0x80)
5257 func (stream, "\t; <illegal shifter operand>");
5258 else if (print_shift)
5259 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5260 arm_regnames[(given & 0xf00) >> 8]);
5261 else
5262 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
5263 }
5264 }
5265
5266 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5267
5268 static bfd_boolean
5269 is_mve_okay_in_it (enum mve_instructions matched_insn)
5270 {
5271 switch (matched_insn)
5272 {
5273 case MVE_VMOV_GP_TO_VEC_LANE:
5274 case MVE_VMOV2_VEC_LANE_TO_GP:
5275 case MVE_VMOV2_GP_TO_VEC_LANE:
5276 case MVE_VMOV_VEC_LANE_TO_GP:
5277 case MVE_LSLL:
5278 case MVE_LSLLI:
5279 case MVE_LSRL:
5280 case MVE_ASRL:
5281 case MVE_ASRLI:
5282 case MVE_SQRSHRL:
5283 case MVE_SQRSHR:
5284 case MVE_UQRSHL:
5285 case MVE_UQRSHLL:
5286 case MVE_UQSHL:
5287 case MVE_UQSHLL:
5288 case MVE_URSHRL:
5289 case MVE_URSHR:
5290 case MVE_SRSHRL:
5291 case MVE_SRSHR:
5292 case MVE_SQSHLL:
5293 case MVE_SQSHL:
5294 return TRUE;
5295 default:
5296 return FALSE;
5297 }
5298 }
5299
5300 static bfd_boolean
5301 is_mve_architecture (struct disassemble_info *info)
5302 {
5303 struct arm_private_data *private_data = info->private_data;
5304 arm_feature_set allowed_arches = private_data->features;
5305
5306 arm_feature_set arm_ext_v8_1m_main
5307 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5308
5309 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5310 && !ARM_CPU_IS_ANY (allowed_arches))
5311 return TRUE;
5312 else
5313 return FALSE;
5314 }
5315
5316 static bfd_boolean
5317 is_vpt_instruction (long given)
5318 {
5319
5320 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5321 if ((given & 0x0040e000) == 0)
5322 return FALSE;
5323
5324 /* VPT floating point T1 variant. */
5325 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5326 /* VPT floating point T2 variant. */
5327 || ((given & 0xefb10f50) == 0xee310f40)
5328 /* VPT vector T1 variant. */
5329 || ((given & 0xff811f51) == 0xfe010f00)
5330 /* VPT vector T2 variant. */
5331 || ((given & 0xff811f51) == 0xfe010f01
5332 && ((given & 0x300000) != 0x300000))
5333 /* VPT vector T3 variant. */
5334 || ((given & 0xff811f50) == 0xfe011f00)
5335 /* VPT vector T4 variant. */
5336 || ((given & 0xff811f70) == 0xfe010f40)
5337 /* VPT vector T5 variant. */
5338 || ((given & 0xff811f70) == 0xfe010f60)
5339 /* VPT vector T6 variant. */
5340 || ((given & 0xff811f50) == 0xfe011f40)
5341 /* VPST vector T variant. */
5342 || ((given & 0xffbf1fff) == 0xfe310f4d))
5343 return TRUE;
5344 else
5345 return FALSE;
5346 }
5347
5348 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5349 and ending bitfield = END. END must be greater than START. */
5350
5351 static unsigned long
5352 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5353 {
5354 int bits = end - start;
5355
5356 if (bits < 0)
5357 abort ();
5358
5359 return ((given >> start) & ((2ul << bits) - 1));
5360 }
5361
5362 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5363 START:END and START2:END2. END/END2 must be greater than
5364 START/START2. */
5365
5366 static unsigned long
5367 arm_decode_field_multiple (unsigned long given, unsigned int start,
5368 unsigned int end, unsigned int start2,
5369 unsigned int end2)
5370 {
5371 int bits = end - start;
5372 int bits2 = end2 - start2;
5373 unsigned long value = 0;
5374 int width = 0;
5375
5376 if (bits2 < 0)
5377 abort ();
5378
5379 value = arm_decode_field (given, start, end);
5380 width += bits + 1;
5381
5382 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5383 return value;
5384 }
5385
5386 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5387 This helps us decode instructions that change mnemonic depending on specific
5388 operand values/encodings. */
5389
5390 static bfd_boolean
5391 is_mve_encoding_conflict (unsigned long given,
5392 enum mve_instructions matched_insn)
5393 {
5394 switch (matched_insn)
5395 {
5396 case MVE_VPST:
5397 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5398 return TRUE;
5399 else
5400 return FALSE;
5401
5402 case MVE_VPT_FP_T1:
5403 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5404 return TRUE;
5405 if ((arm_decode_field (given, 12, 12) == 0)
5406 && (arm_decode_field (given, 0, 0) == 1))
5407 return TRUE;
5408 return FALSE;
5409
5410 case MVE_VPT_FP_T2:
5411 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5412 return TRUE;
5413 if (arm_decode_field (given, 0, 3) == 0xd)
5414 return TRUE;
5415 return FALSE;
5416
5417 case MVE_VPT_VEC_T1:
5418 case MVE_VPT_VEC_T2:
5419 case MVE_VPT_VEC_T3:
5420 case MVE_VPT_VEC_T4:
5421 case MVE_VPT_VEC_T5:
5422 case MVE_VPT_VEC_T6:
5423 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5424 return TRUE;
5425 if (arm_decode_field (given, 20, 21) == 3)
5426 return TRUE;
5427 return FALSE;
5428
5429 case MVE_VCMP_FP_T1:
5430 if ((arm_decode_field (given, 12, 12) == 0)
5431 && (arm_decode_field (given, 0, 0) == 1))
5432 return TRUE;
5433 else
5434 return FALSE;
5435
5436 case MVE_VCMP_FP_T2:
5437 if (arm_decode_field (given, 0, 3) == 0xd)
5438 return TRUE;
5439 else
5440 return FALSE;
5441
5442 case MVE_VQADD_T2:
5443 case MVE_VQSUB_T2:
5444 case MVE_VMUL_VEC_T2:
5445 case MVE_VMULH:
5446 case MVE_VRMULH:
5447 case MVE_VMLA:
5448 case MVE_VMAX:
5449 case MVE_VMIN:
5450 case MVE_VBRSR:
5451 case MVE_VADD_VEC_T2:
5452 case MVE_VSUB_VEC_T2:
5453 case MVE_VABAV:
5454 case MVE_VQRSHL_T1:
5455 case MVE_VQSHL_T4:
5456 case MVE_VRSHL_T1:
5457 case MVE_VSHL_T3:
5458 case MVE_VCADD_VEC:
5459 case MVE_VHCADD:
5460 case MVE_VDDUP:
5461 case MVE_VIDUP:
5462 case MVE_VQRDMLADH:
5463 case MVE_VQDMLAH:
5464 case MVE_VQRDMLAH:
5465 case MVE_VQDMLASH:
5466 case MVE_VQRDMLASH:
5467 case MVE_VQDMLSDH:
5468 case MVE_VQRDMLSDH:
5469 case MVE_VQDMULH_T3:
5470 case MVE_VQRDMULH_T4:
5471 case MVE_VQDMLADH:
5472 case MVE_VMLAS:
5473 case MVE_VMULL_INT:
5474 case MVE_VHADD_T2:
5475 case MVE_VHSUB_T2:
5476 case MVE_VCMP_VEC_T1:
5477 case MVE_VCMP_VEC_T2:
5478 case MVE_VCMP_VEC_T3:
5479 case MVE_VCMP_VEC_T4:
5480 case MVE_VCMP_VEC_T5:
5481 case MVE_VCMP_VEC_T6:
5482 if (arm_decode_field (given, 20, 21) == 3)
5483 return TRUE;
5484 else
5485 return FALSE;
5486
5487 case MVE_VLD2:
5488 case MVE_VLD4:
5489 case MVE_VST2:
5490 case MVE_VST4:
5491 if (arm_decode_field (given, 7, 8) == 3)
5492 return TRUE;
5493 else
5494 return FALSE;
5495
5496 case MVE_VSTRB_T1:
5497 case MVE_VSTRH_T2:
5498 if ((arm_decode_field (given, 24, 24) == 0)
5499 && (arm_decode_field (given, 21, 21) == 0))
5500 {
5501 return TRUE;
5502 }
5503 else if ((arm_decode_field (given, 7, 8) == 3))
5504 return TRUE;
5505 else
5506 return FALSE;
5507
5508 case MVE_VSTRB_T5:
5509 case MVE_VSTRH_T6:
5510 case MVE_VSTRW_T7:
5511 if ((arm_decode_field (given, 24, 24) == 0)
5512 && (arm_decode_field (given, 21, 21) == 0))
5513 {
5514 return TRUE;
5515 }
5516 else
5517 return FALSE;
5518
5519 case MVE_VCVT_FP_FIX_VEC:
5520 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5521
5522 case MVE_VBIC_IMM:
5523 case MVE_VORR_IMM:
5524 {
5525 unsigned long cmode = arm_decode_field (given, 8, 11);
5526
5527 if ((cmode & 1) == 0)
5528 return TRUE;
5529 else if ((cmode & 0xc) == 0xc)
5530 return TRUE;
5531 else
5532 return FALSE;
5533 }
5534
5535 case MVE_VMVN_IMM:
5536 {
5537 unsigned long cmode = arm_decode_field (given, 8, 11);
5538
5539 if ((cmode & 9) == 1)
5540 return TRUE;
5541 else if ((cmode & 5) == 1)
5542 return TRUE;
5543 else if ((cmode & 0xe) == 0xe)
5544 return TRUE;
5545 else
5546 return FALSE;
5547 }
5548
5549 case MVE_VMOV_IMM_TO_VEC:
5550 if ((arm_decode_field (given, 5, 5) == 1)
5551 && (arm_decode_field (given, 8, 11) != 0xe))
5552 return TRUE;
5553 else
5554 return FALSE;
5555
5556 case MVE_VMOVL:
5557 {
5558 unsigned long size = arm_decode_field (given, 19, 20);
5559 if ((size == 0) || (size == 3))
5560 return TRUE;
5561 else
5562 return FALSE;
5563 }
5564
5565 case MVE_VMAXA:
5566 case MVE_VMINA:
5567 case MVE_VMAXV:
5568 case MVE_VMAXAV:
5569 case MVE_VMINV:
5570 case MVE_VMINAV:
5571 case MVE_VQRSHL_T2:
5572 case MVE_VQSHL_T1:
5573 case MVE_VRSHL_T2:
5574 case MVE_VSHL_T2:
5575 case MVE_VSHLL_T2:
5576 case MVE_VADDV:
5577 case MVE_VMOVN:
5578 case MVE_VQMOVUN:
5579 case MVE_VQMOVN:
5580 if (arm_decode_field (given, 18, 19) == 3)
5581 return TRUE;
5582 else
5583 return FALSE;
5584
5585 case MVE_VMLSLDAV:
5586 case MVE_VRMLSLDAVH:
5587 case MVE_VMLALDAV:
5588 case MVE_VADDLV:
5589 if (arm_decode_field (given, 20, 22) == 7)
5590 return TRUE;
5591 else
5592 return FALSE;
5593
5594 case MVE_VRMLALDAVH:
5595 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5596 return TRUE;
5597 else
5598 return FALSE;
5599
5600 case MVE_VDWDUP:
5601 case MVE_VIWDUP:
5602 if ((arm_decode_field (given, 20, 21) == 3)
5603 || (arm_decode_field (given, 1, 3) == 7))
5604 return TRUE;
5605 else
5606 return FALSE;
5607
5608
5609 case MVE_VSHLL_T1:
5610 if (arm_decode_field (given, 16, 18) == 0)
5611 {
5612 unsigned long sz = arm_decode_field (given, 19, 20);
5613
5614 if ((sz == 1) || (sz == 2))
5615 return TRUE;
5616 else
5617 return FALSE;
5618 }
5619 else
5620 return FALSE;
5621
5622 case MVE_VQSHL_T2:
5623 case MVE_VQSHLU_T3:
5624 case MVE_VRSHR:
5625 case MVE_VSHL_T1:
5626 case MVE_VSHR:
5627 case MVE_VSLI:
5628 case MVE_VSRI:
5629 if (arm_decode_field (given, 19, 21) == 0)
5630 return TRUE;
5631 else
5632 return FALSE;
5633
5634 case MVE_VCTP:
5635 if (arm_decode_field (given, 16, 19) == 0xf)
5636 return TRUE;
5637 else
5638 return FALSE;
5639
5640 case MVE_ASRLI:
5641 case MVE_ASRL:
5642 case MVE_LSLLI:
5643 case MVE_LSLL:
5644 case MVE_LSRL:
5645 case MVE_SQRSHRL:
5646 case MVE_SQSHLL:
5647 case MVE_SRSHRL:
5648 case MVE_UQRSHLL:
5649 case MVE_UQSHLL:
5650 case MVE_URSHRL:
5651 if (arm_decode_field (given, 9, 11) == 0x7)
5652 return TRUE;
5653 else
5654 return FALSE;
5655
5656 default:
5657 case MVE_VADD_FP_T1:
5658 case MVE_VADD_FP_T2:
5659 case MVE_VADD_VEC_T1:
5660 return FALSE;
5661
5662 }
5663 }
5664
5665 static void
5666 print_mve_vld_str_addr (struct disassemble_info *info,
5667 unsigned long given,
5668 enum mve_instructions matched_insn)
5669 {
5670 void *stream = info->stream;
5671 fprintf_ftype func = info->fprintf_func;
5672
5673 unsigned long p, w, gpr, imm, add, mod_imm;
5674
5675 imm = arm_decode_field (given, 0, 6);
5676 mod_imm = imm;
5677
5678 switch (matched_insn)
5679 {
5680 case MVE_VLDRB_T1:
5681 case MVE_VSTRB_T1:
5682 gpr = arm_decode_field (given, 16, 18);
5683 break;
5684
5685 case MVE_VLDRH_T2:
5686 case MVE_VSTRH_T2:
5687 gpr = arm_decode_field (given, 16, 18);
5688 mod_imm = imm << 1;
5689 break;
5690
5691 case MVE_VLDRH_T6:
5692 case MVE_VSTRH_T6:
5693 gpr = arm_decode_field (given, 16, 19);
5694 mod_imm = imm << 1;
5695 break;
5696
5697 case MVE_VLDRW_T7:
5698 case MVE_VSTRW_T7:
5699 gpr = arm_decode_field (given, 16, 19);
5700 mod_imm = imm << 2;
5701 break;
5702
5703 case MVE_VLDRB_T5:
5704 case MVE_VSTRB_T5:
5705 gpr = arm_decode_field (given, 16, 19);
5706 break;
5707
5708 default:
5709 return;
5710 }
5711
5712 p = arm_decode_field (given, 24, 24);
5713 w = arm_decode_field (given, 21, 21);
5714
5715 add = arm_decode_field (given, 23, 23);
5716
5717 char * add_sub;
5718
5719 /* Don't print anything for '+' as it is implied. */
5720 if (add == 1)
5721 add_sub = "";
5722 else
5723 add_sub = "-";
5724
5725 if (p == 1)
5726 {
5727 /* Offset mode. */
5728 if (w == 0)
5729 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5730 /* Pre-indexed mode. */
5731 else
5732 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5733 }
5734 else if ((p == 0) && (w == 1))
5735 /* Post-index mode. */
5736 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5737 }
5738
5739 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5740 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5741 this encoding is undefined. */
5742
5743 static bfd_boolean
5744 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5745 enum mve_undefined *undefined_code)
5746 {
5747 *undefined_code = UNDEF_NONE;
5748
5749 switch (matched_insn)
5750 {
5751 case MVE_VDUP:
5752 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5753 {
5754 *undefined_code = UNDEF_SIZE_3;
5755 return TRUE;
5756 }
5757 else
5758 return FALSE;
5759
5760 case MVE_VQADD_T1:
5761 case MVE_VQSUB_T1:
5762 case MVE_VMUL_VEC_T1:
5763 case MVE_VABD_VEC:
5764 case MVE_VADD_VEC_T1:
5765 case MVE_VSUB_VEC_T1:
5766 case MVE_VQDMULH_T1:
5767 case MVE_VQRDMULH_T2:
5768 case MVE_VRHADD:
5769 case MVE_VHADD_T1:
5770 case MVE_VHSUB_T1:
5771 if (arm_decode_field (given, 20, 21) == 3)
5772 {
5773 *undefined_code = UNDEF_SIZE_3;
5774 return TRUE;
5775 }
5776 else
5777 return FALSE;
5778
5779 case MVE_VLDRB_T1:
5780 if (arm_decode_field (given, 7, 8) == 3)
5781 {
5782 *undefined_code = UNDEF_SIZE_3;
5783 return TRUE;
5784 }
5785 else
5786 return FALSE;
5787
5788 case MVE_VLDRH_T2:
5789 if (arm_decode_field (given, 7, 8) <= 1)
5790 {
5791 *undefined_code = UNDEF_SIZE_LE_1;
5792 return TRUE;
5793 }
5794 else
5795 return FALSE;
5796
5797 case MVE_VSTRB_T1:
5798 if ((arm_decode_field (given, 7, 8) == 0))
5799 {
5800 *undefined_code = UNDEF_SIZE_0;
5801 return TRUE;
5802 }
5803 else
5804 return FALSE;
5805
5806 case MVE_VSTRH_T2:
5807 if ((arm_decode_field (given, 7, 8) <= 1))
5808 {
5809 *undefined_code = UNDEF_SIZE_LE_1;
5810 return TRUE;
5811 }
5812 else
5813 return FALSE;
5814
5815 case MVE_VLDRB_GATHER_T1:
5816 if (arm_decode_field (given, 7, 8) == 3)
5817 {
5818 *undefined_code = UNDEF_SIZE_3;
5819 return TRUE;
5820 }
5821 else if ((arm_decode_field (given, 28, 28) == 0)
5822 && (arm_decode_field (given, 7, 8) == 0))
5823 {
5824 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5825 return TRUE;
5826 }
5827 else
5828 return FALSE;
5829
5830 case MVE_VLDRH_GATHER_T2:
5831 if (arm_decode_field (given, 7, 8) == 3)
5832 {
5833 *undefined_code = UNDEF_SIZE_3;
5834 return TRUE;
5835 }
5836 else if ((arm_decode_field (given, 28, 28) == 0)
5837 && (arm_decode_field (given, 7, 8) == 1))
5838 {
5839 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5840 return TRUE;
5841 }
5842 else if (arm_decode_field (given, 7, 8) == 0)
5843 {
5844 *undefined_code = UNDEF_SIZE_0;
5845 return TRUE;
5846 }
5847 else
5848 return FALSE;
5849
5850 case MVE_VLDRW_GATHER_T3:
5851 if (arm_decode_field (given, 7, 8) != 2)
5852 {
5853 *undefined_code = UNDEF_SIZE_NOT_2;
5854 return TRUE;
5855 }
5856 else if (arm_decode_field (given, 28, 28) == 0)
5857 {
5858 *undefined_code = UNDEF_NOT_UNSIGNED;
5859 return TRUE;
5860 }
5861 else
5862 return FALSE;
5863
5864 case MVE_VLDRD_GATHER_T4:
5865 if (arm_decode_field (given, 7, 8) != 3)
5866 {
5867 *undefined_code = UNDEF_SIZE_NOT_3;
5868 return TRUE;
5869 }
5870 else if (arm_decode_field (given, 28, 28) == 0)
5871 {
5872 *undefined_code = UNDEF_NOT_UNSIGNED;
5873 return TRUE;
5874 }
5875 else
5876 return FALSE;
5877
5878 case MVE_VSTRB_SCATTER_T1:
5879 if (arm_decode_field (given, 7, 8) == 3)
5880 {
5881 *undefined_code = UNDEF_SIZE_3;
5882 return TRUE;
5883 }
5884 else
5885 return FALSE;
5886
5887 case MVE_VSTRH_SCATTER_T2:
5888 {
5889 unsigned long size = arm_decode_field (given, 7, 8);
5890 if (size == 3)
5891 {
5892 *undefined_code = UNDEF_SIZE_3;
5893 return TRUE;
5894 }
5895 else if (size == 0)
5896 {
5897 *undefined_code = UNDEF_SIZE_0;
5898 return TRUE;
5899 }
5900 else
5901 return FALSE;
5902 }
5903
5904 case MVE_VSTRW_SCATTER_T3:
5905 if (arm_decode_field (given, 7, 8) != 2)
5906 {
5907 *undefined_code = UNDEF_SIZE_NOT_2;
5908 return TRUE;
5909 }
5910 else
5911 return FALSE;
5912
5913 case MVE_VSTRD_SCATTER_T4:
5914 if (arm_decode_field (given, 7, 8) != 3)
5915 {
5916 *undefined_code = UNDEF_SIZE_NOT_3;
5917 return TRUE;
5918 }
5919 else
5920 return FALSE;
5921
5922 case MVE_VCVT_FP_FIX_VEC:
5923 {
5924 unsigned long imm6 = arm_decode_field (given, 16, 21);
5925 if ((imm6 & 0x20) == 0)
5926 {
5927 *undefined_code = UNDEF_VCVT_IMM6;
5928 return TRUE;
5929 }
5930
5931 if ((arm_decode_field (given, 9, 9) == 0)
5932 && ((imm6 & 0x30) == 0x20))
5933 {
5934 *undefined_code = UNDEF_VCVT_FSI_IMM6;
5935 return TRUE;
5936 }
5937
5938 return FALSE;
5939 }
5940
5941 case MVE_VNEG_FP:
5942 case MVE_VABS_FP:
5943 case MVE_VCVT_BETWEEN_FP_INT:
5944 case MVE_VCVT_FROM_FP_TO_INT:
5945 {
5946 unsigned long size = arm_decode_field (given, 18, 19);
5947 if (size == 0)
5948 {
5949 *undefined_code = UNDEF_SIZE_0;
5950 return TRUE;
5951 }
5952 else if (size == 3)
5953 {
5954 *undefined_code = UNDEF_SIZE_3;
5955 return TRUE;
5956 }
5957 else
5958 return FALSE;
5959 }
5960
5961 case MVE_VMOV_VEC_LANE_TO_GP:
5962 {
5963 unsigned long op1 = arm_decode_field (given, 21, 22);
5964 unsigned long op2 = arm_decode_field (given, 5, 6);
5965 unsigned long u = arm_decode_field (given, 23, 23);
5966
5967 if ((op2 == 0) && (u == 1))
5968 {
5969 if ((op1 == 0) || (op1 == 1))
5970 {
5971 *undefined_code = UNDEF_BAD_U_OP1_OP2;
5972 return TRUE;
5973 }
5974 else
5975 return FALSE;
5976 }
5977 else if (op2 == 2)
5978 {
5979 if ((op1 == 0) || (op1 == 1))
5980 {
5981 *undefined_code = UNDEF_BAD_OP1_OP2;
5982 return TRUE;
5983 }
5984 else
5985 return FALSE;
5986 }
5987
5988 return FALSE;
5989 }
5990
5991 case MVE_VMOV_GP_TO_VEC_LANE:
5992 if (arm_decode_field (given, 5, 6) == 2)
5993 {
5994 unsigned long op1 = arm_decode_field (given, 21, 22);
5995 if ((op1 == 0) || (op1 == 1))
5996 {
5997 *undefined_code = UNDEF_BAD_OP1_OP2;
5998 return TRUE;
5999 }
6000 else
6001 return FALSE;
6002 }
6003 else
6004 return FALSE;
6005
6006 case MVE_VMOV_IMM_TO_VEC:
6007 if (arm_decode_field (given, 5, 5) == 0)
6008 {
6009 unsigned long cmode = arm_decode_field (given, 8, 11);
6010
6011 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6012 {
6013 *undefined_code = UNDEF_OP_0_BAD_CMODE;
6014 return TRUE;
6015 }
6016 else
6017 return FALSE;
6018 }
6019 else
6020 return FALSE;
6021
6022 case MVE_VSHLL_T2:
6023 case MVE_VMOVN:
6024 if (arm_decode_field (given, 18, 19) == 2)
6025 {
6026 *undefined_code = UNDEF_SIZE_2;
6027 return TRUE;
6028 }
6029 else
6030 return FALSE;
6031
6032 case MVE_VRMLALDAVH:
6033 case MVE_VMLADAV_T1:
6034 case MVE_VMLADAV_T2:
6035 case MVE_VMLALDAV:
6036 if ((arm_decode_field (given, 28, 28) == 1)
6037 && (arm_decode_field (given, 12, 12) == 1))
6038 {
6039 *undefined_code = UNDEF_XCHG_UNS;
6040 return TRUE;
6041 }
6042 else
6043 return FALSE;
6044
6045 case MVE_VQSHRN:
6046 case MVE_VQSHRUN:
6047 case MVE_VSHLL_T1:
6048 case MVE_VSHRN:
6049 {
6050 unsigned long sz = arm_decode_field (given, 19, 20);
6051 if (sz == 1)
6052 return FALSE;
6053 else if ((sz & 2) == 2)
6054 return FALSE;
6055 else
6056 {
6057 *undefined_code = UNDEF_SIZE;
6058 return TRUE;
6059 }
6060 }
6061 break;
6062
6063 case MVE_VQSHL_T2:
6064 case MVE_VQSHLU_T3:
6065 case MVE_VRSHR:
6066 case MVE_VSHL_T1:
6067 case MVE_VSHR:
6068 case MVE_VSLI:
6069 case MVE_VSRI:
6070 {
6071 unsigned long sz = arm_decode_field (given, 19, 21);
6072 if ((sz & 7) == 1)
6073 return FALSE;
6074 else if ((sz & 6) == 2)
6075 return FALSE;
6076 else if ((sz & 4) == 4)
6077 return FALSE;
6078 else
6079 {
6080 *undefined_code = UNDEF_SIZE;
6081 return TRUE;
6082 }
6083 }
6084
6085 case MVE_VQRSHRN:
6086 case MVE_VQRSHRUN:
6087 if (arm_decode_field (given, 19, 20) == 0)
6088 {
6089 *undefined_code = UNDEF_SIZE_0;
6090 return TRUE;
6091 }
6092 else
6093 return FALSE;
6094
6095 case MVE_VABS_VEC:
6096 if (arm_decode_field (given, 18, 19) == 3)
6097 {
6098 *undefined_code = UNDEF_SIZE_3;
6099 return TRUE;
6100 }
6101 else
6102 return FALSE;
6103
6104 case MVE_VQNEG:
6105 case MVE_VQABS:
6106 case MVE_VNEG_VEC:
6107 case MVE_VCLS:
6108 case MVE_VCLZ:
6109 if (arm_decode_field (given, 18, 19) == 3)
6110 {
6111 *undefined_code = UNDEF_SIZE_3;
6112 return TRUE;
6113 }
6114 else
6115 return FALSE;
6116
6117 case MVE_VREV16:
6118 if (arm_decode_field (given, 18, 19) == 0)
6119 return FALSE;
6120 else
6121 {
6122 *undefined_code = UNDEF_SIZE_NOT_0;
6123 return TRUE;
6124 }
6125
6126 case MVE_VREV32:
6127 {
6128 unsigned long size = arm_decode_field (given, 18, 19);
6129 if ((size & 2) == 2)
6130 {
6131 *undefined_code = UNDEF_SIZE_2;
6132 return TRUE;
6133 }
6134 else
6135 return FALSE;
6136 }
6137
6138 case MVE_VREV64:
6139 if (arm_decode_field (given, 18, 19) != 3)
6140 return FALSE;
6141 else
6142 {
6143 *undefined_code = UNDEF_SIZE_3;
6144 return TRUE;
6145 }
6146
6147 default:
6148 return FALSE;
6149 }
6150 }
6151
6152 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6153 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6154 why this encoding is unpredictable. */
6155
6156 static bfd_boolean
6157 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6158 enum mve_unpredictable *unpredictable_code)
6159 {
6160 *unpredictable_code = UNPRED_NONE;
6161
6162 switch (matched_insn)
6163 {
6164 case MVE_VCMP_FP_T2:
6165 case MVE_VPT_FP_T2:
6166 if ((arm_decode_field (given, 12, 12) == 0)
6167 && (arm_decode_field (given, 5, 5) == 1))
6168 {
6169 *unpredictable_code = UNPRED_FCA_0_FCB_1;
6170 return TRUE;
6171 }
6172 else
6173 return FALSE;
6174
6175 case MVE_VPT_VEC_T4:
6176 case MVE_VPT_VEC_T5:
6177 case MVE_VPT_VEC_T6:
6178 case MVE_VCMP_VEC_T4:
6179 case MVE_VCMP_VEC_T5:
6180 case MVE_VCMP_VEC_T6:
6181 if (arm_decode_field (given, 0, 3) == 0xd)
6182 {
6183 *unpredictable_code = UNPRED_R13;
6184 return TRUE;
6185 }
6186 else
6187 return FALSE;
6188
6189 case MVE_VDUP:
6190 {
6191 unsigned long gpr = arm_decode_field (given, 12, 15);
6192 if (gpr == 0xd)
6193 {
6194 *unpredictable_code = UNPRED_R13;
6195 return TRUE;
6196 }
6197 else if (gpr == 0xf)
6198 {
6199 *unpredictable_code = UNPRED_R15;
6200 return TRUE;
6201 }
6202
6203 return FALSE;
6204 }
6205
6206 case MVE_VQADD_T2:
6207 case MVE_VQSUB_T2:
6208 case MVE_VMUL_FP_T2:
6209 case MVE_VMUL_VEC_T2:
6210 case MVE_VMLA:
6211 case MVE_VBRSR:
6212 case MVE_VADD_FP_T2:
6213 case MVE_VSUB_FP_T2:
6214 case MVE_VADD_VEC_T2:
6215 case MVE_VSUB_VEC_T2:
6216 case MVE_VQRSHL_T2:
6217 case MVE_VQSHL_T1:
6218 case MVE_VRSHL_T2:
6219 case MVE_VSHL_T2:
6220 case MVE_VSHLC:
6221 case MVE_VQDMLAH:
6222 case MVE_VQRDMLAH:
6223 case MVE_VQDMLASH:
6224 case MVE_VQRDMLASH:
6225 case MVE_VQDMULH_T3:
6226 case MVE_VQRDMULH_T4:
6227 case MVE_VMLAS:
6228 case MVE_VFMA_FP_SCALAR:
6229 case MVE_VFMAS_FP_SCALAR:
6230 case MVE_VHADD_T2:
6231 case MVE_VHSUB_T2:
6232 {
6233 unsigned long gpr = arm_decode_field (given, 0, 3);
6234 if (gpr == 0xd)
6235 {
6236 *unpredictable_code = UNPRED_R13;
6237 return TRUE;
6238 }
6239 else if (gpr == 0xf)
6240 {
6241 *unpredictable_code = UNPRED_R15;
6242 return TRUE;
6243 }
6244
6245 return FALSE;
6246 }
6247
6248 case MVE_VLD2:
6249 case MVE_VST2:
6250 {
6251 unsigned long rn = arm_decode_field (given, 16, 19);
6252
6253 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6254 {
6255 *unpredictable_code = UNPRED_R13_AND_WB;
6256 return TRUE;
6257 }
6258
6259 if (rn == 0xf)
6260 {
6261 *unpredictable_code = UNPRED_R15;
6262 return TRUE;
6263 }
6264
6265 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6266 {
6267 *unpredictable_code = UNPRED_Q_GT_6;
6268 return TRUE;
6269 }
6270 else
6271 return FALSE;
6272 }
6273
6274 case MVE_VLD4:
6275 case MVE_VST4:
6276 {
6277 unsigned long rn = arm_decode_field (given, 16, 19);
6278
6279 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6280 {
6281 *unpredictable_code = UNPRED_R13_AND_WB;
6282 return TRUE;
6283 }
6284
6285 if (rn == 0xf)
6286 {
6287 *unpredictable_code = UNPRED_R15;
6288 return TRUE;
6289 }
6290
6291 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6292 {
6293 *unpredictable_code = UNPRED_Q_GT_4;
6294 return TRUE;
6295 }
6296 else
6297 return FALSE;
6298 }
6299
6300 case MVE_VLDRB_T5:
6301 case MVE_VLDRH_T6:
6302 case MVE_VLDRW_T7:
6303 case MVE_VSTRB_T5:
6304 case MVE_VSTRH_T6:
6305 case MVE_VSTRW_T7:
6306 {
6307 unsigned long rn = arm_decode_field (given, 16, 19);
6308
6309 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6310 {
6311 *unpredictable_code = UNPRED_R13_AND_WB;
6312 return TRUE;
6313 }
6314 else if (rn == 0xf)
6315 {
6316 *unpredictable_code = UNPRED_R15;
6317 return TRUE;
6318 }
6319 else
6320 return FALSE;
6321 }
6322
6323 case MVE_VLDRB_GATHER_T1:
6324 if (arm_decode_field (given, 0, 0) == 1)
6325 {
6326 *unpredictable_code = UNPRED_OS;
6327 return TRUE;
6328 }
6329
6330 /* fall through. */
6331 /* To handle common code with T2-T4 variants. */
6332 case MVE_VLDRH_GATHER_T2:
6333 case MVE_VLDRW_GATHER_T3:
6334 case MVE_VLDRD_GATHER_T4:
6335 {
6336 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6337 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6338
6339 if (qd == qm)
6340 {
6341 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6342 return TRUE;
6343 }
6344
6345 if (arm_decode_field (given, 16, 19) == 0xf)
6346 {
6347 *unpredictable_code = UNPRED_R15;
6348 return TRUE;
6349 }
6350
6351 return FALSE;
6352 }
6353
6354 case MVE_VLDRW_GATHER_T5:
6355 case MVE_VLDRD_GATHER_T6:
6356 {
6357 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6358 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6359
6360 if (qd == qm)
6361 {
6362 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6363 return TRUE;
6364 }
6365 else
6366 return FALSE;
6367 }
6368
6369 case MVE_VSTRB_SCATTER_T1:
6370 if (arm_decode_field (given, 16, 19) == 0xf)
6371 {
6372 *unpredictable_code = UNPRED_R15;
6373 return TRUE;
6374 }
6375 else if (arm_decode_field (given, 0, 0) == 1)
6376 {
6377 *unpredictable_code = UNPRED_OS;
6378 return TRUE;
6379 }
6380 else
6381 return FALSE;
6382
6383 case MVE_VSTRH_SCATTER_T2:
6384 case MVE_VSTRW_SCATTER_T3:
6385 case MVE_VSTRD_SCATTER_T4:
6386 if (arm_decode_field (given, 16, 19) == 0xf)
6387 {
6388 *unpredictable_code = UNPRED_R15;
6389 return TRUE;
6390 }
6391 else
6392 return FALSE;
6393
6394 case MVE_VMOV2_VEC_LANE_TO_GP:
6395 case MVE_VMOV2_GP_TO_VEC_LANE:
6396 case MVE_VCVT_BETWEEN_FP_INT:
6397 case MVE_VCVT_FROM_FP_TO_INT:
6398 {
6399 unsigned long rt = arm_decode_field (given, 0, 3);
6400 unsigned long rt2 = arm_decode_field (given, 16, 19);
6401
6402 if ((rt == 0xd) || (rt2 == 0xd))
6403 {
6404 *unpredictable_code = UNPRED_R13;
6405 return TRUE;
6406 }
6407 else if ((rt == 0xf) || (rt2 == 0xf))
6408 {
6409 *unpredictable_code = UNPRED_R15;
6410 return TRUE;
6411 }
6412 else if (rt == rt2)
6413 {
6414 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6415 return TRUE;
6416 }
6417
6418 return FALSE;
6419 }
6420
6421 case MVE_VMAXV:
6422 case MVE_VMAXAV:
6423 case MVE_VMAXNMV_FP:
6424 case MVE_VMAXNMAV_FP:
6425 case MVE_VMINNMV_FP:
6426 case MVE_VMINNMAV_FP:
6427 case MVE_VMINV:
6428 case MVE_VMINAV:
6429 case MVE_VABAV:
6430 case MVE_VMOV_HFP_TO_GP:
6431 case MVE_VMOV_GP_TO_VEC_LANE:
6432 case MVE_VMOV_VEC_LANE_TO_GP:
6433 {
6434 unsigned long rda = arm_decode_field (given, 12, 15);
6435 if (rda == 0xd)
6436 {
6437 *unpredictable_code = UNPRED_R13;
6438 return TRUE;
6439 }
6440 else if (rda == 0xf)
6441 {
6442 *unpredictable_code = UNPRED_R15;
6443 return TRUE;
6444 }
6445
6446 return FALSE;
6447 }
6448
6449 case MVE_VQRDMLADH:
6450 case MVE_VQDMLSDH:
6451 case MVE_VQRDMLSDH:
6452 case MVE_VQDMLADH:
6453 case MVE_VMULL_INT:
6454 {
6455 unsigned long Qd;
6456 unsigned long Qm;
6457 unsigned long Qn;
6458
6459 if (arm_decode_field (given, 20, 21) == 2)
6460 {
6461 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6462 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6463 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6464
6465 if ((Qd == Qn) || (Qd == Qm))
6466 {
6467 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6468 return TRUE;
6469 }
6470 else
6471 return FALSE;
6472 }
6473 else
6474 return FALSE;
6475 }
6476
6477 case MVE_VCMUL_FP:
6478 case MVE_VQDMULL_T1:
6479 {
6480 unsigned long Qd;
6481 unsigned long Qm;
6482 unsigned long Qn;
6483
6484 if (arm_decode_field (given, 28, 28) == 1)
6485 {
6486 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6487 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6488 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6489
6490 if ((Qd == Qn) || (Qd == Qm))
6491 {
6492 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6493 return TRUE;
6494 }
6495 else
6496 return FALSE;
6497 }
6498 else
6499 return FALSE;
6500 }
6501
6502 case MVE_VQDMULL_T2:
6503 {
6504 unsigned long gpr = arm_decode_field (given, 0, 3);
6505 if (gpr == 0xd)
6506 {
6507 *unpredictable_code = UNPRED_R13;
6508 return TRUE;
6509 }
6510 else if (gpr == 0xf)
6511 {
6512 *unpredictable_code = UNPRED_R15;
6513 return TRUE;
6514 }
6515
6516 if (arm_decode_field (given, 28, 28) == 1)
6517 {
6518 unsigned long Qd
6519 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6520 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6521
6522 if ((Qd == Qn))
6523 {
6524 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6525 return TRUE;
6526 }
6527 else
6528 return FALSE;
6529 }
6530
6531 return FALSE;
6532 }
6533
6534 case MVE_VMLSLDAV:
6535 case MVE_VRMLSLDAVH:
6536 case MVE_VMLALDAV:
6537 case MVE_VADDLV:
6538 if (arm_decode_field (given, 20, 22) == 6)
6539 {
6540 *unpredictable_code = UNPRED_R13;
6541 return TRUE;
6542 }
6543 else
6544 return FALSE;
6545
6546 case MVE_VDWDUP:
6547 case MVE_VIWDUP:
6548 if (arm_decode_field (given, 1, 3) == 6)
6549 {
6550 *unpredictable_code = UNPRED_R13;
6551 return TRUE;
6552 }
6553 else
6554 return FALSE;
6555
6556 case MVE_VCADD_VEC:
6557 case MVE_VHCADD:
6558 {
6559 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6560 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6561 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6562 {
6563 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6564 return TRUE;
6565 }
6566 else
6567 return FALSE;
6568 }
6569
6570 case MVE_VCADD_FP:
6571 {
6572 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6573 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6574 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6575 {
6576 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6577 return TRUE;
6578 }
6579 else
6580 return FALSE;
6581 }
6582
6583 case MVE_VCMLA_FP:
6584 {
6585 unsigned long Qda;
6586 unsigned long Qm;
6587 unsigned long Qn;
6588
6589 if (arm_decode_field (given, 20, 20) == 1)
6590 {
6591 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6592 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6593 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6594
6595 if ((Qda == Qn) || (Qda == Qm))
6596 {
6597 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6598 return TRUE;
6599 }
6600 else
6601 return FALSE;
6602 }
6603 else
6604 return FALSE;
6605
6606 }
6607
6608 case MVE_VCTP:
6609 if (arm_decode_field (given, 16, 19) == 0xd)
6610 {
6611 *unpredictable_code = UNPRED_R13;
6612 return TRUE;
6613 }
6614 else
6615 return FALSE;
6616
6617 case MVE_VREV64:
6618 {
6619 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6620 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6621
6622 if (qd == qm)
6623 {
6624 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6625 return TRUE;
6626 }
6627 else
6628 return FALSE;
6629 }
6630
6631 case MVE_LSLL:
6632 case MVE_LSLLI:
6633 case MVE_LSRL:
6634 case MVE_ASRL:
6635 case MVE_ASRLI:
6636 case MVE_UQSHLL:
6637 case MVE_UQRSHLL:
6638 case MVE_URSHRL:
6639 case MVE_SRSHRL:
6640 case MVE_SQSHLL:
6641 case MVE_SQRSHRL:
6642 {
6643 unsigned long gpr = arm_decode_field (given, 9, 11);
6644 gpr = ((gpr << 1) | 1);
6645 if (gpr == 0xd)
6646 {
6647 *unpredictable_code = UNPRED_R13;
6648 return TRUE;
6649 }
6650 else if (gpr == 0xf)
6651 {
6652 *unpredictable_code = UNPRED_R15;
6653 return TRUE;
6654 }
6655
6656 return FALSE;
6657 }
6658
6659 default:
6660 return FALSE;
6661 }
6662 }
6663
6664 static void
6665 print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6666 {
6667 unsigned long op1 = arm_decode_field (given, 21, 22);
6668 unsigned long op2 = arm_decode_field (given, 5, 6);
6669 unsigned long h = arm_decode_field (given, 16, 16);
6670 unsigned long index, esize, targetBeat, idx;
6671 void *stream = info->stream;
6672 fprintf_ftype func = info->fprintf_func;
6673
6674 if ((op1 & 0x2) == 0x2)
6675 {
6676 index = op2;
6677 esize = 8;
6678 }
6679 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6680 {
6681 index = op2 >> 1;
6682 esize = 16;
6683 }
6684 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6685 {
6686 index = 0;
6687 esize = 32;
6688 }
6689 else
6690 {
6691 func (stream, "<undefined index>");
6692 return;
6693 }
6694
6695 targetBeat = (op1 & 0x1) | (h << 1);
6696 idx = index + targetBeat * (32/esize);
6697
6698 func (stream, "%lu", idx);
6699 }
6700
6701 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6702 in length and integer of floating-point type. */
6703 static void
6704 print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6705 unsigned int ibit_loc, const struct mopcode32 *insn)
6706 {
6707 int bits = 0;
6708 int cmode = (given >> 8) & 0xf;
6709 int op = (given >> 5) & 0x1;
6710 unsigned long value = 0, hival = 0;
6711 unsigned shift;
6712 int size = 0;
6713 int isfloat = 0;
6714 void *stream = info->stream;
6715 fprintf_ftype func = info->fprintf_func;
6716
6717 /* On Neon the 'i' bit is at bit 24, on mve it is
6718 at bit 28. */
6719 bits |= ((given >> ibit_loc) & 1) << 7;
6720 bits |= ((given >> 16) & 7) << 4;
6721 bits |= ((given >> 0) & 15) << 0;
6722
6723 if (cmode < 8)
6724 {
6725 shift = (cmode >> 1) & 3;
6726 value = (unsigned long) bits << (8 * shift);
6727 size = 32;
6728 }
6729 else if (cmode < 12)
6730 {
6731 shift = (cmode >> 1) & 1;
6732 value = (unsigned long) bits << (8 * shift);
6733 size = 16;
6734 }
6735 else if (cmode < 14)
6736 {
6737 shift = (cmode & 1) + 1;
6738 value = (unsigned long) bits << (8 * shift);
6739 value |= (1ul << (8 * shift)) - 1;
6740 size = 32;
6741 }
6742 else if (cmode == 14)
6743 {
6744 if (op)
6745 {
6746 /* Bit replication into bytes. */
6747 int ix;
6748 unsigned long mask;
6749
6750 value = 0;
6751 hival = 0;
6752 for (ix = 7; ix >= 0; ix--)
6753 {
6754 mask = ((bits >> ix) & 1) ? 0xff : 0;
6755 if (ix <= 3)
6756 value = (value << 8) | mask;
6757 else
6758 hival = (hival << 8) | mask;
6759 }
6760 size = 64;
6761 }
6762 else
6763 {
6764 /* Byte replication. */
6765 value = (unsigned long) bits;
6766 size = 8;
6767 }
6768 }
6769 else if (!op)
6770 {
6771 /* Floating point encoding. */
6772 int tmp;
6773
6774 value = (unsigned long) (bits & 0x7f) << 19;
6775 value |= (unsigned long) (bits & 0x80) << 24;
6776 tmp = bits & 0x40 ? 0x3c : 0x40;
6777 value |= (unsigned long) tmp << 24;
6778 size = 32;
6779 isfloat = 1;
6780 }
6781 else
6782 {
6783 func (stream, "<illegal constant %.8x:%x:%x>",
6784 bits, cmode, op);
6785 size = 32;
6786 return;
6787 }
6788
6789 // printU determines whether the immediate value should be printed as
6790 // unsigned.
6791 unsigned printU = 0;
6792 switch (insn->mve_op)
6793 {
6794 default:
6795 break;
6796 // We want this for instructions that don't have a 'signed' type
6797 case MVE_VBIC_IMM:
6798 case MVE_VORR_IMM:
6799 case MVE_VMVN_IMM:
6800 case MVE_VMOV_IMM_TO_VEC:
6801 printU = 1;
6802 break;
6803 }
6804 switch (size)
6805 {
6806 case 8:
6807 func (stream, "#%ld\t; 0x%.2lx", value, value);
6808 break;
6809
6810 case 16:
6811 func (stream,
6812 printU
6813 ? "#%lu\t; 0x%.4lx"
6814 : "#%ld\t; 0x%.4lx", value, value);
6815 break;
6816
6817 case 32:
6818 if (isfloat)
6819 {
6820 unsigned char valbytes[4];
6821 double fvalue;
6822
6823 /* Do this a byte at a time so we don't have to
6824 worry about the host's endianness. */
6825 valbytes[0] = value & 0xff;
6826 valbytes[1] = (value >> 8) & 0xff;
6827 valbytes[2] = (value >> 16) & 0xff;
6828 valbytes[3] = (value >> 24) & 0xff;
6829
6830 floatformat_to_double
6831 (& floatformat_ieee_single_little, valbytes,
6832 & fvalue);
6833
6834 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6835 value);
6836 }
6837 else
6838 func (stream,
6839 printU
6840 ? "#%lu\t; 0x%.8lx"
6841 : "#%ld\t; 0x%.8lx",
6842 (long) (((value & 0x80000000L) != 0)
6843 && !printU
6844 ? value | ~0xffffffffL : value),
6845 value);
6846 break;
6847
6848 case 64:
6849 func (stream, "#0x%.8lx%.8lx", hival, value);
6850 break;
6851
6852 default:
6853 abort ();
6854 }
6855
6856 }
6857
6858 static void
6859 print_mve_undefined (struct disassemble_info *info,
6860 enum mve_undefined undefined_code)
6861 {
6862 void *stream = info->stream;
6863 fprintf_ftype func = info->fprintf_func;
6864
6865 func (stream, "\t\tundefined instruction: ");
6866
6867 switch (undefined_code)
6868 {
6869 case UNDEF_SIZE:
6870 func (stream, "illegal size");
6871 break;
6872
6873 case UNDEF_SIZE_0:
6874 func (stream, "size equals zero");
6875 break;
6876
6877 case UNDEF_SIZE_2:
6878 func (stream, "size equals two");
6879 break;
6880
6881 case UNDEF_SIZE_3:
6882 func (stream, "size equals three");
6883 break;
6884
6885 case UNDEF_SIZE_LE_1:
6886 func (stream, "size <= 1");
6887 break;
6888
6889 case UNDEF_SIZE_NOT_0:
6890 func (stream, "size not equal to 0");
6891 break;
6892
6893 case UNDEF_SIZE_NOT_2:
6894 func (stream, "size not equal to 2");
6895 break;
6896
6897 case UNDEF_SIZE_NOT_3:
6898 func (stream, "size not equal to 3");
6899 break;
6900
6901 case UNDEF_NOT_UNS_SIZE_0:
6902 func (stream, "not unsigned and size = zero");
6903 break;
6904
6905 case UNDEF_NOT_UNS_SIZE_1:
6906 func (stream, "not unsigned and size = one");
6907 break;
6908
6909 case UNDEF_NOT_UNSIGNED:
6910 func (stream, "not unsigned");
6911 break;
6912
6913 case UNDEF_VCVT_IMM6:
6914 func (stream, "invalid imm6");
6915 break;
6916
6917 case UNDEF_VCVT_FSI_IMM6:
6918 func (stream, "fsi = 0 and invalid imm6");
6919 break;
6920
6921 case UNDEF_BAD_OP1_OP2:
6922 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
6923 break;
6924
6925 case UNDEF_BAD_U_OP1_OP2:
6926 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
6927 break;
6928
6929 case UNDEF_OP_0_BAD_CMODE:
6930 func (stream, "op field equal 0 and bad cmode");
6931 break;
6932
6933 case UNDEF_XCHG_UNS:
6934 func (stream, "exchange and unsigned together");
6935 break;
6936
6937 case UNDEF_NONE:
6938 break;
6939 }
6940
6941 }
6942
6943 static void
6944 print_mve_unpredictable (struct disassemble_info *info,
6945 enum mve_unpredictable unpredict_code)
6946 {
6947 void *stream = info->stream;
6948 fprintf_ftype func = info->fprintf_func;
6949
6950 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
6951
6952 switch (unpredict_code)
6953 {
6954 case UNPRED_IT_BLOCK:
6955 func (stream, "mve instruction in it block");
6956 break;
6957
6958 case UNPRED_FCA_0_FCB_1:
6959 func (stream, "condition bits, fca = 0 and fcb = 1");
6960 break;
6961
6962 case UNPRED_R13:
6963 func (stream, "use of r13 (sp)");
6964 break;
6965
6966 case UNPRED_R15:
6967 func (stream, "use of r15 (pc)");
6968 break;
6969
6970 case UNPRED_Q_GT_4:
6971 func (stream, "start register block > r4");
6972 break;
6973
6974 case UNPRED_Q_GT_6:
6975 func (stream, "start register block > r6");
6976 break;
6977
6978 case UNPRED_R13_AND_WB:
6979 func (stream, "use of r13 and write back");
6980 break;
6981
6982 case UNPRED_Q_REGS_EQUAL:
6983 func (stream,
6984 "same vector register used for destination and other operand");
6985 break;
6986
6987 case UNPRED_OS:
6988 func (stream, "use of offset scaled");
6989 break;
6990
6991 case UNPRED_GP_REGS_EQUAL:
6992 func (stream, "same general-purpose register used for both operands");
6993 break;
6994
6995 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
6996 func (stream, "use of identical q registers and size = 1");
6997 break;
6998
6999 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7000 func (stream, "use of identical q registers and size = 1");
7001 break;
7002
7003 case UNPRED_NONE:
7004 break;
7005 }
7006 }
7007
7008 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
7009
7010 static void
7011 print_mve_register_blocks (struct disassemble_info *info,
7012 unsigned long given,
7013 enum mve_instructions matched_insn)
7014 {
7015 void *stream = info->stream;
7016 fprintf_ftype func = info->fprintf_func;
7017
7018 unsigned long q_reg_start = arm_decode_field_multiple (given,
7019 13, 15,
7020 22, 22);
7021 switch (matched_insn)
7022 {
7023 case MVE_VLD2:
7024 case MVE_VST2:
7025 if (q_reg_start <= 6)
7026 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7027 else
7028 func (stream, "<illegal reg q%ld>", q_reg_start);
7029 break;
7030
7031 case MVE_VLD4:
7032 case MVE_VST4:
7033 if (q_reg_start <= 4)
7034 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7035 q_reg_start + 1, q_reg_start + 2,
7036 q_reg_start + 3);
7037 else
7038 func (stream, "<illegal reg q%ld>", q_reg_start);
7039 break;
7040
7041 default:
7042 break;
7043 }
7044 }
7045
7046 static void
7047 print_mve_rounding_mode (struct disassemble_info *info,
7048 unsigned long given,
7049 enum mve_instructions matched_insn)
7050 {
7051 void *stream = info->stream;
7052 fprintf_ftype func = info->fprintf_func;
7053
7054 switch (matched_insn)
7055 {
7056 case MVE_VCVT_FROM_FP_TO_INT:
7057 {
7058 switch (arm_decode_field (given, 8, 9))
7059 {
7060 case 0:
7061 func (stream, "a");
7062 break;
7063
7064 case 1:
7065 func (stream, "n");
7066 break;
7067
7068 case 2:
7069 func (stream, "p");
7070 break;
7071
7072 case 3:
7073 func (stream, "m");
7074 break;
7075
7076 default:
7077 break;
7078 }
7079 }
7080 break;
7081
7082 case MVE_VRINT_FP:
7083 {
7084 switch (arm_decode_field (given, 7, 9))
7085 {
7086 case 0:
7087 func (stream, "n");
7088 break;
7089
7090 case 1:
7091 func (stream, "x");
7092 break;
7093
7094 case 2:
7095 func (stream, "a");
7096 break;
7097
7098 case 3:
7099 func (stream, "z");
7100 break;
7101
7102 case 5:
7103 func (stream, "m");
7104 break;
7105
7106 case 7:
7107 func (stream, "p");
7108
7109 case 4:
7110 case 6:
7111 default:
7112 break;
7113 }
7114 }
7115 break;
7116
7117 default:
7118 break;
7119 }
7120 }
7121
7122 static void
7123 print_mve_vcvt_size (struct disassemble_info *info,
7124 unsigned long given,
7125 enum mve_instructions matched_insn)
7126 {
7127 unsigned long mode = 0;
7128 void *stream = info->stream;
7129 fprintf_ftype func = info->fprintf_func;
7130
7131 switch (matched_insn)
7132 {
7133 case MVE_VCVT_FP_FIX_VEC:
7134 {
7135 mode = (((given & 0x200) >> 7)
7136 | ((given & 0x10000000) >> 27)
7137 | ((given & 0x100) >> 8));
7138
7139 switch (mode)
7140 {
7141 case 0:
7142 func (stream, "f16.s16");
7143 break;
7144
7145 case 1:
7146 func (stream, "s16.f16");
7147 break;
7148
7149 case 2:
7150 func (stream, "f16.u16");
7151 break;
7152
7153 case 3:
7154 func (stream, "u16.f16");
7155 break;
7156
7157 case 4:
7158 func (stream, "f32.s32");
7159 break;
7160
7161 case 5:
7162 func (stream, "s32.f32");
7163 break;
7164
7165 case 6:
7166 func (stream, "f32.u32");
7167 break;
7168
7169 case 7:
7170 func (stream, "u32.f32");
7171 break;
7172
7173 default:
7174 break;
7175 }
7176 break;
7177 }
7178 case MVE_VCVT_BETWEEN_FP_INT:
7179 {
7180 unsigned long size = arm_decode_field (given, 18, 19);
7181 unsigned long op = arm_decode_field (given, 7, 8);
7182
7183 if (size == 1)
7184 {
7185 switch (op)
7186 {
7187 case 0:
7188 func (stream, "f16.s16");
7189 break;
7190
7191 case 1:
7192 func (stream, "f16.u16");
7193 break;
7194
7195 case 2:
7196 func (stream, "s16.f16");
7197 break;
7198
7199 case 3:
7200 func (stream, "u16.f16");
7201 break;
7202
7203 default:
7204 break;
7205 }
7206 }
7207 else if (size == 2)
7208 {
7209 switch (op)
7210 {
7211 case 0:
7212 func (stream, "f32.s32");
7213 break;
7214
7215 case 1:
7216 func (stream, "f32.u32");
7217 break;
7218
7219 case 2:
7220 func (stream, "s32.f32");
7221 break;
7222
7223 case 3:
7224 func (stream, "u32.f32");
7225 break;
7226 }
7227 }
7228 }
7229 break;
7230
7231 case MVE_VCVT_FP_HALF_FP:
7232 {
7233 unsigned long op = arm_decode_field (given, 28, 28);
7234 if (op == 0)
7235 func (stream, "f16.f32");
7236 else if (op == 1)
7237 func (stream, "f32.f16");
7238 }
7239 break;
7240
7241 case MVE_VCVT_FROM_FP_TO_INT:
7242 {
7243 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7244
7245 switch (size)
7246 {
7247 case 2:
7248 func (stream, "s16.f16");
7249 break;
7250
7251 case 3:
7252 func (stream, "u16.f16");
7253 break;
7254
7255 case 4:
7256 func (stream, "s32.f32");
7257 break;
7258
7259 case 5:
7260 func (stream, "u32.f32");
7261 break;
7262
7263 default:
7264 break;
7265 }
7266 }
7267 break;
7268
7269 default:
7270 break;
7271 }
7272 }
7273
7274 static void
7275 print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7276 unsigned long rot_width)
7277 {
7278 void *stream = info->stream;
7279 fprintf_ftype func = info->fprintf_func;
7280
7281 if (rot_width == 1)
7282 {
7283 switch (rot)
7284 {
7285 case 0:
7286 func (stream, "90");
7287 break;
7288 case 1:
7289 func (stream, "270");
7290 break;
7291 default:
7292 break;
7293 }
7294 }
7295 else if (rot_width == 2)
7296 {
7297 switch (rot)
7298 {
7299 case 0:
7300 func (stream, "0");
7301 break;
7302 case 1:
7303 func (stream, "90");
7304 break;
7305 case 2:
7306 func (stream, "180");
7307 break;
7308 case 3:
7309 func (stream, "270");
7310 break;
7311 default:
7312 break;
7313 }
7314 }
7315 }
7316
7317 static void
7318 print_instruction_predicate (struct disassemble_info *info)
7319 {
7320 void *stream = info->stream;
7321 fprintf_ftype func = info->fprintf_func;
7322
7323 if (vpt_block_state.next_pred_state == PRED_THEN)
7324 func (stream, "t");
7325 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7326 func (stream, "e");
7327 }
7328
7329 static void
7330 print_mve_size (struct disassemble_info *info,
7331 unsigned long size,
7332 enum mve_instructions matched_insn)
7333 {
7334 void *stream = info->stream;
7335 fprintf_ftype func = info->fprintf_func;
7336
7337 switch (matched_insn)
7338 {
7339 case MVE_VABAV:
7340 case MVE_VABD_VEC:
7341 case MVE_VABS_FP:
7342 case MVE_VABS_VEC:
7343 case MVE_VADD_VEC_T1:
7344 case MVE_VADD_VEC_T2:
7345 case MVE_VADDV:
7346 case MVE_VBRSR:
7347 case MVE_VCADD_VEC:
7348 case MVE_VCLS:
7349 case MVE_VCLZ:
7350 case MVE_VCMP_VEC_T1:
7351 case MVE_VCMP_VEC_T2:
7352 case MVE_VCMP_VEC_T3:
7353 case MVE_VCMP_VEC_T4:
7354 case MVE_VCMP_VEC_T5:
7355 case MVE_VCMP_VEC_T6:
7356 case MVE_VCTP:
7357 case MVE_VDDUP:
7358 case MVE_VDWDUP:
7359 case MVE_VHADD_T1:
7360 case MVE_VHADD_T2:
7361 case MVE_VHCADD:
7362 case MVE_VHSUB_T1:
7363 case MVE_VHSUB_T2:
7364 case MVE_VIDUP:
7365 case MVE_VIWDUP:
7366 case MVE_VLD2:
7367 case MVE_VLD4:
7368 case MVE_VLDRB_GATHER_T1:
7369 case MVE_VLDRH_GATHER_T2:
7370 case MVE_VLDRW_GATHER_T3:
7371 case MVE_VLDRD_GATHER_T4:
7372 case MVE_VLDRB_T1:
7373 case MVE_VLDRH_T2:
7374 case MVE_VMAX:
7375 case MVE_VMAXA:
7376 case MVE_VMAXV:
7377 case MVE_VMAXAV:
7378 case MVE_VMIN:
7379 case MVE_VMINA:
7380 case MVE_VMINV:
7381 case MVE_VMINAV:
7382 case MVE_VMLA:
7383 case MVE_VMLAS:
7384 case MVE_VMUL_VEC_T1:
7385 case MVE_VMUL_VEC_T2:
7386 case MVE_VMULH:
7387 case MVE_VRMULH:
7388 case MVE_VMULL_INT:
7389 case MVE_VNEG_FP:
7390 case MVE_VNEG_VEC:
7391 case MVE_VPT_VEC_T1:
7392 case MVE_VPT_VEC_T2:
7393 case MVE_VPT_VEC_T3:
7394 case MVE_VPT_VEC_T4:
7395 case MVE_VPT_VEC_T5:
7396 case MVE_VPT_VEC_T6:
7397 case MVE_VQABS:
7398 case MVE_VQADD_T1:
7399 case MVE_VQADD_T2:
7400 case MVE_VQDMLADH:
7401 case MVE_VQRDMLADH:
7402 case MVE_VQDMLAH:
7403 case MVE_VQRDMLAH:
7404 case MVE_VQDMLASH:
7405 case MVE_VQRDMLASH:
7406 case MVE_VQDMLSDH:
7407 case MVE_VQRDMLSDH:
7408 case MVE_VQDMULH_T1:
7409 case MVE_VQRDMULH_T2:
7410 case MVE_VQDMULH_T3:
7411 case MVE_VQRDMULH_T4:
7412 case MVE_VQNEG:
7413 case MVE_VQRSHL_T1:
7414 case MVE_VQRSHL_T2:
7415 case MVE_VQSHL_T1:
7416 case MVE_VQSHL_T4:
7417 case MVE_VQSUB_T1:
7418 case MVE_VQSUB_T2:
7419 case MVE_VREV32:
7420 case MVE_VREV64:
7421 case MVE_VRHADD:
7422 case MVE_VRINT_FP:
7423 case MVE_VRSHL_T1:
7424 case MVE_VRSHL_T2:
7425 case MVE_VSHL_T2:
7426 case MVE_VSHL_T3:
7427 case MVE_VSHLL_T2:
7428 case MVE_VST2:
7429 case MVE_VST4:
7430 case MVE_VSTRB_SCATTER_T1:
7431 case MVE_VSTRH_SCATTER_T2:
7432 case MVE_VSTRW_SCATTER_T3:
7433 case MVE_VSTRB_T1:
7434 case MVE_VSTRH_T2:
7435 case MVE_VSUB_VEC_T1:
7436 case MVE_VSUB_VEC_T2:
7437 if (size <= 3)
7438 func (stream, "%s", mve_vec_sizename[size]);
7439 else
7440 func (stream, "<undef size>");
7441 break;
7442
7443 case MVE_VABD_FP:
7444 case MVE_VADD_FP_T1:
7445 case MVE_VADD_FP_T2:
7446 case MVE_VSUB_FP_T1:
7447 case MVE_VSUB_FP_T2:
7448 case MVE_VCMP_FP_T1:
7449 case MVE_VCMP_FP_T2:
7450 case MVE_VFMA_FP_SCALAR:
7451 case MVE_VFMA_FP:
7452 case MVE_VFMS_FP:
7453 case MVE_VFMAS_FP_SCALAR:
7454 case MVE_VMAXNM_FP:
7455 case MVE_VMAXNMA_FP:
7456 case MVE_VMAXNMV_FP:
7457 case MVE_VMAXNMAV_FP:
7458 case MVE_VMINNM_FP:
7459 case MVE_VMINNMA_FP:
7460 case MVE_VMINNMV_FP:
7461 case MVE_VMINNMAV_FP:
7462 case MVE_VMUL_FP_T1:
7463 case MVE_VMUL_FP_T2:
7464 case MVE_VPT_FP_T1:
7465 case MVE_VPT_FP_T2:
7466 if (size == 0)
7467 func (stream, "32");
7468 else if (size == 1)
7469 func (stream, "16");
7470 break;
7471
7472 case MVE_VCADD_FP:
7473 case MVE_VCMLA_FP:
7474 case MVE_VCMUL_FP:
7475 case MVE_VMLADAV_T1:
7476 case MVE_VMLALDAV:
7477 case MVE_VMLSDAV_T1:
7478 case MVE_VMLSLDAV:
7479 case MVE_VMOVN:
7480 case MVE_VQDMULL_T1:
7481 case MVE_VQDMULL_T2:
7482 case MVE_VQMOVN:
7483 case MVE_VQMOVUN:
7484 if (size == 0)
7485 func (stream, "16");
7486 else if (size == 1)
7487 func (stream, "32");
7488 break;
7489
7490 case MVE_VMOVL:
7491 if (size == 1)
7492 func (stream, "8");
7493 else if (size == 2)
7494 func (stream, "16");
7495 break;
7496
7497 case MVE_VDUP:
7498 switch (size)
7499 {
7500 case 0:
7501 func (stream, "32");
7502 break;
7503 case 1:
7504 func (stream, "16");
7505 break;
7506 case 2:
7507 func (stream, "8");
7508 break;
7509 default:
7510 break;
7511 }
7512 break;
7513
7514 case MVE_VMOV_GP_TO_VEC_LANE:
7515 case MVE_VMOV_VEC_LANE_TO_GP:
7516 switch (size)
7517 {
7518 case 0: case 4:
7519 func (stream, "32");
7520 break;
7521
7522 case 1: case 3:
7523 case 5: case 7:
7524 func (stream, "16");
7525 break;
7526
7527 case 8: case 9: case 10: case 11:
7528 case 12: case 13: case 14: case 15:
7529 func (stream, "8");
7530 break;
7531
7532 default:
7533 break;
7534 }
7535 break;
7536
7537 case MVE_VMOV_IMM_TO_VEC:
7538 switch (size)
7539 {
7540 case 0: case 4: case 8:
7541 case 12: case 24: case 26:
7542 func (stream, "i32");
7543 break;
7544 case 16: case 20:
7545 func (stream, "i16");
7546 break;
7547 case 28:
7548 func (stream, "i8");
7549 break;
7550 case 29:
7551 func (stream, "i64");
7552 break;
7553 case 30:
7554 func (stream, "f32");
7555 break;
7556 default:
7557 break;
7558 }
7559 break;
7560
7561 case MVE_VMULL_POLY:
7562 if (size == 0)
7563 func (stream, "p8");
7564 else if (size == 1)
7565 func (stream, "p16");
7566 break;
7567
7568 case MVE_VMVN_IMM:
7569 switch (size)
7570 {
7571 case 0: case 2: case 4:
7572 case 6: case 12: case 13:
7573 func (stream, "32");
7574 break;
7575
7576 case 8: case 10:
7577 func (stream, "16");
7578 break;
7579
7580 default:
7581 break;
7582 }
7583 break;
7584
7585 case MVE_VBIC_IMM:
7586 case MVE_VORR_IMM:
7587 switch (size)
7588 {
7589 case 1: case 3:
7590 case 5: case 7:
7591 func (stream, "32");
7592 break;
7593
7594 case 9: case 11:
7595 func (stream, "16");
7596 break;
7597
7598 default:
7599 break;
7600 }
7601 break;
7602
7603 case MVE_VQSHRN:
7604 case MVE_VQSHRUN:
7605 case MVE_VQRSHRN:
7606 case MVE_VQRSHRUN:
7607 case MVE_VRSHRN:
7608 case MVE_VSHRN:
7609 {
7610 switch (size)
7611 {
7612 case 1:
7613 func (stream, "16");
7614 break;
7615
7616 case 2: case 3:
7617 func (stream, "32");
7618 break;
7619
7620 default:
7621 break;
7622 }
7623 }
7624 break;
7625
7626 case MVE_VQSHL_T2:
7627 case MVE_VQSHLU_T3:
7628 case MVE_VRSHR:
7629 case MVE_VSHL_T1:
7630 case MVE_VSHLL_T1:
7631 case MVE_VSHR:
7632 case MVE_VSLI:
7633 case MVE_VSRI:
7634 {
7635 switch (size)
7636 {
7637 case 1:
7638 func (stream, "8");
7639 break;
7640
7641 case 2: case 3:
7642 func (stream, "16");
7643 break;
7644
7645 case 4: case 5: case 6: case 7:
7646 func (stream, "32");
7647 break;
7648
7649 default:
7650 break;
7651 }
7652 }
7653 break;
7654
7655 default:
7656 break;
7657 }
7658 }
7659
7660 static void
7661 print_mve_shift_n (struct disassemble_info *info, long given,
7662 enum mve_instructions matched_insn)
7663 {
7664 void *stream = info->stream;
7665 fprintf_ftype func = info->fprintf_func;
7666
7667 int startAt0
7668 = matched_insn == MVE_VQSHL_T2
7669 || matched_insn == MVE_VQSHLU_T3
7670 || matched_insn == MVE_VSHL_T1
7671 || matched_insn == MVE_VSHLL_T1
7672 || matched_insn == MVE_VSLI;
7673
7674 unsigned imm6 = (given & 0x3f0000) >> 16;
7675
7676 if (matched_insn == MVE_VSHLL_T1)
7677 imm6 &= 0x1f;
7678
7679 unsigned shiftAmount = 0;
7680 if ((imm6 & 0x20) != 0)
7681 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7682 else if ((imm6 & 0x10) != 0)
7683 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7684 else if ((imm6 & 0x08) != 0)
7685 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7686 else
7687 print_mve_undefined (info, UNDEF_SIZE_0);
7688
7689 func (stream, "%u", shiftAmount);
7690 }
7691
7692 static void
7693 print_vec_condition (struct disassemble_info *info, long given,
7694 enum mve_instructions matched_insn)
7695 {
7696 void *stream = info->stream;
7697 fprintf_ftype func = info->fprintf_func;
7698 long vec_cond = 0;
7699
7700 switch (matched_insn)
7701 {
7702 case MVE_VPT_FP_T1:
7703 case MVE_VCMP_FP_T1:
7704 vec_cond = (((given & 0x1000) >> 10)
7705 | ((given & 1) << 1)
7706 | ((given & 0x0080) >> 7));
7707 func (stream, "%s",vec_condnames[vec_cond]);
7708 break;
7709
7710 case MVE_VPT_FP_T2:
7711 case MVE_VCMP_FP_T2:
7712 vec_cond = (((given & 0x1000) >> 10)
7713 | ((given & 0x0020) >> 4)
7714 | ((given & 0x0080) >> 7));
7715 func (stream, "%s",vec_condnames[vec_cond]);
7716 break;
7717
7718 case MVE_VPT_VEC_T1:
7719 case MVE_VCMP_VEC_T1:
7720 vec_cond = (given & 0x0080) >> 7;
7721 func (stream, "%s",vec_condnames[vec_cond]);
7722 break;
7723
7724 case MVE_VPT_VEC_T2:
7725 case MVE_VCMP_VEC_T2:
7726 vec_cond = 2 | ((given & 0x0080) >> 7);
7727 func (stream, "%s",vec_condnames[vec_cond]);
7728 break;
7729
7730 case MVE_VPT_VEC_T3:
7731 case MVE_VCMP_VEC_T3:
7732 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7733 func (stream, "%s",vec_condnames[vec_cond]);
7734 break;
7735
7736 case MVE_VPT_VEC_T4:
7737 case MVE_VCMP_VEC_T4:
7738 vec_cond = (given & 0x0080) >> 7;
7739 func (stream, "%s",vec_condnames[vec_cond]);
7740 break;
7741
7742 case MVE_VPT_VEC_T5:
7743 case MVE_VCMP_VEC_T5:
7744 vec_cond = 2 | ((given & 0x0080) >> 7);
7745 func (stream, "%s",vec_condnames[vec_cond]);
7746 break;
7747
7748 case MVE_VPT_VEC_T6:
7749 case MVE_VCMP_VEC_T6:
7750 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7751 func (stream, "%s",vec_condnames[vec_cond]);
7752 break;
7753
7754 case MVE_NONE:
7755 case MVE_VPST:
7756 default:
7757 break;
7758 }
7759 }
7760
7761 #define W_BIT 21
7762 #define I_BIT 22
7763 #define U_BIT 23
7764 #define P_BIT 24
7765
7766 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7767 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7768 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7769 #define PRE_BIT_SET (given & (1 << P_BIT))
7770
7771
7772 /* Print one coprocessor instruction on INFO->STREAM.
7773 Return TRUE if the instuction matched, FALSE if this is not a
7774 recognised coprocessor instruction. */
7775
7776 static bfd_boolean
7777 print_insn_coprocessor (bfd_vma pc,
7778 struct disassemble_info *info,
7779 long given,
7780 bfd_boolean thumb)
7781 {
7782 const struct sopcode32 *insn;
7783 void *stream = info->stream;
7784 fprintf_ftype func = info->fprintf_func;
7785 unsigned long mask;
7786 unsigned long value = 0;
7787 int cond;
7788 int cp_num;
7789 struct arm_private_data *private_data = info->private_data;
7790 arm_feature_set allowed_arches = ARM_ARCH_NONE;
7791 arm_feature_set arm_ext_v8_1m_main =
7792 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
7793
7794 allowed_arches = private_data->features;
7795
7796 for (insn = coprocessor_opcodes; insn->assembler; insn++)
7797 {
7798 unsigned long u_reg = 16;
7799 bfd_boolean is_unpredictable = FALSE;
7800 signed long value_in_comment = 0;
7801 const char *c;
7802
7803 if (ARM_FEATURE_ZERO (insn->arch))
7804 switch (insn->value)
7805 {
7806 case SENTINEL_IWMMXT_START:
7807 if (info->mach != bfd_mach_arm_XScale
7808 && info->mach != bfd_mach_arm_iWMMXt
7809 && info->mach != bfd_mach_arm_iWMMXt2)
7810 do
7811 insn++;
7812 while ((! ARM_FEATURE_ZERO (insn->arch))
7813 && insn->value != SENTINEL_IWMMXT_END);
7814 continue;
7815
7816 case SENTINEL_IWMMXT_END:
7817 continue;
7818
7819 case SENTINEL_GENERIC_START:
7820 allowed_arches = private_data->features;
7821 continue;
7822
7823 default:
7824 abort ();
7825 }
7826
7827 mask = insn->mask;
7828 value = insn->value;
7829 cp_num = (given >> 8) & 0xf;
7830
7831 if (thumb)
7832 {
7833 /* The high 4 bits are 0xe for Arm conditional instructions, and
7834 0xe for arm unconditional instructions. The rest of the
7835 encoding is the same. */
7836 mask |= 0xf0000000;
7837 value |= 0xe0000000;
7838 if (ifthen_state)
7839 cond = IFTHEN_COND;
7840 else
7841 cond = COND_UNCOND;
7842 }
7843 else
7844 {
7845 /* Only match unconditional instuctions against unconditional
7846 patterns. */
7847 if ((given & 0xf0000000) == 0xf0000000)
7848 {
7849 mask |= 0xf0000000;
7850 cond = COND_UNCOND;
7851 }
7852 else
7853 {
7854 cond = (given >> 28) & 0xf;
7855 if (cond == 0xe)
7856 cond = COND_UNCOND;
7857 }
7858 }
7859
7860 if ((insn->isa == T32 && !thumb)
7861 || (insn->isa == ARM && thumb))
7862 continue;
7863
7864 if ((given & mask) != value)
7865 continue;
7866
7867 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
7868 continue;
7869
7870 if (insn->value == 0xfe000010 /* mcr2 */
7871 || insn->value == 0xfe100010 /* mrc2 */
7872 || insn->value == 0xfc100000 /* ldc2 */
7873 || insn->value == 0xfc000000) /* stc2 */
7874 {
7875 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7876 is_unpredictable = TRUE;
7877
7878 /* Armv8.1-M Mainline FP & MVE instructions. */
7879 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7880 && !ARM_CPU_IS_ANY (allowed_arches)
7881 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7882 continue;
7883
7884 }
7885 else if (insn->value == 0x0e000000 /* cdp */
7886 || insn->value == 0xfe000000 /* cdp2 */
7887 || insn->value == 0x0e000010 /* mcr */
7888 || insn->value == 0x0e100010 /* mrc */
7889 || insn->value == 0x0c100000 /* ldc */
7890 || insn->value == 0x0c000000) /* stc */
7891 {
7892 /* Floating-point instructions. */
7893 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7894 continue;
7895
7896 /* Armv8.1-M Mainline FP & MVE instructions. */
7897 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7898 && !ARM_CPU_IS_ANY (allowed_arches)
7899 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7900 continue;
7901 }
7902 else if ((insn->value == 0xec100f80 /* vldr (system register) */
7903 || insn->value == 0xec000f80) /* vstr (system register) */
7904 && arm_decode_field (given, 24, 24) == 0
7905 && arm_decode_field (given, 21, 21) == 0)
7906 /* If the P and W bits are both 0 then these encodings match the MVE
7907 VLDR and VSTR instructions, these are in a different table, so we
7908 don't let it match here. */
7909 continue;
7910
7911 for (c = insn->assembler; *c; c++)
7912 {
7913 if (*c == '%')
7914 {
7915 const char mod = *++c;
7916 switch (mod)
7917 {
7918 case '%':
7919 func (stream, "%%");
7920 break;
7921
7922 case 'A':
7923 case 'K':
7924 {
7925 int rn = (given >> 16) & 0xf;
7926 bfd_vma offset = given & 0xff;
7927
7928 if (mod == 'K')
7929 offset = given & 0x7f;
7930
7931 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
7932
7933 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
7934 {
7935 /* Not unindexed. The offset is scaled. */
7936 if (cp_num == 9)
7937 /* vldr.16/vstr.16 will shift the address
7938 left by 1 bit only. */
7939 offset = offset * 2;
7940 else
7941 offset = offset * 4;
7942
7943 if (NEGATIVE_BIT_SET)
7944 offset = - offset;
7945 if (rn != 15)
7946 value_in_comment = offset;
7947 }
7948
7949 if (PRE_BIT_SET)
7950 {
7951 if (offset)
7952 func (stream, ", #%d]%s",
7953 (int) offset,
7954 WRITEBACK_BIT_SET ? "!" : "");
7955 else if (NEGATIVE_BIT_SET)
7956 func (stream, ", #-0]");
7957 else
7958 func (stream, "]");
7959 }
7960 else
7961 {
7962 func (stream, "]");
7963
7964 if (WRITEBACK_BIT_SET)
7965 {
7966 if (offset)
7967 func (stream, ", #%d", (int) offset);
7968 else if (NEGATIVE_BIT_SET)
7969 func (stream, ", #-0");
7970 }
7971 else
7972 {
7973 func (stream, ", {%s%d}",
7974 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
7975 (int) offset);
7976 value_in_comment = offset;
7977 }
7978 }
7979 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
7980 {
7981 func (stream, "\t; ");
7982 /* For unaligned PCs, apply off-by-alignment
7983 correction. */
7984 info->print_address_func (offset + pc
7985 + info->bytes_per_chunk * 2
7986 - (pc & 3),
7987 info);
7988 }
7989 }
7990 break;
7991
7992 case 'B':
7993 {
7994 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
7995 int offset = (given >> 1) & 0x3f;
7996
7997 if (offset == 1)
7998 func (stream, "{d%d}", regno);
7999 else if (regno + offset > 32)
8000 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8001 else
8002 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8003 }
8004 break;
8005
8006 case 'C':
8007 {
8008 bfd_boolean single = ((given >> 8) & 1) == 0;
8009 char reg_prefix = single ? 's' : 'd';
8010 int Dreg = (given >> 22) & 0x1;
8011 int Vdreg = (given >> 12) & 0xf;
8012 int reg = single ? ((Vdreg << 1) | Dreg)
8013 : ((Dreg << 4) | Vdreg);
8014 int num = (given >> (single ? 0 : 1)) & 0x7f;
8015 int maxreg = single ? 31 : 15;
8016 int topreg = reg + num - 1;
8017
8018 if (!num)
8019 func (stream, "{VPR}");
8020 else if (num == 1)
8021 func (stream, "{%c%d, VPR}", reg_prefix, reg);
8022 else if (topreg > maxreg)
8023 func (stream, "{%c%d-<overflow reg d%d, VPR}",
8024 reg_prefix, reg, single ? topreg >> 1 : topreg);
8025 else
8026 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8027 reg_prefix, topreg);
8028 }
8029 break;
8030
8031 case 'u':
8032 if (cond != COND_UNCOND)
8033 is_unpredictable = TRUE;
8034
8035 /* Fall through. */
8036 case 'c':
8037 if (cond != COND_UNCOND && cp_num == 9)
8038 is_unpredictable = TRUE;
8039
8040 func (stream, "%s", arm_conditional[cond]);
8041 break;
8042
8043 case 'I':
8044 /* Print a Cirrus/DSP shift immediate. */
8045 /* Immediates are 7bit signed ints with bits 0..3 in
8046 bits 0..3 of opcode and bits 4..6 in bits 5..7
8047 of opcode. */
8048 {
8049 int imm;
8050
8051 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8052
8053 /* Is ``imm'' a negative number? */
8054 if (imm & 0x40)
8055 imm -= 0x80;
8056
8057 func (stream, "%d", imm);
8058 }
8059
8060 break;
8061
8062 case 'J':
8063 {
8064 unsigned long regno
8065 = arm_decode_field_multiple (given, 13, 15, 22, 22);
8066
8067 switch (regno)
8068 {
8069 case 0x1:
8070 func (stream, "FPSCR");
8071 break;
8072 case 0x2:
8073 func (stream, "FPSCR_nzcvqc");
8074 break;
8075 case 0xc:
8076 func (stream, "VPR");
8077 break;
8078 case 0xd:
8079 func (stream, "P0");
8080 break;
8081 case 0xe:
8082 func (stream, "FPCXTNS");
8083 break;
8084 case 0xf:
8085 func (stream, "FPCXTS");
8086 break;
8087 default:
8088 func (stream, "<invalid reg %lu>", regno);
8089 break;
8090 }
8091 }
8092 break;
8093
8094 case 'F':
8095 switch (given & 0x00408000)
8096 {
8097 case 0:
8098 func (stream, "4");
8099 break;
8100 case 0x8000:
8101 func (stream, "1");
8102 break;
8103 case 0x00400000:
8104 func (stream, "2");
8105 break;
8106 default:
8107 func (stream, "3");
8108 }
8109 break;
8110
8111 case 'P':
8112 switch (given & 0x00080080)
8113 {
8114 case 0:
8115 func (stream, "s");
8116 break;
8117 case 0x80:
8118 func (stream, "d");
8119 break;
8120 case 0x00080000:
8121 func (stream, "e");
8122 break;
8123 default:
8124 func (stream, _("<illegal precision>"));
8125 break;
8126 }
8127 break;
8128
8129 case 'Q':
8130 switch (given & 0x00408000)
8131 {
8132 case 0:
8133 func (stream, "s");
8134 break;
8135 case 0x8000:
8136 func (stream, "d");
8137 break;
8138 case 0x00400000:
8139 func (stream, "e");
8140 break;
8141 default:
8142 func (stream, "p");
8143 break;
8144 }
8145 break;
8146
8147 case 'R':
8148 switch (given & 0x60)
8149 {
8150 case 0:
8151 break;
8152 case 0x20:
8153 func (stream, "p");
8154 break;
8155 case 0x40:
8156 func (stream, "m");
8157 break;
8158 default:
8159 func (stream, "z");
8160 break;
8161 }
8162 break;
8163
8164 case '0': case '1': case '2': case '3': case '4':
8165 case '5': case '6': case '7': case '8': case '9':
8166 {
8167 int width;
8168
8169 c = arm_decode_bitfield (c, given, &value, &width);
8170
8171 switch (*c)
8172 {
8173 case 'R':
8174 if (value == 15)
8175 is_unpredictable = TRUE;
8176 /* Fall through. */
8177 case 'r':
8178 if (c[1] == 'u')
8179 {
8180 /* Eat the 'u' character. */
8181 ++ c;
8182
8183 if (u_reg == value)
8184 is_unpredictable = TRUE;
8185 u_reg = value;
8186 }
8187 func (stream, "%s", arm_regnames[value]);
8188 break;
8189 case 'V':
8190 if (given & (1 << 6))
8191 goto Q;
8192 /* FALLTHROUGH */
8193 case 'D':
8194 func (stream, "d%ld", value);
8195 break;
8196 case 'Q':
8197 Q:
8198 if (value & 1)
8199 func (stream, "<illegal reg q%ld.5>", value >> 1);
8200 else
8201 func (stream, "q%ld", value >> 1);
8202 break;
8203 case 'd':
8204 func (stream, "%ld", value);
8205 value_in_comment = value;
8206 break;
8207 case 'E':
8208 {
8209 /* Converts immediate 8 bit back to float value. */
8210 unsigned floatVal = (value & 0x80) << 24
8211 | (value & 0x3F) << 19
8212 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8213
8214 /* Quarter float have a maximum value of 31.0.
8215 Get floating point value multiplied by 1e7.
8216 The maximum value stays in limit of a 32-bit int. */
8217 unsigned decVal =
8218 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8219 (16 + (value & 0xF));
8220
8221 if (!(decVal % 1000000))
8222 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8223 floatVal, value & 0x80 ? '-' : ' ',
8224 decVal / 10000000,
8225 decVal % 10000000 / 1000000);
8226 else if (!(decVal % 10000))
8227 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8228 floatVal, value & 0x80 ? '-' : ' ',
8229 decVal / 10000000,
8230 decVal % 10000000 / 10000);
8231 else
8232 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8233 floatVal, value & 0x80 ? '-' : ' ',
8234 decVal / 10000000, decVal % 10000000);
8235 break;
8236 }
8237 case 'k':
8238 {
8239 int from = (given & (1 << 7)) ? 32 : 16;
8240 func (stream, "%ld", from - value);
8241 }
8242 break;
8243
8244 case 'f':
8245 if (value > 7)
8246 func (stream, "#%s", arm_fp_const[value & 7]);
8247 else
8248 func (stream, "f%ld", value);
8249 break;
8250
8251 case 'w':
8252 if (width == 2)
8253 func (stream, "%s", iwmmxt_wwnames[value]);
8254 else
8255 func (stream, "%s", iwmmxt_wwssnames[value]);
8256 break;
8257
8258 case 'g':
8259 func (stream, "%s", iwmmxt_regnames[value]);
8260 break;
8261 case 'G':
8262 func (stream, "%s", iwmmxt_cregnames[value]);
8263 break;
8264
8265 case 'x':
8266 func (stream, "0x%lx", (value & 0xffffffffUL));
8267 break;
8268
8269 case 'c':
8270 switch (value)
8271 {
8272 case 0:
8273 func (stream, "eq");
8274 break;
8275
8276 case 1:
8277 func (stream, "vs");
8278 break;
8279
8280 case 2:
8281 func (stream, "ge");
8282 break;
8283
8284 case 3:
8285 func (stream, "gt");
8286 break;
8287
8288 default:
8289 func (stream, "??");
8290 break;
8291 }
8292 break;
8293
8294 case '`':
8295 c++;
8296 if (value == 0)
8297 func (stream, "%c", *c);
8298 break;
8299 case '\'':
8300 c++;
8301 if (value == ((1ul << width) - 1))
8302 func (stream, "%c", *c);
8303 break;
8304 case '?':
8305 func (stream, "%c", c[(1 << width) - (int) value]);
8306 c += 1 << width;
8307 break;
8308 default:
8309 abort ();
8310 }
8311 }
8312 break;
8313
8314 case 'y':
8315 case 'z':
8316 {
8317 int single = *c++ == 'y';
8318 int regno;
8319
8320 switch (*c)
8321 {
8322 case '4': /* Sm pair */
8323 case '0': /* Sm, Dm */
8324 regno = given & 0x0000000f;
8325 if (single)
8326 {
8327 regno <<= 1;
8328 regno += (given >> 5) & 1;
8329 }
8330 else
8331 regno += ((given >> 5) & 1) << 4;
8332 break;
8333
8334 case '1': /* Sd, Dd */
8335 regno = (given >> 12) & 0x0000000f;
8336 if (single)
8337 {
8338 regno <<= 1;
8339 regno += (given >> 22) & 1;
8340 }
8341 else
8342 regno += ((given >> 22) & 1) << 4;
8343 break;
8344
8345 case '2': /* Sn, Dn */
8346 regno = (given >> 16) & 0x0000000f;
8347 if (single)
8348 {
8349 regno <<= 1;
8350 regno += (given >> 7) & 1;
8351 }
8352 else
8353 regno += ((given >> 7) & 1) << 4;
8354 break;
8355
8356 case '3': /* List */
8357 func (stream, "{");
8358 regno = (given >> 12) & 0x0000000f;
8359 if (single)
8360 {
8361 regno <<= 1;
8362 regno += (given >> 22) & 1;
8363 }
8364 else
8365 regno += ((given >> 22) & 1) << 4;
8366 break;
8367
8368 default:
8369 abort ();
8370 }
8371
8372 func (stream, "%c%d", single ? 's' : 'd', regno);
8373
8374 if (*c == '3')
8375 {
8376 int count = given & 0xff;
8377
8378 if (single == 0)
8379 count >>= 1;
8380
8381 if (--count)
8382 {
8383 func (stream, "-%c%d",
8384 single ? 's' : 'd',
8385 regno + count);
8386 }
8387
8388 func (stream, "}");
8389 }
8390 else if (*c == '4')
8391 func (stream, ", %c%d", single ? 's' : 'd',
8392 regno + 1);
8393 }
8394 break;
8395
8396 case 'L':
8397 switch (given & 0x00400100)
8398 {
8399 case 0x00000000: func (stream, "b"); break;
8400 case 0x00400000: func (stream, "h"); break;
8401 case 0x00000100: func (stream, "w"); break;
8402 case 0x00400100: func (stream, "d"); break;
8403 default:
8404 break;
8405 }
8406 break;
8407
8408 case 'Z':
8409 {
8410 /* given (20, 23) | given (0, 3) */
8411 value = ((given >> 16) & 0xf0) | (given & 0xf);
8412 func (stream, "%d", (int) value);
8413 }
8414 break;
8415
8416 case 'l':
8417 /* This is like the 'A' operator, except that if
8418 the width field "M" is zero, then the offset is
8419 *not* multiplied by four. */
8420 {
8421 int offset = given & 0xff;
8422 int multiplier = (given & 0x00000100) ? 4 : 1;
8423
8424 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8425
8426 if (multiplier > 1)
8427 {
8428 value_in_comment = offset * multiplier;
8429 if (NEGATIVE_BIT_SET)
8430 value_in_comment = - value_in_comment;
8431 }
8432
8433 if (offset)
8434 {
8435 if (PRE_BIT_SET)
8436 func (stream, ", #%s%d]%s",
8437 NEGATIVE_BIT_SET ? "-" : "",
8438 offset * multiplier,
8439 WRITEBACK_BIT_SET ? "!" : "");
8440 else
8441 func (stream, "], #%s%d",
8442 NEGATIVE_BIT_SET ? "-" : "",
8443 offset * multiplier);
8444 }
8445 else
8446 func (stream, "]");
8447 }
8448 break;
8449
8450 case 'r':
8451 {
8452 int imm4 = (given >> 4) & 0xf;
8453 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8454 int ubit = ! NEGATIVE_BIT_SET;
8455 const char *rm = arm_regnames [given & 0xf];
8456 const char *rn = arm_regnames [(given >> 16) & 0xf];
8457
8458 switch (puw_bits)
8459 {
8460 case 1:
8461 case 3:
8462 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8463 if (imm4)
8464 func (stream, ", lsl #%d", imm4);
8465 break;
8466
8467 case 4:
8468 case 5:
8469 case 6:
8470 case 7:
8471 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8472 if (imm4 > 0)
8473 func (stream, ", lsl #%d", imm4);
8474 func (stream, "]");
8475 if (puw_bits == 5 || puw_bits == 7)
8476 func (stream, "!");
8477 break;
8478
8479 default:
8480 func (stream, "INVALID");
8481 }
8482 }
8483 break;
8484
8485 case 'i':
8486 {
8487 long imm5;
8488 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8489 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8490 }
8491 break;
8492
8493 default:
8494 abort ();
8495 }
8496 }
8497 else
8498 func (stream, "%c", *c);
8499 }
8500
8501 if (value_in_comment > 32 || value_in_comment < -16)
8502 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
8503
8504 if (is_unpredictable)
8505 func (stream, UNPREDICTABLE_INSTRUCTION);
8506
8507 return TRUE;
8508 }
8509 return FALSE;
8510 }
8511
8512 /* Decodes and prints ARM addressing modes. Returns the offset
8513 used in the address, if any, if it is worthwhile printing the
8514 offset as a hexadecimal value in a comment at the end of the
8515 line of disassembly. */
8516
8517 static signed long
8518 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8519 {
8520 void *stream = info->stream;
8521 fprintf_ftype func = info->fprintf_func;
8522 bfd_vma offset = 0;
8523
8524 if (((given & 0x000f0000) == 0x000f0000)
8525 && ((given & 0x02000000) == 0))
8526 {
8527 offset = given & 0xfff;
8528
8529 func (stream, "[pc");
8530
8531 if (PRE_BIT_SET)
8532 {
8533 /* Pre-indexed. Elide offset of positive zero when
8534 non-writeback. */
8535 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8536 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8537
8538 if (NEGATIVE_BIT_SET)
8539 offset = -offset;
8540
8541 offset += pc + 8;
8542
8543 /* Cope with the possibility of write-back
8544 being used. Probably a very dangerous thing
8545 for the programmer to do, but who are we to
8546 argue ? */
8547 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
8548 }
8549 else /* Post indexed. */
8550 {
8551 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8552
8553 /* Ie ignore the offset. */
8554 offset = pc + 8;
8555 }
8556
8557 func (stream, "\t; ");
8558 info->print_address_func (offset, info);
8559 offset = 0;
8560 }
8561 else
8562 {
8563 func (stream, "[%s",
8564 arm_regnames[(given >> 16) & 0xf]);
8565
8566 if (PRE_BIT_SET)
8567 {
8568 if ((given & 0x02000000) == 0)
8569 {
8570 /* Elide offset of positive zero when non-writeback. */
8571 offset = given & 0xfff;
8572 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8573 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8574 }
8575 else
8576 {
8577 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
8578 arm_decode_shift (given, func, stream, TRUE);
8579 }
8580
8581 func (stream, "]%s",
8582 WRITEBACK_BIT_SET ? "!" : "");
8583 }
8584 else
8585 {
8586 if ((given & 0x02000000) == 0)
8587 {
8588 /* Always show offset. */
8589 offset = given & 0xfff;
8590 func (stream, "], #%s%d",
8591 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8592 }
8593 else
8594 {
8595 func (stream, "], %s",
8596 NEGATIVE_BIT_SET ? "-" : "");
8597 arm_decode_shift (given, func, stream, TRUE);
8598 }
8599 }
8600 if (NEGATIVE_BIT_SET)
8601 offset = -offset;
8602 }
8603
8604 return (signed long) offset;
8605 }
8606
8607 /* Print one neon instruction on INFO->STREAM.
8608 Return TRUE if the instuction matched, FALSE if this is not a
8609 recognised neon instruction. */
8610
8611 static bfd_boolean
8612 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8613 {
8614 const struct opcode32 *insn;
8615 void *stream = info->stream;
8616 fprintf_ftype func = info->fprintf_func;
8617
8618 if (thumb)
8619 {
8620 if ((given & 0xef000000) == 0xef000000)
8621 {
8622 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
8623 unsigned long bit28 = given & (1 << 28);
8624
8625 given &= 0x00ffffff;
8626 if (bit28)
8627 given |= 0xf3000000;
8628 else
8629 given |= 0xf2000000;
8630 }
8631 else if ((given & 0xff000000) == 0xf9000000)
8632 given ^= 0xf9000000 ^ 0xf4000000;
8633 /* vdup is also a valid neon instruction. */
8634 else if ((given & 0xff910f5f) != 0xee800b10)
8635 return FALSE;
8636 }
8637
8638 for (insn = neon_opcodes; insn->assembler; insn++)
8639 {
8640 if ((given & insn->mask) == insn->value)
8641 {
8642 signed long value_in_comment = 0;
8643 bfd_boolean is_unpredictable = FALSE;
8644 const char *c;
8645
8646 for (c = insn->assembler; *c; c++)
8647 {
8648 if (*c == '%')
8649 {
8650 switch (*++c)
8651 {
8652 case '%':
8653 func (stream, "%%");
8654 break;
8655
8656 case 'u':
8657 if (thumb && ifthen_state)
8658 is_unpredictable = TRUE;
8659
8660 /* Fall through. */
8661 case 'c':
8662 if (thumb && ifthen_state)
8663 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8664 break;
8665
8666 case 'A':
8667 {
8668 static const unsigned char enc[16] =
8669 {
8670 0x4, 0x14, /* st4 0,1 */
8671 0x4, /* st1 2 */
8672 0x4, /* st2 3 */
8673 0x3, /* st3 4 */
8674 0x13, /* st3 5 */
8675 0x3, /* st1 6 */
8676 0x1, /* st1 7 */
8677 0x2, /* st2 8 */
8678 0x12, /* st2 9 */
8679 0x2, /* st1 10 */
8680 0, 0, 0, 0, 0
8681 };
8682 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8683 int rn = ((given >> 16) & 0xf);
8684 int rm = ((given >> 0) & 0xf);
8685 int align = ((given >> 4) & 0x3);
8686 int type = ((given >> 8) & 0xf);
8687 int n = enc[type] & 0xf;
8688 int stride = (enc[type] >> 4) + 1;
8689 int ix;
8690
8691 func (stream, "{");
8692 if (stride > 1)
8693 for (ix = 0; ix != n; ix++)
8694 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
8695 else if (n == 1)
8696 func (stream, "d%d", rd);
8697 else
8698 func (stream, "d%d-d%d", rd, rd + n - 1);
8699 func (stream, "}, [%s", arm_regnames[rn]);
8700 if (align)
8701 func (stream, " :%d", 32 << align);
8702 func (stream, "]");
8703 if (rm == 0xd)
8704 func (stream, "!");
8705 else if (rm != 0xf)
8706 func (stream, ", %s", arm_regnames[rm]);
8707 }
8708 break;
8709
8710 case 'B':
8711 {
8712 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8713 int rn = ((given >> 16) & 0xf);
8714 int rm = ((given >> 0) & 0xf);
8715 int idx_align = ((given >> 4) & 0xf);
8716 int align = 0;
8717 int size = ((given >> 10) & 0x3);
8718 int idx = idx_align >> (size + 1);
8719 int length = ((given >> 8) & 3) + 1;
8720 int stride = 1;
8721 int i;
8722
8723 if (length > 1 && size > 0)
8724 stride = (idx_align & (1 << size)) ? 2 : 1;
8725
8726 switch (length)
8727 {
8728 case 1:
8729 {
8730 int amask = (1 << size) - 1;
8731 if ((idx_align & (1 << size)) != 0)
8732 return FALSE;
8733 if (size > 0)
8734 {
8735 if ((idx_align & amask) == amask)
8736 align = 8 << size;
8737 else if ((idx_align & amask) != 0)
8738 return FALSE;
8739 }
8740 }
8741 break;
8742
8743 case 2:
8744 if (size == 2 && (idx_align & 2) != 0)
8745 return FALSE;
8746 align = (idx_align & 1) ? 16 << size : 0;
8747 break;
8748
8749 case 3:
8750 if ((size == 2 && (idx_align & 3) != 0)
8751 || (idx_align & 1) != 0)
8752 return FALSE;
8753 break;
8754
8755 case 4:
8756 if (size == 2)
8757 {
8758 if ((idx_align & 3) == 3)
8759 return FALSE;
8760 align = (idx_align & 3) * 64;
8761 }
8762 else
8763 align = (idx_align & 1) ? 32 << size : 0;
8764 break;
8765
8766 default:
8767 abort ();
8768 }
8769
8770 func (stream, "{");
8771 for (i = 0; i < length; i++)
8772 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8773 rd + i * stride, idx);
8774 func (stream, "}, [%s", arm_regnames[rn]);
8775 if (align)
8776 func (stream, " :%d", align);
8777 func (stream, "]");
8778 if (rm == 0xd)
8779 func (stream, "!");
8780 else if (rm != 0xf)
8781 func (stream, ", %s", arm_regnames[rm]);
8782 }
8783 break;
8784
8785 case 'C':
8786 {
8787 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8788 int rn = ((given >> 16) & 0xf);
8789 int rm = ((given >> 0) & 0xf);
8790 int align = ((given >> 4) & 0x1);
8791 int size = ((given >> 6) & 0x3);
8792 int type = ((given >> 8) & 0x3);
8793 int n = type + 1;
8794 int stride = ((given >> 5) & 0x1);
8795 int ix;
8796
8797 if (stride && (n == 1))
8798 n++;
8799 else
8800 stride++;
8801
8802 func (stream, "{");
8803 if (stride > 1)
8804 for (ix = 0; ix != n; ix++)
8805 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8806 else if (n == 1)
8807 func (stream, "d%d[]", rd);
8808 else
8809 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8810 func (stream, "}, [%s", arm_regnames[rn]);
8811 if (align)
8812 {
8813 align = (8 * (type + 1)) << size;
8814 if (type == 3)
8815 align = (size > 1) ? align >> 1 : align;
8816 if (type == 2 || (type == 0 && !size))
8817 func (stream, " :<bad align %d>", align);
8818 else
8819 func (stream, " :%d", align);
8820 }
8821 func (stream, "]");
8822 if (rm == 0xd)
8823 func (stream, "!");
8824 else if (rm != 0xf)
8825 func (stream, ", %s", arm_regnames[rm]);
8826 }
8827 break;
8828
8829 case 'D':
8830 {
8831 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
8832 int size = (given >> 20) & 3;
8833 int reg = raw_reg & ((4 << size) - 1);
8834 int ix = raw_reg >> size >> 2;
8835
8836 func (stream, "d%d[%d]", reg, ix);
8837 }
8838 break;
8839
8840 case 'E':
8841 /* Neon encoded constant for mov, mvn, vorr, vbic. */
8842 {
8843 int bits = 0;
8844 int cmode = (given >> 8) & 0xf;
8845 int op = (given >> 5) & 0x1;
8846 unsigned long value = 0, hival = 0;
8847 unsigned shift;
8848 int size = 0;
8849 int isfloat = 0;
8850
8851 bits |= ((given >> 24) & 1) << 7;
8852 bits |= ((given >> 16) & 7) << 4;
8853 bits |= ((given >> 0) & 15) << 0;
8854
8855 if (cmode < 8)
8856 {
8857 shift = (cmode >> 1) & 3;
8858 value = (unsigned long) bits << (8 * shift);
8859 size = 32;
8860 }
8861 else if (cmode < 12)
8862 {
8863 shift = (cmode >> 1) & 1;
8864 value = (unsigned long) bits << (8 * shift);
8865 size = 16;
8866 }
8867 else if (cmode < 14)
8868 {
8869 shift = (cmode & 1) + 1;
8870 value = (unsigned long) bits << (8 * shift);
8871 value |= (1ul << (8 * shift)) - 1;
8872 size = 32;
8873 }
8874 else if (cmode == 14)
8875 {
8876 if (op)
8877 {
8878 /* Bit replication into bytes. */
8879 int ix;
8880 unsigned long mask;
8881
8882 value = 0;
8883 hival = 0;
8884 for (ix = 7; ix >= 0; ix--)
8885 {
8886 mask = ((bits >> ix) & 1) ? 0xff : 0;
8887 if (ix <= 3)
8888 value = (value << 8) | mask;
8889 else
8890 hival = (hival << 8) | mask;
8891 }
8892 size = 64;
8893 }
8894 else
8895 {
8896 /* Byte replication. */
8897 value = (unsigned long) bits;
8898 size = 8;
8899 }
8900 }
8901 else if (!op)
8902 {
8903 /* Floating point encoding. */
8904 int tmp;
8905
8906 value = (unsigned long) (bits & 0x7f) << 19;
8907 value |= (unsigned long) (bits & 0x80) << 24;
8908 tmp = bits & 0x40 ? 0x3c : 0x40;
8909 value |= (unsigned long) tmp << 24;
8910 size = 32;
8911 isfloat = 1;
8912 }
8913 else
8914 {
8915 func (stream, "<illegal constant %.8x:%x:%x>",
8916 bits, cmode, op);
8917 size = 32;
8918 break;
8919 }
8920 switch (size)
8921 {
8922 case 8:
8923 func (stream, "#%ld\t; 0x%.2lx", value, value);
8924 break;
8925
8926 case 16:
8927 func (stream, "#%ld\t; 0x%.4lx", value, value);
8928 break;
8929
8930 case 32:
8931 if (isfloat)
8932 {
8933 unsigned char valbytes[4];
8934 double fvalue;
8935
8936 /* Do this a byte at a time so we don't have to
8937 worry about the host's endianness. */
8938 valbytes[0] = value & 0xff;
8939 valbytes[1] = (value >> 8) & 0xff;
8940 valbytes[2] = (value >> 16) & 0xff;
8941 valbytes[3] = (value >> 24) & 0xff;
8942
8943 floatformat_to_double
8944 (& floatformat_ieee_single_little, valbytes,
8945 & fvalue);
8946
8947 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
8948 value);
8949 }
8950 else
8951 func (stream, "#%ld\t; 0x%.8lx",
8952 (long) (((value & 0x80000000L) != 0)
8953 ? value | ~0xffffffffL : value),
8954 value);
8955 break;
8956
8957 case 64:
8958 func (stream, "#0x%.8lx%.8lx", hival, value);
8959 break;
8960
8961 default:
8962 abort ();
8963 }
8964 }
8965 break;
8966
8967 case 'F':
8968 {
8969 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
8970 int num = (given >> 8) & 0x3;
8971
8972 if (!num)
8973 func (stream, "{d%d}", regno);
8974 else if (num + regno >= 32)
8975 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
8976 else
8977 func (stream, "{d%d-d%d}", regno, regno + num);
8978 }
8979 break;
8980
8981
8982 case '0': case '1': case '2': case '3': case '4':
8983 case '5': case '6': case '7': case '8': case '9':
8984 {
8985 int width;
8986 unsigned long value;
8987
8988 c = arm_decode_bitfield (c, given, &value, &width);
8989
8990 switch (*c)
8991 {
8992 case 'r':
8993 func (stream, "%s", arm_regnames[value]);
8994 break;
8995 case 'd':
8996 func (stream, "%ld", value);
8997 value_in_comment = value;
8998 break;
8999 case 'e':
9000 func (stream, "%ld", (1ul << width) - value);
9001 break;
9002
9003 case 'S':
9004 case 'T':
9005 case 'U':
9006 /* Various width encodings. */
9007 {
9008 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9009 int limit;
9010 unsigned low, high;
9011
9012 c++;
9013 if (*c >= '0' && *c <= '9')
9014 limit = *c - '0';
9015 else if (*c >= 'a' && *c <= 'f')
9016 limit = *c - 'a' + 10;
9017 else
9018 abort ();
9019 low = limit >> 2;
9020 high = limit & 3;
9021
9022 if (value < low || value > high)
9023 func (stream, "<illegal width %d>", base << value);
9024 else
9025 func (stream, "%d", base << value);
9026 }
9027 break;
9028 case 'R':
9029 if (given & (1 << 6))
9030 goto Q;
9031 /* FALLTHROUGH */
9032 case 'D':
9033 func (stream, "d%ld", value);
9034 break;
9035 case 'Q':
9036 Q:
9037 if (value & 1)
9038 func (stream, "<illegal reg q%ld.5>", value >> 1);
9039 else
9040 func (stream, "q%ld", value >> 1);
9041 break;
9042
9043 case '`':
9044 c++;
9045 if (value == 0)
9046 func (stream, "%c", *c);
9047 break;
9048 case '\'':
9049 c++;
9050 if (value == ((1ul << width) - 1))
9051 func (stream, "%c", *c);
9052 break;
9053 case '?':
9054 func (stream, "%c", c[(1 << width) - (int) value]);
9055 c += 1 << width;
9056 break;
9057 default:
9058 abort ();
9059 }
9060 }
9061 break;
9062
9063 default:
9064 abort ();
9065 }
9066 }
9067 else
9068 func (stream, "%c", *c);
9069 }
9070
9071 if (value_in_comment > 32 || value_in_comment < -16)
9072 func (stream, "\t; 0x%lx", value_in_comment);
9073
9074 if (is_unpredictable)
9075 func (stream, UNPREDICTABLE_INSTRUCTION);
9076
9077 return TRUE;
9078 }
9079 }
9080 return FALSE;
9081 }
9082
9083 /* Print one mve instruction on INFO->STREAM.
9084 Return TRUE if the instuction matched, FALSE if this is not a
9085 recognised mve instruction. */
9086
9087 static bfd_boolean
9088 print_insn_mve (struct disassemble_info *info, long given)
9089 {
9090 const struct mopcode32 *insn;
9091 void *stream = info->stream;
9092 fprintf_ftype func = info->fprintf_func;
9093
9094 for (insn = mve_opcodes; insn->assembler; insn++)
9095 {
9096 if (((given & insn->mask) == insn->value)
9097 && !is_mve_encoding_conflict (given, insn->mve_op))
9098 {
9099 signed long value_in_comment = 0;
9100 bfd_boolean is_unpredictable = FALSE;
9101 bfd_boolean is_undefined = FALSE;
9102 const char *c;
9103 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9104 enum mve_undefined undefined_cond = UNDEF_NONE;
9105
9106 /* Most vector mve instruction are illegal in a it block.
9107 There are a few exceptions; check for them. */
9108 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9109 {
9110 is_unpredictable = TRUE;
9111 unpredictable_cond = UNPRED_IT_BLOCK;
9112 }
9113 else if (is_mve_unpredictable (given, insn->mve_op,
9114 &unpredictable_cond))
9115 is_unpredictable = TRUE;
9116
9117 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9118 is_undefined = TRUE;
9119
9120 for (c = insn->assembler; *c; c++)
9121 {
9122 if (*c == '%')
9123 {
9124 switch (*++c)
9125 {
9126 case '%':
9127 func (stream, "%%");
9128 break;
9129
9130 case 'a':
9131 /* Don't print anything for '+' as it is implied. */
9132 if (arm_decode_field (given, 23, 23) == 0)
9133 func (stream, "-");
9134 break;
9135
9136 case 'c':
9137 if (ifthen_state)
9138 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9139 break;
9140
9141 case 'd':
9142 print_mve_vld_str_addr (info, given, insn->mve_op);
9143 break;
9144
9145 case 'i':
9146 {
9147 long mve_mask = mve_extract_pred_mask (given);
9148 func (stream, "%s", mve_predicatenames[mve_mask]);
9149 }
9150 break;
9151
9152 case 'j':
9153 {
9154 unsigned int imm5 = 0;
9155 imm5 |= arm_decode_field (given, 6, 7);
9156 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9157 func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9158 }
9159 break;
9160
9161 case 'n':
9162 print_vec_condition (info, given, insn->mve_op);
9163 break;
9164
9165 case 'o':
9166 if (arm_decode_field (given, 0, 0) == 1)
9167 {
9168 unsigned long size
9169 = arm_decode_field (given, 4, 4)
9170 | (arm_decode_field (given, 6, 6) << 1);
9171
9172 func (stream, ", uxtw #%lu", size);
9173 }
9174 break;
9175
9176 case 'm':
9177 print_mve_rounding_mode (info, given, insn->mve_op);
9178 break;
9179
9180 case 's':
9181 print_mve_vcvt_size (info, given, insn->mve_op);
9182 break;
9183
9184 case 'u':
9185 {
9186 unsigned long op1 = arm_decode_field (given, 21, 22);
9187
9188 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9189 {
9190 /* Check for signed. */
9191 if (arm_decode_field (given, 23, 23) == 0)
9192 {
9193 /* We don't print 's' for S32. */
9194 if ((arm_decode_field (given, 5, 6) == 0)
9195 && ((op1 == 0) || (op1 == 1)))
9196 ;
9197 else
9198 func (stream, "s");
9199 }
9200 else
9201 func (stream, "u");
9202 }
9203 else
9204 {
9205 if (arm_decode_field (given, 28, 28) == 0)
9206 func (stream, "s");
9207 else
9208 func (stream, "u");
9209 }
9210 }
9211 break;
9212
9213 case 'v':
9214 print_instruction_predicate (info);
9215 break;
9216
9217 case 'w':
9218 if (arm_decode_field (given, 21, 21) == 1)
9219 func (stream, "!");
9220 break;
9221
9222 case 'B':
9223 print_mve_register_blocks (info, given, insn->mve_op);
9224 break;
9225
9226 case 'E':
9227 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9228
9229 print_simd_imm8 (info, given, 28, insn);
9230 break;
9231
9232 case 'N':
9233 print_mve_vmov_index (info, given);
9234 break;
9235
9236 case 'T':
9237 if (arm_decode_field (given, 12, 12) == 0)
9238 func (stream, "b");
9239 else
9240 func (stream, "t");
9241 break;
9242
9243 case 'X':
9244 if (arm_decode_field (given, 12, 12) == 1)
9245 func (stream, "x");
9246 break;
9247
9248 case '0': case '1': case '2': case '3': case '4':
9249 case '5': case '6': case '7': case '8': case '9':
9250 {
9251 int width;
9252 unsigned long value;
9253
9254 c = arm_decode_bitfield (c, given, &value, &width);
9255
9256 switch (*c)
9257 {
9258 case 'Z':
9259 if (value == 13)
9260 is_unpredictable = TRUE;
9261 else if (value == 15)
9262 func (stream, "zr");
9263 else
9264 func (stream, "%s", arm_regnames[value]);
9265 break;
9266
9267 case 'S':
9268 if (value == 13 || value == 15)
9269 is_unpredictable = TRUE;
9270 else
9271 func (stream, "%s", arm_regnames[value]);
9272 break;
9273
9274 case 's':
9275 print_mve_size (info,
9276 value,
9277 insn->mve_op);
9278 break;
9279 case 'I':
9280 if (value == 1)
9281 func (stream, "i");
9282 break;
9283 case 'A':
9284 if (value == 1)
9285 func (stream, "a");
9286 break;
9287 case 'h':
9288 {
9289 unsigned int odd_reg = (value << 1) | 1;
9290 func (stream, "%s", arm_regnames[odd_reg]);
9291 }
9292 break;
9293 case 'i':
9294 {
9295 unsigned long imm
9296 = arm_decode_field (given, 0, 6);
9297 unsigned long mod_imm = imm;
9298
9299 switch (insn->mve_op)
9300 {
9301 case MVE_VLDRW_GATHER_T5:
9302 case MVE_VSTRW_SCATTER_T5:
9303 mod_imm = mod_imm << 2;
9304 break;
9305 case MVE_VSTRD_SCATTER_T6:
9306 case MVE_VLDRD_GATHER_T6:
9307 mod_imm = mod_imm << 3;
9308 break;
9309
9310 default:
9311 break;
9312 }
9313
9314 func (stream, "%lu", mod_imm);
9315 }
9316 break;
9317 case 'k':
9318 func (stream, "%lu", 64 - value);
9319 break;
9320 case 'l':
9321 {
9322 unsigned int even_reg = value << 1;
9323 func (stream, "%s", arm_regnames[even_reg]);
9324 }
9325 break;
9326 case 'u':
9327 switch (value)
9328 {
9329 case 0:
9330 func (stream, "1");
9331 break;
9332 case 1:
9333 func (stream, "2");
9334 break;
9335 case 2:
9336 func (stream, "4");
9337 break;
9338 case 3:
9339 func (stream, "8");
9340 break;
9341 default:
9342 break;
9343 }
9344 break;
9345 case 'o':
9346 print_mve_rotate (info, value, width);
9347 break;
9348 case 'r':
9349 func (stream, "%s", arm_regnames[value]);
9350 break;
9351 case 'd':
9352 if (insn->mve_op == MVE_VQSHL_T2
9353 || insn->mve_op == MVE_VQSHLU_T3
9354 || insn->mve_op == MVE_VRSHR
9355 || insn->mve_op == MVE_VRSHRN
9356 || insn->mve_op == MVE_VSHL_T1
9357 || insn->mve_op == MVE_VSHLL_T1
9358 || insn->mve_op == MVE_VSHR
9359 || insn->mve_op == MVE_VSHRN
9360 || insn->mve_op == MVE_VSLI
9361 || insn->mve_op == MVE_VSRI)
9362 print_mve_shift_n (info, given, insn->mve_op);
9363 else if (insn->mve_op == MVE_VSHLL_T2)
9364 {
9365 switch (value)
9366 {
9367 case 0x00:
9368 func (stream, "8");
9369 break;
9370 case 0x01:
9371 func (stream, "16");
9372 break;
9373 case 0x10:
9374 print_mve_undefined (info, UNDEF_SIZE_0);
9375 break;
9376 default:
9377 assert (0);
9378 break;
9379 }
9380 }
9381 else
9382 {
9383 if (insn->mve_op == MVE_VSHLC && value == 0)
9384 value = 32;
9385 func (stream, "%ld", value);
9386 value_in_comment = value;
9387 }
9388 break;
9389 case 'F':
9390 func (stream, "s%ld", value);
9391 break;
9392 case 'Q':
9393 if (value & 0x8)
9394 func (stream, "<illegal reg q%ld.5>", value);
9395 else
9396 func (stream, "q%ld", value);
9397 break;
9398 case 'x':
9399 func (stream, "0x%08lx", value);
9400 break;
9401 default:
9402 abort ();
9403 }
9404 break;
9405 default:
9406 abort ();
9407 }
9408 }
9409 }
9410 else
9411 func (stream, "%c", *c);
9412 }
9413
9414 if (value_in_comment > 32 || value_in_comment < -16)
9415 func (stream, "\t; 0x%lx", value_in_comment);
9416
9417 if (is_unpredictable)
9418 print_mve_unpredictable (info, unpredictable_cond);
9419
9420 if (is_undefined)
9421 print_mve_undefined (info, undefined_cond);
9422
9423 if ((vpt_block_state.in_vpt_block == FALSE)
9424 && !ifthen_state
9425 && (is_vpt_instruction (given) == TRUE))
9426 mark_inside_vpt_block (given);
9427 else if (vpt_block_state.in_vpt_block == TRUE)
9428 update_vpt_block_state ();
9429
9430 return TRUE;
9431 }
9432 }
9433 return FALSE;
9434 }
9435
9436
9437 /* Return the name of a v7A special register. */
9438
9439 static const char *
9440 banked_regname (unsigned reg)
9441 {
9442 switch (reg)
9443 {
9444 case 15: return "CPSR";
9445 case 32: return "R8_usr";
9446 case 33: return "R9_usr";
9447 case 34: return "R10_usr";
9448 case 35: return "R11_usr";
9449 case 36: return "R12_usr";
9450 case 37: return "SP_usr";
9451 case 38: return "LR_usr";
9452 case 40: return "R8_fiq";
9453 case 41: return "R9_fiq";
9454 case 42: return "R10_fiq";
9455 case 43: return "R11_fiq";
9456 case 44: return "R12_fiq";
9457 case 45: return "SP_fiq";
9458 case 46: return "LR_fiq";
9459 case 48: return "LR_irq";
9460 case 49: return "SP_irq";
9461 case 50: return "LR_svc";
9462 case 51: return "SP_svc";
9463 case 52: return "LR_abt";
9464 case 53: return "SP_abt";
9465 case 54: return "LR_und";
9466 case 55: return "SP_und";
9467 case 60: return "LR_mon";
9468 case 61: return "SP_mon";
9469 case 62: return "ELR_hyp";
9470 case 63: return "SP_hyp";
9471 case 79: return "SPSR";
9472 case 110: return "SPSR_fiq";
9473 case 112: return "SPSR_irq";
9474 case 114: return "SPSR_svc";
9475 case 116: return "SPSR_abt";
9476 case 118: return "SPSR_und";
9477 case 124: return "SPSR_mon";
9478 case 126: return "SPSR_hyp";
9479 default: return NULL;
9480 }
9481 }
9482
9483 /* Return the name of the DMB/DSB option. */
9484 static const char *
9485 data_barrier_option (unsigned option)
9486 {
9487 switch (option & 0xf)
9488 {
9489 case 0xf: return "sy";
9490 case 0xe: return "st";
9491 case 0xd: return "ld";
9492 case 0xb: return "ish";
9493 case 0xa: return "ishst";
9494 case 0x9: return "ishld";
9495 case 0x7: return "un";
9496 case 0x6: return "unst";
9497 case 0x5: return "nshld";
9498 case 0x3: return "osh";
9499 case 0x2: return "oshst";
9500 case 0x1: return "oshld";
9501 default: return NULL;
9502 }
9503 }
9504
9505 /* Print one ARM instruction from PC on INFO->STREAM. */
9506
9507 static void
9508 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
9509 {
9510 const struct opcode32 *insn;
9511 void *stream = info->stream;
9512 fprintf_ftype func = info->fprintf_func;
9513 struct arm_private_data *private_data = info->private_data;
9514
9515 if (print_insn_coprocessor (pc, info, given, FALSE))
9516 return;
9517
9518 if (print_insn_neon (info, given, FALSE))
9519 return;
9520
9521 for (insn = arm_opcodes; insn->assembler; insn++)
9522 {
9523 if ((given & insn->mask) != insn->value)
9524 continue;
9525
9526 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
9527 continue;
9528
9529 /* Special case: an instruction with all bits set in the condition field
9530 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9531 or by the catchall at the end of the table. */
9532 if ((given & 0xF0000000) != 0xF0000000
9533 || (insn->mask & 0xF0000000) == 0xF0000000
9534 || (insn->mask == 0 && insn->value == 0))
9535 {
9536 unsigned long u_reg = 16;
9537 unsigned long U_reg = 16;
9538 bfd_boolean is_unpredictable = FALSE;
9539 signed long value_in_comment = 0;
9540 const char *c;
9541
9542 for (c = insn->assembler; *c; c++)
9543 {
9544 if (*c == '%')
9545 {
9546 bfd_boolean allow_unpredictable = FALSE;
9547
9548 switch (*++c)
9549 {
9550 case '%':
9551 func (stream, "%%");
9552 break;
9553
9554 case 'a':
9555 value_in_comment = print_arm_address (pc, info, given);
9556 break;
9557
9558 case 'P':
9559 /* Set P address bit and use normal address
9560 printing routine. */
9561 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
9562 break;
9563
9564 case 'S':
9565 allow_unpredictable = TRUE;
9566 /* Fall through. */
9567 case 's':
9568 if ((given & 0x004f0000) == 0x004f0000)
9569 {
9570 /* PC relative with immediate offset. */
9571 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
9572
9573 if (PRE_BIT_SET)
9574 {
9575 /* Elide positive zero offset. */
9576 if (offset || NEGATIVE_BIT_SET)
9577 func (stream, "[pc, #%s%d]\t; ",
9578 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9579 else
9580 func (stream, "[pc]\t; ");
9581 if (NEGATIVE_BIT_SET)
9582 offset = -offset;
9583 info->print_address_func (offset + pc + 8, info);
9584 }
9585 else
9586 {
9587 /* Always show the offset. */
9588 func (stream, "[pc], #%s%d",
9589 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9590 if (! allow_unpredictable)
9591 is_unpredictable = TRUE;
9592 }
9593 }
9594 else
9595 {
9596 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
9597
9598 func (stream, "[%s",
9599 arm_regnames[(given >> 16) & 0xf]);
9600
9601 if (PRE_BIT_SET)
9602 {
9603 if (IMMEDIATE_BIT_SET)
9604 {
9605 /* Elide offset for non-writeback
9606 positive zero. */
9607 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
9608 || offset)
9609 func (stream, ", #%s%d",
9610 NEGATIVE_BIT_SET ? "-" : "", offset);
9611
9612 if (NEGATIVE_BIT_SET)
9613 offset = -offset;
9614
9615 value_in_comment = offset;
9616 }
9617 else
9618 {
9619 /* Register Offset or Register Pre-Indexed. */
9620 func (stream, ", %s%s",
9621 NEGATIVE_BIT_SET ? "-" : "",
9622 arm_regnames[given & 0xf]);
9623
9624 /* Writing back to the register that is the source/
9625 destination of the load/store is unpredictable. */
9626 if (! allow_unpredictable
9627 && WRITEBACK_BIT_SET
9628 && ((given & 0xf) == ((given >> 12) & 0xf)))
9629 is_unpredictable = TRUE;
9630 }
9631
9632 func (stream, "]%s",
9633 WRITEBACK_BIT_SET ? "!" : "");
9634 }
9635 else
9636 {
9637 if (IMMEDIATE_BIT_SET)
9638 {
9639 /* Immediate Post-indexed. */
9640 /* PR 10924: Offset must be printed, even if it is zero. */
9641 func (stream, "], #%s%d",
9642 NEGATIVE_BIT_SET ? "-" : "", offset);
9643 if (NEGATIVE_BIT_SET)
9644 offset = -offset;
9645 value_in_comment = offset;
9646 }
9647 else
9648 {
9649 /* Register Post-indexed. */
9650 func (stream, "], %s%s",
9651 NEGATIVE_BIT_SET ? "-" : "",
9652 arm_regnames[given & 0xf]);
9653
9654 /* Writing back to the register that is the source/
9655 destination of the load/store is unpredictable. */
9656 if (! allow_unpredictable
9657 && (given & 0xf) == ((given >> 12) & 0xf))
9658 is_unpredictable = TRUE;
9659 }
9660
9661 if (! allow_unpredictable)
9662 {
9663 /* Writeback is automatically implied by post- addressing.
9664 Setting the W bit is unnecessary and ARM specify it as
9665 being unpredictable. */
9666 if (WRITEBACK_BIT_SET
9667 /* Specifying the PC register as the post-indexed
9668 registers is also unpredictable. */
9669 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
9670 is_unpredictable = TRUE;
9671 }
9672 }
9673 }
9674 break;
9675
9676 case 'b':
9677 {
9678 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
9679 info->print_address_func (disp * 4 + pc + 8, info);
9680 }
9681 break;
9682
9683 case 'c':
9684 if (((given >> 28) & 0xf) != 0xe)
9685 func (stream, "%s",
9686 arm_conditional [(given >> 28) & 0xf]);
9687 break;
9688
9689 case 'm':
9690 {
9691 int started = 0;
9692 int reg;
9693
9694 func (stream, "{");
9695 for (reg = 0; reg < 16; reg++)
9696 if ((given & (1 << reg)) != 0)
9697 {
9698 if (started)
9699 func (stream, ", ");
9700 started = 1;
9701 func (stream, "%s", arm_regnames[reg]);
9702 }
9703 func (stream, "}");
9704 if (! started)
9705 is_unpredictable = TRUE;
9706 }
9707 break;
9708
9709 case 'q':
9710 arm_decode_shift (given, func, stream, FALSE);
9711 break;
9712
9713 case 'o':
9714 if ((given & 0x02000000) != 0)
9715 {
9716 unsigned int rotate = (given & 0xf00) >> 7;
9717 unsigned int immed = (given & 0xff);
9718 unsigned int a, i;
9719
9720 a = (((immed << (32 - rotate))
9721 | (immed >> rotate)) & 0xffffffff);
9722 /* If there is another encoding with smaller rotate,
9723 the rotate should be specified directly. */
9724 for (i = 0; i < 32; i += 2)
9725 if ((a << i | a >> (32 - i)) <= 0xff)
9726 break;
9727
9728 if (i != rotate)
9729 func (stream, "#%d, %d", immed, rotate);
9730 else
9731 func (stream, "#%d", a);
9732 value_in_comment = a;
9733 }
9734 else
9735 arm_decode_shift (given, func, stream, TRUE);
9736 break;
9737
9738 case 'p':
9739 if ((given & 0x0000f000) == 0x0000f000)
9740 {
9741 arm_feature_set arm_ext_v6 =
9742 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
9743
9744 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9745 mechanism for setting PSR flag bits. They are
9746 obsolete in V6 onwards. */
9747 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
9748 arm_ext_v6))
9749 func (stream, "p");
9750 else
9751 is_unpredictable = TRUE;
9752 }
9753 break;
9754
9755 case 't':
9756 if ((given & 0x01200000) == 0x00200000)
9757 func (stream, "t");
9758 break;
9759
9760 case 'A':
9761 {
9762 int offset = given & 0xff;
9763
9764 value_in_comment = offset * 4;
9765 if (NEGATIVE_BIT_SET)
9766 value_in_comment = - value_in_comment;
9767
9768 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
9769
9770 if (PRE_BIT_SET)
9771 {
9772 if (offset)
9773 func (stream, ", #%d]%s",
9774 (int) value_in_comment,
9775 WRITEBACK_BIT_SET ? "!" : "");
9776 else
9777 func (stream, "]");
9778 }
9779 else
9780 {
9781 func (stream, "]");
9782
9783 if (WRITEBACK_BIT_SET)
9784 {
9785 if (offset)
9786 func (stream, ", #%d", (int) value_in_comment);
9787 }
9788 else
9789 {
9790 func (stream, ", {%d}", (int) offset);
9791 value_in_comment = offset;
9792 }
9793 }
9794 }
9795 break;
9796
9797 case 'B':
9798 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9799 {
9800 bfd_vma address;
9801 bfd_vma offset = 0;
9802
9803 if (! NEGATIVE_BIT_SET)
9804 /* Is signed, hi bits should be ones. */
9805 offset = (-1) ^ 0x00ffffff;
9806
9807 /* Offset is (SignExtend(offset field)<<2). */
9808 offset += given & 0x00ffffff;
9809 offset <<= 2;
9810 address = offset + pc + 8;
9811
9812 if (given & 0x01000000)
9813 /* H bit allows addressing to 2-byte boundaries. */
9814 address += 2;
9815
9816 info->print_address_func (address, info);
9817 }
9818 break;
9819
9820 case 'C':
9821 if ((given & 0x02000200) == 0x200)
9822 {
9823 const char * name;
9824 unsigned sysm = (given & 0x004f0000) >> 16;
9825
9826 sysm |= (given & 0x300) >> 4;
9827 name = banked_regname (sysm);
9828
9829 if (name != NULL)
9830 func (stream, "%s", name);
9831 else
9832 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9833 }
9834 else
9835 {
9836 func (stream, "%cPSR_",
9837 (given & 0x00400000) ? 'S' : 'C');
9838 if (given & 0x80000)
9839 func (stream, "f");
9840 if (given & 0x40000)
9841 func (stream, "s");
9842 if (given & 0x20000)
9843 func (stream, "x");
9844 if (given & 0x10000)
9845 func (stream, "c");
9846 }
9847 break;
9848
9849 case 'U':
9850 if ((given & 0xf0) == 0x60)
9851 {
9852 switch (given & 0xf)
9853 {
9854 case 0xf: func (stream, "sy"); break;
9855 default:
9856 func (stream, "#%d", (int) given & 0xf);
9857 break;
9858 }
9859 }
9860 else
9861 {
9862 const char * opt = data_barrier_option (given & 0xf);
9863 if (opt != NULL)
9864 func (stream, "%s", opt);
9865 else
9866 func (stream, "#%d", (int) given & 0xf);
9867 }
9868 break;
9869
9870 case '0': case '1': case '2': case '3': case '4':
9871 case '5': case '6': case '7': case '8': case '9':
9872 {
9873 int width;
9874 unsigned long value;
9875
9876 c = arm_decode_bitfield (c, given, &value, &width);
9877
9878 switch (*c)
9879 {
9880 case 'R':
9881 if (value == 15)
9882 is_unpredictable = TRUE;
9883 /* Fall through. */
9884 case 'r':
9885 case 'T':
9886 /* We want register + 1 when decoding T. */
9887 if (*c == 'T')
9888 ++value;
9889
9890 if (c[1] == 'u')
9891 {
9892 /* Eat the 'u' character. */
9893 ++ c;
9894
9895 if (u_reg == value)
9896 is_unpredictable = TRUE;
9897 u_reg = value;
9898 }
9899 if (c[1] == 'U')
9900 {
9901 /* Eat the 'U' character. */
9902 ++ c;
9903
9904 if (U_reg == value)
9905 is_unpredictable = TRUE;
9906 U_reg = value;
9907 }
9908 func (stream, "%s", arm_regnames[value]);
9909 break;
9910 case 'd':
9911 func (stream, "%ld", value);
9912 value_in_comment = value;
9913 break;
9914 case 'b':
9915 func (stream, "%ld", value * 8);
9916 value_in_comment = value * 8;
9917 break;
9918 case 'W':
9919 func (stream, "%ld", value + 1);
9920 value_in_comment = value + 1;
9921 break;
9922 case 'x':
9923 func (stream, "0x%08lx", value);
9924
9925 /* Some SWI instructions have special
9926 meanings. */
9927 if ((given & 0x0fffffff) == 0x0FF00000)
9928 func (stream, "\t; IMB");
9929 else if ((given & 0x0fffffff) == 0x0FF00001)
9930 func (stream, "\t; IMBRange");
9931 break;
9932 case 'X':
9933 func (stream, "%01lx", value & 0xf);
9934 value_in_comment = value;
9935 break;
9936 case '`':
9937 c++;
9938 if (value == 0)
9939 func (stream, "%c", *c);
9940 break;
9941 case '\'':
9942 c++;
9943 if (value == ((1ul << width) - 1))
9944 func (stream, "%c", *c);
9945 break;
9946 case '?':
9947 func (stream, "%c", c[(1 << width) - (int) value]);
9948 c += 1 << width;
9949 break;
9950 default:
9951 abort ();
9952 }
9953 }
9954 break;
9955
9956 case 'e':
9957 {
9958 int imm;
9959
9960 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
9961 func (stream, "%d", imm);
9962 value_in_comment = imm;
9963 }
9964 break;
9965
9966 case 'E':
9967 /* LSB and WIDTH fields of BFI or BFC. The machine-
9968 language instruction encodes LSB and MSB. */
9969 {
9970 long msb = (given & 0x001f0000) >> 16;
9971 long lsb = (given & 0x00000f80) >> 7;
9972 long w = msb - lsb + 1;
9973
9974 if (w > 0)
9975 func (stream, "#%lu, #%lu", lsb, w);
9976 else
9977 func (stream, "(invalid: %lu:%lu)", lsb, msb);
9978 }
9979 break;
9980
9981 case 'R':
9982 /* Get the PSR/banked register name. */
9983 {
9984 const char * name;
9985 unsigned sysm = (given & 0x004f0000) >> 16;
9986
9987 sysm |= (given & 0x300) >> 4;
9988 name = banked_regname (sysm);
9989
9990 if (name != NULL)
9991 func (stream, "%s", name);
9992 else
9993 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9994 }
9995 break;
9996
9997 case 'V':
9998 /* 16-bit unsigned immediate from a MOVT or MOVW
9999 instruction, encoded in bits 0:11 and 15:19. */
10000 {
10001 long hi = (given & 0x000f0000) >> 4;
10002 long lo = (given & 0x00000fff);
10003 long imm16 = hi | lo;
10004
10005 func (stream, "#%lu", imm16);
10006 value_in_comment = imm16;
10007 }
10008 break;
10009
10010 default:
10011 abort ();
10012 }
10013 }
10014 else
10015 func (stream, "%c", *c);
10016 }
10017
10018 if (value_in_comment > 32 || value_in_comment < -16)
10019 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
10020
10021 if (is_unpredictable)
10022 func (stream, UNPREDICTABLE_INSTRUCTION);
10023
10024 return;
10025 }
10026 }
10027 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10028 return;
10029 }
10030
10031 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
10032
10033 static void
10034 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
10035 {
10036 const struct opcode16 *insn;
10037 void *stream = info->stream;
10038 fprintf_ftype func = info->fprintf_func;
10039
10040 for (insn = thumb_opcodes; insn->assembler; insn++)
10041 if ((given & insn->mask) == insn->value)
10042 {
10043 signed long value_in_comment = 0;
10044 const char *c = insn->assembler;
10045
10046 for (; *c; c++)
10047 {
10048 int domaskpc = 0;
10049 int domasklr = 0;
10050
10051 if (*c != '%')
10052 {
10053 func (stream, "%c", *c);
10054 continue;
10055 }
10056
10057 switch (*++c)
10058 {
10059 case '%':
10060 func (stream, "%%");
10061 break;
10062
10063 case 'c':
10064 if (ifthen_state)
10065 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10066 break;
10067
10068 case 'C':
10069 if (ifthen_state)
10070 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10071 else
10072 func (stream, "s");
10073 break;
10074
10075 case 'I':
10076 {
10077 unsigned int tmp;
10078
10079 ifthen_next_state = given & 0xff;
10080 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10081 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10082 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10083 }
10084 break;
10085
10086 case 'x':
10087 if (ifthen_next_state)
10088 func (stream, "\t; unpredictable branch in IT block\n");
10089 break;
10090
10091 case 'X':
10092 if (ifthen_state)
10093 func (stream, "\t; unpredictable <IT:%s>",
10094 arm_conditional[IFTHEN_COND]);
10095 break;
10096
10097 case 'S':
10098 {
10099 long reg;
10100
10101 reg = (given >> 3) & 0x7;
10102 if (given & (1 << 6))
10103 reg += 8;
10104
10105 func (stream, "%s", arm_regnames[reg]);
10106 }
10107 break;
10108
10109 case 'D':
10110 {
10111 long reg;
10112
10113 reg = given & 0x7;
10114 if (given & (1 << 7))
10115 reg += 8;
10116
10117 func (stream, "%s", arm_regnames[reg]);
10118 }
10119 break;
10120
10121 case 'N':
10122 if (given & (1 << 8))
10123 domasklr = 1;
10124 /* Fall through. */
10125 case 'O':
10126 if (*c == 'O' && (given & (1 << 8)))
10127 domaskpc = 1;
10128 /* Fall through. */
10129 case 'M':
10130 {
10131 int started = 0;
10132 int reg;
10133
10134 func (stream, "{");
10135
10136 /* It would be nice if we could spot
10137 ranges, and generate the rS-rE format: */
10138 for (reg = 0; (reg < 8); reg++)
10139 if ((given & (1 << reg)) != 0)
10140 {
10141 if (started)
10142 func (stream, ", ");
10143 started = 1;
10144 func (stream, "%s", arm_regnames[reg]);
10145 }
10146
10147 if (domasklr)
10148 {
10149 if (started)
10150 func (stream, ", ");
10151 started = 1;
10152 func (stream, "%s", arm_regnames[14] /* "lr" */);
10153 }
10154
10155 if (domaskpc)
10156 {
10157 if (started)
10158 func (stream, ", ");
10159 func (stream, "%s", arm_regnames[15] /* "pc" */);
10160 }
10161
10162 func (stream, "}");
10163 }
10164 break;
10165
10166 case 'W':
10167 /* Print writeback indicator for a LDMIA. We are doing a
10168 writeback if the base register is not in the register
10169 mask. */
10170 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10171 func (stream, "!");
10172 break;
10173
10174 case 'b':
10175 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10176 {
10177 bfd_vma address = (pc + 4
10178 + ((given & 0x00f8) >> 2)
10179 + ((given & 0x0200) >> 3));
10180 info->print_address_func (address, info);
10181 }
10182 break;
10183
10184 case 's':
10185 /* Right shift immediate -- bits 6..10; 1-31 print
10186 as themselves, 0 prints as 32. */
10187 {
10188 long imm = (given & 0x07c0) >> 6;
10189 if (imm == 0)
10190 imm = 32;
10191 func (stream, "#%ld", imm);
10192 }
10193 break;
10194
10195 case '0': case '1': case '2': case '3': case '4':
10196 case '5': case '6': case '7': case '8': case '9':
10197 {
10198 int bitstart = *c++ - '0';
10199 int bitend = 0;
10200
10201 while (*c >= '0' && *c <= '9')
10202 bitstart = (bitstart * 10) + *c++ - '0';
10203
10204 switch (*c)
10205 {
10206 case '-':
10207 {
10208 bfd_vma reg;
10209
10210 c++;
10211 while (*c >= '0' && *c <= '9')
10212 bitend = (bitend * 10) + *c++ - '0';
10213 if (!bitend)
10214 abort ();
10215 reg = given >> bitstart;
10216 reg &= (2 << (bitend - bitstart)) - 1;
10217
10218 switch (*c)
10219 {
10220 case 'r':
10221 func (stream, "%s", arm_regnames[reg]);
10222 break;
10223
10224 case 'd':
10225 func (stream, "%ld", (long) reg);
10226 value_in_comment = reg;
10227 break;
10228
10229 case 'H':
10230 func (stream, "%ld", (long) (reg << 1));
10231 value_in_comment = reg << 1;
10232 break;
10233
10234 case 'W':
10235 func (stream, "%ld", (long) (reg << 2));
10236 value_in_comment = reg << 2;
10237 break;
10238
10239 case 'a':
10240 /* PC-relative address -- the bottom two
10241 bits of the address are dropped
10242 before the calculation. */
10243 info->print_address_func
10244 (((pc + 4) & ~3) + (reg << 2), info);
10245 value_in_comment = 0;
10246 break;
10247
10248 case 'x':
10249 func (stream, "0x%04lx", (long) reg);
10250 break;
10251
10252 case 'B':
10253 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
10254 info->print_address_func (reg * 2 + pc + 4, info);
10255 value_in_comment = 0;
10256 break;
10257
10258 case 'c':
10259 func (stream, "%s", arm_conditional [reg]);
10260 break;
10261
10262 default:
10263 abort ();
10264 }
10265 }
10266 break;
10267
10268 case '\'':
10269 c++;
10270 if ((given & (1 << bitstart)) != 0)
10271 func (stream, "%c", *c);
10272 break;
10273
10274 case '?':
10275 ++c;
10276 if ((given & (1 << bitstart)) != 0)
10277 func (stream, "%c", *c++);
10278 else
10279 func (stream, "%c", *++c);
10280 break;
10281
10282 default:
10283 abort ();
10284 }
10285 }
10286 break;
10287
10288 default:
10289 abort ();
10290 }
10291 }
10292
10293 if (value_in_comment > 32 || value_in_comment < -16)
10294 func (stream, "\t; 0x%lx", value_in_comment);
10295 return;
10296 }
10297
10298 /* No match. */
10299 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10300 return;
10301 }
10302
10303 /* Return the name of an V7M special register. */
10304
10305 static const char *
10306 psr_name (int regno)
10307 {
10308 switch (regno)
10309 {
10310 case 0x0: return "APSR";
10311 case 0x1: return "IAPSR";
10312 case 0x2: return "EAPSR";
10313 case 0x3: return "PSR";
10314 case 0x5: return "IPSR";
10315 case 0x6: return "EPSR";
10316 case 0x7: return "IEPSR";
10317 case 0x8: return "MSP";
10318 case 0x9: return "PSP";
10319 case 0xa: return "MSPLIM";
10320 case 0xb: return "PSPLIM";
10321 case 0x10: return "PRIMASK";
10322 case 0x11: return "BASEPRI";
10323 case 0x12: return "BASEPRI_MAX";
10324 case 0x13: return "FAULTMASK";
10325 case 0x14: return "CONTROL";
10326 case 0x88: return "MSP_NS";
10327 case 0x89: return "PSP_NS";
10328 case 0x8a: return "MSPLIM_NS";
10329 case 0x8b: return "PSPLIM_NS";
10330 case 0x90: return "PRIMASK_NS";
10331 case 0x91: return "BASEPRI_NS";
10332 case 0x93: return "FAULTMASK_NS";
10333 case 0x94: return "CONTROL_NS";
10334 case 0x98: return "SP_NS";
10335 default: return "<unknown>";
10336 }
10337 }
10338
10339 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10340
10341 static void
10342 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
10343 {
10344 const struct opcode32 *insn;
10345 void *stream = info->stream;
10346 fprintf_ftype func = info->fprintf_func;
10347 bfd_boolean is_mve = is_mve_architecture (info);
10348
10349 if (print_insn_coprocessor (pc, info, given, TRUE))
10350 return;
10351
10352 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
10353 return;
10354
10355 if (is_mve && print_insn_mve (info, given))
10356 return;
10357
10358 for (insn = thumb32_opcodes; insn->assembler; insn++)
10359 if ((given & insn->mask) == insn->value)
10360 {
10361 bfd_boolean is_clrm = FALSE;
10362 bfd_boolean is_unpredictable = FALSE;
10363 signed long value_in_comment = 0;
10364 const char *c = insn->assembler;
10365
10366 for (; *c; c++)
10367 {
10368 if (*c != '%')
10369 {
10370 func (stream, "%c", *c);
10371 continue;
10372 }
10373
10374 switch (*++c)
10375 {
10376 case '%':
10377 func (stream, "%%");
10378 break;
10379
10380 case 'c':
10381 if (ifthen_state)
10382 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10383 break;
10384
10385 case 'x':
10386 if (ifthen_next_state)
10387 func (stream, "\t; unpredictable branch in IT block\n");
10388 break;
10389
10390 case 'X':
10391 if (ifthen_state)
10392 func (stream, "\t; unpredictable <IT:%s>",
10393 arm_conditional[IFTHEN_COND]);
10394 break;
10395
10396 case 'I':
10397 {
10398 unsigned int imm12 = 0;
10399
10400 imm12 |= (given & 0x000000ffu);
10401 imm12 |= (given & 0x00007000u) >> 4;
10402 imm12 |= (given & 0x04000000u) >> 15;
10403 func (stream, "#%u", imm12);
10404 value_in_comment = imm12;
10405 }
10406 break;
10407
10408 case 'M':
10409 {
10410 unsigned int bits = 0, imm, imm8, mod;
10411
10412 bits |= (given & 0x000000ffu);
10413 bits |= (given & 0x00007000u) >> 4;
10414 bits |= (given & 0x04000000u) >> 15;
10415 imm8 = (bits & 0x0ff);
10416 mod = (bits & 0xf00) >> 8;
10417 switch (mod)
10418 {
10419 case 0: imm = imm8; break;
10420 case 1: imm = ((imm8 << 16) | imm8); break;
10421 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10422 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
10423 default:
10424 mod = (bits & 0xf80) >> 7;
10425 imm8 = (bits & 0x07f) | 0x80;
10426 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10427 }
10428 func (stream, "#%u", imm);
10429 value_in_comment = imm;
10430 }
10431 break;
10432
10433 case 'J':
10434 {
10435 unsigned int imm = 0;
10436
10437 imm |= (given & 0x000000ffu);
10438 imm |= (given & 0x00007000u) >> 4;
10439 imm |= (given & 0x04000000u) >> 15;
10440 imm |= (given & 0x000f0000u) >> 4;
10441 func (stream, "#%u", imm);
10442 value_in_comment = imm;
10443 }
10444 break;
10445
10446 case 'K':
10447 {
10448 unsigned int imm = 0;
10449
10450 imm |= (given & 0x000f0000u) >> 16;
10451 imm |= (given & 0x00000ff0u) >> 0;
10452 imm |= (given & 0x0000000fu) << 12;
10453 func (stream, "#%u", imm);
10454 value_in_comment = imm;
10455 }
10456 break;
10457
10458 case 'H':
10459 {
10460 unsigned int imm = 0;
10461
10462 imm |= (given & 0x000f0000u) >> 4;
10463 imm |= (given & 0x00000fffu) >> 0;
10464 func (stream, "#%u", imm);
10465 value_in_comment = imm;
10466 }
10467 break;
10468
10469 case 'V':
10470 {
10471 unsigned int imm = 0;
10472
10473 imm |= (given & 0x00000fffu);
10474 imm |= (given & 0x000f0000u) >> 4;
10475 func (stream, "#%u", imm);
10476 value_in_comment = imm;
10477 }
10478 break;
10479
10480 case 'S':
10481 {
10482 unsigned int reg = (given & 0x0000000fu);
10483 unsigned int stp = (given & 0x00000030u) >> 4;
10484 unsigned int imm = 0;
10485 imm |= (given & 0x000000c0u) >> 6;
10486 imm |= (given & 0x00007000u) >> 10;
10487
10488 func (stream, "%s", arm_regnames[reg]);
10489 switch (stp)
10490 {
10491 case 0:
10492 if (imm > 0)
10493 func (stream, ", lsl #%u", imm);
10494 break;
10495
10496 case 1:
10497 if (imm == 0)
10498 imm = 32;
10499 func (stream, ", lsr #%u", imm);
10500 break;
10501
10502 case 2:
10503 if (imm == 0)
10504 imm = 32;
10505 func (stream, ", asr #%u", imm);
10506 break;
10507
10508 case 3:
10509 if (imm == 0)
10510 func (stream, ", rrx");
10511 else
10512 func (stream, ", ror #%u", imm);
10513 }
10514 }
10515 break;
10516
10517 case 'a':
10518 {
10519 unsigned int Rn = (given & 0x000f0000) >> 16;
10520 unsigned int U = ! NEGATIVE_BIT_SET;
10521 unsigned int op = (given & 0x00000f00) >> 8;
10522 unsigned int i12 = (given & 0x00000fff);
10523 unsigned int i8 = (given & 0x000000ff);
10524 bfd_boolean writeback = FALSE, postind = FALSE;
10525 bfd_vma offset = 0;
10526
10527 func (stream, "[%s", arm_regnames[Rn]);
10528 if (U) /* 12-bit positive immediate offset. */
10529 {
10530 offset = i12;
10531 if (Rn != 15)
10532 value_in_comment = offset;
10533 }
10534 else if (Rn == 15) /* 12-bit negative immediate offset. */
10535 offset = - (int) i12;
10536 else if (op == 0x0) /* Shifted register offset. */
10537 {
10538 unsigned int Rm = (i8 & 0x0f);
10539 unsigned int sh = (i8 & 0x30) >> 4;
10540
10541 func (stream, ", %s", arm_regnames[Rm]);
10542 if (sh)
10543 func (stream, ", lsl #%u", sh);
10544 func (stream, "]");
10545 break;
10546 }
10547 else switch (op)
10548 {
10549 case 0xE: /* 8-bit positive immediate offset. */
10550 offset = i8;
10551 break;
10552
10553 case 0xC: /* 8-bit negative immediate offset. */
10554 offset = -i8;
10555 break;
10556
10557 case 0xF: /* 8-bit + preindex with wb. */
10558 offset = i8;
10559 writeback = TRUE;
10560 break;
10561
10562 case 0xD: /* 8-bit - preindex with wb. */
10563 offset = -i8;
10564 writeback = TRUE;
10565 break;
10566
10567 case 0xB: /* 8-bit + postindex. */
10568 offset = i8;
10569 postind = TRUE;
10570 break;
10571
10572 case 0x9: /* 8-bit - postindex. */
10573 offset = -i8;
10574 postind = TRUE;
10575 break;
10576
10577 default:
10578 func (stream, ", <undefined>]");
10579 goto skip;
10580 }
10581
10582 if (postind)
10583 func (stream, "], #%d", (int) offset);
10584 else
10585 {
10586 if (offset)
10587 func (stream, ", #%d", (int) offset);
10588 func (stream, writeback ? "]!" : "]");
10589 }
10590
10591 if (Rn == 15)
10592 {
10593 func (stream, "\t; ");
10594 info->print_address_func (((pc + 4) & ~3) + offset, info);
10595 }
10596 }
10597 skip:
10598 break;
10599
10600 case 'A':
10601 {
10602 unsigned int U = ! NEGATIVE_BIT_SET;
10603 unsigned int W = WRITEBACK_BIT_SET;
10604 unsigned int Rn = (given & 0x000f0000) >> 16;
10605 unsigned int off = (given & 0x000000ff);
10606
10607 func (stream, "[%s", arm_regnames[Rn]);
10608
10609 if (PRE_BIT_SET)
10610 {
10611 if (off || !U)
10612 {
10613 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
10614 value_in_comment = off * 4 * (U ? 1 : -1);
10615 }
10616 func (stream, "]");
10617 if (W)
10618 func (stream, "!");
10619 }
10620 else
10621 {
10622 func (stream, "], ");
10623 if (W)
10624 {
10625 func (stream, "#%c%u", U ? '+' : '-', off * 4);
10626 value_in_comment = off * 4 * (U ? 1 : -1);
10627 }
10628 else
10629 {
10630 func (stream, "{%u}", off);
10631 value_in_comment = off;
10632 }
10633 }
10634 }
10635 break;
10636
10637 case 'w':
10638 {
10639 unsigned int Sbit = (given & 0x01000000) >> 24;
10640 unsigned int type = (given & 0x00600000) >> 21;
10641
10642 switch (type)
10643 {
10644 case 0: func (stream, Sbit ? "sb" : "b"); break;
10645 case 1: func (stream, Sbit ? "sh" : "h"); break;
10646 case 2:
10647 if (Sbit)
10648 func (stream, "??");
10649 break;
10650 case 3:
10651 func (stream, "??");
10652 break;
10653 }
10654 }
10655 break;
10656
10657 case 'n':
10658 is_clrm = TRUE;
10659 /* Fall through. */
10660 case 'm':
10661 {
10662 int started = 0;
10663 int reg;
10664
10665 func (stream, "{");
10666 for (reg = 0; reg < 16; reg++)
10667 if ((given & (1 << reg)) != 0)
10668 {
10669 if (started)
10670 func (stream, ", ");
10671 started = 1;
10672 if (is_clrm && reg == 13)
10673 func (stream, "(invalid: %s)", arm_regnames[reg]);
10674 else if (is_clrm && reg == 15)
10675 func (stream, "%s", "APSR");
10676 else
10677 func (stream, "%s", arm_regnames[reg]);
10678 }
10679 func (stream, "}");
10680 }
10681 break;
10682
10683 case 'E':
10684 {
10685 unsigned int msb = (given & 0x0000001f);
10686 unsigned int lsb = 0;
10687
10688 lsb |= (given & 0x000000c0u) >> 6;
10689 lsb |= (given & 0x00007000u) >> 10;
10690 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
10691 }
10692 break;
10693
10694 case 'F':
10695 {
10696 unsigned int width = (given & 0x0000001f) + 1;
10697 unsigned int lsb = 0;
10698
10699 lsb |= (given & 0x000000c0u) >> 6;
10700 lsb |= (given & 0x00007000u) >> 10;
10701 func (stream, "#%u, #%u", lsb, width);
10702 }
10703 break;
10704
10705 case 'G':
10706 {
10707 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
10708 func (stream, "%x", boff);
10709 }
10710 break;
10711
10712 case 'W':
10713 {
10714 unsigned int immA = (given & 0x001f0000u) >> 16;
10715 unsigned int immB = (given & 0x000007feu) >> 1;
10716 unsigned int immC = (given & 0x00000800u) >> 11;
10717 bfd_vma offset = 0;
10718
10719 offset |= immA << 12;
10720 offset |= immB << 2;
10721 offset |= immC << 1;
10722 /* Sign extend. */
10723 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
10724
10725 info->print_address_func (pc + 4 + offset, info);
10726 }
10727 break;
10728
10729 case 'Y':
10730 {
10731 unsigned int immA = (given & 0x007f0000u) >> 16;
10732 unsigned int immB = (given & 0x000007feu) >> 1;
10733 unsigned int immC = (given & 0x00000800u) >> 11;
10734 bfd_vma offset = 0;
10735
10736 offset |= immA << 12;
10737 offset |= immB << 2;
10738 offset |= immC << 1;
10739 /* Sign extend. */
10740 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
10741
10742 info->print_address_func (pc + 4 + offset, info);
10743 }
10744 break;
10745
10746 case 'Z':
10747 {
10748 unsigned int immA = (given & 0x00010000u) >> 16;
10749 unsigned int immB = (given & 0x000007feu) >> 1;
10750 unsigned int immC = (given & 0x00000800u) >> 11;
10751 bfd_vma offset = 0;
10752
10753 offset |= immA << 12;
10754 offset |= immB << 2;
10755 offset |= immC << 1;
10756 /* Sign extend. */
10757 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
10758
10759 info->print_address_func (pc + 4 + offset, info);
10760
10761 unsigned int T = (given & 0x00020000u) >> 17;
10762 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10763 unsigned int boffset = (T == 1) ? 4 : 2;
10764 func (stream, ", ");
10765 func (stream, "%x", endoffset + boffset);
10766 }
10767 break;
10768
10769 case 'Q':
10770 {
10771 unsigned int immh = (given & 0x000007feu) >> 1;
10772 unsigned int imml = (given & 0x00000800u) >> 11;
10773 bfd_vma imm32 = 0;
10774
10775 imm32 |= immh << 2;
10776 imm32 |= imml << 1;
10777
10778 info->print_address_func (pc + 4 + imm32, info);
10779 }
10780 break;
10781
10782 case 'P':
10783 {
10784 unsigned int immh = (given & 0x000007feu) >> 1;
10785 unsigned int imml = (given & 0x00000800u) >> 11;
10786 bfd_vma imm32 = 0;
10787
10788 imm32 |= immh << 2;
10789 imm32 |= imml << 1;
10790
10791 info->print_address_func (pc + 4 - imm32, info);
10792 }
10793 break;
10794
10795 case 'b':
10796 {
10797 unsigned int S = (given & 0x04000000u) >> 26;
10798 unsigned int J1 = (given & 0x00002000u) >> 13;
10799 unsigned int J2 = (given & 0x00000800u) >> 11;
10800 bfd_vma offset = 0;
10801
10802 offset |= !S << 20;
10803 offset |= J2 << 19;
10804 offset |= J1 << 18;
10805 offset |= (given & 0x003f0000) >> 4;
10806 offset |= (given & 0x000007ff) << 1;
10807 offset -= (1 << 20);
10808
10809 info->print_address_func (pc + 4 + offset, info);
10810 }
10811 break;
10812
10813 case 'B':
10814 {
10815 unsigned int S = (given & 0x04000000u) >> 26;
10816 unsigned int I1 = (given & 0x00002000u) >> 13;
10817 unsigned int I2 = (given & 0x00000800u) >> 11;
10818 bfd_vma offset = 0;
10819
10820 offset |= !S << 24;
10821 offset |= !(I1 ^ S) << 23;
10822 offset |= !(I2 ^ S) << 22;
10823 offset |= (given & 0x03ff0000u) >> 4;
10824 offset |= (given & 0x000007ffu) << 1;
10825 offset -= (1 << 24);
10826 offset += pc + 4;
10827
10828 /* BLX target addresses are always word aligned. */
10829 if ((given & 0x00001000u) == 0)
10830 offset &= ~2u;
10831
10832 info->print_address_func (offset, info);
10833 }
10834 break;
10835
10836 case 's':
10837 {
10838 unsigned int shift = 0;
10839
10840 shift |= (given & 0x000000c0u) >> 6;
10841 shift |= (given & 0x00007000u) >> 10;
10842 if (WRITEBACK_BIT_SET)
10843 func (stream, ", asr #%u", shift);
10844 else if (shift)
10845 func (stream, ", lsl #%u", shift);
10846 /* else print nothing - lsl #0 */
10847 }
10848 break;
10849
10850 case 'R':
10851 {
10852 unsigned int rot = (given & 0x00000030) >> 4;
10853
10854 if (rot)
10855 func (stream, ", ror #%u", rot * 8);
10856 }
10857 break;
10858
10859 case 'U':
10860 if ((given & 0xf0) == 0x60)
10861 {
10862 switch (given & 0xf)
10863 {
10864 case 0xf: func (stream, "sy"); break;
10865 default:
10866 func (stream, "#%d", (int) given & 0xf);
10867 break;
10868 }
10869 }
10870 else
10871 {
10872 const char * opt = data_barrier_option (given & 0xf);
10873 if (opt != NULL)
10874 func (stream, "%s", opt);
10875 else
10876 func (stream, "#%d", (int) given & 0xf);
10877 }
10878 break;
10879
10880 case 'C':
10881 if ((given & 0xff) == 0)
10882 {
10883 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
10884 if (given & 0x800)
10885 func (stream, "f");
10886 if (given & 0x400)
10887 func (stream, "s");
10888 if (given & 0x200)
10889 func (stream, "x");
10890 if (given & 0x100)
10891 func (stream, "c");
10892 }
10893 else if ((given & 0x20) == 0x20)
10894 {
10895 char const* name;
10896 unsigned sysm = (given & 0xf00) >> 8;
10897
10898 sysm |= (given & 0x30);
10899 sysm |= (given & 0x00100000) >> 14;
10900 name = banked_regname (sysm);
10901
10902 if (name != NULL)
10903 func (stream, "%s", name);
10904 else
10905 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10906 }
10907 else
10908 {
10909 func (stream, "%s", psr_name (given & 0xff));
10910 }
10911 break;
10912
10913 case 'D':
10914 if (((given & 0xff) == 0)
10915 || ((given & 0x20) == 0x20))
10916 {
10917 char const* name;
10918 unsigned sm = (given & 0xf0000) >> 16;
10919
10920 sm |= (given & 0x30);
10921 sm |= (given & 0x00100000) >> 14;
10922 name = banked_regname (sm);
10923
10924 if (name != NULL)
10925 func (stream, "%s", name);
10926 else
10927 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
10928 }
10929 else
10930 func (stream, "%s", psr_name (given & 0xff));
10931 break;
10932
10933 case '0': case '1': case '2': case '3': case '4':
10934 case '5': case '6': case '7': case '8': case '9':
10935 {
10936 int width;
10937 unsigned long val;
10938
10939 c = arm_decode_bitfield (c, given, &val, &width);
10940
10941 switch (*c)
10942 {
10943 case 's':
10944 if (val <= 3)
10945 func (stream, "%s", mve_vec_sizename[val]);
10946 else
10947 func (stream, "<undef size>");
10948 break;
10949
10950 case 'd':
10951 func (stream, "%lu", val);
10952 value_in_comment = val;
10953 break;
10954
10955 case 'D':
10956 func (stream, "%lu", val + 1);
10957 value_in_comment = val + 1;
10958 break;
10959
10960 case 'W':
10961 func (stream, "%lu", val * 4);
10962 value_in_comment = val * 4;
10963 break;
10964
10965 case 'S':
10966 if (val == 13)
10967 is_unpredictable = TRUE;
10968 /* Fall through. */
10969 case 'R':
10970 if (val == 15)
10971 is_unpredictable = TRUE;
10972 /* Fall through. */
10973 case 'r':
10974 func (stream, "%s", arm_regnames[val]);
10975 break;
10976
10977 case 'c':
10978 func (stream, "%s", arm_conditional[val]);
10979 break;
10980
10981 case '\'':
10982 c++;
10983 if (val == ((1ul << width) - 1))
10984 func (stream, "%c", *c);
10985 break;
10986
10987 case '`':
10988 c++;
10989 if (val == 0)
10990 func (stream, "%c", *c);
10991 break;
10992
10993 case '?':
10994 func (stream, "%c", c[(1 << width) - (int) val]);
10995 c += 1 << width;
10996 break;
10997
10998 case 'x':
10999 func (stream, "0x%lx", val & 0xffffffffUL);
11000 break;
11001
11002 default:
11003 abort ();
11004 }
11005 }
11006 break;
11007
11008 case 'L':
11009 /* PR binutils/12534
11010 If we have a PC relative offset in an LDRD or STRD
11011 instructions then display the decoded address. */
11012 if (((given >> 16) & 0xf) == 0xf)
11013 {
11014 bfd_vma offset = (given & 0xff) * 4;
11015
11016 if ((given & (1 << 23)) == 0)
11017 offset = - offset;
11018 func (stream, "\t; ");
11019 info->print_address_func ((pc & ~3) + 4 + offset, info);
11020 }
11021 break;
11022
11023 default:
11024 abort ();
11025 }
11026 }
11027
11028 if (value_in_comment > 32 || value_in_comment < -16)
11029 func (stream, "\t; 0x%lx", value_in_comment);
11030
11031 if (is_unpredictable)
11032 func (stream, UNPREDICTABLE_INSTRUCTION);
11033
11034 return;
11035 }
11036
11037 /* No match. */
11038 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11039 return;
11040 }
11041
11042 /* Print data bytes on INFO->STREAM. */
11043
11044 static void
11045 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11046 struct disassemble_info *info,
11047 long given)
11048 {
11049 switch (info->bytes_per_chunk)
11050 {
11051 case 1:
11052 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11053 break;
11054 case 2:
11055 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11056 break;
11057 case 4:
11058 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11059 break;
11060 default:
11061 abort ();
11062 }
11063 }
11064
11065 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
11066 being displayed in symbol relative addresses.
11067
11068 Also disallow private symbol, with __tagsym$$ prefix,
11069 from ARM RVCT toolchain being displayed. */
11070
11071 bfd_boolean
11072 arm_symbol_is_valid (asymbol * sym,
11073 struct disassemble_info * info ATTRIBUTE_UNUSED)
11074 {
11075 const char * name;
11076
11077 if (sym == NULL)
11078 return FALSE;
11079
11080 name = bfd_asymbol_name (sym);
11081
11082 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
11083 }
11084
11085 /* Parse the string of disassembler options. */
11086
11087 static void
11088 parse_arm_disassembler_options (const char *options)
11089 {
11090 const char *opt;
11091
11092 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
11093 {
11094 if (CONST_STRNEQ (opt, "reg-names-"))
11095 {
11096 unsigned int i;
11097 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11098 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11099 {
11100 regname_selected = i;
11101 break;
11102 }
11103
11104 if (i >= NUM_ARM_OPTIONS)
11105 /* xgettext: c-format */
11106 opcodes_error_handler (_("unrecognised register name set: %s"),
11107 opt);
11108 }
11109 else if (CONST_STRNEQ (opt, "force-thumb"))
11110 force_thumb = 1;
11111 else if (CONST_STRNEQ (opt, "no-force-thumb"))
11112 force_thumb = 0;
11113 else
11114 /* xgettext: c-format */
11115 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
11116 }
11117
11118 return;
11119 }
11120
11121 static bfd_boolean
11122 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11123 enum map_type *map_symbol);
11124
11125 /* Search back through the insn stream to determine if this instruction is
11126 conditionally executed. */
11127
11128 static void
11129 find_ifthen_state (bfd_vma pc,
11130 struct disassemble_info *info,
11131 bfd_boolean little)
11132 {
11133 unsigned char b[2];
11134 unsigned int insn;
11135 int status;
11136 /* COUNT is twice the number of instructions seen. It will be odd if we
11137 just crossed an instruction boundary. */
11138 int count;
11139 int it_count;
11140 unsigned int seen_it;
11141 bfd_vma addr;
11142
11143 ifthen_address = pc;
11144 ifthen_state = 0;
11145
11146 addr = pc;
11147 count = 1;
11148 it_count = 0;
11149 seen_it = 0;
11150 /* Scan backwards looking for IT instructions, keeping track of where
11151 instruction boundaries are. We don't know if something is actually an
11152 IT instruction until we find a definite instruction boundary. */
11153 for (;;)
11154 {
11155 if (addr == 0 || info->symbol_at_address_func (addr, info))
11156 {
11157 /* A symbol must be on an instruction boundary, and will not
11158 be within an IT block. */
11159 if (seen_it && (count & 1))
11160 break;
11161
11162 return;
11163 }
11164 addr -= 2;
11165 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
11166 if (status)
11167 return;
11168
11169 if (little)
11170 insn = (b[0]) | (b[1] << 8);
11171 else
11172 insn = (b[1]) | (b[0] << 8);
11173 if (seen_it)
11174 {
11175 if ((insn & 0xf800) < 0xe800)
11176 {
11177 /* Addr + 2 is an instruction boundary. See if this matches
11178 the expected boundary based on the position of the last
11179 IT candidate. */
11180 if (count & 1)
11181 break;
11182 seen_it = 0;
11183 }
11184 }
11185 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11186 {
11187 enum map_type type = MAP_ARM;
11188 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
11189
11190 if (!found || (found && type == MAP_THUMB))
11191 {
11192 /* This could be an IT instruction. */
11193 seen_it = insn;
11194 it_count = count >> 1;
11195 }
11196 }
11197 if ((insn & 0xf800) >= 0xe800)
11198 count++;
11199 else
11200 count = (count + 2) | 1;
11201 /* IT blocks contain at most 4 instructions. */
11202 if (count >= 8 && !seen_it)
11203 return;
11204 }
11205 /* We found an IT instruction. */
11206 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11207 if ((ifthen_state & 0xf) == 0)
11208 ifthen_state = 0;
11209 }
11210
11211 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11212 mapping symbol. */
11213
11214 static int
11215 is_mapping_symbol (struct disassemble_info *info, int n,
11216 enum map_type *map_type)
11217 {
11218 const char *name;
11219
11220 name = bfd_asymbol_name (info->symtab[n]);
11221 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11222 && (name[2] == 0 || name[2] == '.'))
11223 {
11224 *map_type = ((name[1] == 'a') ? MAP_ARM
11225 : (name[1] == 't') ? MAP_THUMB
11226 : MAP_DATA);
11227 return TRUE;
11228 }
11229
11230 return FALSE;
11231 }
11232
11233 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11234 Returns nonzero if *MAP_TYPE was set. */
11235
11236 static int
11237 get_map_sym_type (struct disassemble_info *info,
11238 int n,
11239 enum map_type *map_type)
11240 {
11241 /* If the symbol is in a different section, ignore it. */
11242 if (info->section != NULL && info->section != info->symtab[n]->section)
11243 return FALSE;
11244
11245 return is_mapping_symbol (info, n, map_type);
11246 }
11247
11248 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
11249 Returns nonzero if *MAP_TYPE was set. */
11250
11251 static int
11252 get_sym_code_type (struct disassemble_info *info,
11253 int n,
11254 enum map_type *map_type)
11255 {
11256 elf_symbol_type *es;
11257 unsigned int type;
11258
11259 /* If the symbol is in a different section, ignore it. */
11260 if (info->section != NULL && info->section != info->symtab[n]->section)
11261 return FALSE;
11262
11263 es = *(elf_symbol_type **)(info->symtab + n);
11264 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11265
11266 /* If the symbol has function type then use that. */
11267 if (type == STT_FUNC || type == STT_GNU_IFUNC)
11268 {
11269 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11270 == ST_BRANCH_TO_THUMB)
11271 *map_type = MAP_THUMB;
11272 else
11273 *map_type = MAP_ARM;
11274 return TRUE;
11275 }
11276
11277 return FALSE;
11278 }
11279
11280 /* Search the mapping symbol state for instruction at pc. This is only
11281 applicable for elf target.
11282
11283 There is an assumption Here, info->private_data contains the correct AND
11284 up-to-date information about current scan process. The information will be
11285 used to speed this search process.
11286
11287 Return TRUE if the mapping state can be determined, and map_symbol
11288 will be updated accordingly. Otherwise, return FALSE. */
11289
11290 static bfd_boolean
11291 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11292 enum map_type *map_symbol)
11293 {
11294 bfd_vma addr, section_vma = 0;
11295 int n, last_sym = -1;
11296 bfd_boolean found = FALSE;
11297 bfd_boolean can_use_search_opt_p = FALSE;
11298
11299 /* Default to DATA. A text section is required by the ABI to contain an
11300 INSN mapping symbol at the start. A data section has no such
11301 requirement, hence if no mapping symbol is found the section must
11302 contain only data. This however isn't very useful if the user has
11303 fully stripped the binaries. If this is the case use the section
11304 attributes to determine the default. If we have no section default to
11305 INSN as well, as we may be disassembling some raw bytes on a baremetal
11306 HEX file or similar. */
11307 enum map_type type = MAP_DATA;
11308 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11309 type = MAP_ARM;
11310 struct arm_private_data *private_data;
11311
11312 if (info->private_data == NULL
11313 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11314 return FALSE;
11315
11316 private_data = info->private_data;
11317
11318 /* First, look for mapping symbols. */
11319 if (info->symtab_size != 0)
11320 {
11321 if (pc <= private_data->last_mapping_addr)
11322 private_data->last_mapping_sym = -1;
11323
11324 /* Start scanning at the start of the function, or wherever
11325 we finished last time. */
11326 n = info->symtab_pos + 1;
11327
11328 /* If the last stop offset is different from the current one it means we
11329 are disassembling a different glob of bytes. As such the optimization
11330 would not be safe and we should start over. */
11331 can_use_search_opt_p
11332 = private_data->last_mapping_sym >= 0
11333 && info->stop_offset == private_data->last_stop_offset;
11334
11335 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11336 n = private_data->last_mapping_sym;
11337
11338 /* Look down while we haven't passed the location being disassembled.
11339 The reason for this is that there's no defined order between a symbol
11340 and an mapping symbol that may be at the same address. We may have to
11341 look at least one position ahead. */
11342 for (; n < info->symtab_size; n++)
11343 {
11344 addr = bfd_asymbol_value (info->symtab[n]);
11345 if (addr > pc)
11346 break;
11347 if (get_map_sym_type (info, n, &type))
11348 {
11349 last_sym = n;
11350 found = TRUE;
11351 }
11352 }
11353
11354 if (!found)
11355 {
11356 n = info->symtab_pos;
11357 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11358 n = private_data->last_mapping_sym;
11359
11360 /* No mapping symbol found at this address. Look backwards
11361 for a preceeding one, but don't go pass the section start
11362 otherwise a data section with no mapping symbol can pick up
11363 a text mapping symbol of a preceeding section. The documentation
11364 says section can be NULL, in which case we will seek up all the
11365 way to the top. */
11366 if (info->section)
11367 section_vma = info->section->vma;
11368
11369 for (; n >= 0; n--)
11370 {
11371 addr = bfd_asymbol_value (info->symtab[n]);
11372 if (addr < section_vma)
11373 break;
11374
11375 if (get_map_sym_type (info, n, &type))
11376 {
11377 last_sym = n;
11378 found = TRUE;
11379 break;
11380 }
11381 }
11382 }
11383 }
11384
11385 /* If no mapping symbol was found, try looking up without a mapping
11386 symbol. This is done by walking up from the current PC to the nearest
11387 symbol. We don't actually have to loop here since symtab_pos will
11388 contain the nearest symbol already. */
11389 if (!found)
11390 {
11391 n = info->symtab_pos;
11392 if (n >= 0 && get_sym_code_type (info, n, &type))
11393 {
11394 last_sym = n;
11395 found = TRUE;
11396 }
11397 }
11398
11399 private_data->last_mapping_sym = last_sym;
11400 private_data->last_type = type;
11401 private_data->last_stop_offset = info->stop_offset;
11402
11403 *map_symbol = type;
11404 return found;
11405 }
11406
11407 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11408 of the supplied arm_feature_set structure with bitmasks indicating
11409 the supported base architectures and coprocessor extensions.
11410
11411 FIXME: This could more efficiently implemented as a constant array,
11412 although it would also be less robust. */
11413
11414 static void
11415 select_arm_features (unsigned long mach,
11416 arm_feature_set * features)
11417 {
11418 arm_feature_set arch_fset;
11419 const arm_feature_set fpu_any = FPU_ANY;
11420
11421 #undef ARM_SET_FEATURES
11422 #define ARM_SET_FEATURES(FSET) \
11423 { \
11424 const arm_feature_set fset = FSET; \
11425 arch_fset = fset; \
11426 }
11427
11428 /* When several architecture versions share the same bfd_mach_arm_XXX value
11429 the most featureful is chosen. */
11430 switch (mach)
11431 {
11432 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11433 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11434 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11435 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11436 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11437 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11438 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11439 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11440 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11441 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
11442 case bfd_mach_arm_ep9312:
11443 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11444 ARM_CEXT_MAVERICK | FPU_MAVERICK));
11445 break;
11446 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11447 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11448 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11449 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11450 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11451 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11452 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11453 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11454 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11455 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11456 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11457 case bfd_mach_arm_8:
11458 {
11459 /* Add bits for extensions that Armv8.5-A recognizes. */
11460 arm_feature_set armv8_5_ext_fset
11461 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
11462 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
11463 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
11464 break;
11465 }
11466 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
11467 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
11468 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
11469 case bfd_mach_arm_8_1M_MAIN:
11470 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
11471 force_thumb = 1;
11472 break;
11473 /* If the machine type is unknown allow all architecture types and all
11474 extensions. */
11475 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
11476 default:
11477 abort ();
11478 }
11479 #undef ARM_SET_FEATURES
11480
11481 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11482 and thus on bfd_mach_arm_XXX value. Therefore for a given
11483 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11484 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
11485 }
11486
11487
11488 /* NOTE: There are no checks in these routines that
11489 the relevant number of data bytes exist. */
11490
11491 static int
11492 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
11493 {
11494 unsigned char b[4];
11495 long given;
11496 int status;
11497 int is_thumb = FALSE;
11498 int is_data = FALSE;
11499 int little_code;
11500 unsigned int size = 4;
11501 void (*printer) (bfd_vma, struct disassemble_info *, long);
11502 bfd_boolean found = FALSE;
11503 struct arm_private_data *private_data;
11504
11505 if (info->disassembler_options)
11506 {
11507 parse_arm_disassembler_options (info->disassembler_options);
11508
11509 /* To avoid repeated parsing of these options, we remove them here. */
11510 info->disassembler_options = NULL;
11511 }
11512
11513 /* PR 10288: Control which instructions will be disassembled. */
11514 if (info->private_data == NULL)
11515 {
11516 static struct arm_private_data private;
11517
11518 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
11519 /* If the user did not use the -m command line switch then default to
11520 disassembling all types of ARM instruction.
11521
11522 The info->mach value has to be ignored as this will be based on
11523 the default archictecture for the target and/or hints in the notes
11524 section, but it will never be greater than the current largest arm
11525 machine value (iWMMXt2), which is only equivalent to the V5TE
11526 architecture. ARM architectures have advanced beyond the machine
11527 value encoding, and these newer architectures would be ignored if
11528 the machine value was used.
11529
11530 Ie the -m switch is used to restrict which instructions will be
11531 disassembled. If it is necessary to use the -m switch to tell
11532 objdump that an ARM binary is being disassembled, eg because the
11533 input is a raw binary file, but it is also desired to disassemble
11534 all ARM instructions then use "-marm". This will select the
11535 "unknown" arm architecture which is compatible with any ARM
11536 instruction. */
11537 info->mach = bfd_mach_arm_unknown;
11538
11539 /* Compute the architecture bitmask from the machine number.
11540 Note: This assumes that the machine number will not change
11541 during disassembly.... */
11542 select_arm_features (info->mach, & private.features);
11543
11544 private.last_mapping_sym = -1;
11545 private.last_mapping_addr = 0;
11546 private.last_stop_offset = 0;
11547
11548 info->private_data = & private;
11549 }
11550
11551 private_data = info->private_data;
11552
11553 /* Decide if our code is going to be little-endian, despite what the
11554 function argument might say. */
11555 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
11556
11557 /* For ELF, consult the symbol table to determine what kind of code
11558 or data we have. */
11559 if (info->symtab_size != 0
11560 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
11561 {
11562 bfd_vma addr;
11563 int n;
11564 int last_sym = -1;
11565 enum map_type type = MAP_ARM;
11566
11567 found = mapping_symbol_for_insn (pc, info, &type);
11568 last_sym = private_data->last_mapping_sym;
11569
11570 is_thumb = (private_data->last_type == MAP_THUMB);
11571 is_data = (private_data->last_type == MAP_DATA);
11572
11573 /* Look a little bit ahead to see if we should print out
11574 two or four bytes of data. If there's a symbol,
11575 mapping or otherwise, after two bytes then don't
11576 print more. */
11577 if (is_data)
11578 {
11579 size = 4 - (pc & 3);
11580 for (n = last_sym + 1; n < info->symtab_size; n++)
11581 {
11582 addr = bfd_asymbol_value (info->symtab[n]);
11583 if (addr > pc
11584 && (info->section == NULL
11585 || info->section == info->symtab[n]->section))
11586 {
11587 if (addr - pc < size)
11588 size = addr - pc;
11589 break;
11590 }
11591 }
11592 /* If the next symbol is after three bytes, we need to
11593 print only part of the data, so that we can use either
11594 .byte or .short. */
11595 if (size == 3)
11596 size = (pc & 1) ? 1 : 2;
11597 }
11598 }
11599
11600 if (info->symbols != NULL)
11601 {
11602 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
11603 {
11604 coff_symbol_type * cs;
11605
11606 cs = coffsymbol (*info->symbols);
11607 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
11608 || cs->native->u.syment.n_sclass == C_THUMBSTAT
11609 || cs->native->u.syment.n_sclass == C_THUMBLABEL
11610 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
11611 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
11612 }
11613 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
11614 && !found)
11615 {
11616 /* If no mapping symbol has been found then fall back to the type
11617 of the function symbol. */
11618 elf_symbol_type * es;
11619 unsigned int type;
11620
11621 es = *(elf_symbol_type **)(info->symbols);
11622 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11623
11624 is_thumb =
11625 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11626 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
11627 }
11628 else if (bfd_asymbol_flavour (*info->symbols)
11629 == bfd_target_mach_o_flavour)
11630 {
11631 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
11632
11633 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
11634 }
11635 }
11636
11637 if (force_thumb)
11638 is_thumb = TRUE;
11639
11640 if (is_data)
11641 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11642 else
11643 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11644
11645 info->bytes_per_line = 4;
11646
11647 /* PR 10263: Disassemble data if requested to do so by the user. */
11648 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
11649 {
11650 int i;
11651
11652 /* Size was already set above. */
11653 info->bytes_per_chunk = size;
11654 printer = print_insn_data;
11655
11656 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
11657 given = 0;
11658 if (little)
11659 for (i = size - 1; i >= 0; i--)
11660 given = b[i] | (given << 8);
11661 else
11662 for (i = 0; i < (int) size; i++)
11663 given = b[i] | (given << 8);
11664 }
11665 else if (!is_thumb)
11666 {
11667 /* In ARM mode endianness is a straightforward issue: the instruction
11668 is four bytes long and is either ordered 0123 or 3210. */
11669 printer = print_insn_arm;
11670 info->bytes_per_chunk = 4;
11671 size = 4;
11672
11673 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
11674 if (little_code)
11675 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
11676 else
11677 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
11678 }
11679 else
11680 {
11681 /* In Thumb mode we have the additional wrinkle of two
11682 instruction lengths. Fortunately, the bits that determine
11683 the length of the current instruction are always to be found
11684 in the first two bytes. */
11685 printer = print_insn_thumb16;
11686 info->bytes_per_chunk = 2;
11687 size = 2;
11688
11689 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
11690 if (little_code)
11691 given = (b[0]) | (b[1] << 8);
11692 else
11693 given = (b[1]) | (b[0] << 8);
11694
11695 if (!status)
11696 {
11697 /* These bit patterns signal a four-byte Thumb
11698 instruction. */
11699 if ((given & 0xF800) == 0xF800
11700 || (given & 0xF800) == 0xF000
11701 || (given & 0xF800) == 0xE800)
11702 {
11703 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
11704 if (little_code)
11705 given = (b[0]) | (b[1] << 8) | (given << 16);
11706 else
11707 given = (b[1]) | (b[0] << 8) | (given << 16);
11708
11709 printer = print_insn_thumb32;
11710 size = 4;
11711 }
11712 }
11713
11714 if (ifthen_address != pc)
11715 find_ifthen_state (pc, info, little_code);
11716
11717 if (ifthen_state)
11718 {
11719 if ((ifthen_state & 0xf) == 0x8)
11720 ifthen_next_state = 0;
11721 else
11722 ifthen_next_state = (ifthen_state & 0xe0)
11723 | ((ifthen_state & 0xf) << 1);
11724 }
11725 }
11726
11727 if (status)
11728 {
11729 info->memory_error_func (status, pc, info);
11730 return -1;
11731 }
11732 if (info->flags & INSN_HAS_RELOC)
11733 /* If the instruction has a reloc associated with it, then
11734 the offset field in the instruction will actually be the
11735 addend for the reloc. (We are using REL type relocs).
11736 In such cases, we can ignore the pc when computing
11737 addresses, since the addend is not currently pc-relative. */
11738 pc = 0;
11739
11740 printer (pc, info, given);
11741
11742 if (is_thumb)
11743 {
11744 ifthen_state = ifthen_next_state;
11745 ifthen_address += size;
11746 }
11747 return size;
11748 }
11749
11750 int
11751 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
11752 {
11753 /* Detect BE8-ness and record it in the disassembler info. */
11754 if (info->flavour == bfd_target_elf_flavour
11755 && info->section != NULL
11756 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
11757 info->endian_code = BFD_ENDIAN_LITTLE;
11758
11759 return print_insn (pc, info, FALSE);
11760 }
11761
11762 int
11763 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
11764 {
11765 return print_insn (pc, info, TRUE);
11766 }
11767
11768 const disasm_options_and_args_t *
11769 disassembler_options_arm (void)
11770 {
11771 static disasm_options_and_args_t *opts_and_args;
11772
11773 if (opts_and_args == NULL)
11774 {
11775 disasm_options_t *opts;
11776 unsigned int i;
11777
11778 opts_and_args = XNEW (disasm_options_and_args_t);
11779 opts_and_args->args = NULL;
11780
11781 opts = &opts_and_args->options;
11782 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11783 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11784 opts->arg = NULL;
11785 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11786 {
11787 opts->name[i] = regnames[i].name;
11788 if (regnames[i].description != NULL)
11789 opts->description[i] = _(regnames[i].description);
11790 else
11791 opts->description[i] = NULL;
11792 }
11793 /* The array we return must be NULL terminated. */
11794 opts->name[i] = NULL;
11795 opts->description[i] = NULL;
11796 }
11797
11798 return opts_and_args;
11799 }
11800
11801 void
11802 print_arm_disassembler_options (FILE *stream)
11803 {
11804 unsigned int i, max_len = 0;
11805 fprintf (stream, _("\n\
11806 The following ARM specific disassembler options are supported for use with\n\
11807 the -M switch:\n"));
11808
11809 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11810 {
11811 unsigned int len = strlen (regnames[i].name);
11812 if (max_len < len)
11813 max_len = len;
11814 }
11815
11816 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
11817 fprintf (stream, " %s%*c %s\n",
11818 regnames[i].name,
11819 (int)(max_len - strlen (regnames[i].name)), ' ',
11820 _(regnames[i].description));
11821 }
GDB Binutils - Deliverables
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