1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* FIXME: Belongs in global header. */
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
47 /* Cached mapping symbol state. */
55 struct arm_private_data
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features
;
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type
;
63 /* Tracking symbol table information */
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset
;
68 bfd_vma last_mapping_addr
;
121 MVE_VSTRB_SCATTER_T1
,
122 MVE_VSTRH_SCATTER_T2
,
123 MVE_VSTRW_SCATTER_T3
,
124 MVE_VSTRD_SCATTER_T4
,
125 MVE_VSTRW_SCATTER_T5
,
126 MVE_VSTRD_SCATTER_T6
,
128 MVE_VCVT_BETWEEN_FP_INT
,
130 MVE_VCVT_FROM_FP_TO_INT
,
133 MVE_VMOV_GP_TO_VEC_LANE
,
136 MVE_VMOV2_VEC_LANE_TO_GP
,
137 MVE_VMOV2_GP_TO_VEC_LANE
,
138 MVE_VMOV_VEC_LANE_TO_GP
,
296 enum mve_unpredictable
298 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
300 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
302 UNPRED_R13
, /* Unpredictable because r13 (sp) or
304 UNPRED_R15
, /* Unpredictable because r15 (pc) is used. */
305 UNPRED_Q_GT_4
, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6
, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB
, /* Unpredictable becase gp reg = r13
311 UNPRED_Q_REGS_EQUAL
, /* Unpredictable because vector registers are
313 UNPRED_OS
, /* Unpredictable because offset scaled == 1. */
314 UNPRED_GP_REGS_EQUAL
, /* Unpredictable because gp registers are the
316 UNPRED_Q_REGS_EQ_AND_SIZE_1
, /* Unpredictable because q regs equal and
318 UNPRED_Q_REGS_EQ_AND_SIZE_2
, /* Unpredictable because q regs equal and
320 UNPRED_NONE
/* No unpredictable behavior. */
325 UNDEF_SIZE
, /* undefined size. */
326 UNDEF_SIZE_0
, /* undefined because size == 0. */
327 UNDEF_SIZE_2
, /* undefined because size == 2. */
328 UNDEF_SIZE_3
, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1
, /* undefined because size <= 1. */
330 UNDEF_SIZE_NOT_0
, /* undefined because size != 0. */
331 UNDEF_SIZE_NOT_2
, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3
, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0
, /* undefined because U == 0 and
335 UNDEF_NOT_UNS_SIZE_1
, /* undefined because U == 0 and
337 UNDEF_NOT_UNSIGNED
, /* undefined because U == 0. */
338 UNDEF_VCVT_IMM6
, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6
, /* fsi = 0 and 32 >= imm6 <= 47. */
340 UNDEF_BAD_OP1_OP2
, /* undefined with op2 = 2 and
342 UNDEF_BAD_U_OP1_OP2
, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE
, /* undefined because op == 0 and cmode
346 UNDEF_XCHG_UNS
, /* undefined because X == 1 and U == 1. */
347 UNDEF_NONE
/* no undefined behavior. */
352 arm_feature_set arch
; /* Architecture defining this insn. */
353 unsigned long value
; /* If arch is 0 then value is a sentinel. */
354 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
355 const char * assembler
; /* How to disassemble this insn. */
362 arm_feature_set arch
; /* Architecture defining this insn. */
363 enum mve_instructions mve_op
; /* Specific mve instruction for faster
365 unsigned long value
; /* If arch is 0 then value is a sentinel. */
366 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
367 const char * assembler
; /* How to disassemble this insn. */
377 /* Shared (between Arm and Thumb mode) opcode. */
380 enum isa isa
; /* Execution mode instruction availability. */
381 arm_feature_set arch
; /* Architecture defining this insn. */
382 unsigned long value
; /* If arch is 0 then value is a sentinel. */
383 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
384 const char * assembler
; /* How to disassemble this insn. */
389 arm_feature_set arch
; /* Architecture defining this insn. */
390 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
391 const char *assembler
; /* How to disassemble this insn. */
394 /* print_insn_coprocessor recognizes the following format control codes:
398 %c print condition code (always bits 28-31 in ARM mode)
399 %q print shifter argument
400 %u print condition code (unconditional in ARM mode,
401 UNPREDICTABLE if not AL in Thumb)
402 %A print address for ldc/stc/ldf/stf instruction
403 %B print vstm/vldm register list
404 %C print vscclrm register list
405 %I print cirrus signed shift immediate: bits 0..3|4..6
406 %J print register for VLDR instruction
407 %K print address for VLDR instruction
408 %F print the COUNT field of a LFM/SFM instruction.
409 %P print floating point precision in arithmetic insn
410 %Q print floating point precision in ldf/stf insn
411 %R print floating point rounding mode
413 %<bitfield>c print as a condition code (for vsel)
414 %<bitfield>r print as an ARM register
415 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
416 %<bitfield>ru as %<>r but each u register must be unique.
417 %<bitfield>d print the bitfield in decimal
418 %<bitfield>k print immediate for VFPv3 conversion instruction
419 %<bitfield>x print the bitfield in hex
420 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
421 %<bitfield>f print a floating point constant if >7 else a
422 floating point register
423 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
424 %<bitfield>g print as an iWMMXt 64-bit register
425 %<bitfield>G print as an iWMMXt general purpose or control register
426 %<bitfield>D print as a NEON D register
427 %<bitfield>Q print as a NEON Q register
428 %<bitfield>V print as a NEON D or Q register
429 %<bitfield>E print a quarter-float immediate value
431 %y<code> print a single precision VFP reg.
432 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
433 %z<code> print a double precision VFP reg
434 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
436 %<bitfield>'c print specified char iff bitfield is all ones
437 %<bitfield>`c print specified char iff bitfield is all zeroes
438 %<bitfield>?ab... select from array of values in big endian order
440 %L print as an iWMMXt N/M width field.
441 %Z print the Immediate of a WSHUFH instruction.
442 %l like 'A' except use byte offsets for 'B' & 'H'
444 %i print 5-bit immediate in bits 8,3..0
446 %r print register offset address for wldt/wstr instruction. */
448 enum opcode_sentinel_enum
450 SENTINEL_IWMMXT_START
= 1,
452 SENTINEL_GENERIC_START
455 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
456 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
457 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
458 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
460 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
462 static const struct sopcode32 coprocessor_opcodes
[] =
464 /* XScale instructions. */
465 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
466 0x0e200010, 0x0fff0ff0,
467 "mia%c\tacc0, %0-3r, %12-15r"},
468 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
469 0x0e280010, 0x0fff0ff0,
470 "miaph%c\tacc0, %0-3r, %12-15r"},
471 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
472 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
473 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
474 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
475 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
476 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
478 /* Intel Wireless MMX technology instructions. */
479 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
480 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
481 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
482 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
483 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
484 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
485 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
486 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
487 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
488 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
489 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
490 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
491 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
492 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
493 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
494 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
495 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
496 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
497 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
498 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
499 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
500 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
501 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
502 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
503 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
504 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
505 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
506 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
507 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
508 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
509 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
510 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
511 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
512 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
513 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
514 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
515 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
516 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
517 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
518 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
519 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
520 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
521 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
522 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
523 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
524 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
525 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
526 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
527 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
528 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
529 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
530 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
531 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
532 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
533 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
534 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
535 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
536 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
537 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
538 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
539 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
540 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
541 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
542 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
543 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
544 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
545 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
546 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
547 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
548 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
549 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
550 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
551 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
552 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
553 0x0e800120, 0x0f800ff0,
554 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
555 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
556 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
557 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
558 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
559 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
560 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
561 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
562 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
563 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
564 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
565 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
566 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
567 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
568 0x0e8000a0, 0x0f800ff0,
569 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
570 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
571 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
572 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
573 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
574 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
575 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
576 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
577 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
578 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
579 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
580 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
581 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
582 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
583 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
584 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
585 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
586 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
587 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
588 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
589 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
590 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
591 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
592 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
593 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
594 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
595 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
596 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
597 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
598 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
599 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
600 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
601 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
602 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
603 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
604 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
605 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
606 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
607 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
608 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
609 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
610 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
611 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
612 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
613 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
614 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
615 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
616 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
617 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
618 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
619 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
620 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
621 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
622 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
623 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
624 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
625 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
626 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
627 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
628 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
629 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
630 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
631 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
632 {ANY
, ARM_FEATURE_CORE_LOW (0),
633 SENTINEL_IWMMXT_END
, 0, "" },
635 /* Floating point coprocessor (FPA) instructions. */
636 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
637 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
638 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
639 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
640 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
641 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
642 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
643 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
644 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
645 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
646 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
647 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
648 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
649 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
650 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
651 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
652 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
653 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
654 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
655 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
656 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
657 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
658 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
659 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
660 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
661 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
662 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
663 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
664 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
665 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
666 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
667 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
668 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
669 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
670 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
671 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
672 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
673 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
674 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
675 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
676 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
677 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
678 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
679 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
680 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
681 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
682 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
683 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
684 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
685 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
686 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
687 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
688 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
689 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
690 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
691 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
692 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
693 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
694 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
695 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
696 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
697 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
698 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
699 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
700 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
701 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
702 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
703 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
704 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
705 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
706 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
707 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
708 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
709 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
710 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
711 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
712 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
713 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
714 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
715 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
716 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
717 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
718 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
719 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
720 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
721 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
723 /* Armv8.1-M Mainline instructions. */
724 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
725 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
726 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
727 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
729 /* ARMv8-M Mainline Security Extensions instructions. */
730 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
731 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
732 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
733 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
735 /* Register load/store. */
736 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
737 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
738 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
739 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
740 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
741 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
742 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
743 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
744 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
745 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
746 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
747 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
748 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
749 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
750 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
751 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
752 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
753 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
754 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
755 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
756 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
757 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
758 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
759 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
760 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
761 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
762 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
763 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
764 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
765 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
766 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
767 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
768 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
769 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
770 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
771 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
773 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
774 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
775 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
776 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
777 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
778 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
779 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
780 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
782 /* Data transfer between ARM and NEON registers. */
783 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
784 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
785 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
786 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
787 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
788 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
789 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
790 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
791 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
792 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
793 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
794 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
795 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
796 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
797 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
798 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
799 /* Half-precision conversion instructions. */
800 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
801 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
802 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
803 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
804 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
805 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
806 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
807 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
809 /* Floating point coprocessor (VFP) instructions. */
810 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
811 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
812 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_MVE
),
813 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
814 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
815 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
816 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
817 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
818 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
819 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
820 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
821 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
822 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
823 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
824 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
825 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
826 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
827 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
828 {ANY
, ARM_FEATURE_COPROC (FPU_MVE
),
829 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
830 {ANY
, ARM_FEATURE_COPROC (FPU_MVE
),
831 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
832 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
833 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
834 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
835 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
836 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
837 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
838 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
839 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
840 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_MVE
),
841 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
842 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
843 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
844 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
845 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
846 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
847 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
848 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
849 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
850 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
851 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
852 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
853 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
854 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
855 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
856 {ANY
, ARM_FEATURE_COPROC (FPU_MVE
),
857 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
858 {ANY
, ARM_FEATURE_COPROC (FPU_MVE
),
859 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
860 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
861 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
862 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
863 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
864 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
865 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
866 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
867 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
868 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
869 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
870 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
871 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
872 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
873 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
874 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
875 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
876 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
877 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
878 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
879 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
880 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
881 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
882 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
883 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
884 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
885 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
886 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
887 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
888 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
889 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
890 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
891 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
892 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
893 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
894 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
895 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
896 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
897 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
898 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
899 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
900 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
901 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
902 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
903 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
904 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
905 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
906 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
907 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
908 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
909 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
910 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
911 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
912 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
913 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
914 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
915 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
916 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
917 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
918 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
919 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
920 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
921 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
922 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
923 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
924 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
925 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
926 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
927 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
928 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
929 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
930 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
931 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
932 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
933 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
934 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
935 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
936 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
937 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
938 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
939 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
940 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
941 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
942 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
943 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
944 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
945 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
946 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
947 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
948 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
949 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
950 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
951 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
952 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
953 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
954 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
955 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
956 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
957 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
958 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
959 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
960 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
961 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
962 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
963 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
964 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
965 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
966 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
967 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
969 /* Cirrus coprocessor instructions. */
970 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
971 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
972 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
973 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
974 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
975 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
976 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
977 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
978 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
979 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
980 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
981 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
982 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
983 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
984 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
985 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
986 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
987 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
988 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
989 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
990 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
991 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
992 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
993 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
994 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
995 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
996 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
997 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
998 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
999 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1000 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1001 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1002 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1003 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
1004 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1005 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
1006 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1007 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
1008 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1009 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
1010 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1011 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
1012 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1013 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
1014 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1015 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
1016 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1017 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
1018 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1019 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
1020 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1021 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
1022 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1023 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
1024 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1025 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
1026 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1027 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
1028 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1029 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
1030 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1031 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
1032 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1033 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
1034 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1035 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
1036 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1037 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
1038 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1039 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
1040 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1041 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
1042 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1043 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
1044 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1045 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
1046 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1047 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
1048 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1049 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
1050 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1051 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
1052 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1053 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
1054 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1055 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
1056 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1057 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1058 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1059 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1060 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1061 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1062 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1063 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1064 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1065 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1066 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1067 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1068 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1069 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1070 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1071 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1072 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1073 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1074 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1075 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1076 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1077 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1078 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1079 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1080 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1081 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1082 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1083 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1084 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1085 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1086 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1087 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1088 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1089 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1090 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1091 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1092 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1093 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1094 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1095 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1096 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1097 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1098 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1099 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1100 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1101 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1102 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1103 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1104 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1105 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1106 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1107 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1108 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1109 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1110 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1111 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1112 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1113 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1114 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1115 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1116 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1117 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1118 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1119 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1120 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1121 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1122 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1123 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1124 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1125 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1126 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1127 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1128 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1129 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1130 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1131 0x0e000600, 0x0ff00f10,
1132 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1133 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1134 0x0e100600, 0x0ff00f10,
1135 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1136 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1137 0x0e200600, 0x0ff00f10,
1138 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1139 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1140 0x0e300600, 0x0ff00f10,
1141 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1143 /* VFP Fused multiply add instructions. */
1144 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1145 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1146 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1147 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1148 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1149 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1150 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1151 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1152 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1153 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1154 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1155 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1156 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1157 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1158 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1159 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1162 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1163 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1164 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1165 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1166 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1167 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1168 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1169 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1170 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1171 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1172 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1173 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1174 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1175 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1176 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1177 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1178 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1179 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1180 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1181 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1182 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1183 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1184 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1185 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1187 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
1188 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1189 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1190 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1191 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1192 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1193 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1194 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1195 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1196 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1197 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1198 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1199 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1200 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1201 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1202 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1203 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1204 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1205 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1206 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1207 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1208 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1210 /* Dot Product instructions in the space of coprocessor 13. */
1211 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1212 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1213 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1214 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1216 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1217 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1218 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1219 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1220 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1221 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1222 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1223 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1224 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1225 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1226 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1227 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1228 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1229 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1230 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1231 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1232 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1234 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1235 cp_num: bit <11:8> == 0b1001.
1236 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1237 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1238 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1239 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1240 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1241 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1242 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1243 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1244 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1245 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1246 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1247 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1248 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1249 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1250 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1251 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1252 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1253 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1254 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1255 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1256 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1257 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1258 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1259 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1260 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1261 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1262 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1263 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1264 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1265 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1266 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1267 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1268 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1269 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1270 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1271 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1272 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1273 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1274 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1275 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1276 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1277 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1278 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1279 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1280 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1281 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1282 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1283 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1284 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1285 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1286 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1287 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1288 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1289 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1290 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1291 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1292 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1293 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1294 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1295 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1296 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1297 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1298 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1299 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1300 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1301 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1302 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1303 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1304 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1305 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1306 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1308 /* ARMv8.3 javascript conversion instruction. */
1309 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1310 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1312 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1315 /* Generic coprocessor instructions. These are only matched if a more specific
1316 SIMD or co-processor instruction does not match first. */
1318 static const struct sopcode32 generic_coprocessor_opcodes
[] =
1320 /* Generic coprocessor instructions. */
1321 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1322 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1323 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1324 0x0c500000, 0x0ff00000,
1325 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1326 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1327 0x0e000000, 0x0f000010,
1328 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1329 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1330 0x0e10f010, 0x0f10f010,
1331 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1332 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1333 0x0e100010, 0x0f100010,
1334 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1335 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1336 0x0e000010, 0x0f100010,
1337 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1338 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1339 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1340 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1341 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1343 /* V6 coprocessor instructions. */
1344 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1345 0xfc500000, 0xfff00000,
1346 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1347 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1348 0xfc400000, 0xfff00000,
1349 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1351 /* V5 coprocessor instructions. */
1352 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1353 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1354 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1355 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1356 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1357 0xfe000000, 0xff000010,
1358 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1359 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1360 0xfe000010, 0xff100010,
1361 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1362 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1363 0xfe100010, 0xff100010,
1364 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1366 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1369 /* Neon opcode table: This does not encode the top byte -- that is
1370 checked by the print_insn_neon routine, as it depends on whether we are
1371 doing thumb32 or arm32 disassembly. */
1373 /* print_insn_neon recognizes the following format control codes:
1377 %c print condition code
1378 %u print condition code (unconditional in ARM mode,
1379 UNPREDICTABLE if not AL in Thumb)
1380 %A print v{st,ld}[1234] operands
1381 %B print v{st,ld}[1234] any one operands
1382 %C print v{st,ld}[1234] single->all operands
1384 %E print vmov, vmvn, vorr, vbic encoded constant
1385 %F print vtbl,vtbx register list
1387 %<bitfield>r print as an ARM register
1388 %<bitfield>d print the bitfield in decimal
1389 %<bitfield>e print the 2^N - bitfield in decimal
1390 %<bitfield>D print as a NEON D register
1391 %<bitfield>Q print as a NEON Q register
1392 %<bitfield>R print as a NEON D or Q register
1393 %<bitfield>Sn print byte scaled width limited by n
1394 %<bitfield>Tn print short scaled width limited by n
1395 %<bitfield>Un print long scaled width limited by n
1397 %<bitfield>'c print specified char iff bitfield is all ones
1398 %<bitfield>`c print specified char iff bitfield is all zeroes
1399 %<bitfield>?ab... select from array of values in big endian order. */
1401 static const struct opcode32 neon_opcodes
[] =
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1405 0xf2b00840, 0xffb00850,
1406 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1408 0xf2b00000, 0xffb00810,
1409 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1411 /* Data transfer between ARM and NEON registers. */
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1413 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1415 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1417 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1419 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1421 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1423 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1425 /* Move data element to all lanes. */
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1427 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1429 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1431 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1435 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1437 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1439 /* Half-precision conversions. */
1440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1441 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1443 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1445 /* NEON fused multiply add instructions. */
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1447 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1448 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1449 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1451 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1452 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1453 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1455 /* Two registers, miscellaneous. */
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1457 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1459 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1461 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1463 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1464 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1465 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1466 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1467 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1468 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1469 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1470 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1471 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1472 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1473 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1474 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1475 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1476 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1477 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1479 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1481 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1483 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1485 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1487 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1489 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1491 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1493 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1495 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1497 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1499 0xf3b20300, 0xffb30fd0,
1500 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1502 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1503 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1504 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1506 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1507 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1508 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1510 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1512 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1514 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1516 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1518 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1520 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1522 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1524 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1526 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1528 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1530 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1532 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1534 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1536 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1538 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1540 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1542 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1543 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1544 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1546 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1548 0xf3bb0600, 0xffbf0e10,
1549 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1551 0xf3b70600, 0xffbf0e10,
1552 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1554 /* Three registers of the same length. */
1555 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1556 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1557 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1558 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1559 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1560 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1561 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1562 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1563 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1564 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1565 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1566 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1567 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1568 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1570 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1571 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1572 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1574 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1576 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1578 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1580 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1582 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1584 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1586 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1588 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1590 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1592 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1594 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1596 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1598 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1599 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1600 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1602 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1603 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1604 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1606 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1608 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1610 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1612 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1614 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1615 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1616 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1618 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1620 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1622 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1623 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1624 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1626 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1628 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1630 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1632 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1634 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1635 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1636 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1638 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1640 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1642 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1644 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1646 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1647 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1648 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1650 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1652 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1654 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1655 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1656 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1658 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1659 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1660 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1662 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1663 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1664 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1666 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1668 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1670 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1672 0xf2000b00, 0xff800f10,
1673 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1675 0xf2000b10, 0xff800f10,
1676 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1678 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1680 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1682 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1684 0xf3000b00, 0xff800f10,
1685 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1687 0xf2000000, 0xfe800f10,
1688 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1690 0xf2000010, 0xfe800f10,
1691 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1693 0xf2000100, 0xfe800f10,
1694 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1696 0xf2000200, 0xfe800f10,
1697 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1699 0xf2000210, 0xfe800f10,
1700 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1702 0xf2000300, 0xfe800f10,
1703 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1705 0xf2000310, 0xfe800f10,
1706 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1708 0xf2000400, 0xfe800f10,
1709 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1711 0xf2000410, 0xfe800f10,
1712 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1714 0xf2000500, 0xfe800f10,
1715 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1717 0xf2000510, 0xfe800f10,
1718 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1720 0xf2000600, 0xfe800f10,
1721 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1723 0xf2000610, 0xfe800f10,
1724 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1726 0xf2000700, 0xfe800f10,
1727 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1729 0xf2000710, 0xfe800f10,
1730 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1732 0xf2000910, 0xfe800f10,
1733 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1735 0xf2000a00, 0xfe800f10,
1736 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1738 0xf2000a10, 0xfe800f10,
1739 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1741 0xf3000b10, 0xff800f10,
1742 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1744 0xf3000c10, 0xff800f10,
1745 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1747 /* One register and an immediate value. */
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1749 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1751 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1753 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1755 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1757 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1759 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1761 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1763 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1765 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1767 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1769 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1771 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1773 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1775 /* Two registers and a shift amount. */
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1777 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1779 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1780 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1781 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1782 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1783 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1785 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1787 0xf2880950, 0xfeb80fd0,
1788 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1790 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1792 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1794 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1796 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1798 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1800 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1802 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1804 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1806 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1808 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1810 0xf2900950, 0xfeb00fd0,
1811 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1813 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1815 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1817 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1819 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1821 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1823 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1825 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1827 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1829 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1831 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1833 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1835 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1837 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1839 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1841 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1843 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1845 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1847 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1848 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1849 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1851 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1853 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1854 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1855 0xf2a00950, 0xfea00fd0,
1856 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1858 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1860 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1862 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1864 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1866 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1868 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1870 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1872 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1874 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1876 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1878 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1880 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1882 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1884 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1886 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1888 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1890 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1891 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1892 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1894 0xf2a00e10, 0xfea00e90,
1895 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1896 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1897 0xf2a00c10, 0xfea00e90,
1898 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1900 /* Three registers of different lengths. */
1901 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1902 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1904 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1905 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1906 0xf2800400, 0xff800f50,
1907 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1909 0xf2800600, 0xff800f50,
1910 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1911 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1912 0xf2800900, 0xff800f50,
1913 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1915 0xf2800b00, 0xff800f50,
1916 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1917 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1918 0xf2800d00, 0xff800f50,
1919 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1920 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1921 0xf3800400, 0xff800f50,
1922 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1924 0xf3800600, 0xff800f50,
1925 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1926 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1927 0xf2800000, 0xfe800f50,
1928 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1930 0xf2800100, 0xfe800f50,
1931 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1933 0xf2800200, 0xfe800f50,
1934 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1936 0xf2800300, 0xfe800f50,
1937 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1939 0xf2800500, 0xfe800f50,
1940 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1942 0xf2800700, 0xfe800f50,
1943 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1945 0xf2800800, 0xfe800f50,
1946 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1948 0xf2800a00, 0xfe800f50,
1949 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1951 0xf2800c00, 0xfe800f50,
1952 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1954 /* Two registers and a scalar. */
1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1956 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1958 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1959 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1960 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1962 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1963 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1964 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1965 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1966 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1967 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1968 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1970 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1972 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1973 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1974 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1975 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1976 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1978 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1979 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1980 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1981 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1982 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1984 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1985 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1986 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1987 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1988 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1989 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1990 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1991 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1992 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1993 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1994 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1995 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1996 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1997 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1998 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1999 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2000 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2001 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2002 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2003 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2004 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2005 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2006 0xf2800240, 0xfe800f50,
2007 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2008 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2009 0xf2800640, 0xfe800f50,
2010 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2011 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2012 0xf2800a40, 0xfe800f50,
2013 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2014 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2015 0xf2800e40, 0xff800f50,
2016 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2018 0xf2800f40, 0xff800f50,
2019 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2020 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2021 0xf3800e40, 0xff800f50,
2022 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2024 0xf3800f40, 0xff800f50,
2025 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2028 /* Element and structure load/store. */
2029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2030 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2031 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2032 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2034 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2036 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2037 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2038 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2040 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2042 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2043 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2044 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2046 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2048 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2049 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2050 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2052 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2053 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2054 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2055 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2056 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2057 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2058 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2059 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2060 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2061 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2062 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2063 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2064 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2065 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2066 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2068 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2071 /* mve opcode table. */
2073 /* print_insn_mve recognizes the following format control codes:
2077 %a print '+' or '-' or imm offset in vldr[bhwd] and
2079 %c print condition code
2080 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2081 %u print 'U' (unsigned) or 'S' for various mve instructions
2082 %i print MVE predicate(s) for vpt and vpst
2083 %j print a 5-bit immediate from hw2[14:12,7:6]
2084 %k print 48 if the 7th position bit is set else print 64.
2085 %m print rounding mode for vcvt and vrint
2086 %n print vector comparison code for predicated instruction
2087 %s print size for various vcvt instructions
2088 %v print vector predicate for instruction in predicated
2090 %o print offset scaled for vldr[hwd] and vstr[hwd]
2091 %w print writeback mode for MVE v{st,ld}[24]
2092 %B print v{st,ld}[24] any one operands
2093 %E print vmov, vmvn, vorr, vbic encoded constant
2094 %N print generic index for vmov
2095 %T print bottom ('b') or top ('t') of source register
2096 %X print exchange field in vmla* instructions
2098 %<bitfield>r print as an ARM register
2099 %<bitfield>d print the bitfield in decimal
2100 %<bitfield>A print accumulate or not
2101 %<bitfield>c print bitfield as a condition code
2102 %<bitfield>C print bitfield as an inverted condition code
2103 %<bitfield>Q print as a MVE Q register
2104 %<bitfield>F print as a MVE S register
2105 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2108 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
2109 %<bitfield>s print size for vector predicate & non VMOV instructions
2110 %<bitfield>I print carry flag or not
2111 %<bitfield>i print immediate for vstr/vldr reg +/- imm
2112 %<bitfield>h print high half of 64-bit destination reg
2113 %<bitfield>k print immediate for vector conversion instruction
2114 %<bitfield>l print low half of 64-bit destination reg
2115 %<bitfield>o print rotate value for vcmul
2116 %<bitfield>u print immediate value for vddup/vdwdup
2117 %<bitfield>x print the bitfield in hex.
2120 static const struct mopcode32 mve_opcodes
[] =
2124 {ARM_FEATURE_COPROC (FPU_MVE
),
2126 0xfe310f4d, 0xffbf1fff,
2130 /* Floating point VPT T1. */
2131 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2133 0xee310f00, 0xefb10f50,
2134 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2135 /* Floating point VPT T2. */
2136 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2138 0xee310f40, 0xefb10f50,
2139 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2141 /* Vector VPT T1. */
2142 {ARM_FEATURE_COPROC (FPU_MVE
),
2144 0xfe010f00, 0xff811f51,
2145 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2146 /* Vector VPT T2. */
2147 {ARM_FEATURE_COPROC (FPU_MVE
),
2149 0xfe010f01, 0xff811f51,
2150 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2151 /* Vector VPT T3. */
2152 {ARM_FEATURE_COPROC (FPU_MVE
),
2154 0xfe011f00, 0xff811f50,
2155 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2156 /* Vector VPT T4. */
2157 {ARM_FEATURE_COPROC (FPU_MVE
),
2159 0xfe010f40, 0xff811f70,
2160 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2161 /* Vector VPT T5. */
2162 {ARM_FEATURE_COPROC (FPU_MVE
),
2164 0xfe010f60, 0xff811f70,
2165 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2166 /* Vector VPT T6. */
2167 {ARM_FEATURE_COPROC (FPU_MVE
),
2169 0xfe011f40, 0xff811f50,
2170 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2172 /* Vector VBIC immediate. */
2173 {ARM_FEATURE_COPROC (FPU_MVE
),
2175 0xef800070, 0xefb81070,
2176 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2178 /* Vector VBIC register. */
2179 {ARM_FEATURE_COPROC (FPU_MVE
),
2181 0xef100150, 0xffb11f51,
2182 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2185 {ARM_FEATURE_COPROC (FPU_MVE
),
2187 0xee800f01, 0xefc10f51,
2188 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2190 /* Vector VABD floating point. */
2191 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2193 0xff200d40, 0xffa11f51,
2194 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2197 {ARM_FEATURE_COPROC (FPU_MVE
),
2199 0xef000740, 0xef811f51,
2200 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2202 /* Vector VABS floating point. */
2203 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2205 0xFFB10740, 0xFFB31FD1,
2206 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2208 {ARM_FEATURE_COPROC (FPU_MVE
),
2210 0xffb10340, 0xffb31fd1,
2211 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2213 /* Vector VADD floating point T1. */
2214 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2216 0xef000d40, 0xffa11f51,
2217 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2218 /* Vector VADD floating point T2. */
2219 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2221 0xee300f40, 0xefb11f70,
2222 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2223 /* Vector VADD T1. */
2224 {ARM_FEATURE_COPROC (FPU_MVE
),
2226 0xef000840, 0xff811f51,
2227 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2228 /* Vector VADD T2. */
2229 {ARM_FEATURE_COPROC (FPU_MVE
),
2231 0xee010f40, 0xff811f70,
2232 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2234 /* Vector VADDLV. */
2235 {ARM_FEATURE_COPROC (FPU_MVE
),
2237 0xee890f00, 0xef8f1fd1,
2238 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2241 {ARM_FEATURE_COPROC (FPU_MVE
),
2243 0xeef10f00, 0xeff31fd1,
2244 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2247 {ARM_FEATURE_COPROC (FPU_MVE
),
2249 0xee300f00, 0xffb10f51,
2250 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2253 {ARM_FEATURE_COPROC (FPU_MVE
),
2255 0xef000150, 0xffb11f51,
2256 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2258 /* Vector VBRSR register. */
2259 {ARM_FEATURE_COPROC (FPU_MVE
),
2261 0xfe011e60, 0xff811f70,
2262 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2264 /* Vector VCADD floating point. */
2265 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2267 0xfc800840, 0xfea11f51,
2268 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2271 {ARM_FEATURE_COPROC (FPU_MVE
),
2273 0xfe000f00, 0xff810f51,
2274 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2277 {ARM_FEATURE_COPROC (FPU_MVE
),
2279 0xffb00440, 0xffb31fd1,
2280 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2283 {ARM_FEATURE_COPROC (FPU_MVE
),
2285 0xffb004c0, 0xffb31fd1,
2286 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2289 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2291 0xfc200840, 0xfe211f51,
2292 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2294 /* Vector VCMP floating point T1. */
2295 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2297 0xee310f00, 0xeff1ef50,
2298 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2300 /* Vector VCMP floating point T2. */
2301 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2303 0xee310f40, 0xeff1ef50,
2304 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2306 /* Vector VCMP T1. */
2307 {ARM_FEATURE_COPROC (FPU_MVE
),
2309 0xfe010f00, 0xffc1ff51,
2310 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2311 /* Vector VCMP T2. */
2312 {ARM_FEATURE_COPROC (FPU_MVE
),
2314 0xfe010f01, 0xffc1ff51,
2315 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2316 /* Vector VCMP T3. */
2317 {ARM_FEATURE_COPROC (FPU_MVE
),
2319 0xfe011f00, 0xffc1ff50,
2320 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2321 /* Vector VCMP T4. */
2322 {ARM_FEATURE_COPROC (FPU_MVE
),
2324 0xfe010f40, 0xffc1ff70,
2325 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2326 /* Vector VCMP T5. */
2327 {ARM_FEATURE_COPROC (FPU_MVE
),
2329 0xfe010f60, 0xffc1ff70,
2330 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2331 /* Vector VCMP T6. */
2332 {ARM_FEATURE_COPROC (FPU_MVE
),
2334 0xfe011f40, 0xffc1ff50,
2335 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2338 {ARM_FEATURE_COPROC (FPU_MVE
),
2340 0xeea00b10, 0xffb10f5f,
2341 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2344 {ARM_FEATURE_COPROC (FPU_MVE
),
2346 0xff000150, 0xffd11f51,
2347 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2349 /* Vector VFMA, vector * scalar. */
2350 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2352 0xee310e40, 0xefb11f70,
2353 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2355 /* Vector VFMA floating point. */
2356 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2358 0xef000c50, 0xffa11f51,
2359 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2361 /* Vector VFMS floating point. */
2362 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2364 0xef200c50, 0xffa11f51,
2365 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2367 /* Vector VFMAS, vector * scalar. */
2368 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2369 MVE_VFMAS_FP_SCALAR
,
2370 0xee311e40, 0xefb11f70,
2371 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2373 /* Vector VHADD T1. */
2374 {ARM_FEATURE_COPROC (FPU_MVE
),
2376 0xef000040, 0xef811f51,
2377 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2379 /* Vector VHADD T2. */
2380 {ARM_FEATURE_COPROC (FPU_MVE
),
2382 0xee000f40, 0xef811f70,
2383 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2385 /* Vector VHSUB T1. */
2386 {ARM_FEATURE_COPROC (FPU_MVE
),
2388 0xef000240, 0xef811f51,
2389 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2391 /* Vector VHSUB T2. */
2392 {ARM_FEATURE_COPROC (FPU_MVE
),
2394 0xee001f40, 0xef811f70,
2395 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2398 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2400 0xee300e00, 0xefb10f50,
2401 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2404 {ARM_FEATURE_COPROC (FPU_MVE
),
2406 0xf000e801, 0xffc0ffff,
2407 "vctp%v.%20-21s\t%16-19r"},
2410 {ARM_FEATURE_COPROC (FPU_MVE
),
2412 0xeea00b10, 0xffb10f5f,
2413 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2415 /* Vector VRHADD. */
2416 {ARM_FEATURE_COPROC (FPU_MVE
),
2418 0xef000140, 0xef811f51,
2419 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2422 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2423 MVE_VCVT_FP_FIX_VEC
,
2424 0xef800c50, 0xef801cd1,
2425 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2428 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2429 MVE_VCVT_BETWEEN_FP_INT
,
2430 0xffb30640, 0xffb31e51,
2431 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2433 /* Vector VCVT between single and half-precision float, bottom half. */
2434 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2435 MVE_VCVT_FP_HALF_FP
,
2436 0xee3f0e01, 0xefbf1fd1,
2437 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2439 /* Vector VCVT between single and half-precision float, top half. */
2440 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2441 MVE_VCVT_FP_HALF_FP
,
2442 0xee3f1e01, 0xefbf1fd1,
2443 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2446 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2447 MVE_VCVT_FROM_FP_TO_INT
,
2448 0xffb30040, 0xffb31c51,
2449 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2452 {ARM_FEATURE_COPROC (FPU_MVE
),
2454 0xee011f6e, 0xff811f7e,
2455 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2457 /* Vector VDWDUP. */
2458 {ARM_FEATURE_COPROC (FPU_MVE
),
2460 0xee011f60, 0xff811f70,
2461 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2463 /* Vector VHCADD. */
2464 {ARM_FEATURE_COPROC (FPU_MVE
),
2466 0xee000f00, 0xff810f51,
2467 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2469 /* Vector VIWDUP. */
2470 {ARM_FEATURE_COPROC (FPU_MVE
),
2472 0xee010f60, 0xff811f70,
2473 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2476 {ARM_FEATURE_COPROC (FPU_MVE
),
2478 0xee010f6e, 0xff811f7e,
2479 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2482 {ARM_FEATURE_COPROC (FPU_MVE
),
2484 0xfc901e00, 0xff901e5f,
2485 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2488 {ARM_FEATURE_COPROC (FPU_MVE
),
2490 0xfc901e01, 0xff901e1f,
2491 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2493 /* Vector VLDRB gather load. */
2494 {ARM_FEATURE_COPROC (FPU_MVE
),
2495 MVE_VLDRB_GATHER_T1
,
2496 0xec900e00, 0xefb01e50,
2497 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2499 /* Vector VLDRH gather load. */
2500 {ARM_FEATURE_COPROC (FPU_MVE
),
2501 MVE_VLDRH_GATHER_T2
,
2502 0xec900e10, 0xefb01e50,
2503 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2505 /* Vector VLDRW gather load. */
2506 {ARM_FEATURE_COPROC (FPU_MVE
),
2507 MVE_VLDRW_GATHER_T3
,
2508 0xfc900f40, 0xffb01fd0,
2509 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2511 /* Vector VLDRD gather load. */
2512 {ARM_FEATURE_COPROC (FPU_MVE
),
2513 MVE_VLDRD_GATHER_T4
,
2514 0xec900fd0, 0xefb01fd0,
2515 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2517 /* Vector VLDRW gather load. */
2518 {ARM_FEATURE_COPROC (FPU_MVE
),
2519 MVE_VLDRW_GATHER_T5
,
2520 0xfd101e00, 0xff111f00,
2521 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2523 /* Vector VLDRD gather load, variant T6. */
2524 {ARM_FEATURE_COPROC (FPU_MVE
),
2525 MVE_VLDRD_GATHER_T6
,
2526 0xfd101f00, 0xff111f00,
2527 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2530 {ARM_FEATURE_COPROC (FPU_MVE
),
2532 0xec100e00, 0xee581e00,
2533 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2536 {ARM_FEATURE_COPROC (FPU_MVE
),
2538 0xec180e00, 0xee581e00,
2539 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2541 /* Vector VLDRB unsigned, variant T5. */
2542 {ARM_FEATURE_COPROC (FPU_MVE
),
2544 0xec101e00, 0xfe101f80,
2545 "vldrb%v.u8\t%13-15,22Q, %d"},
2547 /* Vector VLDRH unsigned, variant T6. */
2548 {ARM_FEATURE_COPROC (FPU_MVE
),
2550 0xec101e80, 0xfe101f80,
2551 "vldrh%v.u16\t%13-15,22Q, %d"},
2553 /* Vector VLDRW unsigned, variant T7. */
2554 {ARM_FEATURE_COPROC (FPU_MVE
),
2556 0xec101f00, 0xfe101f80,
2557 "vldrw%v.u32\t%13-15,22Q, %d"},
2560 {ARM_FEATURE_COPROC (FPU_MVE
),
2562 0xef000640, 0xef811f51,
2563 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2566 {ARM_FEATURE_COPROC (FPU_MVE
),
2568 0xee330e81, 0xffb31fd1,
2569 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2571 /* Vector VMAXNM floating point. */
2572 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2574 0xff000f50, 0xffa11f51,
2575 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2577 /* Vector VMAXNMA floating point. */
2578 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2580 0xee3f0e81, 0xefbf1fd1,
2581 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2583 /* Vector VMAXNMV floating point. */
2584 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2586 0xeeee0f00, 0xefff0fd1,
2587 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2589 /* Vector VMAXNMAV floating point. */
2590 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2592 0xeeec0f00, 0xefff0fd1,
2593 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2596 {ARM_FEATURE_COPROC (FPU_MVE
),
2598 0xeee20f00, 0xeff30fd1,
2599 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2601 /* Vector VMAXAV. */
2602 {ARM_FEATURE_COPROC (FPU_MVE
),
2604 0xeee00f00, 0xfff30fd1,
2605 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2608 {ARM_FEATURE_COPROC (FPU_MVE
),
2610 0xef000650, 0xef811f51,
2611 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2614 {ARM_FEATURE_COPROC (FPU_MVE
),
2616 0xee331e81, 0xffb31fd1,
2617 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2619 /* Vector VMINNM floating point. */
2620 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2622 0xff200f50, 0xffa11f51,
2623 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2625 /* Vector VMINNMA floating point. */
2626 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2628 0xee3f1e81, 0xefbf1fd1,
2629 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2631 /* Vector VMINNMV floating point. */
2632 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2634 0xeeee0f80, 0xefff0fd1,
2635 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2637 /* Vector VMINNMAV floating point. */
2638 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2640 0xeeec0f80, 0xefff0fd1,
2641 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2644 {ARM_FEATURE_COPROC (FPU_MVE
),
2646 0xeee20f80, 0xeff30fd1,
2647 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2649 /* Vector VMINAV. */
2650 {ARM_FEATURE_COPROC (FPU_MVE
),
2652 0xeee00f80, 0xfff30fd1,
2653 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2656 {ARM_FEATURE_COPROC (FPU_MVE
),
2658 0xee010e40, 0xef811f70,
2659 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2661 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2663 {ARM_FEATURE_COPROC (FPU_MVE
),
2665 0xee801e00, 0xef801f51,
2666 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2668 {ARM_FEATURE_COPROC (FPU_MVE
),
2670 0xee800e00, 0xef801f51,
2671 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2673 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2674 {ARM_FEATURE_COPROC (FPU_MVE
),
2676 0xeef00e00, 0xeff01f51,
2677 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2679 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2680 {ARM_FEATURE_COPROC (FPU_MVE
),
2682 0xeef00f00, 0xeff11f51,
2683 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2685 /* Vector VMLADAV T1 variant. */
2686 {ARM_FEATURE_COPROC (FPU_MVE
),
2688 0xeef01e00, 0xeff01f51,
2689 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2691 /* Vector VMLADAV T2 variant. */
2692 {ARM_FEATURE_COPROC (FPU_MVE
),
2694 0xeef01f00, 0xeff11f51,
2695 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2698 {ARM_FEATURE_COPROC (FPU_MVE
),
2700 0xee011e40, 0xef811f70,
2701 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2703 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2705 {ARM_FEATURE_COPROC (FPU_MVE
),
2707 0xfe800e01, 0xff810f51,
2708 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2710 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2712 {ARM_FEATURE_COPROC (FPU_MVE
),
2714 0xee800e01, 0xff800f51,
2715 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2717 /* Vector VMLSDAV T1 Variant. */
2718 {ARM_FEATURE_COPROC (FPU_MVE
),
2720 0xeef00e01, 0xfff00f51,
2721 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2723 /* Vector VMLSDAV T2 Variant. */
2724 {ARM_FEATURE_COPROC (FPU_MVE
),
2726 0xfef00e01, 0xfff10f51,
2727 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2729 /* Vector VMOV between gpr and half precision register, op == 0. */
2730 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2732 0xee000910, 0xfff00f7f,
2733 "vmov.f16\t%7,16-19F, %12-15r"},
2735 /* Vector VMOV between gpr and half precision register, op == 1. */
2736 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2738 0xee100910, 0xfff00f7f,
2739 "vmov.f16\t%12-15r, %7,16-19F"},
2741 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2742 MVE_VMOV_GP_TO_VEC_LANE
,
2743 0xee000b10, 0xff900f1f,
2744 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2746 /* Vector VORR immediate to vector.
2747 NOTE: MVE_VORR_IMM must appear in the table
2748 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2749 {ARM_FEATURE_COPROC (FPU_MVE
),
2751 0xef800050, 0xefb810f0,
2752 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2754 /* Vector VQSHL T2 Variant.
2755 NOTE: MVE_VQSHL_T2 must appear in the table before
2756 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2757 {ARM_FEATURE_COPROC (FPU_MVE
),
2759 0xef800750, 0xef801fd1,
2760 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2762 /* Vector VQSHLU T3 Variant
2763 NOTE: MVE_VQSHL_T2 must appear in the table before
2764 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2766 {ARM_FEATURE_COPROC (FPU_MVE
),
2768 0xff800650, 0xff801fd1,
2769 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2772 NOTE: MVE_VRSHR must appear in the table before
2773 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2774 {ARM_FEATURE_COPROC (FPU_MVE
),
2776 0xef800250, 0xef801fd1,
2777 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2780 NOTE: MVE_VSHL must appear in the table before
2781 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2782 {ARM_FEATURE_COPROC (FPU_MVE
),
2784 0xef800550, 0xff801fd1,
2785 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2788 NOTE: MVE_VSHR must appear in the table before
2789 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2790 {ARM_FEATURE_COPROC (FPU_MVE
),
2792 0xef800050, 0xef801fd1,
2793 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2796 NOTE: MVE_VSLI must appear in the table before
2797 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2798 {ARM_FEATURE_COPROC (FPU_MVE
),
2800 0xff800550, 0xff801fd1,
2801 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2804 NOTE: MVE_VSRI must appear in the table before
2805 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2806 {ARM_FEATURE_COPROC (FPU_MVE
),
2808 0xff800450, 0xff801fd1,
2809 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2811 /* Vector VMOV immediate to vector,
2812 cmode == 11x1 -> VMVN which is UNDEFINED
2813 for such a cmode. */
2814 {ARM_FEATURE_COPROC (FPU_MVE
),
2815 MVE_VMVN_IMM
, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION
},
2817 /* Vector VMOV immediate to vector. */
2818 {ARM_FEATURE_COPROC (FPU_MVE
),
2819 MVE_VMOV_IMM_TO_VEC
,
2820 0xef800050, 0xefb810d0,
2821 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2823 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2824 {ARM_FEATURE_COPROC (FPU_MVE
),
2825 MVE_VMOV2_VEC_LANE_TO_GP
,
2826 0xec000f00, 0xffb01ff0,
2827 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2829 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2830 {ARM_FEATURE_COPROC (FPU_MVE
),
2831 MVE_VMOV2_VEC_LANE_TO_GP
,
2832 0xec000f10, 0xffb01ff0,
2833 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2835 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2836 {ARM_FEATURE_COPROC (FPU_MVE
),
2837 MVE_VMOV2_GP_TO_VEC_LANE
,
2838 0xec100f00, 0xffb01ff0,
2839 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2841 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2842 {ARM_FEATURE_COPROC (FPU_MVE
),
2843 MVE_VMOV2_GP_TO_VEC_LANE
,
2844 0xec100f10, 0xffb01ff0,
2845 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2847 /* Vector VMOV Vector lane to gpr. */
2848 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2849 MVE_VMOV_VEC_LANE_TO_GP
,
2850 0xee100b10, 0xff100f1f,
2851 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2853 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2854 to instruction opcode aliasing. */
2855 {ARM_FEATURE_COPROC (FPU_MVE
),
2857 0xeea00f40, 0xefa00fd1,
2858 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2860 /* Vector VMOVL long. */
2861 {ARM_FEATURE_COPROC (FPU_MVE
),
2863 0xeea00f40, 0xefa70fd1,
2864 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2866 /* Vector VMOV and narrow. */
2867 {ARM_FEATURE_COPROC (FPU_MVE
),
2869 0xfe310e81, 0xffb30fd1,
2870 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2872 /* Floating point move extract. */
2873 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2875 0xfeb00a40, 0xffbf0fd0,
2876 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2878 /* Vector VMUL floating-point T1 variant. */
2879 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2881 0xff000d50, 0xffa11f51,
2882 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2884 /* Vector VMUL floating-point T2 variant. */
2885 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2887 0xee310e60, 0xefb11f70,
2888 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2890 /* Vector VMUL T1 variant. */
2891 {ARM_FEATURE_COPROC (FPU_MVE
),
2893 0xef000950, 0xff811f51,
2894 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2896 /* Vector VMUL T2 variant. */
2897 {ARM_FEATURE_COPROC (FPU_MVE
),
2899 0xee011e60, 0xff811f70,
2900 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2903 {ARM_FEATURE_COPROC (FPU_MVE
),
2905 0xee010e01, 0xef811f51,
2906 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2908 /* Vector VRMULH. */
2909 {ARM_FEATURE_COPROC (FPU_MVE
),
2911 0xee011e01, 0xef811f51,
2912 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2914 /* Vector VMULL integer. */
2915 {ARM_FEATURE_COPROC (FPU_MVE
),
2917 0xee010e00, 0xef810f51,
2918 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2920 /* Vector VMULL polynomial. */
2921 {ARM_FEATURE_COPROC (FPU_MVE
),
2923 0xee310e00, 0xefb10f51,
2924 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2926 /* Vector VMVN immediate to vector. */
2927 {ARM_FEATURE_COPROC (FPU_MVE
),
2929 0xef800070, 0xefb810f0,
2930 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2932 /* Vector VMVN register. */
2933 {ARM_FEATURE_COPROC (FPU_MVE
),
2935 0xffb005c0, 0xffbf1fd1,
2936 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2938 /* Vector VNEG floating point. */
2939 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2941 0xffb107c0, 0xffb31fd1,
2942 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2945 {ARM_FEATURE_COPROC (FPU_MVE
),
2947 0xffb103c0, 0xffb31fd1,
2948 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2950 /* Vector VORN, vector bitwise or not. */
2951 {ARM_FEATURE_COPROC (FPU_MVE
),
2953 0xef300150, 0xffb11f51,
2954 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2956 /* Vector VORR register. */
2957 {ARM_FEATURE_COPROC (FPU_MVE
),
2959 0xef200150, 0xffb11f51,
2960 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2962 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
2963 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
2964 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
2967 {ARM_FEATURE_COPROC (FPU_MVE
),
2968 MVE_VMOV_VEC_TO_VEC
,
2969 0xef200150, 0xffb11f51,
2970 "vmov%v\t%13-15,22Q, %17-19,7Q"},
2972 /* Vector VQDMULL T1 variant. */
2973 {ARM_FEATURE_COPROC (FPU_MVE
),
2975 0xee300f01, 0xefb10f51,
2976 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2979 {ARM_FEATURE_COPROC (FPU_MVE
),
2981 0xfe310f4d, 0xffffffff,
2985 {ARM_FEATURE_COPROC (FPU_MVE
),
2987 0xfe310f01, 0xffb11f51,
2988 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2991 {ARM_FEATURE_COPROC (FPU_MVE
),
2993 0xffb00740, 0xffb31fd1,
2994 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2996 /* Vector VQADD T1 variant. */
2997 {ARM_FEATURE_COPROC (FPU_MVE
),
2999 0xef000050, 0xef811f51,
3000 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3002 /* Vector VQADD T2 variant. */
3003 {ARM_FEATURE_COPROC (FPU_MVE
),
3005 0xee000f60, 0xef811f70,
3006 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3008 /* Vector VQDMULL T2 variant. */
3009 {ARM_FEATURE_COPROC (FPU_MVE
),
3011 0xee300f60, 0xefb10f70,
3012 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3014 /* Vector VQMOVN. */
3015 {ARM_FEATURE_COPROC (FPU_MVE
),
3017 0xee330e01, 0xefb30fd1,
3018 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3020 /* Vector VQMOVUN. */
3021 {ARM_FEATURE_COPROC (FPU_MVE
),
3023 0xee310e81, 0xffb30fd1,
3024 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3026 /* Vector VQDMLADH. */
3027 {ARM_FEATURE_COPROC (FPU_MVE
),
3029 0xee000e00, 0xff810f51,
3030 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3032 /* Vector VQRDMLADH. */
3033 {ARM_FEATURE_COPROC (FPU_MVE
),
3035 0xee000e01, 0xff810f51,
3036 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3038 /* Vector VQDMLAH. */
3039 {ARM_FEATURE_COPROC (FPU_MVE
),
3041 0xee000e60, 0xff811f70,
3042 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3044 /* Vector VQRDMLAH. */
3045 {ARM_FEATURE_COPROC (FPU_MVE
),
3047 0xee000e40, 0xff811f70,
3048 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3050 /* Vector VQDMLASH. */
3051 {ARM_FEATURE_COPROC (FPU_MVE
),
3053 0xee001e60, 0xff811f70,
3054 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3056 /* Vector VQRDMLASH. */
3057 {ARM_FEATURE_COPROC (FPU_MVE
),
3059 0xee001e40, 0xff811f70,
3060 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3062 /* Vector VQDMLSDH. */
3063 {ARM_FEATURE_COPROC (FPU_MVE
),
3065 0xfe000e00, 0xff810f51,
3066 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3068 /* Vector VQRDMLSDH. */
3069 {ARM_FEATURE_COPROC (FPU_MVE
),
3071 0xfe000e01, 0xff810f51,
3072 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3074 /* Vector VQDMULH T1 variant. */
3075 {ARM_FEATURE_COPROC (FPU_MVE
),
3077 0xef000b40, 0xff811f51,
3078 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3080 /* Vector VQRDMULH T2 variant. */
3081 {ARM_FEATURE_COPROC (FPU_MVE
),
3083 0xff000b40, 0xff811f51,
3084 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3086 /* Vector VQDMULH T3 variant. */
3087 {ARM_FEATURE_COPROC (FPU_MVE
),
3089 0xee010e60, 0xff811f70,
3090 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3092 /* Vector VQRDMULH T4 variant. */
3093 {ARM_FEATURE_COPROC (FPU_MVE
),
3095 0xfe010e60, 0xff811f70,
3096 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3099 {ARM_FEATURE_COPROC (FPU_MVE
),
3101 0xffb007c0, 0xffb31fd1,
3102 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3104 /* Vector VQRSHL T1 variant. */
3105 {ARM_FEATURE_COPROC (FPU_MVE
),
3107 0xef000550, 0xef811f51,
3108 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3110 /* Vector VQRSHL T2 variant. */
3111 {ARM_FEATURE_COPROC (FPU_MVE
),
3113 0xee331ee0, 0xefb31ff0,
3114 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3116 /* Vector VQRSHRN. */
3117 {ARM_FEATURE_COPROC (FPU_MVE
),
3119 0xee800f41, 0xefa00fd1,
3120 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3122 /* Vector VQRSHRUN. */
3123 {ARM_FEATURE_COPROC (FPU_MVE
),
3125 0xfe800fc0, 0xffa00fd1,
3126 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3128 /* Vector VQSHL T1 Variant. */
3129 {ARM_FEATURE_COPROC (FPU_MVE
),
3131 0xee311ee0, 0xefb31ff0,
3132 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3134 /* Vector VQSHL T4 Variant. */
3135 {ARM_FEATURE_COPROC (FPU_MVE
),
3137 0xef000450, 0xef811f51,
3138 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3140 /* Vector VQSHRN. */
3141 {ARM_FEATURE_COPROC (FPU_MVE
),
3143 0xee800f40, 0xefa00fd1,
3144 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3146 /* Vector VQSHRUN. */
3147 {ARM_FEATURE_COPROC (FPU_MVE
),
3149 0xee800fc0, 0xffa00fd1,
3150 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3152 /* Vector VQSUB T1 Variant. */
3153 {ARM_FEATURE_COPROC (FPU_MVE
),
3155 0xef000250, 0xef811f51,
3156 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3158 /* Vector VQSUB T2 Variant. */
3159 {ARM_FEATURE_COPROC (FPU_MVE
),
3161 0xee001f60, 0xef811f70,
3162 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3164 /* Vector VREV16. */
3165 {ARM_FEATURE_COPROC (FPU_MVE
),
3167 0xffb00140, 0xffb31fd1,
3168 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3170 /* Vector VREV32. */
3171 {ARM_FEATURE_COPROC (FPU_MVE
),
3173 0xffb000c0, 0xffb31fd1,
3174 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3176 /* Vector VREV64. */
3177 {ARM_FEATURE_COPROC (FPU_MVE
),
3179 0xffb00040, 0xffb31fd1,
3180 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3182 /* Vector VRINT floating point. */
3183 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
3185 0xffb20440, 0xffb31c51,
3186 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3188 /* Vector VRMLALDAVH. */
3189 {ARM_FEATURE_COPROC (FPU_MVE
),
3191 0xee800f00, 0xef811f51,
3192 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3194 /* Vector VRMLALDAVH. */
3195 {ARM_FEATURE_COPROC (FPU_MVE
),
3197 0xee801f00, 0xef811f51,
3198 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3200 /* Vector VRSHL T1 Variant. */
3201 {ARM_FEATURE_COPROC (FPU_MVE
),
3203 0xef000540, 0xef811f51,
3204 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3206 /* Vector VRSHL T2 Variant. */
3207 {ARM_FEATURE_COPROC (FPU_MVE
),
3209 0xee331e60, 0xefb31ff0,
3210 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3212 /* Vector VRSHRN. */
3213 {ARM_FEATURE_COPROC (FPU_MVE
),
3215 0xfe800fc1, 0xffa00fd1,
3216 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3219 {ARM_FEATURE_COPROC (FPU_MVE
),
3221 0xfe300f00, 0xffb10f51,
3222 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3224 /* Vector VSHL T2 Variant. */
3225 {ARM_FEATURE_COPROC (FPU_MVE
),
3227 0xee311e60, 0xefb31ff0,
3228 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3230 /* Vector VSHL T3 Variant. */
3231 {ARM_FEATURE_COPROC (FPU_MVE
),
3233 0xef000440, 0xef811f51,
3234 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3237 {ARM_FEATURE_COPROC (FPU_MVE
),
3239 0xeea00fc0, 0xffa01ff0,
3240 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3242 /* Vector VSHLL T2 Variant. */
3243 {ARM_FEATURE_COPROC (FPU_MVE
),
3245 0xee310e01, 0xefb30fd1,
3246 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3249 {ARM_FEATURE_COPROC (FPU_MVE
),
3251 0xee800fc1, 0xffa00fd1,
3252 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3254 /* Vector VST2 no writeback. */
3255 {ARM_FEATURE_COPROC (FPU_MVE
),
3257 0xfc801e00, 0xffb01e5f,
3258 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3260 /* Vector VST2 writeback. */
3261 {ARM_FEATURE_COPROC (FPU_MVE
),
3263 0xfca01e00, 0xffb01e5f,
3264 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3266 /* Vector VST4 no writeback. */
3267 {ARM_FEATURE_COPROC (FPU_MVE
),
3269 0xfc801e01, 0xffb01e1f,
3270 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3272 /* Vector VST4 writeback. */
3273 {ARM_FEATURE_COPROC (FPU_MVE
),
3275 0xfca01e01, 0xffb01e1f,
3276 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3278 /* Vector VSTRB scatter store, T1 variant. */
3279 {ARM_FEATURE_COPROC (FPU_MVE
),
3280 MVE_VSTRB_SCATTER_T1
,
3281 0xec800e00, 0xffb01e50,
3282 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3284 /* Vector VSTRH scatter store, T2 variant. */
3285 {ARM_FEATURE_COPROC (FPU_MVE
),
3286 MVE_VSTRH_SCATTER_T2
,
3287 0xec800e10, 0xffb01e50,
3288 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3290 /* Vector VSTRW scatter store, T3 variant. */
3291 {ARM_FEATURE_COPROC (FPU_MVE
),
3292 MVE_VSTRW_SCATTER_T3
,
3293 0xec800e40, 0xffb01e50,
3294 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3296 /* Vector VSTRD scatter store, T4 variant. */
3297 {ARM_FEATURE_COPROC (FPU_MVE
),
3298 MVE_VSTRD_SCATTER_T4
,
3299 0xec800fd0, 0xffb01fd0,
3300 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3302 /* Vector VSTRW scatter store, T5 variant. */
3303 {ARM_FEATURE_COPROC (FPU_MVE
),
3304 MVE_VSTRW_SCATTER_T5
,
3305 0xfd001e00, 0xff111f00,
3306 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3308 /* Vector VSTRD scatter store, T6 variant. */
3309 {ARM_FEATURE_COPROC (FPU_MVE
),
3310 MVE_VSTRD_SCATTER_T6
,
3311 0xfd001f00, 0xff111f00,
3312 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3315 {ARM_FEATURE_COPROC (FPU_MVE
),
3317 0xec000e00, 0xfe581e00,
3318 "vstrb%v.%7-8s\t%13-15Q, %d"},
3321 {ARM_FEATURE_COPROC (FPU_MVE
),
3323 0xec080e00, 0xfe581e00,
3324 "vstrh%v.%7-8s\t%13-15Q, %d"},
3326 /* Vector VSTRB variant T5. */
3327 {ARM_FEATURE_COPROC (FPU_MVE
),
3329 0xec001e00, 0xfe101f80,
3330 "vstrb%v.8\t%13-15,22Q, %d"},
3332 /* Vector VSTRH variant T6. */
3333 {ARM_FEATURE_COPROC (FPU_MVE
),
3335 0xec001e80, 0xfe101f80,
3336 "vstrh%v.16\t%13-15,22Q, %d"},
3338 /* Vector VSTRW variant T7. */
3339 {ARM_FEATURE_COPROC (FPU_MVE
),
3341 0xec001f00, 0xfe101f80,
3342 "vstrw%v.32\t%13-15,22Q, %d"},
3344 /* Vector VSUB floating point T1 variant. */
3345 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
3347 0xef200d40, 0xffa11f51,
3348 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3350 /* Vector VSUB floating point T2 variant. */
3351 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
3353 0xee301f40, 0xefb11f70,
3354 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3356 /* Vector VSUB T1 variant. */
3357 {ARM_FEATURE_COPROC (FPU_MVE
),
3359 0xff000840, 0xff811f51,
3360 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3362 /* Vector VSUB T2 variant. */
3363 {ARM_FEATURE_COPROC (FPU_MVE
),
3365 0xee011f40, 0xff811f70,
3366 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3368 {ARM_FEATURE_COPROC (FPU_MVE
),
3370 0xea50012f, 0xfff1813f,
3371 "asrl%c\t%17-19l, %9-11h, %j"},
3373 {ARM_FEATURE_COPROC (FPU_MVE
),
3375 0xea50012d, 0xfff101ff,
3376 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3378 {ARM_FEATURE_COPROC (FPU_MVE
),
3380 0xea50010f, 0xfff1813f,
3381 "lsll%c\t%17-19l, %9-11h, %j"},
3383 {ARM_FEATURE_COPROC (FPU_MVE
),
3385 0xea50010d, 0xfff101ff,
3386 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3388 {ARM_FEATURE_COPROC (FPU_MVE
),
3390 0xea50011f, 0xfff1813f,
3391 "lsrl%c\t%17-19l, %9-11h, %j"},
3393 {ARM_FEATURE_COPROC (FPU_MVE
),
3395 0xea51012d, 0xfff1017f,
3396 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3398 {ARM_FEATURE_COPROC (FPU_MVE
),
3400 0xea500f2d, 0xfff00fff,
3401 "sqrshr%c\t%16-19S, %12-15S"},
3403 {ARM_FEATURE_COPROC (FPU_MVE
),
3405 0xea51013f, 0xfff1813f,
3406 "sqshll%c\t%17-19l, %9-11h, %j"},
3408 {ARM_FEATURE_COPROC (FPU_MVE
),
3410 0xea500f3f, 0xfff08f3f,
3411 "sqshl%c\t%16-19S, %j"},
3413 {ARM_FEATURE_COPROC (FPU_MVE
),
3415 0xea51012f, 0xfff1813f,
3416 "srshrl%c\t%17-19l, %9-11h, %j"},
3418 {ARM_FEATURE_COPROC (FPU_MVE
),
3420 0xea500f2f, 0xfff08f3f,
3421 "srshr%c\t%16-19S, %j"},
3423 {ARM_FEATURE_COPROC (FPU_MVE
),
3425 0xea51010d, 0xfff1017f,
3426 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3428 {ARM_FEATURE_COPROC (FPU_MVE
),
3430 0xea500f0d, 0xfff00fff,
3431 "uqrshl%c\t%16-19S, %12-15S"},
3433 {ARM_FEATURE_COPROC (FPU_MVE
),
3435 0xea51010f, 0xfff1813f,
3436 "uqshll%c\t%17-19l, %9-11h, %j"},
3438 {ARM_FEATURE_COPROC (FPU_MVE
),
3440 0xea500f0f, 0xfff08f3f,
3441 "uqshl%c\t%16-19S, %j"},
3443 {ARM_FEATURE_COPROC (FPU_MVE
),
3445 0xea51011f, 0xfff1813f,
3446 "urshrl%c\t%17-19l, %9-11h, %j"},
3448 {ARM_FEATURE_COPROC (FPU_MVE
),
3450 0xea500f1f, 0xfff08f3f,
3451 "urshr%c\t%16-19S, %j"},
3453 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3455 0xea509000, 0xfff0f000,
3456 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3460 0xea50a000, 0xfff0f000,
3461 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3465 0xea5f900f, 0xfffff00f,
3466 "cset\t%8-11S, %4-7C"},
3468 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3470 0xea5fa00f, 0xfffff00f,
3471 "csetm\t%8-11S, %4-7C"},
3473 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3475 0xea508000, 0xfff0f000,
3476 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3478 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3480 0xea50b000, 0xfff0f000,
3481 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3485 0xea509000, 0xfff0f000,
3486 "cinc\t%8-11S, %16-19Z, %4-7C"},
3488 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3490 0xea50a000, 0xfff0f000,
3491 "cinv\t%8-11S, %16-19Z, %4-7C"},
3493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3495 0xea50b000, 0xfff0f000,
3496 "cneg\t%8-11S, %16-19Z, %4-7C"},
3498 {ARM_FEATURE_CORE_LOW (0),
3500 0x00000000, 0x00000000, 0}
3503 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3504 ordered: they must be searched linearly from the top to obtain a correct
3507 /* print_insn_arm recognizes the following format control codes:
3511 %a print address for ldr/str instruction
3512 %s print address for ldr/str halfword/signextend instruction
3513 %S like %s but allow UNPREDICTABLE addressing
3514 %b print branch destination
3515 %c print condition code (always bits 28-31)
3516 %m print register mask for ldm/stm instruction
3517 %o print operand2 (immediate or register + shift)
3518 %p print 'p' iff bits 12-15 are 15
3519 %t print 't' iff bit 21 set and bit 24 clear
3520 %B print arm BLX(1) destination
3521 %C print the PSR sub type.
3522 %U print barrier type.
3523 %P print address for pli instruction.
3525 %<bitfield>r print as an ARM register
3526 %<bitfield>T print as an ARM register + 1
3527 %<bitfield>R as %r but r15 is UNPREDICTABLE
3528 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3529 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3530 %<bitfield>d print the bitfield in decimal
3531 %<bitfield>W print the bitfield plus one in decimal
3532 %<bitfield>x print the bitfield in hex
3533 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3535 %<bitfield>'c print specified char iff bitfield is all ones
3536 %<bitfield>`c print specified char iff bitfield is all zeroes
3537 %<bitfield>?ab... select from array of values in big endian order
3539 %e print arm SMI operand (bits 0..7,8..19).
3540 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3541 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3542 %R print the SPSR/CPSR or banked register of an MRS. */
3544 static const struct opcode32 arm_opcodes
[] =
3546 /* ARM instructions. */
3547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3548 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3550 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
3553 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3555 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3557 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
3559 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3561 0x00800090, 0x0fa000f0,
3562 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3564 0x00a00090, 0x0fa000f0,
3565 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3567 /* V8.2 RAS extension instructions. */
3568 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
3569 0xe320f010, 0xffffffff, "esb"},
3571 /* V8 instructions. */
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3573 0x0320f005, 0x0fffffff, "sevl"},
3574 /* Defined in V8 but is in NOP space so available to all arch. */
3575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3576 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3577 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
3578 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3579 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3580 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3582 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3584 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3586 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3587 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3588 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3590 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3591 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3592 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3593 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3594 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3595 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3596 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3598 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3599 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3600 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3601 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3602 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3603 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3604 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3605 /* CRC32 instructions. */
3606 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3607 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3608 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3609 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3610 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3611 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3612 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3613 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3614 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3615 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3616 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3617 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3619 /* Privileged Access Never extension instructions. */
3620 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
3621 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3623 /* Virtualization Extension instructions. */
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3627 /* Integer Divide Extension instructions. */
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3629 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3631 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3633 /* MP Extension instructions. */
3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3636 /* Speculation Barriers. */
3637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
3641 /* V7 instructions. */
3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
3643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3650 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3652 /* ARM V6T2 instructions. */
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3654 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3656 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3658 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3660 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3663 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3665 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3668 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3669 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3670 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3672 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3674 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3676 /* ARM Security extension instructions. */
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
3678 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3680 /* ARM V6K instructions. */
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3682 0xf57ff01f, 0xffffffff, "clrex"},
3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3684 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3686 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3688 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3690 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3692 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3694 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3696 /* ARMv8.5-A instructions. */
3697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
3699 /* ARM V6K NOP hints. */
3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3701 0x0320f001, 0x0fffffff, "yield%c"},
3702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3703 0x0320f002, 0x0fffffff, "wfe%c"},
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3705 0x0320f003, 0x0fffffff, "wfi%c"},
3706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3707 0x0320f004, 0x0fffffff, "sev%c"},
3708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3709 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3711 /* ARM V6 instructions. */
3712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3713 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3715 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3717 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3719 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3721 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3723 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3725 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3727 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3729 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3731 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3733 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3735 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3737 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3739 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3741 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3743 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3745 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3747 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3749 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3751 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3753 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3755 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3757 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3759 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3761 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3763 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3765 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3767 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3769 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3771 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3773 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3775 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3777 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3779 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3781 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3783 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3785 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3787 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3789 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3791 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3793 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3795 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3797 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3799 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3801 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3803 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3805 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3807 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3809 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3811 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3813 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3815 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3817 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3819 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3821 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3823 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3825 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3827 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3829 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3831 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3833 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3835 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3837 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3839 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3841 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3843 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3845 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3847 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3849 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3851 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3853 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3855 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3857 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3859 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3861 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3863 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3865 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3867 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3869 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3871 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3873 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3875 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3877 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3879 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3881 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3883 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3885 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3887 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3889 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3891 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3893 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3895 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3897 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3899 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3901 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3903 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3905 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3907 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3909 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3911 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3913 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3915 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3917 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3919 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3921 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3923 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3925 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3927 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3929 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3931 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3933 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3935 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3937 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3939 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3941 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3943 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3945 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3947 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3949 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3951 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3953 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3955 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3957 /* V5J instruction. */
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
3959 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3961 /* V5 Instructions. */
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3963 0xe1200070, 0xfff000f0,
3964 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3966 0xfa000000, 0xfe000000, "blx\t%B"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3968 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3970 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3972 /* V5E "El Segundo" Instructions. */
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3974 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3976 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3978 0xf450f000, 0xfc70f000, "pld\t%a"},
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3980 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3982 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3984 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3986 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3989 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3991 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3994 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3996 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3998 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4000 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4003 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4005 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4007 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4009 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4012 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4014 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4017 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4019 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4021 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4023 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
4025 /* ARM Instructions. */
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4027 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4030 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4032 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4034 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4036 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4038 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4040 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4043 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4045 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4047 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4049 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4052 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4054 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4056 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4058 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4061 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4063 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4065 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4068 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4070 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4072 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4075 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4077 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4079 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4082 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4084 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4086 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4089 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4091 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4093 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4096 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4098 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4100 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4103 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4105 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4107 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4110 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4112 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4114 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
4117 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
4119 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
4121 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4124 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4126 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4128 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4131 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4133 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4135 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4138 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4140 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4142 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4145 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4147 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4149 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4152 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4154 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4156 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4159 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4161 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4163 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4165 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4167 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4169 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4171 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4174 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4176 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4178 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4181 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4183 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4185 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4188 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4190 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4193 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4196 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4198 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4201 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4203 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4205 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4207 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4209 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4211 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4213 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4215 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4217 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4219 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4221 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4223 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4225 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4227 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4229 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4231 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4233 0x092d0000, 0x0fff0000, "push%c\t%m"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4235 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4237 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4240 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4242 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4244 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4246 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4248 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4250 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4252 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4254 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4256 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4258 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4260 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4262 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4264 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4266 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4268 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4270 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4272 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4274 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4276 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4279 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4281 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
4285 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4287 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
4288 {ARM_FEATURE_CORE_LOW (0),
4289 0x00000000, 0x00000000, 0}
4292 /* print_insn_thumb16 recognizes the following format control codes:
4294 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4295 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4296 %<bitfield>I print bitfield as a signed decimal
4297 (top bit of range being the sign bit)
4298 %N print Thumb register mask (with LR)
4299 %O print Thumb register mask (with PC)
4300 %M print Thumb register mask
4301 %b print CZB's 6-bit unsigned branch destination
4302 %s print Thumb right-shift immediate (6..10; 0 == 32).
4303 %c print the condition code
4304 %C print the condition code, or "s" if not conditional
4305 %x print warning if conditional an not at end of IT block"
4306 %X print "\t; unpredictable <IT:code>" if conditional
4307 %I print IT instruction suffix and operands
4308 %W print Thumb Writeback indicator for LDMIA
4309 %<bitfield>r print bitfield as an ARM register
4310 %<bitfield>d print bitfield as a decimal
4311 %<bitfield>H print (bitfield * 2) as a decimal
4312 %<bitfield>W print (bitfield * 4) as a decimal
4313 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4314 %<bitfield>B print Thumb branch destination (signed displacement)
4315 %<bitfield>c print bitfield as a condition code
4316 %<bitnum>'c print specified char iff bit is one
4317 %<bitnum>?ab print a if bit is one else print b. */
4319 static const struct opcode16 thumb_opcodes
[] =
4321 /* Thumb instructions. */
4323 /* ARMv8-M Security Extensions instructions. */
4324 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
4325 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
4327 /* ARM V8 instructions. */
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
4329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
4330 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
4332 /* ARM V6K no-argument instructions. */
4333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4340 /* ARM V6T2 instructions. */
4341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4342 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4343 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4344 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4360 /* ARM V5 ISA extends Thumb. */
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
4362 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
4363 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
4365 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
4366 /* ARM V4T ISA (Thumb v1). */
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4368 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
4398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4399 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4401 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4403 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4405 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4408 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4410 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4412 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4415 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4417 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4421 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4430 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4433 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4436 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4438 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4440 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4442 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4445 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4447 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4450 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4452 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4455 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4457 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4470 /* The E800 .. FFFF range is unconditionally redirected to the
4471 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4472 are processed via that table. Thus, we can never encounter a
4473 bare "second half of BL/BLX(1)" instruction here. */
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
4475 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4478 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4479 We adopt the convention that hw1 is the high 16 bits of .value and
4480 .mask, hw2 the low 16 bits.
4482 print_insn_thumb32 recognizes the following format control codes:
4486 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4487 %M print a modified 12-bit immediate (same location)
4488 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4489 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4490 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
4491 %S print a possibly-shifted Rm
4493 %L print address for a ldrd/strd instruction
4494 %a print the address of a plain load/store
4495 %w print the width and signedness of a core load/store
4496 %m print register mask for ldm/stm
4497 %n print register mask for clrm
4499 %E print the lsb and width fields of a bfc/bfi instruction
4500 %F print the lsb and width fields of a sbfx/ubfx instruction
4501 %G print a fallback offset for Branch Future instructions
4502 %W print an offset for BF instruction
4503 %Y print an offset for BFL instruction
4504 %Z print an offset for BFCSEL instruction
4505 %Q print an offset for Low Overhead Loop instructions
4506 %P print an offset for Low Overhead Loop end instructions
4507 %b print a conditional branch offset
4508 %B print an unconditional branch offset
4509 %s print the shift field of an SSAT instruction
4510 %R print the rotation field of an SXT instruction
4511 %U print barrier type.
4512 %P print address for pli instruction.
4513 %c print the condition code
4514 %x print warning if conditional an not at end of IT block"
4515 %X print "\t; unpredictable <IT:code>" if conditional
4517 %<bitfield>d print bitfield in decimal
4518 %<bitfield>D print bitfield plus one in decimal
4519 %<bitfield>W print bitfield*4 in decimal
4520 %<bitfield>r print bitfield as an ARM register
4521 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4522 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4523 %<bitfield>c print bitfield as a condition code
4525 %<bitfield>'c print specified char iff bitfield is all ones
4526 %<bitfield>`c print specified char iff bitfield is all zeroes
4527 %<bitfield>?ab... select from array of values in big endian order
4529 With one exception at the bottom (done because BL and BLX(1) need
4530 to come dead last), this table was machine-sorted first in
4531 decreasing order of number of bits set in the mask, then in
4532 increasing numeric order of mask, then in increasing numeric order
4533 of opcode. This order is not the clearest for a human reader, but
4534 is guaranteed never to catch a special-case bit pattern with a more
4535 general mask, which is important, because this instruction encoding
4536 makes heavy use of special-case bit patterns. */
4537 static const struct opcode32 thumb32_opcodes
[] =
4539 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4542 0xf00fe001, 0xffffffff, "lctp%c"},
4543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4544 0xf02fc001, 0xfffff001, "le\t%P"},
4545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4546 0xf00fc001, 0xfffff001, "le\tlr, %P"},
4547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4548 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4550 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4551 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4552 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4554 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4556 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4559 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4561 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4562 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4563 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4565 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4566 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4567 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4570 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4572 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4573 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
4574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4575 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4577 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4578 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4579 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4581 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4583 /* ARM V8.2 RAS extension instructions. */
4584 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
4585 0xf3af8010, 0xffffffff, "esb"},
4587 /* V8 instructions. */
4588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4589 0xf3af8005, 0xffffffff, "sevl%c.w"},
4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4591 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4593 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4595 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4597 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4599 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4601 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4603 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4605 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4607 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4609 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4611 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4613 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4615 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4617 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4619 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4621 /* CRC32 instructions. */
4622 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4623 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4624 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4625 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4626 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4627 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4628 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4629 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4630 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4631 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4632 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4633 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4635 /* Speculation Barriers. */
4636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
4637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
4638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
4640 /* V7 instructions. */
4641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4648 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4649 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4650 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4651 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4653 /* Virtualization Extension instructions. */
4654 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4655 /* We skip ERET as that is SUBS pc, lr, #0. */
4657 /* MP Extension instructions. */
4658 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4660 /* Security extension instructions. */
4661 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4663 /* ARMv8.5-A instructions. */
4664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
4666 /* Instructions defined in the basic V6T2 set. */
4667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
4668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
4669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
4672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4673 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4677 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4679 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4681 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4683 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4685 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4687 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4689 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4691 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4693 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4695 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4697 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4699 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4701 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4703 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4704 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4705 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4707 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4709 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4711 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4713 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4715 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4717 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4719 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4721 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4723 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4725 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4727 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4729 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4731 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4733 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4735 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4737 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4739 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4741 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4743 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4745 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4747 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4749 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4751 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4753 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4755 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4757 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4759 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4761 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4763 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4765 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4767 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4769 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4771 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4773 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4775 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4777 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4779 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4781 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4783 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4785 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4787 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4789 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4791 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4793 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4795 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4797 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4799 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4801 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4803 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4805 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4807 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4809 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4811 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4813 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4815 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4817 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4819 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4821 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4823 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4825 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4827 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4829 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4831 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4832 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4833 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4835 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4837 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4839 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4841 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4843 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4845 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4847 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4849 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4851 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4853 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4855 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4857 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4859 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4861 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4863 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4865 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4867 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4869 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4871 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4873 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4875 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4877 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4879 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4881 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4883 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4885 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4887 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4889 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4891 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4893 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4895 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4897 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4899 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4901 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4903 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4905 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4907 0xf810f000, 0xff70f000, "pld%c\t%a"},
4908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4909 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4911 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4913 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4915 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4917 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4919 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4921 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4923 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4925 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4927 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4929 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4931 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4933 0xfb100000, 0xfff000c0,
4934 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4936 0xfbc00080, 0xfff000c0,
4937 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4939 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4941 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4943 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4945 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4947 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4948 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4949 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4951 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4952 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4953 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4955 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4957 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4959 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4961 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4963 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4965 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4967 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4969 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4971 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4973 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4974 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4975 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4977 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4979 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4981 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4983 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4985 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4987 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4989 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4991 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4993 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4995 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4997 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4999 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5001 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5003 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5005 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5007 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5009 0xe9400000, 0xff500000,
5010 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5012 0xe9500000, 0xff500000,
5013 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5015 0xe8600000, 0xff700000,
5016 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5018 0xe8700000, 0xff700000,
5019 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5021 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5023 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
5025 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
5026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5027 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5029 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5031 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5033 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
5035 /* These have been 32-bit since the invention of Thumb. */
5036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
5037 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
5039 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
5043 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
5044 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5047 static const char *const arm_conditional
[] =
5048 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5049 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5051 static const char *const arm_fp_const
[] =
5052 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5054 static const char *const arm_shift
[] =
5055 {"lsl", "lsr", "asr", "ror"};
5060 const char *description
;
5061 const char *reg_names
[16];
5065 static const arm_regname regnames
[] =
5067 { "reg-names-raw", N_("Select raw register names"),
5068 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5069 { "reg-names-gcc", N_("Select register names used by GCC"),
5070 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
5071 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5072 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
5073 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
5074 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
5075 { "reg-names-apcs", N_("Select register names used in the APCS"),
5076 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
5077 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5078 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
5079 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5080 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
5083 static const char *const iwmmxt_wwnames
[] =
5084 {"b", "h", "w", "d"};
5086 static const char *const iwmmxt_wwssnames
[] =
5087 {"b", "bus", "bc", "bss",
5088 "h", "hus", "hc", "hss",
5089 "w", "wus", "wc", "wss",
5090 "d", "dus", "dc", "dss"
5093 static const char *const iwmmxt_regnames
[] =
5094 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5095 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5098 static const char *const iwmmxt_cregnames
[] =
5099 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5100 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5103 static const char *const vec_condnames
[] =
5104 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5107 static const char *const mve_predicatenames
[] =
5108 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5109 "eee", "ee", "eet", "e", "ett", "et", "ete"
5112 /* Names for 2-bit size field for mve vector isntructions. */
5113 static const char *const mve_vec_sizename
[] =
5114 { "8", "16", "32", "64"};
5116 /* Indicates whether we are processing a then predicate,
5117 else predicate or none at all. */
5125 /* Information used to process a vpt block and subsequent instructions. */
5128 /* Are we in a vpt block. */
5129 bfd_boolean in_vpt_block
;
5131 /* Next predicate state if in vpt block. */
5132 enum vpt_pred_state next_pred_state
;
5134 /* Mask from vpt/vpst instruction. */
5135 long predicate_mask
;
5137 /* Instruction number in vpt block. */
5138 long current_insn_num
;
5140 /* Number of instructions in vpt block.. */
5144 static struct vpt_block vpt_block_state
=
5153 /* Default to GCC register name set. */
5154 static unsigned int regname_selected
= 1;
5156 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
5157 #define arm_regnames regnames[regname_selected].reg_names
5159 static bfd_boolean force_thumb
= FALSE
;
5161 /* Current IT instruction state. This contains the same state as the IT
5162 bits in the CPSR. */
5163 static unsigned int ifthen_state
;
5164 /* IT state for the next instruction. */
5165 static unsigned int ifthen_next_state
;
5166 /* The address of the insn for which the IT state is valid. */
5167 static bfd_vma ifthen_address
;
5168 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5169 /* Indicates that the current Conditional state is unconditional or outside
5171 #define COND_UNCOND 16
5175 /* Extract the predicate mask for a VPT or VPST instruction.
5176 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5179 mve_extract_pred_mask (long given
)
5181 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
5184 /* Return the number of instructions in a MVE predicate block. */
5186 num_instructions_vpt_block (long given
)
5188 long mask
= mve_extract_pred_mask (given
);
5195 if ((mask
& 7) == 4)
5198 if ((mask
& 3) == 2)
5201 if ((mask
& 1) == 1)
5208 mark_outside_vpt_block (void)
5210 vpt_block_state
.in_vpt_block
= FALSE
;
5211 vpt_block_state
.next_pred_state
= PRED_NONE
;
5212 vpt_block_state
.predicate_mask
= 0;
5213 vpt_block_state
.current_insn_num
= 0;
5214 vpt_block_state
.num_pred_insn
= 0;
5218 mark_inside_vpt_block (long given
)
5220 vpt_block_state
.in_vpt_block
= TRUE
;
5221 vpt_block_state
.next_pred_state
= PRED_THEN
;
5222 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
5223 vpt_block_state
.current_insn_num
= 0;
5224 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
5225 assert (vpt_block_state
.num_pred_insn
>= 1);
5228 static enum vpt_pred_state
5229 invert_next_predicate_state (enum vpt_pred_state astate
)
5231 if (astate
== PRED_THEN
)
5233 else if (astate
== PRED_ELSE
)
5239 static enum vpt_pred_state
5240 update_next_predicate_state (void)
5242 long pred_mask
= vpt_block_state
.predicate_mask
;
5243 long mask_for_insn
= 0;
5245 switch (vpt_block_state
.current_insn_num
)
5263 if (pred_mask
& mask_for_insn
)
5264 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
5266 return vpt_block_state
.next_pred_state
;
5270 update_vpt_block_state (void)
5272 vpt_block_state
.current_insn_num
++;
5273 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
5275 /* No more instructions to process in vpt block. */
5276 mark_outside_vpt_block ();
5280 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
5283 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5284 Returns pointer to following character of the format string and
5285 fills in *VALUEP and *WIDTHP with the extracted value and number of
5286 bits extracted. WIDTHP can be NULL. */
5289 arm_decode_bitfield (const char *ptr
,
5291 unsigned long *valuep
,
5294 unsigned long value
= 0;
5302 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
5303 start
= start
* 10 + *ptr
- '0';
5305 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
5306 end
= end
* 10 + *ptr
- '0';
5312 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
5315 while (*ptr
++ == ',');
5323 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
5324 bfd_boolean print_shift
)
5326 func (stream
, "%s", arm_regnames
[given
& 0xf]);
5328 if ((given
& 0xff0) != 0)
5330 if ((given
& 0x10) == 0)
5332 int amount
= (given
& 0xf80) >> 7;
5333 int shift
= (given
& 0x60) >> 5;
5339 func (stream
, ", rrx");
5347 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
5349 func (stream
, ", #%d", amount
);
5351 else if ((given
& 0x80) == 0x80)
5352 func (stream
, "\t; <illegal shifter operand>");
5353 else if (print_shift
)
5354 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
5355 arm_regnames
[(given
& 0xf00) >> 8]);
5357 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
5361 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5364 is_mve_okay_in_it (enum mve_instructions matched_insn
)
5366 switch (matched_insn
)
5368 case MVE_VMOV_GP_TO_VEC_LANE
:
5369 case MVE_VMOV2_VEC_LANE_TO_GP
:
5370 case MVE_VMOV2_GP_TO_VEC_LANE
:
5371 case MVE_VMOV_VEC_LANE_TO_GP
:
5396 is_mve_architecture (struct disassemble_info
*info
)
5398 struct arm_private_data
*private_data
= info
->private_data
;
5399 arm_feature_set allowed_arches
= private_data
->features
;
5401 arm_feature_set arm_ext_v8_1m_main
5402 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
5404 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
5405 && !ARM_CPU_IS_ANY (allowed_arches
))
5412 is_vpt_instruction (long given
)
5415 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5416 if ((given
& 0x0040e000) == 0)
5419 /* VPT floating point T1 variant. */
5420 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
5421 /* VPT floating point T2 variant. */
5422 || ((given
& 0xefb10f50) == 0xee310f40)
5423 /* VPT vector T1 variant. */
5424 || ((given
& 0xff811f51) == 0xfe010f00)
5425 /* VPT vector T2 variant. */
5426 || ((given
& 0xff811f51) == 0xfe010f01
5427 && ((given
& 0x300000) != 0x300000))
5428 /* VPT vector T3 variant. */
5429 || ((given
& 0xff811f50) == 0xfe011f00)
5430 /* VPT vector T4 variant. */
5431 || ((given
& 0xff811f70) == 0xfe010f40)
5432 /* VPT vector T5 variant. */
5433 || ((given
& 0xff811f70) == 0xfe010f60)
5434 /* VPT vector T6 variant. */
5435 || ((given
& 0xff811f50) == 0xfe011f40)
5436 /* VPST vector T variant. */
5437 || ((given
& 0xffbf1fff) == 0xfe310f4d))
5443 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5444 and ending bitfield = END. END must be greater than START. */
5446 static unsigned long
5447 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
5449 int bits
= end
- start
;
5454 return ((given
>> start
) & ((2ul << bits
) - 1));
5457 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5458 START:END and START2:END2. END/END2 must be greater than
5461 static unsigned long
5462 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
5463 unsigned int end
, unsigned int start2
,
5466 int bits
= end
- start
;
5467 int bits2
= end2
- start2
;
5468 unsigned long value
= 0;
5474 value
= arm_decode_field (given
, start
, end
);
5477 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
5481 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5482 This helps us decode instructions that change mnemonic depending on specific
5483 operand values/encodings. */
5486 is_mve_encoding_conflict (unsigned long given
,
5487 enum mve_instructions matched_insn
)
5489 switch (matched_insn
)
5492 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5498 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5500 if ((arm_decode_field (given
, 12, 12) == 0)
5501 && (arm_decode_field (given
, 0, 0) == 1))
5506 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5508 if (arm_decode_field (given
, 0, 3) == 0xd)
5512 case MVE_VPT_VEC_T1
:
5513 case MVE_VPT_VEC_T2
:
5514 case MVE_VPT_VEC_T3
:
5515 case MVE_VPT_VEC_T4
:
5516 case MVE_VPT_VEC_T5
:
5517 case MVE_VPT_VEC_T6
:
5518 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5520 if (arm_decode_field (given
, 20, 21) == 3)
5524 case MVE_VCMP_FP_T1
:
5525 if ((arm_decode_field (given
, 12, 12) == 0)
5526 && (arm_decode_field (given
, 0, 0) == 1))
5531 case MVE_VCMP_FP_T2
:
5532 if (arm_decode_field (given
, 0, 3) == 0xd)
5539 case MVE_VMUL_VEC_T2
:
5546 case MVE_VADD_VEC_T2
:
5547 case MVE_VSUB_VEC_T2
:
5564 case MVE_VQDMULH_T3
:
5565 case MVE_VQRDMULH_T4
:
5571 case MVE_VCMP_VEC_T1
:
5572 case MVE_VCMP_VEC_T2
:
5573 case MVE_VCMP_VEC_T3
:
5574 case MVE_VCMP_VEC_T4
:
5575 case MVE_VCMP_VEC_T5
:
5576 case MVE_VCMP_VEC_T6
:
5577 if (arm_decode_field (given
, 20, 21) == 3)
5586 if (arm_decode_field (given
, 7, 8) == 3)
5593 if ((arm_decode_field (given
, 24, 24) == 0)
5594 && (arm_decode_field (given
, 21, 21) == 0))
5598 else if ((arm_decode_field (given
, 7, 8) == 3))
5606 if ((arm_decode_field (given
, 24, 24) == 0)
5607 && (arm_decode_field (given
, 21, 21) == 0))
5614 case MVE_VCVT_FP_FIX_VEC
:
5615 return (arm_decode_field (given
, 16, 21) & 0x38) == 0;
5620 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5622 if ((cmode
& 1) == 0)
5624 else if ((cmode
& 0xc) == 0xc)
5632 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5634 if ((cmode
& 9) == 1)
5636 else if ((cmode
& 5) == 1)
5638 else if ((cmode
& 0xe) == 0xe)
5644 case MVE_VMOV_IMM_TO_VEC
:
5645 if ((arm_decode_field (given
, 5, 5) == 1)
5646 && (arm_decode_field (given
, 8, 11) != 0xe))
5653 unsigned long size
= arm_decode_field (given
, 19, 20);
5654 if ((size
== 0) || (size
== 3))
5675 if (arm_decode_field (given
, 18, 19) == 3)
5681 case MVE_VRMLSLDAVH
:
5684 if (arm_decode_field (given
, 20, 22) == 7)
5689 case MVE_VRMLALDAVH
:
5690 if ((arm_decode_field (given
, 20, 22) & 6) == 6)
5697 if ((arm_decode_field (given
, 20, 21) == 3)
5698 || (arm_decode_field (given
, 1, 3) == 7))
5705 if (arm_decode_field (given
, 16, 18) == 0)
5707 unsigned long sz
= arm_decode_field (given
, 19, 20);
5709 if ((sz
== 1) || (sz
== 2))
5724 if (arm_decode_field (given
, 19, 21) == 0)
5730 if (arm_decode_field (given
, 16, 19) == 0xf)
5746 if (arm_decode_field (given
, 9, 11) == 0x7)
5754 unsigned long rm
, rn
;
5755 rm
= arm_decode_field (given
, 0, 3);
5756 rn
= arm_decode_field (given
, 16, 19);
5758 if (rm
== 0xf && rn
== 0xf)
5761 else if (rn
== rm
&& rn
!= 0xf)
5767 if (arm_decode_field (given
, 0, 3) == 0xd)
5770 else if (matched_insn
== MVE_CSNEG
)
5771 if (arm_decode_field (given
, 0, 3) == arm_decode_field (given
, 16, 19))
5776 case MVE_VADD_FP_T1
:
5777 case MVE_VADD_FP_T2
:
5778 case MVE_VADD_VEC_T1
:
5785 print_mve_vld_str_addr (struct disassemble_info
*info
,
5786 unsigned long given
,
5787 enum mve_instructions matched_insn
)
5789 void *stream
= info
->stream
;
5790 fprintf_ftype func
= info
->fprintf_func
;
5792 unsigned long p
, w
, gpr
, imm
, add
, mod_imm
;
5794 imm
= arm_decode_field (given
, 0, 6);
5797 switch (matched_insn
)
5801 gpr
= arm_decode_field (given
, 16, 18);
5806 gpr
= arm_decode_field (given
, 16, 18);
5812 gpr
= arm_decode_field (given
, 16, 19);
5818 gpr
= arm_decode_field (given
, 16, 19);
5824 gpr
= arm_decode_field (given
, 16, 19);
5831 p
= arm_decode_field (given
, 24, 24);
5832 w
= arm_decode_field (given
, 21, 21);
5834 add
= arm_decode_field (given
, 23, 23);
5838 /* Don't print anything for '+' as it is implied. */
5848 func (stream
, "[%s, #%s%lu]", arm_regnames
[gpr
], add_sub
, mod_imm
);
5849 /* Pre-indexed mode. */
5851 func (stream
, "[%s, #%s%lu]!", arm_regnames
[gpr
], add_sub
, mod_imm
);
5853 else if ((p
== 0) && (w
== 1))
5854 /* Post-index mode. */
5855 func (stream
, "[%s], #%s%lu", arm_regnames
[gpr
], add_sub
, mod_imm
);
5858 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5859 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5860 this encoding is undefined. */
5863 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
5864 enum mve_undefined
*undefined_code
)
5866 *undefined_code
= UNDEF_NONE
;
5868 switch (matched_insn
)
5871 if (arm_decode_field_multiple (given
, 5, 5, 22, 22) == 3)
5873 *undefined_code
= UNDEF_SIZE_3
;
5881 case MVE_VMUL_VEC_T1
:
5883 case MVE_VADD_VEC_T1
:
5884 case MVE_VSUB_VEC_T1
:
5885 case MVE_VQDMULH_T1
:
5886 case MVE_VQRDMULH_T2
:
5890 if (arm_decode_field (given
, 20, 21) == 3)
5892 *undefined_code
= UNDEF_SIZE_3
;
5899 if (arm_decode_field (given
, 7, 8) == 3)
5901 *undefined_code
= UNDEF_SIZE_3
;
5908 if (arm_decode_field (given
, 7, 8) <= 1)
5910 *undefined_code
= UNDEF_SIZE_LE_1
;
5917 if ((arm_decode_field (given
, 7, 8) == 0))
5919 *undefined_code
= UNDEF_SIZE_0
;
5926 if ((arm_decode_field (given
, 7, 8) <= 1))
5928 *undefined_code
= UNDEF_SIZE_LE_1
;
5934 case MVE_VLDRB_GATHER_T1
:
5935 if (arm_decode_field (given
, 7, 8) == 3)
5937 *undefined_code
= UNDEF_SIZE_3
;
5940 else if ((arm_decode_field (given
, 28, 28) == 0)
5941 && (arm_decode_field (given
, 7, 8) == 0))
5943 *undefined_code
= UNDEF_NOT_UNS_SIZE_0
;
5949 case MVE_VLDRH_GATHER_T2
:
5950 if (arm_decode_field (given
, 7, 8) == 3)
5952 *undefined_code
= UNDEF_SIZE_3
;
5955 else if ((arm_decode_field (given
, 28, 28) == 0)
5956 && (arm_decode_field (given
, 7, 8) == 1))
5958 *undefined_code
= UNDEF_NOT_UNS_SIZE_1
;
5961 else if (arm_decode_field (given
, 7, 8) == 0)
5963 *undefined_code
= UNDEF_SIZE_0
;
5969 case MVE_VLDRW_GATHER_T3
:
5970 if (arm_decode_field (given
, 7, 8) != 2)
5972 *undefined_code
= UNDEF_SIZE_NOT_2
;
5975 else if (arm_decode_field (given
, 28, 28) == 0)
5977 *undefined_code
= UNDEF_NOT_UNSIGNED
;
5983 case MVE_VLDRD_GATHER_T4
:
5984 if (arm_decode_field (given
, 7, 8) != 3)
5986 *undefined_code
= UNDEF_SIZE_NOT_3
;
5989 else if (arm_decode_field (given
, 28, 28) == 0)
5991 *undefined_code
= UNDEF_NOT_UNSIGNED
;
5997 case MVE_VSTRB_SCATTER_T1
:
5998 if (arm_decode_field (given
, 7, 8) == 3)
6000 *undefined_code
= UNDEF_SIZE_3
;
6006 case MVE_VSTRH_SCATTER_T2
:
6008 unsigned long size
= arm_decode_field (given
, 7, 8);
6011 *undefined_code
= UNDEF_SIZE_3
;
6016 *undefined_code
= UNDEF_SIZE_0
;
6023 case MVE_VSTRW_SCATTER_T3
:
6024 if (arm_decode_field (given
, 7, 8) != 2)
6026 *undefined_code
= UNDEF_SIZE_NOT_2
;
6032 case MVE_VSTRD_SCATTER_T4
:
6033 if (arm_decode_field (given
, 7, 8) != 3)
6035 *undefined_code
= UNDEF_SIZE_NOT_3
;
6041 case MVE_VCVT_FP_FIX_VEC
:
6043 unsigned long imm6
= arm_decode_field (given
, 16, 21);
6044 if ((imm6
& 0x20) == 0)
6046 *undefined_code
= UNDEF_VCVT_IMM6
;
6050 if ((arm_decode_field (given
, 9, 9) == 0)
6051 && ((imm6
& 0x30) == 0x20))
6053 *undefined_code
= UNDEF_VCVT_FSI_IMM6
;
6062 case MVE_VCVT_BETWEEN_FP_INT
:
6063 case MVE_VCVT_FROM_FP_TO_INT
:
6065 unsigned long size
= arm_decode_field (given
, 18, 19);
6068 *undefined_code
= UNDEF_SIZE_0
;
6073 *undefined_code
= UNDEF_SIZE_3
;
6080 case MVE_VMOV_VEC_LANE_TO_GP
:
6082 unsigned long op1
= arm_decode_field (given
, 21, 22);
6083 unsigned long op2
= arm_decode_field (given
, 5, 6);
6084 unsigned long u
= arm_decode_field (given
, 23, 23);
6086 if ((op2
== 0) && (u
== 1))
6088 if ((op1
== 0) || (op1
== 1))
6090 *undefined_code
= UNDEF_BAD_U_OP1_OP2
;
6098 if ((op1
== 0) || (op1
== 1))
6100 *undefined_code
= UNDEF_BAD_OP1_OP2
;
6110 case MVE_VMOV_GP_TO_VEC_LANE
:
6111 if (arm_decode_field (given
, 5, 6) == 2)
6113 unsigned long op1
= arm_decode_field (given
, 21, 22);
6114 if ((op1
== 0) || (op1
== 1))
6116 *undefined_code
= UNDEF_BAD_OP1_OP2
;
6125 case MVE_VMOV_VEC_TO_VEC
:
6126 if ((arm_decode_field (given
, 5, 5) == 1)
6127 || (arm_decode_field (given
, 22, 22) == 1))
6131 case MVE_VMOV_IMM_TO_VEC
:
6132 if (arm_decode_field (given
, 5, 5) == 0)
6134 unsigned long cmode
= arm_decode_field (given
, 8, 11);
6136 if (((cmode
& 9) == 1) || ((cmode
& 5) == 1))
6138 *undefined_code
= UNDEF_OP_0_BAD_CMODE
;
6149 if (arm_decode_field (given
, 18, 19) == 2)
6151 *undefined_code
= UNDEF_SIZE_2
;
6157 case MVE_VRMLALDAVH
:
6158 case MVE_VMLADAV_T1
:
6159 case MVE_VMLADAV_T2
:
6161 if ((arm_decode_field (given
, 28, 28) == 1)
6162 && (arm_decode_field (given
, 12, 12) == 1))
6164 *undefined_code
= UNDEF_XCHG_UNS
;
6175 unsigned long sz
= arm_decode_field (given
, 19, 20);
6178 else if ((sz
& 2) == 2)
6182 *undefined_code
= UNDEF_SIZE
;
6196 unsigned long sz
= arm_decode_field (given
, 19, 21);
6199 else if ((sz
& 6) == 2)
6201 else if ((sz
& 4) == 4)
6205 *undefined_code
= UNDEF_SIZE
;
6212 if (arm_decode_field (given
, 19, 20) == 0)
6214 *undefined_code
= UNDEF_SIZE_0
;
6221 if (arm_decode_field (given
, 18, 19) == 3)
6223 *undefined_code
= UNDEF_SIZE_3
;
6234 if (arm_decode_field (given
, 18, 19) == 3)
6236 *undefined_code
= UNDEF_SIZE_3
;
6243 if (arm_decode_field (given
, 18, 19) == 0)
6247 *undefined_code
= UNDEF_SIZE_NOT_0
;
6253 unsigned long size
= arm_decode_field (given
, 18, 19);
6254 if ((size
& 2) == 2)
6256 *undefined_code
= UNDEF_SIZE_2
;
6264 if (arm_decode_field (given
, 18, 19) != 3)
6268 *undefined_code
= UNDEF_SIZE_3
;
6277 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6278 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6279 why this encoding is unpredictable. */
6282 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
6283 enum mve_unpredictable
*unpredictable_code
)
6285 *unpredictable_code
= UNPRED_NONE
;
6287 switch (matched_insn
)
6289 case MVE_VCMP_FP_T2
:
6291 if ((arm_decode_field (given
, 12, 12) == 0)
6292 && (arm_decode_field (given
, 5, 5) == 1))
6294 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
6300 case MVE_VPT_VEC_T4
:
6301 case MVE_VPT_VEC_T5
:
6302 case MVE_VPT_VEC_T6
:
6303 case MVE_VCMP_VEC_T4
:
6304 case MVE_VCMP_VEC_T5
:
6305 case MVE_VCMP_VEC_T6
:
6306 if (arm_decode_field (given
, 0, 3) == 0xd)
6308 *unpredictable_code
= UNPRED_R13
;
6316 unsigned long gpr
= arm_decode_field (given
, 12, 15);
6319 *unpredictable_code
= UNPRED_R13
;
6322 else if (gpr
== 0xf)
6324 *unpredictable_code
= UNPRED_R15
;
6333 case MVE_VMUL_FP_T2
:
6334 case MVE_VMUL_VEC_T2
:
6337 case MVE_VADD_FP_T2
:
6338 case MVE_VSUB_FP_T2
:
6339 case MVE_VADD_VEC_T2
:
6340 case MVE_VSUB_VEC_T2
:
6350 case MVE_VQDMULH_T3
:
6351 case MVE_VQRDMULH_T4
:
6353 case MVE_VFMA_FP_SCALAR
:
6354 case MVE_VFMAS_FP_SCALAR
:
6358 unsigned long gpr
= arm_decode_field (given
, 0, 3);
6361 *unpredictable_code
= UNPRED_R13
;
6364 else if (gpr
== 0xf)
6366 *unpredictable_code
= UNPRED_R15
;
6376 unsigned long rn
= arm_decode_field (given
, 16, 19);
6378 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6380 *unpredictable_code
= UNPRED_R13_AND_WB
;
6386 *unpredictable_code
= UNPRED_R15
;
6390 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 6)
6392 *unpredictable_code
= UNPRED_Q_GT_6
;
6402 unsigned long rn
= arm_decode_field (given
, 16, 19);
6404 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6406 *unpredictable_code
= UNPRED_R13_AND_WB
;
6412 *unpredictable_code
= UNPRED_R15
;
6416 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 4)
6418 *unpredictable_code
= UNPRED_Q_GT_4
;
6432 unsigned long rn
= arm_decode_field (given
, 16, 19);
6434 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6436 *unpredictable_code
= UNPRED_R13_AND_WB
;
6441 *unpredictable_code
= UNPRED_R15
;
6448 case MVE_VLDRB_GATHER_T1
:
6449 if (arm_decode_field (given
, 0, 0) == 1)
6451 *unpredictable_code
= UNPRED_OS
;
6456 /* To handle common code with T2-T4 variants. */
6457 case MVE_VLDRH_GATHER_T2
:
6458 case MVE_VLDRW_GATHER_T3
:
6459 case MVE_VLDRD_GATHER_T4
:
6461 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6462 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6466 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6470 if (arm_decode_field (given
, 16, 19) == 0xf)
6472 *unpredictable_code
= UNPRED_R15
;
6479 case MVE_VLDRW_GATHER_T5
:
6480 case MVE_VLDRD_GATHER_T6
:
6482 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6483 unsigned long qm
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6487 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6494 case MVE_VSTRB_SCATTER_T1
:
6495 if (arm_decode_field (given
, 16, 19) == 0xf)
6497 *unpredictable_code
= UNPRED_R15
;
6500 else if (arm_decode_field (given
, 0, 0) == 1)
6502 *unpredictable_code
= UNPRED_OS
;
6508 case MVE_VSTRH_SCATTER_T2
:
6509 case MVE_VSTRW_SCATTER_T3
:
6510 case MVE_VSTRD_SCATTER_T4
:
6511 if (arm_decode_field (given
, 16, 19) == 0xf)
6513 *unpredictable_code
= UNPRED_R15
;
6519 case MVE_VMOV2_VEC_LANE_TO_GP
:
6520 case MVE_VMOV2_GP_TO_VEC_LANE
:
6521 case MVE_VCVT_BETWEEN_FP_INT
:
6522 case MVE_VCVT_FROM_FP_TO_INT
:
6524 unsigned long rt
= arm_decode_field (given
, 0, 3);
6525 unsigned long rt2
= arm_decode_field (given
, 16, 19);
6527 if ((rt
== 0xd) || (rt2
== 0xd))
6529 *unpredictable_code
= UNPRED_R13
;
6532 else if ((rt
== 0xf) || (rt2
== 0xf))
6534 *unpredictable_code
= UNPRED_R15
;
6539 *unpredictable_code
= UNPRED_GP_REGS_EQUAL
;
6548 case MVE_VMAXNMV_FP
:
6549 case MVE_VMAXNMAV_FP
:
6550 case MVE_VMINNMV_FP
:
6551 case MVE_VMINNMAV_FP
:
6555 case MVE_VMOV_HFP_TO_GP
:
6556 case MVE_VMOV_GP_TO_VEC_LANE
:
6557 case MVE_VMOV_VEC_LANE_TO_GP
:
6559 unsigned long rda
= arm_decode_field (given
, 12, 15);
6562 *unpredictable_code
= UNPRED_R13
;
6565 else if (rda
== 0xf)
6567 *unpredictable_code
= UNPRED_R15
;
6580 if (arm_decode_field (given
, 20, 21) == 2)
6582 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6583 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6584 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6586 if ((Qd
== Qn
) || (Qd
== Qm
))
6588 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6599 case MVE_VQDMULL_T1
:
6605 if (arm_decode_field (given
, 28, 28) == 1)
6607 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6608 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6609 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6611 if ((Qd
== Qn
) || (Qd
== Qm
))
6613 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6623 case MVE_VQDMULL_T2
:
6625 unsigned long gpr
= arm_decode_field (given
, 0, 3);
6628 *unpredictable_code
= UNPRED_R13
;
6631 else if (gpr
== 0xf)
6633 *unpredictable_code
= UNPRED_R15
;
6637 if (arm_decode_field (given
, 28, 28) == 1)
6640 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
6641 unsigned long Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6645 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6656 case MVE_VRMLSLDAVH
:
6659 if (arm_decode_field (given
, 20, 22) == 6)
6661 *unpredictable_code
= UNPRED_R13
;
6669 if (arm_decode_field (given
, 1, 3) == 6)
6671 *unpredictable_code
= UNPRED_R13
;
6680 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6681 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6682 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 21) == 2)
6684 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6693 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6694 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6695 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 20) == 1)
6697 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6710 if (arm_decode_field (given
, 20, 20) == 1)
6712 Qda
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6713 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6714 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6716 if ((Qda
== Qn
) || (Qda
== Qm
))
6718 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6730 if (arm_decode_field (given
, 16, 19) == 0xd)
6732 *unpredictable_code
= UNPRED_R13
;
6740 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6741 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 6, 6);
6745 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6764 unsigned long gpr
= arm_decode_field (given
, 9, 11);
6765 gpr
= ((gpr
<< 1) | 1);
6768 *unpredictable_code
= UNPRED_R13
;
6771 else if (gpr
== 0xf)
6773 *unpredictable_code
= UNPRED_R15
;
6786 print_mve_vmov_index (struct disassemble_info
*info
, unsigned long given
)
6788 unsigned long op1
= arm_decode_field (given
, 21, 22);
6789 unsigned long op2
= arm_decode_field (given
, 5, 6);
6790 unsigned long h
= arm_decode_field (given
, 16, 16);
6791 unsigned long index_operand
, esize
, targetBeat
, idx
;
6792 void *stream
= info
->stream
;
6793 fprintf_ftype func
= info
->fprintf_func
;
6795 if ((op1
& 0x2) == 0x2)
6797 index_operand
= op2
;
6800 else if (((op1
& 0x2) == 0x0) && ((op2
& 0x1) == 0x1))
6802 index_operand
= op2
>> 1;
6805 else if (((op1
& 0x2) == 0) && ((op2
& 0x3) == 0))
6812 func (stream
, "<undefined index>");
6816 targetBeat
= (op1
& 0x1) | (h
<< 1);
6817 idx
= index_operand
+ targetBeat
* (32/esize
);
6819 func (stream
, "%lu", idx
);
6822 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6823 in length and integer of floating-point type. */
6825 print_simd_imm8 (struct disassemble_info
*info
, unsigned long given
,
6826 unsigned int ibit_loc
, const struct mopcode32
*insn
)
6829 int cmode
= (given
>> 8) & 0xf;
6830 int op
= (given
>> 5) & 0x1;
6831 unsigned long value
= 0, hival
= 0;
6835 void *stream
= info
->stream
;
6836 fprintf_ftype func
= info
->fprintf_func
;
6838 /* On Neon the 'i' bit is at bit 24, on mve it is
6840 bits
|= ((given
>> ibit_loc
) & 1) << 7;
6841 bits
|= ((given
>> 16) & 7) << 4;
6842 bits
|= ((given
>> 0) & 15) << 0;
6846 shift
= (cmode
>> 1) & 3;
6847 value
= (unsigned long) bits
<< (8 * shift
);
6850 else if (cmode
< 12)
6852 shift
= (cmode
>> 1) & 1;
6853 value
= (unsigned long) bits
<< (8 * shift
);
6856 else if (cmode
< 14)
6858 shift
= (cmode
& 1) + 1;
6859 value
= (unsigned long) bits
<< (8 * shift
);
6860 value
|= (1ul << (8 * shift
)) - 1;
6863 else if (cmode
== 14)
6867 /* Bit replication into bytes. */
6873 for (ix
= 7; ix
>= 0; ix
--)
6875 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
6877 value
= (value
<< 8) | mask
;
6879 hival
= (hival
<< 8) | mask
;
6885 /* Byte replication. */
6886 value
= (unsigned long) bits
;
6892 /* Floating point encoding. */
6895 value
= (unsigned long) (bits
& 0x7f) << 19;
6896 value
|= (unsigned long) (bits
& 0x80) << 24;
6897 tmp
= bits
& 0x40 ? 0x3c : 0x40;
6898 value
|= (unsigned long) tmp
<< 24;
6904 func (stream
, "<illegal constant %.8x:%x:%x>",
6910 // printU determines whether the immediate value should be printed as
6912 unsigned printU
= 0;
6913 switch (insn
->mve_op
)
6917 // We want this for instructions that don't have a 'signed' type
6921 case MVE_VMOV_IMM_TO_VEC
:
6928 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
6935 : "#%ld\t; 0x%.4lx", value
, value
);
6941 unsigned char valbytes
[4];
6944 /* Do this a byte at a time so we don't have to
6945 worry about the host's endianness. */
6946 valbytes
[0] = value
& 0xff;
6947 valbytes
[1] = (value
>> 8) & 0xff;
6948 valbytes
[2] = (value
>> 16) & 0xff;
6949 valbytes
[3] = (value
>> 24) & 0xff;
6951 floatformat_to_double
6952 (& floatformat_ieee_single_little
, valbytes
,
6955 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
6962 : "#%ld\t; 0x%.8lx",
6963 (long) (((value
& 0x80000000L
) != 0)
6965 ? value
| ~0xffffffffL
: value
),
6970 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
6980 print_mve_undefined (struct disassemble_info
*info
,
6981 enum mve_undefined undefined_code
)
6983 void *stream
= info
->stream
;
6984 fprintf_ftype func
= info
->fprintf_func
;
6986 func (stream
, "\t\tundefined instruction: ");
6988 switch (undefined_code
)
6991 func (stream
, "illegal size");
6995 func (stream
, "size equals zero");
6999 func (stream
, "size equals two");
7003 func (stream
, "size equals three");
7006 case UNDEF_SIZE_LE_1
:
7007 func (stream
, "size <= 1");
7010 case UNDEF_SIZE_NOT_0
:
7011 func (stream
, "size not equal to 0");
7014 case UNDEF_SIZE_NOT_2
:
7015 func (stream
, "size not equal to 2");
7018 case UNDEF_SIZE_NOT_3
:
7019 func (stream
, "size not equal to 3");
7022 case UNDEF_NOT_UNS_SIZE_0
:
7023 func (stream
, "not unsigned and size = zero");
7026 case UNDEF_NOT_UNS_SIZE_1
:
7027 func (stream
, "not unsigned and size = one");
7030 case UNDEF_NOT_UNSIGNED
:
7031 func (stream
, "not unsigned");
7034 case UNDEF_VCVT_IMM6
:
7035 func (stream
, "invalid imm6");
7038 case UNDEF_VCVT_FSI_IMM6
:
7039 func (stream
, "fsi = 0 and invalid imm6");
7042 case UNDEF_BAD_OP1_OP2
:
7043 func (stream
, "bad size with op2 = 2 and op1 = 0 or 1");
7046 case UNDEF_BAD_U_OP1_OP2
:
7047 func (stream
, "unsigned with op2 = 0 and op1 = 0 or 1");
7050 case UNDEF_OP_0_BAD_CMODE
:
7051 func (stream
, "op field equal 0 and bad cmode");
7054 case UNDEF_XCHG_UNS
:
7055 func (stream
, "exchange and unsigned together");
7065 print_mve_unpredictable (struct disassemble_info
*info
,
7066 enum mve_unpredictable unpredict_code
)
7068 void *stream
= info
->stream
;
7069 fprintf_ftype func
= info
->fprintf_func
;
7071 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
7073 switch (unpredict_code
)
7075 case UNPRED_IT_BLOCK
:
7076 func (stream
, "mve instruction in it block");
7079 case UNPRED_FCA_0_FCB_1
:
7080 func (stream
, "condition bits, fca = 0 and fcb = 1");
7084 func (stream
, "use of r13 (sp)");
7088 func (stream
, "use of r15 (pc)");
7092 func (stream
, "start register block > r4");
7096 func (stream
, "start register block > r6");
7099 case UNPRED_R13_AND_WB
:
7100 func (stream
, "use of r13 and write back");
7103 case UNPRED_Q_REGS_EQUAL
:
7105 "same vector register used for destination and other operand");
7109 func (stream
, "use of offset scaled");
7112 case UNPRED_GP_REGS_EQUAL
:
7113 func (stream
, "same general-purpose register used for both operands");
7116 case UNPRED_Q_REGS_EQ_AND_SIZE_1
:
7117 func (stream
, "use of identical q registers and size = 1");
7120 case UNPRED_Q_REGS_EQ_AND_SIZE_2
:
7121 func (stream
, "use of identical q registers and size = 1");
7129 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
7132 print_mve_register_blocks (struct disassemble_info
*info
,
7133 unsigned long given
,
7134 enum mve_instructions matched_insn
)
7136 void *stream
= info
->stream
;
7137 fprintf_ftype func
= info
->fprintf_func
;
7139 unsigned long q_reg_start
= arm_decode_field_multiple (given
,
7142 switch (matched_insn
)
7146 if (q_reg_start
<= 6)
7147 func (stream
, "{q%ld, q%ld}", q_reg_start
, q_reg_start
+ 1);
7149 func (stream
, "<illegal reg q%ld>", q_reg_start
);
7154 if (q_reg_start
<= 4)
7155 func (stream
, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start
,
7156 q_reg_start
+ 1, q_reg_start
+ 2,
7159 func (stream
, "<illegal reg q%ld>", q_reg_start
);
7168 print_mve_rounding_mode (struct disassemble_info
*info
,
7169 unsigned long given
,
7170 enum mve_instructions matched_insn
)
7172 void *stream
= info
->stream
;
7173 fprintf_ftype func
= info
->fprintf_func
;
7175 switch (matched_insn
)
7177 case MVE_VCVT_FROM_FP_TO_INT
:
7179 switch (arm_decode_field (given
, 8, 9))
7205 switch (arm_decode_field (given
, 7, 9))
7244 print_mve_vcvt_size (struct disassemble_info
*info
,
7245 unsigned long given
,
7246 enum mve_instructions matched_insn
)
7248 unsigned long mode
= 0;
7249 void *stream
= info
->stream
;
7250 fprintf_ftype func
= info
->fprintf_func
;
7252 switch (matched_insn
)
7254 case MVE_VCVT_FP_FIX_VEC
:
7256 mode
= (((given
& 0x200) >> 7)
7257 | ((given
& 0x10000000) >> 27)
7258 | ((given
& 0x100) >> 8));
7263 func (stream
, "f16.s16");
7267 func (stream
, "s16.f16");
7271 func (stream
, "f16.u16");
7275 func (stream
, "u16.f16");
7279 func (stream
, "f32.s32");
7283 func (stream
, "s32.f32");
7287 func (stream
, "f32.u32");
7291 func (stream
, "u32.f32");
7299 case MVE_VCVT_BETWEEN_FP_INT
:
7301 unsigned long size
= arm_decode_field (given
, 18, 19);
7302 unsigned long op
= arm_decode_field (given
, 7, 8);
7309 func (stream
, "f16.s16");
7313 func (stream
, "f16.u16");
7317 func (stream
, "s16.f16");
7321 func (stream
, "u16.f16");
7333 func (stream
, "f32.s32");
7337 func (stream
, "f32.u32");
7341 func (stream
, "s32.f32");
7345 func (stream
, "u32.f32");
7352 case MVE_VCVT_FP_HALF_FP
:
7354 unsigned long op
= arm_decode_field (given
, 28, 28);
7356 func (stream
, "f16.f32");
7358 func (stream
, "f32.f16");
7362 case MVE_VCVT_FROM_FP_TO_INT
:
7364 unsigned long size
= arm_decode_field_multiple (given
, 7, 7, 18, 19);
7369 func (stream
, "s16.f16");
7373 func (stream
, "u16.f16");
7377 func (stream
, "s32.f32");
7381 func (stream
, "u32.f32");
7396 print_mve_rotate (struct disassemble_info
*info
, unsigned long rot
,
7397 unsigned long rot_width
)
7399 void *stream
= info
->stream
;
7400 fprintf_ftype func
= info
->fprintf_func
;
7407 func (stream
, "90");
7410 func (stream
, "270");
7416 else if (rot_width
== 2)
7424 func (stream
, "90");
7427 func (stream
, "180");
7430 func (stream
, "270");
7439 print_instruction_predicate (struct disassemble_info
*info
)
7441 void *stream
= info
->stream
;
7442 fprintf_ftype func
= info
->fprintf_func
;
7444 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
7446 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
7451 print_mve_size (struct disassemble_info
*info
,
7453 enum mve_instructions matched_insn
)
7455 void *stream
= info
->stream
;
7456 fprintf_ftype func
= info
->fprintf_func
;
7458 switch (matched_insn
)
7464 case MVE_VADD_VEC_T1
:
7465 case MVE_VADD_VEC_T2
:
7471 case MVE_VCMP_VEC_T1
:
7472 case MVE_VCMP_VEC_T2
:
7473 case MVE_VCMP_VEC_T3
:
7474 case MVE_VCMP_VEC_T4
:
7475 case MVE_VCMP_VEC_T5
:
7476 case MVE_VCMP_VEC_T6
:
7489 case MVE_VLDRB_GATHER_T1
:
7490 case MVE_VLDRH_GATHER_T2
:
7491 case MVE_VLDRW_GATHER_T3
:
7492 case MVE_VLDRD_GATHER_T4
:
7505 case MVE_VMUL_VEC_T1
:
7506 case MVE_VMUL_VEC_T2
:
7512 case MVE_VPT_VEC_T1
:
7513 case MVE_VPT_VEC_T2
:
7514 case MVE_VPT_VEC_T3
:
7515 case MVE_VPT_VEC_T4
:
7516 case MVE_VPT_VEC_T5
:
7517 case MVE_VPT_VEC_T6
:
7529 case MVE_VQDMULH_T1
:
7530 case MVE_VQRDMULH_T2
:
7531 case MVE_VQDMULH_T3
:
7532 case MVE_VQRDMULH_T4
:
7551 case MVE_VSTRB_SCATTER_T1
:
7552 case MVE_VSTRH_SCATTER_T2
:
7553 case MVE_VSTRW_SCATTER_T3
:
7556 case MVE_VSUB_VEC_T1
:
7557 case MVE_VSUB_VEC_T2
:
7559 func (stream
, "%s", mve_vec_sizename
[size
]);
7561 func (stream
, "<undef size>");
7565 case MVE_VADD_FP_T1
:
7566 case MVE_VADD_FP_T2
:
7567 case MVE_VSUB_FP_T1
:
7568 case MVE_VSUB_FP_T2
:
7569 case MVE_VCMP_FP_T1
:
7570 case MVE_VCMP_FP_T2
:
7571 case MVE_VFMA_FP_SCALAR
:
7574 case MVE_VFMAS_FP_SCALAR
:
7576 case MVE_VMAXNMA_FP
:
7577 case MVE_VMAXNMV_FP
:
7578 case MVE_VMAXNMAV_FP
:
7580 case MVE_VMINNMA_FP
:
7581 case MVE_VMINNMV_FP
:
7582 case MVE_VMINNMAV_FP
:
7583 case MVE_VMUL_FP_T1
:
7584 case MVE_VMUL_FP_T2
:
7588 func (stream
, "32");
7590 func (stream
, "16");
7596 case MVE_VMLADAV_T1
:
7598 case MVE_VMLSDAV_T1
:
7601 case MVE_VQDMULL_T1
:
7602 case MVE_VQDMULL_T2
:
7606 func (stream
, "16");
7608 func (stream
, "32");
7615 func (stream
, "16");
7622 func (stream
, "32");
7625 func (stream
, "16");
7635 case MVE_VMOV_GP_TO_VEC_LANE
:
7636 case MVE_VMOV_VEC_LANE_TO_GP
:
7640 func (stream
, "32");
7645 func (stream
, "16");
7648 case 8: case 9: case 10: case 11:
7649 case 12: case 13: case 14: case 15:
7658 case MVE_VMOV_IMM_TO_VEC
:
7661 case 0: case 4: case 8:
7662 case 12: case 24: case 26:
7663 func (stream
, "i32");
7666 func (stream
, "i16");
7669 func (stream
, "i8");
7672 func (stream
, "i64");
7675 func (stream
, "f32");
7682 case MVE_VMULL_POLY
:
7684 func (stream
, "p8");
7686 func (stream
, "p16");
7692 case 0: case 2: case 4:
7693 case 6: case 12: case 13:
7694 func (stream
, "32");
7698 func (stream
, "16");
7712 func (stream
, "32");
7716 func (stream
, "16");
7734 func (stream
, "16");
7738 func (stream
, "32");
7763 func (stream
, "16");
7766 case 4: case 5: case 6: case 7:
7767 func (stream
, "32");
7782 print_mve_shift_n (struct disassemble_info
*info
, long given
,
7783 enum mve_instructions matched_insn
)
7785 void *stream
= info
->stream
;
7786 fprintf_ftype func
= info
->fprintf_func
;
7789 = matched_insn
== MVE_VQSHL_T2
7790 || matched_insn
== MVE_VQSHLU_T3
7791 || matched_insn
== MVE_VSHL_T1
7792 || matched_insn
== MVE_VSHLL_T1
7793 || matched_insn
== MVE_VSLI
;
7795 unsigned imm6
= (given
& 0x3f0000) >> 16;
7797 if (matched_insn
== MVE_VSHLL_T1
)
7800 unsigned shiftAmount
= 0;
7801 if ((imm6
& 0x20) != 0)
7802 shiftAmount
= startAt0
? imm6
- 32 : 64 - imm6
;
7803 else if ((imm6
& 0x10) != 0)
7804 shiftAmount
= startAt0
? imm6
- 16 : 32 - imm6
;
7805 else if ((imm6
& 0x08) != 0)
7806 shiftAmount
= startAt0
? imm6
- 8 : 16 - imm6
;
7808 print_mve_undefined (info
, UNDEF_SIZE_0
);
7810 func (stream
, "%u", shiftAmount
);
7814 print_vec_condition (struct disassemble_info
*info
, long given
,
7815 enum mve_instructions matched_insn
)
7817 void *stream
= info
->stream
;
7818 fprintf_ftype func
= info
->fprintf_func
;
7821 switch (matched_insn
)
7824 case MVE_VCMP_FP_T1
:
7825 vec_cond
= (((given
& 0x1000) >> 10)
7826 | ((given
& 1) << 1)
7827 | ((given
& 0x0080) >> 7));
7828 func (stream
, "%s",vec_condnames
[vec_cond
]);
7832 case MVE_VCMP_FP_T2
:
7833 vec_cond
= (((given
& 0x1000) >> 10)
7834 | ((given
& 0x0020) >> 4)
7835 | ((given
& 0x0080) >> 7));
7836 func (stream
, "%s",vec_condnames
[vec_cond
]);
7839 case MVE_VPT_VEC_T1
:
7840 case MVE_VCMP_VEC_T1
:
7841 vec_cond
= (given
& 0x0080) >> 7;
7842 func (stream
, "%s",vec_condnames
[vec_cond
]);
7845 case MVE_VPT_VEC_T2
:
7846 case MVE_VCMP_VEC_T2
:
7847 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7848 func (stream
, "%s",vec_condnames
[vec_cond
]);
7851 case MVE_VPT_VEC_T3
:
7852 case MVE_VCMP_VEC_T3
:
7853 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
7854 func (stream
, "%s",vec_condnames
[vec_cond
]);
7857 case MVE_VPT_VEC_T4
:
7858 case MVE_VCMP_VEC_T4
:
7859 vec_cond
= (given
& 0x0080) >> 7;
7860 func (stream
, "%s",vec_condnames
[vec_cond
]);
7863 case MVE_VPT_VEC_T5
:
7864 case MVE_VCMP_VEC_T5
:
7865 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7866 func (stream
, "%s",vec_condnames
[vec_cond
]);
7869 case MVE_VPT_VEC_T6
:
7870 case MVE_VCMP_VEC_T6
:
7871 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
7872 func (stream
, "%s",vec_condnames
[vec_cond
]);
7887 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7888 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7889 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7890 #define PRE_BIT_SET (given & (1 << P_BIT))
7893 /* Print one coprocessor instruction on INFO->STREAM.
7894 Return TRUE if the instuction matched, FALSE if this is not a
7895 recognised coprocessor instruction. */
7898 print_insn_coprocessor_1 (const struct sopcode32
*opcodes
,
7900 struct disassemble_info
*info
,
7904 const struct sopcode32
*insn
;
7905 void *stream
= info
->stream
;
7906 fprintf_ftype func
= info
->fprintf_func
;
7908 unsigned long value
= 0;
7911 struct arm_private_data
*private_data
= info
->private_data
;
7912 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
7913 arm_feature_set arm_ext_v8_1m_main
=
7914 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
7916 allowed_arches
= private_data
->features
;
7918 for (insn
= opcodes
; insn
->assembler
; insn
++)
7920 unsigned long u_reg
= 16;
7921 bfd_boolean is_unpredictable
= FALSE
;
7922 signed long value_in_comment
= 0;
7925 if (ARM_FEATURE_ZERO (insn
->arch
))
7926 switch (insn
->value
)
7928 case SENTINEL_IWMMXT_START
:
7929 if (info
->mach
!= bfd_mach_arm_XScale
7930 && info
->mach
!= bfd_mach_arm_iWMMXt
7931 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
7934 while ((! ARM_FEATURE_ZERO (insn
->arch
))
7935 && insn
->value
!= SENTINEL_IWMMXT_END
);
7938 case SENTINEL_IWMMXT_END
:
7941 case SENTINEL_GENERIC_START
:
7942 allowed_arches
= private_data
->features
;
7950 value
= insn
->value
;
7951 cp_num
= (given
>> 8) & 0xf;
7955 /* The high 4 bits are 0xe for Arm conditional instructions, and
7956 0xe for arm unconditional instructions. The rest of the
7957 encoding is the same. */
7959 value
|= 0xe0000000;
7967 /* Only match unconditional instuctions against unconditional
7969 if ((given
& 0xf0000000) == 0xf0000000)
7976 cond
= (given
>> 28) & 0xf;
7982 if ((insn
->isa
== T32
&& !thumb
)
7983 || (insn
->isa
== ARM
&& thumb
))
7986 if ((given
& mask
) != value
)
7989 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
7992 if (insn
->value
== 0xfe000010 /* mcr2 */
7993 || insn
->value
== 0xfe100010 /* mrc2 */
7994 || insn
->value
== 0xfc100000 /* ldc2 */
7995 || insn
->value
== 0xfc000000) /* stc2 */
7997 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
7998 is_unpredictable
= TRUE
;
8000 /* Armv8.1-M Mainline FP & MVE instructions. */
8001 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
8002 && !ARM_CPU_IS_ANY (allowed_arches
)
8003 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
8007 else if (insn
->value
== 0x0e000000 /* cdp */
8008 || insn
->value
== 0xfe000000 /* cdp2 */
8009 || insn
->value
== 0x0e000010 /* mcr */
8010 || insn
->value
== 0x0e100010 /* mrc */
8011 || insn
->value
== 0x0c100000 /* ldc */
8012 || insn
->value
== 0x0c000000) /* stc */
8014 /* Floating-point instructions. */
8015 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
8018 /* Armv8.1-M Mainline FP & MVE instructions. */
8019 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
8020 && !ARM_CPU_IS_ANY (allowed_arches
)
8021 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
8024 else if ((insn
->value
== 0xec100f80 /* vldr (system register) */
8025 || insn
->value
== 0xec000f80) /* vstr (system register) */
8026 && arm_decode_field (given
, 24, 24) == 0
8027 && arm_decode_field (given
, 21, 21) == 0)
8028 /* If the P and W bits are both 0 then these encodings match the MVE
8029 VLDR and VSTR instructions, these are in a different table, so we
8030 don't let it match here. */
8033 for (c
= insn
->assembler
; *c
; c
++)
8037 const char mod
= *++c
;
8041 func (stream
, "%%");
8047 int rn
= (given
>> 16) & 0xf;
8048 bfd_vma offset
= given
& 0xff;
8051 offset
= given
& 0x7f;
8053 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8055 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
8057 /* Not unindexed. The offset is scaled. */
8059 /* vldr.16/vstr.16 will shift the address
8060 left by 1 bit only. */
8061 offset
= offset
* 2;
8063 offset
= offset
* 4;
8065 if (NEGATIVE_BIT_SET
)
8068 value_in_comment
= offset
;
8074 func (stream
, ", #%d]%s",
8076 WRITEBACK_BIT_SET
? "!" : "");
8077 else if (NEGATIVE_BIT_SET
)
8078 func (stream
, ", #-0]");
8086 if (WRITEBACK_BIT_SET
)
8089 func (stream
, ", #%d", (int) offset
);
8090 else if (NEGATIVE_BIT_SET
)
8091 func (stream
, ", #-0");
8095 func (stream
, ", {%s%d}",
8096 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
8098 value_in_comment
= offset
;
8101 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
8103 func (stream
, "\t; ");
8104 /* For unaligned PCs, apply off-by-alignment
8106 info
->print_address_func (offset
+ pc
8107 + info
->bytes_per_chunk
* 2
8116 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
8117 int offset
= (given
>> 1) & 0x3f;
8120 func (stream
, "{d%d}", regno
);
8121 else if (regno
+ offset
> 32)
8122 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
8124 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
8130 bfd_boolean single
= ((given
>> 8) & 1) == 0;
8131 char reg_prefix
= single
? 's' : 'd';
8132 int Dreg
= (given
>> 22) & 0x1;
8133 int Vdreg
= (given
>> 12) & 0xf;
8134 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
8135 : ((Dreg
<< 4) | Vdreg
);
8136 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
8137 int maxreg
= single
? 31 : 15;
8138 int topreg
= reg
+ num
- 1;
8141 func (stream
, "{VPR}");
8143 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
8144 else if (topreg
> maxreg
)
8145 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
8146 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
8148 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
8149 reg_prefix
, topreg
);
8154 if (cond
!= COND_UNCOND
)
8155 is_unpredictable
= TRUE
;
8159 if (cond
!= COND_UNCOND
&& cp_num
== 9)
8160 is_unpredictable
= TRUE
;
8162 func (stream
, "%s", arm_conditional
[cond
]);
8166 /* Print a Cirrus/DSP shift immediate. */
8167 /* Immediates are 7bit signed ints with bits 0..3 in
8168 bits 0..3 of opcode and bits 4..6 in bits 5..7
8173 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
8175 /* Is ``imm'' a negative number? */
8179 func (stream
, "%d", imm
);
8187 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
8192 func (stream
, "FPSCR");
8195 func (stream
, "FPSCR_nzcvqc");
8198 func (stream
, "VPR");
8201 func (stream
, "P0");
8204 func (stream
, "FPCXTNS");
8207 func (stream
, "FPCXTS");
8210 func (stream
, "<invalid reg %lu>", regno
);
8217 switch (given
& 0x00408000)
8234 switch (given
& 0x00080080)
8246 func (stream
, _("<illegal precision>"));
8252 switch (given
& 0x00408000)
8270 switch (given
& 0x60)
8286 case '0': case '1': case '2': case '3': case '4':
8287 case '5': case '6': case '7': case '8': case '9':
8291 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8297 is_unpredictable
= TRUE
;
8302 /* Eat the 'u' character. */
8306 is_unpredictable
= TRUE
;
8309 func (stream
, "%s", arm_regnames
[value
]);
8312 if (given
& (1 << 6))
8316 func (stream
, "d%ld", value
);
8321 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
8323 func (stream
, "q%ld", value
>> 1);
8326 func (stream
, "%ld", value
);
8327 value_in_comment
= value
;
8331 /* Converts immediate 8 bit back to float value. */
8332 unsigned floatVal
= (value
& 0x80) << 24
8333 | (value
& 0x3F) << 19
8334 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
8336 /* Quarter float have a maximum value of 31.0.
8337 Get floating point value multiplied by 1e7.
8338 The maximum value stays in limit of a 32-bit int. */
8340 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
8341 (16 + (value
& 0xF));
8343 if (!(decVal
% 1000000))
8344 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
8345 floatVal
, value
& 0x80 ? '-' : ' ',
8347 decVal
% 10000000 / 1000000);
8348 else if (!(decVal
% 10000))
8349 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
8350 floatVal
, value
& 0x80 ? '-' : ' ',
8352 decVal
% 10000000 / 10000);
8354 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
8355 floatVal
, value
& 0x80 ? '-' : ' ',
8356 decVal
/ 10000000, decVal
% 10000000);
8361 int from
= (given
& (1 << 7)) ? 32 : 16;
8362 func (stream
, "%ld", from
- value
);
8368 func (stream
, "#%s", arm_fp_const
[value
& 7]);
8370 func (stream
, "f%ld", value
);
8375 func (stream
, "%s", iwmmxt_wwnames
[value
]);
8377 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
8381 func (stream
, "%s", iwmmxt_regnames
[value
]);
8384 func (stream
, "%s", iwmmxt_cregnames
[value
]);
8388 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
8395 func (stream
, "eq");
8399 func (stream
, "vs");
8403 func (stream
, "ge");
8407 func (stream
, "gt");
8411 func (stream
, "??");
8419 func (stream
, "%c", *c
);
8423 if (value
== ((1ul << width
) - 1))
8424 func (stream
, "%c", *c
);
8427 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
8439 int single
= *c
++ == 'y';
8444 case '4': /* Sm pair */
8445 case '0': /* Sm, Dm */
8446 regno
= given
& 0x0000000f;
8450 regno
+= (given
>> 5) & 1;
8453 regno
+= ((given
>> 5) & 1) << 4;
8456 case '1': /* Sd, Dd */
8457 regno
= (given
>> 12) & 0x0000000f;
8461 regno
+= (given
>> 22) & 1;
8464 regno
+= ((given
>> 22) & 1) << 4;
8467 case '2': /* Sn, Dn */
8468 regno
= (given
>> 16) & 0x0000000f;
8472 regno
+= (given
>> 7) & 1;
8475 regno
+= ((given
>> 7) & 1) << 4;
8478 case '3': /* List */
8480 regno
= (given
>> 12) & 0x0000000f;
8484 regno
+= (given
>> 22) & 1;
8487 regno
+= ((given
>> 22) & 1) << 4;
8494 func (stream
, "%c%d", single
? 's' : 'd', regno
);
8498 int count
= given
& 0xff;
8505 func (stream
, "-%c%d",
8513 func (stream
, ", %c%d", single
? 's' : 'd',
8519 switch (given
& 0x00400100)
8521 case 0x00000000: func (stream
, "b"); break;
8522 case 0x00400000: func (stream
, "h"); break;
8523 case 0x00000100: func (stream
, "w"); break;
8524 case 0x00400100: func (stream
, "d"); break;
8532 /* given (20, 23) | given (0, 3) */
8533 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
8534 func (stream
, "%d", (int) value
);
8539 /* This is like the 'A' operator, except that if
8540 the width field "M" is zero, then the offset is
8541 *not* multiplied by four. */
8543 int offset
= given
& 0xff;
8544 int multiplier
= (given
& 0x00000100) ? 4 : 1;
8546 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8550 value_in_comment
= offset
* multiplier
;
8551 if (NEGATIVE_BIT_SET
)
8552 value_in_comment
= - value_in_comment
;
8558 func (stream
, ", #%s%d]%s",
8559 NEGATIVE_BIT_SET
? "-" : "",
8560 offset
* multiplier
,
8561 WRITEBACK_BIT_SET
? "!" : "");
8563 func (stream
, "], #%s%d",
8564 NEGATIVE_BIT_SET
? "-" : "",
8565 offset
* multiplier
);
8574 int imm4
= (given
>> 4) & 0xf;
8575 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
8576 int ubit
= ! NEGATIVE_BIT_SET
;
8577 const char *rm
= arm_regnames
[given
& 0xf];
8578 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
8584 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
8586 func (stream
, ", lsl #%d", imm4
);
8593 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
8595 func (stream
, ", lsl #%d", imm4
);
8597 if (puw_bits
== 5 || puw_bits
== 7)
8602 func (stream
, "INVALID");
8610 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
8611 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
8620 func (stream
, "%c", *c
);
8623 if (value_in_comment
> 32 || value_in_comment
< -16)
8624 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
8626 if (is_unpredictable
)
8627 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8635 print_insn_coprocessor (bfd_vma pc
,
8636 struct disassemble_info
*info
,
8640 return print_insn_coprocessor_1 (coprocessor_opcodes
,
8641 pc
, info
, given
, thumb
);
8645 print_insn_generic_coprocessor (bfd_vma pc
,
8646 struct disassemble_info
*info
,
8650 return print_insn_coprocessor_1 (generic_coprocessor_opcodes
,
8651 pc
, info
, given
, thumb
);
8654 /* Decodes and prints ARM addressing modes. Returns the offset
8655 used in the address, if any, if it is worthwhile printing the
8656 offset as a hexadecimal value in a comment at the end of the
8657 line of disassembly. */
8660 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8662 void *stream
= info
->stream
;
8663 fprintf_ftype func
= info
->fprintf_func
;
8666 if (((given
& 0x000f0000) == 0x000f0000)
8667 && ((given
& 0x02000000) == 0))
8669 offset
= given
& 0xfff;
8671 func (stream
, "[pc");
8675 /* Pre-indexed. Elide offset of positive zero when
8677 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
8678 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8680 if (NEGATIVE_BIT_SET
)
8685 /* Cope with the possibility of write-back
8686 being used. Probably a very dangerous thing
8687 for the programmer to do, but who are we to
8689 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
8691 else /* Post indexed. */
8693 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8695 /* Ie ignore the offset. */
8699 func (stream
, "\t; ");
8700 info
->print_address_func (offset
, info
);
8705 func (stream
, "[%s",
8706 arm_regnames
[(given
>> 16) & 0xf]);
8710 if ((given
& 0x02000000) == 0)
8712 /* Elide offset of positive zero when non-writeback. */
8713 offset
= given
& 0xfff;
8714 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
8715 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8719 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
8720 arm_decode_shift (given
, func
, stream
, TRUE
);
8723 func (stream
, "]%s",
8724 WRITEBACK_BIT_SET
? "!" : "");
8728 if ((given
& 0x02000000) == 0)
8730 /* Always show offset. */
8731 offset
= given
& 0xfff;
8732 func (stream
, "], #%s%d",
8733 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8737 func (stream
, "], %s",
8738 NEGATIVE_BIT_SET
? "-" : "");
8739 arm_decode_shift (given
, func
, stream
, TRUE
);
8742 if (NEGATIVE_BIT_SET
)
8746 return (signed long) offset
;
8749 /* Print one neon instruction on INFO->STREAM.
8750 Return TRUE if the instuction matched, FALSE if this is not a
8751 recognised neon instruction. */
8754 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
8756 const struct opcode32
*insn
;
8757 void *stream
= info
->stream
;
8758 fprintf_ftype func
= info
->fprintf_func
;
8762 if ((given
& 0xef000000) == 0xef000000)
8764 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
8765 unsigned long bit28
= given
& (1 << 28);
8767 given
&= 0x00ffffff;
8769 given
|= 0xf3000000;
8771 given
|= 0xf2000000;
8773 else if ((given
& 0xff000000) == 0xf9000000)
8774 given
^= 0xf9000000 ^ 0xf4000000;
8775 /* vdup is also a valid neon instruction. */
8776 else if ((given
& 0xff910f5f) != 0xee800b10)
8780 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
8782 if ((given
& insn
->mask
) == insn
->value
)
8784 signed long value_in_comment
= 0;
8785 bfd_boolean is_unpredictable
= FALSE
;
8788 for (c
= insn
->assembler
; *c
; c
++)
8795 func (stream
, "%%");
8799 if (thumb
&& ifthen_state
)
8800 is_unpredictable
= TRUE
;
8804 if (thumb
&& ifthen_state
)
8805 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8810 static const unsigned char enc
[16] =
8812 0x4, 0x14, /* st4 0,1 */
8824 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
8825 int rn
= ((given
>> 16) & 0xf);
8826 int rm
= ((given
>> 0) & 0xf);
8827 int align
= ((given
>> 4) & 0x3);
8828 int type
= ((given
>> 8) & 0xf);
8829 int n
= enc
[type
] & 0xf;
8830 int stride
= (enc
[type
] >> 4) + 1;
8835 for (ix
= 0; ix
!= n
; ix
++)
8836 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
8838 func (stream
, "d%d", rd
);
8840 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
8841 func (stream
, "}, [%s", arm_regnames
[rn
]);
8843 func (stream
, " :%d", 32 << align
);
8848 func (stream
, ", %s", arm_regnames
[rm
]);
8854 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
8855 int rn
= ((given
>> 16) & 0xf);
8856 int rm
= ((given
>> 0) & 0xf);
8857 int idx_align
= ((given
>> 4) & 0xf);
8859 int size
= ((given
>> 10) & 0x3);
8860 int idx
= idx_align
>> (size
+ 1);
8861 int length
= ((given
>> 8) & 3) + 1;
8865 if (length
> 1 && size
> 0)
8866 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
8872 int amask
= (1 << size
) - 1;
8873 if ((idx_align
& (1 << size
)) != 0)
8877 if ((idx_align
& amask
) == amask
)
8879 else if ((idx_align
& amask
) != 0)
8886 if (size
== 2 && (idx_align
& 2) != 0)
8888 align
= (idx_align
& 1) ? 16 << size
: 0;
8892 if ((size
== 2 && (idx_align
& 3) != 0)
8893 || (idx_align
& 1) != 0)
8900 if ((idx_align
& 3) == 3)
8902 align
= (idx_align
& 3) * 64;
8905 align
= (idx_align
& 1) ? 32 << size
: 0;
8913 for (i
= 0; i
< length
; i
++)
8914 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
8915 rd
+ i
* stride
, idx
);
8916 func (stream
, "}, [%s", arm_regnames
[rn
]);
8918 func (stream
, " :%d", align
);
8923 func (stream
, ", %s", arm_regnames
[rm
]);
8929 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
8930 int rn
= ((given
>> 16) & 0xf);
8931 int rm
= ((given
>> 0) & 0xf);
8932 int align
= ((given
>> 4) & 0x1);
8933 int size
= ((given
>> 6) & 0x3);
8934 int type
= ((given
>> 8) & 0x3);
8936 int stride
= ((given
>> 5) & 0x1);
8939 if (stride
&& (n
== 1))
8946 for (ix
= 0; ix
!= n
; ix
++)
8947 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
8949 func (stream
, "d%d[]", rd
);
8951 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
8952 func (stream
, "}, [%s", arm_regnames
[rn
]);
8955 align
= (8 * (type
+ 1)) << size
;
8957 align
= (size
> 1) ? align
>> 1 : align
;
8958 if (type
== 2 || (type
== 0 && !size
))
8959 func (stream
, " :<bad align %d>", align
);
8961 func (stream
, " :%d", align
);
8967 func (stream
, ", %s", arm_regnames
[rm
]);
8973 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
8974 int size
= (given
>> 20) & 3;
8975 int reg
= raw_reg
& ((4 << size
) - 1);
8976 int ix
= raw_reg
>> size
>> 2;
8978 func (stream
, "d%d[%d]", reg
, ix
);
8983 /* Neon encoded constant for mov, mvn, vorr, vbic. */
8986 int cmode
= (given
>> 8) & 0xf;
8987 int op
= (given
>> 5) & 0x1;
8988 unsigned long value
= 0, hival
= 0;
8993 bits
|= ((given
>> 24) & 1) << 7;
8994 bits
|= ((given
>> 16) & 7) << 4;
8995 bits
|= ((given
>> 0) & 15) << 0;
8999 shift
= (cmode
>> 1) & 3;
9000 value
= (unsigned long) bits
<< (8 * shift
);
9003 else if (cmode
< 12)
9005 shift
= (cmode
>> 1) & 1;
9006 value
= (unsigned long) bits
<< (8 * shift
);
9009 else if (cmode
< 14)
9011 shift
= (cmode
& 1) + 1;
9012 value
= (unsigned long) bits
<< (8 * shift
);
9013 value
|= (1ul << (8 * shift
)) - 1;
9016 else if (cmode
== 14)
9020 /* Bit replication into bytes. */
9026 for (ix
= 7; ix
>= 0; ix
--)
9028 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
9030 value
= (value
<< 8) | mask
;
9032 hival
= (hival
<< 8) | mask
;
9038 /* Byte replication. */
9039 value
= (unsigned long) bits
;
9045 /* Floating point encoding. */
9048 value
= (unsigned long) (bits
& 0x7f) << 19;
9049 value
|= (unsigned long) (bits
& 0x80) << 24;
9050 tmp
= bits
& 0x40 ? 0x3c : 0x40;
9051 value
|= (unsigned long) tmp
<< 24;
9057 func (stream
, "<illegal constant %.8x:%x:%x>",
9065 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
9069 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
9075 unsigned char valbytes
[4];
9078 /* Do this a byte at a time so we don't have to
9079 worry about the host's endianness. */
9080 valbytes
[0] = value
& 0xff;
9081 valbytes
[1] = (value
>> 8) & 0xff;
9082 valbytes
[2] = (value
>> 16) & 0xff;
9083 valbytes
[3] = (value
>> 24) & 0xff;
9085 floatformat_to_double
9086 (& floatformat_ieee_single_little
, valbytes
,
9089 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
9093 func (stream
, "#%ld\t; 0x%.8lx",
9094 (long) (((value
& 0x80000000L
) != 0)
9095 ? value
| ~0xffffffffL
: value
),
9100 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
9111 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
9112 int num
= (given
>> 8) & 0x3;
9115 func (stream
, "{d%d}", regno
);
9116 else if (num
+ regno
>= 32)
9117 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
9119 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
9124 case '0': case '1': case '2': case '3': case '4':
9125 case '5': case '6': case '7': case '8': case '9':
9128 unsigned long value
;
9130 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9135 func (stream
, "%s", arm_regnames
[value
]);
9138 func (stream
, "%ld", value
);
9139 value_in_comment
= value
;
9142 func (stream
, "%ld", (1ul << width
) - value
);
9148 /* Various width encodings. */
9150 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
9155 if (*c
>= '0' && *c
<= '9')
9157 else if (*c
>= 'a' && *c
<= 'f')
9158 limit
= *c
- 'a' + 10;
9164 if (value
< low
|| value
> high
)
9165 func (stream
, "<illegal width %d>", base
<< value
);
9167 func (stream
, "%d", base
<< value
);
9171 if (given
& (1 << 6))
9175 func (stream
, "d%ld", value
);
9180 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
9182 func (stream
, "q%ld", value
>> 1);
9188 func (stream
, "%c", *c
);
9192 if (value
== ((1ul << width
) - 1))
9193 func (stream
, "%c", *c
);
9196 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
9210 func (stream
, "%c", *c
);
9213 if (value_in_comment
> 32 || value_in_comment
< -16)
9214 func (stream
, "\t; 0x%lx", value_in_comment
);
9216 if (is_unpredictable
)
9217 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9225 /* Print one mve instruction on INFO->STREAM.
9226 Return TRUE if the instuction matched, FALSE if this is not a
9227 recognised mve instruction. */
9230 print_insn_mve (struct disassemble_info
*info
, long given
)
9232 const struct mopcode32
*insn
;
9233 void *stream
= info
->stream
;
9234 fprintf_ftype func
= info
->fprintf_func
;
9236 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
9238 if (((given
& insn
->mask
) == insn
->value
)
9239 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
9241 signed long value_in_comment
= 0;
9242 bfd_boolean is_unpredictable
= FALSE
;
9243 bfd_boolean is_undefined
= FALSE
;
9245 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
9246 enum mve_undefined undefined_cond
= UNDEF_NONE
;
9248 /* Most vector mve instruction are illegal in a it block.
9249 There are a few exceptions; check for them. */
9250 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
9252 is_unpredictable
= TRUE
;
9253 unpredictable_cond
= UNPRED_IT_BLOCK
;
9255 else if (is_mve_unpredictable (given
, insn
->mve_op
,
9256 &unpredictable_cond
))
9257 is_unpredictable
= TRUE
;
9259 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
9260 is_undefined
= TRUE
;
9262 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9263 i.e "VMOV Qd, Qm". */
9264 if ((insn
->mve_op
== MVE_VORR_REG
)
9265 && (arm_decode_field (given
, 1, 3)
9266 == arm_decode_field (given
, 17, 19)))
9269 for (c
= insn
->assembler
; *c
; c
++)
9276 func (stream
, "%%");
9280 /* Don't print anything for '+' as it is implied. */
9281 if (arm_decode_field (given
, 23, 23) == 0)
9287 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9291 print_mve_vld_str_addr (info
, given
, insn
->mve_op
);
9296 long mve_mask
= mve_extract_pred_mask (given
);
9297 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
9303 unsigned int imm5
= 0;
9304 imm5
|= arm_decode_field (given
, 6, 7);
9305 imm5
|= (arm_decode_field (given
, 12, 14) << 2);
9306 func (stream
, "#%u", (imm5
== 0) ? 32 : imm5
);
9311 func (stream
, "#%u",
9312 (arm_decode_field (given
, 7, 7) == 0) ? 64 : 48);
9316 print_vec_condition (info
, given
, insn
->mve_op
);
9320 if (arm_decode_field (given
, 0, 0) == 1)
9323 = arm_decode_field (given
, 4, 4)
9324 | (arm_decode_field (given
, 6, 6) << 1);
9326 func (stream
, ", uxtw #%lu", size
);
9331 print_mve_rounding_mode (info
, given
, insn
->mve_op
);
9335 print_mve_vcvt_size (info
, given
, insn
->mve_op
);
9340 unsigned long op1
= arm_decode_field (given
, 21, 22);
9342 if ((insn
->mve_op
== MVE_VMOV_VEC_LANE_TO_GP
))
9344 /* Check for signed. */
9345 if (arm_decode_field (given
, 23, 23) == 0)
9347 /* We don't print 's' for S32. */
9348 if ((arm_decode_field (given
, 5, 6) == 0)
9349 && ((op1
== 0) || (op1
== 1)))
9359 if (arm_decode_field (given
, 28, 28) == 0)
9368 print_instruction_predicate (info
);
9372 if (arm_decode_field (given
, 21, 21) == 1)
9377 print_mve_register_blocks (info
, given
, insn
->mve_op
);
9381 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9383 print_simd_imm8 (info
, given
, 28, insn
);
9387 print_mve_vmov_index (info
, given
);
9391 if (arm_decode_field (given
, 12, 12) == 0)
9398 if (arm_decode_field (given
, 12, 12) == 1)
9402 case '0': case '1': case '2': case '3': case '4':
9403 case '5': case '6': case '7': case '8': case '9':
9406 unsigned long value
;
9408 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9414 is_unpredictable
= TRUE
;
9415 else if (value
== 15)
9416 func (stream
, "zr");
9418 func (stream
, "%s", arm_regnames
[value
]);
9422 func (stream
, "%s", arm_conditional
[value
]);
9427 func (stream
, "%s", arm_conditional
[value
]);
9431 if (value
== 13 || value
== 15)
9432 is_unpredictable
= TRUE
;
9434 func (stream
, "%s", arm_regnames
[value
]);
9438 print_mve_size (info
,
9452 unsigned int odd_reg
= (value
<< 1) | 1;
9453 func (stream
, "%s", arm_regnames
[odd_reg
]);
9459 = arm_decode_field (given
, 0, 6);
9460 unsigned long mod_imm
= imm
;
9462 switch (insn
->mve_op
)
9464 case MVE_VLDRW_GATHER_T5
:
9465 case MVE_VSTRW_SCATTER_T5
:
9466 mod_imm
= mod_imm
<< 2;
9468 case MVE_VSTRD_SCATTER_T6
:
9469 case MVE_VLDRD_GATHER_T6
:
9470 mod_imm
= mod_imm
<< 3;
9477 func (stream
, "%lu", mod_imm
);
9481 func (stream
, "%lu", 64 - value
);
9485 unsigned int even_reg
= value
<< 1;
9486 func (stream
, "%s", arm_regnames
[even_reg
]);
9509 print_mve_rotate (info
, value
, width
);
9512 func (stream
, "%s", arm_regnames
[value
]);
9515 if (insn
->mve_op
== MVE_VQSHL_T2
9516 || insn
->mve_op
== MVE_VQSHLU_T3
9517 || insn
->mve_op
== MVE_VRSHR
9518 || insn
->mve_op
== MVE_VRSHRN
9519 || insn
->mve_op
== MVE_VSHL_T1
9520 || insn
->mve_op
== MVE_VSHLL_T1
9521 || insn
->mve_op
== MVE_VSHR
9522 || insn
->mve_op
== MVE_VSHRN
9523 || insn
->mve_op
== MVE_VSLI
9524 || insn
->mve_op
== MVE_VSRI
)
9525 print_mve_shift_n (info
, given
, insn
->mve_op
);
9526 else if (insn
->mve_op
== MVE_VSHLL_T2
)
9534 func (stream
, "16");
9537 print_mve_undefined (info
, UNDEF_SIZE_0
);
9546 if (insn
->mve_op
== MVE_VSHLC
&& value
== 0)
9548 func (stream
, "%ld", value
);
9549 value_in_comment
= value
;
9553 func (stream
, "s%ld", value
);
9557 func (stream
, "<illegal reg q%ld.5>", value
);
9559 func (stream
, "q%ld", value
);
9562 func (stream
, "0x%08lx", value
);
9574 func (stream
, "%c", *c
);
9577 if (value_in_comment
> 32 || value_in_comment
< -16)
9578 func (stream
, "\t; 0x%lx", value_in_comment
);
9580 if (is_unpredictable
)
9581 print_mve_unpredictable (info
, unpredictable_cond
);
9584 print_mve_undefined (info
, undefined_cond
);
9586 if ((vpt_block_state
.in_vpt_block
== FALSE
)
9588 && (is_vpt_instruction (given
) == TRUE
))
9589 mark_inside_vpt_block (given
);
9590 else if (vpt_block_state
.in_vpt_block
== TRUE
)
9591 update_vpt_block_state ();
9600 /* Return the name of a v7A special register. */
9603 banked_regname (unsigned reg
)
9607 case 15: return "CPSR";
9608 case 32: return "R8_usr";
9609 case 33: return "R9_usr";
9610 case 34: return "R10_usr";
9611 case 35: return "R11_usr";
9612 case 36: return "R12_usr";
9613 case 37: return "SP_usr";
9614 case 38: return "LR_usr";
9615 case 40: return "R8_fiq";
9616 case 41: return "R9_fiq";
9617 case 42: return "R10_fiq";
9618 case 43: return "R11_fiq";
9619 case 44: return "R12_fiq";
9620 case 45: return "SP_fiq";
9621 case 46: return "LR_fiq";
9622 case 48: return "LR_irq";
9623 case 49: return "SP_irq";
9624 case 50: return "LR_svc";
9625 case 51: return "SP_svc";
9626 case 52: return "LR_abt";
9627 case 53: return "SP_abt";
9628 case 54: return "LR_und";
9629 case 55: return "SP_und";
9630 case 60: return "LR_mon";
9631 case 61: return "SP_mon";
9632 case 62: return "ELR_hyp";
9633 case 63: return "SP_hyp";
9634 case 79: return "SPSR";
9635 case 110: return "SPSR_fiq";
9636 case 112: return "SPSR_irq";
9637 case 114: return "SPSR_svc";
9638 case 116: return "SPSR_abt";
9639 case 118: return "SPSR_und";
9640 case 124: return "SPSR_mon";
9641 case 126: return "SPSR_hyp";
9642 default: return NULL
;
9646 /* Return the name of the DMB/DSB option. */
9648 data_barrier_option (unsigned option
)
9650 switch (option
& 0xf)
9652 case 0xf: return "sy";
9653 case 0xe: return "st";
9654 case 0xd: return "ld";
9655 case 0xb: return "ish";
9656 case 0xa: return "ishst";
9657 case 0x9: return "ishld";
9658 case 0x7: return "un";
9659 case 0x6: return "unst";
9660 case 0x5: return "nshld";
9661 case 0x3: return "osh";
9662 case 0x2: return "oshst";
9663 case 0x1: return "oshld";
9664 default: return NULL
;
9668 /* Print one ARM instruction from PC on INFO->STREAM. */
9671 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
9673 const struct opcode32
*insn
;
9674 void *stream
= info
->stream
;
9675 fprintf_ftype func
= info
->fprintf_func
;
9676 struct arm_private_data
*private_data
= info
->private_data
;
9678 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
9681 if (print_insn_neon (info
, given
, FALSE
))
9684 if (print_insn_generic_coprocessor (pc
, info
, given
, FALSE
))
9687 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
9689 if ((given
& insn
->mask
) != insn
->value
)
9692 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
9695 /* Special case: an instruction with all bits set in the condition field
9696 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9697 or by the catchall at the end of the table. */
9698 if ((given
& 0xF0000000) != 0xF0000000
9699 || (insn
->mask
& 0xF0000000) == 0xF0000000
9700 || (insn
->mask
== 0 && insn
->value
== 0))
9702 unsigned long u_reg
= 16;
9703 unsigned long U_reg
= 16;
9704 bfd_boolean is_unpredictable
= FALSE
;
9705 signed long value_in_comment
= 0;
9708 for (c
= insn
->assembler
; *c
; c
++)
9712 bfd_boolean allow_unpredictable
= FALSE
;
9717 func (stream
, "%%");
9721 value_in_comment
= print_arm_address (pc
, info
, given
);
9725 /* Set P address bit and use normal address
9726 printing routine. */
9727 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
9731 allow_unpredictable
= TRUE
;
9734 if ((given
& 0x004f0000) == 0x004f0000)
9736 /* PC relative with immediate offset. */
9737 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
9741 /* Elide positive zero offset. */
9742 if (offset
|| NEGATIVE_BIT_SET
)
9743 func (stream
, "[pc, #%s%d]\t; ",
9744 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
9746 func (stream
, "[pc]\t; ");
9747 if (NEGATIVE_BIT_SET
)
9749 info
->print_address_func (offset
+ pc
+ 8, info
);
9753 /* Always show the offset. */
9754 func (stream
, "[pc], #%s%d",
9755 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
9756 if (! allow_unpredictable
)
9757 is_unpredictable
= TRUE
;
9762 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
9764 func (stream
, "[%s",
9765 arm_regnames
[(given
>> 16) & 0xf]);
9769 if (IMMEDIATE_BIT_SET
)
9771 /* Elide offset for non-writeback
9773 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
9775 func (stream
, ", #%s%d",
9776 NEGATIVE_BIT_SET
? "-" : "", offset
);
9778 if (NEGATIVE_BIT_SET
)
9781 value_in_comment
= offset
;
9785 /* Register Offset or Register Pre-Indexed. */
9786 func (stream
, ", %s%s",
9787 NEGATIVE_BIT_SET
? "-" : "",
9788 arm_regnames
[given
& 0xf]);
9790 /* Writing back to the register that is the source/
9791 destination of the load/store is unpredictable. */
9792 if (! allow_unpredictable
9793 && WRITEBACK_BIT_SET
9794 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
9795 is_unpredictable
= TRUE
;
9798 func (stream
, "]%s",
9799 WRITEBACK_BIT_SET
? "!" : "");
9803 if (IMMEDIATE_BIT_SET
)
9805 /* Immediate Post-indexed. */
9806 /* PR 10924: Offset must be printed, even if it is zero. */
9807 func (stream
, "], #%s%d",
9808 NEGATIVE_BIT_SET
? "-" : "", offset
);
9809 if (NEGATIVE_BIT_SET
)
9811 value_in_comment
= offset
;
9815 /* Register Post-indexed. */
9816 func (stream
, "], %s%s",
9817 NEGATIVE_BIT_SET
? "-" : "",
9818 arm_regnames
[given
& 0xf]);
9820 /* Writing back to the register that is the source/
9821 destination of the load/store is unpredictable. */
9822 if (! allow_unpredictable
9823 && (given
& 0xf) == ((given
>> 12) & 0xf))
9824 is_unpredictable
= TRUE
;
9827 if (! allow_unpredictable
)
9829 /* Writeback is automatically implied by post- addressing.
9830 Setting the W bit is unnecessary and ARM specify it as
9831 being unpredictable. */
9832 if (WRITEBACK_BIT_SET
9833 /* Specifying the PC register as the post-indexed
9834 registers is also unpredictable. */
9835 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
9836 is_unpredictable
= TRUE
;
9844 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
9845 info
->print_address_func (disp
* 4 + pc
+ 8, info
);
9850 if (((given
>> 28) & 0xf) != 0xe)
9852 arm_conditional
[(given
>> 28) & 0xf]);
9861 for (reg
= 0; reg
< 16; reg
++)
9862 if ((given
& (1 << reg
)) != 0)
9865 func (stream
, ", ");
9867 func (stream
, "%s", arm_regnames
[reg
]);
9871 is_unpredictable
= TRUE
;
9876 arm_decode_shift (given
, func
, stream
, FALSE
);
9880 if ((given
& 0x02000000) != 0)
9882 unsigned int rotate
= (given
& 0xf00) >> 7;
9883 unsigned int immed
= (given
& 0xff);
9886 a
= (((immed
<< (32 - rotate
))
9887 | (immed
>> rotate
)) & 0xffffffff);
9888 /* If there is another encoding with smaller rotate,
9889 the rotate should be specified directly. */
9890 for (i
= 0; i
< 32; i
+= 2)
9891 if ((a
<< i
| a
>> (32 - i
)) <= 0xff)
9895 func (stream
, "#%d, %d", immed
, rotate
);
9897 func (stream
, "#%d", a
);
9898 value_in_comment
= a
;
9901 arm_decode_shift (given
, func
, stream
, TRUE
);
9905 if ((given
& 0x0000f000) == 0x0000f000)
9907 arm_feature_set arm_ext_v6
=
9908 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
9910 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9911 mechanism for setting PSR flag bits. They are
9912 obsolete in V6 onwards. */
9913 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
9917 is_unpredictable
= TRUE
;
9922 if ((given
& 0x01200000) == 0x00200000)
9928 int offset
= given
& 0xff;
9930 value_in_comment
= offset
* 4;
9931 if (NEGATIVE_BIT_SET
)
9932 value_in_comment
= - value_in_comment
;
9934 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
9939 func (stream
, ", #%d]%s",
9940 (int) value_in_comment
,
9941 WRITEBACK_BIT_SET
? "!" : "");
9949 if (WRITEBACK_BIT_SET
)
9952 func (stream
, ", #%d", (int) value_in_comment
);
9956 func (stream
, ", {%d}", (int) offset
);
9957 value_in_comment
= offset
;
9964 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9969 if (! NEGATIVE_BIT_SET
)
9970 /* Is signed, hi bits should be ones. */
9971 offset
= (-1) ^ 0x00ffffff;
9973 /* Offset is (SignExtend(offset field)<<2). */
9974 offset
+= given
& 0x00ffffff;
9976 address
= offset
+ pc
+ 8;
9978 if (given
& 0x01000000)
9979 /* H bit allows addressing to 2-byte boundaries. */
9982 info
->print_address_func (address
, info
);
9987 if ((given
& 0x02000200) == 0x200)
9990 unsigned sysm
= (given
& 0x004f0000) >> 16;
9992 sysm
|= (given
& 0x300) >> 4;
9993 name
= banked_regname (sysm
);
9996 func (stream
, "%s", name
);
9998 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10002 func (stream
, "%cPSR_",
10003 (given
& 0x00400000) ? 'S' : 'C');
10004 if (given
& 0x80000)
10005 func (stream
, "f");
10006 if (given
& 0x40000)
10007 func (stream
, "s");
10008 if (given
& 0x20000)
10009 func (stream
, "x");
10010 if (given
& 0x10000)
10011 func (stream
, "c");
10016 if ((given
& 0xf0) == 0x60)
10018 switch (given
& 0xf)
10020 case 0xf: func (stream
, "sy"); break;
10022 func (stream
, "#%d", (int) given
& 0xf);
10028 const char * opt
= data_barrier_option (given
& 0xf);
10030 func (stream
, "%s", opt
);
10032 func (stream
, "#%d", (int) given
& 0xf);
10036 case '0': case '1': case '2': case '3': case '4':
10037 case '5': case '6': case '7': case '8': case '9':
10040 unsigned long value
;
10042 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
10048 is_unpredictable
= TRUE
;
10049 /* Fall through. */
10052 /* We want register + 1 when decoding T. */
10058 /* Eat the 'u' character. */
10061 if (u_reg
== value
)
10062 is_unpredictable
= TRUE
;
10067 /* Eat the 'U' character. */
10070 if (U_reg
== value
)
10071 is_unpredictable
= TRUE
;
10074 func (stream
, "%s", arm_regnames
[value
]);
10077 func (stream
, "%ld", value
);
10078 value_in_comment
= value
;
10081 func (stream
, "%ld", value
* 8);
10082 value_in_comment
= value
* 8;
10085 func (stream
, "%ld", value
+ 1);
10086 value_in_comment
= value
+ 1;
10089 func (stream
, "0x%08lx", value
);
10091 /* Some SWI instructions have special
10093 if ((given
& 0x0fffffff) == 0x0FF00000)
10094 func (stream
, "\t; IMB");
10095 else if ((given
& 0x0fffffff) == 0x0FF00001)
10096 func (stream
, "\t; IMBRange");
10099 func (stream
, "%01lx", value
& 0xf);
10100 value_in_comment
= value
;
10105 func (stream
, "%c", *c
);
10109 if (value
== ((1ul << width
) - 1))
10110 func (stream
, "%c", *c
);
10113 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
10126 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
10127 func (stream
, "%d", imm
);
10128 value_in_comment
= imm
;
10133 /* LSB and WIDTH fields of BFI or BFC. The machine-
10134 language instruction encodes LSB and MSB. */
10136 long msb
= (given
& 0x001f0000) >> 16;
10137 long lsb
= (given
& 0x00000f80) >> 7;
10138 long w
= msb
- lsb
+ 1;
10141 func (stream
, "#%lu, #%lu", lsb
, w
);
10143 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
10148 /* Get the PSR/banked register name. */
10151 unsigned sysm
= (given
& 0x004f0000) >> 16;
10153 sysm
|= (given
& 0x300) >> 4;
10154 name
= banked_regname (sysm
);
10157 func (stream
, "%s", name
);
10159 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10164 /* 16-bit unsigned immediate from a MOVT or MOVW
10165 instruction, encoded in bits 0:11 and 15:19. */
10167 long hi
= (given
& 0x000f0000) >> 4;
10168 long lo
= (given
& 0x00000fff);
10169 long imm16
= hi
| lo
;
10171 func (stream
, "#%lu", imm16
);
10172 value_in_comment
= imm16
;
10181 func (stream
, "%c", *c
);
10184 if (value_in_comment
> 32 || value_in_comment
< -16)
10185 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
10187 if (is_unpredictable
)
10188 func (stream
, UNPREDICTABLE_INSTRUCTION
);
10193 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
10197 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
10200 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
10202 const struct opcode16
*insn
;
10203 void *stream
= info
->stream
;
10204 fprintf_ftype func
= info
->fprintf_func
;
10206 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
10207 if ((given
& insn
->mask
) == insn
->value
)
10209 signed long value_in_comment
= 0;
10210 const char *c
= insn
->assembler
;
10219 func (stream
, "%c", *c
);
10226 func (stream
, "%%");
10231 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10236 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10238 func (stream
, "s");
10245 ifthen_next_state
= given
& 0xff;
10246 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
10247 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
10248 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
10253 if (ifthen_next_state
)
10254 func (stream
, "\t; unpredictable branch in IT block\n");
10259 func (stream
, "\t; unpredictable <IT:%s>",
10260 arm_conditional
[IFTHEN_COND
]);
10267 reg
= (given
>> 3) & 0x7;
10268 if (given
& (1 << 6))
10271 func (stream
, "%s", arm_regnames
[reg
]);
10280 if (given
& (1 << 7))
10283 func (stream
, "%s", arm_regnames
[reg
]);
10288 if (given
& (1 << 8))
10290 /* Fall through. */
10292 if (*c
== 'O' && (given
& (1 << 8)))
10294 /* Fall through. */
10300 func (stream
, "{");
10302 /* It would be nice if we could spot
10303 ranges, and generate the rS-rE format: */
10304 for (reg
= 0; (reg
< 8); reg
++)
10305 if ((given
& (1 << reg
)) != 0)
10308 func (stream
, ", ");
10310 func (stream
, "%s", arm_regnames
[reg
]);
10316 func (stream
, ", ");
10318 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
10324 func (stream
, ", ");
10325 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
10328 func (stream
, "}");
10333 /* Print writeback indicator for a LDMIA. We are doing a
10334 writeback if the base register is not in the register
10336 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
10337 func (stream
, "!");
10341 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10343 bfd_vma address
= (pc
+ 4
10344 + ((given
& 0x00f8) >> 2)
10345 + ((given
& 0x0200) >> 3));
10346 info
->print_address_func (address
, info
);
10351 /* Right shift immediate -- bits 6..10; 1-31 print
10352 as themselves, 0 prints as 32. */
10354 long imm
= (given
& 0x07c0) >> 6;
10357 func (stream
, "#%ld", imm
);
10361 case '0': case '1': case '2': case '3': case '4':
10362 case '5': case '6': case '7': case '8': case '9':
10364 int bitstart
= *c
++ - '0';
10367 while (*c
>= '0' && *c
<= '9')
10368 bitstart
= (bitstart
* 10) + *c
++ - '0';
10377 while (*c
>= '0' && *c
<= '9')
10378 bitend
= (bitend
* 10) + *c
++ - '0';
10381 reg
= given
>> bitstart
;
10382 reg
&= (2 << (bitend
- bitstart
)) - 1;
10387 func (stream
, "%s", arm_regnames
[reg
]);
10391 func (stream
, "%ld", (long) reg
);
10392 value_in_comment
= reg
;
10396 func (stream
, "%ld", (long) (reg
<< 1));
10397 value_in_comment
= reg
<< 1;
10401 func (stream
, "%ld", (long) (reg
<< 2));
10402 value_in_comment
= reg
<< 2;
10406 /* PC-relative address -- the bottom two
10407 bits of the address are dropped
10408 before the calculation. */
10409 info
->print_address_func
10410 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
10411 value_in_comment
= 0;
10415 func (stream
, "0x%04lx", (long) reg
);
10419 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
10420 info
->print_address_func (reg
* 2 + pc
+ 4, info
);
10421 value_in_comment
= 0;
10425 func (stream
, "%s", arm_conditional
[reg
]);
10436 if ((given
& (1 << bitstart
)) != 0)
10437 func (stream
, "%c", *c
);
10442 if ((given
& (1 << bitstart
)) != 0)
10443 func (stream
, "%c", *c
++);
10445 func (stream
, "%c", *++c
);
10459 if (value_in_comment
> 32 || value_in_comment
< -16)
10460 func (stream
, "\t; 0x%lx", value_in_comment
);
10465 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
10469 /* Return the name of an V7M special register. */
10471 static const char *
10472 psr_name (int regno
)
10476 case 0x0: return "APSR";
10477 case 0x1: return "IAPSR";
10478 case 0x2: return "EAPSR";
10479 case 0x3: return "PSR";
10480 case 0x5: return "IPSR";
10481 case 0x6: return "EPSR";
10482 case 0x7: return "IEPSR";
10483 case 0x8: return "MSP";
10484 case 0x9: return "PSP";
10485 case 0xa: return "MSPLIM";
10486 case 0xb: return "PSPLIM";
10487 case 0x10: return "PRIMASK";
10488 case 0x11: return "BASEPRI";
10489 case 0x12: return "BASEPRI_MAX";
10490 case 0x13: return "FAULTMASK";
10491 case 0x14: return "CONTROL";
10492 case 0x88: return "MSP_NS";
10493 case 0x89: return "PSP_NS";
10494 case 0x8a: return "MSPLIM_NS";
10495 case 0x8b: return "PSPLIM_NS";
10496 case 0x90: return "PRIMASK_NS";
10497 case 0x91: return "BASEPRI_NS";
10498 case 0x93: return "FAULTMASK_NS";
10499 case 0x94: return "CONTROL_NS";
10500 case 0x98: return "SP_NS";
10501 default: return "<unknown>";
10505 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10508 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
10510 const struct opcode32
*insn
;
10511 void *stream
= info
->stream
;
10512 fprintf_ftype func
= info
->fprintf_func
;
10513 bfd_boolean is_mve
= is_mve_architecture (info
);
10515 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
10518 if ((is_mve
== FALSE
) && print_insn_neon (info
, given
, TRUE
))
10521 if (is_mve
&& print_insn_mve (info
, given
))
10524 if (print_insn_generic_coprocessor (pc
, info
, given
, TRUE
))
10527 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
10528 if ((given
& insn
->mask
) == insn
->value
)
10530 bfd_boolean is_clrm
= FALSE
;
10531 bfd_boolean is_unpredictable
= FALSE
;
10532 signed long value_in_comment
= 0;
10533 const char *c
= insn
->assembler
;
10539 func (stream
, "%c", *c
);
10546 func (stream
, "%%");
10551 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10555 if (ifthen_next_state
)
10556 func (stream
, "\t; unpredictable branch in IT block\n");
10561 func (stream
, "\t; unpredictable <IT:%s>",
10562 arm_conditional
[IFTHEN_COND
]);
10567 unsigned int imm12
= 0;
10569 imm12
|= (given
& 0x000000ffu
);
10570 imm12
|= (given
& 0x00007000u
) >> 4;
10571 imm12
|= (given
& 0x04000000u
) >> 15;
10572 func (stream
, "#%u", imm12
);
10573 value_in_comment
= imm12
;
10579 unsigned int bits
= 0, imm
, imm8
, mod
;
10581 bits
|= (given
& 0x000000ffu
);
10582 bits
|= (given
& 0x00007000u
) >> 4;
10583 bits
|= (given
& 0x04000000u
) >> 15;
10584 imm8
= (bits
& 0x0ff);
10585 mod
= (bits
& 0xf00) >> 8;
10588 case 0: imm
= imm8
; break;
10589 case 1: imm
= ((imm8
<< 16) | imm8
); break;
10590 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
10591 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
10593 mod
= (bits
& 0xf80) >> 7;
10594 imm8
= (bits
& 0x07f) | 0x80;
10595 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
10597 func (stream
, "#%u", imm
);
10598 value_in_comment
= imm
;
10604 unsigned int imm
= 0;
10606 imm
|= (given
& 0x000000ffu
);
10607 imm
|= (given
& 0x00007000u
) >> 4;
10608 imm
|= (given
& 0x04000000u
) >> 15;
10609 imm
|= (given
& 0x000f0000u
) >> 4;
10610 func (stream
, "#%u", imm
);
10611 value_in_comment
= imm
;
10617 unsigned int imm
= 0;
10619 imm
|= (given
& 0x000f0000u
) >> 16;
10620 imm
|= (given
& 0x00000ff0u
) >> 0;
10621 imm
|= (given
& 0x0000000fu
) << 12;
10622 func (stream
, "#%u", imm
);
10623 value_in_comment
= imm
;
10629 unsigned int imm
= 0;
10631 imm
|= (given
& 0x000f0000u
) >> 4;
10632 imm
|= (given
& 0x00000fffu
) >> 0;
10633 func (stream
, "#%u", imm
);
10634 value_in_comment
= imm
;
10640 unsigned int imm
= 0;
10642 imm
|= (given
& 0x00000fffu
);
10643 imm
|= (given
& 0x000f0000u
) >> 4;
10644 func (stream
, "#%u", imm
);
10645 value_in_comment
= imm
;
10651 unsigned int reg
= (given
& 0x0000000fu
);
10652 unsigned int stp
= (given
& 0x00000030u
) >> 4;
10653 unsigned int imm
= 0;
10654 imm
|= (given
& 0x000000c0u
) >> 6;
10655 imm
|= (given
& 0x00007000u
) >> 10;
10657 func (stream
, "%s", arm_regnames
[reg
]);
10662 func (stream
, ", lsl #%u", imm
);
10668 func (stream
, ", lsr #%u", imm
);
10674 func (stream
, ", asr #%u", imm
);
10679 func (stream
, ", rrx");
10681 func (stream
, ", ror #%u", imm
);
10688 unsigned int Rn
= (given
& 0x000f0000) >> 16;
10689 unsigned int U
= ! NEGATIVE_BIT_SET
;
10690 unsigned int op
= (given
& 0x00000f00) >> 8;
10691 unsigned int i12
= (given
& 0x00000fff);
10692 unsigned int i8
= (given
& 0x000000ff);
10693 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
10694 bfd_vma offset
= 0;
10696 func (stream
, "[%s", arm_regnames
[Rn
]);
10697 if (U
) /* 12-bit positive immediate offset. */
10701 value_in_comment
= offset
;
10703 else if (Rn
== 15) /* 12-bit negative immediate offset. */
10704 offset
= - (int) i12
;
10705 else if (op
== 0x0) /* Shifted register offset. */
10707 unsigned int Rm
= (i8
& 0x0f);
10708 unsigned int sh
= (i8
& 0x30) >> 4;
10710 func (stream
, ", %s", arm_regnames
[Rm
]);
10712 func (stream
, ", lsl #%u", sh
);
10713 func (stream
, "]");
10718 case 0xE: /* 8-bit positive immediate offset. */
10722 case 0xC: /* 8-bit negative immediate offset. */
10726 case 0xF: /* 8-bit + preindex with wb. */
10731 case 0xD: /* 8-bit - preindex with wb. */
10736 case 0xB: /* 8-bit + postindex. */
10741 case 0x9: /* 8-bit - postindex. */
10747 func (stream
, ", <undefined>]");
10752 func (stream
, "], #%d", (int) offset
);
10756 func (stream
, ", #%d", (int) offset
);
10757 func (stream
, writeback
? "]!" : "]");
10762 func (stream
, "\t; ");
10763 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
10771 unsigned int U
= ! NEGATIVE_BIT_SET
;
10772 unsigned int W
= WRITEBACK_BIT_SET
;
10773 unsigned int Rn
= (given
& 0x000f0000) >> 16;
10774 unsigned int off
= (given
& 0x000000ff);
10776 func (stream
, "[%s", arm_regnames
[Rn
]);
10782 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
10783 value_in_comment
= off
* 4 * (U
? 1 : -1);
10785 func (stream
, "]");
10787 func (stream
, "!");
10791 func (stream
, "], ");
10794 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
10795 value_in_comment
= off
* 4 * (U
? 1 : -1);
10799 func (stream
, "{%u}", off
);
10800 value_in_comment
= off
;
10808 unsigned int Sbit
= (given
& 0x01000000) >> 24;
10809 unsigned int type
= (given
& 0x00600000) >> 21;
10813 case 0: func (stream
, Sbit
? "sb" : "b"); break;
10814 case 1: func (stream
, Sbit
? "sh" : "h"); break;
10817 func (stream
, "??");
10820 func (stream
, "??");
10828 /* Fall through. */
10834 func (stream
, "{");
10835 for (reg
= 0; reg
< 16; reg
++)
10836 if ((given
& (1 << reg
)) != 0)
10839 func (stream
, ", ");
10841 if (is_clrm
&& reg
== 13)
10842 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
10843 else if (is_clrm
&& reg
== 15)
10844 func (stream
, "%s", "APSR");
10846 func (stream
, "%s", arm_regnames
[reg
]);
10848 func (stream
, "}");
10854 unsigned int msb
= (given
& 0x0000001f);
10855 unsigned int lsb
= 0;
10857 lsb
|= (given
& 0x000000c0u
) >> 6;
10858 lsb
|= (given
& 0x00007000u
) >> 10;
10859 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
10865 unsigned int width
= (given
& 0x0000001f) + 1;
10866 unsigned int lsb
= 0;
10868 lsb
|= (given
& 0x000000c0u
) >> 6;
10869 lsb
|= (given
& 0x00007000u
) >> 10;
10870 func (stream
, "#%u, #%u", lsb
, width
);
10876 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
10877 func (stream
, "%x", boff
);
10883 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
10884 unsigned int immB
= (given
& 0x000007feu
) >> 1;
10885 unsigned int immC
= (given
& 0x00000800u
) >> 11;
10886 bfd_vma offset
= 0;
10888 offset
|= immA
<< 12;
10889 offset
|= immB
<< 2;
10890 offset
|= immC
<< 1;
10892 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
10894 info
->print_address_func (pc
+ 4 + offset
, info
);
10900 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
10901 unsigned int immB
= (given
& 0x000007feu
) >> 1;
10902 unsigned int immC
= (given
& 0x00000800u
) >> 11;
10903 bfd_vma offset
= 0;
10905 offset
|= immA
<< 12;
10906 offset
|= immB
<< 2;
10907 offset
|= immC
<< 1;
10909 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
10911 info
->print_address_func (pc
+ 4 + offset
, info
);
10917 unsigned int immA
= (given
& 0x00010000u
) >> 16;
10918 unsigned int immB
= (given
& 0x000007feu
) >> 1;
10919 unsigned int immC
= (given
& 0x00000800u
) >> 11;
10920 bfd_vma offset
= 0;
10922 offset
|= immA
<< 12;
10923 offset
|= immB
<< 2;
10924 offset
|= immC
<< 1;
10926 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
10928 info
->print_address_func (pc
+ 4 + offset
, info
);
10930 unsigned int T
= (given
& 0x00020000u
) >> 17;
10931 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
10932 unsigned int boffset
= (T
== 1) ? 4 : 2;
10933 func (stream
, ", ");
10934 func (stream
, "%x", endoffset
+ boffset
);
10940 unsigned int immh
= (given
& 0x000007feu
) >> 1;
10941 unsigned int imml
= (given
& 0x00000800u
) >> 11;
10944 imm32
|= immh
<< 2;
10945 imm32
|= imml
<< 1;
10947 info
->print_address_func (pc
+ 4 + imm32
, info
);
10953 unsigned int immh
= (given
& 0x000007feu
) >> 1;
10954 unsigned int imml
= (given
& 0x00000800u
) >> 11;
10957 imm32
|= immh
<< 2;
10958 imm32
|= imml
<< 1;
10960 info
->print_address_func (pc
+ 4 - imm32
, info
);
10966 unsigned int S
= (given
& 0x04000000u
) >> 26;
10967 unsigned int J1
= (given
& 0x00002000u
) >> 13;
10968 unsigned int J2
= (given
& 0x00000800u
) >> 11;
10969 bfd_vma offset
= 0;
10971 offset
|= !S
<< 20;
10972 offset
|= J2
<< 19;
10973 offset
|= J1
<< 18;
10974 offset
|= (given
& 0x003f0000) >> 4;
10975 offset
|= (given
& 0x000007ff) << 1;
10976 offset
-= (1 << 20);
10978 info
->print_address_func (pc
+ 4 + offset
, info
);
10984 unsigned int S
= (given
& 0x04000000u
) >> 26;
10985 unsigned int I1
= (given
& 0x00002000u
) >> 13;
10986 unsigned int I2
= (given
& 0x00000800u
) >> 11;
10987 bfd_vma offset
= 0;
10989 offset
|= !S
<< 24;
10990 offset
|= !(I1
^ S
) << 23;
10991 offset
|= !(I2
^ S
) << 22;
10992 offset
|= (given
& 0x03ff0000u
) >> 4;
10993 offset
|= (given
& 0x000007ffu
) << 1;
10994 offset
-= (1 << 24);
10997 /* BLX target addresses are always word aligned. */
10998 if ((given
& 0x00001000u
) == 0)
11001 info
->print_address_func (offset
, info
);
11007 unsigned int shift
= 0;
11009 shift
|= (given
& 0x000000c0u
) >> 6;
11010 shift
|= (given
& 0x00007000u
) >> 10;
11011 if (WRITEBACK_BIT_SET
)
11012 func (stream
, ", asr #%u", shift
);
11014 func (stream
, ", lsl #%u", shift
);
11015 /* else print nothing - lsl #0 */
11021 unsigned int rot
= (given
& 0x00000030) >> 4;
11024 func (stream
, ", ror #%u", rot
* 8);
11029 if ((given
& 0xf0) == 0x60)
11031 switch (given
& 0xf)
11033 case 0xf: func (stream
, "sy"); break;
11035 func (stream
, "#%d", (int) given
& 0xf);
11041 const char * opt
= data_barrier_option (given
& 0xf);
11043 func (stream
, "%s", opt
);
11045 func (stream
, "#%d", (int) given
& 0xf);
11050 if ((given
& 0xff) == 0)
11052 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
11054 func (stream
, "f");
11056 func (stream
, "s");
11058 func (stream
, "x");
11060 func (stream
, "c");
11062 else if ((given
& 0x20) == 0x20)
11065 unsigned sysm
= (given
& 0xf00) >> 8;
11067 sysm
|= (given
& 0x30);
11068 sysm
|= (given
& 0x00100000) >> 14;
11069 name
= banked_regname (sysm
);
11072 func (stream
, "%s", name
);
11074 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
11078 func (stream
, "%s", psr_name (given
& 0xff));
11083 if (((given
& 0xff) == 0)
11084 || ((given
& 0x20) == 0x20))
11087 unsigned sm
= (given
& 0xf0000) >> 16;
11089 sm
|= (given
& 0x30);
11090 sm
|= (given
& 0x00100000) >> 14;
11091 name
= banked_regname (sm
);
11094 func (stream
, "%s", name
);
11096 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
11099 func (stream
, "%s", psr_name (given
& 0xff));
11102 case '0': case '1': case '2': case '3': case '4':
11103 case '5': case '6': case '7': case '8': case '9':
11108 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
11114 func (stream
, "%s", mve_vec_sizename
[val
]);
11116 func (stream
, "<undef size>");
11120 func (stream
, "%lu", val
);
11121 value_in_comment
= val
;
11125 func (stream
, "%lu", val
+ 1);
11126 value_in_comment
= val
+ 1;
11130 func (stream
, "%lu", val
* 4);
11131 value_in_comment
= val
* 4;
11136 is_unpredictable
= TRUE
;
11137 /* Fall through. */
11140 is_unpredictable
= TRUE
;
11141 /* Fall through. */
11143 func (stream
, "%s", arm_regnames
[val
]);
11147 func (stream
, "%s", arm_conditional
[val
]);
11152 if (val
== ((1ul << width
) - 1))
11153 func (stream
, "%c", *c
);
11159 func (stream
, "%c", *c
);
11163 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
11168 func (stream
, "0x%lx", val
& 0xffffffffUL
);
11178 /* PR binutils/12534
11179 If we have a PC relative offset in an LDRD or STRD
11180 instructions then display the decoded address. */
11181 if (((given
>> 16) & 0xf) == 0xf)
11183 bfd_vma offset
= (given
& 0xff) * 4;
11185 if ((given
& (1 << 23)) == 0)
11187 func (stream
, "\t; ");
11188 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
11197 if (value_in_comment
> 32 || value_in_comment
< -16)
11198 func (stream
, "\t; 0x%lx", value_in_comment
);
11200 if (is_unpredictable
)
11201 func (stream
, UNPREDICTABLE_INSTRUCTION
);
11207 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
11211 /* Print data bytes on INFO->STREAM. */
11214 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
11215 struct disassemble_info
*info
,
11218 switch (info
->bytes_per_chunk
)
11221 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
11224 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
11227 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
11234 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
11235 being displayed in symbol relative addresses.
11237 Also disallow private symbol, with __tagsym$$ prefix,
11238 from ARM RVCT toolchain being displayed. */
11241 arm_symbol_is_valid (asymbol
* sym
,
11242 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
11249 name
= bfd_asymbol_name (sym
);
11251 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
11254 /* Parse the string of disassembler options. */
11257 parse_arm_disassembler_options (const char *options
)
11261 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
11263 if (CONST_STRNEQ (opt
, "reg-names-"))
11266 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11267 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
11269 regname_selected
= i
;
11273 if (i
>= NUM_ARM_OPTIONS
)
11274 /* xgettext: c-format */
11275 opcodes_error_handler (_("unrecognised register name set: %s"),
11278 else if (CONST_STRNEQ (opt
, "force-thumb"))
11280 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
11283 /* xgettext: c-format */
11284 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
11291 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
11292 enum map_type
*map_symbol
);
11294 /* Search back through the insn stream to determine if this instruction is
11295 conditionally executed. */
11298 find_ifthen_state (bfd_vma pc
,
11299 struct disassemble_info
*info
,
11300 bfd_boolean little
)
11302 unsigned char b
[2];
11305 /* COUNT is twice the number of instructions seen. It will be odd if we
11306 just crossed an instruction boundary. */
11309 unsigned int seen_it
;
11312 ifthen_address
= pc
;
11319 /* Scan backwards looking for IT instructions, keeping track of where
11320 instruction boundaries are. We don't know if something is actually an
11321 IT instruction until we find a definite instruction boundary. */
11324 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
11326 /* A symbol must be on an instruction boundary, and will not
11327 be within an IT block. */
11328 if (seen_it
&& (count
& 1))
11334 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
11339 insn
= (b
[0]) | (b
[1] << 8);
11341 insn
= (b
[1]) | (b
[0] << 8);
11344 if ((insn
& 0xf800) < 0xe800)
11346 /* Addr + 2 is an instruction boundary. See if this matches
11347 the expected boundary based on the position of the last
11354 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
11356 enum map_type type
= MAP_ARM
;
11357 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
11359 if (!found
|| (found
&& type
== MAP_THUMB
))
11361 /* This could be an IT instruction. */
11363 it_count
= count
>> 1;
11366 if ((insn
& 0xf800) >= 0xe800)
11369 count
= (count
+ 2) | 1;
11370 /* IT blocks contain at most 4 instructions. */
11371 if (count
>= 8 && !seen_it
)
11374 /* We found an IT instruction. */
11375 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
11376 if ((ifthen_state
& 0xf) == 0)
11380 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11384 is_mapping_symbol (struct disassemble_info
*info
, int n
,
11385 enum map_type
*map_type
)
11389 name
= bfd_asymbol_name (info
->symtab
[n
]);
11390 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
11391 && (name
[2] == 0 || name
[2] == '.'))
11393 *map_type
= ((name
[1] == 'a') ? MAP_ARM
11394 : (name
[1] == 't') ? MAP_THUMB
11402 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11403 Returns nonzero if *MAP_TYPE was set. */
11406 get_map_sym_type (struct disassemble_info
*info
,
11408 enum map_type
*map_type
)
11410 /* If the symbol is in a different section, ignore it. */
11411 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
11414 return is_mapping_symbol (info
, n
, map_type
);
11417 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
11418 Returns nonzero if *MAP_TYPE was set. */
11421 get_sym_code_type (struct disassemble_info
*info
,
11423 enum map_type
*map_type
)
11425 elf_symbol_type
*es
;
11428 /* If the symbol is in a different section, ignore it. */
11429 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
11432 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
11433 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
11435 /* If the symbol has function type then use that. */
11436 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
11438 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
11439 == ST_BRANCH_TO_THUMB
)
11440 *map_type
= MAP_THUMB
;
11442 *map_type
= MAP_ARM
;
11449 /* Search the mapping symbol state for instruction at pc. This is only
11450 applicable for elf target.
11452 There is an assumption Here, info->private_data contains the correct AND
11453 up-to-date information about current scan process. The information will be
11454 used to speed this search process.
11456 Return TRUE if the mapping state can be determined, and map_symbol
11457 will be updated accordingly. Otherwise, return FALSE. */
11460 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
11461 enum map_type
*map_symbol
)
11463 bfd_vma addr
, section_vma
= 0;
11464 int n
, last_sym
= -1;
11465 bfd_boolean found
= FALSE
;
11466 bfd_boolean can_use_search_opt_p
= FALSE
;
11468 /* Default to DATA. A text section is required by the ABI to contain an
11469 INSN mapping symbol at the start. A data section has no such
11470 requirement, hence if no mapping symbol is found the section must
11471 contain only data. This however isn't very useful if the user has
11472 fully stripped the binaries. If this is the case use the section
11473 attributes to determine the default. If we have no section default to
11474 INSN as well, as we may be disassembling some raw bytes on a baremetal
11475 HEX file or similar. */
11476 enum map_type type
= MAP_DATA
;
11477 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
11479 struct arm_private_data
*private_data
;
11481 if (info
->private_data
== NULL
11482 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
11485 private_data
= info
->private_data
;
11487 /* First, look for mapping symbols. */
11488 if (info
->symtab_size
!= 0)
11490 if (pc
<= private_data
->last_mapping_addr
)
11491 private_data
->last_mapping_sym
= -1;
11493 /* Start scanning at the start of the function, or wherever
11494 we finished last time. */
11495 n
= info
->symtab_pos
+ 1;
11497 /* If the last stop offset is different from the current one it means we
11498 are disassembling a different glob of bytes. As such the optimization
11499 would not be safe and we should start over. */
11500 can_use_search_opt_p
11501 = private_data
->last_mapping_sym
>= 0
11502 && info
->stop_offset
== private_data
->last_stop_offset
;
11504 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
11505 n
= private_data
->last_mapping_sym
;
11507 /* Look down while we haven't passed the location being disassembled.
11508 The reason for this is that there's no defined order between a symbol
11509 and an mapping symbol that may be at the same address. We may have to
11510 look at least one position ahead. */
11511 for (; n
< info
->symtab_size
; n
++)
11513 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11516 if (get_map_sym_type (info
, n
, &type
))
11525 n
= info
->symtab_pos
;
11526 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
11527 n
= private_data
->last_mapping_sym
;
11529 /* No mapping symbol found at this address. Look backwards
11530 for a preceeding one, but don't go pass the section start
11531 otherwise a data section with no mapping symbol can pick up
11532 a text mapping symbol of a preceeding section. The documentation
11533 says section can be NULL, in which case we will seek up all the
11536 section_vma
= info
->section
->vma
;
11538 for (; n
>= 0; n
--)
11540 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11541 if (addr
< section_vma
)
11544 if (get_map_sym_type (info
, n
, &type
))
11554 /* If no mapping symbol was found, try looking up without a mapping
11555 symbol. This is done by walking up from the current PC to the nearest
11556 symbol. We don't actually have to loop here since symtab_pos will
11557 contain the nearest symbol already. */
11560 n
= info
->symtab_pos
;
11561 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
11568 private_data
->last_mapping_sym
= last_sym
;
11569 private_data
->last_type
= type
;
11570 private_data
->last_stop_offset
= info
->stop_offset
;
11572 *map_symbol
= type
;
11576 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11577 of the supplied arm_feature_set structure with bitmasks indicating
11578 the supported base architectures and coprocessor extensions.
11580 FIXME: This could more efficiently implemented as a constant array,
11581 although it would also be less robust. */
11584 select_arm_features (unsigned long mach
,
11585 arm_feature_set
* features
)
11587 arm_feature_set arch_fset
;
11588 const arm_feature_set fpu_any
= FPU_ANY
;
11590 #undef ARM_SET_FEATURES
11591 #define ARM_SET_FEATURES(FSET) \
11593 const arm_feature_set fset = FSET; \
11594 arch_fset = fset; \
11597 /* When several architecture versions share the same bfd_mach_arm_XXX value
11598 the most featureful is chosen. */
11601 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
11602 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
11603 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
11604 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
11605 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
11606 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
11607 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
11608 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
11609 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
11610 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
11611 case bfd_mach_arm_ep9312
:
11612 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
11613 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
11615 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
11616 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
11617 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
11618 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
11619 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
11620 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
11621 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
11622 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
11623 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
11624 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
11625 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
11626 case bfd_mach_arm_8
:
11628 /* Add bits for extensions that Armv8.5-A recognizes. */
11629 arm_feature_set armv8_5_ext_fset
11630 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
11631 ARM_SET_FEATURES (ARM_ARCH_V8_5A
);
11632 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_5_ext_fset
);
11635 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
11636 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
11637 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
11638 case bfd_mach_arm_8_1M_MAIN
:
11639 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
11642 /* If the machine type is unknown allow all architecture types and all
11644 case bfd_mach_arm_unknown
: ARM_SET_FEATURES (ARM_FEATURE_ALL
); break;
11648 #undef ARM_SET_FEATURES
11650 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11651 and thus on bfd_mach_arm_XXX value. Therefore for a given
11652 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11653 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
11657 /* NOTE: There are no checks in these routines that
11658 the relevant number of data bytes exist. */
11661 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
11663 unsigned char b
[4];
11666 int is_thumb
= FALSE
;
11667 int is_data
= FALSE
;
11669 unsigned int size
= 4;
11670 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
11671 bfd_boolean found
= FALSE
;
11672 struct arm_private_data
*private_data
;
11674 if (info
->disassembler_options
)
11676 parse_arm_disassembler_options (info
->disassembler_options
);
11678 /* To avoid repeated parsing of these options, we remove them here. */
11679 info
->disassembler_options
= NULL
;
11682 /* PR 10288: Control which instructions will be disassembled. */
11683 if (info
->private_data
== NULL
)
11685 static struct arm_private_data
private;
11687 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
11688 /* If the user did not use the -m command line switch then default to
11689 disassembling all types of ARM instruction.
11691 The info->mach value has to be ignored as this will be based on
11692 the default archictecture for the target and/or hints in the notes
11693 section, but it will never be greater than the current largest arm
11694 machine value (iWMMXt2), which is only equivalent to the V5TE
11695 architecture. ARM architectures have advanced beyond the machine
11696 value encoding, and these newer architectures would be ignored if
11697 the machine value was used.
11699 Ie the -m switch is used to restrict which instructions will be
11700 disassembled. If it is necessary to use the -m switch to tell
11701 objdump that an ARM binary is being disassembled, eg because the
11702 input is a raw binary file, but it is also desired to disassemble
11703 all ARM instructions then use "-marm". This will select the
11704 "unknown" arm architecture which is compatible with any ARM
11706 info
->mach
= bfd_mach_arm_unknown
;
11708 /* Compute the architecture bitmask from the machine number.
11709 Note: This assumes that the machine number will not change
11710 during disassembly.... */
11711 select_arm_features (info
->mach
, & private.features
);
11713 private.last_mapping_sym
= -1;
11714 private.last_mapping_addr
= 0;
11715 private.last_stop_offset
= 0;
11717 info
->private_data
= & private;
11720 private_data
= info
->private_data
;
11722 /* Decide if our code is going to be little-endian, despite what the
11723 function argument might say. */
11724 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
11726 /* For ELF, consult the symbol table to determine what kind of code
11727 or data we have. */
11728 if (info
->symtab_size
!= 0
11729 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
11734 enum map_type type
= MAP_ARM
;
11736 found
= mapping_symbol_for_insn (pc
, info
, &type
);
11737 last_sym
= private_data
->last_mapping_sym
;
11739 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
11740 is_data
= (private_data
->last_type
== MAP_DATA
);
11742 /* Look a little bit ahead to see if we should print out
11743 two or four bytes of data. If there's a symbol,
11744 mapping or otherwise, after two bytes then don't
11748 size
= 4 - (pc
& 3);
11749 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
11751 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11753 && (info
->section
== NULL
11754 || info
->section
== info
->symtab
[n
]->section
))
11756 if (addr
- pc
< size
)
11761 /* If the next symbol is after three bytes, we need to
11762 print only part of the data, so that we can use either
11763 .byte or .short. */
11765 size
= (pc
& 1) ? 1 : 2;
11769 if (info
->symbols
!= NULL
)
11771 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
11773 coff_symbol_type
* cs
;
11775 cs
= coffsymbol (*info
->symbols
);
11776 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
11777 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
11778 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
11779 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
11780 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
11782 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
11785 /* If no mapping symbol has been found then fall back to the type
11786 of the function symbol. */
11787 elf_symbol_type
* es
;
11790 es
= *(elf_symbol_type
**)(info
->symbols
);
11791 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
11794 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
11795 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
11797 else if (bfd_asymbol_flavour (*info
->symbols
)
11798 == bfd_target_mach_o_flavour
)
11800 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
11802 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
11810 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
11812 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
11814 info
->bytes_per_line
= 4;
11816 /* PR 10263: Disassemble data if requested to do so by the user. */
11817 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
11821 /* Size was already set above. */
11822 info
->bytes_per_chunk
= size
;
11823 printer
= print_insn_data
;
11825 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
11828 for (i
= size
- 1; i
>= 0; i
--)
11829 given
= b
[i
] | (given
<< 8);
11831 for (i
= 0; i
< (int) size
; i
++)
11832 given
= b
[i
] | (given
<< 8);
11834 else if (!is_thumb
)
11836 /* In ARM mode endianness is a straightforward issue: the instruction
11837 is four bytes long and is either ordered 0123 or 3210. */
11838 printer
= print_insn_arm
;
11839 info
->bytes_per_chunk
= 4;
11842 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
11844 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
11846 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | (b
[0] << 24);
11850 /* In Thumb mode we have the additional wrinkle of two
11851 instruction lengths. Fortunately, the bits that determine
11852 the length of the current instruction are always to be found
11853 in the first two bytes. */
11854 printer
= print_insn_thumb16
;
11855 info
->bytes_per_chunk
= 2;
11858 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
11860 given
= (b
[0]) | (b
[1] << 8);
11862 given
= (b
[1]) | (b
[0] << 8);
11866 /* These bit patterns signal a four-byte Thumb
11868 if ((given
& 0xF800) == 0xF800
11869 || (given
& 0xF800) == 0xF000
11870 || (given
& 0xF800) == 0xE800)
11872 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
11874 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
11876 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
11878 printer
= print_insn_thumb32
;
11883 if (ifthen_address
!= pc
)
11884 find_ifthen_state (pc
, info
, little_code
);
11888 if ((ifthen_state
& 0xf) == 0x8)
11889 ifthen_next_state
= 0;
11891 ifthen_next_state
= (ifthen_state
& 0xe0)
11892 | ((ifthen_state
& 0xf) << 1);
11898 info
->memory_error_func (status
, pc
, info
);
11901 if (info
->flags
& INSN_HAS_RELOC
)
11902 /* If the instruction has a reloc associated with it, then
11903 the offset field in the instruction will actually be the
11904 addend for the reloc. (We are using REL type relocs).
11905 In such cases, we can ignore the pc when computing
11906 addresses, since the addend is not currently pc-relative. */
11909 printer (pc
, info
, given
);
11913 ifthen_state
= ifthen_next_state
;
11914 ifthen_address
+= size
;
11920 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
11922 /* Detect BE8-ness and record it in the disassembler info. */
11923 if (info
->flavour
== bfd_target_elf_flavour
11924 && info
->section
!= NULL
11925 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
11926 info
->endian_code
= BFD_ENDIAN_LITTLE
;
11928 return print_insn (pc
, info
, FALSE
);
11932 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
11934 return print_insn (pc
, info
, TRUE
);
11937 const disasm_options_and_args_t
*
11938 disassembler_options_arm (void)
11940 static disasm_options_and_args_t
*opts_and_args
;
11942 if (opts_and_args
== NULL
)
11944 disasm_options_t
*opts
;
11947 opts_and_args
= XNEW (disasm_options_and_args_t
);
11948 opts_and_args
->args
= NULL
;
11950 opts
= &opts_and_args
->options
;
11951 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
11952 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
11954 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11956 opts
->name
[i
] = regnames
[i
].name
;
11957 if (regnames
[i
].description
!= NULL
)
11958 opts
->description
[i
] = _(regnames
[i
].description
);
11960 opts
->description
[i
] = NULL
;
11962 /* The array we return must be NULL terminated. */
11963 opts
->name
[i
] = NULL
;
11964 opts
->description
[i
] = NULL
;
11967 return opts_and_args
;
11971 print_arm_disassembler_options (FILE *stream
)
11973 unsigned int i
, max_len
= 0;
11974 fprintf (stream
, _("\n\
11975 The following ARM specific disassembler options are supported for use with\n\
11976 the -M switch:\n"));
11978 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11980 unsigned int len
= strlen (regnames
[i
].name
);
11985 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
11986 fprintf (stream
, " %s%*c %s\n",
11988 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
11989 _(regnames
[i
].description
));