1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* FIXME: Belongs in global header. */
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
47 /* Cached mapping symbol state. */
55 struct arm_private_data
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features
;
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type
;
63 /* Tracking symbol table information */
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset
;
68 bfd_vma last_mapping_addr
;
121 MVE_VSTRB_SCATTER_T1
,
122 MVE_VSTRH_SCATTER_T2
,
123 MVE_VSTRW_SCATTER_T3
,
124 MVE_VSTRD_SCATTER_T4
,
125 MVE_VSTRW_SCATTER_T5
,
126 MVE_VSTRD_SCATTER_T6
,
128 MVE_VCVT_BETWEEN_FP_INT
,
130 MVE_VCVT_FROM_FP_TO_INT
,
133 MVE_VMOV_GP_TO_VEC_LANE
,
136 MVE_VMOV2_VEC_LANE_TO_GP
,
137 MVE_VMOV2_GP_TO_VEC_LANE
,
138 MVE_VMOV_VEC_LANE_TO_GP
,
296 enum mve_unpredictable
298 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
300 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
302 UNPRED_R13
, /* Unpredictable because r13 (sp) or
304 UNPRED_R15
, /* Unpredictable because r15 (pc) is used. */
305 UNPRED_Q_GT_4
, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6
, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB
, /* Unpredictable becase gp reg = r13
311 UNPRED_Q_REGS_EQUAL
, /* Unpredictable because vector registers are
313 UNPRED_OS
, /* Unpredictable because offset scaled == 1. */
314 UNPRED_GP_REGS_EQUAL
, /* Unpredictable because gp registers are the
316 UNPRED_Q_REGS_EQ_AND_SIZE_1
, /* Unpredictable because q regs equal and
318 UNPRED_Q_REGS_EQ_AND_SIZE_2
, /* Unpredictable because q regs equal and
320 UNPRED_NONE
/* No unpredictable behavior. */
325 UNDEF_SIZE
, /* undefined size. */
326 UNDEF_SIZE_0
, /* undefined because size == 0. */
327 UNDEF_SIZE_2
, /* undefined because size == 2. */
328 UNDEF_SIZE_3
, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1
, /* undefined because size <= 1. */
330 UNDEF_SIZE_NOT_0
, /* undefined because size != 0. */
331 UNDEF_SIZE_NOT_2
, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3
, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0
, /* undefined because U == 0 and
335 UNDEF_NOT_UNS_SIZE_1
, /* undefined because U == 0 and
337 UNDEF_NOT_UNSIGNED
, /* undefined because U == 0. */
338 UNDEF_VCVT_IMM6
, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6
, /* fsi = 0 and 32 >= imm6 <= 47. */
340 UNDEF_BAD_OP1_OP2
, /* undefined with op2 = 2 and
342 UNDEF_BAD_U_OP1_OP2
, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE
, /* undefined because op == 0 and cmode
346 UNDEF_XCHG_UNS
, /* undefined because X == 1 and U == 1. */
347 UNDEF_NONE
/* no undefined behavior. */
352 arm_feature_set arch
; /* Architecture defining this insn. */
353 unsigned long value
; /* If arch is 0 then value is a sentinel. */
354 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
355 const char * assembler
; /* How to disassemble this insn. */
360 arm_feature_set arch
; /* Architecture defining this insn. */
361 uint8_t coproc_shift
; /* coproc is this far into op. */
362 uint16_t coproc_mask
; /* Length of coproc field in op. */
363 unsigned long value
; /* If arch is 0 then value is a sentinel. */
364 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
365 const char * assembler
; /* How to disassemble this insn. */
372 arm_feature_set arch
; /* Architecture defining this insn. */
373 enum mve_instructions mve_op
; /* Specific mve instruction for faster
375 unsigned long value
; /* If arch is 0 then value is a sentinel. */
376 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
377 const char * assembler
; /* How to disassemble this insn. */
387 /* Shared (between Arm and Thumb mode) opcode. */
390 enum isa isa
; /* Execution mode instruction availability. */
391 arm_feature_set arch
; /* Architecture defining this insn. */
392 unsigned long value
; /* If arch is 0 then value is a sentinel. */
393 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
394 const char * assembler
; /* How to disassemble this insn. */
399 arm_feature_set arch
; /* Architecture defining this insn. */
400 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
401 const char *assembler
; /* How to disassemble this insn. */
404 /* print_insn_coprocessor recognizes the following format control codes:
408 %c print condition code (always bits 28-31 in ARM mode)
409 %b print condition code allowing cp_num == 9
410 %q print shifter argument
411 %u print condition code (unconditional in ARM mode,
412 UNPREDICTABLE if not AL in Thumb)
413 %A print address for ldc/stc/ldf/stf instruction
414 %B print vstm/vldm register list
415 %C print vscclrm register list
416 %I print cirrus signed shift immediate: bits 0..3|4..6
417 %J print register for VLDR instruction
418 %K print address for VLDR instruction
419 %F print the COUNT field of a LFM/SFM instruction.
420 %P print floating point precision in arithmetic insn
421 %Q print floating point precision in ldf/stf insn
422 %R print floating point rounding mode
424 %<bitfield>c print as a condition code (for vsel)
425 %<bitfield>r print as an ARM register
426 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
427 %<bitfield>ru as %<>r but each u register must be unique.
428 %<bitfield>d print the bitfield in decimal
429 %<bitfield>k print immediate for VFPv3 conversion instruction
430 %<bitfield>x print the bitfield in hex
431 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
432 %<bitfield>f print a floating point constant if >7 else a
433 floating point register
434 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
435 %<bitfield>g print as an iWMMXt 64-bit register
436 %<bitfield>G print as an iWMMXt general purpose or control register
437 %<bitfield>D print as a NEON D register
438 %<bitfield>Q print as a NEON Q register
439 %<bitfield>V print as a NEON D or Q register
440 %<bitfield>E print a quarter-float immediate value
442 %y<code> print a single precision VFP reg.
443 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
444 %z<code> print a double precision VFP reg
445 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
447 %<bitfield>'c print specified char iff bitfield is all ones
448 %<bitfield>`c print specified char iff bitfield is all zeroes
449 %<bitfield>?ab... select from array of values in big endian order
451 %L print as an iWMMXt N/M width field.
452 %Z print the Immediate of a WSHUFH instruction.
453 %l like 'A' except use byte offsets for 'B' & 'H'
455 %i print 5-bit immediate in bits 8,3..0
457 %r print register offset address for wldt/wstr instruction. */
459 enum opcode_sentinel_enum
461 SENTINEL_IWMMXT_START
= 1,
463 SENTINEL_GENERIC_START
466 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
467 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
468 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
469 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
471 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
473 /* print_insn_cde recognizes the following format control codes:
477 %a print 'a' iff bit 28 is 1
478 %p print bits 8-10 as coprocessor
479 %<bitfield>d print as decimal
480 %<bitfield>r print as an ARM register
481 %<bitfield>n print as an ARM register but r15 is APSR_nzcv
482 %<bitfield>T print as an ARM register + 1
483 %<bitfield>R as %r but r13 is UNPREDICTABLE
484 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
485 %j print immediate taken from bits (16..21,7,0..5)
486 %k print immediate taken from bits (20..21,7,0..5).
487 %l print immediate taken from bits (20..22,7,4..5). */
489 /* At the moment there is only one valid position for the coprocessor number,
490 and hence that's encoded in the macro below. */
491 #define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
492 { ARCH, 8, 7, VALUE, MASK, ASM }
493 static const struct cdeopcode32 cde_opcodes
[] =
495 /* Custom Datapath Extension instructions. */
496 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
497 0xee000000, 0xefc00840,
498 "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"),
499 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
500 0xee000040, 0xefc00840,
501 "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"),
503 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
504 0xee400000, 0xefc00840,
505 "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"),
506 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
507 0xee400040, 0xefc00840,
508 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"),
510 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
511 0xee800000, 0xef800840,
512 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"),
513 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
514 0xee800040, 0xef800840,
515 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
517 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
521 static const struct sopcode32 coprocessor_opcodes
[] =
523 /* XScale instructions. */
524 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
525 0x0e200010, 0x0fff0ff0,
526 "mia%c\tacc0, %0-3r, %12-15r"},
527 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
528 0x0e280010, 0x0fff0ff0,
529 "miaph%c\tacc0, %0-3r, %12-15r"},
530 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
531 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
532 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
533 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
534 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
535 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
537 /* Intel Wireless MMX technology instructions. */
538 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
539 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
540 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
541 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
542 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
543 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
544 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
545 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
546 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
547 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
548 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
549 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
550 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
551 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
552 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
553 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
554 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
555 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
556 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
557 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
558 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
559 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
560 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
561 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
562 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
563 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
564 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
565 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
566 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
567 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
568 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
569 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
570 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
571 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
572 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
573 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
574 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
575 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
576 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
577 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
578 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
579 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
580 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
581 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
582 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
583 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
584 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
585 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
586 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
587 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
588 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
589 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
590 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
591 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
592 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
593 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
594 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
595 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
596 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
597 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
598 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
599 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
600 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
601 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
602 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
603 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
604 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
605 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
606 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
607 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
608 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
609 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
610 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
611 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
612 0x0e800120, 0x0f800ff0,
613 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
614 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
615 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
616 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
617 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
618 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
619 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
620 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
621 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
622 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
623 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
624 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
625 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
626 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
627 0x0e8000a0, 0x0f800ff0,
628 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
629 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
630 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
631 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
632 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
633 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
634 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
635 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
636 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
637 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
638 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
639 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
640 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
641 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
642 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
643 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
644 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
645 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
646 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
647 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
648 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
649 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
650 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
651 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
652 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
653 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
654 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
655 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
656 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
657 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
658 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
659 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
660 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
661 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
662 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
663 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
664 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
665 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
666 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
667 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
668 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
669 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
670 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
671 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
672 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
673 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
674 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
675 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
676 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
677 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
678 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
679 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
680 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
681 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
682 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
683 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
684 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
685 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
686 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
687 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
688 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
689 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
690 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
691 {ANY
, ARM_FEATURE_CORE_LOW (0),
692 SENTINEL_IWMMXT_END
, 0, "" },
694 /* Floating point coprocessor (FPA) instructions. */
695 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
696 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
697 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
698 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
699 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
700 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
701 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
702 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
703 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
704 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
705 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
706 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
707 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
708 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
709 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
710 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
711 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
712 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
713 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
714 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
715 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
716 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
717 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
718 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
719 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
720 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
721 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
722 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
723 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
724 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
725 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
726 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
727 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
728 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
729 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
730 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
731 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
732 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
733 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
734 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
735 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
736 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
737 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
738 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
739 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
740 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
741 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
742 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
743 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
744 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
745 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
746 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
747 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
748 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
749 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
750 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
751 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
752 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
753 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
754 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
755 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
756 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
757 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
758 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
759 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
760 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
761 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
762 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
763 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
764 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
765 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
766 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
767 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
768 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
769 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
770 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
771 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
772 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
773 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
774 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
775 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
776 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
777 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
778 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
779 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
780 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
782 /* Armv8.1-M Mainline instructions. */
783 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
784 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
785 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
786 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
788 /* ARMv8-M Mainline Security Extensions instructions. */
789 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
790 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
791 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
792 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
794 /* Register load/store. */
795 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
796 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
797 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
798 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
799 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
800 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
801 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
802 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
803 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
804 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
805 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
806 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
807 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
808 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
809 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
810 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
811 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
812 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
813 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
814 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
815 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
816 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
817 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
818 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
819 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
820 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
821 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
822 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
823 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
824 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
825 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
826 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
827 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
828 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
829 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
830 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
832 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
833 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
834 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
835 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
836 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
837 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
838 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
839 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
841 /* Data transfer between ARM and NEON registers. */
842 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
843 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
844 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
845 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
846 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
847 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
848 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
849 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
850 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
851 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
852 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
853 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
854 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
855 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
856 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
857 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
858 /* Half-precision conversion instructions. */
859 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
860 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
861 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
862 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
863 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
864 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
865 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
866 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
868 /* Floating point coprocessor (VFP) instructions. */
869 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
870 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
871 {ANY
, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN
, FPU_VFP_EXT_V1xD
),
872 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
873 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
874 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
875 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
876 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
877 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
878 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
879 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
880 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
881 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
882 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
883 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
884 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
885 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
886 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
887 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
888 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
889 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
890 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
891 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
892 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
893 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
894 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
895 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
896 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
897 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
898 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
899 {ANY
, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN
, FPU_VFP_EXT_V1xD
),
900 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
901 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
902 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
903 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
904 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
905 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
906 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
907 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
908 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
909 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
910 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
911 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
912 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
913 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
914 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
915 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
916 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
917 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
918 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
919 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
920 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
921 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
922 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
923 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
924 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
925 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
926 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
927 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
928 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
929 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
930 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
931 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
932 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
933 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
934 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
935 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
936 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
937 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
938 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
939 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
940 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
941 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
942 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
943 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
944 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
945 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
946 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
947 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
948 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
949 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
950 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
951 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
952 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
953 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
954 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
955 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
956 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
957 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
958 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
959 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
960 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
961 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
962 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
963 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
964 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
965 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
966 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
967 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
968 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
969 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
970 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
971 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
972 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
973 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
974 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
975 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
976 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
977 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
978 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
979 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
980 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
981 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
982 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
983 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
984 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
985 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
986 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
987 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
988 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
989 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
990 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
991 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
992 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
993 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
994 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
995 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
996 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
997 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
998 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
999 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1000 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
1001 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1002 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
1003 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1004 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
1005 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1006 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
1007 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1008 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
1009 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1010 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
1011 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1012 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
1013 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1014 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
1015 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1016 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
1017 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1018 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
1019 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1020 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
1021 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1022 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
1023 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1024 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
1025 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1026 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
1028 /* Cirrus coprocessor instructions. */
1029 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1030 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
1031 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1032 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
1033 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1034 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
1035 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1036 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
1037 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1038 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
1039 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1040 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
1041 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1042 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
1043 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1044 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
1045 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1046 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
1047 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1048 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
1049 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1050 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
1051 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1052 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
1053 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1054 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
1055 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1056 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
1057 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1058 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1059 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1060 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1061 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1062 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
1063 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1064 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
1065 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1066 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
1067 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1068 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
1069 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1070 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
1071 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1072 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
1073 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1074 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
1075 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1076 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
1077 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1078 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
1079 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1080 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
1081 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1082 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
1083 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1084 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
1085 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1086 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
1087 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1088 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
1089 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1090 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
1091 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1092 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
1093 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1094 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
1095 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1096 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
1097 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1098 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
1099 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1100 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
1101 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1102 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
1103 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1104 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
1105 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1106 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
1107 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1108 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
1109 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1110 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
1111 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1112 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
1113 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1114 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
1115 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1116 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1117 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1118 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1119 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1120 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1121 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1122 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1123 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1124 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1125 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1126 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1127 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1128 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1129 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1130 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1131 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1132 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1133 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1134 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1135 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1136 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1137 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1138 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1139 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1140 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1141 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1142 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1143 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1144 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1145 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1146 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1147 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1148 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1149 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1150 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1151 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1152 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1153 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1154 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1155 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1156 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1157 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1158 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1159 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1160 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1161 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1162 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1163 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1164 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1165 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1166 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1167 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1168 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1169 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1170 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1171 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1172 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1173 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1174 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1175 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1176 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1177 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1178 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1179 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1180 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1181 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1182 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1183 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1184 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1185 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1186 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1187 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1188 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1189 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1190 0x0e000600, 0x0ff00f10,
1191 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1192 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1193 0x0e100600, 0x0ff00f10,
1194 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1195 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1196 0x0e200600, 0x0ff00f10,
1197 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1198 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1199 0x0e300600, 0x0ff00f10,
1200 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1202 /* VFP Fused multiply add instructions. */
1203 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1204 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1205 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1206 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1207 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1208 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1209 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1210 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1211 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1212 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1213 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1214 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1215 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1216 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1217 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1218 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1221 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1222 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1223 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1224 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1225 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1226 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1227 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1228 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1229 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1230 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1231 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1232 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1233 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1234 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1235 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1236 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1237 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1238 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1239 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1240 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1241 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1242 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1243 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1244 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1246 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
1247 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1248 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1249 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1250 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1251 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1252 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1253 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1254 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1255 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1256 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1257 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1258 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1259 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1260 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1261 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1262 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1263 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1264 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1265 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1266 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1267 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1269 /* BFloat16 instructions. */
1270 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1271 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1273 /* Dot Product instructions in the space of coprocessor 13. */
1274 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1275 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1276 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1277 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1279 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1280 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1281 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1282 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1283 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1284 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1285 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1286 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1287 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1288 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1289 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1290 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1291 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1292 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1293 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1294 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1295 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1297 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1298 cp_num: bit <11:8> == 0b1001.
1299 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1300 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1301 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1302 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1303 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1304 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1305 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1306 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1307 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1308 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1309 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1310 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1311 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1312 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1313 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1314 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1315 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1316 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1317 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1318 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1319 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1320 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1321 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1322 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1323 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1324 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1325 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1326 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1327 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1328 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1329 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1330 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1331 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1332 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1333 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1334 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1335 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1336 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1337 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1338 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1339 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1340 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1341 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1342 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1343 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1344 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1345 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1346 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1347 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1348 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1349 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1350 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1351 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1352 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1353 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1354 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1355 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1356 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1357 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1358 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1359 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1360 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1361 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1362 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1363 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1364 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1365 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1366 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1367 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1368 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1369 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1371 /* ARMv8.3 javascript conversion instruction. */
1372 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1373 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1375 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1378 /* Generic coprocessor instructions. These are only matched if a more specific
1379 SIMD or co-processor instruction does not match first. */
1381 static const struct sopcode32 generic_coprocessor_opcodes
[] =
1383 /* Generic coprocessor instructions. */
1384 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1385 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1386 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1387 0x0c500000, 0x0ff00000,
1388 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1389 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1390 0x0e000000, 0x0f000010,
1391 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1392 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1393 0x0e10f010, 0x0f10f010,
1394 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1395 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1396 0x0e100010, 0x0f100010,
1397 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1398 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1399 0x0e000010, 0x0f100010,
1400 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1401 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1402 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1403 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1404 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1406 /* V6 coprocessor instructions. */
1407 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1408 0xfc500000, 0xfff00000,
1409 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1410 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1411 0xfc400000, 0xfff00000,
1412 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1414 /* V5 coprocessor instructions. */
1415 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1416 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1417 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1418 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1419 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1420 0xfe000000, 0xff000010,
1421 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1422 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1423 0xfe000010, 0xff100010,
1424 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1425 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1426 0xfe100010, 0xff100010,
1427 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1429 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1432 /* Neon opcode table: This does not encode the top byte -- that is
1433 checked by the print_insn_neon routine, as it depends on whether we are
1434 doing thumb32 or arm32 disassembly. */
1436 /* print_insn_neon recognizes the following format control codes:
1440 %c print condition code
1441 %u print condition code (unconditional in ARM mode,
1442 UNPREDICTABLE if not AL in Thumb)
1443 %A print v{st,ld}[1234] operands
1444 %B print v{st,ld}[1234] any one operands
1445 %C print v{st,ld}[1234] single->all operands
1447 %E print vmov, vmvn, vorr, vbic encoded constant
1448 %F print vtbl,vtbx register list
1450 %<bitfield>r print as an ARM register
1451 %<bitfield>d print the bitfield in decimal
1452 %<bitfield>e print the 2^N - bitfield in decimal
1453 %<bitfield>D print as a NEON D register
1454 %<bitfield>Q print as a NEON Q register
1455 %<bitfield>R print as a NEON D or Q register
1456 %<bitfield>Sn print byte scaled width limited by n
1457 %<bitfield>Tn print short scaled width limited by n
1458 %<bitfield>Un print long scaled width limited by n
1460 %<bitfield>'c print specified char iff bitfield is all ones
1461 %<bitfield>`c print specified char iff bitfield is all zeroes
1462 %<bitfield>?ab... select from array of values in big endian order. */
1464 static const struct opcode32 neon_opcodes
[] =
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1468 0xf2b00840, 0xffb00850,
1469 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1471 0xf2b00000, 0xffb00810,
1472 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1474 /* Data transfer between ARM and NEON registers. */
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1476 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1478 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1480 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1482 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1484 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1486 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1488 /* Move data element to all lanes. */
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1490 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1492 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1494 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1498 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1500 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1502 /* Half-precision conversions. */
1503 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1504 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1505 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1506 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1508 /* NEON fused multiply add instructions. */
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1510 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1512 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1514 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1516 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1518 /* BFloat16 instructions. */
1519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1520 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1521 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1522 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1524 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1526 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1528 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1530 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1532 /* Matrix Multiply instructions. */
1533 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1534 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1536 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1538 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1540 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1542 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1544 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1546 /* Two registers, miscellaneous. */
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1548 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1550 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1552 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1554 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1555 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1556 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1557 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1558 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1559 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1560 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1561 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1562 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1563 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1564 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1565 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1566 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1567 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1568 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1570 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1572 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1574 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1576 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1578 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1580 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1582 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1584 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1586 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1588 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1590 0xf3b20300, 0xffb30fd0,
1591 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1593 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1594 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1595 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1597 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1598 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1599 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1601 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1603 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1605 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1607 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1609 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1611 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1613 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1615 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1617 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1619 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1621 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1623 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1625 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1627 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1629 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1631 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1633 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1635 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1637 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1639 0xf3bb0600, 0xffbf0e10,
1640 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1641 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1642 0xf3b70600, 0xffbf0e10,
1643 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1645 /* Three registers of the same length. */
1646 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1647 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1648 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1649 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1650 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1651 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1652 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1653 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1654 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1655 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1656 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1657 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1658 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1659 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1661 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1663 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1665 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1666 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1667 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1669 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1671 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1673 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1675 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1677 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1679 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1681 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1683 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1685 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1687 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1689 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1691 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1693 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1695 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1697 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1699 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1701 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1703 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1705 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1707 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1709 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1711 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1713 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1715 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1717 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1718 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1719 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1721 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1723 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1725 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1727 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1729 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1731 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1733 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1735 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1737 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1739 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1741 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1743 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1745 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1747 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1749 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1751 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1753 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1755 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1757 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1759 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1761 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1763 0xf2000b00, 0xff800f10,
1764 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1765 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1766 0xf2000b10, 0xff800f10,
1767 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1769 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1771 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1773 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1775 0xf3000b00, 0xff800f10,
1776 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1778 0xf2000000, 0xfe800f10,
1779 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1780 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1781 0xf2000010, 0xfe800f10,
1782 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1784 0xf2000100, 0xfe800f10,
1785 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1787 0xf2000200, 0xfe800f10,
1788 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1790 0xf2000210, 0xfe800f10,
1791 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1792 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1793 0xf2000300, 0xfe800f10,
1794 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1796 0xf2000310, 0xfe800f10,
1797 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1798 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1799 0xf2000400, 0xfe800f10,
1800 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1802 0xf2000410, 0xfe800f10,
1803 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1805 0xf2000500, 0xfe800f10,
1806 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1808 0xf2000510, 0xfe800f10,
1809 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1811 0xf2000600, 0xfe800f10,
1812 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1813 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1814 0xf2000610, 0xfe800f10,
1815 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1817 0xf2000700, 0xfe800f10,
1818 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1820 0xf2000710, 0xfe800f10,
1821 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1823 0xf2000910, 0xfe800f10,
1824 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1825 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1826 0xf2000a00, 0xfe800f10,
1827 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1829 0xf2000a10, 0xfe800f10,
1830 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1831 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1832 0xf3000b10, 0xff800f10,
1833 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1835 0xf3000c10, 0xff800f10,
1836 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1838 /* One register and an immediate value. */
1839 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1840 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1842 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1844 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1845 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1846 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1848 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1850 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1852 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1854 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1856 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1858 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1860 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1862 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1864 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1866 /* Two registers and a shift amount. */
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1868 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1870 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1872 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1874 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1876 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1878 0xf2880950, 0xfeb80fd0,
1879 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1881 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1882 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1883 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1885 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1886 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1887 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1889 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1891 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1893 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1895 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1897 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1899 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1901 0xf2900950, 0xfeb00fd0,
1902 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1904 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1905 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1906 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1907 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1908 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1910 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1911 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1912 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1913 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1914 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1916 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1917 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1918 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1920 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1922 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1924 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1925 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1926 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1928 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1930 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1931 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1932 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1934 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1936 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1937 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1938 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1940 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1942 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1944 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1945 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1946 0xf2a00950, 0xfea00fd0,
1947 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1949 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1951 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1952 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1953 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1954 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1955 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1956 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1957 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1958 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1959 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1961 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1963 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1965 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1967 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1969 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1970 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1971 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1972 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1973 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1975 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1976 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1977 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1978 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1979 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1981 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1982 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1983 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1985 0xf2a00e10, 0xfea00e90,
1986 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1988 0xf2a00c10, 0xfea00e90,
1989 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1991 /* Three registers of different lengths. */
1992 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1993 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1995 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1997 0xf2800400, 0xff800f50,
1998 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1999 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2000 0xf2800600, 0xff800f50,
2001 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2002 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2003 0xf2800900, 0xff800f50,
2004 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2005 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2006 0xf2800b00, 0xff800f50,
2007 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2008 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2009 0xf2800d00, 0xff800f50,
2010 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2011 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2012 0xf3800400, 0xff800f50,
2013 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2014 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2015 0xf3800600, 0xff800f50,
2016 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2018 0xf2800000, 0xfe800f50,
2019 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2020 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2021 0xf2800100, 0xfe800f50,
2022 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2024 0xf2800200, 0xfe800f50,
2025 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2026 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2027 0xf2800300, 0xfe800f50,
2028 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2030 0xf2800500, 0xfe800f50,
2031 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2032 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2033 0xf2800700, 0xfe800f50,
2034 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2036 0xf2800800, 0xfe800f50,
2037 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2038 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2039 0xf2800a00, 0xfe800f50,
2040 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2042 0xf2800c00, 0xfe800f50,
2043 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2045 /* Two registers and a scalar. */
2046 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2047 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2048 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2049 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2050 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2051 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
2052 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2053 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2055 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2056 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2057 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2058 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2059 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
2060 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2061 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2063 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2065 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2066 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2067 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
2068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2069 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2071 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2073 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2075 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2077 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2078 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2079 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2081 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2083 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2084 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2085 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2087 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2089 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2090 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2091 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2093 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2094 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2095 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2097 0xf2800240, 0xfe800f50,
2098 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2099 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2100 0xf2800640, 0xfe800f50,
2101 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2103 0xf2800a40, 0xfe800f50,
2104 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2105 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2106 0xf2800e40, 0xff800f50,
2107 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2109 0xf2800f40, 0xff800f50,
2110 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2111 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2112 0xf3800e40, 0xff800f50,
2113 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2114 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2115 0xf3800f40, 0xff800f50,
2116 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2119 /* Element and structure load/store. */
2120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2121 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2122 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2123 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2125 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2127 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2129 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2131 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2132 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2133 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2134 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2135 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2137 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2139 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2141 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2143 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2145 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2147 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2149 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2151 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2153 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2155 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2156 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2157 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2159 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2162 /* mve opcode table. */
2164 /* print_insn_mve recognizes the following format control codes:
2168 %a print '+' or '-' or imm offset in vldr[bhwd] and
2170 %c print condition code
2171 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2172 %u print 'U' (unsigned) or 'S' for various mve instructions
2173 %i print MVE predicate(s) for vpt and vpst
2174 %j print a 5-bit immediate from hw2[14:12,7:6]
2175 %k print 48 if the 7th position bit is set else print 64.
2176 %m print rounding mode for vcvt and vrint
2177 %n print vector comparison code for predicated instruction
2178 %s print size for various vcvt instructions
2179 %v print vector predicate for instruction in predicated
2181 %o print offset scaled for vldr[hwd] and vstr[hwd]
2182 %w print writeback mode for MVE v{st,ld}[24]
2183 %B print v{st,ld}[24] any one operands
2184 %E print vmov, vmvn, vorr, vbic encoded constant
2185 %N print generic index for vmov
2186 %T print bottom ('b') or top ('t') of source register
2187 %X print exchange field in vmla* instructions
2189 %<bitfield>r print as an ARM register
2190 %<bitfield>d print the bitfield in decimal
2191 %<bitfield>A print accumulate or not
2192 %<bitfield>c print bitfield as a condition code
2193 %<bitfield>C print bitfield as an inverted condition code
2194 %<bitfield>Q print as a MVE Q register
2195 %<bitfield>F print as a MVE S register
2196 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2199 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
2200 %<bitfield>s print size for vector predicate & non VMOV instructions
2201 %<bitfield>I print carry flag or not
2202 %<bitfield>i print immediate for vstr/vldr reg +/- imm
2203 %<bitfield>h print high half of 64-bit destination reg
2204 %<bitfield>k print immediate for vector conversion instruction
2205 %<bitfield>l print low half of 64-bit destination reg
2206 %<bitfield>o print rotate value for vcmul
2207 %<bitfield>u print immediate value for vddup/vdwdup
2208 %<bitfield>x print the bitfield in hex.
2211 static const struct mopcode32 mve_opcodes
[] =
2215 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2217 0xfe310f4d, 0xffbf1fff,
2221 /* Floating point VPT T1. */
2222 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2224 0xee310f00, 0xefb10f50,
2225 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2226 /* Floating point VPT T2. */
2227 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2229 0xee310f40, 0xefb10f50,
2230 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2232 /* Vector VPT T1. */
2233 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2235 0xfe010f00, 0xff811f51,
2236 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2237 /* Vector VPT T2. */
2238 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2240 0xfe010f01, 0xff811f51,
2241 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2242 /* Vector VPT T3. */
2243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2245 0xfe011f00, 0xff811f50,
2246 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2247 /* Vector VPT T4. */
2248 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2250 0xfe010f40, 0xff811f70,
2251 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2252 /* Vector VPT T5. */
2253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2255 0xfe010f60, 0xff811f70,
2256 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2257 /* Vector VPT T6. */
2258 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2260 0xfe011f40, 0xff811f50,
2261 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2263 /* Vector VBIC immediate. */
2264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2266 0xef800070, 0xefb81070,
2267 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2269 /* Vector VBIC register. */
2270 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2272 0xef100150, 0xffb11f51,
2273 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2278 0xee800f01, 0xefc10f51,
2279 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2281 /* Vector VABD floating point. */
2282 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2284 0xff200d40, 0xffa11f51,
2285 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2288 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2290 0xef000740, 0xef811f51,
2291 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2293 /* Vector VABS floating point. */
2294 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2296 0xFFB10740, 0xFFB31FD1,
2297 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2299 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2301 0xffb10340, 0xffb31fd1,
2302 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2304 /* Vector VADD floating point T1. */
2305 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2307 0xef000d40, 0xffa11f51,
2308 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2309 /* Vector VADD floating point T2. */
2310 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2312 0xee300f40, 0xefb11f70,
2313 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2314 /* Vector VADD T1. */
2315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2317 0xef000840, 0xff811f51,
2318 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2319 /* Vector VADD T2. */
2320 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2322 0xee010f40, 0xff811f70,
2323 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2325 /* Vector VADDLV. */
2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2328 0xee890f00, 0xef8f1fd1,
2329 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2332 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2334 0xeef10f00, 0xeff31fd1,
2335 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2338 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2340 0xee300f00, 0xffb10f51,
2341 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2344 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2346 0xef000150, 0xffb11f51,
2347 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2349 /* Vector VBRSR register. */
2350 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2352 0xfe011e60, 0xff811f70,
2353 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2355 /* Vector VCADD floating point. */
2356 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2358 0xfc800840, 0xfea11f51,
2359 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2364 0xfe000f00, 0xff810f51,
2365 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2368 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2370 0xffb00440, 0xffb31fd1,
2371 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2374 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2376 0xffb004c0, 0xffb31fd1,
2377 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2380 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2382 0xfc200840, 0xfe211f51,
2383 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2385 /* Vector VCMP floating point T1. */
2386 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2388 0xee310f00, 0xeff1ef50,
2389 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2391 /* Vector VCMP floating point T2. */
2392 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2394 0xee310f40, 0xeff1ef50,
2395 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2397 /* Vector VCMP T1. */
2398 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2400 0xfe010f00, 0xffc1ff51,
2401 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2402 /* Vector VCMP T2. */
2403 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2405 0xfe010f01, 0xffc1ff51,
2406 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2407 /* Vector VCMP T3. */
2408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2410 0xfe011f00, 0xffc1ff50,
2411 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2412 /* Vector VCMP T4. */
2413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2415 0xfe010f40, 0xffc1ff70,
2416 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2417 /* Vector VCMP T5. */
2418 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2420 0xfe010f60, 0xffc1ff70,
2421 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2422 /* Vector VCMP T6. */
2423 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2425 0xfe011f40, 0xffc1ff50,
2426 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2431 0xeea00b10, 0xffb10f5f,
2432 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2435 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2437 0xff000150, 0xffd11f51,
2438 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2440 /* Vector VFMA, vector * scalar. */
2441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2443 0xee310e40, 0xefb11f70,
2444 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2446 /* Vector VFMA floating point. */
2447 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2449 0xef000c50, 0xffa11f51,
2450 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2452 /* Vector VFMS floating point. */
2453 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2455 0xef200c50, 0xffa11f51,
2456 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2458 /* Vector VFMAS, vector * scalar. */
2459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2460 MVE_VFMAS_FP_SCALAR
,
2461 0xee311e40, 0xefb11f70,
2462 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2464 /* Vector VHADD T1. */
2465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2467 0xef000040, 0xef811f51,
2468 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2470 /* Vector VHADD T2. */
2471 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2473 0xee000f40, 0xef811f70,
2474 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2476 /* Vector VHSUB T1. */
2477 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2479 0xef000240, 0xef811f51,
2480 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2482 /* Vector VHSUB T2. */
2483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2485 0xee001f40, 0xef811f70,
2486 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2489 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2491 0xee300e00, 0xefb10f50,
2492 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2497 0xf000e801, 0xffc0ffff,
2498 "vctp%v.%20-21s\t%16-19r"},
2501 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2503 0xeea00b10, 0xffb10f5f,
2504 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2506 /* Vector VRHADD. */
2507 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2509 0xef000140, 0xef811f51,
2510 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2513 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2514 MVE_VCVT_FP_FIX_VEC
,
2515 0xef800c50, 0xef801cd1,
2516 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2520 MVE_VCVT_BETWEEN_FP_INT
,
2521 0xffb30640, 0xffb31e51,
2522 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2524 /* Vector VCVT between single and half-precision float, bottom half. */
2525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2526 MVE_VCVT_FP_HALF_FP
,
2527 0xee3f0e01, 0xefbf1fd1,
2528 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2530 /* Vector VCVT between single and half-precision float, top half. */
2531 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2532 MVE_VCVT_FP_HALF_FP
,
2533 0xee3f1e01, 0xefbf1fd1,
2534 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2538 MVE_VCVT_FROM_FP_TO_INT
,
2539 0xffb30040, 0xffb31c51,
2540 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2545 0xee011f6e, 0xff811f7e,
2546 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2548 /* Vector VDWDUP. */
2549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2551 0xee011f60, 0xff811f70,
2552 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2554 /* Vector VHCADD. */
2555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2557 0xee000f00, 0xff810f51,
2558 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2560 /* Vector VIWDUP. */
2561 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2563 0xee010f60, 0xff811f70,
2564 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2567 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2569 0xee010f6e, 0xff811f7e,
2570 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2573 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2575 0xfc901e00, 0xff901e5f,
2576 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2579 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2581 0xfc901e01, 0xff901e1f,
2582 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2584 /* Vector VLDRB gather load. */
2585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2586 MVE_VLDRB_GATHER_T1
,
2587 0xec900e00, 0xefb01e50,
2588 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2590 /* Vector VLDRH gather load. */
2591 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2592 MVE_VLDRH_GATHER_T2
,
2593 0xec900e10, 0xefb01e50,
2594 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2596 /* Vector VLDRW gather load. */
2597 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2598 MVE_VLDRW_GATHER_T3
,
2599 0xfc900f40, 0xffb01fd0,
2600 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2602 /* Vector VLDRD gather load. */
2603 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2604 MVE_VLDRD_GATHER_T4
,
2605 0xec900fd0, 0xefb01fd0,
2606 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2608 /* Vector VLDRW gather load. */
2609 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2610 MVE_VLDRW_GATHER_T5
,
2611 0xfd101e00, 0xff111f00,
2612 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2614 /* Vector VLDRD gather load, variant T6. */
2615 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2616 MVE_VLDRD_GATHER_T6
,
2617 0xfd101f00, 0xff111f00,
2618 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2621 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2623 0xec100e00, 0xee581e00,
2624 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2629 0xec180e00, 0xee581e00,
2630 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2632 /* Vector VLDRB unsigned, variant T5. */
2633 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2635 0xec101e00, 0xfe101f80,
2636 "vldrb%v.u8\t%13-15,22Q, %d"},
2638 /* Vector VLDRH unsigned, variant T6. */
2639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2641 0xec101e80, 0xfe101f80,
2642 "vldrh%v.u16\t%13-15,22Q, %d"},
2644 /* Vector VLDRW unsigned, variant T7. */
2645 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2647 0xec101f00, 0xfe101f80,
2648 "vldrw%v.u32\t%13-15,22Q, %d"},
2651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2653 0xef000640, 0xef811f51,
2654 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2659 0xee330e81, 0xffb31fd1,
2660 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2662 /* Vector VMAXNM floating point. */
2663 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2665 0xff000f50, 0xffa11f51,
2666 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2668 /* Vector VMAXNMA floating point. */
2669 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2671 0xee3f0e81, 0xefbf1fd1,
2672 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2674 /* Vector VMAXNMV floating point. */
2675 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2677 0xeeee0f00, 0xefff0fd1,
2678 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2680 /* Vector VMAXNMAV floating point. */
2681 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2683 0xeeec0f00, 0xefff0fd1,
2684 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2687 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2689 0xeee20f00, 0xeff30fd1,
2690 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2692 /* Vector VMAXAV. */
2693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2695 0xeee00f00, 0xfff30fd1,
2696 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2699 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2701 0xef000650, 0xef811f51,
2702 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2705 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2707 0xee331e81, 0xffb31fd1,
2708 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2710 /* Vector VMINNM floating point. */
2711 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2713 0xff200f50, 0xffa11f51,
2714 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2716 /* Vector VMINNMA floating point. */
2717 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2719 0xee3f1e81, 0xefbf1fd1,
2720 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2722 /* Vector VMINNMV floating point. */
2723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2725 0xeeee0f80, 0xefff0fd1,
2726 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2728 /* Vector VMINNMAV floating point. */
2729 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2731 0xeeec0f80, 0xefff0fd1,
2732 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2737 0xeee20f80, 0xeff30fd1,
2738 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2740 /* Vector VMINAV. */
2741 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2743 0xeee00f80, 0xfff30fd1,
2744 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2747 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2749 0xee010e40, 0xef811f70,
2750 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2752 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2756 0xee801e00, 0xef801f51,
2757 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2759 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2761 0xee800e00, 0xef801f51,
2762 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2764 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2765 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2767 0xeef00e00, 0xeff01f51,
2768 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2770 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2771 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2773 0xeef00f00, 0xeff11f51,
2774 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2776 /* Vector VMLADAV T1 variant. */
2777 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2779 0xeef01e00, 0xeff01f51,
2780 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2782 /* Vector VMLADAV T2 variant. */
2783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2785 0xeef01f00, 0xeff11f51,
2786 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2789 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2791 0xee011e40, 0xef811f70,
2792 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2794 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2796 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2798 0xfe800e01, 0xff810f51,
2799 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2801 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2803 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2805 0xee800e01, 0xff800f51,
2806 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2808 /* Vector VMLSDAV T1 Variant. */
2809 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2811 0xeef00e01, 0xfff00f51,
2812 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2814 /* Vector VMLSDAV T2 Variant. */
2815 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2817 0xfef00e01, 0xfff10f51,
2818 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2820 /* Vector VMOV between gpr and half precision register, op == 0. */
2821 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2823 0xee000910, 0xfff00f7f,
2824 "vmov.f16\t%7,16-19F, %12-15r"},
2826 /* Vector VMOV between gpr and half precision register, op == 1. */
2827 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2829 0xee100910, 0xfff00f7f,
2830 "vmov.f16\t%12-15r, %7,16-19F"},
2832 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2833 MVE_VMOV_GP_TO_VEC_LANE
,
2834 0xee000b10, 0xff900f1f,
2835 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2837 /* Vector VORR immediate to vector.
2838 NOTE: MVE_VORR_IMM must appear in the table
2839 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2840 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2842 0xef800050, 0xefb810f0,
2843 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2845 /* Vector VQSHL T2 Variant.
2846 NOTE: MVE_VQSHL_T2 must appear in the table before
2847 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2850 0xef800750, 0xef801fd1,
2851 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2853 /* Vector VQSHLU T3 Variant
2854 NOTE: MVE_VQSHL_T2 must appear in the table before
2855 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2857 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2859 0xff800650, 0xff801fd1,
2860 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2863 NOTE: MVE_VRSHR must appear in the table before
2864 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2865 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2867 0xef800250, 0xef801fd1,
2868 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2871 NOTE: MVE_VSHL must appear in the table before
2872 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2873 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2875 0xef800550, 0xff801fd1,
2876 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2879 NOTE: MVE_VSHR must appear in the table before
2880 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2881 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2883 0xef800050, 0xef801fd1,
2884 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2887 NOTE: MVE_VSLI must appear in the table before
2888 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2889 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2891 0xff800550, 0xff801fd1,
2892 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2895 NOTE: MVE_VSRI must appear in the table before
2896 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2899 0xff800450, 0xff801fd1,
2900 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2902 /* Vector VMOV immediate to vector,
2903 undefinded for cmode == 1111 */
2904 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2905 MVE_VMVN_IMM
, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION
},
2907 /* Vector VMOV immediate to vector,
2909 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2910 MVE_VMOV_IMM_TO_VEC
, 0xef800d50, 0xefb81fd0,
2911 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2913 /* Vector VMOV immediate to vector. */
2914 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2915 MVE_VMOV_IMM_TO_VEC
,
2916 0xef800050, 0xefb810d0,
2917 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2919 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2920 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2921 MVE_VMOV2_VEC_LANE_TO_GP
,
2922 0xec000f00, 0xffb01ff0,
2923 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2925 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2926 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2927 MVE_VMOV2_VEC_LANE_TO_GP
,
2928 0xec000f10, 0xffb01ff0,
2929 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2931 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2932 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2933 MVE_VMOV2_GP_TO_VEC_LANE
,
2934 0xec100f00, 0xffb01ff0,
2935 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2937 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2938 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2939 MVE_VMOV2_GP_TO_VEC_LANE
,
2940 0xec100f10, 0xffb01ff0,
2941 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2943 /* Vector VMOV Vector lane to gpr. */
2944 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2945 MVE_VMOV_VEC_LANE_TO_GP
,
2946 0xee100b10, 0xff100f1f,
2947 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2949 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2950 to instruction opcode aliasing. */
2951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2953 0xeea00f40, 0xefa00fd1,
2954 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2956 /* Vector VMOVL long. */
2957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2959 0xeea00f40, 0xefa70fd1,
2960 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2962 /* Vector VMOV and narrow. */
2963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2965 0xfe310e81, 0xffb30fd1,
2966 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2968 /* Floating point move extract. */
2969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2971 0xfeb00a40, 0xffbf0fd0,
2972 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2974 /* Vector VMUL floating-point T1 variant. */
2975 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2977 0xff000d50, 0xffa11f51,
2978 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2980 /* Vector VMUL floating-point T2 variant. */
2981 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2983 0xee310e60, 0xefb11f70,
2984 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2986 /* Vector VMUL T1 variant. */
2987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2989 0xef000950, 0xff811f51,
2990 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2992 /* Vector VMUL T2 variant. */
2993 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2995 0xee011e60, 0xff811f70,
2996 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2999 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3001 0xee010e01, 0xef811f51,
3002 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3004 /* Vector VRMULH. */
3005 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3007 0xee011e01, 0xef811f51,
3008 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3010 /* Vector VMULL integer. */
3011 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3013 0xee010e00, 0xef810f51,
3014 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3016 /* Vector VMULL polynomial. */
3017 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3019 0xee310e00, 0xefb10f51,
3020 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3022 /* Vector VMVN immediate to vector. */
3023 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3025 0xef800070, 0xefb810f0,
3026 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3028 /* Vector VMVN register. */
3029 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3031 0xffb005c0, 0xffbf1fd1,
3032 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3034 /* Vector VNEG floating point. */
3035 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3037 0xffb107c0, 0xffb31fd1,
3038 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3041 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3043 0xffb103c0, 0xffb31fd1,
3044 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3046 /* Vector VORN, vector bitwise or not. */
3047 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3049 0xef300150, 0xffb11f51,
3050 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3052 /* Vector VORR register. */
3053 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3055 0xef200150, 0xffb11f51,
3056 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3058 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3059 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3060 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3063 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3064 MVE_VMOV_VEC_TO_VEC
,
3065 0xef200150, 0xffb11f51,
3066 "vmov%v\t%13-15,22Q, %17-19,7Q"},
3068 /* Vector VQDMULL T1 variant. */
3069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3071 0xee300f01, 0xefb10f51,
3072 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3075 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3077 0xfe310f4d, 0xffffffff,
3081 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3083 0xfe310f01, 0xffb11f51,
3084 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3087 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3089 0xffb00740, 0xffb31fd1,
3090 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3092 /* Vector VQADD T1 variant. */
3093 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3095 0xef000050, 0xef811f51,
3096 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3098 /* Vector VQADD T2 variant. */
3099 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3101 0xee000f60, 0xef811f70,
3102 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3104 /* Vector VQDMULL T2 variant. */
3105 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3107 0xee300f60, 0xefb10f70,
3108 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3110 /* Vector VQMOVN. */
3111 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3113 0xee330e01, 0xefb30fd1,
3114 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3116 /* Vector VQMOVUN. */
3117 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3119 0xee310e81, 0xffb30fd1,
3120 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3122 /* Vector VQDMLADH. */
3123 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3125 0xee000e00, 0xff810f51,
3126 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3128 /* Vector VQRDMLADH. */
3129 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3131 0xee000e01, 0xff810f51,
3132 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3134 /* Vector VQDMLAH. */
3135 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3137 0xee000e60, 0xff811f70,
3138 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3140 /* Vector VQRDMLAH. */
3141 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3143 0xee000e40, 0xff811f70,
3144 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3146 /* Vector VQDMLASH. */
3147 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3149 0xee001e60, 0xff811f70,
3150 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3152 /* Vector VQRDMLASH. */
3153 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3155 0xee001e40, 0xff811f70,
3156 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3158 /* Vector VQDMLSDH. */
3159 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3161 0xfe000e00, 0xff810f51,
3162 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3164 /* Vector VQRDMLSDH. */
3165 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3167 0xfe000e01, 0xff810f51,
3168 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3170 /* Vector VQDMULH T1 variant. */
3171 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3173 0xef000b40, 0xff811f51,
3174 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3176 /* Vector VQRDMULH T2 variant. */
3177 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3179 0xff000b40, 0xff811f51,
3180 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3182 /* Vector VQDMULH T3 variant. */
3183 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3185 0xee010e60, 0xff811f70,
3186 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3188 /* Vector VQRDMULH T4 variant. */
3189 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3191 0xfe010e60, 0xff811f70,
3192 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3195 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3197 0xffb007c0, 0xffb31fd1,
3198 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3200 /* Vector VQRSHL T1 variant. */
3201 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3203 0xef000550, 0xef811f51,
3204 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3206 /* Vector VQRSHL T2 variant. */
3207 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3209 0xee331ee0, 0xefb31ff0,
3210 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3212 /* Vector VQRSHRN. */
3213 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3215 0xee800f41, 0xefa00fd1,
3216 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3218 /* Vector VQRSHRUN. */
3219 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3221 0xfe800fc0, 0xffa00fd1,
3222 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3224 /* Vector VQSHL T1 Variant. */
3225 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3227 0xee311ee0, 0xefb31ff0,
3228 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3230 /* Vector VQSHL T4 Variant. */
3231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3233 0xef000450, 0xef811f51,
3234 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3236 /* Vector VQSHRN. */
3237 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3239 0xee800f40, 0xefa00fd1,
3240 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3242 /* Vector VQSHRUN. */
3243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3245 0xee800fc0, 0xffa00fd1,
3246 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3248 /* Vector VQSUB T1 Variant. */
3249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3251 0xef000250, 0xef811f51,
3252 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3254 /* Vector VQSUB T2 Variant. */
3255 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3257 0xee001f60, 0xef811f70,
3258 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3260 /* Vector VREV16. */
3261 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3263 0xffb00140, 0xffb31fd1,
3264 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3266 /* Vector VREV32. */
3267 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3269 0xffb000c0, 0xffb31fd1,
3270 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3272 /* Vector VREV64. */
3273 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3275 0xffb00040, 0xffb31fd1,
3276 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3278 /* Vector VRINT floating point. */
3279 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3281 0xffb20440, 0xffb31c51,
3282 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3284 /* Vector VRMLALDAVH. */
3285 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3287 0xee800f00, 0xef811f51,
3288 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3290 /* Vector VRMLALDAVH. */
3291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3293 0xee801f00, 0xef811f51,
3294 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3296 /* Vector VRSHL T1 Variant. */
3297 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3299 0xef000540, 0xef811f51,
3300 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3302 /* Vector VRSHL T2 Variant. */
3303 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3305 0xee331e60, 0xefb31ff0,
3306 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3308 /* Vector VRSHRN. */
3309 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3311 0xfe800fc1, 0xffa00fd1,
3312 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3317 0xfe300f00, 0xffb10f51,
3318 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3320 /* Vector VSHL T2 Variant. */
3321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3323 0xee311e60, 0xefb31ff0,
3324 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3326 /* Vector VSHL T3 Variant. */
3327 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3329 0xef000440, 0xef811f51,
3330 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3333 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3335 0xeea00fc0, 0xffa01ff0,
3336 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3338 /* Vector VSHLL T2 Variant. */
3339 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3341 0xee310e01, 0xefb30fd1,
3342 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3345 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3347 0xee800fc1, 0xffa00fd1,
3348 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3350 /* Vector VST2 no writeback. */
3351 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3353 0xfc801e00, 0xffb01e5f,
3354 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3356 /* Vector VST2 writeback. */
3357 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3359 0xfca01e00, 0xffb01e5f,
3360 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3362 /* Vector VST4 no writeback. */
3363 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3365 0xfc801e01, 0xffb01e1f,
3366 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3368 /* Vector VST4 writeback. */
3369 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3371 0xfca01e01, 0xffb01e1f,
3372 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3374 /* Vector VSTRB scatter store, T1 variant. */
3375 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3376 MVE_VSTRB_SCATTER_T1
,
3377 0xec800e00, 0xffb01e50,
3378 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3380 /* Vector VSTRH scatter store, T2 variant. */
3381 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3382 MVE_VSTRH_SCATTER_T2
,
3383 0xec800e10, 0xffb01e50,
3384 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3386 /* Vector VSTRW scatter store, T3 variant. */
3387 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3388 MVE_VSTRW_SCATTER_T3
,
3389 0xec800e40, 0xffb01e50,
3390 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3392 /* Vector VSTRD scatter store, T4 variant. */
3393 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3394 MVE_VSTRD_SCATTER_T4
,
3395 0xec800fd0, 0xffb01fd0,
3396 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3398 /* Vector VSTRW scatter store, T5 variant. */
3399 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3400 MVE_VSTRW_SCATTER_T5
,
3401 0xfd001e00, 0xff111f00,
3402 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3404 /* Vector VSTRD scatter store, T6 variant. */
3405 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3406 MVE_VSTRD_SCATTER_T6
,
3407 0xfd001f00, 0xff111f00,
3408 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3411 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3413 0xec000e00, 0xfe581e00,
3414 "vstrb%v.%7-8s\t%13-15Q, %d"},
3417 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3419 0xec080e00, 0xfe581e00,
3420 "vstrh%v.%7-8s\t%13-15Q, %d"},
3422 /* Vector VSTRB variant T5. */
3423 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3425 0xec001e00, 0xfe101f80,
3426 "vstrb%v.8\t%13-15,22Q, %d"},
3428 /* Vector VSTRH variant T6. */
3429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3431 0xec001e80, 0xfe101f80,
3432 "vstrh%v.16\t%13-15,22Q, %d"},
3434 /* Vector VSTRW variant T7. */
3435 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3437 0xec001f00, 0xfe101f80,
3438 "vstrw%v.32\t%13-15,22Q, %d"},
3440 /* Vector VSUB floating point T1 variant. */
3441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3443 0xef200d40, 0xffa11f51,
3444 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3446 /* Vector VSUB floating point T2 variant. */
3447 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3449 0xee301f40, 0xefb11f70,
3450 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3452 /* Vector VSUB T1 variant. */
3453 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3455 0xff000840, 0xff811f51,
3456 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3458 /* Vector VSUB T2 variant. */
3459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3461 0xee011f40, 0xff811f70,
3462 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3464 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3466 0xea50012f, 0xfff1813f,
3467 "asrl%c\t%17-19l, %9-11h, %j"},
3469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3471 0xea50012d, 0xfff101ff,
3472 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3476 0xea50010f, 0xfff1813f,
3477 "lsll%c\t%17-19l, %9-11h, %j"},
3479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3481 0xea50010d, 0xfff101ff,
3482 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3484 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3486 0xea50011f, 0xfff1813f,
3487 "lsrl%c\t%17-19l, %9-11h, %j"},
3489 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3491 0xea51012d, 0xfff1017f,
3492 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3494 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3496 0xea500f2d, 0xfff00fff,
3497 "sqrshr%c\t%16-19S, %12-15S"},
3499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3501 0xea51013f, 0xfff1813f,
3502 "sqshll%c\t%17-19l, %9-11h, %j"},
3504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3506 0xea500f3f, 0xfff08f3f,
3507 "sqshl%c\t%16-19S, %j"},
3509 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3511 0xea51012f, 0xfff1813f,
3512 "srshrl%c\t%17-19l, %9-11h, %j"},
3514 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3516 0xea500f2f, 0xfff08f3f,
3517 "srshr%c\t%16-19S, %j"},
3519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3521 0xea51010d, 0xfff1017f,
3522 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3524 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3526 0xea500f0d, 0xfff00fff,
3527 "uqrshl%c\t%16-19S, %12-15S"},
3529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3531 0xea51010f, 0xfff1813f,
3532 "uqshll%c\t%17-19l, %9-11h, %j"},
3534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3536 0xea500f0f, 0xfff08f3f,
3537 "uqshl%c\t%16-19S, %j"},
3539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3541 0xea51011f, 0xfff1813f,
3542 "urshrl%c\t%17-19l, %9-11h, %j"},
3544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3546 0xea500f1f, 0xfff08f3f,
3547 "urshr%c\t%16-19S, %j"},
3549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3551 0xea509000, 0xfff0f000,
3552 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3554 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3556 0xea50a000, 0xfff0f000,
3557 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3561 0xea5f900f, 0xfffff00f,
3562 "cset\t%8-11S, %4-7C"},
3564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3566 0xea5fa00f, 0xfffff00f,
3567 "csetm\t%8-11S, %4-7C"},
3569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3571 0xea508000, 0xfff0f000,
3572 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3576 0xea50b000, 0xfff0f000,
3577 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3579 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3581 0xea509000, 0xfff0f000,
3582 "cinc\t%8-11S, %16-19Z, %4-7C"},
3584 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3586 0xea50a000, 0xfff0f000,
3587 "cinv\t%8-11S, %16-19Z, %4-7C"},
3589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3591 0xea50b000, 0xfff0f000,
3592 "cneg\t%8-11S, %16-19Z, %4-7C"},
3594 {ARM_FEATURE_CORE_LOW (0),
3596 0x00000000, 0x00000000, 0}
3599 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3600 ordered: they must be searched linearly from the top to obtain a correct
3603 /* print_insn_arm recognizes the following format control codes:
3607 %a print address for ldr/str instruction
3608 %s print address for ldr/str halfword/signextend instruction
3609 %S like %s but allow UNPREDICTABLE addressing
3610 %b print branch destination
3611 %c print condition code (always bits 28-31)
3612 %m print register mask for ldm/stm instruction
3613 %o print operand2 (immediate or register + shift)
3614 %p print 'p' iff bits 12-15 are 15
3615 %t print 't' iff bit 21 set and bit 24 clear
3616 %B print arm BLX(1) destination
3617 %C print the PSR sub type.
3618 %U print barrier type.
3619 %P print address for pli instruction.
3621 %<bitfield>r print as an ARM register
3622 %<bitfield>T print as an ARM register + 1
3623 %<bitfield>R as %r but r15 is UNPREDICTABLE
3624 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3625 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3626 %<bitfield>d print the bitfield in decimal
3627 %<bitfield>W print the bitfield plus one in decimal
3628 %<bitfield>x print the bitfield in hex
3629 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3631 %<bitfield>'c print specified char iff bitfield is all ones
3632 %<bitfield>`c print specified char iff bitfield is all zeroes
3633 %<bitfield>?ab... select from array of values in big endian order
3635 %e print arm SMI operand (bits 0..7,8..19).
3636 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3637 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3638 %R print the SPSR/CPSR or banked register of an MRS. */
3640 static const struct opcode32 arm_opcodes
[] =
3642 /* ARM instructions. */
3643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3644 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3646 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
3649 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3651 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3653 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
3655 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3657 0x00800090, 0x0fa000f0,
3658 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3660 0x00a00090, 0x0fa000f0,
3661 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3663 /* V8.2 RAS extension instructions. */
3664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
3665 0xe320f010, 0xffffffff, "esb"},
3667 /* V8 instructions. */
3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3669 0x0320f005, 0x0fffffff, "sevl"},
3670 /* Defined in V8 but is in NOP space so available to all arch. */
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3672 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3673 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
3674 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3676 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3678 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3680 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3682 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3683 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3684 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3686 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3687 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3688 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3689 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3690 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3692 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3693 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3694 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3695 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3696 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3698 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3700 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3701 /* CRC32 instructions. */
3702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3703 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3704 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3705 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3707 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3708 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3709 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3711 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3712 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3713 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3715 /* Privileged Access Never extension instructions. */
3716 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
3717 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3719 /* Virtualization Extension instructions. */
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
3721 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3723 /* Integer Divide Extension instructions. */
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3725 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3727 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3729 /* MP Extension instructions. */
3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3732 /* Speculation Barriers. */
3733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
3735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
3737 /* V7 instructions. */
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3746 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3748 /* ARM V6T2 instructions. */
3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3750 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3752 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3754 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3756 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3759 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3761 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3764 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3765 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3766 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3768 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3770 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3772 /* ARM Security extension instructions. */
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
3774 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3776 /* ARM V6K instructions. */
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3778 0xf57ff01f, 0xffffffff, "clrex"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3780 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3782 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3784 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3786 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3788 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3790 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3792 /* ARMv8.5-A instructions. */
3793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
3795 /* ARM V6K NOP hints. */
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3797 0x0320f001, 0x0fffffff, "yield%c"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3799 0x0320f002, 0x0fffffff, "wfe%c"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3801 0x0320f003, 0x0fffffff, "wfi%c"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3803 0x0320f004, 0x0fffffff, "sev%c"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3805 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3807 /* ARM V6 instructions. */
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3809 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3811 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3813 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3815 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3817 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3819 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3821 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3823 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3825 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3827 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3829 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3831 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3833 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3835 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3837 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3839 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3841 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3843 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3845 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3847 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3849 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3851 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3853 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3855 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3857 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3859 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3861 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3863 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3865 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3867 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3869 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3871 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3873 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3875 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3877 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3879 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3881 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3883 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3885 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3887 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3889 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3891 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3893 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3895 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3897 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3899 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3901 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3903 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3905 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3907 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3909 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3911 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3913 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3915 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3917 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3919 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3921 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3923 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3925 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3927 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3929 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3931 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3933 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3935 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3937 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3939 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3941 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3943 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3945 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3947 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3949 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3951 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3953 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3955 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3957 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3959 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3961 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3963 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3965 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3967 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3969 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3971 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3973 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3975 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3977 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3979 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3981 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3983 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3985 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3987 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3989 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3991 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3993 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3995 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3997 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3999 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4001 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4003 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4005 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4007 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4009 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4011 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4013 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4015 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4017 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4019 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4021 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4023 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4025 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4027 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4029 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4031 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4033 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4035 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4037 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4039 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4041 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4043 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4045 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4047 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4049 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
4050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4051 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
4053 /* V5J instruction. */
4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
4055 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
4057 /* V5 Instructions. */
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4059 0xe1200070, 0xfff000f0,
4060 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4062 0xfa000000, 0xfe000000, "blx\t%B"},
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4064 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4066 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4068 /* V5E "El Segundo" Instructions. */
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4070 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4072 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4074 0xf450f000, 0xfc70f000, "pld\t%a"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4076 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4078 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4080 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4082 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4085 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4087 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4090 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4092 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4094 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4096 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4099 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4101 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4103 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4105 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4108 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4110 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4113 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4115 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4117 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4119 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
4121 /* ARM Instructions. */
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4123 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4126 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4128 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4130 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4132 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4134 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4136 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4139 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4141 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4143 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4145 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4148 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4150 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4152 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4154 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4157 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4159 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4161 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4164 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4166 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4168 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4171 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4173 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4175 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4178 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4180 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4182 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4185 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4187 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4189 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4192 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4194 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4196 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4199 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4201 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4203 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4206 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4208 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4210 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
4213 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
4215 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
4217 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4220 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4222 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4224 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4227 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4229 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4231 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4234 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4236 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4238 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4241 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4243 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4245 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4248 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4250 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4252 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4255 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4257 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4259 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4261 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4263 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4265 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4267 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4270 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4272 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4274 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4277 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4279 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4281 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4284 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
4285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4286 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4289 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4292 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4294 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4297 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4299 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4301 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4303 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4305 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4307 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4309 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4311 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4313 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4315 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4317 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4319 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4321 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4323 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4325 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4327 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4329 0x092d0000, 0x0fff0000, "push%c\t%m"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4331 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4333 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4336 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4338 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4340 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4342 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4344 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4346 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4348 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4350 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4352 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4354 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4356 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4358 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4360 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4362 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4364 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4366 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4368 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4370 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4372 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4375 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4377 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
4381 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4383 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
4384 {ARM_FEATURE_CORE_LOW (0),
4385 0x00000000, 0x00000000, 0}
4388 /* print_insn_thumb16 recognizes the following format control codes:
4390 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4391 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4392 %<bitfield>I print bitfield as a signed decimal
4393 (top bit of range being the sign bit)
4394 %N print Thumb register mask (with LR)
4395 %O print Thumb register mask (with PC)
4396 %M print Thumb register mask
4397 %b print CZB's 6-bit unsigned branch destination
4398 %s print Thumb right-shift immediate (6..10; 0 == 32).
4399 %c print the condition code
4400 %C print the condition code, or "s" if not conditional
4401 %x print warning if conditional an not at end of IT block"
4402 %X print "\t; unpredictable <IT:code>" if conditional
4403 %I print IT instruction suffix and operands
4404 %W print Thumb Writeback indicator for LDMIA
4405 %<bitfield>r print bitfield as an ARM register
4406 %<bitfield>d print bitfield as a decimal
4407 %<bitfield>H print (bitfield * 2) as a decimal
4408 %<bitfield>W print (bitfield * 4) as a decimal
4409 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4410 %<bitfield>B print Thumb branch destination (signed displacement)
4411 %<bitfield>c print bitfield as a condition code
4412 %<bitnum>'c print specified char iff bit is one
4413 %<bitnum>?ab print a if bit is one else print b. */
4415 static const struct opcode16 thumb_opcodes
[] =
4417 /* Thumb instructions. */
4419 /* ARMv8-M Security Extensions instructions. */
4420 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
4421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
4423 /* ARM V8 instructions. */
4424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
4425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
4426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
4428 /* ARM V6K no-argument instructions. */
4429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
4430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
4431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
4432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
4433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
4434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4436 /* ARM V6T2 instructions. */
4437 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4438 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4440 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4456 /* ARM V5 ISA extends Thumb. */
4457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
4458 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
4459 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
4460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
4461 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
4462 /* ARM V4T ISA (Thumb v1). */
4463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4464 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4495 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4497 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4499 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4501 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4504 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4506 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4508 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4511 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4513 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4517 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4526 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4529 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4532 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4534 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4536 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4538 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4541 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4543 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4546 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4548 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4551 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4553 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4566 /* The E800 .. FFFF range is unconditionally redirected to the
4567 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4568 are processed via that table. Thus, we can never encounter a
4569 bare "second half of BL/BLX(1)" instruction here. */
4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
4571 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4574 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4575 We adopt the convention that hw1 is the high 16 bits of .value and
4576 .mask, hw2 the low 16 bits.
4578 print_insn_thumb32 recognizes the following format control codes:
4582 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4583 %M print a modified 12-bit immediate (same location)
4584 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4585 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4586 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
4587 %S print a possibly-shifted Rm
4589 %L print address for a ldrd/strd instruction
4590 %a print the address of a plain load/store
4591 %w print the width and signedness of a core load/store
4592 %m print register mask for ldm/stm
4593 %n print register mask for clrm
4595 %E print the lsb and width fields of a bfc/bfi instruction
4596 %F print the lsb and width fields of a sbfx/ubfx instruction
4597 %G print a fallback offset for Branch Future instructions
4598 %W print an offset for BF instruction
4599 %Y print an offset for BFL instruction
4600 %Z print an offset for BFCSEL instruction
4601 %Q print an offset for Low Overhead Loop instructions
4602 %P print an offset for Low Overhead Loop end instructions
4603 %b print a conditional branch offset
4604 %B print an unconditional branch offset
4605 %s print the shift field of an SSAT instruction
4606 %R print the rotation field of an SXT instruction
4607 %U print barrier type.
4608 %P print address for pli instruction.
4609 %c print the condition code
4610 %x print warning if conditional an not at end of IT block"
4611 %X print "\t; unpredictable <IT:code>" if conditional
4613 %<bitfield>d print bitfield in decimal
4614 %<bitfield>D print bitfield plus one in decimal
4615 %<bitfield>W print bitfield*4 in decimal
4616 %<bitfield>r print bitfield as an ARM register
4617 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4618 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4619 %<bitfield>c print bitfield as a condition code
4621 %<bitfield>'c print specified char iff bitfield is all ones
4622 %<bitfield>`c print specified char iff bitfield is all zeroes
4623 %<bitfield>?ab... select from array of values in big endian order
4625 With one exception at the bottom (done because BL and BLX(1) need
4626 to come dead last), this table was machine-sorted first in
4627 decreasing order of number of bits set in the mask, then in
4628 increasing numeric order of mask, then in increasing numeric order
4629 of opcode. This order is not the clearest for a human reader, but
4630 is guaranteed never to catch a special-case bit pattern with a more
4631 general mask, which is important, because this instruction encoding
4632 makes heavy use of special-case bit patterns. */
4633 static const struct opcode32 thumb32_opcodes
[] =
4635 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4637 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4638 0xf00fe001, 0xffffffff, "lctp%c"},
4639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4640 0xf02fc001, 0xfffff001, "le\t%P"},
4641 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4642 0xf00fc001, 0xfffff001, "le\tlr, %P"},
4643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4644 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4645 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4646 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4647 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4648 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4649 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4650 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4652 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4654 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4655 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4656 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4657 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4658 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4659 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4660 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4661 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4663 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4665 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4666 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4668 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4669 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
4670 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4671 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4673 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4674 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4675 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4677 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4679 /* ARM V8.2 RAS extension instructions. */
4680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
4681 0xf3af8010, 0xffffffff, "esb"},
4683 /* V8 instructions. */
4684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4685 0xf3af8005, 0xffffffff, "sevl%c.w"},
4686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4687 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4689 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4691 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4693 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4695 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4697 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4699 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4701 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4703 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4705 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4707 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4709 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4711 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4713 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4715 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4717 /* CRC32 instructions. */
4718 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4719 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4720 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4721 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4723 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4725 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4727 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4728 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4729 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4731 /* Speculation Barriers. */
4732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
4734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
4736 /* V7 instructions. */
4737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4744 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4745 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4746 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4747 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4749 /* Virtualization Extension instructions. */
4750 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4751 /* We skip ERET as that is SUBS pc, lr, #0. */
4753 /* MP Extension instructions. */
4754 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4756 /* Security extension instructions. */
4757 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4759 /* ARMv8.5-A instructions. */
4760 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
4762 /* Instructions defined in the basic V6T2 set. */
4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4769 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4772 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4773 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4775 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4777 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4779 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4781 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4783 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4785 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4787 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4789 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4791 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4793 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4795 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4797 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4799 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4800 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4801 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4802 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4803 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4805 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4807 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4809 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4811 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4813 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4815 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4817 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4819 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4820 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4821 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4823 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4825 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4827 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4829 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4831 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4833 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4835 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4837 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4839 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4841 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4843 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4845 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4847 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4849 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4851 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4853 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4855 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4857 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4859 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4861 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4863 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4865 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4867 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4869 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4871 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4873 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4875 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4877 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4879 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4881 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4883 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4885 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4887 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4889 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4891 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4893 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4895 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4897 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4899 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4901 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4903 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4905 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4907 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4909 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4911 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4913 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4915 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4917 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4919 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4921 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4923 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4925 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4927 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4928 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4929 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4931 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4933 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4935 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4937 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4939 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4941 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4943 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4945 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4947 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4949 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4951 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4953 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4955 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4957 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4959 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4961 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4963 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4965 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4967 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4969 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4971 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4973 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4975 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4977 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4979 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4981 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4983 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4985 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4987 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4989 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4991 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4993 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4995 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4996 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4997 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4999 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5001 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5003 0xf810f000, 0xff70f000, "pld%c\t%a"},
5004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5005 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5007 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5009 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5011 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5013 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5015 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5017 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5019 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5021 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5023 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5025 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5027 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5029 0xfb100000, 0xfff000c0,
5030 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5032 0xfbc00080, 0xfff000c0,
5033 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5035 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5037 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5039 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
5040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5041 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
5042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5043 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
5044 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5045 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5047 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
5048 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5049 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5051 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5053 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5055 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5057 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5059 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5061 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5063 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5065 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5067 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5069 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
5070 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5071 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
5072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5073 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5075 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5077 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5079 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5081 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5083 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5085 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5087 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5089 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5091 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5093 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5095 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5097 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5099 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5101 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5103 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5105 0xe9400000, 0xff500000,
5106 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5108 0xe9500000, 0xff500000,
5109 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5111 0xe8600000, 0xff700000,
5112 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5114 0xe8700000, 0xff700000,
5115 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5117 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5119 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
5121 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
5122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5123 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5125 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5127 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5129 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
5131 /* These have been 32-bit since the invention of Thumb. */
5132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
5133 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
5135 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
5139 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
5140 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5143 static const char *const arm_conditional
[] =
5144 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5145 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5147 static const char *const arm_fp_const
[] =
5148 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5150 static const char *const arm_shift
[] =
5151 {"lsl", "lsr", "asr", "ror"};
5156 const char *description
;
5157 const char *reg_names
[16];
5161 static const arm_regname regnames
[] =
5163 { "reg-names-raw", N_("Select raw register names"),
5164 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5165 { "reg-names-gcc", N_("Select register names used by GCC"),
5166 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
5167 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5168 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
5169 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
5170 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
5171 { "reg-names-apcs", N_("Select register names used in the APCS"),
5172 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
5173 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5174 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
5175 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5176 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
5177 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL
} }
5180 static const char *const iwmmxt_wwnames
[] =
5181 {"b", "h", "w", "d"};
5183 static const char *const iwmmxt_wwssnames
[] =
5184 {"b", "bus", "bc", "bss",
5185 "h", "hus", "hc", "hss",
5186 "w", "wus", "wc", "wss",
5187 "d", "dus", "dc", "dss"
5190 static const char *const iwmmxt_regnames
[] =
5191 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5192 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5195 static const char *const iwmmxt_cregnames
[] =
5196 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5197 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5200 static const char *const vec_condnames
[] =
5201 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5204 static const char *const mve_predicatenames
[] =
5205 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5206 "eee", "ee", "eet", "e", "ett", "et", "ete"
5209 /* Names for 2-bit size field for mve vector isntructions. */
5210 static const char *const mve_vec_sizename
[] =
5211 { "8", "16", "32", "64"};
5213 /* Indicates whether we are processing a then predicate,
5214 else predicate or none at all. */
5222 /* Information used to process a vpt block and subsequent instructions. */
5225 /* Are we in a vpt block. */
5226 bfd_boolean in_vpt_block
;
5228 /* Next predicate state if in vpt block. */
5229 enum vpt_pred_state next_pred_state
;
5231 /* Mask from vpt/vpst instruction. */
5232 long predicate_mask
;
5234 /* Instruction number in vpt block. */
5235 long current_insn_num
;
5237 /* Number of instructions in vpt block.. */
5241 static struct vpt_block vpt_block_state
=
5250 /* Default to GCC register name set. */
5251 static unsigned int regname_selected
= 1;
5253 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
5254 #define arm_regnames regnames[regname_selected].reg_names
5256 static bfd_boolean force_thumb
= FALSE
;
5257 static uint16_t cde_coprocs
= 0;
5259 /* Current IT instruction state. This contains the same state as the IT
5260 bits in the CPSR. */
5261 static unsigned int ifthen_state
;
5262 /* IT state for the next instruction. */
5263 static unsigned int ifthen_next_state
;
5264 /* The address of the insn for which the IT state is valid. */
5265 static bfd_vma ifthen_address
;
5266 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5267 /* Indicates that the current Conditional state is unconditional or outside
5269 #define COND_UNCOND 16
5273 /* Extract the predicate mask for a VPT or VPST instruction.
5274 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5277 mve_extract_pred_mask (long given
)
5279 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
5282 /* Return the number of instructions in a MVE predicate block. */
5284 num_instructions_vpt_block (long given
)
5286 long mask
= mve_extract_pred_mask (given
);
5293 if ((mask
& 7) == 4)
5296 if ((mask
& 3) == 2)
5299 if ((mask
& 1) == 1)
5306 mark_outside_vpt_block (void)
5308 vpt_block_state
.in_vpt_block
= FALSE
;
5309 vpt_block_state
.next_pred_state
= PRED_NONE
;
5310 vpt_block_state
.predicate_mask
= 0;
5311 vpt_block_state
.current_insn_num
= 0;
5312 vpt_block_state
.num_pred_insn
= 0;
5316 mark_inside_vpt_block (long given
)
5318 vpt_block_state
.in_vpt_block
= TRUE
;
5319 vpt_block_state
.next_pred_state
= PRED_THEN
;
5320 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
5321 vpt_block_state
.current_insn_num
= 0;
5322 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
5323 assert (vpt_block_state
.num_pred_insn
>= 1);
5326 static enum vpt_pred_state
5327 invert_next_predicate_state (enum vpt_pred_state astate
)
5329 if (astate
== PRED_THEN
)
5331 else if (astate
== PRED_ELSE
)
5337 static enum vpt_pred_state
5338 update_next_predicate_state (void)
5340 long pred_mask
= vpt_block_state
.predicate_mask
;
5341 long mask_for_insn
= 0;
5343 switch (vpt_block_state
.current_insn_num
)
5361 if (pred_mask
& mask_for_insn
)
5362 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
5364 return vpt_block_state
.next_pred_state
;
5368 update_vpt_block_state (void)
5370 vpt_block_state
.current_insn_num
++;
5371 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
5373 /* No more instructions to process in vpt block. */
5374 mark_outside_vpt_block ();
5378 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
5381 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5382 Returns pointer to following character of the format string and
5383 fills in *VALUEP and *WIDTHP with the extracted value and number of
5384 bits extracted. WIDTHP can be NULL. */
5387 arm_decode_bitfield (const char *ptr
,
5389 unsigned long *valuep
,
5392 unsigned long value
= 0;
5400 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
5401 start
= start
* 10 + *ptr
- '0';
5403 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
5404 end
= end
* 10 + *ptr
- '0';
5410 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
5413 while (*ptr
++ == ',');
5421 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
5422 bfd_boolean print_shift
)
5424 func (stream
, "%s", arm_regnames
[given
& 0xf]);
5426 if ((given
& 0xff0) != 0)
5428 if ((given
& 0x10) == 0)
5430 int amount
= (given
& 0xf80) >> 7;
5431 int shift
= (given
& 0x60) >> 5;
5437 func (stream
, ", rrx");
5445 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
5447 func (stream
, ", #%d", amount
);
5449 else if ((given
& 0x80) == 0x80)
5450 func (stream
, "\t; <illegal shifter operand>");
5451 else if (print_shift
)
5452 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
5453 arm_regnames
[(given
& 0xf00) >> 8]);
5455 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
5459 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5462 is_mve_okay_in_it (enum mve_instructions matched_insn
)
5464 switch (matched_insn
)
5466 case MVE_VMOV_GP_TO_VEC_LANE
:
5467 case MVE_VMOV2_VEC_LANE_TO_GP
:
5468 case MVE_VMOV2_GP_TO_VEC_LANE
:
5469 case MVE_VMOV_VEC_LANE_TO_GP
:
5494 is_mve_architecture (struct disassemble_info
*info
)
5496 struct arm_private_data
*private_data
= info
->private_data
;
5497 arm_feature_set allowed_arches
= private_data
->features
;
5499 arm_feature_set arm_ext_v8_1m_main
5500 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
5502 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
5503 && !ARM_CPU_IS_ANY (allowed_arches
))
5510 is_vpt_instruction (long given
)
5513 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5514 if ((given
& 0x0040e000) == 0)
5517 /* VPT floating point T1 variant. */
5518 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
5519 /* VPT floating point T2 variant. */
5520 || ((given
& 0xefb10f50) == 0xee310f40)
5521 /* VPT vector T1 variant. */
5522 || ((given
& 0xff811f51) == 0xfe010f00)
5523 /* VPT vector T2 variant. */
5524 || ((given
& 0xff811f51) == 0xfe010f01
5525 && ((given
& 0x300000) != 0x300000))
5526 /* VPT vector T3 variant. */
5527 || ((given
& 0xff811f50) == 0xfe011f00)
5528 /* VPT vector T4 variant. */
5529 || ((given
& 0xff811f70) == 0xfe010f40)
5530 /* VPT vector T5 variant. */
5531 || ((given
& 0xff811f70) == 0xfe010f60)
5532 /* VPT vector T6 variant. */
5533 || ((given
& 0xff811f50) == 0xfe011f40)
5534 /* VPST vector T variant. */
5535 || ((given
& 0xffbf1fff) == 0xfe310f4d))
5541 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5542 and ending bitfield = END. END must be greater than START. */
5544 static unsigned long
5545 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
5547 int bits
= end
- start
;
5552 return ((given
>> start
) & ((2ul << bits
) - 1));
5555 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5556 START:END and START2:END2. END/END2 must be greater than
5559 static unsigned long
5560 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
5561 unsigned int end
, unsigned int start2
,
5564 int bits
= end
- start
;
5565 int bits2
= end2
- start2
;
5566 unsigned long value
= 0;
5572 value
= arm_decode_field (given
, start
, end
);
5575 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
5579 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5580 This helps us decode instructions that change mnemonic depending on specific
5581 operand values/encodings. */
5584 is_mve_encoding_conflict (unsigned long given
,
5585 enum mve_instructions matched_insn
)
5587 switch (matched_insn
)
5590 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5596 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5598 if ((arm_decode_field (given
, 12, 12) == 0)
5599 && (arm_decode_field (given
, 0, 0) == 1))
5604 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5606 if (arm_decode_field (given
, 0, 3) == 0xd)
5610 case MVE_VPT_VEC_T1
:
5611 case MVE_VPT_VEC_T2
:
5612 case MVE_VPT_VEC_T3
:
5613 case MVE_VPT_VEC_T4
:
5614 case MVE_VPT_VEC_T5
:
5615 case MVE_VPT_VEC_T6
:
5616 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5618 if (arm_decode_field (given
, 20, 21) == 3)
5622 case MVE_VCMP_FP_T1
:
5623 if ((arm_decode_field (given
, 12, 12) == 0)
5624 && (arm_decode_field (given
, 0, 0) == 1))
5629 case MVE_VCMP_FP_T2
:
5630 if (arm_decode_field (given
, 0, 3) == 0xd)
5637 case MVE_VMUL_VEC_T2
:
5644 case MVE_VADD_VEC_T2
:
5645 case MVE_VSUB_VEC_T2
:
5662 case MVE_VQDMULH_T3
:
5663 case MVE_VQRDMULH_T4
:
5669 case MVE_VCMP_VEC_T1
:
5670 case MVE_VCMP_VEC_T2
:
5671 case MVE_VCMP_VEC_T3
:
5672 case MVE_VCMP_VEC_T4
:
5673 case MVE_VCMP_VEC_T5
:
5674 case MVE_VCMP_VEC_T6
:
5675 if (arm_decode_field (given
, 20, 21) == 3)
5684 if (arm_decode_field (given
, 7, 8) == 3)
5691 if ((arm_decode_field (given
, 24, 24) == 0)
5692 && (arm_decode_field (given
, 21, 21) == 0))
5696 else if ((arm_decode_field (given
, 7, 8) == 3))
5704 if ((arm_decode_field (given
, 24, 24) == 0)
5705 && (arm_decode_field (given
, 21, 21) == 0))
5712 case MVE_VCVT_FP_FIX_VEC
:
5713 return (arm_decode_field (given
, 16, 21) & 0x38) == 0;
5718 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5720 if ((cmode
& 1) == 0)
5722 else if ((cmode
& 0xc) == 0xc)
5730 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5734 else if ((cmode
& 0x9) == 1)
5736 else if ((cmode
& 0xd) == 9)
5742 case MVE_VMOV_IMM_TO_VEC
:
5743 if ((arm_decode_field (given
, 5, 5) == 1)
5744 && (arm_decode_field (given
, 8, 11) != 0xe))
5751 unsigned long size
= arm_decode_field (given
, 19, 20);
5752 if ((size
== 0) || (size
== 3))
5773 if (arm_decode_field (given
, 18, 19) == 3)
5779 case MVE_VRMLSLDAVH
:
5782 if (arm_decode_field (given
, 20, 22) == 7)
5787 case MVE_VRMLALDAVH
:
5788 if ((arm_decode_field (given
, 20, 22) & 6) == 6)
5795 if ((arm_decode_field (given
, 20, 21) == 3)
5796 || (arm_decode_field (given
, 1, 3) == 7))
5803 if (arm_decode_field (given
, 16, 18) == 0)
5805 unsigned long sz
= arm_decode_field (given
, 19, 20);
5807 if ((sz
== 1) || (sz
== 2))
5822 if (arm_decode_field (given
, 19, 21) == 0)
5828 if (arm_decode_field (given
, 16, 19) == 0xf)
5844 if (arm_decode_field (given
, 9, 11) == 0x7)
5852 unsigned long rm
, rn
;
5853 rm
= arm_decode_field (given
, 0, 3);
5854 rn
= arm_decode_field (given
, 16, 19);
5856 if (rm
== 0xf && rn
== 0xf)
5859 else if (rn
== rm
&& rn
!= 0xf)
5865 if (arm_decode_field (given
, 0, 3) == 0xd)
5868 else if (matched_insn
== MVE_CSNEG
)
5869 if (arm_decode_field (given
, 0, 3) == arm_decode_field (given
, 16, 19))
5874 case MVE_VADD_FP_T1
:
5875 case MVE_VADD_FP_T2
:
5876 case MVE_VADD_VEC_T1
:
5883 print_mve_vld_str_addr (struct disassemble_info
*info
,
5884 unsigned long given
,
5885 enum mve_instructions matched_insn
)
5887 void *stream
= info
->stream
;
5888 fprintf_ftype func
= info
->fprintf_func
;
5890 unsigned long p
, w
, gpr
, imm
, add
, mod_imm
;
5892 imm
= arm_decode_field (given
, 0, 6);
5895 switch (matched_insn
)
5899 gpr
= arm_decode_field (given
, 16, 18);
5904 gpr
= arm_decode_field (given
, 16, 18);
5910 gpr
= arm_decode_field (given
, 16, 19);
5916 gpr
= arm_decode_field (given
, 16, 19);
5922 gpr
= arm_decode_field (given
, 16, 19);
5929 p
= arm_decode_field (given
, 24, 24);
5930 w
= arm_decode_field (given
, 21, 21);
5932 add
= arm_decode_field (given
, 23, 23);
5936 /* Don't print anything for '+' as it is implied. */
5946 func (stream
, "[%s, #%s%lu]", arm_regnames
[gpr
], add_sub
, mod_imm
);
5947 /* Pre-indexed mode. */
5949 func (stream
, "[%s, #%s%lu]!", arm_regnames
[gpr
], add_sub
, mod_imm
);
5951 else if ((p
== 0) && (w
== 1))
5952 /* Post-index mode. */
5953 func (stream
, "[%s], #%s%lu", arm_regnames
[gpr
], add_sub
, mod_imm
);
5956 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5957 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5958 this encoding is undefined. */
5961 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
5962 enum mve_undefined
*undefined_code
)
5964 *undefined_code
= UNDEF_NONE
;
5966 switch (matched_insn
)
5969 if (arm_decode_field_multiple (given
, 5, 5, 22, 22) == 3)
5971 *undefined_code
= UNDEF_SIZE_3
;
5979 case MVE_VMUL_VEC_T1
:
5981 case MVE_VADD_VEC_T1
:
5982 case MVE_VSUB_VEC_T1
:
5983 case MVE_VQDMULH_T1
:
5984 case MVE_VQRDMULH_T2
:
5988 if (arm_decode_field (given
, 20, 21) == 3)
5990 *undefined_code
= UNDEF_SIZE_3
;
5997 if (arm_decode_field (given
, 7, 8) == 3)
5999 *undefined_code
= UNDEF_SIZE_3
;
6006 if (arm_decode_field (given
, 7, 8) <= 1)
6008 *undefined_code
= UNDEF_SIZE_LE_1
;
6015 if ((arm_decode_field (given
, 7, 8) == 0))
6017 *undefined_code
= UNDEF_SIZE_0
;
6024 if ((arm_decode_field (given
, 7, 8) <= 1))
6026 *undefined_code
= UNDEF_SIZE_LE_1
;
6032 case MVE_VLDRB_GATHER_T1
:
6033 if (arm_decode_field (given
, 7, 8) == 3)
6035 *undefined_code
= UNDEF_SIZE_3
;
6038 else if ((arm_decode_field (given
, 28, 28) == 0)
6039 && (arm_decode_field (given
, 7, 8) == 0))
6041 *undefined_code
= UNDEF_NOT_UNS_SIZE_0
;
6047 case MVE_VLDRH_GATHER_T2
:
6048 if (arm_decode_field (given
, 7, 8) == 3)
6050 *undefined_code
= UNDEF_SIZE_3
;
6053 else if ((arm_decode_field (given
, 28, 28) == 0)
6054 && (arm_decode_field (given
, 7, 8) == 1))
6056 *undefined_code
= UNDEF_NOT_UNS_SIZE_1
;
6059 else if (arm_decode_field (given
, 7, 8) == 0)
6061 *undefined_code
= UNDEF_SIZE_0
;
6067 case MVE_VLDRW_GATHER_T3
:
6068 if (arm_decode_field (given
, 7, 8) != 2)
6070 *undefined_code
= UNDEF_SIZE_NOT_2
;
6073 else if (arm_decode_field (given
, 28, 28) == 0)
6075 *undefined_code
= UNDEF_NOT_UNSIGNED
;
6081 case MVE_VLDRD_GATHER_T4
:
6082 if (arm_decode_field (given
, 7, 8) != 3)
6084 *undefined_code
= UNDEF_SIZE_NOT_3
;
6087 else if (arm_decode_field (given
, 28, 28) == 0)
6089 *undefined_code
= UNDEF_NOT_UNSIGNED
;
6095 case MVE_VSTRB_SCATTER_T1
:
6096 if (arm_decode_field (given
, 7, 8) == 3)
6098 *undefined_code
= UNDEF_SIZE_3
;
6104 case MVE_VSTRH_SCATTER_T2
:
6106 unsigned long size
= arm_decode_field (given
, 7, 8);
6109 *undefined_code
= UNDEF_SIZE_3
;
6114 *undefined_code
= UNDEF_SIZE_0
;
6121 case MVE_VSTRW_SCATTER_T3
:
6122 if (arm_decode_field (given
, 7, 8) != 2)
6124 *undefined_code
= UNDEF_SIZE_NOT_2
;
6130 case MVE_VSTRD_SCATTER_T4
:
6131 if (arm_decode_field (given
, 7, 8) != 3)
6133 *undefined_code
= UNDEF_SIZE_NOT_3
;
6139 case MVE_VCVT_FP_FIX_VEC
:
6141 unsigned long imm6
= arm_decode_field (given
, 16, 21);
6142 if ((imm6
& 0x20) == 0)
6144 *undefined_code
= UNDEF_VCVT_IMM6
;
6148 if ((arm_decode_field (given
, 9, 9) == 0)
6149 && ((imm6
& 0x30) == 0x20))
6151 *undefined_code
= UNDEF_VCVT_FSI_IMM6
;
6160 case MVE_VCVT_BETWEEN_FP_INT
:
6161 case MVE_VCVT_FROM_FP_TO_INT
:
6163 unsigned long size
= arm_decode_field (given
, 18, 19);
6166 *undefined_code
= UNDEF_SIZE_0
;
6171 *undefined_code
= UNDEF_SIZE_3
;
6178 case MVE_VMOV_VEC_LANE_TO_GP
:
6180 unsigned long op1
= arm_decode_field (given
, 21, 22);
6181 unsigned long op2
= arm_decode_field (given
, 5, 6);
6182 unsigned long u
= arm_decode_field (given
, 23, 23);
6184 if ((op2
== 0) && (u
== 1))
6186 if ((op1
== 0) || (op1
== 1))
6188 *undefined_code
= UNDEF_BAD_U_OP1_OP2
;
6196 if ((op1
== 0) || (op1
== 1))
6198 *undefined_code
= UNDEF_BAD_OP1_OP2
;
6208 case MVE_VMOV_GP_TO_VEC_LANE
:
6209 if (arm_decode_field (given
, 5, 6) == 2)
6211 unsigned long op1
= arm_decode_field (given
, 21, 22);
6212 if ((op1
== 0) || (op1
== 1))
6214 *undefined_code
= UNDEF_BAD_OP1_OP2
;
6223 case MVE_VMOV_VEC_TO_VEC
:
6224 if ((arm_decode_field (given
, 5, 5) == 1)
6225 || (arm_decode_field (given
, 22, 22) == 1))
6229 case MVE_VMOV_IMM_TO_VEC
:
6230 if (arm_decode_field (given
, 5, 5) == 0)
6232 unsigned long cmode
= arm_decode_field (given
, 8, 11);
6234 if (((cmode
& 9) == 1) || ((cmode
& 5) == 1))
6236 *undefined_code
= UNDEF_OP_0_BAD_CMODE
;
6247 if (arm_decode_field (given
, 18, 19) == 2)
6249 *undefined_code
= UNDEF_SIZE_2
;
6255 case MVE_VRMLALDAVH
:
6256 case MVE_VMLADAV_T1
:
6257 case MVE_VMLADAV_T2
:
6259 if ((arm_decode_field (given
, 28, 28) == 1)
6260 && (arm_decode_field (given
, 12, 12) == 1))
6262 *undefined_code
= UNDEF_XCHG_UNS
;
6273 unsigned long sz
= arm_decode_field (given
, 19, 20);
6276 else if ((sz
& 2) == 2)
6280 *undefined_code
= UNDEF_SIZE
;
6294 unsigned long sz
= arm_decode_field (given
, 19, 21);
6297 else if ((sz
& 6) == 2)
6299 else if ((sz
& 4) == 4)
6303 *undefined_code
= UNDEF_SIZE
;
6310 if (arm_decode_field (given
, 19, 20) == 0)
6312 *undefined_code
= UNDEF_SIZE_0
;
6319 if (arm_decode_field (given
, 18, 19) == 3)
6321 *undefined_code
= UNDEF_SIZE_3
;
6332 if (arm_decode_field (given
, 18, 19) == 3)
6334 *undefined_code
= UNDEF_SIZE_3
;
6341 if (arm_decode_field (given
, 18, 19) == 0)
6345 *undefined_code
= UNDEF_SIZE_NOT_0
;
6351 unsigned long size
= arm_decode_field (given
, 18, 19);
6352 if ((size
& 2) == 2)
6354 *undefined_code
= UNDEF_SIZE_2
;
6362 if (arm_decode_field (given
, 18, 19) != 3)
6366 *undefined_code
= UNDEF_SIZE_3
;
6375 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6376 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6377 why this encoding is unpredictable. */
6380 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
6381 enum mve_unpredictable
*unpredictable_code
)
6383 *unpredictable_code
= UNPRED_NONE
;
6385 switch (matched_insn
)
6387 case MVE_VCMP_FP_T2
:
6389 if ((arm_decode_field (given
, 12, 12) == 0)
6390 && (arm_decode_field (given
, 5, 5) == 1))
6392 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
6398 case MVE_VPT_VEC_T4
:
6399 case MVE_VPT_VEC_T5
:
6400 case MVE_VPT_VEC_T6
:
6401 case MVE_VCMP_VEC_T4
:
6402 case MVE_VCMP_VEC_T5
:
6403 case MVE_VCMP_VEC_T6
:
6404 if (arm_decode_field (given
, 0, 3) == 0xd)
6406 *unpredictable_code
= UNPRED_R13
;
6414 unsigned long gpr
= arm_decode_field (given
, 12, 15);
6417 *unpredictable_code
= UNPRED_R13
;
6420 else if (gpr
== 0xf)
6422 *unpredictable_code
= UNPRED_R15
;
6431 case MVE_VMUL_FP_T2
:
6432 case MVE_VMUL_VEC_T2
:
6435 case MVE_VADD_FP_T2
:
6436 case MVE_VSUB_FP_T2
:
6437 case MVE_VADD_VEC_T2
:
6438 case MVE_VSUB_VEC_T2
:
6448 case MVE_VQDMULH_T3
:
6449 case MVE_VQRDMULH_T4
:
6451 case MVE_VFMA_FP_SCALAR
:
6452 case MVE_VFMAS_FP_SCALAR
:
6456 unsigned long gpr
= arm_decode_field (given
, 0, 3);
6459 *unpredictable_code
= UNPRED_R13
;
6462 else if (gpr
== 0xf)
6464 *unpredictable_code
= UNPRED_R15
;
6474 unsigned long rn
= arm_decode_field (given
, 16, 19);
6476 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6478 *unpredictable_code
= UNPRED_R13_AND_WB
;
6484 *unpredictable_code
= UNPRED_R15
;
6488 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 6)
6490 *unpredictable_code
= UNPRED_Q_GT_6
;
6500 unsigned long rn
= arm_decode_field (given
, 16, 19);
6502 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6504 *unpredictable_code
= UNPRED_R13_AND_WB
;
6510 *unpredictable_code
= UNPRED_R15
;
6514 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 4)
6516 *unpredictable_code
= UNPRED_Q_GT_4
;
6530 unsigned long rn
= arm_decode_field (given
, 16, 19);
6532 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6534 *unpredictable_code
= UNPRED_R13_AND_WB
;
6539 *unpredictable_code
= UNPRED_R15
;
6546 case MVE_VLDRB_GATHER_T1
:
6547 if (arm_decode_field (given
, 0, 0) == 1)
6549 *unpredictable_code
= UNPRED_OS
;
6554 /* To handle common code with T2-T4 variants. */
6555 case MVE_VLDRH_GATHER_T2
:
6556 case MVE_VLDRW_GATHER_T3
:
6557 case MVE_VLDRD_GATHER_T4
:
6559 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6560 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6564 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6568 if (arm_decode_field (given
, 16, 19) == 0xf)
6570 *unpredictable_code
= UNPRED_R15
;
6577 case MVE_VLDRW_GATHER_T5
:
6578 case MVE_VLDRD_GATHER_T6
:
6580 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6581 unsigned long qm
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6585 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6592 case MVE_VSTRB_SCATTER_T1
:
6593 if (arm_decode_field (given
, 16, 19) == 0xf)
6595 *unpredictable_code
= UNPRED_R15
;
6598 else if (arm_decode_field (given
, 0, 0) == 1)
6600 *unpredictable_code
= UNPRED_OS
;
6606 case MVE_VSTRH_SCATTER_T2
:
6607 case MVE_VSTRW_SCATTER_T3
:
6608 case MVE_VSTRD_SCATTER_T4
:
6609 if (arm_decode_field (given
, 16, 19) == 0xf)
6611 *unpredictable_code
= UNPRED_R15
;
6617 case MVE_VMOV2_VEC_LANE_TO_GP
:
6618 case MVE_VMOV2_GP_TO_VEC_LANE
:
6619 case MVE_VCVT_BETWEEN_FP_INT
:
6620 case MVE_VCVT_FROM_FP_TO_INT
:
6622 unsigned long rt
= arm_decode_field (given
, 0, 3);
6623 unsigned long rt2
= arm_decode_field (given
, 16, 19);
6625 if ((rt
== 0xd) || (rt2
== 0xd))
6627 *unpredictable_code
= UNPRED_R13
;
6630 else if ((rt
== 0xf) || (rt2
== 0xf))
6632 *unpredictable_code
= UNPRED_R15
;
6637 *unpredictable_code
= UNPRED_GP_REGS_EQUAL
;
6646 case MVE_VMAXNMV_FP
:
6647 case MVE_VMAXNMAV_FP
:
6648 case MVE_VMINNMV_FP
:
6649 case MVE_VMINNMAV_FP
:
6653 case MVE_VMOV_HFP_TO_GP
:
6654 case MVE_VMOV_GP_TO_VEC_LANE
:
6655 case MVE_VMOV_VEC_LANE_TO_GP
:
6657 unsigned long rda
= arm_decode_field (given
, 12, 15);
6660 *unpredictable_code
= UNPRED_R13
;
6663 else if (rda
== 0xf)
6665 *unpredictable_code
= UNPRED_R15
;
6678 if (arm_decode_field (given
, 20, 21) == 2)
6680 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6681 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6682 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6684 if ((Qd
== Qn
) || (Qd
== Qm
))
6686 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6697 case MVE_VQDMULL_T1
:
6703 if (arm_decode_field (given
, 28, 28) == 1)
6705 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6706 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6707 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6709 if ((Qd
== Qn
) || (Qd
== Qm
))
6711 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6721 case MVE_VQDMULL_T2
:
6723 unsigned long gpr
= arm_decode_field (given
, 0, 3);
6726 *unpredictable_code
= UNPRED_R13
;
6729 else if (gpr
== 0xf)
6731 *unpredictable_code
= UNPRED_R15
;
6735 if (arm_decode_field (given
, 28, 28) == 1)
6738 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
6739 unsigned long Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6743 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6754 case MVE_VRMLSLDAVH
:
6757 if (arm_decode_field (given
, 20, 22) == 6)
6759 *unpredictable_code
= UNPRED_R13
;
6767 if (arm_decode_field (given
, 1, 3) == 6)
6769 *unpredictable_code
= UNPRED_R13
;
6778 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6779 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6780 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 21) == 2)
6782 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6791 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6792 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6793 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 20) == 1)
6795 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6808 if (arm_decode_field (given
, 20, 20) == 1)
6810 Qda
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6811 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6812 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6814 if ((Qda
== Qn
) || (Qda
== Qm
))
6816 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6828 if (arm_decode_field (given
, 16, 19) == 0xd)
6830 *unpredictable_code
= UNPRED_R13
;
6838 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6839 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 6, 6);
6843 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6862 unsigned long gpr
= arm_decode_field (given
, 9, 11);
6863 gpr
= ((gpr
<< 1) | 1);
6866 *unpredictable_code
= UNPRED_R13
;
6869 else if (gpr
== 0xf)
6871 *unpredictable_code
= UNPRED_R15
;
6884 print_mve_vmov_index (struct disassemble_info
*info
, unsigned long given
)
6886 unsigned long op1
= arm_decode_field (given
, 21, 22);
6887 unsigned long op2
= arm_decode_field (given
, 5, 6);
6888 unsigned long h
= arm_decode_field (given
, 16, 16);
6889 unsigned long index_operand
, esize
, targetBeat
, idx
;
6890 void *stream
= info
->stream
;
6891 fprintf_ftype func
= info
->fprintf_func
;
6893 if ((op1
& 0x2) == 0x2)
6895 index_operand
= op2
;
6898 else if (((op1
& 0x2) == 0x0) && ((op2
& 0x1) == 0x1))
6900 index_operand
= op2
>> 1;
6903 else if (((op1
& 0x2) == 0) && ((op2
& 0x3) == 0))
6910 func (stream
, "<undefined index>");
6914 targetBeat
= (op1
& 0x1) | (h
<< 1);
6915 idx
= index_operand
+ targetBeat
* (32/esize
);
6917 func (stream
, "%lu", idx
);
6920 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6921 in length and integer of floating-point type. */
6923 print_simd_imm8 (struct disassemble_info
*info
, unsigned long given
,
6924 unsigned int ibit_loc
, const struct mopcode32
*insn
)
6927 int cmode
= (given
>> 8) & 0xf;
6928 int op
= (given
>> 5) & 0x1;
6929 unsigned long value
= 0, hival
= 0;
6933 void *stream
= info
->stream
;
6934 fprintf_ftype func
= info
->fprintf_func
;
6936 /* On Neon the 'i' bit is at bit 24, on mve it is
6938 bits
|= ((given
>> ibit_loc
) & 1) << 7;
6939 bits
|= ((given
>> 16) & 7) << 4;
6940 bits
|= ((given
>> 0) & 15) << 0;
6944 shift
= (cmode
>> 1) & 3;
6945 value
= (unsigned long) bits
<< (8 * shift
);
6948 else if (cmode
< 12)
6950 shift
= (cmode
>> 1) & 1;
6951 value
= (unsigned long) bits
<< (8 * shift
);
6954 else if (cmode
< 14)
6956 shift
= (cmode
& 1) + 1;
6957 value
= (unsigned long) bits
<< (8 * shift
);
6958 value
|= (1ul << (8 * shift
)) - 1;
6961 else if (cmode
== 14)
6965 /* Bit replication into bytes. */
6971 for (ix
= 7; ix
>= 0; ix
--)
6973 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
6975 value
= (value
<< 8) | mask
;
6977 hival
= (hival
<< 8) | mask
;
6983 /* Byte replication. */
6984 value
= (unsigned long) bits
;
6990 /* Floating point encoding. */
6993 value
= (unsigned long) (bits
& 0x7f) << 19;
6994 value
|= (unsigned long) (bits
& 0x80) << 24;
6995 tmp
= bits
& 0x40 ? 0x3c : 0x40;
6996 value
|= (unsigned long) tmp
<< 24;
7002 func (stream
, "<illegal constant %.8x:%x:%x>",
7008 // printU determines whether the immediate value should be printed as
7010 unsigned printU
= 0;
7011 switch (insn
->mve_op
)
7015 // We want this for instructions that don't have a 'signed' type
7019 case MVE_VMOV_IMM_TO_VEC
:
7026 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
7033 : "#%ld\t; 0x%.4lx", value
, value
);
7039 unsigned char valbytes
[4];
7042 /* Do this a byte at a time so we don't have to
7043 worry about the host's endianness. */
7044 valbytes
[0] = value
& 0xff;
7045 valbytes
[1] = (value
>> 8) & 0xff;
7046 valbytes
[2] = (value
>> 16) & 0xff;
7047 valbytes
[3] = (value
>> 24) & 0xff;
7049 floatformat_to_double
7050 (& floatformat_ieee_single_little
, valbytes
,
7053 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
7060 : "#%ld\t; 0x%.8lx",
7061 (long) (((value
& 0x80000000L
) != 0)
7063 ? value
| ~0xffffffffL
: value
),
7068 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
7078 print_mve_undefined (struct disassemble_info
*info
,
7079 enum mve_undefined undefined_code
)
7081 void *stream
= info
->stream
;
7082 fprintf_ftype func
= info
->fprintf_func
;
7084 func (stream
, "\t\tundefined instruction: ");
7086 switch (undefined_code
)
7089 func (stream
, "illegal size");
7093 func (stream
, "size equals zero");
7097 func (stream
, "size equals two");
7101 func (stream
, "size equals three");
7104 case UNDEF_SIZE_LE_1
:
7105 func (stream
, "size <= 1");
7108 case UNDEF_SIZE_NOT_0
:
7109 func (stream
, "size not equal to 0");
7112 case UNDEF_SIZE_NOT_2
:
7113 func (stream
, "size not equal to 2");
7116 case UNDEF_SIZE_NOT_3
:
7117 func (stream
, "size not equal to 3");
7120 case UNDEF_NOT_UNS_SIZE_0
:
7121 func (stream
, "not unsigned and size = zero");
7124 case UNDEF_NOT_UNS_SIZE_1
:
7125 func (stream
, "not unsigned and size = one");
7128 case UNDEF_NOT_UNSIGNED
:
7129 func (stream
, "not unsigned");
7132 case UNDEF_VCVT_IMM6
:
7133 func (stream
, "invalid imm6");
7136 case UNDEF_VCVT_FSI_IMM6
:
7137 func (stream
, "fsi = 0 and invalid imm6");
7140 case UNDEF_BAD_OP1_OP2
:
7141 func (stream
, "bad size with op2 = 2 and op1 = 0 or 1");
7144 case UNDEF_BAD_U_OP1_OP2
:
7145 func (stream
, "unsigned with op2 = 0 and op1 = 0 or 1");
7148 case UNDEF_OP_0_BAD_CMODE
:
7149 func (stream
, "op field equal 0 and bad cmode");
7152 case UNDEF_XCHG_UNS
:
7153 func (stream
, "exchange and unsigned together");
7163 print_mve_unpredictable (struct disassemble_info
*info
,
7164 enum mve_unpredictable unpredict_code
)
7166 void *stream
= info
->stream
;
7167 fprintf_ftype func
= info
->fprintf_func
;
7169 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
7171 switch (unpredict_code
)
7173 case UNPRED_IT_BLOCK
:
7174 func (stream
, "mve instruction in it block");
7177 case UNPRED_FCA_0_FCB_1
:
7178 func (stream
, "condition bits, fca = 0 and fcb = 1");
7182 func (stream
, "use of r13 (sp)");
7186 func (stream
, "use of r15 (pc)");
7190 func (stream
, "start register block > r4");
7194 func (stream
, "start register block > r6");
7197 case UNPRED_R13_AND_WB
:
7198 func (stream
, "use of r13 and write back");
7201 case UNPRED_Q_REGS_EQUAL
:
7203 "same vector register used for destination and other operand");
7207 func (stream
, "use of offset scaled");
7210 case UNPRED_GP_REGS_EQUAL
:
7211 func (stream
, "same general-purpose register used for both operands");
7214 case UNPRED_Q_REGS_EQ_AND_SIZE_1
:
7215 func (stream
, "use of identical q registers and size = 1");
7218 case UNPRED_Q_REGS_EQ_AND_SIZE_2
:
7219 func (stream
, "use of identical q registers and size = 1");
7227 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
7230 print_mve_register_blocks (struct disassemble_info
*info
,
7231 unsigned long given
,
7232 enum mve_instructions matched_insn
)
7234 void *stream
= info
->stream
;
7235 fprintf_ftype func
= info
->fprintf_func
;
7237 unsigned long q_reg_start
= arm_decode_field_multiple (given
,
7240 switch (matched_insn
)
7244 if (q_reg_start
<= 6)
7245 func (stream
, "{q%ld, q%ld}", q_reg_start
, q_reg_start
+ 1);
7247 func (stream
, "<illegal reg q%ld>", q_reg_start
);
7252 if (q_reg_start
<= 4)
7253 func (stream
, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start
,
7254 q_reg_start
+ 1, q_reg_start
+ 2,
7257 func (stream
, "<illegal reg q%ld>", q_reg_start
);
7266 print_mve_rounding_mode (struct disassemble_info
*info
,
7267 unsigned long given
,
7268 enum mve_instructions matched_insn
)
7270 void *stream
= info
->stream
;
7271 fprintf_ftype func
= info
->fprintf_func
;
7273 switch (matched_insn
)
7275 case MVE_VCVT_FROM_FP_TO_INT
:
7277 switch (arm_decode_field (given
, 8, 9))
7303 switch (arm_decode_field (given
, 7, 9))
7342 print_mve_vcvt_size (struct disassemble_info
*info
,
7343 unsigned long given
,
7344 enum mve_instructions matched_insn
)
7346 unsigned long mode
= 0;
7347 void *stream
= info
->stream
;
7348 fprintf_ftype func
= info
->fprintf_func
;
7350 switch (matched_insn
)
7352 case MVE_VCVT_FP_FIX_VEC
:
7354 mode
= (((given
& 0x200) >> 7)
7355 | ((given
& 0x10000000) >> 27)
7356 | ((given
& 0x100) >> 8));
7361 func (stream
, "f16.s16");
7365 func (stream
, "s16.f16");
7369 func (stream
, "f16.u16");
7373 func (stream
, "u16.f16");
7377 func (stream
, "f32.s32");
7381 func (stream
, "s32.f32");
7385 func (stream
, "f32.u32");
7389 func (stream
, "u32.f32");
7397 case MVE_VCVT_BETWEEN_FP_INT
:
7399 unsigned long size
= arm_decode_field (given
, 18, 19);
7400 unsigned long op
= arm_decode_field (given
, 7, 8);
7407 func (stream
, "f16.s16");
7411 func (stream
, "f16.u16");
7415 func (stream
, "s16.f16");
7419 func (stream
, "u16.f16");
7431 func (stream
, "f32.s32");
7435 func (stream
, "f32.u32");
7439 func (stream
, "s32.f32");
7443 func (stream
, "u32.f32");
7450 case MVE_VCVT_FP_HALF_FP
:
7452 unsigned long op
= arm_decode_field (given
, 28, 28);
7454 func (stream
, "f16.f32");
7456 func (stream
, "f32.f16");
7460 case MVE_VCVT_FROM_FP_TO_INT
:
7462 unsigned long size
= arm_decode_field_multiple (given
, 7, 7, 18, 19);
7467 func (stream
, "s16.f16");
7471 func (stream
, "u16.f16");
7475 func (stream
, "s32.f32");
7479 func (stream
, "u32.f32");
7494 print_mve_rotate (struct disassemble_info
*info
, unsigned long rot
,
7495 unsigned long rot_width
)
7497 void *stream
= info
->stream
;
7498 fprintf_ftype func
= info
->fprintf_func
;
7505 func (stream
, "90");
7508 func (stream
, "270");
7514 else if (rot_width
== 2)
7522 func (stream
, "90");
7525 func (stream
, "180");
7528 func (stream
, "270");
7537 print_instruction_predicate (struct disassemble_info
*info
)
7539 void *stream
= info
->stream
;
7540 fprintf_ftype func
= info
->fprintf_func
;
7542 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
7544 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
7549 print_mve_size (struct disassemble_info
*info
,
7551 enum mve_instructions matched_insn
)
7553 void *stream
= info
->stream
;
7554 fprintf_ftype func
= info
->fprintf_func
;
7556 switch (matched_insn
)
7562 case MVE_VADD_VEC_T1
:
7563 case MVE_VADD_VEC_T2
:
7569 case MVE_VCMP_VEC_T1
:
7570 case MVE_VCMP_VEC_T2
:
7571 case MVE_VCMP_VEC_T3
:
7572 case MVE_VCMP_VEC_T4
:
7573 case MVE_VCMP_VEC_T5
:
7574 case MVE_VCMP_VEC_T6
:
7587 case MVE_VLDRB_GATHER_T1
:
7588 case MVE_VLDRH_GATHER_T2
:
7589 case MVE_VLDRW_GATHER_T3
:
7590 case MVE_VLDRD_GATHER_T4
:
7603 case MVE_VMUL_VEC_T1
:
7604 case MVE_VMUL_VEC_T2
:
7610 case MVE_VPT_VEC_T1
:
7611 case MVE_VPT_VEC_T2
:
7612 case MVE_VPT_VEC_T3
:
7613 case MVE_VPT_VEC_T4
:
7614 case MVE_VPT_VEC_T5
:
7615 case MVE_VPT_VEC_T6
:
7627 case MVE_VQDMULH_T1
:
7628 case MVE_VQRDMULH_T2
:
7629 case MVE_VQDMULH_T3
:
7630 case MVE_VQRDMULH_T4
:
7649 case MVE_VSTRB_SCATTER_T1
:
7650 case MVE_VSTRH_SCATTER_T2
:
7651 case MVE_VSTRW_SCATTER_T3
:
7654 case MVE_VSUB_VEC_T1
:
7655 case MVE_VSUB_VEC_T2
:
7657 func (stream
, "%s", mve_vec_sizename
[size
]);
7659 func (stream
, "<undef size>");
7663 case MVE_VADD_FP_T1
:
7664 case MVE_VADD_FP_T2
:
7665 case MVE_VSUB_FP_T1
:
7666 case MVE_VSUB_FP_T2
:
7667 case MVE_VCMP_FP_T1
:
7668 case MVE_VCMP_FP_T2
:
7669 case MVE_VFMA_FP_SCALAR
:
7672 case MVE_VFMAS_FP_SCALAR
:
7674 case MVE_VMAXNMA_FP
:
7675 case MVE_VMAXNMV_FP
:
7676 case MVE_VMAXNMAV_FP
:
7678 case MVE_VMINNMA_FP
:
7679 case MVE_VMINNMV_FP
:
7680 case MVE_VMINNMAV_FP
:
7681 case MVE_VMUL_FP_T1
:
7682 case MVE_VMUL_FP_T2
:
7686 func (stream
, "32");
7688 func (stream
, "16");
7694 case MVE_VMLADAV_T1
:
7696 case MVE_VMLSDAV_T1
:
7699 case MVE_VQDMULL_T1
:
7700 case MVE_VQDMULL_T2
:
7704 func (stream
, "16");
7706 func (stream
, "32");
7713 func (stream
, "16");
7720 func (stream
, "32");
7723 func (stream
, "16");
7733 case MVE_VMOV_GP_TO_VEC_LANE
:
7734 case MVE_VMOV_VEC_LANE_TO_GP
:
7738 func (stream
, "32");
7743 func (stream
, "16");
7746 case 8: case 9: case 10: case 11:
7747 case 12: case 13: case 14: case 15:
7756 case MVE_VMOV_IMM_TO_VEC
:
7759 case 0: case 4: case 8:
7760 case 12: case 24: case 26:
7761 func (stream
, "i32");
7764 func (stream
, "i16");
7767 func (stream
, "i8");
7770 func (stream
, "i64");
7773 func (stream
, "f32");
7780 case MVE_VMULL_POLY
:
7782 func (stream
, "p8");
7784 func (stream
, "p16");
7790 case 0: case 2: case 4:
7791 case 6: case 12: case 13:
7792 func (stream
, "32");
7796 func (stream
, "16");
7810 func (stream
, "32");
7814 func (stream
, "16");
7832 func (stream
, "16");
7836 func (stream
, "32");
7861 func (stream
, "16");
7864 case 4: case 5: case 6: case 7:
7865 func (stream
, "32");
7880 print_mve_shift_n (struct disassemble_info
*info
, long given
,
7881 enum mve_instructions matched_insn
)
7883 void *stream
= info
->stream
;
7884 fprintf_ftype func
= info
->fprintf_func
;
7887 = matched_insn
== MVE_VQSHL_T2
7888 || matched_insn
== MVE_VQSHLU_T3
7889 || matched_insn
== MVE_VSHL_T1
7890 || matched_insn
== MVE_VSHLL_T1
7891 || matched_insn
== MVE_VSLI
;
7893 unsigned imm6
= (given
& 0x3f0000) >> 16;
7895 if (matched_insn
== MVE_VSHLL_T1
)
7898 unsigned shiftAmount
= 0;
7899 if ((imm6
& 0x20) != 0)
7900 shiftAmount
= startAt0
? imm6
- 32 : 64 - imm6
;
7901 else if ((imm6
& 0x10) != 0)
7902 shiftAmount
= startAt0
? imm6
- 16 : 32 - imm6
;
7903 else if ((imm6
& 0x08) != 0)
7904 shiftAmount
= startAt0
? imm6
- 8 : 16 - imm6
;
7906 print_mve_undefined (info
, UNDEF_SIZE_0
);
7908 func (stream
, "%u", shiftAmount
);
7912 print_vec_condition (struct disassemble_info
*info
, long given
,
7913 enum mve_instructions matched_insn
)
7915 void *stream
= info
->stream
;
7916 fprintf_ftype func
= info
->fprintf_func
;
7919 switch (matched_insn
)
7922 case MVE_VCMP_FP_T1
:
7923 vec_cond
= (((given
& 0x1000) >> 10)
7924 | ((given
& 1) << 1)
7925 | ((given
& 0x0080) >> 7));
7926 func (stream
, "%s",vec_condnames
[vec_cond
]);
7930 case MVE_VCMP_FP_T2
:
7931 vec_cond
= (((given
& 0x1000) >> 10)
7932 | ((given
& 0x0020) >> 4)
7933 | ((given
& 0x0080) >> 7));
7934 func (stream
, "%s",vec_condnames
[vec_cond
]);
7937 case MVE_VPT_VEC_T1
:
7938 case MVE_VCMP_VEC_T1
:
7939 vec_cond
= (given
& 0x0080) >> 7;
7940 func (stream
, "%s",vec_condnames
[vec_cond
]);
7943 case MVE_VPT_VEC_T2
:
7944 case MVE_VCMP_VEC_T2
:
7945 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7946 func (stream
, "%s",vec_condnames
[vec_cond
]);
7949 case MVE_VPT_VEC_T3
:
7950 case MVE_VCMP_VEC_T3
:
7951 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
7952 func (stream
, "%s",vec_condnames
[vec_cond
]);
7955 case MVE_VPT_VEC_T4
:
7956 case MVE_VCMP_VEC_T4
:
7957 vec_cond
= (given
& 0x0080) >> 7;
7958 func (stream
, "%s",vec_condnames
[vec_cond
]);
7961 case MVE_VPT_VEC_T5
:
7962 case MVE_VCMP_VEC_T5
:
7963 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7964 func (stream
, "%s",vec_condnames
[vec_cond
]);
7967 case MVE_VPT_VEC_T6
:
7968 case MVE_VCMP_VEC_T6
:
7969 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
7970 func (stream
, "%s",vec_condnames
[vec_cond
]);
7985 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7986 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7987 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7988 #define PRE_BIT_SET (given & (1 << P_BIT))
7991 /* Print one coprocessor instruction on INFO->STREAM.
7992 Return TRUE if the instuction matched, FALSE if this is not a
7993 recognised coprocessor instruction. */
7996 print_insn_coprocessor_1 (const struct sopcode32
*opcodes
,
7998 struct disassemble_info
*info
,
8002 const struct sopcode32
*insn
;
8003 void *stream
= info
->stream
;
8004 fprintf_ftype func
= info
->fprintf_func
;
8006 unsigned long value
= 0;
8009 struct arm_private_data
*private_data
= info
->private_data
;
8010 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
8011 arm_feature_set arm_ext_v8_1m_main
=
8012 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
8014 allowed_arches
= private_data
->features
;
8016 for (insn
= opcodes
; insn
->assembler
; insn
++)
8018 unsigned long u_reg
= 16;
8019 bfd_boolean is_unpredictable
= FALSE
;
8020 signed long value_in_comment
= 0;
8023 if (ARM_FEATURE_ZERO (insn
->arch
))
8024 switch (insn
->value
)
8026 case SENTINEL_IWMMXT_START
:
8027 if (info
->mach
!= bfd_mach_arm_XScale
8028 && info
->mach
!= bfd_mach_arm_iWMMXt
8029 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
8032 while ((! ARM_FEATURE_ZERO (insn
->arch
))
8033 && insn
->value
!= SENTINEL_IWMMXT_END
);
8036 case SENTINEL_IWMMXT_END
:
8039 case SENTINEL_GENERIC_START
:
8040 allowed_arches
= private_data
->features
;
8048 value
= insn
->value
;
8049 cp_num
= (given
>> 8) & 0xf;
8053 /* The high 4 bits are 0xe for Arm conditional instructions, and
8054 0xe for arm unconditional instructions. The rest of the
8055 encoding is the same. */
8057 value
|= 0xe0000000;
8065 /* Only match unconditional instuctions against unconditional
8067 if ((given
& 0xf0000000) == 0xf0000000)
8074 cond
= (given
>> 28) & 0xf;
8080 if ((insn
->isa
== T32
&& !thumb
)
8081 || (insn
->isa
== ARM
&& thumb
))
8084 if ((given
& mask
) != value
)
8087 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
8090 if (insn
->value
== 0xfe000010 /* mcr2 */
8091 || insn
->value
== 0xfe100010 /* mrc2 */
8092 || insn
->value
== 0xfc100000 /* ldc2 */
8093 || insn
->value
== 0xfc000000) /* stc2 */
8095 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
8096 is_unpredictable
= TRUE
;
8098 /* Armv8.1-M Mainline FP & MVE instructions. */
8099 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
8100 && !ARM_CPU_IS_ANY (allowed_arches
)
8101 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
8105 else if (insn
->value
== 0x0e000000 /* cdp */
8106 || insn
->value
== 0xfe000000 /* cdp2 */
8107 || insn
->value
== 0x0e000010 /* mcr */
8108 || insn
->value
== 0x0e100010 /* mrc */
8109 || insn
->value
== 0x0c100000 /* ldc */
8110 || insn
->value
== 0x0c000000) /* stc */
8112 /* Floating-point instructions. */
8113 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
8116 /* Armv8.1-M Mainline FP & MVE instructions. */
8117 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
8118 && !ARM_CPU_IS_ANY (allowed_arches
)
8119 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
8122 else if ((insn
->value
== 0xec100f80 /* vldr (system register) */
8123 || insn
->value
== 0xec000f80) /* vstr (system register) */
8124 && arm_decode_field (given
, 24, 24) == 0
8125 && arm_decode_field (given
, 21, 21) == 0)
8126 /* If the P and W bits are both 0 then these encodings match the MVE
8127 VLDR and VSTR instructions, these are in a different table, so we
8128 don't let it match here. */
8131 for (c
= insn
->assembler
; *c
; c
++)
8135 const char mod
= *++c
;
8139 func (stream
, "%%");
8145 int rn
= (given
>> 16) & 0xf;
8146 bfd_vma offset
= given
& 0xff;
8149 offset
= given
& 0x7f;
8151 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8153 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
8155 /* Not unindexed. The offset is scaled. */
8157 /* vldr.16/vstr.16 will shift the address
8158 left by 1 bit only. */
8159 offset
= offset
* 2;
8161 offset
= offset
* 4;
8163 if (NEGATIVE_BIT_SET
)
8166 value_in_comment
= offset
;
8172 func (stream
, ", #%d]%s",
8174 WRITEBACK_BIT_SET
? "!" : "");
8175 else if (NEGATIVE_BIT_SET
)
8176 func (stream
, ", #-0]");
8184 if (WRITEBACK_BIT_SET
)
8187 func (stream
, ", #%d", (int) offset
);
8188 else if (NEGATIVE_BIT_SET
)
8189 func (stream
, ", #-0");
8193 func (stream
, ", {%s%d}",
8194 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
8196 value_in_comment
= offset
;
8199 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
8201 func (stream
, "\t; ");
8202 /* For unaligned PCs, apply off-by-alignment
8204 info
->print_address_func (offset
+ pc
8205 + info
->bytes_per_chunk
* 2
8214 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
8215 int offset
= (given
>> 1) & 0x3f;
8218 func (stream
, "{d%d}", regno
);
8219 else if (regno
+ offset
> 32)
8220 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
8222 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
8228 bfd_boolean single
= ((given
>> 8) & 1) == 0;
8229 char reg_prefix
= single
? 's' : 'd';
8230 int Dreg
= (given
>> 22) & 0x1;
8231 int Vdreg
= (given
>> 12) & 0xf;
8232 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
8233 : ((Dreg
<< 4) | Vdreg
);
8234 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
8235 int maxreg
= single
? 31 : 15;
8236 int topreg
= reg
+ num
- 1;
8239 func (stream
, "{VPR}");
8241 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
8242 else if (topreg
> maxreg
)
8243 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
8244 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
8246 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
8247 reg_prefix
, topreg
);
8252 if (cond
!= COND_UNCOND
)
8253 is_unpredictable
= TRUE
;
8257 if (cond
!= COND_UNCOND
&& cp_num
== 9)
8258 is_unpredictable
= TRUE
;
8262 func (stream
, "%s", arm_conditional
[cond
]);
8266 /* Print a Cirrus/DSP shift immediate. */
8267 /* Immediates are 7bit signed ints with bits 0..3 in
8268 bits 0..3 of opcode and bits 4..6 in bits 5..7
8273 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
8275 /* Is ``imm'' a negative number? */
8279 func (stream
, "%d", imm
);
8287 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
8292 func (stream
, "FPSCR");
8295 func (stream
, "FPSCR_nzcvqc");
8298 func (stream
, "VPR");
8301 func (stream
, "P0");
8304 func (stream
, "FPCXTNS");
8307 func (stream
, "FPCXTS");
8310 func (stream
, "<invalid reg %lu>", regno
);
8317 switch (given
& 0x00408000)
8334 switch (given
& 0x00080080)
8346 func (stream
, _("<illegal precision>"));
8352 switch (given
& 0x00408000)
8370 switch (given
& 0x60)
8386 case '0': case '1': case '2': case '3': case '4':
8387 case '5': case '6': case '7': case '8': case '9':
8391 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8397 is_unpredictable
= TRUE
;
8402 /* Eat the 'u' character. */
8406 is_unpredictable
= TRUE
;
8409 func (stream
, "%s", arm_regnames
[value
]);
8412 if (given
& (1 << 6))
8416 func (stream
, "d%ld", value
);
8421 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
8423 func (stream
, "q%ld", value
>> 1);
8426 func (stream
, "%ld", value
);
8427 value_in_comment
= value
;
8431 /* Converts immediate 8 bit back to float value. */
8432 unsigned floatVal
= (value
& 0x80) << 24
8433 | (value
& 0x3F) << 19
8434 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
8436 /* Quarter float have a maximum value of 31.0.
8437 Get floating point value multiplied by 1e7.
8438 The maximum value stays in limit of a 32-bit int. */
8440 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
8441 (16 + (value
& 0xF));
8443 if (!(decVal
% 1000000))
8444 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
8445 floatVal
, value
& 0x80 ? '-' : ' ',
8447 decVal
% 10000000 / 1000000);
8448 else if (!(decVal
% 10000))
8449 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
8450 floatVal
, value
& 0x80 ? '-' : ' ',
8452 decVal
% 10000000 / 10000);
8454 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
8455 floatVal
, value
& 0x80 ? '-' : ' ',
8456 decVal
/ 10000000, decVal
% 10000000);
8461 int from
= (given
& (1 << 7)) ? 32 : 16;
8462 func (stream
, "%ld", from
- value
);
8468 func (stream
, "#%s", arm_fp_const
[value
& 7]);
8470 func (stream
, "f%ld", value
);
8475 func (stream
, "%s", iwmmxt_wwnames
[value
]);
8477 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
8481 func (stream
, "%s", iwmmxt_regnames
[value
]);
8484 func (stream
, "%s", iwmmxt_cregnames
[value
]);
8488 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
8495 func (stream
, "eq");
8499 func (stream
, "vs");
8503 func (stream
, "ge");
8507 func (stream
, "gt");
8511 func (stream
, "??");
8519 func (stream
, "%c", *c
);
8523 if (value
== ((1ul << width
) - 1))
8524 func (stream
, "%c", *c
);
8527 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
8539 int single
= *c
++ == 'y';
8544 case '4': /* Sm pair */
8545 case '0': /* Sm, Dm */
8546 regno
= given
& 0x0000000f;
8550 regno
+= (given
>> 5) & 1;
8553 regno
+= ((given
>> 5) & 1) << 4;
8556 case '1': /* Sd, Dd */
8557 regno
= (given
>> 12) & 0x0000000f;
8561 regno
+= (given
>> 22) & 1;
8564 regno
+= ((given
>> 22) & 1) << 4;
8567 case '2': /* Sn, Dn */
8568 regno
= (given
>> 16) & 0x0000000f;
8572 regno
+= (given
>> 7) & 1;
8575 regno
+= ((given
>> 7) & 1) << 4;
8578 case '3': /* List */
8580 regno
= (given
>> 12) & 0x0000000f;
8584 regno
+= (given
>> 22) & 1;
8587 regno
+= ((given
>> 22) & 1) << 4;
8594 func (stream
, "%c%d", single
? 's' : 'd', regno
);
8598 int count
= given
& 0xff;
8605 func (stream
, "-%c%d",
8613 func (stream
, ", %c%d", single
? 's' : 'd',
8619 switch (given
& 0x00400100)
8621 case 0x00000000: func (stream
, "b"); break;
8622 case 0x00400000: func (stream
, "h"); break;
8623 case 0x00000100: func (stream
, "w"); break;
8624 case 0x00400100: func (stream
, "d"); break;
8632 /* given (20, 23) | given (0, 3) */
8633 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
8634 func (stream
, "%d", (int) value
);
8639 /* This is like the 'A' operator, except that if
8640 the width field "M" is zero, then the offset is
8641 *not* multiplied by four. */
8643 int offset
= given
& 0xff;
8644 int multiplier
= (given
& 0x00000100) ? 4 : 1;
8646 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8650 value_in_comment
= offset
* multiplier
;
8651 if (NEGATIVE_BIT_SET
)
8652 value_in_comment
= - value_in_comment
;
8658 func (stream
, ", #%s%d]%s",
8659 NEGATIVE_BIT_SET
? "-" : "",
8660 offset
* multiplier
,
8661 WRITEBACK_BIT_SET
? "!" : "");
8663 func (stream
, "], #%s%d",
8664 NEGATIVE_BIT_SET
? "-" : "",
8665 offset
* multiplier
);
8674 int imm4
= (given
>> 4) & 0xf;
8675 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
8676 int ubit
= ! NEGATIVE_BIT_SET
;
8677 const char *rm
= arm_regnames
[given
& 0xf];
8678 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
8684 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
8686 func (stream
, ", lsl #%d", imm4
);
8693 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
8695 func (stream
, ", lsl #%d", imm4
);
8697 if (puw_bits
== 5 || puw_bits
== 7)
8702 func (stream
, "INVALID");
8710 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
8711 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
8720 func (stream
, "%c", *c
);
8723 if (value_in_comment
> 32 || value_in_comment
< -16)
8724 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
8726 if (is_unpredictable
)
8727 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8735 print_insn_coprocessor (bfd_vma pc
,
8736 struct disassemble_info
*info
,
8740 return print_insn_coprocessor_1 (coprocessor_opcodes
,
8741 pc
, info
, given
, thumb
);
8745 print_insn_generic_coprocessor (bfd_vma pc
,
8746 struct disassemble_info
*info
,
8750 return print_insn_coprocessor_1 (generic_coprocessor_opcodes
,
8751 pc
, info
, given
, thumb
);
8754 /* Decodes and prints ARM addressing modes. Returns the offset
8755 used in the address, if any, if it is worthwhile printing the
8756 offset as a hexadecimal value in a comment at the end of the
8757 line of disassembly. */
8760 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8762 void *stream
= info
->stream
;
8763 fprintf_ftype func
= info
->fprintf_func
;
8766 if (((given
& 0x000f0000) == 0x000f0000)
8767 && ((given
& 0x02000000) == 0))
8769 offset
= given
& 0xfff;
8771 func (stream
, "[pc");
8775 /* Pre-indexed. Elide offset of positive zero when
8777 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
8778 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8780 if (NEGATIVE_BIT_SET
)
8785 /* Cope with the possibility of write-back
8786 being used. Probably a very dangerous thing
8787 for the programmer to do, but who are we to
8789 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
8791 else /* Post indexed. */
8793 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8795 /* Ie ignore the offset. */
8799 func (stream
, "\t; ");
8800 info
->print_address_func (offset
, info
);
8805 func (stream
, "[%s",
8806 arm_regnames
[(given
>> 16) & 0xf]);
8810 if ((given
& 0x02000000) == 0)
8812 /* Elide offset of positive zero when non-writeback. */
8813 offset
= given
& 0xfff;
8814 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
8815 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8819 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
8820 arm_decode_shift (given
, func
, stream
, TRUE
);
8823 func (stream
, "]%s",
8824 WRITEBACK_BIT_SET
? "!" : "");
8828 if ((given
& 0x02000000) == 0)
8830 /* Always show offset. */
8831 offset
= given
& 0xfff;
8832 func (stream
, "], #%s%d",
8833 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8837 func (stream
, "], %s",
8838 NEGATIVE_BIT_SET
? "-" : "");
8839 arm_decode_shift (given
, func
, stream
, TRUE
);
8842 if (NEGATIVE_BIT_SET
)
8846 return (signed long) offset
;
8850 /* Print one cde instruction on INFO->STREAM.
8851 Return TRUE if the instuction matched, FALSE if this is not a
8852 recognised cde instruction. */
8854 print_insn_cde (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
8856 const struct cdeopcode32
*insn
;
8857 void *stream
= info
->stream
;
8858 fprintf_ftype func
= info
->fprintf_func
;
8862 /* Manually extract the coprocessor code from a known point.
8863 This position is the same across all CDE instructions. */
8864 for (insn
= cde_opcodes
; insn
->assembler
; insn
++)
8866 uint16_t coproc
= (given
>> insn
->coproc_shift
) & insn
->coproc_mask
;
8867 uint16_t coproc_mask
= 1 << coproc
;
8868 if (! (coproc_mask
& cde_coprocs
))
8871 if ((given
& insn
->mask
) == insn
->value
)
8873 bfd_boolean is_unpredictable
= FALSE
;
8876 for (c
= insn
->assembler
; *c
; c
++)
8883 func (stream
, "%%");
8886 case '0': case '1': case '2': case '3': case '4':
8887 case '5': case '6': case '7': case '8': case '9':
8890 unsigned long value
;
8892 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8898 is_unpredictable
= TRUE
;
8902 is_unpredictable
= TRUE
;
8905 func (stream
, "%s", arm_regnames
[value
]);
8910 func (stream
, "%s", "APSR_nzcv");
8912 func (stream
, "%s", arm_regnames
[value
]);
8916 func (stream
, "%s", arm_regnames
[value
+ 1]);
8920 func (stream
, "%ld", value
);
8931 uint8_t proc_number
= (given
>> 8) & 0x7;
8932 func (stream
, "p%u", proc_number
);
8938 uint8_t a_offset
= 28;
8939 if (given
& (1 << a_offset
))
8948 func (stream
, "%c", *c
);
8951 if (is_unpredictable
)
8952 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8964 /* Print one neon instruction on INFO->STREAM.
8965 Return TRUE if the instuction matched, FALSE if this is not a
8966 recognised neon instruction. */
8969 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
8971 const struct opcode32
*insn
;
8972 void *stream
= info
->stream
;
8973 fprintf_ftype func
= info
->fprintf_func
;
8977 if ((given
& 0xef000000) == 0xef000000)
8979 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
8980 unsigned long bit28
= given
& (1 << 28);
8982 given
&= 0x00ffffff;
8984 given
|= 0xf3000000;
8986 given
|= 0xf2000000;
8988 else if ((given
& 0xff000000) == 0xf9000000)
8989 given
^= 0xf9000000 ^ 0xf4000000;
8990 /* BFloat16 neon instructions without special top byte handling. */
8991 else if ((given
& 0xff000000) == 0xfe000000
8992 || (given
& 0xff000000) == 0xfc000000)
8994 /* vdup is also a valid neon instruction. */
8995 else if ((given
& 0xff910f5f) != 0xee800b10)
8999 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
9001 if ((given
& insn
->mask
) == insn
->value
)
9003 signed long value_in_comment
= 0;
9004 bfd_boolean is_unpredictable
= FALSE
;
9007 for (c
= insn
->assembler
; *c
; c
++)
9014 func (stream
, "%%");
9018 if (thumb
&& ifthen_state
)
9019 is_unpredictable
= TRUE
;
9023 if (thumb
&& ifthen_state
)
9024 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9029 static const unsigned char enc
[16] =
9031 0x4, 0x14, /* st4 0,1 */
9043 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
9044 int rn
= ((given
>> 16) & 0xf);
9045 int rm
= ((given
>> 0) & 0xf);
9046 int align
= ((given
>> 4) & 0x3);
9047 int type
= ((given
>> 8) & 0xf);
9048 int n
= enc
[type
] & 0xf;
9049 int stride
= (enc
[type
] >> 4) + 1;
9054 for (ix
= 0; ix
!= n
; ix
++)
9055 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
9057 func (stream
, "d%d", rd
);
9059 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
9060 func (stream
, "}, [%s", arm_regnames
[rn
]);
9062 func (stream
, " :%d", 32 << align
);
9067 func (stream
, ", %s", arm_regnames
[rm
]);
9073 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
9074 int rn
= ((given
>> 16) & 0xf);
9075 int rm
= ((given
>> 0) & 0xf);
9076 int idx_align
= ((given
>> 4) & 0xf);
9078 int size
= ((given
>> 10) & 0x3);
9079 int idx
= idx_align
>> (size
+ 1);
9080 int length
= ((given
>> 8) & 3) + 1;
9084 if (length
> 1 && size
> 0)
9085 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
9091 int amask
= (1 << size
) - 1;
9092 if ((idx_align
& (1 << size
)) != 0)
9096 if ((idx_align
& amask
) == amask
)
9098 else if ((idx_align
& amask
) != 0)
9105 if (size
== 2 && (idx_align
& 2) != 0)
9107 align
= (idx_align
& 1) ? 16 << size
: 0;
9111 if ((size
== 2 && (idx_align
& 3) != 0)
9112 || (idx_align
& 1) != 0)
9119 if ((idx_align
& 3) == 3)
9121 align
= (idx_align
& 3) * 64;
9124 align
= (idx_align
& 1) ? 32 << size
: 0;
9132 for (i
= 0; i
< length
; i
++)
9133 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
9134 rd
+ i
* stride
, idx
);
9135 func (stream
, "}, [%s", arm_regnames
[rn
]);
9137 func (stream
, " :%d", align
);
9142 func (stream
, ", %s", arm_regnames
[rm
]);
9148 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
9149 int rn
= ((given
>> 16) & 0xf);
9150 int rm
= ((given
>> 0) & 0xf);
9151 int align
= ((given
>> 4) & 0x1);
9152 int size
= ((given
>> 6) & 0x3);
9153 int type
= ((given
>> 8) & 0x3);
9155 int stride
= ((given
>> 5) & 0x1);
9158 if (stride
&& (n
== 1))
9165 for (ix
= 0; ix
!= n
; ix
++)
9166 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
9168 func (stream
, "d%d[]", rd
);
9170 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
9171 func (stream
, "}, [%s", arm_regnames
[rn
]);
9174 align
= (8 * (type
+ 1)) << size
;
9176 align
= (size
> 1) ? align
>> 1 : align
;
9177 if (type
== 2 || (type
== 0 && !size
))
9178 func (stream
, " :<bad align %d>", align
);
9180 func (stream
, " :%d", align
);
9186 func (stream
, ", %s", arm_regnames
[rm
]);
9192 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
9193 int size
= (given
>> 20) & 3;
9194 int reg
= raw_reg
& ((4 << size
) - 1);
9195 int ix
= raw_reg
>> size
>> 2;
9197 func (stream
, "d%d[%d]", reg
, ix
);
9202 /* Neon encoded constant for mov, mvn, vorr, vbic. */
9205 int cmode
= (given
>> 8) & 0xf;
9206 int op
= (given
>> 5) & 0x1;
9207 unsigned long value
= 0, hival
= 0;
9212 bits
|= ((given
>> 24) & 1) << 7;
9213 bits
|= ((given
>> 16) & 7) << 4;
9214 bits
|= ((given
>> 0) & 15) << 0;
9218 shift
= (cmode
>> 1) & 3;
9219 value
= (unsigned long) bits
<< (8 * shift
);
9222 else if (cmode
< 12)
9224 shift
= (cmode
>> 1) & 1;
9225 value
= (unsigned long) bits
<< (8 * shift
);
9228 else if (cmode
< 14)
9230 shift
= (cmode
& 1) + 1;
9231 value
= (unsigned long) bits
<< (8 * shift
);
9232 value
|= (1ul << (8 * shift
)) - 1;
9235 else if (cmode
== 14)
9239 /* Bit replication into bytes. */
9245 for (ix
= 7; ix
>= 0; ix
--)
9247 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
9249 value
= (value
<< 8) | mask
;
9251 hival
= (hival
<< 8) | mask
;
9257 /* Byte replication. */
9258 value
= (unsigned long) bits
;
9264 /* Floating point encoding. */
9267 value
= (unsigned long) (bits
& 0x7f) << 19;
9268 value
|= (unsigned long) (bits
& 0x80) << 24;
9269 tmp
= bits
& 0x40 ? 0x3c : 0x40;
9270 value
|= (unsigned long) tmp
<< 24;
9276 func (stream
, "<illegal constant %.8x:%x:%x>",
9284 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
9288 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
9294 unsigned char valbytes
[4];
9297 /* Do this a byte at a time so we don't have to
9298 worry about the host's endianness. */
9299 valbytes
[0] = value
& 0xff;
9300 valbytes
[1] = (value
>> 8) & 0xff;
9301 valbytes
[2] = (value
>> 16) & 0xff;
9302 valbytes
[3] = (value
>> 24) & 0xff;
9304 floatformat_to_double
9305 (& floatformat_ieee_single_little
, valbytes
,
9308 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
9312 func (stream
, "#%ld\t; 0x%.8lx",
9313 (long) (((value
& 0x80000000L
) != 0)
9314 ? value
| ~0xffffffffL
: value
),
9319 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
9330 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
9331 int num
= (given
>> 8) & 0x3;
9334 func (stream
, "{d%d}", regno
);
9335 else if (num
+ regno
>= 32)
9336 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
9338 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
9343 case '0': case '1': case '2': case '3': case '4':
9344 case '5': case '6': case '7': case '8': case '9':
9347 unsigned long value
;
9349 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9354 func (stream
, "%s", arm_regnames
[value
]);
9357 func (stream
, "%ld", value
);
9358 value_in_comment
= value
;
9361 func (stream
, "%ld", (1ul << width
) - value
);
9367 /* Various width encodings. */
9369 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
9374 if (*c
>= '0' && *c
<= '9')
9376 else if (*c
>= 'a' && *c
<= 'f')
9377 limit
= *c
- 'a' + 10;
9383 if (value
< low
|| value
> high
)
9384 func (stream
, "<illegal width %d>", base
<< value
);
9386 func (stream
, "%d", base
<< value
);
9390 if (given
& (1 << 6))
9394 func (stream
, "d%ld", value
);
9399 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
9401 func (stream
, "q%ld", value
>> 1);
9407 func (stream
, "%c", *c
);
9411 if (value
== ((1ul << width
) - 1))
9412 func (stream
, "%c", *c
);
9415 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
9429 func (stream
, "%c", *c
);
9432 if (value_in_comment
> 32 || value_in_comment
< -16)
9433 func (stream
, "\t; 0x%lx", value_in_comment
);
9435 if (is_unpredictable
)
9436 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9444 /* Print one mve instruction on INFO->STREAM.
9445 Return TRUE if the instuction matched, FALSE if this is not a
9446 recognised mve instruction. */
9449 print_insn_mve (struct disassemble_info
*info
, long given
)
9451 const struct mopcode32
*insn
;
9452 void *stream
= info
->stream
;
9453 fprintf_ftype func
= info
->fprintf_func
;
9455 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
9457 if (((given
& insn
->mask
) == insn
->value
)
9458 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
9460 signed long value_in_comment
= 0;
9461 bfd_boolean is_unpredictable
= FALSE
;
9462 bfd_boolean is_undefined
= FALSE
;
9464 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
9465 enum mve_undefined undefined_cond
= UNDEF_NONE
;
9467 /* Most vector mve instruction are illegal in a it block.
9468 There are a few exceptions; check for them. */
9469 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
9471 is_unpredictable
= TRUE
;
9472 unpredictable_cond
= UNPRED_IT_BLOCK
;
9474 else if (is_mve_unpredictable (given
, insn
->mve_op
,
9475 &unpredictable_cond
))
9476 is_unpredictable
= TRUE
;
9478 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
9479 is_undefined
= TRUE
;
9481 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9482 i.e "VMOV Qd, Qm". */
9483 if ((insn
->mve_op
== MVE_VORR_REG
)
9484 && (arm_decode_field (given
, 1, 3)
9485 == arm_decode_field (given
, 17, 19)))
9488 for (c
= insn
->assembler
; *c
; c
++)
9495 func (stream
, "%%");
9499 /* Don't print anything for '+' as it is implied. */
9500 if (arm_decode_field (given
, 23, 23) == 0)
9506 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9510 print_mve_vld_str_addr (info
, given
, insn
->mve_op
);
9515 long mve_mask
= mve_extract_pred_mask (given
);
9516 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
9522 unsigned int imm5
= 0;
9523 imm5
|= arm_decode_field (given
, 6, 7);
9524 imm5
|= (arm_decode_field (given
, 12, 14) << 2);
9525 func (stream
, "#%u", (imm5
== 0) ? 32 : imm5
);
9530 func (stream
, "#%u",
9531 (arm_decode_field (given
, 7, 7) == 0) ? 64 : 48);
9535 print_vec_condition (info
, given
, insn
->mve_op
);
9539 if (arm_decode_field (given
, 0, 0) == 1)
9542 = arm_decode_field (given
, 4, 4)
9543 | (arm_decode_field (given
, 6, 6) << 1);
9545 func (stream
, ", uxtw #%lu", size
);
9550 print_mve_rounding_mode (info
, given
, insn
->mve_op
);
9554 print_mve_vcvt_size (info
, given
, insn
->mve_op
);
9559 unsigned long op1
= arm_decode_field (given
, 21, 22);
9561 if ((insn
->mve_op
== MVE_VMOV_VEC_LANE_TO_GP
))
9563 /* Check for signed. */
9564 if (arm_decode_field (given
, 23, 23) == 0)
9566 /* We don't print 's' for S32. */
9567 if ((arm_decode_field (given
, 5, 6) == 0)
9568 && ((op1
== 0) || (op1
== 1)))
9578 if (arm_decode_field (given
, 28, 28) == 0)
9587 print_instruction_predicate (info
);
9591 if (arm_decode_field (given
, 21, 21) == 1)
9596 print_mve_register_blocks (info
, given
, insn
->mve_op
);
9600 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9602 print_simd_imm8 (info
, given
, 28, insn
);
9606 print_mve_vmov_index (info
, given
);
9610 if (arm_decode_field (given
, 12, 12) == 0)
9617 if (arm_decode_field (given
, 12, 12) == 1)
9621 case '0': case '1': case '2': case '3': case '4':
9622 case '5': case '6': case '7': case '8': case '9':
9625 unsigned long value
;
9627 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9633 is_unpredictable
= TRUE
;
9634 else if (value
== 15)
9635 func (stream
, "zr");
9637 func (stream
, "%s", arm_regnames
[value
]);
9641 func (stream
, "%s", arm_conditional
[value
]);
9646 func (stream
, "%s", arm_conditional
[value
]);
9650 if (value
== 13 || value
== 15)
9651 is_unpredictable
= TRUE
;
9653 func (stream
, "%s", arm_regnames
[value
]);
9657 print_mve_size (info
,
9671 unsigned int odd_reg
= (value
<< 1) | 1;
9672 func (stream
, "%s", arm_regnames
[odd_reg
]);
9678 = arm_decode_field (given
, 0, 6);
9679 unsigned long mod_imm
= imm
;
9681 switch (insn
->mve_op
)
9683 case MVE_VLDRW_GATHER_T5
:
9684 case MVE_VSTRW_SCATTER_T5
:
9685 mod_imm
= mod_imm
<< 2;
9687 case MVE_VSTRD_SCATTER_T6
:
9688 case MVE_VLDRD_GATHER_T6
:
9689 mod_imm
= mod_imm
<< 3;
9696 func (stream
, "%lu", mod_imm
);
9700 func (stream
, "%lu", 64 - value
);
9704 unsigned int even_reg
= value
<< 1;
9705 func (stream
, "%s", arm_regnames
[even_reg
]);
9728 print_mve_rotate (info
, value
, width
);
9731 func (stream
, "%s", arm_regnames
[value
]);
9734 if (insn
->mve_op
== MVE_VQSHL_T2
9735 || insn
->mve_op
== MVE_VQSHLU_T3
9736 || insn
->mve_op
== MVE_VRSHR
9737 || insn
->mve_op
== MVE_VRSHRN
9738 || insn
->mve_op
== MVE_VSHL_T1
9739 || insn
->mve_op
== MVE_VSHLL_T1
9740 || insn
->mve_op
== MVE_VSHR
9741 || insn
->mve_op
== MVE_VSHRN
9742 || insn
->mve_op
== MVE_VSLI
9743 || insn
->mve_op
== MVE_VSRI
)
9744 print_mve_shift_n (info
, given
, insn
->mve_op
);
9745 else if (insn
->mve_op
== MVE_VSHLL_T2
)
9753 func (stream
, "16");
9756 print_mve_undefined (info
, UNDEF_SIZE_0
);
9765 if (insn
->mve_op
== MVE_VSHLC
&& value
== 0)
9767 func (stream
, "%ld", value
);
9768 value_in_comment
= value
;
9772 func (stream
, "s%ld", value
);
9776 func (stream
, "<illegal reg q%ld.5>", value
);
9778 func (stream
, "q%ld", value
);
9781 func (stream
, "0x%08lx", value
);
9793 func (stream
, "%c", *c
);
9796 if (value_in_comment
> 32 || value_in_comment
< -16)
9797 func (stream
, "\t; 0x%lx", value_in_comment
);
9799 if (is_unpredictable
)
9800 print_mve_unpredictable (info
, unpredictable_cond
);
9803 print_mve_undefined (info
, undefined_cond
);
9805 if ((vpt_block_state
.in_vpt_block
== FALSE
)
9807 && (is_vpt_instruction (given
) == TRUE
))
9808 mark_inside_vpt_block (given
);
9809 else if (vpt_block_state
.in_vpt_block
== TRUE
)
9810 update_vpt_block_state ();
9819 /* Return the name of a v7A special register. */
9822 banked_regname (unsigned reg
)
9826 case 15: return "CPSR";
9827 case 32: return "R8_usr";
9828 case 33: return "R9_usr";
9829 case 34: return "R10_usr";
9830 case 35: return "R11_usr";
9831 case 36: return "R12_usr";
9832 case 37: return "SP_usr";
9833 case 38: return "LR_usr";
9834 case 40: return "R8_fiq";
9835 case 41: return "R9_fiq";
9836 case 42: return "R10_fiq";
9837 case 43: return "R11_fiq";
9838 case 44: return "R12_fiq";
9839 case 45: return "SP_fiq";
9840 case 46: return "LR_fiq";
9841 case 48: return "LR_irq";
9842 case 49: return "SP_irq";
9843 case 50: return "LR_svc";
9844 case 51: return "SP_svc";
9845 case 52: return "LR_abt";
9846 case 53: return "SP_abt";
9847 case 54: return "LR_und";
9848 case 55: return "SP_und";
9849 case 60: return "LR_mon";
9850 case 61: return "SP_mon";
9851 case 62: return "ELR_hyp";
9852 case 63: return "SP_hyp";
9853 case 79: return "SPSR";
9854 case 110: return "SPSR_fiq";
9855 case 112: return "SPSR_irq";
9856 case 114: return "SPSR_svc";
9857 case 116: return "SPSR_abt";
9858 case 118: return "SPSR_und";
9859 case 124: return "SPSR_mon";
9860 case 126: return "SPSR_hyp";
9861 default: return NULL
;
9865 /* Return the name of the DMB/DSB option. */
9867 data_barrier_option (unsigned option
)
9869 switch (option
& 0xf)
9871 case 0xf: return "sy";
9872 case 0xe: return "st";
9873 case 0xd: return "ld";
9874 case 0xb: return "ish";
9875 case 0xa: return "ishst";
9876 case 0x9: return "ishld";
9877 case 0x7: return "un";
9878 case 0x6: return "unst";
9879 case 0x5: return "nshld";
9880 case 0x3: return "osh";
9881 case 0x2: return "oshst";
9882 case 0x1: return "oshld";
9883 default: return NULL
;
9887 /* Print one ARM instruction from PC on INFO->STREAM. */
9890 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
9892 const struct opcode32
*insn
;
9893 void *stream
= info
->stream
;
9894 fprintf_ftype func
= info
->fprintf_func
;
9895 struct arm_private_data
*private_data
= info
->private_data
;
9897 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
9900 if (print_insn_neon (info
, given
, FALSE
))
9903 if (print_insn_generic_coprocessor (pc
, info
, given
, FALSE
))
9906 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
9908 if ((given
& insn
->mask
) != insn
->value
)
9911 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
9914 /* Special case: an instruction with all bits set in the condition field
9915 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9916 or by the catchall at the end of the table. */
9917 if ((given
& 0xF0000000) != 0xF0000000
9918 || (insn
->mask
& 0xF0000000) == 0xF0000000
9919 || (insn
->mask
== 0 && insn
->value
== 0))
9921 unsigned long u_reg
= 16;
9922 unsigned long U_reg
= 16;
9923 bfd_boolean is_unpredictable
= FALSE
;
9924 signed long value_in_comment
= 0;
9927 for (c
= insn
->assembler
; *c
; c
++)
9931 bfd_boolean allow_unpredictable
= FALSE
;
9936 func (stream
, "%%");
9940 value_in_comment
= print_arm_address (pc
, info
, given
);
9944 /* Set P address bit and use normal address
9945 printing routine. */
9946 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
9950 allow_unpredictable
= TRUE
;
9953 if ((given
& 0x004f0000) == 0x004f0000)
9955 /* PC relative with immediate offset. */
9956 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
9960 /* Elide positive zero offset. */
9961 if (offset
|| NEGATIVE_BIT_SET
)
9962 func (stream
, "[pc, #%s%d]\t; ",
9963 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
9965 func (stream
, "[pc]\t; ");
9966 if (NEGATIVE_BIT_SET
)
9968 info
->print_address_func (offset
+ pc
+ 8, info
);
9972 /* Always show the offset. */
9973 func (stream
, "[pc], #%s%d",
9974 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
9975 if (! allow_unpredictable
)
9976 is_unpredictable
= TRUE
;
9981 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
9983 func (stream
, "[%s",
9984 arm_regnames
[(given
>> 16) & 0xf]);
9988 if (IMMEDIATE_BIT_SET
)
9990 /* Elide offset for non-writeback
9992 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
9994 func (stream
, ", #%s%d",
9995 NEGATIVE_BIT_SET
? "-" : "", offset
);
9997 if (NEGATIVE_BIT_SET
)
10000 value_in_comment
= offset
;
10004 /* Register Offset or Register Pre-Indexed. */
10005 func (stream
, ", %s%s",
10006 NEGATIVE_BIT_SET
? "-" : "",
10007 arm_regnames
[given
& 0xf]);
10009 /* Writing back to the register that is the source/
10010 destination of the load/store is unpredictable. */
10011 if (! allow_unpredictable
10012 && WRITEBACK_BIT_SET
10013 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
10014 is_unpredictable
= TRUE
;
10017 func (stream
, "]%s",
10018 WRITEBACK_BIT_SET
? "!" : "");
10022 if (IMMEDIATE_BIT_SET
)
10024 /* Immediate Post-indexed. */
10025 /* PR 10924: Offset must be printed, even if it is zero. */
10026 func (stream
, "], #%s%d",
10027 NEGATIVE_BIT_SET
? "-" : "", offset
);
10028 if (NEGATIVE_BIT_SET
)
10030 value_in_comment
= offset
;
10034 /* Register Post-indexed. */
10035 func (stream
, "], %s%s",
10036 NEGATIVE_BIT_SET
? "-" : "",
10037 arm_regnames
[given
& 0xf]);
10039 /* Writing back to the register that is the source/
10040 destination of the load/store is unpredictable. */
10041 if (! allow_unpredictable
10042 && (given
& 0xf) == ((given
>> 12) & 0xf))
10043 is_unpredictable
= TRUE
;
10046 if (! allow_unpredictable
)
10048 /* Writeback is automatically implied by post- addressing.
10049 Setting the W bit is unnecessary and ARM specify it as
10050 being unpredictable. */
10051 if (WRITEBACK_BIT_SET
10052 /* Specifying the PC register as the post-indexed
10053 registers is also unpredictable. */
10054 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
10055 is_unpredictable
= TRUE
;
10063 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
10064 bfd_vma target
= disp
* 4 + pc
+ 8;
10065 info
->print_address_func (target
, info
);
10067 /* Fill in instruction information. */
10068 info
->insn_info_valid
= 1;
10069 info
->insn_type
= dis_branch
;
10070 info
->target
= target
;
10075 if (((given
>> 28) & 0xf) != 0xe)
10076 func (stream
, "%s",
10077 arm_conditional
[(given
>> 28) & 0xf]);
10085 func (stream
, "{");
10086 for (reg
= 0; reg
< 16; reg
++)
10087 if ((given
& (1 << reg
)) != 0)
10090 func (stream
, ", ");
10092 func (stream
, "%s", arm_regnames
[reg
]);
10094 func (stream
, "}");
10096 is_unpredictable
= TRUE
;
10101 arm_decode_shift (given
, func
, stream
, FALSE
);
10105 if ((given
& 0x02000000) != 0)
10107 unsigned int rotate
= (given
& 0xf00) >> 7;
10108 unsigned int immed
= (given
& 0xff);
10111 a
= (immed
<< ((32 - rotate
) & 31)
10112 | immed
>> rotate
) & 0xffffffff;
10113 /* If there is another encoding with smaller rotate,
10114 the rotate should be specified directly. */
10115 for (i
= 0; i
< 32; i
+= 2)
10116 if ((a
<< i
| a
>> ((32 - i
) & 31)) <= 0xff)
10120 func (stream
, "#%d, %d", immed
, rotate
);
10122 func (stream
, "#%d", a
);
10123 value_in_comment
= a
;
10126 arm_decode_shift (given
, func
, stream
, TRUE
);
10130 if ((given
& 0x0000f000) == 0x0000f000)
10132 arm_feature_set arm_ext_v6
=
10133 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
10135 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10136 mechanism for setting PSR flag bits. They are
10137 obsolete in V6 onwards. */
10138 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
10140 func (stream
, "p");
10142 is_unpredictable
= TRUE
;
10147 if ((given
& 0x01200000) == 0x00200000)
10148 func (stream
, "t");
10153 int offset
= given
& 0xff;
10155 value_in_comment
= offset
* 4;
10156 if (NEGATIVE_BIT_SET
)
10157 value_in_comment
= - value_in_comment
;
10159 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
10164 func (stream
, ", #%d]%s",
10165 (int) value_in_comment
,
10166 WRITEBACK_BIT_SET
? "!" : "");
10168 func (stream
, "]");
10172 func (stream
, "]");
10174 if (WRITEBACK_BIT_SET
)
10177 func (stream
, ", #%d", (int) value_in_comment
);
10181 func (stream
, ", {%d}", (int) offset
);
10182 value_in_comment
= offset
;
10189 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10192 bfd_vma offset
= 0;
10194 if (! NEGATIVE_BIT_SET
)
10195 /* Is signed, hi bits should be ones. */
10196 offset
= (-1) ^ 0x00ffffff;
10198 /* Offset is (SignExtend(offset field)<<2). */
10199 offset
+= given
& 0x00ffffff;
10201 address
= offset
+ pc
+ 8;
10203 if (given
& 0x01000000)
10204 /* H bit allows addressing to 2-byte boundaries. */
10207 info
->print_address_func (address
, info
);
10209 /* Fill in instruction information. */
10210 info
->insn_info_valid
= 1;
10211 info
->insn_type
= dis_branch
;
10212 info
->target
= address
;
10217 if ((given
& 0x02000200) == 0x200)
10220 unsigned sysm
= (given
& 0x004f0000) >> 16;
10222 sysm
|= (given
& 0x300) >> 4;
10223 name
= banked_regname (sysm
);
10226 func (stream
, "%s", name
);
10228 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10232 func (stream
, "%cPSR_",
10233 (given
& 0x00400000) ? 'S' : 'C');
10234 if (given
& 0x80000)
10235 func (stream
, "f");
10236 if (given
& 0x40000)
10237 func (stream
, "s");
10238 if (given
& 0x20000)
10239 func (stream
, "x");
10240 if (given
& 0x10000)
10241 func (stream
, "c");
10246 if ((given
& 0xf0) == 0x60)
10248 switch (given
& 0xf)
10250 case 0xf: func (stream
, "sy"); break;
10252 func (stream
, "#%d", (int) given
& 0xf);
10258 const char * opt
= data_barrier_option (given
& 0xf);
10260 func (stream
, "%s", opt
);
10262 func (stream
, "#%d", (int) given
& 0xf);
10266 case '0': case '1': case '2': case '3': case '4':
10267 case '5': case '6': case '7': case '8': case '9':
10270 unsigned long value
;
10272 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
10278 is_unpredictable
= TRUE
;
10279 /* Fall through. */
10282 /* We want register + 1 when decoding T. */
10284 value
= (value
+ 1) & 0xf;
10288 /* Eat the 'u' character. */
10291 if (u_reg
== value
)
10292 is_unpredictable
= TRUE
;
10297 /* Eat the 'U' character. */
10300 if (U_reg
== value
)
10301 is_unpredictable
= TRUE
;
10304 func (stream
, "%s", arm_regnames
[value
]);
10307 func (stream
, "%ld", value
);
10308 value_in_comment
= value
;
10311 func (stream
, "%ld", value
* 8);
10312 value_in_comment
= value
* 8;
10315 func (stream
, "%ld", value
+ 1);
10316 value_in_comment
= value
+ 1;
10319 func (stream
, "0x%08lx", value
);
10321 /* Some SWI instructions have special
10323 if ((given
& 0x0fffffff) == 0x0FF00000)
10324 func (stream
, "\t; IMB");
10325 else if ((given
& 0x0fffffff) == 0x0FF00001)
10326 func (stream
, "\t; IMBRange");
10329 func (stream
, "%01lx", value
& 0xf);
10330 value_in_comment
= value
;
10335 func (stream
, "%c", *c
);
10339 if (value
== ((1ul << width
) - 1))
10340 func (stream
, "%c", *c
);
10343 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
10356 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
10357 func (stream
, "%d", imm
);
10358 value_in_comment
= imm
;
10363 /* LSB and WIDTH fields of BFI or BFC. The machine-
10364 language instruction encodes LSB and MSB. */
10366 long msb
= (given
& 0x001f0000) >> 16;
10367 long lsb
= (given
& 0x00000f80) >> 7;
10368 long w
= msb
- lsb
+ 1;
10371 func (stream
, "#%lu, #%lu", lsb
, w
);
10373 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
10378 /* Get the PSR/banked register name. */
10381 unsigned sysm
= (given
& 0x004f0000) >> 16;
10383 sysm
|= (given
& 0x300) >> 4;
10384 name
= banked_regname (sysm
);
10387 func (stream
, "%s", name
);
10389 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10394 /* 16-bit unsigned immediate from a MOVT or MOVW
10395 instruction, encoded in bits 0:11 and 15:19. */
10397 long hi
= (given
& 0x000f0000) >> 4;
10398 long lo
= (given
& 0x00000fff);
10399 long imm16
= hi
| lo
;
10401 func (stream
, "#%lu", imm16
);
10402 value_in_comment
= imm16
;
10411 func (stream
, "%c", *c
);
10414 if (value_in_comment
> 32 || value_in_comment
< -16)
10415 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
10417 if (is_unpredictable
)
10418 func (stream
, UNPREDICTABLE_INSTRUCTION
);
10423 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
10427 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
10430 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
10432 const struct opcode16
*insn
;
10433 void *stream
= info
->stream
;
10434 fprintf_ftype func
= info
->fprintf_func
;
10436 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
10437 if ((given
& insn
->mask
) == insn
->value
)
10439 signed long value_in_comment
= 0;
10440 const char *c
= insn
->assembler
;
10449 func (stream
, "%c", *c
);
10456 func (stream
, "%%");
10461 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10466 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10468 func (stream
, "s");
10475 ifthen_next_state
= given
& 0xff;
10476 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
10477 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
10478 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
10483 if (ifthen_next_state
)
10484 func (stream
, "\t; unpredictable branch in IT block\n");
10489 func (stream
, "\t; unpredictable <IT:%s>",
10490 arm_conditional
[IFTHEN_COND
]);
10497 reg
= (given
>> 3) & 0x7;
10498 if (given
& (1 << 6))
10501 func (stream
, "%s", arm_regnames
[reg
]);
10510 if (given
& (1 << 7))
10513 func (stream
, "%s", arm_regnames
[reg
]);
10518 if (given
& (1 << 8))
10520 /* Fall through. */
10522 if (*c
== 'O' && (given
& (1 << 8)))
10524 /* Fall through. */
10530 func (stream
, "{");
10532 /* It would be nice if we could spot
10533 ranges, and generate the rS-rE format: */
10534 for (reg
= 0; (reg
< 8); reg
++)
10535 if ((given
& (1 << reg
)) != 0)
10538 func (stream
, ", ");
10540 func (stream
, "%s", arm_regnames
[reg
]);
10546 func (stream
, ", ");
10548 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
10554 func (stream
, ", ");
10555 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
10558 func (stream
, "}");
10563 /* Print writeback indicator for a LDMIA. We are doing a
10564 writeback if the base register is not in the register
10566 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
10567 func (stream
, "!");
10571 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10573 bfd_vma address
= (pc
+ 4
10574 + ((given
& 0x00f8) >> 2)
10575 + ((given
& 0x0200) >> 3));
10576 info
->print_address_func (address
, info
);
10578 /* Fill in instruction information. */
10579 info
->insn_info_valid
= 1;
10580 info
->insn_type
= dis_branch
;
10581 info
->target
= address
;
10586 /* Right shift immediate -- bits 6..10; 1-31 print
10587 as themselves, 0 prints as 32. */
10589 long imm
= (given
& 0x07c0) >> 6;
10592 func (stream
, "#%ld", imm
);
10596 case '0': case '1': case '2': case '3': case '4':
10597 case '5': case '6': case '7': case '8': case '9':
10599 int bitstart
= *c
++ - '0';
10602 while (*c
>= '0' && *c
<= '9')
10603 bitstart
= (bitstart
* 10) + *c
++ - '0';
10612 while (*c
>= '0' && *c
<= '9')
10613 bitend
= (bitend
* 10) + *c
++ - '0';
10616 reg
= given
>> bitstart
;
10617 reg
&= (2 << (bitend
- bitstart
)) - 1;
10622 func (stream
, "%s", arm_regnames
[reg
]);
10626 func (stream
, "%ld", (long) reg
);
10627 value_in_comment
= reg
;
10631 func (stream
, "%ld", (long) (reg
<< 1));
10632 value_in_comment
= reg
<< 1;
10636 func (stream
, "%ld", (long) (reg
<< 2));
10637 value_in_comment
= reg
<< 2;
10641 /* PC-relative address -- the bottom two
10642 bits of the address are dropped
10643 before the calculation. */
10644 info
->print_address_func
10645 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
10646 value_in_comment
= 0;
10650 func (stream
, "0x%04lx", (long) reg
);
10654 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
10655 bfd_vma target
= reg
* 2 + pc
+ 4;
10656 info
->print_address_func (target
, info
);
10657 value_in_comment
= 0;
10659 /* Fill in instruction information. */
10660 info
->insn_info_valid
= 1;
10661 info
->insn_type
= dis_branch
;
10662 info
->target
= target
;
10666 func (stream
, "%s", arm_conditional
[reg
]);
10677 if ((given
& (1 << bitstart
)) != 0)
10678 func (stream
, "%c", *c
);
10683 if ((given
& (1 << bitstart
)) != 0)
10684 func (stream
, "%c", *c
++);
10686 func (stream
, "%c", *++c
);
10700 if (value_in_comment
> 32 || value_in_comment
< -16)
10701 func (stream
, "\t; 0x%lx", value_in_comment
);
10706 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
10710 /* Return the name of an V7M special register. */
10712 static const char *
10713 psr_name (int regno
)
10717 case 0x0: return "APSR";
10718 case 0x1: return "IAPSR";
10719 case 0x2: return "EAPSR";
10720 case 0x3: return "PSR";
10721 case 0x5: return "IPSR";
10722 case 0x6: return "EPSR";
10723 case 0x7: return "IEPSR";
10724 case 0x8: return "MSP";
10725 case 0x9: return "PSP";
10726 case 0xa: return "MSPLIM";
10727 case 0xb: return "PSPLIM";
10728 case 0x10: return "PRIMASK";
10729 case 0x11: return "BASEPRI";
10730 case 0x12: return "BASEPRI_MAX";
10731 case 0x13: return "FAULTMASK";
10732 case 0x14: return "CONTROL";
10733 case 0x88: return "MSP_NS";
10734 case 0x89: return "PSP_NS";
10735 case 0x8a: return "MSPLIM_NS";
10736 case 0x8b: return "PSPLIM_NS";
10737 case 0x90: return "PRIMASK_NS";
10738 case 0x91: return "BASEPRI_NS";
10739 case 0x93: return "FAULTMASK_NS";
10740 case 0x94: return "CONTROL_NS";
10741 case 0x98: return "SP_NS";
10742 default: return "<unknown>";
10746 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10749 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
10751 const struct opcode32
*insn
;
10752 void *stream
= info
->stream
;
10753 fprintf_ftype func
= info
->fprintf_func
;
10754 bfd_boolean is_mve
= is_mve_architecture (info
);
10756 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
10759 if ((is_mve
== FALSE
) && print_insn_neon (info
, given
, TRUE
))
10762 if (is_mve
&& print_insn_mve (info
, given
))
10765 if (print_insn_cde (info
, given
, TRUE
))
10768 if (print_insn_generic_coprocessor (pc
, info
, given
, TRUE
))
10771 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
10772 if ((given
& insn
->mask
) == insn
->value
)
10774 bfd_boolean is_clrm
= FALSE
;
10775 bfd_boolean is_unpredictable
= FALSE
;
10776 signed long value_in_comment
= 0;
10777 const char *c
= insn
->assembler
;
10783 func (stream
, "%c", *c
);
10790 func (stream
, "%%");
10795 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10799 if (ifthen_next_state
)
10800 func (stream
, "\t; unpredictable branch in IT block\n");
10805 func (stream
, "\t; unpredictable <IT:%s>",
10806 arm_conditional
[IFTHEN_COND
]);
10811 unsigned int imm12
= 0;
10813 imm12
|= (given
& 0x000000ffu
);
10814 imm12
|= (given
& 0x00007000u
) >> 4;
10815 imm12
|= (given
& 0x04000000u
) >> 15;
10816 func (stream
, "#%u", imm12
);
10817 value_in_comment
= imm12
;
10823 unsigned int bits
= 0, imm
, imm8
, mod
;
10825 bits
|= (given
& 0x000000ffu
);
10826 bits
|= (given
& 0x00007000u
) >> 4;
10827 bits
|= (given
& 0x04000000u
) >> 15;
10828 imm8
= (bits
& 0x0ff);
10829 mod
= (bits
& 0xf00) >> 8;
10832 case 0: imm
= imm8
; break;
10833 case 1: imm
= ((imm8
<< 16) | imm8
); break;
10834 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
10835 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
10837 mod
= (bits
& 0xf80) >> 7;
10838 imm8
= (bits
& 0x07f) | 0x80;
10839 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
10841 func (stream
, "#%u", imm
);
10842 value_in_comment
= imm
;
10848 unsigned int imm
= 0;
10850 imm
|= (given
& 0x000000ffu
);
10851 imm
|= (given
& 0x00007000u
) >> 4;
10852 imm
|= (given
& 0x04000000u
) >> 15;
10853 imm
|= (given
& 0x000f0000u
) >> 4;
10854 func (stream
, "#%u", imm
);
10855 value_in_comment
= imm
;
10861 unsigned int imm
= 0;
10863 imm
|= (given
& 0x000f0000u
) >> 16;
10864 imm
|= (given
& 0x00000ff0u
) >> 0;
10865 imm
|= (given
& 0x0000000fu
) << 12;
10866 func (stream
, "#%u", imm
);
10867 value_in_comment
= imm
;
10873 unsigned int imm
= 0;
10875 imm
|= (given
& 0x000f0000u
) >> 4;
10876 imm
|= (given
& 0x00000fffu
) >> 0;
10877 func (stream
, "#%u", imm
);
10878 value_in_comment
= imm
;
10884 unsigned int imm
= 0;
10886 imm
|= (given
& 0x00000fffu
);
10887 imm
|= (given
& 0x000f0000u
) >> 4;
10888 func (stream
, "#%u", imm
);
10889 value_in_comment
= imm
;
10895 unsigned int reg
= (given
& 0x0000000fu
);
10896 unsigned int stp
= (given
& 0x00000030u
) >> 4;
10897 unsigned int imm
= 0;
10898 imm
|= (given
& 0x000000c0u
) >> 6;
10899 imm
|= (given
& 0x00007000u
) >> 10;
10901 func (stream
, "%s", arm_regnames
[reg
]);
10906 func (stream
, ", lsl #%u", imm
);
10912 func (stream
, ", lsr #%u", imm
);
10918 func (stream
, ", asr #%u", imm
);
10923 func (stream
, ", rrx");
10925 func (stream
, ", ror #%u", imm
);
10932 unsigned int Rn
= (given
& 0x000f0000) >> 16;
10933 unsigned int U
= ! NEGATIVE_BIT_SET
;
10934 unsigned int op
= (given
& 0x00000f00) >> 8;
10935 unsigned int i12
= (given
& 0x00000fff);
10936 unsigned int i8
= (given
& 0x000000ff);
10937 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
10938 bfd_vma offset
= 0;
10940 func (stream
, "[%s", arm_regnames
[Rn
]);
10941 if (U
) /* 12-bit positive immediate offset. */
10945 value_in_comment
= offset
;
10947 else if (Rn
== 15) /* 12-bit negative immediate offset. */
10948 offset
= - (int) i12
;
10949 else if (op
== 0x0) /* Shifted register offset. */
10951 unsigned int Rm
= (i8
& 0x0f);
10952 unsigned int sh
= (i8
& 0x30) >> 4;
10954 func (stream
, ", %s", arm_regnames
[Rm
]);
10956 func (stream
, ", lsl #%u", sh
);
10957 func (stream
, "]");
10962 case 0xE: /* 8-bit positive immediate offset. */
10966 case 0xC: /* 8-bit negative immediate offset. */
10970 case 0xF: /* 8-bit + preindex with wb. */
10975 case 0xD: /* 8-bit - preindex with wb. */
10980 case 0xB: /* 8-bit + postindex. */
10985 case 0x9: /* 8-bit - postindex. */
10991 func (stream
, ", <undefined>]");
10996 func (stream
, "], #%d", (int) offset
);
11000 func (stream
, ", #%d", (int) offset
);
11001 func (stream
, writeback
? "]!" : "]");
11006 func (stream
, "\t; ");
11007 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
11015 unsigned int U
= ! NEGATIVE_BIT_SET
;
11016 unsigned int W
= WRITEBACK_BIT_SET
;
11017 unsigned int Rn
= (given
& 0x000f0000) >> 16;
11018 unsigned int off
= (given
& 0x000000ff);
11020 func (stream
, "[%s", arm_regnames
[Rn
]);
11026 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
11027 value_in_comment
= off
* 4 * (U
? 1 : -1);
11029 func (stream
, "]");
11031 func (stream
, "!");
11035 func (stream
, "], ");
11038 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
11039 value_in_comment
= off
* 4 * (U
? 1 : -1);
11043 func (stream
, "{%u}", off
);
11044 value_in_comment
= off
;
11052 unsigned int Sbit
= (given
& 0x01000000) >> 24;
11053 unsigned int type
= (given
& 0x00600000) >> 21;
11057 case 0: func (stream
, Sbit
? "sb" : "b"); break;
11058 case 1: func (stream
, Sbit
? "sh" : "h"); break;
11061 func (stream
, "??");
11064 func (stream
, "??");
11072 /* Fall through. */
11078 func (stream
, "{");
11079 for (reg
= 0; reg
< 16; reg
++)
11080 if ((given
& (1 << reg
)) != 0)
11083 func (stream
, ", ");
11085 if (is_clrm
&& reg
== 13)
11086 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
11087 else if (is_clrm
&& reg
== 15)
11088 func (stream
, "%s", "APSR");
11090 func (stream
, "%s", arm_regnames
[reg
]);
11092 func (stream
, "}");
11098 unsigned int msb
= (given
& 0x0000001f);
11099 unsigned int lsb
= 0;
11101 lsb
|= (given
& 0x000000c0u
) >> 6;
11102 lsb
|= (given
& 0x00007000u
) >> 10;
11103 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
11109 unsigned int width
= (given
& 0x0000001f) + 1;
11110 unsigned int lsb
= 0;
11112 lsb
|= (given
& 0x000000c0u
) >> 6;
11113 lsb
|= (given
& 0x00007000u
) >> 10;
11114 func (stream
, "#%u, #%u", lsb
, width
);
11120 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
11121 func (stream
, "%x", boff
);
11127 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
11128 unsigned int immB
= (given
& 0x000007feu
) >> 1;
11129 unsigned int immC
= (given
& 0x00000800u
) >> 11;
11130 bfd_vma offset
= 0;
11132 offset
|= immA
<< 12;
11133 offset
|= immB
<< 2;
11134 offset
|= immC
<< 1;
11136 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
11138 info
->print_address_func (pc
+ 4 + offset
, info
);
11144 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
11145 unsigned int immB
= (given
& 0x000007feu
) >> 1;
11146 unsigned int immC
= (given
& 0x00000800u
) >> 11;
11147 bfd_vma offset
= 0;
11149 offset
|= immA
<< 12;
11150 offset
|= immB
<< 2;
11151 offset
|= immC
<< 1;
11153 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
11155 info
->print_address_func (pc
+ 4 + offset
, info
);
11161 unsigned int immA
= (given
& 0x00010000u
) >> 16;
11162 unsigned int immB
= (given
& 0x000007feu
) >> 1;
11163 unsigned int immC
= (given
& 0x00000800u
) >> 11;
11164 bfd_vma offset
= 0;
11166 offset
|= immA
<< 12;
11167 offset
|= immB
<< 2;
11168 offset
|= immC
<< 1;
11170 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
11172 info
->print_address_func (pc
+ 4 + offset
, info
);
11174 unsigned int T
= (given
& 0x00020000u
) >> 17;
11175 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
11176 unsigned int boffset
= (T
== 1) ? 4 : 2;
11177 func (stream
, ", ");
11178 func (stream
, "%x", endoffset
+ boffset
);
11184 unsigned int immh
= (given
& 0x000007feu
) >> 1;
11185 unsigned int imml
= (given
& 0x00000800u
) >> 11;
11188 imm32
|= immh
<< 2;
11189 imm32
|= imml
<< 1;
11191 info
->print_address_func (pc
+ 4 + imm32
, info
);
11197 unsigned int immh
= (given
& 0x000007feu
) >> 1;
11198 unsigned int imml
= (given
& 0x00000800u
) >> 11;
11201 imm32
|= immh
<< 2;
11202 imm32
|= imml
<< 1;
11204 info
->print_address_func (pc
+ 4 - imm32
, info
);
11210 unsigned int S
= (given
& 0x04000000u
) >> 26;
11211 unsigned int J1
= (given
& 0x00002000u
) >> 13;
11212 unsigned int J2
= (given
& 0x00000800u
) >> 11;
11213 bfd_vma offset
= 0;
11215 offset
|= !S
<< 20;
11216 offset
|= J2
<< 19;
11217 offset
|= J1
<< 18;
11218 offset
|= (given
& 0x003f0000) >> 4;
11219 offset
|= (given
& 0x000007ff) << 1;
11220 offset
-= (1 << 20);
11222 bfd_vma target
= pc
+ 4 + offset
;
11223 info
->print_address_func (target
, info
);
11225 /* Fill in instruction information. */
11226 info
->insn_info_valid
= 1;
11227 info
->insn_type
= dis_branch
;
11228 info
->target
= target
;
11234 unsigned int S
= (given
& 0x04000000u
) >> 26;
11235 unsigned int I1
= (given
& 0x00002000u
) >> 13;
11236 unsigned int I2
= (given
& 0x00000800u
) >> 11;
11237 bfd_vma offset
= 0;
11239 offset
|= !S
<< 24;
11240 offset
|= !(I1
^ S
) << 23;
11241 offset
|= !(I2
^ S
) << 22;
11242 offset
|= (given
& 0x03ff0000u
) >> 4;
11243 offset
|= (given
& 0x000007ffu
) << 1;
11244 offset
-= (1 << 24);
11247 /* BLX target addresses are always word aligned. */
11248 if ((given
& 0x00001000u
) == 0)
11251 info
->print_address_func (offset
, info
);
11253 /* Fill in instruction information. */
11254 info
->insn_info_valid
= 1;
11255 info
->insn_type
= dis_branch
;
11256 info
->target
= offset
;
11262 unsigned int shift
= 0;
11264 shift
|= (given
& 0x000000c0u
) >> 6;
11265 shift
|= (given
& 0x00007000u
) >> 10;
11266 if (WRITEBACK_BIT_SET
)
11267 func (stream
, ", asr #%u", shift
);
11269 func (stream
, ", lsl #%u", shift
);
11270 /* else print nothing - lsl #0 */
11276 unsigned int rot
= (given
& 0x00000030) >> 4;
11279 func (stream
, ", ror #%u", rot
* 8);
11284 if ((given
& 0xf0) == 0x60)
11286 switch (given
& 0xf)
11288 case 0xf: func (stream
, "sy"); break;
11290 func (stream
, "#%d", (int) given
& 0xf);
11296 const char * opt
= data_barrier_option (given
& 0xf);
11298 func (stream
, "%s", opt
);
11300 func (stream
, "#%d", (int) given
& 0xf);
11305 if ((given
& 0xff) == 0)
11307 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
11309 func (stream
, "f");
11311 func (stream
, "s");
11313 func (stream
, "x");
11315 func (stream
, "c");
11317 else if ((given
& 0x20) == 0x20)
11320 unsigned sysm
= (given
& 0xf00) >> 8;
11322 sysm
|= (given
& 0x30);
11323 sysm
|= (given
& 0x00100000) >> 14;
11324 name
= banked_regname (sysm
);
11327 func (stream
, "%s", name
);
11329 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
11333 func (stream
, "%s", psr_name (given
& 0xff));
11338 if (((given
& 0xff) == 0)
11339 || ((given
& 0x20) == 0x20))
11342 unsigned sm
= (given
& 0xf0000) >> 16;
11344 sm
|= (given
& 0x30);
11345 sm
|= (given
& 0x00100000) >> 14;
11346 name
= banked_regname (sm
);
11349 func (stream
, "%s", name
);
11351 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
11354 func (stream
, "%s", psr_name (given
& 0xff));
11357 case '0': case '1': case '2': case '3': case '4':
11358 case '5': case '6': case '7': case '8': case '9':
11363 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
11369 func (stream
, "%s", mve_vec_sizename
[val
]);
11371 func (stream
, "<undef size>");
11375 func (stream
, "%lu", val
);
11376 value_in_comment
= val
;
11380 func (stream
, "%lu", val
+ 1);
11381 value_in_comment
= val
+ 1;
11385 func (stream
, "%lu", val
* 4);
11386 value_in_comment
= val
* 4;
11391 is_unpredictable
= TRUE
;
11392 /* Fall through. */
11395 is_unpredictable
= TRUE
;
11396 /* Fall through. */
11398 func (stream
, "%s", arm_regnames
[val
]);
11402 func (stream
, "%s", arm_conditional
[val
]);
11407 if (val
== ((1ul << width
) - 1))
11408 func (stream
, "%c", *c
);
11414 func (stream
, "%c", *c
);
11418 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
11423 func (stream
, "0x%lx", val
& 0xffffffffUL
);
11433 /* PR binutils/12534
11434 If we have a PC relative offset in an LDRD or STRD
11435 instructions then display the decoded address. */
11436 if (((given
>> 16) & 0xf) == 0xf)
11438 bfd_vma offset
= (given
& 0xff) * 4;
11440 if ((given
& (1 << 23)) == 0)
11442 func (stream
, "\t; ");
11443 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
11452 if (value_in_comment
> 32 || value_in_comment
< -16)
11453 func (stream
, "\t; 0x%lx", value_in_comment
);
11455 if (is_unpredictable
)
11456 func (stream
, UNPREDICTABLE_INSTRUCTION
);
11462 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
11466 /* Print data bytes on INFO->STREAM. */
11469 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
11470 struct disassemble_info
*info
,
11473 switch (info
->bytes_per_chunk
)
11476 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
11479 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
11482 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
11489 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
11490 being displayed in symbol relative addresses.
11492 Also disallow private symbol, with __tagsym$$ prefix,
11493 from ARM RVCT toolchain being displayed. */
11496 arm_symbol_is_valid (asymbol
* sym
,
11497 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
11504 name
= bfd_asymbol_name (sym
);
11506 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
11509 /* Parse the string of disassembler options. */
11512 parse_arm_disassembler_options (const char *options
)
11516 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
11518 if (CONST_STRNEQ (opt
, "reg-names-"))
11521 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11522 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
11524 regname_selected
= i
;
11528 if (i
>= NUM_ARM_OPTIONS
)
11529 /* xgettext: c-format */
11530 opcodes_error_handler (_("unrecognised register name set: %s"),
11533 else if (CONST_STRNEQ (opt
, "force-thumb"))
11535 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
11537 else if (CONST_STRNEQ (opt
, "coproc"))
11539 const char *procptr
= opt
+ sizeof ("coproc") - 1;
11541 uint8_t coproc_number
= strtol (procptr
, &endptr
, 10);
11542 if (endptr
!= procptr
+ 1 || coproc_number
> 7)
11544 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
11548 if (*endptr
!= '=')
11550 opcodes_error_handler (_("coproc must have an argument: %s"),
11555 if (CONST_STRNEQ (endptr
, "generic"))
11556 cde_coprocs
&= ~(1 << coproc_number
);
11557 else if (CONST_STRNEQ (endptr
, "cde")
11558 || CONST_STRNEQ (endptr
, "CDE"))
11559 cde_coprocs
|= (1 << coproc_number
);
11562 opcodes_error_handler (
11563 _("coprocN argument takes options \"generic\","
11564 " \"cde\", or \"CDE\": %s"), opt
);
11568 /* xgettext: c-format */
11569 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
11576 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
11577 enum map_type
*map_symbol
);
11579 /* Search back through the insn stream to determine if this instruction is
11580 conditionally executed. */
11583 find_ifthen_state (bfd_vma pc
,
11584 struct disassemble_info
*info
,
11585 bfd_boolean little
)
11587 unsigned char b
[2];
11590 /* COUNT is twice the number of instructions seen. It will be odd if we
11591 just crossed an instruction boundary. */
11594 unsigned int seen_it
;
11597 ifthen_address
= pc
;
11604 /* Scan backwards looking for IT instructions, keeping track of where
11605 instruction boundaries are. We don't know if something is actually an
11606 IT instruction until we find a definite instruction boundary. */
11609 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
11611 /* A symbol must be on an instruction boundary, and will not
11612 be within an IT block. */
11613 if (seen_it
&& (count
& 1))
11619 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
11624 insn
= (b
[0]) | (b
[1] << 8);
11626 insn
= (b
[1]) | (b
[0] << 8);
11629 if ((insn
& 0xf800) < 0xe800)
11631 /* Addr + 2 is an instruction boundary. See if this matches
11632 the expected boundary based on the position of the last
11639 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
11641 enum map_type type
= MAP_ARM
;
11642 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
11644 if (!found
|| (found
&& type
== MAP_THUMB
))
11646 /* This could be an IT instruction. */
11648 it_count
= count
>> 1;
11651 if ((insn
& 0xf800) >= 0xe800)
11654 count
= (count
+ 2) | 1;
11655 /* IT blocks contain at most 4 instructions. */
11656 if (count
>= 8 && !seen_it
)
11659 /* We found an IT instruction. */
11660 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
11661 if ((ifthen_state
& 0xf) == 0)
11665 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11669 is_mapping_symbol (struct disassemble_info
*info
, int n
,
11670 enum map_type
*map_type
)
11674 name
= bfd_asymbol_name (info
->symtab
[n
]);
11675 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
11676 && (name
[2] == 0 || name
[2] == '.'))
11678 *map_type
= ((name
[1] == 'a') ? MAP_ARM
11679 : (name
[1] == 't') ? MAP_THUMB
11687 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11688 Returns nonzero if *MAP_TYPE was set. */
11691 get_map_sym_type (struct disassemble_info
*info
,
11693 enum map_type
*map_type
)
11695 /* If the symbol is in a different section, ignore it. */
11696 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
11699 return is_mapping_symbol (info
, n
, map_type
);
11702 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
11703 Returns nonzero if *MAP_TYPE was set. */
11706 get_sym_code_type (struct disassemble_info
*info
,
11708 enum map_type
*map_type
)
11710 elf_symbol_type
*es
;
11713 /* If the symbol is in a different section, ignore it. */
11714 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
11717 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
11718 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
11720 /* If the symbol has function type then use that. */
11721 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
11723 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
11724 == ST_BRANCH_TO_THUMB
)
11725 *map_type
= MAP_THUMB
;
11727 *map_type
= MAP_ARM
;
11734 /* Search the mapping symbol state for instruction at pc. This is only
11735 applicable for elf target.
11737 There is an assumption Here, info->private_data contains the correct AND
11738 up-to-date information about current scan process. The information will be
11739 used to speed this search process.
11741 Return TRUE if the mapping state can be determined, and map_symbol
11742 will be updated accordingly. Otherwise, return FALSE. */
11745 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
11746 enum map_type
*map_symbol
)
11748 bfd_vma addr
, section_vma
= 0;
11749 int n
, last_sym
= -1;
11750 bfd_boolean found
= FALSE
;
11751 bfd_boolean can_use_search_opt_p
= FALSE
;
11753 /* Default to DATA. A text section is required by the ABI to contain an
11754 INSN mapping symbol at the start. A data section has no such
11755 requirement, hence if no mapping symbol is found the section must
11756 contain only data. This however isn't very useful if the user has
11757 fully stripped the binaries. If this is the case use the section
11758 attributes to determine the default. If we have no section default to
11759 INSN as well, as we may be disassembling some raw bytes on a baremetal
11760 HEX file or similar. */
11761 enum map_type type
= MAP_DATA
;
11762 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
11764 struct arm_private_data
*private_data
;
11766 if (info
->private_data
== NULL
11767 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
11770 private_data
= info
->private_data
;
11772 /* First, look for mapping symbols. */
11773 if (info
->symtab_size
!= 0)
11775 if (pc
<= private_data
->last_mapping_addr
)
11776 private_data
->last_mapping_sym
= -1;
11778 /* Start scanning at the start of the function, or wherever
11779 we finished last time. */
11780 n
= info
->symtab_pos
+ 1;
11782 /* If the last stop offset is different from the current one it means we
11783 are disassembling a different glob of bytes. As such the optimization
11784 would not be safe and we should start over. */
11785 can_use_search_opt_p
11786 = private_data
->last_mapping_sym
>= 0
11787 && info
->stop_offset
== private_data
->last_stop_offset
;
11789 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
11790 n
= private_data
->last_mapping_sym
;
11792 /* Look down while we haven't passed the location being disassembled.
11793 The reason for this is that there's no defined order between a symbol
11794 and an mapping symbol that may be at the same address. We may have to
11795 look at least one position ahead. */
11796 for (; n
< info
->symtab_size
; n
++)
11798 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11801 if (get_map_sym_type (info
, n
, &type
))
11810 n
= info
->symtab_pos
;
11811 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
11812 n
= private_data
->last_mapping_sym
;
11814 /* No mapping symbol found at this address. Look backwards
11815 for a preceeding one, but don't go pass the section start
11816 otherwise a data section with no mapping symbol can pick up
11817 a text mapping symbol of a preceeding section. The documentation
11818 says section can be NULL, in which case we will seek up all the
11821 section_vma
= info
->section
->vma
;
11823 for (; n
>= 0; n
--)
11825 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11826 if (addr
< section_vma
)
11829 if (get_map_sym_type (info
, n
, &type
))
11839 /* If no mapping symbol was found, try looking up without a mapping
11840 symbol. This is done by walking up from the current PC to the nearest
11841 symbol. We don't actually have to loop here since symtab_pos will
11842 contain the nearest symbol already. */
11845 n
= info
->symtab_pos
;
11846 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
11853 private_data
->last_mapping_sym
= last_sym
;
11854 private_data
->last_type
= type
;
11855 private_data
->last_stop_offset
= info
->stop_offset
;
11857 *map_symbol
= type
;
11861 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11862 of the supplied arm_feature_set structure with bitmasks indicating
11863 the supported base architectures and coprocessor extensions.
11865 FIXME: This could more efficiently implemented as a constant array,
11866 although it would also be less robust. */
11869 select_arm_features (unsigned long mach
,
11870 arm_feature_set
* features
)
11872 arm_feature_set arch_fset
;
11873 const arm_feature_set fpu_any
= FPU_ANY
;
11875 #undef ARM_SET_FEATURES
11876 #define ARM_SET_FEATURES(FSET) \
11878 const arm_feature_set fset = FSET; \
11879 arch_fset = fset; \
11882 /* When several architecture versions share the same bfd_mach_arm_XXX value
11883 the most featureful is chosen. */
11886 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
11887 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
11888 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
11889 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
11890 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
11891 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
11892 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
11893 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
11894 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
11895 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
11896 case bfd_mach_arm_ep9312
:
11897 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
11898 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
11900 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
11901 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
11902 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
11903 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
11904 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
11905 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
11906 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
11907 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
11908 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
11909 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
11910 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
11911 case bfd_mach_arm_8
:
11913 /* Add bits for extensions that Armv8.6-A recognizes. */
11914 arm_feature_set armv8_6_ext_fset
11915 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
11916 ARM_SET_FEATURES (ARM_ARCH_V8_6A
);
11917 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_6_ext_fset
);
11920 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
11921 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
11922 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
11923 case bfd_mach_arm_8_1M_MAIN
:
11924 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
11925 arm_feature_set mve_all
11926 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
);
11927 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, mve_all
);
11930 /* If the machine type is unknown allow all architecture types and all
11931 extensions, with the exception of MVE as that clashes with NEON. */
11932 case bfd_mach_arm_unknown
:
11933 ARM_SET_FEATURES (ARM_FEATURE (-1,
11934 -1 & ~(ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
),
11940 #undef ARM_SET_FEATURES
11942 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11943 and thus on bfd_mach_arm_XXX value. Therefore for a given
11944 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11945 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
11949 /* NOTE: There are no checks in these routines that
11950 the relevant number of data bytes exist. */
11953 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
11955 unsigned char b
[4];
11956 unsigned long given
;
11958 int is_thumb
= FALSE
;
11959 int is_data
= FALSE
;
11961 unsigned int size
= 4;
11962 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
11963 bfd_boolean found
= FALSE
;
11964 struct arm_private_data
*private_data
;
11966 /* Clear instruction information field. */
11967 info
->insn_info_valid
= 0;
11968 info
->branch_delay_insns
= 0;
11969 info
->data_size
= 0;
11970 info
->insn_type
= dis_noninsn
;
11974 if (info
->disassembler_options
)
11976 parse_arm_disassembler_options (info
->disassembler_options
);
11978 /* To avoid repeated parsing of these options, we remove them here. */
11979 info
->disassembler_options
= NULL
;
11982 /* PR 10288: Control which instructions will be disassembled. */
11983 if (info
->private_data
== NULL
)
11985 static struct arm_private_data
private;
11987 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
11988 /* If the user did not use the -m command line switch then default to
11989 disassembling all types of ARM instruction.
11991 The info->mach value has to be ignored as this will be based on
11992 the default archictecture for the target and/or hints in the notes
11993 section, but it will never be greater than the current largest arm
11994 machine value (iWMMXt2), which is only equivalent to the V5TE
11995 architecture. ARM architectures have advanced beyond the machine
11996 value encoding, and these newer architectures would be ignored if
11997 the machine value was used.
11999 Ie the -m switch is used to restrict which instructions will be
12000 disassembled. If it is necessary to use the -m switch to tell
12001 objdump that an ARM binary is being disassembled, eg because the
12002 input is a raw binary file, but it is also desired to disassemble
12003 all ARM instructions then use "-marm". This will select the
12004 "unknown" arm architecture which is compatible with any ARM
12006 info
->mach
= bfd_mach_arm_unknown
;
12008 /* Compute the architecture bitmask from the machine number.
12009 Note: This assumes that the machine number will not change
12010 during disassembly.... */
12011 select_arm_features (info
->mach
, & private.features
);
12013 private.last_mapping_sym
= -1;
12014 private.last_mapping_addr
= 0;
12015 private.last_stop_offset
= 0;
12017 info
->private_data
= & private;
12020 private_data
= info
->private_data
;
12022 /* Decide if our code is going to be little-endian, despite what the
12023 function argument might say. */
12024 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
12026 /* For ELF, consult the symbol table to determine what kind of code
12027 or data we have. */
12028 if (info
->symtab_size
!= 0
12029 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
12034 enum map_type type
= MAP_ARM
;
12036 found
= mapping_symbol_for_insn (pc
, info
, &type
);
12037 last_sym
= private_data
->last_mapping_sym
;
12039 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
12040 is_data
= (private_data
->last_type
== MAP_DATA
);
12042 /* Look a little bit ahead to see if we should print out
12043 two or four bytes of data. If there's a symbol,
12044 mapping or otherwise, after two bytes then don't
12048 size
= 4 - (pc
& 3);
12049 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
12051 addr
= bfd_asymbol_value (info
->symtab
[n
]);
12053 && (info
->section
== NULL
12054 || info
->section
== info
->symtab
[n
]->section
))
12056 if (addr
- pc
< size
)
12061 /* If the next symbol is after three bytes, we need to
12062 print only part of the data, so that we can use either
12063 .byte or .short. */
12065 size
= (pc
& 1) ? 1 : 2;
12069 if (info
->symbols
!= NULL
)
12071 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
12073 coff_symbol_type
* cs
;
12075 cs
= coffsymbol (*info
->symbols
);
12076 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
12077 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
12078 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
12079 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
12080 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
12082 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
12085 /* If no mapping symbol has been found then fall back to the type
12086 of the function symbol. */
12087 elf_symbol_type
* es
;
12090 es
= *(elf_symbol_type
**)(info
->symbols
);
12091 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
12094 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
12095 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
12097 else if (bfd_asymbol_flavour (*info
->symbols
)
12098 == bfd_target_mach_o_flavour
)
12100 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
12102 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
12110 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
12112 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
12114 info
->bytes_per_line
= 4;
12116 /* PR 10263: Disassemble data if requested to do so by the user. */
12117 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
12121 /* Size was already set above. */
12122 info
->bytes_per_chunk
= size
;
12123 printer
= print_insn_data
;
12125 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
12128 for (i
= size
- 1; i
>= 0; i
--)
12129 given
= b
[i
] | (given
<< 8);
12131 for (i
= 0; i
< (int) size
; i
++)
12132 given
= b
[i
] | (given
<< 8);
12134 else if (!is_thumb
)
12136 /* In ARM mode endianness is a straightforward issue: the instruction
12137 is four bytes long and is either ordered 0123 or 3210. */
12138 printer
= print_insn_arm
;
12139 info
->bytes_per_chunk
= 4;
12142 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
12144 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | ((unsigned) b
[3] << 24);
12146 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | ((unsigned) b
[0] << 24);
12150 /* In Thumb mode we have the additional wrinkle of two
12151 instruction lengths. Fortunately, the bits that determine
12152 the length of the current instruction are always to be found
12153 in the first two bytes. */
12154 printer
= print_insn_thumb16
;
12155 info
->bytes_per_chunk
= 2;
12158 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
12160 given
= (b
[0]) | (b
[1] << 8);
12162 given
= (b
[1]) | (b
[0] << 8);
12166 /* These bit patterns signal a four-byte Thumb
12168 if ((given
& 0xF800) == 0xF800
12169 || (given
& 0xF800) == 0xF000
12170 || (given
& 0xF800) == 0xE800)
12172 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
12174 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
12176 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
12178 printer
= print_insn_thumb32
;
12183 if (ifthen_address
!= pc
)
12184 find_ifthen_state (pc
, info
, little_code
);
12188 if ((ifthen_state
& 0xf) == 0x8)
12189 ifthen_next_state
= 0;
12191 ifthen_next_state
= (ifthen_state
& 0xe0)
12192 | ((ifthen_state
& 0xf) << 1);
12198 info
->memory_error_func (status
, pc
, info
);
12201 if (info
->flags
& INSN_HAS_RELOC
)
12202 /* If the instruction has a reloc associated with it, then
12203 the offset field in the instruction will actually be the
12204 addend for the reloc. (We are using REL type relocs).
12205 In such cases, we can ignore the pc when computing
12206 addresses, since the addend is not currently pc-relative. */
12209 printer (pc
, info
, given
);
12213 ifthen_state
= ifthen_next_state
;
12214 ifthen_address
+= size
;
12220 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
12222 /* Detect BE8-ness and record it in the disassembler info. */
12223 if (info
->flavour
== bfd_target_elf_flavour
12224 && info
->section
!= NULL
12225 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
12226 info
->endian_code
= BFD_ENDIAN_LITTLE
;
12228 return print_insn (pc
, info
, FALSE
);
12232 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
12234 return print_insn (pc
, info
, TRUE
);
12237 const disasm_options_and_args_t
*
12238 disassembler_options_arm (void)
12240 static disasm_options_and_args_t
*opts_and_args
;
12242 if (opts_and_args
== NULL
)
12244 disasm_options_t
*opts
;
12247 opts_and_args
= XNEW (disasm_options_and_args_t
);
12248 opts_and_args
->args
= NULL
;
12250 opts
= &opts_and_args
->options
;
12251 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
12252 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
12254 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
12256 opts
->name
[i
] = regnames
[i
].name
;
12257 if (regnames
[i
].description
!= NULL
)
12258 opts
->description
[i
] = _(regnames
[i
].description
);
12260 opts
->description
[i
] = NULL
;
12262 /* The array we return must be NULL terminated. */
12263 opts
->name
[i
] = NULL
;
12264 opts
->description
[i
] = NULL
;
12267 return opts_and_args
;
12271 print_arm_disassembler_options (FILE *stream
)
12273 unsigned int i
, max_len
= 0;
12274 fprintf (stream
, _("\n\
12275 The following ARM specific disassembler options are supported for use with\n\
12276 the -M switch:\n"));
12278 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
12280 unsigned int len
= strlen (regnames
[i
].name
);
12285 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
12286 fprintf (stream
, " %s%*c %s\n",
12288 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
12289 _(regnames
[i
].description
));