* alpha-dis.c: Don't include <stdlib.h>.
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This program is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2 of the License, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
22 #include "sysdep.h"
23 #include "dis-asm.h"
24 #define DEFINE_TABLE
25 #include "arm-opc.h"
26 #include "coff/internal.h"
27 #include "libcoff.h"
28 #include "opintl.h"
29
30 /* FIXME: This shouldn't be done here */
31 #include "elf-bfd.h"
32 #include "elf/internal.h"
33 #include "elf/arm.h"
34
35 static char * arm_conditional[] =
36 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
37 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
38
39 static char * arm_regnames_raw[] =
40 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
41 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
42
43 static char * arm_regnames_standard[] =
44 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
45 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc"};
46
47 static char * arm_regnames_apcs[] =
48 {"a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4",
49 "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc"};
50
51 /* Choose which register name set to use. */
52 static char ** arm_regnames = arm_regnames_standard;
53
54 static char * arm_fp_const[] =
55 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
56
57 static char * arm_shift[] =
58 {"lsl", "lsr", "asr", "ror"};
59
60 static int print_insn_arm
61 PARAMS ((bfd_vma, struct disassemble_info *, long));
62
63 static void
64 arm_decode_shift (given, func, stream)
65 long given;
66 fprintf_ftype func;
67 void * stream;
68 {
69 func (stream, "%s", arm_regnames[given & 0xf]);
70
71 if ((given & 0xff0) != 0)
72 {
73 if ((given & 0x10) == 0)
74 {
75 int amount = (given & 0xf80) >> 7;
76 int shift = (given & 0x60) >> 5;
77
78 if (amount == 0)
79 {
80 if (shift == 3)
81 {
82 func (stream, ", rrx");
83 return;
84 }
85
86 amount = 32;
87 }
88
89 func (stream, ", %s #%d", arm_shift[shift], amount);
90 }
91 else
92 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
93 arm_regnames[(given & 0xf00) >> 8]);
94 }
95 }
96
97 /* Print one instruction from PC on INFO->STREAM.
98 Return the size of the instruction (always 4 on ARM). */
99
100 static int
101 print_insn_arm (pc, info, given)
102 bfd_vma pc;
103 struct disassemble_info * info;
104 long given;
105 {
106 struct arm_opcode * insn;
107 void * stream = info->stream;
108 fprintf_ftype func = info->fprintf_func;
109
110 for (insn = arm_opcodes; insn->assembler; insn++)
111 {
112 if ((given & insn->mask) == insn->value)
113 {
114 char * c;
115
116 for (c = insn->assembler; *c; c++)
117 {
118 if (*c == '%')
119 {
120 switch (*++c)
121 {
122 case '%':
123 func (stream, "%%");
124 break;
125
126 case 'a':
127 if (((given & 0x000f0000) == 0x000f0000)
128 && ((given & 0x02000000) == 0))
129 {
130 int offset = given & 0xfff;
131
132 func (stream, "[pc");
133
134 if (given & 0x01000000)
135 {
136 if ((given & 0x00800000) == 0)
137 offset = - offset;
138
139 /* pre-indexed */
140 func (stream, ", #%x]", offset);
141
142 offset += pc + 8;
143
144 /* Cope with the possibility of write-back being used.
145 Probably a very dangerous thing for the programmer
146 to do, but who are we to argue ? */
147 if (given & 0x00200000)
148 func (stream, "!");
149 }
150 else
151 {
152 /* post indexed */
153 func (stream, "], #%x", offset);
154
155 offset = pc + 8; /* ie ignore the offset */
156 }
157
158 func (stream, "\t; ");
159 info->print_address_func (offset, info);
160 }
161 else
162 {
163 func (stream, "[%s",
164 arm_regnames[(given >> 16) & 0xf]);
165 if ((given & 0x01000000) != 0)
166 {
167 if ((given & 0x02000000) == 0)
168 {
169 int offset = given & 0xfff;
170 if (offset)
171 func (stream, ", %s#%d",
172 (((given & 0x00800000) == 0)
173 ? "-" : ""), offset);
174 }
175 else
176 {
177 func (stream, ", %s",
178 (((given & 0x00800000) == 0)
179 ? "-" : ""));
180 arm_decode_shift (given, func, stream);
181 }
182
183 func (stream, "]%s",
184 ((given & 0x00200000) != 0) ? "!" : "");
185 }
186 else
187 {
188 if ((given & 0x02000000) == 0)
189 {
190 int offset = given & 0xfff;
191 if (offset)
192 func (stream, "], %s#%d",
193 (((given & 0x00800000) == 0)
194 ? "-" : ""), offset);
195 else
196 func (stream, "]");
197 }
198 else
199 {
200 func (stream, "], %s",
201 (((given & 0x00800000) == 0)
202 ? "-" : ""));
203 arm_decode_shift (given, func, stream);
204 }
205 }
206 }
207 break;
208
209 case 's':
210 if ((given & 0x004f0000) == 0x004f0000)
211 {
212 /* PC relative with immediate offset */
213 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
214
215 if ((given & 0x00800000) == 0)
216 offset = -offset;
217
218 func (stream, "[pc, #%x]\t; ", offset);
219
220 (*info->print_address_func)
221 (offset + pc + 8, info);
222 }
223 else
224 {
225 func (stream, "[%s",
226 arm_regnames[(given >> 16) & 0xf]);
227 if ((given & 0x01000000) != 0)
228 {
229 /* pre-indexed */
230 if ((given & 0x00400000) == 0x00400000)
231 {
232 /* immediate */
233 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
234 if (offset)
235 func (stream, ", %s#%d",
236 (((given & 0x00800000) == 0)
237 ? "-" : ""), offset);
238 }
239 else
240 {
241 /* register */
242 func (stream, ", %s%s",
243 (((given & 0x00800000) == 0)
244 ? "-" : ""),
245 arm_regnames[given & 0xf]);
246 }
247
248 func (stream, "]%s",
249 ((given & 0x00200000) != 0) ? "!" : "");
250 }
251 else
252 {
253 /* post-indexed */
254 if ((given & 0x00400000) == 0x00400000)
255 {
256 /* immediate */
257 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
258 if (offset)
259 func (stream, "], %s#%d",
260 (((given & 0x00800000) == 0)
261 ? "-" : ""), offset);
262 else
263 func (stream, "]");
264 }
265 else
266 {
267 /* register */
268 func (stream, "], %s%s",
269 (((given & 0x00800000) == 0)
270 ? "-" : ""),
271 arm_regnames[given & 0xf]);
272 }
273 }
274 }
275 break;
276
277 case 'b':
278 (*info->print_address_func)
279 (BDISP (given) * 4 + pc + 8, info);
280 break;
281
282 case 'c':
283 func (stream, "%s",
284 arm_conditional [(given >> 28) & 0xf]);
285 break;
286
287 case 'm':
288 {
289 int started = 0;
290 int reg;
291
292 func (stream, "{");
293 for (reg = 0; reg < 16; reg++)
294 if ((given & (1 << reg)) != 0)
295 {
296 if (started)
297 func (stream, ", ");
298 started = 1;
299 func (stream, "%s", arm_regnames[reg]);
300 }
301 func (stream, "}");
302 }
303 break;
304
305 case 'o':
306 if ((given & 0x02000000) != 0)
307 {
308 int rotate = (given & 0xf00) >> 7;
309 int immed = (given & 0xff);
310 func (stream, "#%d",
311 ((immed << (32 - rotate))
312 | (immed >> rotate)) & 0xffffffff);
313 }
314 else
315 arm_decode_shift (given, func, stream);
316 break;
317
318 case 'p':
319 if ((given & 0x0000f000) == 0x0000f000)
320 func (stream, "p");
321 break;
322
323 case 't':
324 if ((given & 0x01200000) == 0x00200000)
325 func (stream, "t");
326 break;
327
328 case 'h':
329 if ((given & 0x00000020) == 0x00000020)
330 func (stream, "h");
331 else
332 func (stream, "b");
333 break;
334
335 case 'A':
336 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
337 if ((given & 0x01000000) != 0)
338 {
339 int offset = given & 0xff;
340 if (offset)
341 func (stream, ", %s#%d]%s",
342 ((given & 0x00800000) == 0 ? "-" : ""),
343 offset * 4,
344 ((given & 0x00200000) != 0 ? "!" : ""));
345 else
346 func (stream, "]");
347 }
348 else
349 {
350 int offset = given & 0xff;
351 if (offset)
352 func (stream, "], %s#%d",
353 ((given & 0x00800000) == 0 ? "-" : ""),
354 offset * 4);
355 else
356 func (stream, "]");
357 }
358 break;
359
360 case 'C':
361 switch (given & 0x00090000)
362 {
363 default:
364 func (stream, "_???");
365 break;
366 case 0x90000:
367 func (stream, "_all");
368 break;
369 case 0x10000:
370 func (stream, "_ctl");
371 break;
372 case 0x80000:
373 func (stream, "_flg");
374 break;
375 }
376 break;
377
378 case 'F':
379 switch (given & 0x00408000)
380 {
381 case 0:
382 func (stream, "4");
383 break;
384 case 0x8000:
385 func (stream, "1");
386 break;
387 case 0x00400000:
388 func (stream, "2");
389 break;
390 default:
391 func (stream, "3");
392 }
393 break;
394
395 case 'P':
396 switch (given & 0x00080080)
397 {
398 case 0:
399 func (stream, "s");
400 break;
401 case 0x80:
402 func (stream, "d");
403 break;
404 case 0x00080000:
405 func (stream, "e");
406 break;
407 default:
408 func (stream, _("<illegal precision>"));
409 break;
410 }
411 break;
412 case 'Q':
413 switch (given & 0x00408000)
414 {
415 case 0:
416 func (stream, "s");
417 break;
418 case 0x8000:
419 func (stream, "d");
420 break;
421 case 0x00400000:
422 func (stream, "e");
423 break;
424 default:
425 func (stream, "p");
426 break;
427 }
428 break;
429 case 'R':
430 switch (given & 0x60)
431 {
432 case 0:
433 break;
434 case 0x20:
435 func (stream, "p");
436 break;
437 case 0x40:
438 func (stream, "m");
439 break;
440 default:
441 func (stream, "z");
442 break;
443 }
444 break;
445
446 case '0': case '1': case '2': case '3': case '4':
447 case '5': case '6': case '7': case '8': case '9':
448 {
449 int bitstart = *c++ - '0';
450 int bitend = 0;
451 while (*c >= '0' && *c <= '9')
452 bitstart = (bitstart * 10) + *c++ - '0';
453
454 switch (*c)
455 {
456 case '-':
457 c++;
458 while (*c >= '0' && *c <= '9')
459 bitend = (bitend * 10) + *c++ - '0';
460 if (!bitend)
461 abort ();
462 switch (*c)
463 {
464 case 'r':
465 {
466 long reg;
467 reg = given >> bitstart;
468 reg &= (2 << (bitend - bitstart)) - 1;
469 func (stream, "%s", arm_regnames[reg]);
470 }
471 break;
472 case 'd':
473 {
474 long reg;
475 reg = given >> bitstart;
476 reg &= (2 << (bitend - bitstart)) - 1;
477 func (stream, "%d", reg);
478 }
479 break;
480 case 'x':
481 {
482 long reg;
483 reg = given >> bitstart;
484 reg &= (2 << (bitend - bitstart)) - 1;
485 func (stream, "0x%08x", reg);
486
487 /* Some SWI instructions have special meanings. */
488 if ((given & 0x0fffffff) == 0x0FF00000)
489 func (stream, "\t; IMB");
490 else if ((given & 0x0fffffff) == 0x0FF00001)
491 func (stream, "\t; IMBRange");
492 }
493 break;
494 case 'f':
495 {
496 long reg;
497 reg = given >> bitstart;
498 reg &= (2 << (bitend - bitstart)) - 1;
499 if (reg > 7)
500 func (stream, "#%s",
501 arm_fp_const[reg & 7]);
502 else
503 func (stream, "f%d", reg);
504 }
505 break;
506 default:
507 abort ();
508 }
509 break;
510 case '`':
511 c++;
512 if ((given & (1 << bitstart)) == 0)
513 func (stream, "%c", *c);
514 break;
515 case '\'':
516 c++;
517 if ((given & (1 << bitstart)) != 0)
518 func (stream, "%c", *c);
519 break;
520 case '?':
521 ++c;
522 if ((given & (1 << bitstart)) != 0)
523 func (stream, "%c", *c++);
524 else
525 func (stream, "%c", *++c);
526 break;
527 default:
528 abort ();
529 }
530 break;
531
532 default:
533 abort ();
534 }
535 }
536 }
537 else
538 func (stream, "%c", *c);
539 }
540 return 4;
541 }
542 }
543 abort ();
544 }
545
546 /* Print one instruction from PC on INFO->STREAM.
547 Return the size of the instruction. */
548
549 static int
550 print_insn_thumb (pc, info, given)
551 bfd_vma pc;
552 struct disassemble_info * info;
553 long given;
554 {
555 struct thumb_opcode * insn;
556 void * stream = info->stream;
557 fprintf_ftype func = info->fprintf_func;
558
559 for (insn = thumb_opcodes; insn->assembler; insn++)
560 {
561 if ((given & insn->mask) == insn->value)
562 {
563 char * c = insn->assembler;
564
565 /* Special processing for Thumb 2 instruction BL sequence: */
566 if (!*c) /* check for empty (not NULL) assembler string */
567 {
568 info->bytes_per_chunk = 4;
569 info->bytes_per_line = 4;
570
571 func (stream, "%04x\tbl\t", given & 0xffff);
572 (*info->print_address_func)
573 (BDISP23 (given) * 2 + pc + 4, info);
574 return 4;
575 }
576 else
577 {
578 info->bytes_per_chunk = 2;
579 info->bytes_per_line = 4;
580
581 given &= 0xffff;
582 func (stream, "%04x\t", given);
583
584 for (; *c; c++)
585 {
586 if (*c == '%')
587 {
588 int domaskpc = 0;
589 int domasklr = 0;
590
591 switch (*++c)
592 {
593 case '%':
594 func (stream, "%%");
595 break;
596
597 case 'S':
598 {
599 long reg;
600 reg = (given >> 3) & 0x7;
601 if (given & (1 << 6))
602 reg += 8;
603 func (stream, "%s", arm_regnames[reg]);
604 }
605 break;
606
607 case 'D':
608 {
609 long reg;
610
611 reg = given & 0x7;
612 if (given & (1 << 7))
613 reg += 8;
614 func (stream, "%s", arm_regnames[reg]);
615 }
616 break;
617
618 case 'T':
619 func (stream, "%s",
620 arm_conditional [(given >> 8) & 0xf]);
621 break;
622
623 case 'N':
624 if (given & (1 << 8))
625 domasklr = 1;
626 /* fall through */
627 case 'O':
628 if (*c == 'O' && (given & (1 << 8)))
629 domaskpc = 1;
630 /* fall through */
631 case 'M':
632 {
633 int started = 0;
634 int reg;
635
636 func (stream, "{");
637 /* It would be nice if we could spot
638 ranges, and generate the rS-rE format: */
639 for (reg = 0; (reg < 8); reg++)
640 if ((given & (1 << reg)) != 0)
641 {
642 if (started)
643 func (stream, ", ");
644 started = 1;
645 func (stream, "%s", arm_regnames[reg]);
646 }
647
648 if (domasklr)
649 {
650 if (started)
651 func (stream, ", ");
652 started = 1;
653 func (stream, "lr");
654 }
655
656 if (domaskpc)
657 {
658 if (started)
659 func (stream, ", ");
660 func (stream, "pc");
661 }
662
663 func (stream, "}");
664 }
665 break;
666
667
668 case '0': case '1': case '2': case '3': case '4':
669 case '5': case '6': case '7': case '8': case '9':
670 {
671 int bitstart = *c++ - '0';
672 int bitend = 0;
673
674 while (*c >= '0' && *c <= '9')
675 bitstart = (bitstart * 10) + *c++ - '0';
676
677 switch (*c)
678 {
679 case '-':
680 {
681 long reg;
682
683 c++;
684 while (*c >= '0' && *c <= '9')
685 bitend = (bitend * 10) + *c++ - '0';
686 if (!bitend)
687 abort ();
688 reg = given >> bitstart;
689 reg &= (2 << (bitend - bitstart)) - 1;
690 switch (*c)
691 {
692 case 'r':
693 func (stream, "%s", arm_regnames[reg]);
694 break;
695
696 case 'd':
697 func (stream, "%d", reg);
698 break;
699
700 case 'H':
701 func (stream, "%d", reg << 1);
702 break;
703
704 case 'W':
705 func (stream, "%d", reg << 2);
706 break;
707
708 case 'a':
709 /* PC-relative address -- the bottom two
710 bits of the address are dropped before
711 the calculation. */
712 info->print_address_func
713 (((pc + 4) & ~3) + (reg << 2), info);
714 break;
715
716 case 'x':
717 func (stream, "0x%04x", reg);
718 break;
719
720 case 'I':
721 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
722 func (stream, "%d", reg);
723 break;
724
725 case 'B':
726 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
727 (*info->print_address_func)
728 (reg * 2 + pc + 4, info);
729 break;
730
731 default:
732 abort ();
733 }
734 }
735 break;
736
737 case '\'':
738 c++;
739 if ((given & (1 << bitstart)) != 0)
740 func (stream, "%c", *c);
741 break;
742
743 case '?':
744 ++c;
745 if ((given & (1 << bitstart)) != 0)
746 func (stream, "%c", *c++);
747 else
748 func (stream, "%c", *++c);
749 break;
750
751 default:
752 abort ();
753 }
754 }
755 break;
756
757 default:
758 abort ();
759 }
760 }
761 else
762 func (stream, "%c", *c);
763 }
764 }
765 return 2;
766 }
767 }
768
769 /* no match */
770 abort ();
771 }
772
773 /* Select a different register name set.
774 Returns true if the name set selected is the APCS name set. */
775 int
776 arm_toggle_regnames ()
777 {
778 if (arm_regnames == arm_regnames_standard)
779 arm_regnames = arm_regnames_apcs;
780 else
781 arm_regnames = arm_regnames_standard;
782
783 return arm_regnames == arm_regnames_apcs;
784 }
785
786 static void
787 parse_disassembler_options (options)
788 char * options;
789 {
790 if (options == NULL)
791 return;
792
793 if (strncmp (options, "reg-names-", 10) == 0)
794 {
795 options += 10;
796
797 if (strcmp (options, "std") == 0)
798 arm_regnames = arm_regnames_standard;
799 else if (strcmp (options, "apcs") == 0)
800 arm_regnames = arm_regnames_apcs;
801 else if (strcmp (options, "raw") == 0)
802 arm_regnames = arm_regnames_raw;
803 else
804 fprintf (stderr, "Unrecognised register name set: %s\n", options);
805 }
806 else
807 fprintf (stderr, "Unrecognised disassembler option: %s\n", options);
808
809 return;
810 }
811
812 /* NOTE: There are no checks in these routines that the relevant number of data bytes exist */
813
814 int
815 print_insn_big_arm (pc, info)
816 bfd_vma pc;
817 struct disassemble_info * info;
818 {
819 unsigned char b[4];
820 long given;
821 int status;
822 coff_symbol_type * cs;
823 elf_symbol_type * es;
824 int is_thumb;
825
826 if (info->disassembler_options)
827 {
828 parse_disassembler_options (info->disassembler_options);
829
830 /* To avoid repeated parsing of this option, we remove it here. */
831 info->disassembler_options = NULL;
832 }
833
834 is_thumb = false;
835 if (info->symbols != NULL)
836 {
837 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
838 {
839 cs = coffsymbol (*info->symbols);
840 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
841 || cs->native->u.syment.n_sclass == C_THUMBSTAT
842 || cs->native->u.syment.n_sclass == C_THUMBLABEL
843 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
844 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
845 }
846 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
847 {
848 es = *(elf_symbol_type **)(info->symbols);
849 is_thumb = ELF_ST_TYPE (es->internal_elf_sym.st_info) ==
850 STT_ARM_TFUNC;
851 }
852 }
853
854 info->bytes_per_chunk = 4;
855 info->display_endian = BFD_ENDIAN_BIG;
856
857 /* Always fetch word aligned values. */
858
859 status = (*info->read_memory_func) (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info);
860 if (status != 0)
861 {
862 (*info->memory_error_func) (status, pc, info);
863 return -1;
864 }
865
866 if (is_thumb)
867 {
868 if (pc & 0x2)
869 {
870 given = (b[2] << 8) | b[3];
871
872 status = info->read_memory_func ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
873 if (status != 0)
874 {
875 info->memory_error_func (status, pc + 4, info);
876 return -1;
877 }
878
879 given |= (b[0] << 24) | (b[1] << 16);
880 }
881 else
882 given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16);
883 }
884 else
885 given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
886
887 if (is_thumb)
888 status = print_insn_thumb (pc, info, given);
889 else
890 status = print_insn_arm (pc, info, given);
891
892 return status;
893 }
894
895 int
896 print_insn_little_arm (pc, info)
897 bfd_vma pc;
898 struct disassemble_info * info;
899 {
900 unsigned char b[4];
901 long given;
902 int status;
903 coff_symbol_type * cs;
904 elf_symbol_type * es;
905 int is_thumb;
906
907 if (info->disassembler_options)
908 {
909 parse_disassembler_options (info->disassembler_options);
910
911 /* To avoid repeated parsing of this option, we remove it here. */
912 info->disassembler_options = NULL;
913 }
914
915 is_thumb = false;
916
917 if (info->symbols != NULL)
918 {
919 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
920 {
921 cs = coffsymbol (*info->symbols);
922 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
923 || cs->native->u.syment.n_sclass == C_THUMBSTAT
924 || cs->native->u.syment.n_sclass == C_THUMBLABEL
925 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
926 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
927 }
928 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
929 {
930 es = *(elf_symbol_type **)(info->symbols);
931 is_thumb = ELF_ST_TYPE (es->internal_elf_sym.st_info) ==
932 STT_ARM_TFUNC;
933 }
934 }
935
936 info->bytes_per_chunk = 4;
937 info->display_endian = BFD_ENDIAN_LITTLE;
938
939 status = (*info->read_memory_func) (pc, (bfd_byte *) &b[0], 4, info);
940 if (status != 0 && is_thumb)
941 {
942 info->bytes_per_chunk = 2;
943
944 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
945 b[3] = b[2] = 0;
946 }
947 if (status != 0)
948 {
949 (*info->memory_error_func) (status, pc, info);
950 return -1;
951 }
952
953 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
954
955 if (is_thumb)
956 status = print_insn_thumb (pc, info, given);
957 else
958 status = print_insn_arm (pc, info, given);
959
960 return status;
961 }
This page took 0.062602 seconds and 5 git commands to generate.