1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* FIXME: Belongs in global header. */
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
47 /* Cached mapping symbol state. */
55 struct arm_private_data
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features
;
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type
;
63 /* Tracking symbol table information */
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset
;
68 bfd_vma last_mapping_addr
;
121 MVE_VSTRB_SCATTER_T1
,
122 MVE_VSTRH_SCATTER_T2
,
123 MVE_VSTRW_SCATTER_T3
,
124 MVE_VSTRD_SCATTER_T4
,
125 MVE_VSTRW_SCATTER_T5
,
126 MVE_VSTRD_SCATTER_T6
,
128 MVE_VCVT_BETWEEN_FP_INT
,
130 MVE_VCVT_FROM_FP_TO_INT
,
133 MVE_VMOV_GP_TO_VEC_LANE
,
136 MVE_VMOV2_VEC_LANE_TO_GP
,
137 MVE_VMOV2_GP_TO_VEC_LANE
,
138 MVE_VMOV_VEC_LANE_TO_GP
,
190 enum mve_unpredictable
192 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
194 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
196 UNPRED_R13
, /* Unpredictable because r13 (sp) or
198 UNPRED_R15
, /* Unpredictable because r15 (pc) is used. */
199 UNPRED_Q_GT_4
, /* Unpredictable because
200 vec reg start > 4 (vld4/st4). */
201 UNPRED_Q_GT_6
, /* Unpredictable because
202 vec reg start > 6 (vld2/st2). */
203 UNPRED_R13_AND_WB
, /* Unpredictable becase gp reg = r13
205 UNPRED_Q_REGS_EQUAL
, /* Unpredictable because vector registers are
207 UNPRED_OS
, /* Unpredictable because offset scaled == 1. */
208 UNPRED_GP_REGS_EQUAL
, /* Unpredictable because gp registers are the
210 UNPRED_Q_REGS_EQ_AND_SIZE_1
, /* Unpredictable because q regs equal and
212 UNPRED_Q_REGS_EQ_AND_SIZE_2
, /* Unpredictable because q regs equal and
214 UNPRED_NONE
/* No unpredictable behavior. */
219 UNDEF_SIZE_0
, /* undefined because size == 0. */
220 UNDEF_SIZE_2
, /* undefined because size == 2. */
221 UNDEF_SIZE_3
, /* undefined because size == 3. */
222 UNDEF_SIZE_LE_1
, /* undefined because size <= 1. */
223 UNDEF_SIZE_NOT_2
, /* undefined because size != 2. */
224 UNDEF_SIZE_NOT_3
, /* undefined because size != 3. */
225 UNDEF_NOT_UNS_SIZE_0
, /* undefined because U == 0 and
227 UNDEF_NOT_UNS_SIZE_1
, /* undefined because U == 0 and
229 UNDEF_NOT_UNSIGNED
, /* undefined because U == 0. */
230 UNDEF_VCVT_IMM6
, /* imm6 < 32. */
231 UNDEF_VCVT_FSI_IMM6
, /* fsi = 0 and 32 >= imm6 <= 47. */
232 UNDEF_BAD_OP1_OP2
, /* undefined with op2 = 2 and
234 UNDEF_BAD_U_OP1_OP2
, /* undefined with U = 1 and
235 op2 == 0 and op1 == (0 or 1). */
236 UNDEF_OP_0_BAD_CMODE
, /* undefined because op == 0 and cmode
238 UNDEF_XCHG_UNS
, /* undefined because X == 1 and U == 1. */
239 UNDEF_NONE
/* no undefined behavior. */
244 arm_feature_set arch
; /* Architecture defining this insn. */
245 unsigned long value
; /* If arch is 0 then value is a sentinel. */
246 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
247 const char * assembler
; /* How to disassemble this insn. */
254 arm_feature_set arch
; /* Architecture defining this insn. */
255 enum mve_instructions mve_op
; /* Specific mve instruction for faster
257 unsigned long value
; /* If arch is 0 then value is a sentinel. */
258 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
259 const char * assembler
; /* How to disassemble this insn. */
269 /* Shared (between Arm and Thumb mode) opcode. */
272 enum isa isa
; /* Execution mode instruction availability. */
273 arm_feature_set arch
; /* Architecture defining this insn. */
274 unsigned long value
; /* If arch is 0 then value is a sentinel. */
275 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
276 const char * assembler
; /* How to disassemble this insn. */
281 arm_feature_set arch
; /* Architecture defining this insn. */
282 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
283 const char *assembler
; /* How to disassemble this insn. */
286 /* print_insn_coprocessor recognizes the following format control codes:
290 %c print condition code (always bits 28-31 in ARM mode)
291 %q print shifter argument
292 %u print condition code (unconditional in ARM mode,
293 UNPREDICTABLE if not AL in Thumb)
294 %A print address for ldc/stc/ldf/stf instruction
295 %B print vstm/vldm register list
296 %C print vscclrm register list
297 %I print cirrus signed shift immediate: bits 0..3|4..6
298 %J print register for VLDR instruction
299 %K print address for VLDR instruction
300 %F print the COUNT field of a LFM/SFM instruction.
301 %P print floating point precision in arithmetic insn
302 %Q print floating point precision in ldf/stf insn
303 %R print floating point rounding mode
305 %<bitfield>c print as a condition code (for vsel)
306 %<bitfield>r print as an ARM register
307 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
308 %<bitfield>ru as %<>r but each u register must be unique.
309 %<bitfield>d print the bitfield in decimal
310 %<bitfield>k print immediate for VFPv3 conversion instruction
311 %<bitfield>x print the bitfield in hex
312 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
313 %<bitfield>f print a floating point constant if >7 else a
314 floating point register
315 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
316 %<bitfield>g print as an iWMMXt 64-bit register
317 %<bitfield>G print as an iWMMXt general purpose or control register
318 %<bitfield>D print as a NEON D register
319 %<bitfield>Q print as a NEON Q register
320 %<bitfield>V print as a NEON D or Q register
321 %<bitfield>E print a quarter-float immediate value
323 %y<code> print a single precision VFP reg.
324 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
325 %z<code> print a double precision VFP reg
326 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
328 %<bitfield>'c print specified char iff bitfield is all ones
329 %<bitfield>`c print specified char iff bitfield is all zeroes
330 %<bitfield>?ab... select from array of values in big endian order
332 %L print as an iWMMXt N/M width field.
333 %Z print the Immediate of a WSHUFH instruction.
334 %l like 'A' except use byte offsets for 'B' & 'H'
336 %i print 5-bit immediate in bits 8,3..0
338 %r print register offset address for wldt/wstr instruction. */
340 enum opcode_sentinel_enum
342 SENTINEL_IWMMXT_START
= 1,
344 SENTINEL_GENERIC_START
347 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
348 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
349 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
350 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
352 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
354 static const struct sopcode32 coprocessor_opcodes
[] =
356 /* XScale instructions. */
357 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
358 0x0e200010, 0x0fff0ff0,
359 "mia%c\tacc0, %0-3r, %12-15r"},
360 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
361 0x0e280010, 0x0fff0ff0,
362 "miaph%c\tacc0, %0-3r, %12-15r"},
363 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
364 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
365 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
366 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
367 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
368 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
370 /* Intel Wireless MMX technology instructions. */
371 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
372 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
373 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
374 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
375 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
376 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
377 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
378 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
379 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
380 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
381 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
382 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
383 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
384 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
385 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
386 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
387 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
388 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
389 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
390 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
391 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
392 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
393 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
394 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
395 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
396 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
397 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
398 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
399 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
400 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
401 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
402 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
403 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
404 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
405 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
406 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
407 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
408 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
409 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
410 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
411 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
412 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
413 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
414 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
415 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
416 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
417 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
418 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
419 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
420 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
421 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
422 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
423 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
424 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
425 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
426 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
427 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
428 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
429 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
430 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
431 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
432 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
433 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
434 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
435 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
436 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
437 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
438 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
439 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
440 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
441 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
442 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
443 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
444 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
445 0x0e800120, 0x0f800ff0,
446 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
447 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
448 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
449 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
450 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
451 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
452 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
453 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
454 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
455 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
456 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
457 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
458 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
459 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
460 0x0e8000a0, 0x0f800ff0,
461 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
462 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
463 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
464 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
465 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
466 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
467 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
468 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
469 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
470 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
471 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
472 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
473 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
474 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
475 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
476 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
477 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
478 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
479 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
480 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
481 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
482 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
483 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
484 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
485 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
486 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
487 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
488 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
489 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
490 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
491 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
492 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
493 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
494 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
495 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
496 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
497 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
498 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
499 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
500 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
501 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
502 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
503 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
504 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
505 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
506 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
507 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
508 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
509 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
510 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
511 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
512 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
513 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
514 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
515 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
516 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
517 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
518 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
519 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
520 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
521 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
522 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
523 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
524 {ANY
, ARM_FEATURE_CORE_LOW (0),
525 SENTINEL_IWMMXT_END
, 0, "" },
527 /* Floating point coprocessor (FPA) instructions. */
528 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
529 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
530 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
531 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
532 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
533 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
534 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
535 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
536 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
537 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
538 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
539 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
540 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
541 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
542 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
543 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
544 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
545 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
546 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
547 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
548 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
549 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
550 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
551 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
552 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
553 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
554 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
555 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
556 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
557 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
558 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
559 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
560 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
561 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
562 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
563 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
564 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
565 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
566 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
567 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
568 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
569 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
570 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
571 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
572 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
573 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
574 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
575 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
576 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
577 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
578 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
579 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
580 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
581 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
582 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
583 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
584 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
585 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
586 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
587 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
588 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
589 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
590 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
591 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
592 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
593 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
594 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
595 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
596 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
597 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
598 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
599 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
600 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
601 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
602 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
603 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
604 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
605 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
606 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
607 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
608 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
609 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
610 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
611 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
612 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
613 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
615 /* Armv8.1-M Mainline instructions. */
616 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
617 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
618 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
619 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
621 /* ARMv8-M Mainline Security Extensions instructions. */
622 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
623 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
624 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
625 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
627 /* Register load/store. */
628 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
629 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
630 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
631 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
632 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
633 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
634 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
635 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
636 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
637 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
638 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
639 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
640 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
641 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
642 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
643 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
644 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
645 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
646 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
647 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
648 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
649 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
650 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
651 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
652 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
653 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
654 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
655 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
656 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
657 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
658 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
659 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
660 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
661 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
662 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
663 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
665 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
666 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
667 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
668 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
669 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
670 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
671 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
672 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
674 /* Data transfer between ARM and NEON registers. */
675 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
676 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
677 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
678 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
679 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
680 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
681 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
682 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
683 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
684 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
685 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
686 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
687 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
688 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
689 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
690 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
691 /* Half-precision conversion instructions. */
692 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
693 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
694 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
695 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
696 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
697 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
698 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
699 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
701 /* Floating point coprocessor (VFP) instructions. */
702 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
703 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
704 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
705 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
706 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
707 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
708 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
709 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
710 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
711 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
712 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
713 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
714 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
715 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
716 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
717 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
718 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
719 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
720 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
721 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
722 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
723 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
724 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
725 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
726 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
727 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
728 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
729 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
730 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
731 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
732 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
733 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
734 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
735 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
736 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
737 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
738 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
739 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
740 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
741 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
742 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
743 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
744 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
745 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
746 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
747 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
748 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
749 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
750 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
751 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
752 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
753 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
754 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
755 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
756 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
757 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
758 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
759 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
760 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
761 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
762 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
763 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
764 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
765 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
766 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
767 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
768 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
769 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
770 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
771 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
772 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
773 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
774 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
775 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
776 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
777 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
778 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
779 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
780 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
781 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
782 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
783 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
784 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
785 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
786 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
787 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
788 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
789 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
790 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
791 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
792 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
793 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
794 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
795 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
796 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
797 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
798 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
799 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
800 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
801 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
802 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
803 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
804 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
805 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
806 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
807 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
808 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
809 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
810 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
811 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
812 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
813 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
814 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
815 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
816 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
817 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
818 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
819 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
820 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
821 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
822 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
823 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
824 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
825 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
826 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
827 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
828 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
829 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
830 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
831 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
832 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
833 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
834 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
835 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
836 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
837 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
838 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
839 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
841 /* Cirrus coprocessor instructions. */
842 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
843 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
844 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
845 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
846 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
847 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
848 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
849 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
850 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
851 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
852 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
853 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
854 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
855 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
856 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
857 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
858 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
859 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
860 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
861 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
862 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
863 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
864 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
865 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
866 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
867 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
868 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
869 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
870 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
871 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
872 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
873 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
874 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
875 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
876 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
877 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
878 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
879 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
880 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
881 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
882 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
883 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
884 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
885 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
886 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
887 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
888 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
889 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
890 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
891 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
892 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
893 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
894 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
895 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
896 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
897 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
898 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
899 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
900 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
901 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
902 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
903 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
904 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
905 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
906 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
907 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
908 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
909 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
910 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
911 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
912 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
913 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
914 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
915 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
916 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
917 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
918 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
919 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
920 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
921 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
922 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
923 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
924 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
925 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
926 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
927 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
928 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
929 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
930 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
931 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
932 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
933 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
934 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
935 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
936 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
937 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
938 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
939 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
940 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
941 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
942 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
943 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
944 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
945 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
946 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
947 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
948 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
949 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
950 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
951 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
952 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
953 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
954 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
955 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
956 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
957 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
958 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
959 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
960 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
961 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
962 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
963 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
964 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
965 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
966 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
967 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
968 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
969 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
970 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
971 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
972 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
973 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
974 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
975 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
976 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
977 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
978 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
979 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
980 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
981 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
982 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
983 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
984 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
985 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
986 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
987 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
988 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
989 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
990 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
991 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
992 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
993 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
994 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
995 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
996 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
997 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
998 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
999 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1000 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1001 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1002 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1003 0x0e000600, 0x0ff00f10,
1004 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1005 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1006 0x0e100600, 0x0ff00f10,
1007 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1008 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1009 0x0e200600, 0x0ff00f10,
1010 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1011 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1012 0x0e300600, 0x0ff00f10,
1013 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1015 /* VFP Fused multiply add instructions. */
1016 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1017 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1018 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1019 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1020 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1021 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1022 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1023 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1024 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1025 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1026 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1027 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1028 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1029 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1030 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1031 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1034 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1035 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1036 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1037 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1038 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1039 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1040 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1041 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1042 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1043 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1044 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1045 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1046 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1047 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1048 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1049 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1050 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1051 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1052 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1053 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1054 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1055 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1056 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1057 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1059 /* Generic coprocessor instructions. */
1060 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
1061 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1062 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1063 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1064 0x0c500000, 0x0ff00000,
1065 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1066 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1067 0x0e000000, 0x0f000010,
1068 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1069 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1070 0x0e10f010, 0x0f10f010,
1071 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1072 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1073 0x0e100010, 0x0f100010,
1074 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1075 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1076 0x0e000010, 0x0f100010,
1077 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1078 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1079 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1080 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1081 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1083 /* V6 coprocessor instructions. */
1084 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1085 0xfc500000, 0xfff00000,
1086 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1087 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1088 0xfc400000, 0xfff00000,
1089 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1091 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1092 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1093 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1094 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1095 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1096 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1097 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1098 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1099 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1100 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1101 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1102 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1103 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1104 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1105 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1106 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1107 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1108 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1109 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1110 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1111 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1113 /* Dot Product instructions in the space of coprocessor 13. */
1114 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1115 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1116 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1117 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1119 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1120 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1121 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1122 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1123 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1124 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1125 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1126 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1127 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1128 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1129 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1130 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1131 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1132 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1133 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1134 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1135 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1137 /* V5 coprocessor instructions. */
1138 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1139 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1140 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1141 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1142 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1143 0xfe000000, 0xff000010,
1144 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1145 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1146 0xfe000010, 0xff100010,
1147 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1148 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1149 0xfe100010, 0xff100010,
1150 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1152 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1153 cp_num: bit <11:8> == 0b1001.
1154 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1155 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1156 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1157 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1158 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1159 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1160 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1161 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1162 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1163 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1164 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1165 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1166 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1167 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1168 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1169 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1170 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1171 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1172 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1173 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1174 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1175 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1176 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1177 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1178 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1179 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1180 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1181 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1182 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1183 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1184 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1185 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1186 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1187 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1188 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1189 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1190 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1191 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1192 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1193 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1194 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1195 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1196 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1197 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1198 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1199 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1200 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1201 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1202 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1203 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1204 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1205 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1206 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1207 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1208 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1209 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1210 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1211 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1212 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1213 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1214 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1215 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1216 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1217 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1218 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1219 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1220 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1221 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1222 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1223 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1224 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1226 /* ARMv8.3 javascript conversion instruction. */
1227 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1228 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1230 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1233 /* Neon opcode table: This does not encode the top byte -- that is
1234 checked by the print_insn_neon routine, as it depends on whether we are
1235 doing thumb32 or arm32 disassembly. */
1237 /* print_insn_neon recognizes the following format control codes:
1241 %c print condition code
1242 %u print condition code (unconditional in ARM mode,
1243 UNPREDICTABLE if not AL in Thumb)
1244 %A print v{st,ld}[1234] operands
1245 %B print v{st,ld}[1234] any one operands
1246 %C print v{st,ld}[1234] single->all operands
1248 %E print vmov, vmvn, vorr, vbic encoded constant
1249 %F print vtbl,vtbx register list
1251 %<bitfield>r print as an ARM register
1252 %<bitfield>d print the bitfield in decimal
1253 %<bitfield>e print the 2^N - bitfield in decimal
1254 %<bitfield>D print as a NEON D register
1255 %<bitfield>Q print as a NEON Q register
1256 %<bitfield>R print as a NEON D or Q register
1257 %<bitfield>Sn print byte scaled width limited by n
1258 %<bitfield>Tn print short scaled width limited by n
1259 %<bitfield>Un print long scaled width limited by n
1261 %<bitfield>'c print specified char iff bitfield is all ones
1262 %<bitfield>`c print specified char iff bitfield is all zeroes
1263 %<bitfield>?ab... select from array of values in big endian order. */
1265 static const struct opcode32 neon_opcodes
[] =
1268 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1269 0xf2b00840, 0xffb00850,
1270 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1272 0xf2b00000, 0xffb00810,
1273 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1275 /* Data transfer between ARM and NEON registers. */
1276 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1277 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1278 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1279 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1280 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1281 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1282 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1283 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1284 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1285 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1287 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1289 /* Move data element to all lanes. */
1290 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1291 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1292 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1293 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1294 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1295 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1299 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1300 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1301 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1303 /* Half-precision conversions. */
1304 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1305 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1306 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1307 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1309 /* NEON fused multiply add instructions. */
1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1311 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1312 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1313 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1314 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1315 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1316 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1317 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319 /* Two registers, miscellaneous. */
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1321 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1322 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1323 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1325 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1327 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1328 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1329 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1330 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1331 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1332 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1333 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1334 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1335 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1336 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1337 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1338 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1339 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1340 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1341 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1343 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1345 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1347 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1349 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1351 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1353 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1354 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1355 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1357 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1359 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1361 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1363 0xf3b20300, 0xffb30fd0,
1364 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1366 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1367 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1368 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1369 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1370 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1371 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1372 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1374 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1376 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1378 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1380 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1382 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1384 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1386 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1388 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1390 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1392 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1394 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1395 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1396 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1398 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1400 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1401 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1402 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1404 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1406 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1408 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1410 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1412 0xf3bb0600, 0xffbf0e10,
1413 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1415 0xf3b70600, 0xffbf0e10,
1416 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1418 /* Three registers of the same length. */
1419 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1420 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1421 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1422 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1423 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1424 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1425 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1426 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1427 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1428 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1429 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1430 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1431 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1432 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1434 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1435 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1436 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1438 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1440 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1442 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1444 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1446 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1448 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1450 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1452 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1454 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1456 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1458 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1460 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1462 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1464 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1466 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1467 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1468 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1470 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1471 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1472 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1474 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1476 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1478 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1480 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1482 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1484 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1486 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1488 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1490 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1491 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1492 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1494 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1496 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1498 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1500 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1502 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1503 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1504 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1506 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1507 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1508 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1510 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1512 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1514 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1516 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1518 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1520 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1522 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1524 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1526 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1528 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1530 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1532 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1534 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1536 0xf2000b00, 0xff800f10,
1537 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1539 0xf2000b10, 0xff800f10,
1540 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1542 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1543 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1544 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1546 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1548 0xf3000b00, 0xff800f10,
1549 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1551 0xf2000000, 0xfe800f10,
1552 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1554 0xf2000010, 0xfe800f10,
1555 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1557 0xf2000100, 0xfe800f10,
1558 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1560 0xf2000200, 0xfe800f10,
1561 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1563 0xf2000210, 0xfe800f10,
1564 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1566 0xf2000300, 0xfe800f10,
1567 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1569 0xf2000310, 0xfe800f10,
1570 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1572 0xf2000400, 0xfe800f10,
1573 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1575 0xf2000410, 0xfe800f10,
1576 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1578 0xf2000500, 0xfe800f10,
1579 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1581 0xf2000510, 0xfe800f10,
1582 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1584 0xf2000600, 0xfe800f10,
1585 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1587 0xf2000610, 0xfe800f10,
1588 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1590 0xf2000700, 0xfe800f10,
1591 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1593 0xf2000710, 0xfe800f10,
1594 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1596 0xf2000910, 0xfe800f10,
1597 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1599 0xf2000a00, 0xfe800f10,
1600 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1602 0xf2000a10, 0xfe800f10,
1603 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1605 0xf3000b10, 0xff800f10,
1606 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1608 0xf3000c10, 0xff800f10,
1609 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1611 /* One register and an immediate value. */
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1613 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1615 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1617 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1619 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1621 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1623 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1625 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1627 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1629 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1631 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1633 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1635 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1637 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1639 /* Two registers and a shift amount. */
1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1641 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1643 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1645 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1647 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1649 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1651 0xf2880950, 0xfeb80fd0,
1652 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1654 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1656 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1658 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1660 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1662 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1664 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1666 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1668 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1670 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1672 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1674 0xf2900950, 0xfeb00fd0,
1675 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1677 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1679 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1681 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1683 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1685 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1687 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1689 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1691 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1693 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1695 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1697 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1699 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1701 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1703 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1705 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1706 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1707 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1709 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1711 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1713 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1715 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1717 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1719 0xf2a00950, 0xfea00fd0,
1720 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1722 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1724 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1726 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1727 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1728 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1730 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1732 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1733 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1734 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1736 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1738 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1739 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1740 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1742 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1744 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1745 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1746 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1747 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1748 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1750 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1751 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1752 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1753 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1754 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1755 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1756 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1757 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1758 0xf2a00e10, 0xfea00e90,
1759 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1760 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1761 0xf2a00c10, 0xfea00e90,
1762 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1764 /* Three registers of different lengths. */
1765 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1766 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1768 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1770 0xf2800400, 0xff800f50,
1771 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1773 0xf2800600, 0xff800f50,
1774 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1775 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1776 0xf2800900, 0xff800f50,
1777 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1779 0xf2800b00, 0xff800f50,
1780 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1782 0xf2800d00, 0xff800f50,
1783 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1785 0xf3800400, 0xff800f50,
1786 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1788 0xf3800600, 0xff800f50,
1789 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1791 0xf2800000, 0xfe800f50,
1792 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1794 0xf2800100, 0xfe800f50,
1795 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1797 0xf2800200, 0xfe800f50,
1798 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1800 0xf2800300, 0xfe800f50,
1801 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1803 0xf2800500, 0xfe800f50,
1804 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1806 0xf2800700, 0xfe800f50,
1807 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1809 0xf2800800, 0xfe800f50,
1810 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1812 0xf2800a00, 0xfe800f50,
1813 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1815 0xf2800c00, 0xfe800f50,
1816 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1818 /* Two registers and a scalar. */
1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1820 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1821 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1822 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1823 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1824 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1825 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1826 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1827 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1828 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1830 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1831 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1832 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1833 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1834 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1836 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1837 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1838 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1839 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1840 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1842 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1844 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1845 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1846 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1848 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1850 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1851 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1852 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1854 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1856 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1857 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1858 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1860 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1862 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1863 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1864 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1866 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1868 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1870 0xf2800240, 0xfe800f50,
1871 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1873 0xf2800640, 0xfe800f50,
1874 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1876 0xf2800a40, 0xfe800f50,
1877 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1879 0xf2800e40, 0xff800f50,
1880 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1882 0xf2800f40, 0xff800f50,
1883 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1885 0xf3800e40, 0xff800f50,
1886 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1888 0xf3800f40, 0xff800f50,
1889 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1892 /* Element and structure load/store. */
1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1894 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1895 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1896 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1897 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1898 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1899 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1900 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1901 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1902 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1904 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1905 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1906 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1907 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1908 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1910 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1911 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1912 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1913 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1914 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1916 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1917 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1918 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1920 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1922 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1924 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1925 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1926 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1928 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1930 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1932 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1935 /* mve opcode table. */
1937 /* print_insn_mve recognizes the following format control codes:
1941 %a print '+' or '-' or imm offset in vldr[bhwd] and
1943 %c print condition code
1944 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1945 %u print 'U' (unsigned) or 'S' for various mve instructions
1946 %i print MVE predicate(s) for vpt and vpst
1947 %m print rounding mode for vcvt and vrint
1948 %n print vector comparison code for predicated instruction
1949 %s print size for various vcvt instructions
1950 %v print vector predicate for instruction in predicated
1952 %o print offset scaled for vldr[hwd] and vstr[hwd]
1953 %w print writeback mode for MVE v{st,ld}[24]
1954 %B print v{st,ld}[24] any one operands
1955 %E print vmov, vmvn, vorr, vbic encoded constant
1956 %N print generic index for vmov
1957 %T print bottom ('b') or top ('t') of source register
1958 %X print exchange field in vmla* instructions
1960 %<bitfield>r print as an ARM register
1961 %<bitfield>d print the bitfield in decimal
1962 %<bitfield>A print accumulate or not
1963 %<bitfield>Q print as a MVE Q register
1964 %<bitfield>F print as a MVE S register
1965 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1967 %<bitfield>s print size for vector predicate & non VMOV instructions
1968 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1969 %<bitfield>h print high half of 64-bit destination reg
1970 %<bitfield>k print immediate for vector conversion instruction
1971 %<bitfield>l print low half of 64-bit destination reg
1972 %<bitfield>o print rotate value for vcmul
1973 %<bitfield>u print immediate value for vddup/vdwdup
1974 %<bitfield>x print the bitfield in hex.
1977 static const struct mopcode32 mve_opcodes
[] =
1981 {ARM_FEATURE_COPROC (FPU_MVE
),
1983 0xfe310f4d, 0xffbf1fff,
1987 /* Floating point VPT T1. */
1988 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1990 0xee310f00, 0xefb10f50,
1991 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1992 /* Floating point VPT T2. */
1993 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1995 0xee310f40, 0xefb10f50,
1996 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1998 /* Vector VPT T1. */
1999 {ARM_FEATURE_COPROC (FPU_MVE
),
2001 0xfe010f00, 0xff811f51,
2002 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2003 /* Vector VPT T2. */
2004 {ARM_FEATURE_COPROC (FPU_MVE
),
2006 0xfe010f01, 0xff811f51,
2007 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2008 /* Vector VPT T3. */
2009 {ARM_FEATURE_COPROC (FPU_MVE
),
2011 0xfe011f00, 0xff811f50,
2012 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2013 /* Vector VPT T4. */
2014 {ARM_FEATURE_COPROC (FPU_MVE
),
2016 0xfe010f40, 0xff811f70,
2017 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2018 /* Vector VPT T5. */
2019 {ARM_FEATURE_COPROC (FPU_MVE
),
2021 0xfe010f60, 0xff811f70,
2022 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2023 /* Vector VPT T6. */
2024 {ARM_FEATURE_COPROC (FPU_MVE
),
2026 0xfe011f40, 0xff811f50,
2027 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2029 /* Vector VBIC immediate. */
2030 {ARM_FEATURE_COPROC (FPU_MVE
),
2032 0xef800070, 0xefb81070,
2033 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2035 /* Vector VBIC register. */
2036 {ARM_FEATURE_COPROC (FPU_MVE
),
2038 0xef100150, 0xffb11f51,
2039 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2041 /* Vector VADDLV. */
2042 {ARM_FEATURE_COPROC (FPU_MVE
),
2044 0xee890f00, 0xef8f1fd1,
2045 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2048 {ARM_FEATURE_COPROC (FPU_MVE
),
2050 0xeef10f00, 0xeff31fd1,
2051 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2053 /* Vector VCADD floating point. */
2054 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2056 0xfc800840, 0xfea11f51,
2057 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2060 {ARM_FEATURE_COPROC (FPU_MVE
),
2062 0xfe000f00, 0xff810f51,
2063 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2066 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2068 0xfc200840, 0xfe211f51,
2069 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2071 /* Vector VCMP floating point T1. */
2072 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2074 0xee310f00, 0xeff1ef50,
2075 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2077 /* Vector VCMP floating point T2. */
2078 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2080 0xee310f40, 0xeff1ef50,
2081 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2083 /* Vector VCMP T1. */
2084 {ARM_FEATURE_COPROC (FPU_MVE
),
2086 0xfe010f00, 0xffc1ff51,
2087 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2088 /* Vector VCMP T2. */
2089 {ARM_FEATURE_COPROC (FPU_MVE
),
2091 0xfe010f01, 0xffc1ff51,
2092 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2093 /* Vector VCMP T3. */
2094 {ARM_FEATURE_COPROC (FPU_MVE
),
2096 0xfe011f00, 0xffc1ff50,
2097 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2098 /* Vector VCMP T4. */
2099 {ARM_FEATURE_COPROC (FPU_MVE
),
2101 0xfe010f40, 0xffc1ff70,
2102 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2103 /* Vector VCMP T5. */
2104 {ARM_FEATURE_COPROC (FPU_MVE
),
2106 0xfe010f60, 0xffc1ff70,
2107 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2108 /* Vector VCMP T6. */
2109 {ARM_FEATURE_COPROC (FPU_MVE
),
2111 0xfe011f40, 0xffc1ff50,
2112 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2115 {ARM_FEATURE_COPROC (FPU_MVE
),
2117 0xeea00b10, 0xffb10f5f,
2118 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2121 {ARM_FEATURE_COPROC (FPU_MVE
),
2123 0xff000150, 0xffd11f51,
2124 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2126 /* Vector VFMA, vector * scalar. */
2127 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2129 0xee310e40, 0xefb11f70,
2130 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2132 /* Vector VFMA floating point. */
2133 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2135 0xef000c50, 0xffa11f51,
2136 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2138 /* Vector VFMS floating point. */
2139 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2141 0xef200c50, 0xffa11f51,
2142 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2144 /* Vector VFMAS, vector * scalar. */
2145 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2146 MVE_VFMAS_FP_SCALAR
,
2147 0xee311e40, 0xefb11f70,
2148 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2150 /* Vector VHADD T1. */
2151 {ARM_FEATURE_COPROC (FPU_MVE
),
2153 0xef000040, 0xef811f51,
2154 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2156 /* Vector VHADD T2. */
2157 {ARM_FEATURE_COPROC (FPU_MVE
),
2159 0xee000f40, 0xef811f70,
2160 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2162 /* Vector VHSUB T1. */
2163 {ARM_FEATURE_COPROC (FPU_MVE
),
2165 0xef000240, 0xef811f51,
2166 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2168 /* Vector VHSUB T2. */
2169 {ARM_FEATURE_COPROC (FPU_MVE
),
2171 0xee001f40, 0xef811f70,
2172 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2175 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2177 0xee300e00, 0xefb10f50,
2178 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2181 {ARM_FEATURE_COPROC (FPU_MVE
),
2183 0xeea00b10, 0xffb10f5f,
2184 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2186 /* Vector VRHADD. */
2187 {ARM_FEATURE_COPROC (FPU_MVE
),
2189 0xef000140, 0xef811f51,
2190 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2193 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2194 MVE_VCVT_FP_FIX_VEC
,
2195 0xef800c50, 0xef801cd1,
2196 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2199 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2200 MVE_VCVT_BETWEEN_FP_INT
,
2201 0xffb30640, 0xffb31e51,
2202 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2204 /* Vector VCVT between single and half-precision float, bottom half. */
2205 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2206 MVE_VCVT_FP_HALF_FP
,
2207 0xee3f0e01, 0xefbf1fd1,
2208 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2210 /* Vector VCVT between single and half-precision float, top half. */
2211 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2212 MVE_VCVT_FP_HALF_FP
,
2213 0xee3f1e01, 0xefbf1fd1,
2214 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2217 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2218 MVE_VCVT_FROM_FP_TO_INT
,
2219 0xffb30040, 0xffb31c51,
2220 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2223 {ARM_FEATURE_COPROC (FPU_MVE
),
2225 0xee011f6e, 0xff811f7e,
2226 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2228 /* Vector VDWDUP. */
2229 {ARM_FEATURE_COPROC (FPU_MVE
),
2231 0xee011f60, 0xff811f70,
2232 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2234 /* Vector VHCADD. */
2235 {ARM_FEATURE_COPROC (FPU_MVE
),
2237 0xee000f00, 0xff810f51,
2238 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2240 /* Vector VIWDUP. */
2241 {ARM_FEATURE_COPROC (FPU_MVE
),
2243 0xee010f60, 0xff811f70,
2244 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2247 {ARM_FEATURE_COPROC (FPU_MVE
),
2249 0xee010f6e, 0xff811f7e,
2250 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2253 {ARM_FEATURE_COPROC (FPU_MVE
),
2255 0xfc901e00, 0xff901e5f,
2256 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2259 {ARM_FEATURE_COPROC (FPU_MVE
),
2261 0xfc901e01, 0xff901e1f,
2262 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2264 /* Vector VLDRB gather load. */
2265 {ARM_FEATURE_COPROC (FPU_MVE
),
2266 MVE_VLDRB_GATHER_T1
,
2267 0xec900e00, 0xefb01e50,
2268 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2270 /* Vector VLDRH gather load. */
2271 {ARM_FEATURE_COPROC (FPU_MVE
),
2272 MVE_VLDRH_GATHER_T2
,
2273 0xec900e10, 0xefb01e50,
2274 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2276 /* Vector VLDRW gather load. */
2277 {ARM_FEATURE_COPROC (FPU_MVE
),
2278 MVE_VLDRW_GATHER_T3
,
2279 0xfc900f40, 0xffb01fd0,
2280 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2282 /* Vector VLDRD gather load. */
2283 {ARM_FEATURE_COPROC (FPU_MVE
),
2284 MVE_VLDRD_GATHER_T4
,
2285 0xec900fd0, 0xefb01fd0,
2286 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2288 /* Vector VLDRW gather load. */
2289 {ARM_FEATURE_COPROC (FPU_MVE
),
2290 MVE_VLDRW_GATHER_T5
,
2291 0xfd101e00, 0xff111f00,
2292 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2294 /* Vector VLDRD gather load, variant T6. */
2295 {ARM_FEATURE_COPROC (FPU_MVE
),
2296 MVE_VLDRD_GATHER_T6
,
2297 0xfd101f00, 0xff111f00,
2298 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2301 {ARM_FEATURE_COPROC (FPU_MVE
),
2303 0xec100e00, 0xee581e00,
2304 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2307 {ARM_FEATURE_COPROC (FPU_MVE
),
2309 0xec180e00, 0xee581e00,
2310 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2312 /* Vector VLDRB unsigned, variant T5. */
2313 {ARM_FEATURE_COPROC (FPU_MVE
),
2315 0xec101e00, 0xfe101f80,
2316 "vldrb%v.u8\t%13-15,22Q, %d"},
2318 /* Vector VLDRH unsigned, variant T6. */
2319 {ARM_FEATURE_COPROC (FPU_MVE
),
2321 0xec101e80, 0xfe101f80,
2322 "vldrh%v.u16\t%13-15,22Q, %d"},
2324 /* Vector VLDRW unsigned, variant T7. */
2325 {ARM_FEATURE_COPROC (FPU_MVE
),
2327 0xec101f00, 0xfe101f80,
2328 "vldrw%v.u32\t%13-15,22Q, %d"},
2330 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2332 {ARM_FEATURE_COPROC (FPU_MVE
),
2334 0xee801e00, 0xef801f51,
2335 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2337 {ARM_FEATURE_COPROC (FPU_MVE
),
2339 0xee800e00, 0xef801f51,
2340 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2342 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2343 {ARM_FEATURE_COPROC (FPU_MVE
),
2345 0xeef00e00, 0xeff01f51,
2346 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2348 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2349 {ARM_FEATURE_COPROC (FPU_MVE
),
2351 0xeef00f00, 0xeff11f51,
2352 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2354 /* Vector VMLADAV T1 variant. */
2355 {ARM_FEATURE_COPROC (FPU_MVE
),
2357 0xeef01e00, 0xeff01f51,
2358 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2360 /* Vector VMLADAV T2 variant. */
2361 {ARM_FEATURE_COPROC (FPU_MVE
),
2363 0xeef01f00, 0xeff11f51,
2364 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2367 {ARM_FEATURE_COPROC (FPU_MVE
),
2369 0xee011e40, 0xef811f70,
2370 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2372 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2374 {ARM_FEATURE_COPROC (FPU_MVE
),
2376 0xfe800e01, 0xff810f51,
2377 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2379 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2381 {ARM_FEATURE_COPROC (FPU_MVE
),
2383 0xee800e01, 0xff800f51,
2384 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2386 /* Vector VMLSDAV T1 Variant. */
2387 {ARM_FEATURE_COPROC (FPU_MVE
),
2389 0xeef00e01, 0xfff00f51,
2390 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2392 /* Vector VMLSDAV T2 Variant. */
2393 {ARM_FEATURE_COPROC (FPU_MVE
),
2395 0xfef00e01, 0xfff10f51,
2396 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2398 /* Vector VMOV between gpr and half precision register, op == 0. */
2399 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2401 0xee000910, 0xfff00f7f,
2402 "vmov.f16\t%7,16-19F, %12-15r"},
2404 /* Vector VMOV between gpr and half precision register, op == 1. */
2405 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2407 0xee100910, 0xfff00f7f,
2408 "vmov.f16\t%12-15r, %7,16-19F"},
2410 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2411 MVE_VMOV_GP_TO_VEC_LANE
,
2412 0xee000b10, 0xff900f1f,
2413 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2415 /* Vector VORR immediate to vector.
2416 NOTE: MVE_VORR_IMM must appear in the table
2417 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2418 {ARM_FEATURE_COPROC (FPU_MVE
),
2420 0xef800050, 0xefb810f0,
2421 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2423 /* Vector VMOV immediate to vector,
2424 cmode == 11x1 -> VMVN which is UNDEFINED
2425 for such a cmode. */
2426 {ARM_FEATURE_COPROC (FPU_MVE
),
2427 MVE_VMVN_IMM
, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION
},
2429 /* Vector VMOV immediate to vector. */
2430 {ARM_FEATURE_COPROC (FPU_MVE
),
2431 MVE_VMOV_IMM_TO_VEC
,
2432 0xef800050, 0xefb810d0,
2433 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2435 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2436 {ARM_FEATURE_COPROC (FPU_MVE
),
2437 MVE_VMOV2_VEC_LANE_TO_GP
,
2438 0xec000f00, 0xffb01ff0,
2439 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2441 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2442 {ARM_FEATURE_COPROC (FPU_MVE
),
2443 MVE_VMOV2_VEC_LANE_TO_GP
,
2444 0xec000f10, 0xffb01ff0,
2445 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2447 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2448 {ARM_FEATURE_COPROC (FPU_MVE
),
2449 MVE_VMOV2_GP_TO_VEC_LANE
,
2450 0xec100f00, 0xffb01ff0,
2451 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2453 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2454 {ARM_FEATURE_COPROC (FPU_MVE
),
2455 MVE_VMOV2_GP_TO_VEC_LANE
,
2456 0xec100f10, 0xffb01ff0,
2457 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2459 /* Vector VMOV Vector lane to gpr. */
2460 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2461 MVE_VMOV_VEC_LANE_TO_GP
,
2462 0xee100b10, 0xff100f1f,
2463 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2465 /* Vector VMOVL long. */
2466 {ARM_FEATURE_COPROC (FPU_MVE
),
2468 0xeea00f40, 0xefa70fd1,
2469 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2471 /* Vector VMOV and narrow. */
2472 {ARM_FEATURE_COPROC (FPU_MVE
),
2474 0xfe310e81, 0xffb30fd1,
2475 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2477 /* Floating point move extract. */
2478 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2480 0xfeb00a40, 0xffbf0fd0,
2481 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2483 /* Vector VMULL integer. */
2484 {ARM_FEATURE_COPROC (FPU_MVE
),
2486 0xee010e00, 0xef810f51,
2487 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2489 /* Vector VMULL polynomial. */
2490 {ARM_FEATURE_COPROC (FPU_MVE
),
2492 0xee310e00, 0xefb10f51,
2493 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2495 /* Vector VMVN immediate to vector. */
2496 {ARM_FEATURE_COPROC (FPU_MVE
),
2498 0xef800070, 0xefb810f0,
2499 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2501 /* Vector VMVN register. */
2502 {ARM_FEATURE_COPROC (FPU_MVE
),
2504 0xffb005c0, 0xffbf1fd1,
2505 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2507 /* Vector VORN, vector bitwise or not. */
2508 {ARM_FEATURE_COPROC (FPU_MVE
),
2510 0xef300150, 0xffb11f51,
2511 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2513 /* Vector VORR register. */
2514 {ARM_FEATURE_COPROC (FPU_MVE
),
2516 0xef200150, 0xffb11f51,
2517 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2519 /* Vector VQDMULL T1 variant. */
2520 {ARM_FEATURE_COPROC (FPU_MVE
),
2522 0xee300f01, 0xefb10f51,
2523 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2525 /* Vector VQDMULL T2 variant. */
2526 {ARM_FEATURE_COPROC (FPU_MVE
),
2528 0xee300f60, 0xefb10f70,
2529 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2531 /* Vector VQMOVN. */
2532 {ARM_FEATURE_COPROC (FPU_MVE
),
2534 0xee330e01, 0xefb30fd1,
2535 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2537 /* Vector VQMOVUN. */
2538 {ARM_FEATURE_COPROC (FPU_MVE
),
2540 0xee310e81, 0xffb30fd1,
2541 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2543 /* Vector VQDMLADH. */
2544 {ARM_FEATURE_COPROC (FPU_MVE
),
2546 0xee000e00, 0xff810f51,
2547 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2549 /* Vector VQRDMLADH. */
2550 {ARM_FEATURE_COPROC (FPU_MVE
),
2552 0xee000e01, 0xff810f51,
2553 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2555 /* Vector VQDMLAH. */
2556 {ARM_FEATURE_COPROC (FPU_MVE
),
2558 0xee000e60, 0xef811f70,
2559 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2561 /* Vector VQRDMLAH. */
2562 {ARM_FEATURE_COPROC (FPU_MVE
),
2564 0xee000e40, 0xef811f70,
2565 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2567 /* Vector VQDMLASH. */
2568 {ARM_FEATURE_COPROC (FPU_MVE
),
2570 0xee001e60, 0xef811f70,
2571 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2573 /* Vector VQRDMLASH. */
2574 {ARM_FEATURE_COPROC (FPU_MVE
),
2576 0xee001e40, 0xef811f70,
2577 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2579 /* Vector VQDMLSDH. */
2580 {ARM_FEATURE_COPROC (FPU_MVE
),
2582 0xfe000e00, 0xff810f51,
2583 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2585 /* Vector VQRDMLSDH. */
2586 {ARM_FEATURE_COPROC (FPU_MVE
),
2588 0xfe000e01, 0xff810f51,
2589 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2591 /* Vector VQDMULH T1 variant. */
2592 {ARM_FEATURE_COPROC (FPU_MVE
),
2594 0xef000b40, 0xff811f51,
2595 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2597 /* Vector VQRDMULH T2 variant. */
2598 {ARM_FEATURE_COPROC (FPU_MVE
),
2600 0xff000b40, 0xff811f51,
2601 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2603 /* Vector VQDMULH T3 variant. */
2604 {ARM_FEATURE_COPROC (FPU_MVE
),
2606 0xee010e60, 0xff811f70,
2607 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2609 /* Vector VQRDMULH T4 variant. */
2610 {ARM_FEATURE_COPROC (FPU_MVE
),
2612 0xfe010e60, 0xff811f70,
2613 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2615 /* Vector VRINT floating point. */
2616 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2618 0xffb20440, 0xffb31c51,
2619 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2621 /* Vector VRMLALDAVH. */
2622 {ARM_FEATURE_COPROC (FPU_MVE
),
2624 0xee800f00, 0xef811f51,
2625 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2627 /* Vector VRMLALDAVH. */
2628 {ARM_FEATURE_COPROC (FPU_MVE
),
2630 0xee801f00, 0xef811f51,
2631 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2633 /* Vector VST2 no writeback. */
2634 {ARM_FEATURE_COPROC (FPU_MVE
),
2636 0xfc801e00, 0xffb01e5f,
2637 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2639 /* Vector VST2 writeback. */
2640 {ARM_FEATURE_COPROC (FPU_MVE
),
2642 0xfca01e00, 0xffb01e5f,
2643 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2645 /* Vector VST4 no writeback. */
2646 {ARM_FEATURE_COPROC (FPU_MVE
),
2648 0xfc801e01, 0xffb01e1f,
2649 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2651 /* Vector VST4 writeback. */
2652 {ARM_FEATURE_COPROC (FPU_MVE
),
2654 0xfca01e01, 0xffb01e1f,
2655 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2657 /* Vector VSTRB scatter store, T1 variant. */
2658 {ARM_FEATURE_COPROC (FPU_MVE
),
2659 MVE_VSTRB_SCATTER_T1
,
2660 0xec800e00, 0xffb01e50,
2661 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2663 /* Vector VSTRH scatter store, T2 variant. */
2664 {ARM_FEATURE_COPROC (FPU_MVE
),
2665 MVE_VSTRH_SCATTER_T2
,
2666 0xec800e10, 0xffb01e50,
2667 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2669 /* Vector VSTRW scatter store, T3 variant. */
2670 {ARM_FEATURE_COPROC (FPU_MVE
),
2671 MVE_VSTRW_SCATTER_T3
,
2672 0xec800e40, 0xffb01e50,
2673 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2675 /* Vector VSTRD scatter store, T4 variant. */
2676 {ARM_FEATURE_COPROC (FPU_MVE
),
2677 MVE_VSTRD_SCATTER_T4
,
2678 0xec800fd0, 0xffb01fd0,
2679 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2681 /* Vector VSTRW scatter store, T5 variant. */
2682 {ARM_FEATURE_COPROC (FPU_MVE
),
2683 MVE_VSTRW_SCATTER_T5
,
2684 0xfd001e00, 0xff111f00,
2685 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2687 /* Vector VSTRD scatter store, T6 variant. */
2688 {ARM_FEATURE_COPROC (FPU_MVE
),
2689 MVE_VSTRD_SCATTER_T6
,
2690 0xfd001f00, 0xff111f00,
2691 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2694 {ARM_FEATURE_COPROC (FPU_MVE
),
2696 0xec000e00, 0xfe581e00,
2697 "vstrb%v.%7-8s\t%13-15Q, %d"},
2700 {ARM_FEATURE_COPROC (FPU_MVE
),
2702 0xec080e00, 0xfe581e00,
2703 "vstrh%v.%7-8s\t%13-15Q, %d"},
2705 /* Vector VSTRB variant T5. */
2706 {ARM_FEATURE_COPROC (FPU_MVE
),
2708 0xec001e00, 0xfe101f80,
2709 "vstrb%v.8\t%13-15,22Q, %d"},
2711 /* Vector VSTRH variant T6. */
2712 {ARM_FEATURE_COPROC (FPU_MVE
),
2714 0xec001e80, 0xfe101f80,
2715 "vstrh%v.16\t%13-15,22Q, %d"},
2717 /* Vector VSTRW variant T7. */
2718 {ARM_FEATURE_COPROC (FPU_MVE
),
2720 0xec001f00, 0xfe101f80,
2721 "vstrw%v.32\t%13-15,22Q, %d"},
2723 {ARM_FEATURE_CORE_LOW (0),
2725 0x00000000, 0x00000000, 0}
2728 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
2729 ordered: they must be searched linearly from the top to obtain a correct
2732 /* print_insn_arm recognizes the following format control codes:
2736 %a print address for ldr/str instruction
2737 %s print address for ldr/str halfword/signextend instruction
2738 %S like %s but allow UNPREDICTABLE addressing
2739 %b print branch destination
2740 %c print condition code (always bits 28-31)
2741 %m print register mask for ldm/stm instruction
2742 %o print operand2 (immediate or register + shift)
2743 %p print 'p' iff bits 12-15 are 15
2744 %t print 't' iff bit 21 set and bit 24 clear
2745 %B print arm BLX(1) destination
2746 %C print the PSR sub type.
2747 %U print barrier type.
2748 %P print address for pli instruction.
2750 %<bitfield>r print as an ARM register
2751 %<bitfield>T print as an ARM register + 1
2752 %<bitfield>R as %r but r15 is UNPREDICTABLE
2753 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2754 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
2755 %<bitfield>d print the bitfield in decimal
2756 %<bitfield>W print the bitfield plus one in decimal
2757 %<bitfield>x print the bitfield in hex
2758 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2760 %<bitfield>'c print specified char iff bitfield is all ones
2761 %<bitfield>`c print specified char iff bitfield is all zeroes
2762 %<bitfield>?ab... select from array of values in big endian order
2764 %e print arm SMI operand (bits 0..7,8..19).
2765 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
2766 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
2767 %R print the SPSR/CPSR or banked register of an MRS. */
2769 static const struct opcode32 arm_opcodes
[] =
2771 /* ARM instructions. */
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2773 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2775 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
2778 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
2780 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
2782 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
2784 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
2786 0x00800090, 0x0fa000f0,
2787 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
2789 0x00a00090, 0x0fa000f0,
2790 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2792 /* V8.2 RAS extension instructions. */
2793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
2794 0xe320f010, 0xffffffff, "esb"},
2796 /* V8 instructions. */
2797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2798 0x0320f005, 0x0fffffff, "sevl"},
2799 /* Defined in V8 but is in NOP space so available to all arch. */
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2801 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
2802 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
2803 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2805 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2807 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2809 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2811 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2813 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2815 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2817 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2819 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2821 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2823 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2825 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2827 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2829 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2830 /* CRC32 instructions. */
2831 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2832 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
2833 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2834 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
2835 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2836 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
2837 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2838 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
2839 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2840 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
2841 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2842 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
2844 /* Privileged Access Never extension instructions. */
2845 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
2846 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
2848 /* Virtualization Extension instructions. */
2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
2852 /* Integer Divide Extension instructions. */
2853 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
2854 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
2855 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
2856 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
2858 /* MP Extension instructions. */
2859 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
2861 /* Speculation Barriers. */
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
2863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
2866 /* V7 instructions. */
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
2875 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
2877 /* ARM V6T2 instructions. */
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2879 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2881 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2883 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2885 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2888 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2890 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
2892 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2893 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
2894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2895 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2897 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2899 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
2901 /* ARM Security extension instructions. */
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
2903 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2905 /* ARM V6K instructions. */
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2907 0xf57ff01f, 0xffffffff, "clrex"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2909 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2911 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2913 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2915 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2917 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2919 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
2921 /* ARMv8.5-A instructions. */
2922 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
2924 /* ARM V6K NOP hints. */
2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2926 0x0320f001, 0x0fffffff, "yield%c"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2928 0x0320f002, 0x0fffffff, "wfe%c"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2930 0x0320f003, 0x0fffffff, "wfi%c"},
2931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2932 0x0320f004, 0x0fffffff, "sev%c"},
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2934 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
2936 /* ARM V6 instructions. */
2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2938 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2940 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2942 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2944 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2946 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2948 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2950 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2952 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2954 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2956 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2958 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2960 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2962 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2964 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2966 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2968 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2970 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2972 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2974 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2976 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2978 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2980 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2982 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2984 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2986 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2988 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2990 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2992 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2994 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2996 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2998 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3000 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3002 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3004 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3006 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3008 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3010 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3012 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3014 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3016 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3018 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3020 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3022 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3024 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3026 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3028 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3030 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3032 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3034 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3036 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3038 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3040 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3042 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3044 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3046 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3048 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3050 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3052 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3054 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3056 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3058 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3060 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3062 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3064 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3066 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3068 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3070 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3072 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3074 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3076 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3078 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3080 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3082 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3084 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3086 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3088 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3090 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3092 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3094 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3096 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3098 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3100 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3102 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3104 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3106 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3108 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3110 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3112 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3114 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3116 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3118 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3120 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3122 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3124 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3126 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3128 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3130 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3132 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3134 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3136 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3138 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3140 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3142 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3144 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3146 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3148 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3150 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3152 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3154 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3156 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3158 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3160 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3162 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3164 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3166 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3168 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3170 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3172 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3174 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3176 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3178 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3180 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3182 /* V5J instruction. */
3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
3184 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3186 /* V5 Instructions. */
3187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3188 0xe1200070, 0xfff000f0,
3189 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3191 0xfa000000, 0xfe000000, "blx\t%B"},
3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3193 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3195 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3197 /* V5E "El Segundo" Instructions. */
3198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3199 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3201 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3203 0xf450f000, 0xfc70f000, "pld\t%a"},
3204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3205 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3207 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3209 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3211 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3214 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3216 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3219 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3221 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3223 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3225 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3228 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3230 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3232 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3234 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3237 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3239 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3242 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3244 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3246 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3248 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3250 /* ARM Instructions. */
3251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3252 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3255 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3257 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3259 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3261 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3263 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3265 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3268 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3270 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3272 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3274 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3277 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
3278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3279 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3281 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
3282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3283 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3286 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3288 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3290 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3293 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3295 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3297 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3300 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3302 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3304 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3307 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3309 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3311 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3314 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3316 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3318 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3321 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3323 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3325 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3328 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3330 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3332 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3335 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3337 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3339 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3341 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
3342 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
3344 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
3346 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3349 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3351 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3353 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3356 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
3357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3358 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
3359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3360 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3363 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3365 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3367 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3370 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3372 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3374 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3377 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3379 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3381 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3384 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3386 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3388 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3390 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3392 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3394 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3396 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3399 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3401 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3403 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3406 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3408 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3410 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3413 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
3414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3415 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3418 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3421 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3423 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3426 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3428 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3430 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3432 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3434 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3436 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3438 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3440 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3442 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3444 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3446 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3448 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3450 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3452 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3454 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3456 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3458 0x092d0000, 0x0fff0000, "push%c\t%m"},
3459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3460 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3462 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3465 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3467 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3469 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3471 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3473 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3475 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3477 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3479 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3481 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3483 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3485 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3487 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3489 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3491 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3493 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3495 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3497 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3499 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3501 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3504 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3506 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
3509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3510 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
3511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3512 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
3513 {ARM_FEATURE_CORE_LOW (0),
3514 0x00000000, 0x00000000, 0}
3517 /* print_insn_thumb16 recognizes the following format control codes:
3519 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3520 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3521 %<bitfield>I print bitfield as a signed decimal
3522 (top bit of range being the sign bit)
3523 %N print Thumb register mask (with LR)
3524 %O print Thumb register mask (with PC)
3525 %M print Thumb register mask
3526 %b print CZB's 6-bit unsigned branch destination
3527 %s print Thumb right-shift immediate (6..10; 0 == 32).
3528 %c print the condition code
3529 %C print the condition code, or "s" if not conditional
3530 %x print warning if conditional an not at end of IT block"
3531 %X print "\t; unpredictable <IT:code>" if conditional
3532 %I print IT instruction suffix and operands
3533 %W print Thumb Writeback indicator for LDMIA
3534 %<bitfield>r print bitfield as an ARM register
3535 %<bitfield>d print bitfield as a decimal
3536 %<bitfield>H print (bitfield * 2) as a decimal
3537 %<bitfield>W print (bitfield * 4) as a decimal
3538 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3539 %<bitfield>B print Thumb branch destination (signed displacement)
3540 %<bitfield>c print bitfield as a condition code
3541 %<bitnum>'c print specified char iff bit is one
3542 %<bitnum>?ab print a if bit is one else print b. */
3544 static const struct opcode16 thumb_opcodes
[] =
3546 /* Thumb instructions. */
3548 /* ARMv8-M Security Extensions instructions. */
3549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
3552 /* ARM V8 instructions. */
3553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
3555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
3557 /* ARM V6K no-argument instructions. */
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
3559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
3561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
3562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
3565 /* ARM V6T2 instructions. */
3566 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3567 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3568 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3569 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
3573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
3585 /* ARM V5 ISA extends Thumb. */
3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
3587 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
3588 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
3590 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
3591 /* ARM V4T ISA (Thumb v1). */
3592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3593 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
3595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
3615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
3617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
3621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3624 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3626 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3628 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3630 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3633 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3635 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3637 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3640 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3642 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3646 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
3650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
3655 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3658 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
3660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3661 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3663 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3665 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3667 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3670 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3672 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
3674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3675 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3677 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3680 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3682 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
3684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
3687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
3689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
3693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
3695 /* The E800 .. FFFF range is unconditionally redirected to the
3696 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3697 are processed via that table. Thus, we can never encounter a
3698 bare "second half of BL/BLX(1)" instruction here. */
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
3700 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3703 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
3704 We adopt the convention that hw1 is the high 16 bits of .value and
3705 .mask, hw2 the low 16 bits.
3707 print_insn_thumb32 recognizes the following format control codes:
3711 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3712 %M print a modified 12-bit immediate (same location)
3713 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3714 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
3715 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
3716 %S print a possibly-shifted Rm
3718 %L print address for a ldrd/strd instruction
3719 %a print the address of a plain load/store
3720 %w print the width and signedness of a core load/store
3721 %m print register mask for ldm/stm
3722 %n print register mask for clrm
3724 %E print the lsb and width fields of a bfc/bfi instruction
3725 %F print the lsb and width fields of a sbfx/ubfx instruction
3726 %G print a fallback offset for Branch Future instructions
3727 %W print an offset for BF instruction
3728 %Y print an offset for BFL instruction
3729 %Z print an offset for BFCSEL instruction
3730 %Q print an offset for Low Overhead Loop instructions
3731 %P print an offset for Low Overhead Loop end instructions
3732 %b print a conditional branch offset
3733 %B print an unconditional branch offset
3734 %s print the shift field of an SSAT instruction
3735 %R print the rotation field of an SXT instruction
3736 %U print barrier type.
3737 %P print address for pli instruction.
3738 %c print the condition code
3739 %x print warning if conditional an not at end of IT block"
3740 %X print "\t; unpredictable <IT:code>" if conditional
3742 %<bitfield>d print bitfield in decimal
3743 %<bitfield>D print bitfield plus one in decimal
3744 %<bitfield>W print bitfield*4 in decimal
3745 %<bitfield>r print bitfield as an ARM register
3746 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
3747 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
3748 %<bitfield>c print bitfield as a condition code
3750 %<bitfield>'c print specified char iff bitfield is all ones
3751 %<bitfield>`c print specified char iff bitfield is all zeroes
3752 %<bitfield>?ab... select from array of values in big endian order
3754 With one exception at the bottom (done because BL and BLX(1) need
3755 to come dead last), this table was machine-sorted first in
3756 decreasing order of number of bits set in the mask, then in
3757 increasing numeric order of mask, then in increasing numeric order
3758 of opcode. This order is not the clearest for a human reader, but
3759 is guaranteed never to catch a special-case bit pattern with a more
3760 general mask, which is important, because this instruction encoding
3761 makes heavy use of special-case bit patterns. */
3762 static const struct opcode32 thumb32_opcodes
[] =
3764 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3766 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3767 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3768 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3769 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3771 0xf02fc001, 0xfffff001, "le\t%P"},
3772 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3773 0xf00fc001, 0xfffff001, "le\tlr, %P"},
3775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3776 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
3777 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3778 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
3779 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3780 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
3781 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3782 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
3783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3784 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
3786 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3787 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
3789 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
3790 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
3791 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3792 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3794 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
3795 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3796 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3797 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3798 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
3800 /* ARM V8.2 RAS extension instructions. */
3801 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
3802 0xf3af8010, 0xffffffff, "esb"},
3804 /* V8 instructions. */
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3806 0xf3af8005, 0xffffffff, "sevl%c.w"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3808 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3810 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3812 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3814 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
3815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3816 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3818 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3820 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3822 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3824 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3826 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3828 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3830 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3832 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3834 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3836 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
3838 /* CRC32 instructions. */
3839 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3840 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
3841 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3842 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
3843 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3844 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
3845 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3846 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
3847 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3848 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
3849 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3850 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
3852 /* Speculation Barriers. */
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
3857 /* V7 instructions. */
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
3866 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
3868 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
3870 /* Virtualization Extension instructions. */
3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
3872 /* We skip ERET as that is SUBS pc, lr, #0. */
3874 /* MP Extension instructions. */
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
3877 /* Security extension instructions. */
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
3880 /* ARMv8.5-A instructions. */
3881 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
3883 /* Instructions defined in the basic V6T2 set. */
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
3887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3890 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
3893 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3894 0xf3bf8f2f, 0xffffffff, "clrex%c"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3896 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3898 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3900 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3902 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3904 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3906 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3908 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3910 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3912 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3914 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3916 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3918 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3920 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
3921 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3922 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
3923 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3924 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3926 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3928 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3930 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3932 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3934 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3936 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3938 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3940 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
3941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3942 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3944 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3946 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3948 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3950 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3952 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3954 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3956 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3958 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3960 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3962 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3964 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3966 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3968 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3970 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3972 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3974 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3976 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3978 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3980 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3982 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3984 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3986 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3988 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3990 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3992 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3994 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3996 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3998 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4000 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4002 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4004 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4006 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4008 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4010 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4012 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4014 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4016 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4018 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4020 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4022 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4024 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4026 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4028 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4030 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4032 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4034 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4036 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4038 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4040 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4042 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4044 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4046 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4048 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4049 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4050 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4052 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4054 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4056 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4058 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4060 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4062 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4064 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4066 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4068 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4070 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4072 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4074 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4076 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4078 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4080 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4082 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4084 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4086 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4088 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4090 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4092 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4094 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4096 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4098 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4100 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4102 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4104 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4106 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4108 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4110 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4112 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4114 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4116 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4117 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4118 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4120 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4122 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4124 0xf810f000, 0xff70f000, "pld%c\t%a"},
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4126 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4128 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4130 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4132 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4134 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4136 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4138 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4140 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4142 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4144 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4146 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4148 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4150 0xfb100000, 0xfff000c0,
4151 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4153 0xfbc00080, 0xfff000c0,
4154 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4156 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4158 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4160 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4162 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4164 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4165 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4166 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4168 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4170 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4172 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4174 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4176 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4178 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4180 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4182 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4184 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4186 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4188 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4190 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4191 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4192 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4194 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4196 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4198 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4200 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4202 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4204 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4206 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4208 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4210 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4212 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4214 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4216 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4218 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4220 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4222 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4224 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4226 0xe9400000, 0xff500000,
4227 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4229 0xe9500000, 0xff500000,
4230 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4232 0xe8600000, 0xff700000,
4233 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4235 0xe8700000, 0xff700000,
4236 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4238 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4240 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
4242 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4244 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4246 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4248 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4250 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
4252 /* These have been 32-bit since the invention of Thumb. */
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4254 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4256 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
4259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4260 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
4261 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4264 static const char *const arm_conditional
[] =
4265 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
4266 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
4268 static const char *const arm_fp_const
[] =
4269 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4271 static const char *const arm_shift
[] =
4272 {"lsl", "lsr", "asr", "ror"};
4277 const char *description
;
4278 const char *reg_names
[16];
4282 static const arm_regname regnames
[] =
4284 { "reg-names-raw", N_("Select raw register names"),
4285 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
4286 { "reg-names-gcc", N_("Select register names used by GCC"),
4287 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
4288 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
4289 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
4290 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
4291 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
4292 { "reg-names-apcs", N_("Select register names used in the APCS"),
4293 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
4294 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
4295 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
4296 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4297 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
4300 static const char *const iwmmxt_wwnames
[] =
4301 {"b", "h", "w", "d"};
4303 static const char *const iwmmxt_wwssnames
[] =
4304 {"b", "bus", "bc", "bss",
4305 "h", "hus", "hc", "hss",
4306 "w", "wus", "wc", "wss",
4307 "d", "dus", "dc", "dss"
4310 static const char *const iwmmxt_regnames
[] =
4311 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4312 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4315 static const char *const iwmmxt_cregnames
[] =
4316 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4317 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4320 static const char *const vec_condnames
[] =
4321 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4324 static const char *const mve_predicatenames
[] =
4325 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4326 "eee", "ee", "eet", "e", "ett", "et", "ete"
4329 /* Names for 2-bit size field for mve vector isntructions. */
4330 static const char *const mve_vec_sizename
[] =
4331 { "8", "16", "32", "64"};
4333 /* Indicates whether we are processing a then predicate,
4334 else predicate or none at all. */
4342 /* Information used to process a vpt block and subsequent instructions. */
4345 /* Are we in a vpt block. */
4346 bfd_boolean in_vpt_block
;
4348 /* Next predicate state if in vpt block. */
4349 enum vpt_pred_state next_pred_state
;
4351 /* Mask from vpt/vpst instruction. */
4352 long predicate_mask
;
4354 /* Instruction number in vpt block. */
4355 long current_insn_num
;
4357 /* Number of instructions in vpt block.. */
4361 static struct vpt_block vpt_block_state
=
4370 /* Default to GCC register name set. */
4371 static unsigned int regname_selected
= 1;
4373 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
4374 #define arm_regnames regnames[regname_selected].reg_names
4376 static bfd_boolean force_thumb
= FALSE
;
4378 /* Current IT instruction state. This contains the same state as the IT
4379 bits in the CPSR. */
4380 static unsigned int ifthen_state
;
4381 /* IT state for the next instruction. */
4382 static unsigned int ifthen_next_state
;
4383 /* The address of the insn for which the IT state is valid. */
4384 static bfd_vma ifthen_address
;
4385 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
4386 /* Indicates that the current Conditional state is unconditional or outside
4388 #define COND_UNCOND 16
4392 /* Extract the predicate mask for a VPT or VPST instruction.
4393 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4396 mve_extract_pred_mask (long given
)
4398 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
4401 /* Return the number of instructions in a MVE predicate block. */
4403 num_instructions_vpt_block (long given
)
4405 long mask
= mve_extract_pred_mask (given
);
4412 if ((mask
& 7) == 4)
4415 if ((mask
& 3) == 2)
4418 if ((mask
& 1) == 1)
4425 mark_outside_vpt_block (void)
4427 vpt_block_state
.in_vpt_block
= FALSE
;
4428 vpt_block_state
.next_pred_state
= PRED_NONE
;
4429 vpt_block_state
.predicate_mask
= 0;
4430 vpt_block_state
.current_insn_num
= 0;
4431 vpt_block_state
.num_pred_insn
= 0;
4435 mark_inside_vpt_block (long given
)
4437 vpt_block_state
.in_vpt_block
= TRUE
;
4438 vpt_block_state
.next_pred_state
= PRED_THEN
;
4439 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
4440 vpt_block_state
.current_insn_num
= 0;
4441 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
4442 assert (vpt_block_state
.num_pred_insn
>= 1);
4445 static enum vpt_pred_state
4446 invert_next_predicate_state (enum vpt_pred_state astate
)
4448 if (astate
== PRED_THEN
)
4450 else if (astate
== PRED_ELSE
)
4456 static enum vpt_pred_state
4457 update_next_predicate_state (void)
4459 long pred_mask
= vpt_block_state
.predicate_mask
;
4460 long mask_for_insn
= 0;
4462 switch (vpt_block_state
.current_insn_num
)
4480 if (pred_mask
& mask_for_insn
)
4481 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
4483 return vpt_block_state
.next_pred_state
;
4487 update_vpt_block_state (void)
4489 vpt_block_state
.current_insn_num
++;
4490 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
4492 /* No more instructions to process in vpt block. */
4493 mark_outside_vpt_block ();
4497 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
4500 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4501 Returns pointer to following character of the format string and
4502 fills in *VALUEP and *WIDTHP with the extracted value and number of
4503 bits extracted. WIDTHP can be NULL. */
4506 arm_decode_bitfield (const char *ptr
,
4508 unsigned long *valuep
,
4511 unsigned long value
= 0;
4519 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
4520 start
= start
* 10 + *ptr
- '0';
4522 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
4523 end
= end
* 10 + *ptr
- '0';
4529 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
4532 while (*ptr
++ == ',');
4540 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
4541 bfd_boolean print_shift
)
4543 func (stream
, "%s", arm_regnames
[given
& 0xf]);
4545 if ((given
& 0xff0) != 0)
4547 if ((given
& 0x10) == 0)
4549 int amount
= (given
& 0xf80) >> 7;
4550 int shift
= (given
& 0x60) >> 5;
4556 func (stream
, ", rrx");
4564 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
4566 func (stream
, ", #%d", amount
);
4568 else if ((given
& 0x80) == 0x80)
4569 func (stream
, "\t; <illegal shifter operand>");
4570 else if (print_shift
)
4571 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
4572 arm_regnames
[(given
& 0xf00) >> 8]);
4574 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
4578 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4581 is_mve_okay_in_it (enum mve_instructions matched_insn
)
4583 switch (matched_insn
)
4585 case MVE_VMOV_GP_TO_VEC_LANE
:
4586 case MVE_VMOV2_VEC_LANE_TO_GP
:
4587 case MVE_VMOV2_GP_TO_VEC_LANE
:
4588 case MVE_VMOV_VEC_LANE_TO_GP
:
4596 is_mve_architecture (struct disassemble_info
*info
)
4598 struct arm_private_data
*private_data
= info
->private_data
;
4599 arm_feature_set allowed_arches
= private_data
->features
;
4601 arm_feature_set arm_ext_v8_1m_main
4602 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
4604 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
4605 && !ARM_CPU_IS_ANY (allowed_arches
))
4612 is_vpt_instruction (long given
)
4615 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4616 if ((given
& 0x0040e000) == 0)
4619 /* VPT floating point T1 variant. */
4620 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
4621 /* VPT floating point T2 variant. */
4622 || ((given
& 0xefb10f50) == 0xee310f40)
4623 /* VPT vector T1 variant. */
4624 || ((given
& 0xff811f51) == 0xfe010f00)
4625 /* VPT vector T2 variant. */
4626 || ((given
& 0xff811f51) == 0xfe010f01
4627 && ((given
& 0x300000) != 0x300000))
4628 /* VPT vector T3 variant. */
4629 || ((given
& 0xff811f50) == 0xfe011f00)
4630 /* VPT vector T4 variant. */
4631 || ((given
& 0xff811f70) == 0xfe010f40)
4632 /* VPT vector T5 variant. */
4633 || ((given
& 0xff811f70) == 0xfe010f60)
4634 /* VPT vector T6 variant. */
4635 || ((given
& 0xff811f50) == 0xfe011f40)
4636 /* VPST vector T variant. */
4637 || ((given
& 0xffbf1fff) == 0xfe310f4d))
4643 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4644 and ending bitfield = END. END must be greater than START. */
4646 static unsigned long
4647 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
4649 int bits
= end
- start
;
4654 return ((given
>> start
) & ((2ul << bits
) - 1));
4657 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4658 START:END and START2:END2. END/END2 must be greater than
4661 static unsigned long
4662 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
4663 unsigned int end
, unsigned int start2
,
4666 int bits
= end
- start
;
4667 int bits2
= end2
- start2
;
4668 unsigned long value
= 0;
4674 value
= arm_decode_field (given
, start
, end
);
4677 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
4681 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4682 This helps us decode instructions that change mnemonic depending on specific
4683 operand values/encodings. */
4686 is_mve_encoding_conflict (unsigned long given
,
4687 enum mve_instructions matched_insn
)
4689 switch (matched_insn
)
4692 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4698 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4700 if ((arm_decode_field (given
, 12, 12) == 0)
4701 && (arm_decode_field (given
, 0, 0) == 1))
4706 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4708 if (arm_decode_field (given
, 0, 3) == 0xd)
4712 case MVE_VPT_VEC_T1
:
4713 case MVE_VPT_VEC_T2
:
4714 case MVE_VPT_VEC_T3
:
4715 case MVE_VPT_VEC_T4
:
4716 case MVE_VPT_VEC_T5
:
4717 case MVE_VPT_VEC_T6
:
4718 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4720 if (arm_decode_field (given
, 20, 21) == 3)
4724 case MVE_VCMP_FP_T1
:
4725 if ((arm_decode_field (given
, 12, 12) == 0)
4726 && (arm_decode_field (given
, 0, 0) == 1))
4731 case MVE_VCMP_FP_T2
:
4732 if (arm_decode_field (given
, 0, 3) == 0xd)
4748 case MVE_VQDMULH_T3
:
4749 case MVE_VQRDMULH_T4
:
4755 case MVE_VCMP_VEC_T1
:
4756 case MVE_VCMP_VEC_T2
:
4757 case MVE_VCMP_VEC_T3
:
4758 case MVE_VCMP_VEC_T4
:
4759 case MVE_VCMP_VEC_T5
:
4760 case MVE_VCMP_VEC_T6
:
4761 if (arm_decode_field (given
, 20, 21) == 3)
4770 if (arm_decode_field (given
, 7, 8) == 3)
4777 if ((arm_decode_field (given
, 24, 24) == 0)
4778 && (arm_decode_field (given
, 21, 21) == 0))
4782 else if ((arm_decode_field (given
, 7, 8) == 3))
4790 if ((arm_decode_field (given
, 24, 24) == 0)
4791 && (arm_decode_field (given
, 21, 21) == 0))
4798 case MVE_VCVT_FP_FIX_VEC
:
4799 return (arm_decode_field (given
, 16, 21) & 0x38) == 0;
4804 unsigned long cmode
= arm_decode_field (given
, 8, 11);
4806 if ((cmode
& 1) == 0)
4808 else if ((cmode
& 0xc) == 0xc)
4816 unsigned long cmode
= arm_decode_field (given
, 8, 11);
4818 if ((cmode
& 9) == 1)
4820 else if ((cmode
& 5) == 1)
4822 else if ((cmode
& 0xe) == 0xe)
4828 case MVE_VMOV_IMM_TO_VEC
:
4829 if ((arm_decode_field (given
, 5, 5) == 1)
4830 && (arm_decode_field (given
, 8, 11) != 0xe))
4837 unsigned long size
= arm_decode_field (given
, 19, 20);
4838 if ((size
== 0) || (size
== 3))
4848 if (arm_decode_field (given
, 18, 19) == 3)
4854 case MVE_VRMLSLDAVH
:
4857 if (arm_decode_field (given
, 20, 22) == 7)
4862 case MVE_VRMLALDAVH
:
4863 if ((arm_decode_field (given
, 20, 22) & 6) == 6)
4870 if ((arm_decode_field (given
, 20, 21) == 3)
4871 || (arm_decode_field (given
, 1, 3) == 7))
4883 print_mve_vld_str_addr (struct disassemble_info
*info
,
4884 unsigned long given
,
4885 enum mve_instructions matched_insn
)
4887 void *stream
= info
->stream
;
4888 fprintf_ftype func
= info
->fprintf_func
;
4890 unsigned long p
, w
, gpr
, imm
, add
, mod_imm
;
4892 imm
= arm_decode_field (given
, 0, 6);
4895 switch (matched_insn
)
4899 gpr
= arm_decode_field (given
, 16, 18);
4904 gpr
= arm_decode_field (given
, 16, 18);
4910 gpr
= arm_decode_field (given
, 16, 19);
4916 gpr
= arm_decode_field (given
, 16, 19);
4922 gpr
= arm_decode_field (given
, 16, 19);
4929 p
= arm_decode_field (given
, 24, 24);
4930 w
= arm_decode_field (given
, 21, 21);
4932 add
= arm_decode_field (given
, 23, 23);
4936 /* Don't print anything for '+' as it is implied. */
4946 func (stream
, "[%s, #%s%lu]", arm_regnames
[gpr
], add_sub
, mod_imm
);
4947 /* Pre-indexed mode. */
4949 func (stream
, "[%s, #%s%lu]!", arm_regnames
[gpr
], add_sub
, mod_imm
);
4951 else if ((p
== 0) && (w
== 1))
4952 /* Post-index mode. */
4953 func (stream
, "[%s], #%s%lu", arm_regnames
[gpr
], add_sub
, mod_imm
);
4956 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
4957 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
4958 this encoding is undefined. */
4961 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
4962 enum mve_undefined
*undefined_code
)
4964 *undefined_code
= UNDEF_NONE
;
4966 switch (matched_insn
)
4969 if (arm_decode_field_multiple (given
, 5, 5, 22, 22) == 3)
4971 *undefined_code
= UNDEF_SIZE_3
;
4977 case MVE_VQDMULH_T1
:
4978 case MVE_VQRDMULH_T2
:
4982 if (arm_decode_field (given
, 20, 21) == 3)
4984 *undefined_code
= UNDEF_SIZE_3
;
4991 if (arm_decode_field (given
, 7, 8) == 3)
4993 *undefined_code
= UNDEF_SIZE_3
;
5000 if (arm_decode_field (given
, 7, 8) <= 1)
5002 *undefined_code
= UNDEF_SIZE_LE_1
;
5009 if ((arm_decode_field (given
, 7, 8) == 0))
5011 *undefined_code
= UNDEF_SIZE_0
;
5018 if ((arm_decode_field (given
, 7, 8) <= 1))
5020 *undefined_code
= UNDEF_SIZE_LE_1
;
5026 case MVE_VLDRB_GATHER_T1
:
5027 if (arm_decode_field (given
, 7, 8) == 3)
5029 *undefined_code
= UNDEF_SIZE_3
;
5032 else if ((arm_decode_field (given
, 28, 28) == 0)
5033 && (arm_decode_field (given
, 7, 8) == 0))
5035 *undefined_code
= UNDEF_NOT_UNS_SIZE_0
;
5041 case MVE_VLDRH_GATHER_T2
:
5042 if (arm_decode_field (given
, 7, 8) == 3)
5044 *undefined_code
= UNDEF_SIZE_3
;
5047 else if ((arm_decode_field (given
, 28, 28) == 0)
5048 && (arm_decode_field (given
, 7, 8) == 1))
5050 *undefined_code
= UNDEF_NOT_UNS_SIZE_1
;
5053 else if (arm_decode_field (given
, 7, 8) == 0)
5055 *undefined_code
= UNDEF_SIZE_0
;
5061 case MVE_VLDRW_GATHER_T3
:
5062 if (arm_decode_field (given
, 7, 8) != 2)
5064 *undefined_code
= UNDEF_SIZE_NOT_2
;
5067 else if (arm_decode_field (given
, 28, 28) == 0)
5069 *undefined_code
= UNDEF_NOT_UNSIGNED
;
5075 case MVE_VLDRD_GATHER_T4
:
5076 if (arm_decode_field (given
, 7, 8) != 3)
5078 *undefined_code
= UNDEF_SIZE_NOT_3
;
5081 else if (arm_decode_field (given
, 28, 28) == 0)
5083 *undefined_code
= UNDEF_NOT_UNSIGNED
;
5089 case MVE_VSTRB_SCATTER_T1
:
5090 if (arm_decode_field (given
, 7, 8) == 3)
5092 *undefined_code
= UNDEF_SIZE_3
;
5098 case MVE_VSTRH_SCATTER_T2
:
5100 unsigned long size
= arm_decode_field (given
, 7, 8);
5103 *undefined_code
= UNDEF_SIZE_3
;
5108 *undefined_code
= UNDEF_SIZE_0
;
5115 case MVE_VSTRW_SCATTER_T3
:
5116 if (arm_decode_field (given
, 7, 8) != 2)
5118 *undefined_code
= UNDEF_SIZE_NOT_2
;
5124 case MVE_VSTRD_SCATTER_T4
:
5125 if (arm_decode_field (given
, 7, 8) != 3)
5127 *undefined_code
= UNDEF_SIZE_NOT_3
;
5133 case MVE_VCVT_FP_FIX_VEC
:
5135 unsigned long imm6
= arm_decode_field (given
, 16, 21);
5136 if ((imm6
& 0x20) == 0)
5138 *undefined_code
= UNDEF_VCVT_IMM6
;
5142 if ((arm_decode_field (given
, 9, 9) == 0)
5143 && ((imm6
& 0x30) == 0x20))
5145 *undefined_code
= UNDEF_VCVT_FSI_IMM6
;
5152 case MVE_VCVT_BETWEEN_FP_INT
:
5153 case MVE_VCVT_FROM_FP_TO_INT
:
5155 unsigned long size
= arm_decode_field (given
, 18, 19);
5158 *undefined_code
= UNDEF_SIZE_0
;
5163 *undefined_code
= UNDEF_SIZE_3
;
5170 case MVE_VMOV_VEC_LANE_TO_GP
:
5172 unsigned long op1
= arm_decode_field (given
, 21, 22);
5173 unsigned long op2
= arm_decode_field (given
, 5, 6);
5174 unsigned long u
= arm_decode_field (given
, 23, 23);
5176 if ((op2
== 0) && (u
== 1))
5178 if ((op1
== 0) || (op1
== 1))
5180 *undefined_code
= UNDEF_BAD_U_OP1_OP2
;
5188 if ((op1
== 0) || (op1
== 1))
5190 *undefined_code
= UNDEF_BAD_OP1_OP2
;
5200 case MVE_VMOV_GP_TO_VEC_LANE
:
5201 if (arm_decode_field (given
, 5, 6) == 2)
5203 unsigned long op1
= arm_decode_field (given
, 21, 22);
5204 if ((op1
== 0) || (op1
== 1))
5206 *undefined_code
= UNDEF_BAD_OP1_OP2
;
5215 case MVE_VMOV_IMM_TO_VEC
:
5216 if (arm_decode_field (given
, 5, 5) == 0)
5218 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5220 if (((cmode
& 9) == 1) || ((cmode
& 5) == 1))
5222 *undefined_code
= UNDEF_OP_0_BAD_CMODE
;
5232 if (arm_decode_field (given
, 18, 19) == 2)
5234 *undefined_code
= UNDEF_SIZE_2
;
5240 case MVE_VRMLALDAVH
:
5241 case MVE_VMLADAV_T1
:
5242 case MVE_VMLADAV_T2
:
5244 if ((arm_decode_field (given
, 28, 28) == 1)
5245 && (arm_decode_field (given
, 12, 12) == 1))
5247 *undefined_code
= UNDEF_XCHG_UNS
;
5258 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
5259 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
5260 why this encoding is unpredictable. */
5263 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
5264 enum mve_unpredictable
*unpredictable_code
)
5266 *unpredictable_code
= UNPRED_NONE
;
5268 switch (matched_insn
)
5270 case MVE_VCMP_FP_T2
:
5272 if ((arm_decode_field (given
, 12, 12) == 0)
5273 && (arm_decode_field (given
, 5, 5) == 1))
5275 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
5281 case MVE_VPT_VEC_T4
:
5282 case MVE_VPT_VEC_T5
:
5283 case MVE_VPT_VEC_T6
:
5284 case MVE_VCMP_VEC_T4
:
5285 case MVE_VCMP_VEC_T5
:
5286 case MVE_VCMP_VEC_T6
:
5287 if (arm_decode_field (given
, 0, 3) == 0xd)
5289 *unpredictable_code
= UNPRED_R13
;
5297 unsigned long gpr
= arm_decode_field (given
, 12, 15);
5300 *unpredictable_code
= UNPRED_R13
;
5303 else if (gpr
== 0xf)
5305 *unpredictable_code
= UNPRED_R15
;
5316 case MVE_VQDMULH_T3
:
5317 case MVE_VQRDMULH_T4
:
5319 case MVE_VFMA_FP_SCALAR
:
5320 case MVE_VFMAS_FP_SCALAR
:
5324 unsigned long gpr
= arm_decode_field (given
, 0, 3);
5327 *unpredictable_code
= UNPRED_R13
;
5330 else if (gpr
== 0xf)
5332 *unpredictable_code
= UNPRED_R15
;
5342 unsigned long rn
= arm_decode_field (given
, 16, 19);
5344 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5346 *unpredictable_code
= UNPRED_R13_AND_WB
;
5352 *unpredictable_code
= UNPRED_R15
;
5356 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 6)
5358 *unpredictable_code
= UNPRED_Q_GT_6
;
5368 unsigned long rn
= arm_decode_field (given
, 16, 19);
5370 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5372 *unpredictable_code
= UNPRED_R13_AND_WB
;
5378 *unpredictable_code
= UNPRED_R15
;
5382 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 4)
5384 *unpredictable_code
= UNPRED_Q_GT_4
;
5398 unsigned long rn
= arm_decode_field (given
, 16, 19);
5400 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5402 *unpredictable_code
= UNPRED_R13_AND_WB
;
5407 *unpredictable_code
= UNPRED_R15
;
5414 case MVE_VLDRB_GATHER_T1
:
5415 if (arm_decode_field (given
, 0, 0) == 1)
5417 *unpredictable_code
= UNPRED_OS
;
5422 /* To handle common code with T2-T4 variants. */
5423 case MVE_VLDRH_GATHER_T2
:
5424 case MVE_VLDRW_GATHER_T3
:
5425 case MVE_VLDRD_GATHER_T4
:
5427 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5428 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5432 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
5436 if (arm_decode_field (given
, 16, 19) == 0xf)
5438 *unpredictable_code
= UNPRED_R15
;
5445 case MVE_VLDRW_GATHER_T5
:
5446 case MVE_VLDRD_GATHER_T6
:
5448 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5449 unsigned long qm
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5453 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
5460 case MVE_VSTRB_SCATTER_T1
:
5461 if (arm_decode_field (given
, 16, 19) == 0xf)
5463 *unpredictable_code
= UNPRED_R15
;
5466 else if (arm_decode_field (given
, 0, 0) == 1)
5468 *unpredictable_code
= UNPRED_OS
;
5474 case MVE_VSTRH_SCATTER_T2
:
5475 case MVE_VSTRW_SCATTER_T3
:
5476 case MVE_VSTRD_SCATTER_T4
:
5477 if (arm_decode_field (given
, 16, 19) == 0xf)
5479 *unpredictable_code
= UNPRED_R15
;
5485 case MVE_VMOV2_VEC_LANE_TO_GP
:
5486 case MVE_VMOV2_GP_TO_VEC_LANE
:
5487 case MVE_VCVT_BETWEEN_FP_INT
:
5488 case MVE_VCVT_FROM_FP_TO_INT
:
5490 unsigned long rt
= arm_decode_field (given
, 0, 3);
5491 unsigned long rt2
= arm_decode_field (given
, 16, 19);
5493 if ((rt
== 0xd) || (rt2
== 0xd))
5495 *unpredictable_code
= UNPRED_R13
;
5498 else if ((rt
== 0xf) || (rt2
== 0xf))
5500 *unpredictable_code
= UNPRED_R15
;
5505 *unpredictable_code
= UNPRED_GP_REGS_EQUAL
;
5512 case MVE_VMOV_HFP_TO_GP
:
5513 case MVE_VMOV_GP_TO_VEC_LANE
:
5514 case MVE_VMOV_VEC_LANE_TO_GP
:
5516 unsigned long rda
= arm_decode_field (given
, 12, 15);
5519 *unpredictable_code
= UNPRED_R13
;
5522 else if (rda
== 0xf)
5524 *unpredictable_code
= UNPRED_R15
;
5541 if (arm_decode_field (given
, 20, 21) == 2)
5543 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5544 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5545 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5547 if ((Qd
== Qn
) || (Qd
== Qm
))
5549 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
5560 case MVE_VQDMULL_T1
:
5566 if (arm_decode_field (given
, 28, 28) == 1)
5568 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5569 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5570 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5572 if ((Qd
== Qn
) || (Qd
== Qm
))
5574 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
5584 case MVE_VQDMULL_T2
:
5586 unsigned long gpr
= arm_decode_field (given
, 0, 3);
5589 *unpredictable_code
= UNPRED_R13
;
5592 else if (gpr
== 0xf)
5594 *unpredictable_code
= UNPRED_R15
;
5598 if (arm_decode_field (given
, 28, 28) == 1)
5601 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
5602 unsigned long Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5606 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
5617 case MVE_VRMLSLDAVH
:
5620 if (arm_decode_field (given
, 20, 22) == 6)
5622 *unpredictable_code
= UNPRED_R13
;
5630 if (arm_decode_field (given
, 1, 3) == 6)
5632 *unpredictable_code
= UNPRED_R13
;
5641 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5642 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5643 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 21) == 2)
5645 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
5654 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5655 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5656 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 20) == 1)
5658 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
5671 if (arm_decode_field (given
, 20, 20) == 1)
5673 Qda
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5674 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5675 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5677 if ((Qda
== Qn
) || (Qda
== Qm
))
5679 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
5696 print_mve_vmov_index (struct disassemble_info
*info
, unsigned long given
)
5698 unsigned long op1
= arm_decode_field (given
, 21, 22);
5699 unsigned long op2
= arm_decode_field (given
, 5, 6);
5700 unsigned long h
= arm_decode_field (given
, 16, 16);
5701 unsigned long index
, esize
, targetBeat
, idx
;
5702 void *stream
= info
->stream
;
5703 fprintf_ftype func
= info
->fprintf_func
;
5705 if ((op1
& 0x2) == 0x2)
5710 else if (((op1
& 0x2) == 0x0) && ((op2
& 0x1) == 0x1))
5715 else if (((op1
& 0x2) == 0) && ((op2
& 0x3) == 0))
5722 func (stream
, "<undefined index>");
5726 targetBeat
= (op1
& 0x1) | (h
<< 1);
5727 idx
= index
+ targetBeat
* (32/esize
);
5729 func (stream
, "%lu", idx
);
5732 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
5733 in length and integer of floating-point type. */
5735 print_simd_imm8 (struct disassemble_info
*info
, unsigned long given
,
5736 unsigned int ibit_loc
, const struct mopcode32
*insn
)
5739 int cmode
= (given
>> 8) & 0xf;
5740 int op
= (given
>> 5) & 0x1;
5741 unsigned long value
= 0, hival
= 0;
5745 void *stream
= info
->stream
;
5746 fprintf_ftype func
= info
->fprintf_func
;
5748 /* On Neon the 'i' bit is at bit 24, on mve it is
5750 bits
|= ((given
>> ibit_loc
) & 1) << 7;
5751 bits
|= ((given
>> 16) & 7) << 4;
5752 bits
|= ((given
>> 0) & 15) << 0;
5756 shift
= (cmode
>> 1) & 3;
5757 value
= (unsigned long) bits
<< (8 * shift
);
5760 else if (cmode
< 12)
5762 shift
= (cmode
>> 1) & 1;
5763 value
= (unsigned long) bits
<< (8 * shift
);
5766 else if (cmode
< 14)
5768 shift
= (cmode
& 1) + 1;
5769 value
= (unsigned long) bits
<< (8 * shift
);
5770 value
|= (1ul << (8 * shift
)) - 1;
5773 else if (cmode
== 14)
5777 /* Bit replication into bytes. */
5783 for (ix
= 7; ix
>= 0; ix
--)
5785 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
5787 value
= (value
<< 8) | mask
;
5789 hival
= (hival
<< 8) | mask
;
5795 /* Byte replication. */
5796 value
= (unsigned long) bits
;
5802 /* Floating point encoding. */
5805 value
= (unsigned long) (bits
& 0x7f) << 19;
5806 value
|= (unsigned long) (bits
& 0x80) << 24;
5807 tmp
= bits
& 0x40 ? 0x3c : 0x40;
5808 value
|= (unsigned long) tmp
<< 24;
5814 func (stream
, "<illegal constant %.8x:%x:%x>",
5820 // printU determines whether the immediate value should be printed as
5822 unsigned printU
= 0;
5823 switch (insn
->mve_op
)
5827 // We want this for instructions that don't have a 'signed' type
5831 case MVE_VMOV_IMM_TO_VEC
:
5838 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
5845 : "#%ld\t; 0x%.4lx", value
, value
);
5851 unsigned char valbytes
[4];
5854 /* Do this a byte at a time so we don't have to
5855 worry about the host's endianness. */
5856 valbytes
[0] = value
& 0xff;
5857 valbytes
[1] = (value
>> 8) & 0xff;
5858 valbytes
[2] = (value
>> 16) & 0xff;
5859 valbytes
[3] = (value
>> 24) & 0xff;
5861 floatformat_to_double
5862 (& floatformat_ieee_single_little
, valbytes
,
5865 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
5872 : "#%ld\t; 0x%.8lx",
5873 (long) (((value
& 0x80000000L
) != 0)
5875 ? value
| ~0xffffffffL
: value
),
5880 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
5890 print_mve_undefined (struct disassemble_info
*info
,
5891 enum mve_undefined undefined_code
)
5893 void *stream
= info
->stream
;
5894 fprintf_ftype func
= info
->fprintf_func
;
5896 func (stream
, "\t\tundefined instruction: ");
5898 switch (undefined_code
)
5901 func (stream
, "size equals zero");
5905 func (stream
, "size equals two");
5909 func (stream
, "size equals three");
5912 case UNDEF_SIZE_LE_1
:
5913 func (stream
, "size <= 1");
5916 case UNDEF_SIZE_NOT_2
:
5917 func (stream
, "size not equal to 2");
5920 case UNDEF_SIZE_NOT_3
:
5921 func (stream
, "size not equal to 3");
5924 case UNDEF_NOT_UNS_SIZE_0
:
5925 func (stream
, "not unsigned and size = zero");
5928 case UNDEF_NOT_UNS_SIZE_1
:
5929 func (stream
, "not unsigned and size = one");
5932 case UNDEF_NOT_UNSIGNED
:
5933 func (stream
, "not unsigned");
5936 case UNDEF_VCVT_IMM6
:
5937 func (stream
, "invalid imm6");
5940 case UNDEF_VCVT_FSI_IMM6
:
5941 func (stream
, "fsi = 0 and invalid imm6");
5944 case UNDEF_BAD_OP1_OP2
:
5945 func (stream
, "bad size with op2 = 2 and op1 = 0 or 1");
5948 case UNDEF_BAD_U_OP1_OP2
:
5949 func (stream
, "unsigned with op2 = 0 and op1 = 0 or 1");
5952 case UNDEF_OP_0_BAD_CMODE
:
5953 func (stream
, "op field equal 0 and bad cmode");
5956 case UNDEF_XCHG_UNS
:
5957 func (stream
, "exchange and unsigned together");
5967 print_mve_unpredictable (struct disassemble_info
*info
,
5968 enum mve_unpredictable unpredict_code
)
5970 void *stream
= info
->stream
;
5971 fprintf_ftype func
= info
->fprintf_func
;
5973 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
5975 switch (unpredict_code
)
5977 case UNPRED_IT_BLOCK
:
5978 func (stream
, "mve instruction in it block");
5981 case UNPRED_FCA_0_FCB_1
:
5982 func (stream
, "condition bits, fca = 0 and fcb = 1");
5986 func (stream
, "use of r13 (sp)");
5990 func (stream
, "use of r15 (pc)");
5994 func (stream
, "start register block > r4");
5998 func (stream
, "start register block > r6");
6001 case UNPRED_R13_AND_WB
:
6002 func (stream
, "use of r13 and write back");
6005 case UNPRED_Q_REGS_EQUAL
:
6007 "same vector register used for destination and other operand");
6011 func (stream
, "use of offset scaled");
6014 case UNPRED_GP_REGS_EQUAL
:
6015 func (stream
, "same general-purpose register used for both operands");
6018 case UNPRED_Q_REGS_EQ_AND_SIZE_1
:
6019 func (stream
, "use of identical q registers and size = 1");
6022 case UNPRED_Q_REGS_EQ_AND_SIZE_2
:
6023 func (stream
, "use of identical q registers and size = 1");
6031 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
6034 print_mve_register_blocks (struct disassemble_info
*info
,
6035 unsigned long given
,
6036 enum mve_instructions matched_insn
)
6038 void *stream
= info
->stream
;
6039 fprintf_ftype func
= info
->fprintf_func
;
6041 unsigned long q_reg_start
= arm_decode_field_multiple (given
,
6044 switch (matched_insn
)
6048 if (q_reg_start
<= 6)
6049 func (stream
, "{q%ld, q%ld}", q_reg_start
, q_reg_start
+ 1);
6051 func (stream
, "<illegal reg q%ld>", q_reg_start
);
6056 if (q_reg_start
<= 4)
6057 func (stream
, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start
,
6058 q_reg_start
+ 1, q_reg_start
+ 2,
6061 func (stream
, "<illegal reg q%ld>", q_reg_start
);
6070 print_mve_rounding_mode (struct disassemble_info
*info
,
6071 unsigned long given
,
6072 enum mve_instructions matched_insn
)
6074 void *stream
= info
->stream
;
6075 fprintf_ftype func
= info
->fprintf_func
;
6077 switch (matched_insn
)
6079 case MVE_VCVT_FROM_FP_TO_INT
:
6081 switch (arm_decode_field (given
, 8, 9))
6107 switch (arm_decode_field (given
, 7, 9))
6146 print_mve_vcvt_size (struct disassemble_info
*info
,
6147 unsigned long given
,
6148 enum mve_instructions matched_insn
)
6150 unsigned long mode
= 0;
6151 void *stream
= info
->stream
;
6152 fprintf_ftype func
= info
->fprintf_func
;
6154 switch (matched_insn
)
6156 case MVE_VCVT_FP_FIX_VEC
:
6158 mode
= (((given
& 0x200) >> 7)
6159 | ((given
& 0x10000000) >> 27)
6160 | ((given
& 0x100) >> 8));
6165 func (stream
, "f16.s16");
6169 func (stream
, "s16.f16");
6173 func (stream
, "f16.u16");
6177 func (stream
, "u16.f16");
6181 func (stream
, "f32.s32");
6185 func (stream
, "s32.f32");
6189 func (stream
, "f32.u32");
6193 func (stream
, "u32.f32");
6201 case MVE_VCVT_BETWEEN_FP_INT
:
6203 unsigned long size
= arm_decode_field (given
, 18, 19);
6204 unsigned long op
= arm_decode_field (given
, 7, 8);
6211 func (stream
, "f16.s16");
6215 func (stream
, "f16.u16");
6219 func (stream
, "s16.f16");
6223 func (stream
, "u16.f16");
6235 func (stream
, "f32.s32");
6239 func (stream
, "f32.u32");
6243 func (stream
, "s32.f32");
6247 func (stream
, "u32.f32");
6254 case MVE_VCVT_FP_HALF_FP
:
6256 unsigned long op
= arm_decode_field (given
, 28, 28);
6258 func (stream
, "f16.f32");
6260 func (stream
, "f32.f16");
6264 case MVE_VCVT_FROM_FP_TO_INT
:
6266 unsigned long size
= arm_decode_field_multiple (given
, 7, 7, 18, 19);
6271 func (stream
, "s16.f16");
6275 func (stream
, "u16.f16");
6279 func (stream
, "s32.f32");
6283 func (stream
, "u32.f32");
6298 print_mve_rotate (struct disassemble_info
*info
, unsigned long rot
,
6299 unsigned long rot_width
)
6301 void *stream
= info
->stream
;
6302 fprintf_ftype func
= info
->fprintf_func
;
6309 func (stream
, "90");
6312 func (stream
, "270");
6318 else if (rot_width
== 2)
6326 func (stream
, "90");
6329 func (stream
, "180");
6332 func (stream
, "270");
6341 print_instruction_predicate (struct disassemble_info
*info
)
6343 void *stream
= info
->stream
;
6344 fprintf_ftype func
= info
->fprintf_func
;
6346 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
6348 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
6353 print_mve_size (struct disassemble_info
*info
,
6355 enum mve_instructions matched_insn
)
6357 void *stream
= info
->stream
;
6358 fprintf_ftype func
= info
->fprintf_func
;
6360 switch (matched_insn
)
6364 case MVE_VCMP_VEC_T1
:
6365 case MVE_VCMP_VEC_T2
:
6366 case MVE_VCMP_VEC_T3
:
6367 case MVE_VCMP_VEC_T4
:
6368 case MVE_VCMP_VEC_T5
:
6369 case MVE_VCMP_VEC_T6
:
6381 case MVE_VLDRB_GATHER_T1
:
6382 case MVE_VLDRH_GATHER_T2
:
6383 case MVE_VLDRW_GATHER_T3
:
6384 case MVE_VLDRD_GATHER_T4
:
6388 case MVE_VPT_VEC_T1
:
6389 case MVE_VPT_VEC_T2
:
6390 case MVE_VPT_VEC_T3
:
6391 case MVE_VPT_VEC_T4
:
6392 case MVE_VPT_VEC_T5
:
6393 case MVE_VPT_VEC_T6
:
6402 case MVE_VQDMULH_T1
:
6403 case MVE_VQRDMULH_T2
:
6404 case MVE_VQDMULH_T3
:
6405 case MVE_VQRDMULH_T4
:
6410 case MVE_VSTRB_SCATTER_T1
:
6411 case MVE_VSTRH_SCATTER_T2
:
6412 case MVE_VSTRW_SCATTER_T3
:
6416 func (stream
, "%s", mve_vec_sizename
[size
]);
6418 func (stream
, "<undef size>");
6421 case MVE_VCMP_FP_T1
:
6422 case MVE_VCMP_FP_T2
:
6423 case MVE_VFMA_FP_SCALAR
:
6426 case MVE_VFMAS_FP_SCALAR
:
6430 func (stream
, "32");
6432 func (stream
, "16");
6438 case MVE_VMLADAV_T1
:
6440 case MVE_VMLSDAV_T1
:
6443 case MVE_VQDMULL_T1
:
6444 case MVE_VQDMULL_T2
:
6448 func (stream
, "16");
6450 func (stream
, "32");
6457 func (stream
, "16");
6464 func (stream
, "32");
6467 func (stream
, "16");
6477 case MVE_VMOV_GP_TO_VEC_LANE
:
6478 case MVE_VMOV_VEC_LANE_TO_GP
:
6482 func (stream
, "32");
6487 func (stream
, "16");
6490 case 8: case 9: case 10: case 11:
6491 case 12: case 13: case 14: case 15:
6500 case MVE_VMOV_IMM_TO_VEC
:
6503 case 0: case 4: case 8:
6504 case 12: case 24: case 26:
6505 func (stream
, "i32");
6508 func (stream
, "i16");
6511 func (stream
, "i8");
6514 func (stream
, "i64");
6517 func (stream
, "f32");
6524 case MVE_VMULL_POLY
:
6526 func (stream
, "p8");
6528 func (stream
, "p16");
6534 case 0: case 2: case 4:
6535 case 6: case 12: case 13:
6536 func (stream
, "32");
6540 func (stream
, "16");
6554 func (stream
, "32");
6558 func (stream
, "16");
6572 print_vec_condition (struct disassemble_info
*info
, long given
,
6573 enum mve_instructions matched_insn
)
6575 void *stream
= info
->stream
;
6576 fprintf_ftype func
= info
->fprintf_func
;
6579 switch (matched_insn
)
6582 case MVE_VCMP_FP_T1
:
6583 vec_cond
= (((given
& 0x1000) >> 10)
6584 | ((given
& 1) << 1)
6585 | ((given
& 0x0080) >> 7));
6586 func (stream
, "%s",vec_condnames
[vec_cond
]);
6590 case MVE_VCMP_FP_T2
:
6591 vec_cond
= (((given
& 0x1000) >> 10)
6592 | ((given
& 0x0020) >> 4)
6593 | ((given
& 0x0080) >> 7));
6594 func (stream
, "%s",vec_condnames
[vec_cond
]);
6597 case MVE_VPT_VEC_T1
:
6598 case MVE_VCMP_VEC_T1
:
6599 vec_cond
= (given
& 0x0080) >> 7;
6600 func (stream
, "%s",vec_condnames
[vec_cond
]);
6603 case MVE_VPT_VEC_T2
:
6604 case MVE_VCMP_VEC_T2
:
6605 vec_cond
= 2 | ((given
& 0x0080) >> 7);
6606 func (stream
, "%s",vec_condnames
[vec_cond
]);
6609 case MVE_VPT_VEC_T3
:
6610 case MVE_VCMP_VEC_T3
:
6611 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
6612 func (stream
, "%s",vec_condnames
[vec_cond
]);
6615 case MVE_VPT_VEC_T4
:
6616 case MVE_VCMP_VEC_T4
:
6617 vec_cond
= (given
& 0x0080) >> 7;
6618 func (stream
, "%s",vec_condnames
[vec_cond
]);
6621 case MVE_VPT_VEC_T5
:
6622 case MVE_VCMP_VEC_T5
:
6623 vec_cond
= 2 | ((given
& 0x0080) >> 7);
6624 func (stream
, "%s",vec_condnames
[vec_cond
]);
6627 case MVE_VPT_VEC_T6
:
6628 case MVE_VCMP_VEC_T6
:
6629 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
6630 func (stream
, "%s",vec_condnames
[vec_cond
]);
6645 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
6646 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
6647 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
6648 #define PRE_BIT_SET (given & (1 << P_BIT))
6651 /* Print one coprocessor instruction on INFO->STREAM.
6652 Return TRUE if the instuction matched, FALSE if this is not a
6653 recognised coprocessor instruction. */
6656 print_insn_coprocessor (bfd_vma pc
,
6657 struct disassemble_info
*info
,
6661 const struct sopcode32
*insn
;
6662 void *stream
= info
->stream
;
6663 fprintf_ftype func
= info
->fprintf_func
;
6665 unsigned long value
= 0;
6668 struct arm_private_data
*private_data
= info
->private_data
;
6669 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
6670 arm_feature_set arm_ext_v8_1m_main
=
6671 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
6673 allowed_arches
= private_data
->features
;
6675 for (insn
= coprocessor_opcodes
; insn
->assembler
; insn
++)
6677 unsigned long u_reg
= 16;
6678 bfd_boolean is_unpredictable
= FALSE
;
6679 signed long value_in_comment
= 0;
6682 if (ARM_FEATURE_ZERO (insn
->arch
))
6683 switch (insn
->value
)
6685 case SENTINEL_IWMMXT_START
:
6686 if (info
->mach
!= bfd_mach_arm_XScale
6687 && info
->mach
!= bfd_mach_arm_iWMMXt
6688 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
6691 while ((! ARM_FEATURE_ZERO (insn
->arch
))
6692 && insn
->value
!= SENTINEL_IWMMXT_END
);
6695 case SENTINEL_IWMMXT_END
:
6698 case SENTINEL_GENERIC_START
:
6699 allowed_arches
= private_data
->features
;
6707 value
= insn
->value
;
6708 cp_num
= (given
>> 8) & 0xf;
6712 /* The high 4 bits are 0xe for Arm conditional instructions, and
6713 0xe for arm unconditional instructions. The rest of the
6714 encoding is the same. */
6716 value
|= 0xe0000000;
6724 /* Only match unconditional instuctions against unconditional
6726 if ((given
& 0xf0000000) == 0xf0000000)
6733 cond
= (given
>> 28) & 0xf;
6739 if ((insn
->isa
== T32
&& !thumb
)
6740 || (insn
->isa
== ARM
&& thumb
))
6743 if ((given
& mask
) != value
)
6746 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
6749 if (insn
->value
== 0xfe000010 /* mcr2 */
6750 || insn
->value
== 0xfe100010 /* mrc2 */
6751 || insn
->value
== 0xfc100000 /* ldc2 */
6752 || insn
->value
== 0xfc000000) /* stc2 */
6754 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
6755 is_unpredictable
= TRUE
;
6757 /* Armv8.1-M Mainline FP & MVE instructions. */
6758 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
6759 && !ARM_CPU_IS_ANY (allowed_arches
)
6760 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
6764 else if (insn
->value
== 0x0e000000 /* cdp */
6765 || insn
->value
== 0xfe000000 /* cdp2 */
6766 || insn
->value
== 0x0e000010 /* mcr */
6767 || insn
->value
== 0x0e100010 /* mrc */
6768 || insn
->value
== 0x0c100000 /* ldc */
6769 || insn
->value
== 0x0c000000) /* stc */
6771 /* Floating-point instructions. */
6772 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
6775 /* Armv8.1-M Mainline FP & MVE instructions. */
6776 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
6777 && !ARM_CPU_IS_ANY (allowed_arches
)
6778 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
6781 else if ((insn
->value
== 0xec100f80 /* vldr (system register) */
6782 || insn
->value
== 0xec000f80) /* vstr (system register) */
6783 && arm_decode_field (given
, 24, 24) == 0
6784 && arm_decode_field (given
, 21, 21) == 0)
6785 /* If the P and W bits are both 0 then these encodings match the MVE
6786 VLDR and VSTR instructions, these are in a different table, so we
6787 don't let it match here. */
6790 for (c
= insn
->assembler
; *c
; c
++)
6794 const char mod
= *++c
;
6798 func (stream
, "%%");
6804 int rn
= (given
>> 16) & 0xf;
6805 bfd_vma offset
= given
& 0xff;
6808 offset
= given
& 0x7f;
6810 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
6812 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
6814 /* Not unindexed. The offset is scaled. */
6816 /* vldr.16/vstr.16 will shift the address
6817 left by 1 bit only. */
6818 offset
= offset
* 2;
6820 offset
= offset
* 4;
6822 if (NEGATIVE_BIT_SET
)
6825 value_in_comment
= offset
;
6831 func (stream
, ", #%d]%s",
6833 WRITEBACK_BIT_SET
? "!" : "");
6834 else if (NEGATIVE_BIT_SET
)
6835 func (stream
, ", #-0]");
6843 if (WRITEBACK_BIT_SET
)
6846 func (stream
, ", #%d", (int) offset
);
6847 else if (NEGATIVE_BIT_SET
)
6848 func (stream
, ", #-0");
6852 func (stream
, ", {%s%d}",
6853 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
6855 value_in_comment
= offset
;
6858 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
6860 func (stream
, "\t; ");
6861 /* For unaligned PCs, apply off-by-alignment
6863 info
->print_address_func (offset
+ pc
6864 + info
->bytes_per_chunk
* 2
6873 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
6874 int offset
= (given
>> 1) & 0x3f;
6877 func (stream
, "{d%d}", regno
);
6878 else if (regno
+ offset
> 32)
6879 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
6881 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
6887 bfd_boolean single
= ((given
>> 8) & 1) == 0;
6888 char reg_prefix
= single
? 's' : 'd';
6889 int Dreg
= (given
>> 22) & 0x1;
6890 int Vdreg
= (given
>> 12) & 0xf;
6891 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
6892 : ((Dreg
<< 4) | Vdreg
);
6893 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
6894 int maxreg
= single
? 31 : 15;
6895 int topreg
= reg
+ num
- 1;
6898 func (stream
, "{VPR}");
6900 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
6901 else if (topreg
> maxreg
)
6902 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
6903 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
6905 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
6906 reg_prefix
, topreg
);
6911 if (cond
!= COND_UNCOND
)
6912 is_unpredictable
= TRUE
;
6916 if (cond
!= COND_UNCOND
&& cp_num
== 9)
6917 is_unpredictable
= TRUE
;
6919 func (stream
, "%s", arm_conditional
[cond
]);
6923 /* Print a Cirrus/DSP shift immediate. */
6924 /* Immediates are 7bit signed ints with bits 0..3 in
6925 bits 0..3 of opcode and bits 4..6 in bits 5..7
6930 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
6932 /* Is ``imm'' a negative number? */
6936 func (stream
, "%d", imm
);
6944 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
6949 func (stream
, "FPSCR");
6952 func (stream
, "FPSCR_nzcvqc");
6955 func (stream
, "VPR");
6958 func (stream
, "P0");
6961 func (stream
, "FPCXTNS");
6964 func (stream
, "FPCXTS");
6967 func (stream
, "<invalid reg %lu>", regno
);
6974 switch (given
& 0x00408000)
6991 switch (given
& 0x00080080)
7003 func (stream
, _("<illegal precision>"));
7009 switch (given
& 0x00408000)
7027 switch (given
& 0x60)
7043 case '0': case '1': case '2': case '3': case '4':
7044 case '5': case '6': case '7': case '8': case '9':
7048 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
7054 is_unpredictable
= TRUE
;
7059 /* Eat the 'u' character. */
7063 is_unpredictable
= TRUE
;
7066 func (stream
, "%s", arm_regnames
[value
]);
7069 if (given
& (1 << 6))
7073 func (stream
, "d%ld", value
);
7078 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
7080 func (stream
, "q%ld", value
>> 1);
7083 func (stream
, "%ld", value
);
7084 value_in_comment
= value
;
7088 /* Converts immediate 8 bit back to float value. */
7089 unsigned floatVal
= (value
& 0x80) << 24
7090 | (value
& 0x3F) << 19
7091 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
7093 /* Quarter float have a maximum value of 31.0.
7094 Get floating point value multiplied by 1e7.
7095 The maximum value stays in limit of a 32-bit int. */
7097 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
7098 (16 + (value
& 0xF));
7100 if (!(decVal
% 1000000))
7101 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
7102 floatVal
, value
& 0x80 ? '-' : ' ',
7104 decVal
% 10000000 / 1000000);
7105 else if (!(decVal
% 10000))
7106 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
7107 floatVal
, value
& 0x80 ? '-' : ' ',
7109 decVal
% 10000000 / 10000);
7111 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
7112 floatVal
, value
& 0x80 ? '-' : ' ',
7113 decVal
/ 10000000, decVal
% 10000000);
7118 int from
= (given
& (1 << 7)) ? 32 : 16;
7119 func (stream
, "%ld", from
- value
);
7125 func (stream
, "#%s", arm_fp_const
[value
& 7]);
7127 func (stream
, "f%ld", value
);
7132 func (stream
, "%s", iwmmxt_wwnames
[value
]);
7134 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
7138 func (stream
, "%s", iwmmxt_regnames
[value
]);
7141 func (stream
, "%s", iwmmxt_cregnames
[value
]);
7145 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
7152 func (stream
, "eq");
7156 func (stream
, "vs");
7160 func (stream
, "ge");
7164 func (stream
, "gt");
7168 func (stream
, "??");
7176 func (stream
, "%c", *c
);
7180 if (value
== ((1ul << width
) - 1))
7181 func (stream
, "%c", *c
);
7184 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
7196 int single
= *c
++ == 'y';
7201 case '4': /* Sm pair */
7202 case '0': /* Sm, Dm */
7203 regno
= given
& 0x0000000f;
7207 regno
+= (given
>> 5) & 1;
7210 regno
+= ((given
>> 5) & 1) << 4;
7213 case '1': /* Sd, Dd */
7214 regno
= (given
>> 12) & 0x0000000f;
7218 regno
+= (given
>> 22) & 1;
7221 regno
+= ((given
>> 22) & 1) << 4;
7224 case '2': /* Sn, Dn */
7225 regno
= (given
>> 16) & 0x0000000f;
7229 regno
+= (given
>> 7) & 1;
7232 regno
+= ((given
>> 7) & 1) << 4;
7235 case '3': /* List */
7237 regno
= (given
>> 12) & 0x0000000f;
7241 regno
+= (given
>> 22) & 1;
7244 regno
+= ((given
>> 22) & 1) << 4;
7251 func (stream
, "%c%d", single
? 's' : 'd', regno
);
7255 int count
= given
& 0xff;
7262 func (stream
, "-%c%d",
7270 func (stream
, ", %c%d", single
? 's' : 'd',
7276 switch (given
& 0x00400100)
7278 case 0x00000000: func (stream
, "b"); break;
7279 case 0x00400000: func (stream
, "h"); break;
7280 case 0x00000100: func (stream
, "w"); break;
7281 case 0x00400100: func (stream
, "d"); break;
7289 /* given (20, 23) | given (0, 3) */
7290 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
7291 func (stream
, "%d", (int) value
);
7296 /* This is like the 'A' operator, except that if
7297 the width field "M" is zero, then the offset is
7298 *not* multiplied by four. */
7300 int offset
= given
& 0xff;
7301 int multiplier
= (given
& 0x00000100) ? 4 : 1;
7303 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
7307 value_in_comment
= offset
* multiplier
;
7308 if (NEGATIVE_BIT_SET
)
7309 value_in_comment
= - value_in_comment
;
7315 func (stream
, ", #%s%d]%s",
7316 NEGATIVE_BIT_SET
? "-" : "",
7317 offset
* multiplier
,
7318 WRITEBACK_BIT_SET
? "!" : "");
7320 func (stream
, "], #%s%d",
7321 NEGATIVE_BIT_SET
? "-" : "",
7322 offset
* multiplier
);
7331 int imm4
= (given
>> 4) & 0xf;
7332 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
7333 int ubit
= ! NEGATIVE_BIT_SET
;
7334 const char *rm
= arm_regnames
[given
& 0xf];
7335 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
7341 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
7343 func (stream
, ", lsl #%d", imm4
);
7350 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
7352 func (stream
, ", lsl #%d", imm4
);
7354 if (puw_bits
== 5 || puw_bits
== 7)
7359 func (stream
, "INVALID");
7367 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
7368 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
7377 func (stream
, "%c", *c
);
7380 if (value_in_comment
> 32 || value_in_comment
< -16)
7381 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
7383 if (is_unpredictable
)
7384 func (stream
, UNPREDICTABLE_INSTRUCTION
);
7391 /* Decodes and prints ARM addressing modes. Returns the offset
7392 used in the address, if any, if it is worthwhile printing the
7393 offset as a hexadecimal value in a comment at the end of the
7394 line of disassembly. */
7397 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
7399 void *stream
= info
->stream
;
7400 fprintf_ftype func
= info
->fprintf_func
;
7403 if (((given
& 0x000f0000) == 0x000f0000)
7404 && ((given
& 0x02000000) == 0))
7406 offset
= given
& 0xfff;
7408 func (stream
, "[pc");
7412 /* Pre-indexed. Elide offset of positive zero when
7414 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
7415 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7417 if (NEGATIVE_BIT_SET
)
7422 /* Cope with the possibility of write-back
7423 being used. Probably a very dangerous thing
7424 for the programmer to do, but who are we to
7426 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
7428 else /* Post indexed. */
7430 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7432 /* Ie ignore the offset. */
7436 func (stream
, "\t; ");
7437 info
->print_address_func (offset
, info
);
7442 func (stream
, "[%s",
7443 arm_regnames
[(given
>> 16) & 0xf]);
7447 if ((given
& 0x02000000) == 0)
7449 /* Elide offset of positive zero when non-writeback. */
7450 offset
= given
& 0xfff;
7451 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
7452 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7456 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
7457 arm_decode_shift (given
, func
, stream
, TRUE
);
7460 func (stream
, "]%s",
7461 WRITEBACK_BIT_SET
? "!" : "");
7465 if ((given
& 0x02000000) == 0)
7467 /* Always show offset. */
7468 offset
= given
& 0xfff;
7469 func (stream
, "], #%s%d",
7470 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7474 func (stream
, "], %s",
7475 NEGATIVE_BIT_SET
? "-" : "");
7476 arm_decode_shift (given
, func
, stream
, TRUE
);
7479 if (NEGATIVE_BIT_SET
)
7483 return (signed long) offset
;
7486 /* Print one neon instruction on INFO->STREAM.
7487 Return TRUE if the instuction matched, FALSE if this is not a
7488 recognised neon instruction. */
7491 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
7493 const struct opcode32
*insn
;
7494 void *stream
= info
->stream
;
7495 fprintf_ftype func
= info
->fprintf_func
;
7499 if ((given
& 0xef000000) == 0xef000000)
7501 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
7502 unsigned long bit28
= given
& (1 << 28);
7504 given
&= 0x00ffffff;
7506 given
|= 0xf3000000;
7508 given
|= 0xf2000000;
7510 else if ((given
& 0xff000000) == 0xf9000000)
7511 given
^= 0xf9000000 ^ 0xf4000000;
7512 /* vdup is also a valid neon instruction. */
7513 else if ((given
& 0xff910f5f) != 0xee800b10)
7517 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
7519 if ((given
& insn
->mask
) == insn
->value
)
7521 signed long value_in_comment
= 0;
7522 bfd_boolean is_unpredictable
= FALSE
;
7525 for (c
= insn
->assembler
; *c
; c
++)
7532 func (stream
, "%%");
7536 if (thumb
&& ifthen_state
)
7537 is_unpredictable
= TRUE
;
7541 if (thumb
&& ifthen_state
)
7542 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
7547 static const unsigned char enc
[16] =
7549 0x4, 0x14, /* st4 0,1 */
7561 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
7562 int rn
= ((given
>> 16) & 0xf);
7563 int rm
= ((given
>> 0) & 0xf);
7564 int align
= ((given
>> 4) & 0x3);
7565 int type
= ((given
>> 8) & 0xf);
7566 int n
= enc
[type
] & 0xf;
7567 int stride
= (enc
[type
] >> 4) + 1;
7572 for (ix
= 0; ix
!= n
; ix
++)
7573 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
7575 func (stream
, "d%d", rd
);
7577 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
7578 func (stream
, "}, [%s", arm_regnames
[rn
]);
7580 func (stream
, " :%d", 32 << align
);
7585 func (stream
, ", %s", arm_regnames
[rm
]);
7591 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
7592 int rn
= ((given
>> 16) & 0xf);
7593 int rm
= ((given
>> 0) & 0xf);
7594 int idx_align
= ((given
>> 4) & 0xf);
7596 int size
= ((given
>> 10) & 0x3);
7597 int idx
= idx_align
>> (size
+ 1);
7598 int length
= ((given
>> 8) & 3) + 1;
7602 if (length
> 1 && size
> 0)
7603 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
7609 int amask
= (1 << size
) - 1;
7610 if ((idx_align
& (1 << size
)) != 0)
7614 if ((idx_align
& amask
) == amask
)
7616 else if ((idx_align
& amask
) != 0)
7623 if (size
== 2 && (idx_align
& 2) != 0)
7625 align
= (idx_align
& 1) ? 16 << size
: 0;
7629 if ((size
== 2 && (idx_align
& 3) != 0)
7630 || (idx_align
& 1) != 0)
7637 if ((idx_align
& 3) == 3)
7639 align
= (idx_align
& 3) * 64;
7642 align
= (idx_align
& 1) ? 32 << size
: 0;
7650 for (i
= 0; i
< length
; i
++)
7651 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
7652 rd
+ i
* stride
, idx
);
7653 func (stream
, "}, [%s", arm_regnames
[rn
]);
7655 func (stream
, " :%d", align
);
7660 func (stream
, ", %s", arm_regnames
[rm
]);
7666 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
7667 int rn
= ((given
>> 16) & 0xf);
7668 int rm
= ((given
>> 0) & 0xf);
7669 int align
= ((given
>> 4) & 0x1);
7670 int size
= ((given
>> 6) & 0x3);
7671 int type
= ((given
>> 8) & 0x3);
7673 int stride
= ((given
>> 5) & 0x1);
7676 if (stride
&& (n
== 1))
7683 for (ix
= 0; ix
!= n
; ix
++)
7684 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
7686 func (stream
, "d%d[]", rd
);
7688 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
7689 func (stream
, "}, [%s", arm_regnames
[rn
]);
7692 align
= (8 * (type
+ 1)) << size
;
7694 align
= (size
> 1) ? align
>> 1 : align
;
7695 if (type
== 2 || (type
== 0 && !size
))
7696 func (stream
, " :<bad align %d>", align
);
7698 func (stream
, " :%d", align
);
7704 func (stream
, ", %s", arm_regnames
[rm
]);
7710 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
7711 int size
= (given
>> 20) & 3;
7712 int reg
= raw_reg
& ((4 << size
) - 1);
7713 int ix
= raw_reg
>> size
>> 2;
7715 func (stream
, "d%d[%d]", reg
, ix
);
7720 /* Neon encoded constant for mov, mvn, vorr, vbic. */
7723 int cmode
= (given
>> 8) & 0xf;
7724 int op
= (given
>> 5) & 0x1;
7725 unsigned long value
= 0, hival
= 0;
7730 bits
|= ((given
>> 24) & 1) << 7;
7731 bits
|= ((given
>> 16) & 7) << 4;
7732 bits
|= ((given
>> 0) & 15) << 0;
7736 shift
= (cmode
>> 1) & 3;
7737 value
= (unsigned long) bits
<< (8 * shift
);
7740 else if (cmode
< 12)
7742 shift
= (cmode
>> 1) & 1;
7743 value
= (unsigned long) bits
<< (8 * shift
);
7746 else if (cmode
< 14)
7748 shift
= (cmode
& 1) + 1;
7749 value
= (unsigned long) bits
<< (8 * shift
);
7750 value
|= (1ul << (8 * shift
)) - 1;
7753 else if (cmode
== 14)
7757 /* Bit replication into bytes. */
7763 for (ix
= 7; ix
>= 0; ix
--)
7765 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
7767 value
= (value
<< 8) | mask
;
7769 hival
= (hival
<< 8) | mask
;
7775 /* Byte replication. */
7776 value
= (unsigned long) bits
;
7782 /* Floating point encoding. */
7785 value
= (unsigned long) (bits
& 0x7f) << 19;
7786 value
|= (unsigned long) (bits
& 0x80) << 24;
7787 tmp
= bits
& 0x40 ? 0x3c : 0x40;
7788 value
|= (unsigned long) tmp
<< 24;
7794 func (stream
, "<illegal constant %.8x:%x:%x>",
7802 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
7806 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
7812 unsigned char valbytes
[4];
7815 /* Do this a byte at a time so we don't have to
7816 worry about the host's endianness. */
7817 valbytes
[0] = value
& 0xff;
7818 valbytes
[1] = (value
>> 8) & 0xff;
7819 valbytes
[2] = (value
>> 16) & 0xff;
7820 valbytes
[3] = (value
>> 24) & 0xff;
7822 floatformat_to_double
7823 (& floatformat_ieee_single_little
, valbytes
,
7826 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
7830 func (stream
, "#%ld\t; 0x%.8lx",
7831 (long) (((value
& 0x80000000L
) != 0)
7832 ? value
| ~0xffffffffL
: value
),
7837 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
7848 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
7849 int num
= (given
>> 8) & 0x3;
7852 func (stream
, "{d%d}", regno
);
7853 else if (num
+ regno
>= 32)
7854 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
7856 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
7861 case '0': case '1': case '2': case '3': case '4':
7862 case '5': case '6': case '7': case '8': case '9':
7865 unsigned long value
;
7867 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
7872 func (stream
, "%s", arm_regnames
[value
]);
7875 func (stream
, "%ld", value
);
7876 value_in_comment
= value
;
7879 func (stream
, "%ld", (1ul << width
) - value
);
7885 /* Various width encodings. */
7887 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
7892 if (*c
>= '0' && *c
<= '9')
7894 else if (*c
>= 'a' && *c
<= 'f')
7895 limit
= *c
- 'a' + 10;
7901 if (value
< low
|| value
> high
)
7902 func (stream
, "<illegal width %d>", base
<< value
);
7904 func (stream
, "%d", base
<< value
);
7908 if (given
& (1 << 6))
7912 func (stream
, "d%ld", value
);
7917 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
7919 func (stream
, "q%ld", value
>> 1);
7925 func (stream
, "%c", *c
);
7929 if (value
== ((1ul << width
) - 1))
7930 func (stream
, "%c", *c
);
7933 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
7947 func (stream
, "%c", *c
);
7950 if (value_in_comment
> 32 || value_in_comment
< -16)
7951 func (stream
, "\t; 0x%lx", value_in_comment
);
7953 if (is_unpredictable
)
7954 func (stream
, UNPREDICTABLE_INSTRUCTION
);
7962 /* Print one mve instruction on INFO->STREAM.
7963 Return TRUE if the instuction matched, FALSE if this is not a
7964 recognised mve instruction. */
7967 print_insn_mve (struct disassemble_info
*info
, long given
)
7969 const struct mopcode32
*insn
;
7970 void *stream
= info
->stream
;
7971 fprintf_ftype func
= info
->fprintf_func
;
7973 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
7975 if (((given
& insn
->mask
) == insn
->value
)
7976 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
7978 signed long value_in_comment
= 0;
7979 bfd_boolean is_unpredictable
= FALSE
;
7980 bfd_boolean is_undefined
= FALSE
;
7982 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
7983 enum mve_undefined undefined_cond
= UNDEF_NONE
;
7985 /* Most vector mve instruction are illegal in a it block.
7986 There are a few exceptions; check for them. */
7987 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
7989 is_unpredictable
= TRUE
;
7990 unpredictable_cond
= UNPRED_IT_BLOCK
;
7992 else if (is_mve_unpredictable (given
, insn
->mve_op
,
7993 &unpredictable_cond
))
7994 is_unpredictable
= TRUE
;
7996 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
7997 is_undefined
= TRUE
;
7999 for (c
= insn
->assembler
; *c
; c
++)
8006 func (stream
, "%%");
8010 /* Don't print anything for '+' as it is implied. */
8011 if (arm_decode_field (given
, 23, 23) == 0)
8017 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8021 print_mve_vld_str_addr (info
, given
, insn
->mve_op
);
8026 long mve_mask
= mve_extract_pred_mask (given
);
8027 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
8032 print_vec_condition (info
, given
, insn
->mve_op
);
8036 if (arm_decode_field (given
, 0, 0) == 1)
8039 = arm_decode_field (given
, 4, 4)
8040 | (arm_decode_field (given
, 6, 6) << 1);
8042 func (stream
, ", uxtw #%lu", size
);
8047 print_mve_rounding_mode (info
, given
, insn
->mve_op
);
8051 print_mve_vcvt_size (info
, given
, insn
->mve_op
);
8056 unsigned long op1
= arm_decode_field (given
, 21, 22);
8058 if ((insn
->mve_op
== MVE_VMOV_VEC_LANE_TO_GP
))
8060 /* Check for signed. */
8061 if (arm_decode_field (given
, 23, 23) == 0)
8063 /* We don't print 's' for S32. */
8064 if ((arm_decode_field (given
, 5, 6) == 0)
8065 && ((op1
== 0) || (op1
== 1)))
8075 if (arm_decode_field (given
, 28, 28) == 0)
8084 print_instruction_predicate (info
);
8088 if (arm_decode_field (given
, 21, 21) == 1)
8093 print_mve_register_blocks (info
, given
, insn
->mve_op
);
8097 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
8099 print_simd_imm8 (info
, given
, 28, insn
);
8103 print_mve_vmov_index (info
, given
);
8107 if (arm_decode_field (given
, 12, 12) == 0)
8114 if (arm_decode_field (given
, 12, 12) == 1)
8118 case '0': case '1': case '2': case '3': case '4':
8119 case '5': case '6': case '7': case '8': case '9':
8122 unsigned long value
;
8124 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8130 is_unpredictable
= TRUE
;
8131 else if (value
== 15)
8132 func (stream
, "zr");
8134 func (stream
, "%s", arm_regnames
[value
]);
8137 print_mve_size (info
,
8147 unsigned int odd_reg
= (value
<< 1) | 1;
8148 func (stream
, "%s", arm_regnames
[odd_reg
]);
8154 = arm_decode_field (given
, 0, 6);
8155 unsigned long mod_imm
= imm
;
8157 switch (insn
->mve_op
)
8159 case MVE_VLDRW_GATHER_T5
:
8160 case MVE_VSTRW_SCATTER_T5
:
8161 mod_imm
= mod_imm
<< 2;
8163 case MVE_VSTRD_SCATTER_T6
:
8164 case MVE_VLDRD_GATHER_T6
:
8165 mod_imm
= mod_imm
<< 3;
8172 func (stream
, "%lu", mod_imm
);
8176 func (stream
, "%lu", 64 - value
);
8180 unsigned int even_reg
= value
<< 1;
8181 func (stream
, "%s", arm_regnames
[even_reg
]);
8204 print_mve_rotate (info
, value
, width
);
8207 func (stream
, "%s", arm_regnames
[value
]);
8210 func (stream
, "%ld", value
);
8211 value_in_comment
= value
;
8214 func (stream
, "s%ld", value
);
8218 func (stream
, "<illegal reg q%ld.5>", value
);
8220 func (stream
, "q%ld", value
);
8223 func (stream
, "0x%08lx", value
);
8235 func (stream
, "%c", *c
);
8238 if (value_in_comment
> 32 || value_in_comment
< -16)
8239 func (stream
, "\t; 0x%lx", value_in_comment
);
8241 if (is_unpredictable
)
8242 print_mve_unpredictable (info
, unpredictable_cond
);
8245 print_mve_undefined (info
, undefined_cond
);
8247 if ((vpt_block_state
.in_vpt_block
== FALSE
)
8249 && (is_vpt_instruction (given
) == TRUE
))
8250 mark_inside_vpt_block (given
);
8251 else if (vpt_block_state
.in_vpt_block
== TRUE
)
8252 update_vpt_block_state ();
8261 /* Return the name of a v7A special register. */
8264 banked_regname (unsigned reg
)
8268 case 15: return "CPSR";
8269 case 32: return "R8_usr";
8270 case 33: return "R9_usr";
8271 case 34: return "R10_usr";
8272 case 35: return "R11_usr";
8273 case 36: return "R12_usr";
8274 case 37: return "SP_usr";
8275 case 38: return "LR_usr";
8276 case 40: return "R8_fiq";
8277 case 41: return "R9_fiq";
8278 case 42: return "R10_fiq";
8279 case 43: return "R11_fiq";
8280 case 44: return "R12_fiq";
8281 case 45: return "SP_fiq";
8282 case 46: return "LR_fiq";
8283 case 48: return "LR_irq";
8284 case 49: return "SP_irq";
8285 case 50: return "LR_svc";
8286 case 51: return "SP_svc";
8287 case 52: return "LR_abt";
8288 case 53: return "SP_abt";
8289 case 54: return "LR_und";
8290 case 55: return "SP_und";
8291 case 60: return "LR_mon";
8292 case 61: return "SP_mon";
8293 case 62: return "ELR_hyp";
8294 case 63: return "SP_hyp";
8295 case 79: return "SPSR";
8296 case 110: return "SPSR_fiq";
8297 case 112: return "SPSR_irq";
8298 case 114: return "SPSR_svc";
8299 case 116: return "SPSR_abt";
8300 case 118: return "SPSR_und";
8301 case 124: return "SPSR_mon";
8302 case 126: return "SPSR_hyp";
8303 default: return NULL
;
8307 /* Return the name of the DMB/DSB option. */
8309 data_barrier_option (unsigned option
)
8311 switch (option
& 0xf)
8313 case 0xf: return "sy";
8314 case 0xe: return "st";
8315 case 0xd: return "ld";
8316 case 0xb: return "ish";
8317 case 0xa: return "ishst";
8318 case 0x9: return "ishld";
8319 case 0x7: return "un";
8320 case 0x6: return "unst";
8321 case 0x5: return "nshld";
8322 case 0x3: return "osh";
8323 case 0x2: return "oshst";
8324 case 0x1: return "oshld";
8325 default: return NULL
;
8329 /* Print one ARM instruction from PC on INFO->STREAM. */
8332 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8334 const struct opcode32
*insn
;
8335 void *stream
= info
->stream
;
8336 fprintf_ftype func
= info
->fprintf_func
;
8337 struct arm_private_data
*private_data
= info
->private_data
;
8339 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
8342 if (print_insn_neon (info
, given
, FALSE
))
8345 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
8347 if ((given
& insn
->mask
) != insn
->value
)
8350 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
8353 /* Special case: an instruction with all bits set in the condition field
8354 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
8355 or by the catchall at the end of the table. */
8356 if ((given
& 0xF0000000) != 0xF0000000
8357 || (insn
->mask
& 0xF0000000) == 0xF0000000
8358 || (insn
->mask
== 0 && insn
->value
== 0))
8360 unsigned long u_reg
= 16;
8361 unsigned long U_reg
= 16;
8362 bfd_boolean is_unpredictable
= FALSE
;
8363 signed long value_in_comment
= 0;
8366 for (c
= insn
->assembler
; *c
; c
++)
8370 bfd_boolean allow_unpredictable
= FALSE
;
8375 func (stream
, "%%");
8379 value_in_comment
= print_arm_address (pc
, info
, given
);
8383 /* Set P address bit and use normal address
8384 printing routine. */
8385 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
8389 allow_unpredictable
= TRUE
;
8392 if ((given
& 0x004f0000) == 0x004f0000)
8394 /* PC relative with immediate offset. */
8395 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
8399 /* Elide positive zero offset. */
8400 if (offset
|| NEGATIVE_BIT_SET
)
8401 func (stream
, "[pc, #%s%d]\t; ",
8402 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8404 func (stream
, "[pc]\t; ");
8405 if (NEGATIVE_BIT_SET
)
8407 info
->print_address_func (offset
+ pc
+ 8, info
);
8411 /* Always show the offset. */
8412 func (stream
, "[pc], #%s%d",
8413 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8414 if (! allow_unpredictable
)
8415 is_unpredictable
= TRUE
;
8420 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
8422 func (stream
, "[%s",
8423 arm_regnames
[(given
>> 16) & 0xf]);
8427 if (IMMEDIATE_BIT_SET
)
8429 /* Elide offset for non-writeback
8431 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
8433 func (stream
, ", #%s%d",
8434 NEGATIVE_BIT_SET
? "-" : "", offset
);
8436 if (NEGATIVE_BIT_SET
)
8439 value_in_comment
= offset
;
8443 /* Register Offset or Register Pre-Indexed. */
8444 func (stream
, ", %s%s",
8445 NEGATIVE_BIT_SET
? "-" : "",
8446 arm_regnames
[given
& 0xf]);
8448 /* Writing back to the register that is the source/
8449 destination of the load/store is unpredictable. */
8450 if (! allow_unpredictable
8451 && WRITEBACK_BIT_SET
8452 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
8453 is_unpredictable
= TRUE
;
8456 func (stream
, "]%s",
8457 WRITEBACK_BIT_SET
? "!" : "");
8461 if (IMMEDIATE_BIT_SET
)
8463 /* Immediate Post-indexed. */
8464 /* PR 10924: Offset must be printed, even if it is zero. */
8465 func (stream
, "], #%s%d",
8466 NEGATIVE_BIT_SET
? "-" : "", offset
);
8467 if (NEGATIVE_BIT_SET
)
8469 value_in_comment
= offset
;
8473 /* Register Post-indexed. */
8474 func (stream
, "], %s%s",
8475 NEGATIVE_BIT_SET
? "-" : "",
8476 arm_regnames
[given
& 0xf]);
8478 /* Writing back to the register that is the source/
8479 destination of the load/store is unpredictable. */
8480 if (! allow_unpredictable
8481 && (given
& 0xf) == ((given
>> 12) & 0xf))
8482 is_unpredictable
= TRUE
;
8485 if (! allow_unpredictable
)
8487 /* Writeback is automatically implied by post- addressing.
8488 Setting the W bit is unnecessary and ARM specify it as
8489 being unpredictable. */
8490 if (WRITEBACK_BIT_SET
8491 /* Specifying the PC register as the post-indexed
8492 registers is also unpredictable. */
8493 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
8494 is_unpredictable
= TRUE
;
8502 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
8503 info
->print_address_func (disp
* 4 + pc
+ 8, info
);
8508 if (((given
>> 28) & 0xf) != 0xe)
8510 arm_conditional
[(given
>> 28) & 0xf]);
8519 for (reg
= 0; reg
< 16; reg
++)
8520 if ((given
& (1 << reg
)) != 0)
8523 func (stream
, ", ");
8525 func (stream
, "%s", arm_regnames
[reg
]);
8529 is_unpredictable
= TRUE
;
8534 arm_decode_shift (given
, func
, stream
, FALSE
);
8538 if ((given
& 0x02000000) != 0)
8540 unsigned int rotate
= (given
& 0xf00) >> 7;
8541 unsigned int immed
= (given
& 0xff);
8544 a
= (((immed
<< (32 - rotate
))
8545 | (immed
>> rotate
)) & 0xffffffff);
8546 /* If there is another encoding with smaller rotate,
8547 the rotate should be specified directly. */
8548 for (i
= 0; i
< 32; i
+= 2)
8549 if ((a
<< i
| a
>> (32 - i
)) <= 0xff)
8553 func (stream
, "#%d, %d", immed
, rotate
);
8555 func (stream
, "#%d", a
);
8556 value_in_comment
= a
;
8559 arm_decode_shift (given
, func
, stream
, TRUE
);
8563 if ((given
& 0x0000f000) == 0x0000f000)
8565 arm_feature_set arm_ext_v6
=
8566 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
8568 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
8569 mechanism for setting PSR flag bits. They are
8570 obsolete in V6 onwards. */
8571 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
8575 is_unpredictable
= TRUE
;
8580 if ((given
& 0x01200000) == 0x00200000)
8586 int offset
= given
& 0xff;
8588 value_in_comment
= offset
* 4;
8589 if (NEGATIVE_BIT_SET
)
8590 value_in_comment
= - value_in_comment
;
8592 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8597 func (stream
, ", #%d]%s",
8598 (int) value_in_comment
,
8599 WRITEBACK_BIT_SET
? "!" : "");
8607 if (WRITEBACK_BIT_SET
)
8610 func (stream
, ", #%d", (int) value_in_comment
);
8614 func (stream
, ", {%d}", (int) offset
);
8615 value_in_comment
= offset
;
8622 /* Print ARM V5 BLX(1) address: pc+25 bits. */
8627 if (! NEGATIVE_BIT_SET
)
8628 /* Is signed, hi bits should be ones. */
8629 offset
= (-1) ^ 0x00ffffff;
8631 /* Offset is (SignExtend(offset field)<<2). */
8632 offset
+= given
& 0x00ffffff;
8634 address
= offset
+ pc
+ 8;
8636 if (given
& 0x01000000)
8637 /* H bit allows addressing to 2-byte boundaries. */
8640 info
->print_address_func (address
, info
);
8645 if ((given
& 0x02000200) == 0x200)
8648 unsigned sysm
= (given
& 0x004f0000) >> 16;
8650 sysm
|= (given
& 0x300) >> 4;
8651 name
= banked_regname (sysm
);
8654 func (stream
, "%s", name
);
8656 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
8660 func (stream
, "%cPSR_",
8661 (given
& 0x00400000) ? 'S' : 'C');
8662 if (given
& 0x80000)
8664 if (given
& 0x40000)
8666 if (given
& 0x20000)
8668 if (given
& 0x10000)
8674 if ((given
& 0xf0) == 0x60)
8676 switch (given
& 0xf)
8678 case 0xf: func (stream
, "sy"); break;
8680 func (stream
, "#%d", (int) given
& 0xf);
8686 const char * opt
= data_barrier_option (given
& 0xf);
8688 func (stream
, "%s", opt
);
8690 func (stream
, "#%d", (int) given
& 0xf);
8694 case '0': case '1': case '2': case '3': case '4':
8695 case '5': case '6': case '7': case '8': case '9':
8698 unsigned long value
;
8700 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8706 is_unpredictable
= TRUE
;
8710 /* We want register + 1 when decoding T. */
8716 /* Eat the 'u' character. */
8720 is_unpredictable
= TRUE
;
8725 /* Eat the 'U' character. */
8729 is_unpredictable
= TRUE
;
8732 func (stream
, "%s", arm_regnames
[value
]);
8735 func (stream
, "%ld", value
);
8736 value_in_comment
= value
;
8739 func (stream
, "%ld", value
* 8);
8740 value_in_comment
= value
* 8;
8743 func (stream
, "%ld", value
+ 1);
8744 value_in_comment
= value
+ 1;
8747 func (stream
, "0x%08lx", value
);
8749 /* Some SWI instructions have special
8751 if ((given
& 0x0fffffff) == 0x0FF00000)
8752 func (stream
, "\t; IMB");
8753 else if ((given
& 0x0fffffff) == 0x0FF00001)
8754 func (stream
, "\t; IMBRange");
8757 func (stream
, "%01lx", value
& 0xf);
8758 value_in_comment
= value
;
8763 func (stream
, "%c", *c
);
8767 if (value
== ((1ul << width
) - 1))
8768 func (stream
, "%c", *c
);
8771 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
8784 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
8785 func (stream
, "%d", imm
);
8786 value_in_comment
= imm
;
8791 /* LSB and WIDTH fields of BFI or BFC. The machine-
8792 language instruction encodes LSB and MSB. */
8794 long msb
= (given
& 0x001f0000) >> 16;
8795 long lsb
= (given
& 0x00000f80) >> 7;
8796 long w
= msb
- lsb
+ 1;
8799 func (stream
, "#%lu, #%lu", lsb
, w
);
8801 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
8806 /* Get the PSR/banked register name. */
8809 unsigned sysm
= (given
& 0x004f0000) >> 16;
8811 sysm
|= (given
& 0x300) >> 4;
8812 name
= banked_regname (sysm
);
8815 func (stream
, "%s", name
);
8817 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
8822 /* 16-bit unsigned immediate from a MOVT or MOVW
8823 instruction, encoded in bits 0:11 and 15:19. */
8825 long hi
= (given
& 0x000f0000) >> 4;
8826 long lo
= (given
& 0x00000fff);
8827 long imm16
= hi
| lo
;
8829 func (stream
, "#%lu", imm16
);
8830 value_in_comment
= imm16
;
8839 func (stream
, "%c", *c
);
8842 if (value_in_comment
> 32 || value_in_comment
< -16)
8843 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
8845 if (is_unpredictable
)
8846 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8851 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
8855 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
8858 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8860 const struct opcode16
*insn
;
8861 void *stream
= info
->stream
;
8862 fprintf_ftype func
= info
->fprintf_func
;
8864 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
8865 if ((given
& insn
->mask
) == insn
->value
)
8867 signed long value_in_comment
= 0;
8868 const char *c
= insn
->assembler
;
8877 func (stream
, "%c", *c
);
8884 func (stream
, "%%");
8889 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8894 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8903 ifthen_next_state
= given
& 0xff;
8904 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
8905 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
8906 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
8911 if (ifthen_next_state
)
8912 func (stream
, "\t; unpredictable branch in IT block\n");
8917 func (stream
, "\t; unpredictable <IT:%s>",
8918 arm_conditional
[IFTHEN_COND
]);
8925 reg
= (given
>> 3) & 0x7;
8926 if (given
& (1 << 6))
8929 func (stream
, "%s", arm_regnames
[reg
]);
8938 if (given
& (1 << 7))
8941 func (stream
, "%s", arm_regnames
[reg
]);
8946 if (given
& (1 << 8))
8950 if (*c
== 'O' && (given
& (1 << 8)))
8960 /* It would be nice if we could spot
8961 ranges, and generate the rS-rE format: */
8962 for (reg
= 0; (reg
< 8); reg
++)
8963 if ((given
& (1 << reg
)) != 0)
8966 func (stream
, ", ");
8968 func (stream
, "%s", arm_regnames
[reg
]);
8974 func (stream
, ", ");
8976 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
8982 func (stream
, ", ");
8983 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
8991 /* Print writeback indicator for a LDMIA. We are doing a
8992 writeback if the base register is not in the register
8994 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
8999 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
9001 bfd_vma address
= (pc
+ 4
9002 + ((given
& 0x00f8) >> 2)
9003 + ((given
& 0x0200) >> 3));
9004 info
->print_address_func (address
, info
);
9009 /* Right shift immediate -- bits 6..10; 1-31 print
9010 as themselves, 0 prints as 32. */
9012 long imm
= (given
& 0x07c0) >> 6;
9015 func (stream
, "#%ld", imm
);
9019 case '0': case '1': case '2': case '3': case '4':
9020 case '5': case '6': case '7': case '8': case '9':
9022 int bitstart
= *c
++ - '0';
9025 while (*c
>= '0' && *c
<= '9')
9026 bitstart
= (bitstart
* 10) + *c
++ - '0';
9035 while (*c
>= '0' && *c
<= '9')
9036 bitend
= (bitend
* 10) + *c
++ - '0';
9039 reg
= given
>> bitstart
;
9040 reg
&= (2 << (bitend
- bitstart
)) - 1;
9045 func (stream
, "%s", arm_regnames
[reg
]);
9049 func (stream
, "%ld", (long) reg
);
9050 value_in_comment
= reg
;
9054 func (stream
, "%ld", (long) (reg
<< 1));
9055 value_in_comment
= reg
<< 1;
9059 func (stream
, "%ld", (long) (reg
<< 2));
9060 value_in_comment
= reg
<< 2;
9064 /* PC-relative address -- the bottom two
9065 bits of the address are dropped
9066 before the calculation. */
9067 info
->print_address_func
9068 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
9069 value_in_comment
= 0;
9073 func (stream
, "0x%04lx", (long) reg
);
9077 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
9078 info
->print_address_func (reg
* 2 + pc
+ 4, info
);
9079 value_in_comment
= 0;
9083 func (stream
, "%s", arm_conditional
[reg
]);
9094 if ((given
& (1 << bitstart
)) != 0)
9095 func (stream
, "%c", *c
);
9100 if ((given
& (1 << bitstart
)) != 0)
9101 func (stream
, "%c", *c
++);
9103 func (stream
, "%c", *++c
);
9117 if (value_in_comment
> 32 || value_in_comment
< -16)
9118 func (stream
, "\t; 0x%lx", value_in_comment
);
9123 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
9127 /* Return the name of an V7M special register. */
9130 psr_name (int regno
)
9134 case 0x0: return "APSR";
9135 case 0x1: return "IAPSR";
9136 case 0x2: return "EAPSR";
9137 case 0x3: return "PSR";
9138 case 0x5: return "IPSR";
9139 case 0x6: return "EPSR";
9140 case 0x7: return "IEPSR";
9141 case 0x8: return "MSP";
9142 case 0x9: return "PSP";
9143 case 0xa: return "MSPLIM";
9144 case 0xb: return "PSPLIM";
9145 case 0x10: return "PRIMASK";
9146 case 0x11: return "BASEPRI";
9147 case 0x12: return "BASEPRI_MAX";
9148 case 0x13: return "FAULTMASK";
9149 case 0x14: return "CONTROL";
9150 case 0x88: return "MSP_NS";
9151 case 0x89: return "PSP_NS";
9152 case 0x8a: return "MSPLIM_NS";
9153 case 0x8b: return "PSPLIM_NS";
9154 case 0x90: return "PRIMASK_NS";
9155 case 0x91: return "BASEPRI_NS";
9156 case 0x93: return "FAULTMASK_NS";
9157 case 0x94: return "CONTROL_NS";
9158 case 0x98: return "SP_NS";
9159 default: return "<unknown>";
9163 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
9166 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
9168 const struct opcode32
*insn
;
9169 void *stream
= info
->stream
;
9170 fprintf_ftype func
= info
->fprintf_func
;
9171 bfd_boolean is_mve
= is_mve_architecture (info
);
9173 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
9176 if ((is_mve
== FALSE
) && print_insn_neon (info
, given
, TRUE
))
9179 if (is_mve
&& print_insn_mve (info
, given
))
9182 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
9183 if ((given
& insn
->mask
) == insn
->value
)
9185 bfd_boolean is_clrm
= FALSE
;
9186 bfd_boolean is_unpredictable
= FALSE
;
9187 signed long value_in_comment
= 0;
9188 const char *c
= insn
->assembler
;
9194 func (stream
, "%c", *c
);
9201 func (stream
, "%%");
9206 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9210 if (ifthen_next_state
)
9211 func (stream
, "\t; unpredictable branch in IT block\n");
9216 func (stream
, "\t; unpredictable <IT:%s>",
9217 arm_conditional
[IFTHEN_COND
]);
9222 unsigned int imm12
= 0;
9224 imm12
|= (given
& 0x000000ffu
);
9225 imm12
|= (given
& 0x00007000u
) >> 4;
9226 imm12
|= (given
& 0x04000000u
) >> 15;
9227 func (stream
, "#%u", imm12
);
9228 value_in_comment
= imm12
;
9234 unsigned int bits
= 0, imm
, imm8
, mod
;
9236 bits
|= (given
& 0x000000ffu
);
9237 bits
|= (given
& 0x00007000u
) >> 4;
9238 bits
|= (given
& 0x04000000u
) >> 15;
9239 imm8
= (bits
& 0x0ff);
9240 mod
= (bits
& 0xf00) >> 8;
9243 case 0: imm
= imm8
; break;
9244 case 1: imm
= ((imm8
<< 16) | imm8
); break;
9245 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
9246 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
9248 mod
= (bits
& 0xf80) >> 7;
9249 imm8
= (bits
& 0x07f) | 0x80;
9250 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
9252 func (stream
, "#%u", imm
);
9253 value_in_comment
= imm
;
9259 unsigned int imm
= 0;
9261 imm
|= (given
& 0x000000ffu
);
9262 imm
|= (given
& 0x00007000u
) >> 4;
9263 imm
|= (given
& 0x04000000u
) >> 15;
9264 imm
|= (given
& 0x000f0000u
) >> 4;
9265 func (stream
, "#%u", imm
);
9266 value_in_comment
= imm
;
9272 unsigned int imm
= 0;
9274 imm
|= (given
& 0x000f0000u
) >> 16;
9275 imm
|= (given
& 0x00000ff0u
) >> 0;
9276 imm
|= (given
& 0x0000000fu
) << 12;
9277 func (stream
, "#%u", imm
);
9278 value_in_comment
= imm
;
9284 unsigned int imm
= 0;
9286 imm
|= (given
& 0x000f0000u
) >> 4;
9287 imm
|= (given
& 0x00000fffu
) >> 0;
9288 func (stream
, "#%u", imm
);
9289 value_in_comment
= imm
;
9295 unsigned int imm
= 0;
9297 imm
|= (given
& 0x00000fffu
);
9298 imm
|= (given
& 0x000f0000u
) >> 4;
9299 func (stream
, "#%u", imm
);
9300 value_in_comment
= imm
;
9306 unsigned int reg
= (given
& 0x0000000fu
);
9307 unsigned int stp
= (given
& 0x00000030u
) >> 4;
9308 unsigned int imm
= 0;
9309 imm
|= (given
& 0x000000c0u
) >> 6;
9310 imm
|= (given
& 0x00007000u
) >> 10;
9312 func (stream
, "%s", arm_regnames
[reg
]);
9317 func (stream
, ", lsl #%u", imm
);
9323 func (stream
, ", lsr #%u", imm
);
9329 func (stream
, ", asr #%u", imm
);
9334 func (stream
, ", rrx");
9336 func (stream
, ", ror #%u", imm
);
9343 unsigned int Rn
= (given
& 0x000f0000) >> 16;
9344 unsigned int U
= ! NEGATIVE_BIT_SET
;
9345 unsigned int op
= (given
& 0x00000f00) >> 8;
9346 unsigned int i12
= (given
& 0x00000fff);
9347 unsigned int i8
= (given
& 0x000000ff);
9348 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
9351 func (stream
, "[%s", arm_regnames
[Rn
]);
9352 if (U
) /* 12-bit positive immediate offset. */
9356 value_in_comment
= offset
;
9358 else if (Rn
== 15) /* 12-bit negative immediate offset. */
9359 offset
= - (int) i12
;
9360 else if (op
== 0x0) /* Shifted register offset. */
9362 unsigned int Rm
= (i8
& 0x0f);
9363 unsigned int sh
= (i8
& 0x30) >> 4;
9365 func (stream
, ", %s", arm_regnames
[Rm
]);
9367 func (stream
, ", lsl #%u", sh
);
9373 case 0xE: /* 8-bit positive immediate offset. */
9377 case 0xC: /* 8-bit negative immediate offset. */
9381 case 0xF: /* 8-bit + preindex with wb. */
9386 case 0xD: /* 8-bit - preindex with wb. */
9391 case 0xB: /* 8-bit + postindex. */
9396 case 0x9: /* 8-bit - postindex. */
9402 func (stream
, ", <undefined>]");
9407 func (stream
, "], #%d", (int) offset
);
9411 func (stream
, ", #%d", (int) offset
);
9412 func (stream
, writeback
? "]!" : "]");
9417 func (stream
, "\t; ");
9418 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
9426 unsigned int U
= ! NEGATIVE_BIT_SET
;
9427 unsigned int W
= WRITEBACK_BIT_SET
;
9428 unsigned int Rn
= (given
& 0x000f0000) >> 16;
9429 unsigned int off
= (given
& 0x000000ff);
9431 func (stream
, "[%s", arm_regnames
[Rn
]);
9437 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
9438 value_in_comment
= off
* 4 * (U
? 1 : -1);
9446 func (stream
, "], ");
9449 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
9450 value_in_comment
= off
* 4 * (U
? 1 : -1);
9454 func (stream
, "{%u}", off
);
9455 value_in_comment
= off
;
9463 unsigned int Sbit
= (given
& 0x01000000) >> 24;
9464 unsigned int type
= (given
& 0x00600000) >> 21;
9468 case 0: func (stream
, Sbit
? "sb" : "b"); break;
9469 case 1: func (stream
, Sbit
? "sh" : "h"); break;
9472 func (stream
, "??");
9475 func (stream
, "??");
9490 for (reg
= 0; reg
< 16; reg
++)
9491 if ((given
& (1 << reg
)) != 0)
9494 func (stream
, ", ");
9496 if (is_clrm
&& reg
== 13)
9497 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
9498 else if (is_clrm
&& reg
== 15)
9499 func (stream
, "%s", "APSR");
9501 func (stream
, "%s", arm_regnames
[reg
]);
9509 unsigned int msb
= (given
& 0x0000001f);
9510 unsigned int lsb
= 0;
9512 lsb
|= (given
& 0x000000c0u
) >> 6;
9513 lsb
|= (given
& 0x00007000u
) >> 10;
9514 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
9520 unsigned int width
= (given
& 0x0000001f) + 1;
9521 unsigned int lsb
= 0;
9523 lsb
|= (given
& 0x000000c0u
) >> 6;
9524 lsb
|= (given
& 0x00007000u
) >> 10;
9525 func (stream
, "#%u, #%u", lsb
, width
);
9531 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
9532 func (stream
, "%x", boff
);
9538 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
9539 unsigned int immB
= (given
& 0x000007feu
) >> 1;
9540 unsigned int immC
= (given
& 0x00000800u
) >> 11;
9543 offset
|= immA
<< 12;
9544 offset
|= immB
<< 2;
9545 offset
|= immC
<< 1;
9547 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
9549 info
->print_address_func (pc
+ 4 + offset
, info
);
9555 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
9556 unsigned int immB
= (given
& 0x000007feu
) >> 1;
9557 unsigned int immC
= (given
& 0x00000800u
) >> 11;
9560 offset
|= immA
<< 12;
9561 offset
|= immB
<< 2;
9562 offset
|= immC
<< 1;
9564 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
9566 info
->print_address_func (pc
+ 4 + offset
, info
);
9572 unsigned int immA
= (given
& 0x00010000u
) >> 16;
9573 unsigned int immB
= (given
& 0x000007feu
) >> 1;
9574 unsigned int immC
= (given
& 0x00000800u
) >> 11;
9577 offset
|= immA
<< 12;
9578 offset
|= immB
<< 2;
9579 offset
|= immC
<< 1;
9581 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
9583 info
->print_address_func (pc
+ 4 + offset
, info
);
9585 unsigned int T
= (given
& 0x00020000u
) >> 17;
9586 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
9587 unsigned int boffset
= (T
== 1) ? 4 : 2;
9588 func (stream
, ", ");
9589 func (stream
, "%x", endoffset
+ boffset
);
9595 unsigned int immh
= (given
& 0x000007feu
) >> 1;
9596 unsigned int imml
= (given
& 0x00000800u
) >> 11;
9602 info
->print_address_func (pc
+ 4 + imm32
, info
);
9608 unsigned int immh
= (given
& 0x000007feu
) >> 1;
9609 unsigned int imml
= (given
& 0x00000800u
) >> 11;
9615 info
->print_address_func (pc
+ 4 - imm32
, info
);
9621 unsigned int S
= (given
& 0x04000000u
) >> 26;
9622 unsigned int J1
= (given
& 0x00002000u
) >> 13;
9623 unsigned int J2
= (given
& 0x00000800u
) >> 11;
9629 offset
|= (given
& 0x003f0000) >> 4;
9630 offset
|= (given
& 0x000007ff) << 1;
9631 offset
-= (1 << 20);
9633 info
->print_address_func (pc
+ 4 + offset
, info
);
9639 unsigned int S
= (given
& 0x04000000u
) >> 26;
9640 unsigned int I1
= (given
& 0x00002000u
) >> 13;
9641 unsigned int I2
= (given
& 0x00000800u
) >> 11;
9645 offset
|= !(I1
^ S
) << 23;
9646 offset
|= !(I2
^ S
) << 22;
9647 offset
|= (given
& 0x03ff0000u
) >> 4;
9648 offset
|= (given
& 0x000007ffu
) << 1;
9649 offset
-= (1 << 24);
9652 /* BLX target addresses are always word aligned. */
9653 if ((given
& 0x00001000u
) == 0)
9656 info
->print_address_func (offset
, info
);
9662 unsigned int shift
= 0;
9664 shift
|= (given
& 0x000000c0u
) >> 6;
9665 shift
|= (given
& 0x00007000u
) >> 10;
9666 if (WRITEBACK_BIT_SET
)
9667 func (stream
, ", asr #%u", shift
);
9669 func (stream
, ", lsl #%u", shift
);
9670 /* else print nothing - lsl #0 */
9676 unsigned int rot
= (given
& 0x00000030) >> 4;
9679 func (stream
, ", ror #%u", rot
* 8);
9684 if ((given
& 0xf0) == 0x60)
9686 switch (given
& 0xf)
9688 case 0xf: func (stream
, "sy"); break;
9690 func (stream
, "#%d", (int) given
& 0xf);
9696 const char * opt
= data_barrier_option (given
& 0xf);
9698 func (stream
, "%s", opt
);
9700 func (stream
, "#%d", (int) given
& 0xf);
9705 if ((given
& 0xff) == 0)
9707 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
9717 else if ((given
& 0x20) == 0x20)
9720 unsigned sysm
= (given
& 0xf00) >> 8;
9722 sysm
|= (given
& 0x30);
9723 sysm
|= (given
& 0x00100000) >> 14;
9724 name
= banked_regname (sysm
);
9727 func (stream
, "%s", name
);
9729 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
9733 func (stream
, "%s", psr_name (given
& 0xff));
9738 if (((given
& 0xff) == 0)
9739 || ((given
& 0x20) == 0x20))
9742 unsigned sm
= (given
& 0xf0000) >> 16;
9744 sm
|= (given
& 0x30);
9745 sm
|= (given
& 0x00100000) >> 14;
9746 name
= banked_regname (sm
);
9749 func (stream
, "%s", name
);
9751 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
9754 func (stream
, "%s", psr_name (given
& 0xff));
9757 case '0': case '1': case '2': case '3': case '4':
9758 case '5': case '6': case '7': case '8': case '9':
9763 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
9768 func (stream
, "%lu", val
);
9769 value_in_comment
= val
;
9773 func (stream
, "%lu", val
+ 1);
9774 value_in_comment
= val
+ 1;
9778 func (stream
, "%lu", val
* 4);
9779 value_in_comment
= val
* 4;
9784 is_unpredictable
= TRUE
;
9788 is_unpredictable
= TRUE
;
9791 func (stream
, "%s", arm_regnames
[val
]);
9795 func (stream
, "%s", arm_conditional
[val
]);
9800 if (val
== ((1ul << width
) - 1))
9801 func (stream
, "%c", *c
);
9807 func (stream
, "%c", *c
);
9811 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
9816 func (stream
, "0x%lx", val
& 0xffffffffUL
);
9826 /* PR binutils/12534
9827 If we have a PC relative offset in an LDRD or STRD
9828 instructions then display the decoded address. */
9829 if (((given
>> 16) & 0xf) == 0xf)
9831 bfd_vma offset
= (given
& 0xff) * 4;
9833 if ((given
& (1 << 23)) == 0)
9835 func (stream
, "\t; ");
9836 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
9845 if (value_in_comment
> 32 || value_in_comment
< -16)
9846 func (stream
, "\t; 0x%lx", value_in_comment
);
9848 if (is_unpredictable
)
9849 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9855 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
9859 /* Print data bytes on INFO->STREAM. */
9862 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
9863 struct disassemble_info
*info
,
9866 switch (info
->bytes_per_chunk
)
9869 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
9872 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
9875 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
9882 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
9883 being displayed in symbol relative addresses.
9885 Also disallow private symbol, with __tagsym$$ prefix,
9886 from ARM RVCT toolchain being displayed. */
9889 arm_symbol_is_valid (asymbol
* sym
,
9890 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
9897 name
= bfd_asymbol_name (sym
);
9899 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
9902 /* Parse the string of disassembler options. */
9905 parse_arm_disassembler_options (const char *options
)
9909 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
9911 if (CONST_STRNEQ (opt
, "reg-names-"))
9914 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
9915 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
9917 regname_selected
= i
;
9921 if (i
>= NUM_ARM_OPTIONS
)
9922 /* xgettext: c-format */
9923 opcodes_error_handler (_("unrecognised register name set: %s"),
9926 else if (CONST_STRNEQ (opt
, "force-thumb"))
9928 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
9931 /* xgettext: c-format */
9932 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
9939 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
9940 enum map_type
*map_symbol
);
9942 /* Search back through the insn stream to determine if this instruction is
9943 conditionally executed. */
9946 find_ifthen_state (bfd_vma pc
,
9947 struct disassemble_info
*info
,
9953 /* COUNT is twice the number of instructions seen. It will be odd if we
9954 just crossed an instruction boundary. */
9957 unsigned int seen_it
;
9960 ifthen_address
= pc
;
9967 /* Scan backwards looking for IT instructions, keeping track of where
9968 instruction boundaries are. We don't know if something is actually an
9969 IT instruction until we find a definite instruction boundary. */
9972 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
9974 /* A symbol must be on an instruction boundary, and will not
9975 be within an IT block. */
9976 if (seen_it
&& (count
& 1))
9982 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
9987 insn
= (b
[0]) | (b
[1] << 8);
9989 insn
= (b
[1]) | (b
[0] << 8);
9992 if ((insn
& 0xf800) < 0xe800)
9994 /* Addr + 2 is an instruction boundary. See if this matches
9995 the expected boundary based on the position of the last
10002 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
10004 enum map_type type
= MAP_ARM
;
10005 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
10007 if (!found
|| (found
&& type
== MAP_THUMB
))
10009 /* This could be an IT instruction. */
10011 it_count
= count
>> 1;
10014 if ((insn
& 0xf800) >= 0xe800)
10017 count
= (count
+ 2) | 1;
10018 /* IT blocks contain at most 4 instructions. */
10019 if (count
>= 8 && !seen_it
)
10022 /* We found an IT instruction. */
10023 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
10024 if ((ifthen_state
& 0xf) == 0)
10028 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
10032 is_mapping_symbol (struct disassemble_info
*info
, int n
,
10033 enum map_type
*map_type
)
10037 name
= bfd_asymbol_name (info
->symtab
[n
]);
10038 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
10039 && (name
[2] == 0 || name
[2] == '.'))
10041 *map_type
= ((name
[1] == 'a') ? MAP_ARM
10042 : (name
[1] == 't') ? MAP_THUMB
10050 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
10051 Returns nonzero if *MAP_TYPE was set. */
10054 get_map_sym_type (struct disassemble_info
*info
,
10056 enum map_type
*map_type
)
10058 /* If the symbol is in a different section, ignore it. */
10059 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
10062 return is_mapping_symbol (info
, n
, map_type
);
10065 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
10066 Returns nonzero if *MAP_TYPE was set. */
10069 get_sym_code_type (struct disassemble_info
*info
,
10071 enum map_type
*map_type
)
10073 elf_symbol_type
*es
;
10076 /* If the symbol is in a different section, ignore it. */
10077 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
10080 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
10081 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
10083 /* If the symbol has function type then use that. */
10084 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
10086 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
10087 == ST_BRANCH_TO_THUMB
)
10088 *map_type
= MAP_THUMB
;
10090 *map_type
= MAP_ARM
;
10097 /* Search the mapping symbol state for instruction at pc. This is only
10098 applicable for elf target.
10100 There is an assumption Here, info->private_data contains the correct AND
10101 up-to-date information about current scan process. The information will be
10102 used to speed this search process.
10104 Return TRUE if the mapping state can be determined, and map_symbol
10105 will be updated accordingly. Otherwise, return FALSE. */
10108 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
10109 enum map_type
*map_symbol
)
10111 bfd_vma addr
, section_vma
= 0;
10112 int n
, last_sym
= -1;
10113 bfd_boolean found
= FALSE
;
10114 bfd_boolean can_use_search_opt_p
= FALSE
;
10116 /* Default to DATA. A text section is required by the ABI to contain an
10117 INSN mapping symbol at the start. A data section has no such
10118 requirement, hence if no mapping symbol is found the section must
10119 contain only data. This however isn't very useful if the user has
10120 fully stripped the binaries. If this is the case use the section
10121 attributes to determine the default. If we have no section default to
10122 INSN as well, as we may be disassembling some raw bytes on a baremetal
10123 HEX file or similar. */
10124 enum map_type type
= MAP_DATA
;
10125 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
10127 struct arm_private_data
*private_data
;
10129 if (info
->private_data
== NULL
10130 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
10133 private_data
= info
->private_data
;
10135 /* First, look for mapping symbols. */
10136 if (info
->symtab_size
!= 0)
10138 if (pc
<= private_data
->last_mapping_addr
)
10139 private_data
->last_mapping_sym
= -1;
10141 /* Start scanning at the start of the function, or wherever
10142 we finished last time. */
10143 n
= info
->symtab_pos
+ 1;
10145 /* If the last stop offset is different from the current one it means we
10146 are disassembling a different glob of bytes. As such the optimization
10147 would not be safe and we should start over. */
10148 can_use_search_opt_p
10149 = private_data
->last_mapping_sym
>= 0
10150 && info
->stop_offset
== private_data
->last_stop_offset
;
10152 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
10153 n
= private_data
->last_mapping_sym
;
10155 /* Look down while we haven't passed the location being disassembled.
10156 The reason for this is that there's no defined order between a symbol
10157 and an mapping symbol that may be at the same address. We may have to
10158 look at least one position ahead. */
10159 for (; n
< info
->symtab_size
; n
++)
10161 addr
= bfd_asymbol_value (info
->symtab
[n
]);
10164 if (get_map_sym_type (info
, n
, &type
))
10173 n
= info
->symtab_pos
;
10174 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
10175 n
= private_data
->last_mapping_sym
;
10177 /* No mapping symbol found at this address. Look backwards
10178 for a preceeding one, but don't go pass the section start
10179 otherwise a data section with no mapping symbol can pick up
10180 a text mapping symbol of a preceeding section. The documentation
10181 says section can be NULL, in which case we will seek up all the
10184 section_vma
= info
->section
->vma
;
10186 for (; n
>= 0; n
--)
10188 addr
= bfd_asymbol_value (info
->symtab
[n
]);
10189 if (addr
< section_vma
)
10192 if (get_map_sym_type (info
, n
, &type
))
10202 /* If no mapping symbol was found, try looking up without a mapping
10203 symbol. This is done by walking up from the current PC to the nearest
10204 symbol. We don't actually have to loop here since symtab_pos will
10205 contain the nearest symbol already. */
10208 n
= info
->symtab_pos
;
10209 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
10216 private_data
->last_mapping_sym
= last_sym
;
10217 private_data
->last_type
= type
;
10218 private_data
->last_stop_offset
= info
->stop_offset
;
10220 *map_symbol
= type
;
10224 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
10225 of the supplied arm_feature_set structure with bitmasks indicating
10226 the supported base architectures and coprocessor extensions.
10228 FIXME: This could more efficiently implemented as a constant array,
10229 although it would also be less robust. */
10232 select_arm_features (unsigned long mach
,
10233 arm_feature_set
* features
)
10235 arm_feature_set arch_fset
;
10236 const arm_feature_set fpu_any
= FPU_ANY
;
10238 #undef ARM_SET_FEATURES
10239 #define ARM_SET_FEATURES(FSET) \
10241 const arm_feature_set fset = FSET; \
10242 arch_fset = fset; \
10245 /* When several architecture versions share the same bfd_mach_arm_XXX value
10246 the most featureful is chosen. */
10249 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
10250 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
10251 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
10252 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
10253 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
10254 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
10255 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
10256 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
10257 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
10258 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
10259 case bfd_mach_arm_ep9312
:
10260 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
10261 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
10263 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
10264 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
10265 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
10266 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
10267 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
10268 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
10269 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
10270 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
10271 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
10272 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
10273 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
10274 case bfd_mach_arm_8
:
10276 /* Add bits for extensions that Armv8.5-A recognizes. */
10277 arm_feature_set armv8_5_ext_fset
10278 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
10279 ARM_SET_FEATURES (ARM_ARCH_V8_5A
);
10280 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_5_ext_fset
);
10283 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
10284 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
10285 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
10286 case bfd_mach_arm_8_1M_MAIN
:
10287 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
10290 /* If the machine type is unknown allow all architecture types and all
10292 case bfd_mach_arm_unknown
: ARM_SET_FEATURES (ARM_FEATURE_ALL
); break;
10296 #undef ARM_SET_FEATURES
10298 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
10299 and thus on bfd_mach_arm_XXX value. Therefore for a given
10300 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
10301 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
10305 /* NOTE: There are no checks in these routines that
10306 the relevant number of data bytes exist. */
10309 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
10311 unsigned char b
[4];
10314 int is_thumb
= FALSE
;
10315 int is_data
= FALSE
;
10317 unsigned int size
= 4;
10318 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
10319 bfd_boolean found
= FALSE
;
10320 struct arm_private_data
*private_data
;
10322 if (info
->disassembler_options
)
10324 parse_arm_disassembler_options (info
->disassembler_options
);
10326 /* To avoid repeated parsing of these options, we remove them here. */
10327 info
->disassembler_options
= NULL
;
10330 /* PR 10288: Control which instructions will be disassembled. */
10331 if (info
->private_data
== NULL
)
10333 static struct arm_private_data
private;
10335 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
10336 /* If the user did not use the -m command line switch then default to
10337 disassembling all types of ARM instruction.
10339 The info->mach value has to be ignored as this will be based on
10340 the default archictecture for the target and/or hints in the notes
10341 section, but it will never be greater than the current largest arm
10342 machine value (iWMMXt2), which is only equivalent to the V5TE
10343 architecture. ARM architectures have advanced beyond the machine
10344 value encoding, and these newer architectures would be ignored if
10345 the machine value was used.
10347 Ie the -m switch is used to restrict which instructions will be
10348 disassembled. If it is necessary to use the -m switch to tell
10349 objdump that an ARM binary is being disassembled, eg because the
10350 input is a raw binary file, but it is also desired to disassemble
10351 all ARM instructions then use "-marm". This will select the
10352 "unknown" arm architecture which is compatible with any ARM
10354 info
->mach
= bfd_mach_arm_unknown
;
10356 /* Compute the architecture bitmask from the machine number.
10357 Note: This assumes that the machine number will not change
10358 during disassembly.... */
10359 select_arm_features (info
->mach
, & private.features
);
10361 private.last_mapping_sym
= -1;
10362 private.last_mapping_addr
= 0;
10363 private.last_stop_offset
= 0;
10365 info
->private_data
= & private;
10368 private_data
= info
->private_data
;
10370 /* Decide if our code is going to be little-endian, despite what the
10371 function argument might say. */
10372 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
10374 /* For ELF, consult the symbol table to determine what kind of code
10375 or data we have. */
10376 if (info
->symtab_size
!= 0
10377 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
10382 enum map_type type
= MAP_ARM
;
10384 found
= mapping_symbol_for_insn (pc
, info
, &type
);
10385 last_sym
= private_data
->last_mapping_sym
;
10387 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
10388 is_data
= (private_data
->last_type
== MAP_DATA
);
10390 /* Look a little bit ahead to see if we should print out
10391 two or four bytes of data. If there's a symbol,
10392 mapping or otherwise, after two bytes then don't
10396 size
= 4 - (pc
& 3);
10397 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
10399 addr
= bfd_asymbol_value (info
->symtab
[n
]);
10401 && (info
->section
== NULL
10402 || info
->section
== info
->symtab
[n
]->section
))
10404 if (addr
- pc
< size
)
10409 /* If the next symbol is after three bytes, we need to
10410 print only part of the data, so that we can use either
10411 .byte or .short. */
10413 size
= (pc
& 1) ? 1 : 2;
10417 if (info
->symbols
!= NULL
)
10419 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
10421 coff_symbol_type
* cs
;
10423 cs
= coffsymbol (*info
->symbols
);
10424 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
10425 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
10426 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
10427 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
10428 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
10430 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
10433 /* If no mapping symbol has been found then fall back to the type
10434 of the function symbol. */
10435 elf_symbol_type
* es
;
10438 es
= *(elf_symbol_type
**)(info
->symbols
);
10439 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
10442 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
10443 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
10445 else if (bfd_asymbol_flavour (*info
->symbols
)
10446 == bfd_target_mach_o_flavour
)
10448 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
10450 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
10458 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
10460 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
10462 info
->bytes_per_line
= 4;
10464 /* PR 10263: Disassemble data if requested to do so by the user. */
10465 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
10469 /* Size was already set above. */
10470 info
->bytes_per_chunk
= size
;
10471 printer
= print_insn_data
;
10473 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
10476 for (i
= size
- 1; i
>= 0; i
--)
10477 given
= b
[i
] | (given
<< 8);
10479 for (i
= 0; i
< (int) size
; i
++)
10480 given
= b
[i
] | (given
<< 8);
10482 else if (!is_thumb
)
10484 /* In ARM mode endianness is a straightforward issue: the instruction
10485 is four bytes long and is either ordered 0123 or 3210. */
10486 printer
= print_insn_arm
;
10487 info
->bytes_per_chunk
= 4;
10490 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
10492 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
10494 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | (b
[0] << 24);
10498 /* In Thumb mode we have the additional wrinkle of two
10499 instruction lengths. Fortunately, the bits that determine
10500 the length of the current instruction are always to be found
10501 in the first two bytes. */
10502 printer
= print_insn_thumb16
;
10503 info
->bytes_per_chunk
= 2;
10506 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
10508 given
= (b
[0]) | (b
[1] << 8);
10510 given
= (b
[1]) | (b
[0] << 8);
10514 /* These bit patterns signal a four-byte Thumb
10516 if ((given
& 0xF800) == 0xF800
10517 || (given
& 0xF800) == 0xF000
10518 || (given
& 0xF800) == 0xE800)
10520 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
10522 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
10524 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
10526 printer
= print_insn_thumb32
;
10531 if (ifthen_address
!= pc
)
10532 find_ifthen_state (pc
, info
, little_code
);
10536 if ((ifthen_state
& 0xf) == 0x8)
10537 ifthen_next_state
= 0;
10539 ifthen_next_state
= (ifthen_state
& 0xe0)
10540 | ((ifthen_state
& 0xf) << 1);
10546 info
->memory_error_func (status
, pc
, info
);
10549 if (info
->flags
& INSN_HAS_RELOC
)
10550 /* If the instruction has a reloc associated with it, then
10551 the offset field in the instruction will actually be the
10552 addend for the reloc. (We are using REL type relocs).
10553 In such cases, we can ignore the pc when computing
10554 addresses, since the addend is not currently pc-relative. */
10557 printer (pc
, info
, given
);
10561 ifthen_state
= ifthen_next_state
;
10562 ifthen_address
+= size
;
10568 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
10570 /* Detect BE8-ness and record it in the disassembler info. */
10571 if (info
->flavour
== bfd_target_elf_flavour
10572 && info
->section
!= NULL
10573 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
10574 info
->endian_code
= BFD_ENDIAN_LITTLE
;
10576 return print_insn (pc
, info
, FALSE
);
10580 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
10582 return print_insn (pc
, info
, TRUE
);
10585 const disasm_options_and_args_t
*
10586 disassembler_options_arm (void)
10588 static disasm_options_and_args_t
*opts_and_args
;
10590 if (opts_and_args
== NULL
)
10592 disasm_options_t
*opts
;
10595 opts_and_args
= XNEW (disasm_options_and_args_t
);
10596 opts_and_args
->args
= NULL
;
10598 opts
= &opts_and_args
->options
;
10599 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
10600 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
10602 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
10604 opts
->name
[i
] = regnames
[i
].name
;
10605 if (regnames
[i
].description
!= NULL
)
10606 opts
->description
[i
] = _(regnames
[i
].description
);
10608 opts
->description
[i
] = NULL
;
10610 /* The array we return must be NULL terminated. */
10611 opts
->name
[i
] = NULL
;
10612 opts
->description
[i
] = NULL
;
10615 return opts_and_args
;
10619 print_arm_disassembler_options (FILE *stream
)
10621 unsigned int i
, max_len
= 0;
10622 fprintf (stream
, _("\n\
10623 The following ARM specific disassembler options are supported for use with\n\
10624 the -M switch:\n"));
10626 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
10628 unsigned int len
= strlen (regnames
[i
].name
);
10633 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
10634 fprintf (stream
, " %s%*c %s\n",
10636 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
10637 _(regnames
[i
].description
));