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[PATCH 44/57][Arm][OBJDUMP] Add support for MVE instructions: vcvt and vrint
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24 #include <assert.h>
25
26 #include "disassemble.h"
27 #include "opcode/arm.h"
28 #include "opintl.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
32
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
35 #include "libcoff.h"
36 #include "bfd.h"
37 #include "elf-bfd.h"
38 #include "elf/internal.h"
39 #include "elf/arm.h"
40 #include "mach-o.h"
41
42 /* FIXME: Belongs in global header. */
43 #ifndef strneq
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45 #endif
46
47 /* Cached mapping symbol state. */
48 enum map_type
49 {
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53 };
54
55 struct arm_private_data
56 {
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
68 bfd_vma last_mapping_addr;
69 };
70
71 enum mve_instructions
72 {
73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
132 MVE_NONE
133 };
134
135 enum mve_unpredictable
136 {
137 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
138 */
139 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
140 fcB = 1 (vpt). */
141 UNPRED_R13, /* Unpredictable because r13 (sp) or
142 r15 (sp) used. */
143 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
144 UNPRED_Q_GT_4, /* Unpredictable because
145 vec reg start > 4 (vld4/st4). */
146 UNPRED_Q_GT_6, /* Unpredictable because
147 vec reg start > 6 (vld2/st2). */
148 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
149 and WB bit = 1. */
150 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
151 equal. */
152 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
153 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
154 same. */
155 UNPRED_NONE /* No unpredictable behavior. */
156 };
157
158 enum mve_undefined
159 {
160 UNDEF_SIZE_0, /* undefined because size == 0. */
161 UNDEF_SIZE_3, /* undefined because size == 3. */
162 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
163 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
164 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
165 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
166 size == 0. */
167 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
168 size == 1. */
169 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
170 UNDEF_VCVT_IMM6, /* imm6 < 32. */
171 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
172 UNDEF_NONE /* no undefined behavior. */
173 };
174
175 struct opcode32
176 {
177 arm_feature_set arch; /* Architecture defining this insn. */
178 unsigned long value; /* If arch is 0 then value is a sentinel. */
179 unsigned long mask; /* Recognise insn if (op & mask) == value. */
180 const char * assembler; /* How to disassemble this insn. */
181 };
182
183 /* MVE opcodes. */
184
185 struct mopcode32
186 {
187 arm_feature_set arch; /* Architecture defining this insn. */
188 enum mve_instructions mve_op; /* Specific mve instruction for faster
189 decoding. */
190 unsigned long value; /* If arch is 0 then value is a sentinel. */
191 unsigned long mask; /* Recognise insn if (op & mask) == value. */
192 const char * assembler; /* How to disassemble this insn. */
193 };
194
195 enum isa {
196 ANY,
197 T32,
198 ARM
199 };
200
201
202 /* Shared (between Arm and Thumb mode) opcode. */
203 struct sopcode32
204 {
205 enum isa isa; /* Execution mode instruction availability. */
206 arm_feature_set arch; /* Architecture defining this insn. */
207 unsigned long value; /* If arch is 0 then value is a sentinel. */
208 unsigned long mask; /* Recognise insn if (op & mask) == value. */
209 const char * assembler; /* How to disassemble this insn. */
210 };
211
212 struct opcode16
213 {
214 arm_feature_set arch; /* Architecture defining this insn. */
215 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
216 const char *assembler; /* How to disassemble this insn. */
217 };
218
219 /* print_insn_coprocessor recognizes the following format control codes:
220
221 %% %
222
223 %c print condition code (always bits 28-31 in ARM mode)
224 %q print shifter argument
225 %u print condition code (unconditional in ARM mode,
226 UNPREDICTABLE if not AL in Thumb)
227 %A print address for ldc/stc/ldf/stf instruction
228 %B print vstm/vldm register list
229 %C print vscclrm register list
230 %I print cirrus signed shift immediate: bits 0..3|4..6
231 %J print register for VLDR instruction
232 %K print address for VLDR instruction
233 %F print the COUNT field of a LFM/SFM instruction.
234 %P print floating point precision in arithmetic insn
235 %Q print floating point precision in ldf/stf insn
236 %R print floating point rounding mode
237
238 %<bitfield>c print as a condition code (for vsel)
239 %<bitfield>r print as an ARM register
240 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
241 %<bitfield>ru as %<>r but each u register must be unique.
242 %<bitfield>d print the bitfield in decimal
243 %<bitfield>k print immediate for VFPv3 conversion instruction
244 %<bitfield>x print the bitfield in hex
245 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
246 %<bitfield>f print a floating point constant if >7 else a
247 floating point register
248 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
249 %<bitfield>g print as an iWMMXt 64-bit register
250 %<bitfield>G print as an iWMMXt general purpose or control register
251 %<bitfield>D print as a NEON D register
252 %<bitfield>Q print as a NEON Q register
253 %<bitfield>V print as a NEON D or Q register
254 %<bitfield>E print a quarter-float immediate value
255
256 %y<code> print a single precision VFP reg.
257 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
258 %z<code> print a double precision VFP reg
259 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
260
261 %<bitfield>'c print specified char iff bitfield is all ones
262 %<bitfield>`c print specified char iff bitfield is all zeroes
263 %<bitfield>?ab... select from array of values in big endian order
264
265 %L print as an iWMMXt N/M width field.
266 %Z print the Immediate of a WSHUFH instruction.
267 %l like 'A' except use byte offsets for 'B' & 'H'
268 versions.
269 %i print 5-bit immediate in bits 8,3..0
270 (print "32" when 0)
271 %r print register offset address for wldt/wstr instruction. */
272
273 enum opcode_sentinel_enum
274 {
275 SENTINEL_IWMMXT_START = 1,
276 SENTINEL_IWMMXT_END,
277 SENTINEL_GENERIC_START
278 } opcode_sentinels;
279
280 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
281 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
282 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
283 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
284
285 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
286
287 static const struct sopcode32 coprocessor_opcodes[] =
288 {
289 /* XScale instructions. */
290 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200010, 0x0fff0ff0,
292 "mia%c\tacc0, %0-3r, %12-15r"},
293 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
294 0x0e280010, 0x0fff0ff0,
295 "miaph%c\tacc0, %0-3r, %12-15r"},
296 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
298 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
300 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
302
303 /* Intel Wireless MMX technology instructions. */
304 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
305 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
306 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
307 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
308 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
309 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
310 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
311 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
312 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
313 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
314 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
315 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
316 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
317 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
318 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
319 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
320 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
321 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
322 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
323 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
324 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
325 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
326 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
327 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
328 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
329 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
330 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
331 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
332 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
333 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
334 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
335 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
336 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
337 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
338 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
339 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
340 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
341 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
342 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
343 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
344 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
345 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
346 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
347 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
348 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
349 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
350 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
351 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
352 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
353 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
354 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
355 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
356 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
357 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
358 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
359 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
360 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
361 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
362 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
363 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
364 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
365 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
366 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
367 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
368 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
369 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
370 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
371 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
372 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
373 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
374 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
375 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
376 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
377 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
378 0x0e800120, 0x0f800ff0,
379 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
380 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
381 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
382 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
383 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
384 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
385 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
386 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
387 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
388 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
389 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
390 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
391 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
392 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
393 0x0e8000a0, 0x0f800ff0,
394 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
395 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
396 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
397 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
398 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
399 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
400 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
401 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
402 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
403 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
404 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
405 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
406 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
407 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
408 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
409 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
410 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
411 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
412 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
413 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
414 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
415 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
416 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
417 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
418 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
419 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
420 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
421 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
422 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
423 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
424 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
425 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
426 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
427 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
428 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
429 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
430 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
431 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
432 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
433 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
434 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
435 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
436 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
437 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
438 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
439 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
440 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
441 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
442 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
443 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
444 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
445 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
446 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
447 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
448 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
449 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
450 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
451 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
452 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
453 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
454 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
455 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
456 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
457 {ANY, ARM_FEATURE_CORE_LOW (0),
458 SENTINEL_IWMMXT_END, 0, "" },
459
460 /* Floating point coprocessor (FPA) instructions. */
461 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
462 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
463 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
464 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
465 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
466 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
467 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
468 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
469 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
470 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
471 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
472 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
473 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
474 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
475 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
476 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
477 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
478 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
479 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
480 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
481 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
482 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
483 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
484 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
485 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
486 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
487 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
488 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
489 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
490 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
491 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
492 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
493 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
494 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
495 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
496 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
497 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
498 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
499 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
500 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
501 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
502 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
503 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
504 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
505 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
506 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
507 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
508 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
509 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
510 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
511 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
512 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
513 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
514 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
515 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
516 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
517 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
518 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
519 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
520 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
521 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
522 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
523 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
524 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
525 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
526 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
527 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
528 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
529 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
530 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
531 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
532 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
533 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
534 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
535 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
536 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
537 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
538 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
539 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
540 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
541 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
542 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
543 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
544 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
545 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
546 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
547
548 /* Armv8.1-M Mainline instructions. */
549 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
550 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
551 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
552 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
553
554 /* ARMv8-M Mainline Security Extensions instructions. */
555 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
556 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
557 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
558 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
559
560 /* Register load/store. */
561 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
562 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
563 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
564 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
565 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
566 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
567 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
568 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
569 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
570 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
571 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
572 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
573 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
574 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
575 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
576 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
577 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
578 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
579 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
580 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
581 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
582 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
583 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
584 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
585 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
586 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
587 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
588 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
589 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
590 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
591 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
592 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
593 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
594 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
595 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
596 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
597
598 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
599 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
600 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
602 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
603 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
604 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
605 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
606
607 /* Data transfer between ARM and NEON registers. */
608 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
609 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
610 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
611 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
612 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
613 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
614 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
615 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
616 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
617 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
618 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
619 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
620 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
621 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
622 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
623 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
624 /* Half-precision conversion instructions. */
625 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
626 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
627 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
628 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
629 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
630 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
631 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
632 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
633
634 /* Floating point coprocessor (VFP) instructions. */
635 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
636 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
637 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
638 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
639 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
640 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
641 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
642 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
643 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
644 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
645 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
646 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
647 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
648 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
649 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
650 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
651 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
652 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
653 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
654 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
655 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
656 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
657 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
658 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
659 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
660 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
661 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
662 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
663 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
664 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
665 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
666 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
667 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
668 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
669 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
670 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
671 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
672 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
673 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
674 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
675 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
676 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
677 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
678 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
679 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
680 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
681 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
682 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
683 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
684 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
685 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
686 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
687 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
688 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
689 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
690 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
691 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
692 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
693 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
694 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
695 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
696 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
697 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
698 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
699 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
700 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
701 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
702 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
703 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
704 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
705 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
706 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
707 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
708 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
709 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
710 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
711 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
712 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
713 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
714 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
715 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
716 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
717 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
718 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
719 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
720 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
721 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
722 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
723 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
724 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
725 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
726 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
727 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
728 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
729 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
730 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
731 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
732 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
733 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
734 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
735 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
736 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
737 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
738 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
739 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
740 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
741 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
742 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
743 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
744 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
745 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
746 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
747 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
748 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
749 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
750 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
751 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
752 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
753 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
754 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
755 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
756 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
757 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
758 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
759 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
760 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
761 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
762 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
763 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
764 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
765 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
766 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
767 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
768 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
769 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
770 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
771 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
772 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
773
774 /* Cirrus coprocessor instructions. */
775 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
776 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
777 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
778 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
779 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
780 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
781 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
782 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
783 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
784 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
785 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
786 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
787 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
788 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
789 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
790 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
791 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
792 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
793 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
794 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
795 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
796 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
797 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
798 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
799 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
800 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
801 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
802 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
803 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
804 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
805 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
806 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
807 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
808 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
809 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
810 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
811 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
812 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
813 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
814 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
815 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
816 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
817 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
818 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
819 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
820 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
821 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
822 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
823 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
824 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
825 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
826 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
827 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
828 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
829 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
830 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
831 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
832 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
833 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
834 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
835 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
836 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
837 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
838 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
839 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
840 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
841 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
842 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
843 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
844 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
845 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
846 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
847 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
848 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
849 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
850 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
851 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
852 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
853 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
854 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
855 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
856 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
857 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
858 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
859 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
860 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
861 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
862 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
863 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
864 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
865 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
866 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
867 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
868 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
869 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
870 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
871 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
872 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
873 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
874 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
875 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
876 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
877 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
878 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
879 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
880 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
881 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
882 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
883 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
884 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
885 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
886 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
887 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
888 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
889 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
890 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
891 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
892 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
893 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
894 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
895 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
896 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
897 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
898 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
899 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
900 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
901 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
902 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
903 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
904 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
905 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
906 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
907 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
908 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
909 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
910 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
911 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
912 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
913 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
914 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
915 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
916 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
917 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
918 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
919 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
920 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
921 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
922 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
923 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
924 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
925 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
926 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
927 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
928 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
929 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
930 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
931 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
932 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
933 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
934 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
935 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
936 0x0e000600, 0x0ff00f10,
937 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
938 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
939 0x0e100600, 0x0ff00f10,
940 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
941 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
942 0x0e200600, 0x0ff00f10,
943 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
944 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
945 0x0e300600, 0x0ff00f10,
946 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
947
948 /* VFP Fused multiply add instructions. */
949 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
950 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
951 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
952 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
953 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
954 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
955 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
956 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
957 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
958 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
959 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
960 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
961 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
962 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
963 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
964 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
965
966 /* FP v5. */
967 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
968 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
969 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
970 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
971 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
972 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
973 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
974 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
975 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
976 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
977 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
978 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
979 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
980 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
981 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
982 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
983 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
984 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
985 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
986 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
987 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
988 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
989 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
990 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
991
992 /* Generic coprocessor instructions. */
993 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
994 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
995 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
996 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
997 0x0c500000, 0x0ff00000,
998 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
999 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1000 0x0e000000, 0x0f000010,
1001 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1002 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1003 0x0e10f010, 0x0f10f010,
1004 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1005 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1006 0x0e100010, 0x0f100010,
1007 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1008 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1009 0x0e000010, 0x0f100010,
1010 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1011 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1012 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1013 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1014 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1015
1016 /* V6 coprocessor instructions. */
1017 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1018 0xfc500000, 0xfff00000,
1019 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1020 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1021 0xfc400000, 0xfff00000,
1022 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1023
1024 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1025 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1026 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1027 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1028 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1029 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1030 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1031 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1032 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1033 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1034 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1035 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1036 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1037 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1038 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1039 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1040 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1041 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1042 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1043 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1044 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1045
1046 /* Dot Product instructions in the space of coprocessor 13. */
1047 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1048 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1049 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1050 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1051
1052 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1053 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1054 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1055 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1056 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1057 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1058 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1059 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1060 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1061 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1062 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1063 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1064 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1065 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1066 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1067 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1068 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1069
1070 /* V5 coprocessor instructions. */
1071 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1072 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1073 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1074 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1075 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1076 0xfe000000, 0xff000010,
1077 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1078 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1079 0xfe000010, 0xff100010,
1080 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1081 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1082 0xfe100010, 0xff100010,
1083 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1084
1085 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1086 cp_num: bit <11:8> == 0b1001.
1087 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1088 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1089 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1090 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1091 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1092 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1093 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1094 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1095 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1096 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1097 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1098 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1099 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1100 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1101 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1102 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1103 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1104 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1105 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1106 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1107 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1108 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1109 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1110 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1111 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1112 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1113 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1114 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1115 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1116 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1117 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1118 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1119 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1120 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1121 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1122 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1123 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1124 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1125 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1126 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1127 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1128 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1129 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1130 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1131 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1132 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1133 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1134 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1135 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1136 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1137 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1138 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1139 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1140 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1141 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1142 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1143 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1144 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1145 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1146 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1147 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1148 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1149 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1150 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1151 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1152 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1153 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1154 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1155 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1156 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1157 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1158
1159 /* ARMv8.3 javascript conversion instruction. */
1160 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1161 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1162
1163 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1164 };
1165
1166 /* Neon opcode table: This does not encode the top byte -- that is
1167 checked by the print_insn_neon routine, as it depends on whether we are
1168 doing thumb32 or arm32 disassembly. */
1169
1170 /* print_insn_neon recognizes the following format control codes:
1171
1172 %% %
1173
1174 %c print condition code
1175 %u print condition code (unconditional in ARM mode,
1176 UNPREDICTABLE if not AL in Thumb)
1177 %A print v{st,ld}[1234] operands
1178 %B print v{st,ld}[1234] any one operands
1179 %C print v{st,ld}[1234] single->all operands
1180 %D print scalar
1181 %E print vmov, vmvn, vorr, vbic encoded constant
1182 %F print vtbl,vtbx register list
1183
1184 %<bitfield>r print as an ARM register
1185 %<bitfield>d print the bitfield in decimal
1186 %<bitfield>e print the 2^N - bitfield in decimal
1187 %<bitfield>D print as a NEON D register
1188 %<bitfield>Q print as a NEON Q register
1189 %<bitfield>R print as a NEON D or Q register
1190 %<bitfield>Sn print byte scaled width limited by n
1191 %<bitfield>Tn print short scaled width limited by n
1192 %<bitfield>Un print long scaled width limited by n
1193
1194 %<bitfield>'c print specified char iff bitfield is all ones
1195 %<bitfield>`c print specified char iff bitfield is all zeroes
1196 %<bitfield>?ab... select from array of values in big endian order. */
1197
1198 static const struct opcode32 neon_opcodes[] =
1199 {
1200 /* Extract. */
1201 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1202 0xf2b00840, 0xffb00850,
1203 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1204 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1205 0xf2b00000, 0xffb00810,
1206 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1207
1208 /* Data transfer between ARM and NEON registers. */
1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1213 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1220 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1221
1222 /* Move data element to all lanes. */
1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1224 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1229
1230 /* Table lookup. */
1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1233 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1235
1236 /* Half-precision conversions. */
1237 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1238 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1239 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1240 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1241
1242 /* NEON fused multiply add instructions. */
1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1244 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1245 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1246 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1247 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1248 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1250 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1251
1252 /* Two registers, miscellaneous. */
1253 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1254 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1255 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1256 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1257 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1258 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1260 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1261 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1262 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1263 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1264 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1265 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1266 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1267 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1268 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1269 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1270 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1271 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1272 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1273 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1274 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf3b20300, 0xffb30fd0,
1297 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1299 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1300 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1301 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1302 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1303 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1304 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1305 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1306 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1307 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1308 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1309 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1311 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1312 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1313 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1314 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1315 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1319 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1325 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf3bb0600, 0xffbf0e10,
1346 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1347 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1348 0xf3b70600, 0xffbf0e10,
1349 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1350
1351 /* Three registers of the same length. */
1352 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1353 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1354 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1355 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1356 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1357 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1358 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1359 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1360 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1361 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1362 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1363 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1364 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1365 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1366 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1367 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1368 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1369 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1371 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1372 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1373 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1379 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1385 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1387 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1392 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1393 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1397 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1400 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1401 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1404 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1405 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1409 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1412 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1413 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1416 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1417 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1420 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1421 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1425 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1428 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1429 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1432 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1433 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1436 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1437 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1441 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1445 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1448 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1449 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1452 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1453 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1456 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1457 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1460 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1461 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf2000b00, 0xff800f10,
1470 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472 0xf2000b10, 0xff800f10,
1473 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf3000b00, 0xff800f10,
1482 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf2000000, 0xfe800f10,
1485 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf2000010, 0xfe800f10,
1488 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf2000100, 0xfe800f10,
1491 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493 0xf2000200, 0xfe800f10,
1494 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496 0xf2000210, 0xfe800f10,
1497 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499 0xf2000300, 0xfe800f10,
1500 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf2000310, 0xfe800f10,
1503 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1505 0xf2000400, 0xfe800f10,
1506 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf2000410, 0xfe800f10,
1509 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1511 0xf2000500, 0xfe800f10,
1512 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf2000510, 0xfe800f10,
1515 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1517 0xf2000600, 0xfe800f10,
1518 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf2000610, 0xfe800f10,
1521 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1523 0xf2000700, 0xfe800f10,
1524 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526 0xf2000710, 0xfe800f10,
1527 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1528 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1529 0xf2000910, 0xfe800f10,
1530 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf2000a00, 0xfe800f10,
1533 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1535 0xf2000a10, 0xfe800f10,
1536 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1538 0xf3000b10, 0xff800f10,
1539 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1540 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1541 0xf3000c10, 0xff800f10,
1542 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1543
1544 /* One register and an immediate value. */
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1555 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1556 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1562 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1568 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1571
1572 /* Two registers and a shift amount. */
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1574 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf2880950, 0xfeb80fd0,
1585 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1588 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1589 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1595 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1607 0xf2900950, 0xfeb00fd0,
1608 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf2a00950, 0xfea00fd0,
1653 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1659 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1661 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1663 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1665 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1667 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1669 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1671 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1673 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1675 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1677 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1679 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1683 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf2a00e10, 0xfea00e90,
1692 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1694 0xf2a00c10, 0xfea00e90,
1695 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1696
1697 /* Three registers of different lengths. */
1698 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1699 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703 0xf2800400, 0xff800f50,
1704 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf2800600, 0xff800f50,
1707 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709 0xf2800900, 0xff800f50,
1710 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf2800b00, 0xff800f50,
1713 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1715 0xf2800d00, 0xff800f50,
1716 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718 0xf3800400, 0xff800f50,
1719 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721 0xf3800600, 0xff800f50,
1722 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724 0xf2800000, 0xfe800f50,
1725 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1727 0xf2800100, 0xfe800f50,
1728 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730 0xf2800200, 0xfe800f50,
1731 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1733 0xf2800300, 0xfe800f50,
1734 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736 0xf2800500, 0xfe800f50,
1737 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1739 0xf2800700, 0xfe800f50,
1740 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1742 0xf2800800, 0xfe800f50,
1743 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745 0xf2800a00, 0xfe800f50,
1746 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1747 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1748 0xf2800c00, 0xfe800f50,
1749 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1750
1751 /* Two registers and a scalar. */
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1755 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1756 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1757 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1764 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1765 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1767 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1772 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1773 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1780 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1781 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1782 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1783 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1784 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1785 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1790 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1791 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1792 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1793 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1794 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1795 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1796 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1797 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1798 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1799 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1800 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1801 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803 0xf2800240, 0xfe800f50,
1804 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf2800640, 0xfe800f50,
1807 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809 0xf2800a40, 0xfe800f50,
1810 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1812 0xf2800e40, 0xff800f50,
1813 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1815 0xf2800f40, 0xff800f50,
1816 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1818 0xf3800e40, 0xff800f50,
1819 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1821 0xf3800f40, 0xff800f50,
1822 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1823 },
1824
1825 /* Element and structure load/store. */
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1829 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1831 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1835 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1841 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1843 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1847 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1848 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1849 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1851 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1853 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1854 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1855 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1856 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1857 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1858 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1859 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1861 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1862 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1863 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1864
1865 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1866 };
1867
1868 /* mve opcode table. */
1869
1870 /* print_insn_mve recognizes the following format control codes:
1871
1872 %% %
1873
1874 %a print '+' or '-' or imm offset in vldr[bhwd] and
1875 vstr[bhwd]
1876 %c print condition code
1877 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1878 %u print 'U' (unsigned) or 'S' for various mve instructions
1879 %i print MVE predicate(s) for vpt and vpst
1880 %m print rounding mode for vcvt and vrint
1881 %n print vector comparison code for predicated instruction
1882 %s print size for various vcvt instructions
1883 %v print vector predicate for instruction in predicated
1884 block
1885 %o print offset scaled for vldr[hwd] and vstr[hwd]
1886 %w print writeback mode for MVE v{st,ld}[24]
1887 %B print v{st,ld}[24] any one operands
1888
1889 %<bitfield>r print as an ARM register
1890 %<bitfield>d print the bitfield in decimal
1891 %<bitfield>Q print as a MVE Q register
1892 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1893 UNPREDICTABLE
1894 %<bitfield>s print size for vector predicate & non VMOV instructions
1895 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1896 %<bitfield>k print immediate for vector conversion instruction
1897 */
1898
1899 static const struct mopcode32 mve_opcodes[] =
1900 {
1901 /* MVE. */
1902
1903 {ARM_FEATURE_COPROC (FPU_MVE),
1904 MVE_VPST,
1905 0xfe310f4d, 0xffbf1fff,
1906 "vpst%i"
1907 },
1908
1909 /* Floating point VPT T1. */
1910 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1911 MVE_VPT_FP_T1,
1912 0xee310f00, 0xefb10f50,
1913 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1914 /* Floating point VPT T2. */
1915 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1916 MVE_VPT_FP_T2,
1917 0xee310f40, 0xefb10f50,
1918 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1919
1920 /* Vector VPT T1. */
1921 {ARM_FEATURE_COPROC (FPU_MVE),
1922 MVE_VPT_VEC_T1,
1923 0xfe010f00, 0xff811f51,
1924 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1925 /* Vector VPT T2. */
1926 {ARM_FEATURE_COPROC (FPU_MVE),
1927 MVE_VPT_VEC_T2,
1928 0xfe010f01, 0xff811f51,
1929 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1930 /* Vector VPT T3. */
1931 {ARM_FEATURE_COPROC (FPU_MVE),
1932 MVE_VPT_VEC_T3,
1933 0xfe011f00, 0xff811f50,
1934 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1935 /* Vector VPT T4. */
1936 {ARM_FEATURE_COPROC (FPU_MVE),
1937 MVE_VPT_VEC_T4,
1938 0xfe010f40, 0xff811f70,
1939 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
1940 /* Vector VPT T5. */
1941 {ARM_FEATURE_COPROC (FPU_MVE),
1942 MVE_VPT_VEC_T5,
1943 0xfe010f60, 0xff811f70,
1944 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
1945 /* Vector VPT T6. */
1946 {ARM_FEATURE_COPROC (FPU_MVE),
1947 MVE_VPT_VEC_T6,
1948 0xfe011f40, 0xff811f50,
1949 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
1950
1951 /* Vector VCMP floating point T1. */
1952 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1953 MVE_VCMP_FP_T1,
1954 0xee310f00, 0xeff1ef50,
1955 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
1956
1957 /* Vector VCMP floating point T2. */
1958 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1959 MVE_VCMP_FP_T2,
1960 0xee310f40, 0xeff1ef50,
1961 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
1962
1963 /* Vector VCMP T1. */
1964 {ARM_FEATURE_COPROC (FPU_MVE),
1965 MVE_VCMP_VEC_T1,
1966 0xfe010f00, 0xffc1ff51,
1967 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1968 /* Vector VCMP T2. */
1969 {ARM_FEATURE_COPROC (FPU_MVE),
1970 MVE_VCMP_VEC_T2,
1971 0xfe010f01, 0xffc1ff51,
1972 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1973 /* Vector VCMP T3. */
1974 {ARM_FEATURE_COPROC (FPU_MVE),
1975 MVE_VCMP_VEC_T3,
1976 0xfe011f00, 0xffc1ff50,
1977 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1978 /* Vector VCMP T4. */
1979 {ARM_FEATURE_COPROC (FPU_MVE),
1980 MVE_VCMP_VEC_T4,
1981 0xfe010f40, 0xffc1ff70,
1982 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
1983 /* Vector VCMP T5. */
1984 {ARM_FEATURE_COPROC (FPU_MVE),
1985 MVE_VCMP_VEC_T5,
1986 0xfe010f60, 0xffc1ff70,
1987 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
1988 /* Vector VCMP T6. */
1989 {ARM_FEATURE_COPROC (FPU_MVE),
1990 MVE_VCMP_VEC_T6,
1991 0xfe011f40, 0xffc1ff50,
1992 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
1993
1994 /* Vector VDUP. */
1995 {ARM_FEATURE_COPROC (FPU_MVE),
1996 MVE_VDUP,
1997 0xeea00b10, 0xffb10f5f,
1998 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
1999
2000 /* Vector VEOR. */
2001 {ARM_FEATURE_COPROC (FPU_MVE),
2002 MVE_VEOR,
2003 0xff000150, 0xffd11f51,
2004 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2005
2006 /* Vector VFMA, vector * scalar. */
2007 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2008 MVE_VFMA_FP_SCALAR,
2009 0xee310e40, 0xefb11f70,
2010 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2011
2012 /* Vector VFMA floating point. */
2013 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2014 MVE_VFMA_FP,
2015 0xef000c50, 0xffa11f51,
2016 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2017
2018 /* Vector VFMS floating point. */
2019 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2020 MVE_VFMS_FP,
2021 0xef200c50, 0xffa11f51,
2022 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2023
2024 /* Vector VFMAS, vector * scalar. */
2025 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2026 MVE_VFMAS_FP_SCALAR,
2027 0xee311e40, 0xefb11f70,
2028 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2029
2030 /* Vector VHADD T1. */
2031 {ARM_FEATURE_COPROC (FPU_MVE),
2032 MVE_VHADD_T1,
2033 0xef000040, 0xef811f51,
2034 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2035
2036 /* Vector VHADD T2. */
2037 {ARM_FEATURE_COPROC (FPU_MVE),
2038 MVE_VHADD_T2,
2039 0xee000f40, 0xef811f70,
2040 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2041
2042 /* Vector VHSUB T1. */
2043 {ARM_FEATURE_COPROC (FPU_MVE),
2044 MVE_VHSUB_T1,
2045 0xef000240, 0xef811f51,
2046 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2047
2048 /* Vector VHSUB T2. */
2049 {ARM_FEATURE_COPROC (FPU_MVE),
2050 MVE_VHSUB_T2,
2051 0xee001f40, 0xef811f70,
2052 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2053
2054 /* Vector VDUP. */
2055 {ARM_FEATURE_COPROC (FPU_MVE),
2056 MVE_VDUP,
2057 0xeea00b10, 0xffb10f5f,
2058 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2059
2060 /* Vector VRHADD. */
2061 {ARM_FEATURE_COPROC (FPU_MVE),
2062 MVE_VRHADD,
2063 0xef000140, 0xef811f51,
2064 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2065
2066 /* Vector VCVT. */
2067 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2068 MVE_VCVT_FP_FIX_VEC,
2069 0xef800c50, 0xef801cd1,
2070 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2071
2072 /* Vector VCVT. */
2073 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2074 MVE_VCVT_BETWEEN_FP_INT,
2075 0xffb30640, 0xffb31e51,
2076 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2077
2078 /* Vector VCVT between single and half-precision float, bottom half. */
2079 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2080 MVE_VCVT_FP_HALF_FP,
2081 0xee3f0e01, 0xefbf1fd1,
2082 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2083
2084 /* Vector VCVT between single and half-precision float, top half. */
2085 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2086 MVE_VCVT_FP_HALF_FP,
2087 0xee3f1e01, 0xefbf1fd1,
2088 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2089
2090 /* Vector VCVT. */
2091 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2092 MVE_VCVT_FROM_FP_TO_INT,
2093 0xffb30040, 0xffb31c51,
2094 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2095
2096 /* Vector VLD2. */
2097 {ARM_FEATURE_COPROC (FPU_MVE),
2098 MVE_VLD2,
2099 0xfc901e00, 0xff901e5f,
2100 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2101
2102 /* Vector VLD4. */
2103 {ARM_FEATURE_COPROC (FPU_MVE),
2104 MVE_VLD4,
2105 0xfc901e01, 0xff901e1f,
2106 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2107
2108 /* Vector VLDRB gather load. */
2109 {ARM_FEATURE_COPROC (FPU_MVE),
2110 MVE_VLDRB_GATHER_T1,
2111 0xec900e00, 0xefb01e50,
2112 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2113
2114 /* Vector VLDRH gather load. */
2115 {ARM_FEATURE_COPROC (FPU_MVE),
2116 MVE_VLDRH_GATHER_T2,
2117 0xec900e10, 0xefb01e50,
2118 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2119
2120 /* Vector VLDRW gather load. */
2121 {ARM_FEATURE_COPROC (FPU_MVE),
2122 MVE_VLDRW_GATHER_T3,
2123 0xfc900f40, 0xffb01fd0,
2124 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2125
2126 /* Vector VLDRD gather load. */
2127 {ARM_FEATURE_COPROC (FPU_MVE),
2128 MVE_VLDRD_GATHER_T4,
2129 0xec900fd0, 0xefb01fd0,
2130 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2131
2132 /* Vector VLDRW gather load. */
2133 {ARM_FEATURE_COPROC (FPU_MVE),
2134 MVE_VLDRW_GATHER_T5,
2135 0xfd101e00, 0xff111f00,
2136 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2137
2138 /* Vector VLDRD gather load, variant T6. */
2139 {ARM_FEATURE_COPROC (FPU_MVE),
2140 MVE_VLDRD_GATHER_T6,
2141 0xfd101f00, 0xff111f00,
2142 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2143
2144 /* Vector VLDRB. */
2145 {ARM_FEATURE_COPROC (FPU_MVE),
2146 MVE_VLDRB_T1,
2147 0xec100e00, 0xee581e00,
2148 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2149
2150 /* Vector VLDRH. */
2151 {ARM_FEATURE_COPROC (FPU_MVE),
2152 MVE_VLDRH_T2,
2153 0xec180e00, 0xee581e00,
2154 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2155
2156 /* Vector VLDRB unsigned, variant T5. */
2157 {ARM_FEATURE_COPROC (FPU_MVE),
2158 MVE_VLDRB_T5,
2159 0xec101e00, 0xfe101f80,
2160 "vldrb%v.u8\t%13-15,22Q, %d"},
2161
2162 /* Vector VLDRH unsigned, variant T6. */
2163 {ARM_FEATURE_COPROC (FPU_MVE),
2164 MVE_VLDRH_T6,
2165 0xec101e80, 0xfe101f80,
2166 "vldrh%v.u16\t%13-15,22Q, %d"},
2167
2168 /* Vector VLDRW unsigned, variant T7. */
2169 {ARM_FEATURE_COPROC (FPU_MVE),
2170 MVE_VLDRW_T7,
2171 0xec101f00, 0xfe101f80,
2172 "vldrw%v.u32\t%13-15,22Q, %d"},
2173
2174 /* Vector VRINT floating point. */
2175 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2176 MVE_VRINT_FP,
2177 0xffb20440, 0xffb31c51,
2178 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2179
2180 /* Vector VST2 no writeback. */
2181 {ARM_FEATURE_COPROC (FPU_MVE),
2182 MVE_VST2,
2183 0xfc801e00, 0xffb01e5f,
2184 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2185
2186 /* Vector VST2 writeback. */
2187 {ARM_FEATURE_COPROC (FPU_MVE),
2188 MVE_VST2,
2189 0xfca01e00, 0xffb01e5f,
2190 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2191
2192 /* Vector VST4 no writeback. */
2193 {ARM_FEATURE_COPROC (FPU_MVE),
2194 MVE_VST4,
2195 0xfc801e01, 0xffb01e1f,
2196 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2197
2198 /* Vector VST4 writeback. */
2199 {ARM_FEATURE_COPROC (FPU_MVE),
2200 MVE_VST4,
2201 0xfca01e01, 0xffb01e1f,
2202 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2203
2204 /* Vector VSTRB scatter store, T1 variant. */
2205 {ARM_FEATURE_COPROC (FPU_MVE),
2206 MVE_VSTRB_SCATTER_T1,
2207 0xec800e00, 0xffb01e50,
2208 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2209
2210 /* Vector VSTRH scatter store, T2 variant. */
2211 {ARM_FEATURE_COPROC (FPU_MVE),
2212 MVE_VSTRH_SCATTER_T2,
2213 0xec800e10, 0xffb01e50,
2214 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2215
2216 /* Vector VSTRW scatter store, T3 variant. */
2217 {ARM_FEATURE_COPROC (FPU_MVE),
2218 MVE_VSTRW_SCATTER_T3,
2219 0xec800e40, 0xffb01e50,
2220 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2221
2222 /* Vector VSTRD scatter store, T4 variant. */
2223 {ARM_FEATURE_COPROC (FPU_MVE),
2224 MVE_VSTRD_SCATTER_T4,
2225 0xec800fd0, 0xffb01fd0,
2226 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2227
2228 /* Vector VSTRW scatter store, T5 variant. */
2229 {ARM_FEATURE_COPROC (FPU_MVE),
2230 MVE_VSTRW_SCATTER_T5,
2231 0xfd001e00, 0xff111f00,
2232 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2233
2234 /* Vector VSTRD scatter store, T6 variant. */
2235 {ARM_FEATURE_COPROC (FPU_MVE),
2236 MVE_VSTRD_SCATTER_T6,
2237 0xfd001f00, 0xff111f00,
2238 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2239
2240 /* Vector VSTRB. */
2241 {ARM_FEATURE_COPROC (FPU_MVE),
2242 MVE_VSTRB_T1,
2243 0xec000e00, 0xfe581e00,
2244 "vstrb%v.%7-8s\t%13-15Q, %d"},
2245
2246 /* Vector VSTRH. */
2247 {ARM_FEATURE_COPROC (FPU_MVE),
2248 MVE_VSTRH_T2,
2249 0xec080e00, 0xfe581e00,
2250 "vstrh%v.%7-8s\t%13-15Q, %d"},
2251
2252 /* Vector VSTRB variant T5. */
2253 {ARM_FEATURE_COPROC (FPU_MVE),
2254 MVE_VSTRB_T5,
2255 0xec001e00, 0xfe101f80,
2256 "vstrb%v.8\t%13-15,22Q, %d"},
2257
2258 /* Vector VSTRH variant T6. */
2259 {ARM_FEATURE_COPROC (FPU_MVE),
2260 MVE_VSTRH_T6,
2261 0xec001e80, 0xfe101f80,
2262 "vstrh%v.16\t%13-15,22Q, %d"},
2263
2264 /* Vector VSTRW variant T7. */
2265 {ARM_FEATURE_COPROC (FPU_MVE),
2266 MVE_VSTRW_T7,
2267 0xec001f00, 0xfe101f80,
2268 "vstrw%v.32\t%13-15,22Q, %d"},
2269
2270 {ARM_FEATURE_CORE_LOW (0),
2271 MVE_NONE,
2272 0x00000000, 0x00000000, 0}
2273 };
2274
2275 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
2276 ordered: they must be searched linearly from the top to obtain a correct
2277 match. */
2278
2279 /* print_insn_arm recognizes the following format control codes:
2280
2281 %% %
2282
2283 %a print address for ldr/str instruction
2284 %s print address for ldr/str halfword/signextend instruction
2285 %S like %s but allow UNPREDICTABLE addressing
2286 %b print branch destination
2287 %c print condition code (always bits 28-31)
2288 %m print register mask for ldm/stm instruction
2289 %o print operand2 (immediate or register + shift)
2290 %p print 'p' iff bits 12-15 are 15
2291 %t print 't' iff bit 21 set and bit 24 clear
2292 %B print arm BLX(1) destination
2293 %C print the PSR sub type.
2294 %U print barrier type.
2295 %P print address for pli instruction.
2296
2297 %<bitfield>r print as an ARM register
2298 %<bitfield>T print as an ARM register + 1
2299 %<bitfield>R as %r but r15 is UNPREDICTABLE
2300 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2301 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
2302 %<bitfield>d print the bitfield in decimal
2303 %<bitfield>W print the bitfield plus one in decimal
2304 %<bitfield>x print the bitfield in hex
2305 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2306
2307 %<bitfield>'c print specified char iff bitfield is all ones
2308 %<bitfield>`c print specified char iff bitfield is all zeroes
2309 %<bitfield>?ab... select from array of values in big endian order
2310
2311 %e print arm SMI operand (bits 0..7,8..19).
2312 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
2313 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
2314 %R print the SPSR/CPSR or banked register of an MRS. */
2315
2316 static const struct opcode32 arm_opcodes[] =
2317 {
2318 /* ARM instructions. */
2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2320 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2322 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2323
2324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
2325 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2327 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2329 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
2331 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2333 0x00800090, 0x0fa000f0,
2334 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2336 0x00a00090, 0x0fa000f0,
2337 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2338
2339 /* V8.2 RAS extension instructions. */
2340 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
2341 0xe320f010, 0xffffffff, "esb"},
2342
2343 /* V8 instructions. */
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2345 0x0320f005, 0x0fffffff, "sevl"},
2346 /* Defined in V8 but is in NOP space so available to all arch. */
2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2348 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
2349 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
2350 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2352 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2354 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2356 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2358 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2360 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2361 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2362 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
2363 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2364 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2365 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2366 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2368 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2370 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2372 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2373 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2374 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
2375 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2376 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2377 /* CRC32 instructions. */
2378 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2379 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
2380 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2381 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
2382 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2383 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
2384 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2385 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
2386 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2387 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
2388 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2389 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
2390
2391 /* Privileged Access Never extension instructions. */
2392 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
2393 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
2394
2395 /* Virtualization Extension instructions. */
2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
2398
2399 /* Integer Divide Extension instructions. */
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2401 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2403 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
2404
2405 /* MP Extension instructions. */
2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
2407
2408 /* Speculation Barriers. */
2409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
2411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
2412
2413 /* V7 instructions. */
2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
2416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
2418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
2419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2422 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
2423
2424 /* ARM V6T2 instructions. */
2425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2426 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2428 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2430 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2432 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
2433
2434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2435 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2437 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
2438
2439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2440 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
2441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2442 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
2443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2444 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
2445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2446 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
2447
2448 /* ARM Security extension instructions. */
2449 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
2450 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2451
2452 /* ARM V6K instructions. */
2453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2454 0xf57ff01f, 0xffffffff, "clrex"},
2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2456 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2458 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
2459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2460 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2462 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
2463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2464 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
2465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2466 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
2467
2468 /* ARMv8.5-A instructions. */
2469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
2470
2471 /* ARM V6K NOP hints. */
2472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2473 0x0320f001, 0x0fffffff, "yield%c"},
2474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2475 0x0320f002, 0x0fffffff, "wfe%c"},
2476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2477 0x0320f003, 0x0fffffff, "wfi%c"},
2478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2479 0x0320f004, 0x0fffffff, "sev%c"},
2480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2481 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
2482
2483 /* ARM V6 instructions. */
2484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2485 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2487 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2489 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2491 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2493 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2495 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2497 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2499 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2501 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2503 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2505 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2507 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2509 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2511 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2513 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2515 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2517 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2519 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2521 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2523 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2525 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2527 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2529 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2531 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2533 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2535 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2537 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2539 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2541 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2543 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2545 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2547 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2549 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2551 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2553 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2555 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2557 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2559 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2561 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2563 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2565 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2567 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2569 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2571 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2573 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2575 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2577 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2579 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2581 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2583 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2585 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2587 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2589 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2591 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2593 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2595 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2597 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2599 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2601 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2603 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2605 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2607 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2609 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2611 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2613 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2615 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2617 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2619 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2621 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2623 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2625 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2627 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2629 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2631 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2633 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2635 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2637 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2639 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2641 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2643 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2645 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2647 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2649 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2651 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2653 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2655 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2657 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2659 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2661 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2663 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2665 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2667 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2669 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2671 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2673 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2675 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2677 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2679 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2681 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2683 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2685 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2687 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2689 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2691 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2693 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2695 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2697 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2699 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2701 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2703 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2705 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2707 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2709 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2711 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2713 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2715 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2717 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2719 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2721 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2723 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2725 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2727 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2728
2729 /* V5J instruction. */
2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2731 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2732
2733 /* V5 Instructions. */
2734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2735 0xe1200070, 0xfff000f0,
2736 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2738 0xfa000000, 0xfe000000, "blx\t%B"},
2739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2740 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2742 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2743
2744 /* V5E "El Segundo" Instructions. */
2745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2746 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2748 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2750 0xf450f000, 0xfc70f000, "pld\t%a"},
2751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2752 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2754 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2756 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2758 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2759
2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2761 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2763 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2764
2765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2766 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2768 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2770 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2772 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2773
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2775 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2777 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2779 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2781 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2782
2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2784 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2786 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2787
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2789 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2791 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2793 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2795 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2796
2797 /* ARM Instructions. */
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2799 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2800
2801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2802 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2804 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2806 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2808 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2810 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2812 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2813
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2815 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2817 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2819 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2821 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2822
2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2824 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2826 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2828 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2830 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2831
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2833 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2835 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2837 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2838
2839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2840 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2842 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2844 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2845
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2847 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2849 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2851 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2852
2853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2854 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2856 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2858 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2859
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2861 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2863 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2865 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2866
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2868 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2870 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2872 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2873
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2875 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2877 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2879 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2880
2881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2882 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2884 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2886 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2887
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2889 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2891 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2893 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2894
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2896 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2898 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2900 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2901
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2903 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2905 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2907 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2908
2909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2910 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2912 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2914 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2915
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2917 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2919 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2921 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2922
2923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2924 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2926 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2928 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2929
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2931 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2933 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2935 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2937 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2939 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2941 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2943 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2944
2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2946 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2948 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2950 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2951
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2953 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2955 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2957 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2958
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2960 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2962 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2963
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2965 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2966
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2968 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2970 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2971
2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2973 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2975 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2977 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2979 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2981 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2983 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2985 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2987 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2989 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2991 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2993 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2995 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2997 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2999 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3001 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3003 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3005 0x092d0000, 0x0fff0000, "push%c\t%m"},
3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3007 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3009 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3010
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3012 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3014 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3016 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3018 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3020 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3022 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3024 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3026 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3028 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3030 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3032 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3034 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3036 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3038 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3040 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3042 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3044 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3046 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3048 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3049
3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3051 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3053 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
3054
3055 /* The rest. */
3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3057 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3059 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3060 {ARM_FEATURE_CORE_LOW (0),
3061 0x00000000, 0x00000000, 0}
3062 };
3063
3064 /* print_insn_thumb16 recognizes the following format control codes:
3065
3066 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3067 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3068 %<bitfield>I print bitfield as a signed decimal
3069 (top bit of range being the sign bit)
3070 %N print Thumb register mask (with LR)
3071 %O print Thumb register mask (with PC)
3072 %M print Thumb register mask
3073 %b print CZB's 6-bit unsigned branch destination
3074 %s print Thumb right-shift immediate (6..10; 0 == 32).
3075 %c print the condition code
3076 %C print the condition code, or "s" if not conditional
3077 %x print warning if conditional an not at end of IT block"
3078 %X print "\t; unpredictable <IT:code>" if conditional
3079 %I print IT instruction suffix and operands
3080 %W print Thumb Writeback indicator for LDMIA
3081 %<bitfield>r print bitfield as an ARM register
3082 %<bitfield>d print bitfield as a decimal
3083 %<bitfield>H print (bitfield * 2) as a decimal
3084 %<bitfield>W print (bitfield * 4) as a decimal
3085 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3086 %<bitfield>B print Thumb branch destination (signed displacement)
3087 %<bitfield>c print bitfield as a condition code
3088 %<bitnum>'c print specified char iff bit is one
3089 %<bitnum>?ab print a if bit is one else print b. */
3090
3091 static const struct opcode16 thumb_opcodes[] =
3092 {
3093 /* Thumb instructions. */
3094
3095 /* ARMv8-M Security Extensions instructions. */
3096 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
3097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
3098
3099 /* ARM V8 instructions. */
3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
3102 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
3103
3104 /* ARM V6K no-argument instructions. */
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
3108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
3111
3112 /* ARM V6T2 instructions. */
3113 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3114 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3115 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3116 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
3118
3119 /* ARM V6. */
3120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
3131
3132 /* ARM V5 ISA extends Thumb. */
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3134 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
3135 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3137 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
3138 /* ARM V4T ISA (Thumb v1). */
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3140 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
3141 /* Format 4. */
3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
3158 /* format 13 */
3159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
3161 /* format 5 */
3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
3163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
3166 /* format 14 */
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
3169 /* format 2 */
3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3171 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3173 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3175 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3177 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
3178 /* format 8 */
3179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3180 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3182 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3184 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
3185 /* format 7 */
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3187 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3189 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3190 /* format 1 */
3191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3193 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
3196 /* format 3 */
3197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
3201 /* format 6 */
3202 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3204 0x4800, 0xF800,
3205 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
3206 /* format 9 */
3207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3208 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3210 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3212 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3214 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
3215 /* format 10 */
3216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3217 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3219 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
3220 /* format 11 */
3221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3222 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3224 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
3225 /* format 12 */
3226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3227 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3229 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
3230 /* format 15 */
3231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
3233 /* format 17 */
3234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
3235 /* format 16 */
3236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
3238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
3239 /* format 18 */
3240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
3241
3242 /* The E800 .. FFFF range is unconditionally redirected to the
3243 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3244 are processed via that table. Thus, we can never encounter a
3245 bare "second half of BL/BLX(1)" instruction here. */
3246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
3247 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3248 };
3249
3250 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
3251 We adopt the convention that hw1 is the high 16 bits of .value and
3252 .mask, hw2 the low 16 bits.
3253
3254 print_insn_thumb32 recognizes the following format control codes:
3255
3256 %% %
3257
3258 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3259 %M print a modified 12-bit immediate (same location)
3260 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3261 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
3262 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
3263 %S print a possibly-shifted Rm
3264
3265 %L print address for a ldrd/strd instruction
3266 %a print the address of a plain load/store
3267 %w print the width and signedness of a core load/store
3268 %m print register mask for ldm/stm
3269 %n print register mask for clrm
3270
3271 %E print the lsb and width fields of a bfc/bfi instruction
3272 %F print the lsb and width fields of a sbfx/ubfx instruction
3273 %G print a fallback offset for Branch Future instructions
3274 %W print an offset for BF instruction
3275 %Y print an offset for BFL instruction
3276 %Z print an offset for BFCSEL instruction
3277 %Q print an offset for Low Overhead Loop instructions
3278 %P print an offset for Low Overhead Loop end instructions
3279 %b print a conditional branch offset
3280 %B print an unconditional branch offset
3281 %s print the shift field of an SSAT instruction
3282 %R print the rotation field of an SXT instruction
3283 %U print barrier type.
3284 %P print address for pli instruction.
3285 %c print the condition code
3286 %x print warning if conditional an not at end of IT block"
3287 %X print "\t; unpredictable <IT:code>" if conditional
3288
3289 %<bitfield>d print bitfield in decimal
3290 %<bitfield>D print bitfield plus one in decimal
3291 %<bitfield>W print bitfield*4 in decimal
3292 %<bitfield>r print bitfield as an ARM register
3293 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
3294 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
3295 %<bitfield>c print bitfield as a condition code
3296
3297 %<bitfield>'c print specified char iff bitfield is all ones
3298 %<bitfield>`c print specified char iff bitfield is all zeroes
3299 %<bitfield>?ab... select from array of values in big endian order
3300
3301 With one exception at the bottom (done because BL and BLX(1) need
3302 to come dead last), this table was machine-sorted first in
3303 decreasing order of number of bits set in the mask, then in
3304 increasing numeric order of mask, then in increasing numeric order
3305 of opcode. This order is not the clearest for a human reader, but
3306 is guaranteed never to catch a special-case bit pattern with a more
3307 general mask, which is important, because this instruction encoding
3308 makes heavy use of special-case bit patterns. */
3309 static const struct opcode32 thumb32_opcodes[] =
3310 {
3311 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3312 instructions. */
3313 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3314 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3316 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3317 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3318 0xf02fc001, 0xfffff001, "le\t%P"},
3319 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3320 0xf00fc001, 0xfffff001, "le\tlr, %P"},
3321
3322 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3323 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
3324 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3325 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
3326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3327 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
3328 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3329 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
3330 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3331 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
3332
3333 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3334 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
3335
3336 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
3337 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
3338 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3339 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3340 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3341 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
3342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3343 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3344 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3345 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
3346
3347 /* ARM V8.2 RAS extension instructions. */
3348 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3349 0xf3af8010, 0xffffffff, "esb"},
3350
3351 /* V8 instructions. */
3352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3353 0xf3af8005, 0xffffffff, "sevl%c.w"},
3354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3355 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3357 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3359 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3361 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3363 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3365 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
3366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3367 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
3368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3369 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
3370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3371 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3373 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3375 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
3376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3377 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3379 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3381 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3383 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
3384
3385 /* CRC32 instructions. */
3386 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3387 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
3388 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3389 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
3390 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3391 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
3392 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3393 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
3394 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3395 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
3396 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3397 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
3398
3399 /* Speculation Barriers. */
3400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
3401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
3402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
3403
3404 /* V7 instructions. */
3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
3406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
3408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
3409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3412 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3413 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3414 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3415 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
3416
3417 /* Virtualization Extension instructions. */
3418 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
3419 /* We skip ERET as that is SUBS pc, lr, #0. */
3420
3421 /* MP Extension instructions. */
3422 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
3423
3424 /* Security extension instructions. */
3425 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
3426
3427 /* ARMv8.5-A instructions. */
3428 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
3429
3430 /* Instructions defined in the basic V6T2 set. */
3431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
3432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
3433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
3434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
3435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
3436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3437 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
3439
3440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3441 0xf3bf8f2f, 0xffffffff, "clrex%c"},
3442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3443 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3445 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3447 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3449 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3451 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3453 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3455 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3457 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3459 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3461 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3463 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3465 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3467 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
3468 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3469 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
3470 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3471 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3473 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3475 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3477 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3479 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3481 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3483 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3485 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3487 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
3488 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3489 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3491 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3493 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3495 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3497 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3499 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3501 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3503 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3505 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3507 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3509 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3511 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3513 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3515 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3517 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3519 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3521 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3523 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3525 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3527 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3529 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3531 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3533 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3535 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3537 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3539 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3541 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3543 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3545 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3547 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3549 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3551 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3553 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3555 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3557 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3559 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3561 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3563 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3565 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3567 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3569 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3571 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3573 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3575 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3577 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3579 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3581 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3583 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3585 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3587 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3589 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3591 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3593 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3595 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
3596 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3597 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3599 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
3600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3601 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3603 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3605 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3607 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3609 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3611 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3613 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3615 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3617 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3619 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3621 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3623 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3625 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3627 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3629 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3631 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3633 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3635 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3637 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3639 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3641 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3643 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3645 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3647 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3649 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3651 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3653 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3655 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3657 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3659 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3661 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3663 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3665 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3667 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3669 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3671 0xf810f000, 0xff70f000, "pld%c\t%a"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3673 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3675 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3677 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3679 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3681 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3683 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3685 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3687 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3689 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3691 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3693 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3695 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3697 0xfb100000, 0xfff000c0,
3698 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3700 0xfbc00080, 0xfff000c0,
3701 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3703 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3705 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3707 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3709 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3711 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3712 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3713 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3715 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3716 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3717 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3719 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3721 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3723 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3725 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3727 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3729 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3731 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3733 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3735 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3737 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3739 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3741 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3743 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3745 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3747 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3749 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3751 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3753 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3755 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3757 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3759 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3761 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3763 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3765 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3767 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3769 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3771 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3773 0xe9400000, 0xff500000,
3774 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3776 0xe9500000, 0xff500000,
3777 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3779 0xe8600000, 0xff700000,
3780 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3782 0xe8700000, 0xff700000,
3783 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3785 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3787 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3788
3789 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3791 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3793 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3795 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3797 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3798
3799 /* These have been 32-bit since the invention of Thumb. */
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3801 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3803 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3804
3805 /* Fallback. */
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3807 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3808 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3809 };
3810
3811 static const char *const arm_conditional[] =
3812 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3813 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3814
3815 static const char *const arm_fp_const[] =
3816 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3817
3818 static const char *const arm_shift[] =
3819 {"lsl", "lsr", "asr", "ror"};
3820
3821 typedef struct
3822 {
3823 const char *name;
3824 const char *description;
3825 const char *reg_names[16];
3826 }
3827 arm_regname;
3828
3829 static const arm_regname regnames[] =
3830 {
3831 { "reg-names-raw", N_("Select raw register names"),
3832 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3833 { "reg-names-gcc", N_("Select register names used by GCC"),
3834 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3835 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3836 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3837 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3838 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3839 { "reg-names-apcs", N_("Select register names used in the APCS"),
3840 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3841 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3842 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3843 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3844 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
3845 };
3846
3847 static const char *const iwmmxt_wwnames[] =
3848 {"b", "h", "w", "d"};
3849
3850 static const char *const iwmmxt_wwssnames[] =
3851 {"b", "bus", "bc", "bss",
3852 "h", "hus", "hc", "hss",
3853 "w", "wus", "wc", "wss",
3854 "d", "dus", "dc", "dss"
3855 };
3856
3857 static const char *const iwmmxt_regnames[] =
3858 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3859 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3860 };
3861
3862 static const char *const iwmmxt_cregnames[] =
3863 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3864 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3865 };
3866
3867 static const char *const vec_condnames[] =
3868 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
3869 };
3870
3871 static const char *const mve_predicatenames[] =
3872 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
3873 "eee", "ee", "eet", "e", "ett", "et", "ete"
3874 };
3875
3876 /* Names for 2-bit size field for mve vector isntructions. */
3877 static const char *const mve_vec_sizename[] =
3878 { "8", "16", "32", "64"};
3879
3880 /* Indicates whether we are processing a then predicate,
3881 else predicate or none at all. */
3882 enum vpt_pred_state
3883 {
3884 PRED_NONE,
3885 PRED_THEN,
3886 PRED_ELSE
3887 };
3888
3889 /* Information used to process a vpt block and subsequent instructions. */
3890 struct vpt_block
3891 {
3892 /* Are we in a vpt block. */
3893 bfd_boolean in_vpt_block;
3894
3895 /* Next predicate state if in vpt block. */
3896 enum vpt_pred_state next_pred_state;
3897
3898 /* Mask from vpt/vpst instruction. */
3899 long predicate_mask;
3900
3901 /* Instruction number in vpt block. */
3902 long current_insn_num;
3903
3904 /* Number of instructions in vpt block.. */
3905 long num_pred_insn;
3906 };
3907
3908 static struct vpt_block vpt_block_state =
3909 {
3910 FALSE,
3911 PRED_NONE,
3912 0,
3913 0,
3914 0
3915 };
3916
3917 /* Default to GCC register name set. */
3918 static unsigned int regname_selected = 1;
3919
3920 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
3921 #define arm_regnames regnames[regname_selected].reg_names
3922
3923 static bfd_boolean force_thumb = FALSE;
3924
3925 /* Current IT instruction state. This contains the same state as the IT
3926 bits in the CPSR. */
3927 static unsigned int ifthen_state;
3928 /* IT state for the next instruction. */
3929 static unsigned int ifthen_next_state;
3930 /* The address of the insn for which the IT state is valid. */
3931 static bfd_vma ifthen_address;
3932 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3933 /* Indicates that the current Conditional state is unconditional or outside
3934 an IT block. */
3935 #define COND_UNCOND 16
3936
3937 \f
3938 /* Functions. */
3939 /* Extract the predicate mask for a VPT or VPST instruction.
3940 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
3941
3942 static long
3943 mve_extract_pred_mask (long given)
3944 {
3945 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
3946 }
3947
3948 /* Return the number of instructions in a MVE predicate block. */
3949 static long
3950 num_instructions_vpt_block (long given)
3951 {
3952 long mask = mve_extract_pred_mask (given);
3953 if (mask == 0)
3954 return 0;
3955
3956 if (mask == 8)
3957 return 1;
3958
3959 if ((mask & 7) == 4)
3960 return 2;
3961
3962 if ((mask & 3) == 2)
3963 return 3;
3964
3965 if ((mask & 1) == 1)
3966 return 4;
3967
3968 return 0;
3969 }
3970
3971 static void
3972 mark_outside_vpt_block (void)
3973 {
3974 vpt_block_state.in_vpt_block = FALSE;
3975 vpt_block_state.next_pred_state = PRED_NONE;
3976 vpt_block_state.predicate_mask = 0;
3977 vpt_block_state.current_insn_num = 0;
3978 vpt_block_state.num_pred_insn = 0;
3979 }
3980
3981 static void
3982 mark_inside_vpt_block (long given)
3983 {
3984 vpt_block_state.in_vpt_block = TRUE;
3985 vpt_block_state.next_pred_state = PRED_THEN;
3986 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
3987 vpt_block_state.current_insn_num = 0;
3988 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
3989 assert (vpt_block_state.num_pred_insn >= 1);
3990 }
3991
3992 static enum vpt_pred_state
3993 invert_next_predicate_state (enum vpt_pred_state astate)
3994 {
3995 if (astate == PRED_THEN)
3996 return PRED_ELSE;
3997 else if (astate == PRED_ELSE)
3998 return PRED_THEN;
3999 else
4000 return PRED_NONE;
4001 }
4002
4003 static enum vpt_pred_state
4004 update_next_predicate_state (void)
4005 {
4006 long pred_mask = vpt_block_state.predicate_mask;
4007 long mask_for_insn = 0;
4008
4009 switch (vpt_block_state.current_insn_num)
4010 {
4011 case 1:
4012 mask_for_insn = 8;
4013 break;
4014
4015 case 2:
4016 mask_for_insn = 4;
4017 break;
4018
4019 case 3:
4020 mask_for_insn = 2;
4021 break;
4022
4023 case 4:
4024 return PRED_NONE;
4025 }
4026
4027 if (pred_mask & mask_for_insn)
4028 return invert_next_predicate_state (vpt_block_state.next_pred_state);
4029 else
4030 return vpt_block_state.next_pred_state;
4031 }
4032
4033 static void
4034 update_vpt_block_state (void)
4035 {
4036 vpt_block_state.current_insn_num++;
4037 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
4038 {
4039 /* No more instructions to process in vpt block. */
4040 mark_outside_vpt_block ();
4041 return;
4042 }
4043
4044 vpt_block_state.next_pred_state = update_next_predicate_state ();
4045 }
4046
4047 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4048 Returns pointer to following character of the format string and
4049 fills in *VALUEP and *WIDTHP with the extracted value and number of
4050 bits extracted. WIDTHP can be NULL. */
4051
4052 static const char *
4053 arm_decode_bitfield (const char *ptr,
4054 unsigned long insn,
4055 unsigned long *valuep,
4056 int *widthp)
4057 {
4058 unsigned long value = 0;
4059 int width = 0;
4060
4061 do
4062 {
4063 int start, end;
4064 int bits;
4065
4066 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
4067 start = start * 10 + *ptr - '0';
4068 if (*ptr == '-')
4069 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
4070 end = end * 10 + *ptr - '0';
4071 else
4072 end = start;
4073 bits = end - start;
4074 if (bits < 0)
4075 abort ();
4076 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
4077 width += bits + 1;
4078 }
4079 while (*ptr++ == ',');
4080 *valuep = value;
4081 if (widthp)
4082 *widthp = width;
4083 return ptr - 1;
4084 }
4085
4086 static void
4087 arm_decode_shift (long given, fprintf_ftype func, void *stream,
4088 bfd_boolean print_shift)
4089 {
4090 func (stream, "%s", arm_regnames[given & 0xf]);
4091
4092 if ((given & 0xff0) != 0)
4093 {
4094 if ((given & 0x10) == 0)
4095 {
4096 int amount = (given & 0xf80) >> 7;
4097 int shift = (given & 0x60) >> 5;
4098
4099 if (amount == 0)
4100 {
4101 if (shift == 3)
4102 {
4103 func (stream, ", rrx");
4104 return;
4105 }
4106
4107 amount = 32;
4108 }
4109
4110 if (print_shift)
4111 func (stream, ", %s #%d", arm_shift[shift], amount);
4112 else
4113 func (stream, ", #%d", amount);
4114 }
4115 else if ((given & 0x80) == 0x80)
4116 func (stream, "\t; <illegal shifter operand>");
4117 else if (print_shift)
4118 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
4119 arm_regnames[(given & 0xf00) >> 8]);
4120 else
4121 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
4122 }
4123 }
4124
4125 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4126
4127 static bfd_boolean
4128 is_mve_okay_in_it (enum mve_instructions matched_insn)
4129 {
4130 return FALSE;
4131 }
4132
4133 static bfd_boolean
4134 is_mve_architecture (struct disassemble_info *info)
4135 {
4136 struct arm_private_data *private_data = info->private_data;
4137 arm_feature_set allowed_arches = private_data->features;
4138
4139 arm_feature_set arm_ext_v8_1m_main
4140 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
4141
4142 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4143 && !ARM_CPU_IS_ANY (allowed_arches))
4144 return TRUE;
4145 else
4146 return FALSE;
4147 }
4148
4149 static bfd_boolean
4150 is_vpt_instruction (long given)
4151 {
4152
4153 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4154 if ((given & 0x0040e000) == 0)
4155 return FALSE;
4156
4157 /* VPT floating point T1 variant. */
4158 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
4159 /* VPT floating point T2 variant. */
4160 || ((given & 0xefb10f50) == 0xee310f40)
4161 /* VPT vector T1 variant. */
4162 || ((given & 0xff811f51) == 0xfe010f00)
4163 /* VPT vector T2 variant. */
4164 || ((given & 0xff811f51) == 0xfe010f01
4165 && ((given & 0x300000) != 0x300000))
4166 /* VPT vector T3 variant. */
4167 || ((given & 0xff811f50) == 0xfe011f00)
4168 /* VPT vector T4 variant. */
4169 || ((given & 0xff811f70) == 0xfe010f40)
4170 /* VPT vector T5 variant. */
4171 || ((given & 0xff811f70) == 0xfe010f60)
4172 /* VPT vector T6 variant. */
4173 || ((given & 0xff811f50) == 0xfe011f40)
4174 /* VPST vector T variant. */
4175 || ((given & 0xffbf1fff) == 0xfe310f4d))
4176 return TRUE;
4177 else
4178 return FALSE;
4179 }
4180
4181 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4182 and ending bitfield = END. END must be greater than START. */
4183
4184 static unsigned long
4185 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
4186 {
4187 int bits = end - start;
4188
4189 if (bits < 0)
4190 abort ();
4191
4192 return ((given >> start) & ((2ul << bits) - 1));
4193 }
4194
4195 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4196 START:END and START2:END2. END/END2 must be greater than
4197 START/START2. */
4198
4199 static unsigned long
4200 arm_decode_field_multiple (unsigned long given, unsigned int start,
4201 unsigned int end, unsigned int start2,
4202 unsigned int end2)
4203 {
4204 int bits = end - start;
4205 int bits2 = end2 - start2;
4206 unsigned long value = 0;
4207 int width = 0;
4208
4209 if (bits2 < 0)
4210 abort ();
4211
4212 value = arm_decode_field (given, start, end);
4213 width += bits + 1;
4214
4215 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
4216 return value;
4217 }
4218
4219 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4220 This helps us decode instructions that change mnemonic depending on specific
4221 operand values/encodings. */
4222
4223 static bfd_boolean
4224 is_mve_encoding_conflict (unsigned long given,
4225 enum mve_instructions matched_insn)
4226 {
4227 switch (matched_insn)
4228 {
4229 case MVE_VPST:
4230 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4231 return TRUE;
4232 else
4233 return FALSE;
4234
4235 case MVE_VPT_FP_T1:
4236 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4237 return TRUE;
4238 if ((arm_decode_field (given, 12, 12) == 0)
4239 && (arm_decode_field (given, 0, 0) == 1))
4240 return TRUE;
4241 return FALSE;
4242
4243 case MVE_VPT_FP_T2:
4244 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4245 return TRUE;
4246 if (arm_decode_field (given, 0, 3) == 0xd)
4247 return TRUE;
4248 return FALSE;
4249
4250 case MVE_VPT_VEC_T1:
4251 case MVE_VPT_VEC_T2:
4252 case MVE_VPT_VEC_T3:
4253 case MVE_VPT_VEC_T4:
4254 case MVE_VPT_VEC_T5:
4255 case MVE_VPT_VEC_T6:
4256 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4257 return TRUE;
4258 if (arm_decode_field (given, 20, 21) == 3)
4259 return TRUE;
4260 return FALSE;
4261
4262 case MVE_VCMP_FP_T1:
4263 if ((arm_decode_field (given, 12, 12) == 0)
4264 && (arm_decode_field (given, 0, 0) == 1))
4265 return TRUE;
4266 else
4267 return FALSE;
4268
4269 case MVE_VCMP_FP_T2:
4270 if (arm_decode_field (given, 0, 3) == 0xd)
4271 return TRUE;
4272 else
4273 return FALSE;
4274
4275 case MVE_VHADD_T2:
4276 case MVE_VHSUB_T2:
4277 case MVE_VCMP_VEC_T1:
4278 case MVE_VCMP_VEC_T2:
4279 case MVE_VCMP_VEC_T3:
4280 case MVE_VCMP_VEC_T4:
4281 case MVE_VCMP_VEC_T5:
4282 case MVE_VCMP_VEC_T6:
4283 if (arm_decode_field (given, 20, 21) == 3)
4284 return TRUE;
4285 else
4286 return FALSE;
4287
4288 case MVE_VLD2:
4289 case MVE_VLD4:
4290 case MVE_VST2:
4291 case MVE_VST4:
4292 if (arm_decode_field (given, 7, 8) == 3)
4293 return TRUE;
4294 else
4295 return FALSE;
4296
4297 case MVE_VSTRB_T1:
4298 case MVE_VSTRH_T2:
4299 if ((arm_decode_field (given, 24, 24) == 0)
4300 && (arm_decode_field (given, 21, 21) == 0))
4301 {
4302 return TRUE;
4303 }
4304 else if ((arm_decode_field (given, 7, 8) == 3))
4305 return TRUE;
4306 else
4307 return FALSE;
4308
4309 case MVE_VSTRB_T5:
4310 case MVE_VSTRH_T6:
4311 case MVE_VSTRW_T7:
4312 if ((arm_decode_field (given, 24, 24) == 0)
4313 && (arm_decode_field (given, 21, 21) == 0))
4314 {
4315 return TRUE;
4316 }
4317 else
4318 return FALSE;
4319
4320 case MVE_VCVT_FP_FIX_VEC:
4321 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
4322
4323 default:
4324 return FALSE;
4325
4326 }
4327 }
4328
4329 static void
4330 print_mve_vld_str_addr (struct disassemble_info *info,
4331 unsigned long given,
4332 enum mve_instructions matched_insn)
4333 {
4334 void *stream = info->stream;
4335 fprintf_ftype func = info->fprintf_func;
4336
4337 unsigned long p, w, gpr, imm, add, mod_imm;
4338
4339 imm = arm_decode_field (given, 0, 6);
4340 mod_imm = imm;
4341
4342 switch (matched_insn)
4343 {
4344 case MVE_VLDRB_T1:
4345 case MVE_VSTRB_T1:
4346 gpr = arm_decode_field (given, 16, 18);
4347 break;
4348
4349 case MVE_VLDRH_T2:
4350 case MVE_VSTRH_T2:
4351 gpr = arm_decode_field (given, 16, 18);
4352 mod_imm = imm << 1;
4353 break;
4354
4355 case MVE_VLDRH_T6:
4356 case MVE_VSTRH_T6:
4357 gpr = arm_decode_field (given, 16, 19);
4358 mod_imm = imm << 1;
4359 break;
4360
4361 case MVE_VLDRW_T7:
4362 case MVE_VSTRW_T7:
4363 gpr = arm_decode_field (given, 16, 19);
4364 mod_imm = imm << 2;
4365 break;
4366
4367 case MVE_VLDRB_T5:
4368 case MVE_VSTRB_T5:
4369 gpr = arm_decode_field (given, 16, 19);
4370 break;
4371
4372 default:
4373 return;
4374 }
4375
4376 p = arm_decode_field (given, 24, 24);
4377 w = arm_decode_field (given, 21, 21);
4378
4379 add = arm_decode_field (given, 23, 23);
4380
4381 char * add_sub;
4382
4383 /* Don't print anything for '+' as it is implied. */
4384 if (add == 1)
4385 add_sub = "";
4386 else
4387 add_sub = "-";
4388
4389 if (p == 1)
4390 {
4391 /* Offset mode. */
4392 if (w == 0)
4393 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
4394 /* Pre-indexed mode. */
4395 else
4396 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
4397 }
4398 else if ((p == 0) && (w == 1))
4399 /* Post-index mode. */
4400 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
4401 }
4402
4403 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
4404 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
4405 this encoding is undefined. */
4406
4407 static bfd_boolean
4408 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
4409 enum mve_undefined *undefined_code)
4410 {
4411 *undefined_code = UNDEF_NONE;
4412
4413 switch (matched_insn)
4414 {
4415 case MVE_VDUP:
4416 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
4417 {
4418 *undefined_code = UNDEF_SIZE_3;
4419 return TRUE;
4420 }
4421 else
4422 return FALSE;
4423
4424 case MVE_VRHADD:
4425 case MVE_VHADD_T1:
4426 case MVE_VHSUB_T1:
4427 if (arm_decode_field (given, 20, 21) == 3)
4428 {
4429 *undefined_code = UNDEF_SIZE_3;
4430 return TRUE;
4431 }
4432 else
4433 return FALSE;
4434
4435 case MVE_VLDRB_T1:
4436 if (arm_decode_field (given, 7, 8) == 3)
4437 {
4438 *undefined_code = UNDEF_SIZE_3;
4439 return TRUE;
4440 }
4441 else
4442 return FALSE;
4443
4444 case MVE_VLDRH_T2:
4445 if (arm_decode_field (given, 7, 8) <= 1)
4446 {
4447 *undefined_code = UNDEF_SIZE_LE_1;
4448 return TRUE;
4449 }
4450 else
4451 return FALSE;
4452
4453 case MVE_VSTRB_T1:
4454 if ((arm_decode_field (given, 7, 8) == 0))
4455 {
4456 *undefined_code = UNDEF_SIZE_0;
4457 return TRUE;
4458 }
4459 else
4460 return FALSE;
4461
4462 case MVE_VSTRH_T2:
4463 if ((arm_decode_field (given, 7, 8) <= 1))
4464 {
4465 *undefined_code = UNDEF_SIZE_LE_1;
4466 return TRUE;
4467 }
4468 else
4469 return FALSE;
4470
4471 case MVE_VLDRB_GATHER_T1:
4472 if (arm_decode_field (given, 7, 8) == 3)
4473 {
4474 *undefined_code = UNDEF_SIZE_3;
4475 return TRUE;
4476 }
4477 else if ((arm_decode_field (given, 28, 28) == 0)
4478 && (arm_decode_field (given, 7, 8) == 0))
4479 {
4480 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
4481 return TRUE;
4482 }
4483 else
4484 return FALSE;
4485
4486 case MVE_VLDRH_GATHER_T2:
4487 if (arm_decode_field (given, 7, 8) == 3)
4488 {
4489 *undefined_code = UNDEF_SIZE_3;
4490 return TRUE;
4491 }
4492 else if ((arm_decode_field (given, 28, 28) == 0)
4493 && (arm_decode_field (given, 7, 8) == 1))
4494 {
4495 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
4496 return TRUE;
4497 }
4498 else if (arm_decode_field (given, 7, 8) == 0)
4499 {
4500 *undefined_code = UNDEF_SIZE_0;
4501 return TRUE;
4502 }
4503 else
4504 return FALSE;
4505
4506 case MVE_VLDRW_GATHER_T3:
4507 if (arm_decode_field (given, 7, 8) != 2)
4508 {
4509 *undefined_code = UNDEF_SIZE_NOT_2;
4510 return TRUE;
4511 }
4512 else if (arm_decode_field (given, 28, 28) == 0)
4513 {
4514 *undefined_code = UNDEF_NOT_UNSIGNED;
4515 return TRUE;
4516 }
4517 else
4518 return FALSE;
4519
4520 case MVE_VLDRD_GATHER_T4:
4521 if (arm_decode_field (given, 7, 8) != 3)
4522 {
4523 *undefined_code = UNDEF_SIZE_NOT_3;
4524 return TRUE;
4525 }
4526 else if (arm_decode_field (given, 28, 28) == 0)
4527 {
4528 *undefined_code = UNDEF_NOT_UNSIGNED;
4529 return TRUE;
4530 }
4531 else
4532 return FALSE;
4533
4534 case MVE_VSTRB_SCATTER_T1:
4535 if (arm_decode_field (given, 7, 8) == 3)
4536 {
4537 *undefined_code = UNDEF_SIZE_3;
4538 return TRUE;
4539 }
4540 else
4541 return FALSE;
4542
4543 case MVE_VSTRH_SCATTER_T2:
4544 {
4545 unsigned long size = arm_decode_field (given, 7, 8);
4546 if (size == 3)
4547 {
4548 *undefined_code = UNDEF_SIZE_3;
4549 return TRUE;
4550 }
4551 else if (size == 0)
4552 {
4553 *undefined_code = UNDEF_SIZE_0;
4554 return TRUE;
4555 }
4556 else
4557 return FALSE;
4558 }
4559
4560 case MVE_VSTRW_SCATTER_T3:
4561 if (arm_decode_field (given, 7, 8) != 2)
4562 {
4563 *undefined_code = UNDEF_SIZE_NOT_2;
4564 return TRUE;
4565 }
4566 else
4567 return FALSE;
4568
4569 case MVE_VSTRD_SCATTER_T4:
4570 if (arm_decode_field (given, 7, 8) != 3)
4571 {
4572 *undefined_code = UNDEF_SIZE_NOT_3;
4573 return TRUE;
4574 }
4575 else
4576 return FALSE;
4577
4578 case MVE_VCVT_FP_FIX_VEC:
4579 {
4580 unsigned long imm6 = arm_decode_field (given, 16, 21);
4581 if ((imm6 & 0x20) == 0)
4582 {
4583 *undefined_code = UNDEF_VCVT_IMM6;
4584 return TRUE;
4585 }
4586
4587 if ((arm_decode_field (given, 9, 9) == 0)
4588 && ((imm6 & 0x30) == 0x20))
4589 {
4590 *undefined_code = UNDEF_VCVT_FSI_IMM6;
4591 return TRUE;
4592 }
4593
4594 return FALSE;
4595 }
4596
4597 case MVE_VCVT_BETWEEN_FP_INT:
4598 case MVE_VCVT_FROM_FP_TO_INT:
4599 {
4600 unsigned long size = arm_decode_field (given, 18, 19);
4601 if (size == 0)
4602 {
4603 *undefined_code = UNDEF_SIZE_0;
4604 return TRUE;
4605 }
4606 else if (size == 3)
4607 {
4608 *undefined_code = UNDEF_SIZE_3;
4609 return TRUE;
4610 }
4611 else
4612 return FALSE;
4613 }
4614
4615 default:
4616 return FALSE;
4617 }
4618 }
4619
4620 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
4621 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
4622 why this encoding is unpredictable. */
4623
4624 static bfd_boolean
4625 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
4626 enum mve_unpredictable *unpredictable_code)
4627 {
4628 *unpredictable_code = UNPRED_NONE;
4629
4630 switch (matched_insn)
4631 {
4632 case MVE_VCMP_FP_T2:
4633 case MVE_VPT_FP_T2:
4634 if ((arm_decode_field (given, 12, 12) == 0)
4635 && (arm_decode_field (given, 5, 5) == 1))
4636 {
4637 *unpredictable_code = UNPRED_FCA_0_FCB_1;
4638 return TRUE;
4639 }
4640 else
4641 return FALSE;
4642
4643 case MVE_VPT_VEC_T4:
4644 case MVE_VPT_VEC_T5:
4645 case MVE_VPT_VEC_T6:
4646 case MVE_VCMP_VEC_T4:
4647 case MVE_VCMP_VEC_T5:
4648 case MVE_VCMP_VEC_T6:
4649 if (arm_decode_field (given, 0, 3) == 0xd)
4650 {
4651 *unpredictable_code = UNPRED_R13;
4652 return TRUE;
4653 }
4654 else
4655 return FALSE;
4656
4657 case MVE_VDUP:
4658 {
4659 unsigned long gpr = arm_decode_field (given, 12, 15);
4660 if (gpr == 0xd)
4661 {
4662 *unpredictable_code = UNPRED_R13;
4663 return TRUE;
4664 }
4665 else if (gpr == 0xf)
4666 {
4667 *unpredictable_code = UNPRED_R15;
4668 return TRUE;
4669 }
4670
4671 return FALSE;
4672 }
4673
4674 case MVE_VFMA_FP_SCALAR:
4675 case MVE_VFMAS_FP_SCALAR:
4676 case MVE_VHADD_T2:
4677 case MVE_VHSUB_T2:
4678 {
4679 unsigned long gpr = arm_decode_field (given, 0, 3);
4680 if (gpr == 0xd)
4681 {
4682 *unpredictable_code = UNPRED_R13;
4683 return TRUE;
4684 }
4685 else if (gpr == 0xf)
4686 {
4687 *unpredictable_code = UNPRED_R15;
4688 return TRUE;
4689 }
4690
4691 return FALSE;
4692 }
4693
4694 case MVE_VLD2:
4695 case MVE_VST2:
4696 {
4697 unsigned long rn = arm_decode_field (given, 16, 19);
4698
4699 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
4700 {
4701 *unpredictable_code = UNPRED_R13_AND_WB;
4702 return TRUE;
4703 }
4704
4705 if (rn == 0xf)
4706 {
4707 *unpredictable_code = UNPRED_R15;
4708 return TRUE;
4709 }
4710
4711 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
4712 {
4713 *unpredictable_code = UNPRED_Q_GT_6;
4714 return TRUE;
4715 }
4716 else
4717 return FALSE;
4718 }
4719
4720 case MVE_VLD4:
4721 case MVE_VST4:
4722 {
4723 unsigned long rn = arm_decode_field (given, 16, 19);
4724
4725 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
4726 {
4727 *unpredictable_code = UNPRED_R13_AND_WB;
4728 return TRUE;
4729 }
4730
4731 if (rn == 0xf)
4732 {
4733 *unpredictable_code = UNPRED_R15;
4734 return TRUE;
4735 }
4736
4737 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
4738 {
4739 *unpredictable_code = UNPRED_Q_GT_4;
4740 return TRUE;
4741 }
4742 else
4743 return FALSE;
4744 }
4745
4746 case MVE_VLDRB_T5:
4747 case MVE_VLDRH_T6:
4748 case MVE_VLDRW_T7:
4749 case MVE_VSTRB_T5:
4750 case MVE_VSTRH_T6:
4751 case MVE_VSTRW_T7:
4752 {
4753 unsigned long rn = arm_decode_field (given, 16, 19);
4754
4755 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
4756 {
4757 *unpredictable_code = UNPRED_R13_AND_WB;
4758 return TRUE;
4759 }
4760 else if (rn == 0xf)
4761 {
4762 *unpredictable_code = UNPRED_R15;
4763 return TRUE;
4764 }
4765 else
4766 return FALSE;
4767 }
4768
4769 case MVE_VLDRB_GATHER_T1:
4770 if (arm_decode_field (given, 0, 0) == 1)
4771 {
4772 *unpredictable_code = UNPRED_OS;
4773 return TRUE;
4774 }
4775
4776 /* fall through. */
4777 /* To handle common code with T2-T4 variants. */
4778 case MVE_VLDRH_GATHER_T2:
4779 case MVE_VLDRW_GATHER_T3:
4780 case MVE_VLDRD_GATHER_T4:
4781 {
4782 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
4783 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
4784
4785 if (qd == qm)
4786 {
4787 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
4788 return TRUE;
4789 }
4790
4791 if (arm_decode_field (given, 16, 19) == 0xf)
4792 {
4793 *unpredictable_code = UNPRED_R15;
4794 return TRUE;
4795 }
4796
4797 return FALSE;
4798 }
4799
4800 case MVE_VLDRW_GATHER_T5:
4801 case MVE_VLDRD_GATHER_T6:
4802 {
4803 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
4804 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
4805
4806 if (qd == qm)
4807 {
4808 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
4809 return TRUE;
4810 }
4811 else
4812 return FALSE;
4813 }
4814
4815 case MVE_VSTRB_SCATTER_T1:
4816 if (arm_decode_field (given, 16, 19) == 0xf)
4817 {
4818 *unpredictable_code = UNPRED_R15;
4819 return TRUE;
4820 }
4821 else if (arm_decode_field (given, 0, 0) == 1)
4822 {
4823 *unpredictable_code = UNPRED_OS;
4824 return TRUE;
4825 }
4826 else
4827 return FALSE;
4828
4829 case MVE_VSTRH_SCATTER_T2:
4830 case MVE_VSTRW_SCATTER_T3:
4831 case MVE_VSTRD_SCATTER_T4:
4832 if (arm_decode_field (given, 16, 19) == 0xf)
4833 {
4834 *unpredictable_code = UNPRED_R15;
4835 return TRUE;
4836 }
4837 else
4838 return FALSE;
4839
4840 case MVE_VCVT_BETWEEN_FP_INT:
4841 case MVE_VCVT_FROM_FP_TO_INT:
4842 {
4843 unsigned long rt = arm_decode_field (given, 0, 3);
4844 unsigned long rt2 = arm_decode_field (given, 16, 19);
4845
4846 if ((rt == 0xd) || (rt2 == 0xd))
4847 {
4848 *unpredictable_code = UNPRED_R13;
4849 return TRUE;
4850 }
4851 else if ((rt == 0xf) || (rt2 == 0xf))
4852 {
4853 *unpredictable_code = UNPRED_R15;
4854 return TRUE;
4855 }
4856 else if (rt == rt2)
4857 {
4858 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
4859 return TRUE;
4860 }
4861
4862 return FALSE;
4863 }
4864
4865 default:
4866 return FALSE;
4867 }
4868 }
4869
4870 static void
4871 print_mve_undefined (struct disassemble_info *info,
4872 enum mve_undefined undefined_code)
4873 {
4874 void *stream = info->stream;
4875 fprintf_ftype func = info->fprintf_func;
4876
4877 func (stream, "\t\tundefined instruction: ");
4878
4879 switch (undefined_code)
4880 {
4881 case UNDEF_SIZE_0:
4882 func (stream, "size equals zero");
4883 break;
4884
4885 case UNDEF_SIZE_3:
4886 func (stream, "size equals three");
4887 break;
4888
4889 case UNDEF_SIZE_LE_1:
4890 func (stream, "size <= 1");
4891 break;
4892
4893 case UNDEF_SIZE_NOT_2:
4894 func (stream, "size not equal to 2");
4895 break;
4896
4897 case UNDEF_SIZE_NOT_3:
4898 func (stream, "size not equal to 3");
4899 break;
4900
4901 case UNDEF_NOT_UNS_SIZE_0:
4902 func (stream, "not unsigned and size = zero");
4903 break;
4904
4905 case UNDEF_NOT_UNS_SIZE_1:
4906 func (stream, "not unsigned and size = one");
4907 break;
4908
4909 case UNDEF_NOT_UNSIGNED:
4910 func (stream, "not unsigned");
4911 break;
4912
4913 case UNDEF_VCVT_IMM6:
4914 func (stream, "invalid imm6");
4915 break;
4916
4917 case UNDEF_VCVT_FSI_IMM6:
4918 func (stream, "fsi = 0 and invalid imm6");
4919 break;
4920
4921 case UNDEF_NONE:
4922 break;
4923 }
4924
4925 }
4926
4927 static void
4928 print_mve_unpredictable (struct disassemble_info *info,
4929 enum mve_unpredictable unpredict_code)
4930 {
4931 void *stream = info->stream;
4932 fprintf_ftype func = info->fprintf_func;
4933
4934 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
4935
4936 switch (unpredict_code)
4937 {
4938 case UNPRED_IT_BLOCK:
4939 func (stream, "mve instruction in it block");
4940 break;
4941
4942 case UNPRED_FCA_0_FCB_1:
4943 func (stream, "condition bits, fca = 0 and fcb = 1");
4944 break;
4945
4946 case UNPRED_R13:
4947 func (stream, "use of r13 (sp)");
4948 break;
4949
4950 case UNPRED_R15:
4951 func (stream, "use of r15 (pc)");
4952 break;
4953
4954 case UNPRED_Q_GT_4:
4955 func (stream, "start register block > r4");
4956 break;
4957
4958 case UNPRED_Q_GT_6:
4959 func (stream, "start register block > r6");
4960 break;
4961
4962 case UNPRED_R13_AND_WB:
4963 func (stream, "use of r13 and write back");
4964 break;
4965
4966 case UNPRED_Q_REGS_EQUAL:
4967 func (stream,
4968 "same vector register used for destination and other operand");
4969 break;
4970
4971 case UNPRED_OS:
4972 func (stream, "use of offset scaled");
4973 break;
4974
4975 case UNPRED_GP_REGS_EQUAL:
4976 func (stream, "same general-purpose register used for both operands");
4977 break;
4978
4979 case UNPRED_NONE:
4980 break;
4981 }
4982 }
4983
4984 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
4985
4986 static void
4987 print_mve_register_blocks (struct disassemble_info *info,
4988 unsigned long given,
4989 enum mve_instructions matched_insn)
4990 {
4991 void *stream = info->stream;
4992 fprintf_ftype func = info->fprintf_func;
4993
4994 unsigned long q_reg_start = arm_decode_field_multiple (given,
4995 13, 15,
4996 22, 22);
4997 switch (matched_insn)
4998 {
4999 case MVE_VLD2:
5000 case MVE_VST2:
5001 if (q_reg_start <= 6)
5002 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
5003 else
5004 func (stream, "<illegal reg q%ld>", q_reg_start);
5005 break;
5006
5007 case MVE_VLD4:
5008 case MVE_VST4:
5009 if (q_reg_start <= 4)
5010 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
5011 q_reg_start + 1, q_reg_start + 2,
5012 q_reg_start + 3);
5013 else
5014 func (stream, "<illegal reg q%ld>", q_reg_start);
5015 break;
5016
5017 default:
5018 break;
5019 }
5020 }
5021
5022 static void
5023 print_mve_rounding_mode (struct disassemble_info *info,
5024 unsigned long given,
5025 enum mve_instructions matched_insn)
5026 {
5027 void *stream = info->stream;
5028 fprintf_ftype func = info->fprintf_func;
5029
5030 switch (matched_insn)
5031 {
5032 case MVE_VCVT_FROM_FP_TO_INT:
5033 {
5034 switch (arm_decode_field (given, 8, 9))
5035 {
5036 case 0:
5037 func (stream, "a");
5038 break;
5039
5040 case 1:
5041 func (stream, "n");
5042 break;
5043
5044 case 2:
5045 func (stream, "p");
5046 break;
5047
5048 case 3:
5049 func (stream, "m");
5050 break;
5051
5052 default:
5053 break;
5054 }
5055 }
5056 break;
5057
5058 case MVE_VRINT_FP:
5059 {
5060 switch (arm_decode_field (given, 7, 9))
5061 {
5062 case 0:
5063 func (stream, "n");
5064 break;
5065
5066 case 1:
5067 func (stream, "x");
5068 break;
5069
5070 case 2:
5071 func (stream, "a");
5072 break;
5073
5074 case 3:
5075 func (stream, "z");
5076 break;
5077
5078 case 5:
5079 func (stream, "m");
5080 break;
5081
5082 case 7:
5083 func (stream, "p");
5084
5085 case 4:
5086 case 6:
5087 default:
5088 break;
5089 }
5090 }
5091 break;
5092
5093 default:
5094 break;
5095 }
5096 }
5097
5098 static void
5099 print_mve_vcvt_size (struct disassemble_info *info,
5100 unsigned long given,
5101 enum mve_instructions matched_insn)
5102 {
5103 unsigned long mode = 0;
5104 void *stream = info->stream;
5105 fprintf_ftype func = info->fprintf_func;
5106
5107 switch (matched_insn)
5108 {
5109 case MVE_VCVT_FP_FIX_VEC:
5110 {
5111 mode = (((given & 0x200) >> 7)
5112 | ((given & 0x10000000) >> 27)
5113 | ((given & 0x100) >> 8));
5114
5115 switch (mode)
5116 {
5117 case 0:
5118 func (stream, "f16.s16");
5119 break;
5120
5121 case 1:
5122 func (stream, "s16.f16");
5123 break;
5124
5125 case 2:
5126 func (stream, "f16.u16");
5127 break;
5128
5129 case 3:
5130 func (stream, "u16.f16");
5131 break;
5132
5133 case 4:
5134 func (stream, "f32.s32");
5135 break;
5136
5137 case 5:
5138 func (stream, "s32.f32");
5139 break;
5140
5141 case 6:
5142 func (stream, "f32.u32");
5143 break;
5144
5145 case 7:
5146 func (stream, "u32.f32");
5147 break;
5148
5149 default:
5150 break;
5151 }
5152 break;
5153 }
5154 case MVE_VCVT_BETWEEN_FP_INT:
5155 {
5156 unsigned long size = arm_decode_field (given, 18, 19);
5157 unsigned long op = arm_decode_field (given, 7, 8);
5158
5159 if (size == 1)
5160 {
5161 switch (op)
5162 {
5163 case 0:
5164 func (stream, "f16.s16");
5165 break;
5166
5167 case 1:
5168 func (stream, "f16.u16");
5169 break;
5170
5171 case 2:
5172 func (stream, "s16.f16");
5173 break;
5174
5175 case 3:
5176 func (stream, "u16.f16");
5177 break;
5178
5179 default:
5180 break;
5181 }
5182 }
5183 else if (size == 2)
5184 {
5185 switch (op)
5186 {
5187 case 0:
5188 func (stream, "f32.s32");
5189 break;
5190
5191 case 1:
5192 func (stream, "f32.u32");
5193 break;
5194
5195 case 2:
5196 func (stream, "s32.f32");
5197 break;
5198
5199 case 3:
5200 func (stream, "u32.f32");
5201 break;
5202 }
5203 }
5204 }
5205 break;
5206
5207 case MVE_VCVT_FP_HALF_FP:
5208 {
5209 unsigned long op = arm_decode_field (given, 28, 28);
5210 if (op == 0)
5211 func (stream, "f16.f32");
5212 else if (op == 1)
5213 func (stream, "f32.f16");
5214 }
5215 break;
5216
5217 case MVE_VCVT_FROM_FP_TO_INT:
5218 {
5219 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
5220
5221 switch (size)
5222 {
5223 case 2:
5224 func (stream, "s16.f16");
5225 break;
5226
5227 case 3:
5228 func (stream, "u16.f16");
5229 break;
5230
5231 case 4:
5232 func (stream, "s32.f32");
5233 break;
5234
5235 case 5:
5236 func (stream, "u32.f32");
5237 break;
5238
5239 default:
5240 break;
5241 }
5242 }
5243 break;
5244
5245 default:
5246 break;
5247 }
5248 }
5249
5250 static void
5251 print_instruction_predicate (struct disassemble_info *info)
5252 {
5253 void *stream = info->stream;
5254 fprintf_ftype func = info->fprintf_func;
5255
5256 if (vpt_block_state.next_pred_state == PRED_THEN)
5257 func (stream, "t");
5258 else if (vpt_block_state.next_pred_state == PRED_ELSE)
5259 func (stream, "e");
5260 }
5261
5262 static void
5263 print_mve_size (struct disassemble_info *info,
5264 unsigned long size,
5265 enum mve_instructions matched_insn)
5266 {
5267 void *stream = info->stream;
5268 fprintf_ftype func = info->fprintf_func;
5269
5270 switch (matched_insn)
5271 {
5272 case MVE_VCMP_VEC_T1:
5273 case MVE_VCMP_VEC_T2:
5274 case MVE_VCMP_VEC_T3:
5275 case MVE_VCMP_VEC_T4:
5276 case MVE_VCMP_VEC_T5:
5277 case MVE_VCMP_VEC_T6:
5278 case MVE_VHADD_T1:
5279 case MVE_VHADD_T2:
5280 case MVE_VHSUB_T1:
5281 case MVE_VHSUB_T2:
5282 case MVE_VLD2:
5283 case MVE_VLD4:
5284 case MVE_VLDRB_GATHER_T1:
5285 case MVE_VLDRH_GATHER_T2:
5286 case MVE_VLDRW_GATHER_T3:
5287 case MVE_VLDRD_GATHER_T4:
5288 case MVE_VLDRB_T1:
5289 case MVE_VLDRH_T2:
5290 case MVE_VPT_VEC_T1:
5291 case MVE_VPT_VEC_T2:
5292 case MVE_VPT_VEC_T3:
5293 case MVE_VPT_VEC_T4:
5294 case MVE_VPT_VEC_T5:
5295 case MVE_VPT_VEC_T6:
5296 case MVE_VRHADD:
5297 case MVE_VRINT_FP:
5298 case MVE_VST2:
5299 case MVE_VST4:
5300 case MVE_VSTRB_SCATTER_T1:
5301 case MVE_VSTRH_SCATTER_T2:
5302 case MVE_VSTRW_SCATTER_T3:
5303 case MVE_VSTRB_T1:
5304 case MVE_VSTRH_T2:
5305 if (size <= 3)
5306 func (stream, "%s", mve_vec_sizename[size]);
5307 else
5308 func (stream, "<undef size>");
5309 break;
5310
5311 case MVE_VCMP_FP_T1:
5312 case MVE_VCMP_FP_T2:
5313 case MVE_VFMA_FP_SCALAR:
5314 case MVE_VFMA_FP:
5315 case MVE_VFMS_FP:
5316 case MVE_VFMAS_FP_SCALAR:
5317 case MVE_VPT_FP_T1:
5318 case MVE_VPT_FP_T2:
5319 if (size == 0)
5320 func (stream, "32");
5321 else if (size == 1)
5322 func (stream, "16");
5323 break;
5324
5325 case MVE_VDUP:
5326 switch (size)
5327 {
5328 case 0:
5329 func (stream, "32");
5330 break;
5331 case 1:
5332 func (stream, "16");
5333 break;
5334 case 2:
5335 func (stream, "8");
5336 break;
5337 default:
5338 break;
5339 }
5340 break;
5341
5342 default:
5343 break;
5344 }
5345 }
5346
5347 static void
5348 print_vec_condition (struct disassemble_info *info, long given,
5349 enum mve_instructions matched_insn)
5350 {
5351 void *stream = info->stream;
5352 fprintf_ftype func = info->fprintf_func;
5353 long vec_cond = 0;
5354
5355 switch (matched_insn)
5356 {
5357 case MVE_VPT_FP_T1:
5358 case MVE_VCMP_FP_T1:
5359 vec_cond = (((given & 0x1000) >> 10)
5360 | ((given & 1) << 1)
5361 | ((given & 0x0080) >> 7));
5362 func (stream, "%s",vec_condnames[vec_cond]);
5363 break;
5364
5365 case MVE_VPT_FP_T2:
5366 case MVE_VCMP_FP_T2:
5367 vec_cond = (((given & 0x1000) >> 10)
5368 | ((given & 0x0020) >> 4)
5369 | ((given & 0x0080) >> 7));
5370 func (stream, "%s",vec_condnames[vec_cond]);
5371 break;
5372
5373 case MVE_VPT_VEC_T1:
5374 case MVE_VCMP_VEC_T1:
5375 vec_cond = (given & 0x0080) >> 7;
5376 func (stream, "%s",vec_condnames[vec_cond]);
5377 break;
5378
5379 case MVE_VPT_VEC_T2:
5380 case MVE_VCMP_VEC_T2:
5381 vec_cond = 2 | ((given & 0x0080) >> 7);
5382 func (stream, "%s",vec_condnames[vec_cond]);
5383 break;
5384
5385 case MVE_VPT_VEC_T3:
5386 case MVE_VCMP_VEC_T3:
5387 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
5388 func (stream, "%s",vec_condnames[vec_cond]);
5389 break;
5390
5391 case MVE_VPT_VEC_T4:
5392 case MVE_VCMP_VEC_T4:
5393 vec_cond = (given & 0x0080) >> 7;
5394 func (stream, "%s",vec_condnames[vec_cond]);
5395 break;
5396
5397 case MVE_VPT_VEC_T5:
5398 case MVE_VCMP_VEC_T5:
5399 vec_cond = 2 | ((given & 0x0080) >> 7);
5400 func (stream, "%s",vec_condnames[vec_cond]);
5401 break;
5402
5403 case MVE_VPT_VEC_T6:
5404 case MVE_VCMP_VEC_T6:
5405 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
5406 func (stream, "%s",vec_condnames[vec_cond]);
5407 break;
5408
5409 case MVE_NONE:
5410 case MVE_VPST:
5411 default:
5412 break;
5413 }
5414 }
5415
5416 #define W_BIT 21
5417 #define I_BIT 22
5418 #define U_BIT 23
5419 #define P_BIT 24
5420
5421 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
5422 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
5423 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
5424 #define PRE_BIT_SET (given & (1 << P_BIT))
5425
5426
5427 /* Print one coprocessor instruction on INFO->STREAM.
5428 Return TRUE if the instuction matched, FALSE if this is not a
5429 recognised coprocessor instruction. */
5430
5431 static bfd_boolean
5432 print_insn_coprocessor (bfd_vma pc,
5433 struct disassemble_info *info,
5434 long given,
5435 bfd_boolean thumb)
5436 {
5437 const struct sopcode32 *insn;
5438 void *stream = info->stream;
5439 fprintf_ftype func = info->fprintf_func;
5440 unsigned long mask;
5441 unsigned long value = 0;
5442 int cond;
5443 int cp_num;
5444 struct arm_private_data *private_data = info->private_data;
5445 arm_feature_set allowed_arches = ARM_ARCH_NONE;
5446 arm_feature_set arm_ext_v8_1m_main =
5447 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5448
5449 allowed_arches = private_data->features;
5450
5451 for (insn = coprocessor_opcodes; insn->assembler; insn++)
5452 {
5453 unsigned long u_reg = 16;
5454 bfd_boolean is_unpredictable = FALSE;
5455 signed long value_in_comment = 0;
5456 const char *c;
5457
5458 if (ARM_FEATURE_ZERO (insn->arch))
5459 switch (insn->value)
5460 {
5461 case SENTINEL_IWMMXT_START:
5462 if (info->mach != bfd_mach_arm_XScale
5463 && info->mach != bfd_mach_arm_iWMMXt
5464 && info->mach != bfd_mach_arm_iWMMXt2)
5465 do
5466 insn++;
5467 while ((! ARM_FEATURE_ZERO (insn->arch))
5468 && insn->value != SENTINEL_IWMMXT_END);
5469 continue;
5470
5471 case SENTINEL_IWMMXT_END:
5472 continue;
5473
5474 case SENTINEL_GENERIC_START:
5475 allowed_arches = private_data->features;
5476 continue;
5477
5478 default:
5479 abort ();
5480 }
5481
5482 mask = insn->mask;
5483 value = insn->value;
5484 cp_num = (given >> 8) & 0xf;
5485
5486 if (thumb)
5487 {
5488 /* The high 4 bits are 0xe for Arm conditional instructions, and
5489 0xe for arm unconditional instructions. The rest of the
5490 encoding is the same. */
5491 mask |= 0xf0000000;
5492 value |= 0xe0000000;
5493 if (ifthen_state)
5494 cond = IFTHEN_COND;
5495 else
5496 cond = COND_UNCOND;
5497 }
5498 else
5499 {
5500 /* Only match unconditional instuctions against unconditional
5501 patterns. */
5502 if ((given & 0xf0000000) == 0xf0000000)
5503 {
5504 mask |= 0xf0000000;
5505 cond = COND_UNCOND;
5506 }
5507 else
5508 {
5509 cond = (given >> 28) & 0xf;
5510 if (cond == 0xe)
5511 cond = COND_UNCOND;
5512 }
5513 }
5514
5515 if ((insn->isa == T32 && !thumb)
5516 || (insn->isa == ARM && thumb))
5517 continue;
5518
5519 if ((given & mask) != value)
5520 continue;
5521
5522 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
5523 continue;
5524
5525 if (insn->value == 0xfe000010 /* mcr2 */
5526 || insn->value == 0xfe100010 /* mrc2 */
5527 || insn->value == 0xfc100000 /* ldc2 */
5528 || insn->value == 0xfc000000) /* stc2 */
5529 {
5530 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
5531 is_unpredictable = TRUE;
5532
5533 /* Armv8.1-M Mainline FP & MVE instructions. */
5534 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5535 && !ARM_CPU_IS_ANY (allowed_arches)
5536 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
5537 continue;
5538
5539 }
5540 else if (insn->value == 0x0e000000 /* cdp */
5541 || insn->value == 0xfe000000 /* cdp2 */
5542 || insn->value == 0x0e000010 /* mcr */
5543 || insn->value == 0x0e100010 /* mrc */
5544 || insn->value == 0x0c100000 /* ldc */
5545 || insn->value == 0x0c000000) /* stc */
5546 {
5547 /* Floating-point instructions. */
5548 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
5549 continue;
5550
5551 /* Armv8.1-M Mainline FP & MVE instructions. */
5552 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5553 && !ARM_CPU_IS_ANY (allowed_arches)
5554 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
5555 continue;
5556 }
5557 else if ((insn->value == 0xec100f80 /* vldr (system register) */
5558 || insn->value == 0xec000f80) /* vstr (system register) */
5559 && arm_decode_field (given, 24, 24) == 0
5560 && arm_decode_field (given, 21, 21) == 0)
5561 /* If the P and W bits are both 0 then these encodings match the MVE
5562 VLDR and VSTR instructions, these are in a different table, so we
5563 don't let it match here. */
5564 continue;
5565
5566
5567 for (c = insn->assembler; *c; c++)
5568 {
5569 if (*c == '%')
5570 {
5571 const char mod = *++c;
5572 switch (mod)
5573 {
5574 case '%':
5575 func (stream, "%%");
5576 break;
5577
5578 case 'A':
5579 case 'K':
5580 {
5581 int rn = (given >> 16) & 0xf;
5582 bfd_vma offset = given & 0xff;
5583
5584 if (mod == 'K')
5585 offset = given & 0x7f;
5586
5587 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
5588
5589 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
5590 {
5591 /* Not unindexed. The offset is scaled. */
5592 if (cp_num == 9)
5593 /* vldr.16/vstr.16 will shift the address
5594 left by 1 bit only. */
5595 offset = offset * 2;
5596 else
5597 offset = offset * 4;
5598
5599 if (NEGATIVE_BIT_SET)
5600 offset = - offset;
5601 if (rn != 15)
5602 value_in_comment = offset;
5603 }
5604
5605 if (PRE_BIT_SET)
5606 {
5607 if (offset)
5608 func (stream, ", #%d]%s",
5609 (int) offset,
5610 WRITEBACK_BIT_SET ? "!" : "");
5611 else if (NEGATIVE_BIT_SET)
5612 func (stream, ", #-0]");
5613 else
5614 func (stream, "]");
5615 }
5616 else
5617 {
5618 func (stream, "]");
5619
5620 if (WRITEBACK_BIT_SET)
5621 {
5622 if (offset)
5623 func (stream, ", #%d", (int) offset);
5624 else if (NEGATIVE_BIT_SET)
5625 func (stream, ", #-0");
5626 }
5627 else
5628 {
5629 func (stream, ", {%s%d}",
5630 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
5631 (int) offset);
5632 value_in_comment = offset;
5633 }
5634 }
5635 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
5636 {
5637 func (stream, "\t; ");
5638 /* For unaligned PCs, apply off-by-alignment
5639 correction. */
5640 info->print_address_func (offset + pc
5641 + info->bytes_per_chunk * 2
5642 - (pc & 3),
5643 info);
5644 }
5645 }
5646 break;
5647
5648 case 'B':
5649 {
5650 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
5651 int offset = (given >> 1) & 0x3f;
5652
5653 if (offset == 1)
5654 func (stream, "{d%d}", regno);
5655 else if (regno + offset > 32)
5656 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
5657 else
5658 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
5659 }
5660 break;
5661
5662 case 'C':
5663 {
5664 bfd_boolean single = ((given >> 8) & 1) == 0;
5665 char reg_prefix = single ? 's' : 'd';
5666 int Dreg = (given >> 22) & 0x1;
5667 int Vdreg = (given >> 12) & 0xf;
5668 int reg = single ? ((Vdreg << 1) | Dreg)
5669 : ((Dreg << 4) | Vdreg);
5670 int num = (given >> (single ? 0 : 1)) & 0x7f;
5671 int maxreg = single ? 31 : 15;
5672 int topreg = reg + num - 1;
5673
5674 if (!num)
5675 func (stream, "{VPR}");
5676 else if (num == 1)
5677 func (stream, "{%c%d, VPR}", reg_prefix, reg);
5678 else if (topreg > maxreg)
5679 func (stream, "{%c%d-<overflow reg d%d, VPR}",
5680 reg_prefix, reg, single ? topreg >> 1 : topreg);
5681 else
5682 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
5683 reg_prefix, topreg);
5684 }
5685 break;
5686
5687 case 'u':
5688 if (cond != COND_UNCOND)
5689 is_unpredictable = TRUE;
5690
5691 /* Fall through. */
5692 case 'c':
5693 if (cond != COND_UNCOND && cp_num == 9)
5694 is_unpredictable = TRUE;
5695
5696 func (stream, "%s", arm_conditional[cond]);
5697 break;
5698
5699 case 'I':
5700 /* Print a Cirrus/DSP shift immediate. */
5701 /* Immediates are 7bit signed ints with bits 0..3 in
5702 bits 0..3 of opcode and bits 4..6 in bits 5..7
5703 of opcode. */
5704 {
5705 int imm;
5706
5707 imm = (given & 0xf) | ((given & 0xe0) >> 1);
5708
5709 /* Is ``imm'' a negative number? */
5710 if (imm & 0x40)
5711 imm -= 0x80;
5712
5713 func (stream, "%d", imm);
5714 }
5715
5716 break;
5717
5718 case 'J':
5719 {
5720 unsigned long regno
5721 = arm_decode_field_multiple (given, 13, 15, 22, 22);
5722
5723 switch (regno)
5724 {
5725 case 0x1:
5726 func (stream, "FPSCR");
5727 break;
5728 case 0x2:
5729 func (stream, "FPSCR_nzcvqc");
5730 break;
5731 case 0xc:
5732 func (stream, "VPR");
5733 break;
5734 case 0xd:
5735 func (stream, "P0");
5736 break;
5737 case 0xe:
5738 func (stream, "FPCXTNS");
5739 break;
5740 case 0xf:
5741 func (stream, "FPCXTS");
5742 break;
5743 default:
5744 func (stream, "<invalid reg %lu>", regno);
5745 break;
5746 }
5747 }
5748 break;
5749
5750 case 'F':
5751 switch (given & 0x00408000)
5752 {
5753 case 0:
5754 func (stream, "4");
5755 break;
5756 case 0x8000:
5757 func (stream, "1");
5758 break;
5759 case 0x00400000:
5760 func (stream, "2");
5761 break;
5762 default:
5763 func (stream, "3");
5764 }
5765 break;
5766
5767 case 'P':
5768 switch (given & 0x00080080)
5769 {
5770 case 0:
5771 func (stream, "s");
5772 break;
5773 case 0x80:
5774 func (stream, "d");
5775 break;
5776 case 0x00080000:
5777 func (stream, "e");
5778 break;
5779 default:
5780 func (stream, _("<illegal precision>"));
5781 break;
5782 }
5783 break;
5784
5785 case 'Q':
5786 switch (given & 0x00408000)
5787 {
5788 case 0:
5789 func (stream, "s");
5790 break;
5791 case 0x8000:
5792 func (stream, "d");
5793 break;
5794 case 0x00400000:
5795 func (stream, "e");
5796 break;
5797 default:
5798 func (stream, "p");
5799 break;
5800 }
5801 break;
5802
5803 case 'R':
5804 switch (given & 0x60)
5805 {
5806 case 0:
5807 break;
5808 case 0x20:
5809 func (stream, "p");
5810 break;
5811 case 0x40:
5812 func (stream, "m");
5813 break;
5814 default:
5815 func (stream, "z");
5816 break;
5817 }
5818 break;
5819
5820 case '0': case '1': case '2': case '3': case '4':
5821 case '5': case '6': case '7': case '8': case '9':
5822 {
5823 int width;
5824
5825 c = arm_decode_bitfield (c, given, &value, &width);
5826
5827 switch (*c)
5828 {
5829 case 'R':
5830 if (value == 15)
5831 is_unpredictable = TRUE;
5832 /* Fall through. */
5833 case 'r':
5834 if (c[1] == 'u')
5835 {
5836 /* Eat the 'u' character. */
5837 ++ c;
5838
5839 if (u_reg == value)
5840 is_unpredictable = TRUE;
5841 u_reg = value;
5842 }
5843 func (stream, "%s", arm_regnames[value]);
5844 break;
5845 case 'V':
5846 if (given & (1 << 6))
5847 goto Q;
5848 /* FALLTHROUGH */
5849 case 'D':
5850 func (stream, "d%ld", value);
5851 break;
5852 case 'Q':
5853 Q:
5854 if (value & 1)
5855 func (stream, "<illegal reg q%ld.5>", value >> 1);
5856 else
5857 func (stream, "q%ld", value >> 1);
5858 break;
5859 case 'd':
5860 func (stream, "%ld", value);
5861 value_in_comment = value;
5862 break;
5863 case 'E':
5864 {
5865 /* Converts immediate 8 bit back to float value. */
5866 unsigned floatVal = (value & 0x80) << 24
5867 | (value & 0x3F) << 19
5868 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
5869
5870 /* Quarter float have a maximum value of 31.0.
5871 Get floating point value multiplied by 1e7.
5872 The maximum value stays in limit of a 32-bit int. */
5873 unsigned decVal =
5874 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
5875 (16 + (value & 0xF));
5876
5877 if (!(decVal % 1000000))
5878 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
5879 floatVal, value & 0x80 ? '-' : ' ',
5880 decVal / 10000000,
5881 decVal % 10000000 / 1000000);
5882 else if (!(decVal % 10000))
5883 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
5884 floatVal, value & 0x80 ? '-' : ' ',
5885 decVal / 10000000,
5886 decVal % 10000000 / 10000);
5887 else
5888 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
5889 floatVal, value & 0x80 ? '-' : ' ',
5890 decVal / 10000000, decVal % 10000000);
5891 break;
5892 }
5893 case 'k':
5894 {
5895 int from = (given & (1 << 7)) ? 32 : 16;
5896 func (stream, "%ld", from - value);
5897 }
5898 break;
5899
5900 case 'f':
5901 if (value > 7)
5902 func (stream, "#%s", arm_fp_const[value & 7]);
5903 else
5904 func (stream, "f%ld", value);
5905 break;
5906
5907 case 'w':
5908 if (width == 2)
5909 func (stream, "%s", iwmmxt_wwnames[value]);
5910 else
5911 func (stream, "%s", iwmmxt_wwssnames[value]);
5912 break;
5913
5914 case 'g':
5915 func (stream, "%s", iwmmxt_regnames[value]);
5916 break;
5917 case 'G':
5918 func (stream, "%s", iwmmxt_cregnames[value]);
5919 break;
5920
5921 case 'x':
5922 func (stream, "0x%lx", (value & 0xffffffffUL));
5923 break;
5924
5925 case 'c':
5926 switch (value)
5927 {
5928 case 0:
5929 func (stream, "eq");
5930 break;
5931
5932 case 1:
5933 func (stream, "vs");
5934 break;
5935
5936 case 2:
5937 func (stream, "ge");
5938 break;
5939
5940 case 3:
5941 func (stream, "gt");
5942 break;
5943
5944 default:
5945 func (stream, "??");
5946 break;
5947 }
5948 break;
5949
5950 case '`':
5951 c++;
5952 if (value == 0)
5953 func (stream, "%c", *c);
5954 break;
5955 case '\'':
5956 c++;
5957 if (value == ((1ul << width) - 1))
5958 func (stream, "%c", *c);
5959 break;
5960 case '?':
5961 func (stream, "%c", c[(1 << width) - (int) value]);
5962 c += 1 << width;
5963 break;
5964 default:
5965 abort ();
5966 }
5967 }
5968 break;
5969
5970 case 'y':
5971 case 'z':
5972 {
5973 int single = *c++ == 'y';
5974 int regno;
5975
5976 switch (*c)
5977 {
5978 case '4': /* Sm pair */
5979 case '0': /* Sm, Dm */
5980 regno = given & 0x0000000f;
5981 if (single)
5982 {
5983 regno <<= 1;
5984 regno += (given >> 5) & 1;
5985 }
5986 else
5987 regno += ((given >> 5) & 1) << 4;
5988 break;
5989
5990 case '1': /* Sd, Dd */
5991 regno = (given >> 12) & 0x0000000f;
5992 if (single)
5993 {
5994 regno <<= 1;
5995 regno += (given >> 22) & 1;
5996 }
5997 else
5998 regno += ((given >> 22) & 1) << 4;
5999 break;
6000
6001 case '2': /* Sn, Dn */
6002 regno = (given >> 16) & 0x0000000f;
6003 if (single)
6004 {
6005 regno <<= 1;
6006 regno += (given >> 7) & 1;
6007 }
6008 else
6009 regno += ((given >> 7) & 1) << 4;
6010 break;
6011
6012 case '3': /* List */
6013 func (stream, "{");
6014 regno = (given >> 12) & 0x0000000f;
6015 if (single)
6016 {
6017 regno <<= 1;
6018 regno += (given >> 22) & 1;
6019 }
6020 else
6021 regno += ((given >> 22) & 1) << 4;
6022 break;
6023
6024 default:
6025 abort ();
6026 }
6027
6028 func (stream, "%c%d", single ? 's' : 'd', regno);
6029
6030 if (*c == '3')
6031 {
6032 int count = given & 0xff;
6033
6034 if (single == 0)
6035 count >>= 1;
6036
6037 if (--count)
6038 {
6039 func (stream, "-%c%d",
6040 single ? 's' : 'd',
6041 regno + count);
6042 }
6043
6044 func (stream, "}");
6045 }
6046 else if (*c == '4')
6047 func (stream, ", %c%d", single ? 's' : 'd',
6048 regno + 1);
6049 }
6050 break;
6051
6052 case 'L':
6053 switch (given & 0x00400100)
6054 {
6055 case 0x00000000: func (stream, "b"); break;
6056 case 0x00400000: func (stream, "h"); break;
6057 case 0x00000100: func (stream, "w"); break;
6058 case 0x00400100: func (stream, "d"); break;
6059 default:
6060 break;
6061 }
6062 break;
6063
6064 case 'Z':
6065 {
6066 /* given (20, 23) | given (0, 3) */
6067 value = ((given >> 16) & 0xf0) | (given & 0xf);
6068 func (stream, "%d", (int) value);
6069 }
6070 break;
6071
6072 case 'l':
6073 /* This is like the 'A' operator, except that if
6074 the width field "M" is zero, then the offset is
6075 *not* multiplied by four. */
6076 {
6077 int offset = given & 0xff;
6078 int multiplier = (given & 0x00000100) ? 4 : 1;
6079
6080 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
6081
6082 if (multiplier > 1)
6083 {
6084 value_in_comment = offset * multiplier;
6085 if (NEGATIVE_BIT_SET)
6086 value_in_comment = - value_in_comment;
6087 }
6088
6089 if (offset)
6090 {
6091 if (PRE_BIT_SET)
6092 func (stream, ", #%s%d]%s",
6093 NEGATIVE_BIT_SET ? "-" : "",
6094 offset * multiplier,
6095 WRITEBACK_BIT_SET ? "!" : "");
6096 else
6097 func (stream, "], #%s%d",
6098 NEGATIVE_BIT_SET ? "-" : "",
6099 offset * multiplier);
6100 }
6101 else
6102 func (stream, "]");
6103 }
6104 break;
6105
6106 case 'r':
6107 {
6108 int imm4 = (given >> 4) & 0xf;
6109 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
6110 int ubit = ! NEGATIVE_BIT_SET;
6111 const char *rm = arm_regnames [given & 0xf];
6112 const char *rn = arm_regnames [(given >> 16) & 0xf];
6113
6114 switch (puw_bits)
6115 {
6116 case 1:
6117 case 3:
6118 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
6119 if (imm4)
6120 func (stream, ", lsl #%d", imm4);
6121 break;
6122
6123 case 4:
6124 case 5:
6125 case 6:
6126 case 7:
6127 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
6128 if (imm4 > 0)
6129 func (stream, ", lsl #%d", imm4);
6130 func (stream, "]");
6131 if (puw_bits == 5 || puw_bits == 7)
6132 func (stream, "!");
6133 break;
6134
6135 default:
6136 func (stream, "INVALID");
6137 }
6138 }
6139 break;
6140
6141 case 'i':
6142 {
6143 long imm5;
6144 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
6145 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
6146 }
6147 break;
6148
6149 default:
6150 abort ();
6151 }
6152 }
6153 else
6154 func (stream, "%c", *c);
6155 }
6156
6157 if (value_in_comment > 32 || value_in_comment < -16)
6158 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
6159
6160 if (is_unpredictable)
6161 func (stream, UNPREDICTABLE_INSTRUCTION);
6162
6163 return TRUE;
6164 }
6165 return FALSE;
6166 }
6167
6168 /* Decodes and prints ARM addressing modes. Returns the offset
6169 used in the address, if any, if it is worthwhile printing the
6170 offset as a hexadecimal value in a comment at the end of the
6171 line of disassembly. */
6172
6173 static signed long
6174 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
6175 {
6176 void *stream = info->stream;
6177 fprintf_ftype func = info->fprintf_func;
6178 bfd_vma offset = 0;
6179
6180 if (((given & 0x000f0000) == 0x000f0000)
6181 && ((given & 0x02000000) == 0))
6182 {
6183 offset = given & 0xfff;
6184
6185 func (stream, "[pc");
6186
6187 if (PRE_BIT_SET)
6188 {
6189 /* Pre-indexed. Elide offset of positive zero when
6190 non-writeback. */
6191 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
6192 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
6193
6194 if (NEGATIVE_BIT_SET)
6195 offset = -offset;
6196
6197 offset += pc + 8;
6198
6199 /* Cope with the possibility of write-back
6200 being used. Probably a very dangerous thing
6201 for the programmer to do, but who are we to
6202 argue ? */
6203 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
6204 }
6205 else /* Post indexed. */
6206 {
6207 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
6208
6209 /* Ie ignore the offset. */
6210 offset = pc + 8;
6211 }
6212
6213 func (stream, "\t; ");
6214 info->print_address_func (offset, info);
6215 offset = 0;
6216 }
6217 else
6218 {
6219 func (stream, "[%s",
6220 arm_regnames[(given >> 16) & 0xf]);
6221
6222 if (PRE_BIT_SET)
6223 {
6224 if ((given & 0x02000000) == 0)
6225 {
6226 /* Elide offset of positive zero when non-writeback. */
6227 offset = given & 0xfff;
6228 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
6229 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
6230 }
6231 else
6232 {
6233 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
6234 arm_decode_shift (given, func, stream, TRUE);
6235 }
6236
6237 func (stream, "]%s",
6238 WRITEBACK_BIT_SET ? "!" : "");
6239 }
6240 else
6241 {
6242 if ((given & 0x02000000) == 0)
6243 {
6244 /* Always show offset. */
6245 offset = given & 0xfff;
6246 func (stream, "], #%s%d",
6247 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
6248 }
6249 else
6250 {
6251 func (stream, "], %s",
6252 NEGATIVE_BIT_SET ? "-" : "");
6253 arm_decode_shift (given, func, stream, TRUE);
6254 }
6255 }
6256 if (NEGATIVE_BIT_SET)
6257 offset = -offset;
6258 }
6259
6260 return (signed long) offset;
6261 }
6262
6263 /* Print one neon instruction on INFO->STREAM.
6264 Return TRUE if the instuction matched, FALSE if this is not a
6265 recognised neon instruction. */
6266
6267 static bfd_boolean
6268 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
6269 {
6270 const struct opcode32 *insn;
6271 void *stream = info->stream;
6272 fprintf_ftype func = info->fprintf_func;
6273
6274 if (thumb)
6275 {
6276 if ((given & 0xef000000) == 0xef000000)
6277 {
6278 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
6279 unsigned long bit28 = given & (1 << 28);
6280
6281 given &= 0x00ffffff;
6282 if (bit28)
6283 given |= 0xf3000000;
6284 else
6285 given |= 0xf2000000;
6286 }
6287 else if ((given & 0xff000000) == 0xf9000000)
6288 given ^= 0xf9000000 ^ 0xf4000000;
6289 /* vdup is also a valid neon instruction. */
6290 else if ((given & 0xff910f5f) != 0xee800b10)
6291 return FALSE;
6292 }
6293
6294 for (insn = neon_opcodes; insn->assembler; insn++)
6295 {
6296 if ((given & insn->mask) == insn->value)
6297 {
6298 signed long value_in_comment = 0;
6299 bfd_boolean is_unpredictable = FALSE;
6300 const char *c;
6301
6302 for (c = insn->assembler; *c; c++)
6303 {
6304 if (*c == '%')
6305 {
6306 switch (*++c)
6307 {
6308 case '%':
6309 func (stream, "%%");
6310 break;
6311
6312 case 'u':
6313 if (thumb && ifthen_state)
6314 is_unpredictable = TRUE;
6315
6316 /* Fall through. */
6317 case 'c':
6318 if (thumb && ifthen_state)
6319 func (stream, "%s", arm_conditional[IFTHEN_COND]);
6320 break;
6321
6322 case 'A':
6323 {
6324 static const unsigned char enc[16] =
6325 {
6326 0x4, 0x14, /* st4 0,1 */
6327 0x4, /* st1 2 */
6328 0x4, /* st2 3 */
6329 0x3, /* st3 4 */
6330 0x13, /* st3 5 */
6331 0x3, /* st1 6 */
6332 0x1, /* st1 7 */
6333 0x2, /* st2 8 */
6334 0x12, /* st2 9 */
6335 0x2, /* st1 10 */
6336 0, 0, 0, 0, 0
6337 };
6338 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
6339 int rn = ((given >> 16) & 0xf);
6340 int rm = ((given >> 0) & 0xf);
6341 int align = ((given >> 4) & 0x3);
6342 int type = ((given >> 8) & 0xf);
6343 int n = enc[type] & 0xf;
6344 int stride = (enc[type] >> 4) + 1;
6345 int ix;
6346
6347 func (stream, "{");
6348 if (stride > 1)
6349 for (ix = 0; ix != n; ix++)
6350 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
6351 else if (n == 1)
6352 func (stream, "d%d", rd);
6353 else
6354 func (stream, "d%d-d%d", rd, rd + n - 1);
6355 func (stream, "}, [%s", arm_regnames[rn]);
6356 if (align)
6357 func (stream, " :%d", 32 << align);
6358 func (stream, "]");
6359 if (rm == 0xd)
6360 func (stream, "!");
6361 else if (rm != 0xf)
6362 func (stream, ", %s", arm_regnames[rm]);
6363 }
6364 break;
6365
6366 case 'B':
6367 {
6368 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
6369 int rn = ((given >> 16) & 0xf);
6370 int rm = ((given >> 0) & 0xf);
6371 int idx_align = ((given >> 4) & 0xf);
6372 int align = 0;
6373 int size = ((given >> 10) & 0x3);
6374 int idx = idx_align >> (size + 1);
6375 int length = ((given >> 8) & 3) + 1;
6376 int stride = 1;
6377 int i;
6378
6379 if (length > 1 && size > 0)
6380 stride = (idx_align & (1 << size)) ? 2 : 1;
6381
6382 switch (length)
6383 {
6384 case 1:
6385 {
6386 int amask = (1 << size) - 1;
6387 if ((idx_align & (1 << size)) != 0)
6388 return FALSE;
6389 if (size > 0)
6390 {
6391 if ((idx_align & amask) == amask)
6392 align = 8 << size;
6393 else if ((idx_align & amask) != 0)
6394 return FALSE;
6395 }
6396 }
6397 break;
6398
6399 case 2:
6400 if (size == 2 && (idx_align & 2) != 0)
6401 return FALSE;
6402 align = (idx_align & 1) ? 16 << size : 0;
6403 break;
6404
6405 case 3:
6406 if ((size == 2 && (idx_align & 3) != 0)
6407 || (idx_align & 1) != 0)
6408 return FALSE;
6409 break;
6410
6411 case 4:
6412 if (size == 2)
6413 {
6414 if ((idx_align & 3) == 3)
6415 return FALSE;
6416 align = (idx_align & 3) * 64;
6417 }
6418 else
6419 align = (idx_align & 1) ? 32 << size : 0;
6420 break;
6421
6422 default:
6423 abort ();
6424 }
6425
6426 func (stream, "{");
6427 for (i = 0; i < length; i++)
6428 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
6429 rd + i * stride, idx);
6430 func (stream, "}, [%s", arm_regnames[rn]);
6431 if (align)
6432 func (stream, " :%d", align);
6433 func (stream, "]");
6434 if (rm == 0xd)
6435 func (stream, "!");
6436 else if (rm != 0xf)
6437 func (stream, ", %s", arm_regnames[rm]);
6438 }
6439 break;
6440
6441 case 'C':
6442 {
6443 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
6444 int rn = ((given >> 16) & 0xf);
6445 int rm = ((given >> 0) & 0xf);
6446 int align = ((given >> 4) & 0x1);
6447 int size = ((given >> 6) & 0x3);
6448 int type = ((given >> 8) & 0x3);
6449 int n = type + 1;
6450 int stride = ((given >> 5) & 0x1);
6451 int ix;
6452
6453 if (stride && (n == 1))
6454 n++;
6455 else
6456 stride++;
6457
6458 func (stream, "{");
6459 if (stride > 1)
6460 for (ix = 0; ix != n; ix++)
6461 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
6462 else if (n == 1)
6463 func (stream, "d%d[]", rd);
6464 else
6465 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
6466 func (stream, "}, [%s", arm_regnames[rn]);
6467 if (align)
6468 {
6469 align = (8 * (type + 1)) << size;
6470 if (type == 3)
6471 align = (size > 1) ? align >> 1 : align;
6472 if (type == 2 || (type == 0 && !size))
6473 func (stream, " :<bad align %d>", align);
6474 else
6475 func (stream, " :%d", align);
6476 }
6477 func (stream, "]");
6478 if (rm == 0xd)
6479 func (stream, "!");
6480 else if (rm != 0xf)
6481 func (stream, ", %s", arm_regnames[rm]);
6482 }
6483 break;
6484
6485 case 'D':
6486 {
6487 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
6488 int size = (given >> 20) & 3;
6489 int reg = raw_reg & ((4 << size) - 1);
6490 int ix = raw_reg >> size >> 2;
6491
6492 func (stream, "d%d[%d]", reg, ix);
6493 }
6494 break;
6495
6496 case 'E':
6497 /* Neon encoded constant for mov, mvn, vorr, vbic. */
6498 {
6499 int bits = 0;
6500 int cmode = (given >> 8) & 0xf;
6501 int op = (given >> 5) & 0x1;
6502 unsigned long value = 0, hival = 0;
6503 unsigned shift;
6504 int size = 0;
6505 int isfloat = 0;
6506
6507 bits |= ((given >> 24) & 1) << 7;
6508 bits |= ((given >> 16) & 7) << 4;
6509 bits |= ((given >> 0) & 15) << 0;
6510
6511 if (cmode < 8)
6512 {
6513 shift = (cmode >> 1) & 3;
6514 value = (unsigned long) bits << (8 * shift);
6515 size = 32;
6516 }
6517 else if (cmode < 12)
6518 {
6519 shift = (cmode >> 1) & 1;
6520 value = (unsigned long) bits << (8 * shift);
6521 size = 16;
6522 }
6523 else if (cmode < 14)
6524 {
6525 shift = (cmode & 1) + 1;
6526 value = (unsigned long) bits << (8 * shift);
6527 value |= (1ul << (8 * shift)) - 1;
6528 size = 32;
6529 }
6530 else if (cmode == 14)
6531 {
6532 if (op)
6533 {
6534 /* Bit replication into bytes. */
6535 int ix;
6536 unsigned long mask;
6537
6538 value = 0;
6539 hival = 0;
6540 for (ix = 7; ix >= 0; ix--)
6541 {
6542 mask = ((bits >> ix) & 1) ? 0xff : 0;
6543 if (ix <= 3)
6544 value = (value << 8) | mask;
6545 else
6546 hival = (hival << 8) | mask;
6547 }
6548 size = 64;
6549 }
6550 else
6551 {
6552 /* Byte replication. */
6553 value = (unsigned long) bits;
6554 size = 8;
6555 }
6556 }
6557 else if (!op)
6558 {
6559 /* Floating point encoding. */
6560 int tmp;
6561
6562 value = (unsigned long) (bits & 0x7f) << 19;
6563 value |= (unsigned long) (bits & 0x80) << 24;
6564 tmp = bits & 0x40 ? 0x3c : 0x40;
6565 value |= (unsigned long) tmp << 24;
6566 size = 32;
6567 isfloat = 1;
6568 }
6569 else
6570 {
6571 func (stream, "<illegal constant %.8x:%x:%x>",
6572 bits, cmode, op);
6573 size = 32;
6574 break;
6575 }
6576 switch (size)
6577 {
6578 case 8:
6579 func (stream, "#%ld\t; 0x%.2lx", value, value);
6580 break;
6581
6582 case 16:
6583 func (stream, "#%ld\t; 0x%.4lx", value, value);
6584 break;
6585
6586 case 32:
6587 if (isfloat)
6588 {
6589 unsigned char valbytes[4];
6590 double fvalue;
6591
6592 /* Do this a byte at a time so we don't have to
6593 worry about the host's endianness. */
6594 valbytes[0] = value & 0xff;
6595 valbytes[1] = (value >> 8) & 0xff;
6596 valbytes[2] = (value >> 16) & 0xff;
6597 valbytes[3] = (value >> 24) & 0xff;
6598
6599 floatformat_to_double
6600 (& floatformat_ieee_single_little, valbytes,
6601 & fvalue);
6602
6603 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6604 value);
6605 }
6606 else
6607 func (stream, "#%ld\t; 0x%.8lx",
6608 (long) (((value & 0x80000000L) != 0)
6609 ? value | ~0xffffffffL : value),
6610 value);
6611 break;
6612
6613 case 64:
6614 func (stream, "#0x%.8lx%.8lx", hival, value);
6615 break;
6616
6617 default:
6618 abort ();
6619 }
6620 }
6621 break;
6622
6623 case 'F':
6624 {
6625 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
6626 int num = (given >> 8) & 0x3;
6627
6628 if (!num)
6629 func (stream, "{d%d}", regno);
6630 else if (num + regno >= 32)
6631 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
6632 else
6633 func (stream, "{d%d-d%d}", regno, regno + num);
6634 }
6635 break;
6636
6637
6638 case '0': case '1': case '2': case '3': case '4':
6639 case '5': case '6': case '7': case '8': case '9':
6640 {
6641 int width;
6642 unsigned long value;
6643
6644 c = arm_decode_bitfield (c, given, &value, &width);
6645
6646 switch (*c)
6647 {
6648 case 'r':
6649 func (stream, "%s", arm_regnames[value]);
6650 break;
6651 case 'd':
6652 func (stream, "%ld", value);
6653 value_in_comment = value;
6654 break;
6655 case 'e':
6656 func (stream, "%ld", (1ul << width) - value);
6657 break;
6658
6659 case 'S':
6660 case 'T':
6661 case 'U':
6662 /* Various width encodings. */
6663 {
6664 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
6665 int limit;
6666 unsigned low, high;
6667
6668 c++;
6669 if (*c >= '0' && *c <= '9')
6670 limit = *c - '0';
6671 else if (*c >= 'a' && *c <= 'f')
6672 limit = *c - 'a' + 10;
6673 else
6674 abort ();
6675 low = limit >> 2;
6676 high = limit & 3;
6677
6678 if (value < low || value > high)
6679 func (stream, "<illegal width %d>", base << value);
6680 else
6681 func (stream, "%d", base << value);
6682 }
6683 break;
6684 case 'R':
6685 if (given & (1 << 6))
6686 goto Q;
6687 /* FALLTHROUGH */
6688 case 'D':
6689 func (stream, "d%ld", value);
6690 break;
6691 case 'Q':
6692 Q:
6693 if (value & 1)
6694 func (stream, "<illegal reg q%ld.5>", value >> 1);
6695 else
6696 func (stream, "q%ld", value >> 1);
6697 break;
6698
6699 case '`':
6700 c++;
6701 if (value == 0)
6702 func (stream, "%c", *c);
6703 break;
6704 case '\'':
6705 c++;
6706 if (value == ((1ul << width) - 1))
6707 func (stream, "%c", *c);
6708 break;
6709 case '?':
6710 func (stream, "%c", c[(1 << width) - (int) value]);
6711 c += 1 << width;
6712 break;
6713 default:
6714 abort ();
6715 }
6716 }
6717 break;
6718
6719 default:
6720 abort ();
6721 }
6722 }
6723 else
6724 func (stream, "%c", *c);
6725 }
6726
6727 if (value_in_comment > 32 || value_in_comment < -16)
6728 func (stream, "\t; 0x%lx", value_in_comment);
6729
6730 if (is_unpredictable)
6731 func (stream, UNPREDICTABLE_INSTRUCTION);
6732
6733 return TRUE;
6734 }
6735 }
6736 return FALSE;
6737 }
6738
6739 /* Print one mve instruction on INFO->STREAM.
6740 Return TRUE if the instuction matched, FALSE if this is not a
6741 recognised mve instruction. */
6742
6743 static bfd_boolean
6744 print_insn_mve (struct disassemble_info *info, long given)
6745 {
6746 const struct mopcode32 *insn;
6747 void *stream = info->stream;
6748 fprintf_ftype func = info->fprintf_func;
6749
6750 for (insn = mve_opcodes; insn->assembler; insn++)
6751 {
6752 if (((given & insn->mask) == insn->value)
6753 && !is_mve_encoding_conflict (given, insn->mve_op))
6754 {
6755 signed long value_in_comment = 0;
6756 bfd_boolean is_unpredictable = FALSE;
6757 bfd_boolean is_undefined = FALSE;
6758 const char *c;
6759 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
6760 enum mve_undefined undefined_cond = UNDEF_NONE;
6761
6762 /* Most vector mve instruction are illegal in a it block.
6763 There are a few exceptions; check for them. */
6764 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
6765 {
6766 is_unpredictable = TRUE;
6767 unpredictable_cond = UNPRED_IT_BLOCK;
6768 }
6769 else if (is_mve_unpredictable (given, insn->mve_op,
6770 &unpredictable_cond))
6771 is_unpredictable = TRUE;
6772
6773 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
6774 is_undefined = TRUE;
6775
6776 for (c = insn->assembler; *c; c++)
6777 {
6778 if (*c == '%')
6779 {
6780 switch (*++c)
6781 {
6782 case '%':
6783 func (stream, "%%");
6784 break;
6785
6786 case 'a':
6787 /* Don't print anything for '+' as it is implied. */
6788 if (arm_decode_field (given, 23, 23) == 0)
6789 func (stream, "-");
6790 break;
6791
6792 case 'c':
6793 if (ifthen_state)
6794 func (stream, "%s", arm_conditional[IFTHEN_COND]);
6795 break;
6796
6797 case 'd':
6798 print_mve_vld_str_addr (info, given, insn->mve_op);
6799 break;
6800
6801 case 'i':
6802 {
6803 long mve_mask = mve_extract_pred_mask (given);
6804 func (stream, "%s", mve_predicatenames[mve_mask]);
6805 }
6806 break;
6807
6808 case 'n':
6809 print_vec_condition (info, given, insn->mve_op);
6810 break;
6811
6812 case 'o':
6813 if (arm_decode_field (given, 0, 0) == 1)
6814 {
6815 unsigned long size
6816 = arm_decode_field (given, 4, 4)
6817 | (arm_decode_field (given, 6, 6) << 1);
6818
6819 func (stream, ", uxtw #%lu", size);
6820 }
6821 break;
6822
6823 case 'm':
6824 print_mve_rounding_mode (info, given, insn->mve_op);
6825 break;
6826
6827 case 's':
6828 print_mve_vcvt_size (info, given, insn->mve_op);
6829 break;
6830
6831 case 'u':
6832 {
6833 if (arm_decode_field (given, 28, 28) == 0)
6834 func (stream, "s");
6835 else
6836 func (stream, "u");
6837 }
6838 break;
6839
6840 case 'v':
6841 print_instruction_predicate (info);
6842 break;
6843
6844 case 'w':
6845 if (arm_decode_field (given, 21, 21) == 1)
6846 func (stream, "!");
6847 break;
6848
6849 case 'B':
6850 print_mve_register_blocks (info, given, insn->mve_op);
6851 break;
6852
6853 case '0': case '1': case '2': case '3': case '4':
6854 case '5': case '6': case '7': case '8': case '9':
6855 {
6856 int width;
6857 unsigned long value;
6858
6859 c = arm_decode_bitfield (c, given, &value, &width);
6860
6861 switch (*c)
6862 {
6863 case 'Z':
6864 if (value == 13)
6865 is_unpredictable = TRUE;
6866 else if (value == 15)
6867 func (stream, "zr");
6868 else
6869 func (stream, "%s", arm_regnames[value]);
6870 break;
6871 case 's':
6872 print_mve_size (info,
6873 value,
6874 insn->mve_op);
6875 break;
6876 case 'i':
6877 {
6878 unsigned long imm
6879 = arm_decode_field (given, 0, 6);
6880 unsigned long mod_imm = imm;
6881
6882 switch (insn->mve_op)
6883 {
6884 case MVE_VLDRW_GATHER_T5:
6885 case MVE_VSTRW_SCATTER_T5:
6886 mod_imm = mod_imm << 2;
6887 break;
6888 case MVE_VSTRD_SCATTER_T6:
6889 case MVE_VLDRD_GATHER_T6:
6890 mod_imm = mod_imm << 3;
6891 break;
6892
6893 default:
6894 break;
6895 }
6896
6897 func (stream, "%lu", mod_imm);
6898 }
6899 break;
6900 case 'k':
6901 func (stream, "%lu", 64 - value);
6902 break;
6903 case 'r':
6904 func (stream, "%s", arm_regnames[value]);
6905 break;
6906 case 'd':
6907 func (stream, "%ld", value);
6908 value_in_comment = value;
6909 break;
6910 case 'Q':
6911 if (value & 0x8)
6912 func (stream, "<illegal reg q%ld.5>", value);
6913 else
6914 func (stream, "q%ld", value);
6915 break;
6916 default:
6917 abort ();
6918 }
6919 break;
6920 default:
6921 abort ();
6922 }
6923 }
6924 }
6925 else
6926 func (stream, "%c", *c);
6927 }
6928
6929 if (value_in_comment > 32 || value_in_comment < -16)
6930 func (stream, "\t; 0x%lx", value_in_comment);
6931
6932 if (is_unpredictable)
6933 print_mve_unpredictable (info, unpredictable_cond);
6934
6935 if (is_undefined)
6936 print_mve_undefined (info, undefined_cond);
6937
6938 if ((vpt_block_state.in_vpt_block == FALSE)
6939 && !ifthen_state
6940 && (is_vpt_instruction (given) == TRUE))
6941 mark_inside_vpt_block (given);
6942 else if (vpt_block_state.in_vpt_block == TRUE)
6943 update_vpt_block_state ();
6944
6945 return TRUE;
6946 }
6947 }
6948 return FALSE;
6949 }
6950
6951
6952 /* Return the name of a v7A special register. */
6953
6954 static const char *
6955 banked_regname (unsigned reg)
6956 {
6957 switch (reg)
6958 {
6959 case 15: return "CPSR";
6960 case 32: return "R8_usr";
6961 case 33: return "R9_usr";
6962 case 34: return "R10_usr";
6963 case 35: return "R11_usr";
6964 case 36: return "R12_usr";
6965 case 37: return "SP_usr";
6966 case 38: return "LR_usr";
6967 case 40: return "R8_fiq";
6968 case 41: return "R9_fiq";
6969 case 42: return "R10_fiq";
6970 case 43: return "R11_fiq";
6971 case 44: return "R12_fiq";
6972 case 45: return "SP_fiq";
6973 case 46: return "LR_fiq";
6974 case 48: return "LR_irq";
6975 case 49: return "SP_irq";
6976 case 50: return "LR_svc";
6977 case 51: return "SP_svc";
6978 case 52: return "LR_abt";
6979 case 53: return "SP_abt";
6980 case 54: return "LR_und";
6981 case 55: return "SP_und";
6982 case 60: return "LR_mon";
6983 case 61: return "SP_mon";
6984 case 62: return "ELR_hyp";
6985 case 63: return "SP_hyp";
6986 case 79: return "SPSR";
6987 case 110: return "SPSR_fiq";
6988 case 112: return "SPSR_irq";
6989 case 114: return "SPSR_svc";
6990 case 116: return "SPSR_abt";
6991 case 118: return "SPSR_und";
6992 case 124: return "SPSR_mon";
6993 case 126: return "SPSR_hyp";
6994 default: return NULL;
6995 }
6996 }
6997
6998 /* Return the name of the DMB/DSB option. */
6999 static const char *
7000 data_barrier_option (unsigned option)
7001 {
7002 switch (option & 0xf)
7003 {
7004 case 0xf: return "sy";
7005 case 0xe: return "st";
7006 case 0xd: return "ld";
7007 case 0xb: return "ish";
7008 case 0xa: return "ishst";
7009 case 0x9: return "ishld";
7010 case 0x7: return "un";
7011 case 0x6: return "unst";
7012 case 0x5: return "nshld";
7013 case 0x3: return "osh";
7014 case 0x2: return "oshst";
7015 case 0x1: return "oshld";
7016 default: return NULL;
7017 }
7018 }
7019
7020 /* Print one ARM instruction from PC on INFO->STREAM. */
7021
7022 static void
7023 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
7024 {
7025 const struct opcode32 *insn;
7026 void *stream = info->stream;
7027 fprintf_ftype func = info->fprintf_func;
7028 struct arm_private_data *private_data = info->private_data;
7029
7030 if (print_insn_coprocessor (pc, info, given, FALSE))
7031 return;
7032
7033 if (print_insn_neon (info, given, FALSE))
7034 return;
7035
7036 for (insn = arm_opcodes; insn->assembler; insn++)
7037 {
7038 if ((given & insn->mask) != insn->value)
7039 continue;
7040
7041 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
7042 continue;
7043
7044 /* Special case: an instruction with all bits set in the condition field
7045 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
7046 or by the catchall at the end of the table. */
7047 if ((given & 0xF0000000) != 0xF0000000
7048 || (insn->mask & 0xF0000000) == 0xF0000000
7049 || (insn->mask == 0 && insn->value == 0))
7050 {
7051 unsigned long u_reg = 16;
7052 unsigned long U_reg = 16;
7053 bfd_boolean is_unpredictable = FALSE;
7054 signed long value_in_comment = 0;
7055 const char *c;
7056
7057 for (c = insn->assembler; *c; c++)
7058 {
7059 if (*c == '%')
7060 {
7061 bfd_boolean allow_unpredictable = FALSE;
7062
7063 switch (*++c)
7064 {
7065 case '%':
7066 func (stream, "%%");
7067 break;
7068
7069 case 'a':
7070 value_in_comment = print_arm_address (pc, info, given);
7071 break;
7072
7073 case 'P':
7074 /* Set P address bit and use normal address
7075 printing routine. */
7076 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
7077 break;
7078
7079 case 'S':
7080 allow_unpredictable = TRUE;
7081 /* Fall through. */
7082 case 's':
7083 if ((given & 0x004f0000) == 0x004f0000)
7084 {
7085 /* PC relative with immediate offset. */
7086 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
7087
7088 if (PRE_BIT_SET)
7089 {
7090 /* Elide positive zero offset. */
7091 if (offset || NEGATIVE_BIT_SET)
7092 func (stream, "[pc, #%s%d]\t; ",
7093 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
7094 else
7095 func (stream, "[pc]\t; ");
7096 if (NEGATIVE_BIT_SET)
7097 offset = -offset;
7098 info->print_address_func (offset + pc + 8, info);
7099 }
7100 else
7101 {
7102 /* Always show the offset. */
7103 func (stream, "[pc], #%s%d",
7104 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
7105 if (! allow_unpredictable)
7106 is_unpredictable = TRUE;
7107 }
7108 }
7109 else
7110 {
7111 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
7112
7113 func (stream, "[%s",
7114 arm_regnames[(given >> 16) & 0xf]);
7115
7116 if (PRE_BIT_SET)
7117 {
7118 if (IMMEDIATE_BIT_SET)
7119 {
7120 /* Elide offset for non-writeback
7121 positive zero. */
7122 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
7123 || offset)
7124 func (stream, ", #%s%d",
7125 NEGATIVE_BIT_SET ? "-" : "", offset);
7126
7127 if (NEGATIVE_BIT_SET)
7128 offset = -offset;
7129
7130 value_in_comment = offset;
7131 }
7132 else
7133 {
7134 /* Register Offset or Register Pre-Indexed. */
7135 func (stream, ", %s%s",
7136 NEGATIVE_BIT_SET ? "-" : "",
7137 arm_regnames[given & 0xf]);
7138
7139 /* Writing back to the register that is the source/
7140 destination of the load/store is unpredictable. */
7141 if (! allow_unpredictable
7142 && WRITEBACK_BIT_SET
7143 && ((given & 0xf) == ((given >> 12) & 0xf)))
7144 is_unpredictable = TRUE;
7145 }
7146
7147 func (stream, "]%s",
7148 WRITEBACK_BIT_SET ? "!" : "");
7149 }
7150 else
7151 {
7152 if (IMMEDIATE_BIT_SET)
7153 {
7154 /* Immediate Post-indexed. */
7155 /* PR 10924: Offset must be printed, even if it is zero. */
7156 func (stream, "], #%s%d",
7157 NEGATIVE_BIT_SET ? "-" : "", offset);
7158 if (NEGATIVE_BIT_SET)
7159 offset = -offset;
7160 value_in_comment = offset;
7161 }
7162 else
7163 {
7164 /* Register Post-indexed. */
7165 func (stream, "], %s%s",
7166 NEGATIVE_BIT_SET ? "-" : "",
7167 arm_regnames[given & 0xf]);
7168
7169 /* Writing back to the register that is the source/
7170 destination of the load/store is unpredictable. */
7171 if (! allow_unpredictable
7172 && (given & 0xf) == ((given >> 12) & 0xf))
7173 is_unpredictable = TRUE;
7174 }
7175
7176 if (! allow_unpredictable)
7177 {
7178 /* Writeback is automatically implied by post- addressing.
7179 Setting the W bit is unnecessary and ARM specify it as
7180 being unpredictable. */
7181 if (WRITEBACK_BIT_SET
7182 /* Specifying the PC register as the post-indexed
7183 registers is also unpredictable. */
7184 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
7185 is_unpredictable = TRUE;
7186 }
7187 }
7188 }
7189 break;
7190
7191 case 'b':
7192 {
7193 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
7194 info->print_address_func (disp * 4 + pc + 8, info);
7195 }
7196 break;
7197
7198 case 'c':
7199 if (((given >> 28) & 0xf) != 0xe)
7200 func (stream, "%s",
7201 arm_conditional [(given >> 28) & 0xf]);
7202 break;
7203
7204 case 'm':
7205 {
7206 int started = 0;
7207 int reg;
7208
7209 func (stream, "{");
7210 for (reg = 0; reg < 16; reg++)
7211 if ((given & (1 << reg)) != 0)
7212 {
7213 if (started)
7214 func (stream, ", ");
7215 started = 1;
7216 func (stream, "%s", arm_regnames[reg]);
7217 }
7218 func (stream, "}");
7219 if (! started)
7220 is_unpredictable = TRUE;
7221 }
7222 break;
7223
7224 case 'q':
7225 arm_decode_shift (given, func, stream, FALSE);
7226 break;
7227
7228 case 'o':
7229 if ((given & 0x02000000) != 0)
7230 {
7231 unsigned int rotate = (given & 0xf00) >> 7;
7232 unsigned int immed = (given & 0xff);
7233 unsigned int a, i;
7234
7235 a = (((immed << (32 - rotate))
7236 | (immed >> rotate)) & 0xffffffff);
7237 /* If there is another encoding with smaller rotate,
7238 the rotate should be specified directly. */
7239 for (i = 0; i < 32; i += 2)
7240 if ((a << i | a >> (32 - i)) <= 0xff)
7241 break;
7242
7243 if (i != rotate)
7244 func (stream, "#%d, %d", immed, rotate);
7245 else
7246 func (stream, "#%d", a);
7247 value_in_comment = a;
7248 }
7249 else
7250 arm_decode_shift (given, func, stream, TRUE);
7251 break;
7252
7253 case 'p':
7254 if ((given & 0x0000f000) == 0x0000f000)
7255 {
7256 arm_feature_set arm_ext_v6 =
7257 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
7258
7259 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
7260 mechanism for setting PSR flag bits. They are
7261 obsolete in V6 onwards. */
7262 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
7263 arm_ext_v6))
7264 func (stream, "p");
7265 else
7266 is_unpredictable = TRUE;
7267 }
7268 break;
7269
7270 case 't':
7271 if ((given & 0x01200000) == 0x00200000)
7272 func (stream, "t");
7273 break;
7274
7275 case 'A':
7276 {
7277 int offset = given & 0xff;
7278
7279 value_in_comment = offset * 4;
7280 if (NEGATIVE_BIT_SET)
7281 value_in_comment = - value_in_comment;
7282
7283 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
7284
7285 if (PRE_BIT_SET)
7286 {
7287 if (offset)
7288 func (stream, ", #%d]%s",
7289 (int) value_in_comment,
7290 WRITEBACK_BIT_SET ? "!" : "");
7291 else
7292 func (stream, "]");
7293 }
7294 else
7295 {
7296 func (stream, "]");
7297
7298 if (WRITEBACK_BIT_SET)
7299 {
7300 if (offset)
7301 func (stream, ", #%d", (int) value_in_comment);
7302 }
7303 else
7304 {
7305 func (stream, ", {%d}", (int) offset);
7306 value_in_comment = offset;
7307 }
7308 }
7309 }
7310 break;
7311
7312 case 'B':
7313 /* Print ARM V5 BLX(1) address: pc+25 bits. */
7314 {
7315 bfd_vma address;
7316 bfd_vma offset = 0;
7317
7318 if (! NEGATIVE_BIT_SET)
7319 /* Is signed, hi bits should be ones. */
7320 offset = (-1) ^ 0x00ffffff;
7321
7322 /* Offset is (SignExtend(offset field)<<2). */
7323 offset += given & 0x00ffffff;
7324 offset <<= 2;
7325 address = offset + pc + 8;
7326
7327 if (given & 0x01000000)
7328 /* H bit allows addressing to 2-byte boundaries. */
7329 address += 2;
7330
7331 info->print_address_func (address, info);
7332 }
7333 break;
7334
7335 case 'C':
7336 if ((given & 0x02000200) == 0x200)
7337 {
7338 const char * name;
7339 unsigned sysm = (given & 0x004f0000) >> 16;
7340
7341 sysm |= (given & 0x300) >> 4;
7342 name = banked_regname (sysm);
7343
7344 if (name != NULL)
7345 func (stream, "%s", name);
7346 else
7347 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
7348 }
7349 else
7350 {
7351 func (stream, "%cPSR_",
7352 (given & 0x00400000) ? 'S' : 'C');
7353 if (given & 0x80000)
7354 func (stream, "f");
7355 if (given & 0x40000)
7356 func (stream, "s");
7357 if (given & 0x20000)
7358 func (stream, "x");
7359 if (given & 0x10000)
7360 func (stream, "c");
7361 }
7362 break;
7363
7364 case 'U':
7365 if ((given & 0xf0) == 0x60)
7366 {
7367 switch (given & 0xf)
7368 {
7369 case 0xf: func (stream, "sy"); break;
7370 default:
7371 func (stream, "#%d", (int) given & 0xf);
7372 break;
7373 }
7374 }
7375 else
7376 {
7377 const char * opt = data_barrier_option (given & 0xf);
7378 if (opt != NULL)
7379 func (stream, "%s", opt);
7380 else
7381 func (stream, "#%d", (int) given & 0xf);
7382 }
7383 break;
7384
7385 case '0': case '1': case '2': case '3': case '4':
7386 case '5': case '6': case '7': case '8': case '9':
7387 {
7388 int width;
7389 unsigned long value;
7390
7391 c = arm_decode_bitfield (c, given, &value, &width);
7392
7393 switch (*c)
7394 {
7395 case 'R':
7396 if (value == 15)
7397 is_unpredictable = TRUE;
7398 /* Fall through. */
7399 case 'r':
7400 case 'T':
7401 /* We want register + 1 when decoding T. */
7402 if (*c == 'T')
7403 ++value;
7404
7405 if (c[1] == 'u')
7406 {
7407 /* Eat the 'u' character. */
7408 ++ c;
7409
7410 if (u_reg == value)
7411 is_unpredictable = TRUE;
7412 u_reg = value;
7413 }
7414 if (c[1] == 'U')
7415 {
7416 /* Eat the 'U' character. */
7417 ++ c;
7418
7419 if (U_reg == value)
7420 is_unpredictable = TRUE;
7421 U_reg = value;
7422 }
7423 func (stream, "%s", arm_regnames[value]);
7424 break;
7425 case 'd':
7426 func (stream, "%ld", value);
7427 value_in_comment = value;
7428 break;
7429 case 'b':
7430 func (stream, "%ld", value * 8);
7431 value_in_comment = value * 8;
7432 break;
7433 case 'W':
7434 func (stream, "%ld", value + 1);
7435 value_in_comment = value + 1;
7436 break;
7437 case 'x':
7438 func (stream, "0x%08lx", value);
7439
7440 /* Some SWI instructions have special
7441 meanings. */
7442 if ((given & 0x0fffffff) == 0x0FF00000)
7443 func (stream, "\t; IMB");
7444 else if ((given & 0x0fffffff) == 0x0FF00001)
7445 func (stream, "\t; IMBRange");
7446 break;
7447 case 'X':
7448 func (stream, "%01lx", value & 0xf);
7449 value_in_comment = value;
7450 break;
7451 case '`':
7452 c++;
7453 if (value == 0)
7454 func (stream, "%c", *c);
7455 break;
7456 case '\'':
7457 c++;
7458 if (value == ((1ul << width) - 1))
7459 func (stream, "%c", *c);
7460 break;
7461 case '?':
7462 func (stream, "%c", c[(1 << width) - (int) value]);
7463 c += 1 << width;
7464 break;
7465 default:
7466 abort ();
7467 }
7468 }
7469 break;
7470
7471 case 'e':
7472 {
7473 int imm;
7474
7475 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
7476 func (stream, "%d", imm);
7477 value_in_comment = imm;
7478 }
7479 break;
7480
7481 case 'E':
7482 /* LSB and WIDTH fields of BFI or BFC. The machine-
7483 language instruction encodes LSB and MSB. */
7484 {
7485 long msb = (given & 0x001f0000) >> 16;
7486 long lsb = (given & 0x00000f80) >> 7;
7487 long w = msb - lsb + 1;
7488
7489 if (w > 0)
7490 func (stream, "#%lu, #%lu", lsb, w);
7491 else
7492 func (stream, "(invalid: %lu:%lu)", lsb, msb);
7493 }
7494 break;
7495
7496 case 'R':
7497 /* Get the PSR/banked register name. */
7498 {
7499 const char * name;
7500 unsigned sysm = (given & 0x004f0000) >> 16;
7501
7502 sysm |= (given & 0x300) >> 4;
7503 name = banked_regname (sysm);
7504
7505 if (name != NULL)
7506 func (stream, "%s", name);
7507 else
7508 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
7509 }
7510 break;
7511
7512 case 'V':
7513 /* 16-bit unsigned immediate from a MOVT or MOVW
7514 instruction, encoded in bits 0:11 and 15:19. */
7515 {
7516 long hi = (given & 0x000f0000) >> 4;
7517 long lo = (given & 0x00000fff);
7518 long imm16 = hi | lo;
7519
7520 func (stream, "#%lu", imm16);
7521 value_in_comment = imm16;
7522 }
7523 break;
7524
7525 default:
7526 abort ();
7527 }
7528 }
7529 else
7530 func (stream, "%c", *c);
7531 }
7532
7533 if (value_in_comment > 32 || value_in_comment < -16)
7534 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
7535
7536 if (is_unpredictable)
7537 func (stream, UNPREDICTABLE_INSTRUCTION);
7538
7539 return;
7540 }
7541 }
7542 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
7543 return;
7544 }
7545
7546 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
7547
7548 static void
7549 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
7550 {
7551 const struct opcode16 *insn;
7552 void *stream = info->stream;
7553 fprintf_ftype func = info->fprintf_func;
7554
7555 for (insn = thumb_opcodes; insn->assembler; insn++)
7556 if ((given & insn->mask) == insn->value)
7557 {
7558 signed long value_in_comment = 0;
7559 const char *c = insn->assembler;
7560
7561 for (; *c; c++)
7562 {
7563 int domaskpc = 0;
7564 int domasklr = 0;
7565
7566 if (*c != '%')
7567 {
7568 func (stream, "%c", *c);
7569 continue;
7570 }
7571
7572 switch (*++c)
7573 {
7574 case '%':
7575 func (stream, "%%");
7576 break;
7577
7578 case 'c':
7579 if (ifthen_state)
7580 func (stream, "%s", arm_conditional[IFTHEN_COND]);
7581 break;
7582
7583 case 'C':
7584 if (ifthen_state)
7585 func (stream, "%s", arm_conditional[IFTHEN_COND]);
7586 else
7587 func (stream, "s");
7588 break;
7589
7590 case 'I':
7591 {
7592 unsigned int tmp;
7593
7594 ifthen_next_state = given & 0xff;
7595 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
7596 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
7597 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
7598 }
7599 break;
7600
7601 case 'x':
7602 if (ifthen_next_state)
7603 func (stream, "\t; unpredictable branch in IT block\n");
7604 break;
7605
7606 case 'X':
7607 if (ifthen_state)
7608 func (stream, "\t; unpredictable <IT:%s>",
7609 arm_conditional[IFTHEN_COND]);
7610 break;
7611
7612 case 'S':
7613 {
7614 long reg;
7615
7616 reg = (given >> 3) & 0x7;
7617 if (given & (1 << 6))
7618 reg += 8;
7619
7620 func (stream, "%s", arm_regnames[reg]);
7621 }
7622 break;
7623
7624 case 'D':
7625 {
7626 long reg;
7627
7628 reg = given & 0x7;
7629 if (given & (1 << 7))
7630 reg += 8;
7631
7632 func (stream, "%s", arm_regnames[reg]);
7633 }
7634 break;
7635
7636 case 'N':
7637 if (given & (1 << 8))
7638 domasklr = 1;
7639 /* Fall through. */
7640 case 'O':
7641 if (*c == 'O' && (given & (1 << 8)))
7642 domaskpc = 1;
7643 /* Fall through. */
7644 case 'M':
7645 {
7646 int started = 0;
7647 int reg;
7648
7649 func (stream, "{");
7650
7651 /* It would be nice if we could spot
7652 ranges, and generate the rS-rE format: */
7653 for (reg = 0; (reg < 8); reg++)
7654 if ((given & (1 << reg)) != 0)
7655 {
7656 if (started)
7657 func (stream, ", ");
7658 started = 1;
7659 func (stream, "%s", arm_regnames[reg]);
7660 }
7661
7662 if (domasklr)
7663 {
7664 if (started)
7665 func (stream, ", ");
7666 started = 1;
7667 func (stream, "%s", arm_regnames[14] /* "lr" */);
7668 }
7669
7670 if (domaskpc)
7671 {
7672 if (started)
7673 func (stream, ", ");
7674 func (stream, "%s", arm_regnames[15] /* "pc" */);
7675 }
7676
7677 func (stream, "}");
7678 }
7679 break;
7680
7681 case 'W':
7682 /* Print writeback indicator for a LDMIA. We are doing a
7683 writeback if the base register is not in the register
7684 mask. */
7685 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
7686 func (stream, "!");
7687 break;
7688
7689 case 'b':
7690 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
7691 {
7692 bfd_vma address = (pc + 4
7693 + ((given & 0x00f8) >> 2)
7694 + ((given & 0x0200) >> 3));
7695 info->print_address_func (address, info);
7696 }
7697 break;
7698
7699 case 's':
7700 /* Right shift immediate -- bits 6..10; 1-31 print
7701 as themselves, 0 prints as 32. */
7702 {
7703 long imm = (given & 0x07c0) >> 6;
7704 if (imm == 0)
7705 imm = 32;
7706 func (stream, "#%ld", imm);
7707 }
7708 break;
7709
7710 case '0': case '1': case '2': case '3': case '4':
7711 case '5': case '6': case '7': case '8': case '9':
7712 {
7713 int bitstart = *c++ - '0';
7714 int bitend = 0;
7715
7716 while (*c >= '0' && *c <= '9')
7717 bitstart = (bitstart * 10) + *c++ - '0';
7718
7719 switch (*c)
7720 {
7721 case '-':
7722 {
7723 bfd_vma reg;
7724
7725 c++;
7726 while (*c >= '0' && *c <= '9')
7727 bitend = (bitend * 10) + *c++ - '0';
7728 if (!bitend)
7729 abort ();
7730 reg = given >> bitstart;
7731 reg &= (2 << (bitend - bitstart)) - 1;
7732
7733 switch (*c)
7734 {
7735 case 'r':
7736 func (stream, "%s", arm_regnames[reg]);
7737 break;
7738
7739 case 'd':
7740 func (stream, "%ld", (long) reg);
7741 value_in_comment = reg;
7742 break;
7743
7744 case 'H':
7745 func (stream, "%ld", (long) (reg << 1));
7746 value_in_comment = reg << 1;
7747 break;
7748
7749 case 'W':
7750 func (stream, "%ld", (long) (reg << 2));
7751 value_in_comment = reg << 2;
7752 break;
7753
7754 case 'a':
7755 /* PC-relative address -- the bottom two
7756 bits of the address are dropped
7757 before the calculation. */
7758 info->print_address_func
7759 (((pc + 4) & ~3) + (reg << 2), info);
7760 value_in_comment = 0;
7761 break;
7762
7763 case 'x':
7764 func (stream, "0x%04lx", (long) reg);
7765 break;
7766
7767 case 'B':
7768 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
7769 info->print_address_func (reg * 2 + pc + 4, info);
7770 value_in_comment = 0;
7771 break;
7772
7773 case 'c':
7774 func (stream, "%s", arm_conditional [reg]);
7775 break;
7776
7777 default:
7778 abort ();
7779 }
7780 }
7781 break;
7782
7783 case '\'':
7784 c++;
7785 if ((given & (1 << bitstart)) != 0)
7786 func (stream, "%c", *c);
7787 break;
7788
7789 case '?':
7790 ++c;
7791 if ((given & (1 << bitstart)) != 0)
7792 func (stream, "%c", *c++);
7793 else
7794 func (stream, "%c", *++c);
7795 break;
7796
7797 default:
7798 abort ();
7799 }
7800 }
7801 break;
7802
7803 default:
7804 abort ();
7805 }
7806 }
7807
7808 if (value_in_comment > 32 || value_in_comment < -16)
7809 func (stream, "\t; 0x%lx", value_in_comment);
7810 return;
7811 }
7812
7813 /* No match. */
7814 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
7815 return;
7816 }
7817
7818 /* Return the name of an V7M special register. */
7819
7820 static const char *
7821 psr_name (int regno)
7822 {
7823 switch (regno)
7824 {
7825 case 0x0: return "APSR";
7826 case 0x1: return "IAPSR";
7827 case 0x2: return "EAPSR";
7828 case 0x3: return "PSR";
7829 case 0x5: return "IPSR";
7830 case 0x6: return "EPSR";
7831 case 0x7: return "IEPSR";
7832 case 0x8: return "MSP";
7833 case 0x9: return "PSP";
7834 case 0xa: return "MSPLIM";
7835 case 0xb: return "PSPLIM";
7836 case 0x10: return "PRIMASK";
7837 case 0x11: return "BASEPRI";
7838 case 0x12: return "BASEPRI_MAX";
7839 case 0x13: return "FAULTMASK";
7840 case 0x14: return "CONTROL";
7841 case 0x88: return "MSP_NS";
7842 case 0x89: return "PSP_NS";
7843 case 0x8a: return "MSPLIM_NS";
7844 case 0x8b: return "PSPLIM_NS";
7845 case 0x90: return "PRIMASK_NS";
7846 case 0x91: return "BASEPRI_NS";
7847 case 0x93: return "FAULTMASK_NS";
7848 case 0x94: return "CONTROL_NS";
7849 case 0x98: return "SP_NS";
7850 default: return "<unknown>";
7851 }
7852 }
7853
7854 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
7855
7856 static void
7857 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
7858 {
7859 const struct opcode32 *insn;
7860 void *stream = info->stream;
7861 fprintf_ftype func = info->fprintf_func;
7862 bfd_boolean is_mve = is_mve_architecture (info);
7863
7864 if (print_insn_coprocessor (pc, info, given, TRUE))
7865 return;
7866
7867 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
7868 return;
7869
7870 if (is_mve && print_insn_mve (info, given))
7871 return;
7872
7873 for (insn = thumb32_opcodes; insn->assembler; insn++)
7874 if ((given & insn->mask) == insn->value)
7875 {
7876 bfd_boolean is_clrm = FALSE;
7877 bfd_boolean is_unpredictable = FALSE;
7878 signed long value_in_comment = 0;
7879 const char *c = insn->assembler;
7880
7881 for (; *c; c++)
7882 {
7883 if (*c != '%')
7884 {
7885 func (stream, "%c", *c);
7886 continue;
7887 }
7888
7889 switch (*++c)
7890 {
7891 case '%':
7892 func (stream, "%%");
7893 break;
7894
7895 case 'c':
7896 if (ifthen_state)
7897 func (stream, "%s", arm_conditional[IFTHEN_COND]);
7898 break;
7899
7900 case 'x':
7901 if (ifthen_next_state)
7902 func (stream, "\t; unpredictable branch in IT block\n");
7903 break;
7904
7905 case 'X':
7906 if (ifthen_state)
7907 func (stream, "\t; unpredictable <IT:%s>",
7908 arm_conditional[IFTHEN_COND]);
7909 break;
7910
7911 case 'I':
7912 {
7913 unsigned int imm12 = 0;
7914
7915 imm12 |= (given & 0x000000ffu);
7916 imm12 |= (given & 0x00007000u) >> 4;
7917 imm12 |= (given & 0x04000000u) >> 15;
7918 func (stream, "#%u", imm12);
7919 value_in_comment = imm12;
7920 }
7921 break;
7922
7923 case 'M':
7924 {
7925 unsigned int bits = 0, imm, imm8, mod;
7926
7927 bits |= (given & 0x000000ffu);
7928 bits |= (given & 0x00007000u) >> 4;
7929 bits |= (given & 0x04000000u) >> 15;
7930 imm8 = (bits & 0x0ff);
7931 mod = (bits & 0xf00) >> 8;
7932 switch (mod)
7933 {
7934 case 0: imm = imm8; break;
7935 case 1: imm = ((imm8 << 16) | imm8); break;
7936 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
7937 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
7938 default:
7939 mod = (bits & 0xf80) >> 7;
7940 imm8 = (bits & 0x07f) | 0x80;
7941 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
7942 }
7943 func (stream, "#%u", imm);
7944 value_in_comment = imm;
7945 }
7946 break;
7947
7948 case 'J':
7949 {
7950 unsigned int imm = 0;
7951
7952 imm |= (given & 0x000000ffu);
7953 imm |= (given & 0x00007000u) >> 4;
7954 imm |= (given & 0x04000000u) >> 15;
7955 imm |= (given & 0x000f0000u) >> 4;
7956 func (stream, "#%u", imm);
7957 value_in_comment = imm;
7958 }
7959 break;
7960
7961 case 'K':
7962 {
7963 unsigned int imm = 0;
7964
7965 imm |= (given & 0x000f0000u) >> 16;
7966 imm |= (given & 0x00000ff0u) >> 0;
7967 imm |= (given & 0x0000000fu) << 12;
7968 func (stream, "#%u", imm);
7969 value_in_comment = imm;
7970 }
7971 break;
7972
7973 case 'H':
7974 {
7975 unsigned int imm = 0;
7976
7977 imm |= (given & 0x000f0000u) >> 4;
7978 imm |= (given & 0x00000fffu) >> 0;
7979 func (stream, "#%u", imm);
7980 value_in_comment = imm;
7981 }
7982 break;
7983
7984 case 'V':
7985 {
7986 unsigned int imm = 0;
7987
7988 imm |= (given & 0x00000fffu);
7989 imm |= (given & 0x000f0000u) >> 4;
7990 func (stream, "#%u", imm);
7991 value_in_comment = imm;
7992 }
7993 break;
7994
7995 case 'S':
7996 {
7997 unsigned int reg = (given & 0x0000000fu);
7998 unsigned int stp = (given & 0x00000030u) >> 4;
7999 unsigned int imm = 0;
8000 imm |= (given & 0x000000c0u) >> 6;
8001 imm |= (given & 0x00007000u) >> 10;
8002
8003 func (stream, "%s", arm_regnames[reg]);
8004 switch (stp)
8005 {
8006 case 0:
8007 if (imm > 0)
8008 func (stream, ", lsl #%u", imm);
8009 break;
8010
8011 case 1:
8012 if (imm == 0)
8013 imm = 32;
8014 func (stream, ", lsr #%u", imm);
8015 break;
8016
8017 case 2:
8018 if (imm == 0)
8019 imm = 32;
8020 func (stream, ", asr #%u", imm);
8021 break;
8022
8023 case 3:
8024 if (imm == 0)
8025 func (stream, ", rrx");
8026 else
8027 func (stream, ", ror #%u", imm);
8028 }
8029 }
8030 break;
8031
8032 case 'a':
8033 {
8034 unsigned int Rn = (given & 0x000f0000) >> 16;
8035 unsigned int U = ! NEGATIVE_BIT_SET;
8036 unsigned int op = (given & 0x00000f00) >> 8;
8037 unsigned int i12 = (given & 0x00000fff);
8038 unsigned int i8 = (given & 0x000000ff);
8039 bfd_boolean writeback = FALSE, postind = FALSE;
8040 bfd_vma offset = 0;
8041
8042 func (stream, "[%s", arm_regnames[Rn]);
8043 if (U) /* 12-bit positive immediate offset. */
8044 {
8045 offset = i12;
8046 if (Rn != 15)
8047 value_in_comment = offset;
8048 }
8049 else if (Rn == 15) /* 12-bit negative immediate offset. */
8050 offset = - (int) i12;
8051 else if (op == 0x0) /* Shifted register offset. */
8052 {
8053 unsigned int Rm = (i8 & 0x0f);
8054 unsigned int sh = (i8 & 0x30) >> 4;
8055
8056 func (stream, ", %s", arm_regnames[Rm]);
8057 if (sh)
8058 func (stream, ", lsl #%u", sh);
8059 func (stream, "]");
8060 break;
8061 }
8062 else switch (op)
8063 {
8064 case 0xE: /* 8-bit positive immediate offset. */
8065 offset = i8;
8066 break;
8067
8068 case 0xC: /* 8-bit negative immediate offset. */
8069 offset = -i8;
8070 break;
8071
8072 case 0xF: /* 8-bit + preindex with wb. */
8073 offset = i8;
8074 writeback = TRUE;
8075 break;
8076
8077 case 0xD: /* 8-bit - preindex with wb. */
8078 offset = -i8;
8079 writeback = TRUE;
8080 break;
8081
8082 case 0xB: /* 8-bit + postindex. */
8083 offset = i8;
8084 postind = TRUE;
8085 break;
8086
8087 case 0x9: /* 8-bit - postindex. */
8088 offset = -i8;
8089 postind = TRUE;
8090 break;
8091
8092 default:
8093 func (stream, ", <undefined>]");
8094 goto skip;
8095 }
8096
8097 if (postind)
8098 func (stream, "], #%d", (int) offset);
8099 else
8100 {
8101 if (offset)
8102 func (stream, ", #%d", (int) offset);
8103 func (stream, writeback ? "]!" : "]");
8104 }
8105
8106 if (Rn == 15)
8107 {
8108 func (stream, "\t; ");
8109 info->print_address_func (((pc + 4) & ~3) + offset, info);
8110 }
8111 }
8112 skip:
8113 break;
8114
8115 case 'A':
8116 {
8117 unsigned int U = ! NEGATIVE_BIT_SET;
8118 unsigned int W = WRITEBACK_BIT_SET;
8119 unsigned int Rn = (given & 0x000f0000) >> 16;
8120 unsigned int off = (given & 0x000000ff);
8121
8122 func (stream, "[%s", arm_regnames[Rn]);
8123
8124 if (PRE_BIT_SET)
8125 {
8126 if (off || !U)
8127 {
8128 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
8129 value_in_comment = off * 4 * (U ? 1 : -1);
8130 }
8131 func (stream, "]");
8132 if (W)
8133 func (stream, "!");
8134 }
8135 else
8136 {
8137 func (stream, "], ");
8138 if (W)
8139 {
8140 func (stream, "#%c%u", U ? '+' : '-', off * 4);
8141 value_in_comment = off * 4 * (U ? 1 : -1);
8142 }
8143 else
8144 {
8145 func (stream, "{%u}", off);
8146 value_in_comment = off;
8147 }
8148 }
8149 }
8150 break;
8151
8152 case 'w':
8153 {
8154 unsigned int Sbit = (given & 0x01000000) >> 24;
8155 unsigned int type = (given & 0x00600000) >> 21;
8156
8157 switch (type)
8158 {
8159 case 0: func (stream, Sbit ? "sb" : "b"); break;
8160 case 1: func (stream, Sbit ? "sh" : "h"); break;
8161 case 2:
8162 if (Sbit)
8163 func (stream, "??");
8164 break;
8165 case 3:
8166 func (stream, "??");
8167 break;
8168 }
8169 }
8170 break;
8171
8172 case 'n':
8173 is_clrm = TRUE;
8174 /* Fall through. */
8175 case 'm':
8176 {
8177 int started = 0;
8178 int reg;
8179
8180 func (stream, "{");
8181 for (reg = 0; reg < 16; reg++)
8182 if ((given & (1 << reg)) != 0)
8183 {
8184 if (started)
8185 func (stream, ", ");
8186 started = 1;
8187 if (is_clrm && reg == 13)
8188 func (stream, "(invalid: %s)", arm_regnames[reg]);
8189 else if (is_clrm && reg == 15)
8190 func (stream, "%s", "APSR");
8191 else
8192 func (stream, "%s", arm_regnames[reg]);
8193 }
8194 func (stream, "}");
8195 }
8196 break;
8197
8198 case 'E':
8199 {
8200 unsigned int msb = (given & 0x0000001f);
8201 unsigned int lsb = 0;
8202
8203 lsb |= (given & 0x000000c0u) >> 6;
8204 lsb |= (given & 0x00007000u) >> 10;
8205 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
8206 }
8207 break;
8208
8209 case 'F':
8210 {
8211 unsigned int width = (given & 0x0000001f) + 1;
8212 unsigned int lsb = 0;
8213
8214 lsb |= (given & 0x000000c0u) >> 6;
8215 lsb |= (given & 0x00007000u) >> 10;
8216 func (stream, "#%u, #%u", lsb, width);
8217 }
8218 break;
8219
8220 case 'G':
8221 {
8222 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
8223 func (stream, "%x", boff);
8224 }
8225 break;
8226
8227 case 'W':
8228 {
8229 unsigned int immA = (given & 0x001f0000u) >> 16;
8230 unsigned int immB = (given & 0x000007feu) >> 1;
8231 unsigned int immC = (given & 0x00000800u) >> 11;
8232 bfd_vma offset = 0;
8233
8234 offset |= immA << 12;
8235 offset |= immB << 2;
8236 offset |= immC << 1;
8237 /* Sign extend. */
8238 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
8239
8240 info->print_address_func (pc + 4 + offset, info);
8241 }
8242 break;
8243
8244 case 'Y':
8245 {
8246 unsigned int immA = (given & 0x007f0000u) >> 16;
8247 unsigned int immB = (given & 0x000007feu) >> 1;
8248 unsigned int immC = (given & 0x00000800u) >> 11;
8249 bfd_vma offset = 0;
8250
8251 offset |= immA << 12;
8252 offset |= immB << 2;
8253 offset |= immC << 1;
8254 /* Sign extend. */
8255 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
8256
8257 info->print_address_func (pc + 4 + offset, info);
8258 }
8259 break;
8260
8261 case 'Z':
8262 {
8263 unsigned int immA = (given & 0x00010000u) >> 16;
8264 unsigned int immB = (given & 0x000007feu) >> 1;
8265 unsigned int immC = (given & 0x00000800u) >> 11;
8266 bfd_vma offset = 0;
8267
8268 offset |= immA << 12;
8269 offset |= immB << 2;
8270 offset |= immC << 1;
8271 /* Sign extend. */
8272 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
8273
8274 info->print_address_func (pc + 4 + offset, info);
8275
8276 unsigned int T = (given & 0x00020000u) >> 17;
8277 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
8278 unsigned int boffset = (T == 1) ? 4 : 2;
8279 func (stream, ", ");
8280 func (stream, "%x", endoffset + boffset);
8281 }
8282 break;
8283
8284 case 'Q':
8285 {
8286 unsigned int immh = (given & 0x000007feu) >> 1;
8287 unsigned int imml = (given & 0x00000800u) >> 11;
8288 bfd_vma imm32 = 0;
8289
8290 imm32 |= immh << 2;
8291 imm32 |= imml << 1;
8292
8293 info->print_address_func (pc + 4 + imm32, info);
8294 }
8295 break;
8296
8297 case 'P':
8298 {
8299 unsigned int immh = (given & 0x000007feu) >> 1;
8300 unsigned int imml = (given & 0x00000800u) >> 11;
8301 bfd_vma imm32 = 0;
8302
8303 imm32 |= immh << 2;
8304 imm32 |= imml << 1;
8305
8306 info->print_address_func (pc + 4 - imm32, info);
8307 }
8308 break;
8309
8310 case 'b':
8311 {
8312 unsigned int S = (given & 0x04000000u) >> 26;
8313 unsigned int J1 = (given & 0x00002000u) >> 13;
8314 unsigned int J2 = (given & 0x00000800u) >> 11;
8315 bfd_vma offset = 0;
8316
8317 offset |= !S << 20;
8318 offset |= J2 << 19;
8319 offset |= J1 << 18;
8320 offset |= (given & 0x003f0000) >> 4;
8321 offset |= (given & 0x000007ff) << 1;
8322 offset -= (1 << 20);
8323
8324 info->print_address_func (pc + 4 + offset, info);
8325 }
8326 break;
8327
8328 case 'B':
8329 {
8330 unsigned int S = (given & 0x04000000u) >> 26;
8331 unsigned int I1 = (given & 0x00002000u) >> 13;
8332 unsigned int I2 = (given & 0x00000800u) >> 11;
8333 bfd_vma offset = 0;
8334
8335 offset |= !S << 24;
8336 offset |= !(I1 ^ S) << 23;
8337 offset |= !(I2 ^ S) << 22;
8338 offset |= (given & 0x03ff0000u) >> 4;
8339 offset |= (given & 0x000007ffu) << 1;
8340 offset -= (1 << 24);
8341 offset += pc + 4;
8342
8343 /* BLX target addresses are always word aligned. */
8344 if ((given & 0x00001000u) == 0)
8345 offset &= ~2u;
8346
8347 info->print_address_func (offset, info);
8348 }
8349 break;
8350
8351 case 's':
8352 {
8353 unsigned int shift = 0;
8354
8355 shift |= (given & 0x000000c0u) >> 6;
8356 shift |= (given & 0x00007000u) >> 10;
8357 if (WRITEBACK_BIT_SET)
8358 func (stream, ", asr #%u", shift);
8359 else if (shift)
8360 func (stream, ", lsl #%u", shift);
8361 /* else print nothing - lsl #0 */
8362 }
8363 break;
8364
8365 case 'R':
8366 {
8367 unsigned int rot = (given & 0x00000030) >> 4;
8368
8369 if (rot)
8370 func (stream, ", ror #%u", rot * 8);
8371 }
8372 break;
8373
8374 case 'U':
8375 if ((given & 0xf0) == 0x60)
8376 {
8377 switch (given & 0xf)
8378 {
8379 case 0xf: func (stream, "sy"); break;
8380 default:
8381 func (stream, "#%d", (int) given & 0xf);
8382 break;
8383 }
8384 }
8385 else
8386 {
8387 const char * opt = data_barrier_option (given & 0xf);
8388 if (opt != NULL)
8389 func (stream, "%s", opt);
8390 else
8391 func (stream, "#%d", (int) given & 0xf);
8392 }
8393 break;
8394
8395 case 'C':
8396 if ((given & 0xff) == 0)
8397 {
8398 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
8399 if (given & 0x800)
8400 func (stream, "f");
8401 if (given & 0x400)
8402 func (stream, "s");
8403 if (given & 0x200)
8404 func (stream, "x");
8405 if (given & 0x100)
8406 func (stream, "c");
8407 }
8408 else if ((given & 0x20) == 0x20)
8409 {
8410 char const* name;
8411 unsigned sysm = (given & 0xf00) >> 8;
8412
8413 sysm |= (given & 0x30);
8414 sysm |= (given & 0x00100000) >> 14;
8415 name = banked_regname (sysm);
8416
8417 if (name != NULL)
8418 func (stream, "%s", name);
8419 else
8420 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
8421 }
8422 else
8423 {
8424 func (stream, "%s", psr_name (given & 0xff));
8425 }
8426 break;
8427
8428 case 'D':
8429 if (((given & 0xff) == 0)
8430 || ((given & 0x20) == 0x20))
8431 {
8432 char const* name;
8433 unsigned sm = (given & 0xf0000) >> 16;
8434
8435 sm |= (given & 0x30);
8436 sm |= (given & 0x00100000) >> 14;
8437 name = banked_regname (sm);
8438
8439 if (name != NULL)
8440 func (stream, "%s", name);
8441 else
8442 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
8443 }
8444 else
8445 func (stream, "%s", psr_name (given & 0xff));
8446 break;
8447
8448 case '0': case '1': case '2': case '3': case '4':
8449 case '5': case '6': case '7': case '8': case '9':
8450 {
8451 int width;
8452 unsigned long val;
8453
8454 c = arm_decode_bitfield (c, given, &val, &width);
8455
8456 switch (*c)
8457 {
8458 case 'd':
8459 func (stream, "%lu", val);
8460 value_in_comment = val;
8461 break;
8462
8463 case 'D':
8464 func (stream, "%lu", val + 1);
8465 value_in_comment = val + 1;
8466 break;
8467
8468 case 'W':
8469 func (stream, "%lu", val * 4);
8470 value_in_comment = val * 4;
8471 break;
8472
8473 case 'S':
8474 if (val == 13)
8475 is_unpredictable = TRUE;
8476 /* Fall through. */
8477 case 'R':
8478 if (val == 15)
8479 is_unpredictable = TRUE;
8480 /* Fall through. */
8481 case 'r':
8482 func (stream, "%s", arm_regnames[val]);
8483 break;
8484
8485 case 'c':
8486 func (stream, "%s", arm_conditional[val]);
8487 break;
8488
8489 case '\'':
8490 c++;
8491 if (val == ((1ul << width) - 1))
8492 func (stream, "%c", *c);
8493 break;
8494
8495 case '`':
8496 c++;
8497 if (val == 0)
8498 func (stream, "%c", *c);
8499 break;
8500
8501 case '?':
8502 func (stream, "%c", c[(1 << width) - (int) val]);
8503 c += 1 << width;
8504 break;
8505
8506 case 'x':
8507 func (stream, "0x%lx", val & 0xffffffffUL);
8508 break;
8509
8510 default:
8511 abort ();
8512 }
8513 }
8514 break;
8515
8516 case 'L':
8517 /* PR binutils/12534
8518 If we have a PC relative offset in an LDRD or STRD
8519 instructions then display the decoded address. */
8520 if (((given >> 16) & 0xf) == 0xf)
8521 {
8522 bfd_vma offset = (given & 0xff) * 4;
8523
8524 if ((given & (1 << 23)) == 0)
8525 offset = - offset;
8526 func (stream, "\t; ");
8527 info->print_address_func ((pc & ~3) + 4 + offset, info);
8528 }
8529 break;
8530
8531 default:
8532 abort ();
8533 }
8534 }
8535
8536 if (value_in_comment > 32 || value_in_comment < -16)
8537 func (stream, "\t; 0x%lx", value_in_comment);
8538
8539 if (is_unpredictable)
8540 func (stream, UNPREDICTABLE_INSTRUCTION);
8541
8542 return;
8543 }
8544
8545 /* No match. */
8546 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
8547 return;
8548 }
8549
8550 /* Print data bytes on INFO->STREAM. */
8551
8552 static void
8553 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
8554 struct disassemble_info *info,
8555 long given)
8556 {
8557 switch (info->bytes_per_chunk)
8558 {
8559 case 1:
8560 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
8561 break;
8562 case 2:
8563 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
8564 break;
8565 case 4:
8566 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
8567 break;
8568 default:
8569 abort ();
8570 }
8571 }
8572
8573 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
8574 being displayed in symbol relative addresses.
8575
8576 Also disallow private symbol, with __tagsym$$ prefix,
8577 from ARM RVCT toolchain being displayed. */
8578
8579 bfd_boolean
8580 arm_symbol_is_valid (asymbol * sym,
8581 struct disassemble_info * info ATTRIBUTE_UNUSED)
8582 {
8583 const char * name;
8584
8585 if (sym == NULL)
8586 return FALSE;
8587
8588 name = bfd_asymbol_name (sym);
8589
8590 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
8591 }
8592
8593 /* Parse the string of disassembler options. */
8594
8595 static void
8596 parse_arm_disassembler_options (const char *options)
8597 {
8598 const char *opt;
8599
8600 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
8601 {
8602 if (CONST_STRNEQ (opt, "reg-names-"))
8603 {
8604 unsigned int i;
8605 for (i = 0; i < NUM_ARM_OPTIONS; i++)
8606 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
8607 {
8608 regname_selected = i;
8609 break;
8610 }
8611
8612 if (i >= NUM_ARM_OPTIONS)
8613 /* xgettext: c-format */
8614 opcodes_error_handler (_("unrecognised register name set: %s"),
8615 opt);
8616 }
8617 else if (CONST_STRNEQ (opt, "force-thumb"))
8618 force_thumb = 1;
8619 else if (CONST_STRNEQ (opt, "no-force-thumb"))
8620 force_thumb = 0;
8621 else
8622 /* xgettext: c-format */
8623 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
8624 }
8625
8626 return;
8627 }
8628
8629 static bfd_boolean
8630 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
8631 enum map_type *map_symbol);
8632
8633 /* Search back through the insn stream to determine if this instruction is
8634 conditionally executed. */
8635
8636 static void
8637 find_ifthen_state (bfd_vma pc,
8638 struct disassemble_info *info,
8639 bfd_boolean little)
8640 {
8641 unsigned char b[2];
8642 unsigned int insn;
8643 int status;
8644 /* COUNT is twice the number of instructions seen. It will be odd if we
8645 just crossed an instruction boundary. */
8646 int count;
8647 int it_count;
8648 unsigned int seen_it;
8649 bfd_vma addr;
8650
8651 ifthen_address = pc;
8652 ifthen_state = 0;
8653
8654 addr = pc;
8655 count = 1;
8656 it_count = 0;
8657 seen_it = 0;
8658 /* Scan backwards looking for IT instructions, keeping track of where
8659 instruction boundaries are. We don't know if something is actually an
8660 IT instruction until we find a definite instruction boundary. */
8661 for (;;)
8662 {
8663 if (addr == 0 || info->symbol_at_address_func (addr, info))
8664 {
8665 /* A symbol must be on an instruction boundary, and will not
8666 be within an IT block. */
8667 if (seen_it && (count & 1))
8668 break;
8669
8670 return;
8671 }
8672 addr -= 2;
8673 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
8674 if (status)
8675 return;
8676
8677 if (little)
8678 insn = (b[0]) | (b[1] << 8);
8679 else
8680 insn = (b[1]) | (b[0] << 8);
8681 if (seen_it)
8682 {
8683 if ((insn & 0xf800) < 0xe800)
8684 {
8685 /* Addr + 2 is an instruction boundary. See if this matches
8686 the expected boundary based on the position of the last
8687 IT candidate. */
8688 if (count & 1)
8689 break;
8690 seen_it = 0;
8691 }
8692 }
8693 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
8694 {
8695 enum map_type type = MAP_ARM;
8696 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
8697
8698 if (!found || (found && type == MAP_THUMB))
8699 {
8700 /* This could be an IT instruction. */
8701 seen_it = insn;
8702 it_count = count >> 1;
8703 }
8704 }
8705 if ((insn & 0xf800) >= 0xe800)
8706 count++;
8707 else
8708 count = (count + 2) | 1;
8709 /* IT blocks contain at most 4 instructions. */
8710 if (count >= 8 && !seen_it)
8711 return;
8712 }
8713 /* We found an IT instruction. */
8714 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
8715 if ((ifthen_state & 0xf) == 0)
8716 ifthen_state = 0;
8717 }
8718
8719 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
8720 mapping symbol. */
8721
8722 static int
8723 is_mapping_symbol (struct disassemble_info *info, int n,
8724 enum map_type *map_type)
8725 {
8726 const char *name;
8727
8728 name = bfd_asymbol_name (info->symtab[n]);
8729 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
8730 && (name[2] == 0 || name[2] == '.'))
8731 {
8732 *map_type = ((name[1] == 'a') ? MAP_ARM
8733 : (name[1] == 't') ? MAP_THUMB
8734 : MAP_DATA);
8735 return TRUE;
8736 }
8737
8738 return FALSE;
8739 }
8740
8741 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
8742 Returns nonzero if *MAP_TYPE was set. */
8743
8744 static int
8745 get_map_sym_type (struct disassemble_info *info,
8746 int n,
8747 enum map_type *map_type)
8748 {
8749 /* If the symbol is in a different section, ignore it. */
8750 if (info->section != NULL && info->section != info->symtab[n]->section)
8751 return FALSE;
8752
8753 return is_mapping_symbol (info, n, map_type);
8754 }
8755
8756 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
8757 Returns nonzero if *MAP_TYPE was set. */
8758
8759 static int
8760 get_sym_code_type (struct disassemble_info *info,
8761 int n,
8762 enum map_type *map_type)
8763 {
8764 elf_symbol_type *es;
8765 unsigned int type;
8766
8767 /* If the symbol is in a different section, ignore it. */
8768 if (info->section != NULL && info->section != info->symtab[n]->section)
8769 return FALSE;
8770
8771 es = *(elf_symbol_type **)(info->symtab + n);
8772 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
8773
8774 /* If the symbol has function type then use that. */
8775 if (type == STT_FUNC || type == STT_GNU_IFUNC)
8776 {
8777 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
8778 == ST_BRANCH_TO_THUMB)
8779 *map_type = MAP_THUMB;
8780 else
8781 *map_type = MAP_ARM;
8782 return TRUE;
8783 }
8784
8785 return FALSE;
8786 }
8787
8788 /* Search the mapping symbol state for instruction at pc. This is only
8789 applicable for elf target.
8790
8791 There is an assumption Here, info->private_data contains the correct AND
8792 up-to-date information about current scan process. The information will be
8793 used to speed this search process.
8794
8795 Return TRUE if the mapping state can be determined, and map_symbol
8796 will be updated accordingly. Otherwise, return FALSE. */
8797
8798 static bfd_boolean
8799 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
8800 enum map_type *map_symbol)
8801 {
8802 bfd_vma addr, section_vma = 0;
8803 int n, last_sym = -1;
8804 bfd_boolean found = FALSE;
8805 bfd_boolean can_use_search_opt_p = FALSE;
8806
8807 /* Default to DATA. A text section is required by the ABI to contain an
8808 INSN mapping symbol at the start. A data section has no such
8809 requirement, hence if no mapping symbol is found the section must
8810 contain only data. This however isn't very useful if the user has
8811 fully stripped the binaries. If this is the case use the section
8812 attributes to determine the default. If we have no section default to
8813 INSN as well, as we may be disassembling some raw bytes on a baremetal
8814 HEX file or similar. */
8815 enum map_type type = MAP_DATA;
8816 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
8817 type = MAP_ARM;
8818 struct arm_private_data *private_data;
8819
8820 if (info->private_data == NULL
8821 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
8822 return FALSE;
8823
8824 private_data = info->private_data;
8825
8826 /* First, look for mapping symbols. */
8827 if (info->symtab_size != 0)
8828 {
8829 if (pc <= private_data->last_mapping_addr)
8830 private_data->last_mapping_sym = -1;
8831
8832 /* Start scanning at the start of the function, or wherever
8833 we finished last time. */
8834 n = info->symtab_pos + 1;
8835
8836 /* If the last stop offset is different from the current one it means we
8837 are disassembling a different glob of bytes. As such the optimization
8838 would not be safe and we should start over. */
8839 can_use_search_opt_p
8840 = private_data->last_mapping_sym >= 0
8841 && info->stop_offset == private_data->last_stop_offset;
8842
8843 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
8844 n = private_data->last_mapping_sym;
8845
8846 /* Look down while we haven't passed the location being disassembled.
8847 The reason for this is that there's no defined order between a symbol
8848 and an mapping symbol that may be at the same address. We may have to
8849 look at least one position ahead. */
8850 for (; n < info->symtab_size; n++)
8851 {
8852 addr = bfd_asymbol_value (info->symtab[n]);
8853 if (addr > pc)
8854 break;
8855 if (get_map_sym_type (info, n, &type))
8856 {
8857 last_sym = n;
8858 found = TRUE;
8859 }
8860 }
8861
8862 if (!found)
8863 {
8864 n = info->symtab_pos;
8865 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
8866 n = private_data->last_mapping_sym;
8867
8868 /* No mapping symbol found at this address. Look backwards
8869 for a preceeding one, but don't go pass the section start
8870 otherwise a data section with no mapping symbol can pick up
8871 a text mapping symbol of a preceeding section. The documentation
8872 says section can be NULL, in which case we will seek up all the
8873 way to the top. */
8874 if (info->section)
8875 section_vma = info->section->vma;
8876
8877 for (; n >= 0; n--)
8878 {
8879 addr = bfd_asymbol_value (info->symtab[n]);
8880 if (addr < section_vma)
8881 break;
8882
8883 if (get_map_sym_type (info, n, &type))
8884 {
8885 last_sym = n;
8886 found = TRUE;
8887 break;
8888 }
8889 }
8890 }
8891 }
8892
8893 /* If no mapping symbol was found, try looking up without a mapping
8894 symbol. This is done by walking up from the current PC to the nearest
8895 symbol. We don't actually have to loop here since symtab_pos will
8896 contain the nearest symbol already. */
8897 if (!found)
8898 {
8899 n = info->symtab_pos;
8900 if (n >= 0 && get_sym_code_type (info, n, &type))
8901 {
8902 last_sym = n;
8903 found = TRUE;
8904 }
8905 }
8906
8907 private_data->last_mapping_sym = last_sym;
8908 private_data->last_type = type;
8909 private_data->last_stop_offset = info->stop_offset;
8910
8911 *map_symbol = type;
8912 return found;
8913 }
8914
8915 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
8916 of the supplied arm_feature_set structure with bitmasks indicating
8917 the supported base architectures and coprocessor extensions.
8918
8919 FIXME: This could more efficiently implemented as a constant array,
8920 although it would also be less robust. */
8921
8922 static void
8923 select_arm_features (unsigned long mach,
8924 arm_feature_set * features)
8925 {
8926 arm_feature_set arch_fset;
8927 const arm_feature_set fpu_any = FPU_ANY;
8928
8929 #undef ARM_SET_FEATURES
8930 #define ARM_SET_FEATURES(FSET) \
8931 { \
8932 const arm_feature_set fset = FSET; \
8933 arch_fset = fset; \
8934 }
8935
8936 /* When several architecture versions share the same bfd_mach_arm_XXX value
8937 the most featureful is chosen. */
8938 switch (mach)
8939 {
8940 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
8941 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
8942 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
8943 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
8944 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
8945 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
8946 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
8947 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
8948 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
8949 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
8950 case bfd_mach_arm_ep9312:
8951 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
8952 ARM_CEXT_MAVERICK | FPU_MAVERICK));
8953 break;
8954 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
8955 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
8956 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
8957 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
8958 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
8959 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
8960 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
8961 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
8962 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
8963 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
8964 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
8965 case bfd_mach_arm_8:
8966 {
8967 /* Add bits for extensions that Armv8.5-A recognizes. */
8968 arm_feature_set armv8_5_ext_fset
8969 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
8970 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
8971 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
8972 break;
8973 }
8974 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
8975 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
8976 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
8977 case bfd_mach_arm_8_1M_MAIN:
8978 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
8979 force_thumb = 1;
8980 break;
8981 /* If the machine type is unknown allow all architecture types and all
8982 extensions. */
8983 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
8984 default:
8985 abort ();
8986 }
8987 #undef ARM_SET_FEATURES
8988
8989 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
8990 and thus on bfd_mach_arm_XXX value. Therefore for a given
8991 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
8992 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
8993 }
8994
8995
8996 /* NOTE: There are no checks in these routines that
8997 the relevant number of data bytes exist. */
8998
8999 static int
9000 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
9001 {
9002 unsigned char b[4];
9003 long given;
9004 int status;
9005 int is_thumb = FALSE;
9006 int is_data = FALSE;
9007 int little_code;
9008 unsigned int size = 4;
9009 void (*printer) (bfd_vma, struct disassemble_info *, long);
9010 bfd_boolean found = FALSE;
9011 struct arm_private_data *private_data;
9012
9013 if (info->disassembler_options)
9014 {
9015 parse_arm_disassembler_options (info->disassembler_options);
9016
9017 /* To avoid repeated parsing of these options, we remove them here. */
9018 info->disassembler_options = NULL;
9019 }
9020
9021 /* PR 10288: Control which instructions will be disassembled. */
9022 if (info->private_data == NULL)
9023 {
9024 static struct arm_private_data private;
9025
9026 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
9027 /* If the user did not use the -m command line switch then default to
9028 disassembling all types of ARM instruction.
9029
9030 The info->mach value has to be ignored as this will be based on
9031 the default archictecture for the target and/or hints in the notes
9032 section, but it will never be greater than the current largest arm
9033 machine value (iWMMXt2), which is only equivalent to the V5TE
9034 architecture. ARM architectures have advanced beyond the machine
9035 value encoding, and these newer architectures would be ignored if
9036 the machine value was used.
9037
9038 Ie the -m switch is used to restrict which instructions will be
9039 disassembled. If it is necessary to use the -m switch to tell
9040 objdump that an ARM binary is being disassembled, eg because the
9041 input is a raw binary file, but it is also desired to disassemble
9042 all ARM instructions then use "-marm". This will select the
9043 "unknown" arm architecture which is compatible with any ARM
9044 instruction. */
9045 info->mach = bfd_mach_arm_unknown;
9046
9047 /* Compute the architecture bitmask from the machine number.
9048 Note: This assumes that the machine number will not change
9049 during disassembly.... */
9050 select_arm_features (info->mach, & private.features);
9051
9052 private.last_mapping_sym = -1;
9053 private.last_mapping_addr = 0;
9054 private.last_stop_offset = 0;
9055
9056 info->private_data = & private;
9057 }
9058
9059 private_data = info->private_data;
9060
9061 /* Decide if our code is going to be little-endian, despite what the
9062 function argument might say. */
9063 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
9064
9065 /* For ELF, consult the symbol table to determine what kind of code
9066 or data we have. */
9067 if (info->symtab_size != 0
9068 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
9069 {
9070 bfd_vma addr;
9071 int n;
9072 int last_sym = -1;
9073 enum map_type type = MAP_ARM;
9074
9075 found = mapping_symbol_for_insn (pc, info, &type);
9076 last_sym = private_data->last_mapping_sym;
9077
9078 is_thumb = (private_data->last_type == MAP_THUMB);
9079 is_data = (private_data->last_type == MAP_DATA);
9080
9081 /* Look a little bit ahead to see if we should print out
9082 two or four bytes of data. If there's a symbol,
9083 mapping or otherwise, after two bytes then don't
9084 print more. */
9085 if (is_data)
9086 {
9087 size = 4 - (pc & 3);
9088 for (n = last_sym + 1; n < info->symtab_size; n++)
9089 {
9090 addr = bfd_asymbol_value (info->symtab[n]);
9091 if (addr > pc
9092 && (info->section == NULL
9093 || info->section == info->symtab[n]->section))
9094 {
9095 if (addr - pc < size)
9096 size = addr - pc;
9097 break;
9098 }
9099 }
9100 /* If the next symbol is after three bytes, we need to
9101 print only part of the data, so that we can use either
9102 .byte or .short. */
9103 if (size == 3)
9104 size = (pc & 1) ? 1 : 2;
9105 }
9106 }
9107
9108 if (info->symbols != NULL)
9109 {
9110 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
9111 {
9112 coff_symbol_type * cs;
9113
9114 cs = coffsymbol (*info->symbols);
9115 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
9116 || cs->native->u.syment.n_sclass == C_THUMBSTAT
9117 || cs->native->u.syment.n_sclass == C_THUMBLABEL
9118 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
9119 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
9120 }
9121 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
9122 && !found)
9123 {
9124 /* If no mapping symbol has been found then fall back to the type
9125 of the function symbol. */
9126 elf_symbol_type * es;
9127 unsigned int type;
9128
9129 es = *(elf_symbol_type **)(info->symbols);
9130 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
9131
9132 is_thumb =
9133 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
9134 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
9135 }
9136 else if (bfd_asymbol_flavour (*info->symbols)
9137 == bfd_target_mach_o_flavour)
9138 {
9139 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
9140
9141 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
9142 }
9143 }
9144
9145 if (force_thumb)
9146 is_thumb = TRUE;
9147
9148 if (is_data)
9149 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
9150 else
9151 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
9152
9153 info->bytes_per_line = 4;
9154
9155 /* PR 10263: Disassemble data if requested to do so by the user. */
9156 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
9157 {
9158 int i;
9159
9160 /* Size was already set above. */
9161 info->bytes_per_chunk = size;
9162 printer = print_insn_data;
9163
9164 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
9165 given = 0;
9166 if (little)
9167 for (i = size - 1; i >= 0; i--)
9168 given = b[i] | (given << 8);
9169 else
9170 for (i = 0; i < (int) size; i++)
9171 given = b[i] | (given << 8);
9172 }
9173 else if (!is_thumb)
9174 {
9175 /* In ARM mode endianness is a straightforward issue: the instruction
9176 is four bytes long and is either ordered 0123 or 3210. */
9177 printer = print_insn_arm;
9178 info->bytes_per_chunk = 4;
9179 size = 4;
9180
9181 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
9182 if (little_code)
9183 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
9184 else
9185 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
9186 }
9187 else
9188 {
9189 /* In Thumb mode we have the additional wrinkle of two
9190 instruction lengths. Fortunately, the bits that determine
9191 the length of the current instruction are always to be found
9192 in the first two bytes. */
9193 printer = print_insn_thumb16;
9194 info->bytes_per_chunk = 2;
9195 size = 2;
9196
9197 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
9198 if (little_code)
9199 given = (b[0]) | (b[1] << 8);
9200 else
9201 given = (b[1]) | (b[0] << 8);
9202
9203 if (!status)
9204 {
9205 /* These bit patterns signal a four-byte Thumb
9206 instruction. */
9207 if ((given & 0xF800) == 0xF800
9208 || (given & 0xF800) == 0xF000
9209 || (given & 0xF800) == 0xE800)
9210 {
9211 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
9212 if (little_code)
9213 given = (b[0]) | (b[1] << 8) | (given << 16);
9214 else
9215 given = (b[1]) | (b[0] << 8) | (given << 16);
9216
9217 printer = print_insn_thumb32;
9218 size = 4;
9219 }
9220 }
9221
9222 if (ifthen_address != pc)
9223 find_ifthen_state (pc, info, little_code);
9224
9225 if (ifthen_state)
9226 {
9227 if ((ifthen_state & 0xf) == 0x8)
9228 ifthen_next_state = 0;
9229 else
9230 ifthen_next_state = (ifthen_state & 0xe0)
9231 | ((ifthen_state & 0xf) << 1);
9232 }
9233 }
9234
9235 if (status)
9236 {
9237 info->memory_error_func (status, pc, info);
9238 return -1;
9239 }
9240 if (info->flags & INSN_HAS_RELOC)
9241 /* If the instruction has a reloc associated with it, then
9242 the offset field in the instruction will actually be the
9243 addend for the reloc. (We are using REL type relocs).
9244 In such cases, we can ignore the pc when computing
9245 addresses, since the addend is not currently pc-relative. */
9246 pc = 0;
9247
9248 printer (pc, info, given);
9249
9250 if (is_thumb)
9251 {
9252 ifthen_state = ifthen_next_state;
9253 ifthen_address += size;
9254 }
9255 return size;
9256 }
9257
9258 int
9259 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
9260 {
9261 /* Detect BE8-ness and record it in the disassembler info. */
9262 if (info->flavour == bfd_target_elf_flavour
9263 && info->section != NULL
9264 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
9265 info->endian_code = BFD_ENDIAN_LITTLE;
9266
9267 return print_insn (pc, info, FALSE);
9268 }
9269
9270 int
9271 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
9272 {
9273 return print_insn (pc, info, TRUE);
9274 }
9275
9276 const disasm_options_and_args_t *
9277 disassembler_options_arm (void)
9278 {
9279 static disasm_options_and_args_t *opts_and_args;
9280
9281 if (opts_and_args == NULL)
9282 {
9283 disasm_options_t *opts;
9284 unsigned int i;
9285
9286 opts_and_args = XNEW (disasm_options_and_args_t);
9287 opts_and_args->args = NULL;
9288
9289 opts = &opts_and_args->options;
9290 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
9291 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
9292 opts->arg = NULL;
9293 for (i = 0; i < NUM_ARM_OPTIONS; i++)
9294 {
9295 opts->name[i] = regnames[i].name;
9296 if (regnames[i].description != NULL)
9297 opts->description[i] = _(regnames[i].description);
9298 else
9299 opts->description[i] = NULL;
9300 }
9301 /* The array we return must be NULL terminated. */
9302 opts->name[i] = NULL;
9303 opts->description[i] = NULL;
9304 }
9305
9306 return opts_and_args;
9307 }
9308
9309 void
9310 print_arm_disassembler_options (FILE *stream)
9311 {
9312 unsigned int i, max_len = 0;
9313 fprintf (stream, _("\n\
9314 The following ARM specific disassembler options are supported for use with\n\
9315 the -M switch:\n"));
9316
9317 for (i = 0; i < NUM_ARM_OPTIONS; i++)
9318 {
9319 unsigned int len = strlen (regnames[i].name);
9320 if (max_len < len)
9321 max_len = len;
9322 }
9323
9324 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
9325 fprintf (stream, " %s%*c %s\n",
9326 regnames[i].name,
9327 (int)(max_len - strlen (regnames[i].name)), ' ',
9328 _(regnames[i].description));
9329 }
GDB Binutils - Deliverables
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