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[binutils, Arm] Add support for conditional instructions in Armv8.1-M Mainline
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24 #include <assert.h>
25
26 #include "disassemble.h"
27 #include "opcode/arm.h"
28 #include "opintl.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
32
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
35 #include "libcoff.h"
36 #include "bfd.h"
37 #include "elf-bfd.h"
38 #include "elf/internal.h"
39 #include "elf/arm.h"
40 #include "mach-o.h"
41
42 /* FIXME: Belongs in global header. */
43 #ifndef strneq
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45 #endif
46
47 /* Cached mapping symbol state. */
48 enum map_type
49 {
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53 };
54
55 struct arm_private_data
56 {
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
68 bfd_vma last_mapping_addr;
69 };
70
71 enum mve_instructions
72 {
73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
231 MVE_VMAX,
232 MVE_VMAXA,
233 MVE_VMAXNM_FP,
234 MVE_VMAXNMA_FP,
235 MVE_VMAXNMV_FP,
236 MVE_VMAXNMAV_FP,
237 MVE_VMAXV,
238 MVE_VMAXAV,
239 MVE_VMIN,
240 MVE_VMINA,
241 MVE_VMINNM_FP,
242 MVE_VMINNMA_FP,
243 MVE_VMINNMV_FP,
244 MVE_VMINNMAV_FP,
245 MVE_VMINV,
246 MVE_VMINAV,
247 MVE_VMLA,
248 MVE_VMUL_FP_T1,
249 MVE_VMUL_FP_T2,
250 MVE_VMUL_VEC_T1,
251 MVE_VMUL_VEC_T2,
252 MVE_VMULH,
253 MVE_VRMULH,
254 MVE_VNEG_FP,
255 MVE_VNEG_VEC,
256 MVE_VPNOT,
257 MVE_VPSEL,
258 MVE_VQABS,
259 MVE_VQADD_T1,
260 MVE_VQADD_T2,
261 MVE_VQSUB_T1,
262 MVE_VQSUB_T2,
263 MVE_VQNEG,
264 MVE_VREV16,
265 MVE_VREV32,
266 MVE_VREV64,
267 MVE_LSLL,
268 MVE_LSLLI,
269 MVE_LSRL,
270 MVE_ASRL,
271 MVE_ASRLI,
272 MVE_SQRSHRL,
273 MVE_SQRSHR,
274 MVE_UQRSHL,
275 MVE_UQRSHLL,
276 MVE_UQSHL,
277 MVE_UQSHLL,
278 MVE_URSHRL,
279 MVE_URSHR,
280 MVE_SRSHRL,
281 MVE_SRSHR,
282 MVE_SQSHLL,
283 MVE_SQSHL,
284 MVE_CINC,
285 MVE_CINV,
286 MVE_CNEG,
287 MVE_CSINC,
288 MVE_CSINV,
289 MVE_CSET,
290 MVE_CSETM,
291 MVE_CSNEG,
292 MVE_CSEL,
293 MVE_NONE
294 };
295
296 enum mve_unpredictable
297 {
298 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
299 */
300 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
301 fcB = 1 (vpt). */
302 UNPRED_R13, /* Unpredictable because r13 (sp) or
303 r15 (sp) used. */
304 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
305 UNPRED_Q_GT_4, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
310 and WB bit = 1. */
311 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
312 equal. */
313 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
314 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
315 same. */
316 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
317 size = 1. */
318 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
319 size = 2. */
320 UNPRED_NONE /* No unpredictable behavior. */
321 };
322
323 enum mve_undefined
324 {
325 UNDEF_SIZE, /* undefined size. */
326 UNDEF_SIZE_0, /* undefined because size == 0. */
327 UNDEF_SIZE_2, /* undefined because size == 2. */
328 UNDEF_SIZE_3, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
330 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
331 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
334 size == 0. */
335 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
336 size == 1. */
337 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
338 UNDEF_VCVT_IMM6, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
340 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
341 op1 == (0 or 1). */
342 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
345 in {0xx1, x0x1}. */
346 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
347 UNDEF_NONE /* no undefined behavior. */
348 };
349
350 struct opcode32
351 {
352 arm_feature_set arch; /* Architecture defining this insn. */
353 unsigned long value; /* If arch is 0 then value is a sentinel. */
354 unsigned long mask; /* Recognise insn if (op & mask) == value. */
355 const char * assembler; /* How to disassemble this insn. */
356 };
357
358 /* MVE opcodes. */
359
360 struct mopcode32
361 {
362 arm_feature_set arch; /* Architecture defining this insn. */
363 enum mve_instructions mve_op; /* Specific mve instruction for faster
364 decoding. */
365 unsigned long value; /* If arch is 0 then value is a sentinel. */
366 unsigned long mask; /* Recognise insn if (op & mask) == value. */
367 const char * assembler; /* How to disassemble this insn. */
368 };
369
370 enum isa {
371 ANY,
372 T32,
373 ARM
374 };
375
376
377 /* Shared (between Arm and Thumb mode) opcode. */
378 struct sopcode32
379 {
380 enum isa isa; /* Execution mode instruction availability. */
381 arm_feature_set arch; /* Architecture defining this insn. */
382 unsigned long value; /* If arch is 0 then value is a sentinel. */
383 unsigned long mask; /* Recognise insn if (op & mask) == value. */
384 const char * assembler; /* How to disassemble this insn. */
385 };
386
387 struct opcode16
388 {
389 arm_feature_set arch; /* Architecture defining this insn. */
390 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
391 const char *assembler; /* How to disassemble this insn. */
392 };
393
394 /* print_insn_coprocessor recognizes the following format control codes:
395
396 %% %
397
398 %c print condition code (always bits 28-31 in ARM mode)
399 %q print shifter argument
400 %u print condition code (unconditional in ARM mode,
401 UNPREDICTABLE if not AL in Thumb)
402 %A print address for ldc/stc/ldf/stf instruction
403 %B print vstm/vldm register list
404 %C print vscclrm register list
405 %I print cirrus signed shift immediate: bits 0..3|4..6
406 %J print register for VLDR instruction
407 %K print address for VLDR instruction
408 %F print the COUNT field of a LFM/SFM instruction.
409 %P print floating point precision in arithmetic insn
410 %Q print floating point precision in ldf/stf insn
411 %R print floating point rounding mode
412
413 %<bitfield>c print as a condition code (for vsel)
414 %<bitfield>r print as an ARM register
415 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
416 %<bitfield>ru as %<>r but each u register must be unique.
417 %<bitfield>d print the bitfield in decimal
418 %<bitfield>k print immediate for VFPv3 conversion instruction
419 %<bitfield>x print the bitfield in hex
420 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
421 %<bitfield>f print a floating point constant if >7 else a
422 floating point register
423 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
424 %<bitfield>g print as an iWMMXt 64-bit register
425 %<bitfield>G print as an iWMMXt general purpose or control register
426 %<bitfield>D print as a NEON D register
427 %<bitfield>Q print as a NEON Q register
428 %<bitfield>V print as a NEON D or Q register
429 %<bitfield>E print a quarter-float immediate value
430
431 %y<code> print a single precision VFP reg.
432 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
433 %z<code> print a double precision VFP reg
434 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
435
436 %<bitfield>'c print specified char iff bitfield is all ones
437 %<bitfield>`c print specified char iff bitfield is all zeroes
438 %<bitfield>?ab... select from array of values in big endian order
439
440 %L print as an iWMMXt N/M width field.
441 %Z print the Immediate of a WSHUFH instruction.
442 %l like 'A' except use byte offsets for 'B' & 'H'
443 versions.
444 %i print 5-bit immediate in bits 8,3..0
445 (print "32" when 0)
446 %r print register offset address for wldt/wstr instruction. */
447
448 enum opcode_sentinel_enum
449 {
450 SENTINEL_IWMMXT_START = 1,
451 SENTINEL_IWMMXT_END,
452 SENTINEL_GENERIC_START
453 } opcode_sentinels;
454
455 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
456 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
457 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
458 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
459
460 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
461
462 static const struct sopcode32 coprocessor_opcodes[] =
463 {
464 /* XScale instructions. */
465 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
466 0x0e200010, 0x0fff0ff0,
467 "mia%c\tacc0, %0-3r, %12-15r"},
468 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
469 0x0e280010, 0x0fff0ff0,
470 "miaph%c\tacc0, %0-3r, %12-15r"},
471 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
472 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
473 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
474 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
475 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
476 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
477
478 /* Intel Wireless MMX technology instructions. */
479 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
480 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
481 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
482 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
483 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
484 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
485 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
486 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
487 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
488 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
489 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
490 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
491 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
492 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
493 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
494 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
495 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
496 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
497 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
498 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
499 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
500 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
501 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
502 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
503 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
504 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
505 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
506 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
507 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
508 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
509 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
510 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
511 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
512 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
513 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
514 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
515 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
516 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
517 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
518 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
519 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
520 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
521 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
522 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
523 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
524 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
525 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
526 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
527 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
528 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
529 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
530 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
531 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
532 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
533 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
534 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
535 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
536 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
537 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
538 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
539 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
540 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
541 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
542 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
543 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
544 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
545 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
547 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
549 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
551 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
552 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
553 0x0e800120, 0x0f800ff0,
554 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
556 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
557 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
558 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
559 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
560 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
562 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
564 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
566 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
568 0x0e8000a0, 0x0f800ff0,
569 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
570 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
571 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
572 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
573 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
574 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
575 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
576 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
577 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
578 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
579 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
580 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
581 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
582 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
583 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
584 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
585 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
586 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
587 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
588 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
589 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
590 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
591 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
592 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
593 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
594 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
595 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
596 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
597 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
598 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
599 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
600 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
601 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
602 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
603 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
604 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
605 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
606 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
607 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
608 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
609 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
610 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
611 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
612 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
613 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
614 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
615 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
616 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
617 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
618 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
619 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
620 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
621 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
622 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
623 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
624 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
625 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
626 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
627 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
628 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
629 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
631 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
632 {ANY, ARM_FEATURE_CORE_LOW (0),
633 SENTINEL_IWMMXT_END, 0, "" },
634
635 /* Floating point coprocessor (FPA) instructions. */
636 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
637 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
638 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
639 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
640 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
641 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
642 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
643 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
644 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
645 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
646 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
647 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
648 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
649 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
650 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
651 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
652 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
653 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
654 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
655 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
656 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
657 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
658 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
659 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
660 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
661 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
662 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
663 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
664 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
665 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
666 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
667 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
668 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
669 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
670 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
671 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
672 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
673 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
674 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
675 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
676 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
677 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
678 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
679 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
680 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
681 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
682 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
683 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
684 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
685 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
686 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
687 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
688 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
689 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
690 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
691 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
692 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
693 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
694 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
695 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
696 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
697 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
698 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
699 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
700 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
701 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
702 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
703 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
704 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
705 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
706 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
707 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
708 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
709 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
710 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
711 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
712 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
713 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
714 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
715 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
716 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
717 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
718 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
719 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
720 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
721 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
722
723 /* Armv8.1-M Mainline instructions. */
724 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
725 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
726 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
727 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
728
729 /* ARMv8-M Mainline Security Extensions instructions. */
730 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
731 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
732 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
733 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
734
735 /* Register load/store. */
736 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
737 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
738 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
739 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
740 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
741 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
742 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
743 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
744 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
745 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
746 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
747 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
748 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
749 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
750 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
751 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
752 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
753 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
754 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
755 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
756 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
757 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
758 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
759 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
760 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
761 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
762 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
763 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
764 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
765 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
766 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
767 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
768 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
769 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
770 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
771 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
772
773 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
774 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
775 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
776 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
777 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
778 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
779 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
780 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
781
782 /* Data transfer between ARM and NEON registers. */
783 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
784 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
785 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
786 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
787 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
788 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
789 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
790 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
791 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
792 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
793 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
794 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
795 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
796 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
797 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
798 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
799 /* Half-precision conversion instructions. */
800 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
801 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
802 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
803 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
804 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
805 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
806 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
807 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
808
809 /* Floating point coprocessor (VFP) instructions. */
810 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
811 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
812 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
813 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
814 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
815 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
816 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
817 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
818 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
819 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
820 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
821 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
822 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
824 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
825 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
826 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
827 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
828 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
829 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
830 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
831 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
832 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
833 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
834 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
835 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
836 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
837 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
838 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
839 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
840 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
841 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
842 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
843 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
844 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
845 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
846 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
847 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
849 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
851 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
853 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
855 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
856 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
857 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
858 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
859 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
860 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
861 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
862 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
863 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
864 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
865 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
866 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
867 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
868 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
869 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
870 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
871 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
872 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
873 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
874 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
875 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
876 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
877 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
878 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
879 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
880 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
881 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
882 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
883 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
884 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
885 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
886 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
887 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
888 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
889 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
890 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
891 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
892 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
893 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
894 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
895 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
896 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
897 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
898 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
899 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
900 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
901 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
902 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
903 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
904 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
905 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
906 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
907 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
908 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
909 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
910 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
911 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
912 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
913 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
914 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
915 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
916 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
917 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
918 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
919 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
920 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
921 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
922 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
923 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
924 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
925 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
926 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
927 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
928 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
929 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
930 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
931 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
932 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
933 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
934 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
935 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
936 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
937 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
938 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
939 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
940 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
941 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
942 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
943 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
944 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
945 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
946 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
947 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
948
949 /* Cirrus coprocessor instructions. */
950 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
951 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
952 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
953 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
954 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
955 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
956 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
957 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
958 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
959 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
960 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
961 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
962 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
963 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
964 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
965 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
966 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
967 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
968 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
969 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
970 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
971 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
972 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
973 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
974 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
975 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
976 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
977 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
978 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
979 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
980 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
981 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
982 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
983 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
984 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
985 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
986 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
987 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
988 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
989 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
990 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
991 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
992 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
993 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
994 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
995 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
996 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
997 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
998 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
999 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
1000 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1001 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
1002 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1003 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
1004 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1005 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
1006 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1007 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
1008 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1009 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
1010 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1011 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
1012 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1013 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
1014 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1015 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
1016 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1017 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
1018 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1019 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
1020 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1021 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
1022 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1023 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
1024 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1025 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
1026 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1027 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
1028 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1029 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
1030 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1031 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
1032 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1033 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
1034 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1035 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
1036 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1037 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1038 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1039 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1040 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1041 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1042 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1043 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1044 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1045 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1046 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1047 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1048 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1049 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1050 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1051 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1052 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1053 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1054 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1055 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1056 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1057 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1058 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1059 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1060 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1061 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1062 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1063 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1064 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1065 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1066 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1067 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1068 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1069 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1070 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1071 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1072 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1073 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1074 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1075 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1076 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1077 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1078 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1079 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1080 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1081 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1082 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1083 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1084 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1085 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1086 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1087 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1088 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1089 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1090 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1091 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1092 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1093 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1094 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1095 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1096 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1097 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1098 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1099 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1100 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1101 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1102 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1103 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1104 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1105 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1106 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1107 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1108 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1109 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1110 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1111 0x0e000600, 0x0ff00f10,
1112 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1113 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1114 0x0e100600, 0x0ff00f10,
1115 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1116 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1117 0x0e200600, 0x0ff00f10,
1118 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1119 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1120 0x0e300600, 0x0ff00f10,
1121 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1122
1123 /* VFP Fused multiply add instructions. */
1124 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1125 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1126 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1127 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1128 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1129 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1130 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1131 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1132 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1133 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1134 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1135 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1136 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1137 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1138 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1139 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1140
1141 /* FP v5. */
1142 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1143 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1144 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1145 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1146 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1147 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1148 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1149 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1150 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1151 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1152 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1153 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1154 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1155 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1156 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1157 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1158 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1159 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1160 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1161 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1162 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1163 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1164 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1165 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1166
1167 /* Generic coprocessor instructions. */
1168 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1169 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1170 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1171 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1172 0x0c500000, 0x0ff00000,
1173 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1174 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1175 0x0e000000, 0x0f000010,
1176 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1177 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1178 0x0e10f010, 0x0f10f010,
1179 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1180 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1181 0x0e100010, 0x0f100010,
1182 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1183 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1184 0x0e000010, 0x0f100010,
1185 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1186 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1187 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1188 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1189 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1190
1191 /* V6 coprocessor instructions. */
1192 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1193 0xfc500000, 0xfff00000,
1194 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1195 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1196 0xfc400000, 0xfff00000,
1197 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1198
1199 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1200 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1201 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1202 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1203 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1204 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1205 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1206 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1207 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1208 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1209 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1210 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1211 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1212 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1213 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1214 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1215 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1216 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1217 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1218 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1219 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1220
1221 /* Dot Product instructions in the space of coprocessor 13. */
1222 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1223 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1224 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1225 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1226
1227 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1228 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1229 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1230 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1231 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1232 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1233 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1234 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1235 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1236 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1237 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1238 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1239 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1240 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1241 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1242 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1243 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1244
1245 /* V5 coprocessor instructions. */
1246 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1247 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1248 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1249 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1250 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1251 0xfe000000, 0xff000010,
1252 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1253 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1254 0xfe000010, 0xff100010,
1255 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1256 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1257 0xfe100010, 0xff100010,
1258 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1259
1260 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1261 cp_num: bit <11:8> == 0b1001.
1262 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1263 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1264 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1265 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1266 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1267 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1268 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1269 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1270 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1271 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1272 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1273 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1274 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1275 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1276 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1277 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1278 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1279 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1281 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1282 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1283 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1285 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1286 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1287 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1288 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1289 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1290 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1291 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1292 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1293 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1294 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1295 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1296 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1297 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1298 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1299 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1300 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1301 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1302 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1303 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1304 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1305 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1306 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1307 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1308 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1309 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1310 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1311 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1312 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1313 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1314 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1315 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1316 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1317 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1318 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1319 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1320 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1321 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1322 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1323 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1324 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1325 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1326 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1327 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1328 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1329 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1330 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1331 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1332 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1333
1334 /* ARMv8.3 javascript conversion instruction. */
1335 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1336 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1337
1338 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1339 };
1340
1341 /* Neon opcode table: This does not encode the top byte -- that is
1342 checked by the print_insn_neon routine, as it depends on whether we are
1343 doing thumb32 or arm32 disassembly. */
1344
1345 /* print_insn_neon recognizes the following format control codes:
1346
1347 %% %
1348
1349 %c print condition code
1350 %u print condition code (unconditional in ARM mode,
1351 UNPREDICTABLE if not AL in Thumb)
1352 %A print v{st,ld}[1234] operands
1353 %B print v{st,ld}[1234] any one operands
1354 %C print v{st,ld}[1234] single->all operands
1355 %D print scalar
1356 %E print vmov, vmvn, vorr, vbic encoded constant
1357 %F print vtbl,vtbx register list
1358
1359 %<bitfield>r print as an ARM register
1360 %<bitfield>d print the bitfield in decimal
1361 %<bitfield>e print the 2^N - bitfield in decimal
1362 %<bitfield>D print as a NEON D register
1363 %<bitfield>Q print as a NEON Q register
1364 %<bitfield>R print as a NEON D or Q register
1365 %<bitfield>Sn print byte scaled width limited by n
1366 %<bitfield>Tn print short scaled width limited by n
1367 %<bitfield>Un print long scaled width limited by n
1368
1369 %<bitfield>'c print specified char iff bitfield is all ones
1370 %<bitfield>`c print specified char iff bitfield is all zeroes
1371 %<bitfield>?ab... select from array of values in big endian order. */
1372
1373 static const struct opcode32 neon_opcodes[] =
1374 {
1375 /* Extract. */
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf2b00840, 0xffb00850,
1378 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf2b00000, 0xffb00810,
1381 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1382
1383 /* Data transfer between ARM and NEON registers. */
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1385 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1387 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1393 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1396
1397 /* Move data element to all lanes. */
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1404
1405 /* Table lookup. */
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1410
1411 /* Half-precision conversions. */
1412 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1413 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1414 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1415 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1416
1417 /* NEON fused multiply add instructions. */
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1419 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1420 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1421 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1423 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1425 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1426
1427 /* Two registers, miscellaneous. */
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1429 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1430 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1431 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1433 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1435 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1436 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1437 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1438 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1439 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1440 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1441 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1442 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1443 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1444 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1445 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1446 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1447 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1448 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1449 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1457 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf3b20300, 0xffb30fd0,
1472 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1476 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1480 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf3bb0600, 0xffbf0e10,
1521 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1522 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1523 0xf3b70600, 0xffbf0e10,
1524 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1525
1526 /* Three registers of the same length. */
1527 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1528 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1529 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1530 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1531 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1532 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1533 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1534 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1535 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1536 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1537 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1538 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1539 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1540 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1542 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1544 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1546 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1548 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1556 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1562 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1567 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1568 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1571 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1572 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1574 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1576 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1579 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1580 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1584 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1588 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1591 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1592 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1596 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1599 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1600 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1603 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1604 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1608 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1612 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1615 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1616 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1620 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1623 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1624 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1628 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1632 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1635 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1636 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf2000b00, 0xff800f10,
1645 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647 0xf2000b10, 0xff800f10,
1648 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656 0xf3000b00, 0xff800f10,
1657 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1659 0xf2000000, 0xfe800f10,
1660 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf2000010, 0xfe800f10,
1663 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1665 0xf2000100, 0xfe800f10,
1666 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668 0xf2000200, 0xfe800f10,
1669 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1671 0xf2000210, 0xfe800f10,
1672 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf2000300, 0xfe800f10,
1675 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1677 0xf2000310, 0xfe800f10,
1678 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680 0xf2000400, 0xfe800f10,
1681 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1683 0xf2000410, 0xfe800f10,
1684 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686 0xf2000500, 0xfe800f10,
1687 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf2000510, 0xfe800f10,
1690 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692 0xf2000600, 0xfe800f10,
1693 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695 0xf2000610, 0xfe800f10,
1696 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698 0xf2000700, 0xfe800f10,
1699 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701 0xf2000710, 0xfe800f10,
1702 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704 0xf2000910, 0xfe800f10,
1705 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1706 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1707 0xf2000a00, 0xfe800f10,
1708 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710 0xf2000a10, 0xfe800f10,
1711 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1713 0xf3000b10, 0xff800f10,
1714 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1715 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1716 0xf3000c10, 0xff800f10,
1717 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1718
1719 /* One register and an immediate value. */
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1723 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1725 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1727 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1729 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1730 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1731 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1733 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1735 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1737 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1739 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1743 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1746
1747 /* Two registers and a shift amount. */
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1751 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1755 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2880950, 0xfeb80fd0,
1760 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1762 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1763 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1764 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1765 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1766 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1768 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1770 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1771 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1772 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1774 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1775 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1776 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1778 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1780 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2900950, 0xfeb00fd0,
1783 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1791 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1792 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1793 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1794 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1795 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1797 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1798 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1799 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1800 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1801 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1805 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1806 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1807 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1811 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1813 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1817 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1819 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1823 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1825 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf2a00950, 0xfea00fd0,
1828 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1831 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1832 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1833 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1834 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1837 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1838 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1839 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1840 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1844 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1845 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1846 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1848 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1852 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1854 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf2a00e10, 0xfea00e90,
1867 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1868 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1869 0xf2a00c10, 0xfea00e90,
1870 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1871
1872 /* Three registers of different lengths. */
1873 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1874 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf2800400, 0xff800f50,
1879 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1881 0xf2800600, 0xff800f50,
1882 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884 0xf2800900, 0xff800f50,
1885 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1886 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1887 0xf2800b00, 0xff800f50,
1888 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890 0xf2800d00, 0xff800f50,
1891 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1893 0xf3800400, 0xff800f50,
1894 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1895 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1896 0xf3800600, 0xff800f50,
1897 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899 0xf2800000, 0xfe800f50,
1900 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1901 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1902 0xf2800100, 0xfe800f50,
1903 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905 0xf2800200, 0xfe800f50,
1906 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1907 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1908 0xf2800300, 0xfe800f50,
1909 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911 0xf2800500, 0xfe800f50,
1912 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1913 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1914 0xf2800700, 0xfe800f50,
1915 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917 0xf2800800, 0xfe800f50,
1918 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1920 0xf2800a00, 0xfe800f50,
1921 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1922 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1923 0xf2800c00, 0xfe800f50,
1924 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1925
1926 /* Two registers and a scalar. */
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1930 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1931 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1932 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1934 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1936 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1937 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1938 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1939 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1940 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1944 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1945 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1946 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1947 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1948 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1950 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1951 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1952 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1954 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1956 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1958 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1959 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1960 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1963 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1964 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1965 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1966 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1967 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1968 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1970 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1971 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1972 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1973 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1974 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1975 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1976 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1978 0xf2800240, 0xfe800f50,
1979 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1981 0xf2800640, 0xfe800f50,
1982 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1984 0xf2800a40, 0xfe800f50,
1985 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1987 0xf2800e40, 0xff800f50,
1988 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1989 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1990 0xf2800f40, 0xff800f50,
1991 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1993 0xf3800e40, 0xff800f50,
1994 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1995 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1996 0xf3800f40, 0xff800f50,
1997 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1998 },
1999
2000 /* Element and structure load/store. */
2001 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2002 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2003 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2004 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2005 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2006 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2007 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2008 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2010 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2011 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2012 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2013 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2014 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2016 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2018 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2019 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2020 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2022 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2024 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2025 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2026 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2028 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2030 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2031 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2032 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2034 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2036 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2037 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2038 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2039
2040 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2041 };
2042
2043 /* mve opcode table. */
2044
2045 /* print_insn_mve recognizes the following format control codes:
2046
2047 %% %
2048
2049 %a print '+' or '-' or imm offset in vldr[bhwd] and
2050 vstr[bhwd]
2051 %c print condition code
2052 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2053 %u print 'U' (unsigned) or 'S' for various mve instructions
2054 %i print MVE predicate(s) for vpt and vpst
2055 %j print a 5-bit immediate from hw2[14:12,7:6]
2056 %m print rounding mode for vcvt and vrint
2057 %n print vector comparison code for predicated instruction
2058 %s print size for various vcvt instructions
2059 %v print vector predicate for instruction in predicated
2060 block
2061 %o print offset scaled for vldr[hwd] and vstr[hwd]
2062 %w print writeback mode for MVE v{st,ld}[24]
2063 %B print v{st,ld}[24] any one operands
2064 %E print vmov, vmvn, vorr, vbic encoded constant
2065 %N print generic index for vmov
2066 %T print bottom ('b') or top ('t') of source register
2067 %X print exchange field in vmla* instructions
2068
2069 %<bitfield>r print as an ARM register
2070 %<bitfield>d print the bitfield in decimal
2071 %<bitfield>A print accumulate or not
2072 %<bitfield>c print bitfield as a condition code
2073 %<bitfield>C print bitfield as an inverted condition code
2074 %<bitfield>Q print as a MVE Q register
2075 %<bitfield>F print as a MVE S register
2076 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2077 UNPREDICTABLE
2078
2079 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
2080 %<bitfield>s print size for vector predicate & non VMOV instructions
2081 %<bitfield>I print carry flag or not
2082 %<bitfield>i print immediate for vstr/vldr reg +/- imm
2083 %<bitfield>h print high half of 64-bit destination reg
2084 %<bitfield>k print immediate for vector conversion instruction
2085 %<bitfield>l print low half of 64-bit destination reg
2086 %<bitfield>o print rotate value for vcmul
2087 %<bitfield>u print immediate value for vddup/vdwdup
2088 %<bitfield>x print the bitfield in hex.
2089 */
2090
2091 static const struct mopcode32 mve_opcodes[] =
2092 {
2093 /* MVE. */
2094
2095 {ARM_FEATURE_COPROC (FPU_MVE),
2096 MVE_VPST,
2097 0xfe310f4d, 0xffbf1fff,
2098 "vpst%i"
2099 },
2100
2101 /* Floating point VPT T1. */
2102 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2103 MVE_VPT_FP_T1,
2104 0xee310f00, 0xefb10f50,
2105 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2106 /* Floating point VPT T2. */
2107 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2108 MVE_VPT_FP_T2,
2109 0xee310f40, 0xefb10f50,
2110 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2111
2112 /* Vector VPT T1. */
2113 {ARM_FEATURE_COPROC (FPU_MVE),
2114 MVE_VPT_VEC_T1,
2115 0xfe010f00, 0xff811f51,
2116 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2117 /* Vector VPT T2. */
2118 {ARM_FEATURE_COPROC (FPU_MVE),
2119 MVE_VPT_VEC_T2,
2120 0xfe010f01, 0xff811f51,
2121 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2122 /* Vector VPT T3. */
2123 {ARM_FEATURE_COPROC (FPU_MVE),
2124 MVE_VPT_VEC_T3,
2125 0xfe011f00, 0xff811f50,
2126 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2127 /* Vector VPT T4. */
2128 {ARM_FEATURE_COPROC (FPU_MVE),
2129 MVE_VPT_VEC_T4,
2130 0xfe010f40, 0xff811f70,
2131 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2132 /* Vector VPT T5. */
2133 {ARM_FEATURE_COPROC (FPU_MVE),
2134 MVE_VPT_VEC_T5,
2135 0xfe010f60, 0xff811f70,
2136 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2137 /* Vector VPT T6. */
2138 {ARM_FEATURE_COPROC (FPU_MVE),
2139 MVE_VPT_VEC_T6,
2140 0xfe011f40, 0xff811f50,
2141 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2142
2143 /* Vector VBIC immediate. */
2144 {ARM_FEATURE_COPROC (FPU_MVE),
2145 MVE_VBIC_IMM,
2146 0xef800070, 0xefb81070,
2147 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2148
2149 /* Vector VBIC register. */
2150 {ARM_FEATURE_COPROC (FPU_MVE),
2151 MVE_VBIC_REG,
2152 0xef100150, 0xffb11f51,
2153 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2154
2155 /* Vector VABAV. */
2156 {ARM_FEATURE_COPROC (FPU_MVE),
2157 MVE_VABAV,
2158 0xee800f01, 0xefc10f51,
2159 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2160
2161 /* Vector VABD floating point. */
2162 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2163 MVE_VABD_FP,
2164 0xff200d40, 0xffa11f51,
2165 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2166
2167 /* Vector VABD. */
2168 {ARM_FEATURE_COPROC (FPU_MVE),
2169 MVE_VABD_VEC,
2170 0xef000740, 0xef811f51,
2171 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2172
2173 /* Vector VABS floating point. */
2174 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2175 MVE_VABS_FP,
2176 0xFFB10740, 0xFFB31FD1,
2177 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2178 /* Vector VABS. */
2179 {ARM_FEATURE_COPROC (FPU_MVE),
2180 MVE_VABS_VEC,
2181 0xffb10340, 0xffb31fd1,
2182 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2183
2184 /* Vector VADD floating point T1. */
2185 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2186 MVE_VADD_FP_T1,
2187 0xef000d40, 0xffa11f51,
2188 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2189 /* Vector VADD floating point T2. */
2190 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2191 MVE_VADD_FP_T2,
2192 0xee300f40, 0xefb11f70,
2193 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2194 /* Vector VADD T1. */
2195 {ARM_FEATURE_COPROC (FPU_MVE),
2196 MVE_VADD_VEC_T1,
2197 0xef000840, 0xff811f51,
2198 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2199 /* Vector VADD T2. */
2200 {ARM_FEATURE_COPROC (FPU_MVE),
2201 MVE_VADD_VEC_T2,
2202 0xee010f40, 0xff811f70,
2203 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2204
2205 /* Vector VADDLV. */
2206 {ARM_FEATURE_COPROC (FPU_MVE),
2207 MVE_VADDLV,
2208 0xee890f00, 0xef8f1fd1,
2209 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2210
2211 /* Vector VADDV. */
2212 {ARM_FEATURE_COPROC (FPU_MVE),
2213 MVE_VADDV,
2214 0xeef10f00, 0xeff31fd1,
2215 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2216
2217 /* Vector VADC. */
2218 {ARM_FEATURE_COPROC (FPU_MVE),
2219 MVE_VADC,
2220 0xee300f00, 0xffb10f51,
2221 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2222
2223 /* Vector VAND. */
2224 {ARM_FEATURE_COPROC (FPU_MVE),
2225 MVE_VAND,
2226 0xef000150, 0xffb11f51,
2227 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2228
2229 /* Vector VBRSR register. */
2230 {ARM_FEATURE_COPROC (FPU_MVE),
2231 MVE_VBRSR,
2232 0xfe011e60, 0xff811f70,
2233 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2234
2235 /* Vector VCADD floating point. */
2236 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2237 MVE_VCADD_FP,
2238 0xfc800840, 0xfea11f51,
2239 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2240
2241 /* Vector VCADD. */
2242 {ARM_FEATURE_COPROC (FPU_MVE),
2243 MVE_VCADD_VEC,
2244 0xfe000f00, 0xff810f51,
2245 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2246
2247 /* Vector VCLS. */
2248 {ARM_FEATURE_COPROC (FPU_MVE),
2249 MVE_VCLS,
2250 0xffb00440, 0xffb31fd1,
2251 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2252
2253 /* Vector VCLZ. */
2254 {ARM_FEATURE_COPROC (FPU_MVE),
2255 MVE_VCLZ,
2256 0xffb004c0, 0xffb31fd1,
2257 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2258
2259 /* Vector VCMLA. */
2260 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2261 MVE_VCMLA_FP,
2262 0xfc200840, 0xfe211f51,
2263 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2264
2265 /* Vector VCMP floating point T1. */
2266 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2267 MVE_VCMP_FP_T1,
2268 0xee310f00, 0xeff1ef50,
2269 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2270
2271 /* Vector VCMP floating point T2. */
2272 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2273 MVE_VCMP_FP_T2,
2274 0xee310f40, 0xeff1ef50,
2275 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2276
2277 /* Vector VCMP T1. */
2278 {ARM_FEATURE_COPROC (FPU_MVE),
2279 MVE_VCMP_VEC_T1,
2280 0xfe010f00, 0xffc1ff51,
2281 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2282 /* Vector VCMP T2. */
2283 {ARM_FEATURE_COPROC (FPU_MVE),
2284 MVE_VCMP_VEC_T2,
2285 0xfe010f01, 0xffc1ff51,
2286 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2287 /* Vector VCMP T3. */
2288 {ARM_FEATURE_COPROC (FPU_MVE),
2289 MVE_VCMP_VEC_T3,
2290 0xfe011f00, 0xffc1ff50,
2291 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2292 /* Vector VCMP T4. */
2293 {ARM_FEATURE_COPROC (FPU_MVE),
2294 MVE_VCMP_VEC_T4,
2295 0xfe010f40, 0xffc1ff70,
2296 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2297 /* Vector VCMP T5. */
2298 {ARM_FEATURE_COPROC (FPU_MVE),
2299 MVE_VCMP_VEC_T5,
2300 0xfe010f60, 0xffc1ff70,
2301 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2302 /* Vector VCMP T6. */
2303 {ARM_FEATURE_COPROC (FPU_MVE),
2304 MVE_VCMP_VEC_T6,
2305 0xfe011f40, 0xffc1ff50,
2306 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2307
2308 /* Vector VDUP. */
2309 {ARM_FEATURE_COPROC (FPU_MVE),
2310 MVE_VDUP,
2311 0xeea00b10, 0xffb10f5f,
2312 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2313
2314 /* Vector VEOR. */
2315 {ARM_FEATURE_COPROC (FPU_MVE),
2316 MVE_VEOR,
2317 0xff000150, 0xffd11f51,
2318 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2319
2320 /* Vector VFMA, vector * scalar. */
2321 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2322 MVE_VFMA_FP_SCALAR,
2323 0xee310e40, 0xefb11f70,
2324 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2325
2326 /* Vector VFMA floating point. */
2327 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2328 MVE_VFMA_FP,
2329 0xef000c50, 0xffa11f51,
2330 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2331
2332 /* Vector VFMS floating point. */
2333 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2334 MVE_VFMS_FP,
2335 0xef200c50, 0xffa11f51,
2336 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2337
2338 /* Vector VFMAS, vector * scalar. */
2339 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2340 MVE_VFMAS_FP_SCALAR,
2341 0xee311e40, 0xefb11f70,
2342 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2343
2344 /* Vector VHADD T1. */
2345 {ARM_FEATURE_COPROC (FPU_MVE),
2346 MVE_VHADD_T1,
2347 0xef000040, 0xef811f51,
2348 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2349
2350 /* Vector VHADD T2. */
2351 {ARM_FEATURE_COPROC (FPU_MVE),
2352 MVE_VHADD_T2,
2353 0xee000f40, 0xef811f70,
2354 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2355
2356 /* Vector VHSUB T1. */
2357 {ARM_FEATURE_COPROC (FPU_MVE),
2358 MVE_VHSUB_T1,
2359 0xef000240, 0xef811f51,
2360 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2361
2362 /* Vector VHSUB T2. */
2363 {ARM_FEATURE_COPROC (FPU_MVE),
2364 MVE_VHSUB_T2,
2365 0xee001f40, 0xef811f70,
2366 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2367
2368 /* Vector VCMUL. */
2369 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2370 MVE_VCMUL_FP,
2371 0xee300e00, 0xefb10f50,
2372 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2373
2374 /* Vector VCTP. */
2375 {ARM_FEATURE_COPROC (FPU_MVE),
2376 MVE_VCTP,
2377 0xf000e801, 0xffc0ffff,
2378 "vctp%v.%20-21s\t%16-19r"},
2379
2380 /* Vector VDUP. */
2381 {ARM_FEATURE_COPROC (FPU_MVE),
2382 MVE_VDUP,
2383 0xeea00b10, 0xffb10f5f,
2384 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2385
2386 /* Vector VRHADD. */
2387 {ARM_FEATURE_COPROC (FPU_MVE),
2388 MVE_VRHADD,
2389 0xef000140, 0xef811f51,
2390 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2391
2392 /* Vector VCVT. */
2393 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2394 MVE_VCVT_FP_FIX_VEC,
2395 0xef800c50, 0xef801cd1,
2396 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2397
2398 /* Vector VCVT. */
2399 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2400 MVE_VCVT_BETWEEN_FP_INT,
2401 0xffb30640, 0xffb31e51,
2402 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2403
2404 /* Vector VCVT between single and half-precision float, bottom half. */
2405 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2406 MVE_VCVT_FP_HALF_FP,
2407 0xee3f0e01, 0xefbf1fd1,
2408 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2409
2410 /* Vector VCVT between single and half-precision float, top half. */
2411 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2412 MVE_VCVT_FP_HALF_FP,
2413 0xee3f1e01, 0xefbf1fd1,
2414 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2415
2416 /* Vector VCVT. */
2417 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2418 MVE_VCVT_FROM_FP_TO_INT,
2419 0xffb30040, 0xffb31c51,
2420 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2421
2422 /* Vector VDDUP. */
2423 {ARM_FEATURE_COPROC (FPU_MVE),
2424 MVE_VDDUP,
2425 0xee011f6e, 0xff811f7e,
2426 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2427
2428 /* Vector VDWDUP. */
2429 {ARM_FEATURE_COPROC (FPU_MVE),
2430 MVE_VDWDUP,
2431 0xee011f60, 0xff811f70,
2432 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2433
2434 /* Vector VHCADD. */
2435 {ARM_FEATURE_COPROC (FPU_MVE),
2436 MVE_VHCADD,
2437 0xee000f00, 0xff810f51,
2438 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2439
2440 /* Vector VIWDUP. */
2441 {ARM_FEATURE_COPROC (FPU_MVE),
2442 MVE_VIWDUP,
2443 0xee010f60, 0xff811f70,
2444 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2445
2446 /* Vector VIDUP. */
2447 {ARM_FEATURE_COPROC (FPU_MVE),
2448 MVE_VIDUP,
2449 0xee010f6e, 0xff811f7e,
2450 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2451
2452 /* Vector VLD2. */
2453 {ARM_FEATURE_COPROC (FPU_MVE),
2454 MVE_VLD2,
2455 0xfc901e00, 0xff901e5f,
2456 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2457
2458 /* Vector VLD4. */
2459 {ARM_FEATURE_COPROC (FPU_MVE),
2460 MVE_VLD4,
2461 0xfc901e01, 0xff901e1f,
2462 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2463
2464 /* Vector VLDRB gather load. */
2465 {ARM_FEATURE_COPROC (FPU_MVE),
2466 MVE_VLDRB_GATHER_T1,
2467 0xec900e00, 0xefb01e50,
2468 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2469
2470 /* Vector VLDRH gather load. */
2471 {ARM_FEATURE_COPROC (FPU_MVE),
2472 MVE_VLDRH_GATHER_T2,
2473 0xec900e10, 0xefb01e50,
2474 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2475
2476 /* Vector VLDRW gather load. */
2477 {ARM_FEATURE_COPROC (FPU_MVE),
2478 MVE_VLDRW_GATHER_T3,
2479 0xfc900f40, 0xffb01fd0,
2480 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2481
2482 /* Vector VLDRD gather load. */
2483 {ARM_FEATURE_COPROC (FPU_MVE),
2484 MVE_VLDRD_GATHER_T4,
2485 0xec900fd0, 0xefb01fd0,
2486 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2487
2488 /* Vector VLDRW gather load. */
2489 {ARM_FEATURE_COPROC (FPU_MVE),
2490 MVE_VLDRW_GATHER_T5,
2491 0xfd101e00, 0xff111f00,
2492 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2493
2494 /* Vector VLDRD gather load, variant T6. */
2495 {ARM_FEATURE_COPROC (FPU_MVE),
2496 MVE_VLDRD_GATHER_T6,
2497 0xfd101f00, 0xff111f00,
2498 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2499
2500 /* Vector VLDRB. */
2501 {ARM_FEATURE_COPROC (FPU_MVE),
2502 MVE_VLDRB_T1,
2503 0xec100e00, 0xee581e00,
2504 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2505
2506 /* Vector VLDRH. */
2507 {ARM_FEATURE_COPROC (FPU_MVE),
2508 MVE_VLDRH_T2,
2509 0xec180e00, 0xee581e00,
2510 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2511
2512 /* Vector VLDRB unsigned, variant T5. */
2513 {ARM_FEATURE_COPROC (FPU_MVE),
2514 MVE_VLDRB_T5,
2515 0xec101e00, 0xfe101f80,
2516 "vldrb%v.u8\t%13-15,22Q, %d"},
2517
2518 /* Vector VLDRH unsigned, variant T6. */
2519 {ARM_FEATURE_COPROC (FPU_MVE),
2520 MVE_VLDRH_T6,
2521 0xec101e80, 0xfe101f80,
2522 "vldrh%v.u16\t%13-15,22Q, %d"},
2523
2524 /* Vector VLDRW unsigned, variant T7. */
2525 {ARM_FEATURE_COPROC (FPU_MVE),
2526 MVE_VLDRW_T7,
2527 0xec101f00, 0xfe101f80,
2528 "vldrw%v.u32\t%13-15,22Q, %d"},
2529
2530 /* Vector VMAX. */
2531 {ARM_FEATURE_COPROC (FPU_MVE),
2532 MVE_VMAX,
2533 0xef000640, 0xef811f51,
2534 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2535
2536 /* Vector VMAXA. */
2537 {ARM_FEATURE_COPROC (FPU_MVE),
2538 MVE_VMAXA,
2539 0xee330e81, 0xffb31fd1,
2540 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2541
2542 /* Vector VMAXNM floating point. */
2543 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2544 MVE_VMAXNM_FP,
2545 0xff000f50, 0xffa11f51,
2546 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2547
2548 /* Vector VMAXNMA floating point. */
2549 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2550 MVE_VMAXNMA_FP,
2551 0xee3f0e81, 0xefbf1fd1,
2552 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2553
2554 /* Vector VMAXNMV floating point. */
2555 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2556 MVE_VMAXNMV_FP,
2557 0xeeee0f00, 0xefff0fd1,
2558 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2559
2560 /* Vector VMAXNMAV floating point. */
2561 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2562 MVE_VMAXNMAV_FP,
2563 0xeeec0f00, 0xefff0fd1,
2564 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2565
2566 /* Vector VMAXV. */
2567 {ARM_FEATURE_COPROC (FPU_MVE),
2568 MVE_VMAXV,
2569 0xeee20f00, 0xeff30fd1,
2570 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2571
2572 /* Vector VMAXAV. */
2573 {ARM_FEATURE_COPROC (FPU_MVE),
2574 MVE_VMAXAV,
2575 0xeee00f00, 0xfff30fd1,
2576 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2577
2578 /* Vector VMIN. */
2579 {ARM_FEATURE_COPROC (FPU_MVE),
2580 MVE_VMIN,
2581 0xef000650, 0xef811f51,
2582 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2583
2584 /* Vector VMINA. */
2585 {ARM_FEATURE_COPROC (FPU_MVE),
2586 MVE_VMINA,
2587 0xee331e81, 0xffb31fd1,
2588 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2589
2590 /* Vector VMINNM floating point. */
2591 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2592 MVE_VMINNM_FP,
2593 0xff200f50, 0xffa11f51,
2594 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2595
2596 /* Vector VMINNMA floating point. */
2597 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2598 MVE_VMINNMA_FP,
2599 0xee3f1e81, 0xefbf1fd1,
2600 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2601
2602 /* Vector VMINNMV floating point. */
2603 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2604 MVE_VMINNMV_FP,
2605 0xeeee0f80, 0xefff0fd1,
2606 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2607
2608 /* Vector VMINNMAV floating point. */
2609 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2610 MVE_VMINNMAV_FP,
2611 0xeeec0f80, 0xefff0fd1,
2612 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2613
2614 /* Vector VMINV. */
2615 {ARM_FEATURE_COPROC (FPU_MVE),
2616 MVE_VMINV,
2617 0xeee20f80, 0xeff30fd1,
2618 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2619
2620 /* Vector VMINAV. */
2621 {ARM_FEATURE_COPROC (FPU_MVE),
2622 MVE_VMINAV,
2623 0xeee00f80, 0xfff30fd1,
2624 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2625
2626 /* Vector VMLA. */
2627 {ARM_FEATURE_COPROC (FPU_MVE),
2628 MVE_VMLA,
2629 0xee010e40, 0xef811f70,
2630 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2631
2632 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2633 opcode aliasing. */
2634 {ARM_FEATURE_COPROC (FPU_MVE),
2635 MVE_VMLALDAV,
2636 0xee801e00, 0xef801f51,
2637 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2638
2639 {ARM_FEATURE_COPROC (FPU_MVE),
2640 MVE_VMLALDAV,
2641 0xee800e00, 0xef801f51,
2642 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2643
2644 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2645 {ARM_FEATURE_COPROC (FPU_MVE),
2646 MVE_VMLADAV_T1,
2647 0xeef00e00, 0xeff01f51,
2648 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2649
2650 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2651 {ARM_FEATURE_COPROC (FPU_MVE),
2652 MVE_VMLADAV_T2,
2653 0xeef00f00, 0xeff11f51,
2654 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2655
2656 /* Vector VMLADAV T1 variant. */
2657 {ARM_FEATURE_COPROC (FPU_MVE),
2658 MVE_VMLADAV_T1,
2659 0xeef01e00, 0xeff01f51,
2660 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2661
2662 /* Vector VMLADAV T2 variant. */
2663 {ARM_FEATURE_COPROC (FPU_MVE),
2664 MVE_VMLADAV_T2,
2665 0xeef01f00, 0xeff11f51,
2666 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2667
2668 /* Vector VMLAS. */
2669 {ARM_FEATURE_COPROC (FPU_MVE),
2670 MVE_VMLAS,
2671 0xee011e40, 0xef811f70,
2672 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2673
2674 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2675 opcode aliasing. */
2676 {ARM_FEATURE_COPROC (FPU_MVE),
2677 MVE_VRMLSLDAVH,
2678 0xfe800e01, 0xff810f51,
2679 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2680
2681 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2682 opcdoe aliasing. */
2683 {ARM_FEATURE_COPROC (FPU_MVE),
2684 MVE_VMLSLDAV,
2685 0xee800e01, 0xff800f51,
2686 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2687
2688 /* Vector VMLSDAV T1 Variant. */
2689 {ARM_FEATURE_COPROC (FPU_MVE),
2690 MVE_VMLSDAV_T1,
2691 0xeef00e01, 0xfff00f51,
2692 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2693
2694 /* Vector VMLSDAV T2 Variant. */
2695 {ARM_FEATURE_COPROC (FPU_MVE),
2696 MVE_VMLSDAV_T2,
2697 0xfef00e01, 0xfff10f51,
2698 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2699
2700 /* Vector VMOV between gpr and half precision register, op == 0. */
2701 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2702 MVE_VMOV_HFP_TO_GP,
2703 0xee000910, 0xfff00f7f,
2704 "vmov.f16\t%7,16-19F, %12-15r"},
2705
2706 /* Vector VMOV between gpr and half precision register, op == 1. */
2707 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2708 MVE_VMOV_HFP_TO_GP,
2709 0xee100910, 0xfff00f7f,
2710 "vmov.f16\t%12-15r, %7,16-19F"},
2711
2712 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2713 MVE_VMOV_GP_TO_VEC_LANE,
2714 0xee000b10, 0xff900f1f,
2715 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2716
2717 /* Vector VORR immediate to vector.
2718 NOTE: MVE_VORR_IMM must appear in the table
2719 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2720 {ARM_FEATURE_COPROC (FPU_MVE),
2721 MVE_VORR_IMM,
2722 0xef800050, 0xefb810f0,
2723 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2724
2725 /* Vector VQSHL T2 Variant.
2726 NOTE: MVE_VQSHL_T2 must appear in the table before
2727 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2728 {ARM_FEATURE_COPROC (FPU_MVE),
2729 MVE_VQSHL_T2,
2730 0xef800750, 0xef801fd1,
2731 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2732
2733 /* Vector VQSHLU T3 Variant
2734 NOTE: MVE_VQSHL_T2 must appear in the table before
2735 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2736
2737 {ARM_FEATURE_COPROC (FPU_MVE),
2738 MVE_VQSHLU_T3,
2739 0xff800650, 0xff801fd1,
2740 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2741
2742 /* Vector VRSHR
2743 NOTE: MVE_VRSHR must appear in the table before
2744 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2745 {ARM_FEATURE_COPROC (FPU_MVE),
2746 MVE_VRSHR,
2747 0xef800250, 0xef801fd1,
2748 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2749
2750 /* Vector VSHL.
2751 NOTE: MVE_VSHL must appear in the table before
2752 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2753 {ARM_FEATURE_COPROC (FPU_MVE),
2754 MVE_VSHL_T1,
2755 0xef800550, 0xff801fd1,
2756 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2757
2758 /* Vector VSHR
2759 NOTE: MVE_VSHR must appear in the table before
2760 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2761 {ARM_FEATURE_COPROC (FPU_MVE),
2762 MVE_VSHR,
2763 0xef800050, 0xef801fd1,
2764 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2765
2766 /* Vector VSLI
2767 NOTE: MVE_VSLI must appear in the table before
2768 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2769 {ARM_FEATURE_COPROC (FPU_MVE),
2770 MVE_VSLI,
2771 0xff800550, 0xff801fd1,
2772 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2773
2774 /* Vector VSRI
2775 NOTE: MVE_VSRI must appear in the table before
2776 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2777 {ARM_FEATURE_COPROC (FPU_MVE),
2778 MVE_VSRI,
2779 0xff800450, 0xff801fd1,
2780 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2781
2782 /* Vector VMOV immediate to vector,
2783 cmode == 11x1 -> VMVN which is UNDEFINED
2784 for such a cmode. */
2785 {ARM_FEATURE_COPROC (FPU_MVE),
2786 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2787
2788 /* Vector VMOV immediate to vector. */
2789 {ARM_FEATURE_COPROC (FPU_MVE),
2790 MVE_VMOV_IMM_TO_VEC,
2791 0xef800050, 0xefb810d0,
2792 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2793
2794 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2795 {ARM_FEATURE_COPROC (FPU_MVE),
2796 MVE_VMOV2_VEC_LANE_TO_GP,
2797 0xec000f00, 0xffb01ff0,
2798 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2799
2800 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2801 {ARM_FEATURE_COPROC (FPU_MVE),
2802 MVE_VMOV2_VEC_LANE_TO_GP,
2803 0xec000f10, 0xffb01ff0,
2804 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2805
2806 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2807 {ARM_FEATURE_COPROC (FPU_MVE),
2808 MVE_VMOV2_GP_TO_VEC_LANE,
2809 0xec100f00, 0xffb01ff0,
2810 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2811
2812 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2813 {ARM_FEATURE_COPROC (FPU_MVE),
2814 MVE_VMOV2_GP_TO_VEC_LANE,
2815 0xec100f10, 0xffb01ff0,
2816 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2817
2818 /* Vector VMOV Vector lane to gpr. */
2819 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2820 MVE_VMOV_VEC_LANE_TO_GP,
2821 0xee100b10, 0xff100f1f,
2822 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2823
2824 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2825 to instruction opcode aliasing. */
2826 {ARM_FEATURE_COPROC (FPU_MVE),
2827 MVE_VSHLL_T1,
2828 0xeea00f40, 0xefa00fd1,
2829 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2830
2831 /* Vector VMOVL long. */
2832 {ARM_FEATURE_COPROC (FPU_MVE),
2833 MVE_VMOVL,
2834 0xeea00f40, 0xefa70fd1,
2835 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2836
2837 /* Vector VMOV and narrow. */
2838 {ARM_FEATURE_COPROC (FPU_MVE),
2839 MVE_VMOVN,
2840 0xfe310e81, 0xffb30fd1,
2841 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2842
2843 /* Floating point move extract. */
2844 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2845 MVE_VMOVX,
2846 0xfeb00a40, 0xffbf0fd0,
2847 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2848
2849 /* Vector VMUL floating-point T1 variant. */
2850 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2851 MVE_VMUL_FP_T1,
2852 0xff000d50, 0xffa11f51,
2853 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2854
2855 /* Vector VMUL floating-point T2 variant. */
2856 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2857 MVE_VMUL_FP_T2,
2858 0xee310e60, 0xefb11f70,
2859 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2860
2861 /* Vector VMUL T1 variant. */
2862 {ARM_FEATURE_COPROC (FPU_MVE),
2863 MVE_VMUL_VEC_T1,
2864 0xef000950, 0xff811f51,
2865 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2866
2867 /* Vector VMUL T2 variant. */
2868 {ARM_FEATURE_COPROC (FPU_MVE),
2869 MVE_VMUL_VEC_T2,
2870 0xee011e60, 0xff811f70,
2871 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2872
2873 /* Vector VMULH. */
2874 {ARM_FEATURE_COPROC (FPU_MVE),
2875 MVE_VMULH,
2876 0xee010e01, 0xef811f51,
2877 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2878
2879 /* Vector VRMULH. */
2880 {ARM_FEATURE_COPROC (FPU_MVE),
2881 MVE_VRMULH,
2882 0xee011e01, 0xef811f51,
2883 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2884
2885 /* Vector VMULL integer. */
2886 {ARM_FEATURE_COPROC (FPU_MVE),
2887 MVE_VMULL_INT,
2888 0xee010e00, 0xef810f51,
2889 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2890
2891 /* Vector VMULL polynomial. */
2892 {ARM_FEATURE_COPROC (FPU_MVE),
2893 MVE_VMULL_POLY,
2894 0xee310e00, 0xefb10f51,
2895 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2896
2897 /* Vector VMVN immediate to vector. */
2898 {ARM_FEATURE_COPROC (FPU_MVE),
2899 MVE_VMVN_IMM,
2900 0xef800070, 0xefb810f0,
2901 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2902
2903 /* Vector VMVN register. */
2904 {ARM_FEATURE_COPROC (FPU_MVE),
2905 MVE_VMVN_REG,
2906 0xffb005c0, 0xffbf1fd1,
2907 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2908
2909 /* Vector VNEG floating point. */
2910 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2911 MVE_VNEG_FP,
2912 0xffb107c0, 0xffb31fd1,
2913 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2914
2915 /* Vector VNEG. */
2916 {ARM_FEATURE_COPROC (FPU_MVE),
2917 MVE_VNEG_VEC,
2918 0xffb103c0, 0xffb31fd1,
2919 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2920
2921 /* Vector VORN, vector bitwise or not. */
2922 {ARM_FEATURE_COPROC (FPU_MVE),
2923 MVE_VORN,
2924 0xef300150, 0xffb11f51,
2925 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2926
2927 /* Vector VORR register. */
2928 {ARM_FEATURE_COPROC (FPU_MVE),
2929 MVE_VORR_REG,
2930 0xef200150, 0xffb11f51,
2931 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2932
2933 /* Vector VQDMULL T1 variant. */
2934 {ARM_FEATURE_COPROC (FPU_MVE),
2935 MVE_VQDMULL_T1,
2936 0xee300f01, 0xefb10f51,
2937 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2938
2939 /* Vector VPNOT. */
2940 {ARM_FEATURE_COPROC (FPU_MVE),
2941 MVE_VPNOT,
2942 0xfe310f4d, 0xffffffff,
2943 "vpnot%v"},
2944
2945 /* Vector VPSEL. */
2946 {ARM_FEATURE_COPROC (FPU_MVE),
2947 MVE_VPSEL,
2948 0xfe310f01, 0xffb11f51,
2949 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2950
2951 /* Vector VQABS. */
2952 {ARM_FEATURE_COPROC (FPU_MVE),
2953 MVE_VQABS,
2954 0xffb00740, 0xffb31fd1,
2955 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2956
2957 /* Vector VQADD T1 variant. */
2958 {ARM_FEATURE_COPROC (FPU_MVE),
2959 MVE_VQADD_T1,
2960 0xef000050, 0xef811f51,
2961 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2962
2963 /* Vector VQADD T2 variant. */
2964 {ARM_FEATURE_COPROC (FPU_MVE),
2965 MVE_VQADD_T2,
2966 0xee000f60, 0xef811f70,
2967 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2968
2969 /* Vector VQDMULL T2 variant. */
2970 {ARM_FEATURE_COPROC (FPU_MVE),
2971 MVE_VQDMULL_T2,
2972 0xee300f60, 0xefb10f70,
2973 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2974
2975 /* Vector VQMOVN. */
2976 {ARM_FEATURE_COPROC (FPU_MVE),
2977 MVE_VQMOVN,
2978 0xee330e01, 0xefb30fd1,
2979 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2980
2981 /* Vector VQMOVUN. */
2982 {ARM_FEATURE_COPROC (FPU_MVE),
2983 MVE_VQMOVUN,
2984 0xee310e81, 0xffb30fd1,
2985 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2986
2987 /* Vector VQDMLADH. */
2988 {ARM_FEATURE_COPROC (FPU_MVE),
2989 MVE_VQDMLADH,
2990 0xee000e00, 0xff810f51,
2991 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2992
2993 /* Vector VQRDMLADH. */
2994 {ARM_FEATURE_COPROC (FPU_MVE),
2995 MVE_VQRDMLADH,
2996 0xee000e01, 0xff810f51,
2997 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2998
2999 /* Vector VQDMLAH. */
3000 {ARM_FEATURE_COPROC (FPU_MVE),
3001 MVE_VQDMLAH,
3002 0xee000e60, 0xef811f70,
3003 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3004
3005 /* Vector VQRDMLAH. */
3006 {ARM_FEATURE_COPROC (FPU_MVE),
3007 MVE_VQRDMLAH,
3008 0xee000e40, 0xef811f70,
3009 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3010
3011 /* Vector VQDMLASH. */
3012 {ARM_FEATURE_COPROC (FPU_MVE),
3013 MVE_VQDMLASH,
3014 0xee001e60, 0xef811f70,
3015 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3016
3017 /* Vector VQRDMLASH. */
3018 {ARM_FEATURE_COPROC (FPU_MVE),
3019 MVE_VQRDMLASH,
3020 0xee001e40, 0xef811f70,
3021 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3022
3023 /* Vector VQDMLSDH. */
3024 {ARM_FEATURE_COPROC (FPU_MVE),
3025 MVE_VQDMLSDH,
3026 0xfe000e00, 0xff810f51,
3027 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3028
3029 /* Vector VQRDMLSDH. */
3030 {ARM_FEATURE_COPROC (FPU_MVE),
3031 MVE_VQRDMLSDH,
3032 0xfe000e01, 0xff810f51,
3033 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3034
3035 /* Vector VQDMULH T1 variant. */
3036 {ARM_FEATURE_COPROC (FPU_MVE),
3037 MVE_VQDMULH_T1,
3038 0xef000b40, 0xff811f51,
3039 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3040
3041 /* Vector VQRDMULH T2 variant. */
3042 {ARM_FEATURE_COPROC (FPU_MVE),
3043 MVE_VQRDMULH_T2,
3044 0xff000b40, 0xff811f51,
3045 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3046
3047 /* Vector VQDMULH T3 variant. */
3048 {ARM_FEATURE_COPROC (FPU_MVE),
3049 MVE_VQDMULH_T3,
3050 0xee010e60, 0xff811f70,
3051 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3052
3053 /* Vector VQRDMULH T4 variant. */
3054 {ARM_FEATURE_COPROC (FPU_MVE),
3055 MVE_VQRDMULH_T4,
3056 0xfe010e60, 0xff811f70,
3057 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3058
3059 /* Vector VQNEG. */
3060 {ARM_FEATURE_COPROC (FPU_MVE),
3061 MVE_VQNEG,
3062 0xffb007c0, 0xffb31fd1,
3063 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3064
3065 /* Vector VQRSHL T1 variant. */
3066 {ARM_FEATURE_COPROC (FPU_MVE),
3067 MVE_VQRSHL_T1,
3068 0xef000550, 0xef811f51,
3069 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3070
3071 /* Vector VQRSHL T2 variant. */
3072 {ARM_FEATURE_COPROC (FPU_MVE),
3073 MVE_VQRSHL_T2,
3074 0xee331ee0, 0xefb31ff0,
3075 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3076
3077 /* Vector VQRSHRN. */
3078 {ARM_FEATURE_COPROC (FPU_MVE),
3079 MVE_VQRSHRN,
3080 0xee800f41, 0xefa00fd1,
3081 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3082
3083 /* Vector VQRSHRUN. */
3084 {ARM_FEATURE_COPROC (FPU_MVE),
3085 MVE_VQRSHRUN,
3086 0xfe800fc0, 0xffa00fd1,
3087 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3088
3089 /* Vector VQSHL T1 Variant. */
3090 {ARM_FEATURE_COPROC (FPU_MVE),
3091 MVE_VQSHL_T1,
3092 0xee311ee0, 0xefb31ff0,
3093 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3094
3095 /* Vector VQSHL T4 Variant. */
3096 {ARM_FEATURE_COPROC (FPU_MVE),
3097 MVE_VQSHL_T4,
3098 0xef000450, 0xef811f51,
3099 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3100
3101 /* Vector VQSHRN. */
3102 {ARM_FEATURE_COPROC (FPU_MVE),
3103 MVE_VQSHRN,
3104 0xee800f40, 0xefa00fd1,
3105 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3106
3107 /* Vector VQSHRUN. */
3108 {ARM_FEATURE_COPROC (FPU_MVE),
3109 MVE_VQSHRUN,
3110 0xee800fc0, 0xffa00fd1,
3111 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3112
3113 /* Vector VQSUB T1 Variant. */
3114 {ARM_FEATURE_COPROC (FPU_MVE),
3115 MVE_VQSUB_T1,
3116 0xef000250, 0xef811f51,
3117 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3118
3119 /* Vector VQSUB T2 Variant. */
3120 {ARM_FEATURE_COPROC (FPU_MVE),
3121 MVE_VQSUB_T2,
3122 0xee001f60, 0xef811f70,
3123 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3124
3125 /* Vector VREV16. */
3126 {ARM_FEATURE_COPROC (FPU_MVE),
3127 MVE_VREV16,
3128 0xffb00140, 0xffb31fd1,
3129 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3130
3131 /* Vector VREV32. */
3132 {ARM_FEATURE_COPROC (FPU_MVE),
3133 MVE_VREV32,
3134 0xffb000c0, 0xffb31fd1,
3135 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3136
3137 /* Vector VREV64. */
3138 {ARM_FEATURE_COPROC (FPU_MVE),
3139 MVE_VREV64,
3140 0xffb00040, 0xffb31fd1,
3141 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3142
3143 /* Vector VRINT floating point. */
3144 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3145 MVE_VRINT_FP,
3146 0xffb20440, 0xffb31c51,
3147 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3148
3149 /* Vector VRMLALDAVH. */
3150 {ARM_FEATURE_COPROC (FPU_MVE),
3151 MVE_VRMLALDAVH,
3152 0xee800f00, 0xef811f51,
3153 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3154
3155 /* Vector VRMLALDAVH. */
3156 {ARM_FEATURE_COPROC (FPU_MVE),
3157 MVE_VRMLALDAVH,
3158 0xee801f00, 0xef811f51,
3159 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3160
3161 /* Vector VRSHL T1 Variant. */
3162 {ARM_FEATURE_COPROC (FPU_MVE),
3163 MVE_VRSHL_T1,
3164 0xef000540, 0xef811f51,
3165 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3166
3167 /* Vector VRSHL T2 Variant. */
3168 {ARM_FEATURE_COPROC (FPU_MVE),
3169 MVE_VRSHL_T2,
3170 0xee331e60, 0xefb31ff0,
3171 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3172
3173 /* Vector VRSHRN. */
3174 {ARM_FEATURE_COPROC (FPU_MVE),
3175 MVE_VRSHRN,
3176 0xfe800fc1, 0xffa00fd1,
3177 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3178
3179 /* Vector VSBC. */
3180 {ARM_FEATURE_COPROC (FPU_MVE),
3181 MVE_VSBC,
3182 0xfe300f00, 0xffb10f51,
3183 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3184
3185 /* Vector VSHL T2 Variant. */
3186 {ARM_FEATURE_COPROC (FPU_MVE),
3187 MVE_VSHL_T2,
3188 0xee311e60, 0xefb31ff0,
3189 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3190
3191 /* Vector VSHL T3 Variant. */
3192 {ARM_FEATURE_COPROC (FPU_MVE),
3193 MVE_VSHL_T3,
3194 0xef000440, 0xef811f51,
3195 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3196
3197 /* Vector VSHLC. */
3198 {ARM_FEATURE_COPROC (FPU_MVE),
3199 MVE_VSHLC,
3200 0xeea00fc0, 0xffa01ff0,
3201 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3202
3203 /* Vector VSHLL T2 Variant. */
3204 {ARM_FEATURE_COPROC (FPU_MVE),
3205 MVE_VSHLL_T2,
3206 0xee310e01, 0xefb30fd1,
3207 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3208
3209 /* Vector VSHRN. */
3210 {ARM_FEATURE_COPROC (FPU_MVE),
3211 MVE_VSHRN,
3212 0xee800fc1, 0xffa00fd1,
3213 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3214
3215 /* Vector VST2 no writeback. */
3216 {ARM_FEATURE_COPROC (FPU_MVE),
3217 MVE_VST2,
3218 0xfc801e00, 0xffb01e5f,
3219 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3220
3221 /* Vector VST2 writeback. */
3222 {ARM_FEATURE_COPROC (FPU_MVE),
3223 MVE_VST2,
3224 0xfca01e00, 0xffb01e5f,
3225 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3226
3227 /* Vector VST4 no writeback. */
3228 {ARM_FEATURE_COPROC (FPU_MVE),
3229 MVE_VST4,
3230 0xfc801e01, 0xffb01e1f,
3231 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3232
3233 /* Vector VST4 writeback. */
3234 {ARM_FEATURE_COPROC (FPU_MVE),
3235 MVE_VST4,
3236 0xfca01e01, 0xffb01e1f,
3237 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3238
3239 /* Vector VSTRB scatter store, T1 variant. */
3240 {ARM_FEATURE_COPROC (FPU_MVE),
3241 MVE_VSTRB_SCATTER_T1,
3242 0xec800e00, 0xffb01e50,
3243 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3244
3245 /* Vector VSTRH scatter store, T2 variant. */
3246 {ARM_FEATURE_COPROC (FPU_MVE),
3247 MVE_VSTRH_SCATTER_T2,
3248 0xec800e10, 0xffb01e50,
3249 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3250
3251 /* Vector VSTRW scatter store, T3 variant. */
3252 {ARM_FEATURE_COPROC (FPU_MVE),
3253 MVE_VSTRW_SCATTER_T3,
3254 0xec800e40, 0xffb01e50,
3255 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3256
3257 /* Vector VSTRD scatter store, T4 variant. */
3258 {ARM_FEATURE_COPROC (FPU_MVE),
3259 MVE_VSTRD_SCATTER_T4,
3260 0xec800fd0, 0xffb01fd0,
3261 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3262
3263 /* Vector VSTRW scatter store, T5 variant. */
3264 {ARM_FEATURE_COPROC (FPU_MVE),
3265 MVE_VSTRW_SCATTER_T5,
3266 0xfd001e00, 0xff111f00,
3267 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3268
3269 /* Vector VSTRD scatter store, T6 variant. */
3270 {ARM_FEATURE_COPROC (FPU_MVE),
3271 MVE_VSTRD_SCATTER_T6,
3272 0xfd001f00, 0xff111f00,
3273 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3274
3275 /* Vector VSTRB. */
3276 {ARM_FEATURE_COPROC (FPU_MVE),
3277 MVE_VSTRB_T1,
3278 0xec000e00, 0xfe581e00,
3279 "vstrb%v.%7-8s\t%13-15Q, %d"},
3280
3281 /* Vector VSTRH. */
3282 {ARM_FEATURE_COPROC (FPU_MVE),
3283 MVE_VSTRH_T2,
3284 0xec080e00, 0xfe581e00,
3285 "vstrh%v.%7-8s\t%13-15Q, %d"},
3286
3287 /* Vector VSTRB variant T5. */
3288 {ARM_FEATURE_COPROC (FPU_MVE),
3289 MVE_VSTRB_T5,
3290 0xec001e00, 0xfe101f80,
3291 "vstrb%v.8\t%13-15,22Q, %d"},
3292
3293 /* Vector VSTRH variant T6. */
3294 {ARM_FEATURE_COPROC (FPU_MVE),
3295 MVE_VSTRH_T6,
3296 0xec001e80, 0xfe101f80,
3297 "vstrh%v.16\t%13-15,22Q, %d"},
3298
3299 /* Vector VSTRW variant T7. */
3300 {ARM_FEATURE_COPROC (FPU_MVE),
3301 MVE_VSTRW_T7,
3302 0xec001f00, 0xfe101f80,
3303 "vstrw%v.32\t%13-15,22Q, %d"},
3304
3305 /* Vector VSUB floating point T1 variant. */
3306 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3307 MVE_VSUB_FP_T1,
3308 0xef200d40, 0xffa11f51,
3309 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3310
3311 /* Vector VSUB floating point T2 variant. */
3312 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3313 MVE_VSUB_FP_T2,
3314 0xee301f40, 0xefb11f70,
3315 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3316
3317 /* Vector VSUB T1 variant. */
3318 {ARM_FEATURE_COPROC (FPU_MVE),
3319 MVE_VSUB_VEC_T1,
3320 0xff000840, 0xff811f51,
3321 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3322
3323 /* Vector VSUB T2 variant. */
3324 {ARM_FEATURE_COPROC (FPU_MVE),
3325 MVE_VSUB_VEC_T2,
3326 0xee011f40, 0xff811f70,
3327 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3328
3329 {ARM_FEATURE_COPROC (FPU_MVE),
3330 MVE_ASRLI,
3331 0xea50012f, 0xfff1813f,
3332 "asrl%c\t%17-19l, %9-11h, %j"},
3333
3334 {ARM_FEATURE_COPROC (FPU_MVE),
3335 MVE_ASRL,
3336 0xea50012d, 0xfff101ff,
3337 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3338
3339 {ARM_FEATURE_COPROC (FPU_MVE),
3340 MVE_LSLLI,
3341 0xea50010f, 0xfff1813f,
3342 "lsll%c\t%17-19l, %9-11h, %j"},
3343
3344 {ARM_FEATURE_COPROC (FPU_MVE),
3345 MVE_LSLL,
3346 0xea50010d, 0xfff101ff,
3347 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3348
3349 {ARM_FEATURE_COPROC (FPU_MVE),
3350 MVE_LSRL,
3351 0xea50011f, 0xfff1813f,
3352 "lsrl%c\t%17-19l, %9-11h, %j"},
3353
3354 {ARM_FEATURE_COPROC (FPU_MVE),
3355 MVE_SQRSHRL,
3356 0xea51012d, 0xfff101ff,
3357 "sqrshrl%c\t%17-19l, %9-11h, %12-15S"},
3358
3359 {ARM_FEATURE_COPROC (FPU_MVE),
3360 MVE_SQRSHR,
3361 0xea500f2d, 0xfff00fff,
3362 "sqrshr%c\t%16-19S, %12-15S"},
3363
3364 {ARM_FEATURE_COPROC (FPU_MVE),
3365 MVE_SQSHLL,
3366 0xea51013f, 0xfff1813f,
3367 "sqshll%c\t%17-19l, %9-11h, %j"},
3368
3369 {ARM_FEATURE_COPROC (FPU_MVE),
3370 MVE_SQSHL,
3371 0xea500f3f, 0xfff08f3f,
3372 "sqshl%c\t%16-19S, %j"},
3373
3374 {ARM_FEATURE_COPROC (FPU_MVE),
3375 MVE_SRSHRL,
3376 0xea51012f, 0xfff1813f,
3377 "srshrl%c\t%17-19l, %9-11h, %j"},
3378
3379 {ARM_FEATURE_COPROC (FPU_MVE),
3380 MVE_SRSHR,
3381 0xea500f2f, 0xfff08f3f,
3382 "srshr%c\t%16-19S, %j"},
3383
3384 {ARM_FEATURE_COPROC (FPU_MVE),
3385 MVE_UQRSHLL,
3386 0xea51010d, 0xfff101ff,
3387 "uqrshll%c\t%17-19l, %9-11h, %12-15S"},
3388
3389 {ARM_FEATURE_COPROC (FPU_MVE),
3390 MVE_UQRSHL,
3391 0xea500f0d, 0xfff00fff,
3392 "uqrshl%c\t%16-19S, %12-15S"},
3393
3394 {ARM_FEATURE_COPROC (FPU_MVE),
3395 MVE_UQSHLL,
3396 0xea51010f, 0xfff1813f,
3397 "uqshll%c\t%17-19l, %9-11h, %j"},
3398
3399 {ARM_FEATURE_COPROC (FPU_MVE),
3400 MVE_UQSHL,
3401 0xea500f0f, 0xfff08f3f,
3402 "uqshl%c\t%16-19S, %j"},
3403
3404 {ARM_FEATURE_COPROC (FPU_MVE),
3405 MVE_URSHRL,
3406 0xea51011f, 0xfff1813f,
3407 "urshrl%c\t%17-19l, %9-11h, %j"},
3408
3409 {ARM_FEATURE_COPROC (FPU_MVE),
3410 MVE_URSHR,
3411 0xea500f1f, 0xfff08f3f,
3412 "urshr%c\t%16-19S, %j"},
3413
3414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3415 MVE_CSINC,
3416 0xea509000, 0xfff0f000,
3417 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3418
3419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3420 MVE_CSINV,
3421 0xea50a000, 0xfff0f000,
3422 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3423
3424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3425 MVE_CSET,
3426 0xea5f900f, 0xfffff00f,
3427 "cset\t%8-11S, %4-7C"},
3428
3429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3430 MVE_CSETM,
3431 0xea5fa00f, 0xfffff00f,
3432 "csetm\t%8-11S, %4-7C"},
3433
3434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3435 MVE_CSEL,
3436 0xea508000, 0xfff0f000,
3437 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3438
3439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3440 MVE_CSNEG,
3441 0xea50b000, 0xfff0f000,
3442 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3443
3444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3445 MVE_CINC,
3446 0xea509000, 0xfff0f000,
3447 "cinc\t%8-11S, %16-19Z, %4-7C"},
3448
3449 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3450 MVE_CINV,
3451 0xea50a000, 0xfff0f000,
3452 "cinv\t%8-11S, %16-19Z, %4-7C"},
3453
3454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3455 MVE_CNEG,
3456 0xea50b000, 0xfff0f000,
3457 "cneg\t%8-11S, %16-19Z, %4-7C"},
3458
3459 {ARM_FEATURE_CORE_LOW (0),
3460 MVE_NONE,
3461 0x00000000, 0x00000000, 0}
3462 };
3463
3464 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3465 ordered: they must be searched linearly from the top to obtain a correct
3466 match. */
3467
3468 /* print_insn_arm recognizes the following format control codes:
3469
3470 %% %
3471
3472 %a print address for ldr/str instruction
3473 %s print address for ldr/str halfword/signextend instruction
3474 %S like %s but allow UNPREDICTABLE addressing
3475 %b print branch destination
3476 %c print condition code (always bits 28-31)
3477 %m print register mask for ldm/stm instruction
3478 %o print operand2 (immediate or register + shift)
3479 %p print 'p' iff bits 12-15 are 15
3480 %t print 't' iff bit 21 set and bit 24 clear
3481 %B print arm BLX(1) destination
3482 %C print the PSR sub type.
3483 %U print barrier type.
3484 %P print address for pli instruction.
3485
3486 %<bitfield>r print as an ARM register
3487 %<bitfield>T print as an ARM register + 1
3488 %<bitfield>R as %r but r15 is UNPREDICTABLE
3489 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3490 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3491 %<bitfield>d print the bitfield in decimal
3492 %<bitfield>W print the bitfield plus one in decimal
3493 %<bitfield>x print the bitfield in hex
3494 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3495
3496 %<bitfield>'c print specified char iff bitfield is all ones
3497 %<bitfield>`c print specified char iff bitfield is all zeroes
3498 %<bitfield>?ab... select from array of values in big endian order
3499
3500 %e print arm SMI operand (bits 0..7,8..19).
3501 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3502 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3503 %R print the SPSR/CPSR or banked register of an MRS. */
3504
3505 static const struct opcode32 arm_opcodes[] =
3506 {
3507 /* ARM instructions. */
3508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3509 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3511 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3512
3513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3514 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3516 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3518 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3520 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3522 0x00800090, 0x0fa000f0,
3523 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3525 0x00a00090, 0x0fa000f0,
3526 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3527
3528 /* V8.2 RAS extension instructions. */
3529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3530 0xe320f010, 0xffffffff, "esb"},
3531
3532 /* V8 instructions. */
3533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3534 0x0320f005, 0x0fffffff, "sevl"},
3535 /* Defined in V8 but is in NOP space so available to all arch. */
3536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3537 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3538 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
3539 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3541 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3543 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3545 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3546 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3547 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3548 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3549 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3550 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3551 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3552 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3553 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3555 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3557 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3559 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3561 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3562 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3563 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3564 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3565 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3566 /* CRC32 instructions. */
3567 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3568 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3569 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3570 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3571 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3572 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3573 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3574 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3575 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3576 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3577 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3578 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3579
3580 /* Privileged Access Never extension instructions. */
3581 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3582 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3583
3584 /* Virtualization Extension instructions. */
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3587
3588 /* Integer Divide Extension instructions. */
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3590 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3591 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3592 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3593
3594 /* MP Extension instructions. */
3595 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3596
3597 /* Speculation Barriers. */
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3601
3602 /* V7 instructions. */
3603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3611 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3612
3613 /* ARM V6T2 instructions. */
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3615 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3617 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3619 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3621 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3622
3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3624 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3626 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3627
3628 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3629 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3630 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3631 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3633 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3635 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3636
3637 /* ARM Security extension instructions. */
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3639 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3640
3641 /* ARM V6K instructions. */
3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3643 0xf57ff01f, 0xffffffff, "clrex"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3645 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3647 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3649 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3651 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3653 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3655 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3656
3657 /* ARMv8.5-A instructions. */
3658 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3659
3660 /* ARM V6K NOP hints. */
3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3662 0x0320f001, 0x0fffffff, "yield%c"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3664 0x0320f002, 0x0fffffff, "wfe%c"},
3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3666 0x0320f003, 0x0fffffff, "wfi%c"},
3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3668 0x0320f004, 0x0fffffff, "sev%c"},
3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3670 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3671
3672 /* ARM V6 instructions. */
3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3674 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3676 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3678 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3680 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3682 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3684 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3686 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3688 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3690 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3692 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3694 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3696 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3698 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3700 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3702 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3704 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3706 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3708 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3710 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3712 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3714 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3716 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3718 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3720 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3722 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3724 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3726 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3728 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3730 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3732 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3734 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3736 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3738 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3740 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3742 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3744 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3746 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3748 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3750 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3752 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3754 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3756 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3758 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3760 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3762 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3764 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3766 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3768 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3770 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3772 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3774 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3776 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3778 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3780 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3782 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3784 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3786 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3788 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3790 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3792 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3794 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3796 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3798 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3800 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3802 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3804 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3806 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3808 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3810 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3812 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3814 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3816 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3818 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3820 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3822 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3824 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3826 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3828 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3830 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3832 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3834 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3836 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3838 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3840 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3842 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3844 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3846 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3848 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3850 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3852 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3854 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3856 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3858 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3860 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3862 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3864 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3866 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3868 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3870 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3872 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3874 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3876 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3878 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3880 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3882 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3884 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3886 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3888 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3890 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3892 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3894 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3896 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3898 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3900 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3902 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3904 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3906 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3908 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3910 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3912 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3914 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3916 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3917
3918 /* V5J instruction. */
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3920 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3921
3922 /* V5 Instructions. */
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3924 0xe1200070, 0xfff000f0,
3925 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3927 0xfa000000, 0xfe000000, "blx\t%B"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3929 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3931 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3932
3933 /* V5E "El Segundo" Instructions. */
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3935 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3937 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3939 0xf450f000, 0xfc70f000, "pld\t%a"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3941 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3943 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3945 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3947 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3948
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3950 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3952 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3953
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3955 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3957 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3959 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3961 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3962
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3964 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3966 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3968 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3970 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3971
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3973 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3975 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3976
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3978 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3980 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3982 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3984 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3985
3986 /* ARM Instructions. */
3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3988 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3989
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3991 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3993 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3995 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3997 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3999 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4001 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4002
4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4004 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4006 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4008 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4010 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4011
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4013 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4015 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4017 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4019 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4020
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4022 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4024 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4026 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4027
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4029 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4031 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4033 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4034
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4036 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4038 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4040 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4041
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4043 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4045 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4047 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4048
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4050 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4052 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4054 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4055
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4057 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4059 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4061 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4062
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4064 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4066 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4068 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4069
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4071 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4073 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4075 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4076
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4078 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4080 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4082 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4083
4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4085 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4087 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4089 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4090
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4092 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4094 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4096 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4097
4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4099 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4101 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4103 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4104
4105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4106 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4108 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4110 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4111
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4113 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4115 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4117 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4118
4119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4120 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4122 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4124 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4126 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4128 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4130 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4132 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4133
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4135 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4137 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4139 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4140
4141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4142 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4144 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4146 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4147
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4149 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4151 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4152
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4154 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4155
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4157 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4160
4161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4162 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4164 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4166 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4168 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4170 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4172 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4174 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4176 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4178 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4180 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4182 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4190 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4192 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4194 0x092d0000, 0x0fff0000, "push%c\t%m"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4196 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4199
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4201 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4203 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4205 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4211 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4213 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4215 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4217 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4219 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4225 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4227 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4229 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4231 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4233 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4235 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4237 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4238
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4240 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4242 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4243
4244 /* The rest. */
4245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4246 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4248 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4249 {ARM_FEATURE_CORE_LOW (0),
4250 0x00000000, 0x00000000, 0}
4251 };
4252
4253 /* print_insn_thumb16 recognizes the following format control codes:
4254
4255 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4256 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4257 %<bitfield>I print bitfield as a signed decimal
4258 (top bit of range being the sign bit)
4259 %N print Thumb register mask (with LR)
4260 %O print Thumb register mask (with PC)
4261 %M print Thumb register mask
4262 %b print CZB's 6-bit unsigned branch destination
4263 %s print Thumb right-shift immediate (6..10; 0 == 32).
4264 %c print the condition code
4265 %C print the condition code, or "s" if not conditional
4266 %x print warning if conditional an not at end of IT block"
4267 %X print "\t; unpredictable <IT:code>" if conditional
4268 %I print IT instruction suffix and operands
4269 %W print Thumb Writeback indicator for LDMIA
4270 %<bitfield>r print bitfield as an ARM register
4271 %<bitfield>d print bitfield as a decimal
4272 %<bitfield>H print (bitfield * 2) as a decimal
4273 %<bitfield>W print (bitfield * 4) as a decimal
4274 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4275 %<bitfield>B print Thumb branch destination (signed displacement)
4276 %<bitfield>c print bitfield as a condition code
4277 %<bitnum>'c print specified char iff bit is one
4278 %<bitnum>?ab print a if bit is one else print b. */
4279
4280 static const struct opcode16 thumb_opcodes[] =
4281 {
4282 /* Thumb instructions. */
4283
4284 /* ARMv8-M Security Extensions instructions. */
4285 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
4286 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
4287
4288 /* ARM V8 instructions. */
4289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
4291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
4292
4293 /* ARM V6K no-argument instructions. */
4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4300
4301 /* ARM V6T2 instructions. */
4302 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4303 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4304 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4305 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
4307
4308 /* ARM V6. */
4309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4320
4321 /* ARM V5 ISA extends Thumb. */
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4323 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
4324 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
4325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4326 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
4327 /* ARM V4T ISA (Thumb v1). */
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4329 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4330 /* Format 4. */
4331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4347 /* format 13 */
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4350 /* format 5 */
4351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4355 /* format 14 */
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
4358 /* format 2 */
4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4360 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4362 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4364 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4366 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4367 /* format 8 */
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4369 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4371 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4373 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4374 /* format 7 */
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4376 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4378 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4379 /* format 1 */
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4382 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4385 /* format 3 */
4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4390 /* format 6 */
4391 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4393 0x4800, 0xF800,
4394 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4395 /* format 9 */
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4397 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4399 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4401 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4403 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4404 /* format 10 */
4405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4406 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4408 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4409 /* format 11 */
4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4411 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4413 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4414 /* format 12 */
4415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4416 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4418 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4419 /* format 15 */
4420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4422 /* format 17 */
4423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4424 /* format 16 */
4425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4428 /* format 18 */
4429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4430
4431 /* The E800 .. FFFF range is unconditionally redirected to the
4432 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4433 are processed via that table. Thus, we can never encounter a
4434 bare "second half of BL/BLX(1)" instruction here. */
4435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4436 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4437 };
4438
4439 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4440 We adopt the convention that hw1 is the high 16 bits of .value and
4441 .mask, hw2 the low 16 bits.
4442
4443 print_insn_thumb32 recognizes the following format control codes:
4444
4445 %% %
4446
4447 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4448 %M print a modified 12-bit immediate (same location)
4449 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4450 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4451 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
4452 %S print a possibly-shifted Rm
4453
4454 %L print address for a ldrd/strd instruction
4455 %a print the address of a plain load/store
4456 %w print the width and signedness of a core load/store
4457 %m print register mask for ldm/stm
4458 %n print register mask for clrm
4459
4460 %E print the lsb and width fields of a bfc/bfi instruction
4461 %F print the lsb and width fields of a sbfx/ubfx instruction
4462 %G print a fallback offset for Branch Future instructions
4463 %W print an offset for BF instruction
4464 %Y print an offset for BFL instruction
4465 %Z print an offset for BFCSEL instruction
4466 %Q print an offset for Low Overhead Loop instructions
4467 %P print an offset for Low Overhead Loop end instructions
4468 %b print a conditional branch offset
4469 %B print an unconditional branch offset
4470 %s print the shift field of an SSAT instruction
4471 %R print the rotation field of an SXT instruction
4472 %U print barrier type.
4473 %P print address for pli instruction.
4474 %c print the condition code
4475 %x print warning if conditional an not at end of IT block"
4476 %X print "\t; unpredictable <IT:code>" if conditional
4477
4478 %<bitfield>d print bitfield in decimal
4479 %<bitfield>D print bitfield plus one in decimal
4480 %<bitfield>W print bitfield*4 in decimal
4481 %<bitfield>r print bitfield as an ARM register
4482 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4483 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4484 %<bitfield>c print bitfield as a condition code
4485
4486 %<bitfield>'c print specified char iff bitfield is all ones
4487 %<bitfield>`c print specified char iff bitfield is all zeroes
4488 %<bitfield>?ab... select from array of values in big endian order
4489
4490 With one exception at the bottom (done because BL and BLX(1) need
4491 to come dead last), this table was machine-sorted first in
4492 decreasing order of number of bits set in the mask, then in
4493 increasing numeric order of mask, then in increasing numeric order
4494 of opcode. This order is not the clearest for a human reader, but
4495 is guaranteed never to catch a special-case bit pattern with a more
4496 general mask, which is important, because this instruction encoding
4497 makes heavy use of special-case bit patterns. */
4498 static const struct opcode32 thumb32_opcodes[] =
4499 {
4500 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4501 instructions. */
4502 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4503 0xf00fe001, 0xffffffff, "lctp%c"},
4504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4505 0xf02fc001, 0xfffff001, "le\t%P"},
4506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4507 0xf00fc001, 0xfffff001, "le\tlr, %P"},
4508 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4509 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4511 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4512 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4513 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4514 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4515 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4517 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4518
4519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4520 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4521 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4522 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4524 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4526 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4528 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4529
4530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4531 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4532
4533 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4536 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4538 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4540 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4542 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4543
4544 /* ARM V8.2 RAS extension instructions. */
4545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
4546 0xf3af8010, 0xffffffff, "esb"},
4547
4548 /* V8 instructions. */
4549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4550 0xf3af8005, 0xffffffff, "sevl%c.w"},
4551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4552 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4554 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4556 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4558 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4560 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4562 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4564 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4566 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4568 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4570 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4572 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4574 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4576 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4578 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4580 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4581
4582 /* CRC32 instructions. */
4583 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4584 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4585 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4586 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4587 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4588 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4589 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4590 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4591 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4592 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4593 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4594 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4595
4596 /* Speculation Barriers. */
4597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4600
4601 /* V7 instructions. */
4602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4609 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4610 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4611 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4612 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4613
4614 /* Virtualization Extension instructions. */
4615 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4616 /* We skip ERET as that is SUBS pc, lr, #0. */
4617
4618 /* MP Extension instructions. */
4619 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4620
4621 /* Security extension instructions. */
4622 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4623
4624 /* ARMv8.5-A instructions. */
4625 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4626
4627 /* Instructions defined in the basic V6T2 set. */
4628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4634 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4636
4637 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4638 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4640 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4642 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4644 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4646 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4648 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4650 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4652 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4654 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4656 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4658 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4660 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4662 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4664 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4665 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4666 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4668 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4670 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4672 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4674 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4676 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4678 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4680 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4682 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4684 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4686 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4688 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4690 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4692 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4694 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4696 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4698 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4700 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4702 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4704 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4706 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4708 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4710 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4712 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4714 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4716 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4718 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4720 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4722 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4724 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4726 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4728 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4730 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4732 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4734 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4736 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4738 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4740 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4742 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4744 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4746 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4748 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4750 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4752 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4754 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4756 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4758 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4760 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4762 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4764 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4766 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4768 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4770 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4772 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4774 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4776 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4778 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4780 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4782 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4784 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4786 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4788 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4790 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4792 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4794 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4796 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4798 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4800 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4802 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4804 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4806 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4808 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4810 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4812 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4814 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4816 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4818 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4822 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4824 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4828 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4830 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4832 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4834 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4836 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4838 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4840 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4842 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4844 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4846 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4848 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4850 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4852 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4854 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4858 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4860 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4861 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4862 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4864 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4866 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4868 0xf810f000, 0xff70f000, "pld%c\t%a"},
4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894 0xfb100000, 0xfff000c0,
4895 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4897 0xfbc00080, 0xfff000c0,
4898 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4900 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4906 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4908 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4909 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4910 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4912 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4914 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4916 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4918 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4920 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4922 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4924 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4930 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4934 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4936 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4938 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4940 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4942 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4944 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4946 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4948 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4950 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4952 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4954 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4956 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4958 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4960 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4962 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4964 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4966 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4968 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4970 0xe9400000, 0xff500000,
4971 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4973 0xe9500000, 0xff500000,
4974 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4976 0xe8600000, 0xff700000,
4977 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4979 0xe8700000, 0xff700000,
4980 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4982 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4984 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
4985
4986 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
4987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4988 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4990 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4992 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4994 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
4995
4996 /* These have been 32-bit since the invention of Thumb. */
4997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4998 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5000 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5001
5002 /* Fallback. */
5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5004 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5005 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5006 };
5007
5008 static const char *const arm_conditional[] =
5009 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5010 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5011
5012 static const char *const arm_fp_const[] =
5013 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5014
5015 static const char *const arm_shift[] =
5016 {"lsl", "lsr", "asr", "ror"};
5017
5018 typedef struct
5019 {
5020 const char *name;
5021 const char *description;
5022 const char *reg_names[16];
5023 }
5024 arm_regname;
5025
5026 static const arm_regname regnames[] =
5027 {
5028 { "reg-names-raw", N_("Select raw register names"),
5029 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5030 { "reg-names-gcc", N_("Select register names used by GCC"),
5031 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
5032 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5033 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
5034 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5035 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5036 { "reg-names-apcs", N_("Select register names used in the APCS"),
5037 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
5038 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5039 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
5040 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5041 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
5042 };
5043
5044 static const char *const iwmmxt_wwnames[] =
5045 {"b", "h", "w", "d"};
5046
5047 static const char *const iwmmxt_wwssnames[] =
5048 {"b", "bus", "bc", "bss",
5049 "h", "hus", "hc", "hss",
5050 "w", "wus", "wc", "wss",
5051 "d", "dus", "dc", "dss"
5052 };
5053
5054 static const char *const iwmmxt_regnames[] =
5055 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5056 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5057 };
5058
5059 static const char *const iwmmxt_cregnames[] =
5060 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5061 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5062 };
5063
5064 static const char *const vec_condnames[] =
5065 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5066 };
5067
5068 static const char *const mve_predicatenames[] =
5069 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5070 "eee", "ee", "eet", "e", "ett", "et", "ete"
5071 };
5072
5073 /* Names for 2-bit size field for mve vector isntructions. */
5074 static const char *const mve_vec_sizename[] =
5075 { "8", "16", "32", "64"};
5076
5077 /* Indicates whether we are processing a then predicate,
5078 else predicate or none at all. */
5079 enum vpt_pred_state
5080 {
5081 PRED_NONE,
5082 PRED_THEN,
5083 PRED_ELSE
5084 };
5085
5086 /* Information used to process a vpt block and subsequent instructions. */
5087 struct vpt_block
5088 {
5089 /* Are we in a vpt block. */
5090 bfd_boolean in_vpt_block;
5091
5092 /* Next predicate state if in vpt block. */
5093 enum vpt_pred_state next_pred_state;
5094
5095 /* Mask from vpt/vpst instruction. */
5096 long predicate_mask;
5097
5098 /* Instruction number in vpt block. */
5099 long current_insn_num;
5100
5101 /* Number of instructions in vpt block.. */
5102 long num_pred_insn;
5103 };
5104
5105 static struct vpt_block vpt_block_state =
5106 {
5107 FALSE,
5108 PRED_NONE,
5109 0,
5110 0,
5111 0
5112 };
5113
5114 /* Default to GCC register name set. */
5115 static unsigned int regname_selected = 1;
5116
5117 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
5118 #define arm_regnames regnames[regname_selected].reg_names
5119
5120 static bfd_boolean force_thumb = FALSE;
5121
5122 /* Current IT instruction state. This contains the same state as the IT
5123 bits in the CPSR. */
5124 static unsigned int ifthen_state;
5125 /* IT state for the next instruction. */
5126 static unsigned int ifthen_next_state;
5127 /* The address of the insn for which the IT state is valid. */
5128 static bfd_vma ifthen_address;
5129 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5130 /* Indicates that the current Conditional state is unconditional or outside
5131 an IT block. */
5132 #define COND_UNCOND 16
5133
5134 \f
5135 /* Functions. */
5136 /* Extract the predicate mask for a VPT or VPST instruction.
5137 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5138
5139 static long
5140 mve_extract_pred_mask (long given)
5141 {
5142 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5143 }
5144
5145 /* Return the number of instructions in a MVE predicate block. */
5146 static long
5147 num_instructions_vpt_block (long given)
5148 {
5149 long mask = mve_extract_pred_mask (given);
5150 if (mask == 0)
5151 return 0;
5152
5153 if (mask == 8)
5154 return 1;
5155
5156 if ((mask & 7) == 4)
5157 return 2;
5158
5159 if ((mask & 3) == 2)
5160 return 3;
5161
5162 if ((mask & 1) == 1)
5163 return 4;
5164
5165 return 0;
5166 }
5167
5168 static void
5169 mark_outside_vpt_block (void)
5170 {
5171 vpt_block_state.in_vpt_block = FALSE;
5172 vpt_block_state.next_pred_state = PRED_NONE;
5173 vpt_block_state.predicate_mask = 0;
5174 vpt_block_state.current_insn_num = 0;
5175 vpt_block_state.num_pred_insn = 0;
5176 }
5177
5178 static void
5179 mark_inside_vpt_block (long given)
5180 {
5181 vpt_block_state.in_vpt_block = TRUE;
5182 vpt_block_state.next_pred_state = PRED_THEN;
5183 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5184 vpt_block_state.current_insn_num = 0;
5185 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5186 assert (vpt_block_state.num_pred_insn >= 1);
5187 }
5188
5189 static enum vpt_pred_state
5190 invert_next_predicate_state (enum vpt_pred_state astate)
5191 {
5192 if (astate == PRED_THEN)
5193 return PRED_ELSE;
5194 else if (astate == PRED_ELSE)
5195 return PRED_THEN;
5196 else
5197 return PRED_NONE;
5198 }
5199
5200 static enum vpt_pred_state
5201 update_next_predicate_state (void)
5202 {
5203 long pred_mask = vpt_block_state.predicate_mask;
5204 long mask_for_insn = 0;
5205
5206 switch (vpt_block_state.current_insn_num)
5207 {
5208 case 1:
5209 mask_for_insn = 8;
5210 break;
5211
5212 case 2:
5213 mask_for_insn = 4;
5214 break;
5215
5216 case 3:
5217 mask_for_insn = 2;
5218 break;
5219
5220 case 4:
5221 return PRED_NONE;
5222 }
5223
5224 if (pred_mask & mask_for_insn)
5225 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5226 else
5227 return vpt_block_state.next_pred_state;
5228 }
5229
5230 static void
5231 update_vpt_block_state (void)
5232 {
5233 vpt_block_state.current_insn_num++;
5234 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5235 {
5236 /* No more instructions to process in vpt block. */
5237 mark_outside_vpt_block ();
5238 return;
5239 }
5240
5241 vpt_block_state.next_pred_state = update_next_predicate_state ();
5242 }
5243
5244 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5245 Returns pointer to following character of the format string and
5246 fills in *VALUEP and *WIDTHP with the extracted value and number of
5247 bits extracted. WIDTHP can be NULL. */
5248
5249 static const char *
5250 arm_decode_bitfield (const char *ptr,
5251 unsigned long insn,
5252 unsigned long *valuep,
5253 int *widthp)
5254 {
5255 unsigned long value = 0;
5256 int width = 0;
5257
5258 do
5259 {
5260 int start, end;
5261 int bits;
5262
5263 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5264 start = start * 10 + *ptr - '0';
5265 if (*ptr == '-')
5266 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5267 end = end * 10 + *ptr - '0';
5268 else
5269 end = start;
5270 bits = end - start;
5271 if (bits < 0)
5272 abort ();
5273 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5274 width += bits + 1;
5275 }
5276 while (*ptr++ == ',');
5277 *valuep = value;
5278 if (widthp)
5279 *widthp = width;
5280 return ptr - 1;
5281 }
5282
5283 static void
5284 arm_decode_shift (long given, fprintf_ftype func, void *stream,
5285 bfd_boolean print_shift)
5286 {
5287 func (stream, "%s", arm_regnames[given & 0xf]);
5288
5289 if ((given & 0xff0) != 0)
5290 {
5291 if ((given & 0x10) == 0)
5292 {
5293 int amount = (given & 0xf80) >> 7;
5294 int shift = (given & 0x60) >> 5;
5295
5296 if (amount == 0)
5297 {
5298 if (shift == 3)
5299 {
5300 func (stream, ", rrx");
5301 return;
5302 }
5303
5304 amount = 32;
5305 }
5306
5307 if (print_shift)
5308 func (stream, ", %s #%d", arm_shift[shift], amount);
5309 else
5310 func (stream, ", #%d", amount);
5311 }
5312 else if ((given & 0x80) == 0x80)
5313 func (stream, "\t; <illegal shifter operand>");
5314 else if (print_shift)
5315 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5316 arm_regnames[(given & 0xf00) >> 8]);
5317 else
5318 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
5319 }
5320 }
5321
5322 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5323
5324 static bfd_boolean
5325 is_mve_okay_in_it (enum mve_instructions matched_insn)
5326 {
5327 switch (matched_insn)
5328 {
5329 case MVE_VMOV_GP_TO_VEC_LANE:
5330 case MVE_VMOV2_VEC_LANE_TO_GP:
5331 case MVE_VMOV2_GP_TO_VEC_LANE:
5332 case MVE_VMOV_VEC_LANE_TO_GP:
5333 case MVE_LSLL:
5334 case MVE_LSLLI:
5335 case MVE_LSRL:
5336 case MVE_ASRL:
5337 case MVE_ASRLI:
5338 case MVE_SQRSHRL:
5339 case MVE_SQRSHR:
5340 case MVE_UQRSHL:
5341 case MVE_UQRSHLL:
5342 case MVE_UQSHL:
5343 case MVE_UQSHLL:
5344 case MVE_URSHRL:
5345 case MVE_URSHR:
5346 case MVE_SRSHRL:
5347 case MVE_SRSHR:
5348 case MVE_SQSHLL:
5349 case MVE_SQSHL:
5350 return TRUE;
5351 default:
5352 return FALSE;
5353 }
5354 }
5355
5356 static bfd_boolean
5357 is_mve_architecture (struct disassemble_info *info)
5358 {
5359 struct arm_private_data *private_data = info->private_data;
5360 arm_feature_set allowed_arches = private_data->features;
5361
5362 arm_feature_set arm_ext_v8_1m_main
5363 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5364
5365 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5366 && !ARM_CPU_IS_ANY (allowed_arches))
5367 return TRUE;
5368 else
5369 return FALSE;
5370 }
5371
5372 static bfd_boolean
5373 is_vpt_instruction (long given)
5374 {
5375
5376 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5377 if ((given & 0x0040e000) == 0)
5378 return FALSE;
5379
5380 /* VPT floating point T1 variant. */
5381 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5382 /* VPT floating point T2 variant. */
5383 || ((given & 0xefb10f50) == 0xee310f40)
5384 /* VPT vector T1 variant. */
5385 || ((given & 0xff811f51) == 0xfe010f00)
5386 /* VPT vector T2 variant. */
5387 || ((given & 0xff811f51) == 0xfe010f01
5388 && ((given & 0x300000) != 0x300000))
5389 /* VPT vector T3 variant. */
5390 || ((given & 0xff811f50) == 0xfe011f00)
5391 /* VPT vector T4 variant. */
5392 || ((given & 0xff811f70) == 0xfe010f40)
5393 /* VPT vector T5 variant. */
5394 || ((given & 0xff811f70) == 0xfe010f60)
5395 /* VPT vector T6 variant. */
5396 || ((given & 0xff811f50) == 0xfe011f40)
5397 /* VPST vector T variant. */
5398 || ((given & 0xffbf1fff) == 0xfe310f4d))
5399 return TRUE;
5400 else
5401 return FALSE;
5402 }
5403
5404 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5405 and ending bitfield = END. END must be greater than START. */
5406
5407 static unsigned long
5408 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5409 {
5410 int bits = end - start;
5411
5412 if (bits < 0)
5413 abort ();
5414
5415 return ((given >> start) & ((2ul << bits) - 1));
5416 }
5417
5418 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5419 START:END and START2:END2. END/END2 must be greater than
5420 START/START2. */
5421
5422 static unsigned long
5423 arm_decode_field_multiple (unsigned long given, unsigned int start,
5424 unsigned int end, unsigned int start2,
5425 unsigned int end2)
5426 {
5427 int bits = end - start;
5428 int bits2 = end2 - start2;
5429 unsigned long value = 0;
5430 int width = 0;
5431
5432 if (bits2 < 0)
5433 abort ();
5434
5435 value = arm_decode_field (given, start, end);
5436 width += bits + 1;
5437
5438 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5439 return value;
5440 }
5441
5442 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5443 This helps us decode instructions that change mnemonic depending on specific
5444 operand values/encodings. */
5445
5446 static bfd_boolean
5447 is_mve_encoding_conflict (unsigned long given,
5448 enum mve_instructions matched_insn)
5449 {
5450 switch (matched_insn)
5451 {
5452 case MVE_VPST:
5453 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5454 return TRUE;
5455 else
5456 return FALSE;
5457
5458 case MVE_VPT_FP_T1:
5459 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5460 return TRUE;
5461 if ((arm_decode_field (given, 12, 12) == 0)
5462 && (arm_decode_field (given, 0, 0) == 1))
5463 return TRUE;
5464 return FALSE;
5465
5466 case MVE_VPT_FP_T2:
5467 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5468 return TRUE;
5469 if (arm_decode_field (given, 0, 3) == 0xd)
5470 return TRUE;
5471 return FALSE;
5472
5473 case MVE_VPT_VEC_T1:
5474 case MVE_VPT_VEC_T2:
5475 case MVE_VPT_VEC_T3:
5476 case MVE_VPT_VEC_T4:
5477 case MVE_VPT_VEC_T5:
5478 case MVE_VPT_VEC_T6:
5479 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5480 return TRUE;
5481 if (arm_decode_field (given, 20, 21) == 3)
5482 return TRUE;
5483 return FALSE;
5484
5485 case MVE_VCMP_FP_T1:
5486 if ((arm_decode_field (given, 12, 12) == 0)
5487 && (arm_decode_field (given, 0, 0) == 1))
5488 return TRUE;
5489 else
5490 return FALSE;
5491
5492 case MVE_VCMP_FP_T2:
5493 if (arm_decode_field (given, 0, 3) == 0xd)
5494 return TRUE;
5495 else
5496 return FALSE;
5497
5498 case MVE_VQADD_T2:
5499 case MVE_VQSUB_T2:
5500 case MVE_VMUL_VEC_T2:
5501 case MVE_VMULH:
5502 case MVE_VRMULH:
5503 case MVE_VMLA:
5504 case MVE_VMAX:
5505 case MVE_VMIN:
5506 case MVE_VBRSR:
5507 case MVE_VADD_VEC_T2:
5508 case MVE_VSUB_VEC_T2:
5509 case MVE_VABAV:
5510 case MVE_VQRSHL_T1:
5511 case MVE_VQSHL_T4:
5512 case MVE_VRSHL_T1:
5513 case MVE_VSHL_T3:
5514 case MVE_VCADD_VEC:
5515 case MVE_VHCADD:
5516 case MVE_VDDUP:
5517 case MVE_VIDUP:
5518 case MVE_VQRDMLADH:
5519 case MVE_VQDMLAH:
5520 case MVE_VQRDMLAH:
5521 case MVE_VQDMLASH:
5522 case MVE_VQRDMLASH:
5523 case MVE_VQDMLSDH:
5524 case MVE_VQRDMLSDH:
5525 case MVE_VQDMULH_T3:
5526 case MVE_VQRDMULH_T4:
5527 case MVE_VQDMLADH:
5528 case MVE_VMLAS:
5529 case MVE_VMULL_INT:
5530 case MVE_VHADD_T2:
5531 case MVE_VHSUB_T2:
5532 case MVE_VCMP_VEC_T1:
5533 case MVE_VCMP_VEC_T2:
5534 case MVE_VCMP_VEC_T3:
5535 case MVE_VCMP_VEC_T4:
5536 case MVE_VCMP_VEC_T5:
5537 case MVE_VCMP_VEC_T6:
5538 if (arm_decode_field (given, 20, 21) == 3)
5539 return TRUE;
5540 else
5541 return FALSE;
5542
5543 case MVE_VLD2:
5544 case MVE_VLD4:
5545 case MVE_VST2:
5546 case MVE_VST4:
5547 if (arm_decode_field (given, 7, 8) == 3)
5548 return TRUE;
5549 else
5550 return FALSE;
5551
5552 case MVE_VSTRB_T1:
5553 case MVE_VSTRH_T2:
5554 if ((arm_decode_field (given, 24, 24) == 0)
5555 && (arm_decode_field (given, 21, 21) == 0))
5556 {
5557 return TRUE;
5558 }
5559 else if ((arm_decode_field (given, 7, 8) == 3))
5560 return TRUE;
5561 else
5562 return FALSE;
5563
5564 case MVE_VSTRB_T5:
5565 case MVE_VSTRH_T6:
5566 case MVE_VSTRW_T7:
5567 if ((arm_decode_field (given, 24, 24) == 0)
5568 && (arm_decode_field (given, 21, 21) == 0))
5569 {
5570 return TRUE;
5571 }
5572 else
5573 return FALSE;
5574
5575 case MVE_VCVT_FP_FIX_VEC:
5576 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5577
5578 case MVE_VBIC_IMM:
5579 case MVE_VORR_IMM:
5580 {
5581 unsigned long cmode = arm_decode_field (given, 8, 11);
5582
5583 if ((cmode & 1) == 0)
5584 return TRUE;
5585 else if ((cmode & 0xc) == 0xc)
5586 return TRUE;
5587 else
5588 return FALSE;
5589 }
5590
5591 case MVE_VMVN_IMM:
5592 {
5593 unsigned long cmode = arm_decode_field (given, 8, 11);
5594
5595 if ((cmode & 9) == 1)
5596 return TRUE;
5597 else if ((cmode & 5) == 1)
5598 return TRUE;
5599 else if ((cmode & 0xe) == 0xe)
5600 return TRUE;
5601 else
5602 return FALSE;
5603 }
5604
5605 case MVE_VMOV_IMM_TO_VEC:
5606 if ((arm_decode_field (given, 5, 5) == 1)
5607 && (arm_decode_field (given, 8, 11) != 0xe))
5608 return TRUE;
5609 else
5610 return FALSE;
5611
5612 case MVE_VMOVL:
5613 {
5614 unsigned long size = arm_decode_field (given, 19, 20);
5615 if ((size == 0) || (size == 3))
5616 return TRUE;
5617 else
5618 return FALSE;
5619 }
5620
5621 case MVE_VMAXA:
5622 case MVE_VMINA:
5623 case MVE_VMAXV:
5624 case MVE_VMAXAV:
5625 case MVE_VMINV:
5626 case MVE_VMINAV:
5627 case MVE_VQRSHL_T2:
5628 case MVE_VQSHL_T1:
5629 case MVE_VRSHL_T2:
5630 case MVE_VSHL_T2:
5631 case MVE_VSHLL_T2:
5632 case MVE_VADDV:
5633 case MVE_VMOVN:
5634 case MVE_VQMOVUN:
5635 case MVE_VQMOVN:
5636 if (arm_decode_field (given, 18, 19) == 3)
5637 return TRUE;
5638 else
5639 return FALSE;
5640
5641 case MVE_VMLSLDAV:
5642 case MVE_VRMLSLDAVH:
5643 case MVE_VMLALDAV:
5644 case MVE_VADDLV:
5645 if (arm_decode_field (given, 20, 22) == 7)
5646 return TRUE;
5647 else
5648 return FALSE;
5649
5650 case MVE_VRMLALDAVH:
5651 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5652 return TRUE;
5653 else
5654 return FALSE;
5655
5656 case MVE_VDWDUP:
5657 case MVE_VIWDUP:
5658 if ((arm_decode_field (given, 20, 21) == 3)
5659 || (arm_decode_field (given, 1, 3) == 7))
5660 return TRUE;
5661 else
5662 return FALSE;
5663
5664
5665 case MVE_VSHLL_T1:
5666 if (arm_decode_field (given, 16, 18) == 0)
5667 {
5668 unsigned long sz = arm_decode_field (given, 19, 20);
5669
5670 if ((sz == 1) || (sz == 2))
5671 return TRUE;
5672 else
5673 return FALSE;
5674 }
5675 else
5676 return FALSE;
5677
5678 case MVE_VQSHL_T2:
5679 case MVE_VQSHLU_T3:
5680 case MVE_VRSHR:
5681 case MVE_VSHL_T1:
5682 case MVE_VSHR:
5683 case MVE_VSLI:
5684 case MVE_VSRI:
5685 if (arm_decode_field (given, 19, 21) == 0)
5686 return TRUE;
5687 else
5688 return FALSE;
5689
5690 case MVE_VCTP:
5691 if (arm_decode_field (given, 16, 19) == 0xf)
5692 return TRUE;
5693 else
5694 return FALSE;
5695
5696 case MVE_ASRLI:
5697 case MVE_ASRL:
5698 case MVE_LSLLI:
5699 case MVE_LSLL:
5700 case MVE_LSRL:
5701 case MVE_SQRSHRL:
5702 case MVE_SQSHLL:
5703 case MVE_SRSHRL:
5704 case MVE_UQRSHLL:
5705 case MVE_UQSHLL:
5706 case MVE_URSHRL:
5707 if (arm_decode_field (given, 9, 11) == 0x7)
5708 return TRUE;
5709 else
5710 return FALSE;
5711
5712 case MVE_CSINC:
5713 case MVE_CSINV:
5714 {
5715 unsigned long rm, rn;
5716 rm = arm_decode_field (given, 0, 3);
5717 rn = arm_decode_field (given, 16, 19);
5718 /* CSET/CSETM. */
5719 if (rm == 0xf && rn == 0xf)
5720 return TRUE;
5721 /* CINC/CINV. */
5722 else if (rn == rm && rn != 0xf)
5723 return TRUE;
5724 }
5725 /* Fall through. */
5726 case MVE_CSEL:
5727 case MVE_CSNEG:
5728 if (arm_decode_field (given, 0, 3) == 0xd)
5729 return TRUE;
5730 /* CNEG. */
5731 else if (matched_insn == MVE_CSNEG)
5732 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5733 return TRUE;
5734 return FALSE;
5735
5736 default:
5737 case MVE_VADD_FP_T1:
5738 case MVE_VADD_FP_T2:
5739 case MVE_VADD_VEC_T1:
5740 return FALSE;
5741
5742 }
5743 }
5744
5745 static void
5746 print_mve_vld_str_addr (struct disassemble_info *info,
5747 unsigned long given,
5748 enum mve_instructions matched_insn)
5749 {
5750 void *stream = info->stream;
5751 fprintf_ftype func = info->fprintf_func;
5752
5753 unsigned long p, w, gpr, imm, add, mod_imm;
5754
5755 imm = arm_decode_field (given, 0, 6);
5756 mod_imm = imm;
5757
5758 switch (matched_insn)
5759 {
5760 case MVE_VLDRB_T1:
5761 case MVE_VSTRB_T1:
5762 gpr = arm_decode_field (given, 16, 18);
5763 break;
5764
5765 case MVE_VLDRH_T2:
5766 case MVE_VSTRH_T2:
5767 gpr = arm_decode_field (given, 16, 18);
5768 mod_imm = imm << 1;
5769 break;
5770
5771 case MVE_VLDRH_T6:
5772 case MVE_VSTRH_T6:
5773 gpr = arm_decode_field (given, 16, 19);
5774 mod_imm = imm << 1;
5775 break;
5776
5777 case MVE_VLDRW_T7:
5778 case MVE_VSTRW_T7:
5779 gpr = arm_decode_field (given, 16, 19);
5780 mod_imm = imm << 2;
5781 break;
5782
5783 case MVE_VLDRB_T5:
5784 case MVE_VSTRB_T5:
5785 gpr = arm_decode_field (given, 16, 19);
5786 break;
5787
5788 default:
5789 return;
5790 }
5791
5792 p = arm_decode_field (given, 24, 24);
5793 w = arm_decode_field (given, 21, 21);
5794
5795 add = arm_decode_field (given, 23, 23);
5796
5797 char * add_sub;
5798
5799 /* Don't print anything for '+' as it is implied. */
5800 if (add == 1)
5801 add_sub = "";
5802 else
5803 add_sub = "-";
5804
5805 if (p == 1)
5806 {
5807 /* Offset mode. */
5808 if (w == 0)
5809 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5810 /* Pre-indexed mode. */
5811 else
5812 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5813 }
5814 else if ((p == 0) && (w == 1))
5815 /* Post-index mode. */
5816 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5817 }
5818
5819 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5820 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5821 this encoding is undefined. */
5822
5823 static bfd_boolean
5824 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5825 enum mve_undefined *undefined_code)
5826 {
5827 *undefined_code = UNDEF_NONE;
5828
5829 switch (matched_insn)
5830 {
5831 case MVE_VDUP:
5832 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5833 {
5834 *undefined_code = UNDEF_SIZE_3;
5835 return TRUE;
5836 }
5837 else
5838 return FALSE;
5839
5840 case MVE_VQADD_T1:
5841 case MVE_VQSUB_T1:
5842 case MVE_VMUL_VEC_T1:
5843 case MVE_VABD_VEC:
5844 case MVE_VADD_VEC_T1:
5845 case MVE_VSUB_VEC_T1:
5846 case MVE_VQDMULH_T1:
5847 case MVE_VQRDMULH_T2:
5848 case MVE_VRHADD:
5849 case MVE_VHADD_T1:
5850 case MVE_VHSUB_T1:
5851 if (arm_decode_field (given, 20, 21) == 3)
5852 {
5853 *undefined_code = UNDEF_SIZE_3;
5854 return TRUE;
5855 }
5856 else
5857 return FALSE;
5858
5859 case MVE_VLDRB_T1:
5860 if (arm_decode_field (given, 7, 8) == 3)
5861 {
5862 *undefined_code = UNDEF_SIZE_3;
5863 return TRUE;
5864 }
5865 else
5866 return FALSE;
5867
5868 case MVE_VLDRH_T2:
5869 if (arm_decode_field (given, 7, 8) <= 1)
5870 {
5871 *undefined_code = UNDEF_SIZE_LE_1;
5872 return TRUE;
5873 }
5874 else
5875 return FALSE;
5876
5877 case MVE_VSTRB_T1:
5878 if ((arm_decode_field (given, 7, 8) == 0))
5879 {
5880 *undefined_code = UNDEF_SIZE_0;
5881 return TRUE;
5882 }
5883 else
5884 return FALSE;
5885
5886 case MVE_VSTRH_T2:
5887 if ((arm_decode_field (given, 7, 8) <= 1))
5888 {
5889 *undefined_code = UNDEF_SIZE_LE_1;
5890 return TRUE;
5891 }
5892 else
5893 return FALSE;
5894
5895 case MVE_VLDRB_GATHER_T1:
5896 if (arm_decode_field (given, 7, 8) == 3)
5897 {
5898 *undefined_code = UNDEF_SIZE_3;
5899 return TRUE;
5900 }
5901 else if ((arm_decode_field (given, 28, 28) == 0)
5902 && (arm_decode_field (given, 7, 8) == 0))
5903 {
5904 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5905 return TRUE;
5906 }
5907 else
5908 return FALSE;
5909
5910 case MVE_VLDRH_GATHER_T2:
5911 if (arm_decode_field (given, 7, 8) == 3)
5912 {
5913 *undefined_code = UNDEF_SIZE_3;
5914 return TRUE;
5915 }
5916 else if ((arm_decode_field (given, 28, 28) == 0)
5917 && (arm_decode_field (given, 7, 8) == 1))
5918 {
5919 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5920 return TRUE;
5921 }
5922 else if (arm_decode_field (given, 7, 8) == 0)
5923 {
5924 *undefined_code = UNDEF_SIZE_0;
5925 return TRUE;
5926 }
5927 else
5928 return FALSE;
5929
5930 case MVE_VLDRW_GATHER_T3:
5931 if (arm_decode_field (given, 7, 8) != 2)
5932 {
5933 *undefined_code = UNDEF_SIZE_NOT_2;
5934 return TRUE;
5935 }
5936 else if (arm_decode_field (given, 28, 28) == 0)
5937 {
5938 *undefined_code = UNDEF_NOT_UNSIGNED;
5939 return TRUE;
5940 }
5941 else
5942 return FALSE;
5943
5944 case MVE_VLDRD_GATHER_T4:
5945 if (arm_decode_field (given, 7, 8) != 3)
5946 {
5947 *undefined_code = UNDEF_SIZE_NOT_3;
5948 return TRUE;
5949 }
5950 else if (arm_decode_field (given, 28, 28) == 0)
5951 {
5952 *undefined_code = UNDEF_NOT_UNSIGNED;
5953 return TRUE;
5954 }
5955 else
5956 return FALSE;
5957
5958 case MVE_VSTRB_SCATTER_T1:
5959 if (arm_decode_field (given, 7, 8) == 3)
5960 {
5961 *undefined_code = UNDEF_SIZE_3;
5962 return TRUE;
5963 }
5964 else
5965 return FALSE;
5966
5967 case MVE_VSTRH_SCATTER_T2:
5968 {
5969 unsigned long size = arm_decode_field (given, 7, 8);
5970 if (size == 3)
5971 {
5972 *undefined_code = UNDEF_SIZE_3;
5973 return TRUE;
5974 }
5975 else if (size == 0)
5976 {
5977 *undefined_code = UNDEF_SIZE_0;
5978 return TRUE;
5979 }
5980 else
5981 return FALSE;
5982 }
5983
5984 case MVE_VSTRW_SCATTER_T3:
5985 if (arm_decode_field (given, 7, 8) != 2)
5986 {
5987 *undefined_code = UNDEF_SIZE_NOT_2;
5988 return TRUE;
5989 }
5990 else
5991 return FALSE;
5992
5993 case MVE_VSTRD_SCATTER_T4:
5994 if (arm_decode_field (given, 7, 8) != 3)
5995 {
5996 *undefined_code = UNDEF_SIZE_NOT_3;
5997 return TRUE;
5998 }
5999 else
6000 return FALSE;
6001
6002 case MVE_VCVT_FP_FIX_VEC:
6003 {
6004 unsigned long imm6 = arm_decode_field (given, 16, 21);
6005 if ((imm6 & 0x20) == 0)
6006 {
6007 *undefined_code = UNDEF_VCVT_IMM6;
6008 return TRUE;
6009 }
6010
6011 if ((arm_decode_field (given, 9, 9) == 0)
6012 && ((imm6 & 0x30) == 0x20))
6013 {
6014 *undefined_code = UNDEF_VCVT_FSI_IMM6;
6015 return TRUE;
6016 }
6017
6018 return FALSE;
6019 }
6020
6021 case MVE_VNEG_FP:
6022 case MVE_VABS_FP:
6023 case MVE_VCVT_BETWEEN_FP_INT:
6024 case MVE_VCVT_FROM_FP_TO_INT:
6025 {
6026 unsigned long size = arm_decode_field (given, 18, 19);
6027 if (size == 0)
6028 {
6029 *undefined_code = UNDEF_SIZE_0;
6030 return TRUE;
6031 }
6032 else if (size == 3)
6033 {
6034 *undefined_code = UNDEF_SIZE_3;
6035 return TRUE;
6036 }
6037 else
6038 return FALSE;
6039 }
6040
6041 case MVE_VMOV_VEC_LANE_TO_GP:
6042 {
6043 unsigned long op1 = arm_decode_field (given, 21, 22);
6044 unsigned long op2 = arm_decode_field (given, 5, 6);
6045 unsigned long u = arm_decode_field (given, 23, 23);
6046
6047 if ((op2 == 0) && (u == 1))
6048 {
6049 if ((op1 == 0) || (op1 == 1))
6050 {
6051 *undefined_code = UNDEF_BAD_U_OP1_OP2;
6052 return TRUE;
6053 }
6054 else
6055 return FALSE;
6056 }
6057 else if (op2 == 2)
6058 {
6059 if ((op1 == 0) || (op1 == 1))
6060 {
6061 *undefined_code = UNDEF_BAD_OP1_OP2;
6062 return TRUE;
6063 }
6064 else
6065 return FALSE;
6066 }
6067
6068 return FALSE;
6069 }
6070
6071 case MVE_VMOV_GP_TO_VEC_LANE:
6072 if (arm_decode_field (given, 5, 6) == 2)
6073 {
6074 unsigned long op1 = arm_decode_field (given, 21, 22);
6075 if ((op1 == 0) || (op1 == 1))
6076 {
6077 *undefined_code = UNDEF_BAD_OP1_OP2;
6078 return TRUE;
6079 }
6080 else
6081 return FALSE;
6082 }
6083 else
6084 return FALSE;
6085
6086 case MVE_VMOV_IMM_TO_VEC:
6087 if (arm_decode_field (given, 5, 5) == 0)
6088 {
6089 unsigned long cmode = arm_decode_field (given, 8, 11);
6090
6091 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6092 {
6093 *undefined_code = UNDEF_OP_0_BAD_CMODE;
6094 return TRUE;
6095 }
6096 else
6097 return FALSE;
6098 }
6099 else
6100 return FALSE;
6101
6102 case MVE_VSHLL_T2:
6103 case MVE_VMOVN:
6104 if (arm_decode_field (given, 18, 19) == 2)
6105 {
6106 *undefined_code = UNDEF_SIZE_2;
6107 return TRUE;
6108 }
6109 else
6110 return FALSE;
6111
6112 case MVE_VRMLALDAVH:
6113 case MVE_VMLADAV_T1:
6114 case MVE_VMLADAV_T2:
6115 case MVE_VMLALDAV:
6116 if ((arm_decode_field (given, 28, 28) == 1)
6117 && (arm_decode_field (given, 12, 12) == 1))
6118 {
6119 *undefined_code = UNDEF_XCHG_UNS;
6120 return TRUE;
6121 }
6122 else
6123 return FALSE;
6124
6125 case MVE_VQSHRN:
6126 case MVE_VQSHRUN:
6127 case MVE_VSHLL_T1:
6128 case MVE_VSHRN:
6129 {
6130 unsigned long sz = arm_decode_field (given, 19, 20);
6131 if (sz == 1)
6132 return FALSE;
6133 else if ((sz & 2) == 2)
6134 return FALSE;
6135 else
6136 {
6137 *undefined_code = UNDEF_SIZE;
6138 return TRUE;
6139 }
6140 }
6141 break;
6142
6143 case MVE_VQSHL_T2:
6144 case MVE_VQSHLU_T3:
6145 case MVE_VRSHR:
6146 case MVE_VSHL_T1:
6147 case MVE_VSHR:
6148 case MVE_VSLI:
6149 case MVE_VSRI:
6150 {
6151 unsigned long sz = arm_decode_field (given, 19, 21);
6152 if ((sz & 7) == 1)
6153 return FALSE;
6154 else if ((sz & 6) == 2)
6155 return FALSE;
6156 else if ((sz & 4) == 4)
6157 return FALSE;
6158 else
6159 {
6160 *undefined_code = UNDEF_SIZE;
6161 return TRUE;
6162 }
6163 }
6164
6165 case MVE_VQRSHRN:
6166 case MVE_VQRSHRUN:
6167 if (arm_decode_field (given, 19, 20) == 0)
6168 {
6169 *undefined_code = UNDEF_SIZE_0;
6170 return TRUE;
6171 }
6172 else
6173 return FALSE;
6174
6175 case MVE_VABS_VEC:
6176 if (arm_decode_field (given, 18, 19) == 3)
6177 {
6178 *undefined_code = UNDEF_SIZE_3;
6179 return TRUE;
6180 }
6181 else
6182 return FALSE;
6183
6184 case MVE_VQNEG:
6185 case MVE_VQABS:
6186 case MVE_VNEG_VEC:
6187 case MVE_VCLS:
6188 case MVE_VCLZ:
6189 if (arm_decode_field (given, 18, 19) == 3)
6190 {
6191 *undefined_code = UNDEF_SIZE_3;
6192 return TRUE;
6193 }
6194 else
6195 return FALSE;
6196
6197 case MVE_VREV16:
6198 if (arm_decode_field (given, 18, 19) == 0)
6199 return FALSE;
6200 else
6201 {
6202 *undefined_code = UNDEF_SIZE_NOT_0;
6203 return TRUE;
6204 }
6205
6206 case MVE_VREV32:
6207 {
6208 unsigned long size = arm_decode_field (given, 18, 19);
6209 if ((size & 2) == 2)
6210 {
6211 *undefined_code = UNDEF_SIZE_2;
6212 return TRUE;
6213 }
6214 else
6215 return FALSE;
6216 }
6217
6218 case MVE_VREV64:
6219 if (arm_decode_field (given, 18, 19) != 3)
6220 return FALSE;
6221 else
6222 {
6223 *undefined_code = UNDEF_SIZE_3;
6224 return TRUE;
6225 }
6226
6227 default:
6228 return FALSE;
6229 }
6230 }
6231
6232 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6233 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6234 why this encoding is unpredictable. */
6235
6236 static bfd_boolean
6237 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6238 enum mve_unpredictable *unpredictable_code)
6239 {
6240 *unpredictable_code = UNPRED_NONE;
6241
6242 switch (matched_insn)
6243 {
6244 case MVE_VCMP_FP_T2:
6245 case MVE_VPT_FP_T2:
6246 if ((arm_decode_field (given, 12, 12) == 0)
6247 && (arm_decode_field (given, 5, 5) == 1))
6248 {
6249 *unpredictable_code = UNPRED_FCA_0_FCB_1;
6250 return TRUE;
6251 }
6252 else
6253 return FALSE;
6254
6255 case MVE_VPT_VEC_T4:
6256 case MVE_VPT_VEC_T5:
6257 case MVE_VPT_VEC_T6:
6258 case MVE_VCMP_VEC_T4:
6259 case MVE_VCMP_VEC_T5:
6260 case MVE_VCMP_VEC_T6:
6261 if (arm_decode_field (given, 0, 3) == 0xd)
6262 {
6263 *unpredictable_code = UNPRED_R13;
6264 return TRUE;
6265 }
6266 else
6267 return FALSE;
6268
6269 case MVE_VDUP:
6270 {
6271 unsigned long gpr = arm_decode_field (given, 12, 15);
6272 if (gpr == 0xd)
6273 {
6274 *unpredictable_code = UNPRED_R13;
6275 return TRUE;
6276 }
6277 else if (gpr == 0xf)
6278 {
6279 *unpredictable_code = UNPRED_R15;
6280 return TRUE;
6281 }
6282
6283 return FALSE;
6284 }
6285
6286 case MVE_VQADD_T2:
6287 case MVE_VQSUB_T2:
6288 case MVE_VMUL_FP_T2:
6289 case MVE_VMUL_VEC_T2:
6290 case MVE_VMLA:
6291 case MVE_VBRSR:
6292 case MVE_VADD_FP_T2:
6293 case MVE_VSUB_FP_T2:
6294 case MVE_VADD_VEC_T2:
6295 case MVE_VSUB_VEC_T2:
6296 case MVE_VQRSHL_T2:
6297 case MVE_VQSHL_T1:
6298 case MVE_VRSHL_T2:
6299 case MVE_VSHL_T2:
6300 case MVE_VSHLC:
6301 case MVE_VQDMLAH:
6302 case MVE_VQRDMLAH:
6303 case MVE_VQDMLASH:
6304 case MVE_VQRDMLASH:
6305 case MVE_VQDMULH_T3:
6306 case MVE_VQRDMULH_T4:
6307 case MVE_VMLAS:
6308 case MVE_VFMA_FP_SCALAR:
6309 case MVE_VFMAS_FP_SCALAR:
6310 case MVE_VHADD_T2:
6311 case MVE_VHSUB_T2:
6312 {
6313 unsigned long gpr = arm_decode_field (given, 0, 3);
6314 if (gpr == 0xd)
6315 {
6316 *unpredictable_code = UNPRED_R13;
6317 return TRUE;
6318 }
6319 else if (gpr == 0xf)
6320 {
6321 *unpredictable_code = UNPRED_R15;
6322 return TRUE;
6323 }
6324
6325 return FALSE;
6326 }
6327
6328 case MVE_VLD2:
6329 case MVE_VST2:
6330 {
6331 unsigned long rn = arm_decode_field (given, 16, 19);
6332
6333 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6334 {
6335 *unpredictable_code = UNPRED_R13_AND_WB;
6336 return TRUE;
6337 }
6338
6339 if (rn == 0xf)
6340 {
6341 *unpredictable_code = UNPRED_R15;
6342 return TRUE;
6343 }
6344
6345 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6346 {
6347 *unpredictable_code = UNPRED_Q_GT_6;
6348 return TRUE;
6349 }
6350 else
6351 return FALSE;
6352 }
6353
6354 case MVE_VLD4:
6355 case MVE_VST4:
6356 {
6357 unsigned long rn = arm_decode_field (given, 16, 19);
6358
6359 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6360 {
6361 *unpredictable_code = UNPRED_R13_AND_WB;
6362 return TRUE;
6363 }
6364
6365 if (rn == 0xf)
6366 {
6367 *unpredictable_code = UNPRED_R15;
6368 return TRUE;
6369 }
6370
6371 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6372 {
6373 *unpredictable_code = UNPRED_Q_GT_4;
6374 return TRUE;
6375 }
6376 else
6377 return FALSE;
6378 }
6379
6380 case MVE_VLDRB_T5:
6381 case MVE_VLDRH_T6:
6382 case MVE_VLDRW_T7:
6383 case MVE_VSTRB_T5:
6384 case MVE_VSTRH_T6:
6385 case MVE_VSTRW_T7:
6386 {
6387 unsigned long rn = arm_decode_field (given, 16, 19);
6388
6389 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6390 {
6391 *unpredictable_code = UNPRED_R13_AND_WB;
6392 return TRUE;
6393 }
6394 else if (rn == 0xf)
6395 {
6396 *unpredictable_code = UNPRED_R15;
6397 return TRUE;
6398 }
6399 else
6400 return FALSE;
6401 }
6402
6403 case MVE_VLDRB_GATHER_T1:
6404 if (arm_decode_field (given, 0, 0) == 1)
6405 {
6406 *unpredictable_code = UNPRED_OS;
6407 return TRUE;
6408 }
6409
6410 /* fall through. */
6411 /* To handle common code with T2-T4 variants. */
6412 case MVE_VLDRH_GATHER_T2:
6413 case MVE_VLDRW_GATHER_T3:
6414 case MVE_VLDRD_GATHER_T4:
6415 {
6416 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6417 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6418
6419 if (qd == qm)
6420 {
6421 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6422 return TRUE;
6423 }
6424
6425 if (arm_decode_field (given, 16, 19) == 0xf)
6426 {
6427 *unpredictable_code = UNPRED_R15;
6428 return TRUE;
6429 }
6430
6431 return FALSE;
6432 }
6433
6434 case MVE_VLDRW_GATHER_T5:
6435 case MVE_VLDRD_GATHER_T6:
6436 {
6437 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6438 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6439
6440 if (qd == qm)
6441 {
6442 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6443 return TRUE;
6444 }
6445 else
6446 return FALSE;
6447 }
6448
6449 case MVE_VSTRB_SCATTER_T1:
6450 if (arm_decode_field (given, 16, 19) == 0xf)
6451 {
6452 *unpredictable_code = UNPRED_R15;
6453 return TRUE;
6454 }
6455 else if (arm_decode_field (given, 0, 0) == 1)
6456 {
6457 *unpredictable_code = UNPRED_OS;
6458 return TRUE;
6459 }
6460 else
6461 return FALSE;
6462
6463 case MVE_VSTRH_SCATTER_T2:
6464 case MVE_VSTRW_SCATTER_T3:
6465 case MVE_VSTRD_SCATTER_T4:
6466 if (arm_decode_field (given, 16, 19) == 0xf)
6467 {
6468 *unpredictable_code = UNPRED_R15;
6469 return TRUE;
6470 }
6471 else
6472 return FALSE;
6473
6474 case MVE_VMOV2_VEC_LANE_TO_GP:
6475 case MVE_VMOV2_GP_TO_VEC_LANE:
6476 case MVE_VCVT_BETWEEN_FP_INT:
6477 case MVE_VCVT_FROM_FP_TO_INT:
6478 {
6479 unsigned long rt = arm_decode_field (given, 0, 3);
6480 unsigned long rt2 = arm_decode_field (given, 16, 19);
6481
6482 if ((rt == 0xd) || (rt2 == 0xd))
6483 {
6484 *unpredictable_code = UNPRED_R13;
6485 return TRUE;
6486 }
6487 else if ((rt == 0xf) || (rt2 == 0xf))
6488 {
6489 *unpredictable_code = UNPRED_R15;
6490 return TRUE;
6491 }
6492 else if (rt == rt2)
6493 {
6494 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6495 return TRUE;
6496 }
6497
6498 return FALSE;
6499 }
6500
6501 case MVE_VMAXV:
6502 case MVE_VMAXAV:
6503 case MVE_VMAXNMV_FP:
6504 case MVE_VMAXNMAV_FP:
6505 case MVE_VMINNMV_FP:
6506 case MVE_VMINNMAV_FP:
6507 case MVE_VMINV:
6508 case MVE_VMINAV:
6509 case MVE_VABAV:
6510 case MVE_VMOV_HFP_TO_GP:
6511 case MVE_VMOV_GP_TO_VEC_LANE:
6512 case MVE_VMOV_VEC_LANE_TO_GP:
6513 {
6514 unsigned long rda = arm_decode_field (given, 12, 15);
6515 if (rda == 0xd)
6516 {
6517 *unpredictable_code = UNPRED_R13;
6518 return TRUE;
6519 }
6520 else if (rda == 0xf)
6521 {
6522 *unpredictable_code = UNPRED_R15;
6523 return TRUE;
6524 }
6525
6526 return FALSE;
6527 }
6528
6529 case MVE_VQRDMLADH:
6530 case MVE_VQDMLSDH:
6531 case MVE_VQRDMLSDH:
6532 case MVE_VQDMLADH:
6533 case MVE_VMULL_INT:
6534 {
6535 unsigned long Qd;
6536 unsigned long Qm;
6537 unsigned long Qn;
6538
6539 if (arm_decode_field (given, 20, 21) == 2)
6540 {
6541 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6542 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6543 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6544
6545 if ((Qd == Qn) || (Qd == Qm))
6546 {
6547 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6548 return TRUE;
6549 }
6550 else
6551 return FALSE;
6552 }
6553 else
6554 return FALSE;
6555 }
6556
6557 case MVE_VCMUL_FP:
6558 case MVE_VQDMULL_T1:
6559 {
6560 unsigned long Qd;
6561 unsigned long Qm;
6562 unsigned long Qn;
6563
6564 if (arm_decode_field (given, 28, 28) == 1)
6565 {
6566 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6567 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6568 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6569
6570 if ((Qd == Qn) || (Qd == Qm))
6571 {
6572 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6573 return TRUE;
6574 }
6575 else
6576 return FALSE;
6577 }
6578 else
6579 return FALSE;
6580 }
6581
6582 case MVE_VQDMULL_T2:
6583 {
6584 unsigned long gpr = arm_decode_field (given, 0, 3);
6585 if (gpr == 0xd)
6586 {
6587 *unpredictable_code = UNPRED_R13;
6588 return TRUE;
6589 }
6590 else if (gpr == 0xf)
6591 {
6592 *unpredictable_code = UNPRED_R15;
6593 return TRUE;
6594 }
6595
6596 if (arm_decode_field (given, 28, 28) == 1)
6597 {
6598 unsigned long Qd
6599 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6600 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6601
6602 if ((Qd == Qn))
6603 {
6604 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6605 return TRUE;
6606 }
6607 else
6608 return FALSE;
6609 }
6610
6611 return FALSE;
6612 }
6613
6614 case MVE_VMLSLDAV:
6615 case MVE_VRMLSLDAVH:
6616 case MVE_VMLALDAV:
6617 case MVE_VADDLV:
6618 if (arm_decode_field (given, 20, 22) == 6)
6619 {
6620 *unpredictable_code = UNPRED_R13;
6621 return TRUE;
6622 }
6623 else
6624 return FALSE;
6625
6626 case MVE_VDWDUP:
6627 case MVE_VIWDUP:
6628 if (arm_decode_field (given, 1, 3) == 6)
6629 {
6630 *unpredictable_code = UNPRED_R13;
6631 return TRUE;
6632 }
6633 else
6634 return FALSE;
6635
6636 case MVE_VCADD_VEC:
6637 case MVE_VHCADD:
6638 {
6639 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6640 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6641 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6642 {
6643 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6644 return TRUE;
6645 }
6646 else
6647 return FALSE;
6648 }
6649
6650 case MVE_VCADD_FP:
6651 {
6652 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6653 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6654 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6655 {
6656 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6657 return TRUE;
6658 }
6659 else
6660 return FALSE;
6661 }
6662
6663 case MVE_VCMLA_FP:
6664 {
6665 unsigned long Qda;
6666 unsigned long Qm;
6667 unsigned long Qn;
6668
6669 if (arm_decode_field (given, 20, 20) == 1)
6670 {
6671 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6672 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6673 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6674
6675 if ((Qda == Qn) || (Qda == Qm))
6676 {
6677 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6678 return TRUE;
6679 }
6680 else
6681 return FALSE;
6682 }
6683 else
6684 return FALSE;
6685
6686 }
6687
6688 case MVE_VCTP:
6689 if (arm_decode_field (given, 16, 19) == 0xd)
6690 {
6691 *unpredictable_code = UNPRED_R13;
6692 return TRUE;
6693 }
6694 else
6695 return FALSE;
6696
6697 case MVE_VREV64:
6698 {
6699 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6700 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6701
6702 if (qd == qm)
6703 {
6704 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6705 return TRUE;
6706 }
6707 else
6708 return FALSE;
6709 }
6710
6711 case MVE_LSLL:
6712 case MVE_LSLLI:
6713 case MVE_LSRL:
6714 case MVE_ASRL:
6715 case MVE_ASRLI:
6716 case MVE_UQSHLL:
6717 case MVE_UQRSHLL:
6718 case MVE_URSHRL:
6719 case MVE_SRSHRL:
6720 case MVE_SQSHLL:
6721 case MVE_SQRSHRL:
6722 {
6723 unsigned long gpr = arm_decode_field (given, 9, 11);
6724 gpr = ((gpr << 1) | 1);
6725 if (gpr == 0xd)
6726 {
6727 *unpredictable_code = UNPRED_R13;
6728 return TRUE;
6729 }
6730 else if (gpr == 0xf)
6731 {
6732 *unpredictable_code = UNPRED_R15;
6733 return TRUE;
6734 }
6735
6736 return FALSE;
6737 }
6738
6739 default:
6740 return FALSE;
6741 }
6742 }
6743
6744 static void
6745 print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6746 {
6747 unsigned long op1 = arm_decode_field (given, 21, 22);
6748 unsigned long op2 = arm_decode_field (given, 5, 6);
6749 unsigned long h = arm_decode_field (given, 16, 16);
6750 unsigned long index, esize, targetBeat, idx;
6751 void *stream = info->stream;
6752 fprintf_ftype func = info->fprintf_func;
6753
6754 if ((op1 & 0x2) == 0x2)
6755 {
6756 index = op2;
6757 esize = 8;
6758 }
6759 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6760 {
6761 index = op2 >> 1;
6762 esize = 16;
6763 }
6764 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6765 {
6766 index = 0;
6767 esize = 32;
6768 }
6769 else
6770 {
6771 func (stream, "<undefined index>");
6772 return;
6773 }
6774
6775 targetBeat = (op1 & 0x1) | (h << 1);
6776 idx = index + targetBeat * (32/esize);
6777
6778 func (stream, "%lu", idx);
6779 }
6780
6781 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6782 in length and integer of floating-point type. */
6783 static void
6784 print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6785 unsigned int ibit_loc, const struct mopcode32 *insn)
6786 {
6787 int bits = 0;
6788 int cmode = (given >> 8) & 0xf;
6789 int op = (given >> 5) & 0x1;
6790 unsigned long value = 0, hival = 0;
6791 unsigned shift;
6792 int size = 0;
6793 int isfloat = 0;
6794 void *stream = info->stream;
6795 fprintf_ftype func = info->fprintf_func;
6796
6797 /* On Neon the 'i' bit is at bit 24, on mve it is
6798 at bit 28. */
6799 bits |= ((given >> ibit_loc) & 1) << 7;
6800 bits |= ((given >> 16) & 7) << 4;
6801 bits |= ((given >> 0) & 15) << 0;
6802
6803 if (cmode < 8)
6804 {
6805 shift = (cmode >> 1) & 3;
6806 value = (unsigned long) bits << (8 * shift);
6807 size = 32;
6808 }
6809 else if (cmode < 12)
6810 {
6811 shift = (cmode >> 1) & 1;
6812 value = (unsigned long) bits << (8 * shift);
6813 size = 16;
6814 }
6815 else if (cmode < 14)
6816 {
6817 shift = (cmode & 1) + 1;
6818 value = (unsigned long) bits << (8 * shift);
6819 value |= (1ul << (8 * shift)) - 1;
6820 size = 32;
6821 }
6822 else if (cmode == 14)
6823 {
6824 if (op)
6825 {
6826 /* Bit replication into bytes. */
6827 int ix;
6828 unsigned long mask;
6829
6830 value = 0;
6831 hival = 0;
6832 for (ix = 7; ix >= 0; ix--)
6833 {
6834 mask = ((bits >> ix) & 1) ? 0xff : 0;
6835 if (ix <= 3)
6836 value = (value << 8) | mask;
6837 else
6838 hival = (hival << 8) | mask;
6839 }
6840 size = 64;
6841 }
6842 else
6843 {
6844 /* Byte replication. */
6845 value = (unsigned long) bits;
6846 size = 8;
6847 }
6848 }
6849 else if (!op)
6850 {
6851 /* Floating point encoding. */
6852 int tmp;
6853
6854 value = (unsigned long) (bits & 0x7f) << 19;
6855 value |= (unsigned long) (bits & 0x80) << 24;
6856 tmp = bits & 0x40 ? 0x3c : 0x40;
6857 value |= (unsigned long) tmp << 24;
6858 size = 32;
6859 isfloat = 1;
6860 }
6861 else
6862 {
6863 func (stream, "<illegal constant %.8x:%x:%x>",
6864 bits, cmode, op);
6865 size = 32;
6866 return;
6867 }
6868
6869 // printU determines whether the immediate value should be printed as
6870 // unsigned.
6871 unsigned printU = 0;
6872 switch (insn->mve_op)
6873 {
6874 default:
6875 break;
6876 // We want this for instructions that don't have a 'signed' type
6877 case MVE_VBIC_IMM:
6878 case MVE_VORR_IMM:
6879 case MVE_VMVN_IMM:
6880 case MVE_VMOV_IMM_TO_VEC:
6881 printU = 1;
6882 break;
6883 }
6884 switch (size)
6885 {
6886 case 8:
6887 func (stream, "#%ld\t; 0x%.2lx", value, value);
6888 break;
6889
6890 case 16:
6891 func (stream,
6892 printU
6893 ? "#%lu\t; 0x%.4lx"
6894 : "#%ld\t; 0x%.4lx", value, value);
6895 break;
6896
6897 case 32:
6898 if (isfloat)
6899 {
6900 unsigned char valbytes[4];
6901 double fvalue;
6902
6903 /* Do this a byte at a time so we don't have to
6904 worry about the host's endianness. */
6905 valbytes[0] = value & 0xff;
6906 valbytes[1] = (value >> 8) & 0xff;
6907 valbytes[2] = (value >> 16) & 0xff;
6908 valbytes[3] = (value >> 24) & 0xff;
6909
6910 floatformat_to_double
6911 (& floatformat_ieee_single_little, valbytes,
6912 & fvalue);
6913
6914 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6915 value);
6916 }
6917 else
6918 func (stream,
6919 printU
6920 ? "#%lu\t; 0x%.8lx"
6921 : "#%ld\t; 0x%.8lx",
6922 (long) (((value & 0x80000000L) != 0)
6923 && !printU
6924 ? value | ~0xffffffffL : value),
6925 value);
6926 break;
6927
6928 case 64:
6929 func (stream, "#0x%.8lx%.8lx", hival, value);
6930 break;
6931
6932 default:
6933 abort ();
6934 }
6935
6936 }
6937
6938 static void
6939 print_mve_undefined (struct disassemble_info *info,
6940 enum mve_undefined undefined_code)
6941 {
6942 void *stream = info->stream;
6943 fprintf_ftype func = info->fprintf_func;
6944
6945 func (stream, "\t\tundefined instruction: ");
6946
6947 switch (undefined_code)
6948 {
6949 case UNDEF_SIZE:
6950 func (stream, "illegal size");
6951 break;
6952
6953 case UNDEF_SIZE_0:
6954 func (stream, "size equals zero");
6955 break;
6956
6957 case UNDEF_SIZE_2:
6958 func (stream, "size equals two");
6959 break;
6960
6961 case UNDEF_SIZE_3:
6962 func (stream, "size equals three");
6963 break;
6964
6965 case UNDEF_SIZE_LE_1:
6966 func (stream, "size <= 1");
6967 break;
6968
6969 case UNDEF_SIZE_NOT_0:
6970 func (stream, "size not equal to 0");
6971 break;
6972
6973 case UNDEF_SIZE_NOT_2:
6974 func (stream, "size not equal to 2");
6975 break;
6976
6977 case UNDEF_SIZE_NOT_3:
6978 func (stream, "size not equal to 3");
6979 break;
6980
6981 case UNDEF_NOT_UNS_SIZE_0:
6982 func (stream, "not unsigned and size = zero");
6983 break;
6984
6985 case UNDEF_NOT_UNS_SIZE_1:
6986 func (stream, "not unsigned and size = one");
6987 break;
6988
6989 case UNDEF_NOT_UNSIGNED:
6990 func (stream, "not unsigned");
6991 break;
6992
6993 case UNDEF_VCVT_IMM6:
6994 func (stream, "invalid imm6");
6995 break;
6996
6997 case UNDEF_VCVT_FSI_IMM6:
6998 func (stream, "fsi = 0 and invalid imm6");
6999 break;
7000
7001 case UNDEF_BAD_OP1_OP2:
7002 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7003 break;
7004
7005 case UNDEF_BAD_U_OP1_OP2:
7006 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7007 break;
7008
7009 case UNDEF_OP_0_BAD_CMODE:
7010 func (stream, "op field equal 0 and bad cmode");
7011 break;
7012
7013 case UNDEF_XCHG_UNS:
7014 func (stream, "exchange and unsigned together");
7015 break;
7016
7017 case UNDEF_NONE:
7018 break;
7019 }
7020
7021 }
7022
7023 static void
7024 print_mve_unpredictable (struct disassemble_info *info,
7025 enum mve_unpredictable unpredict_code)
7026 {
7027 void *stream = info->stream;
7028 fprintf_ftype func = info->fprintf_func;
7029
7030 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7031
7032 switch (unpredict_code)
7033 {
7034 case UNPRED_IT_BLOCK:
7035 func (stream, "mve instruction in it block");
7036 break;
7037
7038 case UNPRED_FCA_0_FCB_1:
7039 func (stream, "condition bits, fca = 0 and fcb = 1");
7040 break;
7041
7042 case UNPRED_R13:
7043 func (stream, "use of r13 (sp)");
7044 break;
7045
7046 case UNPRED_R15:
7047 func (stream, "use of r15 (pc)");
7048 break;
7049
7050 case UNPRED_Q_GT_4:
7051 func (stream, "start register block > r4");
7052 break;
7053
7054 case UNPRED_Q_GT_6:
7055 func (stream, "start register block > r6");
7056 break;
7057
7058 case UNPRED_R13_AND_WB:
7059 func (stream, "use of r13 and write back");
7060 break;
7061
7062 case UNPRED_Q_REGS_EQUAL:
7063 func (stream,
7064 "same vector register used for destination and other operand");
7065 break;
7066
7067 case UNPRED_OS:
7068 func (stream, "use of offset scaled");
7069 break;
7070
7071 case UNPRED_GP_REGS_EQUAL:
7072 func (stream, "same general-purpose register used for both operands");
7073 break;
7074
7075 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7076 func (stream, "use of identical q registers and size = 1");
7077 break;
7078
7079 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7080 func (stream, "use of identical q registers and size = 1");
7081 break;
7082
7083 case UNPRED_NONE:
7084 break;
7085 }
7086 }
7087
7088 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
7089
7090 static void
7091 print_mve_register_blocks (struct disassemble_info *info,
7092 unsigned long given,
7093 enum mve_instructions matched_insn)
7094 {
7095 void *stream = info->stream;
7096 fprintf_ftype func = info->fprintf_func;
7097
7098 unsigned long q_reg_start = arm_decode_field_multiple (given,
7099 13, 15,
7100 22, 22);
7101 switch (matched_insn)
7102 {
7103 case MVE_VLD2:
7104 case MVE_VST2:
7105 if (q_reg_start <= 6)
7106 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7107 else
7108 func (stream, "<illegal reg q%ld>", q_reg_start);
7109 break;
7110
7111 case MVE_VLD4:
7112 case MVE_VST4:
7113 if (q_reg_start <= 4)
7114 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7115 q_reg_start + 1, q_reg_start + 2,
7116 q_reg_start + 3);
7117 else
7118 func (stream, "<illegal reg q%ld>", q_reg_start);
7119 break;
7120
7121 default:
7122 break;
7123 }
7124 }
7125
7126 static void
7127 print_mve_rounding_mode (struct disassemble_info *info,
7128 unsigned long given,
7129 enum mve_instructions matched_insn)
7130 {
7131 void *stream = info->stream;
7132 fprintf_ftype func = info->fprintf_func;
7133
7134 switch (matched_insn)
7135 {
7136 case MVE_VCVT_FROM_FP_TO_INT:
7137 {
7138 switch (arm_decode_field (given, 8, 9))
7139 {
7140 case 0:
7141 func (stream, "a");
7142 break;
7143
7144 case 1:
7145 func (stream, "n");
7146 break;
7147
7148 case 2:
7149 func (stream, "p");
7150 break;
7151
7152 case 3:
7153 func (stream, "m");
7154 break;
7155
7156 default:
7157 break;
7158 }
7159 }
7160 break;
7161
7162 case MVE_VRINT_FP:
7163 {
7164 switch (arm_decode_field (given, 7, 9))
7165 {
7166 case 0:
7167 func (stream, "n");
7168 break;
7169
7170 case 1:
7171 func (stream, "x");
7172 break;
7173
7174 case 2:
7175 func (stream, "a");
7176 break;
7177
7178 case 3:
7179 func (stream, "z");
7180 break;
7181
7182 case 5:
7183 func (stream, "m");
7184 break;
7185
7186 case 7:
7187 func (stream, "p");
7188
7189 case 4:
7190 case 6:
7191 default:
7192 break;
7193 }
7194 }
7195 break;
7196
7197 default:
7198 break;
7199 }
7200 }
7201
7202 static void
7203 print_mve_vcvt_size (struct disassemble_info *info,
7204 unsigned long given,
7205 enum mve_instructions matched_insn)
7206 {
7207 unsigned long mode = 0;
7208 void *stream = info->stream;
7209 fprintf_ftype func = info->fprintf_func;
7210
7211 switch (matched_insn)
7212 {
7213 case MVE_VCVT_FP_FIX_VEC:
7214 {
7215 mode = (((given & 0x200) >> 7)
7216 | ((given & 0x10000000) >> 27)
7217 | ((given & 0x100) >> 8));
7218
7219 switch (mode)
7220 {
7221 case 0:
7222 func (stream, "f16.s16");
7223 break;
7224
7225 case 1:
7226 func (stream, "s16.f16");
7227 break;
7228
7229 case 2:
7230 func (stream, "f16.u16");
7231 break;
7232
7233 case 3:
7234 func (stream, "u16.f16");
7235 break;
7236
7237 case 4:
7238 func (stream, "f32.s32");
7239 break;
7240
7241 case 5:
7242 func (stream, "s32.f32");
7243 break;
7244
7245 case 6:
7246 func (stream, "f32.u32");
7247 break;
7248
7249 case 7:
7250 func (stream, "u32.f32");
7251 break;
7252
7253 default:
7254 break;
7255 }
7256 break;
7257 }
7258 case MVE_VCVT_BETWEEN_FP_INT:
7259 {
7260 unsigned long size = arm_decode_field (given, 18, 19);
7261 unsigned long op = arm_decode_field (given, 7, 8);
7262
7263 if (size == 1)
7264 {
7265 switch (op)
7266 {
7267 case 0:
7268 func (stream, "f16.s16");
7269 break;
7270
7271 case 1:
7272 func (stream, "f16.u16");
7273 break;
7274
7275 case 2:
7276 func (stream, "s16.f16");
7277 break;
7278
7279 case 3:
7280 func (stream, "u16.f16");
7281 break;
7282
7283 default:
7284 break;
7285 }
7286 }
7287 else if (size == 2)
7288 {
7289 switch (op)
7290 {
7291 case 0:
7292 func (stream, "f32.s32");
7293 break;
7294
7295 case 1:
7296 func (stream, "f32.u32");
7297 break;
7298
7299 case 2:
7300 func (stream, "s32.f32");
7301 break;
7302
7303 case 3:
7304 func (stream, "u32.f32");
7305 break;
7306 }
7307 }
7308 }
7309 break;
7310
7311 case MVE_VCVT_FP_HALF_FP:
7312 {
7313 unsigned long op = arm_decode_field (given, 28, 28);
7314 if (op == 0)
7315 func (stream, "f16.f32");
7316 else if (op == 1)
7317 func (stream, "f32.f16");
7318 }
7319 break;
7320
7321 case MVE_VCVT_FROM_FP_TO_INT:
7322 {
7323 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7324
7325 switch (size)
7326 {
7327 case 2:
7328 func (stream, "s16.f16");
7329 break;
7330
7331 case 3:
7332 func (stream, "u16.f16");
7333 break;
7334
7335 case 4:
7336 func (stream, "s32.f32");
7337 break;
7338
7339 case 5:
7340 func (stream, "u32.f32");
7341 break;
7342
7343 default:
7344 break;
7345 }
7346 }
7347 break;
7348
7349 default:
7350 break;
7351 }
7352 }
7353
7354 static void
7355 print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7356 unsigned long rot_width)
7357 {
7358 void *stream = info->stream;
7359 fprintf_ftype func = info->fprintf_func;
7360
7361 if (rot_width == 1)
7362 {
7363 switch (rot)
7364 {
7365 case 0:
7366 func (stream, "90");
7367 break;
7368 case 1:
7369 func (stream, "270");
7370 break;
7371 default:
7372 break;
7373 }
7374 }
7375 else if (rot_width == 2)
7376 {
7377 switch (rot)
7378 {
7379 case 0:
7380 func (stream, "0");
7381 break;
7382 case 1:
7383 func (stream, "90");
7384 break;
7385 case 2:
7386 func (stream, "180");
7387 break;
7388 case 3:
7389 func (stream, "270");
7390 break;
7391 default:
7392 break;
7393 }
7394 }
7395 }
7396
7397 static void
7398 print_instruction_predicate (struct disassemble_info *info)
7399 {
7400 void *stream = info->stream;
7401 fprintf_ftype func = info->fprintf_func;
7402
7403 if (vpt_block_state.next_pred_state == PRED_THEN)
7404 func (stream, "t");
7405 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7406 func (stream, "e");
7407 }
7408
7409 static void
7410 print_mve_size (struct disassemble_info *info,
7411 unsigned long size,
7412 enum mve_instructions matched_insn)
7413 {
7414 void *stream = info->stream;
7415 fprintf_ftype func = info->fprintf_func;
7416
7417 switch (matched_insn)
7418 {
7419 case MVE_VABAV:
7420 case MVE_VABD_VEC:
7421 case MVE_VABS_FP:
7422 case MVE_VABS_VEC:
7423 case MVE_VADD_VEC_T1:
7424 case MVE_VADD_VEC_T2:
7425 case MVE_VADDV:
7426 case MVE_VBRSR:
7427 case MVE_VCADD_VEC:
7428 case MVE_VCLS:
7429 case MVE_VCLZ:
7430 case MVE_VCMP_VEC_T1:
7431 case MVE_VCMP_VEC_T2:
7432 case MVE_VCMP_VEC_T3:
7433 case MVE_VCMP_VEC_T4:
7434 case MVE_VCMP_VEC_T5:
7435 case MVE_VCMP_VEC_T6:
7436 case MVE_VCTP:
7437 case MVE_VDDUP:
7438 case MVE_VDWDUP:
7439 case MVE_VHADD_T1:
7440 case MVE_VHADD_T2:
7441 case MVE_VHCADD:
7442 case MVE_VHSUB_T1:
7443 case MVE_VHSUB_T2:
7444 case MVE_VIDUP:
7445 case MVE_VIWDUP:
7446 case MVE_VLD2:
7447 case MVE_VLD4:
7448 case MVE_VLDRB_GATHER_T1:
7449 case MVE_VLDRH_GATHER_T2:
7450 case MVE_VLDRW_GATHER_T3:
7451 case MVE_VLDRD_GATHER_T4:
7452 case MVE_VLDRB_T1:
7453 case MVE_VLDRH_T2:
7454 case MVE_VMAX:
7455 case MVE_VMAXA:
7456 case MVE_VMAXV:
7457 case MVE_VMAXAV:
7458 case MVE_VMIN:
7459 case MVE_VMINA:
7460 case MVE_VMINV:
7461 case MVE_VMINAV:
7462 case MVE_VMLA:
7463 case MVE_VMLAS:
7464 case MVE_VMUL_VEC_T1:
7465 case MVE_VMUL_VEC_T2:
7466 case MVE_VMULH:
7467 case MVE_VRMULH:
7468 case MVE_VMULL_INT:
7469 case MVE_VNEG_FP:
7470 case MVE_VNEG_VEC:
7471 case MVE_VPT_VEC_T1:
7472 case MVE_VPT_VEC_T2:
7473 case MVE_VPT_VEC_T3:
7474 case MVE_VPT_VEC_T4:
7475 case MVE_VPT_VEC_T5:
7476 case MVE_VPT_VEC_T6:
7477 case MVE_VQABS:
7478 case MVE_VQADD_T1:
7479 case MVE_VQADD_T2:
7480 case MVE_VQDMLADH:
7481 case MVE_VQRDMLADH:
7482 case MVE_VQDMLAH:
7483 case MVE_VQRDMLAH:
7484 case MVE_VQDMLASH:
7485 case MVE_VQRDMLASH:
7486 case MVE_VQDMLSDH:
7487 case MVE_VQRDMLSDH:
7488 case MVE_VQDMULH_T1:
7489 case MVE_VQRDMULH_T2:
7490 case MVE_VQDMULH_T3:
7491 case MVE_VQRDMULH_T4:
7492 case MVE_VQNEG:
7493 case MVE_VQRSHL_T1:
7494 case MVE_VQRSHL_T2:
7495 case MVE_VQSHL_T1:
7496 case MVE_VQSHL_T4:
7497 case MVE_VQSUB_T1:
7498 case MVE_VQSUB_T2:
7499 case MVE_VREV32:
7500 case MVE_VREV64:
7501 case MVE_VRHADD:
7502 case MVE_VRINT_FP:
7503 case MVE_VRSHL_T1:
7504 case MVE_VRSHL_T2:
7505 case MVE_VSHL_T2:
7506 case MVE_VSHL_T3:
7507 case MVE_VSHLL_T2:
7508 case MVE_VST2:
7509 case MVE_VST4:
7510 case MVE_VSTRB_SCATTER_T1:
7511 case MVE_VSTRH_SCATTER_T2:
7512 case MVE_VSTRW_SCATTER_T3:
7513 case MVE_VSTRB_T1:
7514 case MVE_VSTRH_T2:
7515 case MVE_VSUB_VEC_T1:
7516 case MVE_VSUB_VEC_T2:
7517 if (size <= 3)
7518 func (stream, "%s", mve_vec_sizename[size]);
7519 else
7520 func (stream, "<undef size>");
7521 break;
7522
7523 case MVE_VABD_FP:
7524 case MVE_VADD_FP_T1:
7525 case MVE_VADD_FP_T2:
7526 case MVE_VSUB_FP_T1:
7527 case MVE_VSUB_FP_T2:
7528 case MVE_VCMP_FP_T1:
7529 case MVE_VCMP_FP_T2:
7530 case MVE_VFMA_FP_SCALAR:
7531 case MVE_VFMA_FP:
7532 case MVE_VFMS_FP:
7533 case MVE_VFMAS_FP_SCALAR:
7534 case MVE_VMAXNM_FP:
7535 case MVE_VMAXNMA_FP:
7536 case MVE_VMAXNMV_FP:
7537 case MVE_VMAXNMAV_FP:
7538 case MVE_VMINNM_FP:
7539 case MVE_VMINNMA_FP:
7540 case MVE_VMINNMV_FP:
7541 case MVE_VMINNMAV_FP:
7542 case MVE_VMUL_FP_T1:
7543 case MVE_VMUL_FP_T2:
7544 case MVE_VPT_FP_T1:
7545 case MVE_VPT_FP_T2:
7546 if (size == 0)
7547 func (stream, "32");
7548 else if (size == 1)
7549 func (stream, "16");
7550 break;
7551
7552 case MVE_VCADD_FP:
7553 case MVE_VCMLA_FP:
7554 case MVE_VCMUL_FP:
7555 case MVE_VMLADAV_T1:
7556 case MVE_VMLALDAV:
7557 case MVE_VMLSDAV_T1:
7558 case MVE_VMLSLDAV:
7559 case MVE_VMOVN:
7560 case MVE_VQDMULL_T1:
7561 case MVE_VQDMULL_T2:
7562 case MVE_VQMOVN:
7563 case MVE_VQMOVUN:
7564 if (size == 0)
7565 func (stream, "16");
7566 else if (size == 1)
7567 func (stream, "32");
7568 break;
7569
7570 case MVE_VMOVL:
7571 if (size == 1)
7572 func (stream, "8");
7573 else if (size == 2)
7574 func (stream, "16");
7575 break;
7576
7577 case MVE_VDUP:
7578 switch (size)
7579 {
7580 case 0:
7581 func (stream, "32");
7582 break;
7583 case 1:
7584 func (stream, "16");
7585 break;
7586 case 2:
7587 func (stream, "8");
7588 break;
7589 default:
7590 break;
7591 }
7592 break;
7593
7594 case MVE_VMOV_GP_TO_VEC_LANE:
7595 case MVE_VMOV_VEC_LANE_TO_GP:
7596 switch (size)
7597 {
7598 case 0: case 4:
7599 func (stream, "32");
7600 break;
7601
7602 case 1: case 3:
7603 case 5: case 7:
7604 func (stream, "16");
7605 break;
7606
7607 case 8: case 9: case 10: case 11:
7608 case 12: case 13: case 14: case 15:
7609 func (stream, "8");
7610 break;
7611
7612 default:
7613 break;
7614 }
7615 break;
7616
7617 case MVE_VMOV_IMM_TO_VEC:
7618 switch (size)
7619 {
7620 case 0: case 4: case 8:
7621 case 12: case 24: case 26:
7622 func (stream, "i32");
7623 break;
7624 case 16: case 20:
7625 func (stream, "i16");
7626 break;
7627 case 28:
7628 func (stream, "i8");
7629 break;
7630 case 29:
7631 func (stream, "i64");
7632 break;
7633 case 30:
7634 func (stream, "f32");
7635 break;
7636 default:
7637 break;
7638 }
7639 break;
7640
7641 case MVE_VMULL_POLY:
7642 if (size == 0)
7643 func (stream, "p8");
7644 else if (size == 1)
7645 func (stream, "p16");
7646 break;
7647
7648 case MVE_VMVN_IMM:
7649 switch (size)
7650 {
7651 case 0: case 2: case 4:
7652 case 6: case 12: case 13:
7653 func (stream, "32");
7654 break;
7655
7656 case 8: case 10:
7657 func (stream, "16");
7658 break;
7659
7660 default:
7661 break;
7662 }
7663 break;
7664
7665 case MVE_VBIC_IMM:
7666 case MVE_VORR_IMM:
7667 switch (size)
7668 {
7669 case 1: case 3:
7670 case 5: case 7:
7671 func (stream, "32");
7672 break;
7673
7674 case 9: case 11:
7675 func (stream, "16");
7676 break;
7677
7678 default:
7679 break;
7680 }
7681 break;
7682
7683 case MVE_VQSHRN:
7684 case MVE_VQSHRUN:
7685 case MVE_VQRSHRN:
7686 case MVE_VQRSHRUN:
7687 case MVE_VRSHRN:
7688 case MVE_VSHRN:
7689 {
7690 switch (size)
7691 {
7692 case 1:
7693 func (stream, "16");
7694 break;
7695
7696 case 2: case 3:
7697 func (stream, "32");
7698 break;
7699
7700 default:
7701 break;
7702 }
7703 }
7704 break;
7705
7706 case MVE_VQSHL_T2:
7707 case MVE_VQSHLU_T3:
7708 case MVE_VRSHR:
7709 case MVE_VSHL_T1:
7710 case MVE_VSHLL_T1:
7711 case MVE_VSHR:
7712 case MVE_VSLI:
7713 case MVE_VSRI:
7714 {
7715 switch (size)
7716 {
7717 case 1:
7718 func (stream, "8");
7719 break;
7720
7721 case 2: case 3:
7722 func (stream, "16");
7723 break;
7724
7725 case 4: case 5: case 6: case 7:
7726 func (stream, "32");
7727 break;
7728
7729 default:
7730 break;
7731 }
7732 }
7733 break;
7734
7735 default:
7736 break;
7737 }
7738 }
7739
7740 static void
7741 print_mve_shift_n (struct disassemble_info *info, long given,
7742 enum mve_instructions matched_insn)
7743 {
7744 void *stream = info->stream;
7745 fprintf_ftype func = info->fprintf_func;
7746
7747 int startAt0
7748 = matched_insn == MVE_VQSHL_T2
7749 || matched_insn == MVE_VQSHLU_T3
7750 || matched_insn == MVE_VSHL_T1
7751 || matched_insn == MVE_VSHLL_T1
7752 || matched_insn == MVE_VSLI;
7753
7754 unsigned imm6 = (given & 0x3f0000) >> 16;
7755
7756 if (matched_insn == MVE_VSHLL_T1)
7757 imm6 &= 0x1f;
7758
7759 unsigned shiftAmount = 0;
7760 if ((imm6 & 0x20) != 0)
7761 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7762 else if ((imm6 & 0x10) != 0)
7763 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7764 else if ((imm6 & 0x08) != 0)
7765 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7766 else
7767 print_mve_undefined (info, UNDEF_SIZE_0);
7768
7769 func (stream, "%u", shiftAmount);
7770 }
7771
7772 static void
7773 print_vec_condition (struct disassemble_info *info, long given,
7774 enum mve_instructions matched_insn)
7775 {
7776 void *stream = info->stream;
7777 fprintf_ftype func = info->fprintf_func;
7778 long vec_cond = 0;
7779
7780 switch (matched_insn)
7781 {
7782 case MVE_VPT_FP_T1:
7783 case MVE_VCMP_FP_T1:
7784 vec_cond = (((given & 0x1000) >> 10)
7785 | ((given & 1) << 1)
7786 | ((given & 0x0080) >> 7));
7787 func (stream, "%s",vec_condnames[vec_cond]);
7788 break;
7789
7790 case MVE_VPT_FP_T2:
7791 case MVE_VCMP_FP_T2:
7792 vec_cond = (((given & 0x1000) >> 10)
7793 | ((given & 0x0020) >> 4)
7794 | ((given & 0x0080) >> 7));
7795 func (stream, "%s",vec_condnames[vec_cond]);
7796 break;
7797
7798 case MVE_VPT_VEC_T1:
7799 case MVE_VCMP_VEC_T1:
7800 vec_cond = (given & 0x0080) >> 7;
7801 func (stream, "%s",vec_condnames[vec_cond]);
7802 break;
7803
7804 case MVE_VPT_VEC_T2:
7805 case MVE_VCMP_VEC_T2:
7806 vec_cond = 2 | ((given & 0x0080) >> 7);
7807 func (stream, "%s",vec_condnames[vec_cond]);
7808 break;
7809
7810 case MVE_VPT_VEC_T3:
7811 case MVE_VCMP_VEC_T3:
7812 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7813 func (stream, "%s",vec_condnames[vec_cond]);
7814 break;
7815
7816 case MVE_VPT_VEC_T4:
7817 case MVE_VCMP_VEC_T4:
7818 vec_cond = (given & 0x0080) >> 7;
7819 func (stream, "%s",vec_condnames[vec_cond]);
7820 break;
7821
7822 case MVE_VPT_VEC_T5:
7823 case MVE_VCMP_VEC_T5:
7824 vec_cond = 2 | ((given & 0x0080) >> 7);
7825 func (stream, "%s",vec_condnames[vec_cond]);
7826 break;
7827
7828 case MVE_VPT_VEC_T6:
7829 case MVE_VCMP_VEC_T6:
7830 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7831 func (stream, "%s",vec_condnames[vec_cond]);
7832 break;
7833
7834 case MVE_NONE:
7835 case MVE_VPST:
7836 default:
7837 break;
7838 }
7839 }
7840
7841 #define W_BIT 21
7842 #define I_BIT 22
7843 #define U_BIT 23
7844 #define P_BIT 24
7845
7846 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7847 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7848 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7849 #define PRE_BIT_SET (given & (1 << P_BIT))
7850
7851
7852 /* Print one coprocessor instruction on INFO->STREAM.
7853 Return TRUE if the instuction matched, FALSE if this is not a
7854 recognised coprocessor instruction. */
7855
7856 static bfd_boolean
7857 print_insn_coprocessor (bfd_vma pc,
7858 struct disassemble_info *info,
7859 long given,
7860 bfd_boolean thumb)
7861 {
7862 const struct sopcode32 *insn;
7863 void *stream = info->stream;
7864 fprintf_ftype func = info->fprintf_func;
7865 unsigned long mask;
7866 unsigned long value = 0;
7867 int cond;
7868 int cp_num;
7869 struct arm_private_data *private_data = info->private_data;
7870 arm_feature_set allowed_arches = ARM_ARCH_NONE;
7871 arm_feature_set arm_ext_v8_1m_main =
7872 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
7873
7874 allowed_arches = private_data->features;
7875
7876 for (insn = coprocessor_opcodes; insn->assembler; insn++)
7877 {
7878 unsigned long u_reg = 16;
7879 bfd_boolean is_unpredictable = FALSE;
7880 signed long value_in_comment = 0;
7881 const char *c;
7882
7883 if (ARM_FEATURE_ZERO (insn->arch))
7884 switch (insn->value)
7885 {
7886 case SENTINEL_IWMMXT_START:
7887 if (info->mach != bfd_mach_arm_XScale
7888 && info->mach != bfd_mach_arm_iWMMXt
7889 && info->mach != bfd_mach_arm_iWMMXt2)
7890 do
7891 insn++;
7892 while ((! ARM_FEATURE_ZERO (insn->arch))
7893 && insn->value != SENTINEL_IWMMXT_END);
7894 continue;
7895
7896 case SENTINEL_IWMMXT_END:
7897 continue;
7898
7899 case SENTINEL_GENERIC_START:
7900 allowed_arches = private_data->features;
7901 continue;
7902
7903 default:
7904 abort ();
7905 }
7906
7907 mask = insn->mask;
7908 value = insn->value;
7909 cp_num = (given >> 8) & 0xf;
7910
7911 if (thumb)
7912 {
7913 /* The high 4 bits are 0xe for Arm conditional instructions, and
7914 0xe for arm unconditional instructions. The rest of the
7915 encoding is the same. */
7916 mask |= 0xf0000000;
7917 value |= 0xe0000000;
7918 if (ifthen_state)
7919 cond = IFTHEN_COND;
7920 else
7921 cond = COND_UNCOND;
7922 }
7923 else
7924 {
7925 /* Only match unconditional instuctions against unconditional
7926 patterns. */
7927 if ((given & 0xf0000000) == 0xf0000000)
7928 {
7929 mask |= 0xf0000000;
7930 cond = COND_UNCOND;
7931 }
7932 else
7933 {
7934 cond = (given >> 28) & 0xf;
7935 if (cond == 0xe)
7936 cond = COND_UNCOND;
7937 }
7938 }
7939
7940 if ((insn->isa == T32 && !thumb)
7941 || (insn->isa == ARM && thumb))
7942 continue;
7943
7944 if ((given & mask) != value)
7945 continue;
7946
7947 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
7948 continue;
7949
7950 if (insn->value == 0xfe000010 /* mcr2 */
7951 || insn->value == 0xfe100010 /* mrc2 */
7952 || insn->value == 0xfc100000 /* ldc2 */
7953 || insn->value == 0xfc000000) /* stc2 */
7954 {
7955 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7956 is_unpredictable = TRUE;
7957
7958 /* Armv8.1-M Mainline FP & MVE instructions. */
7959 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7960 && !ARM_CPU_IS_ANY (allowed_arches)
7961 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7962 continue;
7963
7964 }
7965 else if (insn->value == 0x0e000000 /* cdp */
7966 || insn->value == 0xfe000000 /* cdp2 */
7967 || insn->value == 0x0e000010 /* mcr */
7968 || insn->value == 0x0e100010 /* mrc */
7969 || insn->value == 0x0c100000 /* ldc */
7970 || insn->value == 0x0c000000) /* stc */
7971 {
7972 /* Floating-point instructions. */
7973 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7974 continue;
7975
7976 /* Armv8.1-M Mainline FP & MVE instructions. */
7977 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7978 && !ARM_CPU_IS_ANY (allowed_arches)
7979 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7980 continue;
7981 }
7982 else if ((insn->value == 0xec100f80 /* vldr (system register) */
7983 || insn->value == 0xec000f80) /* vstr (system register) */
7984 && arm_decode_field (given, 24, 24) == 0
7985 && arm_decode_field (given, 21, 21) == 0)
7986 /* If the P and W bits are both 0 then these encodings match the MVE
7987 VLDR and VSTR instructions, these are in a different table, so we
7988 don't let it match here. */
7989 continue;
7990
7991 for (c = insn->assembler; *c; c++)
7992 {
7993 if (*c == '%')
7994 {
7995 const char mod = *++c;
7996 switch (mod)
7997 {
7998 case '%':
7999 func (stream, "%%");
8000 break;
8001
8002 case 'A':
8003 case 'K':
8004 {
8005 int rn = (given >> 16) & 0xf;
8006 bfd_vma offset = given & 0xff;
8007
8008 if (mod == 'K')
8009 offset = given & 0x7f;
8010
8011 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8012
8013 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8014 {
8015 /* Not unindexed. The offset is scaled. */
8016 if (cp_num == 9)
8017 /* vldr.16/vstr.16 will shift the address
8018 left by 1 bit only. */
8019 offset = offset * 2;
8020 else
8021 offset = offset * 4;
8022
8023 if (NEGATIVE_BIT_SET)
8024 offset = - offset;
8025 if (rn != 15)
8026 value_in_comment = offset;
8027 }
8028
8029 if (PRE_BIT_SET)
8030 {
8031 if (offset)
8032 func (stream, ", #%d]%s",
8033 (int) offset,
8034 WRITEBACK_BIT_SET ? "!" : "");
8035 else if (NEGATIVE_BIT_SET)
8036 func (stream, ", #-0]");
8037 else
8038 func (stream, "]");
8039 }
8040 else
8041 {
8042 func (stream, "]");
8043
8044 if (WRITEBACK_BIT_SET)
8045 {
8046 if (offset)
8047 func (stream, ", #%d", (int) offset);
8048 else if (NEGATIVE_BIT_SET)
8049 func (stream, ", #-0");
8050 }
8051 else
8052 {
8053 func (stream, ", {%s%d}",
8054 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
8055 (int) offset);
8056 value_in_comment = offset;
8057 }
8058 }
8059 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8060 {
8061 func (stream, "\t; ");
8062 /* For unaligned PCs, apply off-by-alignment
8063 correction. */
8064 info->print_address_func (offset + pc
8065 + info->bytes_per_chunk * 2
8066 - (pc & 3),
8067 info);
8068 }
8069 }
8070 break;
8071
8072 case 'B':
8073 {
8074 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8075 int offset = (given >> 1) & 0x3f;
8076
8077 if (offset == 1)
8078 func (stream, "{d%d}", regno);
8079 else if (regno + offset > 32)
8080 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8081 else
8082 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8083 }
8084 break;
8085
8086 case 'C':
8087 {
8088 bfd_boolean single = ((given >> 8) & 1) == 0;
8089 char reg_prefix = single ? 's' : 'd';
8090 int Dreg = (given >> 22) & 0x1;
8091 int Vdreg = (given >> 12) & 0xf;
8092 int reg = single ? ((Vdreg << 1) | Dreg)
8093 : ((Dreg << 4) | Vdreg);
8094 int num = (given >> (single ? 0 : 1)) & 0x7f;
8095 int maxreg = single ? 31 : 15;
8096 int topreg = reg + num - 1;
8097
8098 if (!num)
8099 func (stream, "{VPR}");
8100 else if (num == 1)
8101 func (stream, "{%c%d, VPR}", reg_prefix, reg);
8102 else if (topreg > maxreg)
8103 func (stream, "{%c%d-<overflow reg d%d, VPR}",
8104 reg_prefix, reg, single ? topreg >> 1 : topreg);
8105 else
8106 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8107 reg_prefix, topreg);
8108 }
8109 break;
8110
8111 case 'u':
8112 if (cond != COND_UNCOND)
8113 is_unpredictable = TRUE;
8114
8115 /* Fall through. */
8116 case 'c':
8117 if (cond != COND_UNCOND && cp_num == 9)
8118 is_unpredictable = TRUE;
8119
8120 func (stream, "%s", arm_conditional[cond]);
8121 break;
8122
8123 case 'I':
8124 /* Print a Cirrus/DSP shift immediate. */
8125 /* Immediates are 7bit signed ints with bits 0..3 in
8126 bits 0..3 of opcode and bits 4..6 in bits 5..7
8127 of opcode. */
8128 {
8129 int imm;
8130
8131 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8132
8133 /* Is ``imm'' a negative number? */
8134 if (imm & 0x40)
8135 imm -= 0x80;
8136
8137 func (stream, "%d", imm);
8138 }
8139
8140 break;
8141
8142 case 'J':
8143 {
8144 unsigned long regno
8145 = arm_decode_field_multiple (given, 13, 15, 22, 22);
8146
8147 switch (regno)
8148 {
8149 case 0x1:
8150 func (stream, "FPSCR");
8151 break;
8152 case 0x2:
8153 func (stream, "FPSCR_nzcvqc");
8154 break;
8155 case 0xc:
8156 func (stream, "VPR");
8157 break;
8158 case 0xd:
8159 func (stream, "P0");
8160 break;
8161 case 0xe:
8162 func (stream, "FPCXTNS");
8163 break;
8164 case 0xf:
8165 func (stream, "FPCXTS");
8166 break;
8167 default:
8168 func (stream, "<invalid reg %lu>", regno);
8169 break;
8170 }
8171 }
8172 break;
8173
8174 case 'F':
8175 switch (given & 0x00408000)
8176 {
8177 case 0:
8178 func (stream, "4");
8179 break;
8180 case 0x8000:
8181 func (stream, "1");
8182 break;
8183 case 0x00400000:
8184 func (stream, "2");
8185 break;
8186 default:
8187 func (stream, "3");
8188 }
8189 break;
8190
8191 case 'P':
8192 switch (given & 0x00080080)
8193 {
8194 case 0:
8195 func (stream, "s");
8196 break;
8197 case 0x80:
8198 func (stream, "d");
8199 break;
8200 case 0x00080000:
8201 func (stream, "e");
8202 break;
8203 default:
8204 func (stream, _("<illegal precision>"));
8205 break;
8206 }
8207 break;
8208
8209 case 'Q':
8210 switch (given & 0x00408000)
8211 {
8212 case 0:
8213 func (stream, "s");
8214 break;
8215 case 0x8000:
8216 func (stream, "d");
8217 break;
8218 case 0x00400000:
8219 func (stream, "e");
8220 break;
8221 default:
8222 func (stream, "p");
8223 break;
8224 }
8225 break;
8226
8227 case 'R':
8228 switch (given & 0x60)
8229 {
8230 case 0:
8231 break;
8232 case 0x20:
8233 func (stream, "p");
8234 break;
8235 case 0x40:
8236 func (stream, "m");
8237 break;
8238 default:
8239 func (stream, "z");
8240 break;
8241 }
8242 break;
8243
8244 case '0': case '1': case '2': case '3': case '4':
8245 case '5': case '6': case '7': case '8': case '9':
8246 {
8247 int width;
8248
8249 c = arm_decode_bitfield (c, given, &value, &width);
8250
8251 switch (*c)
8252 {
8253 case 'R':
8254 if (value == 15)
8255 is_unpredictable = TRUE;
8256 /* Fall through. */
8257 case 'r':
8258 if (c[1] == 'u')
8259 {
8260 /* Eat the 'u' character. */
8261 ++ c;
8262
8263 if (u_reg == value)
8264 is_unpredictable = TRUE;
8265 u_reg = value;
8266 }
8267 func (stream, "%s", arm_regnames[value]);
8268 break;
8269 case 'V':
8270 if (given & (1 << 6))
8271 goto Q;
8272 /* FALLTHROUGH */
8273 case 'D':
8274 func (stream, "d%ld", value);
8275 break;
8276 case 'Q':
8277 Q:
8278 if (value & 1)
8279 func (stream, "<illegal reg q%ld.5>", value >> 1);
8280 else
8281 func (stream, "q%ld", value >> 1);
8282 break;
8283 case 'd':
8284 func (stream, "%ld", value);
8285 value_in_comment = value;
8286 break;
8287 case 'E':
8288 {
8289 /* Converts immediate 8 bit back to float value. */
8290 unsigned floatVal = (value & 0x80) << 24
8291 | (value & 0x3F) << 19
8292 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8293
8294 /* Quarter float have a maximum value of 31.0.
8295 Get floating point value multiplied by 1e7.
8296 The maximum value stays in limit of a 32-bit int. */
8297 unsigned decVal =
8298 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8299 (16 + (value & 0xF));
8300
8301 if (!(decVal % 1000000))
8302 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8303 floatVal, value & 0x80 ? '-' : ' ',
8304 decVal / 10000000,
8305 decVal % 10000000 / 1000000);
8306 else if (!(decVal % 10000))
8307 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8308 floatVal, value & 0x80 ? '-' : ' ',
8309 decVal / 10000000,
8310 decVal % 10000000 / 10000);
8311 else
8312 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8313 floatVal, value & 0x80 ? '-' : ' ',
8314 decVal / 10000000, decVal % 10000000);
8315 break;
8316 }
8317 case 'k':
8318 {
8319 int from = (given & (1 << 7)) ? 32 : 16;
8320 func (stream, "%ld", from - value);
8321 }
8322 break;
8323
8324 case 'f':
8325 if (value > 7)
8326 func (stream, "#%s", arm_fp_const[value & 7]);
8327 else
8328 func (stream, "f%ld", value);
8329 break;
8330
8331 case 'w':
8332 if (width == 2)
8333 func (stream, "%s", iwmmxt_wwnames[value]);
8334 else
8335 func (stream, "%s", iwmmxt_wwssnames[value]);
8336 break;
8337
8338 case 'g':
8339 func (stream, "%s", iwmmxt_regnames[value]);
8340 break;
8341 case 'G':
8342 func (stream, "%s", iwmmxt_cregnames[value]);
8343 break;
8344
8345 case 'x':
8346 func (stream, "0x%lx", (value & 0xffffffffUL));
8347 break;
8348
8349 case 'c':
8350 switch (value)
8351 {
8352 case 0:
8353 func (stream, "eq");
8354 break;
8355
8356 case 1:
8357 func (stream, "vs");
8358 break;
8359
8360 case 2:
8361 func (stream, "ge");
8362 break;
8363
8364 case 3:
8365 func (stream, "gt");
8366 break;
8367
8368 default:
8369 func (stream, "??");
8370 break;
8371 }
8372 break;
8373
8374 case '`':
8375 c++;
8376 if (value == 0)
8377 func (stream, "%c", *c);
8378 break;
8379 case '\'':
8380 c++;
8381 if (value == ((1ul << width) - 1))
8382 func (stream, "%c", *c);
8383 break;
8384 case '?':
8385 func (stream, "%c", c[(1 << width) - (int) value]);
8386 c += 1 << width;
8387 break;
8388 default:
8389 abort ();
8390 }
8391 }
8392 break;
8393
8394 case 'y':
8395 case 'z':
8396 {
8397 int single = *c++ == 'y';
8398 int regno;
8399
8400 switch (*c)
8401 {
8402 case '4': /* Sm pair */
8403 case '0': /* Sm, Dm */
8404 regno = given & 0x0000000f;
8405 if (single)
8406 {
8407 regno <<= 1;
8408 regno += (given >> 5) & 1;
8409 }
8410 else
8411 regno += ((given >> 5) & 1) << 4;
8412 break;
8413
8414 case '1': /* Sd, Dd */
8415 regno = (given >> 12) & 0x0000000f;
8416 if (single)
8417 {
8418 regno <<= 1;
8419 regno += (given >> 22) & 1;
8420 }
8421 else
8422 regno += ((given >> 22) & 1) << 4;
8423 break;
8424
8425 case '2': /* Sn, Dn */
8426 regno = (given >> 16) & 0x0000000f;
8427 if (single)
8428 {
8429 regno <<= 1;
8430 regno += (given >> 7) & 1;
8431 }
8432 else
8433 regno += ((given >> 7) & 1) << 4;
8434 break;
8435
8436 case '3': /* List */
8437 func (stream, "{");
8438 regno = (given >> 12) & 0x0000000f;
8439 if (single)
8440 {
8441 regno <<= 1;
8442 regno += (given >> 22) & 1;
8443 }
8444 else
8445 regno += ((given >> 22) & 1) << 4;
8446 break;
8447
8448 default:
8449 abort ();
8450 }
8451
8452 func (stream, "%c%d", single ? 's' : 'd', regno);
8453
8454 if (*c == '3')
8455 {
8456 int count = given & 0xff;
8457
8458 if (single == 0)
8459 count >>= 1;
8460
8461 if (--count)
8462 {
8463 func (stream, "-%c%d",
8464 single ? 's' : 'd',
8465 regno + count);
8466 }
8467
8468 func (stream, "}");
8469 }
8470 else if (*c == '4')
8471 func (stream, ", %c%d", single ? 's' : 'd',
8472 regno + 1);
8473 }
8474 break;
8475
8476 case 'L':
8477 switch (given & 0x00400100)
8478 {
8479 case 0x00000000: func (stream, "b"); break;
8480 case 0x00400000: func (stream, "h"); break;
8481 case 0x00000100: func (stream, "w"); break;
8482 case 0x00400100: func (stream, "d"); break;
8483 default:
8484 break;
8485 }
8486 break;
8487
8488 case 'Z':
8489 {
8490 /* given (20, 23) | given (0, 3) */
8491 value = ((given >> 16) & 0xf0) | (given & 0xf);
8492 func (stream, "%d", (int) value);
8493 }
8494 break;
8495
8496 case 'l':
8497 /* This is like the 'A' operator, except that if
8498 the width field "M" is zero, then the offset is
8499 *not* multiplied by four. */
8500 {
8501 int offset = given & 0xff;
8502 int multiplier = (given & 0x00000100) ? 4 : 1;
8503
8504 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8505
8506 if (multiplier > 1)
8507 {
8508 value_in_comment = offset * multiplier;
8509 if (NEGATIVE_BIT_SET)
8510 value_in_comment = - value_in_comment;
8511 }
8512
8513 if (offset)
8514 {
8515 if (PRE_BIT_SET)
8516 func (stream, ", #%s%d]%s",
8517 NEGATIVE_BIT_SET ? "-" : "",
8518 offset * multiplier,
8519 WRITEBACK_BIT_SET ? "!" : "");
8520 else
8521 func (stream, "], #%s%d",
8522 NEGATIVE_BIT_SET ? "-" : "",
8523 offset * multiplier);
8524 }
8525 else
8526 func (stream, "]");
8527 }
8528 break;
8529
8530 case 'r':
8531 {
8532 int imm4 = (given >> 4) & 0xf;
8533 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8534 int ubit = ! NEGATIVE_BIT_SET;
8535 const char *rm = arm_regnames [given & 0xf];
8536 const char *rn = arm_regnames [(given >> 16) & 0xf];
8537
8538 switch (puw_bits)
8539 {
8540 case 1:
8541 case 3:
8542 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8543 if (imm4)
8544 func (stream, ", lsl #%d", imm4);
8545 break;
8546
8547 case 4:
8548 case 5:
8549 case 6:
8550 case 7:
8551 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8552 if (imm4 > 0)
8553 func (stream, ", lsl #%d", imm4);
8554 func (stream, "]");
8555 if (puw_bits == 5 || puw_bits == 7)
8556 func (stream, "!");
8557 break;
8558
8559 default:
8560 func (stream, "INVALID");
8561 }
8562 }
8563 break;
8564
8565 case 'i':
8566 {
8567 long imm5;
8568 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8569 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8570 }
8571 break;
8572
8573 default:
8574 abort ();
8575 }
8576 }
8577 else
8578 func (stream, "%c", *c);
8579 }
8580
8581 if (value_in_comment > 32 || value_in_comment < -16)
8582 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
8583
8584 if (is_unpredictable)
8585 func (stream, UNPREDICTABLE_INSTRUCTION);
8586
8587 return TRUE;
8588 }
8589 return FALSE;
8590 }
8591
8592 /* Decodes and prints ARM addressing modes. Returns the offset
8593 used in the address, if any, if it is worthwhile printing the
8594 offset as a hexadecimal value in a comment at the end of the
8595 line of disassembly. */
8596
8597 static signed long
8598 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8599 {
8600 void *stream = info->stream;
8601 fprintf_ftype func = info->fprintf_func;
8602 bfd_vma offset = 0;
8603
8604 if (((given & 0x000f0000) == 0x000f0000)
8605 && ((given & 0x02000000) == 0))
8606 {
8607 offset = given & 0xfff;
8608
8609 func (stream, "[pc");
8610
8611 if (PRE_BIT_SET)
8612 {
8613 /* Pre-indexed. Elide offset of positive zero when
8614 non-writeback. */
8615 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8616 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8617
8618 if (NEGATIVE_BIT_SET)
8619 offset = -offset;
8620
8621 offset += pc + 8;
8622
8623 /* Cope with the possibility of write-back
8624 being used. Probably a very dangerous thing
8625 for the programmer to do, but who are we to
8626 argue ? */
8627 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
8628 }
8629 else /* Post indexed. */
8630 {
8631 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8632
8633 /* Ie ignore the offset. */
8634 offset = pc + 8;
8635 }
8636
8637 func (stream, "\t; ");
8638 info->print_address_func (offset, info);
8639 offset = 0;
8640 }
8641 else
8642 {
8643 func (stream, "[%s",
8644 arm_regnames[(given >> 16) & 0xf]);
8645
8646 if (PRE_BIT_SET)
8647 {
8648 if ((given & 0x02000000) == 0)
8649 {
8650 /* Elide offset of positive zero when non-writeback. */
8651 offset = given & 0xfff;
8652 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8653 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8654 }
8655 else
8656 {
8657 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
8658 arm_decode_shift (given, func, stream, TRUE);
8659 }
8660
8661 func (stream, "]%s",
8662 WRITEBACK_BIT_SET ? "!" : "");
8663 }
8664 else
8665 {
8666 if ((given & 0x02000000) == 0)
8667 {
8668 /* Always show offset. */
8669 offset = given & 0xfff;
8670 func (stream, "], #%s%d",
8671 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8672 }
8673 else
8674 {
8675 func (stream, "], %s",
8676 NEGATIVE_BIT_SET ? "-" : "");
8677 arm_decode_shift (given, func, stream, TRUE);
8678 }
8679 }
8680 if (NEGATIVE_BIT_SET)
8681 offset = -offset;
8682 }
8683
8684 return (signed long) offset;
8685 }
8686
8687 /* Print one neon instruction on INFO->STREAM.
8688 Return TRUE if the instuction matched, FALSE if this is not a
8689 recognised neon instruction. */
8690
8691 static bfd_boolean
8692 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8693 {
8694 const struct opcode32 *insn;
8695 void *stream = info->stream;
8696 fprintf_ftype func = info->fprintf_func;
8697
8698 if (thumb)
8699 {
8700 if ((given & 0xef000000) == 0xef000000)
8701 {
8702 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
8703 unsigned long bit28 = given & (1 << 28);
8704
8705 given &= 0x00ffffff;
8706 if (bit28)
8707 given |= 0xf3000000;
8708 else
8709 given |= 0xf2000000;
8710 }
8711 else if ((given & 0xff000000) == 0xf9000000)
8712 given ^= 0xf9000000 ^ 0xf4000000;
8713 /* vdup is also a valid neon instruction. */
8714 else if ((given & 0xff910f5f) != 0xee800b10)
8715 return FALSE;
8716 }
8717
8718 for (insn = neon_opcodes; insn->assembler; insn++)
8719 {
8720 if ((given & insn->mask) == insn->value)
8721 {
8722 signed long value_in_comment = 0;
8723 bfd_boolean is_unpredictable = FALSE;
8724 const char *c;
8725
8726 for (c = insn->assembler; *c; c++)
8727 {
8728 if (*c == '%')
8729 {
8730 switch (*++c)
8731 {
8732 case '%':
8733 func (stream, "%%");
8734 break;
8735
8736 case 'u':
8737 if (thumb && ifthen_state)
8738 is_unpredictable = TRUE;
8739
8740 /* Fall through. */
8741 case 'c':
8742 if (thumb && ifthen_state)
8743 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8744 break;
8745
8746 case 'A':
8747 {
8748 static const unsigned char enc[16] =
8749 {
8750 0x4, 0x14, /* st4 0,1 */
8751 0x4, /* st1 2 */
8752 0x4, /* st2 3 */
8753 0x3, /* st3 4 */
8754 0x13, /* st3 5 */
8755 0x3, /* st1 6 */
8756 0x1, /* st1 7 */
8757 0x2, /* st2 8 */
8758 0x12, /* st2 9 */
8759 0x2, /* st1 10 */
8760 0, 0, 0, 0, 0
8761 };
8762 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8763 int rn = ((given >> 16) & 0xf);
8764 int rm = ((given >> 0) & 0xf);
8765 int align = ((given >> 4) & 0x3);
8766 int type = ((given >> 8) & 0xf);
8767 int n = enc[type] & 0xf;
8768 int stride = (enc[type] >> 4) + 1;
8769 int ix;
8770
8771 func (stream, "{");
8772 if (stride > 1)
8773 for (ix = 0; ix != n; ix++)
8774 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
8775 else if (n == 1)
8776 func (stream, "d%d", rd);
8777 else
8778 func (stream, "d%d-d%d", rd, rd + n - 1);
8779 func (stream, "}, [%s", arm_regnames[rn]);
8780 if (align)
8781 func (stream, " :%d", 32 << align);
8782 func (stream, "]");
8783 if (rm == 0xd)
8784 func (stream, "!");
8785 else if (rm != 0xf)
8786 func (stream, ", %s", arm_regnames[rm]);
8787 }
8788 break;
8789
8790 case 'B':
8791 {
8792 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8793 int rn = ((given >> 16) & 0xf);
8794 int rm = ((given >> 0) & 0xf);
8795 int idx_align = ((given >> 4) & 0xf);
8796 int align = 0;
8797 int size = ((given >> 10) & 0x3);
8798 int idx = idx_align >> (size + 1);
8799 int length = ((given >> 8) & 3) + 1;
8800 int stride = 1;
8801 int i;
8802
8803 if (length > 1 && size > 0)
8804 stride = (idx_align & (1 << size)) ? 2 : 1;
8805
8806 switch (length)
8807 {
8808 case 1:
8809 {
8810 int amask = (1 << size) - 1;
8811 if ((idx_align & (1 << size)) != 0)
8812 return FALSE;
8813 if (size > 0)
8814 {
8815 if ((idx_align & amask) == amask)
8816 align = 8 << size;
8817 else if ((idx_align & amask) != 0)
8818 return FALSE;
8819 }
8820 }
8821 break;
8822
8823 case 2:
8824 if (size == 2 && (idx_align & 2) != 0)
8825 return FALSE;
8826 align = (idx_align & 1) ? 16 << size : 0;
8827 break;
8828
8829 case 3:
8830 if ((size == 2 && (idx_align & 3) != 0)
8831 || (idx_align & 1) != 0)
8832 return FALSE;
8833 break;
8834
8835 case 4:
8836 if (size == 2)
8837 {
8838 if ((idx_align & 3) == 3)
8839 return FALSE;
8840 align = (idx_align & 3) * 64;
8841 }
8842 else
8843 align = (idx_align & 1) ? 32 << size : 0;
8844 break;
8845
8846 default:
8847 abort ();
8848 }
8849
8850 func (stream, "{");
8851 for (i = 0; i < length; i++)
8852 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8853 rd + i * stride, idx);
8854 func (stream, "}, [%s", arm_regnames[rn]);
8855 if (align)
8856 func (stream, " :%d", align);
8857 func (stream, "]");
8858 if (rm == 0xd)
8859 func (stream, "!");
8860 else if (rm != 0xf)
8861 func (stream, ", %s", arm_regnames[rm]);
8862 }
8863 break;
8864
8865 case 'C':
8866 {
8867 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8868 int rn = ((given >> 16) & 0xf);
8869 int rm = ((given >> 0) & 0xf);
8870 int align = ((given >> 4) & 0x1);
8871 int size = ((given >> 6) & 0x3);
8872 int type = ((given >> 8) & 0x3);
8873 int n = type + 1;
8874 int stride = ((given >> 5) & 0x1);
8875 int ix;
8876
8877 if (stride && (n == 1))
8878 n++;
8879 else
8880 stride++;
8881
8882 func (stream, "{");
8883 if (stride > 1)
8884 for (ix = 0; ix != n; ix++)
8885 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8886 else if (n == 1)
8887 func (stream, "d%d[]", rd);
8888 else
8889 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8890 func (stream, "}, [%s", arm_regnames[rn]);
8891 if (align)
8892 {
8893 align = (8 * (type + 1)) << size;
8894 if (type == 3)
8895 align = (size > 1) ? align >> 1 : align;
8896 if (type == 2 || (type == 0 && !size))
8897 func (stream, " :<bad align %d>", align);
8898 else
8899 func (stream, " :%d", align);
8900 }
8901 func (stream, "]");
8902 if (rm == 0xd)
8903 func (stream, "!");
8904 else if (rm != 0xf)
8905 func (stream, ", %s", arm_regnames[rm]);
8906 }
8907 break;
8908
8909 case 'D':
8910 {
8911 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
8912 int size = (given >> 20) & 3;
8913 int reg = raw_reg & ((4 << size) - 1);
8914 int ix = raw_reg >> size >> 2;
8915
8916 func (stream, "d%d[%d]", reg, ix);
8917 }
8918 break;
8919
8920 case 'E':
8921 /* Neon encoded constant for mov, mvn, vorr, vbic. */
8922 {
8923 int bits = 0;
8924 int cmode = (given >> 8) & 0xf;
8925 int op = (given >> 5) & 0x1;
8926 unsigned long value = 0, hival = 0;
8927 unsigned shift;
8928 int size = 0;
8929 int isfloat = 0;
8930
8931 bits |= ((given >> 24) & 1) << 7;
8932 bits |= ((given >> 16) & 7) << 4;
8933 bits |= ((given >> 0) & 15) << 0;
8934
8935 if (cmode < 8)
8936 {
8937 shift = (cmode >> 1) & 3;
8938 value = (unsigned long) bits << (8 * shift);
8939 size = 32;
8940 }
8941 else if (cmode < 12)
8942 {
8943 shift = (cmode >> 1) & 1;
8944 value = (unsigned long) bits << (8 * shift);
8945 size = 16;
8946 }
8947 else if (cmode < 14)
8948 {
8949 shift = (cmode & 1) + 1;
8950 value = (unsigned long) bits << (8 * shift);
8951 value |= (1ul << (8 * shift)) - 1;
8952 size = 32;
8953 }
8954 else if (cmode == 14)
8955 {
8956 if (op)
8957 {
8958 /* Bit replication into bytes. */
8959 int ix;
8960 unsigned long mask;
8961
8962 value = 0;
8963 hival = 0;
8964 for (ix = 7; ix >= 0; ix--)
8965 {
8966 mask = ((bits >> ix) & 1) ? 0xff : 0;
8967 if (ix <= 3)
8968 value = (value << 8) | mask;
8969 else
8970 hival = (hival << 8) | mask;
8971 }
8972 size = 64;
8973 }
8974 else
8975 {
8976 /* Byte replication. */
8977 value = (unsigned long) bits;
8978 size = 8;
8979 }
8980 }
8981 else if (!op)
8982 {
8983 /* Floating point encoding. */
8984 int tmp;
8985
8986 value = (unsigned long) (bits & 0x7f) << 19;
8987 value |= (unsigned long) (bits & 0x80) << 24;
8988 tmp = bits & 0x40 ? 0x3c : 0x40;
8989 value |= (unsigned long) tmp << 24;
8990 size = 32;
8991 isfloat = 1;
8992 }
8993 else
8994 {
8995 func (stream, "<illegal constant %.8x:%x:%x>",
8996 bits, cmode, op);
8997 size = 32;
8998 break;
8999 }
9000 switch (size)
9001 {
9002 case 8:
9003 func (stream, "#%ld\t; 0x%.2lx", value, value);
9004 break;
9005
9006 case 16:
9007 func (stream, "#%ld\t; 0x%.4lx", value, value);
9008 break;
9009
9010 case 32:
9011 if (isfloat)
9012 {
9013 unsigned char valbytes[4];
9014 double fvalue;
9015
9016 /* Do this a byte at a time so we don't have to
9017 worry about the host's endianness. */
9018 valbytes[0] = value & 0xff;
9019 valbytes[1] = (value >> 8) & 0xff;
9020 valbytes[2] = (value >> 16) & 0xff;
9021 valbytes[3] = (value >> 24) & 0xff;
9022
9023 floatformat_to_double
9024 (& floatformat_ieee_single_little, valbytes,
9025 & fvalue);
9026
9027 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9028 value);
9029 }
9030 else
9031 func (stream, "#%ld\t; 0x%.8lx",
9032 (long) (((value & 0x80000000L) != 0)
9033 ? value | ~0xffffffffL : value),
9034 value);
9035 break;
9036
9037 case 64:
9038 func (stream, "#0x%.8lx%.8lx", hival, value);
9039 break;
9040
9041 default:
9042 abort ();
9043 }
9044 }
9045 break;
9046
9047 case 'F':
9048 {
9049 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9050 int num = (given >> 8) & 0x3;
9051
9052 if (!num)
9053 func (stream, "{d%d}", regno);
9054 else if (num + regno >= 32)
9055 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9056 else
9057 func (stream, "{d%d-d%d}", regno, regno + num);
9058 }
9059 break;
9060
9061
9062 case '0': case '1': case '2': case '3': case '4':
9063 case '5': case '6': case '7': case '8': case '9':
9064 {
9065 int width;
9066 unsigned long value;
9067
9068 c = arm_decode_bitfield (c, given, &value, &width);
9069
9070 switch (*c)
9071 {
9072 case 'r':
9073 func (stream, "%s", arm_regnames[value]);
9074 break;
9075 case 'd':
9076 func (stream, "%ld", value);
9077 value_in_comment = value;
9078 break;
9079 case 'e':
9080 func (stream, "%ld", (1ul << width) - value);
9081 break;
9082
9083 case 'S':
9084 case 'T':
9085 case 'U':
9086 /* Various width encodings. */
9087 {
9088 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9089 int limit;
9090 unsigned low, high;
9091
9092 c++;
9093 if (*c >= '0' && *c <= '9')
9094 limit = *c - '0';
9095 else if (*c >= 'a' && *c <= 'f')
9096 limit = *c - 'a' + 10;
9097 else
9098 abort ();
9099 low = limit >> 2;
9100 high = limit & 3;
9101
9102 if (value < low || value > high)
9103 func (stream, "<illegal width %d>", base << value);
9104 else
9105 func (stream, "%d", base << value);
9106 }
9107 break;
9108 case 'R':
9109 if (given & (1 << 6))
9110 goto Q;
9111 /* FALLTHROUGH */
9112 case 'D':
9113 func (stream, "d%ld", value);
9114 break;
9115 case 'Q':
9116 Q:
9117 if (value & 1)
9118 func (stream, "<illegal reg q%ld.5>", value >> 1);
9119 else
9120 func (stream, "q%ld", value >> 1);
9121 break;
9122
9123 case '`':
9124 c++;
9125 if (value == 0)
9126 func (stream, "%c", *c);
9127 break;
9128 case '\'':
9129 c++;
9130 if (value == ((1ul << width) - 1))
9131 func (stream, "%c", *c);
9132 break;
9133 case '?':
9134 func (stream, "%c", c[(1 << width) - (int) value]);
9135 c += 1 << width;
9136 break;
9137 default:
9138 abort ();
9139 }
9140 }
9141 break;
9142
9143 default:
9144 abort ();
9145 }
9146 }
9147 else
9148 func (stream, "%c", *c);
9149 }
9150
9151 if (value_in_comment > 32 || value_in_comment < -16)
9152 func (stream, "\t; 0x%lx", value_in_comment);
9153
9154 if (is_unpredictable)
9155 func (stream, UNPREDICTABLE_INSTRUCTION);
9156
9157 return TRUE;
9158 }
9159 }
9160 return FALSE;
9161 }
9162
9163 /* Print one mve instruction on INFO->STREAM.
9164 Return TRUE if the instuction matched, FALSE if this is not a
9165 recognised mve instruction. */
9166
9167 static bfd_boolean
9168 print_insn_mve (struct disassemble_info *info, long given)
9169 {
9170 const struct mopcode32 *insn;
9171 void *stream = info->stream;
9172 fprintf_ftype func = info->fprintf_func;
9173
9174 for (insn = mve_opcodes; insn->assembler; insn++)
9175 {
9176 if (((given & insn->mask) == insn->value)
9177 && !is_mve_encoding_conflict (given, insn->mve_op))
9178 {
9179 signed long value_in_comment = 0;
9180 bfd_boolean is_unpredictable = FALSE;
9181 bfd_boolean is_undefined = FALSE;
9182 const char *c;
9183 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9184 enum mve_undefined undefined_cond = UNDEF_NONE;
9185
9186 /* Most vector mve instruction are illegal in a it block.
9187 There are a few exceptions; check for them. */
9188 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9189 {
9190 is_unpredictable = TRUE;
9191 unpredictable_cond = UNPRED_IT_BLOCK;
9192 }
9193 else if (is_mve_unpredictable (given, insn->mve_op,
9194 &unpredictable_cond))
9195 is_unpredictable = TRUE;
9196
9197 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9198 is_undefined = TRUE;
9199
9200 for (c = insn->assembler; *c; c++)
9201 {
9202 if (*c == '%')
9203 {
9204 switch (*++c)
9205 {
9206 case '%':
9207 func (stream, "%%");
9208 break;
9209
9210 case 'a':
9211 /* Don't print anything for '+' as it is implied. */
9212 if (arm_decode_field (given, 23, 23) == 0)
9213 func (stream, "-");
9214 break;
9215
9216 case 'c':
9217 if (ifthen_state)
9218 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9219 break;
9220
9221 case 'd':
9222 print_mve_vld_str_addr (info, given, insn->mve_op);
9223 break;
9224
9225 case 'i':
9226 {
9227 long mve_mask = mve_extract_pred_mask (given);
9228 func (stream, "%s", mve_predicatenames[mve_mask]);
9229 }
9230 break;
9231
9232 case 'j':
9233 {
9234 unsigned int imm5 = 0;
9235 imm5 |= arm_decode_field (given, 6, 7);
9236 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9237 func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9238 }
9239 break;
9240
9241 case 'n':
9242 print_vec_condition (info, given, insn->mve_op);
9243 break;
9244
9245 case 'o':
9246 if (arm_decode_field (given, 0, 0) == 1)
9247 {
9248 unsigned long size
9249 = arm_decode_field (given, 4, 4)
9250 | (arm_decode_field (given, 6, 6) << 1);
9251
9252 func (stream, ", uxtw #%lu", size);
9253 }
9254 break;
9255
9256 case 'm':
9257 print_mve_rounding_mode (info, given, insn->mve_op);
9258 break;
9259
9260 case 's':
9261 print_mve_vcvt_size (info, given, insn->mve_op);
9262 break;
9263
9264 case 'u':
9265 {
9266 unsigned long op1 = arm_decode_field (given, 21, 22);
9267
9268 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9269 {
9270 /* Check for signed. */
9271 if (arm_decode_field (given, 23, 23) == 0)
9272 {
9273 /* We don't print 's' for S32. */
9274 if ((arm_decode_field (given, 5, 6) == 0)
9275 && ((op1 == 0) || (op1 == 1)))
9276 ;
9277 else
9278 func (stream, "s");
9279 }
9280 else
9281 func (stream, "u");
9282 }
9283 else
9284 {
9285 if (arm_decode_field (given, 28, 28) == 0)
9286 func (stream, "s");
9287 else
9288 func (stream, "u");
9289 }
9290 }
9291 break;
9292
9293 case 'v':
9294 print_instruction_predicate (info);
9295 break;
9296
9297 case 'w':
9298 if (arm_decode_field (given, 21, 21) == 1)
9299 func (stream, "!");
9300 break;
9301
9302 case 'B':
9303 print_mve_register_blocks (info, given, insn->mve_op);
9304 break;
9305
9306 case 'E':
9307 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9308
9309 print_simd_imm8 (info, given, 28, insn);
9310 break;
9311
9312 case 'N':
9313 print_mve_vmov_index (info, given);
9314 break;
9315
9316 case 'T':
9317 if (arm_decode_field (given, 12, 12) == 0)
9318 func (stream, "b");
9319 else
9320 func (stream, "t");
9321 break;
9322
9323 case 'X':
9324 if (arm_decode_field (given, 12, 12) == 1)
9325 func (stream, "x");
9326 break;
9327
9328 case '0': case '1': case '2': case '3': case '4':
9329 case '5': case '6': case '7': case '8': case '9':
9330 {
9331 int width;
9332 unsigned long value;
9333
9334 c = arm_decode_bitfield (c, given, &value, &width);
9335
9336 switch (*c)
9337 {
9338 case 'Z':
9339 if (value == 13)
9340 is_unpredictable = TRUE;
9341 else if (value == 15)
9342 func (stream, "zr");
9343 else
9344 func (stream, "%s", arm_regnames[value]);
9345 break;
9346
9347 case 'c':
9348 func (stream, "%s", arm_conditional[value]);
9349 break;
9350
9351 case 'C':
9352 value ^= 1;
9353 func (stream, "%s", arm_conditional[value]);
9354 break;
9355
9356 case 'S':
9357 if (value == 13 || value == 15)
9358 is_unpredictable = TRUE;
9359 else
9360 func (stream, "%s", arm_regnames[value]);
9361 break;
9362
9363 case 's':
9364 print_mve_size (info,
9365 value,
9366 insn->mve_op);
9367 break;
9368 case 'I':
9369 if (value == 1)
9370 func (stream, "i");
9371 break;
9372 case 'A':
9373 if (value == 1)
9374 func (stream, "a");
9375 break;
9376 case 'h':
9377 {
9378 unsigned int odd_reg = (value << 1) | 1;
9379 func (stream, "%s", arm_regnames[odd_reg]);
9380 }
9381 break;
9382 case 'i':
9383 {
9384 unsigned long imm
9385 = arm_decode_field (given, 0, 6);
9386 unsigned long mod_imm = imm;
9387
9388 switch (insn->mve_op)
9389 {
9390 case MVE_VLDRW_GATHER_T5:
9391 case MVE_VSTRW_SCATTER_T5:
9392 mod_imm = mod_imm << 2;
9393 break;
9394 case MVE_VSTRD_SCATTER_T6:
9395 case MVE_VLDRD_GATHER_T6:
9396 mod_imm = mod_imm << 3;
9397 break;
9398
9399 default:
9400 break;
9401 }
9402
9403 func (stream, "%lu", mod_imm);
9404 }
9405 break;
9406 case 'k':
9407 func (stream, "%lu", 64 - value);
9408 break;
9409 case 'l':
9410 {
9411 unsigned int even_reg = value << 1;
9412 func (stream, "%s", arm_regnames[even_reg]);
9413 }
9414 break;
9415 case 'u':
9416 switch (value)
9417 {
9418 case 0:
9419 func (stream, "1");
9420 break;
9421 case 1:
9422 func (stream, "2");
9423 break;
9424 case 2:
9425 func (stream, "4");
9426 break;
9427 case 3:
9428 func (stream, "8");
9429 break;
9430 default:
9431 break;
9432 }
9433 break;
9434 case 'o':
9435 print_mve_rotate (info, value, width);
9436 break;
9437 case 'r':
9438 func (stream, "%s", arm_regnames[value]);
9439 break;
9440 case 'd':
9441 if (insn->mve_op == MVE_VQSHL_T2
9442 || insn->mve_op == MVE_VQSHLU_T3
9443 || insn->mve_op == MVE_VRSHR
9444 || insn->mve_op == MVE_VRSHRN
9445 || insn->mve_op == MVE_VSHL_T1
9446 || insn->mve_op == MVE_VSHLL_T1
9447 || insn->mve_op == MVE_VSHR
9448 || insn->mve_op == MVE_VSHRN
9449 || insn->mve_op == MVE_VSLI
9450 || insn->mve_op == MVE_VSRI)
9451 print_mve_shift_n (info, given, insn->mve_op);
9452 else if (insn->mve_op == MVE_VSHLL_T2)
9453 {
9454 switch (value)
9455 {
9456 case 0x00:
9457 func (stream, "8");
9458 break;
9459 case 0x01:
9460 func (stream, "16");
9461 break;
9462 case 0x10:
9463 print_mve_undefined (info, UNDEF_SIZE_0);
9464 break;
9465 default:
9466 assert (0);
9467 break;
9468 }
9469 }
9470 else
9471 {
9472 if (insn->mve_op == MVE_VSHLC && value == 0)
9473 value = 32;
9474 func (stream, "%ld", value);
9475 value_in_comment = value;
9476 }
9477 break;
9478 case 'F':
9479 func (stream, "s%ld", value);
9480 break;
9481 case 'Q':
9482 if (value & 0x8)
9483 func (stream, "<illegal reg q%ld.5>", value);
9484 else
9485 func (stream, "q%ld", value);
9486 break;
9487 case 'x':
9488 func (stream, "0x%08lx", value);
9489 break;
9490 default:
9491 abort ();
9492 }
9493 break;
9494 default:
9495 abort ();
9496 }
9497 }
9498 }
9499 else
9500 func (stream, "%c", *c);
9501 }
9502
9503 if (value_in_comment > 32 || value_in_comment < -16)
9504 func (stream, "\t; 0x%lx", value_in_comment);
9505
9506 if (is_unpredictable)
9507 print_mve_unpredictable (info, unpredictable_cond);
9508
9509 if (is_undefined)
9510 print_mve_undefined (info, undefined_cond);
9511
9512 if ((vpt_block_state.in_vpt_block == FALSE)
9513 && !ifthen_state
9514 && (is_vpt_instruction (given) == TRUE))
9515 mark_inside_vpt_block (given);
9516 else if (vpt_block_state.in_vpt_block == TRUE)
9517 update_vpt_block_state ();
9518
9519 return TRUE;
9520 }
9521 }
9522 return FALSE;
9523 }
9524
9525
9526 /* Return the name of a v7A special register. */
9527
9528 static const char *
9529 banked_regname (unsigned reg)
9530 {
9531 switch (reg)
9532 {
9533 case 15: return "CPSR";
9534 case 32: return "R8_usr";
9535 case 33: return "R9_usr";
9536 case 34: return "R10_usr";
9537 case 35: return "R11_usr";
9538 case 36: return "R12_usr";
9539 case 37: return "SP_usr";
9540 case 38: return "LR_usr";
9541 case 40: return "R8_fiq";
9542 case 41: return "R9_fiq";
9543 case 42: return "R10_fiq";
9544 case 43: return "R11_fiq";
9545 case 44: return "R12_fiq";
9546 case 45: return "SP_fiq";
9547 case 46: return "LR_fiq";
9548 case 48: return "LR_irq";
9549 case 49: return "SP_irq";
9550 case 50: return "LR_svc";
9551 case 51: return "SP_svc";
9552 case 52: return "LR_abt";
9553 case 53: return "SP_abt";
9554 case 54: return "LR_und";
9555 case 55: return "SP_und";
9556 case 60: return "LR_mon";
9557 case 61: return "SP_mon";
9558 case 62: return "ELR_hyp";
9559 case 63: return "SP_hyp";
9560 case 79: return "SPSR";
9561 case 110: return "SPSR_fiq";
9562 case 112: return "SPSR_irq";
9563 case 114: return "SPSR_svc";
9564 case 116: return "SPSR_abt";
9565 case 118: return "SPSR_und";
9566 case 124: return "SPSR_mon";
9567 case 126: return "SPSR_hyp";
9568 default: return NULL;
9569 }
9570 }
9571
9572 /* Return the name of the DMB/DSB option. */
9573 static const char *
9574 data_barrier_option (unsigned option)
9575 {
9576 switch (option & 0xf)
9577 {
9578 case 0xf: return "sy";
9579 case 0xe: return "st";
9580 case 0xd: return "ld";
9581 case 0xb: return "ish";
9582 case 0xa: return "ishst";
9583 case 0x9: return "ishld";
9584 case 0x7: return "un";
9585 case 0x6: return "unst";
9586 case 0x5: return "nshld";
9587 case 0x3: return "osh";
9588 case 0x2: return "oshst";
9589 case 0x1: return "oshld";
9590 default: return NULL;
9591 }
9592 }
9593
9594 /* Print one ARM instruction from PC on INFO->STREAM. */
9595
9596 static void
9597 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
9598 {
9599 const struct opcode32 *insn;
9600 void *stream = info->stream;
9601 fprintf_ftype func = info->fprintf_func;
9602 struct arm_private_data *private_data = info->private_data;
9603
9604 if (print_insn_coprocessor (pc, info, given, FALSE))
9605 return;
9606
9607 if (print_insn_neon (info, given, FALSE))
9608 return;
9609
9610 for (insn = arm_opcodes; insn->assembler; insn++)
9611 {
9612 if ((given & insn->mask) != insn->value)
9613 continue;
9614
9615 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
9616 continue;
9617
9618 /* Special case: an instruction with all bits set in the condition field
9619 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9620 or by the catchall at the end of the table. */
9621 if ((given & 0xF0000000) != 0xF0000000
9622 || (insn->mask & 0xF0000000) == 0xF0000000
9623 || (insn->mask == 0 && insn->value == 0))
9624 {
9625 unsigned long u_reg = 16;
9626 unsigned long U_reg = 16;
9627 bfd_boolean is_unpredictable = FALSE;
9628 signed long value_in_comment = 0;
9629 const char *c;
9630
9631 for (c = insn->assembler; *c; c++)
9632 {
9633 if (*c == '%')
9634 {
9635 bfd_boolean allow_unpredictable = FALSE;
9636
9637 switch (*++c)
9638 {
9639 case '%':
9640 func (stream, "%%");
9641 break;
9642
9643 case 'a':
9644 value_in_comment = print_arm_address (pc, info, given);
9645 break;
9646
9647 case 'P':
9648 /* Set P address bit and use normal address
9649 printing routine. */
9650 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
9651 break;
9652
9653 case 'S':
9654 allow_unpredictable = TRUE;
9655 /* Fall through. */
9656 case 's':
9657 if ((given & 0x004f0000) == 0x004f0000)
9658 {
9659 /* PC relative with immediate offset. */
9660 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
9661
9662 if (PRE_BIT_SET)
9663 {
9664 /* Elide positive zero offset. */
9665 if (offset || NEGATIVE_BIT_SET)
9666 func (stream, "[pc, #%s%d]\t; ",
9667 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9668 else
9669 func (stream, "[pc]\t; ");
9670 if (NEGATIVE_BIT_SET)
9671 offset = -offset;
9672 info->print_address_func (offset + pc + 8, info);
9673 }
9674 else
9675 {
9676 /* Always show the offset. */
9677 func (stream, "[pc], #%s%d",
9678 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9679 if (! allow_unpredictable)
9680 is_unpredictable = TRUE;
9681 }
9682 }
9683 else
9684 {
9685 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
9686
9687 func (stream, "[%s",
9688 arm_regnames[(given >> 16) & 0xf]);
9689
9690 if (PRE_BIT_SET)
9691 {
9692 if (IMMEDIATE_BIT_SET)
9693 {
9694 /* Elide offset for non-writeback
9695 positive zero. */
9696 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
9697 || offset)
9698 func (stream, ", #%s%d",
9699 NEGATIVE_BIT_SET ? "-" : "", offset);
9700
9701 if (NEGATIVE_BIT_SET)
9702 offset = -offset;
9703
9704 value_in_comment = offset;
9705 }
9706 else
9707 {
9708 /* Register Offset or Register Pre-Indexed. */
9709 func (stream, ", %s%s",
9710 NEGATIVE_BIT_SET ? "-" : "",
9711 arm_regnames[given & 0xf]);
9712
9713 /* Writing back to the register that is the source/
9714 destination of the load/store is unpredictable. */
9715 if (! allow_unpredictable
9716 && WRITEBACK_BIT_SET
9717 && ((given & 0xf) == ((given >> 12) & 0xf)))
9718 is_unpredictable = TRUE;
9719 }
9720
9721 func (stream, "]%s",
9722 WRITEBACK_BIT_SET ? "!" : "");
9723 }
9724 else
9725 {
9726 if (IMMEDIATE_BIT_SET)
9727 {
9728 /* Immediate Post-indexed. */
9729 /* PR 10924: Offset must be printed, even if it is zero. */
9730 func (stream, "], #%s%d",
9731 NEGATIVE_BIT_SET ? "-" : "", offset);
9732 if (NEGATIVE_BIT_SET)
9733 offset = -offset;
9734 value_in_comment = offset;
9735 }
9736 else
9737 {
9738 /* Register Post-indexed. */
9739 func (stream, "], %s%s",
9740 NEGATIVE_BIT_SET ? "-" : "",
9741 arm_regnames[given & 0xf]);
9742
9743 /* Writing back to the register that is the source/
9744 destination of the load/store is unpredictable. */
9745 if (! allow_unpredictable
9746 && (given & 0xf) == ((given >> 12) & 0xf))
9747 is_unpredictable = TRUE;
9748 }
9749
9750 if (! allow_unpredictable)
9751 {
9752 /* Writeback is automatically implied by post- addressing.
9753 Setting the W bit is unnecessary and ARM specify it as
9754 being unpredictable. */
9755 if (WRITEBACK_BIT_SET
9756 /* Specifying the PC register as the post-indexed
9757 registers is also unpredictable. */
9758 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
9759 is_unpredictable = TRUE;
9760 }
9761 }
9762 }
9763 break;
9764
9765 case 'b':
9766 {
9767 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
9768 info->print_address_func (disp * 4 + pc + 8, info);
9769 }
9770 break;
9771
9772 case 'c':
9773 if (((given >> 28) & 0xf) != 0xe)
9774 func (stream, "%s",
9775 arm_conditional [(given >> 28) & 0xf]);
9776 break;
9777
9778 case 'm':
9779 {
9780 int started = 0;
9781 int reg;
9782
9783 func (stream, "{");
9784 for (reg = 0; reg < 16; reg++)
9785 if ((given & (1 << reg)) != 0)
9786 {
9787 if (started)
9788 func (stream, ", ");
9789 started = 1;
9790 func (stream, "%s", arm_regnames[reg]);
9791 }
9792 func (stream, "}");
9793 if (! started)
9794 is_unpredictable = TRUE;
9795 }
9796 break;
9797
9798 case 'q':
9799 arm_decode_shift (given, func, stream, FALSE);
9800 break;
9801
9802 case 'o':
9803 if ((given & 0x02000000) != 0)
9804 {
9805 unsigned int rotate = (given & 0xf00) >> 7;
9806 unsigned int immed = (given & 0xff);
9807 unsigned int a, i;
9808
9809 a = (((immed << (32 - rotate))
9810 | (immed >> rotate)) & 0xffffffff);
9811 /* If there is another encoding with smaller rotate,
9812 the rotate should be specified directly. */
9813 for (i = 0; i < 32; i += 2)
9814 if ((a << i | a >> (32 - i)) <= 0xff)
9815 break;
9816
9817 if (i != rotate)
9818 func (stream, "#%d, %d", immed, rotate);
9819 else
9820 func (stream, "#%d", a);
9821 value_in_comment = a;
9822 }
9823 else
9824 arm_decode_shift (given, func, stream, TRUE);
9825 break;
9826
9827 case 'p':
9828 if ((given & 0x0000f000) == 0x0000f000)
9829 {
9830 arm_feature_set arm_ext_v6 =
9831 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
9832
9833 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9834 mechanism for setting PSR flag bits. They are
9835 obsolete in V6 onwards. */
9836 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
9837 arm_ext_v6))
9838 func (stream, "p");
9839 else
9840 is_unpredictable = TRUE;
9841 }
9842 break;
9843
9844 case 't':
9845 if ((given & 0x01200000) == 0x00200000)
9846 func (stream, "t");
9847 break;
9848
9849 case 'A':
9850 {
9851 int offset = given & 0xff;
9852
9853 value_in_comment = offset * 4;
9854 if (NEGATIVE_BIT_SET)
9855 value_in_comment = - value_in_comment;
9856
9857 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
9858
9859 if (PRE_BIT_SET)
9860 {
9861 if (offset)
9862 func (stream, ", #%d]%s",
9863 (int) value_in_comment,
9864 WRITEBACK_BIT_SET ? "!" : "");
9865 else
9866 func (stream, "]");
9867 }
9868 else
9869 {
9870 func (stream, "]");
9871
9872 if (WRITEBACK_BIT_SET)
9873 {
9874 if (offset)
9875 func (stream, ", #%d", (int) value_in_comment);
9876 }
9877 else
9878 {
9879 func (stream, ", {%d}", (int) offset);
9880 value_in_comment = offset;
9881 }
9882 }
9883 }
9884 break;
9885
9886 case 'B':
9887 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9888 {
9889 bfd_vma address;
9890 bfd_vma offset = 0;
9891
9892 if (! NEGATIVE_BIT_SET)
9893 /* Is signed, hi bits should be ones. */
9894 offset = (-1) ^ 0x00ffffff;
9895
9896 /* Offset is (SignExtend(offset field)<<2). */
9897 offset += given & 0x00ffffff;
9898 offset <<= 2;
9899 address = offset + pc + 8;
9900
9901 if (given & 0x01000000)
9902 /* H bit allows addressing to 2-byte boundaries. */
9903 address += 2;
9904
9905 info->print_address_func (address, info);
9906 }
9907 break;
9908
9909 case 'C':
9910 if ((given & 0x02000200) == 0x200)
9911 {
9912 const char * name;
9913 unsigned sysm = (given & 0x004f0000) >> 16;
9914
9915 sysm |= (given & 0x300) >> 4;
9916 name = banked_regname (sysm);
9917
9918 if (name != NULL)
9919 func (stream, "%s", name);
9920 else
9921 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9922 }
9923 else
9924 {
9925 func (stream, "%cPSR_",
9926 (given & 0x00400000) ? 'S' : 'C');
9927 if (given & 0x80000)
9928 func (stream, "f");
9929 if (given & 0x40000)
9930 func (stream, "s");
9931 if (given & 0x20000)
9932 func (stream, "x");
9933 if (given & 0x10000)
9934 func (stream, "c");
9935 }
9936 break;
9937
9938 case 'U':
9939 if ((given & 0xf0) == 0x60)
9940 {
9941 switch (given & 0xf)
9942 {
9943 case 0xf: func (stream, "sy"); break;
9944 default:
9945 func (stream, "#%d", (int) given & 0xf);
9946 break;
9947 }
9948 }
9949 else
9950 {
9951 const char * opt = data_barrier_option (given & 0xf);
9952 if (opt != NULL)
9953 func (stream, "%s", opt);
9954 else
9955 func (stream, "#%d", (int) given & 0xf);
9956 }
9957 break;
9958
9959 case '0': case '1': case '2': case '3': case '4':
9960 case '5': case '6': case '7': case '8': case '9':
9961 {
9962 int width;
9963 unsigned long value;
9964
9965 c = arm_decode_bitfield (c, given, &value, &width);
9966
9967 switch (*c)
9968 {
9969 case 'R':
9970 if (value == 15)
9971 is_unpredictable = TRUE;
9972 /* Fall through. */
9973 case 'r':
9974 case 'T':
9975 /* We want register + 1 when decoding T. */
9976 if (*c == 'T')
9977 ++value;
9978
9979 if (c[1] == 'u')
9980 {
9981 /* Eat the 'u' character. */
9982 ++ c;
9983
9984 if (u_reg == value)
9985 is_unpredictable = TRUE;
9986 u_reg = value;
9987 }
9988 if (c[1] == 'U')
9989 {
9990 /* Eat the 'U' character. */
9991 ++ c;
9992
9993 if (U_reg == value)
9994 is_unpredictable = TRUE;
9995 U_reg = value;
9996 }
9997 func (stream, "%s", arm_regnames[value]);
9998 break;
9999 case 'd':
10000 func (stream, "%ld", value);
10001 value_in_comment = value;
10002 break;
10003 case 'b':
10004 func (stream, "%ld", value * 8);
10005 value_in_comment = value * 8;
10006 break;
10007 case 'W':
10008 func (stream, "%ld", value + 1);
10009 value_in_comment = value + 1;
10010 break;
10011 case 'x':
10012 func (stream, "0x%08lx", value);
10013
10014 /* Some SWI instructions have special
10015 meanings. */
10016 if ((given & 0x0fffffff) == 0x0FF00000)
10017 func (stream, "\t; IMB");
10018 else if ((given & 0x0fffffff) == 0x0FF00001)
10019 func (stream, "\t; IMBRange");
10020 break;
10021 case 'X':
10022 func (stream, "%01lx", value & 0xf);
10023 value_in_comment = value;
10024 break;
10025 case '`':
10026 c++;
10027 if (value == 0)
10028 func (stream, "%c", *c);
10029 break;
10030 case '\'':
10031 c++;
10032 if (value == ((1ul << width) - 1))
10033 func (stream, "%c", *c);
10034 break;
10035 case '?':
10036 func (stream, "%c", c[(1 << width) - (int) value]);
10037 c += 1 << width;
10038 break;
10039 default:
10040 abort ();
10041 }
10042 }
10043 break;
10044
10045 case 'e':
10046 {
10047 int imm;
10048
10049 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10050 func (stream, "%d", imm);
10051 value_in_comment = imm;
10052 }
10053 break;
10054
10055 case 'E':
10056 /* LSB and WIDTH fields of BFI or BFC. The machine-
10057 language instruction encodes LSB and MSB. */
10058 {
10059 long msb = (given & 0x001f0000) >> 16;
10060 long lsb = (given & 0x00000f80) >> 7;
10061 long w = msb - lsb + 1;
10062
10063 if (w > 0)
10064 func (stream, "#%lu, #%lu", lsb, w);
10065 else
10066 func (stream, "(invalid: %lu:%lu)", lsb, msb);
10067 }
10068 break;
10069
10070 case 'R':
10071 /* Get the PSR/banked register name. */
10072 {
10073 const char * name;
10074 unsigned sysm = (given & 0x004f0000) >> 16;
10075
10076 sysm |= (given & 0x300) >> 4;
10077 name = banked_regname (sysm);
10078
10079 if (name != NULL)
10080 func (stream, "%s", name);
10081 else
10082 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10083 }
10084 break;
10085
10086 case 'V':
10087 /* 16-bit unsigned immediate from a MOVT or MOVW
10088 instruction, encoded in bits 0:11 and 15:19. */
10089 {
10090 long hi = (given & 0x000f0000) >> 4;
10091 long lo = (given & 0x00000fff);
10092 long imm16 = hi | lo;
10093
10094 func (stream, "#%lu", imm16);
10095 value_in_comment = imm16;
10096 }
10097 break;
10098
10099 default:
10100 abort ();
10101 }
10102 }
10103 else
10104 func (stream, "%c", *c);
10105 }
10106
10107 if (value_in_comment > 32 || value_in_comment < -16)
10108 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
10109
10110 if (is_unpredictable)
10111 func (stream, UNPREDICTABLE_INSTRUCTION);
10112
10113 return;
10114 }
10115 }
10116 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10117 return;
10118 }
10119
10120 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
10121
10122 static void
10123 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
10124 {
10125 const struct opcode16 *insn;
10126 void *stream = info->stream;
10127 fprintf_ftype func = info->fprintf_func;
10128
10129 for (insn = thumb_opcodes; insn->assembler; insn++)
10130 if ((given & insn->mask) == insn->value)
10131 {
10132 signed long value_in_comment = 0;
10133 const char *c = insn->assembler;
10134
10135 for (; *c; c++)
10136 {
10137 int domaskpc = 0;
10138 int domasklr = 0;
10139
10140 if (*c != '%')
10141 {
10142 func (stream, "%c", *c);
10143 continue;
10144 }
10145
10146 switch (*++c)
10147 {
10148 case '%':
10149 func (stream, "%%");
10150 break;
10151
10152 case 'c':
10153 if (ifthen_state)
10154 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10155 break;
10156
10157 case 'C':
10158 if (ifthen_state)
10159 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10160 else
10161 func (stream, "s");
10162 break;
10163
10164 case 'I':
10165 {
10166 unsigned int tmp;
10167
10168 ifthen_next_state = given & 0xff;
10169 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10170 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10171 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10172 }
10173 break;
10174
10175 case 'x':
10176 if (ifthen_next_state)
10177 func (stream, "\t; unpredictable branch in IT block\n");
10178 break;
10179
10180 case 'X':
10181 if (ifthen_state)
10182 func (stream, "\t; unpredictable <IT:%s>",
10183 arm_conditional[IFTHEN_COND]);
10184 break;
10185
10186 case 'S':
10187 {
10188 long reg;
10189
10190 reg = (given >> 3) & 0x7;
10191 if (given & (1 << 6))
10192 reg += 8;
10193
10194 func (stream, "%s", arm_regnames[reg]);
10195 }
10196 break;
10197
10198 case 'D':
10199 {
10200 long reg;
10201
10202 reg = given & 0x7;
10203 if (given & (1 << 7))
10204 reg += 8;
10205
10206 func (stream, "%s", arm_regnames[reg]);
10207 }
10208 break;
10209
10210 case 'N':
10211 if (given & (1 << 8))
10212 domasklr = 1;
10213 /* Fall through. */
10214 case 'O':
10215 if (*c == 'O' && (given & (1 << 8)))
10216 domaskpc = 1;
10217 /* Fall through. */
10218 case 'M':
10219 {
10220 int started = 0;
10221 int reg;
10222
10223 func (stream, "{");
10224
10225 /* It would be nice if we could spot
10226 ranges, and generate the rS-rE format: */
10227 for (reg = 0; (reg < 8); reg++)
10228 if ((given & (1 << reg)) != 0)
10229 {
10230 if (started)
10231 func (stream, ", ");
10232 started = 1;
10233 func (stream, "%s", arm_regnames[reg]);
10234 }
10235
10236 if (domasklr)
10237 {
10238 if (started)
10239 func (stream, ", ");
10240 started = 1;
10241 func (stream, "%s", arm_regnames[14] /* "lr" */);
10242 }
10243
10244 if (domaskpc)
10245 {
10246 if (started)
10247 func (stream, ", ");
10248 func (stream, "%s", arm_regnames[15] /* "pc" */);
10249 }
10250
10251 func (stream, "}");
10252 }
10253 break;
10254
10255 case 'W':
10256 /* Print writeback indicator for a LDMIA. We are doing a
10257 writeback if the base register is not in the register
10258 mask. */
10259 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10260 func (stream, "!");
10261 break;
10262
10263 case 'b':
10264 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10265 {
10266 bfd_vma address = (pc + 4
10267 + ((given & 0x00f8) >> 2)
10268 + ((given & 0x0200) >> 3));
10269 info->print_address_func (address, info);
10270 }
10271 break;
10272
10273 case 's':
10274 /* Right shift immediate -- bits 6..10; 1-31 print
10275 as themselves, 0 prints as 32. */
10276 {
10277 long imm = (given & 0x07c0) >> 6;
10278 if (imm == 0)
10279 imm = 32;
10280 func (stream, "#%ld", imm);
10281 }
10282 break;
10283
10284 case '0': case '1': case '2': case '3': case '4':
10285 case '5': case '6': case '7': case '8': case '9':
10286 {
10287 int bitstart = *c++ - '0';
10288 int bitend = 0;
10289
10290 while (*c >= '0' && *c <= '9')
10291 bitstart = (bitstart * 10) + *c++ - '0';
10292
10293 switch (*c)
10294 {
10295 case '-':
10296 {
10297 bfd_vma reg;
10298
10299 c++;
10300 while (*c >= '0' && *c <= '9')
10301 bitend = (bitend * 10) + *c++ - '0';
10302 if (!bitend)
10303 abort ();
10304 reg = given >> bitstart;
10305 reg &= (2 << (bitend - bitstart)) - 1;
10306
10307 switch (*c)
10308 {
10309 case 'r':
10310 func (stream, "%s", arm_regnames[reg]);
10311 break;
10312
10313 case 'd':
10314 func (stream, "%ld", (long) reg);
10315 value_in_comment = reg;
10316 break;
10317
10318 case 'H':
10319 func (stream, "%ld", (long) (reg << 1));
10320 value_in_comment = reg << 1;
10321 break;
10322
10323 case 'W':
10324 func (stream, "%ld", (long) (reg << 2));
10325 value_in_comment = reg << 2;
10326 break;
10327
10328 case 'a':
10329 /* PC-relative address -- the bottom two
10330 bits of the address are dropped
10331 before the calculation. */
10332 info->print_address_func
10333 (((pc + 4) & ~3) + (reg << 2), info);
10334 value_in_comment = 0;
10335 break;
10336
10337 case 'x':
10338 func (stream, "0x%04lx", (long) reg);
10339 break;
10340
10341 case 'B':
10342 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
10343 info->print_address_func (reg * 2 + pc + 4, info);
10344 value_in_comment = 0;
10345 break;
10346
10347 case 'c':
10348 func (stream, "%s", arm_conditional [reg]);
10349 break;
10350
10351 default:
10352 abort ();
10353 }
10354 }
10355 break;
10356
10357 case '\'':
10358 c++;
10359 if ((given & (1 << bitstart)) != 0)
10360 func (stream, "%c", *c);
10361 break;
10362
10363 case '?':
10364 ++c;
10365 if ((given & (1 << bitstart)) != 0)
10366 func (stream, "%c", *c++);
10367 else
10368 func (stream, "%c", *++c);
10369 break;
10370
10371 default:
10372 abort ();
10373 }
10374 }
10375 break;
10376
10377 default:
10378 abort ();
10379 }
10380 }
10381
10382 if (value_in_comment > 32 || value_in_comment < -16)
10383 func (stream, "\t; 0x%lx", value_in_comment);
10384 return;
10385 }
10386
10387 /* No match. */
10388 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10389 return;
10390 }
10391
10392 /* Return the name of an V7M special register. */
10393
10394 static const char *
10395 psr_name (int regno)
10396 {
10397 switch (regno)
10398 {
10399 case 0x0: return "APSR";
10400 case 0x1: return "IAPSR";
10401 case 0x2: return "EAPSR";
10402 case 0x3: return "PSR";
10403 case 0x5: return "IPSR";
10404 case 0x6: return "EPSR";
10405 case 0x7: return "IEPSR";
10406 case 0x8: return "MSP";
10407 case 0x9: return "PSP";
10408 case 0xa: return "MSPLIM";
10409 case 0xb: return "PSPLIM";
10410 case 0x10: return "PRIMASK";
10411 case 0x11: return "BASEPRI";
10412 case 0x12: return "BASEPRI_MAX";
10413 case 0x13: return "FAULTMASK";
10414 case 0x14: return "CONTROL";
10415 case 0x88: return "MSP_NS";
10416 case 0x89: return "PSP_NS";
10417 case 0x8a: return "MSPLIM_NS";
10418 case 0x8b: return "PSPLIM_NS";
10419 case 0x90: return "PRIMASK_NS";
10420 case 0x91: return "BASEPRI_NS";
10421 case 0x93: return "FAULTMASK_NS";
10422 case 0x94: return "CONTROL_NS";
10423 case 0x98: return "SP_NS";
10424 default: return "<unknown>";
10425 }
10426 }
10427
10428 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10429
10430 static void
10431 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
10432 {
10433 const struct opcode32 *insn;
10434 void *stream = info->stream;
10435 fprintf_ftype func = info->fprintf_func;
10436 bfd_boolean is_mve = is_mve_architecture (info);
10437
10438 if (print_insn_coprocessor (pc, info, given, TRUE))
10439 return;
10440
10441 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
10442 return;
10443
10444 if (is_mve && print_insn_mve (info, given))
10445 return;
10446
10447 for (insn = thumb32_opcodes; insn->assembler; insn++)
10448 if ((given & insn->mask) == insn->value)
10449 {
10450 bfd_boolean is_clrm = FALSE;
10451 bfd_boolean is_unpredictable = FALSE;
10452 signed long value_in_comment = 0;
10453 const char *c = insn->assembler;
10454
10455 for (; *c; c++)
10456 {
10457 if (*c != '%')
10458 {
10459 func (stream, "%c", *c);
10460 continue;
10461 }
10462
10463 switch (*++c)
10464 {
10465 case '%':
10466 func (stream, "%%");
10467 break;
10468
10469 case 'c':
10470 if (ifthen_state)
10471 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10472 break;
10473
10474 case 'x':
10475 if (ifthen_next_state)
10476 func (stream, "\t; unpredictable branch in IT block\n");
10477 break;
10478
10479 case 'X':
10480 if (ifthen_state)
10481 func (stream, "\t; unpredictable <IT:%s>",
10482 arm_conditional[IFTHEN_COND]);
10483 break;
10484
10485 case 'I':
10486 {
10487 unsigned int imm12 = 0;
10488
10489 imm12 |= (given & 0x000000ffu);
10490 imm12 |= (given & 0x00007000u) >> 4;
10491 imm12 |= (given & 0x04000000u) >> 15;
10492 func (stream, "#%u", imm12);
10493 value_in_comment = imm12;
10494 }
10495 break;
10496
10497 case 'M':
10498 {
10499 unsigned int bits = 0, imm, imm8, mod;
10500
10501 bits |= (given & 0x000000ffu);
10502 bits |= (given & 0x00007000u) >> 4;
10503 bits |= (given & 0x04000000u) >> 15;
10504 imm8 = (bits & 0x0ff);
10505 mod = (bits & 0xf00) >> 8;
10506 switch (mod)
10507 {
10508 case 0: imm = imm8; break;
10509 case 1: imm = ((imm8 << 16) | imm8); break;
10510 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10511 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
10512 default:
10513 mod = (bits & 0xf80) >> 7;
10514 imm8 = (bits & 0x07f) | 0x80;
10515 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10516 }
10517 func (stream, "#%u", imm);
10518 value_in_comment = imm;
10519 }
10520 break;
10521
10522 case 'J':
10523 {
10524 unsigned int imm = 0;
10525
10526 imm |= (given & 0x000000ffu);
10527 imm |= (given & 0x00007000u) >> 4;
10528 imm |= (given & 0x04000000u) >> 15;
10529 imm |= (given & 0x000f0000u) >> 4;
10530 func (stream, "#%u", imm);
10531 value_in_comment = imm;
10532 }
10533 break;
10534
10535 case 'K':
10536 {
10537 unsigned int imm = 0;
10538
10539 imm |= (given & 0x000f0000u) >> 16;
10540 imm |= (given & 0x00000ff0u) >> 0;
10541 imm |= (given & 0x0000000fu) << 12;
10542 func (stream, "#%u", imm);
10543 value_in_comment = imm;
10544 }
10545 break;
10546
10547 case 'H':
10548 {
10549 unsigned int imm = 0;
10550
10551 imm |= (given & 0x000f0000u) >> 4;
10552 imm |= (given & 0x00000fffu) >> 0;
10553 func (stream, "#%u", imm);
10554 value_in_comment = imm;
10555 }
10556 break;
10557
10558 case 'V':
10559 {
10560 unsigned int imm = 0;
10561
10562 imm |= (given & 0x00000fffu);
10563 imm |= (given & 0x000f0000u) >> 4;
10564 func (stream, "#%u", imm);
10565 value_in_comment = imm;
10566 }
10567 break;
10568
10569 case 'S':
10570 {
10571 unsigned int reg = (given & 0x0000000fu);
10572 unsigned int stp = (given & 0x00000030u) >> 4;
10573 unsigned int imm = 0;
10574 imm |= (given & 0x000000c0u) >> 6;
10575 imm |= (given & 0x00007000u) >> 10;
10576
10577 func (stream, "%s", arm_regnames[reg]);
10578 switch (stp)
10579 {
10580 case 0:
10581 if (imm > 0)
10582 func (stream, ", lsl #%u", imm);
10583 break;
10584
10585 case 1:
10586 if (imm == 0)
10587 imm = 32;
10588 func (stream, ", lsr #%u", imm);
10589 break;
10590
10591 case 2:
10592 if (imm == 0)
10593 imm = 32;
10594 func (stream, ", asr #%u", imm);
10595 break;
10596
10597 case 3:
10598 if (imm == 0)
10599 func (stream, ", rrx");
10600 else
10601 func (stream, ", ror #%u", imm);
10602 }
10603 }
10604 break;
10605
10606 case 'a':
10607 {
10608 unsigned int Rn = (given & 0x000f0000) >> 16;
10609 unsigned int U = ! NEGATIVE_BIT_SET;
10610 unsigned int op = (given & 0x00000f00) >> 8;
10611 unsigned int i12 = (given & 0x00000fff);
10612 unsigned int i8 = (given & 0x000000ff);
10613 bfd_boolean writeback = FALSE, postind = FALSE;
10614 bfd_vma offset = 0;
10615
10616 func (stream, "[%s", arm_regnames[Rn]);
10617 if (U) /* 12-bit positive immediate offset. */
10618 {
10619 offset = i12;
10620 if (Rn != 15)
10621 value_in_comment = offset;
10622 }
10623 else if (Rn == 15) /* 12-bit negative immediate offset. */
10624 offset = - (int) i12;
10625 else if (op == 0x0) /* Shifted register offset. */
10626 {
10627 unsigned int Rm = (i8 & 0x0f);
10628 unsigned int sh = (i8 & 0x30) >> 4;
10629
10630 func (stream, ", %s", arm_regnames[Rm]);
10631 if (sh)
10632 func (stream, ", lsl #%u", sh);
10633 func (stream, "]");
10634 break;
10635 }
10636 else switch (op)
10637 {
10638 case 0xE: /* 8-bit positive immediate offset. */
10639 offset = i8;
10640 break;
10641
10642 case 0xC: /* 8-bit negative immediate offset. */
10643 offset = -i8;
10644 break;
10645
10646 case 0xF: /* 8-bit + preindex with wb. */
10647 offset = i8;
10648 writeback = TRUE;
10649 break;
10650
10651 case 0xD: /* 8-bit - preindex with wb. */
10652 offset = -i8;
10653 writeback = TRUE;
10654 break;
10655
10656 case 0xB: /* 8-bit + postindex. */
10657 offset = i8;
10658 postind = TRUE;
10659 break;
10660
10661 case 0x9: /* 8-bit - postindex. */
10662 offset = -i8;
10663 postind = TRUE;
10664 break;
10665
10666 default:
10667 func (stream, ", <undefined>]");
10668 goto skip;
10669 }
10670
10671 if (postind)
10672 func (stream, "], #%d", (int) offset);
10673 else
10674 {
10675 if (offset)
10676 func (stream, ", #%d", (int) offset);
10677 func (stream, writeback ? "]!" : "]");
10678 }
10679
10680 if (Rn == 15)
10681 {
10682 func (stream, "\t; ");
10683 info->print_address_func (((pc + 4) & ~3) + offset, info);
10684 }
10685 }
10686 skip:
10687 break;
10688
10689 case 'A':
10690 {
10691 unsigned int U = ! NEGATIVE_BIT_SET;
10692 unsigned int W = WRITEBACK_BIT_SET;
10693 unsigned int Rn = (given & 0x000f0000) >> 16;
10694 unsigned int off = (given & 0x000000ff);
10695
10696 func (stream, "[%s", arm_regnames[Rn]);
10697
10698 if (PRE_BIT_SET)
10699 {
10700 if (off || !U)
10701 {
10702 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
10703 value_in_comment = off * 4 * (U ? 1 : -1);
10704 }
10705 func (stream, "]");
10706 if (W)
10707 func (stream, "!");
10708 }
10709 else
10710 {
10711 func (stream, "], ");
10712 if (W)
10713 {
10714 func (stream, "#%c%u", U ? '+' : '-', off * 4);
10715 value_in_comment = off * 4 * (U ? 1 : -1);
10716 }
10717 else
10718 {
10719 func (stream, "{%u}", off);
10720 value_in_comment = off;
10721 }
10722 }
10723 }
10724 break;
10725
10726 case 'w':
10727 {
10728 unsigned int Sbit = (given & 0x01000000) >> 24;
10729 unsigned int type = (given & 0x00600000) >> 21;
10730
10731 switch (type)
10732 {
10733 case 0: func (stream, Sbit ? "sb" : "b"); break;
10734 case 1: func (stream, Sbit ? "sh" : "h"); break;
10735 case 2:
10736 if (Sbit)
10737 func (stream, "??");
10738 break;
10739 case 3:
10740 func (stream, "??");
10741 break;
10742 }
10743 }
10744 break;
10745
10746 case 'n':
10747 is_clrm = TRUE;
10748 /* Fall through. */
10749 case 'm':
10750 {
10751 int started = 0;
10752 int reg;
10753
10754 func (stream, "{");
10755 for (reg = 0; reg < 16; reg++)
10756 if ((given & (1 << reg)) != 0)
10757 {
10758 if (started)
10759 func (stream, ", ");
10760 started = 1;
10761 if (is_clrm && reg == 13)
10762 func (stream, "(invalid: %s)", arm_regnames[reg]);
10763 else if (is_clrm && reg == 15)
10764 func (stream, "%s", "APSR");
10765 else
10766 func (stream, "%s", arm_regnames[reg]);
10767 }
10768 func (stream, "}");
10769 }
10770 break;
10771
10772 case 'E':
10773 {
10774 unsigned int msb = (given & 0x0000001f);
10775 unsigned int lsb = 0;
10776
10777 lsb |= (given & 0x000000c0u) >> 6;
10778 lsb |= (given & 0x00007000u) >> 10;
10779 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
10780 }
10781 break;
10782
10783 case 'F':
10784 {
10785 unsigned int width = (given & 0x0000001f) + 1;
10786 unsigned int lsb = 0;
10787
10788 lsb |= (given & 0x000000c0u) >> 6;
10789 lsb |= (given & 0x00007000u) >> 10;
10790 func (stream, "#%u, #%u", lsb, width);
10791 }
10792 break;
10793
10794 case 'G':
10795 {
10796 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
10797 func (stream, "%x", boff);
10798 }
10799 break;
10800
10801 case 'W':
10802 {
10803 unsigned int immA = (given & 0x001f0000u) >> 16;
10804 unsigned int immB = (given & 0x000007feu) >> 1;
10805 unsigned int immC = (given & 0x00000800u) >> 11;
10806 bfd_vma offset = 0;
10807
10808 offset |= immA << 12;
10809 offset |= immB << 2;
10810 offset |= immC << 1;
10811 /* Sign extend. */
10812 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
10813
10814 info->print_address_func (pc + 4 + offset, info);
10815 }
10816 break;
10817
10818 case 'Y':
10819 {
10820 unsigned int immA = (given & 0x007f0000u) >> 16;
10821 unsigned int immB = (given & 0x000007feu) >> 1;
10822 unsigned int immC = (given & 0x00000800u) >> 11;
10823 bfd_vma offset = 0;
10824
10825 offset |= immA << 12;
10826 offset |= immB << 2;
10827 offset |= immC << 1;
10828 /* Sign extend. */
10829 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
10830
10831 info->print_address_func (pc + 4 + offset, info);
10832 }
10833 break;
10834
10835 case 'Z':
10836 {
10837 unsigned int immA = (given & 0x00010000u) >> 16;
10838 unsigned int immB = (given & 0x000007feu) >> 1;
10839 unsigned int immC = (given & 0x00000800u) >> 11;
10840 bfd_vma offset = 0;
10841
10842 offset |= immA << 12;
10843 offset |= immB << 2;
10844 offset |= immC << 1;
10845 /* Sign extend. */
10846 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
10847
10848 info->print_address_func (pc + 4 + offset, info);
10849
10850 unsigned int T = (given & 0x00020000u) >> 17;
10851 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10852 unsigned int boffset = (T == 1) ? 4 : 2;
10853 func (stream, ", ");
10854 func (stream, "%x", endoffset + boffset);
10855 }
10856 break;
10857
10858 case 'Q':
10859 {
10860 unsigned int immh = (given & 0x000007feu) >> 1;
10861 unsigned int imml = (given & 0x00000800u) >> 11;
10862 bfd_vma imm32 = 0;
10863
10864 imm32 |= immh << 2;
10865 imm32 |= imml << 1;
10866
10867 info->print_address_func (pc + 4 + imm32, info);
10868 }
10869 break;
10870
10871 case 'P':
10872 {
10873 unsigned int immh = (given & 0x000007feu) >> 1;
10874 unsigned int imml = (given & 0x00000800u) >> 11;
10875 bfd_vma imm32 = 0;
10876
10877 imm32 |= immh << 2;
10878 imm32 |= imml << 1;
10879
10880 info->print_address_func (pc + 4 - imm32, info);
10881 }
10882 break;
10883
10884 case 'b':
10885 {
10886 unsigned int S = (given & 0x04000000u) >> 26;
10887 unsigned int J1 = (given & 0x00002000u) >> 13;
10888 unsigned int J2 = (given & 0x00000800u) >> 11;
10889 bfd_vma offset = 0;
10890
10891 offset |= !S << 20;
10892 offset |= J2 << 19;
10893 offset |= J1 << 18;
10894 offset |= (given & 0x003f0000) >> 4;
10895 offset |= (given & 0x000007ff) << 1;
10896 offset -= (1 << 20);
10897
10898 info->print_address_func (pc + 4 + offset, info);
10899 }
10900 break;
10901
10902 case 'B':
10903 {
10904 unsigned int S = (given & 0x04000000u) >> 26;
10905 unsigned int I1 = (given & 0x00002000u) >> 13;
10906 unsigned int I2 = (given & 0x00000800u) >> 11;
10907 bfd_vma offset = 0;
10908
10909 offset |= !S << 24;
10910 offset |= !(I1 ^ S) << 23;
10911 offset |= !(I2 ^ S) << 22;
10912 offset |= (given & 0x03ff0000u) >> 4;
10913 offset |= (given & 0x000007ffu) << 1;
10914 offset -= (1 << 24);
10915 offset += pc + 4;
10916
10917 /* BLX target addresses are always word aligned. */
10918 if ((given & 0x00001000u) == 0)
10919 offset &= ~2u;
10920
10921 info->print_address_func (offset, info);
10922 }
10923 break;
10924
10925 case 's':
10926 {
10927 unsigned int shift = 0;
10928
10929 shift |= (given & 0x000000c0u) >> 6;
10930 shift |= (given & 0x00007000u) >> 10;
10931 if (WRITEBACK_BIT_SET)
10932 func (stream, ", asr #%u", shift);
10933 else if (shift)
10934 func (stream, ", lsl #%u", shift);
10935 /* else print nothing - lsl #0 */
10936 }
10937 break;
10938
10939 case 'R':
10940 {
10941 unsigned int rot = (given & 0x00000030) >> 4;
10942
10943 if (rot)
10944 func (stream, ", ror #%u", rot * 8);
10945 }
10946 break;
10947
10948 case 'U':
10949 if ((given & 0xf0) == 0x60)
10950 {
10951 switch (given & 0xf)
10952 {
10953 case 0xf: func (stream, "sy"); break;
10954 default:
10955 func (stream, "#%d", (int) given & 0xf);
10956 break;
10957 }
10958 }
10959 else
10960 {
10961 const char * opt = data_barrier_option (given & 0xf);
10962 if (opt != NULL)
10963 func (stream, "%s", opt);
10964 else
10965 func (stream, "#%d", (int) given & 0xf);
10966 }
10967 break;
10968
10969 case 'C':
10970 if ((given & 0xff) == 0)
10971 {
10972 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
10973 if (given & 0x800)
10974 func (stream, "f");
10975 if (given & 0x400)
10976 func (stream, "s");
10977 if (given & 0x200)
10978 func (stream, "x");
10979 if (given & 0x100)
10980 func (stream, "c");
10981 }
10982 else if ((given & 0x20) == 0x20)
10983 {
10984 char const* name;
10985 unsigned sysm = (given & 0xf00) >> 8;
10986
10987 sysm |= (given & 0x30);
10988 sysm |= (given & 0x00100000) >> 14;
10989 name = banked_regname (sysm);
10990
10991 if (name != NULL)
10992 func (stream, "%s", name);
10993 else
10994 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10995 }
10996 else
10997 {
10998 func (stream, "%s", psr_name (given & 0xff));
10999 }
11000 break;
11001
11002 case 'D':
11003 if (((given & 0xff) == 0)
11004 || ((given & 0x20) == 0x20))
11005 {
11006 char const* name;
11007 unsigned sm = (given & 0xf0000) >> 16;
11008
11009 sm |= (given & 0x30);
11010 sm |= (given & 0x00100000) >> 14;
11011 name = banked_regname (sm);
11012
11013 if (name != NULL)
11014 func (stream, "%s", name);
11015 else
11016 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
11017 }
11018 else
11019 func (stream, "%s", psr_name (given & 0xff));
11020 break;
11021
11022 case '0': case '1': case '2': case '3': case '4':
11023 case '5': case '6': case '7': case '8': case '9':
11024 {
11025 int width;
11026 unsigned long val;
11027
11028 c = arm_decode_bitfield (c, given, &val, &width);
11029
11030 switch (*c)
11031 {
11032 case 's':
11033 if (val <= 3)
11034 func (stream, "%s", mve_vec_sizename[val]);
11035 else
11036 func (stream, "<undef size>");
11037 break;
11038
11039 case 'd':
11040 func (stream, "%lu", val);
11041 value_in_comment = val;
11042 break;
11043
11044 case 'D':
11045 func (stream, "%lu", val + 1);
11046 value_in_comment = val + 1;
11047 break;
11048
11049 case 'W':
11050 func (stream, "%lu", val * 4);
11051 value_in_comment = val * 4;
11052 break;
11053
11054 case 'S':
11055 if (val == 13)
11056 is_unpredictable = TRUE;
11057 /* Fall through. */
11058 case 'R':
11059 if (val == 15)
11060 is_unpredictable = TRUE;
11061 /* Fall through. */
11062 case 'r':
11063 func (stream, "%s", arm_regnames[val]);
11064 break;
11065
11066 case 'c':
11067 func (stream, "%s", arm_conditional[val]);
11068 break;
11069
11070 case '\'':
11071 c++;
11072 if (val == ((1ul << width) - 1))
11073 func (stream, "%c", *c);
11074 break;
11075
11076 case '`':
11077 c++;
11078 if (val == 0)
11079 func (stream, "%c", *c);
11080 break;
11081
11082 case '?':
11083 func (stream, "%c", c[(1 << width) - (int) val]);
11084 c += 1 << width;
11085 break;
11086
11087 case 'x':
11088 func (stream, "0x%lx", val & 0xffffffffUL);
11089 break;
11090
11091 default:
11092 abort ();
11093 }
11094 }
11095 break;
11096
11097 case 'L':
11098 /* PR binutils/12534
11099 If we have a PC relative offset in an LDRD or STRD
11100 instructions then display the decoded address. */
11101 if (((given >> 16) & 0xf) == 0xf)
11102 {
11103 bfd_vma offset = (given & 0xff) * 4;
11104
11105 if ((given & (1 << 23)) == 0)
11106 offset = - offset;
11107 func (stream, "\t; ");
11108 info->print_address_func ((pc & ~3) + 4 + offset, info);
11109 }
11110 break;
11111
11112 default:
11113 abort ();
11114 }
11115 }
11116
11117 if (value_in_comment > 32 || value_in_comment < -16)
11118 func (stream, "\t; 0x%lx", value_in_comment);
11119
11120 if (is_unpredictable)
11121 func (stream, UNPREDICTABLE_INSTRUCTION);
11122
11123 return;
11124 }
11125
11126 /* No match. */
11127 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11128 return;
11129 }
11130
11131 /* Print data bytes on INFO->STREAM. */
11132
11133 static void
11134 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11135 struct disassemble_info *info,
11136 long given)
11137 {
11138 switch (info->bytes_per_chunk)
11139 {
11140 case 1:
11141 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11142 break;
11143 case 2:
11144 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11145 break;
11146 case 4:
11147 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11148 break;
11149 default:
11150 abort ();
11151 }
11152 }
11153
11154 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
11155 being displayed in symbol relative addresses.
11156
11157 Also disallow private symbol, with __tagsym$$ prefix,
11158 from ARM RVCT toolchain being displayed. */
11159
11160 bfd_boolean
11161 arm_symbol_is_valid (asymbol * sym,
11162 struct disassemble_info * info ATTRIBUTE_UNUSED)
11163 {
11164 const char * name;
11165
11166 if (sym == NULL)
11167 return FALSE;
11168
11169 name = bfd_asymbol_name (sym);
11170
11171 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
11172 }
11173
11174 /* Parse the string of disassembler options. */
11175
11176 static void
11177 parse_arm_disassembler_options (const char *options)
11178 {
11179 const char *opt;
11180
11181 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
11182 {
11183 if (CONST_STRNEQ (opt, "reg-names-"))
11184 {
11185 unsigned int i;
11186 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11187 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11188 {
11189 regname_selected = i;
11190 break;
11191 }
11192
11193 if (i >= NUM_ARM_OPTIONS)
11194 /* xgettext: c-format */
11195 opcodes_error_handler (_("unrecognised register name set: %s"),
11196 opt);
11197 }
11198 else if (CONST_STRNEQ (opt, "force-thumb"))
11199 force_thumb = 1;
11200 else if (CONST_STRNEQ (opt, "no-force-thumb"))
11201 force_thumb = 0;
11202 else
11203 /* xgettext: c-format */
11204 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
11205 }
11206
11207 return;
11208 }
11209
11210 static bfd_boolean
11211 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11212 enum map_type *map_symbol);
11213
11214 /* Search back through the insn stream to determine if this instruction is
11215 conditionally executed. */
11216
11217 static void
11218 find_ifthen_state (bfd_vma pc,
11219 struct disassemble_info *info,
11220 bfd_boolean little)
11221 {
11222 unsigned char b[2];
11223 unsigned int insn;
11224 int status;
11225 /* COUNT is twice the number of instructions seen. It will be odd if we
11226 just crossed an instruction boundary. */
11227 int count;
11228 int it_count;
11229 unsigned int seen_it;
11230 bfd_vma addr;
11231
11232 ifthen_address = pc;
11233 ifthen_state = 0;
11234
11235 addr = pc;
11236 count = 1;
11237 it_count = 0;
11238 seen_it = 0;
11239 /* Scan backwards looking for IT instructions, keeping track of where
11240 instruction boundaries are. We don't know if something is actually an
11241 IT instruction until we find a definite instruction boundary. */
11242 for (;;)
11243 {
11244 if (addr == 0 || info->symbol_at_address_func (addr, info))
11245 {
11246 /* A symbol must be on an instruction boundary, and will not
11247 be within an IT block. */
11248 if (seen_it && (count & 1))
11249 break;
11250
11251 return;
11252 }
11253 addr -= 2;
11254 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
11255 if (status)
11256 return;
11257
11258 if (little)
11259 insn = (b[0]) | (b[1] << 8);
11260 else
11261 insn = (b[1]) | (b[0] << 8);
11262 if (seen_it)
11263 {
11264 if ((insn & 0xf800) < 0xe800)
11265 {
11266 /* Addr + 2 is an instruction boundary. See if this matches
11267 the expected boundary based on the position of the last
11268 IT candidate. */
11269 if (count & 1)
11270 break;
11271 seen_it = 0;
11272 }
11273 }
11274 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11275 {
11276 enum map_type type = MAP_ARM;
11277 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
11278
11279 if (!found || (found && type == MAP_THUMB))
11280 {
11281 /* This could be an IT instruction. */
11282 seen_it = insn;
11283 it_count = count >> 1;
11284 }
11285 }
11286 if ((insn & 0xf800) >= 0xe800)
11287 count++;
11288 else
11289 count = (count + 2) | 1;
11290 /* IT blocks contain at most 4 instructions. */
11291 if (count >= 8 && !seen_it)
11292 return;
11293 }
11294 /* We found an IT instruction. */
11295 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11296 if ((ifthen_state & 0xf) == 0)
11297 ifthen_state = 0;
11298 }
11299
11300 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11301 mapping symbol. */
11302
11303 static int
11304 is_mapping_symbol (struct disassemble_info *info, int n,
11305 enum map_type *map_type)
11306 {
11307 const char *name;
11308
11309 name = bfd_asymbol_name (info->symtab[n]);
11310 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11311 && (name[2] == 0 || name[2] == '.'))
11312 {
11313 *map_type = ((name[1] == 'a') ? MAP_ARM
11314 : (name[1] == 't') ? MAP_THUMB
11315 : MAP_DATA);
11316 return TRUE;
11317 }
11318
11319 return FALSE;
11320 }
11321
11322 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11323 Returns nonzero if *MAP_TYPE was set. */
11324
11325 static int
11326 get_map_sym_type (struct disassemble_info *info,
11327 int n,
11328 enum map_type *map_type)
11329 {
11330 /* If the symbol is in a different section, ignore it. */
11331 if (info->section != NULL && info->section != info->symtab[n]->section)
11332 return FALSE;
11333
11334 return is_mapping_symbol (info, n, map_type);
11335 }
11336
11337 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
11338 Returns nonzero if *MAP_TYPE was set. */
11339
11340 static int
11341 get_sym_code_type (struct disassemble_info *info,
11342 int n,
11343 enum map_type *map_type)
11344 {
11345 elf_symbol_type *es;
11346 unsigned int type;
11347
11348 /* If the symbol is in a different section, ignore it. */
11349 if (info->section != NULL && info->section != info->symtab[n]->section)
11350 return FALSE;
11351
11352 es = *(elf_symbol_type **)(info->symtab + n);
11353 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11354
11355 /* If the symbol has function type then use that. */
11356 if (type == STT_FUNC || type == STT_GNU_IFUNC)
11357 {
11358 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11359 == ST_BRANCH_TO_THUMB)
11360 *map_type = MAP_THUMB;
11361 else
11362 *map_type = MAP_ARM;
11363 return TRUE;
11364 }
11365
11366 return FALSE;
11367 }
11368
11369 /* Search the mapping symbol state for instruction at pc. This is only
11370 applicable for elf target.
11371
11372 There is an assumption Here, info->private_data contains the correct AND
11373 up-to-date information about current scan process. The information will be
11374 used to speed this search process.
11375
11376 Return TRUE if the mapping state can be determined, and map_symbol
11377 will be updated accordingly. Otherwise, return FALSE. */
11378
11379 static bfd_boolean
11380 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11381 enum map_type *map_symbol)
11382 {
11383 bfd_vma addr, section_vma = 0;
11384 int n, last_sym = -1;
11385 bfd_boolean found = FALSE;
11386 bfd_boolean can_use_search_opt_p = FALSE;
11387
11388 /* Default to DATA. A text section is required by the ABI to contain an
11389 INSN mapping symbol at the start. A data section has no such
11390 requirement, hence if no mapping symbol is found the section must
11391 contain only data. This however isn't very useful if the user has
11392 fully stripped the binaries. If this is the case use the section
11393 attributes to determine the default. If we have no section default to
11394 INSN as well, as we may be disassembling some raw bytes on a baremetal
11395 HEX file or similar. */
11396 enum map_type type = MAP_DATA;
11397 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11398 type = MAP_ARM;
11399 struct arm_private_data *private_data;
11400
11401 if (info->private_data == NULL
11402 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11403 return FALSE;
11404
11405 private_data = info->private_data;
11406
11407 /* First, look for mapping symbols. */
11408 if (info->symtab_size != 0)
11409 {
11410 if (pc <= private_data->last_mapping_addr)
11411 private_data->last_mapping_sym = -1;
11412
11413 /* Start scanning at the start of the function, or wherever
11414 we finished last time. */
11415 n = info->symtab_pos + 1;
11416
11417 /* If the last stop offset is different from the current one it means we
11418 are disassembling a different glob of bytes. As such the optimization
11419 would not be safe and we should start over. */
11420 can_use_search_opt_p
11421 = private_data->last_mapping_sym >= 0
11422 && info->stop_offset == private_data->last_stop_offset;
11423
11424 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11425 n = private_data->last_mapping_sym;
11426
11427 /* Look down while we haven't passed the location being disassembled.
11428 The reason for this is that there's no defined order between a symbol
11429 and an mapping symbol that may be at the same address. We may have to
11430 look at least one position ahead. */
11431 for (; n < info->symtab_size; n++)
11432 {
11433 addr = bfd_asymbol_value (info->symtab[n]);
11434 if (addr > pc)
11435 break;
11436 if (get_map_sym_type (info, n, &type))
11437 {
11438 last_sym = n;
11439 found = TRUE;
11440 }
11441 }
11442
11443 if (!found)
11444 {
11445 n = info->symtab_pos;
11446 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11447 n = private_data->last_mapping_sym;
11448
11449 /* No mapping symbol found at this address. Look backwards
11450 for a preceeding one, but don't go pass the section start
11451 otherwise a data section with no mapping symbol can pick up
11452 a text mapping symbol of a preceeding section. The documentation
11453 says section can be NULL, in which case we will seek up all the
11454 way to the top. */
11455 if (info->section)
11456 section_vma = info->section->vma;
11457
11458 for (; n >= 0; n--)
11459 {
11460 addr = bfd_asymbol_value (info->symtab[n]);
11461 if (addr < section_vma)
11462 break;
11463
11464 if (get_map_sym_type (info, n, &type))
11465 {
11466 last_sym = n;
11467 found = TRUE;
11468 break;
11469 }
11470 }
11471 }
11472 }
11473
11474 /* If no mapping symbol was found, try looking up without a mapping
11475 symbol. This is done by walking up from the current PC to the nearest
11476 symbol. We don't actually have to loop here since symtab_pos will
11477 contain the nearest symbol already. */
11478 if (!found)
11479 {
11480 n = info->symtab_pos;
11481 if (n >= 0 && get_sym_code_type (info, n, &type))
11482 {
11483 last_sym = n;
11484 found = TRUE;
11485 }
11486 }
11487
11488 private_data->last_mapping_sym = last_sym;
11489 private_data->last_type = type;
11490 private_data->last_stop_offset = info->stop_offset;
11491
11492 *map_symbol = type;
11493 return found;
11494 }
11495
11496 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11497 of the supplied arm_feature_set structure with bitmasks indicating
11498 the supported base architectures and coprocessor extensions.
11499
11500 FIXME: This could more efficiently implemented as a constant array,
11501 although it would also be less robust. */
11502
11503 static void
11504 select_arm_features (unsigned long mach,
11505 arm_feature_set * features)
11506 {
11507 arm_feature_set arch_fset;
11508 const arm_feature_set fpu_any = FPU_ANY;
11509
11510 #undef ARM_SET_FEATURES
11511 #define ARM_SET_FEATURES(FSET) \
11512 { \
11513 const arm_feature_set fset = FSET; \
11514 arch_fset = fset; \
11515 }
11516
11517 /* When several architecture versions share the same bfd_mach_arm_XXX value
11518 the most featureful is chosen. */
11519 switch (mach)
11520 {
11521 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11522 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11523 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11524 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11525 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11526 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11527 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11528 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11529 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11530 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
11531 case bfd_mach_arm_ep9312:
11532 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11533 ARM_CEXT_MAVERICK | FPU_MAVERICK));
11534 break;
11535 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11536 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11537 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11538 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11539 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11540 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11541 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11542 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11543 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11544 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11545 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11546 case bfd_mach_arm_8:
11547 {
11548 /* Add bits for extensions that Armv8.5-A recognizes. */
11549 arm_feature_set armv8_5_ext_fset
11550 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
11551 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
11552 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
11553 break;
11554 }
11555 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
11556 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
11557 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
11558 case bfd_mach_arm_8_1M_MAIN:
11559 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
11560 force_thumb = 1;
11561 break;
11562 /* If the machine type is unknown allow all architecture types and all
11563 extensions. */
11564 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
11565 default:
11566 abort ();
11567 }
11568 #undef ARM_SET_FEATURES
11569
11570 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11571 and thus on bfd_mach_arm_XXX value. Therefore for a given
11572 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11573 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
11574 }
11575
11576
11577 /* NOTE: There are no checks in these routines that
11578 the relevant number of data bytes exist. */
11579
11580 static int
11581 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
11582 {
11583 unsigned char b[4];
11584 long given;
11585 int status;
11586 int is_thumb = FALSE;
11587 int is_data = FALSE;
11588 int little_code;
11589 unsigned int size = 4;
11590 void (*printer) (bfd_vma, struct disassemble_info *, long);
11591 bfd_boolean found = FALSE;
11592 struct arm_private_data *private_data;
11593
11594 if (info->disassembler_options)
11595 {
11596 parse_arm_disassembler_options (info->disassembler_options);
11597
11598 /* To avoid repeated parsing of these options, we remove them here. */
11599 info->disassembler_options = NULL;
11600 }
11601
11602 /* PR 10288: Control which instructions will be disassembled. */
11603 if (info->private_data == NULL)
11604 {
11605 static struct arm_private_data private;
11606
11607 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
11608 /* If the user did not use the -m command line switch then default to
11609 disassembling all types of ARM instruction.
11610
11611 The info->mach value has to be ignored as this will be based on
11612 the default archictecture for the target and/or hints in the notes
11613 section, but it will never be greater than the current largest arm
11614 machine value (iWMMXt2), which is only equivalent to the V5TE
11615 architecture. ARM architectures have advanced beyond the machine
11616 value encoding, and these newer architectures would be ignored if
11617 the machine value was used.
11618
11619 Ie the -m switch is used to restrict which instructions will be
11620 disassembled. If it is necessary to use the -m switch to tell
11621 objdump that an ARM binary is being disassembled, eg because the
11622 input is a raw binary file, but it is also desired to disassemble
11623 all ARM instructions then use "-marm". This will select the
11624 "unknown" arm architecture which is compatible with any ARM
11625 instruction. */
11626 info->mach = bfd_mach_arm_unknown;
11627
11628 /* Compute the architecture bitmask from the machine number.
11629 Note: This assumes that the machine number will not change
11630 during disassembly.... */
11631 select_arm_features (info->mach, & private.features);
11632
11633 private.last_mapping_sym = -1;
11634 private.last_mapping_addr = 0;
11635 private.last_stop_offset = 0;
11636
11637 info->private_data = & private;
11638 }
11639
11640 private_data = info->private_data;
11641
11642 /* Decide if our code is going to be little-endian, despite what the
11643 function argument might say. */
11644 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
11645
11646 /* For ELF, consult the symbol table to determine what kind of code
11647 or data we have. */
11648 if (info->symtab_size != 0
11649 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
11650 {
11651 bfd_vma addr;
11652 int n;
11653 int last_sym = -1;
11654 enum map_type type = MAP_ARM;
11655
11656 found = mapping_symbol_for_insn (pc, info, &type);
11657 last_sym = private_data->last_mapping_sym;
11658
11659 is_thumb = (private_data->last_type == MAP_THUMB);
11660 is_data = (private_data->last_type == MAP_DATA);
11661
11662 /* Look a little bit ahead to see if we should print out
11663 two or four bytes of data. If there's a symbol,
11664 mapping or otherwise, after two bytes then don't
11665 print more. */
11666 if (is_data)
11667 {
11668 size = 4 - (pc & 3);
11669 for (n = last_sym + 1; n < info->symtab_size; n++)
11670 {
11671 addr = bfd_asymbol_value (info->symtab[n]);
11672 if (addr > pc
11673 && (info->section == NULL
11674 || info->section == info->symtab[n]->section))
11675 {
11676 if (addr - pc < size)
11677 size = addr - pc;
11678 break;
11679 }
11680 }
11681 /* If the next symbol is after three bytes, we need to
11682 print only part of the data, so that we can use either
11683 .byte or .short. */
11684 if (size == 3)
11685 size = (pc & 1) ? 1 : 2;
11686 }
11687 }
11688
11689 if (info->symbols != NULL)
11690 {
11691 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
11692 {
11693 coff_symbol_type * cs;
11694
11695 cs = coffsymbol (*info->symbols);
11696 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
11697 || cs->native->u.syment.n_sclass == C_THUMBSTAT
11698 || cs->native->u.syment.n_sclass == C_THUMBLABEL
11699 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
11700 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
11701 }
11702 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
11703 && !found)
11704 {
11705 /* If no mapping symbol has been found then fall back to the type
11706 of the function symbol. */
11707 elf_symbol_type * es;
11708 unsigned int type;
11709
11710 es = *(elf_symbol_type **)(info->symbols);
11711 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11712
11713 is_thumb =
11714 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11715 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
11716 }
11717 else if (bfd_asymbol_flavour (*info->symbols)
11718 == bfd_target_mach_o_flavour)
11719 {
11720 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
11721
11722 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
11723 }
11724 }
11725
11726 if (force_thumb)
11727 is_thumb = TRUE;
11728
11729 if (is_data)
11730 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11731 else
11732 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11733
11734 info->bytes_per_line = 4;
11735
11736 /* PR 10263: Disassemble data if requested to do so by the user. */
11737 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
11738 {
11739 int i;
11740
11741 /* Size was already set above. */
11742 info->bytes_per_chunk = size;
11743 printer = print_insn_data;
11744
11745 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
11746 given = 0;
11747 if (little)
11748 for (i = size - 1; i >= 0; i--)
11749 given = b[i] | (given << 8);
11750 else
11751 for (i = 0; i < (int) size; i++)
11752 given = b[i] | (given << 8);
11753 }
11754 else if (!is_thumb)
11755 {
11756 /* In ARM mode endianness is a straightforward issue: the instruction
11757 is four bytes long and is either ordered 0123 or 3210. */
11758 printer = print_insn_arm;
11759 info->bytes_per_chunk = 4;
11760 size = 4;
11761
11762 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
11763 if (little_code)
11764 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
11765 else
11766 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
11767 }
11768 else
11769 {
11770 /* In Thumb mode we have the additional wrinkle of two
11771 instruction lengths. Fortunately, the bits that determine
11772 the length of the current instruction are always to be found
11773 in the first two bytes. */
11774 printer = print_insn_thumb16;
11775 info->bytes_per_chunk = 2;
11776 size = 2;
11777
11778 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
11779 if (little_code)
11780 given = (b[0]) | (b[1] << 8);
11781 else
11782 given = (b[1]) | (b[0] << 8);
11783
11784 if (!status)
11785 {
11786 /* These bit patterns signal a four-byte Thumb
11787 instruction. */
11788 if ((given & 0xF800) == 0xF800
11789 || (given & 0xF800) == 0xF000
11790 || (given & 0xF800) == 0xE800)
11791 {
11792 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
11793 if (little_code)
11794 given = (b[0]) | (b[1] << 8) | (given << 16);
11795 else
11796 given = (b[1]) | (b[0] << 8) | (given << 16);
11797
11798 printer = print_insn_thumb32;
11799 size = 4;
11800 }
11801 }
11802
11803 if (ifthen_address != pc)
11804 find_ifthen_state (pc, info, little_code);
11805
11806 if (ifthen_state)
11807 {
11808 if ((ifthen_state & 0xf) == 0x8)
11809 ifthen_next_state = 0;
11810 else
11811 ifthen_next_state = (ifthen_state & 0xe0)
11812 | ((ifthen_state & 0xf) << 1);
11813 }
11814 }
11815
11816 if (status)
11817 {
11818 info->memory_error_func (status, pc, info);
11819 return -1;
11820 }
11821 if (info->flags & INSN_HAS_RELOC)
11822 /* If the instruction has a reloc associated with it, then
11823 the offset field in the instruction will actually be the
11824 addend for the reloc. (We are using REL type relocs).
11825 In such cases, we can ignore the pc when computing
11826 addresses, since the addend is not currently pc-relative. */
11827 pc = 0;
11828
11829 printer (pc, info, given);
11830
11831 if (is_thumb)
11832 {
11833 ifthen_state = ifthen_next_state;
11834 ifthen_address += size;
11835 }
11836 return size;
11837 }
11838
11839 int
11840 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
11841 {
11842 /* Detect BE8-ness and record it in the disassembler info. */
11843 if (info->flavour == bfd_target_elf_flavour
11844 && info->section != NULL
11845 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
11846 info->endian_code = BFD_ENDIAN_LITTLE;
11847
11848 return print_insn (pc, info, FALSE);
11849 }
11850
11851 int
11852 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
11853 {
11854 return print_insn (pc, info, TRUE);
11855 }
11856
11857 const disasm_options_and_args_t *
11858 disassembler_options_arm (void)
11859 {
11860 static disasm_options_and_args_t *opts_and_args;
11861
11862 if (opts_and_args == NULL)
11863 {
11864 disasm_options_t *opts;
11865 unsigned int i;
11866
11867 opts_and_args = XNEW (disasm_options_and_args_t);
11868 opts_and_args->args = NULL;
11869
11870 opts = &opts_and_args->options;
11871 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11872 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11873 opts->arg = NULL;
11874 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11875 {
11876 opts->name[i] = regnames[i].name;
11877 if (regnames[i].description != NULL)
11878 opts->description[i] = _(regnames[i].description);
11879 else
11880 opts->description[i] = NULL;
11881 }
11882 /* The array we return must be NULL terminated. */
11883 opts->name[i] = NULL;
11884 opts->description[i] = NULL;
11885 }
11886
11887 return opts_and_args;
11888 }
11889
11890 void
11891 print_arm_disassembler_options (FILE *stream)
11892 {
11893 unsigned int i, max_len = 0;
11894 fprintf (stream, _("\n\
11895 The following ARM specific disassembler options are supported for use with\n\
11896 the -M switch:\n"));
11897
11898 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11899 {
11900 unsigned int len = strlen (regnames[i].name);
11901 if (max_len < len)
11902 max_len = len;
11903 }
11904
11905 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
11906 fprintf (stream, " %s%*c %s\n",
11907 regnames[i].name,
11908 (int)(max_len - strlen (regnames[i].name)), ' ',
11909 _(regnames[i].description));
11910 }
GDB Binutils - Deliverables
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