projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[PATCH 50/57][Arm][OBJDUMP] Add support for MVE shift instructions
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24 #include <assert.h>
25
26 #include "disassemble.h"
27 #include "opcode/arm.h"
28 #include "opintl.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
32
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
35 #include "libcoff.h"
36 #include "bfd.h"
37 #include "elf-bfd.h"
38 #include "elf/internal.h"
39 #include "elf/arm.h"
40 #include "mach-o.h"
41
42 /* FIXME: Belongs in global header. */
43 #ifndef strneq
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45 #endif
46
47 /* Cached mapping symbol state. */
48 enum map_type
49 {
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53 };
54
55 struct arm_private_data
56 {
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
68 bfd_vma last_mapping_addr;
69 };
70
71 enum mve_instructions
72 {
73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
211 MVE_NONE
212 };
213
214 enum mve_unpredictable
215 {
216 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
217 */
218 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
219 fcB = 1 (vpt). */
220 UNPRED_R13, /* Unpredictable because r13 (sp) or
221 r15 (sp) used. */
222 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
223 UNPRED_Q_GT_4, /* Unpredictable because
224 vec reg start > 4 (vld4/st4). */
225 UNPRED_Q_GT_6, /* Unpredictable because
226 vec reg start > 6 (vld2/st2). */
227 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
228 and WB bit = 1. */
229 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
230 equal. */
231 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
232 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
233 same. */
234 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
235 size = 1. */
236 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
237 size = 2. */
238 UNPRED_NONE /* No unpredictable behavior. */
239 };
240
241 enum mve_undefined
242 {
243 UNDEF_SIZE, /* undefined size. */
244 UNDEF_SIZE_0, /* undefined because size == 0. */
245 UNDEF_SIZE_2, /* undefined because size == 2. */
246 UNDEF_SIZE_3, /* undefined because size == 3. */
247 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
248 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
249 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
250 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
251 size == 0. */
252 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
253 size == 1. */
254 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
255 UNDEF_VCVT_IMM6, /* imm6 < 32. */
256 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
257 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
258 op1 == (0 or 1). */
259 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
260 op2 == 0 and op1 == (0 or 1). */
261 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
262 in {0xx1, x0x1}. */
263 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
264 UNDEF_NONE /* no undefined behavior. */
265 };
266
267 struct opcode32
268 {
269 arm_feature_set arch; /* Architecture defining this insn. */
270 unsigned long value; /* If arch is 0 then value is a sentinel. */
271 unsigned long mask; /* Recognise insn if (op & mask) == value. */
272 const char * assembler; /* How to disassemble this insn. */
273 };
274
275 /* MVE opcodes. */
276
277 struct mopcode32
278 {
279 arm_feature_set arch; /* Architecture defining this insn. */
280 enum mve_instructions mve_op; /* Specific mve instruction for faster
281 decoding. */
282 unsigned long value; /* If arch is 0 then value is a sentinel. */
283 unsigned long mask; /* Recognise insn if (op & mask) == value. */
284 const char * assembler; /* How to disassemble this insn. */
285 };
286
287 enum isa {
288 ANY,
289 T32,
290 ARM
291 };
292
293
294 /* Shared (between Arm and Thumb mode) opcode. */
295 struct sopcode32
296 {
297 enum isa isa; /* Execution mode instruction availability. */
298 arm_feature_set arch; /* Architecture defining this insn. */
299 unsigned long value; /* If arch is 0 then value is a sentinel. */
300 unsigned long mask; /* Recognise insn if (op & mask) == value. */
301 const char * assembler; /* How to disassemble this insn. */
302 };
303
304 struct opcode16
305 {
306 arm_feature_set arch; /* Architecture defining this insn. */
307 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
308 const char *assembler; /* How to disassemble this insn. */
309 };
310
311 /* print_insn_coprocessor recognizes the following format control codes:
312
313 %% %
314
315 %c print condition code (always bits 28-31 in ARM mode)
316 %q print shifter argument
317 %u print condition code (unconditional in ARM mode,
318 UNPREDICTABLE if not AL in Thumb)
319 %A print address for ldc/stc/ldf/stf instruction
320 %B print vstm/vldm register list
321 %C print vscclrm register list
322 %I print cirrus signed shift immediate: bits 0..3|4..6
323 %J print register for VLDR instruction
324 %K print address for VLDR instruction
325 %F print the COUNT field of a LFM/SFM instruction.
326 %P print floating point precision in arithmetic insn
327 %Q print floating point precision in ldf/stf insn
328 %R print floating point rounding mode
329
330 %<bitfield>c print as a condition code (for vsel)
331 %<bitfield>r print as an ARM register
332 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
333 %<bitfield>ru as %<>r but each u register must be unique.
334 %<bitfield>d print the bitfield in decimal
335 %<bitfield>k print immediate for VFPv3 conversion instruction
336 %<bitfield>x print the bitfield in hex
337 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
338 %<bitfield>f print a floating point constant if >7 else a
339 floating point register
340 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
341 %<bitfield>g print as an iWMMXt 64-bit register
342 %<bitfield>G print as an iWMMXt general purpose or control register
343 %<bitfield>D print as a NEON D register
344 %<bitfield>Q print as a NEON Q register
345 %<bitfield>V print as a NEON D or Q register
346 %<bitfield>E print a quarter-float immediate value
347
348 %y<code> print a single precision VFP reg.
349 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
350 %z<code> print a double precision VFP reg
351 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
352
353 %<bitfield>'c print specified char iff bitfield is all ones
354 %<bitfield>`c print specified char iff bitfield is all zeroes
355 %<bitfield>?ab... select from array of values in big endian order
356
357 %L print as an iWMMXt N/M width field.
358 %Z print the Immediate of a WSHUFH instruction.
359 %l like 'A' except use byte offsets for 'B' & 'H'
360 versions.
361 %i print 5-bit immediate in bits 8,3..0
362 (print "32" when 0)
363 %r print register offset address for wldt/wstr instruction. */
364
365 enum opcode_sentinel_enum
366 {
367 SENTINEL_IWMMXT_START = 1,
368 SENTINEL_IWMMXT_END,
369 SENTINEL_GENERIC_START
370 } opcode_sentinels;
371
372 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
373 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
374 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
375 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
376
377 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
378
379 static const struct sopcode32 coprocessor_opcodes[] =
380 {
381 /* XScale instructions. */
382 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
383 0x0e200010, 0x0fff0ff0,
384 "mia%c\tacc0, %0-3r, %12-15r"},
385 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
386 0x0e280010, 0x0fff0ff0,
387 "miaph%c\tacc0, %0-3r, %12-15r"},
388 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
389 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
390 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
391 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
392 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
393 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
394
395 /* Intel Wireless MMX technology instructions. */
396 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
397 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
398 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
399 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
400 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
401 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
402 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
403 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
404 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
405 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
406 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
407 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
408 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
409 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
410 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
411 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
412 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
413 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
414 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
415 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
416 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
417 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
418 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
419 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
420 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
421 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
422 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
423 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
424 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
425 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
426 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
427 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
428 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
429 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
430 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
431 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
432 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
433 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
434 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
435 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
436 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
437 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
438 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
439 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
440 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
441 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
442 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
443 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
444 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
445 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
446 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
447 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
448 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
449 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
450 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
451 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
452 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
453 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
454 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
455 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
456 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
457 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
458 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
459 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
460 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
461 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
462 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
463 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
464 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
465 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
466 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
467 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
468 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
469 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
470 0x0e800120, 0x0f800ff0,
471 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
472 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
473 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
474 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
475 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
476 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
477 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
478 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
479 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
480 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
481 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
482 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
483 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
484 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
485 0x0e8000a0, 0x0f800ff0,
486 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
487 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
488 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
489 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
490 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
491 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
492 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
493 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
494 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
495 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
496 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
497 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
498 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
499 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
500 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
501 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
502 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
503 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
504 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
505 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
506 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
507 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
508 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
509 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
510 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
511 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
512 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
513 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
514 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
515 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
516 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
517 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
518 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
519 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
520 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
521 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
522 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
523 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
524 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
525 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
526 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
527 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
528 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
529 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
530 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
531 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
532 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
533 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
534 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
535 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
536 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
537 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
538 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
539 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
540 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
541 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
542 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
544 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
545 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
546 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
547 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
548 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
549 {ANY, ARM_FEATURE_CORE_LOW (0),
550 SENTINEL_IWMMXT_END, 0, "" },
551
552 /* Floating point coprocessor (FPA) instructions. */
553 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
554 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
555 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
556 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
557 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
558 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
559 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
560 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
561 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
562 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
563 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
564 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
565 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
566 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
567 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
568 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
569 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
570 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
571 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
572 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
573 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
574 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
575 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
576 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
577 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
578 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
579 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
580 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
581 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
582 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
583 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
584 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
585 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
586 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
587 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
588 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
589 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
590 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
591 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
592 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
593 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
594 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
595 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
596 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
597 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
598 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
599 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
600 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
601 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
602 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
603 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
604 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
605 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
606 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
607 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
608 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
609 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
610 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
611 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
612 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
613 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
614 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
615 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
616 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
617 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
618 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
619 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
620 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
621 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
622 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
623 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
624 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
625 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
626 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
627 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
628 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
629 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
630 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
631 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
632 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
633 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
634 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
635 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
636 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
637 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
638 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
639
640 /* Armv8.1-M Mainline instructions. */
641 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
642 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
643 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
644 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
645
646 /* ARMv8-M Mainline Security Extensions instructions. */
647 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
648 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
649 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
650 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
651
652 /* Register load/store. */
653 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
654 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
655 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
656 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
657 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
658 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
659 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
660 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
661 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
662 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
663 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
664 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
665 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
666 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
667 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
668 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
669 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
670 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
671 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
672 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
673 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
674 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
675 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
676 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
677 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
678 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
679 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
680 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
681 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
682 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
683 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
684 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
685 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
686 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
687 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
688 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
689
690 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
691 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
692 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
693 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
694 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
695 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
696 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
697 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
698
699 /* Data transfer between ARM and NEON registers. */
700 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
701 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
702 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
703 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
704 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
705 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
706 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
707 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
708 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
709 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
710 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
711 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
712 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
713 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
714 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
715 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
716 /* Half-precision conversion instructions. */
717 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
718 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
719 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
720 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
721 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
722 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
723 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
724 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
725
726 /* Floating point coprocessor (VFP) instructions. */
727 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
728 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
729 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
730 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
731 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
732 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
733 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
734 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
735 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
736 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
737 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
738 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
739 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
740 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
741 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
742 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
743 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
744 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
745 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
746 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
747 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
748 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
749 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
750 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
751 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
752 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
753 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
754 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
755 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
756 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
757 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
758 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
759 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
760 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
761 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
762 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
763 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
764 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
765 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
766 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
767 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
768 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
769 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
770 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
771 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
772 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
773 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
774 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
775 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
776 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
777 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
778 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
779 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
780 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
781 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
782 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
783 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
784 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
785 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
786 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
787 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
788 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
789 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
790 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
791 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
792 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
793 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
794 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
795 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
796 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
797 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
798 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
799 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
800 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
801 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
802 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
803 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
804 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
805 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
806 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
807 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
808 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
809 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
810 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
812 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
814 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
815 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
816 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
818 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
820 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
822 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
824 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
826 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
828 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
829 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
830 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
831 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
832 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
833 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
834 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
835 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
836 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
838 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
840 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
842 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
843 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
844 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
845 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
846 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
847 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
848 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
849 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
850 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
851 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
852 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
853 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
854 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
855 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
856 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
857 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
858 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
859 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
860 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
861 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
862 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
863 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
864 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
865
866 /* Cirrus coprocessor instructions. */
867 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
868 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
869 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
870 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
871 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
872 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
873 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
874 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
875 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
876 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
877 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
878 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
879 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
880 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
881 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
882 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
883 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
884 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
885 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
886 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
887 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
888 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
889 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
890 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
891 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
892 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
893 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
894 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
895 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
896 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
897 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
898 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
899 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
900 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
901 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
902 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
903 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
904 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
905 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
906 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
907 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
908 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
909 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
910 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
911 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
912 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
913 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
914 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
915 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
916 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
917 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
918 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
919 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
920 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
921 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
922 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
923 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
924 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
925 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
926 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
927 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
928 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
929 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
930 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
931 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
932 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
933 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
934 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
935 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
936 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
937 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
938 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
939 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
940 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
941 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
942 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
943 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
944 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
945 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
946 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
947 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
948 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
949 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
950 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
951 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
952 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
953 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
954 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
955 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
956 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
957 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
958 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
959 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
960 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
961 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
962 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
963 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
964 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
965 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
966 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
967 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
968 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
969 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
970 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
971 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
972 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
973 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
974 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
975 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
976 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
977 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
978 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
979 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
980 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
981 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
982 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
983 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
984 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
985 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
986 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
987 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
988 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
989 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
990 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
991 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
992 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
993 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
994 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
995 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
996 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
997 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
998 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
999 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1000 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1001 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1002 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1003 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1004 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1005 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1006 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1007 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1008 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1009 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1010 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1011 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1012 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1013 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1014 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1015 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1016 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1017 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1018 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1019 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1020 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1021 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1022 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1023 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1024 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1025 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1026 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1027 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1028 0x0e000600, 0x0ff00f10,
1029 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1030 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1031 0x0e100600, 0x0ff00f10,
1032 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1033 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1034 0x0e200600, 0x0ff00f10,
1035 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1036 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1037 0x0e300600, 0x0ff00f10,
1038 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1039
1040 /* VFP Fused multiply add instructions. */
1041 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1042 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1043 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1044 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1045 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1046 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1047 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1048 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1049 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1050 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1051 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1052 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1053 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1054 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1055 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1056 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1057
1058 /* FP v5. */
1059 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1060 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1061 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1062 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1063 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1064 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1065 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1066 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1067 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1068 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1069 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1070 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1071 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1072 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1073 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1074 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1075 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1076 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1077 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1078 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1079 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1080 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1081 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1082 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1083
1084 /* Generic coprocessor instructions. */
1085 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1086 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1087 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1088 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1089 0x0c500000, 0x0ff00000,
1090 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1091 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1092 0x0e000000, 0x0f000010,
1093 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1094 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1095 0x0e10f010, 0x0f10f010,
1096 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1097 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1098 0x0e100010, 0x0f100010,
1099 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1100 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1101 0x0e000010, 0x0f100010,
1102 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1103 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1104 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1105 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1106 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1107
1108 /* V6 coprocessor instructions. */
1109 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1110 0xfc500000, 0xfff00000,
1111 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1112 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1113 0xfc400000, 0xfff00000,
1114 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1115
1116 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1117 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1118 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1119 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1120 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1121 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1122 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1123 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1124 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1125 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1126 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1127 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1128 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1129 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1130 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1131 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1132 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1133 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1134 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1135 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1136 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1137
1138 /* Dot Product instructions in the space of coprocessor 13. */
1139 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1140 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1141 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1142 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1143
1144 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1145 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1146 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1147 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1148 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1149 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1150 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1151 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1152 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1153 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1154 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1155 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1156 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1157 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1158 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1159 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1160 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1161
1162 /* V5 coprocessor instructions. */
1163 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1164 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1165 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1166 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1167 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1168 0xfe000000, 0xff000010,
1169 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1170 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1171 0xfe000010, 0xff100010,
1172 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1173 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1174 0xfe100010, 0xff100010,
1175 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1176
1177 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1178 cp_num: bit <11:8> == 0b1001.
1179 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1180 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1181 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1182 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1183 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1184 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1185 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1186 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1187 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1188 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1189 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1190 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1191 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1192 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1193 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1194 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1195 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1196 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1197 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1198 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1199 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1200 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1201 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1202 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1203 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1204 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1205 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1206 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1207 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1208 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1209 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1210 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1211 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1212 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1213 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1214 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1215 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1216 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1217 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1218 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1219 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1220 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1221 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1222 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1223 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1224 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1225 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1226 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1227 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1228 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1229 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1230 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1231 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1232 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1233 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1234 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1235 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1236 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1237 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1238 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1239 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1240 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1241 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1242 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1243 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1244 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1245 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1246 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1247 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1248 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1249 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1250
1251 /* ARMv8.3 javascript conversion instruction. */
1252 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1253 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1254
1255 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1256 };
1257
1258 /* Neon opcode table: This does not encode the top byte -- that is
1259 checked by the print_insn_neon routine, as it depends on whether we are
1260 doing thumb32 or arm32 disassembly. */
1261
1262 /* print_insn_neon recognizes the following format control codes:
1263
1264 %% %
1265
1266 %c print condition code
1267 %u print condition code (unconditional in ARM mode,
1268 UNPREDICTABLE if not AL in Thumb)
1269 %A print v{st,ld}[1234] operands
1270 %B print v{st,ld}[1234] any one operands
1271 %C print v{st,ld}[1234] single->all operands
1272 %D print scalar
1273 %E print vmov, vmvn, vorr, vbic encoded constant
1274 %F print vtbl,vtbx register list
1275
1276 %<bitfield>r print as an ARM register
1277 %<bitfield>d print the bitfield in decimal
1278 %<bitfield>e print the 2^N - bitfield in decimal
1279 %<bitfield>D print as a NEON D register
1280 %<bitfield>Q print as a NEON Q register
1281 %<bitfield>R print as a NEON D or Q register
1282 %<bitfield>Sn print byte scaled width limited by n
1283 %<bitfield>Tn print short scaled width limited by n
1284 %<bitfield>Un print long scaled width limited by n
1285
1286 %<bitfield>'c print specified char iff bitfield is all ones
1287 %<bitfield>`c print specified char iff bitfield is all zeroes
1288 %<bitfield>?ab... select from array of values in big endian order. */
1289
1290 static const struct opcode32 neon_opcodes[] =
1291 {
1292 /* Extract. */
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf2b00840, 0xffb00850,
1295 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1296 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1297 0xf2b00000, 0xffb00810,
1298 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1299
1300 /* Data transfer between ARM and NEON registers. */
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1313
1314 /* Move data element to all lanes. */
1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1321
1322 /* Table lookup. */
1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1327
1328 /* Half-precision conversions. */
1329 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1330 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1331 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1332 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1333
1334 /* NEON fused multiply add instructions. */
1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1336 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1337 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1338 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1340 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1342 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1343
1344 /* Two registers, miscellaneous. */
1345 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1346 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1347 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1348 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1350 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1351 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1352 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1353 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1354 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1355 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1356 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1357 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1358 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1359 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1360 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1361 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1362 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1363 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1364 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1365 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1366 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1369 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1370 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1372 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1376 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1388 0xf3b20300, 0xffb30fd0,
1389 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1392 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1393 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1397 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437 0xf3bb0600, 0xffbf0e10,
1438 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1440 0xf3b70600, 0xffbf0e10,
1441 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1442
1443 /* Three registers of the same length. */
1444 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1445 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1446 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1447 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1448 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1449 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1450 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1451 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1452 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1453 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1454 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1455 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1456 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1457 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1459 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1460 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1461 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1463 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1464 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1465 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1484 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1485 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1488 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1489 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1492 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1493 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1496 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1497 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1501 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1505 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1507 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1508 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1509 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1511 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1512 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1513 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1517 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1519 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1521 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1523 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1524 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1525 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1529 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1531 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1533 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1535 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1537 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1541 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1545 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1546 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1547 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1549 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1551 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1552 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1553 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1558 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1559 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561 0xf2000b00, 0xff800f10,
1562 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf2000b10, 0xff800f10,
1565 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1570 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1571 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573 0xf3000b00, 0xff800f10,
1574 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2000000, 0xfe800f10,
1577 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579 0xf2000010, 0xfe800f10,
1580 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf2000100, 0xfe800f10,
1583 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1585 0xf2000200, 0xfe800f10,
1586 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf2000210, 0xfe800f10,
1589 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591 0xf2000300, 0xfe800f10,
1592 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf2000310, 0xfe800f10,
1595 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf2000400, 0xfe800f10,
1598 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600 0xf2000410, 0xfe800f10,
1601 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603 0xf2000500, 0xfe800f10,
1604 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf2000510, 0xfe800f10,
1607 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609 0xf2000600, 0xfe800f10,
1610 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612 0xf2000610, 0xfe800f10,
1613 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1615 0xf2000700, 0xfe800f10,
1616 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf2000710, 0xfe800f10,
1619 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf2000910, 0xfe800f10,
1622 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf2000a00, 0xfe800f10,
1625 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627 0xf2000a10, 0xfe800f10,
1628 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1630 0xf3000b10, 0xff800f10,
1631 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1633 0xf3000c10, 0xff800f10,
1634 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1635
1636 /* One register and an immediate value. */
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1663
1664 /* Two registers and a shift amount. */
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1666 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf2880950, 0xfeb80fd0,
1677 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1679 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1683 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf2900950, 0xfeb00fd0,
1700 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1715 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1716 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1720 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1722 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1727 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1728 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1733 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1734 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1738 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1739 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1740 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1742 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744 0xf2a00950, 0xfea00fd0,
1745 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1751 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1755 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1767 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1780 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1781 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1782 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1783 0xf2a00e10, 0xfea00e90,
1784 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1786 0xf2a00c10, 0xfea00e90,
1787 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1788
1789 /* Three registers of different lengths. */
1790 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1791 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1792 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1793 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1794 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1795 0xf2800400, 0xff800f50,
1796 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798 0xf2800600, 0xff800f50,
1799 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1800 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1801 0xf2800900, 0xff800f50,
1802 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804 0xf2800b00, 0xff800f50,
1805 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1806 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1807 0xf2800d00, 0xff800f50,
1808 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810 0xf3800400, 0xff800f50,
1811 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1813 0xf3800600, 0xff800f50,
1814 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1815 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1816 0xf2800000, 0xfe800f50,
1817 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1819 0xf2800100, 0xfe800f50,
1820 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1821 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1822 0xf2800200, 0xfe800f50,
1823 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1825 0xf2800300, 0xfe800f50,
1826 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1827 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1828 0xf2800500, 0xfe800f50,
1829 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1831 0xf2800700, 0xfe800f50,
1832 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1833 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1834 0xf2800800, 0xfe800f50,
1835 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf2800a00, 0xfe800f50,
1838 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1839 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1840 0xf2800c00, 0xfe800f50,
1841 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1842
1843 /* Two registers and a scalar. */
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1847 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1848 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1849 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1851 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1853 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1854 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1855 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1856 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1857 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1858 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1859 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1861 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1862 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1863 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1864 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1865 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1866 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1867 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1868 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1869 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1870 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1871 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1873 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1874 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1875 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1876 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1877 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1879 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1881 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1882 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1883 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1885 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1886 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1887 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1888 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1889 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1891 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1893 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1895 0xf2800240, 0xfe800f50,
1896 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1897 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1898 0xf2800640, 0xfe800f50,
1899 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901 0xf2800a40, 0xfe800f50,
1902 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1904 0xf2800e40, 0xff800f50,
1905 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1907 0xf2800f40, 0xff800f50,
1908 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1910 0xf3800e40, 0xff800f50,
1911 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1913 0xf3800f40, 0xff800f50,
1914 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1915 },
1916
1917 /* Element and structure load/store. */
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1919 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1920 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1921 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1922 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1923 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1925 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1926 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1927 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1928 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1929 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1931 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1933 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1934 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1935 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1937 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1939 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1941 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1943 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1945 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1946 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1947 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1949 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1951 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1952 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1953 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1954 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1955 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1956
1957 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1958 };
1959
1960 /* mve opcode table. */
1961
1962 /* print_insn_mve recognizes the following format control codes:
1963
1964 %% %
1965
1966 %a print '+' or '-' or imm offset in vldr[bhwd] and
1967 vstr[bhwd]
1968 %c print condition code
1969 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1970 %u print 'U' (unsigned) or 'S' for various mve instructions
1971 %i print MVE predicate(s) for vpt and vpst
1972 %m print rounding mode for vcvt and vrint
1973 %n print vector comparison code for predicated instruction
1974 %s print size for various vcvt instructions
1975 %v print vector predicate for instruction in predicated
1976 block
1977 %o print offset scaled for vldr[hwd] and vstr[hwd]
1978 %w print writeback mode for MVE v{st,ld}[24]
1979 %B print v{st,ld}[24] any one operands
1980 %E print vmov, vmvn, vorr, vbic encoded constant
1981 %N print generic index for vmov
1982 %T print bottom ('b') or top ('t') of source register
1983 %X print exchange field in vmla* instructions
1984
1985 %<bitfield>r print as an ARM register
1986 %<bitfield>d print the bitfield in decimal
1987 %<bitfield>A print accumulate or not
1988 %<bitfield>Q print as a MVE Q register
1989 %<bitfield>F print as a MVE S register
1990 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1991 UNPREDICTABLE
1992 %<bitfield>s print size for vector predicate & non VMOV instructions
1993 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1994 %<bitfield>h print high half of 64-bit destination reg
1995 %<bitfield>k print immediate for vector conversion instruction
1996 %<bitfield>l print low half of 64-bit destination reg
1997 %<bitfield>o print rotate value for vcmul
1998 %<bitfield>u print immediate value for vddup/vdwdup
1999 %<bitfield>x print the bitfield in hex.
2000 */
2001
2002 static const struct mopcode32 mve_opcodes[] =
2003 {
2004 /* MVE. */
2005
2006 {ARM_FEATURE_COPROC (FPU_MVE),
2007 MVE_VPST,
2008 0xfe310f4d, 0xffbf1fff,
2009 "vpst%i"
2010 },
2011
2012 /* Floating point VPT T1. */
2013 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2014 MVE_VPT_FP_T1,
2015 0xee310f00, 0xefb10f50,
2016 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2017 /* Floating point VPT T2. */
2018 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2019 MVE_VPT_FP_T2,
2020 0xee310f40, 0xefb10f50,
2021 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2022
2023 /* Vector VPT T1. */
2024 {ARM_FEATURE_COPROC (FPU_MVE),
2025 MVE_VPT_VEC_T1,
2026 0xfe010f00, 0xff811f51,
2027 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2028 /* Vector VPT T2. */
2029 {ARM_FEATURE_COPROC (FPU_MVE),
2030 MVE_VPT_VEC_T2,
2031 0xfe010f01, 0xff811f51,
2032 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2033 /* Vector VPT T3. */
2034 {ARM_FEATURE_COPROC (FPU_MVE),
2035 MVE_VPT_VEC_T3,
2036 0xfe011f00, 0xff811f50,
2037 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2038 /* Vector VPT T4. */
2039 {ARM_FEATURE_COPROC (FPU_MVE),
2040 MVE_VPT_VEC_T4,
2041 0xfe010f40, 0xff811f70,
2042 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2043 /* Vector VPT T5. */
2044 {ARM_FEATURE_COPROC (FPU_MVE),
2045 MVE_VPT_VEC_T5,
2046 0xfe010f60, 0xff811f70,
2047 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2048 /* Vector VPT T6. */
2049 {ARM_FEATURE_COPROC (FPU_MVE),
2050 MVE_VPT_VEC_T6,
2051 0xfe011f40, 0xff811f50,
2052 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2053
2054 /* Vector VBIC immediate. */
2055 {ARM_FEATURE_COPROC (FPU_MVE),
2056 MVE_VBIC_IMM,
2057 0xef800070, 0xefb81070,
2058 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2059
2060 /* Vector VBIC register. */
2061 {ARM_FEATURE_COPROC (FPU_MVE),
2062 MVE_VBIC_REG,
2063 0xef100150, 0xffb11f51,
2064 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2065
2066 /* Vector VADDLV. */
2067 {ARM_FEATURE_COPROC (FPU_MVE),
2068 MVE_VADDLV,
2069 0xee890f00, 0xef8f1fd1,
2070 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2071
2072 /* Vector VADDV. */
2073 {ARM_FEATURE_COPROC (FPU_MVE),
2074 MVE_VADDV,
2075 0xeef10f00, 0xeff31fd1,
2076 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2077
2078 /* Vector VCADD floating point. */
2079 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2080 MVE_VCADD_FP,
2081 0xfc800840, 0xfea11f51,
2082 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2083
2084 /* Vector VCADD. */
2085 {ARM_FEATURE_COPROC (FPU_MVE),
2086 MVE_VCADD_VEC,
2087 0xfe000f00, 0xff810f51,
2088 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2089
2090 /* Vector VCMLA. */
2091 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2092 MVE_VCMLA_FP,
2093 0xfc200840, 0xfe211f51,
2094 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2095
2096 /* Vector VCMP floating point T1. */
2097 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2098 MVE_VCMP_FP_T1,
2099 0xee310f00, 0xeff1ef50,
2100 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2101
2102 /* Vector VCMP floating point T2. */
2103 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2104 MVE_VCMP_FP_T2,
2105 0xee310f40, 0xeff1ef50,
2106 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2107
2108 /* Vector VCMP T1. */
2109 {ARM_FEATURE_COPROC (FPU_MVE),
2110 MVE_VCMP_VEC_T1,
2111 0xfe010f00, 0xffc1ff51,
2112 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2113 /* Vector VCMP T2. */
2114 {ARM_FEATURE_COPROC (FPU_MVE),
2115 MVE_VCMP_VEC_T2,
2116 0xfe010f01, 0xffc1ff51,
2117 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2118 /* Vector VCMP T3. */
2119 {ARM_FEATURE_COPROC (FPU_MVE),
2120 MVE_VCMP_VEC_T3,
2121 0xfe011f00, 0xffc1ff50,
2122 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2123 /* Vector VCMP T4. */
2124 {ARM_FEATURE_COPROC (FPU_MVE),
2125 MVE_VCMP_VEC_T4,
2126 0xfe010f40, 0xffc1ff70,
2127 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2128 /* Vector VCMP T5. */
2129 {ARM_FEATURE_COPROC (FPU_MVE),
2130 MVE_VCMP_VEC_T5,
2131 0xfe010f60, 0xffc1ff70,
2132 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2133 /* Vector VCMP T6. */
2134 {ARM_FEATURE_COPROC (FPU_MVE),
2135 MVE_VCMP_VEC_T6,
2136 0xfe011f40, 0xffc1ff50,
2137 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2138
2139 /* Vector VDUP. */
2140 {ARM_FEATURE_COPROC (FPU_MVE),
2141 MVE_VDUP,
2142 0xeea00b10, 0xffb10f5f,
2143 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2144
2145 /* Vector VEOR. */
2146 {ARM_FEATURE_COPROC (FPU_MVE),
2147 MVE_VEOR,
2148 0xff000150, 0xffd11f51,
2149 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2150
2151 /* Vector VFMA, vector * scalar. */
2152 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2153 MVE_VFMA_FP_SCALAR,
2154 0xee310e40, 0xefb11f70,
2155 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2156
2157 /* Vector VFMA floating point. */
2158 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2159 MVE_VFMA_FP,
2160 0xef000c50, 0xffa11f51,
2161 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2162
2163 /* Vector VFMS floating point. */
2164 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2165 MVE_VFMS_FP,
2166 0xef200c50, 0xffa11f51,
2167 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2168
2169 /* Vector VFMAS, vector * scalar. */
2170 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2171 MVE_VFMAS_FP_SCALAR,
2172 0xee311e40, 0xefb11f70,
2173 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2174
2175 /* Vector VHADD T1. */
2176 {ARM_FEATURE_COPROC (FPU_MVE),
2177 MVE_VHADD_T1,
2178 0xef000040, 0xef811f51,
2179 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2180
2181 /* Vector VHADD T2. */
2182 {ARM_FEATURE_COPROC (FPU_MVE),
2183 MVE_VHADD_T2,
2184 0xee000f40, 0xef811f70,
2185 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2186
2187 /* Vector VHSUB T1. */
2188 {ARM_FEATURE_COPROC (FPU_MVE),
2189 MVE_VHSUB_T1,
2190 0xef000240, 0xef811f51,
2191 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2192
2193 /* Vector VHSUB T2. */
2194 {ARM_FEATURE_COPROC (FPU_MVE),
2195 MVE_VHSUB_T2,
2196 0xee001f40, 0xef811f70,
2197 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2198
2199 /* Vector VCMUL. */
2200 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2201 MVE_VCMUL_FP,
2202 0xee300e00, 0xefb10f50,
2203 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2204
2205 /* Vector VDUP. */
2206 {ARM_FEATURE_COPROC (FPU_MVE),
2207 MVE_VDUP,
2208 0xeea00b10, 0xffb10f5f,
2209 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2210
2211 /* Vector VRHADD. */
2212 {ARM_FEATURE_COPROC (FPU_MVE),
2213 MVE_VRHADD,
2214 0xef000140, 0xef811f51,
2215 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2216
2217 /* Vector VCVT. */
2218 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2219 MVE_VCVT_FP_FIX_VEC,
2220 0xef800c50, 0xef801cd1,
2221 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2222
2223 /* Vector VCVT. */
2224 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2225 MVE_VCVT_BETWEEN_FP_INT,
2226 0xffb30640, 0xffb31e51,
2227 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2228
2229 /* Vector VCVT between single and half-precision float, bottom half. */
2230 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2231 MVE_VCVT_FP_HALF_FP,
2232 0xee3f0e01, 0xefbf1fd1,
2233 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2234
2235 /* Vector VCVT between single and half-precision float, top half. */
2236 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2237 MVE_VCVT_FP_HALF_FP,
2238 0xee3f1e01, 0xefbf1fd1,
2239 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2240
2241 /* Vector VCVT. */
2242 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2243 MVE_VCVT_FROM_FP_TO_INT,
2244 0xffb30040, 0xffb31c51,
2245 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2246
2247 /* Vector VDDUP. */
2248 {ARM_FEATURE_COPROC (FPU_MVE),
2249 MVE_VDDUP,
2250 0xee011f6e, 0xff811f7e,
2251 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2252
2253 /* Vector VDWDUP. */
2254 {ARM_FEATURE_COPROC (FPU_MVE),
2255 MVE_VDWDUP,
2256 0xee011f60, 0xff811f70,
2257 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2258
2259 /* Vector VHCADD. */
2260 {ARM_FEATURE_COPROC (FPU_MVE),
2261 MVE_VHCADD,
2262 0xee000f00, 0xff810f51,
2263 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2264
2265 /* Vector VIWDUP. */
2266 {ARM_FEATURE_COPROC (FPU_MVE),
2267 MVE_VIWDUP,
2268 0xee010f60, 0xff811f70,
2269 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2270
2271 /* Vector VIDUP. */
2272 {ARM_FEATURE_COPROC (FPU_MVE),
2273 MVE_VIDUP,
2274 0xee010f6e, 0xff811f7e,
2275 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2276
2277 /* Vector VLD2. */
2278 {ARM_FEATURE_COPROC (FPU_MVE),
2279 MVE_VLD2,
2280 0xfc901e00, 0xff901e5f,
2281 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2282
2283 /* Vector VLD4. */
2284 {ARM_FEATURE_COPROC (FPU_MVE),
2285 MVE_VLD4,
2286 0xfc901e01, 0xff901e1f,
2287 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2288
2289 /* Vector VLDRB gather load. */
2290 {ARM_FEATURE_COPROC (FPU_MVE),
2291 MVE_VLDRB_GATHER_T1,
2292 0xec900e00, 0xefb01e50,
2293 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2294
2295 /* Vector VLDRH gather load. */
2296 {ARM_FEATURE_COPROC (FPU_MVE),
2297 MVE_VLDRH_GATHER_T2,
2298 0xec900e10, 0xefb01e50,
2299 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2300
2301 /* Vector VLDRW gather load. */
2302 {ARM_FEATURE_COPROC (FPU_MVE),
2303 MVE_VLDRW_GATHER_T3,
2304 0xfc900f40, 0xffb01fd0,
2305 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2306
2307 /* Vector VLDRD gather load. */
2308 {ARM_FEATURE_COPROC (FPU_MVE),
2309 MVE_VLDRD_GATHER_T4,
2310 0xec900fd0, 0xefb01fd0,
2311 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2312
2313 /* Vector VLDRW gather load. */
2314 {ARM_FEATURE_COPROC (FPU_MVE),
2315 MVE_VLDRW_GATHER_T5,
2316 0xfd101e00, 0xff111f00,
2317 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2318
2319 /* Vector VLDRD gather load, variant T6. */
2320 {ARM_FEATURE_COPROC (FPU_MVE),
2321 MVE_VLDRD_GATHER_T6,
2322 0xfd101f00, 0xff111f00,
2323 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2324
2325 /* Vector VLDRB. */
2326 {ARM_FEATURE_COPROC (FPU_MVE),
2327 MVE_VLDRB_T1,
2328 0xec100e00, 0xee581e00,
2329 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2330
2331 /* Vector VLDRH. */
2332 {ARM_FEATURE_COPROC (FPU_MVE),
2333 MVE_VLDRH_T2,
2334 0xec180e00, 0xee581e00,
2335 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2336
2337 /* Vector VLDRB unsigned, variant T5. */
2338 {ARM_FEATURE_COPROC (FPU_MVE),
2339 MVE_VLDRB_T5,
2340 0xec101e00, 0xfe101f80,
2341 "vldrb%v.u8\t%13-15,22Q, %d"},
2342
2343 /* Vector VLDRH unsigned, variant T6. */
2344 {ARM_FEATURE_COPROC (FPU_MVE),
2345 MVE_VLDRH_T6,
2346 0xec101e80, 0xfe101f80,
2347 "vldrh%v.u16\t%13-15,22Q, %d"},
2348
2349 /* Vector VLDRW unsigned, variant T7. */
2350 {ARM_FEATURE_COPROC (FPU_MVE),
2351 MVE_VLDRW_T7,
2352 0xec101f00, 0xfe101f80,
2353 "vldrw%v.u32\t%13-15,22Q, %d"},
2354
2355 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2356 opcode aliasing. */
2357 {ARM_FEATURE_COPROC (FPU_MVE),
2358 MVE_VMLALDAV,
2359 0xee801e00, 0xef801f51,
2360 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2361
2362 {ARM_FEATURE_COPROC (FPU_MVE),
2363 MVE_VMLALDAV,
2364 0xee800e00, 0xef801f51,
2365 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2366
2367 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2368 {ARM_FEATURE_COPROC (FPU_MVE),
2369 MVE_VMLADAV_T1,
2370 0xeef00e00, 0xeff01f51,
2371 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2372
2373 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2374 {ARM_FEATURE_COPROC (FPU_MVE),
2375 MVE_VMLADAV_T2,
2376 0xeef00f00, 0xeff11f51,
2377 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2378
2379 /* Vector VMLADAV T1 variant. */
2380 {ARM_FEATURE_COPROC (FPU_MVE),
2381 MVE_VMLADAV_T1,
2382 0xeef01e00, 0xeff01f51,
2383 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2384
2385 /* Vector VMLADAV T2 variant. */
2386 {ARM_FEATURE_COPROC (FPU_MVE),
2387 MVE_VMLADAV_T2,
2388 0xeef01f00, 0xeff11f51,
2389 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2390
2391 /* Vector VMLAS. */
2392 {ARM_FEATURE_COPROC (FPU_MVE),
2393 MVE_VMLAS,
2394 0xee011e40, 0xef811f70,
2395 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2396
2397 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2398 opcode aliasing. */
2399 {ARM_FEATURE_COPROC (FPU_MVE),
2400 MVE_VRMLSLDAVH,
2401 0xfe800e01, 0xff810f51,
2402 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2403
2404 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2405 opcdoe aliasing. */
2406 {ARM_FEATURE_COPROC (FPU_MVE),
2407 MVE_VMLSLDAV,
2408 0xee800e01, 0xff800f51,
2409 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2410
2411 /* Vector VMLSDAV T1 Variant. */
2412 {ARM_FEATURE_COPROC (FPU_MVE),
2413 MVE_VMLSDAV_T1,
2414 0xeef00e01, 0xfff00f51,
2415 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2416
2417 /* Vector VMLSDAV T2 Variant. */
2418 {ARM_FEATURE_COPROC (FPU_MVE),
2419 MVE_VMLSDAV_T2,
2420 0xfef00e01, 0xfff10f51,
2421 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2422
2423 /* Vector VMOV between gpr and half precision register, op == 0. */
2424 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2425 MVE_VMOV_HFP_TO_GP,
2426 0xee000910, 0xfff00f7f,
2427 "vmov.f16\t%7,16-19F, %12-15r"},
2428
2429 /* Vector VMOV between gpr and half precision register, op == 1. */
2430 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2431 MVE_VMOV_HFP_TO_GP,
2432 0xee100910, 0xfff00f7f,
2433 "vmov.f16\t%12-15r, %7,16-19F"},
2434
2435 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2436 MVE_VMOV_GP_TO_VEC_LANE,
2437 0xee000b10, 0xff900f1f,
2438 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2439
2440 /* Vector VORR immediate to vector.
2441 NOTE: MVE_VORR_IMM must appear in the table
2442 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2443 {ARM_FEATURE_COPROC (FPU_MVE),
2444 MVE_VORR_IMM,
2445 0xef800050, 0xefb810f0,
2446 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2447
2448 /* Vector VQSHL T2 Variant.
2449 NOTE: MVE_VQSHL_T2 must appear in the table before
2450 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2451 {ARM_FEATURE_COPROC (FPU_MVE),
2452 MVE_VQSHL_T2,
2453 0xef800750, 0xef801fd1,
2454 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2455
2456 /* Vector VQSHLU T3 Variant
2457 NOTE: MVE_VQSHL_T2 must appear in the table before
2458 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2459
2460 {ARM_FEATURE_COPROC (FPU_MVE),
2461 MVE_VQSHLU_T3,
2462 0xff800650, 0xff801fd1,
2463 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2464
2465 /* Vector VRSHR
2466 NOTE: MVE_VRSHR must appear in the table before
2467 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2468 {ARM_FEATURE_COPROC (FPU_MVE),
2469 MVE_VRSHR,
2470 0xef800250, 0xef801fd1,
2471 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2472
2473 /* Vector VSHL.
2474 NOTE: MVE_VSHL must appear in the table before
2475 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2476 {ARM_FEATURE_COPROC (FPU_MVE),
2477 MVE_VSHL_T1,
2478 0xef800550, 0xff801fd1,
2479 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2480
2481 /* Vector VSHR
2482 NOTE: MVE_VSHR must appear in the table before
2483 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2484 {ARM_FEATURE_COPROC (FPU_MVE),
2485 MVE_VSHR,
2486 0xef800050, 0xef801fd1,
2487 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2488
2489 /* Vector VSLI
2490 NOTE: MVE_VSLI must appear in the table before
2491 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2492 {ARM_FEATURE_COPROC (FPU_MVE),
2493 MVE_VSLI,
2494 0xff800550, 0xff801fd1,
2495 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2496
2497 /* Vector VSRI
2498 NOTE: MVE_VSRI must appear in the table before
2499 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2500 {ARM_FEATURE_COPROC (FPU_MVE),
2501 MVE_VSRI,
2502 0xff800450, 0xff801fd1,
2503 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2504
2505 /* Vector VMOV immediate to vector,
2506 cmode == 11x1 -> VMVN which is UNDEFINED
2507 for such a cmode. */
2508 {ARM_FEATURE_COPROC (FPU_MVE),
2509 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2510
2511 /* Vector VMOV immediate to vector. */
2512 {ARM_FEATURE_COPROC (FPU_MVE),
2513 MVE_VMOV_IMM_TO_VEC,
2514 0xef800050, 0xefb810d0,
2515 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2516
2517 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2518 {ARM_FEATURE_COPROC (FPU_MVE),
2519 MVE_VMOV2_VEC_LANE_TO_GP,
2520 0xec000f00, 0xffb01ff0,
2521 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2522
2523 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2524 {ARM_FEATURE_COPROC (FPU_MVE),
2525 MVE_VMOV2_VEC_LANE_TO_GP,
2526 0xec000f10, 0xffb01ff0,
2527 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2528
2529 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2530 {ARM_FEATURE_COPROC (FPU_MVE),
2531 MVE_VMOV2_GP_TO_VEC_LANE,
2532 0xec100f00, 0xffb01ff0,
2533 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2534
2535 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2536 {ARM_FEATURE_COPROC (FPU_MVE),
2537 MVE_VMOV2_GP_TO_VEC_LANE,
2538 0xec100f10, 0xffb01ff0,
2539 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2540
2541 /* Vector VMOV Vector lane to gpr. */
2542 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2543 MVE_VMOV_VEC_LANE_TO_GP,
2544 0xee100b10, 0xff100f1f,
2545 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2546
2547 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2548 to instruction opcode aliasing. */
2549 {ARM_FEATURE_COPROC (FPU_MVE),
2550 MVE_VSHLL_T1,
2551 0xeea00f40, 0xefa00fd1,
2552 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2553
2554 /* Vector VMOVL long. */
2555 {ARM_FEATURE_COPROC (FPU_MVE),
2556 MVE_VMOVL,
2557 0xeea00f40, 0xefa70fd1,
2558 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2559
2560 /* Vector VMOV and narrow. */
2561 {ARM_FEATURE_COPROC (FPU_MVE),
2562 MVE_VMOVN,
2563 0xfe310e81, 0xffb30fd1,
2564 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2565
2566 /* Floating point move extract. */
2567 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2568 MVE_VMOVX,
2569 0xfeb00a40, 0xffbf0fd0,
2570 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2571
2572 /* Vector VMULL integer. */
2573 {ARM_FEATURE_COPROC (FPU_MVE),
2574 MVE_VMULL_INT,
2575 0xee010e00, 0xef810f51,
2576 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2577
2578 /* Vector VMULL polynomial. */
2579 {ARM_FEATURE_COPROC (FPU_MVE),
2580 MVE_VMULL_POLY,
2581 0xee310e00, 0xefb10f51,
2582 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2583
2584 /* Vector VMVN immediate to vector. */
2585 {ARM_FEATURE_COPROC (FPU_MVE),
2586 MVE_VMVN_IMM,
2587 0xef800070, 0xefb810f0,
2588 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2589
2590 /* Vector VMVN register. */
2591 {ARM_FEATURE_COPROC (FPU_MVE),
2592 MVE_VMVN_REG,
2593 0xffb005c0, 0xffbf1fd1,
2594 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2595
2596 /* Vector VORN, vector bitwise or not. */
2597 {ARM_FEATURE_COPROC (FPU_MVE),
2598 MVE_VORN,
2599 0xef300150, 0xffb11f51,
2600 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2601
2602 /* Vector VORR register. */
2603 {ARM_FEATURE_COPROC (FPU_MVE),
2604 MVE_VORR_REG,
2605 0xef200150, 0xffb11f51,
2606 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2607
2608 /* Vector VQDMULL T1 variant. */
2609 {ARM_FEATURE_COPROC (FPU_MVE),
2610 MVE_VQDMULL_T1,
2611 0xee300f01, 0xefb10f51,
2612 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2613
2614 /* Vector VQDMULL T2 variant. */
2615 {ARM_FEATURE_COPROC (FPU_MVE),
2616 MVE_VQDMULL_T2,
2617 0xee300f60, 0xefb10f70,
2618 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2619
2620 /* Vector VQMOVN. */
2621 {ARM_FEATURE_COPROC (FPU_MVE),
2622 MVE_VQMOVN,
2623 0xee330e01, 0xefb30fd1,
2624 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2625
2626 /* Vector VQMOVUN. */
2627 {ARM_FEATURE_COPROC (FPU_MVE),
2628 MVE_VQMOVUN,
2629 0xee310e81, 0xffb30fd1,
2630 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2631
2632 /* Vector VQDMLADH. */
2633 {ARM_FEATURE_COPROC (FPU_MVE),
2634 MVE_VQDMLADH,
2635 0xee000e00, 0xff810f51,
2636 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2637
2638 /* Vector VQRDMLADH. */
2639 {ARM_FEATURE_COPROC (FPU_MVE),
2640 MVE_VQRDMLADH,
2641 0xee000e01, 0xff810f51,
2642 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2643
2644 /* Vector VQDMLAH. */
2645 {ARM_FEATURE_COPROC (FPU_MVE),
2646 MVE_VQDMLAH,
2647 0xee000e60, 0xef811f70,
2648 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2649
2650 /* Vector VQRDMLAH. */
2651 {ARM_FEATURE_COPROC (FPU_MVE),
2652 MVE_VQRDMLAH,
2653 0xee000e40, 0xef811f70,
2654 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2655
2656 /* Vector VQDMLASH. */
2657 {ARM_FEATURE_COPROC (FPU_MVE),
2658 MVE_VQDMLASH,
2659 0xee001e60, 0xef811f70,
2660 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2661
2662 /* Vector VQRDMLASH. */
2663 {ARM_FEATURE_COPROC (FPU_MVE),
2664 MVE_VQRDMLASH,
2665 0xee001e40, 0xef811f70,
2666 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2667
2668 /* Vector VQDMLSDH. */
2669 {ARM_FEATURE_COPROC (FPU_MVE),
2670 MVE_VQDMLSDH,
2671 0xfe000e00, 0xff810f51,
2672 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2673
2674 /* Vector VQRDMLSDH. */
2675 {ARM_FEATURE_COPROC (FPU_MVE),
2676 MVE_VQRDMLSDH,
2677 0xfe000e01, 0xff810f51,
2678 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2679
2680 /* Vector VQDMULH T1 variant. */
2681 {ARM_FEATURE_COPROC (FPU_MVE),
2682 MVE_VQDMULH_T1,
2683 0xef000b40, 0xff811f51,
2684 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2685
2686 /* Vector VQRDMULH T2 variant. */
2687 {ARM_FEATURE_COPROC (FPU_MVE),
2688 MVE_VQRDMULH_T2,
2689 0xff000b40, 0xff811f51,
2690 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2691
2692 /* Vector VQDMULH T3 variant. */
2693 {ARM_FEATURE_COPROC (FPU_MVE),
2694 MVE_VQDMULH_T3,
2695 0xee010e60, 0xff811f70,
2696 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2697
2698 /* Vector VQRDMULH T4 variant. */
2699 {ARM_FEATURE_COPROC (FPU_MVE),
2700 MVE_VQRDMULH_T4,
2701 0xfe010e60, 0xff811f70,
2702 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2703
2704 /* Vector VQRSHL T1 variant. */
2705 {ARM_FEATURE_COPROC (FPU_MVE),
2706 MVE_VQRSHL_T1,
2707 0xef000550, 0xef811f51,
2708 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2709
2710 /* Vector VQRSHL T2 variant. */
2711 {ARM_FEATURE_COPROC (FPU_MVE),
2712 MVE_VQRSHL_T2,
2713 0xee331ee0, 0xefb31ff0,
2714 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2715
2716 /* Vector VQRSHRN. */
2717 {ARM_FEATURE_COPROC (FPU_MVE),
2718 MVE_VQRSHRN,
2719 0xee800f41, 0xefa00fd1,
2720 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2721
2722 /* Vector VQRSHRUN. */
2723 {ARM_FEATURE_COPROC (FPU_MVE),
2724 MVE_VQRSHRUN,
2725 0xfe800fc0, 0xffa00fd1,
2726 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2727
2728 /* Vector VQSHL T1 Variant. */
2729 {ARM_FEATURE_COPROC (FPU_MVE),
2730 MVE_VQSHL_T1,
2731 0xee311ee0, 0xefb31ff0,
2732 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2733
2734 /* Vector VQSHL T4 Variant. */
2735 {ARM_FEATURE_COPROC (FPU_MVE),
2736 MVE_VQSHL_T4,
2737 0xef000450, 0xef811f51,
2738 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2739
2740 /* Vector VQSHRN. */
2741 {ARM_FEATURE_COPROC (FPU_MVE),
2742 MVE_VQSHRN,
2743 0xee800f40, 0xefa00fd1,
2744 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2745
2746 /* Vector VQSHRUN. */
2747 {ARM_FEATURE_COPROC (FPU_MVE),
2748 MVE_VQSHRUN,
2749 0xee800fc0, 0xffa00fd1,
2750 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2751
2752 /* Vector VRINT floating point. */
2753 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2754 MVE_VRINT_FP,
2755 0xffb20440, 0xffb31c51,
2756 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2757
2758 /* Vector VRMLALDAVH. */
2759 {ARM_FEATURE_COPROC (FPU_MVE),
2760 MVE_VRMLALDAVH,
2761 0xee800f00, 0xef811f51,
2762 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2763
2764 /* Vector VRMLALDAVH. */
2765 {ARM_FEATURE_COPROC (FPU_MVE),
2766 MVE_VRMLALDAVH,
2767 0xee801f00, 0xef811f51,
2768 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2769
2770 /* Vector VRSHL T1 Variant. */
2771 {ARM_FEATURE_COPROC (FPU_MVE),
2772 MVE_VRSHL_T1,
2773 0xef000540, 0xef811f51,
2774 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2775
2776 /* Vector VRSHL T2 Variant. */
2777 {ARM_FEATURE_COPROC (FPU_MVE),
2778 MVE_VRSHL_T2,
2779 0xee331e60, 0xefb31ff0,
2780 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2781
2782 /* Vector VRSHRN. */
2783 {ARM_FEATURE_COPROC (FPU_MVE),
2784 MVE_VRSHRN,
2785 0xfe800fc1, 0xffa00fd1,
2786 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2787
2788 /* Vector VSHL T2 Variant. */
2789 {ARM_FEATURE_COPROC (FPU_MVE),
2790 MVE_VSHL_T2,
2791 0xee311e60, 0xefb31ff0,
2792 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2793
2794 /* Vector VSHL T3 Variant. */
2795 {ARM_FEATURE_COPROC (FPU_MVE),
2796 MVE_VSHL_T3,
2797 0xef000440, 0xef811f51,
2798 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2799
2800 /* Vector VSHLC. */
2801 {ARM_FEATURE_COPROC (FPU_MVE),
2802 MVE_VSHLC,
2803 0xeea00fc0, 0xffa01ff0,
2804 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
2805
2806 /* Vector VSHLL T2 Variant. */
2807 {ARM_FEATURE_COPROC (FPU_MVE),
2808 MVE_VSHLL_T2,
2809 0xee310e01, 0xefb30fd1,
2810 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
2811
2812 /* Vector VSHRN. */
2813 {ARM_FEATURE_COPROC (FPU_MVE),
2814 MVE_VSHRN,
2815 0xee800fc1, 0xffa00fd1,
2816 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2817
2818 /* Vector VST2 no writeback. */
2819 {ARM_FEATURE_COPROC (FPU_MVE),
2820 MVE_VST2,
2821 0xfc801e00, 0xffb01e5f,
2822 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2823
2824 /* Vector VST2 writeback. */
2825 {ARM_FEATURE_COPROC (FPU_MVE),
2826 MVE_VST2,
2827 0xfca01e00, 0xffb01e5f,
2828 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2829
2830 /* Vector VST4 no writeback. */
2831 {ARM_FEATURE_COPROC (FPU_MVE),
2832 MVE_VST4,
2833 0xfc801e01, 0xffb01e1f,
2834 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2835
2836 /* Vector VST4 writeback. */
2837 {ARM_FEATURE_COPROC (FPU_MVE),
2838 MVE_VST4,
2839 0xfca01e01, 0xffb01e1f,
2840 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2841
2842 /* Vector VSTRB scatter store, T1 variant. */
2843 {ARM_FEATURE_COPROC (FPU_MVE),
2844 MVE_VSTRB_SCATTER_T1,
2845 0xec800e00, 0xffb01e50,
2846 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2847
2848 /* Vector VSTRH scatter store, T2 variant. */
2849 {ARM_FEATURE_COPROC (FPU_MVE),
2850 MVE_VSTRH_SCATTER_T2,
2851 0xec800e10, 0xffb01e50,
2852 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2853
2854 /* Vector VSTRW scatter store, T3 variant. */
2855 {ARM_FEATURE_COPROC (FPU_MVE),
2856 MVE_VSTRW_SCATTER_T3,
2857 0xec800e40, 0xffb01e50,
2858 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2859
2860 /* Vector VSTRD scatter store, T4 variant. */
2861 {ARM_FEATURE_COPROC (FPU_MVE),
2862 MVE_VSTRD_SCATTER_T4,
2863 0xec800fd0, 0xffb01fd0,
2864 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2865
2866 /* Vector VSTRW scatter store, T5 variant. */
2867 {ARM_FEATURE_COPROC (FPU_MVE),
2868 MVE_VSTRW_SCATTER_T5,
2869 0xfd001e00, 0xff111f00,
2870 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2871
2872 /* Vector VSTRD scatter store, T6 variant. */
2873 {ARM_FEATURE_COPROC (FPU_MVE),
2874 MVE_VSTRD_SCATTER_T6,
2875 0xfd001f00, 0xff111f00,
2876 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2877
2878 /* Vector VSTRB. */
2879 {ARM_FEATURE_COPROC (FPU_MVE),
2880 MVE_VSTRB_T1,
2881 0xec000e00, 0xfe581e00,
2882 "vstrb%v.%7-8s\t%13-15Q, %d"},
2883
2884 /* Vector VSTRH. */
2885 {ARM_FEATURE_COPROC (FPU_MVE),
2886 MVE_VSTRH_T2,
2887 0xec080e00, 0xfe581e00,
2888 "vstrh%v.%7-8s\t%13-15Q, %d"},
2889
2890 /* Vector VSTRB variant T5. */
2891 {ARM_FEATURE_COPROC (FPU_MVE),
2892 MVE_VSTRB_T5,
2893 0xec001e00, 0xfe101f80,
2894 "vstrb%v.8\t%13-15,22Q, %d"},
2895
2896 /* Vector VSTRH variant T6. */
2897 {ARM_FEATURE_COPROC (FPU_MVE),
2898 MVE_VSTRH_T6,
2899 0xec001e80, 0xfe101f80,
2900 "vstrh%v.16\t%13-15,22Q, %d"},
2901
2902 /* Vector VSTRW variant T7. */
2903 {ARM_FEATURE_COPROC (FPU_MVE),
2904 MVE_VSTRW_T7,
2905 0xec001f00, 0xfe101f80,
2906 "vstrw%v.32\t%13-15,22Q, %d"},
2907
2908 {ARM_FEATURE_CORE_LOW (0),
2909 MVE_NONE,
2910 0x00000000, 0x00000000, 0}
2911 };
2912
2913 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
2914 ordered: they must be searched linearly from the top to obtain a correct
2915 match. */
2916
2917 /* print_insn_arm recognizes the following format control codes:
2918
2919 %% %
2920
2921 %a print address for ldr/str instruction
2922 %s print address for ldr/str halfword/signextend instruction
2923 %S like %s but allow UNPREDICTABLE addressing
2924 %b print branch destination
2925 %c print condition code (always bits 28-31)
2926 %m print register mask for ldm/stm instruction
2927 %o print operand2 (immediate or register + shift)
2928 %p print 'p' iff bits 12-15 are 15
2929 %t print 't' iff bit 21 set and bit 24 clear
2930 %B print arm BLX(1) destination
2931 %C print the PSR sub type.
2932 %U print barrier type.
2933 %P print address for pli instruction.
2934
2935 %<bitfield>r print as an ARM register
2936 %<bitfield>T print as an ARM register + 1
2937 %<bitfield>R as %r but r15 is UNPREDICTABLE
2938 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2939 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
2940 %<bitfield>d print the bitfield in decimal
2941 %<bitfield>W print the bitfield plus one in decimal
2942 %<bitfield>x print the bitfield in hex
2943 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2944
2945 %<bitfield>'c print specified char iff bitfield is all ones
2946 %<bitfield>`c print specified char iff bitfield is all zeroes
2947 %<bitfield>?ab... select from array of values in big endian order
2948
2949 %e print arm SMI operand (bits 0..7,8..19).
2950 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
2951 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
2952 %R print the SPSR/CPSR or banked register of an MRS. */
2953
2954 static const struct opcode32 arm_opcodes[] =
2955 {
2956 /* ARM instructions. */
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2958 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2960 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2961
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
2963 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2965 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2967 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
2969 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2971 0x00800090, 0x0fa000f0,
2972 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2974 0x00a00090, 0x0fa000f0,
2975 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2976
2977 /* V8.2 RAS extension instructions. */
2978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
2979 0xe320f010, 0xffffffff, "esb"},
2980
2981 /* V8 instructions. */
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2983 0x0320f005, 0x0fffffff, "sevl"},
2984 /* Defined in V8 but is in NOP space so available to all arch. */
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2986 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
2987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
2988 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2990 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2992 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2994 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2996 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2998 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3000 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3002 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3004 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3006 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3008 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3010 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3012 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3014 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3015 /* CRC32 instructions. */
3016 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3017 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3018 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3019 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3020 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3021 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3022 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3023 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3024 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3025 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3026 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3027 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3028
3029 /* Privileged Access Never extension instructions. */
3030 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3031 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3032
3033 /* Virtualization Extension instructions. */
3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3036
3037 /* Integer Divide Extension instructions. */
3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3039 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3041 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3042
3043 /* MP Extension instructions. */
3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3045
3046 /* Speculation Barriers. */
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3050
3051 /* V7 instructions. */
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3060 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3061
3062 /* ARM V6T2 instructions. */
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3064 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3066 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3068 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3070 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3071
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3073 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3075 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3076
3077 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3078 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3080 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3082 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3084 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3085
3086 /* ARM Security extension instructions. */
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3088 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3089
3090 /* ARM V6K instructions. */
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3092 0xf57ff01f, 0xffffffff, "clrex"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3094 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3096 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3098 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3100 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3102 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3104 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3105
3106 /* ARMv8.5-A instructions. */
3107 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3108
3109 /* ARM V6K NOP hints. */
3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3111 0x0320f001, 0x0fffffff, "yield%c"},
3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3113 0x0320f002, 0x0fffffff, "wfe%c"},
3114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3115 0x0320f003, 0x0fffffff, "wfi%c"},
3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3117 0x0320f004, 0x0fffffff, "sev%c"},
3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3119 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3120
3121 /* ARM V6 instructions. */
3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3123 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3125 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3127 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3129 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3131 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3133 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3135 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3137 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3139 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3141 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3143 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3145 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3147 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3149 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3151 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3153 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3155 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3157 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3159 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3161 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3163 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3165 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3167 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3169 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3171 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3173 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3175 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3177 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3179 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3181 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3183 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3185 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3187 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3189 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3191 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3193 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3195 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3197 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3199 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3201 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3203 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3205 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3207 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3209 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3211 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3213 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3215 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3217 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3219 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3221 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3223 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3225 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3227 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3229 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3231 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3233 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3235 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3237 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3239 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3241 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3243 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3245 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3247 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3249 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3251 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3253 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3255 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3257 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3259 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3261 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3263 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3265 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3267 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3269 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3271 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3273 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3275 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3277 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3279 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3281 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3283 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3285 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3287 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3289 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3291 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3293 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3295 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3297 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3299 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3301 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3303 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3305 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3307 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3309 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3311 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3313 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3315 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3317 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3319 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3321 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3323 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3325 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3327 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3329 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3331 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3333 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3335 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3337 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3339 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3341 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3343 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3345 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3347 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3349 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3351 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3353 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3355 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3357 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3359 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3361 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3363 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3365 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3366
3367 /* V5J instruction. */
3368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3369 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3370
3371 /* V5 Instructions. */
3372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3373 0xe1200070, 0xfff000f0,
3374 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3376 0xfa000000, 0xfe000000, "blx\t%B"},
3377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3378 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3380 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3381
3382 /* V5E "El Segundo" Instructions. */
3383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3384 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3386 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3388 0xf450f000, 0xfc70f000, "pld\t%a"},
3389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3390 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3392 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3394 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3396 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3397
3398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3399 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3401 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3402
3403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3404 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3406 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3408 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3410 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3411
3412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3413 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3415 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3417 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3419 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3420
3421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3422 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3424 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3425
3426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3427 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3429 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3431 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3433 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3434
3435 /* ARM Instructions. */
3436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3437 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3438
3439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3440 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3442 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3444 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3446 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3448 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3450 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3451
3452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3453 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3455 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3457 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3459 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3460
3461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3462 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3464 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3466 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3468 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3469
3470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3471 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3473 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3475 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3476
3477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3478 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3480 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3482 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3483
3484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3485 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3487 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3489 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3490
3491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3492 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3494 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3496 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3497
3498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3499 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3501 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3503 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3504
3505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3506 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3508 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3510 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3511
3512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3513 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3515 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3517 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3518
3519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3520 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3522 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3524 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3525
3526 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
3527 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3529 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3531 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3532
3533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3534 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3536 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3538 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3539
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3541 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3543 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3545 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
3546
3547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3548 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3550 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3552 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3553
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3555 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3557 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3559 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3560
3561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3562 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3564 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3566 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3567
3568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3569 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3571 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3573 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3575 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3577 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3579 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3581 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3582
3583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3584 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3586 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3588 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3589
3590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3591 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3593 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3595 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3596
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3598 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
3599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3600 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3601
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3603 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3604
3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3606 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3608 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3609
3610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3611 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3613 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3615 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3617 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3619 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3621 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3623 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3625 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3627 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3629 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3631 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3633 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3635 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3637 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3639 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3641 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3643 0x092d0000, 0x0fff0000, "push%c\t%m"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3645 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3647 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3648
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3650 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3652 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3654 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3656 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3658 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3660 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3662 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3664 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3666 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3668 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3670 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3672 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3674 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3676 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3678 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3680 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3682 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3684 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3686 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3687
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3689 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3691 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
3692
3693 /* The rest. */
3694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3695 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3697 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3698 {ARM_FEATURE_CORE_LOW (0),
3699 0x00000000, 0x00000000, 0}
3700 };
3701
3702 /* print_insn_thumb16 recognizes the following format control codes:
3703
3704 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3705 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3706 %<bitfield>I print bitfield as a signed decimal
3707 (top bit of range being the sign bit)
3708 %N print Thumb register mask (with LR)
3709 %O print Thumb register mask (with PC)
3710 %M print Thumb register mask
3711 %b print CZB's 6-bit unsigned branch destination
3712 %s print Thumb right-shift immediate (6..10; 0 == 32).
3713 %c print the condition code
3714 %C print the condition code, or "s" if not conditional
3715 %x print warning if conditional an not at end of IT block"
3716 %X print "\t; unpredictable <IT:code>" if conditional
3717 %I print IT instruction suffix and operands
3718 %W print Thumb Writeback indicator for LDMIA
3719 %<bitfield>r print bitfield as an ARM register
3720 %<bitfield>d print bitfield as a decimal
3721 %<bitfield>H print (bitfield * 2) as a decimal
3722 %<bitfield>W print (bitfield * 4) as a decimal
3723 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3724 %<bitfield>B print Thumb branch destination (signed displacement)
3725 %<bitfield>c print bitfield as a condition code
3726 %<bitnum>'c print specified char iff bit is one
3727 %<bitnum>?ab print a if bit is one else print b. */
3728
3729 static const struct opcode16 thumb_opcodes[] =
3730 {
3731 /* Thumb instructions. */
3732
3733 /* ARMv8-M Security Extensions instructions. */
3734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
3735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
3736
3737 /* ARM V8 instructions. */
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
3740 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
3741
3742 /* ARM V6K no-argument instructions. */
3743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
3749
3750 /* ARM V6T2 instructions. */
3751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3752 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3753 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3754 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
3756
3757 /* ARM V6. */
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
3769
3770 /* ARM V5 ISA extends Thumb. */
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3772 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
3773 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3775 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
3776 /* ARM V4T ISA (Thumb v1). */
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3778 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
3779 /* Format 4. */
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
3796 /* format 13 */
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
3799 /* format 5 */
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
3804 /* format 14 */
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
3807 /* format 2 */
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3809 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3811 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3813 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3815 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
3816 /* format 8 */
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3818 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3820 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3822 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
3823 /* format 7 */
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3825 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3827 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3828 /* format 1 */
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3831 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
3834 /* format 3 */
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
3839 /* format 6 */
3840 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3842 0x4800, 0xF800,
3843 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
3844 /* format 9 */
3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3846 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3848 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3850 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3852 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
3853 /* format 10 */
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3855 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3857 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
3858 /* format 11 */
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3860 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3862 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
3863 /* format 12 */
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3865 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3867 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
3868 /* format 15 */
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
3871 /* format 17 */
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
3873 /* format 16 */
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
3877 /* format 18 */
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
3879
3880 /* The E800 .. FFFF range is unconditionally redirected to the
3881 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3882 are processed via that table. Thus, we can never encounter a
3883 bare "second half of BL/BLX(1)" instruction here. */
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
3885 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3886 };
3887
3888 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
3889 We adopt the convention that hw1 is the high 16 bits of .value and
3890 .mask, hw2 the low 16 bits.
3891
3892 print_insn_thumb32 recognizes the following format control codes:
3893
3894 %% %
3895
3896 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3897 %M print a modified 12-bit immediate (same location)
3898 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3899 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
3900 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
3901 %S print a possibly-shifted Rm
3902
3903 %L print address for a ldrd/strd instruction
3904 %a print the address of a plain load/store
3905 %w print the width and signedness of a core load/store
3906 %m print register mask for ldm/stm
3907 %n print register mask for clrm
3908
3909 %E print the lsb and width fields of a bfc/bfi instruction
3910 %F print the lsb and width fields of a sbfx/ubfx instruction
3911 %G print a fallback offset for Branch Future instructions
3912 %W print an offset for BF instruction
3913 %Y print an offset for BFL instruction
3914 %Z print an offset for BFCSEL instruction
3915 %Q print an offset for Low Overhead Loop instructions
3916 %P print an offset for Low Overhead Loop end instructions
3917 %b print a conditional branch offset
3918 %B print an unconditional branch offset
3919 %s print the shift field of an SSAT instruction
3920 %R print the rotation field of an SXT instruction
3921 %U print barrier type.
3922 %P print address for pli instruction.
3923 %c print the condition code
3924 %x print warning if conditional an not at end of IT block"
3925 %X print "\t; unpredictable <IT:code>" if conditional
3926
3927 %<bitfield>d print bitfield in decimal
3928 %<bitfield>D print bitfield plus one in decimal
3929 %<bitfield>W print bitfield*4 in decimal
3930 %<bitfield>r print bitfield as an ARM register
3931 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
3932 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
3933 %<bitfield>c print bitfield as a condition code
3934
3935 %<bitfield>'c print specified char iff bitfield is all ones
3936 %<bitfield>`c print specified char iff bitfield is all zeroes
3937 %<bitfield>?ab... select from array of values in big endian order
3938
3939 With one exception at the bottom (done because BL and BLX(1) need
3940 to come dead last), this table was machine-sorted first in
3941 decreasing order of number of bits set in the mask, then in
3942 increasing numeric order of mask, then in increasing numeric order
3943 of opcode. This order is not the clearest for a human reader, but
3944 is guaranteed never to catch a special-case bit pattern with a more
3945 general mask, which is important, because this instruction encoding
3946 makes heavy use of special-case bit patterns. */
3947 static const struct opcode32 thumb32_opcodes[] =
3948 {
3949 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3950 instructions. */
3951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3952 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3954 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3956 0xf02fc001, 0xfffff001, "le\t%P"},
3957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3958 0xf00fc001, 0xfffff001, "le\tlr, %P"},
3959
3960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3961 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
3962 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3963 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
3964 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3965 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
3966 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3967 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
3968 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3969 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
3970
3971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3972 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
3973
3974 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
3975 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
3976 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3977 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3979 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
3980 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3981 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3982 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3983 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
3984
3985 /* ARM V8.2 RAS extension instructions. */
3986 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3987 0xf3af8010, 0xffffffff, "esb"},
3988
3989 /* V8 instructions. */
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3991 0xf3af8005, 0xffffffff, "sevl%c.w"},
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3993 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3995 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3997 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3999 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4001 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4003 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4005 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4007 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4009 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4011 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4013 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4015 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4017 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4019 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4021 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4022
4023 /* CRC32 instructions. */
4024 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4025 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4026 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4027 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4028 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4029 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4030 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4031 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4032 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4033 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4034 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4035 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4036
4037 /* Speculation Barriers. */
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4041
4042 /* V7 instructions. */
4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4050 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4051 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4053 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4054
4055 /* Virtualization Extension instructions. */
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4057 /* We skip ERET as that is SUBS pc, lr, #0. */
4058
4059 /* MP Extension instructions. */
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4061
4062 /* Security extension instructions. */
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4064
4065 /* ARMv8.5-A instructions. */
4066 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4067
4068 /* Instructions defined in the basic V6T2 set. */
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4075 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4077
4078 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4079 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4081 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4083 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4085 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4087 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4089 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4091 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4093 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4095 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4097 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4099 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4101 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4103 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4105 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4106 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4107 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4108 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4109 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4111 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4113 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4115 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4117 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4119 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4121 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4123 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4125 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4126 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4127 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4129 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4131 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4133 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4135 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4137 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4139 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4141 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4143 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4145 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4147 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4149 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4151 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4153 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4155 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4157 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4159 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4161 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4163 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4165 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4167 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4169 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4171 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4173 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4175 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4177 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4179 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4181 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4183 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4185 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4187 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4189 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4191 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4193 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4195 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4197 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4199 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4201 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4203 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4205 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4207 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4209 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4211 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4213 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4215 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4217 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4219 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4221 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4223 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4225 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4227 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4229 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4231 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4233 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4234 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4235 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4237 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4239 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4241 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4243 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4245 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4247 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4249 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4251 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4253 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4255 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4257 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4259 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4261 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4263 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4265 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4267 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4269 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4271 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4273 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4275 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4277 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4279 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4281 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4283 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4285 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4287 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4289 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4291 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4293 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4295 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4297 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4299 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4301 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4302 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4303 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4305 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4307 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4309 0xf810f000, 0xff70f000, "pld%c\t%a"},
4310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4311 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4313 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4315 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4317 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4319 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4321 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4323 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4325 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4327 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4329 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4331 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4333 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4335 0xfb100000, 0xfff000c0,
4336 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4338 0xfbc00080, 0xfff000c0,
4339 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4341 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4343 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4345 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4347 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4349 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4350 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4351 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4353 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4355 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4357 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4359 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4361 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4363 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4365 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4367 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4369 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4371 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4373 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4375 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4376 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4377 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4379 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4381 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4383 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4385 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4387 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4389 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4391 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4393 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4395 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4397 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4399 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4401 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4403 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4405 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4407 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4409 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4411 0xe9400000, 0xff500000,
4412 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4414 0xe9500000, 0xff500000,
4415 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4417 0xe8600000, 0xff700000,
4418 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4420 0xe8700000, 0xff700000,
4421 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4423 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4425 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
4426
4427 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
4428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4429 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4431 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4433 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4435 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
4436
4437 /* These have been 32-bit since the invention of Thumb. */
4438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4439 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4441 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
4442
4443 /* Fallback. */
4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4445 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4446 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4447 };
4448
4449 static const char *const arm_conditional[] =
4450 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
4451 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
4452
4453 static const char *const arm_fp_const[] =
4454 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4455
4456 static const char *const arm_shift[] =
4457 {"lsl", "lsr", "asr", "ror"};
4458
4459 typedef struct
4460 {
4461 const char *name;
4462 const char *description;
4463 const char *reg_names[16];
4464 }
4465 arm_regname;
4466
4467 static const arm_regname regnames[] =
4468 {
4469 { "reg-names-raw", N_("Select raw register names"),
4470 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
4471 { "reg-names-gcc", N_("Select register names used by GCC"),
4472 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
4473 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
4474 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
4475 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4476 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4477 { "reg-names-apcs", N_("Select register names used in the APCS"),
4478 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
4479 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
4480 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
4481 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4482 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
4483 };
4484
4485 static const char *const iwmmxt_wwnames[] =
4486 {"b", "h", "w", "d"};
4487
4488 static const char *const iwmmxt_wwssnames[] =
4489 {"b", "bus", "bc", "bss",
4490 "h", "hus", "hc", "hss",
4491 "w", "wus", "wc", "wss",
4492 "d", "dus", "dc", "dss"
4493 };
4494
4495 static const char *const iwmmxt_regnames[] =
4496 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4497 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4498 };
4499
4500 static const char *const iwmmxt_cregnames[] =
4501 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4502 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4503 };
4504
4505 static const char *const vec_condnames[] =
4506 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4507 };
4508
4509 static const char *const mve_predicatenames[] =
4510 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4511 "eee", "ee", "eet", "e", "ett", "et", "ete"
4512 };
4513
4514 /* Names for 2-bit size field for mve vector isntructions. */
4515 static const char *const mve_vec_sizename[] =
4516 { "8", "16", "32", "64"};
4517
4518 /* Indicates whether we are processing a then predicate,
4519 else predicate or none at all. */
4520 enum vpt_pred_state
4521 {
4522 PRED_NONE,
4523 PRED_THEN,
4524 PRED_ELSE
4525 };
4526
4527 /* Information used to process a vpt block and subsequent instructions. */
4528 struct vpt_block
4529 {
4530 /* Are we in a vpt block. */
4531 bfd_boolean in_vpt_block;
4532
4533 /* Next predicate state if in vpt block. */
4534 enum vpt_pred_state next_pred_state;
4535
4536 /* Mask from vpt/vpst instruction. */
4537 long predicate_mask;
4538
4539 /* Instruction number in vpt block. */
4540 long current_insn_num;
4541
4542 /* Number of instructions in vpt block.. */
4543 long num_pred_insn;
4544 };
4545
4546 static struct vpt_block vpt_block_state =
4547 {
4548 FALSE,
4549 PRED_NONE,
4550 0,
4551 0,
4552 0
4553 };
4554
4555 /* Default to GCC register name set. */
4556 static unsigned int regname_selected = 1;
4557
4558 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
4559 #define arm_regnames regnames[regname_selected].reg_names
4560
4561 static bfd_boolean force_thumb = FALSE;
4562
4563 /* Current IT instruction state. This contains the same state as the IT
4564 bits in the CPSR. */
4565 static unsigned int ifthen_state;
4566 /* IT state for the next instruction. */
4567 static unsigned int ifthen_next_state;
4568 /* The address of the insn for which the IT state is valid. */
4569 static bfd_vma ifthen_address;
4570 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
4571 /* Indicates that the current Conditional state is unconditional or outside
4572 an IT block. */
4573 #define COND_UNCOND 16
4574
4575 \f
4576 /* Functions. */
4577 /* Extract the predicate mask for a VPT or VPST instruction.
4578 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4579
4580 static long
4581 mve_extract_pred_mask (long given)
4582 {
4583 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
4584 }
4585
4586 /* Return the number of instructions in a MVE predicate block. */
4587 static long
4588 num_instructions_vpt_block (long given)
4589 {
4590 long mask = mve_extract_pred_mask (given);
4591 if (mask == 0)
4592 return 0;
4593
4594 if (mask == 8)
4595 return 1;
4596
4597 if ((mask & 7) == 4)
4598 return 2;
4599
4600 if ((mask & 3) == 2)
4601 return 3;
4602
4603 if ((mask & 1) == 1)
4604 return 4;
4605
4606 return 0;
4607 }
4608
4609 static void
4610 mark_outside_vpt_block (void)
4611 {
4612 vpt_block_state.in_vpt_block = FALSE;
4613 vpt_block_state.next_pred_state = PRED_NONE;
4614 vpt_block_state.predicate_mask = 0;
4615 vpt_block_state.current_insn_num = 0;
4616 vpt_block_state.num_pred_insn = 0;
4617 }
4618
4619 static void
4620 mark_inside_vpt_block (long given)
4621 {
4622 vpt_block_state.in_vpt_block = TRUE;
4623 vpt_block_state.next_pred_state = PRED_THEN;
4624 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
4625 vpt_block_state.current_insn_num = 0;
4626 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
4627 assert (vpt_block_state.num_pred_insn >= 1);
4628 }
4629
4630 static enum vpt_pred_state
4631 invert_next_predicate_state (enum vpt_pred_state astate)
4632 {
4633 if (astate == PRED_THEN)
4634 return PRED_ELSE;
4635 else if (astate == PRED_ELSE)
4636 return PRED_THEN;
4637 else
4638 return PRED_NONE;
4639 }
4640
4641 static enum vpt_pred_state
4642 update_next_predicate_state (void)
4643 {
4644 long pred_mask = vpt_block_state.predicate_mask;
4645 long mask_for_insn = 0;
4646
4647 switch (vpt_block_state.current_insn_num)
4648 {
4649 case 1:
4650 mask_for_insn = 8;
4651 break;
4652
4653 case 2:
4654 mask_for_insn = 4;
4655 break;
4656
4657 case 3:
4658 mask_for_insn = 2;
4659 break;
4660
4661 case 4:
4662 return PRED_NONE;
4663 }
4664
4665 if (pred_mask & mask_for_insn)
4666 return invert_next_predicate_state (vpt_block_state.next_pred_state);
4667 else
4668 return vpt_block_state.next_pred_state;
4669 }
4670
4671 static void
4672 update_vpt_block_state (void)
4673 {
4674 vpt_block_state.current_insn_num++;
4675 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
4676 {
4677 /* No more instructions to process in vpt block. */
4678 mark_outside_vpt_block ();
4679 return;
4680 }
4681
4682 vpt_block_state.next_pred_state = update_next_predicate_state ();
4683 }
4684
4685 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4686 Returns pointer to following character of the format string and
4687 fills in *VALUEP and *WIDTHP with the extracted value and number of
4688 bits extracted. WIDTHP can be NULL. */
4689
4690 static const char *
4691 arm_decode_bitfield (const char *ptr,
4692 unsigned long insn,
4693 unsigned long *valuep,
4694 int *widthp)
4695 {
4696 unsigned long value = 0;
4697 int width = 0;
4698
4699 do
4700 {
4701 int start, end;
4702 int bits;
4703
4704 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
4705 start = start * 10 + *ptr - '0';
4706 if (*ptr == '-')
4707 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
4708 end = end * 10 + *ptr - '0';
4709 else
4710 end = start;
4711 bits = end - start;
4712 if (bits < 0)
4713 abort ();
4714 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
4715 width += bits + 1;
4716 }
4717 while (*ptr++ == ',');
4718 *valuep = value;
4719 if (widthp)
4720 *widthp = width;
4721 return ptr - 1;
4722 }
4723
4724 static void
4725 arm_decode_shift (long given, fprintf_ftype func, void *stream,
4726 bfd_boolean print_shift)
4727 {
4728 func (stream, "%s", arm_regnames[given & 0xf]);
4729
4730 if ((given & 0xff0) != 0)
4731 {
4732 if ((given & 0x10) == 0)
4733 {
4734 int amount = (given & 0xf80) >> 7;
4735 int shift = (given & 0x60) >> 5;
4736
4737 if (amount == 0)
4738 {
4739 if (shift == 3)
4740 {
4741 func (stream, ", rrx");
4742 return;
4743 }
4744
4745 amount = 32;
4746 }
4747
4748 if (print_shift)
4749 func (stream, ", %s #%d", arm_shift[shift], amount);
4750 else
4751 func (stream, ", #%d", amount);
4752 }
4753 else if ((given & 0x80) == 0x80)
4754 func (stream, "\t; <illegal shifter operand>");
4755 else if (print_shift)
4756 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
4757 arm_regnames[(given & 0xf00) >> 8]);
4758 else
4759 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
4760 }
4761 }
4762
4763 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4764
4765 static bfd_boolean
4766 is_mve_okay_in_it (enum mve_instructions matched_insn)
4767 {
4768 switch (matched_insn)
4769 {
4770 case MVE_VMOV_GP_TO_VEC_LANE:
4771 case MVE_VMOV2_VEC_LANE_TO_GP:
4772 case MVE_VMOV2_GP_TO_VEC_LANE:
4773 case MVE_VMOV_VEC_LANE_TO_GP:
4774 return TRUE;
4775 default:
4776 return FALSE;
4777 }
4778 }
4779
4780 static bfd_boolean
4781 is_mve_architecture (struct disassemble_info *info)
4782 {
4783 struct arm_private_data *private_data = info->private_data;
4784 arm_feature_set allowed_arches = private_data->features;
4785
4786 arm_feature_set arm_ext_v8_1m_main
4787 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
4788
4789 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4790 && !ARM_CPU_IS_ANY (allowed_arches))
4791 return TRUE;
4792 else
4793 return FALSE;
4794 }
4795
4796 static bfd_boolean
4797 is_vpt_instruction (long given)
4798 {
4799
4800 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4801 if ((given & 0x0040e000) == 0)
4802 return FALSE;
4803
4804 /* VPT floating point T1 variant. */
4805 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
4806 /* VPT floating point T2 variant. */
4807 || ((given & 0xefb10f50) == 0xee310f40)
4808 /* VPT vector T1 variant. */
4809 || ((given & 0xff811f51) == 0xfe010f00)
4810 /* VPT vector T2 variant. */
4811 || ((given & 0xff811f51) == 0xfe010f01
4812 && ((given & 0x300000) != 0x300000))
4813 /* VPT vector T3 variant. */
4814 || ((given & 0xff811f50) == 0xfe011f00)
4815 /* VPT vector T4 variant. */
4816 || ((given & 0xff811f70) == 0xfe010f40)
4817 /* VPT vector T5 variant. */
4818 || ((given & 0xff811f70) == 0xfe010f60)
4819 /* VPT vector T6 variant. */
4820 || ((given & 0xff811f50) == 0xfe011f40)
4821 /* VPST vector T variant. */
4822 || ((given & 0xffbf1fff) == 0xfe310f4d))
4823 return TRUE;
4824 else
4825 return FALSE;
4826 }
4827
4828 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4829 and ending bitfield = END. END must be greater than START. */
4830
4831 static unsigned long
4832 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
4833 {
4834 int bits = end - start;
4835
4836 if (bits < 0)
4837 abort ();
4838
4839 return ((given >> start) & ((2ul << bits) - 1));
4840 }
4841
4842 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4843 START:END and START2:END2. END/END2 must be greater than
4844 START/START2. */
4845
4846 static unsigned long
4847 arm_decode_field_multiple (unsigned long given, unsigned int start,
4848 unsigned int end, unsigned int start2,
4849 unsigned int end2)
4850 {
4851 int bits = end - start;
4852 int bits2 = end2 - start2;
4853 unsigned long value = 0;
4854 int width = 0;
4855
4856 if (bits2 < 0)
4857 abort ();
4858
4859 value = arm_decode_field (given, start, end);
4860 width += bits + 1;
4861
4862 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
4863 return value;
4864 }
4865
4866 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4867 This helps us decode instructions that change mnemonic depending on specific
4868 operand values/encodings. */
4869
4870 static bfd_boolean
4871 is_mve_encoding_conflict (unsigned long given,
4872 enum mve_instructions matched_insn)
4873 {
4874 switch (matched_insn)
4875 {
4876 case MVE_VPST:
4877 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4878 return TRUE;
4879 else
4880 return FALSE;
4881
4882 case MVE_VPT_FP_T1:
4883 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4884 return TRUE;
4885 if ((arm_decode_field (given, 12, 12) == 0)
4886 && (arm_decode_field (given, 0, 0) == 1))
4887 return TRUE;
4888 return FALSE;
4889
4890 case MVE_VPT_FP_T2:
4891 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4892 return TRUE;
4893 if (arm_decode_field (given, 0, 3) == 0xd)
4894 return TRUE;
4895 return FALSE;
4896
4897 case MVE_VPT_VEC_T1:
4898 case MVE_VPT_VEC_T2:
4899 case MVE_VPT_VEC_T3:
4900 case MVE_VPT_VEC_T4:
4901 case MVE_VPT_VEC_T5:
4902 case MVE_VPT_VEC_T6:
4903 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4904 return TRUE;
4905 if (arm_decode_field (given, 20, 21) == 3)
4906 return TRUE;
4907 return FALSE;
4908
4909 case MVE_VCMP_FP_T1:
4910 if ((arm_decode_field (given, 12, 12) == 0)
4911 && (arm_decode_field (given, 0, 0) == 1))
4912 return TRUE;
4913 else
4914 return FALSE;
4915
4916 case MVE_VCMP_FP_T2:
4917 if (arm_decode_field (given, 0, 3) == 0xd)
4918 return TRUE;
4919 else
4920 return FALSE;
4921
4922 case MVE_VQRSHL_T1:
4923 case MVE_VQSHL_T4:
4924 case MVE_VRSHL_T1:
4925 case MVE_VSHL_T3:
4926 case MVE_VCADD_VEC:
4927 case MVE_VHCADD:
4928 case MVE_VDDUP:
4929 case MVE_VIDUP:
4930 case MVE_VQRDMLADH:
4931 case MVE_VQDMLAH:
4932 case MVE_VQRDMLAH:
4933 case MVE_VQDMLASH:
4934 case MVE_VQRDMLASH:
4935 case MVE_VQDMLSDH:
4936 case MVE_VQRDMLSDH:
4937 case MVE_VQDMULH_T3:
4938 case MVE_VQRDMULH_T4:
4939 case MVE_VQDMLADH:
4940 case MVE_VMLAS:
4941 case MVE_VMULL_INT:
4942 case MVE_VHADD_T2:
4943 case MVE_VHSUB_T2:
4944 case MVE_VCMP_VEC_T1:
4945 case MVE_VCMP_VEC_T2:
4946 case MVE_VCMP_VEC_T3:
4947 case MVE_VCMP_VEC_T4:
4948 case MVE_VCMP_VEC_T5:
4949 case MVE_VCMP_VEC_T6:
4950 if (arm_decode_field (given, 20, 21) == 3)
4951 return TRUE;
4952 else
4953 return FALSE;
4954
4955 case MVE_VLD2:
4956 case MVE_VLD4:
4957 case MVE_VST2:
4958 case MVE_VST4:
4959 if (arm_decode_field (given, 7, 8) == 3)
4960 return TRUE;
4961 else
4962 return FALSE;
4963
4964 case MVE_VSTRB_T1:
4965 case MVE_VSTRH_T2:
4966 if ((arm_decode_field (given, 24, 24) == 0)
4967 && (arm_decode_field (given, 21, 21) == 0))
4968 {
4969 return TRUE;
4970 }
4971 else if ((arm_decode_field (given, 7, 8) == 3))
4972 return TRUE;
4973 else
4974 return FALSE;
4975
4976 case MVE_VSTRB_T5:
4977 case MVE_VSTRH_T6:
4978 case MVE_VSTRW_T7:
4979 if ((arm_decode_field (given, 24, 24) == 0)
4980 && (arm_decode_field (given, 21, 21) == 0))
4981 {
4982 return TRUE;
4983 }
4984 else
4985 return FALSE;
4986
4987 case MVE_VCVT_FP_FIX_VEC:
4988 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
4989
4990 case MVE_VBIC_IMM:
4991 case MVE_VORR_IMM:
4992 {
4993 unsigned long cmode = arm_decode_field (given, 8, 11);
4994
4995 if ((cmode & 1) == 0)
4996 return TRUE;
4997 else if ((cmode & 0xc) == 0xc)
4998 return TRUE;
4999 else
5000 return FALSE;
5001 }
5002
5003 case MVE_VMVN_IMM:
5004 {
5005 unsigned long cmode = arm_decode_field (given, 8, 11);
5006
5007 if ((cmode & 9) == 1)
5008 return TRUE;
5009 else if ((cmode & 5) == 1)
5010 return TRUE;
5011 else if ((cmode & 0xe) == 0xe)
5012 return TRUE;
5013 else
5014 return FALSE;
5015 }
5016
5017 case MVE_VMOV_IMM_TO_VEC:
5018 if ((arm_decode_field (given, 5, 5) == 1)
5019 && (arm_decode_field (given, 8, 11) != 0xe))
5020 return TRUE;
5021 else
5022 return FALSE;
5023
5024 case MVE_VMOVL:
5025 {
5026 unsigned long size = arm_decode_field (given, 19, 20);
5027 if ((size == 0) || (size == 3))
5028 return TRUE;
5029 else
5030 return FALSE;
5031 }
5032
5033 case MVE_VQRSHL_T2:
5034 case MVE_VQSHL_T1:
5035 case MVE_VRSHL_T2:
5036 case MVE_VSHL_T2:
5037 case MVE_VSHLL_T2:
5038 case MVE_VADDV:
5039 case MVE_VMOVN:
5040 case MVE_VQMOVUN:
5041 case MVE_VQMOVN:
5042 if (arm_decode_field (given, 18, 19) == 3)
5043 return TRUE;
5044 else
5045 return FALSE;
5046
5047 case MVE_VMLSLDAV:
5048 case MVE_VRMLSLDAVH:
5049 case MVE_VMLALDAV:
5050 case MVE_VADDLV:
5051 if (arm_decode_field (given, 20, 22) == 7)
5052 return TRUE;
5053 else
5054 return FALSE;
5055
5056 case MVE_VRMLALDAVH:
5057 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5058 return TRUE;
5059 else
5060 return FALSE;
5061
5062 case MVE_VDWDUP:
5063 case MVE_VIWDUP:
5064 if ((arm_decode_field (given, 20, 21) == 3)
5065 || (arm_decode_field (given, 1, 3) == 7))
5066 return TRUE;
5067 else
5068 return FALSE;
5069
5070
5071 case MVE_VSHLL_T1:
5072 if (arm_decode_field (given, 16, 18) == 0)
5073 {
5074 unsigned long sz = arm_decode_field (given, 19, 20);
5075
5076 if ((sz == 1) || (sz == 2))
5077 return TRUE;
5078 else
5079 return FALSE;
5080 }
5081 else
5082 return FALSE;
5083
5084 case MVE_VQSHL_T2:
5085 case MVE_VQSHLU_T3:
5086 case MVE_VRSHR:
5087 case MVE_VSHL_T1:
5088 case MVE_VSHR:
5089 case MVE_VSLI:
5090 case MVE_VSRI:
5091 if (arm_decode_field (given, 19, 21) == 0)
5092 return TRUE;
5093 else
5094 return FALSE;
5095
5096 default:
5097 return FALSE;
5098
5099 }
5100 }
5101
5102 static void
5103 print_mve_vld_str_addr (struct disassemble_info *info,
5104 unsigned long given,
5105 enum mve_instructions matched_insn)
5106 {
5107 void *stream = info->stream;
5108 fprintf_ftype func = info->fprintf_func;
5109
5110 unsigned long p, w, gpr, imm, add, mod_imm;
5111
5112 imm = arm_decode_field (given, 0, 6);
5113 mod_imm = imm;
5114
5115 switch (matched_insn)
5116 {
5117 case MVE_VLDRB_T1:
5118 case MVE_VSTRB_T1:
5119 gpr = arm_decode_field (given, 16, 18);
5120 break;
5121
5122 case MVE_VLDRH_T2:
5123 case MVE_VSTRH_T2:
5124 gpr = arm_decode_field (given, 16, 18);
5125 mod_imm = imm << 1;
5126 break;
5127
5128 case MVE_VLDRH_T6:
5129 case MVE_VSTRH_T6:
5130 gpr = arm_decode_field (given, 16, 19);
5131 mod_imm = imm << 1;
5132 break;
5133
5134 case MVE_VLDRW_T7:
5135 case MVE_VSTRW_T7:
5136 gpr = arm_decode_field (given, 16, 19);
5137 mod_imm = imm << 2;
5138 break;
5139
5140 case MVE_VLDRB_T5:
5141 case MVE_VSTRB_T5:
5142 gpr = arm_decode_field (given, 16, 19);
5143 break;
5144
5145 default:
5146 return;
5147 }
5148
5149 p = arm_decode_field (given, 24, 24);
5150 w = arm_decode_field (given, 21, 21);
5151
5152 add = arm_decode_field (given, 23, 23);
5153
5154 char * add_sub;
5155
5156 /* Don't print anything for '+' as it is implied. */
5157 if (add == 1)
5158 add_sub = "";
5159 else
5160 add_sub = "-";
5161
5162 if (p == 1)
5163 {
5164 /* Offset mode. */
5165 if (w == 0)
5166 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5167 /* Pre-indexed mode. */
5168 else
5169 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5170 }
5171 else if ((p == 0) && (w == 1))
5172 /* Post-index mode. */
5173 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5174 }
5175
5176 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5177 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5178 this encoding is undefined. */
5179
5180 static bfd_boolean
5181 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5182 enum mve_undefined *undefined_code)
5183 {
5184 *undefined_code = UNDEF_NONE;
5185
5186 switch (matched_insn)
5187 {
5188 case MVE_VDUP:
5189 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5190 {
5191 *undefined_code = UNDEF_SIZE_3;
5192 return TRUE;
5193 }
5194 else
5195 return FALSE;
5196
5197 case MVE_VQDMULH_T1:
5198 case MVE_VQRDMULH_T2:
5199 case MVE_VRHADD:
5200 case MVE_VHADD_T1:
5201 case MVE_VHSUB_T1:
5202 if (arm_decode_field (given, 20, 21) == 3)
5203 {
5204 *undefined_code = UNDEF_SIZE_3;
5205 return TRUE;
5206 }
5207 else
5208 return FALSE;
5209
5210 case MVE_VLDRB_T1:
5211 if (arm_decode_field (given, 7, 8) == 3)
5212 {
5213 *undefined_code = UNDEF_SIZE_3;
5214 return TRUE;
5215 }
5216 else
5217 return FALSE;
5218
5219 case MVE_VLDRH_T2:
5220 if (arm_decode_field (given, 7, 8) <= 1)
5221 {
5222 *undefined_code = UNDEF_SIZE_LE_1;
5223 return TRUE;
5224 }
5225 else
5226 return FALSE;
5227
5228 case MVE_VSTRB_T1:
5229 if ((arm_decode_field (given, 7, 8) == 0))
5230 {
5231 *undefined_code = UNDEF_SIZE_0;
5232 return TRUE;
5233 }
5234 else
5235 return FALSE;
5236
5237 case MVE_VSTRH_T2:
5238 if ((arm_decode_field (given, 7, 8) <= 1))
5239 {
5240 *undefined_code = UNDEF_SIZE_LE_1;
5241 return TRUE;
5242 }
5243 else
5244 return FALSE;
5245
5246 case MVE_VLDRB_GATHER_T1:
5247 if (arm_decode_field (given, 7, 8) == 3)
5248 {
5249 *undefined_code = UNDEF_SIZE_3;
5250 return TRUE;
5251 }
5252 else if ((arm_decode_field (given, 28, 28) == 0)
5253 && (arm_decode_field (given, 7, 8) == 0))
5254 {
5255 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5256 return TRUE;
5257 }
5258 else
5259 return FALSE;
5260
5261 case MVE_VLDRH_GATHER_T2:
5262 if (arm_decode_field (given, 7, 8) == 3)
5263 {
5264 *undefined_code = UNDEF_SIZE_3;
5265 return TRUE;
5266 }
5267 else if ((arm_decode_field (given, 28, 28) == 0)
5268 && (arm_decode_field (given, 7, 8) == 1))
5269 {
5270 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5271 return TRUE;
5272 }
5273 else if (arm_decode_field (given, 7, 8) == 0)
5274 {
5275 *undefined_code = UNDEF_SIZE_0;
5276 return TRUE;
5277 }
5278 else
5279 return FALSE;
5280
5281 case MVE_VLDRW_GATHER_T3:
5282 if (arm_decode_field (given, 7, 8) != 2)
5283 {
5284 *undefined_code = UNDEF_SIZE_NOT_2;
5285 return TRUE;
5286 }
5287 else if (arm_decode_field (given, 28, 28) == 0)
5288 {
5289 *undefined_code = UNDEF_NOT_UNSIGNED;
5290 return TRUE;
5291 }
5292 else
5293 return FALSE;
5294
5295 case MVE_VLDRD_GATHER_T4:
5296 if (arm_decode_field (given, 7, 8) != 3)
5297 {
5298 *undefined_code = UNDEF_SIZE_NOT_3;
5299 return TRUE;
5300 }
5301 else if (arm_decode_field (given, 28, 28) == 0)
5302 {
5303 *undefined_code = UNDEF_NOT_UNSIGNED;
5304 return TRUE;
5305 }
5306 else
5307 return FALSE;
5308
5309 case MVE_VSTRB_SCATTER_T1:
5310 if (arm_decode_field (given, 7, 8) == 3)
5311 {
5312 *undefined_code = UNDEF_SIZE_3;
5313 return TRUE;
5314 }
5315 else
5316 return FALSE;
5317
5318 case MVE_VSTRH_SCATTER_T2:
5319 {
5320 unsigned long size = arm_decode_field (given, 7, 8);
5321 if (size == 3)
5322 {
5323 *undefined_code = UNDEF_SIZE_3;
5324 return TRUE;
5325 }
5326 else if (size == 0)
5327 {
5328 *undefined_code = UNDEF_SIZE_0;
5329 return TRUE;
5330 }
5331 else
5332 return FALSE;
5333 }
5334
5335 case MVE_VSTRW_SCATTER_T3:
5336 if (arm_decode_field (given, 7, 8) != 2)
5337 {
5338 *undefined_code = UNDEF_SIZE_NOT_2;
5339 return TRUE;
5340 }
5341 else
5342 return FALSE;
5343
5344 case MVE_VSTRD_SCATTER_T4:
5345 if (arm_decode_field (given, 7, 8) != 3)
5346 {
5347 *undefined_code = UNDEF_SIZE_NOT_3;
5348 return TRUE;
5349 }
5350 else
5351 return FALSE;
5352
5353 case MVE_VCVT_FP_FIX_VEC:
5354 {
5355 unsigned long imm6 = arm_decode_field (given, 16, 21);
5356 if ((imm6 & 0x20) == 0)
5357 {
5358 *undefined_code = UNDEF_VCVT_IMM6;
5359 return TRUE;
5360 }
5361
5362 if ((arm_decode_field (given, 9, 9) == 0)
5363 && ((imm6 & 0x30) == 0x20))
5364 {
5365 *undefined_code = UNDEF_VCVT_FSI_IMM6;
5366 return TRUE;
5367 }
5368
5369 return FALSE;
5370 }
5371
5372 case MVE_VCVT_BETWEEN_FP_INT:
5373 case MVE_VCVT_FROM_FP_TO_INT:
5374 {
5375 unsigned long size = arm_decode_field (given, 18, 19);
5376 if (size == 0)
5377 {
5378 *undefined_code = UNDEF_SIZE_0;
5379 return TRUE;
5380 }
5381 else if (size == 3)
5382 {
5383 *undefined_code = UNDEF_SIZE_3;
5384 return TRUE;
5385 }
5386 else
5387 return FALSE;
5388 }
5389
5390 case MVE_VMOV_VEC_LANE_TO_GP:
5391 {
5392 unsigned long op1 = arm_decode_field (given, 21, 22);
5393 unsigned long op2 = arm_decode_field (given, 5, 6);
5394 unsigned long u = arm_decode_field (given, 23, 23);
5395
5396 if ((op2 == 0) && (u == 1))
5397 {
5398 if ((op1 == 0) || (op1 == 1))
5399 {
5400 *undefined_code = UNDEF_BAD_U_OP1_OP2;
5401 return TRUE;
5402 }
5403 else
5404 return FALSE;
5405 }
5406 else if (op2 == 2)
5407 {
5408 if ((op1 == 0) || (op1 == 1))
5409 {
5410 *undefined_code = UNDEF_BAD_OP1_OP2;
5411 return TRUE;
5412 }
5413 else
5414 return FALSE;
5415 }
5416
5417 return FALSE;
5418 }
5419
5420 case MVE_VMOV_GP_TO_VEC_LANE:
5421 if (arm_decode_field (given, 5, 6) == 2)
5422 {
5423 unsigned long op1 = arm_decode_field (given, 21, 22);
5424 if ((op1 == 0) || (op1 == 1))
5425 {
5426 *undefined_code = UNDEF_BAD_OP1_OP2;
5427 return TRUE;
5428 }
5429 else
5430 return FALSE;
5431 }
5432 else
5433 return FALSE;
5434
5435 case MVE_VMOV_IMM_TO_VEC:
5436 if (arm_decode_field (given, 5, 5) == 0)
5437 {
5438 unsigned long cmode = arm_decode_field (given, 8, 11);
5439
5440 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
5441 {
5442 *undefined_code = UNDEF_OP_0_BAD_CMODE;
5443 return TRUE;
5444 }
5445 else
5446 return FALSE;
5447 }
5448 else
5449 return FALSE;
5450
5451 case MVE_VSHLL_T2:
5452 case MVE_VMOVN:
5453 if (arm_decode_field (given, 18, 19) == 2)
5454 {
5455 *undefined_code = UNDEF_SIZE_2;
5456 return TRUE;
5457 }
5458 else
5459 return FALSE;
5460
5461 case MVE_VRMLALDAVH:
5462 case MVE_VMLADAV_T1:
5463 case MVE_VMLADAV_T2:
5464 case MVE_VMLALDAV:
5465 if ((arm_decode_field (given, 28, 28) == 1)
5466 && (arm_decode_field (given, 12, 12) == 1))
5467 {
5468 *undefined_code = UNDEF_XCHG_UNS;
5469 return TRUE;
5470 }
5471 else
5472 return FALSE;
5473
5474 case MVE_VQSHRN:
5475 case MVE_VQSHRUN:
5476 case MVE_VSHLL_T1:
5477 case MVE_VSHRN:
5478 {
5479 unsigned long sz = arm_decode_field (given, 19, 20);
5480 if (sz == 1)
5481 return FALSE;
5482 else if ((sz & 2) == 2)
5483 return FALSE;
5484 else
5485 {
5486 *undefined_code = UNDEF_SIZE;
5487 return TRUE;
5488 }
5489 }
5490 break;
5491
5492 case MVE_VQSHL_T2:
5493 case MVE_VQSHLU_T3:
5494 case MVE_VRSHR:
5495 case MVE_VSHL_T1:
5496 case MVE_VSHR:
5497 case MVE_VSLI:
5498 case MVE_VSRI:
5499 {
5500 unsigned long sz = arm_decode_field (given, 19, 21);
5501 if ((sz & 7) == 1)
5502 return FALSE;
5503 else if ((sz & 6) == 2)
5504 return FALSE;
5505 else if ((sz & 4) == 4)
5506 return FALSE;
5507 else
5508 {
5509 *undefined_code = UNDEF_SIZE;
5510 return TRUE;
5511 }
5512 }
5513
5514 case MVE_VQRSHRN:
5515 case MVE_VQRSHRUN:
5516 if (arm_decode_field (given, 19, 20) == 0)
5517 {
5518 *undefined_code = UNDEF_SIZE_0;
5519 return TRUE;
5520 }
5521 else
5522 return FALSE;
5523
5524 default:
5525 return FALSE;
5526 }
5527 }
5528
5529 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
5530 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
5531 why this encoding is unpredictable. */
5532
5533 static bfd_boolean
5534 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
5535 enum mve_unpredictable *unpredictable_code)
5536 {
5537 *unpredictable_code = UNPRED_NONE;
5538
5539 switch (matched_insn)
5540 {
5541 case MVE_VCMP_FP_T2:
5542 case MVE_VPT_FP_T2:
5543 if ((arm_decode_field (given, 12, 12) == 0)
5544 && (arm_decode_field (given, 5, 5) == 1))
5545 {
5546 *unpredictable_code = UNPRED_FCA_0_FCB_1;
5547 return TRUE;
5548 }
5549 else
5550 return FALSE;
5551
5552 case MVE_VPT_VEC_T4:
5553 case MVE_VPT_VEC_T5:
5554 case MVE_VPT_VEC_T6:
5555 case MVE_VCMP_VEC_T4:
5556 case MVE_VCMP_VEC_T5:
5557 case MVE_VCMP_VEC_T6:
5558 if (arm_decode_field (given, 0, 3) == 0xd)
5559 {
5560 *unpredictable_code = UNPRED_R13;
5561 return TRUE;
5562 }
5563 else
5564 return FALSE;
5565
5566 case MVE_VDUP:
5567 {
5568 unsigned long gpr = arm_decode_field (given, 12, 15);
5569 if (gpr == 0xd)
5570 {
5571 *unpredictable_code = UNPRED_R13;
5572 return TRUE;
5573 }
5574 else if (gpr == 0xf)
5575 {
5576 *unpredictable_code = UNPRED_R15;
5577 return TRUE;
5578 }
5579
5580 return FALSE;
5581 }
5582
5583 case MVE_VQRSHL_T2:
5584 case MVE_VQSHL_T1:
5585 case MVE_VRSHL_T2:
5586 case MVE_VSHL_T2:
5587 case MVE_VSHLC:
5588 case MVE_VQDMLAH:
5589 case MVE_VQRDMLAH:
5590 case MVE_VQDMLASH:
5591 case MVE_VQRDMLASH:
5592 case MVE_VQDMULH_T3:
5593 case MVE_VQRDMULH_T4:
5594 case MVE_VMLAS:
5595 case MVE_VFMA_FP_SCALAR:
5596 case MVE_VFMAS_FP_SCALAR:
5597 case MVE_VHADD_T2:
5598 case MVE_VHSUB_T2:
5599 {
5600 unsigned long gpr = arm_decode_field (given, 0, 3);
5601 if (gpr == 0xd)
5602 {
5603 *unpredictable_code = UNPRED_R13;
5604 return TRUE;
5605 }
5606 else if (gpr == 0xf)
5607 {
5608 *unpredictable_code = UNPRED_R15;
5609 return TRUE;
5610 }
5611
5612 return FALSE;
5613 }
5614
5615 case MVE_VLD2:
5616 case MVE_VST2:
5617 {
5618 unsigned long rn = arm_decode_field (given, 16, 19);
5619
5620 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5621 {
5622 *unpredictable_code = UNPRED_R13_AND_WB;
5623 return TRUE;
5624 }
5625
5626 if (rn == 0xf)
5627 {
5628 *unpredictable_code = UNPRED_R15;
5629 return TRUE;
5630 }
5631
5632 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
5633 {
5634 *unpredictable_code = UNPRED_Q_GT_6;
5635 return TRUE;
5636 }
5637 else
5638 return FALSE;
5639 }
5640
5641 case MVE_VLD4:
5642 case MVE_VST4:
5643 {
5644 unsigned long rn = arm_decode_field (given, 16, 19);
5645
5646 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5647 {
5648 *unpredictable_code = UNPRED_R13_AND_WB;
5649 return TRUE;
5650 }
5651
5652 if (rn == 0xf)
5653 {
5654 *unpredictable_code = UNPRED_R15;
5655 return TRUE;
5656 }
5657
5658 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
5659 {
5660 *unpredictable_code = UNPRED_Q_GT_4;
5661 return TRUE;
5662 }
5663 else
5664 return FALSE;
5665 }
5666
5667 case MVE_VLDRB_T5:
5668 case MVE_VLDRH_T6:
5669 case MVE_VLDRW_T7:
5670 case MVE_VSTRB_T5:
5671 case MVE_VSTRH_T6:
5672 case MVE_VSTRW_T7:
5673 {
5674 unsigned long rn = arm_decode_field (given, 16, 19);
5675
5676 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5677 {
5678 *unpredictable_code = UNPRED_R13_AND_WB;
5679 return TRUE;
5680 }
5681 else if (rn == 0xf)
5682 {
5683 *unpredictable_code = UNPRED_R15;
5684 return TRUE;
5685 }
5686 else
5687 return FALSE;
5688 }
5689
5690 case MVE_VLDRB_GATHER_T1:
5691 if (arm_decode_field (given, 0, 0) == 1)
5692 {
5693 *unpredictable_code = UNPRED_OS;
5694 return TRUE;
5695 }
5696
5697 /* fall through. */
5698 /* To handle common code with T2-T4 variants. */
5699 case MVE_VLDRH_GATHER_T2:
5700 case MVE_VLDRW_GATHER_T3:
5701 case MVE_VLDRD_GATHER_T4:
5702 {
5703 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5704 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5705
5706 if (qd == qm)
5707 {
5708 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5709 return TRUE;
5710 }
5711
5712 if (arm_decode_field (given, 16, 19) == 0xf)
5713 {
5714 *unpredictable_code = UNPRED_R15;
5715 return TRUE;
5716 }
5717
5718 return FALSE;
5719 }
5720
5721 case MVE_VLDRW_GATHER_T5:
5722 case MVE_VLDRD_GATHER_T6:
5723 {
5724 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5725 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
5726
5727 if (qd == qm)
5728 {
5729 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5730 return TRUE;
5731 }
5732 else
5733 return FALSE;
5734 }
5735
5736 case MVE_VSTRB_SCATTER_T1:
5737 if (arm_decode_field (given, 16, 19) == 0xf)
5738 {
5739 *unpredictable_code = UNPRED_R15;
5740 return TRUE;
5741 }
5742 else if (arm_decode_field (given, 0, 0) == 1)
5743 {
5744 *unpredictable_code = UNPRED_OS;
5745 return TRUE;
5746 }
5747 else
5748 return FALSE;
5749
5750 case MVE_VSTRH_SCATTER_T2:
5751 case MVE_VSTRW_SCATTER_T3:
5752 case MVE_VSTRD_SCATTER_T4:
5753 if (arm_decode_field (given, 16, 19) == 0xf)
5754 {
5755 *unpredictable_code = UNPRED_R15;
5756 return TRUE;
5757 }
5758 else
5759 return FALSE;
5760
5761 case MVE_VMOV2_VEC_LANE_TO_GP:
5762 case MVE_VMOV2_GP_TO_VEC_LANE:
5763 case MVE_VCVT_BETWEEN_FP_INT:
5764 case MVE_VCVT_FROM_FP_TO_INT:
5765 {
5766 unsigned long rt = arm_decode_field (given, 0, 3);
5767 unsigned long rt2 = arm_decode_field (given, 16, 19);
5768
5769 if ((rt == 0xd) || (rt2 == 0xd))
5770 {
5771 *unpredictable_code = UNPRED_R13;
5772 return TRUE;
5773 }
5774 else if ((rt == 0xf) || (rt2 == 0xf))
5775 {
5776 *unpredictable_code = UNPRED_R15;
5777 return TRUE;
5778 }
5779 else if (rt == rt2)
5780 {
5781 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
5782 return TRUE;
5783 }
5784
5785 return FALSE;
5786 }
5787
5788 case MVE_VMOV_HFP_TO_GP:
5789 case MVE_VMOV_GP_TO_VEC_LANE:
5790 case MVE_VMOV_VEC_LANE_TO_GP:
5791 {
5792 unsigned long rda = arm_decode_field (given, 12, 15);
5793 if (rda == 0xd)
5794 {
5795 *unpredictable_code = UNPRED_R13;
5796 return TRUE;
5797 }
5798 else if (rda == 0xf)
5799 {
5800 *unpredictable_code = UNPRED_R15;
5801 return TRUE;
5802 }
5803
5804 return FALSE;
5805 }
5806
5807 case MVE_VQRDMLADH:
5808 case MVE_VQDMLSDH:
5809 case MVE_VQRDMLSDH:
5810 case MVE_VQDMLADH:
5811 case MVE_VMULL_INT:
5812 {
5813 unsigned long Qd;
5814 unsigned long Qm;
5815 unsigned long Qn;
5816
5817 if (arm_decode_field (given, 20, 21) == 2)
5818 {
5819 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5820 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5821 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5822
5823 if ((Qd == Qn) || (Qd == Qm))
5824 {
5825 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
5826 return TRUE;
5827 }
5828 else
5829 return FALSE;
5830 }
5831 else
5832 return FALSE;
5833 }
5834
5835 case MVE_VCMUL_FP:
5836 case MVE_VQDMULL_T1:
5837 {
5838 unsigned long Qd;
5839 unsigned long Qm;
5840 unsigned long Qn;
5841
5842 if (arm_decode_field (given, 28, 28) == 1)
5843 {
5844 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5845 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5846 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5847
5848 if ((Qd == Qn) || (Qd == Qm))
5849 {
5850 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5851 return TRUE;
5852 }
5853 else
5854 return FALSE;
5855 }
5856 else
5857 return FALSE;
5858 }
5859
5860 case MVE_VQDMULL_T2:
5861 {
5862 unsigned long gpr = arm_decode_field (given, 0, 3);
5863 if (gpr == 0xd)
5864 {
5865 *unpredictable_code = UNPRED_R13;
5866 return TRUE;
5867 }
5868 else if (gpr == 0xf)
5869 {
5870 *unpredictable_code = UNPRED_R15;
5871 return TRUE;
5872 }
5873
5874 if (arm_decode_field (given, 28, 28) == 1)
5875 {
5876 unsigned long Qd
5877 = arm_decode_field_multiple (given, 13, 15, 22, 22);
5878 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5879
5880 if ((Qd == Qn))
5881 {
5882 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5883 return TRUE;
5884 }
5885 else
5886 return FALSE;
5887 }
5888
5889 return FALSE;
5890 }
5891
5892 case MVE_VMLSLDAV:
5893 case MVE_VRMLSLDAVH:
5894 case MVE_VMLALDAV:
5895 case MVE_VADDLV:
5896 if (arm_decode_field (given, 20, 22) == 6)
5897 {
5898 *unpredictable_code = UNPRED_R13;
5899 return TRUE;
5900 }
5901 else
5902 return FALSE;
5903
5904 case MVE_VDWDUP:
5905 case MVE_VIWDUP:
5906 if (arm_decode_field (given, 1, 3) == 6)
5907 {
5908 *unpredictable_code = UNPRED_R13;
5909 return TRUE;
5910 }
5911 else
5912 return FALSE;
5913
5914 case MVE_VCADD_VEC:
5915 case MVE_VHCADD:
5916 {
5917 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5918 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5919 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
5920 {
5921 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
5922 return TRUE;
5923 }
5924 else
5925 return FALSE;
5926 }
5927
5928 case MVE_VCADD_FP:
5929 {
5930 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5931 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5932 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
5933 {
5934 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5935 return TRUE;
5936 }
5937 else
5938 return FALSE;
5939 }
5940
5941 case MVE_VCMLA_FP:
5942 {
5943 unsigned long Qda;
5944 unsigned long Qm;
5945 unsigned long Qn;
5946
5947 if (arm_decode_field (given, 20, 20) == 1)
5948 {
5949 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
5950 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5951 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5952
5953 if ((Qda == Qn) || (Qda == Qm))
5954 {
5955 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5956 return TRUE;
5957 }
5958 else
5959 return FALSE;
5960 }
5961 else
5962 return FALSE;
5963
5964 }
5965
5966 default:
5967 return FALSE;
5968 }
5969 }
5970
5971 static void
5972 print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
5973 {
5974 unsigned long op1 = arm_decode_field (given, 21, 22);
5975 unsigned long op2 = arm_decode_field (given, 5, 6);
5976 unsigned long h = arm_decode_field (given, 16, 16);
5977 unsigned long index, esize, targetBeat, idx;
5978 void *stream = info->stream;
5979 fprintf_ftype func = info->fprintf_func;
5980
5981 if ((op1 & 0x2) == 0x2)
5982 {
5983 index = op2;
5984 esize = 8;
5985 }
5986 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
5987 {
5988 index = op2 >> 1;
5989 esize = 16;
5990 }
5991 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
5992 {
5993 index = 0;
5994 esize = 32;
5995 }
5996 else
5997 {
5998 func (stream, "<undefined index>");
5999 return;
6000 }
6001
6002 targetBeat = (op1 & 0x1) | (h << 1);
6003 idx = index + targetBeat * (32/esize);
6004
6005 func (stream, "%lu", idx);
6006 }
6007
6008 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6009 in length and integer of floating-point type. */
6010 static void
6011 print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6012 unsigned int ibit_loc, const struct mopcode32 *insn)
6013 {
6014 int bits = 0;
6015 int cmode = (given >> 8) & 0xf;
6016 int op = (given >> 5) & 0x1;
6017 unsigned long value = 0, hival = 0;
6018 unsigned shift;
6019 int size = 0;
6020 int isfloat = 0;
6021 void *stream = info->stream;
6022 fprintf_ftype func = info->fprintf_func;
6023
6024 /* On Neon the 'i' bit is at bit 24, on mve it is
6025 at bit 28. */
6026 bits |= ((given >> ibit_loc) & 1) << 7;
6027 bits |= ((given >> 16) & 7) << 4;
6028 bits |= ((given >> 0) & 15) << 0;
6029
6030 if (cmode < 8)
6031 {
6032 shift = (cmode >> 1) & 3;
6033 value = (unsigned long) bits << (8 * shift);
6034 size = 32;
6035 }
6036 else if (cmode < 12)
6037 {
6038 shift = (cmode >> 1) & 1;
6039 value = (unsigned long) bits << (8 * shift);
6040 size = 16;
6041 }
6042 else if (cmode < 14)
6043 {
6044 shift = (cmode & 1) + 1;
6045 value = (unsigned long) bits << (8 * shift);
6046 value |= (1ul << (8 * shift)) - 1;
6047 size = 32;
6048 }
6049 else if (cmode == 14)
6050 {
6051 if (op)
6052 {
6053 /* Bit replication into bytes. */
6054 int ix;
6055 unsigned long mask;
6056
6057 value = 0;
6058 hival = 0;
6059 for (ix = 7; ix >= 0; ix--)
6060 {
6061 mask = ((bits >> ix) & 1) ? 0xff : 0;
6062 if (ix <= 3)
6063 value = (value << 8) | mask;
6064 else
6065 hival = (hival << 8) | mask;
6066 }
6067 size = 64;
6068 }
6069 else
6070 {
6071 /* Byte replication. */
6072 value = (unsigned long) bits;
6073 size = 8;
6074 }
6075 }
6076 else if (!op)
6077 {
6078 /* Floating point encoding. */
6079 int tmp;
6080
6081 value = (unsigned long) (bits & 0x7f) << 19;
6082 value |= (unsigned long) (bits & 0x80) << 24;
6083 tmp = bits & 0x40 ? 0x3c : 0x40;
6084 value |= (unsigned long) tmp << 24;
6085 size = 32;
6086 isfloat = 1;
6087 }
6088 else
6089 {
6090 func (stream, "<illegal constant %.8x:%x:%x>",
6091 bits, cmode, op);
6092 size = 32;
6093 return;
6094 }
6095
6096 // printU determines whether the immediate value should be printed as
6097 // unsigned.
6098 unsigned printU = 0;
6099 switch (insn->mve_op)
6100 {
6101 default:
6102 break;
6103 // We want this for instructions that don't have a 'signed' type
6104 case MVE_VBIC_IMM:
6105 case MVE_VORR_IMM:
6106 case MVE_VMVN_IMM:
6107 case MVE_VMOV_IMM_TO_VEC:
6108 printU = 1;
6109 break;
6110 }
6111 switch (size)
6112 {
6113 case 8:
6114 func (stream, "#%ld\t; 0x%.2lx", value, value);
6115 break;
6116
6117 case 16:
6118 func (stream,
6119 printU
6120 ? "#%lu\t; 0x%.4lx"
6121 : "#%ld\t; 0x%.4lx", value, value);
6122 break;
6123
6124 case 32:
6125 if (isfloat)
6126 {
6127 unsigned char valbytes[4];
6128 double fvalue;
6129
6130 /* Do this a byte at a time so we don't have to
6131 worry about the host's endianness. */
6132 valbytes[0] = value & 0xff;
6133 valbytes[1] = (value >> 8) & 0xff;
6134 valbytes[2] = (value >> 16) & 0xff;
6135 valbytes[3] = (value >> 24) & 0xff;
6136
6137 floatformat_to_double
6138 (& floatformat_ieee_single_little, valbytes,
6139 & fvalue);
6140
6141 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6142 value);
6143 }
6144 else
6145 func (stream,
6146 printU
6147 ? "#%lu\t; 0x%.8lx"
6148 : "#%ld\t; 0x%.8lx",
6149 (long) (((value & 0x80000000L) != 0)
6150 && !printU
6151 ? value | ~0xffffffffL : value),
6152 value);
6153 break;
6154
6155 case 64:
6156 func (stream, "#0x%.8lx%.8lx", hival, value);
6157 break;
6158
6159 default:
6160 abort ();
6161 }
6162
6163 }
6164
6165 static void
6166 print_mve_undefined (struct disassemble_info *info,
6167 enum mve_undefined undefined_code)
6168 {
6169 void *stream = info->stream;
6170 fprintf_ftype func = info->fprintf_func;
6171
6172 func (stream, "\t\tundefined instruction: ");
6173
6174 switch (undefined_code)
6175 {
6176 case UNDEF_SIZE:
6177 func (stream, "illegal size");
6178 break;
6179
6180 case UNDEF_SIZE_0:
6181 func (stream, "size equals zero");
6182 break;
6183
6184 case UNDEF_SIZE_2:
6185 func (stream, "size equals two");
6186 break;
6187
6188 case UNDEF_SIZE_3:
6189 func (stream, "size equals three");
6190 break;
6191
6192 case UNDEF_SIZE_LE_1:
6193 func (stream, "size <= 1");
6194 break;
6195
6196 case UNDEF_SIZE_NOT_2:
6197 func (stream, "size not equal to 2");
6198 break;
6199
6200 case UNDEF_SIZE_NOT_3:
6201 func (stream, "size not equal to 3");
6202 break;
6203
6204 case UNDEF_NOT_UNS_SIZE_0:
6205 func (stream, "not unsigned and size = zero");
6206 break;
6207
6208 case UNDEF_NOT_UNS_SIZE_1:
6209 func (stream, "not unsigned and size = one");
6210 break;
6211
6212 case UNDEF_NOT_UNSIGNED:
6213 func (stream, "not unsigned");
6214 break;
6215
6216 case UNDEF_VCVT_IMM6:
6217 func (stream, "invalid imm6");
6218 break;
6219
6220 case UNDEF_VCVT_FSI_IMM6:
6221 func (stream, "fsi = 0 and invalid imm6");
6222 break;
6223
6224 case UNDEF_BAD_OP1_OP2:
6225 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
6226 break;
6227
6228 case UNDEF_BAD_U_OP1_OP2:
6229 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
6230 break;
6231
6232 case UNDEF_OP_0_BAD_CMODE:
6233 func (stream, "op field equal 0 and bad cmode");
6234 break;
6235
6236 case UNDEF_XCHG_UNS:
6237 func (stream, "exchange and unsigned together");
6238 break;
6239
6240 case UNDEF_NONE:
6241 break;
6242 }
6243
6244 }
6245
6246 static void
6247 print_mve_unpredictable (struct disassemble_info *info,
6248 enum mve_unpredictable unpredict_code)
6249 {
6250 void *stream = info->stream;
6251 fprintf_ftype func = info->fprintf_func;
6252
6253 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
6254
6255 switch (unpredict_code)
6256 {
6257 case UNPRED_IT_BLOCK:
6258 func (stream, "mve instruction in it block");
6259 break;
6260
6261 case UNPRED_FCA_0_FCB_1:
6262 func (stream, "condition bits, fca = 0 and fcb = 1");
6263 break;
6264
6265 case UNPRED_R13:
6266 func (stream, "use of r13 (sp)");
6267 break;
6268
6269 case UNPRED_R15:
6270 func (stream, "use of r15 (pc)");
6271 break;
6272
6273 case UNPRED_Q_GT_4:
6274 func (stream, "start register block > r4");
6275 break;
6276
6277 case UNPRED_Q_GT_6:
6278 func (stream, "start register block > r6");
6279 break;
6280
6281 case UNPRED_R13_AND_WB:
6282 func (stream, "use of r13 and write back");
6283 break;
6284
6285 case UNPRED_Q_REGS_EQUAL:
6286 func (stream,
6287 "same vector register used for destination and other operand");
6288 break;
6289
6290 case UNPRED_OS:
6291 func (stream, "use of offset scaled");
6292 break;
6293
6294 case UNPRED_GP_REGS_EQUAL:
6295 func (stream, "same general-purpose register used for both operands");
6296 break;
6297
6298 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
6299 func (stream, "use of identical q registers and size = 1");
6300 break;
6301
6302 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
6303 func (stream, "use of identical q registers and size = 1");
6304 break;
6305
6306 case UNPRED_NONE:
6307 break;
6308 }
6309 }
6310
6311 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
6312
6313 static void
6314 print_mve_register_blocks (struct disassemble_info *info,
6315 unsigned long given,
6316 enum mve_instructions matched_insn)
6317 {
6318 void *stream = info->stream;
6319 fprintf_ftype func = info->fprintf_func;
6320
6321 unsigned long q_reg_start = arm_decode_field_multiple (given,
6322 13, 15,
6323 22, 22);
6324 switch (matched_insn)
6325 {
6326 case MVE_VLD2:
6327 case MVE_VST2:
6328 if (q_reg_start <= 6)
6329 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
6330 else
6331 func (stream, "<illegal reg q%ld>", q_reg_start);
6332 break;
6333
6334 case MVE_VLD4:
6335 case MVE_VST4:
6336 if (q_reg_start <= 4)
6337 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
6338 q_reg_start + 1, q_reg_start + 2,
6339 q_reg_start + 3);
6340 else
6341 func (stream, "<illegal reg q%ld>", q_reg_start);
6342 break;
6343
6344 default:
6345 break;
6346 }
6347 }
6348
6349 static void
6350 print_mve_rounding_mode (struct disassemble_info *info,
6351 unsigned long given,
6352 enum mve_instructions matched_insn)
6353 {
6354 void *stream = info->stream;
6355 fprintf_ftype func = info->fprintf_func;
6356
6357 switch (matched_insn)
6358 {
6359 case MVE_VCVT_FROM_FP_TO_INT:
6360 {
6361 switch (arm_decode_field (given, 8, 9))
6362 {
6363 case 0:
6364 func (stream, "a");
6365 break;
6366
6367 case 1:
6368 func (stream, "n");
6369 break;
6370
6371 case 2:
6372 func (stream, "p");
6373 break;
6374
6375 case 3:
6376 func (stream, "m");
6377 break;
6378
6379 default:
6380 break;
6381 }
6382 }
6383 break;
6384
6385 case MVE_VRINT_FP:
6386 {
6387 switch (arm_decode_field (given, 7, 9))
6388 {
6389 case 0:
6390 func (stream, "n");
6391 break;
6392
6393 case 1:
6394 func (stream, "x");
6395 break;
6396
6397 case 2:
6398 func (stream, "a");
6399 break;
6400
6401 case 3:
6402 func (stream, "z");
6403 break;
6404
6405 case 5:
6406 func (stream, "m");
6407 break;
6408
6409 case 7:
6410 func (stream, "p");
6411
6412 case 4:
6413 case 6:
6414 default:
6415 break;
6416 }
6417 }
6418 break;
6419
6420 default:
6421 break;
6422 }
6423 }
6424
6425 static void
6426 print_mve_vcvt_size (struct disassemble_info *info,
6427 unsigned long given,
6428 enum mve_instructions matched_insn)
6429 {
6430 unsigned long mode = 0;
6431 void *stream = info->stream;
6432 fprintf_ftype func = info->fprintf_func;
6433
6434 switch (matched_insn)
6435 {
6436 case MVE_VCVT_FP_FIX_VEC:
6437 {
6438 mode = (((given & 0x200) >> 7)
6439 | ((given & 0x10000000) >> 27)
6440 | ((given & 0x100) >> 8));
6441
6442 switch (mode)
6443 {
6444 case 0:
6445 func (stream, "f16.s16");
6446 break;
6447
6448 case 1:
6449 func (stream, "s16.f16");
6450 break;
6451
6452 case 2:
6453 func (stream, "f16.u16");
6454 break;
6455
6456 case 3:
6457 func (stream, "u16.f16");
6458 break;
6459
6460 case 4:
6461 func (stream, "f32.s32");
6462 break;
6463
6464 case 5:
6465 func (stream, "s32.f32");
6466 break;
6467
6468 case 6:
6469 func (stream, "f32.u32");
6470 break;
6471
6472 case 7:
6473 func (stream, "u32.f32");
6474 break;
6475
6476 default:
6477 break;
6478 }
6479 break;
6480 }
6481 case MVE_VCVT_BETWEEN_FP_INT:
6482 {
6483 unsigned long size = arm_decode_field (given, 18, 19);
6484 unsigned long op = arm_decode_field (given, 7, 8);
6485
6486 if (size == 1)
6487 {
6488 switch (op)
6489 {
6490 case 0:
6491 func (stream, "f16.s16");
6492 break;
6493
6494 case 1:
6495 func (stream, "f16.u16");
6496 break;
6497
6498 case 2:
6499 func (stream, "s16.f16");
6500 break;
6501
6502 case 3:
6503 func (stream, "u16.f16");
6504 break;
6505
6506 default:
6507 break;
6508 }
6509 }
6510 else if (size == 2)
6511 {
6512 switch (op)
6513 {
6514 case 0:
6515 func (stream, "f32.s32");
6516 break;
6517
6518 case 1:
6519 func (stream, "f32.u32");
6520 break;
6521
6522 case 2:
6523 func (stream, "s32.f32");
6524 break;
6525
6526 case 3:
6527 func (stream, "u32.f32");
6528 break;
6529 }
6530 }
6531 }
6532 break;
6533
6534 case MVE_VCVT_FP_HALF_FP:
6535 {
6536 unsigned long op = arm_decode_field (given, 28, 28);
6537 if (op == 0)
6538 func (stream, "f16.f32");
6539 else if (op == 1)
6540 func (stream, "f32.f16");
6541 }
6542 break;
6543
6544 case MVE_VCVT_FROM_FP_TO_INT:
6545 {
6546 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
6547
6548 switch (size)
6549 {
6550 case 2:
6551 func (stream, "s16.f16");
6552 break;
6553
6554 case 3:
6555 func (stream, "u16.f16");
6556 break;
6557
6558 case 4:
6559 func (stream, "s32.f32");
6560 break;
6561
6562 case 5:
6563 func (stream, "u32.f32");
6564 break;
6565
6566 default:
6567 break;
6568 }
6569 }
6570 break;
6571
6572 default:
6573 break;
6574 }
6575 }
6576
6577 static void
6578 print_mve_rotate (struct disassemble_info *info, unsigned long rot,
6579 unsigned long rot_width)
6580 {
6581 void *stream = info->stream;
6582 fprintf_ftype func = info->fprintf_func;
6583
6584 if (rot_width == 1)
6585 {
6586 switch (rot)
6587 {
6588 case 0:
6589 func (stream, "90");
6590 break;
6591 case 1:
6592 func (stream, "270");
6593 break;
6594 default:
6595 break;
6596 }
6597 }
6598 else if (rot_width == 2)
6599 {
6600 switch (rot)
6601 {
6602 case 0:
6603 func (stream, "0");
6604 break;
6605 case 1:
6606 func (stream, "90");
6607 break;
6608 case 2:
6609 func (stream, "180");
6610 break;
6611 case 3:
6612 func (stream, "270");
6613 break;
6614 default:
6615 break;
6616 }
6617 }
6618 }
6619
6620 static void
6621 print_instruction_predicate (struct disassemble_info *info)
6622 {
6623 void *stream = info->stream;
6624 fprintf_ftype func = info->fprintf_func;
6625
6626 if (vpt_block_state.next_pred_state == PRED_THEN)
6627 func (stream, "t");
6628 else if (vpt_block_state.next_pred_state == PRED_ELSE)
6629 func (stream, "e");
6630 }
6631
6632 static void
6633 print_mve_size (struct disassemble_info *info,
6634 unsigned long size,
6635 enum mve_instructions matched_insn)
6636 {
6637 void *stream = info->stream;
6638 fprintf_ftype func = info->fprintf_func;
6639
6640 switch (matched_insn)
6641 {
6642 case MVE_VADDV:
6643 case MVE_VCADD_VEC:
6644 case MVE_VCMP_VEC_T1:
6645 case MVE_VCMP_VEC_T2:
6646 case MVE_VCMP_VEC_T3:
6647 case MVE_VCMP_VEC_T4:
6648 case MVE_VCMP_VEC_T5:
6649 case MVE_VCMP_VEC_T6:
6650 case MVE_VDDUP:
6651 case MVE_VDWDUP:
6652 case MVE_VHADD_T1:
6653 case MVE_VHADD_T2:
6654 case MVE_VHCADD:
6655 case MVE_VHSUB_T1:
6656 case MVE_VHSUB_T2:
6657 case MVE_VIDUP:
6658 case MVE_VIWDUP:
6659 case MVE_VLD2:
6660 case MVE_VLD4:
6661 case MVE_VLDRB_GATHER_T1:
6662 case MVE_VLDRH_GATHER_T2:
6663 case MVE_VLDRW_GATHER_T3:
6664 case MVE_VLDRD_GATHER_T4:
6665 case MVE_VLDRB_T1:
6666 case MVE_VLDRH_T2:
6667 case MVE_VMLAS:
6668 case MVE_VPT_VEC_T1:
6669 case MVE_VPT_VEC_T2:
6670 case MVE_VPT_VEC_T3:
6671 case MVE_VPT_VEC_T4:
6672 case MVE_VPT_VEC_T5:
6673 case MVE_VPT_VEC_T6:
6674 case MVE_VQDMLADH:
6675 case MVE_VQRDMLADH:
6676 case MVE_VQDMLAH:
6677 case MVE_VQRDMLAH:
6678 case MVE_VQDMLASH:
6679 case MVE_VQRDMLASH:
6680 case MVE_VQDMLSDH:
6681 case MVE_VQRDMLSDH:
6682 case MVE_VQDMULH_T1:
6683 case MVE_VQRDMULH_T2:
6684 case MVE_VQDMULH_T3:
6685 case MVE_VQRDMULH_T4:
6686 case MVE_VQRSHL_T1:
6687 case MVE_VQRSHL_T2:
6688 case MVE_VQSHL_T1:
6689 case MVE_VQSHL_T4:
6690 case MVE_VRHADD:
6691 case MVE_VRINT_FP:
6692 case MVE_VRSHL_T1:
6693 case MVE_VRSHL_T2:
6694 case MVE_VSHL_T2:
6695 case MVE_VSHL_T3:
6696 case MVE_VSHLL_T2:
6697 case MVE_VST2:
6698 case MVE_VST4:
6699 case MVE_VSTRB_SCATTER_T1:
6700 case MVE_VSTRH_SCATTER_T2:
6701 case MVE_VSTRW_SCATTER_T3:
6702 case MVE_VSTRB_T1:
6703 case MVE_VSTRH_T2:
6704 if (size <= 3)
6705 func (stream, "%s", mve_vec_sizename[size]);
6706 else
6707 func (stream, "<undef size>");
6708 break;
6709
6710 case MVE_VCMP_FP_T1:
6711 case MVE_VCMP_FP_T2:
6712 case MVE_VFMA_FP_SCALAR:
6713 case MVE_VFMA_FP:
6714 case MVE_VFMS_FP:
6715 case MVE_VFMAS_FP_SCALAR:
6716 case MVE_VPT_FP_T1:
6717 case MVE_VPT_FP_T2:
6718 if (size == 0)
6719 func (stream, "32");
6720 else if (size == 1)
6721 func (stream, "16");
6722 break;
6723
6724 case MVE_VCADD_FP:
6725 case MVE_VCMLA_FP:
6726 case MVE_VCMUL_FP:
6727 case MVE_VMLADAV_T1:
6728 case MVE_VMLALDAV:
6729 case MVE_VMLSDAV_T1:
6730 case MVE_VMLSLDAV:
6731 case MVE_VMOVN:
6732 case MVE_VQDMULL_T1:
6733 case MVE_VQDMULL_T2:
6734 case MVE_VQMOVN:
6735 case MVE_VQMOVUN:
6736 if (size == 0)
6737 func (stream, "16");
6738 else if (size == 1)
6739 func (stream, "32");
6740 break;
6741
6742 case MVE_VMOVL:
6743 if (size == 1)
6744 func (stream, "8");
6745 else if (size == 2)
6746 func (stream, "16");
6747 break;
6748
6749 case MVE_VDUP:
6750 switch (size)
6751 {
6752 case 0:
6753 func (stream, "32");
6754 break;
6755 case 1:
6756 func (stream, "16");
6757 break;
6758 case 2:
6759 func (stream, "8");
6760 break;
6761 default:
6762 break;
6763 }
6764 break;
6765
6766 case MVE_VMOV_GP_TO_VEC_LANE:
6767 case MVE_VMOV_VEC_LANE_TO_GP:
6768 switch (size)
6769 {
6770 case 0: case 4:
6771 func (stream, "32");
6772 break;
6773
6774 case 1: case 3:
6775 case 5: case 7:
6776 func (stream, "16");
6777 break;
6778
6779 case 8: case 9: case 10: case 11:
6780 case 12: case 13: case 14: case 15:
6781 func (stream, "8");
6782 break;
6783
6784 default:
6785 break;
6786 }
6787 break;
6788
6789 case MVE_VMOV_IMM_TO_VEC:
6790 switch (size)
6791 {
6792 case 0: case 4: case 8:
6793 case 12: case 24: case 26:
6794 func (stream, "i32");
6795 break;
6796 case 16: case 20:
6797 func (stream, "i16");
6798 break;
6799 case 28:
6800 func (stream, "i8");
6801 break;
6802 case 29:
6803 func (stream, "i64");
6804 break;
6805 case 30:
6806 func (stream, "f32");
6807 break;
6808 default:
6809 break;
6810 }
6811 break;
6812
6813 case MVE_VMULL_POLY:
6814 if (size == 0)
6815 func (stream, "p8");
6816 else if (size == 1)
6817 func (stream, "p16");
6818 break;
6819
6820 case MVE_VMVN_IMM:
6821 switch (size)
6822 {
6823 case 0: case 2: case 4:
6824 case 6: case 12: case 13:
6825 func (stream, "32");
6826 break;
6827
6828 case 8: case 10:
6829 func (stream, "16");
6830 break;
6831
6832 default:
6833 break;
6834 }
6835 break;
6836
6837 case MVE_VBIC_IMM:
6838 case MVE_VORR_IMM:
6839 switch (size)
6840 {
6841 case 1: case 3:
6842 case 5: case 7:
6843 func (stream, "32");
6844 break;
6845
6846 case 9: case 11:
6847 func (stream, "16");
6848 break;
6849
6850 default:
6851 break;
6852 }
6853 break;
6854
6855 case MVE_VQSHRN:
6856 case MVE_VQSHRUN:
6857 case MVE_VQRSHRN:
6858 case MVE_VQRSHRUN:
6859 case MVE_VRSHRN:
6860 case MVE_VSHRN:
6861 {
6862 switch (size)
6863 {
6864 case 1:
6865 func (stream, "16");
6866 break;
6867
6868 case 2: case 3:
6869 func (stream, "32");
6870 break;
6871
6872 default:
6873 break;
6874 }
6875 }
6876 break;
6877
6878 case MVE_VQSHL_T2:
6879 case MVE_VQSHLU_T3:
6880 case MVE_VRSHR:
6881 case MVE_VSHL_T1:
6882 case MVE_VSHLL_T1:
6883 case MVE_VSHR:
6884 case MVE_VSLI:
6885 case MVE_VSRI:
6886 {
6887 switch (size)
6888 {
6889 case 1:
6890 func (stream, "8");
6891 break;
6892
6893 case 2: case 3:
6894 func (stream, "16");
6895 break;
6896
6897 case 4: case 5: case 6: case 7:
6898 func (stream, "32");
6899 break;
6900
6901 default:
6902 break;
6903 }
6904 }
6905 break;
6906
6907 default:
6908 break;
6909 }
6910 }
6911
6912 static void
6913 print_mve_shift_n (struct disassemble_info *info, long given,
6914 enum mve_instructions matched_insn)
6915 {
6916 void *stream = info->stream;
6917 fprintf_ftype func = info->fprintf_func;
6918
6919 int startAt0
6920 = matched_insn == MVE_VQSHL_T2
6921 || matched_insn == MVE_VQSHLU_T3
6922 || matched_insn == MVE_VSHL_T1
6923 || matched_insn == MVE_VSHLL_T1
6924 || matched_insn == MVE_VSLI;
6925
6926 unsigned imm6 = (given & 0x3f0000) >> 16;
6927
6928 if (matched_insn == MVE_VSHLL_T1)
6929 imm6 &= 0x1f;
6930
6931 unsigned shiftAmount = 0;
6932 if ((imm6 & 0x20) != 0)
6933 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
6934 else if ((imm6 & 0x10) != 0)
6935 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
6936 else if ((imm6 & 0x08) != 0)
6937 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
6938 else
6939 print_mve_undefined (info, UNDEF_SIZE_0);
6940
6941 func (stream, "%u", shiftAmount);
6942 }
6943
6944 static void
6945 print_vec_condition (struct disassemble_info *info, long given,
6946 enum mve_instructions matched_insn)
6947 {
6948 void *stream = info->stream;
6949 fprintf_ftype func = info->fprintf_func;
6950 long vec_cond = 0;
6951
6952 switch (matched_insn)
6953 {
6954 case MVE_VPT_FP_T1:
6955 case MVE_VCMP_FP_T1:
6956 vec_cond = (((given & 0x1000) >> 10)
6957 | ((given & 1) << 1)
6958 | ((given & 0x0080) >> 7));
6959 func (stream, "%s",vec_condnames[vec_cond]);
6960 break;
6961
6962 case MVE_VPT_FP_T2:
6963 case MVE_VCMP_FP_T2:
6964 vec_cond = (((given & 0x1000) >> 10)
6965 | ((given & 0x0020) >> 4)
6966 | ((given & 0x0080) >> 7));
6967 func (stream, "%s",vec_condnames[vec_cond]);
6968 break;
6969
6970 case MVE_VPT_VEC_T1:
6971 case MVE_VCMP_VEC_T1:
6972 vec_cond = (given & 0x0080) >> 7;
6973 func (stream, "%s",vec_condnames[vec_cond]);
6974 break;
6975
6976 case MVE_VPT_VEC_T2:
6977 case MVE_VCMP_VEC_T2:
6978 vec_cond = 2 | ((given & 0x0080) >> 7);
6979 func (stream, "%s",vec_condnames[vec_cond]);
6980 break;
6981
6982 case MVE_VPT_VEC_T3:
6983 case MVE_VCMP_VEC_T3:
6984 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
6985 func (stream, "%s",vec_condnames[vec_cond]);
6986 break;
6987
6988 case MVE_VPT_VEC_T4:
6989 case MVE_VCMP_VEC_T4:
6990 vec_cond = (given & 0x0080) >> 7;
6991 func (stream, "%s",vec_condnames[vec_cond]);
6992 break;
6993
6994 case MVE_VPT_VEC_T5:
6995 case MVE_VCMP_VEC_T5:
6996 vec_cond = 2 | ((given & 0x0080) >> 7);
6997 func (stream, "%s",vec_condnames[vec_cond]);
6998 break;
6999
7000 case MVE_VPT_VEC_T6:
7001 case MVE_VCMP_VEC_T6:
7002 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7003 func (stream, "%s",vec_condnames[vec_cond]);
7004 break;
7005
7006 case MVE_NONE:
7007 case MVE_VPST:
7008 default:
7009 break;
7010 }
7011 }
7012
7013 #define W_BIT 21
7014 #define I_BIT 22
7015 #define U_BIT 23
7016 #define P_BIT 24
7017
7018 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7019 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7020 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7021 #define PRE_BIT_SET (given & (1 << P_BIT))
7022
7023
7024 /* Print one coprocessor instruction on INFO->STREAM.
7025 Return TRUE if the instuction matched, FALSE if this is not a
7026 recognised coprocessor instruction. */
7027
7028 static bfd_boolean
7029 print_insn_coprocessor (bfd_vma pc,
7030 struct disassemble_info *info,
7031 long given,
7032 bfd_boolean thumb)
7033 {
7034 const struct sopcode32 *insn;
7035 void *stream = info->stream;
7036 fprintf_ftype func = info->fprintf_func;
7037 unsigned long mask;
7038 unsigned long value = 0;
7039 int cond;
7040 int cp_num;
7041 struct arm_private_data *private_data = info->private_data;
7042 arm_feature_set allowed_arches = ARM_ARCH_NONE;
7043 arm_feature_set arm_ext_v8_1m_main =
7044 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
7045
7046 allowed_arches = private_data->features;
7047
7048 for (insn = coprocessor_opcodes; insn->assembler; insn++)
7049 {
7050 unsigned long u_reg = 16;
7051 bfd_boolean is_unpredictable = FALSE;
7052 signed long value_in_comment = 0;
7053 const char *c;
7054
7055 if (ARM_FEATURE_ZERO (insn->arch))
7056 switch (insn->value)
7057 {
7058 case SENTINEL_IWMMXT_START:
7059 if (info->mach != bfd_mach_arm_XScale
7060 && info->mach != bfd_mach_arm_iWMMXt
7061 && info->mach != bfd_mach_arm_iWMMXt2)
7062 do
7063 insn++;
7064 while ((! ARM_FEATURE_ZERO (insn->arch))
7065 && insn->value != SENTINEL_IWMMXT_END);
7066 continue;
7067
7068 case SENTINEL_IWMMXT_END:
7069 continue;
7070
7071 case SENTINEL_GENERIC_START:
7072 allowed_arches = private_data->features;
7073 continue;
7074
7075 default:
7076 abort ();
7077 }
7078
7079 mask = insn->mask;
7080 value = insn->value;
7081 cp_num = (given >> 8) & 0xf;
7082
7083 if (thumb)
7084 {
7085 /* The high 4 bits are 0xe for Arm conditional instructions, and
7086 0xe for arm unconditional instructions. The rest of the
7087 encoding is the same. */
7088 mask |= 0xf0000000;
7089 value |= 0xe0000000;
7090 if (ifthen_state)
7091 cond = IFTHEN_COND;
7092 else
7093 cond = COND_UNCOND;
7094 }
7095 else
7096 {
7097 /* Only match unconditional instuctions against unconditional
7098 patterns. */
7099 if ((given & 0xf0000000) == 0xf0000000)
7100 {
7101 mask |= 0xf0000000;
7102 cond = COND_UNCOND;
7103 }
7104 else
7105 {
7106 cond = (given >> 28) & 0xf;
7107 if (cond == 0xe)
7108 cond = COND_UNCOND;
7109 }
7110 }
7111
7112 if ((insn->isa == T32 && !thumb)
7113 || (insn->isa == ARM && thumb))
7114 continue;
7115
7116 if ((given & mask) != value)
7117 continue;
7118
7119 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
7120 continue;
7121
7122 if (insn->value == 0xfe000010 /* mcr2 */
7123 || insn->value == 0xfe100010 /* mrc2 */
7124 || insn->value == 0xfc100000 /* ldc2 */
7125 || insn->value == 0xfc000000) /* stc2 */
7126 {
7127 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7128 is_unpredictable = TRUE;
7129
7130 /* Armv8.1-M Mainline FP & MVE instructions. */
7131 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7132 && !ARM_CPU_IS_ANY (allowed_arches)
7133 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7134 continue;
7135
7136 }
7137 else if (insn->value == 0x0e000000 /* cdp */
7138 || insn->value == 0xfe000000 /* cdp2 */
7139 || insn->value == 0x0e000010 /* mcr */
7140 || insn->value == 0x0e100010 /* mrc */
7141 || insn->value == 0x0c100000 /* ldc */
7142 || insn->value == 0x0c000000) /* stc */
7143 {
7144 /* Floating-point instructions. */
7145 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7146 continue;
7147
7148 /* Armv8.1-M Mainline FP & MVE instructions. */
7149 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7150 && !ARM_CPU_IS_ANY (allowed_arches)
7151 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7152 continue;
7153 }
7154 else if ((insn->value == 0xec100f80 /* vldr (system register) */
7155 || insn->value == 0xec000f80) /* vstr (system register) */
7156 && arm_decode_field (given, 24, 24) == 0
7157 && arm_decode_field (given, 21, 21) == 0)
7158 /* If the P and W bits are both 0 then these encodings match the MVE
7159 VLDR and VSTR instructions, these are in a different table, so we
7160 don't let it match here. */
7161 continue;
7162
7163 for (c = insn->assembler; *c; c++)
7164 {
7165 if (*c == '%')
7166 {
7167 const char mod = *++c;
7168 switch (mod)
7169 {
7170 case '%':
7171 func (stream, "%%");
7172 break;
7173
7174 case 'A':
7175 case 'K':
7176 {
7177 int rn = (given >> 16) & 0xf;
7178 bfd_vma offset = given & 0xff;
7179
7180 if (mod == 'K')
7181 offset = given & 0x7f;
7182
7183 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
7184
7185 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
7186 {
7187 /* Not unindexed. The offset is scaled. */
7188 if (cp_num == 9)
7189 /* vldr.16/vstr.16 will shift the address
7190 left by 1 bit only. */
7191 offset = offset * 2;
7192 else
7193 offset = offset * 4;
7194
7195 if (NEGATIVE_BIT_SET)
7196 offset = - offset;
7197 if (rn != 15)
7198 value_in_comment = offset;
7199 }
7200
7201 if (PRE_BIT_SET)
7202 {
7203 if (offset)
7204 func (stream, ", #%d]%s",
7205 (int) offset,
7206 WRITEBACK_BIT_SET ? "!" : "");
7207 else if (NEGATIVE_BIT_SET)
7208 func (stream, ", #-0]");
7209 else
7210 func (stream, "]");
7211 }
7212 else
7213 {
7214 func (stream, "]");
7215
7216 if (WRITEBACK_BIT_SET)
7217 {
7218 if (offset)
7219 func (stream, ", #%d", (int) offset);
7220 else if (NEGATIVE_BIT_SET)
7221 func (stream, ", #-0");
7222 }
7223 else
7224 {
7225 func (stream, ", {%s%d}",
7226 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
7227 (int) offset);
7228 value_in_comment = offset;
7229 }
7230 }
7231 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
7232 {
7233 func (stream, "\t; ");
7234 /* For unaligned PCs, apply off-by-alignment
7235 correction. */
7236 info->print_address_func (offset + pc
7237 + info->bytes_per_chunk * 2
7238 - (pc & 3),
7239 info);
7240 }
7241 }
7242 break;
7243
7244 case 'B':
7245 {
7246 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
7247 int offset = (given >> 1) & 0x3f;
7248
7249 if (offset == 1)
7250 func (stream, "{d%d}", regno);
7251 else if (regno + offset > 32)
7252 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
7253 else
7254 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
7255 }
7256 break;
7257
7258 case 'C':
7259 {
7260 bfd_boolean single = ((given >> 8) & 1) == 0;
7261 char reg_prefix = single ? 's' : 'd';
7262 int Dreg = (given >> 22) & 0x1;
7263 int Vdreg = (given >> 12) & 0xf;
7264 int reg = single ? ((Vdreg << 1) | Dreg)
7265 : ((Dreg << 4) | Vdreg);
7266 int num = (given >> (single ? 0 : 1)) & 0x7f;
7267 int maxreg = single ? 31 : 15;
7268 int topreg = reg + num - 1;
7269
7270 if (!num)
7271 func (stream, "{VPR}");
7272 else if (num == 1)
7273 func (stream, "{%c%d, VPR}", reg_prefix, reg);
7274 else if (topreg > maxreg)
7275 func (stream, "{%c%d-<overflow reg d%d, VPR}",
7276 reg_prefix, reg, single ? topreg >> 1 : topreg);
7277 else
7278 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
7279 reg_prefix, topreg);
7280 }
7281 break;
7282
7283 case 'u':
7284 if (cond != COND_UNCOND)
7285 is_unpredictable = TRUE;
7286
7287 /* Fall through. */
7288 case 'c':
7289 if (cond != COND_UNCOND && cp_num == 9)
7290 is_unpredictable = TRUE;
7291
7292 func (stream, "%s", arm_conditional[cond]);
7293 break;
7294
7295 case 'I':
7296 /* Print a Cirrus/DSP shift immediate. */
7297 /* Immediates are 7bit signed ints with bits 0..3 in
7298 bits 0..3 of opcode and bits 4..6 in bits 5..7
7299 of opcode. */
7300 {
7301 int imm;
7302
7303 imm = (given & 0xf) | ((given & 0xe0) >> 1);
7304
7305 /* Is ``imm'' a negative number? */
7306 if (imm & 0x40)
7307 imm -= 0x80;
7308
7309 func (stream, "%d", imm);
7310 }
7311
7312 break;
7313
7314 case 'J':
7315 {
7316 unsigned long regno
7317 = arm_decode_field_multiple (given, 13, 15, 22, 22);
7318
7319 switch (regno)
7320 {
7321 case 0x1:
7322 func (stream, "FPSCR");
7323 break;
7324 case 0x2:
7325 func (stream, "FPSCR_nzcvqc");
7326 break;
7327 case 0xc:
7328 func (stream, "VPR");
7329 break;
7330 case 0xd:
7331 func (stream, "P0");
7332 break;
7333 case 0xe:
7334 func (stream, "FPCXTNS");
7335 break;
7336 case 0xf:
7337 func (stream, "FPCXTS");
7338 break;
7339 default:
7340 func (stream, "<invalid reg %lu>", regno);
7341 break;
7342 }
7343 }
7344 break;
7345
7346 case 'F':
7347 switch (given & 0x00408000)
7348 {
7349 case 0:
7350 func (stream, "4");
7351 break;
7352 case 0x8000:
7353 func (stream, "1");
7354 break;
7355 case 0x00400000:
7356 func (stream, "2");
7357 break;
7358 default:
7359 func (stream, "3");
7360 }
7361 break;
7362
7363 case 'P':
7364 switch (given & 0x00080080)
7365 {
7366 case 0:
7367 func (stream, "s");
7368 break;
7369 case 0x80:
7370 func (stream, "d");
7371 break;
7372 case 0x00080000:
7373 func (stream, "e");
7374 break;
7375 default:
7376 func (stream, _("<illegal precision>"));
7377 break;
7378 }
7379 break;
7380
7381 case 'Q':
7382 switch (given & 0x00408000)
7383 {
7384 case 0:
7385 func (stream, "s");
7386 break;
7387 case 0x8000:
7388 func (stream, "d");
7389 break;
7390 case 0x00400000:
7391 func (stream, "e");
7392 break;
7393 default:
7394 func (stream, "p");
7395 break;
7396 }
7397 break;
7398
7399 case 'R':
7400 switch (given & 0x60)
7401 {
7402 case 0:
7403 break;
7404 case 0x20:
7405 func (stream, "p");
7406 break;
7407 case 0x40:
7408 func (stream, "m");
7409 break;
7410 default:
7411 func (stream, "z");
7412 break;
7413 }
7414 break;
7415
7416 case '0': case '1': case '2': case '3': case '4':
7417 case '5': case '6': case '7': case '8': case '9':
7418 {
7419 int width;
7420
7421 c = arm_decode_bitfield (c, given, &value, &width);
7422
7423 switch (*c)
7424 {
7425 case 'R':
7426 if (value == 15)
7427 is_unpredictable = TRUE;
7428 /* Fall through. */
7429 case 'r':
7430 if (c[1] == 'u')
7431 {
7432 /* Eat the 'u' character. */
7433 ++ c;
7434
7435 if (u_reg == value)
7436 is_unpredictable = TRUE;
7437 u_reg = value;
7438 }
7439 func (stream, "%s", arm_regnames[value]);
7440 break;
7441 case 'V':
7442 if (given & (1 << 6))
7443 goto Q;
7444 /* FALLTHROUGH */
7445 case 'D':
7446 func (stream, "d%ld", value);
7447 break;
7448 case 'Q':
7449 Q:
7450 if (value & 1)
7451 func (stream, "<illegal reg q%ld.5>", value >> 1);
7452 else
7453 func (stream, "q%ld", value >> 1);
7454 break;
7455 case 'd':
7456 func (stream, "%ld", value);
7457 value_in_comment = value;
7458 break;
7459 case 'E':
7460 {
7461 /* Converts immediate 8 bit back to float value. */
7462 unsigned floatVal = (value & 0x80) << 24
7463 | (value & 0x3F) << 19
7464 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
7465
7466 /* Quarter float have a maximum value of 31.0.
7467 Get floating point value multiplied by 1e7.
7468 The maximum value stays in limit of a 32-bit int. */
7469 unsigned decVal =
7470 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
7471 (16 + (value & 0xF));
7472
7473 if (!(decVal % 1000000))
7474 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
7475 floatVal, value & 0x80 ? '-' : ' ',
7476 decVal / 10000000,
7477 decVal % 10000000 / 1000000);
7478 else if (!(decVal % 10000))
7479 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
7480 floatVal, value & 0x80 ? '-' : ' ',
7481 decVal / 10000000,
7482 decVal % 10000000 / 10000);
7483 else
7484 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
7485 floatVal, value & 0x80 ? '-' : ' ',
7486 decVal / 10000000, decVal % 10000000);
7487 break;
7488 }
7489 case 'k':
7490 {
7491 int from = (given & (1 << 7)) ? 32 : 16;
7492 func (stream, "%ld", from - value);
7493 }
7494 break;
7495
7496 case 'f':
7497 if (value > 7)
7498 func (stream, "#%s", arm_fp_const[value & 7]);
7499 else
7500 func (stream, "f%ld", value);
7501 break;
7502
7503 case 'w':
7504 if (width == 2)
7505 func (stream, "%s", iwmmxt_wwnames[value]);
7506 else
7507 func (stream, "%s", iwmmxt_wwssnames[value]);
7508 break;
7509
7510 case 'g':
7511 func (stream, "%s", iwmmxt_regnames[value]);
7512 break;
7513 case 'G':
7514 func (stream, "%s", iwmmxt_cregnames[value]);
7515 break;
7516
7517 case 'x':
7518 func (stream, "0x%lx", (value & 0xffffffffUL));
7519 break;
7520
7521 case 'c':
7522 switch (value)
7523 {
7524 case 0:
7525 func (stream, "eq");
7526 break;
7527
7528 case 1:
7529 func (stream, "vs");
7530 break;
7531
7532 case 2:
7533 func (stream, "ge");
7534 break;
7535
7536 case 3:
7537 func (stream, "gt");
7538 break;
7539
7540 default:
7541 func (stream, "??");
7542 break;
7543 }
7544 break;
7545
7546 case '`':
7547 c++;
7548 if (value == 0)
7549 func (stream, "%c", *c);
7550 break;
7551 case '\'':
7552 c++;
7553 if (value == ((1ul << width) - 1))
7554 func (stream, "%c", *c);
7555 break;
7556 case '?':
7557 func (stream, "%c", c[(1 << width) - (int) value]);
7558 c += 1 << width;
7559 break;
7560 default:
7561 abort ();
7562 }
7563 }
7564 break;
7565
7566 case 'y':
7567 case 'z':
7568 {
7569 int single = *c++ == 'y';
7570 int regno;
7571
7572 switch (*c)
7573 {
7574 case '4': /* Sm pair */
7575 case '0': /* Sm, Dm */
7576 regno = given & 0x0000000f;
7577 if (single)
7578 {
7579 regno <<= 1;
7580 regno += (given >> 5) & 1;
7581 }
7582 else
7583 regno += ((given >> 5) & 1) << 4;
7584 break;
7585
7586 case '1': /* Sd, Dd */
7587 regno = (given >> 12) & 0x0000000f;
7588 if (single)
7589 {
7590 regno <<= 1;
7591 regno += (given >> 22) & 1;
7592 }
7593 else
7594 regno += ((given >> 22) & 1) << 4;
7595 break;
7596
7597 case '2': /* Sn, Dn */
7598 regno = (given >> 16) & 0x0000000f;
7599 if (single)
7600 {
7601 regno <<= 1;
7602 regno += (given >> 7) & 1;
7603 }
7604 else
7605 regno += ((given >> 7) & 1) << 4;
7606 break;
7607
7608 case '3': /* List */
7609 func (stream, "{");
7610 regno = (given >> 12) & 0x0000000f;
7611 if (single)
7612 {
7613 regno <<= 1;
7614 regno += (given >> 22) & 1;
7615 }
7616 else
7617 regno += ((given >> 22) & 1) << 4;
7618 break;
7619
7620 default:
7621 abort ();
7622 }
7623
7624 func (stream, "%c%d", single ? 's' : 'd', regno);
7625
7626 if (*c == '3')
7627 {
7628 int count = given & 0xff;
7629
7630 if (single == 0)
7631 count >>= 1;
7632
7633 if (--count)
7634 {
7635 func (stream, "-%c%d",
7636 single ? 's' : 'd',
7637 regno + count);
7638 }
7639
7640 func (stream, "}");
7641 }
7642 else if (*c == '4')
7643 func (stream, ", %c%d", single ? 's' : 'd',
7644 regno + 1);
7645 }
7646 break;
7647
7648 case 'L':
7649 switch (given & 0x00400100)
7650 {
7651 case 0x00000000: func (stream, "b"); break;
7652 case 0x00400000: func (stream, "h"); break;
7653 case 0x00000100: func (stream, "w"); break;
7654 case 0x00400100: func (stream, "d"); break;
7655 default:
7656 break;
7657 }
7658 break;
7659
7660 case 'Z':
7661 {
7662 /* given (20, 23) | given (0, 3) */
7663 value = ((given >> 16) & 0xf0) | (given & 0xf);
7664 func (stream, "%d", (int) value);
7665 }
7666 break;
7667
7668 case 'l':
7669 /* This is like the 'A' operator, except that if
7670 the width field "M" is zero, then the offset is
7671 *not* multiplied by four. */
7672 {
7673 int offset = given & 0xff;
7674 int multiplier = (given & 0x00000100) ? 4 : 1;
7675
7676 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
7677
7678 if (multiplier > 1)
7679 {
7680 value_in_comment = offset * multiplier;
7681 if (NEGATIVE_BIT_SET)
7682 value_in_comment = - value_in_comment;
7683 }
7684
7685 if (offset)
7686 {
7687 if (PRE_BIT_SET)
7688 func (stream, ", #%s%d]%s",
7689 NEGATIVE_BIT_SET ? "-" : "",
7690 offset * multiplier,
7691 WRITEBACK_BIT_SET ? "!" : "");
7692 else
7693 func (stream, "], #%s%d",
7694 NEGATIVE_BIT_SET ? "-" : "",
7695 offset * multiplier);
7696 }
7697 else
7698 func (stream, "]");
7699 }
7700 break;
7701
7702 case 'r':
7703 {
7704 int imm4 = (given >> 4) & 0xf;
7705 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
7706 int ubit = ! NEGATIVE_BIT_SET;
7707 const char *rm = arm_regnames [given & 0xf];
7708 const char *rn = arm_regnames [(given >> 16) & 0xf];
7709
7710 switch (puw_bits)
7711 {
7712 case 1:
7713 case 3:
7714 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
7715 if (imm4)
7716 func (stream, ", lsl #%d", imm4);
7717 break;
7718
7719 case 4:
7720 case 5:
7721 case 6:
7722 case 7:
7723 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
7724 if (imm4 > 0)
7725 func (stream, ", lsl #%d", imm4);
7726 func (stream, "]");
7727 if (puw_bits == 5 || puw_bits == 7)
7728 func (stream, "!");
7729 break;
7730
7731 default:
7732 func (stream, "INVALID");
7733 }
7734 }
7735 break;
7736
7737 case 'i':
7738 {
7739 long imm5;
7740 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
7741 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
7742 }
7743 break;
7744
7745 default:
7746 abort ();
7747 }
7748 }
7749 else
7750 func (stream, "%c", *c);
7751 }
7752
7753 if (value_in_comment > 32 || value_in_comment < -16)
7754 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
7755
7756 if (is_unpredictable)
7757 func (stream, UNPREDICTABLE_INSTRUCTION);
7758
7759 return TRUE;
7760 }
7761 return FALSE;
7762 }
7763
7764 /* Decodes and prints ARM addressing modes. Returns the offset
7765 used in the address, if any, if it is worthwhile printing the
7766 offset as a hexadecimal value in a comment at the end of the
7767 line of disassembly. */
7768
7769 static signed long
7770 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
7771 {
7772 void *stream = info->stream;
7773 fprintf_ftype func = info->fprintf_func;
7774 bfd_vma offset = 0;
7775
7776 if (((given & 0x000f0000) == 0x000f0000)
7777 && ((given & 0x02000000) == 0))
7778 {
7779 offset = given & 0xfff;
7780
7781 func (stream, "[pc");
7782
7783 if (PRE_BIT_SET)
7784 {
7785 /* Pre-indexed. Elide offset of positive zero when
7786 non-writeback. */
7787 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
7788 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
7789
7790 if (NEGATIVE_BIT_SET)
7791 offset = -offset;
7792
7793 offset += pc + 8;
7794
7795 /* Cope with the possibility of write-back
7796 being used. Probably a very dangerous thing
7797 for the programmer to do, but who are we to
7798 argue ? */
7799 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
7800 }
7801 else /* Post indexed. */
7802 {
7803 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
7804
7805 /* Ie ignore the offset. */
7806 offset = pc + 8;
7807 }
7808
7809 func (stream, "\t; ");
7810 info->print_address_func (offset, info);
7811 offset = 0;
7812 }
7813 else
7814 {
7815 func (stream, "[%s",
7816 arm_regnames[(given >> 16) & 0xf]);
7817
7818 if (PRE_BIT_SET)
7819 {
7820 if ((given & 0x02000000) == 0)
7821 {
7822 /* Elide offset of positive zero when non-writeback. */
7823 offset = given & 0xfff;
7824 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
7825 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
7826 }
7827 else
7828 {
7829 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
7830 arm_decode_shift (given, func, stream, TRUE);
7831 }
7832
7833 func (stream, "]%s",
7834 WRITEBACK_BIT_SET ? "!" : "");
7835 }
7836 else
7837 {
7838 if ((given & 0x02000000) == 0)
7839 {
7840 /* Always show offset. */
7841 offset = given & 0xfff;
7842 func (stream, "], #%s%d",
7843 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
7844 }
7845 else
7846 {
7847 func (stream, "], %s",
7848 NEGATIVE_BIT_SET ? "-" : "");
7849 arm_decode_shift (given, func, stream, TRUE);
7850 }
7851 }
7852 if (NEGATIVE_BIT_SET)
7853 offset = -offset;
7854 }
7855
7856 return (signed long) offset;
7857 }
7858
7859 /* Print one neon instruction on INFO->STREAM.
7860 Return TRUE if the instuction matched, FALSE if this is not a
7861 recognised neon instruction. */
7862
7863 static bfd_boolean
7864 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
7865 {
7866 const struct opcode32 *insn;
7867 void *stream = info->stream;
7868 fprintf_ftype func = info->fprintf_func;
7869
7870 if (thumb)
7871 {
7872 if ((given & 0xef000000) == 0xef000000)
7873 {
7874 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
7875 unsigned long bit28 = given & (1 << 28);
7876
7877 given &= 0x00ffffff;
7878 if (bit28)
7879 given |= 0xf3000000;
7880 else
7881 given |= 0xf2000000;
7882 }
7883 else if ((given & 0xff000000) == 0xf9000000)
7884 given ^= 0xf9000000 ^ 0xf4000000;
7885 /* vdup is also a valid neon instruction. */
7886 else if ((given & 0xff910f5f) != 0xee800b10)
7887 return FALSE;
7888 }
7889
7890 for (insn = neon_opcodes; insn->assembler; insn++)
7891 {
7892 if ((given & insn->mask) == insn->value)
7893 {
7894 signed long value_in_comment = 0;
7895 bfd_boolean is_unpredictable = FALSE;
7896 const char *c;
7897
7898 for (c = insn->assembler; *c; c++)
7899 {
7900 if (*c == '%')
7901 {
7902 switch (*++c)
7903 {
7904 case '%':
7905 func (stream, "%%");
7906 break;
7907
7908 case 'u':
7909 if (thumb && ifthen_state)
7910 is_unpredictable = TRUE;
7911
7912 /* Fall through. */
7913 case 'c':
7914 if (thumb && ifthen_state)
7915 func (stream, "%s", arm_conditional[IFTHEN_COND]);
7916 break;
7917
7918 case 'A':
7919 {
7920 static const unsigned char enc[16] =
7921 {
7922 0x4, 0x14, /* st4 0,1 */
7923 0x4, /* st1 2 */
7924 0x4, /* st2 3 */
7925 0x3, /* st3 4 */
7926 0x13, /* st3 5 */
7927 0x3, /* st1 6 */
7928 0x1, /* st1 7 */
7929 0x2, /* st2 8 */
7930 0x12, /* st2 9 */
7931 0x2, /* st1 10 */
7932 0, 0, 0, 0, 0
7933 };
7934 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7935 int rn = ((given >> 16) & 0xf);
7936 int rm = ((given >> 0) & 0xf);
7937 int align = ((given >> 4) & 0x3);
7938 int type = ((given >> 8) & 0xf);
7939 int n = enc[type] & 0xf;
7940 int stride = (enc[type] >> 4) + 1;
7941 int ix;
7942
7943 func (stream, "{");
7944 if (stride > 1)
7945 for (ix = 0; ix != n; ix++)
7946 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
7947 else if (n == 1)
7948 func (stream, "d%d", rd);
7949 else
7950 func (stream, "d%d-d%d", rd, rd + n - 1);
7951 func (stream, "}, [%s", arm_regnames[rn]);
7952 if (align)
7953 func (stream, " :%d", 32 << align);
7954 func (stream, "]");
7955 if (rm == 0xd)
7956 func (stream, "!");
7957 else if (rm != 0xf)
7958 func (stream, ", %s", arm_regnames[rm]);
7959 }
7960 break;
7961
7962 case 'B':
7963 {
7964 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7965 int rn = ((given >> 16) & 0xf);
7966 int rm = ((given >> 0) & 0xf);
7967 int idx_align = ((given >> 4) & 0xf);
7968 int align = 0;
7969 int size = ((given >> 10) & 0x3);
7970 int idx = idx_align >> (size + 1);
7971 int length = ((given >> 8) & 3) + 1;
7972 int stride = 1;
7973 int i;
7974
7975 if (length > 1 && size > 0)
7976 stride = (idx_align & (1 << size)) ? 2 : 1;
7977
7978 switch (length)
7979 {
7980 case 1:
7981 {
7982 int amask = (1 << size) - 1;
7983 if ((idx_align & (1 << size)) != 0)
7984 return FALSE;
7985 if (size > 0)
7986 {
7987 if ((idx_align & amask) == amask)
7988 align = 8 << size;
7989 else if ((idx_align & amask) != 0)
7990 return FALSE;
7991 }
7992 }
7993 break;
7994
7995 case 2:
7996 if (size == 2 && (idx_align & 2) != 0)
7997 return FALSE;
7998 align = (idx_align & 1) ? 16 << size : 0;
7999 break;
8000
8001 case 3:
8002 if ((size == 2 && (idx_align & 3) != 0)
8003 || (idx_align & 1) != 0)
8004 return FALSE;
8005 break;
8006
8007 case 4:
8008 if (size == 2)
8009 {
8010 if ((idx_align & 3) == 3)
8011 return FALSE;
8012 align = (idx_align & 3) * 64;
8013 }
8014 else
8015 align = (idx_align & 1) ? 32 << size : 0;
8016 break;
8017
8018 default:
8019 abort ();
8020 }
8021
8022 func (stream, "{");
8023 for (i = 0; i < length; i++)
8024 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8025 rd + i * stride, idx);
8026 func (stream, "}, [%s", arm_regnames[rn]);
8027 if (align)
8028 func (stream, " :%d", align);
8029 func (stream, "]");
8030 if (rm == 0xd)
8031 func (stream, "!");
8032 else if (rm != 0xf)
8033 func (stream, ", %s", arm_regnames[rm]);
8034 }
8035 break;
8036
8037 case 'C':
8038 {
8039 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8040 int rn = ((given >> 16) & 0xf);
8041 int rm = ((given >> 0) & 0xf);
8042 int align = ((given >> 4) & 0x1);
8043 int size = ((given >> 6) & 0x3);
8044 int type = ((given >> 8) & 0x3);
8045 int n = type + 1;
8046 int stride = ((given >> 5) & 0x1);
8047 int ix;
8048
8049 if (stride && (n == 1))
8050 n++;
8051 else
8052 stride++;
8053
8054 func (stream, "{");
8055 if (stride > 1)
8056 for (ix = 0; ix != n; ix++)
8057 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8058 else if (n == 1)
8059 func (stream, "d%d[]", rd);
8060 else
8061 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8062 func (stream, "}, [%s", arm_regnames[rn]);
8063 if (align)
8064 {
8065 align = (8 * (type + 1)) << size;
8066 if (type == 3)
8067 align = (size > 1) ? align >> 1 : align;
8068 if (type == 2 || (type == 0 && !size))
8069 func (stream, " :<bad align %d>", align);
8070 else
8071 func (stream, " :%d", align);
8072 }
8073 func (stream, "]");
8074 if (rm == 0xd)
8075 func (stream, "!");
8076 else if (rm != 0xf)
8077 func (stream, ", %s", arm_regnames[rm]);
8078 }
8079 break;
8080
8081 case 'D':
8082 {
8083 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
8084 int size = (given >> 20) & 3;
8085 int reg = raw_reg & ((4 << size) - 1);
8086 int ix = raw_reg >> size >> 2;
8087
8088 func (stream, "d%d[%d]", reg, ix);
8089 }
8090 break;
8091
8092 case 'E':
8093 /* Neon encoded constant for mov, mvn, vorr, vbic. */
8094 {
8095 int bits = 0;
8096 int cmode = (given >> 8) & 0xf;
8097 int op = (given >> 5) & 0x1;
8098 unsigned long value = 0, hival = 0;
8099 unsigned shift;
8100 int size = 0;
8101 int isfloat = 0;
8102
8103 bits |= ((given >> 24) & 1) << 7;
8104 bits |= ((given >> 16) & 7) << 4;
8105 bits |= ((given >> 0) & 15) << 0;
8106
8107 if (cmode < 8)
8108 {
8109 shift = (cmode >> 1) & 3;
8110 value = (unsigned long) bits << (8 * shift);
8111 size = 32;
8112 }
8113 else if (cmode < 12)
8114 {
8115 shift = (cmode >> 1) & 1;
8116 value = (unsigned long) bits << (8 * shift);
8117 size = 16;
8118 }
8119 else if (cmode < 14)
8120 {
8121 shift = (cmode & 1) + 1;
8122 value = (unsigned long) bits << (8 * shift);
8123 value |= (1ul << (8 * shift)) - 1;
8124 size = 32;
8125 }
8126 else if (cmode == 14)
8127 {
8128 if (op)
8129 {
8130 /* Bit replication into bytes. */
8131 int ix;
8132 unsigned long mask;
8133
8134 value = 0;
8135 hival = 0;
8136 for (ix = 7; ix >= 0; ix--)
8137 {
8138 mask = ((bits >> ix) & 1) ? 0xff : 0;
8139 if (ix <= 3)
8140 value = (value << 8) | mask;
8141 else
8142 hival = (hival << 8) | mask;
8143 }
8144 size = 64;
8145 }
8146 else
8147 {
8148 /* Byte replication. */
8149 value = (unsigned long) bits;
8150 size = 8;
8151 }
8152 }
8153 else if (!op)
8154 {
8155 /* Floating point encoding. */
8156 int tmp;
8157
8158 value = (unsigned long) (bits & 0x7f) << 19;
8159 value |= (unsigned long) (bits & 0x80) << 24;
8160 tmp = bits & 0x40 ? 0x3c : 0x40;
8161 value |= (unsigned long) tmp << 24;
8162 size = 32;
8163 isfloat = 1;
8164 }
8165 else
8166 {
8167 func (stream, "<illegal constant %.8x:%x:%x>",
8168 bits, cmode, op);
8169 size = 32;
8170 break;
8171 }
8172 switch (size)
8173 {
8174 case 8:
8175 func (stream, "#%ld\t; 0x%.2lx", value, value);
8176 break;
8177
8178 case 16:
8179 func (stream, "#%ld\t; 0x%.4lx", value, value);
8180 break;
8181
8182 case 32:
8183 if (isfloat)
8184 {
8185 unsigned char valbytes[4];
8186 double fvalue;
8187
8188 /* Do this a byte at a time so we don't have to
8189 worry about the host's endianness. */
8190 valbytes[0] = value & 0xff;
8191 valbytes[1] = (value >> 8) & 0xff;
8192 valbytes[2] = (value >> 16) & 0xff;
8193 valbytes[3] = (value >> 24) & 0xff;
8194
8195 floatformat_to_double
8196 (& floatformat_ieee_single_little, valbytes,
8197 & fvalue);
8198
8199 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
8200 value);
8201 }
8202 else
8203 func (stream, "#%ld\t; 0x%.8lx",
8204 (long) (((value & 0x80000000L) != 0)
8205 ? value | ~0xffffffffL : value),
8206 value);
8207 break;
8208
8209 case 64:
8210 func (stream, "#0x%.8lx%.8lx", hival, value);
8211 break;
8212
8213 default:
8214 abort ();
8215 }
8216 }
8217 break;
8218
8219 case 'F':
8220 {
8221 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
8222 int num = (given >> 8) & 0x3;
8223
8224 if (!num)
8225 func (stream, "{d%d}", regno);
8226 else if (num + regno >= 32)
8227 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
8228 else
8229 func (stream, "{d%d-d%d}", regno, regno + num);
8230 }
8231 break;
8232
8233
8234 case '0': case '1': case '2': case '3': case '4':
8235 case '5': case '6': case '7': case '8': case '9':
8236 {
8237 int width;
8238 unsigned long value;
8239
8240 c = arm_decode_bitfield (c, given, &value, &width);
8241
8242 switch (*c)
8243 {
8244 case 'r':
8245 func (stream, "%s", arm_regnames[value]);
8246 break;
8247 case 'd':
8248 func (stream, "%ld", value);
8249 value_in_comment = value;
8250 break;
8251 case 'e':
8252 func (stream, "%ld", (1ul << width) - value);
8253 break;
8254
8255 case 'S':
8256 case 'T':
8257 case 'U':
8258 /* Various width encodings. */
8259 {
8260 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
8261 int limit;
8262 unsigned low, high;
8263
8264 c++;
8265 if (*c >= '0' && *c <= '9')
8266 limit = *c - '0';
8267 else if (*c >= 'a' && *c <= 'f')
8268 limit = *c - 'a' + 10;
8269 else
8270 abort ();
8271 low = limit >> 2;
8272 high = limit & 3;
8273
8274 if (value < low || value > high)
8275 func (stream, "<illegal width %d>", base << value);
8276 else
8277 func (stream, "%d", base << value);
8278 }
8279 break;
8280 case 'R':
8281 if (given & (1 << 6))
8282 goto Q;
8283 /* FALLTHROUGH */
8284 case 'D':
8285 func (stream, "d%ld", value);
8286 break;
8287 case 'Q':
8288 Q:
8289 if (value & 1)
8290 func (stream, "<illegal reg q%ld.5>", value >> 1);
8291 else
8292 func (stream, "q%ld", value >> 1);
8293 break;
8294
8295 case '`':
8296 c++;
8297 if (value == 0)
8298 func (stream, "%c", *c);
8299 break;
8300 case '\'':
8301 c++;
8302 if (value == ((1ul << width) - 1))
8303 func (stream, "%c", *c);
8304 break;
8305 case '?':
8306 func (stream, "%c", c[(1 << width) - (int) value]);
8307 c += 1 << width;
8308 break;
8309 default:
8310 abort ();
8311 }
8312 }
8313 break;
8314
8315 default:
8316 abort ();
8317 }
8318 }
8319 else
8320 func (stream, "%c", *c);
8321 }
8322
8323 if (value_in_comment > 32 || value_in_comment < -16)
8324 func (stream, "\t; 0x%lx", value_in_comment);
8325
8326 if (is_unpredictable)
8327 func (stream, UNPREDICTABLE_INSTRUCTION);
8328
8329 return TRUE;
8330 }
8331 }
8332 return FALSE;
8333 }
8334
8335 /* Print one mve instruction on INFO->STREAM.
8336 Return TRUE if the instuction matched, FALSE if this is not a
8337 recognised mve instruction. */
8338
8339 static bfd_boolean
8340 print_insn_mve (struct disassemble_info *info, long given)
8341 {
8342 const struct mopcode32 *insn;
8343 void *stream = info->stream;
8344 fprintf_ftype func = info->fprintf_func;
8345
8346 for (insn = mve_opcodes; insn->assembler; insn++)
8347 {
8348 if (((given & insn->mask) == insn->value)
8349 && !is_mve_encoding_conflict (given, insn->mve_op))
8350 {
8351 signed long value_in_comment = 0;
8352 bfd_boolean is_unpredictable = FALSE;
8353 bfd_boolean is_undefined = FALSE;
8354 const char *c;
8355 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
8356 enum mve_undefined undefined_cond = UNDEF_NONE;
8357
8358 /* Most vector mve instruction are illegal in a it block.
8359 There are a few exceptions; check for them. */
8360 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
8361 {
8362 is_unpredictable = TRUE;
8363 unpredictable_cond = UNPRED_IT_BLOCK;
8364 }
8365 else if (is_mve_unpredictable (given, insn->mve_op,
8366 &unpredictable_cond))
8367 is_unpredictable = TRUE;
8368
8369 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
8370 is_undefined = TRUE;
8371
8372 for (c = insn->assembler; *c; c++)
8373 {
8374 if (*c == '%')
8375 {
8376 switch (*++c)
8377 {
8378 case '%':
8379 func (stream, "%%");
8380 break;
8381
8382 case 'a':
8383 /* Don't print anything for '+' as it is implied. */
8384 if (arm_decode_field (given, 23, 23) == 0)
8385 func (stream, "-");
8386 break;
8387
8388 case 'c':
8389 if (ifthen_state)
8390 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8391 break;
8392
8393 case 'd':
8394 print_mve_vld_str_addr (info, given, insn->mve_op);
8395 break;
8396
8397 case 'i':
8398 {
8399 long mve_mask = mve_extract_pred_mask (given);
8400 func (stream, "%s", mve_predicatenames[mve_mask]);
8401 }
8402 break;
8403
8404 case 'n':
8405 print_vec_condition (info, given, insn->mve_op);
8406 break;
8407
8408 case 'o':
8409 if (arm_decode_field (given, 0, 0) == 1)
8410 {
8411 unsigned long size
8412 = arm_decode_field (given, 4, 4)
8413 | (arm_decode_field (given, 6, 6) << 1);
8414
8415 func (stream, ", uxtw #%lu", size);
8416 }
8417 break;
8418
8419 case 'm':
8420 print_mve_rounding_mode (info, given, insn->mve_op);
8421 break;
8422
8423 case 's':
8424 print_mve_vcvt_size (info, given, insn->mve_op);
8425 break;
8426
8427 case 'u':
8428 {
8429 unsigned long op1 = arm_decode_field (given, 21, 22);
8430
8431 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
8432 {
8433 /* Check for signed. */
8434 if (arm_decode_field (given, 23, 23) == 0)
8435 {
8436 /* We don't print 's' for S32. */
8437 if ((arm_decode_field (given, 5, 6) == 0)
8438 && ((op1 == 0) || (op1 == 1)))
8439 ;
8440 else
8441 func (stream, "s");
8442 }
8443 else
8444 func (stream, "u");
8445 }
8446 else
8447 {
8448 if (arm_decode_field (given, 28, 28) == 0)
8449 func (stream, "s");
8450 else
8451 func (stream, "u");
8452 }
8453 }
8454 break;
8455
8456 case 'v':
8457 print_instruction_predicate (info);
8458 break;
8459
8460 case 'w':
8461 if (arm_decode_field (given, 21, 21) == 1)
8462 func (stream, "!");
8463 break;
8464
8465 case 'B':
8466 print_mve_register_blocks (info, given, insn->mve_op);
8467 break;
8468
8469 case 'E':
8470 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
8471
8472 print_simd_imm8 (info, given, 28, insn);
8473 break;
8474
8475 case 'N':
8476 print_mve_vmov_index (info, given);
8477 break;
8478
8479 case 'T':
8480 if (arm_decode_field (given, 12, 12) == 0)
8481 func (stream, "b");
8482 else
8483 func (stream, "t");
8484 break;
8485
8486 case 'X':
8487 if (arm_decode_field (given, 12, 12) == 1)
8488 func (stream, "x");
8489 break;
8490
8491 case '0': case '1': case '2': case '3': case '4':
8492 case '5': case '6': case '7': case '8': case '9':
8493 {
8494 int width;
8495 unsigned long value;
8496
8497 c = arm_decode_bitfield (c, given, &value, &width);
8498
8499 switch (*c)
8500 {
8501 case 'Z':
8502 if (value == 13)
8503 is_unpredictable = TRUE;
8504 else if (value == 15)
8505 func (stream, "zr");
8506 else
8507 func (stream, "%s", arm_regnames[value]);
8508 break;
8509 case 's':
8510 print_mve_size (info,
8511 value,
8512 insn->mve_op);
8513 break;
8514 case 'A':
8515 if (value == 1)
8516 func (stream, "a");
8517 break;
8518 case 'h':
8519 {
8520 unsigned int odd_reg = (value << 1) | 1;
8521 func (stream, "%s", arm_regnames[odd_reg]);
8522 }
8523 break;
8524 case 'i':
8525 {
8526 unsigned long imm
8527 = arm_decode_field (given, 0, 6);
8528 unsigned long mod_imm = imm;
8529
8530 switch (insn->mve_op)
8531 {
8532 case MVE_VLDRW_GATHER_T5:
8533 case MVE_VSTRW_SCATTER_T5:
8534 mod_imm = mod_imm << 2;
8535 break;
8536 case MVE_VSTRD_SCATTER_T6:
8537 case MVE_VLDRD_GATHER_T6:
8538 mod_imm = mod_imm << 3;
8539 break;
8540
8541 default:
8542 break;
8543 }
8544
8545 func (stream, "%lu", mod_imm);
8546 }
8547 break;
8548 case 'k':
8549 func (stream, "%lu", 64 - value);
8550 break;
8551 case 'l':
8552 {
8553 unsigned int even_reg = value << 1;
8554 func (stream, "%s", arm_regnames[even_reg]);
8555 }
8556 break;
8557 case 'u':
8558 switch (value)
8559 {
8560 case 0:
8561 func (stream, "1");
8562 break;
8563 case 1:
8564 func (stream, "2");
8565 break;
8566 case 2:
8567 func (stream, "4");
8568 break;
8569 case 3:
8570 func (stream, "8");
8571 break;
8572 default:
8573 break;
8574 }
8575 break;
8576 case 'o':
8577 print_mve_rotate (info, value, width);
8578 break;
8579 case 'r':
8580 func (stream, "%s", arm_regnames[value]);
8581 break;
8582 case 'd':
8583 if (insn->mve_op == MVE_VQSHL_T2
8584 || insn->mve_op == MVE_VQSHLU_T3
8585 || insn->mve_op == MVE_VRSHR
8586 || insn->mve_op == MVE_VRSHRN
8587 || insn->mve_op == MVE_VSHL_T1
8588 || insn->mve_op == MVE_VSHLL_T1
8589 || insn->mve_op == MVE_VSHR
8590 || insn->mve_op == MVE_VSHRN
8591 || insn->mve_op == MVE_VSLI
8592 || insn->mve_op == MVE_VSRI)
8593 print_mve_shift_n (info, given, insn->mve_op);
8594 else if (insn->mve_op == MVE_VSHLL_T2)
8595 {
8596 switch (value)
8597 {
8598 case 0x00:
8599 func (stream, "8");
8600 break;
8601 case 0x01:
8602 func (stream, "16");
8603 break;
8604 case 0x10:
8605 print_mve_undefined (info, UNDEF_SIZE_0);
8606 break;
8607 default:
8608 assert (0);
8609 break;
8610 }
8611 }
8612 else
8613 {
8614 if (insn->mve_op == MVE_VSHLC && value == 0)
8615 value = 32;
8616 func (stream, "%ld", value);
8617 value_in_comment = value;
8618 }
8619 break;
8620 case 'F':
8621 func (stream, "s%ld", value);
8622 break;
8623 case 'Q':
8624 if (value & 0x8)
8625 func (stream, "<illegal reg q%ld.5>", value);
8626 else
8627 func (stream, "q%ld", value);
8628 break;
8629 case 'x':
8630 func (stream, "0x%08lx", value);
8631 break;
8632 default:
8633 abort ();
8634 }
8635 break;
8636 default:
8637 abort ();
8638 }
8639 }
8640 }
8641 else
8642 func (stream, "%c", *c);
8643 }
8644
8645 if (value_in_comment > 32 || value_in_comment < -16)
8646 func (stream, "\t; 0x%lx", value_in_comment);
8647
8648 if (is_unpredictable)
8649 print_mve_unpredictable (info, unpredictable_cond);
8650
8651 if (is_undefined)
8652 print_mve_undefined (info, undefined_cond);
8653
8654 if ((vpt_block_state.in_vpt_block == FALSE)
8655 && !ifthen_state
8656 && (is_vpt_instruction (given) == TRUE))
8657 mark_inside_vpt_block (given);
8658 else if (vpt_block_state.in_vpt_block == TRUE)
8659 update_vpt_block_state ();
8660
8661 return TRUE;
8662 }
8663 }
8664 return FALSE;
8665 }
8666
8667
8668 /* Return the name of a v7A special register. */
8669
8670 static const char *
8671 banked_regname (unsigned reg)
8672 {
8673 switch (reg)
8674 {
8675 case 15: return "CPSR";
8676 case 32: return "R8_usr";
8677 case 33: return "R9_usr";
8678 case 34: return "R10_usr";
8679 case 35: return "R11_usr";
8680 case 36: return "R12_usr";
8681 case 37: return "SP_usr";
8682 case 38: return "LR_usr";
8683 case 40: return "R8_fiq";
8684 case 41: return "R9_fiq";
8685 case 42: return "R10_fiq";
8686 case 43: return "R11_fiq";
8687 case 44: return "R12_fiq";
8688 case 45: return "SP_fiq";
8689 case 46: return "LR_fiq";
8690 case 48: return "LR_irq";
8691 case 49: return "SP_irq";
8692 case 50: return "LR_svc";
8693 case 51: return "SP_svc";
8694 case 52: return "LR_abt";
8695 case 53: return "SP_abt";
8696 case 54: return "LR_und";
8697 case 55: return "SP_und";
8698 case 60: return "LR_mon";
8699 case 61: return "SP_mon";
8700 case 62: return "ELR_hyp";
8701 case 63: return "SP_hyp";
8702 case 79: return "SPSR";
8703 case 110: return "SPSR_fiq";
8704 case 112: return "SPSR_irq";
8705 case 114: return "SPSR_svc";
8706 case 116: return "SPSR_abt";
8707 case 118: return "SPSR_und";
8708 case 124: return "SPSR_mon";
8709 case 126: return "SPSR_hyp";
8710 default: return NULL;
8711 }
8712 }
8713
8714 /* Return the name of the DMB/DSB option. */
8715 static const char *
8716 data_barrier_option (unsigned option)
8717 {
8718 switch (option & 0xf)
8719 {
8720 case 0xf: return "sy";
8721 case 0xe: return "st";
8722 case 0xd: return "ld";
8723 case 0xb: return "ish";
8724 case 0xa: return "ishst";
8725 case 0x9: return "ishld";
8726 case 0x7: return "un";
8727 case 0x6: return "unst";
8728 case 0x5: return "nshld";
8729 case 0x3: return "osh";
8730 case 0x2: return "oshst";
8731 case 0x1: return "oshld";
8732 default: return NULL;
8733 }
8734 }
8735
8736 /* Print one ARM instruction from PC on INFO->STREAM. */
8737
8738 static void
8739 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
8740 {
8741 const struct opcode32 *insn;
8742 void *stream = info->stream;
8743 fprintf_ftype func = info->fprintf_func;
8744 struct arm_private_data *private_data = info->private_data;
8745
8746 if (print_insn_coprocessor (pc, info, given, FALSE))
8747 return;
8748
8749 if (print_insn_neon (info, given, FALSE))
8750 return;
8751
8752 for (insn = arm_opcodes; insn->assembler; insn++)
8753 {
8754 if ((given & insn->mask) != insn->value)
8755 continue;
8756
8757 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
8758 continue;
8759
8760 /* Special case: an instruction with all bits set in the condition field
8761 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
8762 or by the catchall at the end of the table. */
8763 if ((given & 0xF0000000) != 0xF0000000
8764 || (insn->mask & 0xF0000000) == 0xF0000000
8765 || (insn->mask == 0 && insn->value == 0))
8766 {
8767 unsigned long u_reg = 16;
8768 unsigned long U_reg = 16;
8769 bfd_boolean is_unpredictable = FALSE;
8770 signed long value_in_comment = 0;
8771 const char *c;
8772
8773 for (c = insn->assembler; *c; c++)
8774 {
8775 if (*c == '%')
8776 {
8777 bfd_boolean allow_unpredictable = FALSE;
8778
8779 switch (*++c)
8780 {
8781 case '%':
8782 func (stream, "%%");
8783 break;
8784
8785 case 'a':
8786 value_in_comment = print_arm_address (pc, info, given);
8787 break;
8788
8789 case 'P':
8790 /* Set P address bit and use normal address
8791 printing routine. */
8792 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
8793 break;
8794
8795 case 'S':
8796 allow_unpredictable = TRUE;
8797 /* Fall through. */
8798 case 's':
8799 if ((given & 0x004f0000) == 0x004f0000)
8800 {
8801 /* PC relative with immediate offset. */
8802 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
8803
8804 if (PRE_BIT_SET)
8805 {
8806 /* Elide positive zero offset. */
8807 if (offset || NEGATIVE_BIT_SET)
8808 func (stream, "[pc, #%s%d]\t; ",
8809 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8810 else
8811 func (stream, "[pc]\t; ");
8812 if (NEGATIVE_BIT_SET)
8813 offset = -offset;
8814 info->print_address_func (offset + pc + 8, info);
8815 }
8816 else
8817 {
8818 /* Always show the offset. */
8819 func (stream, "[pc], #%s%d",
8820 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8821 if (! allow_unpredictable)
8822 is_unpredictable = TRUE;
8823 }
8824 }
8825 else
8826 {
8827 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
8828
8829 func (stream, "[%s",
8830 arm_regnames[(given >> 16) & 0xf]);
8831
8832 if (PRE_BIT_SET)
8833 {
8834 if (IMMEDIATE_BIT_SET)
8835 {
8836 /* Elide offset for non-writeback
8837 positive zero. */
8838 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
8839 || offset)
8840 func (stream, ", #%s%d",
8841 NEGATIVE_BIT_SET ? "-" : "", offset);
8842
8843 if (NEGATIVE_BIT_SET)
8844 offset = -offset;
8845
8846 value_in_comment = offset;
8847 }
8848 else
8849 {
8850 /* Register Offset or Register Pre-Indexed. */
8851 func (stream, ", %s%s",
8852 NEGATIVE_BIT_SET ? "-" : "",
8853 arm_regnames[given & 0xf]);
8854
8855 /* Writing back to the register that is the source/
8856 destination of the load/store is unpredictable. */
8857 if (! allow_unpredictable
8858 && WRITEBACK_BIT_SET
8859 && ((given & 0xf) == ((given >> 12) & 0xf)))
8860 is_unpredictable = TRUE;
8861 }
8862
8863 func (stream, "]%s",
8864 WRITEBACK_BIT_SET ? "!" : "");
8865 }
8866 else
8867 {
8868 if (IMMEDIATE_BIT_SET)
8869 {
8870 /* Immediate Post-indexed. */
8871 /* PR 10924: Offset must be printed, even if it is zero. */
8872 func (stream, "], #%s%d",
8873 NEGATIVE_BIT_SET ? "-" : "", offset);
8874 if (NEGATIVE_BIT_SET)
8875 offset = -offset;
8876 value_in_comment = offset;
8877 }
8878 else
8879 {
8880 /* Register Post-indexed. */
8881 func (stream, "], %s%s",
8882 NEGATIVE_BIT_SET ? "-" : "",
8883 arm_regnames[given & 0xf]);
8884
8885 /* Writing back to the register that is the source/
8886 destination of the load/store is unpredictable. */
8887 if (! allow_unpredictable
8888 && (given & 0xf) == ((given >> 12) & 0xf))
8889 is_unpredictable = TRUE;
8890 }
8891
8892 if (! allow_unpredictable)
8893 {
8894 /* Writeback is automatically implied by post- addressing.
8895 Setting the W bit is unnecessary and ARM specify it as
8896 being unpredictable. */
8897 if (WRITEBACK_BIT_SET
8898 /* Specifying the PC register as the post-indexed
8899 registers is also unpredictable. */
8900 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
8901 is_unpredictable = TRUE;
8902 }
8903 }
8904 }
8905 break;
8906
8907 case 'b':
8908 {
8909 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
8910 info->print_address_func (disp * 4 + pc + 8, info);
8911 }
8912 break;
8913
8914 case 'c':
8915 if (((given >> 28) & 0xf) != 0xe)
8916 func (stream, "%s",
8917 arm_conditional [(given >> 28) & 0xf]);
8918 break;
8919
8920 case 'm':
8921 {
8922 int started = 0;
8923 int reg;
8924
8925 func (stream, "{");
8926 for (reg = 0; reg < 16; reg++)
8927 if ((given & (1 << reg)) != 0)
8928 {
8929 if (started)
8930 func (stream, ", ");
8931 started = 1;
8932 func (stream, "%s", arm_regnames[reg]);
8933 }
8934 func (stream, "}");
8935 if (! started)
8936 is_unpredictable = TRUE;
8937 }
8938 break;
8939
8940 case 'q':
8941 arm_decode_shift (given, func, stream, FALSE);
8942 break;
8943
8944 case 'o':
8945 if ((given & 0x02000000) != 0)
8946 {
8947 unsigned int rotate = (given & 0xf00) >> 7;
8948 unsigned int immed = (given & 0xff);
8949 unsigned int a, i;
8950
8951 a = (((immed << (32 - rotate))
8952 | (immed >> rotate)) & 0xffffffff);
8953 /* If there is another encoding with smaller rotate,
8954 the rotate should be specified directly. */
8955 for (i = 0; i < 32; i += 2)
8956 if ((a << i | a >> (32 - i)) <= 0xff)
8957 break;
8958
8959 if (i != rotate)
8960 func (stream, "#%d, %d", immed, rotate);
8961 else
8962 func (stream, "#%d", a);
8963 value_in_comment = a;
8964 }
8965 else
8966 arm_decode_shift (given, func, stream, TRUE);
8967 break;
8968
8969 case 'p':
8970 if ((given & 0x0000f000) == 0x0000f000)
8971 {
8972 arm_feature_set arm_ext_v6 =
8973 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
8974
8975 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
8976 mechanism for setting PSR flag bits. They are
8977 obsolete in V6 onwards. */
8978 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
8979 arm_ext_v6))
8980 func (stream, "p");
8981 else
8982 is_unpredictable = TRUE;
8983 }
8984 break;
8985
8986 case 't':
8987 if ((given & 0x01200000) == 0x00200000)
8988 func (stream, "t");
8989 break;
8990
8991 case 'A':
8992 {
8993 int offset = given & 0xff;
8994
8995 value_in_comment = offset * 4;
8996 if (NEGATIVE_BIT_SET)
8997 value_in_comment = - value_in_comment;
8998
8999 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
9000
9001 if (PRE_BIT_SET)
9002 {
9003 if (offset)
9004 func (stream, ", #%d]%s",
9005 (int) value_in_comment,
9006 WRITEBACK_BIT_SET ? "!" : "");
9007 else
9008 func (stream, "]");
9009 }
9010 else
9011 {
9012 func (stream, "]");
9013
9014 if (WRITEBACK_BIT_SET)
9015 {
9016 if (offset)
9017 func (stream, ", #%d", (int) value_in_comment);
9018 }
9019 else
9020 {
9021 func (stream, ", {%d}", (int) offset);
9022 value_in_comment = offset;
9023 }
9024 }
9025 }
9026 break;
9027
9028 case 'B':
9029 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9030 {
9031 bfd_vma address;
9032 bfd_vma offset = 0;
9033
9034 if (! NEGATIVE_BIT_SET)
9035 /* Is signed, hi bits should be ones. */
9036 offset = (-1) ^ 0x00ffffff;
9037
9038 /* Offset is (SignExtend(offset field)<<2). */
9039 offset += given & 0x00ffffff;
9040 offset <<= 2;
9041 address = offset + pc + 8;
9042
9043 if (given & 0x01000000)
9044 /* H bit allows addressing to 2-byte boundaries. */
9045 address += 2;
9046
9047 info->print_address_func (address, info);
9048 }
9049 break;
9050
9051 case 'C':
9052 if ((given & 0x02000200) == 0x200)
9053 {
9054 const char * name;
9055 unsigned sysm = (given & 0x004f0000) >> 16;
9056
9057 sysm |= (given & 0x300) >> 4;
9058 name = banked_regname (sysm);
9059
9060 if (name != NULL)
9061 func (stream, "%s", name);
9062 else
9063 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9064 }
9065 else
9066 {
9067 func (stream, "%cPSR_",
9068 (given & 0x00400000) ? 'S' : 'C');
9069 if (given & 0x80000)
9070 func (stream, "f");
9071 if (given & 0x40000)
9072 func (stream, "s");
9073 if (given & 0x20000)
9074 func (stream, "x");
9075 if (given & 0x10000)
9076 func (stream, "c");
9077 }
9078 break;
9079
9080 case 'U':
9081 if ((given & 0xf0) == 0x60)
9082 {
9083 switch (given & 0xf)
9084 {
9085 case 0xf: func (stream, "sy"); break;
9086 default:
9087 func (stream, "#%d", (int) given & 0xf);
9088 break;
9089 }
9090 }
9091 else
9092 {
9093 const char * opt = data_barrier_option (given & 0xf);
9094 if (opt != NULL)
9095 func (stream, "%s", opt);
9096 else
9097 func (stream, "#%d", (int) given & 0xf);
9098 }
9099 break;
9100
9101 case '0': case '1': case '2': case '3': case '4':
9102 case '5': case '6': case '7': case '8': case '9':
9103 {
9104 int width;
9105 unsigned long value;
9106
9107 c = arm_decode_bitfield (c, given, &value, &width);
9108
9109 switch (*c)
9110 {
9111 case 'R':
9112 if (value == 15)
9113 is_unpredictable = TRUE;
9114 /* Fall through. */
9115 case 'r':
9116 case 'T':
9117 /* We want register + 1 when decoding T. */
9118 if (*c == 'T')
9119 ++value;
9120
9121 if (c[1] == 'u')
9122 {
9123 /* Eat the 'u' character. */
9124 ++ c;
9125
9126 if (u_reg == value)
9127 is_unpredictable = TRUE;
9128 u_reg = value;
9129 }
9130 if (c[1] == 'U')
9131 {
9132 /* Eat the 'U' character. */
9133 ++ c;
9134
9135 if (U_reg == value)
9136 is_unpredictable = TRUE;
9137 U_reg = value;
9138 }
9139 func (stream, "%s", arm_regnames[value]);
9140 break;
9141 case 'd':
9142 func (stream, "%ld", value);
9143 value_in_comment = value;
9144 break;
9145 case 'b':
9146 func (stream, "%ld", value * 8);
9147 value_in_comment = value * 8;
9148 break;
9149 case 'W':
9150 func (stream, "%ld", value + 1);
9151 value_in_comment = value + 1;
9152 break;
9153 case 'x':
9154 func (stream, "0x%08lx", value);
9155
9156 /* Some SWI instructions have special
9157 meanings. */
9158 if ((given & 0x0fffffff) == 0x0FF00000)
9159 func (stream, "\t; IMB");
9160 else if ((given & 0x0fffffff) == 0x0FF00001)
9161 func (stream, "\t; IMBRange");
9162 break;
9163 case 'X':
9164 func (stream, "%01lx", value & 0xf);
9165 value_in_comment = value;
9166 break;
9167 case '`':
9168 c++;
9169 if (value == 0)
9170 func (stream, "%c", *c);
9171 break;
9172 case '\'':
9173 c++;
9174 if (value == ((1ul << width) - 1))
9175 func (stream, "%c", *c);
9176 break;
9177 case '?':
9178 func (stream, "%c", c[(1 << width) - (int) value]);
9179 c += 1 << width;
9180 break;
9181 default:
9182 abort ();
9183 }
9184 }
9185 break;
9186
9187 case 'e':
9188 {
9189 int imm;
9190
9191 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
9192 func (stream, "%d", imm);
9193 value_in_comment = imm;
9194 }
9195 break;
9196
9197 case 'E':
9198 /* LSB and WIDTH fields of BFI or BFC. The machine-
9199 language instruction encodes LSB and MSB. */
9200 {
9201 long msb = (given & 0x001f0000) >> 16;
9202 long lsb = (given & 0x00000f80) >> 7;
9203 long w = msb - lsb + 1;
9204
9205 if (w > 0)
9206 func (stream, "#%lu, #%lu", lsb, w);
9207 else
9208 func (stream, "(invalid: %lu:%lu)", lsb, msb);
9209 }
9210 break;
9211
9212 case 'R':
9213 /* Get the PSR/banked register name. */
9214 {
9215 const char * name;
9216 unsigned sysm = (given & 0x004f0000) >> 16;
9217
9218 sysm |= (given & 0x300) >> 4;
9219 name = banked_regname (sysm);
9220
9221 if (name != NULL)
9222 func (stream, "%s", name);
9223 else
9224 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9225 }
9226 break;
9227
9228 case 'V':
9229 /* 16-bit unsigned immediate from a MOVT or MOVW
9230 instruction, encoded in bits 0:11 and 15:19. */
9231 {
9232 long hi = (given & 0x000f0000) >> 4;
9233 long lo = (given & 0x00000fff);
9234 long imm16 = hi | lo;
9235
9236 func (stream, "#%lu", imm16);
9237 value_in_comment = imm16;
9238 }
9239 break;
9240
9241 default:
9242 abort ();
9243 }
9244 }
9245 else
9246 func (stream, "%c", *c);
9247 }
9248
9249 if (value_in_comment > 32 || value_in_comment < -16)
9250 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
9251
9252 if (is_unpredictable)
9253 func (stream, UNPREDICTABLE_INSTRUCTION);
9254
9255 return;
9256 }
9257 }
9258 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
9259 return;
9260 }
9261
9262 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
9263
9264 static void
9265 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
9266 {
9267 const struct opcode16 *insn;
9268 void *stream = info->stream;
9269 fprintf_ftype func = info->fprintf_func;
9270
9271 for (insn = thumb_opcodes; insn->assembler; insn++)
9272 if ((given & insn->mask) == insn->value)
9273 {
9274 signed long value_in_comment = 0;
9275 const char *c = insn->assembler;
9276
9277 for (; *c; c++)
9278 {
9279 int domaskpc = 0;
9280 int domasklr = 0;
9281
9282 if (*c != '%')
9283 {
9284 func (stream, "%c", *c);
9285 continue;
9286 }
9287
9288 switch (*++c)
9289 {
9290 case '%':
9291 func (stream, "%%");
9292 break;
9293
9294 case 'c':
9295 if (ifthen_state)
9296 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9297 break;
9298
9299 case 'C':
9300 if (ifthen_state)
9301 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9302 else
9303 func (stream, "s");
9304 break;
9305
9306 case 'I':
9307 {
9308 unsigned int tmp;
9309
9310 ifthen_next_state = given & 0xff;
9311 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
9312 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
9313 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
9314 }
9315 break;
9316
9317 case 'x':
9318 if (ifthen_next_state)
9319 func (stream, "\t; unpredictable branch in IT block\n");
9320 break;
9321
9322 case 'X':
9323 if (ifthen_state)
9324 func (stream, "\t; unpredictable <IT:%s>",
9325 arm_conditional[IFTHEN_COND]);
9326 break;
9327
9328 case 'S':
9329 {
9330 long reg;
9331
9332 reg = (given >> 3) & 0x7;
9333 if (given & (1 << 6))
9334 reg += 8;
9335
9336 func (stream, "%s", arm_regnames[reg]);
9337 }
9338 break;
9339
9340 case 'D':
9341 {
9342 long reg;
9343
9344 reg = given & 0x7;
9345 if (given & (1 << 7))
9346 reg += 8;
9347
9348 func (stream, "%s", arm_regnames[reg]);
9349 }
9350 break;
9351
9352 case 'N':
9353 if (given & (1 << 8))
9354 domasklr = 1;
9355 /* Fall through. */
9356 case 'O':
9357 if (*c == 'O' && (given & (1 << 8)))
9358 domaskpc = 1;
9359 /* Fall through. */
9360 case 'M':
9361 {
9362 int started = 0;
9363 int reg;
9364
9365 func (stream, "{");
9366
9367 /* It would be nice if we could spot
9368 ranges, and generate the rS-rE format: */
9369 for (reg = 0; (reg < 8); reg++)
9370 if ((given & (1 << reg)) != 0)
9371 {
9372 if (started)
9373 func (stream, ", ");
9374 started = 1;
9375 func (stream, "%s", arm_regnames[reg]);
9376 }
9377
9378 if (domasklr)
9379 {
9380 if (started)
9381 func (stream, ", ");
9382 started = 1;
9383 func (stream, "%s", arm_regnames[14] /* "lr" */);
9384 }
9385
9386 if (domaskpc)
9387 {
9388 if (started)
9389 func (stream, ", ");
9390 func (stream, "%s", arm_regnames[15] /* "pc" */);
9391 }
9392
9393 func (stream, "}");
9394 }
9395 break;
9396
9397 case 'W':
9398 /* Print writeback indicator for a LDMIA. We are doing a
9399 writeback if the base register is not in the register
9400 mask. */
9401 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
9402 func (stream, "!");
9403 break;
9404
9405 case 'b':
9406 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
9407 {
9408 bfd_vma address = (pc + 4
9409 + ((given & 0x00f8) >> 2)
9410 + ((given & 0x0200) >> 3));
9411 info->print_address_func (address, info);
9412 }
9413 break;
9414
9415 case 's':
9416 /* Right shift immediate -- bits 6..10; 1-31 print
9417 as themselves, 0 prints as 32. */
9418 {
9419 long imm = (given & 0x07c0) >> 6;
9420 if (imm == 0)
9421 imm = 32;
9422 func (stream, "#%ld", imm);
9423 }
9424 break;
9425
9426 case '0': case '1': case '2': case '3': case '4':
9427 case '5': case '6': case '7': case '8': case '9':
9428 {
9429 int bitstart = *c++ - '0';
9430 int bitend = 0;
9431
9432 while (*c >= '0' && *c <= '9')
9433 bitstart = (bitstart * 10) + *c++ - '0';
9434
9435 switch (*c)
9436 {
9437 case '-':
9438 {
9439 bfd_vma reg;
9440
9441 c++;
9442 while (*c >= '0' && *c <= '9')
9443 bitend = (bitend * 10) + *c++ - '0';
9444 if (!bitend)
9445 abort ();
9446 reg = given >> bitstart;
9447 reg &= (2 << (bitend - bitstart)) - 1;
9448
9449 switch (*c)
9450 {
9451 case 'r':
9452 func (stream, "%s", arm_regnames[reg]);
9453 break;
9454
9455 case 'd':
9456 func (stream, "%ld", (long) reg);
9457 value_in_comment = reg;
9458 break;
9459
9460 case 'H':
9461 func (stream, "%ld", (long) (reg << 1));
9462 value_in_comment = reg << 1;
9463 break;
9464
9465 case 'W':
9466 func (stream, "%ld", (long) (reg << 2));
9467 value_in_comment = reg << 2;
9468 break;
9469
9470 case 'a':
9471 /* PC-relative address -- the bottom two
9472 bits of the address are dropped
9473 before the calculation. */
9474 info->print_address_func
9475 (((pc + 4) & ~3) + (reg << 2), info);
9476 value_in_comment = 0;
9477 break;
9478
9479 case 'x':
9480 func (stream, "0x%04lx", (long) reg);
9481 break;
9482
9483 case 'B':
9484 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
9485 info->print_address_func (reg * 2 + pc + 4, info);
9486 value_in_comment = 0;
9487 break;
9488
9489 case 'c':
9490 func (stream, "%s", arm_conditional [reg]);
9491 break;
9492
9493 default:
9494 abort ();
9495 }
9496 }
9497 break;
9498
9499 case '\'':
9500 c++;
9501 if ((given & (1 << bitstart)) != 0)
9502 func (stream, "%c", *c);
9503 break;
9504
9505 case '?':
9506 ++c;
9507 if ((given & (1 << bitstart)) != 0)
9508 func (stream, "%c", *c++);
9509 else
9510 func (stream, "%c", *++c);
9511 break;
9512
9513 default:
9514 abort ();
9515 }
9516 }
9517 break;
9518
9519 default:
9520 abort ();
9521 }
9522 }
9523
9524 if (value_in_comment > 32 || value_in_comment < -16)
9525 func (stream, "\t; 0x%lx", value_in_comment);
9526 return;
9527 }
9528
9529 /* No match. */
9530 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
9531 return;
9532 }
9533
9534 /* Return the name of an V7M special register. */
9535
9536 static const char *
9537 psr_name (int regno)
9538 {
9539 switch (regno)
9540 {
9541 case 0x0: return "APSR";
9542 case 0x1: return "IAPSR";
9543 case 0x2: return "EAPSR";
9544 case 0x3: return "PSR";
9545 case 0x5: return "IPSR";
9546 case 0x6: return "EPSR";
9547 case 0x7: return "IEPSR";
9548 case 0x8: return "MSP";
9549 case 0x9: return "PSP";
9550 case 0xa: return "MSPLIM";
9551 case 0xb: return "PSPLIM";
9552 case 0x10: return "PRIMASK";
9553 case 0x11: return "BASEPRI";
9554 case 0x12: return "BASEPRI_MAX";
9555 case 0x13: return "FAULTMASK";
9556 case 0x14: return "CONTROL";
9557 case 0x88: return "MSP_NS";
9558 case 0x89: return "PSP_NS";
9559 case 0x8a: return "MSPLIM_NS";
9560 case 0x8b: return "PSPLIM_NS";
9561 case 0x90: return "PRIMASK_NS";
9562 case 0x91: return "BASEPRI_NS";
9563 case 0x93: return "FAULTMASK_NS";
9564 case 0x94: return "CONTROL_NS";
9565 case 0x98: return "SP_NS";
9566 default: return "<unknown>";
9567 }
9568 }
9569
9570 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
9571
9572 static void
9573 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
9574 {
9575 const struct opcode32 *insn;
9576 void *stream = info->stream;
9577 fprintf_ftype func = info->fprintf_func;
9578 bfd_boolean is_mve = is_mve_architecture (info);
9579
9580 if (print_insn_coprocessor (pc, info, given, TRUE))
9581 return;
9582
9583 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
9584 return;
9585
9586 if (is_mve && print_insn_mve (info, given))
9587 return;
9588
9589 for (insn = thumb32_opcodes; insn->assembler; insn++)
9590 if ((given & insn->mask) == insn->value)
9591 {
9592 bfd_boolean is_clrm = FALSE;
9593 bfd_boolean is_unpredictable = FALSE;
9594 signed long value_in_comment = 0;
9595 const char *c = insn->assembler;
9596
9597 for (; *c; c++)
9598 {
9599 if (*c != '%')
9600 {
9601 func (stream, "%c", *c);
9602 continue;
9603 }
9604
9605 switch (*++c)
9606 {
9607 case '%':
9608 func (stream, "%%");
9609 break;
9610
9611 case 'c':
9612 if (ifthen_state)
9613 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9614 break;
9615
9616 case 'x':
9617 if (ifthen_next_state)
9618 func (stream, "\t; unpredictable branch in IT block\n");
9619 break;
9620
9621 case 'X':
9622 if (ifthen_state)
9623 func (stream, "\t; unpredictable <IT:%s>",
9624 arm_conditional[IFTHEN_COND]);
9625 break;
9626
9627 case 'I':
9628 {
9629 unsigned int imm12 = 0;
9630
9631 imm12 |= (given & 0x000000ffu);
9632 imm12 |= (given & 0x00007000u) >> 4;
9633 imm12 |= (given & 0x04000000u) >> 15;
9634 func (stream, "#%u", imm12);
9635 value_in_comment = imm12;
9636 }
9637 break;
9638
9639 case 'M':
9640 {
9641 unsigned int bits = 0, imm, imm8, mod;
9642
9643 bits |= (given & 0x000000ffu);
9644 bits |= (given & 0x00007000u) >> 4;
9645 bits |= (given & 0x04000000u) >> 15;
9646 imm8 = (bits & 0x0ff);
9647 mod = (bits & 0xf00) >> 8;
9648 switch (mod)
9649 {
9650 case 0: imm = imm8; break;
9651 case 1: imm = ((imm8 << 16) | imm8); break;
9652 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
9653 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
9654 default:
9655 mod = (bits & 0xf80) >> 7;
9656 imm8 = (bits & 0x07f) | 0x80;
9657 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
9658 }
9659 func (stream, "#%u", imm);
9660 value_in_comment = imm;
9661 }
9662 break;
9663
9664 case 'J':
9665 {
9666 unsigned int imm = 0;
9667
9668 imm |= (given & 0x000000ffu);
9669 imm |= (given & 0x00007000u) >> 4;
9670 imm |= (given & 0x04000000u) >> 15;
9671 imm |= (given & 0x000f0000u) >> 4;
9672 func (stream, "#%u", imm);
9673 value_in_comment = imm;
9674 }
9675 break;
9676
9677 case 'K':
9678 {
9679 unsigned int imm = 0;
9680
9681 imm |= (given & 0x000f0000u) >> 16;
9682 imm |= (given & 0x00000ff0u) >> 0;
9683 imm |= (given & 0x0000000fu) << 12;
9684 func (stream, "#%u", imm);
9685 value_in_comment = imm;
9686 }
9687 break;
9688
9689 case 'H':
9690 {
9691 unsigned int imm = 0;
9692
9693 imm |= (given & 0x000f0000u) >> 4;
9694 imm |= (given & 0x00000fffu) >> 0;
9695 func (stream, "#%u", imm);
9696 value_in_comment = imm;
9697 }
9698 break;
9699
9700 case 'V':
9701 {
9702 unsigned int imm = 0;
9703
9704 imm |= (given & 0x00000fffu);
9705 imm |= (given & 0x000f0000u) >> 4;
9706 func (stream, "#%u", imm);
9707 value_in_comment = imm;
9708 }
9709 break;
9710
9711 case 'S':
9712 {
9713 unsigned int reg = (given & 0x0000000fu);
9714 unsigned int stp = (given & 0x00000030u) >> 4;
9715 unsigned int imm = 0;
9716 imm |= (given & 0x000000c0u) >> 6;
9717 imm |= (given & 0x00007000u) >> 10;
9718
9719 func (stream, "%s", arm_regnames[reg]);
9720 switch (stp)
9721 {
9722 case 0:
9723 if (imm > 0)
9724 func (stream, ", lsl #%u", imm);
9725 break;
9726
9727 case 1:
9728 if (imm == 0)
9729 imm = 32;
9730 func (stream, ", lsr #%u", imm);
9731 break;
9732
9733 case 2:
9734 if (imm == 0)
9735 imm = 32;
9736 func (stream, ", asr #%u", imm);
9737 break;
9738
9739 case 3:
9740 if (imm == 0)
9741 func (stream, ", rrx");
9742 else
9743 func (stream, ", ror #%u", imm);
9744 }
9745 }
9746 break;
9747
9748 case 'a':
9749 {
9750 unsigned int Rn = (given & 0x000f0000) >> 16;
9751 unsigned int U = ! NEGATIVE_BIT_SET;
9752 unsigned int op = (given & 0x00000f00) >> 8;
9753 unsigned int i12 = (given & 0x00000fff);
9754 unsigned int i8 = (given & 0x000000ff);
9755 bfd_boolean writeback = FALSE, postind = FALSE;
9756 bfd_vma offset = 0;
9757
9758 func (stream, "[%s", arm_regnames[Rn]);
9759 if (U) /* 12-bit positive immediate offset. */
9760 {
9761 offset = i12;
9762 if (Rn != 15)
9763 value_in_comment = offset;
9764 }
9765 else if (Rn == 15) /* 12-bit negative immediate offset. */
9766 offset = - (int) i12;
9767 else if (op == 0x0) /* Shifted register offset. */
9768 {
9769 unsigned int Rm = (i8 & 0x0f);
9770 unsigned int sh = (i8 & 0x30) >> 4;
9771
9772 func (stream, ", %s", arm_regnames[Rm]);
9773 if (sh)
9774 func (stream, ", lsl #%u", sh);
9775 func (stream, "]");
9776 break;
9777 }
9778 else switch (op)
9779 {
9780 case 0xE: /* 8-bit positive immediate offset. */
9781 offset = i8;
9782 break;
9783
9784 case 0xC: /* 8-bit negative immediate offset. */
9785 offset = -i8;
9786 break;
9787
9788 case 0xF: /* 8-bit + preindex with wb. */
9789 offset = i8;
9790 writeback = TRUE;
9791 break;
9792
9793 case 0xD: /* 8-bit - preindex with wb. */
9794 offset = -i8;
9795 writeback = TRUE;
9796 break;
9797
9798 case 0xB: /* 8-bit + postindex. */
9799 offset = i8;
9800 postind = TRUE;
9801 break;
9802
9803 case 0x9: /* 8-bit - postindex. */
9804 offset = -i8;
9805 postind = TRUE;
9806 break;
9807
9808 default:
9809 func (stream, ", <undefined>]");
9810 goto skip;
9811 }
9812
9813 if (postind)
9814 func (stream, "], #%d", (int) offset);
9815 else
9816 {
9817 if (offset)
9818 func (stream, ", #%d", (int) offset);
9819 func (stream, writeback ? "]!" : "]");
9820 }
9821
9822 if (Rn == 15)
9823 {
9824 func (stream, "\t; ");
9825 info->print_address_func (((pc + 4) & ~3) + offset, info);
9826 }
9827 }
9828 skip:
9829 break;
9830
9831 case 'A':
9832 {
9833 unsigned int U = ! NEGATIVE_BIT_SET;
9834 unsigned int W = WRITEBACK_BIT_SET;
9835 unsigned int Rn = (given & 0x000f0000) >> 16;
9836 unsigned int off = (given & 0x000000ff);
9837
9838 func (stream, "[%s", arm_regnames[Rn]);
9839
9840 if (PRE_BIT_SET)
9841 {
9842 if (off || !U)
9843 {
9844 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
9845 value_in_comment = off * 4 * (U ? 1 : -1);
9846 }
9847 func (stream, "]");
9848 if (W)
9849 func (stream, "!");
9850 }
9851 else
9852 {
9853 func (stream, "], ");
9854 if (W)
9855 {
9856 func (stream, "#%c%u", U ? '+' : '-', off * 4);
9857 value_in_comment = off * 4 * (U ? 1 : -1);
9858 }
9859 else
9860 {
9861 func (stream, "{%u}", off);
9862 value_in_comment = off;
9863 }
9864 }
9865 }
9866 break;
9867
9868 case 'w':
9869 {
9870 unsigned int Sbit = (given & 0x01000000) >> 24;
9871 unsigned int type = (given & 0x00600000) >> 21;
9872
9873 switch (type)
9874 {
9875 case 0: func (stream, Sbit ? "sb" : "b"); break;
9876 case 1: func (stream, Sbit ? "sh" : "h"); break;
9877 case 2:
9878 if (Sbit)
9879 func (stream, "??");
9880 break;
9881 case 3:
9882 func (stream, "??");
9883 break;
9884 }
9885 }
9886 break;
9887
9888 case 'n':
9889 is_clrm = TRUE;
9890 /* Fall through. */
9891 case 'm':
9892 {
9893 int started = 0;
9894 int reg;
9895
9896 func (stream, "{");
9897 for (reg = 0; reg < 16; reg++)
9898 if ((given & (1 << reg)) != 0)
9899 {
9900 if (started)
9901 func (stream, ", ");
9902 started = 1;
9903 if (is_clrm && reg == 13)
9904 func (stream, "(invalid: %s)", arm_regnames[reg]);
9905 else if (is_clrm && reg == 15)
9906 func (stream, "%s", "APSR");
9907 else
9908 func (stream, "%s", arm_regnames[reg]);
9909 }
9910 func (stream, "}");
9911 }
9912 break;
9913
9914 case 'E':
9915 {
9916 unsigned int msb = (given & 0x0000001f);
9917 unsigned int lsb = 0;
9918
9919 lsb |= (given & 0x000000c0u) >> 6;
9920 lsb |= (given & 0x00007000u) >> 10;
9921 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
9922 }
9923 break;
9924
9925 case 'F':
9926 {
9927 unsigned int width = (given & 0x0000001f) + 1;
9928 unsigned int lsb = 0;
9929
9930 lsb |= (given & 0x000000c0u) >> 6;
9931 lsb |= (given & 0x00007000u) >> 10;
9932 func (stream, "#%u, #%u", lsb, width);
9933 }
9934 break;
9935
9936 case 'G':
9937 {
9938 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
9939 func (stream, "%x", boff);
9940 }
9941 break;
9942
9943 case 'W':
9944 {
9945 unsigned int immA = (given & 0x001f0000u) >> 16;
9946 unsigned int immB = (given & 0x000007feu) >> 1;
9947 unsigned int immC = (given & 0x00000800u) >> 11;
9948 bfd_vma offset = 0;
9949
9950 offset |= immA << 12;
9951 offset |= immB << 2;
9952 offset |= immC << 1;
9953 /* Sign extend. */
9954 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
9955
9956 info->print_address_func (pc + 4 + offset, info);
9957 }
9958 break;
9959
9960 case 'Y':
9961 {
9962 unsigned int immA = (given & 0x007f0000u) >> 16;
9963 unsigned int immB = (given & 0x000007feu) >> 1;
9964 unsigned int immC = (given & 0x00000800u) >> 11;
9965 bfd_vma offset = 0;
9966
9967 offset |= immA << 12;
9968 offset |= immB << 2;
9969 offset |= immC << 1;
9970 /* Sign extend. */
9971 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
9972
9973 info->print_address_func (pc + 4 + offset, info);
9974 }
9975 break;
9976
9977 case 'Z':
9978 {
9979 unsigned int immA = (given & 0x00010000u) >> 16;
9980 unsigned int immB = (given & 0x000007feu) >> 1;
9981 unsigned int immC = (given & 0x00000800u) >> 11;
9982 bfd_vma offset = 0;
9983
9984 offset |= immA << 12;
9985 offset |= immB << 2;
9986 offset |= immC << 1;
9987 /* Sign extend. */
9988 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
9989
9990 info->print_address_func (pc + 4 + offset, info);
9991
9992 unsigned int T = (given & 0x00020000u) >> 17;
9993 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
9994 unsigned int boffset = (T == 1) ? 4 : 2;
9995 func (stream, ", ");
9996 func (stream, "%x", endoffset + boffset);
9997 }
9998 break;
9999
10000 case 'Q':
10001 {
10002 unsigned int immh = (given & 0x000007feu) >> 1;
10003 unsigned int imml = (given & 0x00000800u) >> 11;
10004 bfd_vma imm32 = 0;
10005
10006 imm32 |= immh << 2;
10007 imm32 |= imml << 1;
10008
10009 info->print_address_func (pc + 4 + imm32, info);
10010 }
10011 break;
10012
10013 case 'P':
10014 {
10015 unsigned int immh = (given & 0x000007feu) >> 1;
10016 unsigned int imml = (given & 0x00000800u) >> 11;
10017 bfd_vma imm32 = 0;
10018
10019 imm32 |= immh << 2;
10020 imm32 |= imml << 1;
10021
10022 info->print_address_func (pc + 4 - imm32, info);
10023 }
10024 break;
10025
10026 case 'b':
10027 {
10028 unsigned int S = (given & 0x04000000u) >> 26;
10029 unsigned int J1 = (given & 0x00002000u) >> 13;
10030 unsigned int J2 = (given & 0x00000800u) >> 11;
10031 bfd_vma offset = 0;
10032
10033 offset |= !S << 20;
10034 offset |= J2 << 19;
10035 offset |= J1 << 18;
10036 offset |= (given & 0x003f0000) >> 4;
10037 offset |= (given & 0x000007ff) << 1;
10038 offset -= (1 << 20);
10039
10040 info->print_address_func (pc + 4 + offset, info);
10041 }
10042 break;
10043
10044 case 'B':
10045 {
10046 unsigned int S = (given & 0x04000000u) >> 26;
10047 unsigned int I1 = (given & 0x00002000u) >> 13;
10048 unsigned int I2 = (given & 0x00000800u) >> 11;
10049 bfd_vma offset = 0;
10050
10051 offset |= !S << 24;
10052 offset |= !(I1 ^ S) << 23;
10053 offset |= !(I2 ^ S) << 22;
10054 offset |= (given & 0x03ff0000u) >> 4;
10055 offset |= (given & 0x000007ffu) << 1;
10056 offset -= (1 << 24);
10057 offset += pc + 4;
10058
10059 /* BLX target addresses are always word aligned. */
10060 if ((given & 0x00001000u) == 0)
10061 offset &= ~2u;
10062
10063 info->print_address_func (offset, info);
10064 }
10065 break;
10066
10067 case 's':
10068 {
10069 unsigned int shift = 0;
10070
10071 shift |= (given & 0x000000c0u) >> 6;
10072 shift |= (given & 0x00007000u) >> 10;
10073 if (WRITEBACK_BIT_SET)
10074 func (stream, ", asr #%u", shift);
10075 else if (shift)
10076 func (stream, ", lsl #%u", shift);
10077 /* else print nothing - lsl #0 */
10078 }
10079 break;
10080
10081 case 'R':
10082 {
10083 unsigned int rot = (given & 0x00000030) >> 4;
10084
10085 if (rot)
10086 func (stream, ", ror #%u", rot * 8);
10087 }
10088 break;
10089
10090 case 'U':
10091 if ((given & 0xf0) == 0x60)
10092 {
10093 switch (given & 0xf)
10094 {
10095 case 0xf: func (stream, "sy"); break;
10096 default:
10097 func (stream, "#%d", (int) given & 0xf);
10098 break;
10099 }
10100 }
10101 else
10102 {
10103 const char * opt = data_barrier_option (given & 0xf);
10104 if (opt != NULL)
10105 func (stream, "%s", opt);
10106 else
10107 func (stream, "#%d", (int) given & 0xf);
10108 }
10109 break;
10110
10111 case 'C':
10112 if ((given & 0xff) == 0)
10113 {
10114 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
10115 if (given & 0x800)
10116 func (stream, "f");
10117 if (given & 0x400)
10118 func (stream, "s");
10119 if (given & 0x200)
10120 func (stream, "x");
10121 if (given & 0x100)
10122 func (stream, "c");
10123 }
10124 else if ((given & 0x20) == 0x20)
10125 {
10126 char const* name;
10127 unsigned sysm = (given & 0xf00) >> 8;
10128
10129 sysm |= (given & 0x30);
10130 sysm |= (given & 0x00100000) >> 14;
10131 name = banked_regname (sysm);
10132
10133 if (name != NULL)
10134 func (stream, "%s", name);
10135 else
10136 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10137 }
10138 else
10139 {
10140 func (stream, "%s", psr_name (given & 0xff));
10141 }
10142 break;
10143
10144 case 'D':
10145 if (((given & 0xff) == 0)
10146 || ((given & 0x20) == 0x20))
10147 {
10148 char const* name;
10149 unsigned sm = (given & 0xf0000) >> 16;
10150
10151 sm |= (given & 0x30);
10152 sm |= (given & 0x00100000) >> 14;
10153 name = banked_regname (sm);
10154
10155 if (name != NULL)
10156 func (stream, "%s", name);
10157 else
10158 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
10159 }
10160 else
10161 func (stream, "%s", psr_name (given & 0xff));
10162 break;
10163
10164 case '0': case '1': case '2': case '3': case '4':
10165 case '5': case '6': case '7': case '8': case '9':
10166 {
10167 int width;
10168 unsigned long val;
10169
10170 c = arm_decode_bitfield (c, given, &val, &width);
10171
10172 switch (*c)
10173 {
10174 case 'd':
10175 func (stream, "%lu", val);
10176 value_in_comment = val;
10177 break;
10178
10179 case 'D':
10180 func (stream, "%lu", val + 1);
10181 value_in_comment = val + 1;
10182 break;
10183
10184 case 'W':
10185 func (stream, "%lu", val * 4);
10186 value_in_comment = val * 4;
10187 break;
10188
10189 case 'S':
10190 if (val == 13)
10191 is_unpredictable = TRUE;
10192 /* Fall through. */
10193 case 'R':
10194 if (val == 15)
10195 is_unpredictable = TRUE;
10196 /* Fall through. */
10197 case 'r':
10198 func (stream, "%s", arm_regnames[val]);
10199 break;
10200
10201 case 'c':
10202 func (stream, "%s", arm_conditional[val]);
10203 break;
10204
10205 case '\'':
10206 c++;
10207 if (val == ((1ul << width) - 1))
10208 func (stream, "%c", *c);
10209 break;
10210
10211 case '`':
10212 c++;
10213 if (val == 0)
10214 func (stream, "%c", *c);
10215 break;
10216
10217 case '?':
10218 func (stream, "%c", c[(1 << width) - (int) val]);
10219 c += 1 << width;
10220 break;
10221
10222 case 'x':
10223 func (stream, "0x%lx", val & 0xffffffffUL);
10224 break;
10225
10226 default:
10227 abort ();
10228 }
10229 }
10230 break;
10231
10232 case 'L':
10233 /* PR binutils/12534
10234 If we have a PC relative offset in an LDRD or STRD
10235 instructions then display the decoded address. */
10236 if (((given >> 16) & 0xf) == 0xf)
10237 {
10238 bfd_vma offset = (given & 0xff) * 4;
10239
10240 if ((given & (1 << 23)) == 0)
10241 offset = - offset;
10242 func (stream, "\t; ");
10243 info->print_address_func ((pc & ~3) + 4 + offset, info);
10244 }
10245 break;
10246
10247 default:
10248 abort ();
10249 }
10250 }
10251
10252 if (value_in_comment > 32 || value_in_comment < -16)
10253 func (stream, "\t; 0x%lx", value_in_comment);
10254
10255 if (is_unpredictable)
10256 func (stream, UNPREDICTABLE_INSTRUCTION);
10257
10258 return;
10259 }
10260
10261 /* No match. */
10262 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10263 return;
10264 }
10265
10266 /* Print data bytes on INFO->STREAM. */
10267
10268 static void
10269 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
10270 struct disassemble_info *info,
10271 long given)
10272 {
10273 switch (info->bytes_per_chunk)
10274 {
10275 case 1:
10276 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
10277 break;
10278 case 2:
10279 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
10280 break;
10281 case 4:
10282 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
10283 break;
10284 default:
10285 abort ();
10286 }
10287 }
10288
10289 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
10290 being displayed in symbol relative addresses.
10291
10292 Also disallow private symbol, with __tagsym$$ prefix,
10293 from ARM RVCT toolchain being displayed. */
10294
10295 bfd_boolean
10296 arm_symbol_is_valid (asymbol * sym,
10297 struct disassemble_info * info ATTRIBUTE_UNUSED)
10298 {
10299 const char * name;
10300
10301 if (sym == NULL)
10302 return FALSE;
10303
10304 name = bfd_asymbol_name (sym);
10305
10306 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
10307 }
10308
10309 /* Parse the string of disassembler options. */
10310
10311 static void
10312 parse_arm_disassembler_options (const char *options)
10313 {
10314 const char *opt;
10315
10316 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
10317 {
10318 if (CONST_STRNEQ (opt, "reg-names-"))
10319 {
10320 unsigned int i;
10321 for (i = 0; i < NUM_ARM_OPTIONS; i++)
10322 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
10323 {
10324 regname_selected = i;
10325 break;
10326 }
10327
10328 if (i >= NUM_ARM_OPTIONS)
10329 /* xgettext: c-format */
10330 opcodes_error_handler (_("unrecognised register name set: %s"),
10331 opt);
10332 }
10333 else if (CONST_STRNEQ (opt, "force-thumb"))
10334 force_thumb = 1;
10335 else if (CONST_STRNEQ (opt, "no-force-thumb"))
10336 force_thumb = 0;
10337 else
10338 /* xgettext: c-format */
10339 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
10340 }
10341
10342 return;
10343 }
10344
10345 static bfd_boolean
10346 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
10347 enum map_type *map_symbol);
10348
10349 /* Search back through the insn stream to determine if this instruction is
10350 conditionally executed. */
10351
10352 static void
10353 find_ifthen_state (bfd_vma pc,
10354 struct disassemble_info *info,
10355 bfd_boolean little)
10356 {
10357 unsigned char b[2];
10358 unsigned int insn;
10359 int status;
10360 /* COUNT is twice the number of instructions seen. It will be odd if we
10361 just crossed an instruction boundary. */
10362 int count;
10363 int it_count;
10364 unsigned int seen_it;
10365 bfd_vma addr;
10366
10367 ifthen_address = pc;
10368 ifthen_state = 0;
10369
10370 addr = pc;
10371 count = 1;
10372 it_count = 0;
10373 seen_it = 0;
10374 /* Scan backwards looking for IT instructions, keeping track of where
10375 instruction boundaries are. We don't know if something is actually an
10376 IT instruction until we find a definite instruction boundary. */
10377 for (;;)
10378 {
10379 if (addr == 0 || info->symbol_at_address_func (addr, info))
10380 {
10381 /* A symbol must be on an instruction boundary, and will not
10382 be within an IT block. */
10383 if (seen_it && (count & 1))
10384 break;
10385
10386 return;
10387 }
10388 addr -= 2;
10389 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
10390 if (status)
10391 return;
10392
10393 if (little)
10394 insn = (b[0]) | (b[1] << 8);
10395 else
10396 insn = (b[1]) | (b[0] << 8);
10397 if (seen_it)
10398 {
10399 if ((insn & 0xf800) < 0xe800)
10400 {
10401 /* Addr + 2 is an instruction boundary. See if this matches
10402 the expected boundary based on the position of the last
10403 IT candidate. */
10404 if (count & 1)
10405 break;
10406 seen_it = 0;
10407 }
10408 }
10409 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
10410 {
10411 enum map_type type = MAP_ARM;
10412 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
10413
10414 if (!found || (found && type == MAP_THUMB))
10415 {
10416 /* This could be an IT instruction. */
10417 seen_it = insn;
10418 it_count = count >> 1;
10419 }
10420 }
10421 if ((insn & 0xf800) >= 0xe800)
10422 count++;
10423 else
10424 count = (count + 2) | 1;
10425 /* IT blocks contain at most 4 instructions. */
10426 if (count >= 8 && !seen_it)
10427 return;
10428 }
10429 /* We found an IT instruction. */
10430 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
10431 if ((ifthen_state & 0xf) == 0)
10432 ifthen_state = 0;
10433 }
10434
10435 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
10436 mapping symbol. */
10437
10438 static int
10439 is_mapping_symbol (struct disassemble_info *info, int n,
10440 enum map_type *map_type)
10441 {
10442 const char *name;
10443
10444 name = bfd_asymbol_name (info->symtab[n]);
10445 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
10446 && (name[2] == 0 || name[2] == '.'))
10447 {
10448 *map_type = ((name[1] == 'a') ? MAP_ARM
10449 : (name[1] == 't') ? MAP_THUMB
10450 : MAP_DATA);
10451 return TRUE;
10452 }
10453
10454 return FALSE;
10455 }
10456
10457 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
10458 Returns nonzero if *MAP_TYPE was set. */
10459
10460 static int
10461 get_map_sym_type (struct disassemble_info *info,
10462 int n,
10463 enum map_type *map_type)
10464 {
10465 /* If the symbol is in a different section, ignore it. */
10466 if (info->section != NULL && info->section != info->symtab[n]->section)
10467 return FALSE;
10468
10469 return is_mapping_symbol (info, n, map_type);
10470 }
10471
10472 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
10473 Returns nonzero if *MAP_TYPE was set. */
10474
10475 static int
10476 get_sym_code_type (struct disassemble_info *info,
10477 int n,
10478 enum map_type *map_type)
10479 {
10480 elf_symbol_type *es;
10481 unsigned int type;
10482
10483 /* If the symbol is in a different section, ignore it. */
10484 if (info->section != NULL && info->section != info->symtab[n]->section)
10485 return FALSE;
10486
10487 es = *(elf_symbol_type **)(info->symtab + n);
10488 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
10489
10490 /* If the symbol has function type then use that. */
10491 if (type == STT_FUNC || type == STT_GNU_IFUNC)
10492 {
10493 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
10494 == ST_BRANCH_TO_THUMB)
10495 *map_type = MAP_THUMB;
10496 else
10497 *map_type = MAP_ARM;
10498 return TRUE;
10499 }
10500
10501 return FALSE;
10502 }
10503
10504 /* Search the mapping symbol state for instruction at pc. This is only
10505 applicable for elf target.
10506
10507 There is an assumption Here, info->private_data contains the correct AND
10508 up-to-date information about current scan process. The information will be
10509 used to speed this search process.
10510
10511 Return TRUE if the mapping state can be determined, and map_symbol
10512 will be updated accordingly. Otherwise, return FALSE. */
10513
10514 static bfd_boolean
10515 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
10516 enum map_type *map_symbol)
10517 {
10518 bfd_vma addr, section_vma = 0;
10519 int n, last_sym = -1;
10520 bfd_boolean found = FALSE;
10521 bfd_boolean can_use_search_opt_p = FALSE;
10522
10523 /* Default to DATA. A text section is required by the ABI to contain an
10524 INSN mapping symbol at the start. A data section has no such
10525 requirement, hence if no mapping symbol is found the section must
10526 contain only data. This however isn't very useful if the user has
10527 fully stripped the binaries. If this is the case use the section
10528 attributes to determine the default. If we have no section default to
10529 INSN as well, as we may be disassembling some raw bytes on a baremetal
10530 HEX file or similar. */
10531 enum map_type type = MAP_DATA;
10532 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
10533 type = MAP_ARM;
10534 struct arm_private_data *private_data;
10535
10536 if (info->private_data == NULL
10537 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
10538 return FALSE;
10539
10540 private_data = info->private_data;
10541
10542 /* First, look for mapping symbols. */
10543 if (info->symtab_size != 0)
10544 {
10545 if (pc <= private_data->last_mapping_addr)
10546 private_data->last_mapping_sym = -1;
10547
10548 /* Start scanning at the start of the function, or wherever
10549 we finished last time. */
10550 n = info->symtab_pos + 1;
10551
10552 /* If the last stop offset is different from the current one it means we
10553 are disassembling a different glob of bytes. As such the optimization
10554 would not be safe and we should start over. */
10555 can_use_search_opt_p
10556 = private_data->last_mapping_sym >= 0
10557 && info->stop_offset == private_data->last_stop_offset;
10558
10559 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
10560 n = private_data->last_mapping_sym;
10561
10562 /* Look down while we haven't passed the location being disassembled.
10563 The reason for this is that there's no defined order between a symbol
10564 and an mapping symbol that may be at the same address. We may have to
10565 look at least one position ahead. */
10566 for (; n < info->symtab_size; n++)
10567 {
10568 addr = bfd_asymbol_value (info->symtab[n]);
10569 if (addr > pc)
10570 break;
10571 if (get_map_sym_type (info, n, &type))
10572 {
10573 last_sym = n;
10574 found = TRUE;
10575 }
10576 }
10577
10578 if (!found)
10579 {
10580 n = info->symtab_pos;
10581 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
10582 n = private_data->last_mapping_sym;
10583
10584 /* No mapping symbol found at this address. Look backwards
10585 for a preceeding one, but don't go pass the section start
10586 otherwise a data section with no mapping symbol can pick up
10587 a text mapping symbol of a preceeding section. The documentation
10588 says section can be NULL, in which case we will seek up all the
10589 way to the top. */
10590 if (info->section)
10591 section_vma = info->section->vma;
10592
10593 for (; n >= 0; n--)
10594 {
10595 addr = bfd_asymbol_value (info->symtab[n]);
10596 if (addr < section_vma)
10597 break;
10598
10599 if (get_map_sym_type (info, n, &type))
10600 {
10601 last_sym = n;
10602 found = TRUE;
10603 break;
10604 }
10605 }
10606 }
10607 }
10608
10609 /* If no mapping symbol was found, try looking up without a mapping
10610 symbol. This is done by walking up from the current PC to the nearest
10611 symbol. We don't actually have to loop here since symtab_pos will
10612 contain the nearest symbol already. */
10613 if (!found)
10614 {
10615 n = info->symtab_pos;
10616 if (n >= 0 && get_sym_code_type (info, n, &type))
10617 {
10618 last_sym = n;
10619 found = TRUE;
10620 }
10621 }
10622
10623 private_data->last_mapping_sym = last_sym;
10624 private_data->last_type = type;
10625 private_data->last_stop_offset = info->stop_offset;
10626
10627 *map_symbol = type;
10628 return found;
10629 }
10630
10631 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
10632 of the supplied arm_feature_set structure with bitmasks indicating
10633 the supported base architectures and coprocessor extensions.
10634
10635 FIXME: This could more efficiently implemented as a constant array,
10636 although it would also be less robust. */
10637
10638 static void
10639 select_arm_features (unsigned long mach,
10640 arm_feature_set * features)
10641 {
10642 arm_feature_set arch_fset;
10643 const arm_feature_set fpu_any = FPU_ANY;
10644
10645 #undef ARM_SET_FEATURES
10646 #define ARM_SET_FEATURES(FSET) \
10647 { \
10648 const arm_feature_set fset = FSET; \
10649 arch_fset = fset; \
10650 }
10651
10652 /* When several architecture versions share the same bfd_mach_arm_XXX value
10653 the most featureful is chosen. */
10654 switch (mach)
10655 {
10656 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
10657 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
10658 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
10659 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
10660 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
10661 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
10662 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
10663 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
10664 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
10665 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
10666 case bfd_mach_arm_ep9312:
10667 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
10668 ARM_CEXT_MAVERICK | FPU_MAVERICK));
10669 break;
10670 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
10671 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
10672 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
10673 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
10674 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
10675 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
10676 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
10677 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
10678 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
10679 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
10680 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
10681 case bfd_mach_arm_8:
10682 {
10683 /* Add bits for extensions that Armv8.5-A recognizes. */
10684 arm_feature_set armv8_5_ext_fset
10685 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
10686 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
10687 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
10688 break;
10689 }
10690 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
10691 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
10692 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
10693 case bfd_mach_arm_8_1M_MAIN:
10694 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
10695 force_thumb = 1;
10696 break;
10697 /* If the machine type is unknown allow all architecture types and all
10698 extensions. */
10699 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
10700 default:
10701 abort ();
10702 }
10703 #undef ARM_SET_FEATURES
10704
10705 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
10706 and thus on bfd_mach_arm_XXX value. Therefore for a given
10707 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
10708 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
10709 }
10710
10711
10712 /* NOTE: There are no checks in these routines that
10713 the relevant number of data bytes exist. */
10714
10715 static int
10716 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
10717 {
10718 unsigned char b[4];
10719 long given;
10720 int status;
10721 int is_thumb = FALSE;
10722 int is_data = FALSE;
10723 int little_code;
10724 unsigned int size = 4;
10725 void (*printer) (bfd_vma, struct disassemble_info *, long);
10726 bfd_boolean found = FALSE;
10727 struct arm_private_data *private_data;
10728
10729 if (info->disassembler_options)
10730 {
10731 parse_arm_disassembler_options (info->disassembler_options);
10732
10733 /* To avoid repeated parsing of these options, we remove them here. */
10734 info->disassembler_options = NULL;
10735 }
10736
10737 /* PR 10288: Control which instructions will be disassembled. */
10738 if (info->private_data == NULL)
10739 {
10740 static struct arm_private_data private;
10741
10742 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
10743 /* If the user did not use the -m command line switch then default to
10744 disassembling all types of ARM instruction.
10745
10746 The info->mach value has to be ignored as this will be based on
10747 the default archictecture for the target and/or hints in the notes
10748 section, but it will never be greater than the current largest arm
10749 machine value (iWMMXt2), which is only equivalent to the V5TE
10750 architecture. ARM architectures have advanced beyond the machine
10751 value encoding, and these newer architectures would be ignored if
10752 the machine value was used.
10753
10754 Ie the -m switch is used to restrict which instructions will be
10755 disassembled. If it is necessary to use the -m switch to tell
10756 objdump that an ARM binary is being disassembled, eg because the
10757 input is a raw binary file, but it is also desired to disassemble
10758 all ARM instructions then use "-marm". This will select the
10759 "unknown" arm architecture which is compatible with any ARM
10760 instruction. */
10761 info->mach = bfd_mach_arm_unknown;
10762
10763 /* Compute the architecture bitmask from the machine number.
10764 Note: This assumes that the machine number will not change
10765 during disassembly.... */
10766 select_arm_features (info->mach, & private.features);
10767
10768 private.last_mapping_sym = -1;
10769 private.last_mapping_addr = 0;
10770 private.last_stop_offset = 0;
10771
10772 info->private_data = & private;
10773 }
10774
10775 private_data = info->private_data;
10776
10777 /* Decide if our code is going to be little-endian, despite what the
10778 function argument might say. */
10779 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
10780
10781 /* For ELF, consult the symbol table to determine what kind of code
10782 or data we have. */
10783 if (info->symtab_size != 0
10784 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
10785 {
10786 bfd_vma addr;
10787 int n;
10788 int last_sym = -1;
10789 enum map_type type = MAP_ARM;
10790
10791 found = mapping_symbol_for_insn (pc, info, &type);
10792 last_sym = private_data->last_mapping_sym;
10793
10794 is_thumb = (private_data->last_type == MAP_THUMB);
10795 is_data = (private_data->last_type == MAP_DATA);
10796
10797 /* Look a little bit ahead to see if we should print out
10798 two or four bytes of data. If there's a symbol,
10799 mapping or otherwise, after two bytes then don't
10800 print more. */
10801 if (is_data)
10802 {
10803 size = 4 - (pc & 3);
10804 for (n = last_sym + 1; n < info->symtab_size; n++)
10805 {
10806 addr = bfd_asymbol_value (info->symtab[n]);
10807 if (addr > pc
10808 && (info->section == NULL
10809 || info->section == info->symtab[n]->section))
10810 {
10811 if (addr - pc < size)
10812 size = addr - pc;
10813 break;
10814 }
10815 }
10816 /* If the next symbol is after three bytes, we need to
10817 print only part of the data, so that we can use either
10818 .byte or .short. */
10819 if (size == 3)
10820 size = (pc & 1) ? 1 : 2;
10821 }
10822 }
10823
10824 if (info->symbols != NULL)
10825 {
10826 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
10827 {
10828 coff_symbol_type * cs;
10829
10830 cs = coffsymbol (*info->symbols);
10831 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
10832 || cs->native->u.syment.n_sclass == C_THUMBSTAT
10833 || cs->native->u.syment.n_sclass == C_THUMBLABEL
10834 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
10835 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
10836 }
10837 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
10838 && !found)
10839 {
10840 /* If no mapping symbol has been found then fall back to the type
10841 of the function symbol. */
10842 elf_symbol_type * es;
10843 unsigned int type;
10844
10845 es = *(elf_symbol_type **)(info->symbols);
10846 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
10847
10848 is_thumb =
10849 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
10850 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
10851 }
10852 else if (bfd_asymbol_flavour (*info->symbols)
10853 == bfd_target_mach_o_flavour)
10854 {
10855 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
10856
10857 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
10858 }
10859 }
10860
10861 if (force_thumb)
10862 is_thumb = TRUE;
10863
10864 if (is_data)
10865 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
10866 else
10867 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
10868
10869 info->bytes_per_line = 4;
10870
10871 /* PR 10263: Disassemble data if requested to do so by the user. */
10872 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
10873 {
10874 int i;
10875
10876 /* Size was already set above. */
10877 info->bytes_per_chunk = size;
10878 printer = print_insn_data;
10879
10880 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
10881 given = 0;
10882 if (little)
10883 for (i = size - 1; i >= 0; i--)
10884 given = b[i] | (given << 8);
10885 else
10886 for (i = 0; i < (int) size; i++)
10887 given = b[i] | (given << 8);
10888 }
10889 else if (!is_thumb)
10890 {
10891 /* In ARM mode endianness is a straightforward issue: the instruction
10892 is four bytes long and is either ordered 0123 or 3210. */
10893 printer = print_insn_arm;
10894 info->bytes_per_chunk = 4;
10895 size = 4;
10896
10897 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
10898 if (little_code)
10899 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
10900 else
10901 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
10902 }
10903 else
10904 {
10905 /* In Thumb mode we have the additional wrinkle of two
10906 instruction lengths. Fortunately, the bits that determine
10907 the length of the current instruction are always to be found
10908 in the first two bytes. */
10909 printer = print_insn_thumb16;
10910 info->bytes_per_chunk = 2;
10911 size = 2;
10912
10913 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
10914 if (little_code)
10915 given = (b[0]) | (b[1] << 8);
10916 else
10917 given = (b[1]) | (b[0] << 8);
10918
10919 if (!status)
10920 {
10921 /* These bit patterns signal a four-byte Thumb
10922 instruction. */
10923 if ((given & 0xF800) == 0xF800
10924 || (given & 0xF800) == 0xF000
10925 || (given & 0xF800) == 0xE800)
10926 {
10927 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
10928 if (little_code)
10929 given = (b[0]) | (b[1] << 8) | (given << 16);
10930 else
10931 given = (b[1]) | (b[0] << 8) | (given << 16);
10932
10933 printer = print_insn_thumb32;
10934 size = 4;
10935 }
10936 }
10937
10938 if (ifthen_address != pc)
10939 find_ifthen_state (pc, info, little_code);
10940
10941 if (ifthen_state)
10942 {
10943 if ((ifthen_state & 0xf) == 0x8)
10944 ifthen_next_state = 0;
10945 else
10946 ifthen_next_state = (ifthen_state & 0xe0)
10947 | ((ifthen_state & 0xf) << 1);
10948 }
10949 }
10950
10951 if (status)
10952 {
10953 info->memory_error_func (status, pc, info);
10954 return -1;
10955 }
10956 if (info->flags & INSN_HAS_RELOC)
10957 /* If the instruction has a reloc associated with it, then
10958 the offset field in the instruction will actually be the
10959 addend for the reloc. (We are using REL type relocs).
10960 In such cases, we can ignore the pc when computing
10961 addresses, since the addend is not currently pc-relative. */
10962 pc = 0;
10963
10964 printer (pc, info, given);
10965
10966 if (is_thumb)
10967 {
10968 ifthen_state = ifthen_next_state;
10969 ifthen_address += size;
10970 }
10971 return size;
10972 }
10973
10974 int
10975 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
10976 {
10977 /* Detect BE8-ness and record it in the disassembler info. */
10978 if (info->flavour == bfd_target_elf_flavour
10979 && info->section != NULL
10980 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
10981 info->endian_code = BFD_ENDIAN_LITTLE;
10982
10983 return print_insn (pc, info, FALSE);
10984 }
10985
10986 int
10987 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
10988 {
10989 return print_insn (pc, info, TRUE);
10990 }
10991
10992 const disasm_options_and_args_t *
10993 disassembler_options_arm (void)
10994 {
10995 static disasm_options_and_args_t *opts_and_args;
10996
10997 if (opts_and_args == NULL)
10998 {
10999 disasm_options_t *opts;
11000 unsigned int i;
11001
11002 opts_and_args = XNEW (disasm_options_and_args_t);
11003 opts_and_args->args = NULL;
11004
11005 opts = &opts_and_args->options;
11006 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11007 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11008 opts->arg = NULL;
11009 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11010 {
11011 opts->name[i] = regnames[i].name;
11012 if (regnames[i].description != NULL)
11013 opts->description[i] = _(regnames[i].description);
11014 else
11015 opts->description[i] = NULL;
11016 }
11017 /* The array we return must be NULL terminated. */
11018 opts->name[i] = NULL;
11019 opts->description[i] = NULL;
11020 }
11021
11022 return opts_and_args;
11023 }
11024
11025 void
11026 print_arm_disassembler_options (FILE *stream)
11027 {
11028 unsigned int i, max_len = 0;
11029 fprintf (stream, _("\n\
11030 The following ARM specific disassembler options are supported for use with\n\
11031 the -M switch:\n"));
11032
11033 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11034 {
11035 unsigned int len = strlen (regnames[i].name);
11036 if (max_len < len)
11037 max_len = len;
11038 }
11039
11040 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
11041 fprintf (stream, " %s%*c %s\n",
11042 regnames[i].name,
11043 (int)(max_len - strlen (regnames[i].name)), ' ',
11044 _(regnames[i].description));
11045 }
GDB Binutils - Deliverables
This page took 0.489294 seconds and 5 git commands to generate.