projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ubsan: v850: left shift cannot be represented in type 'long'
[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c
1 /* Disassemble ADI Blackfin Instructions.
2 Copyright (C) 2005-2019 Free Software Foundation, Inc.
3
4 This file is part of libopcodes.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include "sysdep.h"
22 #include <stdio.h>
23
24 #include "opcode/bfin.h"
25
26 #ifndef PRINTF
27 #define PRINTF printf
28 #endif
29
30 #ifndef EXIT
31 #define EXIT exit
32 #endif
33
34 typedef long TIword;
35
36 #define SIGNBIT(bits) (1ul << ((bits) - 1))
37 #define MASKBITS(val, bits) ((val) & ((1ul << (bits)) - 1))
38 #define SIGNEXTEND(v, n) ((MASKBITS (v, n) ^ SIGNBIT (n)) - SIGNBIT (n))
39
40 #include "disassemble.h"
41
42 typedef unsigned int bu32;
43
44 struct private
45 {
46 TIword iw0;
47 bfd_boolean comment, parallel;
48 };
49
50 typedef enum
51 {
52 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
53 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
54 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
55 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
56 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
57 } const_forms_t;
58
59 static const struct
60 {
61 const char *name;
62 const int nbits;
63 const char reloc;
64 const char issigned;
65 const char pcrel;
66 const char scale;
67 const char offset;
68 const char negative;
69 const char positive;
70 const char decimal;
71 const char leading;
72 const char exact;
73 } constant_formats[] =
74 {
75 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
76 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
78 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
79 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
80 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
81 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
82 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
83 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
84 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
85 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
86 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
88 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
89 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
91 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
92 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
94 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
95 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
97 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
98 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
99 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
100 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
101 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
102 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
103 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
104 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
107 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
108 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
109 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
110 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
111 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
112 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
113 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
114 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
118 };
119
120 static const char *
121 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
122 {
123 static char buf[60];
124
125 if (constant_formats[cf].reloc)
126 {
127 bfd_vma ea;
128
129 if (constant_formats[cf].pcrel)
130 x = SIGNEXTEND (x, constant_formats[cf].nbits);
131 ea = (x + constant_formats[cf].offset) << constant_formats[cf].scale;
132 if (constant_formats[cf].pcrel)
133 ea += pc;
134
135 /* truncate to 32-bits for proper symbol lookup/matching */
136 ea = (bu32)ea;
137
138 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
139 {
140 outf->print_address_func (ea, outf);
141 return "";
142 }
143 else
144 {
145 sprintf (buf, "%lx", (unsigned long) x);
146 return buf;
147 }
148 }
149
150 /* Negative constants have an implied sign bit. */
151 if (constant_formats[cf].negative)
152 {
153 int nb = constant_formats[cf].nbits + 1;
154
155 x = x | (1 << constant_formats[cf].nbits);
156 x = SIGNEXTEND (x, nb);
157 }
158 else if (constant_formats[cf].issigned)
159 x = SIGNEXTEND (x, constant_formats[cf].nbits);
160
161 if (constant_formats[cf].offset)
162 x += constant_formats[cf].offset;
163
164 if (constant_formats[cf].scale)
165 x <<= constant_formats[cf].scale;
166
167 if (constant_formats[cf].decimal)
168 sprintf (buf, "%*li", constant_formats[cf].leading, x);
169 else
170 {
171 if (constant_formats[cf].issigned && x < 0)
172 sprintf (buf, "-0x%lx", (unsigned long)(- x));
173 else
174 sprintf (buf, "0x%lx", (unsigned long) x);
175 }
176
177 return buf;
178 }
179
180 static bu32
181 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
182 {
183 if (0 && constant_formats[cf].reloc)
184 {
185 bu32 ea;
186
187 if (constant_formats[cf].pcrel)
188 x = SIGNEXTEND (x, constant_formats[cf].nbits);
189 ea = (x + constant_formats[cf].offset) << constant_formats[cf].scale;
190 if (constant_formats[cf].pcrel)
191 ea += pc;
192
193 return ea;
194 }
195
196 /* Negative constants have an implied sign bit. */
197 if (constant_formats[cf].negative)
198 {
199 int nb = constant_formats[cf].nbits + 1;
200 x = x | (1u << constant_formats[cf].nbits);
201 x = SIGNEXTEND (x, nb);
202 }
203 else if (constant_formats[cf].issigned)
204 x = SIGNEXTEND (x, constant_formats[cf].nbits);
205
206 x += constant_formats[cf].offset;
207 x <<= constant_formats[cf].scale;
208
209 return x;
210 }
211
212 enum machine_registers
213 {
214 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
215 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
216 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
217 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
218 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
219 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
220 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
221 REG_L2, REG_L3,
222 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
223 REG_AQ, REG_V, REG_VS,
224 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
225 REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
226 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
227 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
228 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
229 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
230 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
231 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
232 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
233 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
234 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
235 REG_LASTREG,
236 };
237
238 enum reg_class
239 {
240 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
241 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
242 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
243 rc_sysregs3, rc_allregs,
244 LIM_REG_CLASSES
245 };
246
247 static const char * const reg_names[] =
248 {
249 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
250 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
251 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
252 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
253 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
254 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
255 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
256 "L2", "L3",
257 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
258 "AQ", "V", "VS",
259 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
260 "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
261 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
262 "RETE", "EMUDAT",
263 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
264 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
265 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
266 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
267 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
268 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
269 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
270 "AC0_COPY", "V_COPY", "RND_MOD",
271 "LASTREG",
272 0
273 };
274
275 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
276
277 /* RL(0..7). */
278 static const enum machine_registers decode_dregs_lo[] =
279 {
280 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
281 };
282
283 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
284
285 /* RH(0..7). */
286 static const enum machine_registers decode_dregs_hi[] =
287 {
288 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
289 };
290
291 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
292
293 /* R(0..7). */
294 static const enum machine_registers decode_dregs[] =
295 {
296 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
297 };
298
299 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
300
301 /* R BYTE(0..7). */
302 static const enum machine_registers decode_dregs_byte[] =
303 {
304 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
305 };
306
307 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
308
309 /* P(0..5) SP FP. */
310 static const enum machine_registers decode_pregs[] =
311 {
312 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
313 };
314
315 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
316 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
317 #define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
318 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
319 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
320 #define accum(x) REGNAME (decode_accum[(x) & 1])
321
322 /* I(0..3). */
323 static const enum machine_registers decode_iregs[] =
324 {
325 REG_I0, REG_I1, REG_I2, REG_I3,
326 };
327
328 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
329
330 /* M(0..3). */
331 static const enum machine_registers decode_mregs[] =
332 {
333 REG_M0, REG_M1, REG_M2, REG_M3,
334 };
335
336 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
337 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
338 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
339
340 /* dregs pregs. */
341 static const enum machine_registers decode_dpregs[] =
342 {
343 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
344 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
345 };
346
347 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
348
349 /* [dregs pregs]. */
350 static const enum machine_registers decode_gregs[] =
351 {
352 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
353 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
354 };
355
356 #define gregs(x, i) REGNAME (decode_gregs[(((i) << 3) | (x)) & 15])
357
358 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
359 static const enum machine_registers decode_regs[] =
360 {
361 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
362 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
363 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
364 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
365 };
366
367 #define regs(x, i) REGNAME (decode_regs[(((i) << 3) | (x)) & 31])
368
369 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
370 static const enum machine_registers decode_regs_lo[] =
371 {
372 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
373 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
374 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
375 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
376 };
377
378 #define regs_lo(x, i) REGNAME (decode_regs_lo[(((i) << 3) | (x)) & 31])
379
380 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
381 static const enum machine_registers decode_regs_hi[] =
382 {
383 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
384 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
385 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
386 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
387 };
388
389 #define regs_hi(x, i) REGNAME (decode_regs_hi[(((i) << 3) | (x)) & 31])
390
391 static const enum machine_registers decode_statbits[] =
392 {
393 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
394 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
395 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
396 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
397 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
398 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
399 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
400 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
401 };
402
403 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
404
405 /* LC0 LC1. */
406 static const enum machine_registers decode_counters[] =
407 {
408 REG_LC0, REG_LC1,
409 };
410
411 #define counters(x) REGNAME (decode_counters[(x) & 1])
412 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
413
414 /* [dregs pregs (iregs mregs) (bregs lregs)
415 dregs2_sysregs1 open sysregs2 sysregs3]. */
416 static const enum machine_registers decode_allregs[] =
417 {
418 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
419 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
420 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
421 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
422 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
423 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
424 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
425 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
426 REG_LASTREG,
427 };
428
429 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
430 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
431 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
432 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
433 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
434 #define IS_SYSREG(g,r) \
435 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
436 #define IS_RESERVEDREG(g,r) \
437 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
438
439 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
440 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
441
442 #define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
443 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
444 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
445 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
446 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
447 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
448 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
449 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
450 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
451 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
452 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
453 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
454 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
455 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
456 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
457 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
458 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
459 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
460 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
461 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
462 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
463 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
464 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
465 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
466 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
467 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
468 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
469 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
470 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
471 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
472 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
473 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
474 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
475 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
476 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
477 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
478 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
479 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
480 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
481 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
482 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
483 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
484 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
485
486 /* (arch.pm)arch_disassembler_functions. */
487 #ifndef OUTS
488 #define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
489 #endif
490 #define OUT(p, txt, ...) (p)->fprintf_func ((p)->stream, txt, ## __VA_ARGS__)
491
492 static void
493 amod0 (int s0, int x0, disassemble_info *outf)
494 {
495 if (s0 == 1 && x0 == 0)
496 OUTS (outf, " (S)");
497 else if (s0 == 0 && x0 == 1)
498 OUTS (outf, " (CO)");
499 else if (s0 == 1 && x0 == 1)
500 OUTS (outf, " (SCO)");
501 }
502
503 static void
504 amod1 (int s0, int x0, disassemble_info *outf)
505 {
506 if (s0 == 0 && x0 == 0)
507 OUTS (outf, " (NS)");
508 else if (s0 == 1 && x0 == 0)
509 OUTS (outf, " (S)");
510 }
511
512 static void
513 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
514 {
515 if (s0 == 1 && x0 == 0 && aop0 == 0)
516 OUTS (outf, " (S)");
517 else if (s0 == 0 && x0 == 1 && aop0 == 0)
518 OUTS (outf, " (CO)");
519 else if (s0 == 1 && x0 == 1 && aop0 == 0)
520 OUTS (outf, " (SCO)");
521 else if (s0 == 0 && x0 == 0 && aop0 == 2)
522 OUTS (outf, " (ASR)");
523 else if (s0 == 1 && x0 == 0 && aop0 == 2)
524 OUTS (outf, " (S, ASR)");
525 else if (s0 == 0 && x0 == 1 && aop0 == 2)
526 OUTS (outf, " (CO, ASR)");
527 else if (s0 == 1 && x0 == 1 && aop0 == 2)
528 OUTS (outf, " (SCO, ASR)");
529 else if (s0 == 0 && x0 == 0 && aop0 == 3)
530 OUTS (outf, " (ASL)");
531 else if (s0 == 1 && x0 == 0 && aop0 == 3)
532 OUTS (outf, " (S, ASL)");
533 else if (s0 == 0 && x0 == 1 && aop0 == 3)
534 OUTS (outf, " (CO, ASL)");
535 else if (s0 == 1 && x0 == 1 && aop0 == 3)
536 OUTS (outf, " (SCO, ASL)");
537 }
538
539 static void
540 searchmod (int r0, disassemble_info *outf)
541 {
542 if (r0 == 0)
543 OUTS (outf, "GT");
544 else if (r0 == 1)
545 OUTS (outf, "GE");
546 else if (r0 == 2)
547 OUTS (outf, "LT");
548 else if (r0 == 3)
549 OUTS (outf, "LE");
550 }
551
552 static void
553 aligndir (int r0, disassemble_info *outf)
554 {
555 if (r0 == 1)
556 OUTS (outf, " (R)");
557 }
558
559 static int
560 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
561 {
562 const char *s0, *s1;
563
564 if (h0)
565 s0 = dregs_hi (src0);
566 else
567 s0 = dregs_lo (src0);
568
569 if (h1)
570 s1 = dregs_hi (src1);
571 else
572 s1 = dregs_lo (src1);
573
574 OUTS (outf, s0);
575 OUTS (outf, " * ");
576 OUTS (outf, s1);
577 return 0;
578 }
579
580 static int
581 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
582 {
583 const char *a;
584 const char *sop = "<unknown op>";
585
586 if (which)
587 a = "A1";
588 else
589 a = "A0";
590
591 if (op == 3)
592 {
593 OUTS (outf, a);
594 return 0;
595 }
596
597 switch (op)
598 {
599 case 0: sop = " = "; break;
600 case 1: sop = " += "; break;
601 case 2: sop = " -= "; break;
602 default: break;
603 }
604
605 OUTS (outf, a);
606 OUTS (outf, sop);
607 decode_multfunc (h0, h1, src0, src1, outf);
608
609 return 0;
610 }
611
612 static void
613 decode_optmode (int mod, int MM, disassemble_info *outf)
614 {
615 if (mod == 0 && MM == 0)
616 return;
617
618 OUTS (outf, " (");
619
620 if (MM && !mod)
621 {
622 OUTS (outf, "M)");
623 return;
624 }
625
626 if (MM)
627 OUTS (outf, "M, ");
628
629 if (mod == M_S2RND)
630 OUTS (outf, "S2RND");
631 else if (mod == M_T)
632 OUTS (outf, "T");
633 else if (mod == M_W32)
634 OUTS (outf, "W32");
635 else if (mod == M_FU)
636 OUTS (outf, "FU");
637 else if (mod == M_TFU)
638 OUTS (outf, "TFU");
639 else if (mod == M_IS)
640 OUTS (outf, "IS");
641 else if (mod == M_ISS2)
642 OUTS (outf, "ISS2");
643 else if (mod == M_IH)
644 OUTS (outf, "IH");
645 else if (mod == M_IU)
646 OUTS (outf, "IU");
647 else
648 abort ();
649
650 OUTS (outf, ")");
651 }
652
653 static struct saved_state
654 {
655 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
656 bu32 ax[2], aw[2];
657 bu32 lt[2], lc[2], lb[2];
658 bu32 rets;
659 } saved_state;
660
661 #define DREG(x) (saved_state.dpregs[x])
662 #define GREG(x, i) DPREG ((x) | ((i) << 3))
663 #define DPREG(x) (saved_state.dpregs[x])
664 #define DREG(x) (saved_state.dpregs[x])
665 #define PREG(x) (saved_state.dpregs[(x) + 8])
666 #define SPREG PREG (6)
667 #define FPREG PREG (7)
668 #define IREG(x) (saved_state.iregs[x])
669 #define MREG(x) (saved_state.mregs[x])
670 #define BREG(x) (saved_state.bregs[x])
671 #define LREG(x) (saved_state.lregs[x])
672 #define AXREG(x) (saved_state.ax[x])
673 #define AWREG(x) (saved_state.aw[x])
674 #define LCREG(x) (saved_state.lc[x])
675 #define LTREG(x) (saved_state.lt[x])
676 #define LBREG(x) (saved_state.lb[x])
677 #define RETSREG (saved_state.rets)
678
679 static bu32 *
680 get_allreg (int grp, int reg)
681 {
682 int fullreg = (grp << 3) | reg;
683 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
684 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
685 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
686 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
687 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
688 , , , , , , , ,
689 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
690 REG_CYCLES2,
691 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
692 REG_LASTREG */
693 switch (fullreg >> 2)
694 {
695 case 0: case 1: return &DREG (reg);
696 case 2: case 3: return &PREG (reg);
697 case 4: return &IREG (reg & 3);
698 case 5: return &MREG (reg & 3);
699 case 6: return &BREG (reg & 3);
700 case 7: return &LREG (reg & 3);
701 default:
702 switch (fullreg)
703 {
704 case 32: return &AXREG (0);
705 case 33: return &AWREG (0);
706 case 34: return &AXREG (1);
707 case 35: return &AWREG (1);
708 case 39: return &RETSREG;
709 case 48: return &LCREG (0);
710 case 49: return &LTREG (0);
711 case 50: return &LBREG (0);
712 case 51: return &LCREG (1);
713 case 52: return &LTREG (1);
714 case 53: return &LBREG (1);
715 }
716 }
717 abort ();
718 }
719
720 static int
721 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
722 {
723 struct private *priv = outf->private_data;
724 /* ProgCtrl
725 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
726 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
727 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
728 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
729 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
730
731 if (prgfunc == 0 && poprnd == 0)
732 OUTS (outf, "NOP");
733 else if (priv->parallel)
734 return 0;
735 else if (prgfunc == 1 && poprnd == 0)
736 OUTS (outf, "RTS");
737 else if (prgfunc == 1 && poprnd == 1)
738 OUTS (outf, "RTI");
739 else if (prgfunc == 1 && poprnd == 2)
740 OUTS (outf, "RTX");
741 else if (prgfunc == 1 && poprnd == 3)
742 OUTS (outf, "RTN");
743 else if (prgfunc == 1 && poprnd == 4)
744 OUTS (outf, "RTE");
745 else if (prgfunc == 2 && poprnd == 0)
746 OUTS (outf, "IDLE");
747 else if (prgfunc == 2 && poprnd == 3)
748 OUTS (outf, "CSYNC");
749 else if (prgfunc == 2 && poprnd == 4)
750 OUTS (outf, "SSYNC");
751 else if (prgfunc == 2 && poprnd == 5)
752 OUTS (outf, "EMUEXCPT");
753 else if (prgfunc == 3 && IS_DREG (0, poprnd))
754 {
755 OUTS (outf, "CLI ");
756 OUTS (outf, dregs (poprnd));
757 }
758 else if (prgfunc == 4 && IS_DREG (0, poprnd))
759 {
760 OUTS (outf, "STI ");
761 OUTS (outf, dregs (poprnd));
762 }
763 else if (prgfunc == 5 && IS_PREG (1, poprnd))
764 {
765 OUTS (outf, "JUMP (");
766 OUTS (outf, pregs (poprnd));
767 OUTS (outf, ")");
768 }
769 else if (prgfunc == 6 && IS_PREG (1, poprnd))
770 {
771 OUTS (outf, "CALL (");
772 OUTS (outf, pregs (poprnd));
773 OUTS (outf, ")");
774 }
775 else if (prgfunc == 7 && IS_PREG (1, poprnd))
776 {
777 OUTS (outf, "CALL (PC + ");
778 OUTS (outf, pregs (poprnd));
779 OUTS (outf, ")");
780 }
781 else if (prgfunc == 8 && IS_PREG (1, poprnd))
782 {
783 OUTS (outf, "JUMP (PC + ");
784 OUTS (outf, pregs (poprnd));
785 OUTS (outf, ")");
786 }
787 else if (prgfunc == 9)
788 {
789 OUTS (outf, "RAISE ");
790 OUTS (outf, uimm4 (poprnd));
791 }
792 else if (prgfunc == 10)
793 {
794 OUTS (outf, "EXCPT ");
795 OUTS (outf, uimm4 (poprnd));
796 }
797 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
798 {
799 OUTS (outf, "TESTSET (");
800 OUTS (outf, pregs (poprnd));
801 OUTS (outf, ")");
802 }
803 else
804 return 0;
805 return 2;
806 }
807
808 static int
809 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
810 {
811 struct private *priv = outf->private_data;
812 /* CaCTRL
813 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
814 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
815 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
816 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
817 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
818 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
819
820 if (priv->parallel)
821 return 0;
822
823 if (a == 0 && op == 0)
824 {
825 OUTS (outf, "PREFETCH[");
826 OUTS (outf, pregs (reg));
827 OUTS (outf, "]");
828 }
829 else if (a == 0 && op == 1)
830 {
831 OUTS (outf, "FLUSHINV[");
832 OUTS (outf, pregs (reg));
833 OUTS (outf, "]");
834 }
835 else if (a == 0 && op == 2)
836 {
837 OUTS (outf, "FLUSH[");
838 OUTS (outf, pregs (reg));
839 OUTS (outf, "]");
840 }
841 else if (a == 0 && op == 3)
842 {
843 OUTS (outf, "IFLUSH[");
844 OUTS (outf, pregs (reg));
845 OUTS (outf, "]");
846 }
847 else if (a == 1 && op == 0)
848 {
849 OUTS (outf, "PREFETCH[");
850 OUTS (outf, pregs (reg));
851 OUTS (outf, "++]");
852 }
853 else if (a == 1 && op == 1)
854 {
855 OUTS (outf, "FLUSHINV[");
856 OUTS (outf, pregs (reg));
857 OUTS (outf, "++]");
858 }
859 else if (a == 1 && op == 2)
860 {
861 OUTS (outf, "FLUSH[");
862 OUTS (outf, pregs (reg));
863 OUTS (outf, "++]");
864 }
865 else if (a == 1 && op == 3)
866 {
867 OUTS (outf, "IFLUSH[");
868 OUTS (outf, pregs (reg));
869 OUTS (outf, "++]");
870 }
871 else
872 return 0;
873 return 2;
874 }
875
876 static int
877 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
878 {
879 struct private *priv = outf->private_data;
880 /* PushPopReg
881 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
882 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
883 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
884 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
885 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
886 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
887
888 if (priv->parallel)
889 return 0;
890
891 if (W == 0 && mostreg (reg, grp))
892 {
893 OUTS (outf, allregs (reg, grp));
894 OUTS (outf, " = [SP++]");
895 }
896 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
897 {
898 OUTS (outf, "[--SP] = ");
899 OUTS (outf, allregs (reg, grp));
900 }
901 else
902 return 0;
903 return 2;
904 }
905
906 static int
907 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
908 {
909 struct private *priv = outf->private_data;
910 /* PushPopMultiple
911 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
912 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
913 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
914 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
915 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
916 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
917 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
918 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
919
920 if (priv->parallel)
921 return 0;
922
923 if (pr > 5)
924 return 0;
925
926 if (W == 1 && d == 1 && p == 1)
927 {
928 OUTS (outf, "[--SP] = (R7:");
929 OUTS (outf, imm5d (dr));
930 OUTS (outf, ", P5:");
931 OUTS (outf, imm5d (pr));
932 OUTS (outf, ")");
933 }
934 else if (W == 1 && d == 1 && p == 0 && pr == 0)
935 {
936 OUTS (outf, "[--SP] = (R7:");
937 OUTS (outf, imm5d (dr));
938 OUTS (outf, ")");
939 }
940 else if (W == 1 && d == 0 && p == 1 && dr == 0)
941 {
942 OUTS (outf, "[--SP] = (P5:");
943 OUTS (outf, imm5d (pr));
944 OUTS (outf, ")");
945 }
946 else if (W == 0 && d == 1 && p == 1)
947 {
948 OUTS (outf, "(R7:");
949 OUTS (outf, imm5d (dr));
950 OUTS (outf, ", P5:");
951 OUTS (outf, imm5d (pr));
952 OUTS (outf, ") = [SP++]");
953 }
954 else if (W == 0 && d == 1 && p == 0 && pr == 0)
955 {
956 OUTS (outf, "(R7:");
957 OUTS (outf, imm5d (dr));
958 OUTS (outf, ") = [SP++]");
959 }
960 else if (W == 0 && d == 0 && p == 1 && dr == 0)
961 {
962 OUTS (outf, "(P5:");
963 OUTS (outf, imm5d (pr));
964 OUTS (outf, ") = [SP++]");
965 }
966 else
967 return 0;
968 return 2;
969 }
970
971 static int
972 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
973 {
974 struct private *priv = outf->private_data;
975 /* ccMV
976 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
977 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
978 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
979 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
980 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
981 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
982 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
983 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
984
985 if (priv->parallel)
986 return 0;
987
988 if (T == 1)
989 {
990 OUTS (outf, "IF CC ");
991 OUTS (outf, gregs (dst, d));
992 OUTS (outf, " = ");
993 OUTS (outf, gregs (src, s));
994 }
995 else if (T == 0)
996 {
997 OUTS (outf, "IF !CC ");
998 OUTS (outf, gregs (dst, d));
999 OUTS (outf, " = ");
1000 OUTS (outf, gregs (src, s));
1001 }
1002 else
1003 return 0;
1004 return 2;
1005 }
1006
1007 static int
1008 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1009 {
1010 struct private *priv = outf->private_data;
1011 /* CCflag
1012 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1013 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1014 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1015 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1016 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1017 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1018 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1019 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1020
1021 if (priv->parallel)
1022 return 0;
1023
1024 if (opc == 0 && I == 0 && G == 0)
1025 {
1026 OUTS (outf, "CC = ");
1027 OUTS (outf, dregs (x));
1028 OUTS (outf, " == ");
1029 OUTS (outf, dregs (y));
1030 }
1031 else if (opc == 1 && I == 0 && G == 0)
1032 {
1033 OUTS (outf, "CC = ");
1034 OUTS (outf, dregs (x));
1035 OUTS (outf, " < ");
1036 OUTS (outf, dregs (y));
1037 }
1038 else if (opc == 2 && I == 0 && G == 0)
1039 {
1040 OUTS (outf, "CC = ");
1041 OUTS (outf, dregs (x));
1042 OUTS (outf, " <= ");
1043 OUTS (outf, dregs (y));
1044 }
1045 else if (opc == 3 && I == 0 && G == 0)
1046 {
1047 OUTS (outf, "CC = ");
1048 OUTS (outf, dregs (x));
1049 OUTS (outf, " < ");
1050 OUTS (outf, dregs (y));
1051 OUTS (outf, " (IU)");
1052 }
1053 else if (opc == 4 && I == 0 && G == 0)
1054 {
1055 OUTS (outf, "CC = ");
1056 OUTS (outf, dregs (x));
1057 OUTS (outf, " <= ");
1058 OUTS (outf, dregs (y));
1059 OUTS (outf, " (IU)");
1060 }
1061 else if (opc == 0 && I == 1 && G == 0)
1062 {
1063 OUTS (outf, "CC = ");
1064 OUTS (outf, dregs (x));
1065 OUTS (outf, " == ");
1066 OUTS (outf, imm3 (y));
1067 }
1068 else if (opc == 1 && I == 1 && G == 0)
1069 {
1070 OUTS (outf, "CC = ");
1071 OUTS (outf, dregs (x));
1072 OUTS (outf, " < ");
1073 OUTS (outf, imm3 (y));
1074 }
1075 else if (opc == 2 && I == 1 && G == 0)
1076 {
1077 OUTS (outf, "CC = ");
1078 OUTS (outf, dregs (x));
1079 OUTS (outf, " <= ");
1080 OUTS (outf, imm3 (y));
1081 }
1082 else if (opc == 3 && I == 1 && G == 0)
1083 {
1084 OUTS (outf, "CC = ");
1085 OUTS (outf, dregs (x));
1086 OUTS (outf, " < ");
1087 OUTS (outf, uimm3 (y));
1088 OUTS (outf, " (IU)");
1089 }
1090 else if (opc == 4 && I == 1 && G == 0)
1091 {
1092 OUTS (outf, "CC = ");
1093 OUTS (outf, dregs (x));
1094 OUTS (outf, " <= ");
1095 OUTS (outf, uimm3 (y));
1096 OUTS (outf, " (IU)");
1097 }
1098 else if (opc == 0 && I == 0 && G == 1)
1099 {
1100 OUTS (outf, "CC = ");
1101 OUTS (outf, pregs (x));
1102 OUTS (outf, " == ");
1103 OUTS (outf, pregs (y));
1104 }
1105 else if (opc == 1 && I == 0 && G == 1)
1106 {
1107 OUTS (outf, "CC = ");
1108 OUTS (outf, pregs (x));
1109 OUTS (outf, " < ");
1110 OUTS (outf, pregs (y));
1111 }
1112 else if (opc == 2 && I == 0 && G == 1)
1113 {
1114 OUTS (outf, "CC = ");
1115 OUTS (outf, pregs (x));
1116 OUTS (outf, " <= ");
1117 OUTS (outf, pregs (y));
1118 }
1119 else if (opc == 3 && I == 0 && G == 1)
1120 {
1121 OUTS (outf, "CC = ");
1122 OUTS (outf, pregs (x));
1123 OUTS (outf, " < ");
1124 OUTS (outf, pregs (y));
1125 OUTS (outf, " (IU)");
1126 }
1127 else if (opc == 4 && I == 0 && G == 1)
1128 {
1129 OUTS (outf, "CC = ");
1130 OUTS (outf, pregs (x));
1131 OUTS (outf, " <= ");
1132 OUTS (outf, pregs (y));
1133 OUTS (outf, " (IU)");
1134 }
1135 else if (opc == 0 && I == 1 && G == 1)
1136 {
1137 OUTS (outf, "CC = ");
1138 OUTS (outf, pregs (x));
1139 OUTS (outf, " == ");
1140 OUTS (outf, imm3 (y));
1141 }
1142 else if (opc == 1 && I == 1 && G == 1)
1143 {
1144 OUTS (outf, "CC = ");
1145 OUTS (outf, pregs (x));
1146 OUTS (outf, " < ");
1147 OUTS (outf, imm3 (y));
1148 }
1149 else if (opc == 2 && I == 1 && G == 1)
1150 {
1151 OUTS (outf, "CC = ");
1152 OUTS (outf, pregs (x));
1153 OUTS (outf, " <= ");
1154 OUTS (outf, imm3 (y));
1155 }
1156 else if (opc == 3 && I == 1 && G == 1)
1157 {
1158 OUTS (outf, "CC = ");
1159 OUTS (outf, pregs (x));
1160 OUTS (outf, " < ");
1161 OUTS (outf, uimm3 (y));
1162 OUTS (outf, " (IU)");
1163 }
1164 else if (opc == 4 && I == 1 && G == 1)
1165 {
1166 OUTS (outf, "CC = ");
1167 OUTS (outf, pregs (x));
1168 OUTS (outf, " <= ");
1169 OUTS (outf, uimm3 (y));
1170 OUTS (outf, " (IU)");
1171 }
1172 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
1173 OUTS (outf, "CC = A0 == A1");
1174
1175 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
1176 OUTS (outf, "CC = A0 < A1");
1177
1178 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
1179 OUTS (outf, "CC = A0 <= A1");
1180
1181 else
1182 return 0;
1183 return 2;
1184 }
1185
1186 static int
1187 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1188 {
1189 struct private *priv = outf->private_data;
1190 /* CC2dreg
1191 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1192 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1193 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1194 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1195 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1196
1197 if (priv->parallel)
1198 return 0;
1199
1200 if (op == 0)
1201 {
1202 OUTS (outf, dregs (reg));
1203 OUTS (outf, " = CC");
1204 }
1205 else if (op == 1)
1206 {
1207 OUTS (outf, "CC = ");
1208 OUTS (outf, dregs (reg));
1209 }
1210 else if (op == 3 && reg == 0)
1211 OUTS (outf, "CC = !CC");
1212 else
1213 return 0;
1214
1215 return 2;
1216 }
1217
1218 static int
1219 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1220 {
1221 struct private *priv = outf->private_data;
1222 /* CC2stat
1223 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1224 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1225 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1226 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1227 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1228 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1229
1230 const char *bitname = statbits (cbit);
1231 const char * const op_names[] = { "", "|", "&", "^" } ;
1232
1233 if (priv->parallel)
1234 return 0;
1235
1236 if (decode_statbits[cbit] == REG_LASTREG)
1237 {
1238 /* All ASTAT bits except CC may be operated on in hardware, but may
1239 not have a dedicated insn, so still decode "valid" insns. */
1240 static char bitnames[64];
1241 if (cbit != 5)
1242 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1243 else
1244 return 0;
1245
1246 bitname = bitnames;
1247 }
1248
1249 if (D == 0)
1250 OUT (outf, "CC %s= %s", op_names[op], bitname);
1251 else
1252 OUT (outf, "%s %s= CC", bitname, op_names[op]);
1253
1254 return 2;
1255 }
1256
1257 static int
1258 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1259 {
1260 struct private *priv = outf->private_data;
1261 /* BRCC
1262 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1263 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1264 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1265 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1266 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1267 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1268
1269 if (priv->parallel)
1270 return 0;
1271
1272 if (T == 1 && B == 1)
1273 {
1274 OUTS (outf, "IF CC JUMP 0x");
1275 OUTS (outf, pcrel10 (offset));
1276 OUTS (outf, " (BP)");
1277 }
1278 else if (T == 0 && B == 1)
1279 {
1280 OUTS (outf, "IF !CC JUMP 0x");
1281 OUTS (outf, pcrel10 (offset));
1282 OUTS (outf, " (BP)");
1283 }
1284 else if (T == 1)
1285 {
1286 OUTS (outf, "IF CC JUMP 0x");
1287 OUTS (outf, pcrel10 (offset));
1288 }
1289 else if (T == 0)
1290 {
1291 OUTS (outf, "IF !CC JUMP 0x");
1292 OUTS (outf, pcrel10 (offset));
1293 }
1294 else
1295 return 0;
1296
1297 return 2;
1298 }
1299
1300 static int
1301 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1302 {
1303 struct private *priv = outf->private_data;
1304 /* UJUMP
1305 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1306 | 0 | 0 | 1 | 0 |.offset........................................|
1307 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1308 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1309
1310 if (priv->parallel)
1311 return 0;
1312
1313 OUTS (outf, "JUMP.S 0x");
1314 OUTS (outf, pcrel12 (offset));
1315 return 2;
1316 }
1317
1318 static int
1319 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1320 {
1321 /* REGMV
1322 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1323 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1324 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1325 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1326 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1327 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1328 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1329
1330 /* Reserved slots cannot be a src/dst. */
1331 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1332 goto invalid_move;
1333
1334 /* Standard register moves */
1335 if ((gs < 2) || /* Dregs/Pregs as source */
1336 (gd < 2) || /* Dregs/Pregs as dest */
1337 (gs == 4 && src < 4) || /* Accumulators as source */
1338 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1339 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1340 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1341 goto valid_move;
1342
1343 /* dareg = dareg (IMBL) */
1344 if (gs < 4 && gd < 4)
1345 goto valid_move;
1346
1347 /* USP can be src to sysregs, but not dagregs. */
1348 if ((gs == 7 && src == 0) && (gd >= 4))
1349 goto valid_move;
1350
1351 /* USP can move between genregs (only check Accumulators). */
1352 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1353 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1354 goto valid_move;
1355
1356 /* Still here ? Invalid reg pair. */
1357 invalid_move:
1358 return 0;
1359
1360 valid_move:
1361 OUTS (outf, allregs (dst, gd));
1362 OUTS (outf, " = ");
1363 OUTS (outf, allregs (src, gs));
1364 return 2;
1365 }
1366
1367 static int
1368 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1369 {
1370 /* ALU2op
1371 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1372 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1373 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1374 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1375 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1376 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1377
1378 if (opc == 0)
1379 {
1380 OUTS (outf, dregs (dst));
1381 OUTS (outf, " >>>= ");
1382 OUTS (outf, dregs (src));
1383 }
1384 else if (opc == 1)
1385 {
1386 OUTS (outf, dregs (dst));
1387 OUTS (outf, " >>= ");
1388 OUTS (outf, dregs (src));
1389 }
1390 else if (opc == 2)
1391 {
1392 OUTS (outf, dregs (dst));
1393 OUTS (outf, " <<= ");
1394 OUTS (outf, dregs (src));
1395 }
1396 else if (opc == 3)
1397 {
1398 OUTS (outf, dregs (dst));
1399 OUTS (outf, " *= ");
1400 OUTS (outf, dregs (src));
1401 }
1402 else if (opc == 4)
1403 {
1404 OUTS (outf, dregs (dst));
1405 OUTS (outf, " = (");
1406 OUTS (outf, dregs (dst));
1407 OUTS (outf, " + ");
1408 OUTS (outf, dregs (src));
1409 OUTS (outf, ") << 0x1");
1410 }
1411 else if (opc == 5)
1412 {
1413 OUTS (outf, dregs (dst));
1414 OUTS (outf, " = (");
1415 OUTS (outf, dregs (dst));
1416 OUTS (outf, " + ");
1417 OUTS (outf, dregs (src));
1418 OUTS (outf, ") << 0x2");
1419 }
1420 else if (opc == 8)
1421 {
1422 OUTS (outf, "DIVQ (");
1423 OUTS (outf, dregs (dst));
1424 OUTS (outf, ", ");
1425 OUTS (outf, dregs (src));
1426 OUTS (outf, ")");
1427 }
1428 else if (opc == 9)
1429 {
1430 OUTS (outf, "DIVS (");
1431 OUTS (outf, dregs (dst));
1432 OUTS (outf, ", ");
1433 OUTS (outf, dregs (src));
1434 OUTS (outf, ")");
1435 }
1436 else if (opc == 10)
1437 {
1438 OUTS (outf, dregs (dst));
1439 OUTS (outf, " = ");
1440 OUTS (outf, dregs_lo (src));
1441 OUTS (outf, " (X)");
1442 }
1443 else if (opc == 11)
1444 {
1445 OUTS (outf, dregs (dst));
1446 OUTS (outf, " = ");
1447 OUTS (outf, dregs_lo (src));
1448 OUTS (outf, " (Z)");
1449 }
1450 else if (opc == 12)
1451 {
1452 OUTS (outf, dregs (dst));
1453 OUTS (outf, " = ");
1454 OUTS (outf, dregs_byte (src));
1455 OUTS (outf, " (X)");
1456 }
1457 else if (opc == 13)
1458 {
1459 OUTS (outf, dregs (dst));
1460 OUTS (outf, " = ");
1461 OUTS (outf, dregs_byte (src));
1462 OUTS (outf, " (Z)");
1463 }
1464 else if (opc == 14)
1465 {
1466 OUTS (outf, dregs (dst));
1467 OUTS (outf, " = -");
1468 OUTS (outf, dregs (src));
1469 }
1470 else if (opc == 15)
1471 {
1472 OUTS (outf, dregs (dst));
1473 OUTS (outf, " =~ ");
1474 OUTS (outf, dregs (src));
1475 }
1476 else
1477 return 0;
1478
1479 return 2;
1480 }
1481
1482 static int
1483 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1484 {
1485 /* PTR2op
1486 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1487 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1488 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1489 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1490 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1491 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1492
1493 if (opc == 0)
1494 {
1495 OUTS (outf, pregs (dst));
1496 OUTS (outf, " -= ");
1497 OUTS (outf, pregs (src));
1498 }
1499 else if (opc == 1)
1500 {
1501 OUTS (outf, pregs (dst));
1502 OUTS (outf, " = ");
1503 OUTS (outf, pregs (src));
1504 OUTS (outf, " << 0x2");
1505 }
1506 else if (opc == 3)
1507 {
1508 OUTS (outf, pregs (dst));
1509 OUTS (outf, " = ");
1510 OUTS (outf, pregs (src));
1511 OUTS (outf, " >> 0x2");
1512 }
1513 else if (opc == 4)
1514 {
1515 OUTS (outf, pregs (dst));
1516 OUTS (outf, " = ");
1517 OUTS (outf, pregs (src));
1518 OUTS (outf, " >> 0x1");
1519 }
1520 else if (opc == 5)
1521 {
1522 OUTS (outf, pregs (dst));
1523 OUTS (outf, " += ");
1524 OUTS (outf, pregs (src));
1525 OUTS (outf, " (BREV)");
1526 }
1527 else if (opc == 6)
1528 {
1529 OUTS (outf, pregs (dst));
1530 OUTS (outf, " = (");
1531 OUTS (outf, pregs (dst));
1532 OUTS (outf, " + ");
1533 OUTS (outf, pregs (src));
1534 OUTS (outf, ") << 0x1");
1535 }
1536 else if (opc == 7)
1537 {
1538 OUTS (outf, pregs (dst));
1539 OUTS (outf, " = (");
1540 OUTS (outf, pregs (dst));
1541 OUTS (outf, " + ");
1542 OUTS (outf, pregs (src));
1543 OUTS (outf, ") << 0x2");
1544 }
1545 else
1546 return 0;
1547
1548 return 2;
1549 }
1550
1551 static int
1552 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1553 {
1554 struct private *priv = outf->private_data;
1555 /* LOGI2op
1556 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1557 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1558 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1559 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1560 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1561 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1562
1563 if (priv->parallel)
1564 return 0;
1565
1566 if (opc == 0)
1567 {
1568 OUTS (outf, "CC = !BITTST (");
1569 OUTS (outf, dregs (dst));
1570 OUTS (outf, ", ");
1571 OUTS (outf, uimm5 (src));
1572 OUTS (outf, ");\t\t/* bit");
1573 OUTS (outf, imm7d (src));
1574 OUTS (outf, " */");
1575 priv->comment = TRUE;
1576 }
1577 else if (opc == 1)
1578 {
1579 OUTS (outf, "CC = BITTST (");
1580 OUTS (outf, dregs (dst));
1581 OUTS (outf, ", ");
1582 OUTS (outf, uimm5 (src));
1583 OUTS (outf, ");\t\t/* bit");
1584 OUTS (outf, imm7d (src));
1585 OUTS (outf, " */");
1586 priv->comment = TRUE;
1587 }
1588 else if (opc == 2)
1589 {
1590 OUTS (outf, "BITSET (");
1591 OUTS (outf, dregs (dst));
1592 OUTS (outf, ", ");
1593 OUTS (outf, uimm5 (src));
1594 OUTS (outf, ");\t\t/* bit");
1595 OUTS (outf, imm7d (src));
1596 OUTS (outf, " */");
1597 priv->comment = TRUE;
1598 }
1599 else if (opc == 3)
1600 {
1601 OUTS (outf, "BITTGL (");
1602 OUTS (outf, dregs (dst));
1603 OUTS (outf, ", ");
1604 OUTS (outf, uimm5 (src));
1605 OUTS (outf, ");\t\t/* bit");
1606 OUTS (outf, imm7d (src));
1607 OUTS (outf, " */");
1608 priv->comment = TRUE;
1609 }
1610 else if (opc == 4)
1611 {
1612 OUTS (outf, "BITCLR (");
1613 OUTS (outf, dregs (dst));
1614 OUTS (outf, ", ");
1615 OUTS (outf, uimm5 (src));
1616 OUTS (outf, ");\t\t/* bit");
1617 OUTS (outf, imm7d (src));
1618 OUTS (outf, " */");
1619 priv->comment = TRUE;
1620 }
1621 else if (opc == 5)
1622 {
1623 OUTS (outf, dregs (dst));
1624 OUTS (outf, " >>>= ");
1625 OUTS (outf, uimm5 (src));
1626 }
1627 else if (opc == 6)
1628 {
1629 OUTS (outf, dregs (dst));
1630 OUTS (outf, " >>= ");
1631 OUTS (outf, uimm5 (src));
1632 }
1633 else if (opc == 7)
1634 {
1635 OUTS (outf, dregs (dst));
1636 OUTS (outf, " <<= ");
1637 OUTS (outf, uimm5 (src));
1638 }
1639 else
1640 return 0;
1641
1642 return 2;
1643 }
1644
1645 static int
1646 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1647 {
1648 /* COMP3op
1649 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1650 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1651 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1652 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1653 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1654 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1655 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1656
1657 if (opc == 5 && src1 == src0)
1658 {
1659 OUTS (outf, pregs (dst));
1660 OUTS (outf, " = ");
1661 OUTS (outf, pregs (src0));
1662 OUTS (outf, " << 0x1");
1663 }
1664 else if (opc == 1)
1665 {
1666 OUTS (outf, dregs (dst));
1667 OUTS (outf, " = ");
1668 OUTS (outf, dregs (src0));
1669 OUTS (outf, " - ");
1670 OUTS (outf, dregs (src1));
1671 }
1672 else if (opc == 2)
1673 {
1674 OUTS (outf, dregs (dst));
1675 OUTS (outf, " = ");
1676 OUTS (outf, dregs (src0));
1677 OUTS (outf, " & ");
1678 OUTS (outf, dregs (src1));
1679 }
1680 else if (opc == 3)
1681 {
1682 OUTS (outf, dregs (dst));
1683 OUTS (outf, " = ");
1684 OUTS (outf, dregs (src0));
1685 OUTS (outf, " | ");
1686 OUTS (outf, dregs (src1));
1687 }
1688 else if (opc == 4)
1689 {
1690 OUTS (outf, dregs (dst));
1691 OUTS (outf, " = ");
1692 OUTS (outf, dregs (src0));
1693 OUTS (outf, " ^ ");
1694 OUTS (outf, dregs (src1));
1695 }
1696 else if (opc == 5)
1697 {
1698 OUTS (outf, pregs (dst));
1699 OUTS (outf, " = ");
1700 OUTS (outf, pregs (src0));
1701 OUTS (outf, " + ");
1702 OUTS (outf, pregs (src1));
1703 }
1704 else if (opc == 6)
1705 {
1706 OUTS (outf, pregs (dst));
1707 OUTS (outf, " = ");
1708 OUTS (outf, pregs (src0));
1709 OUTS (outf, " + (");
1710 OUTS (outf, pregs (src1));
1711 OUTS (outf, " << 0x1)");
1712 }
1713 else if (opc == 7)
1714 {
1715 OUTS (outf, pregs (dst));
1716 OUTS (outf, " = ");
1717 OUTS (outf, pregs (src0));
1718 OUTS (outf, " + (");
1719 OUTS (outf, pregs (src1));
1720 OUTS (outf, " << 0x2)");
1721 }
1722 else if (opc == 0)
1723 {
1724 OUTS (outf, dregs (dst));
1725 OUTS (outf, " = ");
1726 OUTS (outf, dregs (src0));
1727 OUTS (outf, " + ");
1728 OUTS (outf, dregs (src1));
1729 }
1730 else
1731 return 0;
1732
1733 return 2;
1734 }
1735
1736 static int
1737 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1738 {
1739 struct private *priv = outf->private_data;
1740 /* COMPI2opD
1741 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1742 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1743 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1744 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1745 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1746 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1747
1748 bu32 *pval = get_allreg (0, dst);
1749
1750 if (priv->parallel)
1751 return 0;
1752
1753 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1754 to combine them, so it prints out the right values.
1755 Here we keep track of the registers. */
1756 if (op == 0)
1757 {
1758 *pval = imm7_val (src);
1759 if (src & 0x40)
1760 *pval |= 0xFFFFFF80;
1761 else
1762 *pval &= 0x7F;
1763 }
1764
1765 if (op == 0)
1766 {
1767 OUTS (outf, dregs (dst));
1768 OUTS (outf, " = ");
1769 OUTS (outf, imm7 (src));
1770 OUTS (outf, " (X);\t\t/*\t\t");
1771 OUTS (outf, dregs (dst));
1772 OUTS (outf, "=");
1773 OUTS (outf, uimm32 (*pval));
1774 OUTS (outf, "(");
1775 OUTS (outf, imm32 (*pval));
1776 OUTS (outf, ") */");
1777 priv->comment = TRUE;
1778 }
1779 else if (op == 1)
1780 {
1781 OUTS (outf, dregs (dst));
1782 OUTS (outf, " += ");
1783 OUTS (outf, imm7 (src));
1784 OUTS (outf, ";\t\t/* (");
1785 OUTS (outf, imm7d (src));
1786 OUTS (outf, ") */");
1787 priv->comment = TRUE;
1788 }
1789 else
1790 return 0;
1791
1792 return 2;
1793 }
1794
1795 static int
1796 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1797 {
1798 struct private *priv = outf->private_data;
1799 /* COMPI2opP
1800 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1801 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1802 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1803 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1804 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1805 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1806
1807 bu32 *pval = get_allreg (1, dst);
1808
1809 if (priv->parallel)
1810 return 0;
1811
1812 if (op == 0)
1813 {
1814 *pval = imm7_val (src);
1815 if (src & 0x40)
1816 *pval |= 0xFFFFFF80;
1817 else
1818 *pval &= 0x7F;
1819 }
1820
1821 if (op == 0)
1822 {
1823 OUTS (outf, pregs (dst));
1824 OUTS (outf, " = ");
1825 OUTS (outf, imm7 (src));
1826 OUTS (outf, " (X);\t\t/*\t\t");
1827 OUTS (outf, pregs (dst));
1828 OUTS (outf, "=");
1829 OUTS (outf, uimm32 (*pval));
1830 OUTS (outf, "(");
1831 OUTS (outf, imm32 (*pval));
1832 OUTS (outf, ") */");
1833 priv->comment = TRUE;
1834 }
1835 else if (op == 1)
1836 {
1837 OUTS (outf, pregs (dst));
1838 OUTS (outf, " += ");
1839 OUTS (outf, imm7 (src));
1840 OUTS (outf, ";\t\t/* (");
1841 OUTS (outf, imm7d (src));
1842 OUTS (outf, ") */");
1843 priv->comment = TRUE;
1844 }
1845 else
1846 return 0;
1847
1848 return 2;
1849 }
1850
1851 static int
1852 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1853 {
1854 /* LDSTpmod
1855 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1856 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1857 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1858 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1859 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1860 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1861 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1862 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1863
1864 if (aop == 1 && W == 0 && idx == ptr)
1865 {
1866 OUTS (outf, dregs_lo (reg));
1867 OUTS (outf, " = W[");
1868 OUTS (outf, pregs (ptr));
1869 OUTS (outf, "]");
1870 }
1871 else if (aop == 2 && W == 0 && idx == ptr)
1872 {
1873 OUTS (outf, dregs_hi (reg));
1874 OUTS (outf, " = W[");
1875 OUTS (outf, pregs (ptr));
1876 OUTS (outf, "]");
1877 }
1878 else if (aop == 1 && W == 1 && idx == ptr)
1879 {
1880 OUTS (outf, "W[");
1881 OUTS (outf, pregs (ptr));
1882 OUTS (outf, "] = ");
1883 OUTS (outf, dregs_lo (reg));
1884 }
1885 else if (aop == 2 && W == 1 && idx == ptr)
1886 {
1887 OUTS (outf, "W[");
1888 OUTS (outf, pregs (ptr));
1889 OUTS (outf, "] = ");
1890 OUTS (outf, dregs_hi (reg));
1891 }
1892 else if (aop == 0 && W == 0)
1893 {
1894 OUTS (outf, dregs (reg));
1895 OUTS (outf, " = [");
1896 OUTS (outf, pregs (ptr));
1897 OUTS (outf, " ++ ");
1898 OUTS (outf, pregs (idx));
1899 OUTS (outf, "]");
1900 }
1901 else if (aop == 1 && W == 0)
1902 {
1903 OUTS (outf, dregs_lo (reg));
1904 OUTS (outf, " = W[");
1905 OUTS (outf, pregs (ptr));
1906 OUTS (outf, " ++ ");
1907 OUTS (outf, pregs (idx));
1908 OUTS (outf, "]");
1909 }
1910 else if (aop == 2 && W == 0)
1911 {
1912 OUTS (outf, dregs_hi (reg));
1913 OUTS (outf, " = W[");
1914 OUTS (outf, pregs (ptr));
1915 OUTS (outf, " ++ ");
1916 OUTS (outf, pregs (idx));
1917 OUTS (outf, "]");
1918 }
1919 else if (aop == 3 && W == 0)
1920 {
1921 OUTS (outf, dregs (reg));
1922 OUTS (outf, " = W[");
1923 OUTS (outf, pregs (ptr));
1924 OUTS (outf, " ++ ");
1925 OUTS (outf, pregs (idx));
1926 OUTS (outf, "] (Z)");
1927 }
1928 else if (aop == 3 && W == 1)
1929 {
1930 OUTS (outf, dregs (reg));
1931 OUTS (outf, " = W[");
1932 OUTS (outf, pregs (ptr));
1933 OUTS (outf, " ++ ");
1934 OUTS (outf, pregs (idx));
1935 OUTS (outf, "] (X)");
1936 }
1937 else if (aop == 0 && W == 1)
1938 {
1939 OUTS (outf, "[");
1940 OUTS (outf, pregs (ptr));
1941 OUTS (outf, " ++ ");
1942 OUTS (outf, pregs (idx));
1943 OUTS (outf, "] = ");
1944 OUTS (outf, dregs (reg));
1945 }
1946 else if (aop == 1 && W == 1)
1947 {
1948 OUTS (outf, "W[");
1949 OUTS (outf, pregs (ptr));
1950 OUTS (outf, " ++ ");
1951 OUTS (outf, pregs (idx));
1952 OUTS (outf, "] = ");
1953 OUTS (outf, dregs_lo (reg));
1954 }
1955 else if (aop == 2 && W == 1)
1956 {
1957 OUTS (outf, "W[");
1958 OUTS (outf, pregs (ptr));
1959 OUTS (outf, " ++ ");
1960 OUTS (outf, pregs (idx));
1961 OUTS (outf, "] = ");
1962 OUTS (outf, dregs_hi (reg));
1963 }
1964 else
1965 return 0;
1966
1967 return 2;
1968 }
1969
1970 static int
1971 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1972 {
1973 /* dagMODim
1974 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1975 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1976 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1977 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1978 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1979 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1980 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
1981
1982 if (op == 0 && br == 1)
1983 {
1984 OUTS (outf, iregs (i));
1985 OUTS (outf, " += ");
1986 OUTS (outf, mregs (m));
1987 OUTS (outf, " (BREV)");
1988 }
1989 else if (op == 0)
1990 {
1991 OUTS (outf, iregs (i));
1992 OUTS (outf, " += ");
1993 OUTS (outf, mregs (m));
1994 }
1995 else if (op == 1 && br == 0)
1996 {
1997 OUTS (outf, iregs (i));
1998 OUTS (outf, " -= ");
1999 OUTS (outf, mregs (m));
2000 }
2001 else
2002 return 0;
2003
2004 return 2;
2005 }
2006
2007 static int
2008 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2009 {
2010 struct private *priv = outf->private_data;
2011 /* dagMODik
2012 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2013 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2014 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2015 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2016 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2017
2018 if (op == 0)
2019 {
2020 OUTS (outf, iregs (i));
2021 OUTS (outf, " += 0x2");
2022 }
2023 else if (op == 1)
2024 {
2025 OUTS (outf, iregs (i));
2026 OUTS (outf, " -= 0x2");
2027 }
2028 else if (op == 2)
2029 {
2030 OUTS (outf, iregs (i));
2031 OUTS (outf, " += 0x4");
2032 }
2033 else if (op == 3)
2034 {
2035 OUTS (outf, iregs (i));
2036 OUTS (outf, " -= 0x4");
2037 }
2038 else
2039 return 0;
2040
2041 if (!priv->parallel)
2042 {
2043 OUTS (outf, ";\t\t/* ( ");
2044 if (op == 0 || op == 1)
2045 OUTS (outf, "2");
2046 else if (op == 2 || op == 3)
2047 OUTS (outf, "4");
2048 OUTS (outf, ") */");
2049 priv->comment = TRUE;
2050 }
2051
2052 return 2;
2053 }
2054
2055 static int
2056 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2057 {
2058 /* dspLDST
2059 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2060 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2061 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2062 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2063 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2064 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2065 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2066 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2067
2068 if (aop == 0 && W == 0 && m == 0)
2069 {
2070 OUTS (outf, dregs (reg));
2071 OUTS (outf, " = [");
2072 OUTS (outf, iregs (i));
2073 OUTS (outf, "++]");
2074 }
2075 else if (aop == 0 && W == 0 && m == 1)
2076 {
2077 OUTS (outf, dregs_lo (reg));
2078 OUTS (outf, " = W[");
2079 OUTS (outf, iregs (i));
2080 OUTS (outf, "++]");
2081 }
2082 else if (aop == 0 && W == 0 && m == 2)
2083 {
2084 OUTS (outf, dregs_hi (reg));
2085 OUTS (outf, " = W[");
2086 OUTS (outf, iregs (i));
2087 OUTS (outf, "++]");
2088 }
2089 else if (aop == 1 && W == 0 && m == 0)
2090 {
2091 OUTS (outf, dregs (reg));
2092 OUTS (outf, " = [");
2093 OUTS (outf, iregs (i));
2094 OUTS (outf, "--]");
2095 }
2096 else if (aop == 1 && W == 0 && m == 1)
2097 {
2098 OUTS (outf, dregs_lo (reg));
2099 OUTS (outf, " = W[");
2100 OUTS (outf, iregs (i));
2101 OUTS (outf, "--]");
2102 }
2103 else if (aop == 1 && W == 0 && m == 2)
2104 {
2105 OUTS (outf, dregs_hi (reg));
2106 OUTS (outf, " = W[");
2107 OUTS (outf, iregs (i));
2108 OUTS (outf, "--]");
2109 }
2110 else if (aop == 2 && W == 0 && m == 0)
2111 {
2112 OUTS (outf, dregs (reg));
2113 OUTS (outf, " = [");
2114 OUTS (outf, iregs (i));
2115 OUTS (outf, "]");
2116 }
2117 else if (aop == 2 && W == 0 && m == 1)
2118 {
2119 OUTS (outf, dregs_lo (reg));
2120 OUTS (outf, " = W[");
2121 OUTS (outf, iregs (i));
2122 OUTS (outf, "]");
2123 }
2124 else if (aop == 2 && W == 0 && m == 2)
2125 {
2126 OUTS (outf, dregs_hi (reg));
2127 OUTS (outf, " = W[");
2128 OUTS (outf, iregs (i));
2129 OUTS (outf, "]");
2130 }
2131 else if (aop == 0 && W == 1 && m == 0)
2132 {
2133 OUTS (outf, "[");
2134 OUTS (outf, iregs (i));
2135 OUTS (outf, "++] = ");
2136 OUTS (outf, dregs (reg));
2137 }
2138 else if (aop == 0 && W == 1 && m == 1)
2139 {
2140 OUTS (outf, "W[");
2141 OUTS (outf, iregs (i));
2142 OUTS (outf, "++] = ");
2143 OUTS (outf, dregs_lo (reg));
2144 }
2145 else if (aop == 0 && W == 1 && m == 2)
2146 {
2147 OUTS (outf, "W[");
2148 OUTS (outf, iregs (i));
2149 OUTS (outf, "++] = ");
2150 OUTS (outf, dregs_hi (reg));
2151 }
2152 else if (aop == 1 && W == 1 && m == 0)
2153 {
2154 OUTS (outf, "[");
2155 OUTS (outf, iregs (i));
2156 OUTS (outf, "--] = ");
2157 OUTS (outf, dregs (reg));
2158 }
2159 else if (aop == 1 && W == 1 && m == 1)
2160 {
2161 OUTS (outf, "W[");
2162 OUTS (outf, iregs (i));
2163 OUTS (outf, "--] = ");
2164 OUTS (outf, dregs_lo (reg));
2165 }
2166 else if (aop == 1 && W == 1 && m == 2)
2167 {
2168 OUTS (outf, "W[");
2169 OUTS (outf, iregs (i));
2170 OUTS (outf, "--] = ");
2171 OUTS (outf, dregs_hi (reg));
2172 }
2173 else if (aop == 2 && W == 1 && m == 0)
2174 {
2175 OUTS (outf, "[");
2176 OUTS (outf, iregs (i));
2177 OUTS (outf, "] = ");
2178 OUTS (outf, dregs (reg));
2179 }
2180 else if (aop == 2 && W == 1 && m == 1)
2181 {
2182 OUTS (outf, "W[");
2183 OUTS (outf, iregs (i));
2184 OUTS (outf, "] = ");
2185 OUTS (outf, dregs_lo (reg));
2186 }
2187 else if (aop == 2 && W == 1 && m == 2)
2188 {
2189 OUTS (outf, "W[");
2190 OUTS (outf, iregs (i));
2191 OUTS (outf, "] = ");
2192 OUTS (outf, dregs_hi (reg));
2193 }
2194 else if (aop == 3 && W == 0)
2195 {
2196 OUTS (outf, dregs (reg));
2197 OUTS (outf, " = [");
2198 OUTS (outf, iregs (i));
2199 OUTS (outf, " ++ ");
2200 OUTS (outf, mregs (m));
2201 OUTS (outf, "]");
2202 }
2203 else if (aop == 3 && W == 1)
2204 {
2205 OUTS (outf, "[");
2206 OUTS (outf, iregs (i));
2207 OUTS (outf, " ++ ");
2208 OUTS (outf, mregs (m));
2209 OUTS (outf, "] = ");
2210 OUTS (outf, dregs (reg));
2211 }
2212 else
2213 return 0;
2214
2215 return 2;
2216 }
2217
2218 static int
2219 decode_LDST_0 (TIword iw0, disassemble_info *outf)
2220 {
2221 /* LDST
2222 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2223 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2224 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2225 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2226 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2227 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2228 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2229 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2230 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2231
2232 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2233 {
2234 OUTS (outf, dregs (reg));
2235 OUTS (outf, " = [");
2236 OUTS (outf, pregs (ptr));
2237 OUTS (outf, "++]");
2238 }
2239 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2240 {
2241 OUTS (outf, pregs (reg));
2242 OUTS (outf, " = [");
2243 OUTS (outf, pregs (ptr));
2244 OUTS (outf, "++]");
2245 }
2246 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2247 {
2248 OUTS (outf, dregs (reg));
2249 OUTS (outf, " = W[");
2250 OUTS (outf, pregs (ptr));
2251 OUTS (outf, "++] (Z)");
2252 }
2253 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2254 {
2255 OUTS (outf, dregs (reg));
2256 OUTS (outf, " = W[");
2257 OUTS (outf, pregs (ptr));
2258 OUTS (outf, "++] (X)");
2259 }
2260 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2261 {
2262 OUTS (outf, dregs (reg));
2263 OUTS (outf, " = B[");
2264 OUTS (outf, pregs (ptr));
2265 OUTS (outf, "++] (Z)");
2266 }
2267 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2268 {
2269 OUTS (outf, dregs (reg));
2270 OUTS (outf, " = B[");
2271 OUTS (outf, pregs (ptr));
2272 OUTS (outf, "++] (X)");
2273 }
2274 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2275 {
2276 OUTS (outf, dregs (reg));
2277 OUTS (outf, " = [");
2278 OUTS (outf, pregs (ptr));
2279 OUTS (outf, "--]");
2280 }
2281 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2282 {
2283 OUTS (outf, pregs (reg));
2284 OUTS (outf, " = [");
2285 OUTS (outf, pregs (ptr));
2286 OUTS (outf, "--]");
2287 }
2288 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2289 {
2290 OUTS (outf, dregs (reg));
2291 OUTS (outf, " = W[");
2292 OUTS (outf, pregs (ptr));
2293 OUTS (outf, "--] (Z)");
2294 }
2295 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2296 {
2297 OUTS (outf, dregs (reg));
2298 OUTS (outf, " = W[");
2299 OUTS (outf, pregs (ptr));
2300 OUTS (outf, "--] (X)");
2301 }
2302 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2303 {
2304 OUTS (outf, dregs (reg));
2305 OUTS (outf, " = B[");
2306 OUTS (outf, pregs (ptr));
2307 OUTS (outf, "--] (Z)");
2308 }
2309 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2310 {
2311 OUTS (outf, dregs (reg));
2312 OUTS (outf, " = B[");
2313 OUTS (outf, pregs (ptr));
2314 OUTS (outf, "--] (X)");
2315 }
2316 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2317 {
2318 OUTS (outf, dregs (reg));
2319 OUTS (outf, " = [");
2320 OUTS (outf, pregs (ptr));
2321 OUTS (outf, "]");
2322 }
2323 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2324 {
2325 OUTS (outf, pregs (reg));
2326 OUTS (outf, " = [");
2327 OUTS (outf, pregs (ptr));
2328 OUTS (outf, "]");
2329 }
2330 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2331 {
2332 OUTS (outf, dregs (reg));
2333 OUTS (outf, " = W[");
2334 OUTS (outf, pregs (ptr));
2335 OUTS (outf, "] (Z)");
2336 }
2337 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2338 {
2339 OUTS (outf, dregs (reg));
2340 OUTS (outf, " = W[");
2341 OUTS (outf, pregs (ptr));
2342 OUTS (outf, "] (X)");
2343 }
2344 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2345 {
2346 OUTS (outf, dregs (reg));
2347 OUTS (outf, " = B[");
2348 OUTS (outf, pregs (ptr));
2349 OUTS (outf, "] (Z)");
2350 }
2351 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2352 {
2353 OUTS (outf, dregs (reg));
2354 OUTS (outf, " = B[");
2355 OUTS (outf, pregs (ptr));
2356 OUTS (outf, "] (X)");
2357 }
2358 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2359 {
2360 OUTS (outf, "[");
2361 OUTS (outf, pregs (ptr));
2362 OUTS (outf, "++] = ");
2363 OUTS (outf, dregs (reg));
2364 }
2365 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2366 {
2367 OUTS (outf, "[");
2368 OUTS (outf, pregs (ptr));
2369 OUTS (outf, "++] = ");
2370 OUTS (outf, pregs (reg));
2371 }
2372 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2373 {
2374 OUTS (outf, "W[");
2375 OUTS (outf, pregs (ptr));
2376 OUTS (outf, "++] = ");
2377 OUTS (outf, dregs (reg));
2378 }
2379 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2380 {
2381 OUTS (outf, "B[");
2382 OUTS (outf, pregs (ptr));
2383 OUTS (outf, "++] = ");
2384 OUTS (outf, dregs (reg));
2385 }
2386 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2387 {
2388 OUTS (outf, "[");
2389 OUTS (outf, pregs (ptr));
2390 OUTS (outf, "--] = ");
2391 OUTS (outf, dregs (reg));
2392 }
2393 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2394 {
2395 OUTS (outf, "[");
2396 OUTS (outf, pregs (ptr));
2397 OUTS (outf, "--] = ");
2398 OUTS (outf, pregs (reg));
2399 }
2400 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2401 {
2402 OUTS (outf, "W[");
2403 OUTS (outf, pregs (ptr));
2404 OUTS (outf, "--] = ");
2405 OUTS (outf, dregs (reg));
2406 }
2407 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2408 {
2409 OUTS (outf, "B[");
2410 OUTS (outf, pregs (ptr));
2411 OUTS (outf, "--] = ");
2412 OUTS (outf, dregs (reg));
2413 }
2414 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2415 {
2416 OUTS (outf, "[");
2417 OUTS (outf, pregs (ptr));
2418 OUTS (outf, "] = ");
2419 OUTS (outf, dregs (reg));
2420 }
2421 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2422 {
2423 OUTS (outf, "[");
2424 OUTS (outf, pregs (ptr));
2425 OUTS (outf, "] = ");
2426 OUTS (outf, pregs (reg));
2427 }
2428 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2429 {
2430 OUTS (outf, "W[");
2431 OUTS (outf, pregs (ptr));
2432 OUTS (outf, "] = ");
2433 OUTS (outf, dregs (reg));
2434 }
2435 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2436 {
2437 OUTS (outf, "B[");
2438 OUTS (outf, pregs (ptr));
2439 OUTS (outf, "] = ");
2440 OUTS (outf, dregs (reg));
2441 }
2442 else
2443 return 0;
2444
2445 return 2;
2446 }
2447
2448 static int
2449 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2450 {
2451 /* LDSTiiFP
2452 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2453 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2454 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2455 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2456 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2457 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2458
2459 if (W == 0)
2460 {
2461 OUTS (outf, dpregs (reg));
2462 OUTS (outf, " = [FP ");
2463 OUTS (outf, negimm5s4 (offset));
2464 OUTS (outf, "]");
2465 }
2466 else if (W == 1)
2467 {
2468 OUTS (outf, "[FP ");
2469 OUTS (outf, negimm5s4 (offset));
2470 OUTS (outf, "] = ");
2471 OUTS (outf, dpregs (reg));
2472 }
2473 else
2474 return 0;
2475
2476 return 2;
2477 }
2478
2479 static int
2480 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2481 {
2482 /* LDSTii
2483 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2484 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2485 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2486 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2487 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2488 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2489 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2490 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2491
2492 if (W == 0 && op == 0)
2493 {
2494 OUTS (outf, dregs (reg));
2495 OUTS (outf, " = [");
2496 OUTS (outf, pregs (ptr));
2497 OUTS (outf, " + ");
2498 OUTS (outf, uimm4s4 (offset));
2499 OUTS (outf, "]");
2500 }
2501 else if (W == 0 && op == 1)
2502 {
2503 OUTS (outf, dregs (reg));
2504 OUTS (outf, " = W[");
2505 OUTS (outf, pregs (ptr));
2506 OUTS (outf, " + ");
2507 OUTS (outf, uimm4s2 (offset));
2508 OUTS (outf, "] (Z)");
2509 }
2510 else if (W == 0 && op == 2)
2511 {
2512 OUTS (outf, dregs (reg));
2513 OUTS (outf, " = W[");
2514 OUTS (outf, pregs (ptr));
2515 OUTS (outf, " + ");
2516 OUTS (outf, uimm4s2 (offset));
2517 OUTS (outf, "] (X)");
2518 }
2519 else if (W == 0 && op == 3)
2520 {
2521 OUTS (outf, pregs (reg));
2522 OUTS (outf, " = [");
2523 OUTS (outf, pregs (ptr));
2524 OUTS (outf, " + ");
2525 OUTS (outf, uimm4s4 (offset));
2526 OUTS (outf, "]");
2527 }
2528 else if (W == 1 && op == 0)
2529 {
2530 OUTS (outf, "[");
2531 OUTS (outf, pregs (ptr));
2532 OUTS (outf, " + ");
2533 OUTS (outf, uimm4s4 (offset));
2534 OUTS (outf, "] = ");
2535 OUTS (outf, dregs (reg));
2536 }
2537 else if (W == 1 && op == 1)
2538 {
2539 OUTS (outf, "W[");
2540 OUTS (outf, pregs (ptr));
2541 OUTS (outf, " + ");
2542 OUTS (outf, uimm4s2 (offset));
2543 OUTS (outf, "] = ");
2544 OUTS (outf, dregs (reg));
2545 }
2546 else if (W == 1 && op == 3)
2547 {
2548 OUTS (outf, "[");
2549 OUTS (outf, pregs (ptr));
2550 OUTS (outf, " + ");
2551 OUTS (outf, uimm4s4 (offset));
2552 OUTS (outf, "] = ");
2553 OUTS (outf, pregs (reg));
2554 }
2555 else
2556 return 0;
2557
2558 return 2;
2559 }
2560
2561 static int
2562 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2563 {
2564 struct private *priv = outf->private_data;
2565 /* LoopSetup
2566 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2567 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2568 |.reg...........| - | - |.eoffset...............................|
2569 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2570 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2571 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2572 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2573 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2574 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2575
2576 if (priv->parallel)
2577 return 0;
2578
2579 if (reg > 7)
2580 return 0;
2581
2582 if (rop == 0)
2583 {
2584 OUTS (outf, "LSETUP");
2585 OUTS (outf, "(0x");
2586 OUTS (outf, pcrel4 (soffset));
2587 OUTS (outf, ", 0x");
2588 OUTS (outf, lppcrel10 (eoffset));
2589 OUTS (outf, ") ");
2590 OUTS (outf, counters (c));
2591 }
2592 else if (rop == 1)
2593 {
2594 OUTS (outf, "LSETUP");
2595 OUTS (outf, "(0x");
2596 OUTS (outf, pcrel4 (soffset));
2597 OUTS (outf, ", 0x");
2598 OUTS (outf, lppcrel10 (eoffset));
2599 OUTS (outf, ") ");
2600 OUTS (outf, counters (c));
2601 OUTS (outf, " = ");
2602 OUTS (outf, pregs (reg));
2603 }
2604 else if (rop == 3)
2605 {
2606 OUTS (outf, "LSETUP");
2607 OUTS (outf, "(0x");
2608 OUTS (outf, pcrel4 (soffset));
2609 OUTS (outf, ", 0x");
2610 OUTS (outf, lppcrel10 (eoffset));
2611 OUTS (outf, ") ");
2612 OUTS (outf, counters (c));
2613 OUTS (outf, " = ");
2614 OUTS (outf, pregs (reg));
2615 OUTS (outf, " >> 0x1");
2616 }
2617 else
2618 return 0;
2619
2620 return 4;
2621 }
2622
2623 static int
2624 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2625 {
2626 struct private *priv = outf->private_data;
2627 /* LDIMMhalf
2628 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2629 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2630 |.hword.........................................................|
2631 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2632 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2633 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2634 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2635 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2636 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2637 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2638
2639 bu32 *pval = get_allreg (grp, reg);
2640
2641 if (priv->parallel)
2642 return 0;
2643
2644 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2645 to combine them, so it prints out the right values.
2646 Here we keep track of the registers. */
2647 if (H == 0 && S == 1 && Z == 0)
2648 {
2649 /* regs = imm16 (x) */
2650 *pval = imm16_val (hword);
2651 if (hword & 0x8000)
2652 *pval |= 0xFFFF0000;
2653 else
2654 *pval &= 0xFFFF;
2655 }
2656 else if (H == 0 && S == 0 && Z == 1)
2657 {
2658 /* regs = luimm16 (Z) */
2659 *pval = luimm16_val (hword);
2660 *pval &= 0xFFFF;
2661 }
2662 else if (H == 0 && S == 0 && Z == 0)
2663 {
2664 /* regs_lo = luimm16 */
2665 *pval &= 0xFFFF0000;
2666 *pval |= luimm16_val (hword);
2667 }
2668 else if (H == 1 && S == 0 && Z == 0)
2669 {
2670 /* regs_hi = huimm16 */
2671 *pval &= 0xFFFF;
2672 *pval |= luimm16_val (hword) << 16;
2673 }
2674
2675 /* Here we do the disassembly */
2676 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2677 {
2678 OUTS (outf, dregs_lo (reg));
2679 OUTS (outf, " = ");
2680 OUTS (outf, uimm16 (hword));
2681 }
2682 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2683 {
2684 OUTS (outf, dregs_hi (reg));
2685 OUTS (outf, " = ");
2686 OUTS (outf, uimm16 (hword));
2687 }
2688 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2689 {
2690 OUTS (outf, dregs (reg));
2691 OUTS (outf, " = ");
2692 OUTS (outf, imm16 (hword));
2693 OUTS (outf, " (X)");
2694 }
2695 else if (H == 0 && S == 1 && Z == 0)
2696 {
2697 OUTS (outf, regs (reg, grp));
2698 OUTS (outf, " = ");
2699 OUTS (outf, imm16 (hword));
2700 OUTS (outf, " (X)");
2701 }
2702 else if (H == 0 && S == 0 && Z == 1)
2703 {
2704 OUTS (outf, regs (reg, grp));
2705 OUTS (outf, " = ");
2706 OUTS (outf, uimm16 (hword));
2707 OUTS (outf, " (Z)");
2708 }
2709 else if (H == 0 && S == 0 && Z == 0)
2710 {
2711 OUTS (outf, regs_lo (reg, grp));
2712 OUTS (outf, " = ");
2713 OUTS (outf, uimm16 (hword));
2714 }
2715 else if (H == 1 && S == 0 && Z == 0)
2716 {
2717 OUTS (outf, regs_hi (reg, grp));
2718 OUTS (outf, " = ");
2719 OUTS (outf, uimm16 (hword));
2720 }
2721 else
2722 return 0;
2723
2724 /* And we print out the 32-bit value if it is a pointer. */
2725 if (S == 0 && Z == 0)
2726 {
2727 OUTS (outf, ";\t\t/* (");
2728 OUTS (outf, imm16d (hword));
2729 OUTS (outf, ")\t");
2730
2731 /* If it is an MMR, don't print the symbol. */
2732 if (*pval < 0xFFC00000 && grp == 1)
2733 {
2734 OUTS (outf, regs (reg, grp));
2735 OUTS (outf, "=0x");
2736 OUTS (outf, huimm32e (*pval));
2737 }
2738 else
2739 {
2740 OUTS (outf, regs (reg, grp));
2741 OUTS (outf, "=0x");
2742 OUTS (outf, huimm32e (*pval));
2743 OUTS (outf, "(");
2744 OUTS (outf, imm32 (*pval));
2745 OUTS (outf, ")");
2746 }
2747
2748 OUTS (outf, " */");
2749 priv->comment = TRUE;
2750 }
2751 if (S == 1 || Z == 1)
2752 {
2753 OUTS (outf, ";\t\t/*\t\t");
2754 OUTS (outf, regs (reg, grp));
2755 OUTS (outf, "=0x");
2756 OUTS (outf, huimm32e (*pval));
2757 OUTS (outf, "(");
2758 OUTS (outf, imm32 (*pval));
2759 OUTS (outf, ") */");
2760 priv->comment = TRUE;
2761 }
2762 return 4;
2763 }
2764
2765 static int
2766 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2767 {
2768 struct private *priv = outf->private_data;
2769 /* CALLa
2770 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2771 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2772 |.lsw...........................................................|
2773 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2774 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2775 int lsw = ((iw1 >> 0) & 0xffff);
2776 int msw = ((iw0 >> 0) & 0xff);
2777
2778 if (priv->parallel)
2779 return 0;
2780
2781 if (S == 1)
2782 OUTS (outf, "CALL 0x");
2783 else if (S == 0)
2784 OUTS (outf, "JUMP.L 0x");
2785 else
2786 return 0;
2787
2788 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2789 return 4;
2790 }
2791
2792 static int
2793 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2794 {
2795 /* LDSTidxI
2796 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2797 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2798 |.offset........................................................|
2799 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2800 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2801 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2802 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2803 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2804 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2805 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2806
2807 if (W == 0 && sz == 0 && Z == 0)
2808 {
2809 OUTS (outf, dregs (reg));
2810 OUTS (outf, " = [");
2811 OUTS (outf, pregs (ptr));
2812 OUTS (outf, " + ");
2813 OUTS (outf, imm16s4 (offset));
2814 OUTS (outf, "]");
2815 }
2816 else if (W == 0 && sz == 0 && Z == 1)
2817 {
2818 OUTS (outf, pregs (reg));
2819 OUTS (outf, " = [");
2820 OUTS (outf, pregs (ptr));
2821 OUTS (outf, " + ");
2822 OUTS (outf, imm16s4 (offset));
2823 OUTS (outf, "]");
2824 }
2825 else if (W == 0 && sz == 1 && Z == 0)
2826 {
2827 OUTS (outf, dregs (reg));
2828 OUTS (outf, " = W[");
2829 OUTS (outf, pregs (ptr));
2830 OUTS (outf, " + ");
2831 OUTS (outf, imm16s2 (offset));
2832 OUTS (outf, "] (Z)");
2833 }
2834 else if (W == 0 && sz == 1 && Z == 1)
2835 {
2836 OUTS (outf, dregs (reg));
2837 OUTS (outf, " = W[");
2838 OUTS (outf, pregs (ptr));
2839 OUTS (outf, " + ");
2840 OUTS (outf, imm16s2 (offset));
2841 OUTS (outf, "] (X)");
2842 }
2843 else if (W == 0 && sz == 2 && Z == 0)
2844 {
2845 OUTS (outf, dregs (reg));
2846 OUTS (outf, " = B[");
2847 OUTS (outf, pregs (ptr));
2848 OUTS (outf, " + ");
2849 OUTS (outf, imm16 (offset));
2850 OUTS (outf, "] (Z)");
2851 }
2852 else if (W == 0 && sz == 2 && Z == 1)
2853 {
2854 OUTS (outf, dregs (reg));
2855 OUTS (outf, " = B[");
2856 OUTS (outf, pregs (ptr));
2857 OUTS (outf, " + ");
2858 OUTS (outf, imm16 (offset));
2859 OUTS (outf, "] (X)");
2860 }
2861 else if (W == 1 && sz == 0 && Z == 0)
2862 {
2863 OUTS (outf, "[");
2864 OUTS (outf, pregs (ptr));
2865 OUTS (outf, " + ");
2866 OUTS (outf, imm16s4 (offset));
2867 OUTS (outf, "] = ");
2868 OUTS (outf, dregs (reg));
2869 }
2870 else if (W == 1 && sz == 0 && Z == 1)
2871 {
2872 OUTS (outf, "[");
2873 OUTS (outf, pregs (ptr));
2874 OUTS (outf, " + ");
2875 OUTS (outf, imm16s4 (offset));
2876 OUTS (outf, "] = ");
2877 OUTS (outf, pregs (reg));
2878 }
2879 else if (W == 1 && sz == 1 && Z == 0)
2880 {
2881 OUTS (outf, "W[");
2882 OUTS (outf, pregs (ptr));
2883 OUTS (outf, " + ");
2884 OUTS (outf, imm16s2 (offset));
2885 OUTS (outf, "] = ");
2886 OUTS (outf, dregs (reg));
2887 }
2888 else if (W == 1 && sz == 2 && Z == 0)
2889 {
2890 OUTS (outf, "B[");
2891 OUTS (outf, pregs (ptr));
2892 OUTS (outf, " + ");
2893 OUTS (outf, imm16 (offset));
2894 OUTS (outf, "] = ");
2895 OUTS (outf, dregs (reg));
2896 }
2897 else
2898 return 0;
2899
2900 return 4;
2901 }
2902
2903 static int
2904 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2905 {
2906 struct private *priv = outf->private_data;
2907 /* linkage
2908 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2909 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2910 |.framesize.....................................................|
2911 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2912 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2913 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2914
2915 if (priv->parallel)
2916 return 0;
2917
2918 if (R == 0)
2919 {
2920 OUTS (outf, "LINK ");
2921 OUTS (outf, uimm16s4 (framesize));
2922 OUTS (outf, ";\t\t/* (");
2923 OUTS (outf, uimm16s4d (framesize));
2924 OUTS (outf, ") */");
2925 priv->comment = TRUE;
2926 }
2927 else if (R == 1)
2928 OUTS (outf, "UNLINK");
2929 else
2930 return 0;
2931
2932 return 4;
2933 }
2934
2935 static int
2936 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2937 {
2938 /* dsp32mac
2939 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2940 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2941 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2942 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2943 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2944 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2945 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2946 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2947 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2948 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2949 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2950 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2951 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2952 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2953 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2954 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2955 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2956 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2957
2958 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2959 return 0;
2960
2961 if (op1 == 3 && MM)
2962 return 0;
2963
2964 if ((w1 || w0) && mmod == M_W32)
2965 return 0;
2966
2967 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2968 return 0;
2969
2970 if (w1 == 1 || op1 != 3)
2971 {
2972 if (w1)
2973 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2974
2975 if (op1 == 3)
2976 OUTS (outf, " = A1");
2977 else
2978 {
2979 if (w1)
2980 OUTS (outf, " = (");
2981 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2982 if (w1)
2983 OUTS (outf, ")");
2984 }
2985
2986 if (w0 == 1 || op0 != 3)
2987 {
2988 if (MM)
2989 OUTS (outf, " (M)");
2990 OUTS (outf, ", ");
2991 }
2992 }
2993
2994 if (w0 == 1 || op0 != 3)
2995 {
2996 /* Clear MM option since it only matters for MAC1, and if we made
2997 it this far, we've already shown it or we want to ignore it. */
2998 MM = 0;
2999
3000 if (w0)
3001 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3002
3003 if (op0 == 3)
3004 OUTS (outf, " = A0");
3005 else
3006 {
3007 if (w0)
3008 OUTS (outf, " = (");
3009 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3010 if (w0)
3011 OUTS (outf, ")");
3012 }
3013 }
3014
3015 decode_optmode (mmod, MM, outf);
3016
3017 return 4;
3018 }
3019
3020 static int
3021 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3022 {
3023 /* dsp32mult
3024 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3025 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3026 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3027 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3028 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3029 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3030 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
3031 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
3032 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3033 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3034 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3035 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3036 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3037 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3038 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3039 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3040
3041 if (w1 == 0 && w0 == 0)
3042 return 0;
3043
3044 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3045 return 0;
3046
3047 if (w1)
3048 {
3049 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3050 OUTS (outf, " = ");
3051 decode_multfunc (h01, h11, src0, src1, outf);
3052
3053 if (w0)
3054 {
3055 if (MM)
3056 OUTS (outf, " (M)");
3057 MM = 0;
3058 OUTS (outf, ", ");
3059 }
3060 }
3061
3062 if (w0)
3063 {
3064 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3065 OUTS (outf, " = ");
3066 decode_multfunc (h00, h10, src0, src1, outf);
3067 }
3068
3069 decode_optmode (mmod, MM, outf);
3070 return 4;
3071 }
3072
3073 static int
3074 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3075 {
3076 /* dsp32alu
3077 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3078 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3079 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3080 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3081 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3082 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3083 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3084 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3085 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3086 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3087 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3088 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3089 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3090
3091 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3092 {
3093 OUTS (outf, "A0.L = ");
3094 OUTS (outf, dregs_lo (src0));
3095 }
3096 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3097 {
3098 OUTS (outf, "A1.H = ");
3099 OUTS (outf, dregs_hi (src0));
3100 }
3101 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3102 {
3103 OUTS (outf, "A1.L = ");
3104 OUTS (outf, dregs_lo (src0));
3105 }
3106 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3107 {
3108 OUTS (outf, "A0.H = ");
3109 OUTS (outf, dregs_hi (src0));
3110 }
3111 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3112 {
3113 OUTS (outf, dregs_hi (dst0));
3114 OUTS (outf, " = ");
3115 OUTS (outf, dregs (src0));
3116 OUTS (outf, " - ");
3117 OUTS (outf, dregs (src1));
3118 OUTS (outf, " (RND20)");
3119 }
3120 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3121 {
3122 OUTS (outf, dregs_hi (dst0));
3123 OUTS (outf, " = ");
3124 OUTS (outf, dregs (src0));
3125 OUTS (outf, " + ");
3126 OUTS (outf, dregs (src1));
3127 OUTS (outf, " (RND20)");
3128 }
3129 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3130 {
3131 OUTS (outf, dregs_lo (dst0));
3132 OUTS (outf, " = ");
3133 OUTS (outf, dregs (src0));
3134 OUTS (outf, " - ");
3135 OUTS (outf, dregs (src1));
3136 OUTS (outf, " (RND12)");
3137 }
3138 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3139 {
3140 OUTS (outf, dregs_lo (dst0));
3141 OUTS (outf, " = ");
3142 OUTS (outf, dregs (src0));
3143 OUTS (outf, " + ");
3144 OUTS (outf, dregs (src1));
3145 OUTS (outf, " (RND12)");
3146 }
3147 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3148 {
3149 OUTS (outf, dregs_lo (dst0));
3150 OUTS (outf, " = ");
3151 OUTS (outf, dregs (src0));
3152 OUTS (outf, " - ");
3153 OUTS (outf, dregs (src1));
3154 OUTS (outf, " (RND20)");
3155 }
3156 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3157 {
3158 OUTS (outf, dregs_hi (dst0));
3159 OUTS (outf, " = ");
3160 OUTS (outf, dregs (src0));
3161 OUTS (outf, " + ");
3162 OUTS (outf, dregs (src1));
3163 OUTS (outf, " (RND12)");
3164 }
3165 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3166 {
3167 OUTS (outf, dregs_lo (dst0));
3168 OUTS (outf, " = ");
3169 OUTS (outf, dregs (src0));
3170 OUTS (outf, " + ");
3171 OUTS (outf, dregs (src1));
3172 OUTS (outf, " (RND20)");
3173 }
3174 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3175 {
3176 OUTS (outf, dregs_hi (dst0));
3177 OUTS (outf, " = ");
3178 OUTS (outf, dregs (src0));
3179 OUTS (outf, " - ");
3180 OUTS (outf, dregs (src1));
3181 OUTS (outf, " (RND12)");
3182 }
3183 else if (HL == 1 && aop == 0 && aopcde == 2)
3184 {
3185 OUTS (outf, dregs_hi (dst0));
3186 OUTS (outf, " = ");
3187 OUTS (outf, dregs_lo (src0));
3188 OUTS (outf, " + ");
3189 OUTS (outf, dregs_lo (src1));
3190 amod1 (s, x, outf);
3191 }
3192 else if (HL == 1 && aop == 1 && aopcde == 2)
3193 {
3194 OUTS (outf, dregs_hi (dst0));
3195 OUTS (outf, " = ");
3196 OUTS (outf, dregs_lo (src0));
3197 OUTS (outf, " + ");
3198 OUTS (outf, dregs_hi (src1));
3199 amod1 (s, x, outf);
3200 }
3201 else if (HL == 1 && aop == 2 && aopcde == 2)
3202 {
3203 OUTS (outf, dregs_hi (dst0));
3204 OUTS (outf, " = ");
3205 OUTS (outf, dregs_hi (src0));
3206 OUTS (outf, " + ");
3207 OUTS (outf, dregs_lo (src1));
3208 amod1 (s, x, outf);
3209 }
3210 else if (HL == 1 && aop == 3 && aopcde == 2)
3211 {
3212 OUTS (outf, dregs_hi (dst0));
3213 OUTS (outf, " = ");
3214 OUTS (outf, dregs_hi (src0));
3215 OUTS (outf, " + ");
3216 OUTS (outf, dregs_hi (src1));
3217 amod1 (s, x, outf);
3218 }
3219 else if (HL == 0 && aop == 0 && aopcde == 3)
3220 {
3221 OUTS (outf, dregs_lo (dst0));
3222 OUTS (outf, " = ");
3223 OUTS (outf, dregs_lo (src0));
3224 OUTS (outf, " - ");
3225 OUTS (outf, dregs_lo (src1));
3226 amod1 (s, x, outf);
3227 }
3228 else if (HL == 0 && aop == 1 && aopcde == 3)
3229 {
3230 OUTS (outf, dregs_lo (dst0));
3231 OUTS (outf, " = ");
3232 OUTS (outf, dregs_lo (src0));
3233 OUTS (outf, " - ");
3234 OUTS (outf, dregs_hi (src1));
3235 amod1 (s, x, outf);
3236 }
3237 else if (HL == 0 && aop == 3 && aopcde == 2)
3238 {
3239 OUTS (outf, dregs_lo (dst0));
3240 OUTS (outf, " = ");
3241 OUTS (outf, dregs_hi (src0));
3242 OUTS (outf, " + ");
3243 OUTS (outf, dregs_hi (src1));
3244 amod1 (s, x, outf);
3245 }
3246 else if (HL == 1 && aop == 0 && aopcde == 3)
3247 {
3248 OUTS (outf, dregs_hi (dst0));
3249 OUTS (outf, " = ");
3250 OUTS (outf, dregs_lo (src0));
3251 OUTS (outf, " - ");
3252 OUTS (outf, dregs_lo (src1));
3253 amod1 (s, x, outf);
3254 }
3255 else if (HL == 1 && aop == 1 && aopcde == 3)
3256 {
3257 OUTS (outf, dregs_hi (dst0));
3258 OUTS (outf, " = ");
3259 OUTS (outf, dregs_lo (src0));
3260 OUTS (outf, " - ");
3261 OUTS (outf, dregs_hi (src1));
3262 amod1 (s, x, outf);
3263 }
3264 else if (HL == 1 && aop == 2 && aopcde == 3)
3265 {
3266 OUTS (outf, dregs_hi (dst0));
3267 OUTS (outf, " = ");
3268 OUTS (outf, dregs_hi (src0));
3269 OUTS (outf, " - ");
3270 OUTS (outf, dregs_lo (src1));
3271 amod1 (s, x, outf);
3272 }
3273 else if (HL == 1 && aop == 3 && aopcde == 3)
3274 {
3275 OUTS (outf, dregs_hi (dst0));
3276 OUTS (outf, " = ");
3277 OUTS (outf, dregs_hi (src0));
3278 OUTS (outf, " - ");
3279 OUTS (outf, dregs_hi (src1));
3280 amod1 (s, x, outf);
3281 }
3282 else if (HL == 0 && aop == 2 && aopcde == 2)
3283 {
3284 OUTS (outf, dregs_lo (dst0));
3285 OUTS (outf, " = ");
3286 OUTS (outf, dregs_hi (src0));
3287 OUTS (outf, " + ");
3288 OUTS (outf, dregs_lo (src1));
3289 amod1 (s, x, outf);
3290 }
3291 else if (HL == 0 && aop == 1 && aopcde == 2)
3292 {
3293 OUTS (outf, dregs_lo (dst0));
3294 OUTS (outf, " = ");
3295 OUTS (outf, dregs_lo (src0));
3296 OUTS (outf, " + ");
3297 OUTS (outf, dregs_hi (src1));
3298 amod1 (s, x, outf);
3299 }
3300 else if (HL == 0 && aop == 2 && aopcde == 3)
3301 {
3302 OUTS (outf, dregs_lo (dst0));
3303 OUTS (outf, " = ");
3304 OUTS (outf, dregs_hi (src0));
3305 OUTS (outf, " - ");
3306 OUTS (outf, dregs_lo (src1));
3307 amod1 (s, x, outf);
3308 }
3309 else if (HL == 0 && aop == 3 && aopcde == 3)
3310 {
3311 OUTS (outf, dregs_lo (dst0));
3312 OUTS (outf, " = ");
3313 OUTS (outf, dregs_hi (src0));
3314 OUTS (outf, " - ");
3315 OUTS (outf, dregs_hi (src1));
3316 amod1 (s, x, outf);
3317 }
3318 else if (HL == 0 && aop == 0 && aopcde == 2)
3319 {
3320 OUTS (outf, dregs_lo (dst0));
3321 OUTS (outf, " = ");
3322 OUTS (outf, dregs_lo (src0));
3323 OUTS (outf, " + ");
3324 OUTS (outf, dregs_lo (src1));
3325 amod1 (s, x, outf);
3326 }
3327 else if (aop == 0 && aopcde == 9 && s == 1)
3328 {
3329 OUTS (outf, "A0 = ");
3330 OUTS (outf, dregs (src0));
3331 }
3332 else if (aop == 3 && aopcde == 11 && s == 0)
3333 OUTS (outf, "A0 -= A1");
3334
3335 else if (aop == 3 && aopcde == 11 && s == 1)
3336 OUTS (outf, "A0 -= A1 (W32)");
3337
3338 else if (aop == 1 && aopcde == 22 && HL == 1)
3339 {
3340 OUTS (outf, dregs (dst0));
3341 OUTS (outf, " = BYTEOP2P (");
3342 OUTS (outf, dregs (src0 + 1));
3343 OUTS (outf, ":");
3344 OUTS (outf, imm5d (src0));
3345 OUTS (outf, ", ");
3346 OUTS (outf, dregs (src1 + 1));
3347 OUTS (outf, ":");
3348 OUTS (outf, imm5d (src1));
3349 OUTS (outf, ") (TH");
3350 if (s == 1)
3351 OUTS (outf, ", R)");
3352 else
3353 OUTS (outf, ")");
3354 }
3355 else if (aop == 1 && aopcde == 22 && HL == 0)
3356 {
3357 OUTS (outf, dregs (dst0));
3358 OUTS (outf, " = BYTEOP2P (");
3359 OUTS (outf, dregs (src0 + 1));
3360 OUTS (outf, ":");
3361 OUTS (outf, imm5d (src0));
3362 OUTS (outf, ", ");
3363 OUTS (outf, dregs (src1 + 1));
3364 OUTS (outf, ":");
3365 OUTS (outf, imm5d (src1));
3366 OUTS (outf, ") (TL");
3367 if (s == 1)
3368 OUTS (outf, ", R)");
3369 else
3370 OUTS (outf, ")");
3371 }
3372 else if (aop == 0 && aopcde == 22 && HL == 1)
3373 {
3374 OUTS (outf, dregs (dst0));
3375 OUTS (outf, " = BYTEOP2P (");
3376 OUTS (outf, dregs (src0 + 1));
3377 OUTS (outf, ":");
3378 OUTS (outf, imm5d (src0));
3379 OUTS (outf, ", ");
3380 OUTS (outf, dregs (src1 + 1));
3381 OUTS (outf, ":");
3382 OUTS (outf, imm5d (src1));
3383 OUTS (outf, ") (RNDH");
3384 if (s == 1)
3385 OUTS (outf, ", R)");
3386 else
3387 OUTS (outf, ")");
3388 }
3389 else if (aop == 0 && aopcde == 22 && HL == 0)
3390 {
3391 OUTS (outf, dregs (dst0));
3392 OUTS (outf, " = BYTEOP2P (");
3393 OUTS (outf, dregs (src0 + 1));
3394 OUTS (outf, ":");
3395 OUTS (outf, imm5d (src0));
3396 OUTS (outf, ", ");
3397 OUTS (outf, dregs (src1 + 1));
3398 OUTS (outf, ":");
3399 OUTS (outf, imm5d (src1));
3400 OUTS (outf, ") (RNDL");
3401 if (s == 1)
3402 OUTS (outf, ", R)");
3403 else
3404 OUTS (outf, ")");
3405 }
3406 else if (aop == 0 && s == 0 && aopcde == 8)
3407 OUTS (outf, "A0 = 0");
3408
3409 else if (aop == 0 && s == 1 && aopcde == 8)
3410 OUTS (outf, "A0 = A0 (S)");
3411
3412 else if (aop == 1 && s == 0 && aopcde == 8)
3413 OUTS (outf, "A1 = 0");
3414
3415 else if (aop == 1 && s == 1 && aopcde == 8)
3416 OUTS (outf, "A1 = A1 (S)");
3417
3418 else if (aop == 2 && s == 0 && aopcde == 8)
3419 OUTS (outf, "A1 = A0 = 0");
3420
3421 else if (aop == 2 && s == 1 && aopcde == 8)
3422 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3423
3424 else if (aop == 3 && s == 0 && aopcde == 8)
3425 OUTS (outf, "A0 = A1");
3426
3427 else if (aop == 3 && s == 1 && aopcde == 8)
3428 OUTS (outf, "A1 = A0");
3429
3430 else if (aop == 1 && aopcde == 9 && s == 0)
3431 {
3432 OUTS (outf, "A0.X = ");
3433 OUTS (outf, dregs_lo (src0));
3434 }
3435 else if (aop == 1 && HL == 0 && aopcde == 11)
3436 {
3437 OUTS (outf, dregs_lo (dst0));
3438 OUTS (outf, " = (A0 += A1)");
3439 }
3440 else if (aop == 3 && HL == 0 && aopcde == 16)
3441 OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
3442
3443 else if (aop == 0 && aopcde == 23 && HL == 1)
3444 {
3445 OUTS (outf, dregs (dst0));
3446 OUTS (outf, " = BYTEOP3P (");
3447 OUTS (outf, dregs (src0 + 1));
3448 OUTS (outf, ":");
3449 OUTS (outf, imm5d (src0));
3450 OUTS (outf, ", ");
3451 OUTS (outf, dregs (src1 + 1));
3452 OUTS (outf, ":");
3453 OUTS (outf, imm5d (src1));
3454 OUTS (outf, ") (HI");
3455 if (s == 1)
3456 OUTS (outf, ", R)");
3457 else
3458 OUTS (outf, ")");
3459 }
3460 else if (aop == 3 && aopcde == 9 && s == 0)
3461 {
3462 OUTS (outf, "A1.X = ");
3463 OUTS (outf, dregs_lo (src0));
3464 }
3465 else if (aop == 1 && HL == 1 && aopcde == 16)
3466 OUTS (outf, "A1 = ABS A1");
3467
3468 else if (aop == 0 && HL == 1 && aopcde == 16)
3469 OUTS (outf, "A1 = ABS A0");
3470
3471 else if (aop == 2 && aopcde == 9 && s == 1)
3472 {
3473 OUTS (outf, "A1 = ");
3474 OUTS (outf, dregs (src0));
3475 }
3476 else if (HL == 0 && aop == 3 && aopcde == 12)
3477 {
3478 OUTS (outf, dregs_lo (dst0));
3479 OUTS (outf, " = ");
3480 OUTS (outf, dregs (src0));
3481 OUTS (outf, " (RND)");
3482 }
3483 else if (aop == 1 && HL == 0 && aopcde == 16)
3484 OUTS (outf, "A0 = ABS A1");
3485
3486 else if (aop == 0 && HL == 0 && aopcde == 16)
3487 OUTS (outf, "A0 = ABS A0");
3488
3489 else if (aop == 3 && HL == 0 && aopcde == 15)
3490 {
3491 OUTS (outf, dregs (dst0));
3492 OUTS (outf, " = -");
3493 OUTS (outf, dregs (src0));
3494 OUTS (outf, " (V)");
3495 }
3496 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3497 {
3498 OUTS (outf, dregs (dst0));
3499 OUTS (outf, " = -");
3500 OUTS (outf, dregs (src0));
3501 OUTS (outf, " (S)");
3502 }
3503 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3504 {
3505 OUTS (outf, dregs (dst0));
3506 OUTS (outf, " = -");
3507 OUTS (outf, dregs (src0));
3508 OUTS (outf, " (NS)");
3509 }
3510 else if (aop == 1 && HL == 1 && aopcde == 11)
3511 {
3512 OUTS (outf, dregs_hi (dst0));
3513 OUTS (outf, " = (A0 += A1)");
3514 }
3515 else if (aop == 2 && aopcde == 11 && s == 0)
3516 OUTS (outf, "A0 += A1");
3517
3518 else if (aop == 2 && aopcde == 11 && s == 1)
3519 OUTS (outf, "A0 += A1 (W32)");
3520
3521 else if (aop == 3 && HL == 0 && aopcde == 14)
3522 OUTS (outf, "A1 = -A1, A0 = -A0");
3523
3524 else if (HL == 1 && aop == 3 && aopcde == 12)
3525 {
3526 OUTS (outf, dregs_hi (dst0));
3527 OUTS (outf, " = ");
3528 OUTS (outf, dregs (src0));
3529 OUTS (outf, " (RND)");
3530 }
3531 else if (aop == 0 && aopcde == 23 && HL == 0)
3532 {
3533 OUTS (outf, dregs (dst0));
3534 OUTS (outf, " = BYTEOP3P (");
3535 OUTS (outf, dregs (src0 + 1));
3536 OUTS (outf, ":");
3537 OUTS (outf, imm5d (src0));
3538 OUTS (outf, ", ");
3539 OUTS (outf, dregs (src1 + 1));
3540 OUTS (outf, ":");
3541 OUTS (outf, imm5d (src1));
3542 OUTS (outf, ") (LO");
3543 if (s == 1)
3544 OUTS (outf, ", R)");
3545 else
3546 OUTS (outf, ")");
3547 }
3548 else if (aop == 0 && HL == 0 && aopcde == 14)
3549 OUTS (outf, "A0 = -A0");
3550
3551 else if (aop == 1 && HL == 0 && aopcde == 14)
3552 OUTS (outf, "A0 = -A1");
3553
3554 else if (aop == 0 && HL == 1 && aopcde == 14)
3555 OUTS (outf, "A1 = -A0");
3556
3557 else if (aop == 1 && HL == 1 && aopcde == 14)
3558 OUTS (outf, "A1 = -A1");
3559
3560 else if (aop == 0 && aopcde == 12)
3561 {
3562 OUTS (outf, dregs_hi (dst0));
3563 OUTS (outf, " = ");
3564 OUTS (outf, dregs_lo (dst0));
3565 OUTS (outf, " = SIGN (");
3566 OUTS (outf, dregs_hi (src0));
3567 OUTS (outf, ") * ");
3568 OUTS (outf, dregs_hi (src1));
3569 OUTS (outf, " + SIGN (");
3570 OUTS (outf, dregs_lo (src0));
3571 OUTS (outf, ") * ");
3572 OUTS (outf, dregs_lo (src1));
3573 }
3574 else if (aop == 2 && aopcde == 0)
3575 {
3576 OUTS (outf, dregs (dst0));
3577 OUTS (outf, " = ");
3578 OUTS (outf, dregs (src0));
3579 OUTS (outf, " -|+ ");
3580 OUTS (outf, dregs (src1));
3581 amod0 (s, x, outf);
3582 }
3583 else if (aop == 1 && aopcde == 12)
3584 {
3585 OUTS (outf, dregs (dst1));
3586 OUTS (outf, " = A1.L + A1.H, ");
3587 OUTS (outf, dregs (dst0));
3588 OUTS (outf, " = A0.L + A0.H");
3589 }
3590 else if (aop == 2 && aopcde == 4)
3591 {
3592 OUTS (outf, dregs (dst1));
3593 OUTS (outf, " = ");
3594 OUTS (outf, dregs (src0));
3595 OUTS (outf, " + ");
3596 OUTS (outf, dregs (src1));
3597 OUTS (outf, ", ");
3598 OUTS (outf, dregs (dst0));
3599 OUTS (outf, " = ");
3600 OUTS (outf, dregs (src0));
3601 OUTS (outf, " - ");
3602 OUTS (outf, dregs (src1));
3603 amod1 (s, x, outf);
3604 }
3605 else if (HL == 0 && aopcde == 1)
3606 {
3607 OUTS (outf, dregs (dst1));
3608 OUTS (outf, " = ");
3609 OUTS (outf, dregs (src0));
3610 OUTS (outf, " +|+ ");
3611 OUTS (outf, dregs (src1));
3612 OUTS (outf, ", ");
3613 OUTS (outf, dregs (dst0));
3614 OUTS (outf, " = ");
3615 OUTS (outf, dregs (src0));
3616 OUTS (outf, " -|- ");
3617 OUTS (outf, dregs (src1));
3618 amod0amod2 (s, x, aop, outf);
3619 }
3620 else if (aop == 0 && aopcde == 11)
3621 {
3622 OUTS (outf, dregs (dst0));
3623 OUTS (outf, " = (A0 += A1)");
3624 }
3625 else if (aop == 0 && aopcde == 10)
3626 {
3627 OUTS (outf, dregs_lo (dst0));
3628 OUTS (outf, " = A0.X");
3629 }
3630 else if (aop == 1 && aopcde == 10)
3631 {
3632 OUTS (outf, dregs_lo (dst0));
3633 OUTS (outf, " = A1.X");
3634 }
3635 else if (aop == 1 && aopcde == 0)
3636 {
3637 OUTS (outf, dregs (dst0));
3638 OUTS (outf, " = ");
3639 OUTS (outf, dregs (src0));
3640 OUTS (outf, " +|- ");
3641 OUTS (outf, dregs (src1));
3642 amod0 (s, x, outf);
3643 }
3644 else if (aop == 3 && aopcde == 0)
3645 {
3646 OUTS (outf, dregs (dst0));
3647 OUTS (outf, " = ");
3648 OUTS (outf, dregs (src0));
3649 OUTS (outf, " -|- ");
3650 OUTS (outf, dregs (src1));
3651 amod0 (s, x, outf);
3652 }
3653 else if (aop == 1 && aopcde == 4)
3654 {
3655 OUTS (outf, dregs (dst0));
3656 OUTS (outf, " = ");
3657 OUTS (outf, dregs (src0));
3658 OUTS (outf, " - ");
3659 OUTS (outf, dregs (src1));
3660 amod1 (s, x, outf);
3661 }
3662 else if (aop == 0 && aopcde == 17)
3663 {
3664 OUTS (outf, dregs (dst1));
3665 OUTS (outf, " = A1 + A0, ");
3666 OUTS (outf, dregs (dst0));
3667 OUTS (outf, " = A1 - A0");
3668 amod1 (s, x, outf);
3669 }
3670 else if (aop == 1 && aopcde == 17)
3671 {
3672 OUTS (outf, dregs (dst1));
3673 OUTS (outf, " = A0 + A1, ");
3674 OUTS (outf, dregs (dst0));
3675 OUTS (outf, " = A0 - A1");
3676 amod1 (s, x, outf);
3677 }
3678 else if (aop == 0 && aopcde == 18)
3679 {
3680 OUTS (outf, "SAA (");
3681 OUTS (outf, dregs (src0 + 1));
3682 OUTS (outf, ":");
3683 OUTS (outf, imm5d (src0));
3684 OUTS (outf, ", ");
3685 OUTS (outf, dregs (src1 + 1));
3686 OUTS (outf, ":");
3687 OUTS (outf, imm5d (src1));
3688 OUTS (outf, ")");
3689 aligndir (s, outf);
3690 }
3691 else if (aop == 3 && aopcde == 18)
3692 OUTS (outf, "DISALGNEXCPT");
3693
3694 else if (aop == 0 && aopcde == 20)
3695 {
3696 OUTS (outf, dregs (dst0));
3697 OUTS (outf, " = BYTEOP1P (");
3698 OUTS (outf, dregs (src0 + 1));
3699 OUTS (outf, ":");
3700 OUTS (outf, imm5d (src0));
3701 OUTS (outf, ", ");
3702 OUTS (outf, dregs (src1 + 1));
3703 OUTS (outf, ":");
3704 OUTS (outf, imm5d (src1));
3705 OUTS (outf, ")");
3706 aligndir (s, outf);
3707 }
3708 else if (aop == 1 && aopcde == 20)
3709 {
3710 OUTS (outf, dregs (dst0));
3711 OUTS (outf, " = BYTEOP1P (");
3712 OUTS (outf, dregs (src0 + 1));
3713 OUTS (outf, ":");
3714 OUTS (outf, imm5d (src0));
3715 OUTS (outf, ", ");
3716 OUTS (outf, dregs (src1 + 1));
3717 OUTS (outf, ":");
3718 OUTS (outf, imm5d (src1));
3719 OUTS (outf, ") (T");
3720 if (s == 1)
3721 OUTS (outf, ", R)");
3722 else
3723 OUTS (outf, ")");
3724 }
3725 else if (aop == 0 && aopcde == 21)
3726 {
3727 OUTS (outf, "(");
3728 OUTS (outf, dregs (dst1));
3729 OUTS (outf, ", ");
3730 OUTS (outf, dregs (dst0));
3731 OUTS (outf, ") = BYTEOP16P (");
3732 OUTS (outf, dregs (src0 + 1));
3733 OUTS (outf, ":");
3734 OUTS (outf, imm5d (src0));
3735 OUTS (outf, ", ");
3736 OUTS (outf, dregs (src1 + 1));
3737 OUTS (outf, ":");
3738 OUTS (outf, imm5d (src1));
3739 OUTS (outf, ")");
3740 aligndir (s, outf);
3741 }
3742 else if (aop == 1 && aopcde == 21)
3743 {
3744 OUTS (outf, "(");
3745 OUTS (outf, dregs (dst1));
3746 OUTS (outf, ", ");
3747 OUTS (outf, dregs (dst0));
3748 OUTS (outf, ") = BYTEOP16M (");
3749 OUTS (outf, dregs (src0 + 1));
3750 OUTS (outf, ":");
3751 OUTS (outf, imm5d (src0));
3752 OUTS (outf, ", ");
3753 OUTS (outf, dregs (src1 + 1));
3754 OUTS (outf, ":");
3755 OUTS (outf, imm5d (src1));
3756 OUTS (outf, ")");
3757 aligndir (s, outf);
3758 }
3759 else if (aop == 2 && aopcde == 7)
3760 {
3761 OUTS (outf, dregs (dst0));
3762 OUTS (outf, " = ABS ");
3763 OUTS (outf, dregs (src0));
3764 }
3765 else if (aop == 1 && aopcde == 7)
3766 {
3767 OUTS (outf, dregs (dst0));
3768 OUTS (outf, " = MIN (");
3769 OUTS (outf, dregs (src0));
3770 OUTS (outf, ", ");
3771 OUTS (outf, dregs (src1));
3772 OUTS (outf, ")");
3773 }
3774 else if (aop == 0 && aopcde == 7)
3775 {
3776 OUTS (outf, dregs (dst0));
3777 OUTS (outf, " = MAX (");
3778 OUTS (outf, dregs (src0));
3779 OUTS (outf, ", ");
3780 OUTS (outf, dregs (src1));
3781 OUTS (outf, ")");
3782 }
3783 else if (aop == 2 && aopcde == 6)
3784 {
3785 OUTS (outf, dregs (dst0));
3786 OUTS (outf, " = ABS ");
3787 OUTS (outf, dregs (src0));
3788 OUTS (outf, " (V)");
3789 }
3790 else if (aop == 1 && aopcde == 6)
3791 {
3792 OUTS (outf, dregs (dst0));
3793 OUTS (outf, " = MIN (");
3794 OUTS (outf, dregs (src0));
3795 OUTS (outf, ", ");
3796 OUTS (outf, dregs (src1));
3797 OUTS (outf, ") (V)");
3798 }
3799 else if (aop == 0 && aopcde == 6)
3800 {
3801 OUTS (outf, dregs (dst0));
3802 OUTS (outf, " = MAX (");
3803 OUTS (outf, dregs (src0));
3804 OUTS (outf, ", ");
3805 OUTS (outf, dregs (src1));
3806 OUTS (outf, ") (V)");
3807 }
3808 else if (HL == 1 && aopcde == 1)
3809 {
3810 OUTS (outf, dregs (dst1));
3811 OUTS (outf, " = ");
3812 OUTS (outf, dregs (src0));
3813 OUTS (outf, " +|- ");
3814 OUTS (outf, dregs (src1));
3815 OUTS (outf, ", ");
3816 OUTS (outf, dregs (dst0));
3817 OUTS (outf, " = ");
3818 OUTS (outf, dregs (src0));
3819 OUTS (outf, " -|+ ");
3820 OUTS (outf, dregs (src1));
3821 amod0amod2 (s, x, aop, outf);
3822 }
3823 else if (aop == 0 && aopcde == 4)
3824 {
3825 OUTS (outf, dregs (dst0));
3826 OUTS (outf, " = ");
3827 OUTS (outf, dregs (src0));
3828 OUTS (outf, " + ");
3829 OUTS (outf, dregs (src1));
3830 amod1 (s, x, outf);
3831 }
3832 else if (aop == 0 && aopcde == 0)
3833 {
3834 OUTS (outf, dregs (dst0));
3835 OUTS (outf, " = ");
3836 OUTS (outf, dregs (src0));
3837 OUTS (outf, " +|+ ");
3838 OUTS (outf, dregs (src1));
3839 amod0 (s, x, outf);
3840 }
3841 else if (aop == 0 && aopcde == 24)
3842 {
3843 OUTS (outf, dregs (dst0));
3844 OUTS (outf, " = BYTEPACK (");
3845 OUTS (outf, dregs (src0));
3846 OUTS (outf, ", ");
3847 OUTS (outf, dregs (src1));
3848 OUTS (outf, ")");
3849 }
3850 else if (aop == 1 && aopcde == 24)
3851 {
3852 OUTS (outf, "(");
3853 OUTS (outf, dregs (dst1));
3854 OUTS (outf, ", ");
3855 OUTS (outf, dregs (dst0));
3856 OUTS (outf, ") = BYTEUNPACK ");
3857 OUTS (outf, dregs (src0 + 1));
3858 OUTS (outf, ":");
3859 OUTS (outf, imm5d (src0));
3860 aligndir (s, outf);
3861 }
3862 else if (aopcde == 13)
3863 {
3864 OUTS (outf, "(");
3865 OUTS (outf, dregs (dst1));
3866 OUTS (outf, ", ");
3867 OUTS (outf, dregs (dst0));
3868 OUTS (outf, ") = SEARCH ");
3869 OUTS (outf, dregs (src0));
3870 OUTS (outf, " (");
3871 searchmod (aop, outf);
3872 OUTS (outf, ")");
3873 }
3874 else
3875 return 0;
3876
3877 return 4;
3878 }
3879
3880 static int
3881 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3882 {
3883 /* dsp32shift
3884 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3885 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3886 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3887 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3888 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3889 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3890 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3891 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3892 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3893 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3894 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3895
3896 if (HLs == 0 && sop == 0 && sopcde == 0)
3897 {
3898 OUTS (outf, dregs_lo (dst0));
3899 OUTS (outf, " = ASHIFT ");
3900 OUTS (outf, dregs_lo (src1));
3901 OUTS (outf, " BY ");
3902 OUTS (outf, dregs_lo (src0));
3903 }
3904 else if (HLs == 1 && sop == 0 && sopcde == 0)
3905 {
3906 OUTS (outf, dregs_lo (dst0));
3907 OUTS (outf, " = ASHIFT ");
3908 OUTS (outf, dregs_hi (src1));
3909 OUTS (outf, " BY ");
3910 OUTS (outf, dregs_lo (src0));
3911 }
3912 else if (HLs == 2 && sop == 0 && sopcde == 0)
3913 {
3914 OUTS (outf, dregs_hi (dst0));
3915 OUTS (outf, " = ASHIFT ");
3916 OUTS (outf, dregs_lo (src1));
3917 OUTS (outf, " BY ");
3918 OUTS (outf, dregs_lo (src0));
3919 }
3920 else if (HLs == 3 && sop == 0 && sopcde == 0)
3921 {
3922 OUTS (outf, dregs_hi (dst0));
3923 OUTS (outf, " = ASHIFT ");
3924 OUTS (outf, dregs_hi (src1));
3925 OUTS (outf, " BY ");
3926 OUTS (outf, dregs_lo (src0));
3927 }
3928 else if (HLs == 0 && sop == 1 && sopcde == 0)
3929 {
3930 OUTS (outf, dregs_lo (dst0));
3931 OUTS (outf, " = ASHIFT ");
3932 OUTS (outf, dregs_lo (src1));
3933 OUTS (outf, " BY ");
3934 OUTS (outf, dregs_lo (src0));
3935 OUTS (outf, " (S)");
3936 }
3937 else if (HLs == 1 && sop == 1 && sopcde == 0)
3938 {
3939 OUTS (outf, dregs_lo (dst0));
3940 OUTS (outf, " = ASHIFT ");
3941 OUTS (outf, dregs_hi (src1));
3942 OUTS (outf, " BY ");
3943 OUTS (outf, dregs_lo (src0));
3944 OUTS (outf, " (S)");
3945 }
3946 else if (HLs == 2 && sop == 1 && sopcde == 0)
3947 {
3948 OUTS (outf, dregs_hi (dst0));
3949 OUTS (outf, " = ASHIFT ");
3950 OUTS (outf, dregs_lo (src1));
3951 OUTS (outf, " BY ");
3952 OUTS (outf, dregs_lo (src0));
3953 OUTS (outf, " (S)");
3954 }
3955 else if (HLs == 3 && sop == 1 && sopcde == 0)
3956 {
3957 OUTS (outf, dregs_hi (dst0));
3958 OUTS (outf, " = ASHIFT ");
3959 OUTS (outf, dregs_hi (src1));
3960 OUTS (outf, " BY ");
3961 OUTS (outf, dregs_lo (src0));
3962 OUTS (outf, " (S)");
3963 }
3964 else if (sop == 2 && sopcde == 0)
3965 {
3966 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
3967 OUTS (outf, " = LSHIFT ");
3968 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
3969 OUTS (outf, " BY ");
3970 OUTS (outf, dregs_lo (src0));
3971 }
3972 else if (sop == 0 && sopcde == 3)
3973 {
3974 OUTS (outf, acc01);
3975 OUTS (outf, " = ASHIFT ");
3976 OUTS (outf, acc01);
3977 OUTS (outf, " BY ");
3978 OUTS (outf, dregs_lo (src0));
3979 }
3980 else if (sop == 1 && sopcde == 3)
3981 {
3982 OUTS (outf, acc01);
3983 OUTS (outf, " = LSHIFT ");
3984 OUTS (outf, acc01);
3985 OUTS (outf, " BY ");
3986 OUTS (outf, dregs_lo (src0));
3987 }
3988 else if (sop == 2 && sopcde == 3)
3989 {
3990 OUTS (outf, acc01);
3991 OUTS (outf, " = ROT ");
3992 OUTS (outf, acc01);
3993 OUTS (outf, " BY ");
3994 OUTS (outf, dregs_lo (src0));
3995 }
3996 else if (sop == 3 && sopcde == 3)
3997 {
3998 OUTS (outf, dregs (dst0));
3999 OUTS (outf, " = ROT ");
4000 OUTS (outf, dregs (src1));
4001 OUTS (outf, " BY ");
4002 OUTS (outf, dregs_lo (src0));
4003 }
4004 else if (sop == 1 && sopcde == 1)
4005 {
4006 OUTS (outf, dregs (dst0));
4007 OUTS (outf, " = ASHIFT ");
4008 OUTS (outf, dregs (src1));
4009 OUTS (outf, " BY ");
4010 OUTS (outf, dregs_lo (src0));
4011 OUTS (outf, " (V, S)");
4012 }
4013 else if (sop == 0 && sopcde == 1)
4014 {
4015 OUTS (outf, dregs (dst0));
4016 OUTS (outf, " = ASHIFT ");
4017 OUTS (outf, dregs (src1));
4018 OUTS (outf, " BY ");
4019 OUTS (outf, dregs_lo (src0));
4020 OUTS (outf, " (V)");
4021 }
4022 else if (sop == 0 && sopcde == 2)
4023 {
4024 OUTS (outf, dregs (dst0));
4025 OUTS (outf, " = ASHIFT ");
4026 OUTS (outf, dregs (src1));
4027 OUTS (outf, " BY ");
4028 OUTS (outf, dregs_lo (src0));
4029 }
4030 else if (sop == 1 && sopcde == 2)
4031 {
4032 OUTS (outf, dregs (dst0));
4033 OUTS (outf, " = ASHIFT ");
4034 OUTS (outf, dregs (src1));
4035 OUTS (outf, " BY ");
4036 OUTS (outf, dregs_lo (src0));
4037 OUTS (outf, " (S)");
4038 }
4039 else if (sop == 2 && sopcde == 2)
4040 {
4041 OUTS (outf, dregs (dst0));
4042 OUTS (outf, " = LSHIFT ");
4043 OUTS (outf, dregs (src1));
4044 OUTS (outf, " BY ");
4045 OUTS (outf, dregs_lo (src0));
4046 }
4047 else if (sop == 3 && sopcde == 2)
4048 {
4049 OUTS (outf, dregs (dst0));
4050 OUTS (outf, " = ROT ");
4051 OUTS (outf, dregs (src1));
4052 OUTS (outf, " BY ");
4053 OUTS (outf, dregs_lo (src0));
4054 }
4055 else if (sop == 2 && sopcde == 1)
4056 {
4057 OUTS (outf, dregs (dst0));
4058 OUTS (outf, " = LSHIFT ");
4059 OUTS (outf, dregs (src1));
4060 OUTS (outf, " BY ");
4061 OUTS (outf, dregs_lo (src0));
4062 OUTS (outf, " (V)");
4063 }
4064 else if (sop == 0 && sopcde == 4)
4065 {
4066 OUTS (outf, dregs (dst0));
4067 OUTS (outf, " = PACK (");
4068 OUTS (outf, dregs_lo (src1));
4069 OUTS (outf, ", ");
4070 OUTS (outf, dregs_lo (src0));
4071 OUTS (outf, ")");
4072 }
4073 else if (sop == 1 && sopcde == 4)
4074 {
4075 OUTS (outf, dregs (dst0));
4076 OUTS (outf, " = PACK (");
4077 OUTS (outf, dregs_lo (src1));
4078 OUTS (outf, ", ");
4079 OUTS (outf, dregs_hi (src0));
4080 OUTS (outf, ")");
4081 }
4082 else if (sop == 2 && sopcde == 4)
4083 {
4084 OUTS (outf, dregs (dst0));
4085 OUTS (outf, " = PACK (");
4086 OUTS (outf, dregs_hi (src1));
4087 OUTS (outf, ", ");
4088 OUTS (outf, dregs_lo (src0));
4089 OUTS (outf, ")");
4090 }
4091 else if (sop == 3 && sopcde == 4)
4092 {
4093 OUTS (outf, dregs (dst0));
4094 OUTS (outf, " = PACK (");
4095 OUTS (outf, dregs_hi (src1));
4096 OUTS (outf, ", ");
4097 OUTS (outf, dregs_hi (src0));
4098 OUTS (outf, ")");
4099 }
4100 else if (sop == 0 && sopcde == 5)
4101 {
4102 OUTS (outf, dregs_lo (dst0));
4103 OUTS (outf, " = SIGNBITS ");
4104 OUTS (outf, dregs (src1));
4105 }
4106 else if (sop == 1 && sopcde == 5)
4107 {
4108 OUTS (outf, dregs_lo (dst0));
4109 OUTS (outf, " = SIGNBITS ");
4110 OUTS (outf, dregs_lo (src1));
4111 }
4112 else if (sop == 2 && sopcde == 5)
4113 {
4114 OUTS (outf, dregs_lo (dst0));
4115 OUTS (outf, " = SIGNBITS ");
4116 OUTS (outf, dregs_hi (src1));
4117 }
4118 else if (sop == 0 && sopcde == 6)
4119 {
4120 OUTS (outf, dregs_lo (dst0));
4121 OUTS (outf, " = SIGNBITS A0");
4122 }
4123 else if (sop == 1 && sopcde == 6)
4124 {
4125 OUTS (outf, dregs_lo (dst0));
4126 OUTS (outf, " = SIGNBITS A1");
4127 }
4128 else if (sop == 3 && sopcde == 6)
4129 {
4130 OUTS (outf, dregs_lo (dst0));
4131 OUTS (outf, " = ONES ");
4132 OUTS (outf, dregs (src1));
4133 }
4134 else if (sop == 0 && sopcde == 7)
4135 {
4136 OUTS (outf, dregs_lo (dst0));
4137 OUTS (outf, " = EXPADJ (");
4138 OUTS (outf, dregs (src1));
4139 OUTS (outf, ", ");
4140 OUTS (outf, dregs_lo (src0));
4141 OUTS (outf, ")");
4142 }
4143 else if (sop == 1 && sopcde == 7)
4144 {
4145 OUTS (outf, dregs_lo (dst0));
4146 OUTS (outf, " = EXPADJ (");
4147 OUTS (outf, dregs (src1));
4148 OUTS (outf, ", ");
4149 OUTS (outf, dregs_lo (src0));
4150 OUTS (outf, ") (V)");
4151 }
4152 else if (sop == 2 && sopcde == 7)
4153 {
4154 OUTS (outf, dregs_lo (dst0));
4155 OUTS (outf, " = EXPADJ (");
4156 OUTS (outf, dregs_lo (src1));
4157 OUTS (outf, ", ");
4158 OUTS (outf, dregs_lo (src0));
4159 OUTS (outf, ")");
4160 }
4161 else if (sop == 3 && sopcde == 7)
4162 {
4163 OUTS (outf, dregs_lo (dst0));
4164 OUTS (outf, " = EXPADJ (");
4165 OUTS (outf, dregs_hi (src1));
4166 OUTS (outf, ", ");
4167 OUTS (outf, dregs_lo (src0));
4168 OUTS (outf, ")");
4169 }
4170 else if (sop == 0 && sopcde == 8)
4171 {
4172 OUTS (outf, "BITMUX (");
4173 OUTS (outf, dregs (src0));
4174 OUTS (outf, ", ");
4175 OUTS (outf, dregs (src1));
4176 OUTS (outf, ", A0) (ASR)");
4177 }
4178 else if (sop == 1 && sopcde == 8)
4179 {
4180 OUTS (outf, "BITMUX (");
4181 OUTS (outf, dregs (src0));
4182 OUTS (outf, ", ");
4183 OUTS (outf, dregs (src1));
4184 OUTS (outf, ", A0) (ASL)");
4185 }
4186 else if (sop == 0 && sopcde == 9)
4187 {
4188 OUTS (outf, dregs_lo (dst0));
4189 OUTS (outf, " = VIT_MAX (");
4190 OUTS (outf, dregs (src1));
4191 OUTS (outf, ") (ASL)");
4192 }
4193 else if (sop == 1 && sopcde == 9)
4194 {
4195 OUTS (outf, dregs_lo (dst0));
4196 OUTS (outf, " = VIT_MAX (");
4197 OUTS (outf, dregs (src1));
4198 OUTS (outf, ") (ASR)");
4199 }
4200 else if (sop == 2 && sopcde == 9)
4201 {
4202 OUTS (outf, dregs (dst0));
4203 OUTS (outf, " = VIT_MAX (");
4204 OUTS (outf, dregs (src1));
4205 OUTS (outf, ", ");
4206 OUTS (outf, dregs (src0));
4207 OUTS (outf, ") (ASL)");
4208 }
4209 else if (sop == 3 && sopcde == 9)
4210 {
4211 OUTS (outf, dregs (dst0));
4212 OUTS (outf, " = VIT_MAX (");
4213 OUTS (outf, dregs (src1));
4214 OUTS (outf, ", ");
4215 OUTS (outf, dregs (src0));
4216 OUTS (outf, ") (ASR)");
4217 }
4218 else if (sop == 0 && sopcde == 10)
4219 {
4220 OUTS (outf, dregs (dst0));
4221 OUTS (outf, " = EXTRACT (");
4222 OUTS (outf, dregs (src1));
4223 OUTS (outf, ", ");
4224 OUTS (outf, dregs_lo (src0));
4225 OUTS (outf, ") (Z)");
4226 }
4227 else if (sop == 1 && sopcde == 10)
4228 {
4229 OUTS (outf, dregs (dst0));
4230 OUTS (outf, " = EXTRACT (");
4231 OUTS (outf, dregs (src1));
4232 OUTS (outf, ", ");
4233 OUTS (outf, dregs_lo (src0));
4234 OUTS (outf, ") (X)");
4235 }
4236 else if (sop == 2 && sopcde == 10)
4237 {
4238 OUTS (outf, dregs (dst0));
4239 OUTS (outf, " = DEPOSIT (");
4240 OUTS (outf, dregs (src1));
4241 OUTS (outf, ", ");
4242 OUTS (outf, dregs (src0));
4243 OUTS (outf, ")");
4244 }
4245 else if (sop == 3 && sopcde == 10)
4246 {
4247 OUTS (outf, dregs (dst0));
4248 OUTS (outf, " = DEPOSIT (");
4249 OUTS (outf, dregs (src1));
4250 OUTS (outf, ", ");
4251 OUTS (outf, dregs (src0));
4252 OUTS (outf, ") (X)");
4253 }
4254 else if (sop == 0 && sopcde == 11)
4255 {
4256 OUTS (outf, dregs_lo (dst0));
4257 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4258 OUTS (outf, dregs (src0));
4259 OUTS (outf, ")");
4260 }
4261 else if (sop == 1 && sopcde == 11)
4262 {
4263 OUTS (outf, dregs_lo (dst0));
4264 OUTS (outf, " = CC = BXOR (A0, ");
4265 OUTS (outf, dregs (src0));
4266 OUTS (outf, ")");
4267 }
4268 else if (sop == 0 && sopcde == 12)
4269 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4270
4271 else if (sop == 1 && sopcde == 12)
4272 {
4273 OUTS (outf, dregs_lo (dst0));
4274 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4275 }
4276 else if (sop == 0 && sopcde == 13)
4277 {
4278 OUTS (outf, dregs (dst0));
4279 OUTS (outf, " = ALIGN8 (");
4280 OUTS (outf, dregs (src1));
4281 OUTS (outf, ", ");
4282 OUTS (outf, dregs (src0));
4283 OUTS (outf, ")");
4284 }
4285 else if (sop == 1 && sopcde == 13)
4286 {
4287 OUTS (outf, dregs (dst0));
4288 OUTS (outf, " = ALIGN16 (");
4289 OUTS (outf, dregs (src1));
4290 OUTS (outf, ", ");
4291 OUTS (outf, dregs (src0));
4292 OUTS (outf, ")");
4293 }
4294 else if (sop == 2 && sopcde == 13)
4295 {
4296 OUTS (outf, dregs (dst0));
4297 OUTS (outf, " = ALIGN24 (");
4298 OUTS (outf, dregs (src1));
4299 OUTS (outf, ", ");
4300 OUTS (outf, dregs (src0));
4301 OUTS (outf, ")");
4302 }
4303 else
4304 return 0;
4305
4306 return 4;
4307 }
4308
4309 static int
4310 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4311 {
4312 /* dsp32shiftimm
4313 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4314 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4315 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4316 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4317 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4318 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4319 int bit8 = ((iw1 >> 8) & 0x1);
4320 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4321 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4322 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4323 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4324 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4325
4326 if (sop == 0 && sopcde == 0)
4327 {
4328 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4329 OUTS (outf, " = ");
4330 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4331 OUTS (outf, " >>> ");
4332 OUTS (outf, uimm4 (newimmag));
4333 }
4334 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4335 {
4336 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4337 OUTS (outf, " = ");
4338 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4339 OUTS (outf, " << ");
4340 OUTS (outf, uimm4 (immag));
4341 OUTS (outf, " (S)");
4342 }
4343 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4344 {
4345 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4346 OUTS (outf, " = ");
4347 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4348 OUTS (outf, " >>> ");
4349 OUTS (outf, uimm4 (newimmag));
4350 OUTS (outf, " (S)");
4351 }
4352 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4353 {
4354 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4355 OUTS (outf, " = ");
4356 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4357 OUTS (outf, " << ");
4358 OUTS (outf, uimm4 (immag));
4359 }
4360 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4361 {
4362 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4363 OUTS (outf, " = ");
4364 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4365 OUTS (outf, " >> ");
4366 OUTS (outf, uimm4 (newimmag));
4367 }
4368 else if (sop == 2 && sopcde == 3 && HLs == 1)
4369 {
4370 OUTS (outf, "A1 = ROT A1 BY ");
4371 OUTS (outf, imm6 (immag));
4372 }
4373 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4374 {
4375 OUTS (outf, "A0 = A0 << ");
4376 OUTS (outf, uimm5 (immag));
4377 }
4378 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4379 {
4380 OUTS (outf, "A0 = A0 >>> ");
4381 OUTS (outf, uimm5 (newimmag));
4382 }
4383 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4384 {
4385 OUTS (outf, "A1 = A1 << ");
4386 OUTS (outf, uimm5 (immag));
4387 }
4388 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4389 {
4390 OUTS (outf, "A1 = A1 >>> ");
4391 OUTS (outf, uimm5 (newimmag));
4392 }
4393 else if (sop == 1 && sopcde == 3 && HLs == 0)
4394 {
4395 OUTS (outf, "A0 = A0 >> ");
4396 OUTS (outf, uimm5 (newimmag));
4397 }
4398 else if (sop == 1 && sopcde == 3 && HLs == 1)
4399 {
4400 OUTS (outf, "A1 = A1 >> ");
4401 OUTS (outf, uimm5 (newimmag));
4402 }
4403 else if (sop == 2 && sopcde == 3 && HLs == 0)
4404 {
4405 OUTS (outf, "A0 = ROT A0 BY ");
4406 OUTS (outf, imm6 (immag));
4407 }
4408 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4409 {
4410 OUTS (outf, dregs (dst0));
4411 OUTS (outf, " = ");
4412 OUTS (outf, dregs (src1));
4413 OUTS (outf, " << ");
4414 OUTS (outf, uimm5 (immag));
4415 OUTS (outf, " (V, S)");
4416 }
4417 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4418 {
4419 OUTS (outf, dregs (dst0));
4420 OUTS (outf, " = ");
4421 OUTS (outf, dregs (src1));
4422 OUTS (outf, " >>> ");
4423 OUTS (outf, imm5 (-immag));
4424 OUTS (outf, " (V, S)");
4425 }
4426 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4427 {
4428 OUTS (outf, dregs (dst0));
4429 OUTS (outf, " = ");
4430 OUTS (outf, dregs (src1));
4431 OUTS (outf, " >> ");
4432 OUTS (outf, uimm5 (newimmag));
4433 OUTS (outf, " (V)");
4434 }
4435 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4436 {
4437 OUTS (outf, dregs (dst0));
4438 OUTS (outf, " = ");
4439 OUTS (outf, dregs (src1));
4440 OUTS (outf, " << ");
4441 OUTS (outf, imm5 (immag));
4442 OUTS (outf, " (V)");
4443 }
4444 else if (sop == 0 && sopcde == 1)
4445 {
4446 OUTS (outf, dregs (dst0));
4447 OUTS (outf, " = ");
4448 OUTS (outf, dregs (src1));
4449 OUTS (outf, " >>> ");
4450 OUTS (outf, uimm5 (newimmag));
4451 OUTS (outf, " (V)");
4452 }
4453 else if (sop == 1 && sopcde == 2)
4454 {
4455 OUTS (outf, dregs (dst0));
4456 OUTS (outf, " = ");
4457 OUTS (outf, dregs (src1));
4458 OUTS (outf, " << ");
4459 OUTS (outf, uimm5 (immag));
4460 OUTS (outf, " (S)");
4461 }
4462 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4463 {
4464 OUTS (outf, dregs (dst0));
4465 OUTS (outf, " = ");
4466 OUTS (outf, dregs (src1));
4467 OUTS (outf, " >> ");
4468 OUTS (outf, uimm5 (newimmag));
4469 }
4470 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4471 {
4472 OUTS (outf, dregs (dst0));
4473 OUTS (outf, " = ");
4474 OUTS (outf, dregs (src1));
4475 OUTS (outf, " << ");
4476 OUTS (outf, uimm5 (immag));
4477 }
4478 else if (sop == 3 && sopcde == 2)
4479 {
4480 OUTS (outf, dregs (dst0));
4481 OUTS (outf, " = ROT ");
4482 OUTS (outf, dregs (src1));
4483 OUTS (outf, " BY ");
4484 OUTS (outf, imm6 (immag));
4485 }
4486 else if (sop == 0 && sopcde == 2)
4487 {
4488 OUTS (outf, dregs (dst0));
4489 OUTS (outf, " = ");
4490 OUTS (outf, dregs (src1));
4491 OUTS (outf, " >>> ");
4492 OUTS (outf, uimm5 (newimmag));
4493 }
4494 else
4495 return 0;
4496
4497 return 4;
4498 }
4499
4500 static int
4501 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4502 {
4503 struct private *priv = outf->private_data;
4504 /* pseudoDEBUG
4505 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4506 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4507 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4508 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4509 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4510 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4511
4512 if (priv->parallel)
4513 return 0;
4514
4515 if (reg == 0 && fn == 3)
4516 OUTS (outf, "DBG A0");
4517
4518 else if (reg == 1 && fn == 3)
4519 OUTS (outf, "DBG A1");
4520
4521 else if (reg == 3 && fn == 3)
4522 OUTS (outf, "ABORT");
4523
4524 else if (reg == 4 && fn == 3)
4525 OUTS (outf, "HLT");
4526
4527 else if (reg == 5 && fn == 3)
4528 OUTS (outf, "DBGHALT");
4529
4530 else if (reg == 6 && fn == 3)
4531 {
4532 OUTS (outf, "DBGCMPLX (");
4533 OUTS (outf, dregs (grp));
4534 OUTS (outf, ")");
4535 }
4536 else if (reg == 7 && fn == 3)
4537 OUTS (outf, "DBG");
4538
4539 else if (grp == 0 && fn == 2)
4540 {
4541 OUTS (outf, "OUTC ");
4542 OUTS (outf, dregs (reg));
4543 }
4544 else if (fn == 0)
4545 {
4546 OUTS (outf, "DBG ");
4547 OUTS (outf, allregs (reg, grp));
4548 }
4549 else if (fn == 1)
4550 {
4551 OUTS (outf, "PRNT ");
4552 OUTS (outf, allregs (reg, grp));
4553 }
4554 else
4555 return 0;
4556
4557 return 2;
4558 }
4559
4560 static int
4561 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4562 {
4563 struct private *priv = outf->private_data;
4564 /* psedoOChar
4565 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4566 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4567 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4568 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4569
4570 if (priv->parallel)
4571 return 0;
4572
4573 OUTS (outf, "OUTC ");
4574 OUTS (outf, uimm8 (ch));
4575
4576 return 2;
4577 }
4578
4579 static int
4580 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4581 {
4582 struct private *priv = outf->private_data;
4583 /* pseudodbg_assert
4584 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4585 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4586 |.expected......................................................|
4587 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4588 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4589 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4590 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4591 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4592
4593 if (priv->parallel)
4594 return 0;
4595
4596 if (dbgop == 0)
4597 {
4598 OUTS (outf, "DBGA (");
4599 OUTS (outf, regs_lo (regtest, grp));
4600 OUTS (outf, ", ");
4601 OUTS (outf, uimm16 (expected));
4602 OUTS (outf, ")");
4603 }
4604 else if (dbgop == 1)
4605 {
4606 OUTS (outf, "DBGA (");
4607 OUTS (outf, regs_hi (regtest, grp));
4608 OUTS (outf, ", ");
4609 OUTS (outf, uimm16 (expected));
4610 OUTS (outf, ")");
4611 }
4612 else if (dbgop == 2)
4613 {
4614 OUTS (outf, "DBGAL (");
4615 OUTS (outf, allregs (regtest, grp));
4616 OUTS (outf, ", ");
4617 OUTS (outf, uimm16 (expected));
4618 OUTS (outf, ")");
4619 }
4620 else if (dbgop == 3)
4621 {
4622 OUTS (outf, "DBGAH (");
4623 OUTS (outf, allregs (regtest, grp));
4624 OUTS (outf, ", ");
4625 OUTS (outf, uimm16 (expected));
4626 OUTS (outf, ")");
4627 }
4628 else
4629 return 0;
4630 return 4;
4631 }
4632
4633 static int
4634 ifetch (bfd_vma pc, disassemble_info *outf, TIword *iw)
4635 {
4636 bfd_byte buf[2];
4637 int status;
4638
4639 status = (*outf->read_memory_func) (pc, buf, 2, outf);
4640 if (status != 0)
4641 {
4642 (*outf->memory_error_func) (status, pc, outf);
4643 return -1;
4644 }
4645
4646 *iw = bfd_getl16 (buf);
4647 return 0;
4648 }
4649
4650 static int
4651 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4652 {
4653 struct private *priv = outf->private_data;
4654 TIword iw0;
4655 TIword iw1;
4656 int rv = 0;
4657
4658 /* The PC must be 16-bit aligned. */
4659 if (pc & 1)
4660 {
4661 OUTS (outf, "ILLEGAL (UNALIGNED)");
4662 /* For people dumping data, just re-align the return value. */
4663 return 1;
4664 }
4665
4666 if (ifetch (pc, outf, &iw0))
4667 return -1;
4668 priv->iw0 = iw0;
4669
4670 if (((iw0 & 0xc000) == 0xc000) && ((iw0 & 0xff00) != 0xf800))
4671 {
4672 /* 32-bit insn. */
4673 if (ifetch (pc + 2, outf, &iw1))
4674 return -1;
4675 }
4676 else
4677 /* 16-bit insn. */
4678 iw1 = 0;
4679
4680 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4681 {
4682 if (priv->parallel)
4683 {
4684 OUTS (outf, "ILLEGAL");
4685 return 0;
4686 }
4687 OUTS (outf, "MNOP");
4688 return 4;
4689 }
4690 else if ((iw0 & 0xff00) == 0x0000)
4691 rv = decode_ProgCtrl_0 (iw0, outf);
4692 else if ((iw0 & 0xffc0) == 0x0240)
4693 rv = decode_CaCTRL_0 (iw0, outf);
4694 else if ((iw0 & 0xff80) == 0x0100)
4695 rv = decode_PushPopReg_0 (iw0, outf);
4696 else if ((iw0 & 0xfe00) == 0x0400)
4697 rv = decode_PushPopMultiple_0 (iw0, outf);
4698 else if ((iw0 & 0xfe00) == 0x0600)
4699 rv = decode_ccMV_0 (iw0, outf);
4700 else if ((iw0 & 0xf800) == 0x0800)
4701 rv = decode_CCflag_0 (iw0, outf);
4702 else if ((iw0 & 0xffe0) == 0x0200)
4703 rv = decode_CC2dreg_0 (iw0, outf);
4704 else if ((iw0 & 0xff00) == 0x0300)
4705 rv = decode_CC2stat_0 (iw0, outf);
4706 else if ((iw0 & 0xf000) == 0x1000)
4707 rv = decode_BRCC_0 (iw0, pc, outf);
4708 else if ((iw0 & 0xf000) == 0x2000)
4709 rv = decode_UJUMP_0 (iw0, pc, outf);
4710 else if ((iw0 & 0xf000) == 0x3000)
4711 rv = decode_REGMV_0 (iw0, outf);
4712 else if ((iw0 & 0xfc00) == 0x4000)
4713 rv = decode_ALU2op_0 (iw0, outf);
4714 else if ((iw0 & 0xfe00) == 0x4400)
4715 rv = decode_PTR2op_0 (iw0, outf);
4716 else if ((iw0 & 0xf800) == 0x4800)
4717 rv = decode_LOGI2op_0 (iw0, outf);
4718 else if ((iw0 & 0xf000) == 0x5000)
4719 rv = decode_COMP3op_0 (iw0, outf);
4720 else if ((iw0 & 0xf800) == 0x6000)
4721 rv = decode_COMPI2opD_0 (iw0, outf);
4722 else if ((iw0 & 0xf800) == 0x6800)
4723 rv = decode_COMPI2opP_0 (iw0, outf);
4724 else if ((iw0 & 0xf000) == 0x8000)
4725 rv = decode_LDSTpmod_0 (iw0, outf);
4726 else if ((iw0 & 0xff60) == 0x9e60)
4727 rv = decode_dagMODim_0 (iw0, outf);
4728 else if ((iw0 & 0xfff0) == 0x9f60)
4729 rv = decode_dagMODik_0 (iw0, outf);
4730 else if ((iw0 & 0xfc00) == 0x9c00)
4731 rv = decode_dspLDST_0 (iw0, outf);
4732 else if ((iw0 & 0xf000) == 0x9000)
4733 rv = decode_LDST_0 (iw0, outf);
4734 else if ((iw0 & 0xfc00) == 0xb800)
4735 rv = decode_LDSTiiFP_0 (iw0, outf);
4736 else if ((iw0 & 0xe000) == 0xA000)
4737 rv = decode_LDSTii_0 (iw0, outf);
4738 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4739 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4740 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4741 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4742 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4743 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4744 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4745 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4746 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4747 rv = decode_linkage_0 (iw0, iw1, outf);
4748 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4749 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4750 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4751 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4752 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4753 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4754 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4755 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4756 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4757 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4758 else if ((iw0 & 0xff00) == 0xf800)
4759 rv = decode_pseudoDEBUG_0 (iw0, outf);
4760 else if ((iw0 & 0xFF00) == 0xF900)
4761 rv = decode_pseudoOChar_0 (iw0, outf);
4762 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4763 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4764
4765 if (rv == 0)
4766 OUTS (outf, "ILLEGAL");
4767
4768 return rv;
4769 }
4770
4771 int
4772 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4773 {
4774 struct private priv;
4775 int count;
4776
4777 priv.parallel = FALSE;
4778 priv.comment = FALSE;
4779 outf->private_data = &priv;
4780
4781 count = _print_insn_bfin (pc, outf);
4782 if (count == -1)
4783 return -1;
4784
4785 /* Proper display of multiple issue instructions. */
4786
4787 if (count == 4 && (priv.iw0 & 0xc000) == 0xc000 && (priv.iw0 & BIT_MULTI_INS)
4788 && ((priv.iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4789 {
4790 bfd_boolean legal = TRUE;
4791 int len;
4792
4793 priv.parallel = TRUE;
4794 OUTS (outf, " || ");
4795 len = _print_insn_bfin (pc + 4, outf);
4796 if (len == -1)
4797 return -1;
4798 OUTS (outf, " || ");
4799 if (len != 2)
4800 legal = FALSE;
4801 len = _print_insn_bfin (pc + 6, outf);
4802 if (len == -1)
4803 return -1;
4804 if (len != 2)
4805 legal = FALSE;
4806
4807 if (legal)
4808 count = 8;
4809 else
4810 {
4811 OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4812 priv.comment = TRUE;
4813 count = 0;
4814 }
4815 }
4816
4817 if (!priv.comment)
4818 OUTS (outf, ";");
4819
4820 if (count == 0)
4821 return 2;
4822
4823 return count;
4824 }
GDB Binutils - Deliverables
This page took 0.142155 seconds and 4 git commands to generate.