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opcodes: blackfin: fix style
[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c
1 /* Disassemble ADI Blackfin Instructions.
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4
5 This file is part of libopcodes.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #include <stdio.h>
23 #include <stdlib.h>
24 #include <string.h>
25
26 #include "opcode/bfin.h"
27
28 #ifndef PRINTF
29 #define PRINTF printf
30 #endif
31
32 #ifndef EXIT
33 #define EXIT exit
34 #endif
35
36 typedef long TIword;
37
38 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
39 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
40 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
41 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
42
43 #include "dis-asm.h"
44
45 typedef unsigned int bu32;
46
47 static char comment = 0;
48 static char parallel = 0;
49
50 typedef enum
51 {
52 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
53 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
54 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
55 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
56 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
57 } const_forms_t;
58
59 static const struct
60 {
61 const char *name;
62 const int nbits;
63 const char reloc;
64 const char issigned;
65 const char pcrel;
66 const char scale;
67 const char offset;
68 const char negative;
69 const char positive;
70 const char decimal;
71 const char leading;
72 const char exact;
73 } constant_formats[] =
74 {
75 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
76 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
78 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
79 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
80 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
81 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
82 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
83 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
84 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
85 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
86 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
88 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
89 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
91 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
92 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
94 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
95 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
97 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
98 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
99 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
100 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
101 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
102 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
103 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
104 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
107 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
108 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
109 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
110 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
111 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
112 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
113 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
114 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
118 };
119
120 static const char *
121 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
122 {
123 static char buf[60];
124
125 if (constant_formats[cf].reloc)
126 {
127 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
128 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
129 if (constant_formats[cf].pcrel)
130 ea += pc;
131
132 /* truncate to 32-bits for proper symbol lookup/matching */
133 ea = (bu32)ea;
134
135 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
136 {
137 outf->print_address_func (ea, outf);
138 return "";
139 }
140 else
141 {
142 sprintf (buf, "%lx", (unsigned long) x);
143 return buf;
144 }
145 }
146
147 /* Negative constants have an implied sign bit. */
148 if (constant_formats[cf].negative)
149 {
150 int nb = constant_formats[cf].nbits + 1;
151
152 x = x | (1 << constant_formats[cf].nbits);
153 x = SIGNEXTEND (x, nb);
154 }
155 else
156 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
157
158 if (constant_formats[cf].offset)
159 x += constant_formats[cf].offset;
160
161 if (constant_formats[cf].scale)
162 x <<= constant_formats[cf].scale;
163
164 if (constant_formats[cf].decimal)
165 {
166 if (constant_formats[cf].leading)
167 {
168 char ps[10];
169 sprintf (ps, "%%%ii", constant_formats[cf].leading);
170 sprintf (buf, ps, x);
171 }
172 else
173 sprintf (buf, "%li", x);
174 }
175 else
176 {
177 if (constant_formats[cf].issigned && x < 0)
178 sprintf (buf, "-0x%x", abs (x));
179 else
180 sprintf (buf, "0x%lx", (unsigned long) x);
181 }
182
183 return buf;
184 }
185
186 static bu32
187 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
188 {
189 if (0 && constant_formats[cf].reloc)
190 {
191 bu32 ea = (((constant_formats[cf].pcrel
192 ? SIGNEXTEND (x, constant_formats[cf].nbits)
193 : x) + constant_formats[cf].offset)
194 << constant_formats[cf].scale);
195 if (constant_formats[cf].pcrel)
196 ea += pc;
197
198 return ea;
199 }
200
201 /* Negative constants have an implied sign bit. */
202 if (constant_formats[cf].negative)
203 {
204 int nb = constant_formats[cf].nbits + 1;
205 x = x | (1 << constant_formats[cf].nbits);
206 x = SIGNEXTEND (x, nb);
207 }
208 else if (constant_formats[cf].issigned)
209 x = SIGNEXTEND (x, constant_formats[cf].nbits);
210
211 x += constant_formats[cf].offset;
212 x <<= constant_formats[cf].scale;
213
214 return x;
215 }
216
217 enum machine_registers
218 {
219 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
220 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
221 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
222 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
223 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
224 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
225 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
226 REG_L2, REG_L3,
227 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
228 REG_AQ, REG_V, REG_VS,
229 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
230 REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
231 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
232 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
233 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
234 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
235 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
236 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
237 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
238 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
239 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
240 REG_LASTREG,
241 };
242
243 enum reg_class
244 {
245 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
246 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
247 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
248 rc_sysregs3, rc_allregs,
249 LIM_REG_CLASSES
250 };
251
252 static const char * const reg_names[] =
253 {
254 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
255 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
256 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
257 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
258 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
259 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
260 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
261 "L2", "L3",
262 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
263 "AQ", "V", "VS",
264 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
265 "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
266 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
267 "RETE", "EMUDAT",
268 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
269 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
270 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
271 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
272 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
273 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
274 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
275 "AC0_COPY", "V_COPY", "RND_MOD",
276 "LASTREG",
277 0
278 };
279
280 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
281
282 /* RL(0..7). */
283 static const enum machine_registers decode_dregs_lo[] =
284 {
285 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
286 };
287
288 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
289
290 /* RH(0..7). */
291 static const enum machine_registers decode_dregs_hi[] =
292 {
293 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
294 };
295
296 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
297
298 /* R(0..7). */
299 static const enum machine_registers decode_dregs[] =
300 {
301 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
302 };
303
304 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
305
306 /* R BYTE(0..7). */
307 static const enum machine_registers decode_dregs_byte[] =
308 {
309 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
310 };
311
312 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
313
314 /* P(0..5) SP FP. */
315 static const enum machine_registers decode_pregs[] =
316 {
317 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
318 };
319
320 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
321 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
322 #define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
323 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
324 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
325 #define accum(x) REGNAME (decode_accum[(x) & 1])
326
327 /* I(0..3). */
328 static const enum machine_registers decode_iregs[] =
329 {
330 REG_I0, REG_I1, REG_I2, REG_I3,
331 };
332
333 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
334
335 /* M(0..3). */
336 static const enum machine_registers decode_mregs[] =
337 {
338 REG_M0, REG_M1, REG_M2, REG_M3,
339 };
340
341 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
342 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
343 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
344
345 /* dregs pregs. */
346 static const enum machine_registers decode_dpregs[] =
347 {
348 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
349 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
350 };
351
352 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
353
354 /* [dregs pregs]. */
355 static const enum machine_registers decode_gregs[] =
356 {
357 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
358 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
359 };
360
361 #define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
362
363 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
364 static const enum machine_registers decode_regs[] =
365 {
366 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
367 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
368 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
369 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
370 };
371
372 #define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
373
374 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
375 static const enum machine_registers decode_regs_lo[] =
376 {
377 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
378 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
379 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
380 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
381 };
382
383 #define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
384
385 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
386 static const enum machine_registers decode_regs_hi[] =
387 {
388 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
389 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
390 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
391 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
392 };
393
394 #define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
395
396 static const enum machine_registers decode_statbits[] =
397 {
398 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
399 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
400 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
401 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
402 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
403 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
404 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
405 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
406 };
407
408 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
409
410 /* LC0 LC1. */
411 static const enum machine_registers decode_counters[] =
412 {
413 REG_LC0, REG_LC1,
414 };
415
416 #define counters(x) REGNAME (decode_counters[(x) & 1])
417 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
418
419 /* [dregs pregs (iregs mregs) (bregs lregs)
420 dregs2_sysregs1 open sysregs2 sysregs3]. */
421 static const enum machine_registers decode_allregs[] =
422 {
423 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
424 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
425 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
426 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
427 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
428 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
429 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
430 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
431 REG_LASTREG,
432 };
433
434 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
435 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
436 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
437 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
438 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
439 #define IS_SYSREG(g,r) \
440 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
441 #define IS_RESERVEDREG(g,r) \
442 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
443
444 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
445 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
446
447 #define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
448 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
449 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
450 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
451 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
452 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
453 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
454 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
455 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
456 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
457 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
458 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
459 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
460 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
461 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
462 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
463 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
464 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
465 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
466 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
467 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
468 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
469 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
470 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
471 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
472 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
473 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
474 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
475 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
476 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
477 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
478 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
479 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
480 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
481 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
482 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
483 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
484 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
485 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
486 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
487 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
488 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
489 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
490
491 /* (arch.pm)arch_disassembler_functions. */
492 #ifndef OUTS
493 #define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
494 #endif
495
496 static void
497 amod0 (int s0, int x0, disassemble_info *outf)
498 {
499 if (s0 == 1 && x0 == 0)
500 OUTS (outf, " (S)");
501 else if (s0 == 0 && x0 == 1)
502 OUTS (outf, " (CO)");
503 else if (s0 == 1 && x0 == 1)
504 OUTS (outf, " (SCO)");
505 }
506
507 static void
508 amod1 (int s0, int x0, disassemble_info *outf)
509 {
510 if (s0 == 0 && x0 == 0)
511 OUTS (outf, " (NS)");
512 else if (s0 == 1 && x0 == 0)
513 OUTS (outf, " (S)");
514 }
515
516 static void
517 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
518 {
519 if (s0 == 1 && x0 == 0 && aop0 == 0)
520 OUTS (outf, " (S)");
521 else if (s0 == 0 && x0 == 1 && aop0 == 0)
522 OUTS (outf, " (CO)");
523 else if (s0 == 1 && x0 == 1 && aop0 == 0)
524 OUTS (outf, " (SCO)");
525 else if (s0 == 0 && x0 == 0 && aop0 == 2)
526 OUTS (outf, " (ASR)");
527 else if (s0 == 1 && x0 == 0 && aop0 == 2)
528 OUTS (outf, " (S, ASR)");
529 else if (s0 == 0 && x0 == 1 && aop0 == 2)
530 OUTS (outf, " (CO, ASR)");
531 else if (s0 == 1 && x0 == 1 && aop0 == 2)
532 OUTS (outf, " (SCO, ASR)");
533 else if (s0 == 0 && x0 == 0 && aop0 == 3)
534 OUTS (outf, " (ASL)");
535 else if (s0 == 1 && x0 == 0 && aop0 == 3)
536 OUTS (outf, " (S, ASL)");
537 else if (s0 == 0 && x0 == 1 && aop0 == 3)
538 OUTS (outf, " (CO, ASL)");
539 else if (s0 == 1 && x0 == 1 && aop0 == 3)
540 OUTS (outf, " (SCO, ASL)");
541 }
542
543 static void
544 searchmod (int r0, disassemble_info *outf)
545 {
546 if (r0 == 0)
547 OUTS (outf, "GT");
548 else if (r0 == 1)
549 OUTS (outf, "GE");
550 else if (r0 == 2)
551 OUTS (outf, "LT");
552 else if (r0 == 3)
553 OUTS (outf, "LE");
554 }
555
556 static void
557 aligndir (int r0, disassemble_info *outf)
558 {
559 if (r0 == 1)
560 OUTS (outf, " (R)");
561 }
562
563 static int
564 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
565 {
566 const char *s0, *s1;
567
568 if (h0)
569 s0 = dregs_hi (src0);
570 else
571 s0 = dregs_lo (src0);
572
573 if (h1)
574 s1 = dregs_hi (src1);
575 else
576 s1 = dregs_lo (src1);
577
578 OUTS (outf, s0);
579 OUTS (outf, " * ");
580 OUTS (outf, s1);
581 return 0;
582 }
583
584 static int
585 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
586 {
587 const char *a;
588 const char *sop = "<unknown op>";
589
590 if (which)
591 a = "A1";
592 else
593 a = "A0";
594
595 if (op == 3)
596 {
597 OUTS (outf, a);
598 return 0;
599 }
600
601 switch (op)
602 {
603 case 0: sop = " = "; break;
604 case 1: sop = " += "; break;
605 case 2: sop = " -= "; break;
606 default: break;
607 }
608
609 OUTS (outf, a);
610 OUTS (outf, sop);
611 decode_multfunc (h0, h1, src0, src1, outf);
612
613 return 0;
614 }
615
616 static void
617 decode_optmode (int mod, int MM, disassemble_info *outf)
618 {
619 if (mod == 0 && MM == 0)
620 return;
621
622 OUTS (outf, " (");
623
624 if (MM && !mod)
625 {
626 OUTS (outf, "M)");
627 return;
628 }
629
630 if (MM)
631 OUTS (outf, "M, ");
632
633 if (mod == M_S2RND)
634 OUTS (outf, "S2RND");
635 else if (mod == M_T)
636 OUTS (outf, "T");
637 else if (mod == M_W32)
638 OUTS (outf, "W32");
639 else if (mod == M_FU)
640 OUTS (outf, "FU");
641 else if (mod == M_TFU)
642 OUTS (outf, "TFU");
643 else if (mod == M_IS)
644 OUTS (outf, "IS");
645 else if (mod == M_ISS2)
646 OUTS (outf, "ISS2");
647 else if (mod == M_IH)
648 OUTS (outf, "IH");
649 else if (mod == M_IU)
650 OUTS (outf, "IU");
651 else
652 abort ();
653
654 OUTS (outf, ")");
655 }
656
657 struct saved_state
658 {
659 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
660 bu32 a0x, a0w, a1x, a1w;
661 bu32 lt[2], lc[2], lb[2];
662 int ac0, ac0_copy, ac1, an, aq;
663 int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
664 int rnd_mod;
665 int v_internal;
666 bu32 pc, rets;
667
668 int ticks;
669 int insts;
670
671 int exception;
672
673 int end_of_registers;
674
675 int msize;
676 unsigned char *memory;
677 unsigned long bfd_mach;
678 } saved_state;
679
680 #define DREG(x) (saved_state.dpregs[x])
681 #define GREG(x, i) DPREG ((x) | ((i) << 3))
682 #define DPREG(x) (saved_state.dpregs[x])
683 #define DREG(x) (saved_state.dpregs[x])
684 #define PREG(x) (saved_state.dpregs[(x) + 8])
685 #define SPREG PREG (6)
686 #define FPREG PREG (7)
687 #define IREG(x) (saved_state.iregs[x])
688 #define MREG(x) (saved_state.mregs[x])
689 #define BREG(x) (saved_state.bregs[x])
690 #define LREG(x) (saved_state.lregs[x])
691 #define A0XREG (saved_state.a0x)
692 #define A0WREG (saved_state.a0w)
693 #define A1XREG (saved_state.a1x)
694 #define A1WREG (saved_state.a1w)
695 #define CCREG (saved_state.cc)
696 #define LC0REG (saved_state.lc[0])
697 #define LT0REG (saved_state.lt[0])
698 #define LB0REG (saved_state.lb[0])
699 #define LC1REG (saved_state.lc[1])
700 #define LT1REG (saved_state.lt[1])
701 #define LB1REG (saved_state.lb[1])
702 #define RETSREG (saved_state.rets)
703 #define PCREG (saved_state.pc)
704
705 static bu32 *
706 get_allreg (int grp, int reg)
707 {
708 int fullreg = (grp << 3) | reg;
709 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
710 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
711 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
712 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
713 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
714 , , , , , , , ,
715 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
716 REG_CYCLES2,
717 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
718 REG_LASTREG */
719 switch (fullreg >> 2)
720 {
721 case 0: case 1: return &DREG (reg); break;
722 case 2: case 3: return &PREG (reg); break;
723 case 4: return &IREG (reg & 3); break;
724 case 5: return &MREG (reg & 3); break;
725 case 6: return &BREG (reg & 3); break;
726 case 7: return &LREG (reg & 3); break;
727 default:
728 switch (fullreg)
729 {
730 case 32: return &saved_state.a0x;
731 case 33: return &saved_state.a0w;
732 case 34: return &saved_state.a1x;
733 case 35: return &saved_state.a1w;
734 case 39: return &saved_state.rets;
735 case 48: return &LC0REG;
736 case 49: return &LT0REG;
737 case 50: return &LB0REG;
738 case 51: return &LC1REG;
739 case 52: return &LT1REG;
740 case 53: return &LB1REG;
741 }
742 return 0;
743 }
744 }
745
746 static int
747 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
748 {
749 /* ProgCtrl
750 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
751 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
752 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
753 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
754 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
755
756 if (prgfunc == 0 && poprnd == 0)
757 OUTS (outf, "NOP");
758 else if (parallel)
759 return 0;
760 else if (prgfunc == 1 && poprnd == 0)
761 OUTS (outf, "RTS");
762 else if (prgfunc == 1 && poprnd == 1)
763 OUTS (outf, "RTI");
764 else if (prgfunc == 1 && poprnd == 2)
765 OUTS (outf, "RTX");
766 else if (prgfunc == 1 && poprnd == 3)
767 OUTS (outf, "RTN");
768 else if (prgfunc == 1 && poprnd == 4)
769 OUTS (outf, "RTE");
770 else if (prgfunc == 2 && poprnd == 0)
771 OUTS (outf, "IDLE");
772 else if (prgfunc == 2 && poprnd == 3)
773 OUTS (outf, "CSYNC");
774 else if (prgfunc == 2 && poprnd == 4)
775 OUTS (outf, "SSYNC");
776 else if (prgfunc == 2 && poprnd == 5)
777 OUTS (outf, "EMUEXCPT");
778 else if (prgfunc == 3 && IS_DREG (0, poprnd))
779 {
780 OUTS (outf, "CLI ");
781 OUTS (outf, dregs (poprnd));
782 }
783 else if (prgfunc == 4 && IS_DREG (0, poprnd))
784 {
785 OUTS (outf, "STI ");
786 OUTS (outf, dregs (poprnd));
787 }
788 else if (prgfunc == 5 && IS_PREG (1, poprnd))
789 {
790 OUTS (outf, "JUMP (");
791 OUTS (outf, pregs (poprnd));
792 OUTS (outf, ")");
793 }
794 else if (prgfunc == 6 && IS_PREG (1, poprnd))
795 {
796 OUTS (outf, "CALL (");
797 OUTS (outf, pregs (poprnd));
798 OUTS (outf, ")");
799 }
800 else if (prgfunc == 7 && IS_PREG (1, poprnd))
801 {
802 OUTS (outf, "CALL (PC + ");
803 OUTS (outf, pregs (poprnd));
804 OUTS (outf, ")");
805 }
806 else if (prgfunc == 8 && IS_PREG (1, poprnd))
807 {
808 OUTS (outf, "JUMP (PC + ");
809 OUTS (outf, pregs (poprnd));
810 OUTS (outf, ")");
811 }
812 else if (prgfunc == 9)
813 {
814 OUTS (outf, "RAISE ");
815 OUTS (outf, uimm4 (poprnd));
816 }
817 else if (prgfunc == 10)
818 {
819 OUTS (outf, "EXCPT ");
820 OUTS (outf, uimm4 (poprnd));
821 }
822 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
823 {
824 OUTS (outf, "TESTSET (");
825 OUTS (outf, pregs (poprnd));
826 OUTS (outf, ")");
827 }
828 else
829 return 0;
830 return 2;
831 }
832
833 static int
834 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
835 {
836 /* CaCTRL
837 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
838 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
839 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
840 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
841 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
842 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
843
844 if (parallel)
845 return 0;
846
847 if (a == 0 && op == 0)
848 {
849 OUTS (outf, "PREFETCH[");
850 OUTS (outf, pregs (reg));
851 OUTS (outf, "]");
852 }
853 else if (a == 0 && op == 1)
854 {
855 OUTS (outf, "FLUSHINV[");
856 OUTS (outf, pregs (reg));
857 OUTS (outf, "]");
858 }
859 else if (a == 0 && op == 2)
860 {
861 OUTS (outf, "FLUSH[");
862 OUTS (outf, pregs (reg));
863 OUTS (outf, "]");
864 }
865 else if (a == 0 && op == 3)
866 {
867 OUTS (outf, "IFLUSH[");
868 OUTS (outf, pregs (reg));
869 OUTS (outf, "]");
870 }
871 else if (a == 1 && op == 0)
872 {
873 OUTS (outf, "PREFETCH[");
874 OUTS (outf, pregs (reg));
875 OUTS (outf, "++]");
876 }
877 else if (a == 1 && op == 1)
878 {
879 OUTS (outf, "FLUSHINV[");
880 OUTS (outf, pregs (reg));
881 OUTS (outf, "++]");
882 }
883 else if (a == 1 && op == 2)
884 {
885 OUTS (outf, "FLUSH[");
886 OUTS (outf, pregs (reg));
887 OUTS (outf, "++]");
888 }
889 else if (a == 1 && op == 3)
890 {
891 OUTS (outf, "IFLUSH[");
892 OUTS (outf, pregs (reg));
893 OUTS (outf, "++]");
894 }
895 else
896 return 0;
897 return 2;
898 }
899
900 static int
901 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
902 {
903 /* PushPopReg
904 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
905 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
906 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
907 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
908 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
909 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
910
911 if (parallel)
912 return 0;
913
914 if (W == 0 && mostreg (reg, grp))
915 {
916 OUTS (outf, allregs (reg, grp));
917 OUTS (outf, " = [SP++]");
918 }
919 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
920 {
921 OUTS (outf, "[--SP] = ");
922 OUTS (outf, allregs (reg, grp));
923 }
924 else
925 return 0;
926 return 2;
927 }
928
929 static int
930 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
931 {
932 /* PushPopMultiple
933 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
934 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
935 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
936 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
937 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
938 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
939 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
940 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
941
942 if (parallel)
943 return 0;
944
945 if (pr > 5)
946 return 0;
947
948 if (W == 1 && d == 1 && p == 1)
949 {
950 OUTS (outf, "[--SP] = (R7:");
951 OUTS (outf, imm5d (dr));
952 OUTS (outf, ", P5:");
953 OUTS (outf, imm5d (pr));
954 OUTS (outf, ")");
955 }
956 else if (W == 1 && d == 1 && p == 0 && pr == 0)
957 {
958 OUTS (outf, "[--SP] = (R7:");
959 OUTS (outf, imm5d (dr));
960 OUTS (outf, ")");
961 }
962 else if (W == 1 && d == 0 && p == 1 && dr == 0)
963 {
964 OUTS (outf, "[--SP] = (P5:");
965 OUTS (outf, imm5d (pr));
966 OUTS (outf, ")");
967 }
968 else if (W == 0 && d == 1 && p == 1)
969 {
970 OUTS (outf, "(R7:");
971 OUTS (outf, imm5d (dr));
972 OUTS (outf, ", P5:");
973 OUTS (outf, imm5d (pr));
974 OUTS (outf, ") = [SP++]");
975 }
976 else if (W == 0 && d == 1 && p == 0 && pr == 0)
977 {
978 OUTS (outf, "(R7:");
979 OUTS (outf, imm5d (dr));
980 OUTS (outf, ") = [SP++]");
981 }
982 else if (W == 0 && d == 0 && p == 1 && dr == 0)
983 {
984 OUTS (outf, "(P5:");
985 OUTS (outf, imm5d (pr));
986 OUTS (outf, ") = [SP++]");
987 }
988 else
989 return 0;
990 return 2;
991 }
992
993 static int
994 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
995 {
996 /* ccMV
997 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
998 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
999 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1000 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
1001 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
1002 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
1003 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
1004 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
1005
1006 if (parallel)
1007 return 0;
1008
1009 if (T == 1)
1010 {
1011 OUTS (outf, "IF CC ");
1012 OUTS (outf, gregs (dst, d));
1013 OUTS (outf, " = ");
1014 OUTS (outf, gregs (src, s));
1015 }
1016 else if (T == 0)
1017 {
1018 OUTS (outf, "IF !CC ");
1019 OUTS (outf, gregs (dst, d));
1020 OUTS (outf, " = ");
1021 OUTS (outf, gregs (src, s));
1022 }
1023 else
1024 return 0;
1025 return 2;
1026 }
1027
1028 static int
1029 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1030 {
1031 /* CCflag
1032 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1033 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1034 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1035 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1036 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1037 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1038 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1039 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1040
1041 if (parallel)
1042 return 0;
1043
1044 if (opc == 0 && I == 0 && G == 0)
1045 {
1046 OUTS (outf, "CC = ");
1047 OUTS (outf, dregs (x));
1048 OUTS (outf, " == ");
1049 OUTS (outf, dregs (y));
1050 }
1051 else if (opc == 1 && I == 0 && G == 0)
1052 {
1053 OUTS (outf, "CC = ");
1054 OUTS (outf, dregs (x));
1055 OUTS (outf, " < ");
1056 OUTS (outf, dregs (y));
1057 }
1058 else if (opc == 2 && I == 0 && G == 0)
1059 {
1060 OUTS (outf, "CC = ");
1061 OUTS (outf, dregs (x));
1062 OUTS (outf, " <= ");
1063 OUTS (outf, dregs (y));
1064 }
1065 else if (opc == 3 && I == 0 && G == 0)
1066 {
1067 OUTS (outf, "CC = ");
1068 OUTS (outf, dregs (x));
1069 OUTS (outf, " < ");
1070 OUTS (outf, dregs (y));
1071 OUTS (outf, " (IU)");
1072 }
1073 else if (opc == 4 && I == 0 && G == 0)
1074 {
1075 OUTS (outf, "CC = ");
1076 OUTS (outf, dregs (x));
1077 OUTS (outf, " <= ");
1078 OUTS (outf, dregs (y));
1079 OUTS (outf, " (IU)");
1080 }
1081 else if (opc == 0 && I == 1 && G == 0)
1082 {
1083 OUTS (outf, "CC = ");
1084 OUTS (outf, dregs (x));
1085 OUTS (outf, " == ");
1086 OUTS (outf, imm3 (y));
1087 }
1088 else if (opc == 1 && I == 1 && G == 0)
1089 {
1090 OUTS (outf, "CC = ");
1091 OUTS (outf, dregs (x));
1092 OUTS (outf, " < ");
1093 OUTS (outf, imm3 (y));
1094 }
1095 else if (opc == 2 && I == 1 && G == 0)
1096 {
1097 OUTS (outf, "CC = ");
1098 OUTS (outf, dregs (x));
1099 OUTS (outf, " <= ");
1100 OUTS (outf, imm3 (y));
1101 }
1102 else if (opc == 3 && I == 1 && G == 0)
1103 {
1104 OUTS (outf, "CC = ");
1105 OUTS (outf, dregs (x));
1106 OUTS (outf, " < ");
1107 OUTS (outf, uimm3 (y));
1108 OUTS (outf, " (IU)");
1109 }
1110 else if (opc == 4 && I == 1 && G == 0)
1111 {
1112 OUTS (outf, "CC = ");
1113 OUTS (outf, dregs (x));
1114 OUTS (outf, " <= ");
1115 OUTS (outf, uimm3 (y));
1116 OUTS (outf, " (IU)");
1117 }
1118 else if (opc == 0 && I == 0 && G == 1)
1119 {
1120 OUTS (outf, "CC = ");
1121 OUTS (outf, pregs (x));
1122 OUTS (outf, " == ");
1123 OUTS (outf, pregs (y));
1124 }
1125 else if (opc == 1 && I == 0 && G == 1)
1126 {
1127 OUTS (outf, "CC = ");
1128 OUTS (outf, pregs (x));
1129 OUTS (outf, " < ");
1130 OUTS (outf, pregs (y));
1131 }
1132 else if (opc == 2 && I == 0 && G == 1)
1133 {
1134 OUTS (outf, "CC = ");
1135 OUTS (outf, pregs (x));
1136 OUTS (outf, " <= ");
1137 OUTS (outf, pregs (y));
1138 }
1139 else if (opc == 3 && I == 0 && G == 1)
1140 {
1141 OUTS (outf, "CC = ");
1142 OUTS (outf, pregs (x));
1143 OUTS (outf, " < ");
1144 OUTS (outf, pregs (y));
1145 OUTS (outf, " (IU)");
1146 }
1147 else if (opc == 4 && I == 0 && G == 1)
1148 {
1149 OUTS (outf, "CC = ");
1150 OUTS (outf, pregs (x));
1151 OUTS (outf, " <= ");
1152 OUTS (outf, pregs (y));
1153 OUTS (outf, " (IU)");
1154 }
1155 else if (opc == 0 && I == 1 && G == 1)
1156 {
1157 OUTS (outf, "CC = ");
1158 OUTS (outf, pregs (x));
1159 OUTS (outf, " == ");
1160 OUTS (outf, imm3 (y));
1161 }
1162 else if (opc == 1 && I == 1 && G == 1)
1163 {
1164 OUTS (outf, "CC = ");
1165 OUTS (outf, pregs (x));
1166 OUTS (outf, " < ");
1167 OUTS (outf, imm3 (y));
1168 }
1169 else if (opc == 2 && I == 1 && G == 1)
1170 {
1171 OUTS (outf, "CC = ");
1172 OUTS (outf, pregs (x));
1173 OUTS (outf, " <= ");
1174 OUTS (outf, imm3 (y));
1175 }
1176 else if (opc == 3 && I == 1 && G == 1)
1177 {
1178 OUTS (outf, "CC = ");
1179 OUTS (outf, pregs (x));
1180 OUTS (outf, " < ");
1181 OUTS (outf, uimm3 (y));
1182 OUTS (outf, " (IU)");
1183 }
1184 else if (opc == 4 && I == 1 && G == 1)
1185 {
1186 OUTS (outf, "CC = ");
1187 OUTS (outf, pregs (x));
1188 OUTS (outf, " <= ");
1189 OUTS (outf, uimm3 (y));
1190 OUTS (outf, " (IU)");
1191 }
1192 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
1193 OUTS (outf, "CC = A0 == A1");
1194
1195 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
1196 OUTS (outf, "CC = A0 < A1");
1197
1198 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
1199 OUTS (outf, "CC = A0 <= A1");
1200
1201 else
1202 return 0;
1203 return 2;
1204 }
1205
1206 static int
1207 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1208 {
1209 /* CC2dreg
1210 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1211 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1212 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1213 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1214 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1215
1216 if (parallel)
1217 return 0;
1218
1219 if (op == 0)
1220 {
1221 OUTS (outf, dregs (reg));
1222 OUTS (outf, " = CC");
1223 }
1224 else if (op == 1)
1225 {
1226 OUTS (outf, "CC = ");
1227 OUTS (outf, dregs (reg));
1228 }
1229 else if (op == 3 && reg == 0)
1230 OUTS (outf, "CC = !CC");
1231 else
1232 return 0;
1233
1234 return 2;
1235 }
1236
1237 static int
1238 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1239 {
1240 /* CC2stat
1241 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1242 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1243 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1244 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1245 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1246 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1247
1248 const char *bitname = statbits (cbit);
1249
1250 if (parallel)
1251 return 0;
1252
1253 if (decode_statbits[cbit] == REG_LASTREG)
1254 {
1255 /* All ASTAT bits except CC may be operated on in hardware, but may
1256 not have a dedicated insn, so still decode "valid" insns. */
1257 static char bitnames[64];
1258 if (cbit != 5)
1259 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1260 else
1261 return 0;
1262
1263 bitname = bitnames;
1264 }
1265
1266 if (op == 0 && D == 0)
1267 {
1268 OUTS (outf, "CC = ");
1269 OUTS (outf, bitname);
1270 }
1271 else if (op == 1 && D == 0)
1272 {
1273 OUTS (outf, "CC |= ");
1274 OUTS (outf, bitname);
1275 }
1276 else if (op == 2 && D == 0)
1277 {
1278 OUTS (outf, "CC &= ");
1279 OUTS (outf, bitname);
1280 }
1281 else if (op == 3 && D == 0)
1282 {
1283 OUTS (outf, "CC ^= ");
1284 OUTS (outf, bitname);
1285 }
1286 else if (op == 0 && D == 1)
1287 {
1288 OUTS (outf, bitname);
1289 OUTS (outf, " = CC");
1290 }
1291 else if (op == 1 && D == 1)
1292 {
1293 OUTS (outf, bitname);
1294 OUTS (outf, " |= CC");
1295 }
1296 else if (op == 2 && D == 1)
1297 {
1298 OUTS (outf, bitname);
1299 OUTS (outf, " &= CC");
1300 }
1301 else if (op == 3 && D == 1)
1302 {
1303 OUTS (outf, bitname);
1304 OUTS (outf, " ^= CC");
1305 }
1306 else
1307 return 0;
1308
1309 return 2;
1310 }
1311
1312 static int
1313 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1314 {
1315 /* BRCC
1316 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1317 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1318 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1319 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1320 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1321 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1322
1323 if (parallel)
1324 return 0;
1325
1326 if (T == 1 && B == 1)
1327 {
1328 OUTS (outf, "IF CC JUMP 0x");
1329 OUTS (outf, pcrel10 (offset));
1330 OUTS (outf, " (BP)");
1331 }
1332 else if (T == 0 && B == 1)
1333 {
1334 OUTS (outf, "IF !CC JUMP 0x");
1335 OUTS (outf, pcrel10 (offset));
1336 OUTS (outf, " (BP)");
1337 }
1338 else if (T == 1)
1339 {
1340 OUTS (outf, "IF CC JUMP 0x");
1341 OUTS (outf, pcrel10 (offset));
1342 }
1343 else if (T == 0)
1344 {
1345 OUTS (outf, "IF !CC JUMP 0x");
1346 OUTS (outf, pcrel10 (offset));
1347 }
1348 else
1349 return 0;
1350
1351 return 2;
1352 }
1353
1354 static int
1355 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1356 {
1357 /* UJUMP
1358 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1359 | 0 | 0 | 1 | 0 |.offset........................................|
1360 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1361 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1362
1363 if (parallel)
1364 return 0;
1365
1366 OUTS (outf, "JUMP.S 0x");
1367 OUTS (outf, pcrel12 (offset));
1368 return 2;
1369 }
1370
1371 static int
1372 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1373 {
1374 /* REGMV
1375 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1376 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1377 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1378 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1379 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1380 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1381 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1382
1383 /* Reserved slots cannot be a src/dst. */
1384 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1385 goto invalid_move;
1386
1387 /* Standard register moves */
1388 if ((gs < 2) || /* Dregs/Pregs as source */
1389 (gd < 2) || /* Dregs/Pregs as dest */
1390 (gs == 4 && src < 4) || /* Accumulators as source */
1391 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1392 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1393 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1394 goto valid_move;
1395
1396 /* dareg = dareg (IMBL) */
1397 if (gs < 4 && gd < 4)
1398 goto valid_move;
1399
1400 /* USP can be src to sysregs, but not dagregs. */
1401 if ((gs == 7 && src == 0) && (gd >= 4))
1402 goto valid_move;
1403
1404 /* USP can move between genregs (only check Accumulators). */
1405 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1406 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1407 goto valid_move;
1408
1409 /* Still here ? Invalid reg pair. */
1410 invalid_move:
1411 return 0;
1412
1413 valid_move:
1414 OUTS (outf, allregs (dst, gd));
1415 OUTS (outf, " = ");
1416 OUTS (outf, allregs (src, gs));
1417 return 2;
1418 }
1419
1420 static int
1421 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1422 {
1423 /* ALU2op
1424 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1425 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1426 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1427 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1428 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1429 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1430
1431 if (opc == 0)
1432 {
1433 OUTS (outf, dregs (dst));
1434 OUTS (outf, " >>>= ");
1435 OUTS (outf, dregs (src));
1436 }
1437 else if (opc == 1)
1438 {
1439 OUTS (outf, dregs (dst));
1440 OUTS (outf, " >>= ");
1441 OUTS (outf, dregs (src));
1442 }
1443 else if (opc == 2)
1444 {
1445 OUTS (outf, dregs (dst));
1446 OUTS (outf, " <<= ");
1447 OUTS (outf, dregs (src));
1448 }
1449 else if (opc == 3)
1450 {
1451 OUTS (outf, dregs (dst));
1452 OUTS (outf, " *= ");
1453 OUTS (outf, dregs (src));
1454 }
1455 else if (opc == 4)
1456 {
1457 OUTS (outf, dregs (dst));
1458 OUTS (outf, " = (");
1459 OUTS (outf, dregs (dst));
1460 OUTS (outf, " + ");
1461 OUTS (outf, dregs (src));
1462 OUTS (outf, ") << 0x1");
1463 }
1464 else if (opc == 5)
1465 {
1466 OUTS (outf, dregs (dst));
1467 OUTS (outf, " = (");
1468 OUTS (outf, dregs (dst));
1469 OUTS (outf, " + ");
1470 OUTS (outf, dregs (src));
1471 OUTS (outf, ") << 0x2");
1472 }
1473 else if (opc == 8)
1474 {
1475 OUTS (outf, "DIVQ (");
1476 OUTS (outf, dregs (dst));
1477 OUTS (outf, ", ");
1478 OUTS (outf, dregs (src));
1479 OUTS (outf, ")");
1480 }
1481 else if (opc == 9)
1482 {
1483 OUTS (outf, "DIVS (");
1484 OUTS (outf, dregs (dst));
1485 OUTS (outf, ", ");
1486 OUTS (outf, dregs (src));
1487 OUTS (outf, ")");
1488 }
1489 else if (opc == 10)
1490 {
1491 OUTS (outf, dregs (dst));
1492 OUTS (outf, " = ");
1493 OUTS (outf, dregs_lo (src));
1494 OUTS (outf, " (X)");
1495 }
1496 else if (opc == 11)
1497 {
1498 OUTS (outf, dregs (dst));
1499 OUTS (outf, " = ");
1500 OUTS (outf, dregs_lo (src));
1501 OUTS (outf, " (Z)");
1502 }
1503 else if (opc == 12)
1504 {
1505 OUTS (outf, dregs (dst));
1506 OUTS (outf, " = ");
1507 OUTS (outf, dregs_byte (src));
1508 OUTS (outf, " (X)");
1509 }
1510 else if (opc == 13)
1511 {
1512 OUTS (outf, dregs (dst));
1513 OUTS (outf, " = ");
1514 OUTS (outf, dregs_byte (src));
1515 OUTS (outf, " (Z)");
1516 }
1517 else if (opc == 14)
1518 {
1519 OUTS (outf, dregs (dst));
1520 OUTS (outf, " = -");
1521 OUTS (outf, dregs (src));
1522 }
1523 else if (opc == 15)
1524 {
1525 OUTS (outf, dregs (dst));
1526 OUTS (outf, " =~ ");
1527 OUTS (outf, dregs (src));
1528 }
1529 else
1530 return 0;
1531
1532 return 2;
1533 }
1534
1535 static int
1536 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1537 {
1538 /* PTR2op
1539 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1540 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1541 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1542 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1543 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1544 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1545
1546 if (opc == 0)
1547 {
1548 OUTS (outf, pregs (dst));
1549 OUTS (outf, " -= ");
1550 OUTS (outf, pregs (src));
1551 }
1552 else if (opc == 1)
1553 {
1554 OUTS (outf, pregs (dst));
1555 OUTS (outf, " = ");
1556 OUTS (outf, pregs (src));
1557 OUTS (outf, " << 0x2");
1558 }
1559 else if (opc == 3)
1560 {
1561 OUTS (outf, pregs (dst));
1562 OUTS (outf, " = ");
1563 OUTS (outf, pregs (src));
1564 OUTS (outf, " >> 0x2");
1565 }
1566 else if (opc == 4)
1567 {
1568 OUTS (outf, pregs (dst));
1569 OUTS (outf, " = ");
1570 OUTS (outf, pregs (src));
1571 OUTS (outf, " >> 0x1");
1572 }
1573 else if (opc == 5)
1574 {
1575 OUTS (outf, pregs (dst));
1576 OUTS (outf, " += ");
1577 OUTS (outf, pregs (src));
1578 OUTS (outf, " (BREV)");
1579 }
1580 else if (opc == 6)
1581 {
1582 OUTS (outf, pregs (dst));
1583 OUTS (outf, " = (");
1584 OUTS (outf, pregs (dst));
1585 OUTS (outf, " + ");
1586 OUTS (outf, pregs (src));
1587 OUTS (outf, ") << 0x1");
1588 }
1589 else if (opc == 7)
1590 {
1591 OUTS (outf, pregs (dst));
1592 OUTS (outf, " = (");
1593 OUTS (outf, pregs (dst));
1594 OUTS (outf, " + ");
1595 OUTS (outf, pregs (src));
1596 OUTS (outf, ") << 0x2");
1597 }
1598 else
1599 return 0;
1600
1601 return 2;
1602 }
1603
1604 static int
1605 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1606 {
1607 /* LOGI2op
1608 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1609 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1610 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1611 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1612 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1613 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1614
1615 if (parallel)
1616 return 0;
1617
1618 if (opc == 0)
1619 {
1620 OUTS (outf, "CC = !BITTST (");
1621 OUTS (outf, dregs (dst));
1622 OUTS (outf, ", ");
1623 OUTS (outf, uimm5 (src));
1624 OUTS (outf, ");\t\t/* bit");
1625 OUTS (outf, imm7d (src));
1626 OUTS (outf, " */");
1627 comment = 1;
1628 }
1629 else if (opc == 1)
1630 {
1631 OUTS (outf, "CC = BITTST (");
1632 OUTS (outf, dregs (dst));
1633 OUTS (outf, ", ");
1634 OUTS (outf, uimm5 (src));
1635 OUTS (outf, ");\t\t/* bit");
1636 OUTS (outf, imm7d (src));
1637 OUTS (outf, " */");
1638 comment = 1;
1639 }
1640 else if (opc == 2)
1641 {
1642 OUTS (outf, "BITSET (");
1643 OUTS (outf, dregs (dst));
1644 OUTS (outf, ", ");
1645 OUTS (outf, uimm5 (src));
1646 OUTS (outf, ");\t\t/* bit");
1647 OUTS (outf, imm7d (src));
1648 OUTS (outf, " */");
1649 comment = 1;
1650 }
1651 else if (opc == 3)
1652 {
1653 OUTS (outf, "BITTGL (");
1654 OUTS (outf, dregs (dst));
1655 OUTS (outf, ", ");
1656 OUTS (outf, uimm5 (src));
1657 OUTS (outf, ");\t\t/* bit");
1658 OUTS (outf, imm7d (src));
1659 OUTS (outf, " */");
1660 comment = 1;
1661 }
1662 else if (opc == 4)
1663 {
1664 OUTS (outf, "BITCLR (");
1665 OUTS (outf, dregs (dst));
1666 OUTS (outf, ", ");
1667 OUTS (outf, uimm5 (src));
1668 OUTS (outf, ");\t\t/* bit");
1669 OUTS (outf, imm7d (src));
1670 OUTS (outf, " */");
1671 comment = 1;
1672 }
1673 else if (opc == 5)
1674 {
1675 OUTS (outf, dregs (dst));
1676 OUTS (outf, " >>>= ");
1677 OUTS (outf, uimm5 (src));
1678 }
1679 else if (opc == 6)
1680 {
1681 OUTS (outf, dregs (dst));
1682 OUTS (outf, " >>= ");
1683 OUTS (outf, uimm5 (src));
1684 }
1685 else if (opc == 7)
1686 {
1687 OUTS (outf, dregs (dst));
1688 OUTS (outf, " <<= ");
1689 OUTS (outf, uimm5 (src));
1690 }
1691 else
1692 return 0;
1693
1694 return 2;
1695 }
1696
1697 static int
1698 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1699 {
1700 /* COMP3op
1701 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1702 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1703 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1704 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1705 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1706 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1707 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1708
1709 if (opc == 5 && src1 == src0)
1710 {
1711 OUTS (outf, pregs (dst));
1712 OUTS (outf, " = ");
1713 OUTS (outf, pregs (src0));
1714 OUTS (outf, " << 0x1");
1715 }
1716 else if (opc == 1)
1717 {
1718 OUTS (outf, dregs (dst));
1719 OUTS (outf, " = ");
1720 OUTS (outf, dregs (src0));
1721 OUTS (outf, " - ");
1722 OUTS (outf, dregs (src1));
1723 }
1724 else if (opc == 2)
1725 {
1726 OUTS (outf, dregs (dst));
1727 OUTS (outf, " = ");
1728 OUTS (outf, dregs (src0));
1729 OUTS (outf, " & ");
1730 OUTS (outf, dregs (src1));
1731 }
1732 else if (opc == 3)
1733 {
1734 OUTS (outf, dregs (dst));
1735 OUTS (outf, " = ");
1736 OUTS (outf, dregs (src0));
1737 OUTS (outf, " | ");
1738 OUTS (outf, dregs (src1));
1739 }
1740 else if (opc == 4)
1741 {
1742 OUTS (outf, dregs (dst));
1743 OUTS (outf, " = ");
1744 OUTS (outf, dregs (src0));
1745 OUTS (outf, " ^ ");
1746 OUTS (outf, dregs (src1));
1747 }
1748 else if (opc == 5)
1749 {
1750 OUTS (outf, pregs (dst));
1751 OUTS (outf, " = ");
1752 OUTS (outf, pregs (src0));
1753 OUTS (outf, " + ");
1754 OUTS (outf, pregs (src1));
1755 }
1756 else if (opc == 6)
1757 {
1758 OUTS (outf, pregs (dst));
1759 OUTS (outf, " = ");
1760 OUTS (outf, pregs (src0));
1761 OUTS (outf, " + (");
1762 OUTS (outf, pregs (src1));
1763 OUTS (outf, " << 0x1)");
1764 }
1765 else if (opc == 7)
1766 {
1767 OUTS (outf, pregs (dst));
1768 OUTS (outf, " = ");
1769 OUTS (outf, pregs (src0));
1770 OUTS (outf, " + (");
1771 OUTS (outf, pregs (src1));
1772 OUTS (outf, " << 0x2)");
1773 }
1774 else if (opc == 0)
1775 {
1776 OUTS (outf, dregs (dst));
1777 OUTS (outf, " = ");
1778 OUTS (outf, dregs (src0));
1779 OUTS (outf, " + ");
1780 OUTS (outf, dregs (src1));
1781 }
1782 else
1783 return 0;
1784
1785 return 2;
1786 }
1787
1788 static int
1789 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1790 {
1791 /* COMPI2opD
1792 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1793 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1794 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1795 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1796 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1797 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1798
1799 bu32 *pval = get_allreg (0, dst);
1800
1801 if (parallel)
1802 return 0;
1803
1804 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1805 to combine them, so it prints out the right values.
1806 Here we keep track of the registers. */
1807 if (op == 0)
1808 {
1809 *pval = imm7_val (src);
1810 if (src & 0x40)
1811 *pval |= 0xFFFFFF80;
1812 else
1813 *pval &= 0x7F;
1814 }
1815
1816 if (op == 0)
1817 {
1818 OUTS (outf, dregs (dst));
1819 OUTS (outf, " = ");
1820 OUTS (outf, imm7 (src));
1821 OUTS (outf, " (X);\t\t/*\t\t");
1822 OUTS (outf, dregs (dst));
1823 OUTS (outf, "=");
1824 OUTS (outf, uimm32 (*pval));
1825 OUTS (outf, "(");
1826 OUTS (outf, imm32 (*pval));
1827 OUTS (outf, ") */");
1828 comment = 1;
1829 }
1830 else if (op == 1)
1831 {
1832 OUTS (outf, dregs (dst));
1833 OUTS (outf, " += ");
1834 OUTS (outf, imm7 (src));
1835 OUTS (outf, ";\t\t/* (");
1836 OUTS (outf, imm7d (src));
1837 OUTS (outf, ") */");
1838 comment = 1;
1839 }
1840 else
1841 return 0;
1842
1843 return 2;
1844 }
1845
1846 static int
1847 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1848 {
1849 /* COMPI2opP
1850 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1851 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1852 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1853 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1854 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1855 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1856
1857 bu32 *pval = get_allreg (1, dst);
1858
1859 if (parallel)
1860 return 0;
1861
1862 if (op == 0)
1863 {
1864 *pval = imm7_val (src);
1865 if (src & 0x40)
1866 *pval |= 0xFFFFFF80;
1867 else
1868 *pval &= 0x7F;
1869 }
1870
1871 if (op == 0)
1872 {
1873 OUTS (outf, pregs (dst));
1874 OUTS (outf, " = ");
1875 OUTS (outf, imm7 (src));
1876 OUTS (outf, " (X);\t\t/*\t\t");
1877 OUTS (outf, pregs (dst));
1878 OUTS (outf, "=");
1879 OUTS (outf, uimm32 (*pval));
1880 OUTS (outf, "(");
1881 OUTS (outf, imm32 (*pval));
1882 OUTS (outf, ") */");
1883 comment = 1;
1884 }
1885 else if (op == 1)
1886 {
1887 OUTS (outf, pregs (dst));
1888 OUTS (outf, " += ");
1889 OUTS (outf, imm7 (src));
1890 OUTS (outf, ";\t\t/* (");
1891 OUTS (outf, imm7d (src));
1892 OUTS (outf, ") */");
1893 comment = 1;
1894 }
1895 else
1896 return 0;
1897
1898 return 2;
1899 }
1900
1901 static int
1902 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1903 {
1904 /* LDSTpmod
1905 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1906 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1907 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1908 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1909 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1910 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1911 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1912 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1913
1914 if (aop == 1 && W == 0 && idx == ptr)
1915 {
1916 OUTS (outf, dregs_lo (reg));
1917 OUTS (outf, " = W[");
1918 OUTS (outf, pregs (ptr));
1919 OUTS (outf, "]");
1920 }
1921 else if (aop == 2 && W == 0 && idx == ptr)
1922 {
1923 OUTS (outf, dregs_hi (reg));
1924 OUTS (outf, " = W[");
1925 OUTS (outf, pregs (ptr));
1926 OUTS (outf, "]");
1927 }
1928 else if (aop == 1 && W == 1 && idx == ptr)
1929 {
1930 OUTS (outf, "W[");
1931 OUTS (outf, pregs (ptr));
1932 OUTS (outf, "] = ");
1933 OUTS (outf, dregs_lo (reg));
1934 }
1935 else if (aop == 2 && W == 1 && idx == ptr)
1936 {
1937 OUTS (outf, "W[");
1938 OUTS (outf, pregs (ptr));
1939 OUTS (outf, "] = ");
1940 OUTS (outf, dregs_hi (reg));
1941 }
1942 else if (aop == 0 && W == 0)
1943 {
1944 OUTS (outf, dregs (reg));
1945 OUTS (outf, " = [");
1946 OUTS (outf, pregs (ptr));
1947 OUTS (outf, " ++ ");
1948 OUTS (outf, pregs (idx));
1949 OUTS (outf, "]");
1950 }
1951 else if (aop == 1 && W == 0)
1952 {
1953 OUTS (outf, dregs_lo (reg));
1954 OUTS (outf, " = W[");
1955 OUTS (outf, pregs (ptr));
1956 OUTS (outf, " ++ ");
1957 OUTS (outf, pregs (idx));
1958 OUTS (outf, "]");
1959 }
1960 else if (aop == 2 && W == 0)
1961 {
1962 OUTS (outf, dregs_hi (reg));
1963 OUTS (outf, " = W[");
1964 OUTS (outf, pregs (ptr));
1965 OUTS (outf, " ++ ");
1966 OUTS (outf, pregs (idx));
1967 OUTS (outf, "]");
1968 }
1969 else if (aop == 3 && W == 0)
1970 {
1971 OUTS (outf, dregs (reg));
1972 OUTS (outf, " = W[");
1973 OUTS (outf, pregs (ptr));
1974 OUTS (outf, " ++ ");
1975 OUTS (outf, pregs (idx));
1976 OUTS (outf, "] (Z)");
1977 }
1978 else if (aop == 3 && W == 1)
1979 {
1980 OUTS (outf, dregs (reg));
1981 OUTS (outf, " = W[");
1982 OUTS (outf, pregs (ptr));
1983 OUTS (outf, " ++ ");
1984 OUTS (outf, pregs (idx));
1985 OUTS (outf, "] (X)");
1986 }
1987 else if (aop == 0 && W == 1)
1988 {
1989 OUTS (outf, "[");
1990 OUTS (outf, pregs (ptr));
1991 OUTS (outf, " ++ ");
1992 OUTS (outf, pregs (idx));
1993 OUTS (outf, "] = ");
1994 OUTS (outf, dregs (reg));
1995 }
1996 else if (aop == 1 && W == 1)
1997 {
1998 OUTS (outf, "W[");
1999 OUTS (outf, pregs (ptr));
2000 OUTS (outf, " ++ ");
2001 OUTS (outf, pregs (idx));
2002 OUTS (outf, "] = ");
2003 OUTS (outf, dregs_lo (reg));
2004 }
2005 else if (aop == 2 && W == 1)
2006 {
2007 OUTS (outf, "W[");
2008 OUTS (outf, pregs (ptr));
2009 OUTS (outf, " ++ ");
2010 OUTS (outf, pregs (idx));
2011 OUTS (outf, "] = ");
2012 OUTS (outf, dregs_hi (reg));
2013 }
2014 else
2015 return 0;
2016
2017 return 2;
2018 }
2019
2020 static int
2021 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
2022 {
2023 /* dagMODim
2024 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2025 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2026 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2027 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
2028 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
2029 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
2030 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2031
2032 if (op == 0 && br == 1)
2033 {
2034 OUTS (outf, iregs (i));
2035 OUTS (outf, " += ");
2036 OUTS (outf, mregs (m));
2037 OUTS (outf, " (BREV)");
2038 }
2039 else if (op == 0)
2040 {
2041 OUTS (outf, iregs (i));
2042 OUTS (outf, " += ");
2043 OUTS (outf, mregs (m));
2044 }
2045 else if (op == 1 && br == 0)
2046 {
2047 OUTS (outf, iregs (i));
2048 OUTS (outf, " -= ");
2049 OUTS (outf, mregs (m));
2050 }
2051 else
2052 return 0;
2053
2054 return 2;
2055 }
2056
2057 static int
2058 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2059 {
2060 /* dagMODik
2061 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2062 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2063 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2064 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2065 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2066
2067 if (op == 0)
2068 {
2069 OUTS (outf, iregs (i));
2070 OUTS (outf, " += 0x2");
2071 }
2072 else if (op == 1)
2073 {
2074 OUTS (outf, iregs (i));
2075 OUTS (outf, " -= 0x2");
2076 }
2077 else if (op == 2)
2078 {
2079 OUTS (outf, iregs (i));
2080 OUTS (outf, " += 0x4");
2081 }
2082 else if (op == 3)
2083 {
2084 OUTS (outf, iregs (i));
2085 OUTS (outf, " -= 0x4");
2086 }
2087 else
2088 return 0;
2089
2090 if (! parallel)
2091 {
2092 OUTS (outf, ";\t\t/* ( ");
2093 if (op == 0 || op == 1)
2094 OUTS (outf, "2");
2095 else if (op == 2 || op == 3)
2096 OUTS (outf, "4");
2097 OUTS (outf, ") */");
2098 comment = 1;
2099 }
2100
2101 return 2;
2102 }
2103
2104 static int
2105 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2106 {
2107 /* dspLDST
2108 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2109 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2110 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2111 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2112 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2113 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2114 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2115 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2116
2117 if (aop == 0 && W == 0 && m == 0)
2118 {
2119 OUTS (outf, dregs (reg));
2120 OUTS (outf, " = [");
2121 OUTS (outf, iregs (i));
2122 OUTS (outf, "++]");
2123 }
2124 else if (aop == 0 && W == 0 && m == 1)
2125 {
2126 OUTS (outf, dregs_lo (reg));
2127 OUTS (outf, " = W[");
2128 OUTS (outf, iregs (i));
2129 OUTS (outf, "++]");
2130 }
2131 else if (aop == 0 && W == 0 && m == 2)
2132 {
2133 OUTS (outf, dregs_hi (reg));
2134 OUTS (outf, " = W[");
2135 OUTS (outf, iregs (i));
2136 OUTS (outf, "++]");
2137 }
2138 else if (aop == 1 && W == 0 && m == 0)
2139 {
2140 OUTS (outf, dregs (reg));
2141 OUTS (outf, " = [");
2142 OUTS (outf, iregs (i));
2143 OUTS (outf, "--]");
2144 }
2145 else if (aop == 1 && W == 0 && m == 1)
2146 {
2147 OUTS (outf, dregs_lo (reg));
2148 OUTS (outf, " = W[");
2149 OUTS (outf, iregs (i));
2150 OUTS (outf, "--]");
2151 }
2152 else if (aop == 1 && W == 0 && m == 2)
2153 {
2154 OUTS (outf, dregs_hi (reg));
2155 OUTS (outf, " = W[");
2156 OUTS (outf, iregs (i));
2157 OUTS (outf, "--]");
2158 }
2159 else if (aop == 2 && W == 0 && m == 0)
2160 {
2161 OUTS (outf, dregs (reg));
2162 OUTS (outf, " = [");
2163 OUTS (outf, iregs (i));
2164 OUTS (outf, "]");
2165 }
2166 else if (aop == 2 && W == 0 && m == 1)
2167 {
2168 OUTS (outf, dregs_lo (reg));
2169 OUTS (outf, " = W[");
2170 OUTS (outf, iregs (i));
2171 OUTS (outf, "]");
2172 }
2173 else if (aop == 2 && W == 0 && m == 2)
2174 {
2175 OUTS (outf, dregs_hi (reg));
2176 OUTS (outf, " = W[");
2177 OUTS (outf, iregs (i));
2178 OUTS (outf, "]");
2179 }
2180 else if (aop == 0 && W == 1 && m == 0)
2181 {
2182 OUTS (outf, "[");
2183 OUTS (outf, iregs (i));
2184 OUTS (outf, "++] = ");
2185 OUTS (outf, dregs (reg));
2186 }
2187 else if (aop == 0 && W == 1 && m == 1)
2188 {
2189 OUTS (outf, "W[");
2190 OUTS (outf, iregs (i));
2191 OUTS (outf, "++] = ");
2192 OUTS (outf, dregs_lo (reg));
2193 }
2194 else if (aop == 0 && W == 1 && m == 2)
2195 {
2196 OUTS (outf, "W[");
2197 OUTS (outf, iregs (i));
2198 OUTS (outf, "++] = ");
2199 OUTS (outf, dregs_hi (reg));
2200 }
2201 else if (aop == 1 && W == 1 && m == 0)
2202 {
2203 OUTS (outf, "[");
2204 OUTS (outf, iregs (i));
2205 OUTS (outf, "--] = ");
2206 OUTS (outf, dregs (reg));
2207 }
2208 else if (aop == 1 && W == 1 && m == 1)
2209 {
2210 OUTS (outf, "W[");
2211 OUTS (outf, iregs (i));
2212 OUTS (outf, "--] = ");
2213 OUTS (outf, dregs_lo (reg));
2214 }
2215 else if (aop == 1 && W == 1 && m == 2)
2216 {
2217 OUTS (outf, "W[");
2218 OUTS (outf, iregs (i));
2219 OUTS (outf, "--] = ");
2220 OUTS (outf, dregs_hi (reg));
2221 }
2222 else if (aop == 2 && W == 1 && m == 0)
2223 {
2224 OUTS (outf, "[");
2225 OUTS (outf, iregs (i));
2226 OUTS (outf, "] = ");
2227 OUTS (outf, dregs (reg));
2228 }
2229 else if (aop == 2 && W == 1 && m == 1)
2230 {
2231 OUTS (outf, "W[");
2232 OUTS (outf, iregs (i));
2233 OUTS (outf, "] = ");
2234 OUTS (outf, dregs_lo (reg));
2235 }
2236 else if (aop == 2 && W == 1 && m == 2)
2237 {
2238 OUTS (outf, "W[");
2239 OUTS (outf, iregs (i));
2240 OUTS (outf, "] = ");
2241 OUTS (outf, dregs_hi (reg));
2242 }
2243 else if (aop == 3 && W == 0)
2244 {
2245 OUTS (outf, dregs (reg));
2246 OUTS (outf, " = [");
2247 OUTS (outf, iregs (i));
2248 OUTS (outf, " ++ ");
2249 OUTS (outf, mregs (m));
2250 OUTS (outf, "]");
2251 }
2252 else if (aop == 3 && W == 1)
2253 {
2254 OUTS (outf, "[");
2255 OUTS (outf, iregs (i));
2256 OUTS (outf, " ++ ");
2257 OUTS (outf, mregs (m));
2258 OUTS (outf, "] = ");
2259 OUTS (outf, dregs (reg));
2260 }
2261 else
2262 return 0;
2263
2264 return 2;
2265 }
2266
2267 static int
2268 decode_LDST_0 (TIword iw0, disassemble_info *outf)
2269 {
2270 /* LDST
2271 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2272 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2273 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2274 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2275 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2276 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2277 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2278 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2279 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2280
2281 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2282 {
2283 OUTS (outf, dregs (reg));
2284 OUTS (outf, " = [");
2285 OUTS (outf, pregs (ptr));
2286 OUTS (outf, "++]");
2287 }
2288 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2289 {
2290 OUTS (outf, pregs (reg));
2291 OUTS (outf, " = [");
2292 OUTS (outf, pregs (ptr));
2293 OUTS (outf, "++]");
2294 }
2295 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2296 {
2297 OUTS (outf, dregs (reg));
2298 OUTS (outf, " = W[");
2299 OUTS (outf, pregs (ptr));
2300 OUTS (outf, "++] (Z)");
2301 }
2302 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2303 {
2304 OUTS (outf, dregs (reg));
2305 OUTS (outf, " = W[");
2306 OUTS (outf, pregs (ptr));
2307 OUTS (outf, "++] (X)");
2308 }
2309 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2310 {
2311 OUTS (outf, dregs (reg));
2312 OUTS (outf, " = B[");
2313 OUTS (outf, pregs (ptr));
2314 OUTS (outf, "++] (Z)");
2315 }
2316 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2317 {
2318 OUTS (outf, dregs (reg));
2319 OUTS (outf, " = B[");
2320 OUTS (outf, pregs (ptr));
2321 OUTS (outf, "++] (X)");
2322 }
2323 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2324 {
2325 OUTS (outf, dregs (reg));
2326 OUTS (outf, " = [");
2327 OUTS (outf, pregs (ptr));
2328 OUTS (outf, "--]");
2329 }
2330 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2331 {
2332 OUTS (outf, pregs (reg));
2333 OUTS (outf, " = [");
2334 OUTS (outf, pregs (ptr));
2335 OUTS (outf, "--]");
2336 }
2337 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2338 {
2339 OUTS (outf, dregs (reg));
2340 OUTS (outf, " = W[");
2341 OUTS (outf, pregs (ptr));
2342 OUTS (outf, "--] (Z)");
2343 }
2344 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2345 {
2346 OUTS (outf, dregs (reg));
2347 OUTS (outf, " = W[");
2348 OUTS (outf, pregs (ptr));
2349 OUTS (outf, "--] (X)");
2350 }
2351 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2352 {
2353 OUTS (outf, dregs (reg));
2354 OUTS (outf, " = B[");
2355 OUTS (outf, pregs (ptr));
2356 OUTS (outf, "--] (Z)");
2357 }
2358 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2359 {
2360 OUTS (outf, dregs (reg));
2361 OUTS (outf, " = B[");
2362 OUTS (outf, pregs (ptr));
2363 OUTS (outf, "--] (X)");
2364 }
2365 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2366 {
2367 OUTS (outf, dregs (reg));
2368 OUTS (outf, " = [");
2369 OUTS (outf, pregs (ptr));
2370 OUTS (outf, "]");
2371 }
2372 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2373 {
2374 OUTS (outf, pregs (reg));
2375 OUTS (outf, " = [");
2376 OUTS (outf, pregs (ptr));
2377 OUTS (outf, "]");
2378 }
2379 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2380 {
2381 OUTS (outf, dregs (reg));
2382 OUTS (outf, " = W[");
2383 OUTS (outf, pregs (ptr));
2384 OUTS (outf, "] (Z)");
2385 }
2386 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2387 {
2388 OUTS (outf, dregs (reg));
2389 OUTS (outf, " = W[");
2390 OUTS (outf, pregs (ptr));
2391 OUTS (outf, "] (X)");
2392 }
2393 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2394 {
2395 OUTS (outf, dregs (reg));
2396 OUTS (outf, " = B[");
2397 OUTS (outf, pregs (ptr));
2398 OUTS (outf, "] (Z)");
2399 }
2400 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2401 {
2402 OUTS (outf, dregs (reg));
2403 OUTS (outf, " = B[");
2404 OUTS (outf, pregs (ptr));
2405 OUTS (outf, "] (X)");
2406 }
2407 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2408 {
2409 OUTS (outf, "[");
2410 OUTS (outf, pregs (ptr));
2411 OUTS (outf, "++] = ");
2412 OUTS (outf, dregs (reg));
2413 }
2414 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2415 {
2416 OUTS (outf, "[");
2417 OUTS (outf, pregs (ptr));
2418 OUTS (outf, "++] = ");
2419 OUTS (outf, pregs (reg));
2420 }
2421 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2422 {
2423 OUTS (outf, "W[");
2424 OUTS (outf, pregs (ptr));
2425 OUTS (outf, "++] = ");
2426 OUTS (outf, dregs (reg));
2427 }
2428 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2429 {
2430 OUTS (outf, "B[");
2431 OUTS (outf, pregs (ptr));
2432 OUTS (outf, "++] = ");
2433 OUTS (outf, dregs (reg));
2434 }
2435 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2436 {
2437 OUTS (outf, "[");
2438 OUTS (outf, pregs (ptr));
2439 OUTS (outf, "--] = ");
2440 OUTS (outf, dregs (reg));
2441 }
2442 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2443 {
2444 OUTS (outf, "[");
2445 OUTS (outf, pregs (ptr));
2446 OUTS (outf, "--] = ");
2447 OUTS (outf, pregs (reg));
2448 }
2449 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2450 {
2451 OUTS (outf, "W[");
2452 OUTS (outf, pregs (ptr));
2453 OUTS (outf, "--] = ");
2454 OUTS (outf, dregs (reg));
2455 }
2456 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2457 {
2458 OUTS (outf, "B[");
2459 OUTS (outf, pregs (ptr));
2460 OUTS (outf, "--] = ");
2461 OUTS (outf, dregs (reg));
2462 }
2463 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2464 {
2465 OUTS (outf, "[");
2466 OUTS (outf, pregs (ptr));
2467 OUTS (outf, "] = ");
2468 OUTS (outf, dregs (reg));
2469 }
2470 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2471 {
2472 OUTS (outf, "[");
2473 OUTS (outf, pregs (ptr));
2474 OUTS (outf, "] = ");
2475 OUTS (outf, pregs (reg));
2476 }
2477 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2478 {
2479 OUTS (outf, "W[");
2480 OUTS (outf, pregs (ptr));
2481 OUTS (outf, "] = ");
2482 OUTS (outf, dregs (reg));
2483 }
2484 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2485 {
2486 OUTS (outf, "B[");
2487 OUTS (outf, pregs (ptr));
2488 OUTS (outf, "] = ");
2489 OUTS (outf, dregs (reg));
2490 }
2491 else
2492 return 0;
2493
2494 return 2;
2495 }
2496
2497 static int
2498 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2499 {
2500 /* LDSTiiFP
2501 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2502 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2503 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2504 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2505 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2506 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2507
2508 if (W == 0)
2509 {
2510 OUTS (outf, dpregs (reg));
2511 OUTS (outf, " = [FP ");
2512 OUTS (outf, negimm5s4 (offset));
2513 OUTS (outf, "]");
2514 }
2515 else if (W == 1)
2516 {
2517 OUTS (outf, "[FP ");
2518 OUTS (outf, negimm5s4 (offset));
2519 OUTS (outf, "] = ");
2520 OUTS (outf, dpregs (reg));
2521 }
2522 else
2523 return 0;
2524
2525 return 2;
2526 }
2527
2528 static int
2529 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2530 {
2531 /* LDSTii
2532 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2533 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2534 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2535 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2536 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2537 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2538 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2539 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2540
2541 if (W == 0 && op == 0)
2542 {
2543 OUTS (outf, dregs (reg));
2544 OUTS (outf, " = [");
2545 OUTS (outf, pregs (ptr));
2546 OUTS (outf, " + ");
2547 OUTS (outf, uimm4s4 (offset));
2548 OUTS (outf, "]");
2549 }
2550 else if (W == 0 && op == 1)
2551 {
2552 OUTS (outf, dregs (reg));
2553 OUTS (outf, " = W[");
2554 OUTS (outf, pregs (ptr));
2555 OUTS (outf, " + ");
2556 OUTS (outf, uimm4s2 (offset));
2557 OUTS (outf, "] (Z)");
2558 }
2559 else if (W == 0 && op == 2)
2560 {
2561 OUTS (outf, dregs (reg));
2562 OUTS (outf, " = W[");
2563 OUTS (outf, pregs (ptr));
2564 OUTS (outf, " + ");
2565 OUTS (outf, uimm4s2 (offset));
2566 OUTS (outf, "] (X)");
2567 }
2568 else if (W == 0 && op == 3)
2569 {
2570 OUTS (outf, pregs (reg));
2571 OUTS (outf, " = [");
2572 OUTS (outf, pregs (ptr));
2573 OUTS (outf, " + ");
2574 OUTS (outf, uimm4s4 (offset));
2575 OUTS (outf, "]");
2576 }
2577 else if (W == 1 && op == 0)
2578 {
2579 OUTS (outf, "[");
2580 OUTS (outf, pregs (ptr));
2581 OUTS (outf, " + ");
2582 OUTS (outf, uimm4s4 (offset));
2583 OUTS (outf, "] = ");
2584 OUTS (outf, dregs (reg));
2585 }
2586 else if (W == 1 && op == 1)
2587 {
2588 OUTS (outf, "W[");
2589 OUTS (outf, pregs (ptr));
2590 OUTS (outf, " + ");
2591 OUTS (outf, uimm4s2 (offset));
2592 OUTS (outf, "] = ");
2593 OUTS (outf, dregs (reg));
2594 }
2595 else if (W == 1 && op == 3)
2596 {
2597 OUTS (outf, "[");
2598 OUTS (outf, pregs (ptr));
2599 OUTS (outf, " + ");
2600 OUTS (outf, uimm4s4 (offset));
2601 OUTS (outf, "] = ");
2602 OUTS (outf, pregs (reg));
2603 }
2604 else
2605 return 0;
2606
2607 return 2;
2608 }
2609
2610 static int
2611 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2612 {
2613 /* LoopSetup
2614 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2615 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2616 |.reg...........| - | - |.eoffset...............................|
2617 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2618 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2619 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2620 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2621 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2622 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2623
2624 if (parallel)
2625 return 0;
2626
2627 if (reg > 7)
2628 return 0;
2629
2630 if (rop == 0)
2631 {
2632 OUTS (outf, "LSETUP");
2633 OUTS (outf, "(0x");
2634 OUTS (outf, pcrel4 (soffset));
2635 OUTS (outf, ", 0x");
2636 OUTS (outf, lppcrel10 (eoffset));
2637 OUTS (outf, ") ");
2638 OUTS (outf, counters (c));
2639 }
2640 else if (rop == 1)
2641 {
2642 OUTS (outf, "LSETUP");
2643 OUTS (outf, "(0x");
2644 OUTS (outf, pcrel4 (soffset));
2645 OUTS (outf, ", 0x");
2646 OUTS (outf, lppcrel10 (eoffset));
2647 OUTS (outf, ") ");
2648 OUTS (outf, counters (c));
2649 OUTS (outf, " = ");
2650 OUTS (outf, pregs (reg));
2651 }
2652 else if (rop == 3)
2653 {
2654 OUTS (outf, "LSETUP");
2655 OUTS (outf, "(0x");
2656 OUTS (outf, pcrel4 (soffset));
2657 OUTS (outf, ", 0x");
2658 OUTS (outf, lppcrel10 (eoffset));
2659 OUTS (outf, ") ");
2660 OUTS (outf, counters (c));
2661 OUTS (outf, " = ");
2662 OUTS (outf, pregs (reg));
2663 OUTS (outf, " >> 0x1");
2664 }
2665 else
2666 return 0;
2667
2668 return 4;
2669 }
2670
2671 static int
2672 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2673 {
2674 /* LDIMMhalf
2675 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2676 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2677 |.hword.........................................................|
2678 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2679 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2680 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2681 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2682 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2683 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2684 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2685
2686 bu32 *pval = get_allreg (grp, reg);
2687
2688 if (parallel)
2689 return 0;
2690
2691 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2692 to combine them, so it prints out the right values.
2693 Here we keep track of the registers. */
2694 if (H == 0 && S == 1 && Z == 0)
2695 {
2696 /* regs = imm16 (x) */
2697 *pval = imm16_val (hword);
2698 if (hword & 0x8000)
2699 *pval |= 0xFFFF0000;
2700 else
2701 *pval &= 0xFFFF;
2702 }
2703 else if (H == 0 && S == 0 && Z == 1)
2704 {
2705 /* regs = luimm16 (Z) */
2706 *pval = luimm16_val (hword);
2707 *pval &= 0xFFFF;
2708 }
2709 else if (H == 0 && S == 0 && Z == 0)
2710 {
2711 /* regs_lo = luimm16 */
2712 *pval &= 0xFFFF0000;
2713 *pval |= luimm16_val (hword);
2714 }
2715 else if (H == 1 && S == 0 && Z == 0)
2716 {
2717 /* regs_hi = huimm16 */
2718 *pval &= 0xFFFF;
2719 *pval |= luimm16_val (hword) << 16;
2720 }
2721
2722 /* Here we do the disassembly */
2723 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2724 {
2725 OUTS (outf, dregs_lo (reg));
2726 OUTS (outf, " = ");
2727 OUTS (outf, uimm16 (hword));
2728 }
2729 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2730 {
2731 OUTS (outf, dregs_hi (reg));
2732 OUTS (outf, " = ");
2733 OUTS (outf, uimm16 (hword));
2734 }
2735 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2736 {
2737 OUTS (outf, dregs (reg));
2738 OUTS (outf, " = ");
2739 OUTS (outf, imm16 (hword));
2740 OUTS (outf, " (X)");
2741 }
2742 else if (H == 0 && S == 1 && Z == 0)
2743 {
2744 OUTS (outf, regs (reg, grp));
2745 OUTS (outf, " = ");
2746 OUTS (outf, imm16 (hword));
2747 OUTS (outf, " (X)");
2748 }
2749 else if (H == 0 && S == 0 && Z == 1)
2750 {
2751 OUTS (outf, regs (reg, grp));
2752 OUTS (outf, " = ");
2753 OUTS (outf, uimm16 (hword));
2754 OUTS (outf, " (Z)");
2755 }
2756 else if (H == 0 && S == 0 && Z == 0)
2757 {
2758 OUTS (outf, regs_lo (reg, grp));
2759 OUTS (outf, " = ");
2760 OUTS (outf, uimm16 (hword));
2761 }
2762 else if (H == 1 && S == 0 && Z == 0)
2763 {
2764 OUTS (outf, regs_hi (reg, grp));
2765 OUTS (outf, " = ");
2766 OUTS (outf, uimm16 (hword));
2767 }
2768 else
2769 return 0;
2770
2771 /* And we print out the 32-bit value if it is a pointer. */
2772 if (S == 0 && Z == 0)
2773 {
2774 OUTS (outf, ";\t\t/* (");
2775 OUTS (outf, imm16d (hword));
2776 OUTS (outf, ")\t");
2777
2778 /* If it is an MMR, don't print the symbol. */
2779 if (*pval < 0xFFC00000 && grp == 1)
2780 {
2781 OUTS (outf, regs (reg, grp));
2782 OUTS (outf, "=0x");
2783 OUTS (outf, huimm32e (*pval));
2784 }
2785 else
2786 {
2787 OUTS (outf, regs (reg, grp));
2788 OUTS (outf, "=0x");
2789 OUTS (outf, huimm32e (*pval));
2790 OUTS (outf, "(");
2791 OUTS (outf, imm32 (*pval));
2792 OUTS (outf, ")");
2793 }
2794
2795 OUTS (outf, " */");
2796 comment = 1;
2797 }
2798 if (S == 1 || Z == 1)
2799 {
2800 OUTS (outf, ";\t\t/*\t\t");
2801 OUTS (outf, regs (reg, grp));
2802 OUTS (outf, "=0x");
2803 OUTS (outf, huimm32e (*pval));
2804 OUTS (outf, "(");
2805 OUTS (outf, imm32 (*pval));
2806 OUTS (outf, ") */");
2807 comment = 1;
2808 }
2809 return 4;
2810 }
2811
2812 static int
2813 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2814 {
2815 /* CALLa
2816 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2817 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2818 |.lsw...........................................................|
2819 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2820 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2821 int lsw = ((iw1 >> 0) & 0xffff);
2822 int msw = ((iw0 >> 0) & 0xff);
2823
2824 if (parallel)
2825 return 0;
2826
2827 if (S == 1)
2828 OUTS (outf, "CALL 0x");
2829 else if (S == 0)
2830 OUTS (outf, "JUMP.L 0x");
2831 else
2832 return 0;
2833
2834 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2835 return 4;
2836 }
2837
2838 static int
2839 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2840 {
2841 /* LDSTidxI
2842 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2843 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2844 |.offset........................................................|
2845 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2846 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2847 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2848 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2849 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2850 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2851 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2852
2853 if (W == 0 && sz == 0 && Z == 0)
2854 {
2855 OUTS (outf, dregs (reg));
2856 OUTS (outf, " = [");
2857 OUTS (outf, pregs (ptr));
2858 OUTS (outf, " + ");
2859 OUTS (outf, imm16s4 (offset));
2860 OUTS (outf, "]");
2861 }
2862 else if (W == 0 && sz == 0 && Z == 1)
2863 {
2864 OUTS (outf, pregs (reg));
2865 OUTS (outf, " = [");
2866 OUTS (outf, pregs (ptr));
2867 OUTS (outf, " + ");
2868 OUTS (outf, imm16s4 (offset));
2869 OUTS (outf, "]");
2870 }
2871 else if (W == 0 && sz == 1 && Z == 0)
2872 {
2873 OUTS (outf, dregs (reg));
2874 OUTS (outf, " = W[");
2875 OUTS (outf, pregs (ptr));
2876 OUTS (outf, " + ");
2877 OUTS (outf, imm16s2 (offset));
2878 OUTS (outf, "] (Z)");
2879 }
2880 else if (W == 0 && sz == 1 && Z == 1)
2881 {
2882 OUTS (outf, dregs (reg));
2883 OUTS (outf, " = W[");
2884 OUTS (outf, pregs (ptr));
2885 OUTS (outf, " + ");
2886 OUTS (outf, imm16s2 (offset));
2887 OUTS (outf, "] (X)");
2888 }
2889 else if (W == 0 && sz == 2 && Z == 0)
2890 {
2891 OUTS (outf, dregs (reg));
2892 OUTS (outf, " = B[");
2893 OUTS (outf, pregs (ptr));
2894 OUTS (outf, " + ");
2895 OUTS (outf, imm16 (offset));
2896 OUTS (outf, "] (Z)");
2897 }
2898 else if (W == 0 && sz == 2 && Z == 1)
2899 {
2900 OUTS (outf, dregs (reg));
2901 OUTS (outf, " = B[");
2902 OUTS (outf, pregs (ptr));
2903 OUTS (outf, " + ");
2904 OUTS (outf, imm16 (offset));
2905 OUTS (outf, "] (X)");
2906 }
2907 else if (W == 1 && sz == 0 && Z == 0)
2908 {
2909 OUTS (outf, "[");
2910 OUTS (outf, pregs (ptr));
2911 OUTS (outf, " + ");
2912 OUTS (outf, imm16s4 (offset));
2913 OUTS (outf, "] = ");
2914 OUTS (outf, dregs (reg));
2915 }
2916 else if (W == 1 && sz == 0 && Z == 1)
2917 {
2918 OUTS (outf, "[");
2919 OUTS (outf, pregs (ptr));
2920 OUTS (outf, " + ");
2921 OUTS (outf, imm16s4 (offset));
2922 OUTS (outf, "] = ");
2923 OUTS (outf, pregs (reg));
2924 }
2925 else if (W == 1 && sz == 1 && Z == 0)
2926 {
2927 OUTS (outf, "W[");
2928 OUTS (outf, pregs (ptr));
2929 OUTS (outf, " + ");
2930 OUTS (outf, imm16s2 (offset));
2931 OUTS (outf, "] = ");
2932 OUTS (outf, dregs (reg));
2933 }
2934 else if (W == 1 && sz == 2 && Z == 0)
2935 {
2936 OUTS (outf, "B[");
2937 OUTS (outf, pregs (ptr));
2938 OUTS (outf, " + ");
2939 OUTS (outf, imm16 (offset));
2940 OUTS (outf, "] = ");
2941 OUTS (outf, dregs (reg));
2942 }
2943 else
2944 return 0;
2945
2946 return 4;
2947 }
2948
2949 static int
2950 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2951 {
2952 /* linkage
2953 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2954 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2955 |.framesize.....................................................|
2956 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2957 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2958 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2959
2960 if (parallel)
2961 return 0;
2962
2963 if (R == 0)
2964 {
2965 OUTS (outf, "LINK ");
2966 OUTS (outf, uimm16s4 (framesize));
2967 OUTS (outf, ";\t\t/* (");
2968 OUTS (outf, uimm16s4d (framesize));
2969 OUTS (outf, ") */");
2970 comment = 1;
2971 }
2972 else if (R == 1)
2973 OUTS (outf, "UNLINK");
2974 else
2975 return 0;
2976
2977 return 4;
2978 }
2979
2980 static int
2981 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2982 {
2983 /* dsp32mac
2984 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2985 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2986 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2987 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2988 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2989 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2990 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2991 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2992 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2993 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2994 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2995 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2996 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2997 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2998 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2999 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
3000 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3001 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3002
3003 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
3004 return 0;
3005
3006 if (op1 == 3 && MM)
3007 return 0;
3008
3009 if ((w1 || w0) && mmod == M_W32)
3010 return 0;
3011
3012 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
3013 return 0;
3014
3015 if (w1 == 1 || op1 != 3)
3016 {
3017 if (w1)
3018 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3019
3020 if (op1 == 3)
3021 OUTS (outf, " = A1");
3022 else
3023 {
3024 if (w1)
3025 OUTS (outf, " = (");
3026 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
3027 if (w1)
3028 OUTS (outf, ")");
3029 }
3030
3031 if (w0 == 1 || op0 != 3)
3032 {
3033 if (MM)
3034 OUTS (outf, " (M)");
3035 MM = 0;
3036 OUTS (outf, ", ");
3037 }
3038 }
3039
3040 if (w0 == 1 || op0 != 3)
3041 {
3042 if (w0)
3043 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3044
3045 if (op0 == 3)
3046 OUTS (outf, " = A0");
3047 else
3048 {
3049 if (w0)
3050 OUTS (outf, " = (");
3051 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3052 if (w0)
3053 OUTS (outf, ")");
3054 }
3055 }
3056
3057 decode_optmode (mmod, MM, outf);
3058
3059 return 4;
3060 }
3061
3062 static int
3063 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3064 {
3065 /* dsp32mult
3066 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3067 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3068 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3069 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3070 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3071 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3072 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
3073 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
3074 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3075 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3076 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3077 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3078 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3079 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3080 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3081 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3082
3083 if (w1 == 0 && w0 == 0)
3084 return 0;
3085
3086 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3087 return 0;
3088
3089 if (w1)
3090 {
3091 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3092 OUTS (outf, " = ");
3093 decode_multfunc (h01, h11, src0, src1, outf);
3094
3095 if (w0)
3096 {
3097 if (MM)
3098 OUTS (outf, " (M)");
3099 MM = 0;
3100 OUTS (outf, ", ");
3101 }
3102 }
3103
3104 if (w0)
3105 {
3106 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3107 OUTS (outf, " = ");
3108 decode_multfunc (h00, h10, src0, src1, outf);
3109 }
3110
3111 decode_optmode (mmod, MM, outf);
3112 return 4;
3113 }
3114
3115 static int
3116 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3117 {
3118 /* dsp32alu
3119 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3120 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3121 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3122 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3123 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3124 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3125 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3126 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3127 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3128 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3129 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3130 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3131 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3132
3133 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3134 {
3135 OUTS (outf, "A0.L = ");
3136 OUTS (outf, dregs_lo (src0));
3137 }
3138 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3139 {
3140 OUTS (outf, "A1.H = ");
3141 OUTS (outf, dregs_hi (src0));
3142 }
3143 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3144 {
3145 OUTS (outf, "A1.L = ");
3146 OUTS (outf, dregs_lo (src0));
3147 }
3148 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3149 {
3150 OUTS (outf, "A0.H = ");
3151 OUTS (outf, dregs_hi (src0));
3152 }
3153 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3154 {
3155 OUTS (outf, dregs_hi (dst0));
3156 OUTS (outf, " = ");
3157 OUTS (outf, dregs (src0));
3158 OUTS (outf, " - ");
3159 OUTS (outf, dregs (src1));
3160 OUTS (outf, " (RND20)");
3161 }
3162 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3163 {
3164 OUTS (outf, dregs_hi (dst0));
3165 OUTS (outf, " = ");
3166 OUTS (outf, dregs (src0));
3167 OUTS (outf, " + ");
3168 OUTS (outf, dregs (src1));
3169 OUTS (outf, " (RND20)");
3170 }
3171 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3172 {
3173 OUTS (outf, dregs_lo (dst0));
3174 OUTS (outf, " = ");
3175 OUTS (outf, dregs (src0));
3176 OUTS (outf, " - ");
3177 OUTS (outf, dregs (src1));
3178 OUTS (outf, " (RND12)");
3179 }
3180 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3181 {
3182 OUTS (outf, dregs_lo (dst0));
3183 OUTS (outf, " = ");
3184 OUTS (outf, dregs (src0));
3185 OUTS (outf, " + ");
3186 OUTS (outf, dregs (src1));
3187 OUTS (outf, " (RND12)");
3188 }
3189 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3190 {
3191 OUTS (outf, dregs_lo (dst0));
3192 OUTS (outf, " = ");
3193 OUTS (outf, dregs (src0));
3194 OUTS (outf, " - ");
3195 OUTS (outf, dregs (src1));
3196 OUTS (outf, " (RND20)");
3197 }
3198 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3199 {
3200 OUTS (outf, dregs_hi (dst0));
3201 OUTS (outf, " = ");
3202 OUTS (outf, dregs (src0));
3203 OUTS (outf, " + ");
3204 OUTS (outf, dregs (src1));
3205 OUTS (outf, " (RND12)");
3206 }
3207 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3208 {
3209 OUTS (outf, dregs_lo (dst0));
3210 OUTS (outf, " = ");
3211 OUTS (outf, dregs (src0));
3212 OUTS (outf, " + ");
3213 OUTS (outf, dregs (src1));
3214 OUTS (outf, " (RND20)");
3215 }
3216 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3217 {
3218 OUTS (outf, dregs_hi (dst0));
3219 OUTS (outf, " = ");
3220 OUTS (outf, dregs (src0));
3221 OUTS (outf, " - ");
3222 OUTS (outf, dregs (src1));
3223 OUTS (outf, " (RND12)");
3224 }
3225 else if (HL == 1 && aop == 0 && aopcde == 2)
3226 {
3227 OUTS (outf, dregs_hi (dst0));
3228 OUTS (outf, " = ");
3229 OUTS (outf, dregs_lo (src0));
3230 OUTS (outf, " + ");
3231 OUTS (outf, dregs_lo (src1));
3232 amod1 (s, x, outf);
3233 }
3234 else if (HL == 1 && aop == 1 && aopcde == 2)
3235 {
3236 OUTS (outf, dregs_hi (dst0));
3237 OUTS (outf, " = ");
3238 OUTS (outf, dregs_lo (src0));
3239 OUTS (outf, " + ");
3240 OUTS (outf, dregs_hi (src1));
3241 amod1 (s, x, outf);
3242 }
3243 else if (HL == 1 && aop == 2 && aopcde == 2)
3244 {
3245 OUTS (outf, dregs_hi (dst0));
3246 OUTS (outf, " = ");
3247 OUTS (outf, dregs_hi (src0));
3248 OUTS (outf, " + ");
3249 OUTS (outf, dregs_lo (src1));
3250 amod1 (s, x, outf);
3251 }
3252 else if (HL == 1 && aop == 3 && aopcde == 2)
3253 {
3254 OUTS (outf, dregs_hi (dst0));
3255 OUTS (outf, " = ");
3256 OUTS (outf, dregs_hi (src0));
3257 OUTS (outf, " + ");
3258 OUTS (outf, dregs_hi (src1));
3259 amod1 (s, x, outf);
3260 }
3261 else if (HL == 0 && aop == 0 && aopcde == 3)
3262 {
3263 OUTS (outf, dregs_lo (dst0));
3264 OUTS (outf, " = ");
3265 OUTS (outf, dregs_lo (src0));
3266 OUTS (outf, " - ");
3267 OUTS (outf, dregs_lo (src1));
3268 amod1 (s, x, outf);
3269 }
3270 else if (HL == 0 && aop == 1 && aopcde == 3)
3271 {
3272 OUTS (outf, dregs_lo (dst0));
3273 OUTS (outf, " = ");
3274 OUTS (outf, dregs_lo (src0));
3275 OUTS (outf, " - ");
3276 OUTS (outf, dregs_hi (src1));
3277 amod1 (s, x, outf);
3278 }
3279 else if (HL == 0 && aop == 3 && aopcde == 2)
3280 {
3281 OUTS (outf, dregs_lo (dst0));
3282 OUTS (outf, " = ");
3283 OUTS (outf, dregs_hi (src0));
3284 OUTS (outf, " + ");
3285 OUTS (outf, dregs_hi (src1));
3286 amod1 (s, x, outf);
3287 }
3288 else if (HL == 1 && aop == 0 && aopcde == 3)
3289 {
3290 OUTS (outf, dregs_hi (dst0));
3291 OUTS (outf, " = ");
3292 OUTS (outf, dregs_lo (src0));
3293 OUTS (outf, " - ");
3294 OUTS (outf, dregs_lo (src1));
3295 amod1 (s, x, outf);
3296 }
3297 else if (HL == 1 && aop == 1 && aopcde == 3)
3298 {
3299 OUTS (outf, dregs_hi (dst0));
3300 OUTS (outf, " = ");
3301 OUTS (outf, dregs_lo (src0));
3302 OUTS (outf, " - ");
3303 OUTS (outf, dregs_hi (src1));
3304 amod1 (s, x, outf);
3305 }
3306 else if (HL == 1 && aop == 2 && aopcde == 3)
3307 {
3308 OUTS (outf, dregs_hi (dst0));
3309 OUTS (outf, " = ");
3310 OUTS (outf, dregs_hi (src0));
3311 OUTS (outf, " - ");
3312 OUTS (outf, dregs_lo (src1));
3313 amod1 (s, x, outf);
3314 }
3315 else if (HL == 1 && aop == 3 && aopcde == 3)
3316 {
3317 OUTS (outf, dregs_hi (dst0));
3318 OUTS (outf, " = ");
3319 OUTS (outf, dregs_hi (src0));
3320 OUTS (outf, " - ");
3321 OUTS (outf, dregs_hi (src1));
3322 amod1 (s, x, outf);
3323 }
3324 else if (HL == 0 && aop == 2 && aopcde == 2)
3325 {
3326 OUTS (outf, dregs_lo (dst0));
3327 OUTS (outf, " = ");
3328 OUTS (outf, dregs_hi (src0));
3329 OUTS (outf, " + ");
3330 OUTS (outf, dregs_lo (src1));
3331 amod1 (s, x, outf);
3332 }
3333 else if (HL == 0 && aop == 1 && aopcde == 2)
3334 {
3335 OUTS (outf, dregs_lo (dst0));
3336 OUTS (outf, " = ");
3337 OUTS (outf, dregs_lo (src0));
3338 OUTS (outf, " + ");
3339 OUTS (outf, dregs_hi (src1));
3340 amod1 (s, x, outf);
3341 }
3342 else if (HL == 0 && aop == 2 && aopcde == 3)
3343 {
3344 OUTS (outf, dregs_lo (dst0));
3345 OUTS (outf, " = ");
3346 OUTS (outf, dregs_hi (src0));
3347 OUTS (outf, " - ");
3348 OUTS (outf, dregs_lo (src1));
3349 amod1 (s, x, outf);
3350 }
3351 else if (HL == 0 && aop == 3 && aopcde == 3)
3352 {
3353 OUTS (outf, dregs_lo (dst0));
3354 OUTS (outf, " = ");
3355 OUTS (outf, dregs_hi (src0));
3356 OUTS (outf, " - ");
3357 OUTS (outf, dregs_hi (src1));
3358 amod1 (s, x, outf);
3359 }
3360 else if (HL == 0 && aop == 0 && aopcde == 2)
3361 {
3362 OUTS (outf, dregs_lo (dst0));
3363 OUTS (outf, " = ");
3364 OUTS (outf, dregs_lo (src0));
3365 OUTS (outf, " + ");
3366 OUTS (outf, dregs_lo (src1));
3367 amod1 (s, x, outf);
3368 }
3369 else if (aop == 0 && aopcde == 9 && s == 1)
3370 {
3371 OUTS (outf, "A0 = ");
3372 OUTS (outf, dregs (src0));
3373 }
3374 else if (aop == 3 && aopcde == 11 && s == 0)
3375 OUTS (outf, "A0 -= A1");
3376
3377 else if (aop == 3 && aopcde == 11 && s == 1)
3378 OUTS (outf, "A0 -= A1 (W32)");
3379
3380 else if (aop == 1 && aopcde == 22 && HL == 1)
3381 {
3382 OUTS (outf, dregs (dst0));
3383 OUTS (outf, " = BYTEOP2P (");
3384 OUTS (outf, dregs (src0 + 1));
3385 OUTS (outf, ":");
3386 OUTS (outf, imm5d (src0));
3387 OUTS (outf, ", ");
3388 OUTS (outf, dregs (src1 + 1));
3389 OUTS (outf, ":");
3390 OUTS (outf, imm5d (src1));
3391 OUTS (outf, ") (TH");
3392 if (s == 1)
3393 OUTS (outf, ", R)");
3394 else
3395 OUTS (outf, ")");
3396 }
3397 else if (aop == 1 && aopcde == 22 && HL == 0)
3398 {
3399 OUTS (outf, dregs (dst0));
3400 OUTS (outf, " = BYTEOP2P (");
3401 OUTS (outf, dregs (src0 + 1));
3402 OUTS (outf, ":");
3403 OUTS (outf, imm5d (src0));
3404 OUTS (outf, ", ");
3405 OUTS (outf, dregs (src1 + 1));
3406 OUTS (outf, ":");
3407 OUTS (outf, imm5d (src1));
3408 OUTS (outf, ") (TL");
3409 if (s == 1)
3410 OUTS (outf, ", R)");
3411 else
3412 OUTS (outf, ")");
3413 }
3414 else if (aop == 0 && aopcde == 22 && HL == 1)
3415 {
3416 OUTS (outf, dregs (dst0));
3417 OUTS (outf, " = BYTEOP2P (");
3418 OUTS (outf, dregs (src0 + 1));
3419 OUTS (outf, ":");
3420 OUTS (outf, imm5d (src0));
3421 OUTS (outf, ", ");
3422 OUTS (outf, dregs (src1 + 1));
3423 OUTS (outf, ":");
3424 OUTS (outf, imm5d (src1));
3425 OUTS (outf, ") (RNDH");
3426 if (s == 1)
3427 OUTS (outf, ", R)");
3428 else
3429 OUTS (outf, ")");
3430 }
3431 else if (aop == 0 && aopcde == 22 && HL == 0)
3432 {
3433 OUTS (outf, dregs (dst0));
3434 OUTS (outf, " = BYTEOP2P (");
3435 OUTS (outf, dregs (src0 + 1));
3436 OUTS (outf, ":");
3437 OUTS (outf, imm5d (src0));
3438 OUTS (outf, ", ");
3439 OUTS (outf, dregs (src1 + 1));
3440 OUTS (outf, ":");
3441 OUTS (outf, imm5d (src1));
3442 OUTS (outf, ") (RNDL");
3443 if (s == 1)
3444 OUTS (outf, ", R)");
3445 else
3446 OUTS (outf, ")");
3447 }
3448 else if (aop == 0 && s == 0 && aopcde == 8)
3449 OUTS (outf, "A0 = 0");
3450
3451 else if (aop == 0 && s == 1 && aopcde == 8)
3452 OUTS (outf, "A0 = A0 (S)");
3453
3454 else if (aop == 1 && s == 0 && aopcde == 8)
3455 OUTS (outf, "A1 = 0");
3456
3457 else if (aop == 1 && s == 1 && aopcde == 8)
3458 OUTS (outf, "A1 = A1 (S)");
3459
3460 else if (aop == 2 && s == 0 && aopcde == 8)
3461 OUTS (outf, "A1 = A0 = 0");
3462
3463 else if (aop == 2 && s == 1 && aopcde == 8)
3464 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3465
3466 else if (aop == 3 && s == 0 && aopcde == 8)
3467 OUTS (outf, "A0 = A1");
3468
3469 else if (aop == 3 && s == 1 && aopcde == 8)
3470 OUTS (outf, "A1 = A0");
3471
3472 else if (aop == 1 && aopcde == 9 && s == 0)
3473 {
3474 OUTS (outf, "A0.X = ");
3475 OUTS (outf, dregs_lo (src0));
3476 }
3477 else if (aop == 1 && HL == 0 && aopcde == 11)
3478 {
3479 OUTS (outf, dregs_lo (dst0));
3480 OUTS (outf, " = (A0 += A1)");
3481 }
3482 else if (aop == 3 && HL == 0 && aopcde == 16)
3483 OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
3484
3485 else if (aop == 0 && aopcde == 23 && HL == 1)
3486 {
3487 OUTS (outf, dregs (dst0));
3488 OUTS (outf, " = BYTEOP3P (");
3489 OUTS (outf, dregs (src0 + 1));
3490 OUTS (outf, ":");
3491 OUTS (outf, imm5d (src0));
3492 OUTS (outf, ", ");
3493 OUTS (outf, dregs (src1 + 1));
3494 OUTS (outf, ":");
3495 OUTS (outf, imm5d (src1));
3496 OUTS (outf, ") (HI");
3497 if (s == 1)
3498 OUTS (outf, ", R)");
3499 else
3500 OUTS (outf, ")");
3501 }
3502 else if (aop == 3 && aopcde == 9 && s == 0)
3503 {
3504 OUTS (outf, "A1.X = ");
3505 OUTS (outf, dregs_lo (src0));
3506 }
3507 else if (aop == 1 && HL == 1 && aopcde == 16)
3508 OUTS (outf, "A1 = ABS A1");
3509
3510 else if (aop == 0 && HL == 1 && aopcde == 16)
3511 OUTS (outf, "A1 = ABS A0");
3512
3513 else if (aop == 2 && aopcde == 9 && s == 1)
3514 {
3515 OUTS (outf, "A1 = ");
3516 OUTS (outf, dregs (src0));
3517 }
3518 else if (HL == 0 && aop == 3 && aopcde == 12)
3519 {
3520 OUTS (outf, dregs_lo (dst0));
3521 OUTS (outf, " = ");
3522 OUTS (outf, dregs (src0));
3523 OUTS (outf, " (RND)");
3524 }
3525 else if (aop == 1 && HL == 0 && aopcde == 16)
3526 OUTS (outf, "A0 = ABS A1");
3527
3528 else if (aop == 0 && HL == 0 && aopcde == 16)
3529 OUTS (outf, "A0 = ABS A0");
3530
3531 else if (aop == 3 && HL == 0 && aopcde == 15)
3532 {
3533 OUTS (outf, dregs (dst0));
3534 OUTS (outf, " = -");
3535 OUTS (outf, dregs (src0));
3536 OUTS (outf, " (V)");
3537 }
3538 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3539 {
3540 OUTS (outf, dregs (dst0));
3541 OUTS (outf, " = -");
3542 OUTS (outf, dregs (src0));
3543 OUTS (outf, " (S)");
3544 }
3545 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3546 {
3547 OUTS (outf, dregs (dst0));
3548 OUTS (outf, " = -");
3549 OUTS (outf, dregs (src0));
3550 OUTS (outf, " (NS)");
3551 }
3552 else if (aop == 1 && HL == 1 && aopcde == 11)
3553 {
3554 OUTS (outf, dregs_hi (dst0));
3555 OUTS (outf, " = (A0 += A1)");
3556 }
3557 else if (aop == 2 && aopcde == 11 && s == 0)
3558 OUTS (outf, "A0 += A1");
3559
3560 else if (aop == 2 && aopcde == 11 && s == 1)
3561 OUTS (outf, "A0 += A1 (W32)");
3562
3563 else if (aop == 3 && HL == 0 && aopcde == 14)
3564 OUTS (outf, "A1 = -A1, A0 = -A0");
3565
3566 else if (HL == 1 && aop == 3 && aopcde == 12)
3567 {
3568 OUTS (outf, dregs_hi (dst0));
3569 OUTS (outf, " = ");
3570 OUTS (outf, dregs (src0));
3571 OUTS (outf, " (RND)");
3572 }
3573 else if (aop == 0 && aopcde == 23 && HL == 0)
3574 {
3575 OUTS (outf, dregs (dst0));
3576 OUTS (outf, " = BYTEOP3P (");
3577 OUTS (outf, dregs (src0 + 1));
3578 OUTS (outf, ":");
3579 OUTS (outf, imm5d (src0));
3580 OUTS (outf, ", ");
3581 OUTS (outf, dregs (src1 + 1));
3582 OUTS (outf, ":");
3583 OUTS (outf, imm5d (src1));
3584 OUTS (outf, ") (LO");
3585 if (s == 1)
3586 OUTS (outf, ", R)");
3587 else
3588 OUTS (outf, ")");
3589 }
3590 else if (aop == 0 && HL == 0 && aopcde == 14)
3591 OUTS (outf, "A0 = -A0");
3592
3593 else if (aop == 1 && HL == 0 && aopcde == 14)
3594 OUTS (outf, "A0 = -A1");
3595
3596 else if (aop == 0 && HL == 1 && aopcde == 14)
3597 OUTS (outf, "A1 = -A0");
3598
3599 else if (aop == 1 && HL == 1 && aopcde == 14)
3600 OUTS (outf, "A1 = -A1");
3601
3602 else if (aop == 0 && aopcde == 12)
3603 {
3604 OUTS (outf, dregs_hi (dst0));
3605 OUTS (outf, " = ");
3606 OUTS (outf, dregs_lo (dst0));
3607 OUTS (outf, " = SIGN (");
3608 OUTS (outf, dregs_hi (src0));
3609 OUTS (outf, ") * ");
3610 OUTS (outf, dregs_hi (src1));
3611 OUTS (outf, " + SIGN (");
3612 OUTS (outf, dregs_lo (src0));
3613 OUTS (outf, ") * ");
3614 OUTS (outf, dregs_lo (src1));
3615 }
3616 else if (aop == 2 && aopcde == 0)
3617 {
3618 OUTS (outf, dregs (dst0));
3619 OUTS (outf, " = ");
3620 OUTS (outf, dregs (src0));
3621 OUTS (outf, " -|+ ");
3622 OUTS (outf, dregs (src1));
3623 amod0 (s, x, outf);
3624 }
3625 else if (aop == 1 && aopcde == 12)
3626 {
3627 OUTS (outf, dregs (dst1));
3628 OUTS (outf, " = A1.L + A1.H, ");
3629 OUTS (outf, dregs (dst0));
3630 OUTS (outf, " = A0.L + A0.H");
3631 }
3632 else if (aop == 2 && aopcde == 4)
3633 {
3634 OUTS (outf, dregs (dst1));
3635 OUTS (outf, " = ");
3636 OUTS (outf, dregs (src0));
3637 OUTS (outf, " + ");
3638 OUTS (outf, dregs (src1));
3639 OUTS (outf, ", ");
3640 OUTS (outf, dregs (dst0));
3641 OUTS (outf, " = ");
3642 OUTS (outf, dregs (src0));
3643 OUTS (outf, " - ");
3644 OUTS (outf, dregs (src1));
3645 amod1 (s, x, outf);
3646 }
3647 else if (HL == 0 && aopcde == 1)
3648 {
3649 OUTS (outf, dregs (dst1));
3650 OUTS (outf, " = ");
3651 OUTS (outf, dregs (src0));
3652 OUTS (outf, " +|+ ");
3653 OUTS (outf, dregs (src1));
3654 OUTS (outf, ", ");
3655 OUTS (outf, dregs (dst0));
3656 OUTS (outf, " = ");
3657 OUTS (outf, dregs (src0));
3658 OUTS (outf, " -|- ");
3659 OUTS (outf, dregs (src1));
3660 amod0amod2 (s, x, aop, outf);
3661 }
3662 else if (aop == 0 && aopcde == 11)
3663 {
3664 OUTS (outf, dregs (dst0));
3665 OUTS (outf, " = (A0 += A1)");
3666 }
3667 else if (aop == 0 && aopcde == 10)
3668 {
3669 OUTS (outf, dregs_lo (dst0));
3670 OUTS (outf, " = A0.X");
3671 }
3672 else if (aop == 1 && aopcde == 10)
3673 {
3674 OUTS (outf, dregs_lo (dst0));
3675 OUTS (outf, " = A1.X");
3676 }
3677 else if (aop == 1 && aopcde == 0)
3678 {
3679 OUTS (outf, dregs (dst0));
3680 OUTS (outf, " = ");
3681 OUTS (outf, dregs (src0));
3682 OUTS (outf, " +|- ");
3683 OUTS (outf, dregs (src1));
3684 amod0 (s, x, outf);
3685 }
3686 else if (aop == 3 && aopcde == 0)
3687 {
3688 OUTS (outf, dregs (dst0));
3689 OUTS (outf, " = ");
3690 OUTS (outf, dregs (src0));
3691 OUTS (outf, " -|- ");
3692 OUTS (outf, dregs (src1));
3693 amod0 (s, x, outf);
3694 }
3695 else if (aop == 1 && aopcde == 4)
3696 {
3697 OUTS (outf, dregs (dst0));
3698 OUTS (outf, " = ");
3699 OUTS (outf, dregs (src0));
3700 OUTS (outf, " - ");
3701 OUTS (outf, dregs (src1));
3702 amod1 (s, x, outf);
3703 }
3704 else if (aop == 0 && aopcde == 17)
3705 {
3706 OUTS (outf, dregs (dst1));
3707 OUTS (outf, " = A1 + A0, ");
3708 OUTS (outf, dregs (dst0));
3709 OUTS (outf, " = A1 - A0");
3710 amod1 (s, x, outf);
3711 }
3712 else if (aop == 1 && aopcde == 17)
3713 {
3714 OUTS (outf, dregs (dst1));
3715 OUTS (outf, " = A0 + A1, ");
3716 OUTS (outf, dregs (dst0));
3717 OUTS (outf, " = A0 - A1");
3718 amod1 (s, x, outf);
3719 }
3720 else if (aop == 0 && aopcde == 18)
3721 {
3722 OUTS (outf, "SAA (");
3723 OUTS (outf, dregs (src0 + 1));
3724 OUTS (outf, ":");
3725 OUTS (outf, imm5d (src0));
3726 OUTS (outf, ", ");
3727 OUTS (outf, dregs (src1 + 1));
3728 OUTS (outf, ":");
3729 OUTS (outf, imm5d (src1));
3730 OUTS (outf, ")");
3731 aligndir (s, outf);
3732 }
3733 else if (aop == 3 && aopcde == 18)
3734 OUTS (outf, "DISALGNEXCPT");
3735
3736 else if (aop == 0 && aopcde == 20)
3737 {
3738 OUTS (outf, dregs (dst0));
3739 OUTS (outf, " = BYTEOP1P (");
3740 OUTS (outf, dregs (src0 + 1));
3741 OUTS (outf, ":");
3742 OUTS (outf, imm5d (src0));
3743 OUTS (outf, ", ");
3744 OUTS (outf, dregs (src1 + 1));
3745 OUTS (outf, ":");
3746 OUTS (outf, imm5d (src1));
3747 OUTS (outf, ")");
3748 aligndir (s, outf);
3749 }
3750 else if (aop == 1 && aopcde == 20)
3751 {
3752 OUTS (outf, dregs (dst0));
3753 OUTS (outf, " = BYTEOP1P (");
3754 OUTS (outf, dregs (src0 + 1));
3755 OUTS (outf, ":");
3756 OUTS (outf, imm5d (src0));
3757 OUTS (outf, ", ");
3758 OUTS (outf, dregs (src1 + 1));
3759 OUTS (outf, ":");
3760 OUTS (outf, imm5d (src1));
3761 OUTS (outf, ") (T");
3762 if (s == 1)
3763 OUTS (outf, ", R)");
3764 else
3765 OUTS (outf, ")");
3766 }
3767 else if (aop == 0 && aopcde == 21)
3768 {
3769 OUTS (outf, "(");
3770 OUTS (outf, dregs (dst1));
3771 OUTS (outf, ", ");
3772 OUTS (outf, dregs (dst0));
3773 OUTS (outf, ") = BYTEOP16P (");
3774 OUTS (outf, dregs (src0 + 1));
3775 OUTS (outf, ":");
3776 OUTS (outf, imm5d (src0));
3777 OUTS (outf, ", ");
3778 OUTS (outf, dregs (src1 + 1));
3779 OUTS (outf, ":");
3780 OUTS (outf, imm5d (src1));
3781 OUTS (outf, ")");
3782 aligndir (s, outf);
3783 }
3784 else if (aop == 1 && aopcde == 21)
3785 {
3786 OUTS (outf, "(");
3787 OUTS (outf, dregs (dst1));
3788 OUTS (outf, ", ");
3789 OUTS (outf, dregs (dst0));
3790 OUTS (outf, ") = BYTEOP16M (");
3791 OUTS (outf, dregs (src0 + 1));
3792 OUTS (outf, ":");
3793 OUTS (outf, imm5d (src0));
3794 OUTS (outf, ", ");
3795 OUTS (outf, dregs (src1 + 1));
3796 OUTS (outf, ":");
3797 OUTS (outf, imm5d (src1));
3798 OUTS (outf, ")");
3799 aligndir (s, outf);
3800 }
3801 else if (aop == 2 && aopcde == 7)
3802 {
3803 OUTS (outf, dregs (dst0));
3804 OUTS (outf, " = ABS ");
3805 OUTS (outf, dregs (src0));
3806 }
3807 else if (aop == 1 && aopcde == 7)
3808 {
3809 OUTS (outf, dregs (dst0));
3810 OUTS (outf, " = MIN (");
3811 OUTS (outf, dregs (src0));
3812 OUTS (outf, ", ");
3813 OUTS (outf, dregs (src1));
3814 OUTS (outf, ")");
3815 }
3816 else if (aop == 0 && aopcde == 7)
3817 {
3818 OUTS (outf, dregs (dst0));
3819 OUTS (outf, " = MAX (");
3820 OUTS (outf, dregs (src0));
3821 OUTS (outf, ", ");
3822 OUTS (outf, dregs (src1));
3823 OUTS (outf, ")");
3824 }
3825 else if (aop == 2 && aopcde == 6)
3826 {
3827 OUTS (outf, dregs (dst0));
3828 OUTS (outf, " = ABS ");
3829 OUTS (outf, dregs (src0));
3830 OUTS (outf, " (V)");
3831 }
3832 else if (aop == 1 && aopcde == 6)
3833 {
3834 OUTS (outf, dregs (dst0));
3835 OUTS (outf, " = MIN (");
3836 OUTS (outf, dregs (src0));
3837 OUTS (outf, ", ");
3838 OUTS (outf, dregs (src1));
3839 OUTS (outf, ") (V)");
3840 }
3841 else if (aop == 0 && aopcde == 6)
3842 {
3843 OUTS (outf, dregs (dst0));
3844 OUTS (outf, " = MAX (");
3845 OUTS (outf, dregs (src0));
3846 OUTS (outf, ", ");
3847 OUTS (outf, dregs (src1));
3848 OUTS (outf, ") (V)");
3849 }
3850 else if (HL == 1 && aopcde == 1)
3851 {
3852 OUTS (outf, dregs (dst1));
3853 OUTS (outf, " = ");
3854 OUTS (outf, dregs (src0));
3855 OUTS (outf, " +|- ");
3856 OUTS (outf, dregs (src1));
3857 OUTS (outf, ", ");
3858 OUTS (outf, dregs (dst0));
3859 OUTS (outf, " = ");
3860 OUTS (outf, dregs (src0));
3861 OUTS (outf, " -|+ ");
3862 OUTS (outf, dregs (src1));
3863 amod0amod2 (s, x, aop, outf);
3864 }
3865 else if (aop == 0 && aopcde == 4)
3866 {
3867 OUTS (outf, dregs (dst0));
3868 OUTS (outf, " = ");
3869 OUTS (outf, dregs (src0));
3870 OUTS (outf, " + ");
3871 OUTS (outf, dregs (src1));
3872 amod1 (s, x, outf);
3873 }
3874 else if (aop == 0 && aopcde == 0)
3875 {
3876 OUTS (outf, dregs (dst0));
3877 OUTS (outf, " = ");
3878 OUTS (outf, dregs (src0));
3879 OUTS (outf, " +|+ ");
3880 OUTS (outf, dregs (src1));
3881 amod0 (s, x, outf);
3882 }
3883 else if (aop == 0 && aopcde == 24)
3884 {
3885 OUTS (outf, dregs (dst0));
3886 OUTS (outf, " = BYTEPACK (");
3887 OUTS (outf, dregs (src0));
3888 OUTS (outf, ", ");
3889 OUTS (outf, dregs (src1));
3890 OUTS (outf, ")");
3891 }
3892 else if (aop == 1 && aopcde == 24)
3893 {
3894 OUTS (outf, "(");
3895 OUTS (outf, dregs (dst1));
3896 OUTS (outf, ", ");
3897 OUTS (outf, dregs (dst0));
3898 OUTS (outf, ") = BYTEUNPACK ");
3899 OUTS (outf, dregs (src0 + 1));
3900 OUTS (outf, ":");
3901 OUTS (outf, imm5d (src0));
3902 aligndir (s, outf);
3903 }
3904 else if (aopcde == 13)
3905 {
3906 OUTS (outf, "(");
3907 OUTS (outf, dregs (dst1));
3908 OUTS (outf, ", ");
3909 OUTS (outf, dregs (dst0));
3910 OUTS (outf, ") = SEARCH ");
3911 OUTS (outf, dregs (src0));
3912 OUTS (outf, " (");
3913 searchmod (aop, outf);
3914 OUTS (outf, ")");
3915 }
3916 else
3917 return 0;
3918
3919 return 4;
3920 }
3921
3922 static int
3923 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3924 {
3925 /* dsp32shift
3926 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3927 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3928 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3929 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3930 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3931 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3932 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3933 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3934 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3935 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3936 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3937
3938 if (HLs == 0 && sop == 0 && sopcde == 0)
3939 {
3940 OUTS (outf, dregs_lo (dst0));
3941 OUTS (outf, " = ASHIFT ");
3942 OUTS (outf, dregs_lo (src1));
3943 OUTS (outf, " BY ");
3944 OUTS (outf, dregs_lo (src0));
3945 }
3946 else if (HLs == 1 && sop == 0 && sopcde == 0)
3947 {
3948 OUTS (outf, dregs_lo (dst0));
3949 OUTS (outf, " = ASHIFT ");
3950 OUTS (outf, dregs_hi (src1));
3951 OUTS (outf, " BY ");
3952 OUTS (outf, dregs_lo (src0));
3953 }
3954 else if (HLs == 2 && sop == 0 && sopcde == 0)
3955 {
3956 OUTS (outf, dregs_hi (dst0));
3957 OUTS (outf, " = ASHIFT ");
3958 OUTS (outf, dregs_lo (src1));
3959 OUTS (outf, " BY ");
3960 OUTS (outf, dregs_lo (src0));
3961 }
3962 else if (HLs == 3 && sop == 0 && sopcde == 0)
3963 {
3964 OUTS (outf, dregs_hi (dst0));
3965 OUTS (outf, " = ASHIFT ");
3966 OUTS (outf, dregs_hi (src1));
3967 OUTS (outf, " BY ");
3968 OUTS (outf, dregs_lo (src0));
3969 }
3970 else if (HLs == 0 && sop == 1 && sopcde == 0)
3971 {
3972 OUTS (outf, dregs_lo (dst0));
3973 OUTS (outf, " = ASHIFT ");
3974 OUTS (outf, dregs_lo (src1));
3975 OUTS (outf, " BY ");
3976 OUTS (outf, dregs_lo (src0));
3977 OUTS (outf, " (S)");
3978 }
3979 else if (HLs == 1 && sop == 1 && sopcde == 0)
3980 {
3981 OUTS (outf, dregs_lo (dst0));
3982 OUTS (outf, " = ASHIFT ");
3983 OUTS (outf, dregs_hi (src1));
3984 OUTS (outf, " BY ");
3985 OUTS (outf, dregs_lo (src0));
3986 OUTS (outf, " (S)");
3987 }
3988 else if (HLs == 2 && sop == 1 && sopcde == 0)
3989 {
3990 OUTS (outf, dregs_hi (dst0));
3991 OUTS (outf, " = ASHIFT ");
3992 OUTS (outf, dregs_lo (src1));
3993 OUTS (outf, " BY ");
3994 OUTS (outf, dregs_lo (src0));
3995 OUTS (outf, " (S)");
3996 }
3997 else if (HLs == 3 && sop == 1 && sopcde == 0)
3998 {
3999 OUTS (outf, dregs_hi (dst0));
4000 OUTS (outf, " = ASHIFT ");
4001 OUTS (outf, dregs_hi (src1));
4002 OUTS (outf, " BY ");
4003 OUTS (outf, dregs_lo (src0));
4004 OUTS (outf, " (S)");
4005 }
4006 else if (sop == 2 && sopcde == 0)
4007 {
4008 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
4009 OUTS (outf, " = LSHIFT ");
4010 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
4011 OUTS (outf, " BY ");
4012 OUTS (outf, dregs_lo (src0));
4013 }
4014 else if (sop == 0 && sopcde == 3)
4015 {
4016 OUTS (outf, acc01);
4017 OUTS (outf, " = ASHIFT ");
4018 OUTS (outf, acc01);
4019 OUTS (outf, " BY ");
4020 OUTS (outf, dregs_lo (src0));
4021 }
4022 else if (sop == 1 && sopcde == 3)
4023 {
4024 OUTS (outf, acc01);
4025 OUTS (outf, " = LSHIFT ");
4026 OUTS (outf, acc01);
4027 OUTS (outf, " BY ");
4028 OUTS (outf, dregs_lo (src0));
4029 }
4030 else if (sop == 2 && sopcde == 3)
4031 {
4032 OUTS (outf, acc01);
4033 OUTS (outf, " = ROT ");
4034 OUTS (outf, acc01);
4035 OUTS (outf, " BY ");
4036 OUTS (outf, dregs_lo (src0));
4037 }
4038 else if (sop == 3 && sopcde == 3)
4039 {
4040 OUTS (outf, dregs (dst0));
4041 OUTS (outf, " = ROT ");
4042 OUTS (outf, dregs (src1));
4043 OUTS (outf, " BY ");
4044 OUTS (outf, dregs_lo (src0));
4045 }
4046 else if (sop == 1 && sopcde == 1)
4047 {
4048 OUTS (outf, dregs (dst0));
4049 OUTS (outf, " = ASHIFT ");
4050 OUTS (outf, dregs (src1));
4051 OUTS (outf, " BY ");
4052 OUTS (outf, dregs_lo (src0));
4053 OUTS (outf, " (V, S)");
4054 }
4055 else if (sop == 0 && sopcde == 1)
4056 {
4057 OUTS (outf, dregs (dst0));
4058 OUTS (outf, " = ASHIFT ");
4059 OUTS (outf, dregs (src1));
4060 OUTS (outf, " BY ");
4061 OUTS (outf, dregs_lo (src0));
4062 OUTS (outf, " (V)");
4063 }
4064 else if (sop == 0 && sopcde == 2)
4065 {
4066 OUTS (outf, dregs (dst0));
4067 OUTS (outf, " = ASHIFT ");
4068 OUTS (outf, dregs (src1));
4069 OUTS (outf, " BY ");
4070 OUTS (outf, dregs_lo (src0));
4071 }
4072 else if (sop == 1 && sopcde == 2)
4073 {
4074 OUTS (outf, dregs (dst0));
4075 OUTS (outf, " = ASHIFT ");
4076 OUTS (outf, dregs (src1));
4077 OUTS (outf, " BY ");
4078 OUTS (outf, dregs_lo (src0));
4079 OUTS (outf, " (S)");
4080 }
4081 else if (sop == 2 && sopcde == 2)
4082 {
4083 OUTS (outf, dregs (dst0));
4084 OUTS (outf, " = LSHIFT ");
4085 OUTS (outf, dregs (src1));
4086 OUTS (outf, " BY ");
4087 OUTS (outf, dregs_lo (src0));
4088 }
4089 else if (sop == 3 && sopcde == 2)
4090 {
4091 OUTS (outf, dregs (dst0));
4092 OUTS (outf, " = ROT ");
4093 OUTS (outf, dregs (src1));
4094 OUTS (outf, " BY ");
4095 OUTS (outf, dregs_lo (src0));
4096 }
4097 else if (sop == 2 && sopcde == 1)
4098 {
4099 OUTS (outf, dregs (dst0));
4100 OUTS (outf, " = LSHIFT ");
4101 OUTS (outf, dregs (src1));
4102 OUTS (outf, " BY ");
4103 OUTS (outf, dregs_lo (src0));
4104 OUTS (outf, " (V)");
4105 }
4106 else if (sop == 0 && sopcde == 4)
4107 {
4108 OUTS (outf, dregs (dst0));
4109 OUTS (outf, " = PACK (");
4110 OUTS (outf, dregs_lo (src1));
4111 OUTS (outf, ", ");
4112 OUTS (outf, dregs_lo (src0));
4113 OUTS (outf, ")");
4114 }
4115 else if (sop == 1 && sopcde == 4)
4116 {
4117 OUTS (outf, dregs (dst0));
4118 OUTS (outf, " = PACK (");
4119 OUTS (outf, dregs_lo (src1));
4120 OUTS (outf, ", ");
4121 OUTS (outf, dregs_hi (src0));
4122 OUTS (outf, ")");
4123 }
4124 else if (sop == 2 && sopcde == 4)
4125 {
4126 OUTS (outf, dregs (dst0));
4127 OUTS (outf, " = PACK (");
4128 OUTS (outf, dregs_hi (src1));
4129 OUTS (outf, ", ");
4130 OUTS (outf, dregs_lo (src0));
4131 OUTS (outf, ")");
4132 }
4133 else if (sop == 3 && sopcde == 4)
4134 {
4135 OUTS (outf, dregs (dst0));
4136 OUTS (outf, " = PACK (");
4137 OUTS (outf, dregs_hi (src1));
4138 OUTS (outf, ", ");
4139 OUTS (outf, dregs_hi (src0));
4140 OUTS (outf, ")");
4141 }
4142 else if (sop == 0 && sopcde == 5)
4143 {
4144 OUTS (outf, dregs_lo (dst0));
4145 OUTS (outf, " = SIGNBITS ");
4146 OUTS (outf, dregs (src1));
4147 }
4148 else if (sop == 1 && sopcde == 5)
4149 {
4150 OUTS (outf, dregs_lo (dst0));
4151 OUTS (outf, " = SIGNBITS ");
4152 OUTS (outf, dregs_lo (src1));
4153 }
4154 else if (sop == 2 && sopcde == 5)
4155 {
4156 OUTS (outf, dregs_lo (dst0));
4157 OUTS (outf, " = SIGNBITS ");
4158 OUTS (outf, dregs_hi (src1));
4159 }
4160 else if (sop == 0 && sopcde == 6)
4161 {
4162 OUTS (outf, dregs_lo (dst0));
4163 OUTS (outf, " = SIGNBITS A0");
4164 }
4165 else if (sop == 1 && sopcde == 6)
4166 {
4167 OUTS (outf, dregs_lo (dst0));
4168 OUTS (outf, " = SIGNBITS A1");
4169 }
4170 else if (sop == 3 && sopcde == 6)
4171 {
4172 OUTS (outf, dregs_lo (dst0));
4173 OUTS (outf, " = ONES ");
4174 OUTS (outf, dregs (src1));
4175 }
4176 else if (sop == 0 && sopcde == 7)
4177 {
4178 OUTS (outf, dregs_lo (dst0));
4179 OUTS (outf, " = EXPADJ (");
4180 OUTS (outf, dregs (src1));
4181 OUTS (outf, ", ");
4182 OUTS (outf, dregs_lo (src0));
4183 OUTS (outf, ")");
4184 }
4185 else if (sop == 1 && sopcde == 7)
4186 {
4187 OUTS (outf, dregs_lo (dst0));
4188 OUTS (outf, " = EXPADJ (");
4189 OUTS (outf, dregs (src1));
4190 OUTS (outf, ", ");
4191 OUTS (outf, dregs_lo (src0));
4192 OUTS (outf, ") (V)");
4193 }
4194 else if (sop == 2 && sopcde == 7)
4195 {
4196 OUTS (outf, dregs_lo (dst0));
4197 OUTS (outf, " = EXPADJ (");
4198 OUTS (outf, dregs_lo (src1));
4199 OUTS (outf, ", ");
4200 OUTS (outf, dregs_lo (src0));
4201 OUTS (outf, ")");
4202 }
4203 else if (sop == 3 && sopcde == 7)
4204 {
4205 OUTS (outf, dregs_lo (dst0));
4206 OUTS (outf, " = EXPADJ (");
4207 OUTS (outf, dregs_hi (src1));
4208 OUTS (outf, ", ");
4209 OUTS (outf, dregs_lo (src0));
4210 OUTS (outf, ")");
4211 }
4212 else if (sop == 0 && sopcde == 8)
4213 {
4214 OUTS (outf, "BITMUX (");
4215 OUTS (outf, dregs (src0));
4216 OUTS (outf, ", ");
4217 OUTS (outf, dregs (src1));
4218 OUTS (outf, ", A0) (ASR)");
4219 }
4220 else if (sop == 1 && sopcde == 8)
4221 {
4222 OUTS (outf, "BITMUX (");
4223 OUTS (outf, dregs (src0));
4224 OUTS (outf, ", ");
4225 OUTS (outf, dregs (src1));
4226 OUTS (outf, ", A0) (ASL)");
4227 }
4228 else if (sop == 0 && sopcde == 9)
4229 {
4230 OUTS (outf, dregs_lo (dst0));
4231 OUTS (outf, " = VIT_MAX (");
4232 OUTS (outf, dregs (src1));
4233 OUTS (outf, ") (ASL)");
4234 }
4235 else if (sop == 1 && sopcde == 9)
4236 {
4237 OUTS (outf, dregs_lo (dst0));
4238 OUTS (outf, " = VIT_MAX (");
4239 OUTS (outf, dregs (src1));
4240 OUTS (outf, ") (ASR)");
4241 }
4242 else if (sop == 2 && sopcde == 9)
4243 {
4244 OUTS (outf, dregs (dst0));
4245 OUTS (outf, " = VIT_MAX (");
4246 OUTS (outf, dregs (src1));
4247 OUTS (outf, ", ");
4248 OUTS (outf, dregs (src0));
4249 OUTS (outf, ") (ASL)");
4250 }
4251 else if (sop == 3 && sopcde == 9)
4252 {
4253 OUTS (outf, dregs (dst0));
4254 OUTS (outf, " = VIT_MAX (");
4255 OUTS (outf, dregs (src1));
4256 OUTS (outf, ", ");
4257 OUTS (outf, dregs (src0));
4258 OUTS (outf, ") (ASR)");
4259 }
4260 else if (sop == 0 && sopcde == 10)
4261 {
4262 OUTS (outf, dregs (dst0));
4263 OUTS (outf, " = EXTRACT (");
4264 OUTS (outf, dregs (src1));
4265 OUTS (outf, ", ");
4266 OUTS (outf, dregs_lo (src0));
4267 OUTS (outf, ") (Z)");
4268 }
4269 else if (sop == 1 && sopcde == 10)
4270 {
4271 OUTS (outf, dregs (dst0));
4272 OUTS (outf, " = EXTRACT (");
4273 OUTS (outf, dregs (src1));
4274 OUTS (outf, ", ");
4275 OUTS (outf, dregs_lo (src0));
4276 OUTS (outf, ") (X)");
4277 }
4278 else if (sop == 2 && sopcde == 10)
4279 {
4280 OUTS (outf, dregs (dst0));
4281 OUTS (outf, " = DEPOSIT (");
4282 OUTS (outf, dregs (src1));
4283 OUTS (outf, ", ");
4284 OUTS (outf, dregs (src0));
4285 OUTS (outf, ")");
4286 }
4287 else if (sop == 3 && sopcde == 10)
4288 {
4289 OUTS (outf, dregs (dst0));
4290 OUTS (outf, " = DEPOSIT (");
4291 OUTS (outf, dregs (src1));
4292 OUTS (outf, ", ");
4293 OUTS (outf, dregs (src0));
4294 OUTS (outf, ") (X)");
4295 }
4296 else if (sop == 0 && sopcde == 11)
4297 {
4298 OUTS (outf, dregs_lo (dst0));
4299 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4300 OUTS (outf, dregs (src0));
4301 OUTS (outf, ")");
4302 }
4303 else if (sop == 1 && sopcde == 11)
4304 {
4305 OUTS (outf, dregs_lo (dst0));
4306 OUTS (outf, " = CC = BXOR (A0, ");
4307 OUTS (outf, dregs (src0));
4308 OUTS (outf, ")");
4309 }
4310 else if (sop == 0 && sopcde == 12)
4311 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4312
4313 else if (sop == 1 && sopcde == 12)
4314 {
4315 OUTS (outf, dregs_lo (dst0));
4316 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4317 }
4318 else if (sop == 0 && sopcde == 13)
4319 {
4320 OUTS (outf, dregs (dst0));
4321 OUTS (outf, " = ALIGN8 (");
4322 OUTS (outf, dregs (src1));
4323 OUTS (outf, ", ");
4324 OUTS (outf, dregs (src0));
4325 OUTS (outf, ")");
4326 }
4327 else if (sop == 1 && sopcde == 13)
4328 {
4329 OUTS (outf, dregs (dst0));
4330 OUTS (outf, " = ALIGN16 (");
4331 OUTS (outf, dregs (src1));
4332 OUTS (outf, ", ");
4333 OUTS (outf, dregs (src0));
4334 OUTS (outf, ")");
4335 }
4336 else if (sop == 2 && sopcde == 13)
4337 {
4338 OUTS (outf, dregs (dst0));
4339 OUTS (outf, " = ALIGN24 (");
4340 OUTS (outf, dregs (src1));
4341 OUTS (outf, ", ");
4342 OUTS (outf, dregs (src0));
4343 OUTS (outf, ")");
4344 }
4345 else
4346 return 0;
4347
4348 return 4;
4349 }
4350
4351 static int
4352 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4353 {
4354 /* dsp32shiftimm
4355 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4356 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4357 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4358 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4359 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4360 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4361 int bit8 = ((iw1 >> 8) & 0x1);
4362 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4363 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4364 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4365 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4366 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4367
4368 if (sop == 0 && sopcde == 0)
4369 {
4370 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4371 OUTS (outf, " = ");
4372 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4373 OUTS (outf, " >>> ");
4374 OUTS (outf, uimm4 (newimmag));
4375 }
4376 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4377 {
4378 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4379 OUTS (outf, " = ");
4380 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4381 OUTS (outf, " << ");
4382 OUTS (outf, uimm4 (immag));
4383 OUTS (outf, " (S)");
4384 }
4385 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4386 {
4387 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4388 OUTS (outf, " = ");
4389 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4390 OUTS (outf, " >>> ");
4391 OUTS (outf, uimm4 (newimmag));
4392 OUTS (outf, " (S)");
4393 }
4394 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4395 {
4396 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4397 OUTS (outf, " = ");
4398 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4399 OUTS (outf, " << ");
4400 OUTS (outf, uimm4 (immag));
4401 }
4402 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4403 {
4404 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4405 OUTS (outf, " = ");
4406 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4407 OUTS (outf, " >> ");
4408 OUTS (outf, uimm4 (newimmag));
4409 }
4410 else if (sop == 2 && sopcde == 3 && HLs == 1)
4411 {
4412 OUTS (outf, "A1 = ROT A1 BY ");
4413 OUTS (outf, imm6 (immag));
4414 }
4415 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4416 {
4417 OUTS (outf, "A0 = A0 << ");
4418 OUTS (outf, uimm5 (immag));
4419 }
4420 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4421 {
4422 OUTS (outf, "A0 = A0 >>> ");
4423 OUTS (outf, uimm5 (newimmag));
4424 }
4425 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4426 {
4427 OUTS (outf, "A1 = A1 << ");
4428 OUTS (outf, uimm5 (immag));
4429 }
4430 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4431 {
4432 OUTS (outf, "A1 = A1 >>> ");
4433 OUTS (outf, uimm5 (newimmag));
4434 }
4435 else if (sop == 1 && sopcde == 3 && HLs == 0)
4436 {
4437 OUTS (outf, "A0 = A0 >> ");
4438 OUTS (outf, uimm5 (newimmag));
4439 }
4440 else if (sop == 1 && sopcde == 3 && HLs == 1)
4441 {
4442 OUTS (outf, "A1 = A1 >> ");
4443 OUTS (outf, uimm5 (newimmag));
4444 }
4445 else if (sop == 2 && sopcde == 3 && HLs == 0)
4446 {
4447 OUTS (outf, "A0 = ROT A0 BY ");
4448 OUTS (outf, imm6 (immag));
4449 }
4450 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4451 {
4452 OUTS (outf, dregs (dst0));
4453 OUTS (outf, " = ");
4454 OUTS (outf, dregs (src1));
4455 OUTS (outf, " << ");
4456 OUTS (outf, uimm5 (immag));
4457 OUTS (outf, " (V, S)");
4458 }
4459 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4460 {
4461 OUTS (outf, dregs (dst0));
4462 OUTS (outf, " = ");
4463 OUTS (outf, dregs (src1));
4464 OUTS (outf, " >>> ");
4465 OUTS (outf, imm5 (-immag));
4466 OUTS (outf, " (V, S)");
4467 }
4468 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4469 {
4470 OUTS (outf, dregs (dst0));
4471 OUTS (outf, " = ");
4472 OUTS (outf, dregs (src1));
4473 OUTS (outf, " >> ");
4474 OUTS (outf, uimm5 (newimmag));
4475 OUTS (outf, " (V)");
4476 }
4477 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4478 {
4479 OUTS (outf, dregs (dst0));
4480 OUTS (outf, " = ");
4481 OUTS (outf, dregs (src1));
4482 OUTS (outf, " << ");
4483 OUTS (outf, imm5 (immag));
4484 OUTS (outf, " (V)");
4485 }
4486 else if (sop == 0 && sopcde == 1)
4487 {
4488 OUTS (outf, dregs (dst0));
4489 OUTS (outf, " = ");
4490 OUTS (outf, dregs (src1));
4491 OUTS (outf, " >>> ");
4492 OUTS (outf, uimm5 (newimmag));
4493 OUTS (outf, " (V)");
4494 }
4495 else if (sop == 1 && sopcde == 2)
4496 {
4497 OUTS (outf, dregs (dst0));
4498 OUTS (outf, " = ");
4499 OUTS (outf, dregs (src1));
4500 OUTS (outf, " << ");
4501 OUTS (outf, uimm5 (immag));
4502 OUTS (outf, " (S)");
4503 }
4504 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4505 {
4506 OUTS (outf, dregs (dst0));
4507 OUTS (outf, " = ");
4508 OUTS (outf, dregs (src1));
4509 OUTS (outf, " >> ");
4510 OUTS (outf, uimm5 (newimmag));
4511 }
4512 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4513 {
4514 OUTS (outf, dregs (dst0));
4515 OUTS (outf, " = ");
4516 OUTS (outf, dregs (src1));
4517 OUTS (outf, " << ");
4518 OUTS (outf, uimm5 (immag));
4519 }
4520 else if (sop == 3 && sopcde == 2)
4521 {
4522 OUTS (outf, dregs (dst0));
4523 OUTS (outf, " = ROT ");
4524 OUTS (outf, dregs (src1));
4525 OUTS (outf, " BY ");
4526 OUTS (outf, imm6 (immag));
4527 }
4528 else if (sop == 0 && sopcde == 2)
4529 {
4530 OUTS (outf, dregs (dst0));
4531 OUTS (outf, " = ");
4532 OUTS (outf, dregs (src1));
4533 OUTS (outf, " >>> ");
4534 OUTS (outf, uimm5 (newimmag));
4535 }
4536 else
4537 return 0;
4538
4539 return 4;
4540 }
4541
4542 static int
4543 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4544 {
4545 /* pseudoDEBUG
4546 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4547 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4548 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4549 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4550 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4551 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4552
4553 if (parallel)
4554 return 0;
4555
4556 if (reg == 0 && fn == 3)
4557 OUTS (outf, "DBG A0");
4558
4559 else if (reg == 1 && fn == 3)
4560 OUTS (outf, "DBG A1");
4561
4562 else if (reg == 3 && fn == 3)
4563 OUTS (outf, "ABORT");
4564
4565 else if (reg == 4 && fn == 3)
4566 OUTS (outf, "HLT");
4567
4568 else if (reg == 5 && fn == 3)
4569 OUTS (outf, "DBGHALT");
4570
4571 else if (reg == 6 && fn == 3)
4572 {
4573 OUTS (outf, "DBGCMPLX (");
4574 OUTS (outf, dregs (grp));
4575 OUTS (outf, ")");
4576 }
4577 else if (reg == 7 && fn == 3)
4578 OUTS (outf, "DBG");
4579
4580 else if (grp == 0 && fn == 2)
4581 {
4582 OUTS (outf, "OUTC ");
4583 OUTS (outf, dregs (reg));
4584 }
4585 else if (fn == 0)
4586 {
4587 OUTS (outf, "DBG ");
4588 OUTS (outf, allregs (reg, grp));
4589 }
4590 else if (fn == 1)
4591 {
4592 OUTS (outf, "PRNT ");
4593 OUTS (outf, allregs (reg, grp));
4594 }
4595 else
4596 return 0;
4597
4598 return 2;
4599 }
4600
4601 static int
4602 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4603 {
4604 /* psedoOChar
4605 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4606 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4607 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4608 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4609
4610 if (parallel)
4611 return 0;
4612
4613 OUTS (outf, "OUTC ");
4614 OUTS (outf, uimm8 (ch));
4615
4616 return 2;
4617 }
4618
4619 static int
4620 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4621 {
4622 /* pseudodbg_assert
4623 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4624 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4625 |.expected......................................................|
4626 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4627 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4628 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4629 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4630 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4631
4632 if (parallel)
4633 return 0;
4634
4635 if (dbgop == 0)
4636 {
4637 OUTS (outf, "DBGA (");
4638 OUTS (outf, regs_lo (regtest, grp));
4639 OUTS (outf, ", ");
4640 OUTS (outf, uimm16 (expected));
4641 OUTS (outf, ")");
4642 }
4643 else if (dbgop == 1)
4644 {
4645 OUTS (outf, "DBGA (");
4646 OUTS (outf, regs_hi (regtest, grp));
4647 OUTS (outf, ", ");
4648 OUTS (outf, uimm16 (expected));
4649 OUTS (outf, ")");
4650 }
4651 else if (dbgop == 2)
4652 {
4653 OUTS (outf, "DBGAL (");
4654 OUTS (outf, allregs (regtest, grp));
4655 OUTS (outf, ", ");
4656 OUTS (outf, uimm16 (expected));
4657 OUTS (outf, ")");
4658 }
4659 else if (dbgop == 3)
4660 {
4661 OUTS (outf, "DBGAH (");
4662 OUTS (outf, allregs (regtest, grp));
4663 OUTS (outf, ", ");
4664 OUTS (outf, uimm16 (expected));
4665 OUTS (outf, ")");
4666 }
4667 else
4668 return 0;
4669 return 4;
4670 }
4671
4672 static int
4673 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4674 {
4675 bfd_byte buf[4];
4676 TIword iw0;
4677 TIword iw1;
4678 int status;
4679 int rv = 0;
4680
4681 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4682 /* FIXME */
4683 (void) status;
4684 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4685 /* FIXME */
4686 (void) status;
4687
4688 iw0 = bfd_getl16 (buf);
4689 iw1 = bfd_getl16 (buf + 2);
4690
4691 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4692 {
4693 if (parallel)
4694 {
4695 OUTS (outf, "ILLEGAL");
4696 return 0;
4697 }
4698 OUTS (outf, "MNOP");
4699 return 4;
4700 }
4701 else if ((iw0 & 0xff00) == 0x0000)
4702 rv = decode_ProgCtrl_0 (iw0, outf);
4703 else if ((iw0 & 0xffc0) == 0x0240)
4704 rv = decode_CaCTRL_0 (iw0, outf);
4705 else if ((iw0 & 0xff80) == 0x0100)
4706 rv = decode_PushPopReg_0 (iw0, outf);
4707 else if ((iw0 & 0xfe00) == 0x0400)
4708 rv = decode_PushPopMultiple_0 (iw0, outf);
4709 else if ((iw0 & 0xfe00) == 0x0600)
4710 rv = decode_ccMV_0 (iw0, outf);
4711 else if ((iw0 & 0xf800) == 0x0800)
4712 rv = decode_CCflag_0 (iw0, outf);
4713 else if ((iw0 & 0xffe0) == 0x0200)
4714 rv = decode_CC2dreg_0 (iw0, outf);
4715 else if ((iw0 & 0xff00) == 0x0300)
4716 rv = decode_CC2stat_0 (iw0, outf);
4717 else if ((iw0 & 0xf000) == 0x1000)
4718 rv = decode_BRCC_0 (iw0, pc, outf);
4719 else if ((iw0 & 0xf000) == 0x2000)
4720 rv = decode_UJUMP_0 (iw0, pc, outf);
4721 else if ((iw0 & 0xf000) == 0x3000)
4722 rv = decode_REGMV_0 (iw0, outf);
4723 else if ((iw0 & 0xfc00) == 0x4000)
4724 rv = decode_ALU2op_0 (iw0, outf);
4725 else if ((iw0 & 0xfe00) == 0x4400)
4726 rv = decode_PTR2op_0 (iw0, outf);
4727 else if ((iw0 & 0xf800) == 0x4800)
4728 rv = decode_LOGI2op_0 (iw0, outf);
4729 else if ((iw0 & 0xf000) == 0x5000)
4730 rv = decode_COMP3op_0 (iw0, outf);
4731 else if ((iw0 & 0xf800) == 0x6000)
4732 rv = decode_COMPI2opD_0 (iw0, outf);
4733 else if ((iw0 & 0xf800) == 0x6800)
4734 rv = decode_COMPI2opP_0 (iw0, outf);
4735 else if ((iw0 & 0xf000) == 0x8000)
4736 rv = decode_LDSTpmod_0 (iw0, outf);
4737 else if ((iw0 & 0xff60) == 0x9e60)
4738 rv = decode_dagMODim_0 (iw0, outf);
4739 else if ((iw0 & 0xfff0) == 0x9f60)
4740 rv = decode_dagMODik_0 (iw0, outf);
4741 else if ((iw0 & 0xfc00) == 0x9c00)
4742 rv = decode_dspLDST_0 (iw0, outf);
4743 else if ((iw0 & 0xf000) == 0x9000)
4744 rv = decode_LDST_0 (iw0, outf);
4745 else if ((iw0 & 0xfc00) == 0xb800)
4746 rv = decode_LDSTiiFP_0 (iw0, outf);
4747 else if ((iw0 & 0xe000) == 0xA000)
4748 rv = decode_LDSTii_0 (iw0, outf);
4749 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4750 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4751 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4752 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4753 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4754 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4755 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4756 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4757 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4758 rv = decode_linkage_0 (iw0, iw1, outf);
4759 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4760 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4761 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4762 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4763 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4764 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4765 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4766 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4767 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4768 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4769 else if ((iw0 & 0xff00) == 0xf800)
4770 rv = decode_pseudoDEBUG_0 (iw0, outf);
4771 else if ((iw0 & 0xFF00) == 0xF900)
4772 rv = decode_pseudoOChar_0 (iw0, outf);
4773 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4774 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4775
4776 if (rv == 0)
4777 OUTS (outf, "ILLEGAL");
4778
4779 return rv;
4780 }
4781
4782 int
4783 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4784 {
4785 bfd_byte buf[2];
4786 unsigned short iw0;
4787 int status;
4788 int count = 0;
4789
4790 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4791 /* FIXME */
4792 (void) status;
4793 iw0 = bfd_getl16 (buf);
4794
4795 count += _print_insn_bfin (pc, outf);
4796
4797 /* Proper display of multiple issue instructions. */
4798
4799 if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4800 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4801 {
4802 int legal = 1;
4803 int len;
4804
4805 parallel = 1;
4806 outf->fprintf_func (outf->stream, " || ");
4807 len = _print_insn_bfin (pc + 4, outf);
4808 outf->fprintf_func (outf->stream, " || ");
4809 if (len != 2)
4810 legal = 0;
4811 len = _print_insn_bfin (pc + 6, outf);
4812 if (len != 2)
4813 legal = 0;
4814
4815 if (legal)
4816 count = 8;
4817 else
4818 {
4819 outf->fprintf_func (outf->stream, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4820 comment = 1;
4821 count = 0;
4822 }
4823 parallel = 0;
4824 }
4825
4826 if (!comment)
4827 outf->fprintf_func (outf->stream, ";");
4828
4829 if (count == 0)
4830 return 2;
4831
4832 comment = 0;
4833
4834 return count;
4835 }
GDB Binutils - Deliverables
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