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opcodes: blackfin: mark push/pop insns with a P6/P7 range as illegal
[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c
1 /* Disassemble ADI Blackfin Instructions.
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
3
4 This file is part of libopcodes.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include <stdio.h>
22 #include <stdlib.h>
23 #include <string.h>
24
25 #include "opcode/bfin.h"
26
27 #define M_S2RND 1
28 #define M_T 2
29 #define M_W32 3
30 #define M_FU 4
31 #define M_TFU 6
32 #define M_IS 8
33 #define M_ISS2 9
34 #define M_IH 11
35 #define M_IU 12
36
37 #ifndef PRINTF
38 #define PRINTF printf
39 #endif
40
41 #ifndef EXIT
42 #define EXIT exit
43 #endif
44
45 typedef long TIword;
46
47 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
48 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
49 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
50 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
51
52 #include "dis-asm.h"
53
54 typedef unsigned int bu32;
55
56 static char comment = 0;
57 static char parallel = 0;
58
59 typedef enum
60 {
61 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
62 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
63 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
64 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
65 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
66 } const_forms_t;
67
68 static const struct
69 {
70 const char *name;
71 const int nbits;
72 const char reloc;
73 const char issigned;
74 const char pcrel;
75 const char scale;
76 const char offset;
77 const char negative;
78 const char positive;
79 const char decimal;
80 const char leading;
81 const char exact;
82 } constant_formats[] =
83 {
84 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
85 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
86 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
88 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
89 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
91 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
92 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
94 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
95 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
97 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
98 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
99 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
100 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
101 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
102 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
103 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
104 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
107 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
108 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
109 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
110 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
111 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
112 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
113 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
114 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
118 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
119 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
120 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
121 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
122 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
123 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
124 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
125 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
126 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
127 };
128
129 static const char *
130 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
131 {
132 static char buf[60];
133
134 if (constant_formats[cf].reloc)
135 {
136 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
137 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
138 if (constant_formats[cf].pcrel)
139 ea += pc;
140
141 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
142 {
143 outf->print_address_func (ea, outf);
144 return "";
145 }
146 else
147 {
148 sprintf (buf, "%lx", (unsigned long) x);
149 return buf;
150 }
151 }
152
153 /* Negative constants have an implied sign bit. */
154 if (constant_formats[cf].negative)
155 {
156 int nb = constant_formats[cf].nbits + 1;
157
158 x = x | (1 << constant_formats[cf].nbits);
159 x = SIGNEXTEND (x, nb);
160 }
161 else
162 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
163
164 if (constant_formats[cf].offset)
165 x += constant_formats[cf].offset;
166
167 if (constant_formats[cf].scale)
168 x <<= constant_formats[cf].scale;
169
170 if (constant_formats[cf].decimal)
171 {
172 if (constant_formats[cf].leading)
173 {
174 char ps[10];
175 sprintf (ps, "%%%ii", constant_formats[cf].leading);
176 sprintf (buf, ps, x);
177 }
178 else
179 sprintf (buf, "%li", x);
180 }
181 else
182 {
183 if (constant_formats[cf].issigned && x < 0)
184 sprintf (buf, "-0x%x", abs (x));
185 else
186 sprintf (buf, "0x%lx", (unsigned long) x);
187 }
188
189 return buf;
190 }
191
192 static bu32
193 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
194 {
195 if (0 && constant_formats[cf].reloc)
196 {
197 bu32 ea = (((constant_formats[cf].pcrel
198 ? SIGNEXTEND (x, constant_formats[cf].nbits)
199 : x) + constant_formats[cf].offset)
200 << constant_formats[cf].scale);
201 if (constant_formats[cf].pcrel)
202 ea += pc;
203
204 return ea;
205 }
206
207 /* Negative constants have an implied sign bit. */
208 if (constant_formats[cf].negative)
209 {
210 int nb = constant_formats[cf].nbits + 1;
211 x = x | (1 << constant_formats[cf].nbits);
212 x = SIGNEXTEND (x, nb);
213 }
214 else if (constant_formats[cf].issigned)
215 x = SIGNEXTEND (x, constant_formats[cf].nbits);
216
217 x += constant_formats[cf].offset;
218 x <<= constant_formats[cf].scale;
219
220 return x;
221 }
222
223 enum machine_registers
224 {
225 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
226 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
227 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
228 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
229 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
230 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
231 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
232 REG_L2, REG_L3,
233 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
234 REG_AQ, REG_V, REG_VS,
235 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
236 REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
237 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
238 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
239 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
240 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
241 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
242 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
243 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
244 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
245 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
246 REG_LASTREG,
247 };
248
249 enum reg_class
250 {
251 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
252 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
253 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
254 rc_sysregs3, rc_allregs,
255 LIM_REG_CLASSES
256 };
257
258 static const char *reg_names[] =
259 {
260 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
261 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
262 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
263 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
264 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
265 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
266 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
267 "L2", "L3",
268 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
269 "AQ", "V", "VS",
270 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
271 "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
272 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
273 "RETE", "EMUDAT",
274 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
275 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
276 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
277 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
278 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
279 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
280 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
281 "AC0_COPY", "V_COPY", "RND_MOD",
282 "LASTREG",
283 0
284 };
285
286 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
287
288 /* RL(0..7). */
289 static enum machine_registers decode_dregs_lo[] =
290 {
291 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
292 };
293
294 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
295
296 /* RH(0..7). */
297 static enum machine_registers decode_dregs_hi[] =
298 {
299 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
300 };
301
302 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
303
304 /* R(0..7). */
305 static enum machine_registers decode_dregs[] =
306 {
307 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
308 };
309
310 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
311
312 /* R BYTE(0..7). */
313 static enum machine_registers decode_dregs_byte[] =
314 {
315 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
316 };
317
318 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
319
320 /* P(0..5) SP FP. */
321 static enum machine_registers decode_pregs[] =
322 {
323 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
324 };
325
326 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
327 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
328 #define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
329 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
330 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
331 #define accum(x) REGNAME (decode_accum[(x) & 1])
332
333 /* I(0..3). */
334 static enum machine_registers decode_iregs[] =
335 {
336 REG_I0, REG_I1, REG_I2, REG_I3,
337 };
338
339 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
340
341 /* M(0..3). */
342 static enum machine_registers decode_mregs[] =
343 {
344 REG_M0, REG_M1, REG_M2, REG_M3,
345 };
346
347 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
348 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
349 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
350
351 /* dregs pregs. */
352 static enum machine_registers decode_dpregs[] =
353 {
354 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
355 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
356 };
357
358 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
359
360 /* [dregs pregs]. */
361 static enum machine_registers decode_gregs[] =
362 {
363 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
364 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
365 };
366
367 #define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
368
369 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
370 static enum machine_registers decode_regs[] =
371 {
372 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
373 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
374 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
375 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
376 };
377
378 #define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
379
380 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
381 static enum machine_registers decode_regs_lo[] =
382 {
383 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
384 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
385 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
386 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
387 };
388
389 #define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
390 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
391 static enum machine_registers decode_regs_hi[] =
392 {
393 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
394 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
395 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
396 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
397 };
398
399 #define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
400
401 static enum machine_registers decode_statbits[] =
402 {
403 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
404 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
405 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
406 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
407 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
408 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
409 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
410 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
411 };
412
413 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
414
415 /* LC0 LC1. */
416 static enum machine_registers decode_counters[] =
417 {
418 REG_LC0, REG_LC1,
419 };
420
421 #define counters(x) REGNAME (decode_counters[(x) & 1])
422 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
423
424 /* [dregs pregs (iregs mregs) (bregs lregs)
425 dregs2_sysregs1 open sysregs2 sysregs3]. */
426 static enum machine_registers decode_allregs[] =
427 {
428 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
429 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
430 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
431 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
432 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
433 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
434 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
435 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
436 REG_LASTREG,
437 };
438
439 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
440 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
441 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
442 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
443 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
444 #define IS_SYSREG(g,r) \
445 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
446 #define IS_RESERVEDREG(g,r) \
447 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
448
449 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
450 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
451
452 #define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
453 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
454 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
455 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
456 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
457 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
458 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
459 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
460 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
461 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
462 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
463 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
464 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
465 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
466 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
467 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
468 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
469 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
470 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
471 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
472 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
473 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
474 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
475 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
476 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
477 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
478 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
479 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
480 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
481 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
482 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
483 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
484 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
485 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
486 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
487 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
488 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
489 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
490 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
491 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
492 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
493 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
494 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
495
496 /* (arch.pm)arch_disassembler_functions. */
497 #ifndef OUTS
498 #define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
499 #endif
500
501 static void
502 amod0 (int s0, int x0, disassemble_info *outf)
503 {
504 if (s0 == 1 && x0 == 0)
505 OUTS (outf, " (S)");
506 else if (s0 == 0 && x0 == 1)
507 OUTS (outf, " (CO)");
508 else if (s0 == 1 && x0 == 1)
509 OUTS (outf, " (SCO)");
510 }
511
512 static void
513 amod1 (int s0, int x0, disassemble_info *outf)
514 {
515 if (s0 == 0 && x0 == 0)
516 OUTS (outf, " (NS)");
517 else if (s0 == 1 && x0 == 0)
518 OUTS (outf, " (S)");
519 }
520
521 static void
522 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
523 {
524 if (s0 == 1 && x0 == 0 && aop0 == 0)
525 OUTS (outf, " (S)");
526 else if (s0 == 0 && x0 == 1 && aop0 == 0)
527 OUTS (outf, " (CO)");
528 else if (s0 == 1 && x0 == 1 && aop0 == 0)
529 OUTS (outf, " (SCO)");
530 else if (s0 == 0 && x0 == 0 && aop0 == 2)
531 OUTS (outf, " (ASR)");
532 else if (s0 == 1 && x0 == 0 && aop0 == 2)
533 OUTS (outf, " (S, ASR)");
534 else if (s0 == 0 && x0 == 1 && aop0 == 2)
535 OUTS (outf, " (CO, ASR)");
536 else if (s0 == 1 && x0 == 1 && aop0 == 2)
537 OUTS (outf, " (SCO, ASR)");
538 else if (s0 == 0 && x0 == 0 && aop0 == 3)
539 OUTS (outf, " (ASL)");
540 else if (s0 == 1 && x0 == 0 && aop0 == 3)
541 OUTS (outf, " (S, ASL)");
542 else if (s0 == 0 && x0 == 1 && aop0 == 3)
543 OUTS (outf, " (CO, ASL)");
544 else if (s0 == 1 && x0 == 1 && aop0 == 3)
545 OUTS (outf, " (SCO, ASL)");
546 }
547
548 static void
549 searchmod (int r0, disassemble_info *outf)
550 {
551 if (r0 == 0)
552 OUTS (outf, "GT");
553 else if (r0 == 1)
554 OUTS (outf, "GE");
555 else if (r0 == 2)
556 OUTS (outf, "LT");
557 else if (r0 == 3)
558 OUTS (outf, "LE");
559 }
560
561 static void
562 aligndir (int r0, disassemble_info *outf)
563 {
564 if (r0 == 1)
565 OUTS (outf, " (R)");
566 }
567
568 static int
569 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
570 {
571 const char *s0, *s1;
572
573 if (h0)
574 s0 = dregs_hi (src0);
575 else
576 s0 = dregs_lo (src0);
577
578 if (h1)
579 s1 = dregs_hi (src1);
580 else
581 s1 = dregs_lo (src1);
582
583 OUTS (outf, s0);
584 OUTS (outf, " * ");
585 OUTS (outf, s1);
586 return 0;
587 }
588
589 static int
590 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
591 {
592 const char *a;
593 const char *sop = "<unknown op>";
594
595 if (which)
596 a = "A1";
597 else
598 a = "A0";
599
600 if (op == 3)
601 {
602 OUTS (outf, a);
603 return 0;
604 }
605
606 switch (op)
607 {
608 case 0: sop = " = "; break;
609 case 1: sop = " += "; break;
610 case 2: sop = " -= "; break;
611 default: break;
612 }
613
614 OUTS (outf, a);
615 OUTS (outf, sop);
616 decode_multfunc (h0, h1, src0, src1, outf);
617
618 return 0;
619 }
620
621 static void
622 decode_optmode (int mod, int MM, disassemble_info *outf)
623 {
624 if (mod == 0 && MM == 0)
625 return;
626
627 OUTS (outf, " (");
628
629 if (MM && !mod)
630 {
631 OUTS (outf, "M)");
632 return;
633 }
634
635 if (MM)
636 OUTS (outf, "M, ");
637
638 if (mod == M_S2RND)
639 OUTS (outf, "S2RND");
640 else if (mod == M_T)
641 OUTS (outf, "T");
642 else if (mod == M_W32)
643 OUTS (outf, "W32");
644 else if (mod == M_FU)
645 OUTS (outf, "FU");
646 else if (mod == M_TFU)
647 OUTS (outf, "TFU");
648 else if (mod == M_IS)
649 OUTS (outf, "IS");
650 else if (mod == M_ISS2)
651 OUTS (outf, "ISS2");
652 else if (mod == M_IH)
653 OUTS (outf, "IH");
654 else if (mod == M_IU)
655 OUTS (outf, "IU");
656 else
657 abort ();
658
659 OUTS (outf, ")");
660 }
661
662 struct saved_state
663 {
664 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
665 bu32 a0x, a0w, a1x, a1w;
666 bu32 lt[2], lc[2], lb[2];
667 int ac0, ac0_copy, ac1, an, aq;
668 int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
669 int rnd_mod;
670 int v_internal;
671 bu32 pc, rets;
672
673 int ticks;
674 int insts;
675
676 int exception;
677
678 int end_of_registers;
679
680 int msize;
681 unsigned char *memory;
682 unsigned long bfd_mach;
683 } saved_state;
684
685 #define DREG(x) (saved_state.dpregs[x])
686 #define GREG(x,i) DPREG ((x) | (i << 3))
687 #define DPREG(x) (saved_state.dpregs[x])
688 #define DREG(x) (saved_state.dpregs[x])
689 #define PREG(x) (saved_state.dpregs[x + 8])
690 #define SPREG PREG (6)
691 #define FPREG PREG (7)
692 #define IREG(x) (saved_state.iregs[x])
693 #define MREG(x) (saved_state.mregs[x])
694 #define BREG(x) (saved_state.bregs[x])
695 #define LREG(x) (saved_state.lregs[x])
696 #define A0XREG (saved_state.a0x)
697 #define A0WREG (saved_state.a0w)
698 #define A1XREG (saved_state.a1x)
699 #define A1WREG (saved_state.a1w)
700 #define CCREG (saved_state.cc)
701 #define LC0REG (saved_state.lc[0])
702 #define LT0REG (saved_state.lt[0])
703 #define LB0REG (saved_state.lb[0])
704 #define LC1REG (saved_state.lc[1])
705 #define LT1REG (saved_state.lt[1])
706 #define LB1REG (saved_state.lb[1])
707 #define RETSREG (saved_state.rets)
708 #define PCREG (saved_state.pc)
709
710 static bu32 *
711 get_allreg (int grp, int reg)
712 {
713 int fullreg = (grp << 3) | reg;
714 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
715 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
716 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
717 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
718 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
719 , , , , , , , ,
720 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
721 REG_CYCLES2,
722 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
723 REG_LASTREG */
724 switch (fullreg >> 2)
725 {
726 case 0: case 1: return &DREG (reg); break;
727 case 2: case 3: return &PREG (reg); break;
728 case 4: return &IREG (reg & 3); break;
729 case 5: return &MREG (reg & 3); break;
730 case 6: return &BREG (reg & 3); break;
731 case 7: return &LREG (reg & 3); break;
732 default:
733 switch (fullreg)
734 {
735 case 32: return &saved_state.a0x;
736 case 33: return &saved_state.a0w;
737 case 34: return &saved_state.a1x;
738 case 35: return &saved_state.a1w;
739 case 39: return &saved_state.rets;
740 case 48: return &LC0REG;
741 case 49: return &LT0REG;
742 case 50: return &LB0REG;
743 case 51: return &LC1REG;
744 case 52: return &LT1REG;
745 case 53: return &LB1REG;
746 }
747 return 0;
748 }
749 }
750
751 static int
752 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
753 {
754 /* ProgCtrl
755 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
756 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
757 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
758 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
759 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
760
761 if (prgfunc == 0 && poprnd == 0)
762 OUTS (outf, "NOP");
763 else if (prgfunc == 1 && poprnd == 0)
764 OUTS (outf, "RTS");
765 else if (prgfunc == 1 && poprnd == 1)
766 OUTS (outf, "RTI");
767 else if (prgfunc == 1 && poprnd == 2)
768 OUTS (outf, "RTX");
769 else if (prgfunc == 1 && poprnd == 3)
770 OUTS (outf, "RTN");
771 else if (prgfunc == 1 && poprnd == 4)
772 OUTS (outf, "RTE");
773 else if (prgfunc == 2 && poprnd == 0)
774 OUTS (outf, "IDLE");
775 else if (prgfunc == 2 && poprnd == 3)
776 OUTS (outf, "CSYNC");
777 else if (prgfunc == 2 && poprnd == 4)
778 OUTS (outf, "SSYNC");
779 else if (prgfunc == 2 && poprnd == 5)
780 OUTS (outf, "EMUEXCPT");
781 else if (prgfunc == 3 && IS_DREG (0, poprnd))
782 {
783 OUTS (outf, "CLI ");
784 OUTS (outf, dregs (poprnd));
785 }
786 else if (prgfunc == 4 && IS_DREG (0, poprnd))
787 {
788 OUTS (outf, "STI ");
789 OUTS (outf, dregs (poprnd));
790 }
791 else if (prgfunc == 5 && IS_PREG (1, poprnd))
792 {
793 OUTS (outf, "JUMP (");
794 OUTS (outf, pregs (poprnd));
795 OUTS (outf, ")");
796 }
797 else if (prgfunc == 6 && IS_PREG (1, poprnd))
798 {
799 OUTS (outf, "CALL (");
800 OUTS (outf, pregs (poprnd));
801 OUTS (outf, ")");
802 }
803 else if (prgfunc == 7 && IS_PREG (1, poprnd))
804 {
805 OUTS (outf, "CALL (PC + ");
806 OUTS (outf, pregs (poprnd));
807 OUTS (outf, ")");
808 }
809 else if (prgfunc == 8 && IS_PREG (1, poprnd))
810 {
811 OUTS (outf, "JUMP (PC + ");
812 OUTS (outf, pregs (poprnd));
813 OUTS (outf, ")");
814 }
815 else if (prgfunc == 9)
816 {
817 OUTS (outf, "RAISE ");
818 OUTS (outf, uimm4 (poprnd));
819 }
820 else if (prgfunc == 10)
821 {
822 OUTS (outf, "EXCPT ");
823 OUTS (outf, uimm4 (poprnd));
824 }
825 else if (prgfunc == 11 && IS_PREG (1, poprnd))
826 {
827 OUTS (outf, "TESTSET (");
828 OUTS (outf, pregs (poprnd));
829 OUTS (outf, ")");
830 }
831 else
832 return 0;
833 return 2;
834 }
835
836 static int
837 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
838 {
839 /* CaCTRL
840 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
841 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
842 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
843 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
844 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
845 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
846
847 if (a == 0 && op == 0)
848 {
849 OUTS (outf, "PREFETCH[");
850 OUTS (outf, pregs (reg));
851 OUTS (outf, "]");
852 }
853 else if (a == 0 && op == 1)
854 {
855 OUTS (outf, "FLUSHINV[");
856 OUTS (outf, pregs (reg));
857 OUTS (outf, "]");
858 }
859 else if (a == 0 && op == 2)
860 {
861 OUTS (outf, "FLUSH[");
862 OUTS (outf, pregs (reg));
863 OUTS (outf, "]");
864 }
865 else if (a == 0 && op == 3)
866 {
867 OUTS (outf, "IFLUSH[");
868 OUTS (outf, pregs (reg));
869 OUTS (outf, "]");
870 }
871 else if (a == 1 && op == 0)
872 {
873 OUTS (outf, "PREFETCH[");
874 OUTS (outf, pregs (reg));
875 OUTS (outf, "++]");
876 }
877 else if (a == 1 && op == 1)
878 {
879 OUTS (outf, "FLUSHINV[");
880 OUTS (outf, pregs (reg));
881 OUTS (outf, "++]");
882 }
883 else if (a == 1 && op == 2)
884 {
885 OUTS (outf, "FLUSH[");
886 OUTS (outf, pregs (reg));
887 OUTS (outf, "++]");
888 }
889 else if (a == 1 && op == 3)
890 {
891 OUTS (outf, "IFLUSH[");
892 OUTS (outf, pregs (reg));
893 OUTS (outf, "++]");
894 }
895 else
896 return 0;
897 return 2;
898 }
899
900 static int
901 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
902 {
903 /* PushPopReg
904 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
905 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
906 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
907 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
908 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
909 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
910
911 if (W == 0 && mostreg (reg, grp))
912 {
913 OUTS (outf, allregs (reg, grp));
914 OUTS (outf, " = [SP++]");
915 }
916 else if (W == 1 && allreg (reg, grp))
917 {
918 OUTS (outf, "[--SP] = ");
919 OUTS (outf, allregs (reg, grp));
920 }
921 else
922 return 0;
923 return 2;
924 }
925
926 static int
927 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
928 {
929 /* PushPopMultiple
930 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
931 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
932 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
933 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
934 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
935 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
936 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
937 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
938
939 if (pr > 5)
940 return 0;
941
942 if (W == 1 && d == 1 && p == 1)
943 {
944 OUTS (outf, "[--SP] = (R7:");
945 OUTS (outf, imm5d (dr));
946 OUTS (outf, ", P5:");
947 OUTS (outf, imm5d (pr));
948 OUTS (outf, ")");
949 }
950 else if (W == 1 && d == 1 && p == 0)
951 {
952 OUTS (outf, "[--SP] = (R7:");
953 OUTS (outf, imm5d (dr));
954 OUTS (outf, ")");
955 }
956 else if (W == 1 && d == 0 && p == 1)
957 {
958 OUTS (outf, "[--SP] = (P5:");
959 OUTS (outf, imm5d (pr));
960 OUTS (outf, ")");
961 }
962 else if (W == 0 && d == 1 && p == 1)
963 {
964 OUTS (outf, "(R7:");
965 OUTS (outf, imm5d (dr));
966 OUTS (outf, ", P5:");
967 OUTS (outf, imm5d (pr));
968 OUTS (outf, ") = [SP++]");
969 }
970 else if (W == 0 && d == 1 && p == 0)
971 {
972 OUTS (outf, "(R7:");
973 OUTS (outf, imm5d (dr));
974 OUTS (outf, ") = [SP++]");
975 }
976 else if (W == 0 && d == 0 && p == 1)
977 {
978 OUTS (outf, "(P5:");
979 OUTS (outf, imm5d (pr));
980 OUTS (outf, ") = [SP++]");
981 }
982 else
983 return 0;
984 return 2;
985 }
986
987 static int
988 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
989 {
990 /* ccMV
991 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
992 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
993 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
994 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
995 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
996 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
997 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
998 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
999
1000 if (T == 1)
1001 {
1002 OUTS (outf, "IF CC ");
1003 OUTS (outf, gregs (dst, d));
1004 OUTS (outf, " = ");
1005 OUTS (outf, gregs (src, s));
1006 }
1007 else if (T == 0)
1008 {
1009 OUTS (outf, "IF !CC ");
1010 OUTS (outf, gregs (dst, d));
1011 OUTS (outf, " = ");
1012 OUTS (outf, gregs (src, s));
1013 }
1014 else
1015 return 0;
1016 return 2;
1017 }
1018
1019 static int
1020 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1021 {
1022 /* CCflag
1023 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1024 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1025 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1026 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1027 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1028 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1029 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1030 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1031
1032 if (opc == 0 && I == 0 && G == 0)
1033 {
1034 OUTS (outf, "CC = ");
1035 OUTS (outf, dregs (x));
1036 OUTS (outf, " == ");
1037 OUTS (outf, dregs (y));
1038 }
1039 else if (opc == 1 && I == 0 && G == 0)
1040 {
1041 OUTS (outf, "CC = ");
1042 OUTS (outf, dregs (x));
1043 OUTS (outf, " < ");
1044 OUTS (outf, dregs (y));
1045 }
1046 else if (opc == 2 && I == 0 && G == 0)
1047 {
1048 OUTS (outf, "CC = ");
1049 OUTS (outf, dregs (x));
1050 OUTS (outf, " <= ");
1051 OUTS (outf, dregs (y));
1052 }
1053 else if (opc == 3 && I == 0 && G == 0)
1054 {
1055 OUTS (outf, "CC = ");
1056 OUTS (outf, dregs (x));
1057 OUTS (outf, " < ");
1058 OUTS (outf, dregs (y));
1059 OUTS (outf, " (IU)");
1060 }
1061 else if (opc == 4 && I == 0 && G == 0)
1062 {
1063 OUTS (outf, "CC = ");
1064 OUTS (outf, dregs (x));
1065 OUTS (outf, " <= ");
1066 OUTS (outf, dregs (y));
1067 OUTS (outf, " (IU)");
1068 }
1069 else if (opc == 0 && I == 1 && G == 0)
1070 {
1071 OUTS (outf, "CC = ");
1072 OUTS (outf, dregs (x));
1073 OUTS (outf, " == ");
1074 OUTS (outf, imm3 (y));
1075 }
1076 else if (opc == 1 && I == 1 && G == 0)
1077 {
1078 OUTS (outf, "CC = ");
1079 OUTS (outf, dregs (x));
1080 OUTS (outf, " < ");
1081 OUTS (outf, imm3 (y));
1082 }
1083 else if (opc == 2 && I == 1 && G == 0)
1084 {
1085 OUTS (outf, "CC = ");
1086 OUTS (outf, dregs (x));
1087 OUTS (outf, " <= ");
1088 OUTS (outf, imm3 (y));
1089 }
1090 else if (opc == 3 && I == 1 && G == 0)
1091 {
1092 OUTS (outf, "CC = ");
1093 OUTS (outf, dregs (x));
1094 OUTS (outf, " < ");
1095 OUTS (outf, uimm3 (y));
1096 OUTS (outf, " (IU)");
1097 }
1098 else if (opc == 4 && I == 1 && G == 0)
1099 {
1100 OUTS (outf, "CC = ");
1101 OUTS (outf, dregs (x));
1102 OUTS (outf, " <= ");
1103 OUTS (outf, uimm3 (y));
1104 OUTS (outf, " (IU)");
1105 }
1106 else if (opc == 0 && I == 0 && G == 1)
1107 {
1108 OUTS (outf, "CC = ");
1109 OUTS (outf, pregs (x));
1110 OUTS (outf, " == ");
1111 OUTS (outf, pregs (y));
1112 }
1113 else if (opc == 1 && I == 0 && G == 1)
1114 {
1115 OUTS (outf, "CC = ");
1116 OUTS (outf, pregs (x));
1117 OUTS (outf, " < ");
1118 OUTS (outf, pregs (y));
1119 }
1120 else if (opc == 2 && I == 0 && G == 1)
1121 {
1122 OUTS (outf, "CC = ");
1123 OUTS (outf, pregs (x));
1124 OUTS (outf, " <= ");
1125 OUTS (outf, pregs (y));
1126 }
1127 else if (opc == 3 && I == 0 && G == 1)
1128 {
1129 OUTS (outf, "CC = ");
1130 OUTS (outf, pregs (x));
1131 OUTS (outf, " < ");
1132 OUTS (outf, pregs (y));
1133 OUTS (outf, " (IU)");
1134 }
1135 else if (opc == 4 && I == 0 && G == 1)
1136 {
1137 OUTS (outf, "CC = ");
1138 OUTS (outf, pregs (x));
1139 OUTS (outf, " <= ");
1140 OUTS (outf, pregs (y));
1141 OUTS (outf, " (IU)");
1142 }
1143 else if (opc == 0 && I == 1 && G == 1)
1144 {
1145 OUTS (outf, "CC = ");
1146 OUTS (outf, pregs (x));
1147 OUTS (outf, " == ");
1148 OUTS (outf, imm3 (y));
1149 }
1150 else if (opc == 1 && I == 1 && G == 1)
1151 {
1152 OUTS (outf, "CC = ");
1153 OUTS (outf, pregs (x));
1154 OUTS (outf, " < ");
1155 OUTS (outf, imm3 (y));
1156 }
1157 else if (opc == 2 && I == 1 && G == 1)
1158 {
1159 OUTS (outf, "CC = ");
1160 OUTS (outf, pregs (x));
1161 OUTS (outf, " <= ");
1162 OUTS (outf, imm3 (y));
1163 }
1164 else if (opc == 3 && I == 1 && G == 1)
1165 {
1166 OUTS (outf, "CC = ");
1167 OUTS (outf, pregs (x));
1168 OUTS (outf, " < ");
1169 OUTS (outf, uimm3 (y));
1170 OUTS (outf, " (IU)");
1171 }
1172 else if (opc == 4 && I == 1 && G == 1)
1173 {
1174 OUTS (outf, "CC = ");
1175 OUTS (outf, pregs (x));
1176 OUTS (outf, " <= ");
1177 OUTS (outf, uimm3 (y));
1178 OUTS (outf, " (IU)");
1179 }
1180 else if (opc == 5 && I == 0 && G == 0)
1181 OUTS (outf, "CC = A0 == A1");
1182
1183 else if (opc == 6 && I == 0 && G == 0)
1184 OUTS (outf, "CC = A0 < A1");
1185
1186 else if (opc == 7 && I == 0 && G == 0)
1187 OUTS (outf, "CC = A0 <= A1");
1188
1189 else
1190 return 0;
1191 return 2;
1192 }
1193
1194 static int
1195 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1196 {
1197 /* CC2dreg
1198 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1199 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1200 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1201 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1202 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1203
1204 if (op == 0)
1205 {
1206 OUTS (outf, dregs (reg));
1207 OUTS (outf, " = CC");
1208 }
1209 else if (op == 1)
1210 {
1211 OUTS (outf, "CC = ");
1212 OUTS (outf, dregs (reg));
1213 }
1214 else if (op == 3 && reg == 0)
1215 OUTS (outf, "CC = !CC");
1216 else
1217 return 0;
1218
1219 return 2;
1220 }
1221
1222 static int
1223 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1224 {
1225 /* CC2stat
1226 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1227 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1228 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1229 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1230 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1231 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1232
1233 const char *bitname = statbits (cbit);
1234 if (decode_statbits[cbit] == REG_LASTREG)
1235 {
1236 /* All ASTAT bits except CC may be operated on in hardware, but may
1237 not have a dedicated insn, so still decode "valid" insns. */
1238 static char bitnames[64];
1239 if (cbit != 5)
1240 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1241 else
1242 strcpy (bitnames, "CC /* ... Illegal register ... */");
1243 bitname = bitnames;
1244 }
1245
1246 if (op == 0 && D == 0)
1247 {
1248 OUTS (outf, "CC = ");
1249 OUTS (outf, bitname);
1250 }
1251 else if (op == 1 && D == 0)
1252 {
1253 OUTS (outf, "CC |= ");
1254 OUTS (outf, bitname);
1255 }
1256 else if (op == 2 && D == 0)
1257 {
1258 OUTS (outf, "CC &= ");
1259 OUTS (outf, bitname);
1260 }
1261 else if (op == 3 && D == 0)
1262 {
1263 OUTS (outf, "CC ^= ");
1264 OUTS (outf, bitname);
1265 }
1266 else if (op == 0 && D == 1)
1267 {
1268 OUTS (outf, bitname);
1269 OUTS (outf, " = CC");
1270 }
1271 else if (op == 1 && D == 1)
1272 {
1273 OUTS (outf, bitname);
1274 OUTS (outf, " |= CC");
1275 }
1276 else if (op == 2 && D == 1)
1277 {
1278 OUTS (outf, bitname);
1279 OUTS (outf, " &= CC");
1280 }
1281 else if (op == 3 && D == 1)
1282 {
1283 OUTS (outf, bitname);
1284 OUTS (outf, " ^= CC");
1285 }
1286 else
1287 return 0;
1288
1289 return 2;
1290 }
1291
1292 static int
1293 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1294 {
1295 /* BRCC
1296 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1297 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1298 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1299 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1300 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1301 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1302
1303 if (T == 1 && B == 1)
1304 {
1305 OUTS (outf, "IF CC JUMP 0x");
1306 OUTS (outf, pcrel10 (offset));
1307 OUTS (outf, " (BP)");
1308 }
1309 else if (T == 0 && B == 1)
1310 {
1311 OUTS (outf, "IF !CC JUMP 0x");
1312 OUTS (outf, pcrel10 (offset));
1313 OUTS (outf, " (BP)");
1314 }
1315 else if (T == 1)
1316 {
1317 OUTS (outf, "IF CC JUMP 0x");
1318 OUTS (outf, pcrel10 (offset));
1319 }
1320 else if (T == 0)
1321 {
1322 OUTS (outf, "IF !CC JUMP 0x");
1323 OUTS (outf, pcrel10 (offset));
1324 }
1325 else
1326 return 0;
1327
1328 return 2;
1329 }
1330
1331 static int
1332 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1333 {
1334 /* UJUMP
1335 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1336 | 0 | 0 | 1 | 0 |.offset........................................|
1337 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1338 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1339
1340 OUTS (outf, "JUMP.S 0x");
1341 OUTS (outf, pcrel12 (offset));
1342 return 2;
1343 }
1344
1345 static int
1346 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1347 {
1348 /* REGMV
1349 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1350 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1351 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1352 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1353 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1354 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1355 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1356
1357 if (!((IS_GENREG (gd, dst) && IS_GENREG (gs, src))
1358 || (IS_GENREG (gd, dst) && IS_DAGREG (gs, src))
1359 || (IS_DAGREG (gd, dst) && IS_GENREG (gs, src))
1360 || (IS_DAGREG (gd, dst) && IS_DAGREG (gs, src))
1361 || (IS_GENREG (gd, dst) && gs == 7 && src == 0)
1362 || (gd == 7 && dst == 0 && IS_GENREG (gs, src))
1363 || (IS_DREG (gd, dst) && IS_SYSREG (gs, src))
1364 || (IS_PREG (gd, dst) && IS_SYSREG (gs, src))
1365 || (IS_SYSREG (gd, dst) && IS_DREG (gs, src))
1366 || (IS_SYSREG (gd, dst) && IS_PREG (gs, src))
1367 || (IS_SYSREG (gd, dst) && gs == 7 && src == 0)))
1368 return 0;
1369
1370 OUTS (outf, allregs (dst, gd));
1371 OUTS (outf, " = ");
1372 OUTS (outf, allregs (src, gs));
1373 return 2;
1374 }
1375
1376 static int
1377 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1378 {
1379 /* ALU2op
1380 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1381 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1382 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1383 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1384 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1385 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1386
1387 if (opc == 0)
1388 {
1389 OUTS (outf, dregs (dst));
1390 OUTS (outf, " >>>= ");
1391 OUTS (outf, dregs (src));
1392 }
1393 else if (opc == 1)
1394 {
1395 OUTS (outf, dregs (dst));
1396 OUTS (outf, " >>= ");
1397 OUTS (outf, dregs (src));
1398 }
1399 else if (opc == 2)
1400 {
1401 OUTS (outf, dregs (dst));
1402 OUTS (outf, " <<= ");
1403 OUTS (outf, dregs (src));
1404 }
1405 else if (opc == 3)
1406 {
1407 OUTS (outf, dregs (dst));
1408 OUTS (outf, " *= ");
1409 OUTS (outf, dregs (src));
1410 }
1411 else if (opc == 4)
1412 {
1413 OUTS (outf, dregs (dst));
1414 OUTS (outf, " = (");
1415 OUTS (outf, dregs (dst));
1416 OUTS (outf, " + ");
1417 OUTS (outf, dregs (src));
1418 OUTS (outf, ") << 0x1");
1419 }
1420 else if (opc == 5)
1421 {
1422 OUTS (outf, dregs (dst));
1423 OUTS (outf, " = (");
1424 OUTS (outf, dregs (dst));
1425 OUTS (outf, " + ");
1426 OUTS (outf, dregs (src));
1427 OUTS (outf, ") << 0x2");
1428 }
1429 else if (opc == 8)
1430 {
1431 OUTS (outf, "DIVQ (");
1432 OUTS (outf, dregs (dst));
1433 OUTS (outf, ", ");
1434 OUTS (outf, dregs (src));
1435 OUTS (outf, ")");
1436 }
1437 else if (opc == 9)
1438 {
1439 OUTS (outf, "DIVS (");
1440 OUTS (outf, dregs (dst));
1441 OUTS (outf, ", ");
1442 OUTS (outf, dregs (src));
1443 OUTS (outf, ")");
1444 }
1445 else if (opc == 10)
1446 {
1447 OUTS (outf, dregs (dst));
1448 OUTS (outf, " = ");
1449 OUTS (outf, dregs_lo (src));
1450 OUTS (outf, " (X)");
1451 }
1452 else if (opc == 11)
1453 {
1454 OUTS (outf, dregs (dst));
1455 OUTS (outf, " = ");
1456 OUTS (outf, dregs_lo (src));
1457 OUTS (outf, " (Z)");
1458 }
1459 else if (opc == 12)
1460 {
1461 OUTS (outf, dregs (dst));
1462 OUTS (outf, " = ");
1463 OUTS (outf, dregs_byte (src));
1464 OUTS (outf, " (X)");
1465 }
1466 else if (opc == 13)
1467 {
1468 OUTS (outf, dregs (dst));
1469 OUTS (outf, " = ");
1470 OUTS (outf, dregs_byte (src));
1471 OUTS (outf, " (Z)");
1472 }
1473 else if (opc == 14)
1474 {
1475 OUTS (outf, dregs (dst));
1476 OUTS (outf, " = -");
1477 OUTS (outf, dregs (src));
1478 }
1479 else if (opc == 15)
1480 {
1481 OUTS (outf, dregs (dst));
1482 OUTS (outf, " =~ ");
1483 OUTS (outf, dregs (src));
1484 }
1485 else
1486 return 0;
1487
1488 return 2;
1489 }
1490
1491 static int
1492 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1493 {
1494 /* PTR2op
1495 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1496 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1497 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1498 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1499 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1500 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1501
1502 if (opc == 0)
1503 {
1504 OUTS (outf, pregs (dst));
1505 OUTS (outf, " -= ");
1506 OUTS (outf, pregs (src));
1507 }
1508 else if (opc == 1)
1509 {
1510 OUTS (outf, pregs (dst));
1511 OUTS (outf, " = ");
1512 OUTS (outf, pregs (src));
1513 OUTS (outf, " << 0x2");
1514 }
1515 else if (opc == 3)
1516 {
1517 OUTS (outf, pregs (dst));
1518 OUTS (outf, " = ");
1519 OUTS (outf, pregs (src));
1520 OUTS (outf, " >> 0x2");
1521 }
1522 else if (opc == 4)
1523 {
1524 OUTS (outf, pregs (dst));
1525 OUTS (outf, " = ");
1526 OUTS (outf, pregs (src));
1527 OUTS (outf, " >> 0x1");
1528 }
1529 else if (opc == 5)
1530 {
1531 OUTS (outf, pregs (dst));
1532 OUTS (outf, " += ");
1533 OUTS (outf, pregs (src));
1534 OUTS (outf, " (BREV)");
1535 }
1536 else if (opc == 6)
1537 {
1538 OUTS (outf, pregs (dst));
1539 OUTS (outf, " = (");
1540 OUTS (outf, pregs (dst));
1541 OUTS (outf, " + ");
1542 OUTS (outf, pregs (src));
1543 OUTS (outf, ") << 0x1");
1544 }
1545 else if (opc == 7)
1546 {
1547 OUTS (outf, pregs (dst));
1548 OUTS (outf, " = (");
1549 OUTS (outf, pregs (dst));
1550 OUTS (outf, " + ");
1551 OUTS (outf, pregs (src));
1552 OUTS (outf, ") << 0x2");
1553 }
1554 else
1555 return 0;
1556
1557 return 2;
1558 }
1559
1560 static int
1561 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1562 {
1563 /* LOGI2op
1564 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1565 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1566 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1567 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1568 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1569 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1570
1571 if (opc == 0)
1572 {
1573 OUTS (outf, "CC = !BITTST (");
1574 OUTS (outf, dregs (dst));
1575 OUTS (outf, ", ");
1576 OUTS (outf, uimm5 (src));
1577 OUTS (outf, ");\t\t/* bit");
1578 OUTS (outf, imm7d (src));
1579 OUTS (outf, " */");
1580 comment = 1;
1581 }
1582 else if (opc == 1)
1583 {
1584 OUTS (outf, "CC = BITTST (");
1585 OUTS (outf, dregs (dst));
1586 OUTS (outf, ", ");
1587 OUTS (outf, uimm5 (src));
1588 OUTS (outf, ");\t\t/* bit");
1589 OUTS (outf, imm7d (src));
1590 OUTS (outf, " */");
1591 comment = 1;
1592 }
1593 else if (opc == 2)
1594 {
1595 OUTS (outf, "BITSET (");
1596 OUTS (outf, dregs (dst));
1597 OUTS (outf, ", ");
1598 OUTS (outf, uimm5 (src));
1599 OUTS (outf, ");\t\t/* bit");
1600 OUTS (outf, imm7d (src));
1601 OUTS (outf, " */");
1602 comment = 1;
1603 }
1604 else if (opc == 3)
1605 {
1606 OUTS (outf, "BITTGL (");
1607 OUTS (outf, dregs (dst));
1608 OUTS (outf, ", ");
1609 OUTS (outf, uimm5 (src));
1610 OUTS (outf, ");\t\t/* bit");
1611 OUTS (outf, imm7d (src));
1612 OUTS (outf, " */");
1613 comment = 1;
1614 }
1615 else if (opc == 4)
1616 {
1617 OUTS (outf, "BITCLR (");
1618 OUTS (outf, dregs (dst));
1619 OUTS (outf, ", ");
1620 OUTS (outf, uimm5 (src));
1621 OUTS (outf, ");\t\t/* bit");
1622 OUTS (outf, imm7d (src));
1623 OUTS (outf, " */");
1624 comment = 1;
1625 }
1626 else if (opc == 5)
1627 {
1628 OUTS (outf, dregs (dst));
1629 OUTS (outf, " >>>= ");
1630 OUTS (outf, uimm5 (src));
1631 }
1632 else if (opc == 6)
1633 {
1634 OUTS (outf, dregs (dst));
1635 OUTS (outf, " >>= ");
1636 OUTS (outf, uimm5 (src));
1637 }
1638 else if (opc == 7)
1639 {
1640 OUTS (outf, dregs (dst));
1641 OUTS (outf, " <<= ");
1642 OUTS (outf, uimm5 (src));
1643 }
1644 else
1645 return 0;
1646
1647 return 2;
1648 }
1649
1650 static int
1651 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1652 {
1653 /* COMP3op
1654 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1655 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1656 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1657 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1658 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1659 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1660 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1661
1662 if (opc == 5 && src1 == src0)
1663 {
1664 OUTS (outf, pregs (dst));
1665 OUTS (outf, " = ");
1666 OUTS (outf, pregs (src0));
1667 OUTS (outf, " << 0x1");
1668 }
1669 else if (opc == 1)
1670 {
1671 OUTS (outf, dregs (dst));
1672 OUTS (outf, " = ");
1673 OUTS (outf, dregs (src0));
1674 OUTS (outf, " - ");
1675 OUTS (outf, dregs (src1));
1676 }
1677 else if (opc == 2)
1678 {
1679 OUTS (outf, dregs (dst));
1680 OUTS (outf, " = ");
1681 OUTS (outf, dregs (src0));
1682 OUTS (outf, " & ");
1683 OUTS (outf, dregs (src1));
1684 }
1685 else if (opc == 3)
1686 {
1687 OUTS (outf, dregs (dst));
1688 OUTS (outf, " = ");
1689 OUTS (outf, dregs (src0));
1690 OUTS (outf, " | ");
1691 OUTS (outf, dregs (src1));
1692 }
1693 else if (opc == 4)
1694 {
1695 OUTS (outf, dregs (dst));
1696 OUTS (outf, " = ");
1697 OUTS (outf, dregs (src0));
1698 OUTS (outf, " ^ ");
1699 OUTS (outf, dregs (src1));
1700 }
1701 else if (opc == 5)
1702 {
1703 OUTS (outf, pregs (dst));
1704 OUTS (outf, " = ");
1705 OUTS (outf, pregs (src0));
1706 OUTS (outf, " + ");
1707 OUTS (outf, pregs (src1));
1708 }
1709 else if (opc == 6)
1710 {
1711 OUTS (outf, pregs (dst));
1712 OUTS (outf, " = ");
1713 OUTS (outf, pregs (src0));
1714 OUTS (outf, " + (");
1715 OUTS (outf, pregs (src1));
1716 OUTS (outf, " << 0x1)");
1717 }
1718 else if (opc == 7)
1719 {
1720 OUTS (outf, pregs (dst));
1721 OUTS (outf, " = ");
1722 OUTS (outf, pregs (src0));
1723 OUTS (outf, " + (");
1724 OUTS (outf, pregs (src1));
1725 OUTS (outf, " << 0x2)");
1726 }
1727 else if (opc == 0)
1728 {
1729 OUTS (outf, dregs (dst));
1730 OUTS (outf, " = ");
1731 OUTS (outf, dregs (src0));
1732 OUTS (outf, " + ");
1733 OUTS (outf, dregs (src1));
1734 }
1735 else
1736 return 0;
1737
1738 return 2;
1739 }
1740
1741 static int
1742 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1743 {
1744 /* COMPI2opD
1745 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1746 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1747 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1748 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1749 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1750 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1751
1752 bu32 *pval = get_allreg (0, dst);
1753
1754 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1755 to combine them, so it prints out the right values.
1756 Here we keep track of the registers. */
1757 if (op == 0)
1758 {
1759 *pval = imm7_val (src);
1760 if (src & 0x40)
1761 *pval |= 0xFFFFFF80;
1762 else
1763 *pval &= 0x7F;
1764 }
1765
1766 if (op == 0)
1767 {
1768 OUTS (outf, dregs (dst));
1769 OUTS (outf, " = ");
1770 OUTS (outf, imm7 (src));
1771 OUTS (outf, " (X);\t\t/*\t\t");
1772 OUTS (outf, dregs (dst));
1773 OUTS (outf, "=");
1774 OUTS (outf, uimm32 (*pval));
1775 OUTS (outf, "(");
1776 OUTS (outf, imm32 (*pval));
1777 OUTS (outf, ") */");
1778 comment = 1;
1779 }
1780 else if (op == 1)
1781 {
1782 OUTS (outf, dregs (dst));
1783 OUTS (outf, " += ");
1784 OUTS (outf, imm7 (src));
1785 OUTS (outf, ";\t\t/* (");
1786 OUTS (outf, imm7d (src));
1787 OUTS (outf, ") */");
1788 comment = 1;
1789 }
1790 else
1791 return 0;
1792
1793 return 2;
1794 }
1795
1796 static int
1797 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1798 {
1799 /* COMPI2opP
1800 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1801 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1802 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1803 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1804 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1805 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1806
1807 bu32 *pval = get_allreg (1, dst);
1808
1809 if (op == 0)
1810 {
1811 *pval = imm7_val (src);
1812 if (src & 0x40)
1813 *pval |= 0xFFFFFF80;
1814 else
1815 *pval &= 0x7F;
1816 }
1817
1818 if (op == 0)
1819 {
1820 OUTS (outf, pregs (dst));
1821 OUTS (outf, " = ");
1822 OUTS (outf, imm7 (src));
1823 OUTS (outf, " (X);\t\t/*\t\t");
1824 OUTS (outf, pregs (dst));
1825 OUTS (outf, "=");
1826 OUTS (outf, uimm32 (*pval));
1827 OUTS (outf, "(");
1828 OUTS (outf, imm32 (*pval));
1829 OUTS (outf, ") */");
1830 comment = 1;
1831 }
1832 else if (op == 1)
1833 {
1834 OUTS (outf, pregs (dst));
1835 OUTS (outf, " += ");
1836 OUTS (outf, imm7 (src));
1837 OUTS (outf, ";\t\t/* (");
1838 OUTS (outf, imm7d (src));
1839 OUTS (outf, ") */");
1840 comment = 1;
1841 }
1842 else
1843 return 0;
1844
1845 return 2;
1846 }
1847
1848 static int
1849 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1850 {
1851 /* LDSTpmod
1852 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1853 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1854 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1855 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1856 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1857 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1858 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1859 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1860
1861 if (aop == 1 && W == 0 && idx == ptr)
1862 {
1863 OUTS (outf, dregs_lo (reg));
1864 OUTS (outf, " = W[");
1865 OUTS (outf, pregs (ptr));
1866 OUTS (outf, "]");
1867 }
1868 else if (aop == 2 && W == 0 && idx == ptr)
1869 {
1870 OUTS (outf, dregs_hi (reg));
1871 OUTS (outf, " = W[");
1872 OUTS (outf, pregs (ptr));
1873 OUTS (outf, "]");
1874 }
1875 else if (aop == 1 && W == 1 && idx == ptr)
1876 {
1877 OUTS (outf, "W[");
1878 OUTS (outf, pregs (ptr));
1879 OUTS (outf, "] = ");
1880 OUTS (outf, dregs_lo (reg));
1881 }
1882 else if (aop == 2 && W == 1 && idx == ptr)
1883 {
1884 OUTS (outf, "W[");
1885 OUTS (outf, pregs (ptr));
1886 OUTS (outf, "] = ");
1887 OUTS (outf, dregs_hi (reg));
1888 }
1889 else if (aop == 0 && W == 0)
1890 {
1891 OUTS (outf, dregs (reg));
1892 OUTS (outf, " = [");
1893 OUTS (outf, pregs (ptr));
1894 OUTS (outf, " ++ ");
1895 OUTS (outf, pregs (idx));
1896 OUTS (outf, "]");
1897 }
1898 else if (aop == 1 && W == 0)
1899 {
1900 OUTS (outf, dregs_lo (reg));
1901 OUTS (outf, " = W[");
1902 OUTS (outf, pregs (ptr));
1903 OUTS (outf, " ++ ");
1904 OUTS (outf, pregs (idx));
1905 OUTS (outf, "]");
1906 }
1907 else if (aop == 2 && W == 0)
1908 {
1909 OUTS (outf, dregs_hi (reg));
1910 OUTS (outf, " = W[");
1911 OUTS (outf, pregs (ptr));
1912 OUTS (outf, " ++ ");
1913 OUTS (outf, pregs (idx));
1914 OUTS (outf, "]");
1915 }
1916 else if (aop == 3 && W == 0)
1917 {
1918 OUTS (outf, dregs (reg));
1919 OUTS (outf, " = W[");
1920 OUTS (outf, pregs (ptr));
1921 OUTS (outf, " ++ ");
1922 OUTS (outf, pregs (idx));
1923 OUTS (outf, "] (Z)");
1924 }
1925 else if (aop == 3 && W == 1)
1926 {
1927 OUTS (outf, dregs (reg));
1928 OUTS (outf, " = W[");
1929 OUTS (outf, pregs (ptr));
1930 OUTS (outf, " ++ ");
1931 OUTS (outf, pregs (idx));
1932 OUTS (outf, "] (X)");
1933 }
1934 else if (aop == 0 && W == 1)
1935 {
1936 OUTS (outf, "[");
1937 OUTS (outf, pregs (ptr));
1938 OUTS (outf, " ++ ");
1939 OUTS (outf, pregs (idx));
1940 OUTS (outf, "] = ");
1941 OUTS (outf, dregs (reg));
1942 }
1943 else if (aop == 1 && W == 1)
1944 {
1945 OUTS (outf, "W[");
1946 OUTS (outf, pregs (ptr));
1947 OUTS (outf, " ++ ");
1948 OUTS (outf, pregs (idx));
1949 OUTS (outf, "] = ");
1950 OUTS (outf, dregs_lo (reg));
1951 }
1952 else if (aop == 2 && W == 1)
1953 {
1954 OUTS (outf, "W[");
1955 OUTS (outf, pregs (ptr));
1956 OUTS (outf, " ++ ");
1957 OUTS (outf, pregs (idx));
1958 OUTS (outf, "] = ");
1959 OUTS (outf, dregs_hi (reg));
1960 }
1961 else
1962 return 0;
1963
1964 return 2;
1965 }
1966
1967 static int
1968 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1969 {
1970 /* dagMODim
1971 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1972 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1973 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1974 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1975 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1976 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1977 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
1978
1979 if (op == 0 && br == 1)
1980 {
1981 OUTS (outf, iregs (i));
1982 OUTS (outf, " += ");
1983 OUTS (outf, mregs (m));
1984 OUTS (outf, " (BREV)");
1985 }
1986 else if (op == 0)
1987 {
1988 OUTS (outf, iregs (i));
1989 OUTS (outf, " += ");
1990 OUTS (outf, mregs (m));
1991 }
1992 else if (op == 1)
1993 {
1994 OUTS (outf, iregs (i));
1995 OUTS (outf, " -= ");
1996 OUTS (outf, mregs (m));
1997 }
1998 else
1999 return 0;
2000
2001 return 2;
2002 }
2003
2004 static int
2005 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2006 {
2007 /* dagMODik
2008 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2009 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2010 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2011 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2012 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2013
2014 if (op == 0)
2015 {
2016 OUTS (outf, iregs (i));
2017 OUTS (outf, " += 0x2");
2018 }
2019 else if (op == 1)
2020 {
2021 OUTS (outf, iregs (i));
2022 OUTS (outf, " -= 0x2");
2023 }
2024 else if (op == 2)
2025 {
2026 OUTS (outf, iregs (i));
2027 OUTS (outf, " += 0x4");
2028 }
2029 else if (op == 3)
2030 {
2031 OUTS (outf, iregs (i));
2032 OUTS (outf, " -= 0x4");
2033 }
2034 else
2035 return 0;
2036
2037 if (! parallel )
2038 {
2039 OUTS (outf, ";\t\t/* ( ");
2040 if (op == 0 || op == 1)
2041 OUTS (outf, "2");
2042 else if (op == 2 || op == 3)
2043 OUTS (outf, "4");
2044 OUTS (outf, ") */");
2045 comment = 1;
2046 }
2047
2048 return 2;
2049 }
2050
2051 static int
2052 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2053 {
2054 /* dspLDST
2055 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2056 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2057 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2058 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2059 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2060 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2061 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2062 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2063
2064 if (aop == 0 && W == 0 && m == 0)
2065 {
2066 OUTS (outf, dregs (reg));
2067 OUTS (outf, " = [");
2068 OUTS (outf, iregs (i));
2069 OUTS (outf, "++]");
2070 }
2071 else if (aop == 0 && W == 0 && m == 1)
2072 {
2073 OUTS (outf, dregs_lo (reg));
2074 OUTS (outf, " = W[");
2075 OUTS (outf, iregs (i));
2076 OUTS (outf, "++]");
2077 }
2078 else if (aop == 0 && W == 0 && m == 2)
2079 {
2080 OUTS (outf, dregs_hi (reg));
2081 OUTS (outf, " = W[");
2082 OUTS (outf, iregs (i));
2083 OUTS (outf, "++]");
2084 }
2085 else if (aop == 1 && W == 0 && m == 0)
2086 {
2087 OUTS (outf, dregs (reg));
2088 OUTS (outf, " = [");
2089 OUTS (outf, iregs (i));
2090 OUTS (outf, "--]");
2091 }
2092 else if (aop == 1 && W == 0 && m == 1)
2093 {
2094 OUTS (outf, dregs_lo (reg));
2095 OUTS (outf, " = W[");
2096 OUTS (outf, iregs (i));
2097 OUTS (outf, "--]");
2098 }
2099 else if (aop == 1 && W == 0 && m == 2)
2100 {
2101 OUTS (outf, dregs_hi (reg));
2102 OUTS (outf, " = W[");
2103 OUTS (outf, iregs (i));
2104 OUTS (outf, "--]");
2105 }
2106 else if (aop == 2 && W == 0 && m == 0)
2107 {
2108 OUTS (outf, dregs (reg));
2109 OUTS (outf, " = [");
2110 OUTS (outf, iregs (i));
2111 OUTS (outf, "]");
2112 }
2113 else if (aop == 2 && W == 0 && m == 1)
2114 {
2115 OUTS (outf, dregs_lo (reg));
2116 OUTS (outf, " = W[");
2117 OUTS (outf, iregs (i));
2118 OUTS (outf, "]");
2119 }
2120 else if (aop == 2 && W == 0 && m == 2)
2121 {
2122 OUTS (outf, dregs_hi (reg));
2123 OUTS (outf, " = W[");
2124 OUTS (outf, iregs (i));
2125 OUTS (outf, "]");
2126 }
2127 else if (aop == 0 && W == 1 && m == 0)
2128 {
2129 OUTS (outf, "[");
2130 OUTS (outf, iregs (i));
2131 OUTS (outf, "++] = ");
2132 OUTS (outf, dregs (reg));
2133 }
2134 else if (aop == 0 && W == 1 && m == 1)
2135 {
2136 OUTS (outf, "W[");
2137 OUTS (outf, iregs (i));
2138 OUTS (outf, "++] = ");
2139 OUTS (outf, dregs_lo (reg));
2140 }
2141 else if (aop == 0 && W == 1 && m == 2)
2142 {
2143 OUTS (outf, "W[");
2144 OUTS (outf, iregs (i));
2145 OUTS (outf, "++] = ");
2146 OUTS (outf, dregs_hi (reg));
2147 }
2148 else if (aop == 1 && W == 1 && m == 0)
2149 {
2150 OUTS (outf, "[");
2151 OUTS (outf, iregs (i));
2152 OUTS (outf, "--] = ");
2153 OUTS (outf, dregs (reg));
2154 }
2155 else if (aop == 1 && W == 1 && m == 1)
2156 {
2157 OUTS (outf, "W[");
2158 OUTS (outf, iregs (i));
2159 OUTS (outf, "--] = ");
2160 OUTS (outf, dregs_lo (reg));
2161 }
2162 else if (aop == 1 && W == 1 && m == 2)
2163 {
2164 OUTS (outf, "W[");
2165 OUTS (outf, iregs (i));
2166 OUTS (outf, "--] = ");
2167 OUTS (outf, dregs_hi (reg));
2168 }
2169 else if (aop == 2 && W == 1 && m == 0)
2170 {
2171 OUTS (outf, "[");
2172 OUTS (outf, iregs (i));
2173 OUTS (outf, "] = ");
2174 OUTS (outf, dregs (reg));
2175 }
2176 else if (aop == 2 && W == 1 && m == 1)
2177 {
2178 OUTS (outf, "W[");
2179 OUTS (outf, iregs (i));
2180 OUTS (outf, "] = ");
2181 OUTS (outf, dregs_lo (reg));
2182 }
2183 else if (aop == 2 && W == 1 && m == 2)
2184 {
2185 OUTS (outf, "W[");
2186 OUTS (outf, iregs (i));
2187 OUTS (outf, "] = ");
2188 OUTS (outf, dregs_hi (reg));
2189 }
2190 else if (aop == 3 && W == 0)
2191 {
2192 OUTS (outf, dregs (reg));
2193 OUTS (outf, " = [");
2194 OUTS (outf, iregs (i));
2195 OUTS (outf, " ++ ");
2196 OUTS (outf, mregs (m));
2197 OUTS (outf, "]");
2198 }
2199 else if (aop == 3 && W == 1)
2200 {
2201 OUTS (outf, "[");
2202 OUTS (outf, iregs (i));
2203 OUTS (outf, " ++ ");
2204 OUTS (outf, mregs (m));
2205 OUTS (outf, "] = ");
2206 OUTS (outf, dregs (reg));
2207 }
2208 else
2209 return 0;
2210
2211 return 2;
2212 }
2213
2214 static int
2215 decode_LDST_0 (TIword iw0, disassemble_info *outf)
2216 {
2217 /* LDST
2218 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2219 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2220 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2221 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2222 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2223 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2224 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2225 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2226 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2227
2228 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2229 {
2230 OUTS (outf, dregs (reg));
2231 OUTS (outf, " = [");
2232 OUTS (outf, pregs (ptr));
2233 OUTS (outf, "++]");
2234 }
2235 else if (aop == 0 && sz == 0 && Z == 1 && W == 0)
2236 {
2237 OUTS (outf, pregs (reg));
2238 OUTS (outf, " = [");
2239 OUTS (outf, pregs (ptr));
2240 OUTS (outf, "++]");
2241 }
2242 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2243 {
2244 OUTS (outf, dregs (reg));
2245 OUTS (outf, " = W[");
2246 OUTS (outf, pregs (ptr));
2247 OUTS (outf, "++] (Z)");
2248 }
2249 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2250 {
2251 OUTS (outf, dregs (reg));
2252 OUTS (outf, " = W[");
2253 OUTS (outf, pregs (ptr));
2254 OUTS (outf, "++] (X)");
2255 }
2256 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2257 {
2258 OUTS (outf, dregs (reg));
2259 OUTS (outf, " = B[");
2260 OUTS (outf, pregs (ptr));
2261 OUTS (outf, "++] (Z)");
2262 }
2263 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2264 {
2265 OUTS (outf, dregs (reg));
2266 OUTS (outf, " = B[");
2267 OUTS (outf, pregs (ptr));
2268 OUTS (outf, "++] (X)");
2269 }
2270 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2271 {
2272 OUTS (outf, dregs (reg));
2273 OUTS (outf, " = [");
2274 OUTS (outf, pregs (ptr));
2275 OUTS (outf, "--]");
2276 }
2277 else if (aop == 1 && sz == 0 && Z == 1 && W == 0)
2278 {
2279 OUTS (outf, pregs (reg));
2280 OUTS (outf, " = [");
2281 OUTS (outf, pregs (ptr));
2282 OUTS (outf, "--]");
2283 }
2284 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2285 {
2286 OUTS (outf, dregs (reg));
2287 OUTS (outf, " = W[");
2288 OUTS (outf, pregs (ptr));
2289 OUTS (outf, "--] (Z)");
2290 }
2291 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2292 {
2293 OUTS (outf, dregs (reg));
2294 OUTS (outf, " = W[");
2295 OUTS (outf, pregs (ptr));
2296 OUTS (outf, "--] (X)");
2297 }
2298 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2299 {
2300 OUTS (outf, dregs (reg));
2301 OUTS (outf, " = B[");
2302 OUTS (outf, pregs (ptr));
2303 OUTS (outf, "--] (Z)");
2304 }
2305 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2306 {
2307 OUTS (outf, dregs (reg));
2308 OUTS (outf, " = B[");
2309 OUTS (outf, pregs (ptr));
2310 OUTS (outf, "--] (X)");
2311 }
2312 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2313 {
2314 OUTS (outf, dregs (reg));
2315 OUTS (outf, " = [");
2316 OUTS (outf, pregs (ptr));
2317 OUTS (outf, "]");
2318 }
2319 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2320 {
2321 OUTS (outf, pregs (reg));
2322 OUTS (outf, " = [");
2323 OUTS (outf, pregs (ptr));
2324 OUTS (outf, "]");
2325 }
2326 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2327 {
2328 OUTS (outf, dregs (reg));
2329 OUTS (outf, " = W[");
2330 OUTS (outf, pregs (ptr));
2331 OUTS (outf, "] (Z)");
2332 }
2333 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2334 {
2335 OUTS (outf, dregs (reg));
2336 OUTS (outf, " = W[");
2337 OUTS (outf, pregs (ptr));
2338 OUTS (outf, "] (X)");
2339 }
2340 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2341 {
2342 OUTS (outf, dregs (reg));
2343 OUTS (outf, " = B[");
2344 OUTS (outf, pregs (ptr));
2345 OUTS (outf, "] (Z)");
2346 }
2347 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2348 {
2349 OUTS (outf, dregs (reg));
2350 OUTS (outf, " = B[");
2351 OUTS (outf, pregs (ptr));
2352 OUTS (outf, "] (X)");
2353 }
2354 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2355 {
2356 OUTS (outf, "[");
2357 OUTS (outf, pregs (ptr));
2358 OUTS (outf, "++] = ");
2359 OUTS (outf, dregs (reg));
2360 }
2361 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2362 {
2363 OUTS (outf, "[");
2364 OUTS (outf, pregs (ptr));
2365 OUTS (outf, "++] = ");
2366 OUTS (outf, pregs (reg));
2367 }
2368 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2369 {
2370 OUTS (outf, "W[");
2371 OUTS (outf, pregs (ptr));
2372 OUTS (outf, "++] = ");
2373 OUTS (outf, dregs (reg));
2374 }
2375 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2376 {
2377 OUTS (outf, "B[");
2378 OUTS (outf, pregs (ptr));
2379 OUTS (outf, "++] = ");
2380 OUTS (outf, dregs (reg));
2381 }
2382 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2383 {
2384 OUTS (outf, "[");
2385 OUTS (outf, pregs (ptr));
2386 OUTS (outf, "--] = ");
2387 OUTS (outf, dregs (reg));
2388 }
2389 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2390 {
2391 OUTS (outf, "[");
2392 OUTS (outf, pregs (ptr));
2393 OUTS (outf, "--] = ");
2394 OUTS (outf, pregs (reg));
2395 }
2396 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2397 {
2398 OUTS (outf, "W[");
2399 OUTS (outf, pregs (ptr));
2400 OUTS (outf, "--] = ");
2401 OUTS (outf, dregs (reg));
2402 }
2403 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2404 {
2405 OUTS (outf, "B[");
2406 OUTS (outf, pregs (ptr));
2407 OUTS (outf, "--] = ");
2408 OUTS (outf, dregs (reg));
2409 }
2410 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2411 {
2412 OUTS (outf, "[");
2413 OUTS (outf, pregs (ptr));
2414 OUTS (outf, "] = ");
2415 OUTS (outf, dregs (reg));
2416 }
2417 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2418 {
2419 OUTS (outf, "[");
2420 OUTS (outf, pregs (ptr));
2421 OUTS (outf, "] = ");
2422 OUTS (outf, pregs (reg));
2423 }
2424 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2425 {
2426 OUTS (outf, "W[");
2427 OUTS (outf, pregs (ptr));
2428 OUTS (outf, "] = ");
2429 OUTS (outf, dregs (reg));
2430 }
2431 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2432 {
2433 OUTS (outf, "B[");
2434 OUTS (outf, pregs (ptr));
2435 OUTS (outf, "] = ");
2436 OUTS (outf, dregs (reg));
2437 }
2438 else
2439 return 0;
2440
2441 return 2;
2442 }
2443
2444 static int
2445 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2446 {
2447 /* LDSTiiFP
2448 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2449 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2450 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2451 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2452 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2453 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2454
2455 if (W == 0)
2456 {
2457 OUTS (outf, dpregs (reg));
2458 OUTS (outf, " = [FP ");
2459 OUTS (outf, negimm5s4 (offset));
2460 OUTS (outf, "]");
2461 }
2462 else if (W == 1)
2463 {
2464 OUTS (outf, "[FP ");
2465 OUTS (outf, negimm5s4 (offset));
2466 OUTS (outf, "] = ");
2467 OUTS (outf, dpregs (reg));
2468 }
2469 else
2470 return 0;
2471
2472 return 2;
2473 }
2474
2475 static int
2476 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2477 {
2478 /* LDSTii
2479 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2480 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2481 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2482 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2483 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2484 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2485 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2486 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2487
2488 if (W == 0 && op == 0)
2489 {
2490 OUTS (outf, dregs (reg));
2491 OUTS (outf, " = [");
2492 OUTS (outf, pregs (ptr));
2493 OUTS (outf, " + ");
2494 OUTS (outf, uimm4s4 (offset));
2495 OUTS (outf, "]");
2496 }
2497 else if (W == 0 && op == 1)
2498 {
2499 OUTS (outf, dregs (reg));
2500 OUTS (outf, " = W[");
2501 OUTS (outf, pregs (ptr));
2502 OUTS (outf, " + ");
2503 OUTS (outf, uimm4s2 (offset));
2504 OUTS (outf, "] (Z)");
2505 }
2506 else if (W == 0 && op == 2)
2507 {
2508 OUTS (outf, dregs (reg));
2509 OUTS (outf, " = W[");
2510 OUTS (outf, pregs (ptr));
2511 OUTS (outf, " + ");
2512 OUTS (outf, uimm4s2 (offset));
2513 OUTS (outf, "] (X)");
2514 }
2515 else if (W == 0 && op == 3)
2516 {
2517 OUTS (outf, pregs (reg));
2518 OUTS (outf, " = [");
2519 OUTS (outf, pregs (ptr));
2520 OUTS (outf, " + ");
2521 OUTS (outf, uimm4s4 (offset));
2522 OUTS (outf, "]");
2523 }
2524 else if (W == 1 && op == 0)
2525 {
2526 OUTS (outf, "[");
2527 OUTS (outf, pregs (ptr));
2528 OUTS (outf, " + ");
2529 OUTS (outf, uimm4s4 (offset));
2530 OUTS (outf, "] = ");
2531 OUTS (outf, dregs (reg));
2532 }
2533 else if (W == 1 && op == 1)
2534 {
2535 OUTS (outf, "W[");
2536 OUTS (outf, pregs (ptr));
2537 OUTS (outf, " + ");
2538 OUTS (outf, uimm4s2 (offset));
2539 OUTS (outf, "] = ");
2540 OUTS (outf, dregs (reg));
2541 }
2542 else if (W == 1 && op == 3)
2543 {
2544 OUTS (outf, "[");
2545 OUTS (outf, pregs (ptr));
2546 OUTS (outf, " + ");
2547 OUTS (outf, uimm4s4 (offset));
2548 OUTS (outf, "] = ");
2549 OUTS (outf, pregs (reg));
2550 }
2551 else
2552 return 0;
2553
2554 return 2;
2555 }
2556
2557 static int
2558 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2559 {
2560 /* LoopSetup
2561 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2562 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2563 |.reg...........| - | - |.eoffset...............................|
2564 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2565 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2566 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2567 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2568 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2569 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2570
2571 if (rop == 0)
2572 {
2573 OUTS (outf, "LSETUP");
2574 OUTS (outf, "(0x");
2575 OUTS (outf, pcrel4 (soffset));
2576 OUTS (outf, ", 0x");
2577 OUTS (outf, lppcrel10 (eoffset));
2578 OUTS (outf, ") ");
2579 OUTS (outf, counters (c));
2580 }
2581 else if (rop == 1)
2582 {
2583 OUTS (outf, "LSETUP");
2584 OUTS (outf, "(0x");
2585 OUTS (outf, pcrel4 (soffset));
2586 OUTS (outf, ", 0x");
2587 OUTS (outf, lppcrel10 (eoffset));
2588 OUTS (outf, ") ");
2589 OUTS (outf, counters (c));
2590 OUTS (outf, " = ");
2591 OUTS (outf, pregs (reg));
2592 }
2593 else if (rop == 3)
2594 {
2595 OUTS (outf, "LSETUP");
2596 OUTS (outf, "(0x");
2597 OUTS (outf, pcrel4 (soffset));
2598 OUTS (outf, ", 0x");
2599 OUTS (outf, lppcrel10 (eoffset));
2600 OUTS (outf, ") ");
2601 OUTS (outf, counters (c));
2602 OUTS (outf, " = ");
2603 OUTS (outf, pregs (reg));
2604 OUTS (outf, " >> 0x1");
2605 }
2606 else
2607 return 0;
2608
2609 return 4;
2610 }
2611
2612 static int
2613 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2614 {
2615 /* LDIMMhalf
2616 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2617 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2618 |.hword.........................................................|
2619 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2620 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2621 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2622 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2623 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2624 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2625 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2626
2627 bu32 *pval = get_allreg (grp, reg);
2628
2629 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2630 to combine them, so it prints out the right values.
2631 Here we keep track of the registers. */
2632 if (H == 0 && S == 1 && Z == 0)
2633 {
2634 /* regs = imm16 (x) */
2635 *pval = imm16_val (hword);
2636 if (hword & 0x8000)
2637 *pval |= 0xFFFF0000;
2638 else
2639 *pval &= 0xFFFF;
2640 }
2641 else if (H == 0 && S == 0 && Z == 1)
2642 {
2643 /* regs = luimm16 (Z) */
2644 *pval = luimm16_val (hword);
2645 *pval &= 0xFFFF;
2646 }
2647 else if (H == 0 && S == 0 && Z == 0)
2648 {
2649 /* regs_lo = luimm16 */
2650 *pval &= 0xFFFF0000;
2651 *pval |= luimm16_val (hword);
2652 }
2653 else if (H == 1 && S == 0 && Z == 0)
2654 {
2655 /* regs_hi = huimm16 */
2656 *pval &= 0xFFFF;
2657 *pval |= luimm16_val (hword) << 16;
2658 }
2659
2660 /* Here we do the disassembly */
2661 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2662 {
2663 OUTS (outf, dregs_lo (reg));
2664 OUTS (outf, " = ");
2665 OUTS (outf, uimm16 (hword));
2666 }
2667 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2668 {
2669 OUTS (outf, dregs_hi (reg));
2670 OUTS (outf, " = ");
2671 OUTS (outf, uimm16 (hword));
2672 }
2673 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2674 {
2675 OUTS (outf, dregs (reg));
2676 OUTS (outf, " = ");
2677 OUTS (outf, imm16 (hword));
2678 OUTS (outf, " (X)");
2679 }
2680 else if (H == 0 && S == 1 && Z == 0)
2681 {
2682 OUTS (outf, regs (reg, grp));
2683 OUTS (outf, " = ");
2684 OUTS (outf, imm16 (hword));
2685 OUTS (outf, " (X)");
2686 }
2687 else if (H == 0 && S == 0 && Z == 1)
2688 {
2689 OUTS (outf, regs (reg, grp));
2690 OUTS (outf, " = ");
2691 OUTS (outf, uimm16 (hword));
2692 OUTS (outf, " (Z)");
2693 }
2694 else if (H == 0 && S == 0 && Z == 0)
2695 {
2696 OUTS (outf, regs_lo (reg, grp));
2697 OUTS (outf, " = ");
2698 OUTS (outf, uimm16 (hword));
2699 }
2700 else if (H == 1 && S == 0 && Z == 0)
2701 {
2702 OUTS (outf, regs_hi (reg, grp));
2703 OUTS (outf, " = ");
2704 OUTS (outf, uimm16 (hword));
2705 }
2706 else
2707 return 0;
2708
2709 /* And we print out the 32-bit value if it is a pointer. */
2710 if (S == 0 && Z == 0)
2711 {
2712 OUTS (outf, ";\t\t/* (");
2713 OUTS (outf, imm16d (hword));
2714 OUTS (outf, ")\t");
2715
2716 /* If it is an MMR, don't print the symbol. */
2717 if (*pval < 0xFFC00000 && grp == 1)
2718 {
2719 OUTS (outf, regs (reg, grp));
2720 OUTS (outf, "=0x");
2721 OUTS (outf, huimm32e (*pval));
2722 }
2723 else
2724 {
2725 OUTS (outf, regs (reg, grp));
2726 OUTS (outf, "=0x");
2727 OUTS (outf, huimm32e (*pval));
2728 OUTS (outf, "(");
2729 OUTS (outf, imm32 (*pval));
2730 OUTS (outf, ")");
2731 }
2732
2733 OUTS (outf, " */");
2734 comment = 1;
2735 }
2736 if (S == 1 || Z == 1)
2737 {
2738 OUTS (outf, ";\t\t/*\t\t");
2739 OUTS (outf, regs (reg, grp));
2740 OUTS (outf, "=0x");
2741 OUTS (outf, huimm32e (*pval));
2742 OUTS (outf, "(");
2743 OUTS (outf, imm32 (*pval));
2744 OUTS (outf, ") */");
2745 comment = 1;
2746 }
2747 return 4;
2748 }
2749
2750 static int
2751 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2752 {
2753 /* CALLa
2754 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2755 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2756 |.lsw...........................................................|
2757 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2758 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2759 int lsw = ((iw1 >> 0) & 0xffff);
2760 int msw = ((iw0 >> 0) & 0xff);
2761
2762 if (S == 1)
2763 OUTS (outf, "CALL 0x");
2764 else if (S == 0)
2765 OUTS (outf, "JUMP.L 0x");
2766 else
2767 return 0;
2768
2769 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2770 return 4;
2771 }
2772
2773 static int
2774 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2775 {
2776 /* LDSTidxI
2777 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2778 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2779 |.offset........................................................|
2780 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2781 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2782 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2783 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2784 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2785 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2786 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2787
2788 if (W == 0 && sz == 0 && Z == 0)
2789 {
2790 OUTS (outf, dregs (reg));
2791 OUTS (outf, " = [");
2792 OUTS (outf, pregs (ptr));
2793 OUTS (outf, " + ");
2794 OUTS (outf, imm16s4 (offset));
2795 OUTS (outf, "]");
2796 }
2797 else if (W == 0 && sz == 0 && Z == 1)
2798 {
2799 OUTS (outf, pregs (reg));
2800 OUTS (outf, " = [");
2801 OUTS (outf, pregs (ptr));
2802 OUTS (outf, " + ");
2803 OUTS (outf, imm16s4 (offset));
2804 OUTS (outf, "]");
2805 }
2806 else if (W == 0 && sz == 1 && Z == 0)
2807 {
2808 OUTS (outf, dregs (reg));
2809 OUTS (outf, " = W[");
2810 OUTS (outf, pregs (ptr));
2811 OUTS (outf, " + ");
2812 OUTS (outf, imm16s2 (offset));
2813 OUTS (outf, "] (Z)");
2814 }
2815 else if (W == 0 && sz == 1 && Z == 1)
2816 {
2817 OUTS (outf, dregs (reg));
2818 OUTS (outf, " = W[");
2819 OUTS (outf, pregs (ptr));
2820 OUTS (outf, " + ");
2821 OUTS (outf, imm16s2 (offset));
2822 OUTS (outf, "] (X)");
2823 }
2824 else if (W == 0 && sz == 2 && Z == 0)
2825 {
2826 OUTS (outf, dregs (reg));
2827 OUTS (outf, " = B[");
2828 OUTS (outf, pregs (ptr));
2829 OUTS (outf, " + ");
2830 OUTS (outf, imm16 (offset));
2831 OUTS (outf, "] (Z)");
2832 }
2833 else if (W == 0 && sz == 2 && Z == 1)
2834 {
2835 OUTS (outf, dregs (reg));
2836 OUTS (outf, " = B[");
2837 OUTS (outf, pregs (ptr));
2838 OUTS (outf, " + ");
2839 OUTS (outf, imm16 (offset));
2840 OUTS (outf, "] (X)");
2841 }
2842 else if (W == 1 && sz == 0 && Z == 0)
2843 {
2844 OUTS (outf, "[");
2845 OUTS (outf, pregs (ptr));
2846 OUTS (outf, " + ");
2847 OUTS (outf, imm16s4 (offset));
2848 OUTS (outf, "] = ");
2849 OUTS (outf, dregs (reg));
2850 }
2851 else if (W == 1 && sz == 0 && Z == 1)
2852 {
2853 OUTS (outf, "[");
2854 OUTS (outf, pregs (ptr));
2855 OUTS (outf, " + ");
2856 OUTS (outf, imm16s4 (offset));
2857 OUTS (outf, "] = ");
2858 OUTS (outf, pregs (reg));
2859 }
2860 else if (W == 1 && sz == 1 && Z == 0)
2861 {
2862 OUTS (outf, "W[");
2863 OUTS (outf, pregs (ptr));
2864 OUTS (outf, " + ");
2865 OUTS (outf, imm16s2 (offset));
2866 OUTS (outf, "] = ");
2867 OUTS (outf, dregs (reg));
2868 }
2869 else if (W == 1 && sz == 2 && Z == 0)
2870 {
2871 OUTS (outf, "B[");
2872 OUTS (outf, pregs (ptr));
2873 OUTS (outf, " + ");
2874 OUTS (outf, imm16 (offset));
2875 OUTS (outf, "] = ");
2876 OUTS (outf, dregs (reg));
2877 }
2878 else
2879 return 0;
2880
2881 return 4;
2882 }
2883
2884 static int
2885 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2886 {
2887 /* linkage
2888 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2889 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2890 |.framesize.....................................................|
2891 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2892 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2893 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2894
2895 if (R == 0)
2896 {
2897 OUTS (outf, "LINK ");
2898 OUTS (outf, uimm16s4 (framesize));
2899 OUTS (outf, ";\t\t/* (");
2900 OUTS (outf, uimm16s4d (framesize));
2901 OUTS (outf, ") */");
2902 comment = 1;
2903 }
2904 else if (R == 1)
2905 OUTS (outf, "UNLINK");
2906 else
2907 return 0;
2908
2909 return 4;
2910 }
2911
2912 static int
2913 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2914 {
2915 /* dsp32mac
2916 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2917 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2918 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2919 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2920 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2921 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2922 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2923 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2924 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2925 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2926 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2927 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2928 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2929 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2930 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2931 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2932 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2933 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2934
2935 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2936 return 0;
2937
2938 if (op1 == 3 && MM)
2939 return 0;
2940
2941 if ((w1 || w0) && mmod == M_W32)
2942 return 0;
2943
2944 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2945 return 0;
2946
2947 if (w1 == 1 || op1 != 3)
2948 {
2949 if (w1)
2950 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2951
2952 if (op1 == 3)
2953 OUTS (outf, " = A1");
2954 else
2955 {
2956 if (w1)
2957 OUTS (outf, " = (");
2958 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2959 if (w1)
2960 OUTS (outf, ")");
2961 }
2962
2963 if (w0 == 1 || op0 != 3)
2964 {
2965 if (MM)
2966 OUTS (outf, " (M)");
2967 MM = 0;
2968 OUTS (outf, ", ");
2969 }
2970 }
2971
2972 if (w0 == 1 || op0 != 3)
2973 {
2974 if (w0)
2975 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
2976
2977 if (op0 == 3)
2978 OUTS (outf, " = A0");
2979 else
2980 {
2981 if (w0)
2982 OUTS (outf, " = (");
2983 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
2984 if (w0)
2985 OUTS (outf, ")");
2986 }
2987 }
2988
2989 decode_optmode (mmod, MM, outf);
2990
2991 return 4;
2992 }
2993
2994 static int
2995 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2996 {
2997 /* dsp32mult
2998 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2999 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3000 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3001 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3002 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3003 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3004 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
3005 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
3006 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3007 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3008 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3009 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3010 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3011 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3012 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3013 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3014
3015 if (w1 == 0 && w0 == 0)
3016 return 0;
3017
3018 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3019 return 0;
3020
3021 if (w1)
3022 {
3023 OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
3024 OUTS (outf, " = ");
3025 decode_multfunc (h01, h11, src0, src1, outf);
3026
3027 if (w0)
3028 {
3029 if (MM)
3030 OUTS (outf, " (M)");
3031 MM = 0;
3032 OUTS (outf, ", ");
3033 }
3034 }
3035
3036 if (w0)
3037 {
3038 OUTS (outf, dregs (dst));
3039 OUTS (outf, " = ");
3040 decode_multfunc (h00, h10, src0, src1, outf);
3041 }
3042
3043 decode_optmode (mmod, MM, outf);
3044 return 4;
3045 }
3046
3047 static int
3048 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3049 {
3050 /* dsp32alu
3051 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3052 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3053 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3054 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3055 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3056 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3057 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3058 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3059 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3060 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3061 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3062 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3063 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3064
3065 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3066 {
3067 OUTS (outf, "A0.L = ");
3068 OUTS (outf, dregs_lo (src0));
3069 }
3070 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3071 {
3072 OUTS (outf, "A1.H = ");
3073 OUTS (outf, dregs_hi (src0));
3074 }
3075 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3076 {
3077 OUTS (outf, "A1.L = ");
3078 OUTS (outf, dregs_lo (src0));
3079 }
3080 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3081 {
3082 OUTS (outf, "A0.H = ");
3083 OUTS (outf, dregs_hi (src0));
3084 }
3085 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3086 {
3087 OUTS (outf, dregs_hi (dst0));
3088 OUTS (outf, " = ");
3089 OUTS (outf, dregs (src0));
3090 OUTS (outf, " - ");
3091 OUTS (outf, dregs (src1));
3092 OUTS (outf, " (RND20)");
3093 }
3094 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3095 {
3096 OUTS (outf, dregs_hi (dst0));
3097 OUTS (outf, " = ");
3098 OUTS (outf, dregs (src0));
3099 OUTS (outf, " + ");
3100 OUTS (outf, dregs (src1));
3101 OUTS (outf, " (RND20)");
3102 }
3103 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3104 {
3105 OUTS (outf, dregs_lo (dst0));
3106 OUTS (outf, " = ");
3107 OUTS (outf, dregs (src0));
3108 OUTS (outf, " - ");
3109 OUTS (outf, dregs (src1));
3110 OUTS (outf, " (RND12)");
3111 }
3112 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3113 {
3114 OUTS (outf, dregs_lo (dst0));
3115 OUTS (outf, " = ");
3116 OUTS (outf, dregs (src0));
3117 OUTS (outf, " + ");
3118 OUTS (outf, dregs (src1));
3119 OUTS (outf, " (RND12)");
3120 }
3121 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3122 {
3123 OUTS (outf, dregs_lo (dst0));
3124 OUTS (outf, " = ");
3125 OUTS (outf, dregs (src0));
3126 OUTS (outf, " - ");
3127 OUTS (outf, dregs (src1));
3128 OUTS (outf, " (RND20)");
3129 }
3130 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3131 {
3132 OUTS (outf, dregs_hi (dst0));
3133 OUTS (outf, " = ");
3134 OUTS (outf, dregs (src0));
3135 OUTS (outf, " + ");
3136 OUTS (outf, dregs (src1));
3137 OUTS (outf, " (RND12)");
3138 }
3139 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3140 {
3141 OUTS (outf, dregs_lo (dst0));
3142 OUTS (outf, " = ");
3143 OUTS (outf, dregs (src0));
3144 OUTS (outf, " + ");
3145 OUTS (outf, dregs (src1));
3146 OUTS (outf, " (RND20)");
3147 }
3148 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3149 {
3150 OUTS (outf, dregs_hi (dst0));
3151 OUTS (outf, " = ");
3152 OUTS (outf, dregs (src0));
3153 OUTS (outf, " - ");
3154 OUTS (outf, dregs (src1));
3155 OUTS (outf, " (RND12)");
3156 }
3157 else if (HL == 1 && aop == 0 && aopcde == 2)
3158 {
3159 OUTS (outf, dregs_hi (dst0));
3160 OUTS (outf, " = ");
3161 OUTS (outf, dregs_lo (src0));
3162 OUTS (outf, " + ");
3163 OUTS (outf, dregs_lo (src1));
3164 amod1 (s, x, outf);
3165 }
3166 else if (HL == 1 && aop == 1 && aopcde == 2)
3167 {
3168 OUTS (outf, dregs_hi (dst0));
3169 OUTS (outf, " = ");
3170 OUTS (outf, dregs_lo (src0));
3171 OUTS (outf, " + ");
3172 OUTS (outf, dregs_hi (src1));
3173 amod1 (s, x, outf);
3174 }
3175 else if (HL == 1 && aop == 2 && aopcde == 2)
3176 {
3177 OUTS (outf, dregs_hi (dst0));
3178 OUTS (outf, " = ");
3179 OUTS (outf, dregs_hi (src0));
3180 OUTS (outf, " + ");
3181 OUTS (outf, dregs_lo (src1));
3182 amod1 (s, x, outf);
3183 }
3184 else if (HL == 1 && aop == 3 && aopcde == 2)
3185 {
3186 OUTS (outf, dregs_hi (dst0));
3187 OUTS (outf, " = ");
3188 OUTS (outf, dregs_hi (src0));
3189 OUTS (outf, " + ");
3190 OUTS (outf, dregs_hi (src1));
3191 amod1 (s, x, outf);
3192 }
3193 else if (HL == 0 && aop == 0 && aopcde == 3)
3194 {
3195 OUTS (outf, dregs_lo (dst0));
3196 OUTS (outf, " = ");
3197 OUTS (outf, dregs_lo (src0));
3198 OUTS (outf, " - ");
3199 OUTS (outf, dregs_lo (src1));
3200 amod1 (s, x, outf);
3201 }
3202 else if (HL == 0 && aop == 1 && aopcde == 3)
3203 {
3204 OUTS (outf, dregs_lo (dst0));
3205 OUTS (outf, " = ");
3206 OUTS (outf, dregs_lo (src0));
3207 OUTS (outf, " - ");
3208 OUTS (outf, dregs_hi (src1));
3209 amod1 (s, x, outf);
3210 }
3211 else if (HL == 0 && aop == 3 && aopcde == 2)
3212 {
3213 OUTS (outf, dregs_lo (dst0));
3214 OUTS (outf, " = ");
3215 OUTS (outf, dregs_hi (src0));
3216 OUTS (outf, " + ");
3217 OUTS (outf, dregs_hi (src1));
3218 amod1 (s, x, outf);
3219 }
3220 else if (HL == 1 && aop == 0 && aopcde == 3)
3221 {
3222 OUTS (outf, dregs_hi (dst0));
3223 OUTS (outf, " = ");
3224 OUTS (outf, dregs_lo (src0));
3225 OUTS (outf, " - ");
3226 OUTS (outf, dregs_lo (src1));
3227 amod1 (s, x, outf);
3228 }
3229 else if (HL == 1 && aop == 1 && aopcde == 3)
3230 {
3231 OUTS (outf, dregs_hi (dst0));
3232 OUTS (outf, " = ");
3233 OUTS (outf, dregs_lo (src0));
3234 OUTS (outf, " - ");
3235 OUTS (outf, dregs_hi (src1));
3236 amod1 (s, x, outf);
3237 }
3238 else if (HL == 1 && aop == 2 && aopcde == 3)
3239 {
3240 OUTS (outf, dregs_hi (dst0));
3241 OUTS (outf, " = ");
3242 OUTS (outf, dregs_hi (src0));
3243 OUTS (outf, " - ");
3244 OUTS (outf, dregs_lo (src1));
3245 amod1 (s, x, outf);
3246 }
3247 else if (HL == 1 && aop == 3 && aopcde == 3)
3248 {
3249 OUTS (outf, dregs_hi (dst0));
3250 OUTS (outf, " = ");
3251 OUTS (outf, dregs_hi (src0));
3252 OUTS (outf, " - ");
3253 OUTS (outf, dregs_hi (src1));
3254 amod1 (s, x, outf);
3255 }
3256 else if (HL == 0 && aop == 2 && aopcde == 2)
3257 {
3258 OUTS (outf, dregs_lo (dst0));
3259 OUTS (outf, " = ");
3260 OUTS (outf, dregs_hi (src0));
3261 OUTS (outf, " + ");
3262 OUTS (outf, dregs_lo (src1));
3263 amod1 (s, x, outf);
3264 }
3265 else if (HL == 0 && aop == 1 && aopcde == 2)
3266 {
3267 OUTS (outf, dregs_lo (dst0));
3268 OUTS (outf, " = ");
3269 OUTS (outf, dregs_lo (src0));
3270 OUTS (outf, " + ");
3271 OUTS (outf, dregs_hi (src1));
3272 amod1 (s, x, outf);
3273 }
3274 else if (HL == 0 && aop == 2 && aopcde == 3)
3275 {
3276 OUTS (outf, dregs_lo (dst0));
3277 OUTS (outf, " = ");
3278 OUTS (outf, dregs_hi (src0));
3279 OUTS (outf, " - ");
3280 OUTS (outf, dregs_lo (src1));
3281 amod1 (s, x, outf);
3282 }
3283 else if (HL == 0 && aop == 3 && aopcde == 3)
3284 {
3285 OUTS (outf, dregs_lo (dst0));
3286 OUTS (outf, " = ");
3287 OUTS (outf, dregs_hi (src0));
3288 OUTS (outf, " - ");
3289 OUTS (outf, dregs_hi (src1));
3290 amod1 (s, x, outf);
3291 }
3292 else if (HL == 0 && aop == 0 && aopcde == 2)
3293 {
3294 OUTS (outf, dregs_lo (dst0));
3295 OUTS (outf, " = ");
3296 OUTS (outf, dregs_lo (src0));
3297 OUTS (outf, " + ");
3298 OUTS (outf, dregs_lo (src1));
3299 amod1 (s, x, outf);
3300 }
3301 else if (aop == 0 && aopcde == 9 && s == 1)
3302 {
3303 OUTS (outf, "A0 = ");
3304 OUTS (outf, dregs (src0));
3305 }
3306 else if (aop == 3 && aopcde == 11 && s == 0)
3307 OUTS (outf, "A0 -= A1");
3308
3309 else if (aop == 3 && aopcde == 11 && s == 1)
3310 OUTS (outf, "A0 -= A1 (W32)");
3311
3312 else if (aop == 3 && aopcde == 22 && HL == 1)
3313 {
3314 OUTS (outf, dregs (dst0));
3315 OUTS (outf, " = BYTEOP2M (");
3316 OUTS (outf, dregs (src0 + 1));
3317 OUTS (outf, ":");
3318 OUTS (outf, imm5 (src0));
3319 OUTS (outf, ", ");
3320 OUTS (outf, dregs (src1 + 1));
3321 OUTS (outf, ":");
3322 OUTS (outf, imm5 (src1));
3323 OUTS (outf, ") (TH");
3324 if (s == 1)
3325 OUTS (outf, ", R)");
3326 else
3327 OUTS (outf, ")");
3328 }
3329 else if (aop == 3 && aopcde == 22 && HL == 0)
3330 {
3331 OUTS (outf, dregs (dst0));
3332 OUTS (outf, " = BYTEOP2M (");
3333 OUTS (outf, dregs (src0 + 1));
3334 OUTS (outf, ":");
3335 OUTS (outf, imm5 (src0));
3336 OUTS (outf, ", ");
3337 OUTS (outf, dregs (src1 + 1));
3338 OUTS (outf, ":");
3339 OUTS (outf, imm5 (src1));
3340 OUTS (outf, ") (TL");
3341 if (s == 1)
3342 OUTS (outf, ", R)");
3343 else
3344 OUTS (outf, ")");
3345 }
3346 else if (aop == 2 && aopcde == 22 && HL == 1)
3347 {
3348 OUTS (outf, dregs (dst0));
3349 OUTS (outf, " = BYTEOP2M (");
3350 OUTS (outf, dregs (src0 + 1));
3351 OUTS (outf, ":");
3352 OUTS (outf, imm5 (src0));
3353 OUTS (outf, ", ");
3354 OUTS (outf, dregs (src1 + 1));
3355 OUTS (outf, ":");
3356 OUTS (outf, imm5 (src1));
3357 OUTS (outf, ") (RNDH");
3358 if (s == 1)
3359 OUTS (outf, ", R)");
3360 else
3361 OUTS (outf, ")");
3362 }
3363 else if (aop == 2 && aopcde == 22 && HL == 0)
3364 {
3365 OUTS (outf, dregs (dst0));
3366 OUTS (outf, " = BYTEOP2M (");
3367 OUTS (outf, dregs (src0 + 1));
3368 OUTS (outf, ":");
3369 OUTS (outf, imm5 (src0));
3370 OUTS (outf, ", ");
3371 OUTS (outf, dregs (src1 + 1));
3372 OUTS (outf, ":");
3373 OUTS (outf, imm5 (src1));
3374 OUTS (outf, ") (RNDL");
3375 if (s == 1)
3376 OUTS (outf, ", R)");
3377 else
3378 OUTS (outf, ")");
3379 }
3380 else if (aop == 1 && aopcde == 22 && HL == 1)
3381 {
3382 OUTS (outf, dregs (dst0));
3383 OUTS (outf, " = BYTEOP2P (");
3384 OUTS (outf, dregs (src0 + 1));
3385 OUTS (outf, ":");
3386 OUTS (outf, imm5d (src0));
3387 OUTS (outf, ", ");
3388 OUTS (outf, dregs (src1 + 1));
3389 OUTS (outf, ":");
3390 OUTS (outf, imm5d (src1));
3391 OUTS (outf, ") (TH");
3392 if (s == 1)
3393 OUTS (outf, ", R)");
3394 else
3395 OUTS (outf, ")");
3396 }
3397 else if (aop == 1 && aopcde == 22 && HL == 0)
3398 {
3399 OUTS (outf, dregs (dst0));
3400 OUTS (outf, " = BYTEOP2P (");
3401 OUTS (outf, dregs (src0 + 1));
3402 OUTS (outf, ":");
3403 OUTS (outf, imm5d (src0));
3404 OUTS (outf, ", ");
3405 OUTS (outf, dregs (src1 + 1));
3406 OUTS (outf, ":");
3407 OUTS (outf, imm5d (src1));
3408 OUTS (outf, ") (TL");
3409 if (s == 1)
3410 OUTS (outf, ", R)");
3411 else
3412 OUTS (outf, ")");
3413 }
3414 else if (aop == 0 && aopcde == 22 && HL == 1)
3415 {
3416 OUTS (outf, dregs (dst0));
3417 OUTS (outf, " = BYTEOP2P (");
3418 OUTS (outf, dregs (src0 + 1));
3419 OUTS (outf, ":");
3420 OUTS (outf, imm5d (src0));
3421 OUTS (outf, ", ");
3422 OUTS (outf, dregs (src1 + 1));
3423 OUTS (outf, ":");
3424 OUTS (outf, imm5d (src1));
3425 OUTS (outf, ") (RNDH");
3426 if (s == 1)
3427 OUTS (outf, ", R)");
3428 else
3429 OUTS (outf, ")");
3430 }
3431 else if (aop == 0 && aopcde == 22 && HL == 0)
3432 {
3433 OUTS (outf, dregs (dst0));
3434 OUTS (outf, " = BYTEOP2P (");
3435 OUTS (outf, dregs (src0 + 1));
3436 OUTS (outf, ":");
3437 OUTS (outf, imm5d (src0));
3438 OUTS (outf, ", ");
3439 OUTS (outf, dregs (src1 + 1));
3440 OUTS (outf, ":");
3441 OUTS (outf, imm5d (src1));
3442 OUTS (outf, ") (RNDL");
3443 if (s == 1)
3444 OUTS (outf, ", R)");
3445 else
3446 OUTS (outf, ")");
3447 }
3448 else if (aop == 0 && s == 0 && aopcde == 8)
3449 OUTS (outf, "A0 = 0");
3450
3451 else if (aop == 0 && s == 1 && aopcde == 8)
3452 OUTS (outf, "A0 = A0 (S)");
3453
3454 else if (aop == 1 && s == 0 && aopcde == 8)
3455 OUTS (outf, "A1 = 0");
3456
3457 else if (aop == 1 && s == 1 && aopcde == 8)
3458 OUTS (outf, "A1 = A1 (S)");
3459
3460 else if (aop == 2 && s == 0 && aopcde == 8)
3461 OUTS (outf, "A1 = A0 = 0");
3462
3463 else if (aop == 2 && s == 1 && aopcde == 8)
3464 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3465
3466 else if (aop == 3 && s == 0 && aopcde == 8)
3467 OUTS (outf, "A0 = A1");
3468
3469 else if (aop == 3 && s == 1 && aopcde == 8)
3470 OUTS (outf, "A1 = A0");
3471
3472 else if (aop == 1 && aopcde == 9 && s == 0)
3473 {
3474 OUTS (outf, "A0.X = ");
3475 OUTS (outf, dregs_lo (src0));
3476 }
3477 else if (aop == 1 && HL == 0 && aopcde == 11)
3478 {
3479 OUTS (outf, dregs_lo (dst0));
3480 OUTS (outf, " = (A0 += A1)");
3481 }
3482 else if (aop == 3 && HL == 0 && aopcde == 16)
3483 OUTS (outf, "A1 = ABS A0, A0 = ABS A0");
3484
3485 else if (aop == 0 && aopcde == 23 && HL == 1)
3486 {
3487 OUTS (outf, dregs (dst0));
3488 OUTS (outf, " = BYTEOP3P (");
3489 OUTS (outf, dregs (src0 + 1));
3490 OUTS (outf, ":");
3491 OUTS (outf, imm5d (src0));
3492 OUTS (outf, ", ");
3493 OUTS (outf, dregs (src1 + 1));
3494 OUTS (outf, ":");
3495 OUTS (outf, imm5d (src1));
3496 OUTS (outf, ") (HI");
3497 if (s == 1)
3498 OUTS (outf, ", R)");
3499 else
3500 OUTS (outf, ")");
3501 }
3502 else if (aop == 3 && aopcde == 9 && s == 0)
3503 {
3504 OUTS (outf, "A1.X = ");
3505 OUTS (outf, dregs_lo (src0));
3506 }
3507 else if (aop == 1 && HL == 1 && aopcde == 16)
3508 OUTS (outf, "A1 = ABS A1");
3509
3510 else if (aop == 0 && HL == 1 && aopcde == 16)
3511 OUTS (outf, "A1 = ABS A0");
3512
3513 else if (aop == 2 && aopcde == 9 && s == 1)
3514 {
3515 OUTS (outf, "A1 = ");
3516 OUTS (outf, dregs (src0));
3517 }
3518 else if (HL == 0 && aop == 3 && aopcde == 12)
3519 {
3520 OUTS (outf, dregs_lo (dst0));
3521 OUTS (outf, " = ");
3522 OUTS (outf, dregs (src0));
3523 OUTS (outf, " (RND)");
3524 }
3525 else if (aop == 1 && HL == 0 && aopcde == 16)
3526 OUTS (outf, "A0 = ABS A1");
3527
3528 else if (aop == 0 && HL == 0 && aopcde == 16)
3529 OUTS (outf, "A0 = ABS A0");
3530
3531 else if (aop == 3 && HL == 0 && aopcde == 15)
3532 {
3533 OUTS (outf, dregs (dst0));
3534 OUTS (outf, " = -");
3535 OUTS (outf, dregs (src0));
3536 OUTS (outf, " (V)");
3537 }
3538 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3539 {
3540 OUTS (outf, dregs (dst0));
3541 OUTS (outf, " = -");
3542 OUTS (outf, dregs (src0));
3543 OUTS (outf, " (S)");
3544 }
3545 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3546 {
3547 OUTS (outf, dregs (dst0));
3548 OUTS (outf, " = -");
3549 OUTS (outf, dregs (src0));
3550 OUTS (outf, " (NS)");
3551 }
3552 else if (aop == 1 && HL == 1 && aopcde == 11)
3553 {
3554 OUTS (outf, dregs_hi (dst0));
3555 OUTS (outf, " = (A0 += A1)");
3556 }
3557 else if (aop == 2 && aopcde == 11 && s == 0)
3558 OUTS (outf, "A0 += A1");
3559
3560 else if (aop == 2 && aopcde == 11 && s == 1)
3561 OUTS (outf, "A0 += A1 (W32)");
3562
3563 else if (aop == 3 && HL == 0 && aopcde == 14)
3564 OUTS (outf, "A1 = -A1, A0 = -A0");
3565
3566 else if (HL == 1 && aop == 3 && aopcde == 12)
3567 {
3568 OUTS (outf, dregs_hi (dst0));
3569 OUTS (outf, " = ");
3570 OUTS (outf, dregs (src0));
3571 OUTS (outf, " (RND)");
3572 }
3573 else if (aop == 0 && aopcde == 23 && HL == 0)
3574 {
3575 OUTS (outf, dregs (dst0));
3576 OUTS (outf, " = BYTEOP3P (");
3577 OUTS (outf, dregs (src0 + 1));
3578 OUTS (outf, ":");
3579 OUTS (outf, imm5d (src0));
3580 OUTS (outf, ", ");
3581 OUTS (outf, dregs (src1 + 1));
3582 OUTS (outf, ":");
3583 OUTS (outf, imm5d (src1));
3584 OUTS (outf, ") (LO");
3585 if (s == 1)
3586 OUTS (outf, ", R)");
3587 else
3588 OUTS (outf, ")");
3589 }
3590 else if (aop == 0 && HL == 0 && aopcde == 14)
3591 OUTS (outf, "A0 = -A0");
3592
3593 else if (aop == 1 && HL == 0 && aopcde == 14)
3594 OUTS (outf, "A0 = -A1");
3595
3596 else if (aop == 0 && HL == 1 && aopcde == 14)
3597 OUTS (outf, "A1 = -A0");
3598
3599 else if (aop == 1 && HL == 1 && aopcde == 14)
3600 OUTS (outf, "A1 = -A1");
3601
3602 else if (aop == 0 && aopcde == 12)
3603 {
3604 OUTS (outf, dregs_hi (dst0));
3605 OUTS (outf, " = ");
3606 OUTS (outf, dregs_lo (dst0));
3607 OUTS (outf, " = SIGN (");
3608 OUTS (outf, dregs_hi (src0));
3609 OUTS (outf, ") * ");
3610 OUTS (outf, dregs_hi (src1));
3611 OUTS (outf, " + SIGN (");
3612 OUTS (outf, dregs_lo (src0));
3613 OUTS (outf, ") * ");
3614 OUTS (outf, dregs_lo (src1));
3615 }
3616 else if (aop == 2 && aopcde == 0)
3617 {
3618 OUTS (outf, dregs (dst0));
3619 OUTS (outf, " = ");
3620 OUTS (outf, dregs (src0));
3621 OUTS (outf, " -|+ ");
3622 OUTS (outf, dregs (src1));
3623 amod0 (s, x, outf);
3624 }
3625 else if (aop == 1 && aopcde == 12)
3626 {
3627 OUTS (outf, dregs (dst1));
3628 OUTS (outf, " = A1.L + A1.H, ");
3629 OUTS (outf, dregs (dst0));
3630 OUTS (outf, " = A0.L + A0.H");
3631 }
3632 else if (aop == 2 && aopcde == 4)
3633 {
3634 OUTS (outf, dregs (dst1));
3635 OUTS (outf, " = ");
3636 OUTS (outf, dregs (src0));
3637 OUTS (outf, " + ");
3638 OUTS (outf, dregs (src1));
3639 OUTS (outf, ", ");
3640 OUTS (outf, dregs (dst0));
3641 OUTS (outf, " = ");
3642 OUTS (outf, dregs (src0));
3643 OUTS (outf, " - ");
3644 OUTS (outf, dregs (src1));
3645 amod1 (s, x, outf);
3646 }
3647 else if (HL == 0 && aopcde == 1)
3648 {
3649 OUTS (outf, dregs (dst1));
3650 OUTS (outf, " = ");
3651 OUTS (outf, dregs (src0));
3652 OUTS (outf, " +|+ ");
3653 OUTS (outf, dregs (src1));
3654 OUTS (outf, ", ");
3655 OUTS (outf, dregs (dst0));
3656 OUTS (outf, " = ");
3657 OUTS (outf, dregs (src0));
3658 OUTS (outf, " -|- ");
3659 OUTS (outf, dregs (src1));
3660 amod0amod2 (s, x, aop, outf);
3661 }
3662 else if (aop == 0 && aopcde == 11)
3663 {
3664 OUTS (outf, dregs (dst0));
3665 OUTS (outf, " = (A0 += A1)");
3666 }
3667 else if (aop == 0 && aopcde == 10)
3668 {
3669 OUTS (outf, dregs_lo (dst0));
3670 OUTS (outf, " = A0.X");
3671 }
3672 else if (aop == 1 && aopcde == 10)
3673 {
3674 OUTS (outf, dregs_lo (dst0));
3675 OUTS (outf, " = A1.X");
3676 }
3677 else if (aop == 1 && aopcde == 0)
3678 {
3679 OUTS (outf, dregs (dst0));
3680 OUTS (outf, " = ");
3681 OUTS (outf, dregs (src0));
3682 OUTS (outf, " +|- ");
3683 OUTS (outf, dregs (src1));
3684 amod0 (s, x, outf);
3685 }
3686 else if (aop == 3 && aopcde == 0)
3687 {
3688 OUTS (outf, dregs (dst0));
3689 OUTS (outf, " = ");
3690 OUTS (outf, dregs (src0));
3691 OUTS (outf, " -|- ");
3692 OUTS (outf, dregs (src1));
3693 amod0 (s, x, outf);
3694 }
3695 else if (aop == 1 && aopcde == 4)
3696 {
3697 OUTS (outf, dregs (dst0));
3698 OUTS (outf, " = ");
3699 OUTS (outf, dregs (src0));
3700 OUTS (outf, " - ");
3701 OUTS (outf, dregs (src1));
3702 amod1 (s, x, outf);
3703 }
3704 else if (aop == 0 && aopcde == 17)
3705 {
3706 OUTS (outf, dregs (dst1));
3707 OUTS (outf, " = A1 + A0, ");
3708 OUTS (outf, dregs (dst0));
3709 OUTS (outf, " = A1 - A0");
3710 amod1 (s, x, outf);
3711 }
3712 else if (aop == 1 && aopcde == 17)
3713 {
3714 OUTS (outf, dregs (dst1));
3715 OUTS (outf, " = A0 + A1, ");
3716 OUTS (outf, dregs (dst0));
3717 OUTS (outf, " = A0 - A1");
3718 amod1 (s, x, outf);
3719 }
3720 else if (aop == 0 && aopcde == 18)
3721 {
3722 OUTS (outf, "SAA (");
3723 OUTS (outf, dregs (src0 + 1));
3724 OUTS (outf, ":");
3725 OUTS (outf, imm5d (src0));
3726 OUTS (outf, ", ");
3727 OUTS (outf, dregs (src1 + 1));
3728 OUTS (outf, ":");
3729 OUTS (outf, imm5d (src1));
3730 OUTS (outf, ")");
3731 aligndir (s, outf);
3732 }
3733 else if (aop == 3 && aopcde == 18)
3734 OUTS (outf, "DISALGNEXCPT");
3735
3736 else if (aop == 0 && aopcde == 20)
3737 {
3738 OUTS (outf, dregs (dst0));
3739 OUTS (outf, " = BYTEOP1P (");
3740 OUTS (outf, dregs (src0 + 1));
3741 OUTS (outf, ":");
3742 OUTS (outf, imm5d (src0));
3743 OUTS (outf, ", ");
3744 OUTS (outf, dregs (src1 + 1));
3745 OUTS (outf, ":");
3746 OUTS (outf, imm5d (src1));
3747 OUTS (outf, ")");
3748 aligndir (s, outf);
3749 }
3750 else if (aop == 1 && aopcde == 20)
3751 {
3752 OUTS (outf, dregs (dst0));
3753 OUTS (outf, " = BYTEOP1P (");
3754 OUTS (outf, dregs (src0 + 1));
3755 OUTS (outf, ":");
3756 OUTS (outf, imm5d (src0));
3757 OUTS (outf, ", ");
3758 OUTS (outf, dregs (src1 + 1));
3759 OUTS (outf, ":");
3760 OUTS (outf, imm5d (src1));
3761 OUTS (outf, ") (T");
3762 if (s == 1)
3763 OUTS (outf, ", R)");
3764 else
3765 OUTS (outf, ")");
3766 }
3767 else if (aop == 0 && aopcde == 21)
3768 {
3769 OUTS (outf, "(");
3770 OUTS (outf, dregs (dst1));
3771 OUTS (outf, ", ");
3772 OUTS (outf, dregs (dst0));
3773 OUTS (outf, ") = BYTEOP16P (");
3774 OUTS (outf, dregs (src0 + 1));
3775 OUTS (outf, ":");
3776 OUTS (outf, imm5d (src0));
3777 OUTS (outf, ", ");
3778 OUTS (outf, dregs (src1 + 1));
3779 OUTS (outf, ":");
3780 OUTS (outf, imm5d (src1));
3781 OUTS (outf, ")");
3782 aligndir (s, outf);
3783 }
3784 else if (aop == 1 && aopcde == 21)
3785 {
3786 OUTS (outf, "(");
3787 OUTS (outf, dregs (dst1));
3788 OUTS (outf, ", ");
3789 OUTS (outf, dregs (dst0));
3790 OUTS (outf, ") = BYTEOP16M (");
3791 OUTS (outf, dregs (src0 + 1));
3792 OUTS (outf, ":");
3793 OUTS (outf, imm5d (src0));
3794 OUTS (outf, ", ");
3795 OUTS (outf, dregs (src1 + 1));
3796 OUTS (outf, ":");
3797 OUTS (outf, imm5d (src1));
3798 OUTS (outf, ")");
3799 aligndir (s, outf);
3800 }
3801 else if (aop == 2 && aopcde == 7)
3802 {
3803 OUTS (outf, dregs (dst0));
3804 OUTS (outf, " = ABS ");
3805 OUTS (outf, dregs (src0));
3806 }
3807 else if (aop == 1 && aopcde == 7)
3808 {
3809 OUTS (outf, dregs (dst0));
3810 OUTS (outf, " = MIN (");
3811 OUTS (outf, dregs (src0));
3812 OUTS (outf, ", ");
3813 OUTS (outf, dregs (src1));
3814 OUTS (outf, ")");
3815 }
3816 else if (aop == 0 && aopcde == 7)
3817 {
3818 OUTS (outf, dregs (dst0));
3819 OUTS (outf, " = MAX (");
3820 OUTS (outf, dregs (src0));
3821 OUTS (outf, ", ");
3822 OUTS (outf, dregs (src1));
3823 OUTS (outf, ")");
3824 }
3825 else if (aop == 2 && aopcde == 6)
3826 {
3827 OUTS (outf, dregs (dst0));
3828 OUTS (outf, " = ABS ");
3829 OUTS (outf, dregs (src0));
3830 OUTS (outf, " (V)");
3831 }
3832 else if (aop == 1 && aopcde == 6)
3833 {
3834 OUTS (outf, dregs (dst0));
3835 OUTS (outf, " = MIN (");
3836 OUTS (outf, dregs (src0));
3837 OUTS (outf, ", ");
3838 OUTS (outf, dregs (src1));
3839 OUTS (outf, ") (V)");
3840 }
3841 else if (aop == 0 && aopcde == 6)
3842 {
3843 OUTS (outf, dregs (dst0));
3844 OUTS (outf, " = MAX (");
3845 OUTS (outf, dregs (src0));
3846 OUTS (outf, ", ");
3847 OUTS (outf, dregs (src1));
3848 OUTS (outf, ") (V)");
3849 }
3850 else if (HL == 1 && aopcde == 1)
3851 {
3852 OUTS (outf, dregs (dst1));
3853 OUTS (outf, " = ");
3854 OUTS (outf, dregs (src0));
3855 OUTS (outf, " +|- ");
3856 OUTS (outf, dregs (src1));
3857 OUTS (outf, ", ");
3858 OUTS (outf, dregs (dst0));
3859 OUTS (outf, " = ");
3860 OUTS (outf, dregs (src0));
3861 OUTS (outf, " -|+ ");
3862 OUTS (outf, dregs (src1));
3863 amod0amod2 (s, x, aop, outf);
3864 }
3865 else if (aop == 0 && aopcde == 4)
3866 {
3867 OUTS (outf, dregs (dst0));
3868 OUTS (outf, " = ");
3869 OUTS (outf, dregs (src0));
3870 OUTS (outf, " + ");
3871 OUTS (outf, dregs (src1));
3872 amod1 (s, x, outf);
3873 }
3874 else if (aop == 0 && aopcde == 0)
3875 {
3876 OUTS (outf, dregs (dst0));
3877 OUTS (outf, " = ");
3878 OUTS (outf, dregs (src0));
3879 OUTS (outf, " +|+ ");
3880 OUTS (outf, dregs (src1));
3881 amod0 (s, x, outf);
3882 }
3883 else if (aop == 0 && aopcde == 24)
3884 {
3885 OUTS (outf, dregs (dst0));
3886 OUTS (outf, " = BYTEPACK (");
3887 OUTS (outf, dregs (src0));
3888 OUTS (outf, ", ");
3889 OUTS (outf, dregs (src1));
3890 OUTS (outf, ")");
3891 }
3892 else if (aop == 1 && aopcde == 24)
3893 {
3894 OUTS (outf, "(");
3895 OUTS (outf, dregs (dst1));
3896 OUTS (outf, ", ");
3897 OUTS (outf, dregs (dst0));
3898 OUTS (outf, ") = BYTEUNPACK ");
3899 OUTS (outf, dregs (src0 + 1));
3900 OUTS (outf, ":");
3901 OUTS (outf, imm5d (src0));
3902 aligndir (s, outf);
3903 }
3904 else if (aopcde == 13)
3905 {
3906 OUTS (outf, "(");
3907 OUTS (outf, dregs (dst1));
3908 OUTS (outf, ", ");
3909 OUTS (outf, dregs (dst0));
3910 OUTS (outf, ") = SEARCH ");
3911 OUTS (outf, dregs (src0));
3912 OUTS (outf, " (");
3913 searchmod (aop, outf);
3914 OUTS (outf, ")");
3915 }
3916 else
3917 return 0;
3918
3919 return 4;
3920 }
3921
3922 static int
3923 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3924 {
3925 /* dsp32shift
3926 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3927 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3928 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3929 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3930 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3931 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3932 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3933 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3934 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3935 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3936 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3937
3938 if (HLs == 0 && sop == 0 && sopcde == 0)
3939 {
3940 OUTS (outf, dregs_lo (dst0));
3941 OUTS (outf, " = ASHIFT ");
3942 OUTS (outf, dregs_lo (src1));
3943 OUTS (outf, " BY ");
3944 OUTS (outf, dregs_lo (src0));
3945 }
3946 else if (HLs == 1 && sop == 0 && sopcde == 0)
3947 {
3948 OUTS (outf, dregs_lo (dst0));
3949 OUTS (outf, " = ASHIFT ");
3950 OUTS (outf, dregs_hi (src1));
3951 OUTS (outf, " BY ");
3952 OUTS (outf, dregs_lo (src0));
3953 }
3954 else if (HLs == 2 && sop == 0 && sopcde == 0)
3955 {
3956 OUTS (outf, dregs_hi (dst0));
3957 OUTS (outf, " = ASHIFT ");
3958 OUTS (outf, dregs_lo (src1));
3959 OUTS (outf, " BY ");
3960 OUTS (outf, dregs_lo (src0));
3961 }
3962 else if (HLs == 3 && sop == 0 && sopcde == 0)
3963 {
3964 OUTS (outf, dregs_hi (dst0));
3965 OUTS (outf, " = ASHIFT ");
3966 OUTS (outf, dregs_hi (src1));
3967 OUTS (outf, " BY ");
3968 OUTS (outf, dregs_lo (src0));
3969 }
3970 else if (HLs == 0 && sop == 1 && sopcde == 0)
3971 {
3972 OUTS (outf, dregs_lo (dst0));
3973 OUTS (outf, " = ASHIFT ");
3974 OUTS (outf, dregs_lo (src1));
3975 OUTS (outf, " BY ");
3976 OUTS (outf, dregs_lo (src0));
3977 OUTS (outf, " (S)");
3978 }
3979 else if (HLs == 1 && sop == 1 && sopcde == 0)
3980 {
3981 OUTS (outf, dregs_lo (dst0));
3982 OUTS (outf, " = ASHIFT ");
3983 OUTS (outf, dregs_hi (src1));
3984 OUTS (outf, " BY ");
3985 OUTS (outf, dregs_lo (src0));
3986 OUTS (outf, " (S)");
3987 }
3988 else if (HLs == 2 && sop == 1 && sopcde == 0)
3989 {
3990 OUTS (outf, dregs_hi (dst0));
3991 OUTS (outf, " = ASHIFT ");
3992 OUTS (outf, dregs_lo (src1));
3993 OUTS (outf, " BY ");
3994 OUTS (outf, dregs_lo (src0));
3995 OUTS (outf, " (S)");
3996 }
3997 else if (HLs == 3 && sop == 1 && sopcde == 0)
3998 {
3999 OUTS (outf, dregs_hi (dst0));
4000 OUTS (outf, " = ASHIFT ");
4001 OUTS (outf, dregs_hi (src1));
4002 OUTS (outf, " BY ");
4003 OUTS (outf, dregs_lo (src0));
4004 OUTS (outf, " (S)");
4005 }
4006 else if (sop == 2 && sopcde == 0)
4007 {
4008 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
4009 OUTS (outf, " = LSHIFT ");
4010 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
4011 OUTS (outf, " BY ");
4012 OUTS (outf, dregs_lo (src0));
4013 }
4014 else if (sop == 0 && sopcde == 3)
4015 {
4016 OUTS (outf, acc01);
4017 OUTS (outf, " = ASHIFT ");
4018 OUTS (outf, acc01);
4019 OUTS (outf, " BY ");
4020 OUTS (outf, dregs_lo (src0));
4021 }
4022 else if (sop == 1 && sopcde == 3)
4023 {
4024 OUTS (outf, acc01);
4025 OUTS (outf, " = LSHIFT ");
4026 OUTS (outf, acc01);
4027 OUTS (outf, " BY ");
4028 OUTS (outf, dregs_lo (src0));
4029 }
4030 else if (sop == 2 && sopcde == 3)
4031 {
4032 OUTS (outf, acc01);
4033 OUTS (outf, " = ROT ");
4034 OUTS (outf, acc01);
4035 OUTS (outf, " BY ");
4036 OUTS (outf, dregs_lo (src0));
4037 }
4038 else if (sop == 3 && sopcde == 3)
4039 {
4040 OUTS (outf, dregs (dst0));
4041 OUTS (outf, " = ROT ");
4042 OUTS (outf, dregs (src1));
4043 OUTS (outf, " BY ");
4044 OUTS (outf, dregs_lo (src0));
4045 }
4046 else if (sop == 1 && sopcde == 1)
4047 {
4048 OUTS (outf, dregs (dst0));
4049 OUTS (outf, " = ASHIFT ");
4050 OUTS (outf, dregs (src1));
4051 OUTS (outf, " BY ");
4052 OUTS (outf, dregs_lo (src0));
4053 OUTS (outf, " (V, S)");
4054 }
4055 else if (sop == 0 && sopcde == 1)
4056 {
4057 OUTS (outf, dregs (dst0));
4058 OUTS (outf, " = ASHIFT ");
4059 OUTS (outf, dregs (src1));
4060 OUTS (outf, " BY ");
4061 OUTS (outf, dregs_lo (src0));
4062 OUTS (outf, " (V)");
4063 }
4064 else if (sop == 0 && sopcde == 2)
4065 {
4066 OUTS (outf, dregs (dst0));
4067 OUTS (outf, " = ASHIFT ");
4068 OUTS (outf, dregs (src1));
4069 OUTS (outf, " BY ");
4070 OUTS (outf, dregs_lo (src0));
4071 }
4072 else if (sop == 1 && sopcde == 2)
4073 {
4074 OUTS (outf, dregs (dst0));
4075 OUTS (outf, " = ASHIFT ");
4076 OUTS (outf, dregs (src1));
4077 OUTS (outf, " BY ");
4078 OUTS (outf, dregs_lo (src0));
4079 OUTS (outf, " (S)");
4080 }
4081 else if (sop == 2 && sopcde == 2)
4082 {
4083 OUTS (outf, dregs (dst0));
4084 OUTS (outf, " = LSHIFT ");
4085 OUTS (outf, dregs (src1));
4086 OUTS (outf, " BY ");
4087 OUTS (outf, dregs_lo (src0));
4088 }
4089 else if (sop == 3 && sopcde == 2)
4090 {
4091 OUTS (outf, dregs (dst0));
4092 OUTS (outf, " = ROT ");
4093 OUTS (outf, dregs (src1));
4094 OUTS (outf, " BY ");
4095 OUTS (outf, dregs_lo (src0));
4096 }
4097 else if (sop == 2 && sopcde == 1)
4098 {
4099 OUTS (outf, dregs (dst0));
4100 OUTS (outf, " = LSHIFT ");
4101 OUTS (outf, dregs (src1));
4102 OUTS (outf, " BY ");
4103 OUTS (outf, dregs_lo (src0));
4104 OUTS (outf, " (V)");
4105 }
4106 else if (sop == 0 && sopcde == 4)
4107 {
4108 OUTS (outf, dregs (dst0));
4109 OUTS (outf, " = PACK (");
4110 OUTS (outf, dregs_lo (src1));
4111 OUTS (outf, ", ");
4112 OUTS (outf, dregs_lo (src0));
4113 OUTS (outf, ")");
4114 }
4115 else if (sop == 1 && sopcde == 4)
4116 {
4117 OUTS (outf, dregs (dst0));
4118 OUTS (outf, " = PACK (");
4119 OUTS (outf, dregs_lo (src1));
4120 OUTS (outf, ", ");
4121 OUTS (outf, dregs_hi (src0));
4122 OUTS (outf, ")");
4123 }
4124 else if (sop == 2 && sopcde == 4)
4125 {
4126 OUTS (outf, dregs (dst0));
4127 OUTS (outf, " = PACK (");
4128 OUTS (outf, dregs_hi (src1));
4129 OUTS (outf, ", ");
4130 OUTS (outf, dregs_lo (src0));
4131 OUTS (outf, ")");
4132 }
4133 else if (sop == 3 && sopcde == 4)
4134 {
4135 OUTS (outf, dregs (dst0));
4136 OUTS (outf, " = PACK (");
4137 OUTS (outf, dregs_hi (src1));
4138 OUTS (outf, ", ");
4139 OUTS (outf, dregs_hi (src0));
4140 OUTS (outf, ")");
4141 }
4142 else if (sop == 0 && sopcde == 5)
4143 {
4144 OUTS (outf, dregs_lo (dst0));
4145 OUTS (outf, " = SIGNBITS ");
4146 OUTS (outf, dregs (src1));
4147 }
4148 else if (sop == 1 && sopcde == 5)
4149 {
4150 OUTS (outf, dregs_lo (dst0));
4151 OUTS (outf, " = SIGNBITS ");
4152 OUTS (outf, dregs_lo (src1));
4153 }
4154 else if (sop == 2 && sopcde == 5)
4155 {
4156 OUTS (outf, dregs_lo (dst0));
4157 OUTS (outf, " = SIGNBITS ");
4158 OUTS (outf, dregs_hi (src1));
4159 }
4160 else if (sop == 0 && sopcde == 6)
4161 {
4162 OUTS (outf, dregs_lo (dst0));
4163 OUTS (outf, " = SIGNBITS A0");
4164 }
4165 else if (sop == 1 && sopcde == 6)
4166 {
4167 OUTS (outf, dregs_lo (dst0));
4168 OUTS (outf, " = SIGNBITS A1");
4169 }
4170 else if (sop == 3 && sopcde == 6)
4171 {
4172 OUTS (outf, dregs_lo (dst0));
4173 OUTS (outf, " = ONES ");
4174 OUTS (outf, dregs (src1));
4175 }
4176 else if (sop == 0 && sopcde == 7)
4177 {
4178 OUTS (outf, dregs_lo (dst0));
4179 OUTS (outf, " = EXPADJ (");
4180 OUTS (outf, dregs (src1));
4181 OUTS (outf, ", ");
4182 OUTS (outf, dregs_lo (src0));
4183 OUTS (outf, ")");
4184 }
4185 else if (sop == 1 && sopcde == 7)
4186 {
4187 OUTS (outf, dregs_lo (dst0));
4188 OUTS (outf, " = EXPADJ (");
4189 OUTS (outf, dregs (src1));
4190 OUTS (outf, ", ");
4191 OUTS (outf, dregs_lo (src0));
4192 OUTS (outf, ") (V)");
4193 }
4194 else if (sop == 2 && sopcde == 7)
4195 {
4196 OUTS (outf, dregs_lo (dst0));
4197 OUTS (outf, " = EXPADJ (");
4198 OUTS (outf, dregs_lo (src1));
4199 OUTS (outf, ", ");
4200 OUTS (outf, dregs_lo (src0));
4201 OUTS (outf, ")");
4202 }
4203 else if (sop == 3 && sopcde == 7)
4204 {
4205 OUTS (outf, dregs_lo (dst0));
4206 OUTS (outf, " = EXPADJ (");
4207 OUTS (outf, dregs_hi (src1));
4208 OUTS (outf, ", ");
4209 OUTS (outf, dregs_lo (src0));
4210 OUTS (outf, ")");
4211 }
4212 else if (sop == 0 && sopcde == 8)
4213 {
4214 OUTS (outf, "BITMUX (");
4215 OUTS (outf, dregs (src0));
4216 OUTS (outf, ", ");
4217 OUTS (outf, dregs (src1));
4218 OUTS (outf, ", A0) (ASR)");
4219 }
4220 else if (sop == 1 && sopcde == 8)
4221 {
4222 OUTS (outf, "BITMUX (");
4223 OUTS (outf, dregs (src0));
4224 OUTS (outf, ", ");
4225 OUTS (outf, dregs (src1));
4226 OUTS (outf, ", A0) (ASL)");
4227 }
4228 else if (sop == 0 && sopcde == 9)
4229 {
4230 OUTS (outf, dregs_lo (dst0));
4231 OUTS (outf, " = VIT_MAX (");
4232 OUTS (outf, dregs (src1));
4233 OUTS (outf, ") (ASL)");
4234 }
4235 else if (sop == 1 && sopcde == 9)
4236 {
4237 OUTS (outf, dregs_lo (dst0));
4238 OUTS (outf, " = VIT_MAX (");
4239 OUTS (outf, dregs (src1));
4240 OUTS (outf, ") (ASR)");
4241 }
4242 else if (sop == 2 && sopcde == 9)
4243 {
4244 OUTS (outf, dregs (dst0));
4245 OUTS (outf, " = VIT_MAX (");
4246 OUTS (outf, dregs (src1));
4247 OUTS (outf, ", ");
4248 OUTS (outf, dregs (src0));
4249 OUTS (outf, ") (ASL)");
4250 }
4251 else if (sop == 3 && sopcde == 9)
4252 {
4253 OUTS (outf, dregs (dst0));
4254 OUTS (outf, " = VIT_MAX (");
4255 OUTS (outf, dregs (src1));
4256 OUTS (outf, ", ");
4257 OUTS (outf, dregs (src0));
4258 OUTS (outf, ") (ASR)");
4259 }
4260 else if (sop == 0 && sopcde == 10)
4261 {
4262 OUTS (outf, dregs (dst0));
4263 OUTS (outf, " = EXTRACT (");
4264 OUTS (outf, dregs (src1));
4265 OUTS (outf, ", ");
4266 OUTS (outf, dregs_lo (src0));
4267 OUTS (outf, ") (Z)");
4268 }
4269 else if (sop == 1 && sopcde == 10)
4270 {
4271 OUTS (outf, dregs (dst0));
4272 OUTS (outf, " = EXTRACT (");
4273 OUTS (outf, dregs (src1));
4274 OUTS (outf, ", ");
4275 OUTS (outf, dregs_lo (src0));
4276 OUTS (outf, ") (X)");
4277 }
4278 else if (sop == 2 && sopcde == 10)
4279 {
4280 OUTS (outf, dregs (dst0));
4281 OUTS (outf, " = DEPOSIT (");
4282 OUTS (outf, dregs (src1));
4283 OUTS (outf, ", ");
4284 OUTS (outf, dregs (src0));
4285 OUTS (outf, ")");
4286 }
4287 else if (sop == 3 && sopcde == 10)
4288 {
4289 OUTS (outf, dregs (dst0));
4290 OUTS (outf, " = DEPOSIT (");
4291 OUTS (outf, dregs (src1));
4292 OUTS (outf, ", ");
4293 OUTS (outf, dregs (src0));
4294 OUTS (outf, ") (X)");
4295 }
4296 else if (sop == 0 && sopcde == 11)
4297 {
4298 OUTS (outf, dregs_lo (dst0));
4299 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4300 OUTS (outf, dregs (src0));
4301 OUTS (outf, ")");
4302 }
4303 else if (sop == 1 && sopcde == 11)
4304 {
4305 OUTS (outf, dregs_lo (dst0));
4306 OUTS (outf, " = CC = BXOR (A0, ");
4307 OUTS (outf, dregs (src0));
4308 OUTS (outf, ")");
4309 }
4310 else if (sop == 0 && sopcde == 12)
4311 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4312
4313 else if (sop == 1 && sopcde == 12)
4314 {
4315 OUTS (outf, dregs_lo (dst0));
4316 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4317 }
4318 else if (sop == 0 && sopcde == 13)
4319 {
4320 OUTS (outf, dregs (dst0));
4321 OUTS (outf, " = ALIGN8 (");
4322 OUTS (outf, dregs (src1));
4323 OUTS (outf, ", ");
4324 OUTS (outf, dregs (src0));
4325 OUTS (outf, ")");
4326 }
4327 else if (sop == 1 && sopcde == 13)
4328 {
4329 OUTS (outf, dregs (dst0));
4330 OUTS (outf, " = ALIGN16 (");
4331 OUTS (outf, dregs (src1));
4332 OUTS (outf, ", ");
4333 OUTS (outf, dregs (src0));
4334 OUTS (outf, ")");
4335 }
4336 else if (sop == 2 && sopcde == 13)
4337 {
4338 OUTS (outf, dregs (dst0));
4339 OUTS (outf, " = ALIGN24 (");
4340 OUTS (outf, dregs (src1));
4341 OUTS (outf, ", ");
4342 OUTS (outf, dregs (src0));
4343 OUTS (outf, ")");
4344 }
4345 else
4346 return 0;
4347
4348 return 4;
4349 }
4350
4351 static int
4352 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4353 {
4354 /* dsp32shiftimm
4355 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4356 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4357 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4358 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4359 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4360 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4361 int bit8 = ((iw1 >> 8) & 0x1);
4362 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4363 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4364 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4365 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4366 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4367
4368
4369 if (sop == 0 && sopcde == 0)
4370 {
4371 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4372 OUTS (outf, " = ");
4373 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4374 OUTS (outf, " >>> ");
4375 OUTS (outf, uimm4 (newimmag));
4376 }
4377 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4378 {
4379 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4380 OUTS (outf, " = ");
4381 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4382 OUTS (outf, " << ");
4383 OUTS (outf, uimm4 (immag));
4384 OUTS (outf, " (S)");
4385 }
4386 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4387 {
4388 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4389 OUTS (outf, " = ");
4390 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4391 OUTS (outf, " >>> ");
4392 OUTS (outf, uimm4 (newimmag));
4393 OUTS (outf, " (S)");
4394 }
4395 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4396 {
4397 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4398 OUTS (outf, " = ");
4399 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4400 OUTS (outf, " << ");
4401 OUTS (outf, uimm4 (immag));
4402 }
4403 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4404 {
4405 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4406 OUTS (outf, " = ");
4407 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4408 OUTS (outf, " >> ");
4409 OUTS (outf, uimm4 (newimmag));
4410 }
4411 else if (sop == 2 && sopcde == 3 && HLs == 1)
4412 {
4413 OUTS (outf, "A1 = ROT A1 BY ");
4414 OUTS (outf, imm6 (immag));
4415 }
4416 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4417 {
4418 OUTS (outf, "A0 = A0 << ");
4419 OUTS (outf, uimm5 (immag));
4420 }
4421 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4422 {
4423 OUTS (outf, "A0 = A0 >>> ");
4424 OUTS (outf, uimm5 (newimmag));
4425 }
4426 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4427 {
4428 OUTS (outf, "A1 = A1 << ");
4429 OUTS (outf, uimm5 (immag));
4430 }
4431 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4432 {
4433 OUTS (outf, "A1 = A1 >>> ");
4434 OUTS (outf, uimm5 (newimmag));
4435 }
4436 else if (sop == 1 && sopcde == 3 && HLs == 0)
4437 {
4438 OUTS (outf, "A0 = A0 >> ");
4439 OUTS (outf, uimm5 (newimmag));
4440 }
4441 else if (sop == 1 && sopcde == 3 && HLs == 1)
4442 {
4443 OUTS (outf, "A1 = A1 >> ");
4444 OUTS (outf, uimm5 (newimmag));
4445 }
4446 else if (sop == 2 && sopcde == 3 && HLs == 0)
4447 {
4448 OUTS (outf, "A0 = ROT A0 BY ");
4449 OUTS (outf, imm6 (immag));
4450 }
4451 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4452 {
4453 OUTS (outf, dregs (dst0));
4454 OUTS (outf, " = ");
4455 OUTS (outf, dregs (src1));
4456 OUTS (outf, " << ");
4457 OUTS (outf, uimm5 (immag));
4458 OUTS (outf, " (V, S)");
4459 }
4460 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4461 {
4462 OUTS (outf, dregs (dst0));
4463 OUTS (outf, " = ");
4464 OUTS (outf, dregs (src1));
4465 OUTS (outf, " >>> ");
4466 OUTS (outf, imm5 (-immag));
4467 OUTS (outf, " (V, S)");
4468 }
4469 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4470 {
4471 OUTS (outf, dregs (dst0));
4472 OUTS (outf, " = ");
4473 OUTS (outf, dregs (src1));
4474 OUTS (outf, " >> ");
4475 OUTS (outf, uimm5 (newimmag));
4476 OUTS (outf, " (V)");
4477 }
4478 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4479 {
4480 OUTS (outf, dregs (dst0));
4481 OUTS (outf, " = ");
4482 OUTS (outf, dregs (src1));
4483 OUTS (outf, " << ");
4484 OUTS (outf, imm5 (immag));
4485 OUTS (outf, " (V)");
4486 }
4487 else if (sop == 0 && sopcde == 1)
4488 {
4489 OUTS (outf, dregs (dst0));
4490 OUTS (outf, " = ");
4491 OUTS (outf, dregs (src1));
4492 OUTS (outf, " >>> ");
4493 OUTS (outf, uimm5 (newimmag));
4494 OUTS (outf, " (V)");
4495 }
4496 else if (sop == 1 && sopcde == 2)
4497 {
4498 OUTS (outf, dregs (dst0));
4499 OUTS (outf, " = ");
4500 OUTS (outf, dregs (src1));
4501 OUTS (outf, " << ");
4502 OUTS (outf, uimm5 (immag));
4503 OUTS (outf, " (S)");
4504 }
4505 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4506 {
4507 OUTS (outf, dregs (dst0));
4508 OUTS (outf, " = ");
4509 OUTS (outf, dregs (src1));
4510 OUTS (outf, " >> ");
4511 OUTS (outf, uimm5 (newimmag));
4512 }
4513 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4514 {
4515 OUTS (outf, dregs (dst0));
4516 OUTS (outf, " = ");
4517 OUTS (outf, dregs (src1));
4518 OUTS (outf, " << ");
4519 OUTS (outf, uimm5 (immag));
4520 }
4521 else if (sop == 3 && sopcde == 2)
4522 {
4523 OUTS (outf, dregs (dst0));
4524 OUTS (outf, " = ROT ");
4525 OUTS (outf, dregs (src1));
4526 OUTS (outf, " BY ");
4527 OUTS (outf, imm6 (immag));
4528 }
4529 else if (sop == 0 && sopcde == 2)
4530 {
4531 OUTS (outf, dregs (dst0));
4532 OUTS (outf, " = ");
4533 OUTS (outf, dregs (src1));
4534 OUTS (outf, " >>> ");
4535 OUTS (outf, uimm5 (newimmag));
4536 }
4537 else
4538 return 0;
4539
4540 return 4;
4541 }
4542
4543 static int
4544 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4545 {
4546 /* pseudoDEBUG
4547 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4548 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4549 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4550 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4551 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4552 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4553
4554 if (reg == 0 && fn == 3)
4555 OUTS (outf, "DBG A0");
4556
4557 else if (reg == 1 && fn == 3)
4558 OUTS (outf, "DBG A1");
4559
4560 else if (reg == 3 && fn == 3)
4561 OUTS (outf, "ABORT");
4562
4563 else if (reg == 4 && fn == 3)
4564 OUTS (outf, "HLT");
4565
4566 else if (reg == 5 && fn == 3)
4567 OUTS (outf, "DBGHALT");
4568
4569 else if (reg == 6 && fn == 3)
4570 {
4571 OUTS (outf, "DBGCMPLX (");
4572 OUTS (outf, dregs (grp));
4573 OUTS (outf, ")");
4574 }
4575 else if (reg == 7 && fn == 3)
4576 OUTS (outf, "DBG");
4577
4578 else if (grp == 0 && fn == 2)
4579 {
4580 OUTS (outf, "OUTC ");
4581 OUTS (outf, dregs (reg));
4582 }
4583 else if (fn == 0)
4584 {
4585 OUTS (outf, "DBG ");
4586 OUTS (outf, allregs (reg, grp));
4587 }
4588 else if (fn == 1)
4589 {
4590 OUTS (outf, "PRNT");
4591 OUTS (outf, allregs (reg, grp));
4592 }
4593 else
4594 return 0;
4595
4596 return 2;
4597 }
4598
4599 static int
4600 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4601 {
4602 /* psedoOChar
4603 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4604 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4605 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4606 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4607
4608 OUTS (outf, "OUTC ");
4609 OUTS (outf, uimm8 (ch));
4610
4611 return 2;
4612 }
4613
4614 static int
4615 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4616 {
4617 /* pseudodbg_assert
4618 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4619 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4620 |.expected......................................................|
4621 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4622 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4623 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4624 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4625 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4626
4627 if (dbgop == 0)
4628 {
4629 OUTS (outf, "DBGA (");
4630 OUTS (outf, regs_lo (regtest, grp));
4631 OUTS (outf, ", ");
4632 OUTS (outf, uimm16 (expected));
4633 OUTS (outf, ")");
4634 }
4635 else if (dbgop == 1)
4636 {
4637 OUTS (outf, "DBGA (");
4638 OUTS (outf, regs_hi (regtest, grp));
4639 OUTS (outf, ", ");
4640 OUTS (outf, uimm16 (expected));
4641 OUTS (outf, ")");
4642 }
4643 else if (dbgop == 2)
4644 {
4645 OUTS (outf, "DBGAL (");
4646 OUTS (outf, allregs (regtest, grp));
4647 OUTS (outf, ", ");
4648 OUTS (outf, uimm16 (expected));
4649 OUTS (outf, ")");
4650 }
4651 else if (dbgop == 3)
4652 {
4653 OUTS (outf, "DBGAH (");
4654 OUTS (outf, allregs (regtest, grp));
4655 OUTS (outf, ", ");
4656 OUTS (outf, uimm16 (expected));
4657 OUTS (outf, ")");
4658 }
4659 else
4660 return 0;
4661 return 4;
4662 }
4663
4664 static int
4665 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4666 {
4667 bfd_byte buf[4];
4668 TIword iw0;
4669 TIword iw1;
4670 int status;
4671 int rv = 0;
4672
4673 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4674 /* FIXME */
4675 (void) status;
4676 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4677 /* FIXME */
4678 (void) status;
4679
4680 iw0 = bfd_getl16 (buf);
4681 iw1 = bfd_getl16 (buf + 2);
4682
4683 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4684 {
4685 OUTS (outf, "MNOP");
4686 return 4;
4687 }
4688 else if ((iw0 & 0xff00) == 0x0000)
4689 rv = decode_ProgCtrl_0 (iw0, outf);
4690 else if ((iw0 & 0xffc0) == 0x0240)
4691 rv = decode_CaCTRL_0 (iw0, outf);
4692 else if ((iw0 & 0xff80) == 0x0100)
4693 rv = decode_PushPopReg_0 (iw0, outf);
4694 else if ((iw0 & 0xfe00) == 0x0400)
4695 rv = decode_PushPopMultiple_0 (iw0, outf);
4696 else if ((iw0 & 0xfe00) == 0x0600)
4697 rv = decode_ccMV_0 (iw0, outf);
4698 else if ((iw0 & 0xf800) == 0x0800)
4699 rv = decode_CCflag_0 (iw0, outf);
4700 else if ((iw0 & 0xffe0) == 0x0200)
4701 rv = decode_CC2dreg_0 (iw0, outf);
4702 else if ((iw0 & 0xff00) == 0x0300)
4703 rv = decode_CC2stat_0 (iw0, outf);
4704 else if ((iw0 & 0xf000) == 0x1000)
4705 rv = decode_BRCC_0 (iw0, pc, outf);
4706 else if ((iw0 & 0xf000) == 0x2000)
4707 rv = decode_UJUMP_0 (iw0, pc, outf);
4708 else if ((iw0 & 0xf000) == 0x3000)
4709 rv = decode_REGMV_0 (iw0, outf);
4710 else if ((iw0 & 0xfc00) == 0x4000)
4711 rv = decode_ALU2op_0 (iw0, outf);
4712 else if ((iw0 & 0xfe00) == 0x4400)
4713 rv = decode_PTR2op_0 (iw0, outf);
4714 else if ((iw0 & 0xf800) == 0x4800)
4715 rv = decode_LOGI2op_0 (iw0, outf);
4716 else if ((iw0 & 0xf000) == 0x5000)
4717 rv = decode_COMP3op_0 (iw0, outf);
4718 else if ((iw0 & 0xf800) == 0x6000)
4719 rv = decode_COMPI2opD_0 (iw0, outf);
4720 else if ((iw0 & 0xf800) == 0x6800)
4721 rv = decode_COMPI2opP_0 (iw0, outf);
4722 else if ((iw0 & 0xf000) == 0x8000)
4723 rv = decode_LDSTpmod_0 (iw0, outf);
4724 else if ((iw0 & 0xff60) == 0x9e60)
4725 rv = decode_dagMODim_0 (iw0, outf);
4726 else if ((iw0 & 0xfff0) == 0x9f60)
4727 rv = decode_dagMODik_0 (iw0, outf);
4728 else if ((iw0 & 0xfc00) == 0x9c00)
4729 rv = decode_dspLDST_0 (iw0, outf);
4730 else if ((iw0 & 0xf000) == 0x9000)
4731 rv = decode_LDST_0 (iw0, outf);
4732 else if ((iw0 & 0xfc00) == 0xb800)
4733 rv = decode_LDSTiiFP_0 (iw0, outf);
4734 else if ((iw0 & 0xe000) == 0xA000)
4735 rv = decode_LDSTii_0 (iw0, outf);
4736 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4737 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4738 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4739 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4740 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4741 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4742 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4743 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4744 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4745 rv = decode_linkage_0 (iw0, iw1, outf);
4746 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4747 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4748 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4749 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4750 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4751 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4752 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4753 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4754 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4755 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4756 else if ((iw0 & 0xff00) == 0xf800)
4757 rv = decode_pseudoDEBUG_0 (iw0, outf);
4758 else if ((iw0 & 0xFF00) == 0xF900)
4759 rv = decode_pseudoOChar_0 (iw0, outf);
4760 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4761 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4762
4763 return rv;
4764 }
4765
4766
4767 int
4768 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4769 {
4770 bfd_byte buf[2];
4771 unsigned short iw0;
4772 int status;
4773 int count = 0;
4774
4775 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4776 /* FIXME */
4777 (void) status;
4778 iw0 = bfd_getl16 (buf);
4779
4780 count += _print_insn_bfin (pc, outf);
4781
4782 /* Proper display of multiple issue instructions. */
4783
4784 if ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4785 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4786 {
4787 parallel = 1;
4788 outf->fprintf_func (outf->stream, " || ");
4789 count += _print_insn_bfin (pc + 4, outf);
4790 outf->fprintf_func (outf->stream, " || ");
4791 count += _print_insn_bfin (pc + 6, outf);
4792 parallel = 0;
4793 }
4794 if (count == 0)
4795 {
4796 outf->fprintf_func (outf->stream, "ILLEGAL");
4797 return 2;
4798 }
4799 if (!comment)
4800 outf->fprintf_func (outf->stream, ";");
4801
4802 comment = 0;
4803
4804 return count;
4805 }
GDB Binutils - Deliverables
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