1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
2 /* Instruction opcode table for bpf.
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
6 Copyright (C) 1996-2019 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
10 This file is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License along
21 with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
32 #include "libiberty.h"
37 /* The hash functions are recorded here to help keep assembler code out of
38 the disassembler and vice versa. */
40 static int asm_hash_insn_p (const CGEN_INSN
*);
41 static unsigned int asm_hash_insn (const char *);
42 static int dis_hash_insn_p (const CGEN_INSN
*);
43 static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT
);
45 /* Instruction formats. */
47 #define F(f) & bpf_cgen_ifld_table[BPF_##f]
48 static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED
= {
52 static const CGEN_IFMT ifmt_addile ATTRIBUTE_UNUSED
= {
53 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_CODE
) }, { F (F_DSTLE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
56 static const CGEN_IFMT ifmt_addrle ATTRIBUTE_UNUSED
= {
57 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_CODE
) }, { F (F_DSTLE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
60 static const CGEN_IFMT ifmt_negle ATTRIBUTE_UNUSED
= {
61 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_CODE
) }, { F (F_DSTLE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
64 static const CGEN_IFMT ifmt_addibe ATTRIBUTE_UNUSED
= {
65 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_CODE
) }, { F (F_SRCBE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
68 static const CGEN_IFMT ifmt_addrbe ATTRIBUTE_UNUSED
= {
69 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_CODE
) }, { F (F_SRCBE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
72 static const CGEN_IFMT ifmt_negbe ATTRIBUTE_UNUSED
= {
73 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_CODE
) }, { F (F_SRCBE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
76 static const CGEN_IFMT ifmt_endlele ATTRIBUTE_UNUSED
= {
77 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_CODE
) }, { F (F_DSTLE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
80 static const CGEN_IFMT ifmt_endlebe ATTRIBUTE_UNUSED
= {
81 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_CODE
) }, { F (F_SRCBE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
84 static const CGEN_IFMT ifmt_lddwle ATTRIBUTE_UNUSED
= {
85 8, 128, 0xff, { { F (F_IMM64
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_DSTLE
) }, { F (F_OP_CLASS
) }, { 0 } }
88 static const CGEN_IFMT ifmt_lddwbe ATTRIBUTE_UNUSED
= {
89 8, 128, 0xff, { { F (F_IMM64
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_SRCBE
) }, { F (F_OP_CLASS
) }, { 0 } }
92 static const CGEN_IFMT ifmt_ldabsw ATTRIBUTE_UNUSED
= {
93 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_REGS
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_OP_CLASS
) }, { 0 } }
96 static const CGEN_IFMT ifmt_ldindwle ATTRIBUTE_UNUSED
= {
97 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_DSTLE
) }, { F (F_OP_CLASS
) }, { 0 } }
100 static const CGEN_IFMT ifmt_ldindwbe ATTRIBUTE_UNUSED
= {
101 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_SRCBE
) }, { F (F_OP_CLASS
) }, { 0 } }
104 static const CGEN_IFMT ifmt_ldxwle ATTRIBUTE_UNUSED
= {
105 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_DSTLE
) }, { F (F_OP_CLASS
) }, { 0 } }
108 static const CGEN_IFMT ifmt_ldxwbe ATTRIBUTE_UNUSED
= {
109 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_SRCBE
) }, { F (F_OP_CLASS
) }, { 0 } }
112 static const CGEN_IFMT ifmt_stble ATTRIBUTE_UNUSED
= {
113 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_DSTLE
) }, { F (F_OP_CLASS
) }, { 0 } }
116 static const CGEN_IFMT ifmt_stbbe ATTRIBUTE_UNUSED
= {
117 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_SRCBE
) }, { F (F_OP_CLASS
) }, { 0 } }
120 static const CGEN_IFMT ifmt_jeqile ATTRIBUTE_UNUSED
= {
121 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_CODE
) }, { F (F_DSTLE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
124 static const CGEN_IFMT ifmt_jeqrle ATTRIBUTE_UNUSED
= {
125 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_CODE
) }, { F (F_DSTLE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
128 static const CGEN_IFMT ifmt_jeqibe ATTRIBUTE_UNUSED
= {
129 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_CODE
) }, { F (F_SRCBE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
132 static const CGEN_IFMT ifmt_jeqrbe ATTRIBUTE_UNUSED
= {
133 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_CODE
) }, { F (F_SRCBE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
136 static const CGEN_IFMT ifmt_ja ATTRIBUTE_UNUSED
= {
137 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_REGS
) }, { F (F_OP_CODE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
140 static const CGEN_IFMT ifmt_call ATTRIBUTE_UNUSED
= {
141 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_REGS
) }, { F (F_OP_CODE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
144 static const CGEN_IFMT ifmt_exit ATTRIBUTE_UNUSED
= {
145 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_REGS
) }, { F (F_OP_CODE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
150 #define A(a) (1 << CGEN_INSN_##a)
151 #define OPERAND(op) BPF_OPERAND_##op
152 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
153 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
155 /* The instruction table. */
157 static const CGEN_OPCODE bpf_cgen_insn_opcode_table
[MAX_INSNS
] =
159 /* Special null first entry.
160 A `num' value of zero is thus invalid.
161 Also, the special `invalid' insn resides here. */
162 { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
163 /* add $dstle,$imm32 */
166 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
167 & ifmt_addile
, { 0x7 }
169 /* add $dstle,$srcle */
172 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
173 & ifmt_addrle
, { 0xf }
175 /* add32 $dstle,$imm32 */
178 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
179 & ifmt_addile
, { 0x4 }
181 /* add32 $dstle,$srcle */
184 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
185 & ifmt_addrle
, { 0xc }
187 /* sub $dstle,$imm32 */
190 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
191 & ifmt_addile
, { 0x17 }
193 /* sub $dstle,$srcle */
196 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
197 & ifmt_addrle
, { 0x1f }
199 /* sub32 $dstle,$imm32 */
202 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
203 & ifmt_addile
, { 0x14 }
205 /* sub32 $dstle,$srcle */
208 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
209 & ifmt_addrle
, { 0x1c }
211 /* mul $dstle,$imm32 */
214 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
215 & ifmt_addile
, { 0x27 }
217 /* mul $dstle,$srcle */
220 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
221 & ifmt_addrle
, { 0x2f }
223 /* mul32 $dstle,$imm32 */
226 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
227 & ifmt_addile
, { 0x24 }
229 /* mul32 $dstle,$srcle */
232 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
233 & ifmt_addrle
, { 0x2c }
235 /* div $dstle,$imm32 */
238 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
239 & ifmt_addile
, { 0x37 }
241 /* div $dstle,$srcle */
244 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
245 & ifmt_addrle
, { 0x3f }
247 /* div32 $dstle,$imm32 */
250 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
251 & ifmt_addile
, { 0x34 }
253 /* div32 $dstle,$srcle */
256 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
257 & ifmt_addrle
, { 0x3c }
259 /* or $dstle,$imm32 */
262 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
263 & ifmt_addile
, { 0x47 }
265 /* or $dstle,$srcle */
268 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
269 & ifmt_addrle
, { 0x4f }
271 /* or32 $dstle,$imm32 */
274 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
275 & ifmt_addile
, { 0x44 }
277 /* or32 $dstle,$srcle */
280 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
281 & ifmt_addrle
, { 0x4c }
283 /* and $dstle,$imm32 */
286 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
287 & ifmt_addile
, { 0x57 }
289 /* and $dstle,$srcle */
292 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
293 & ifmt_addrle
, { 0x5f }
295 /* and32 $dstle,$imm32 */
298 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
299 & ifmt_addile
, { 0x54 }
301 /* and32 $dstle,$srcle */
304 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
305 & ifmt_addrle
, { 0x5c }
307 /* lsh $dstle,$imm32 */
310 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
311 & ifmt_addile
, { 0x67 }
313 /* lsh $dstle,$srcle */
316 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
317 & ifmt_addrle
, { 0x6f }
319 /* lsh32 $dstle,$imm32 */
322 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
323 & ifmt_addile
, { 0x64 }
325 /* lsh32 $dstle,$srcle */
328 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
329 & ifmt_addrle
, { 0x6c }
331 /* rsh $dstle,$imm32 */
334 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
335 & ifmt_addile
, { 0x77 }
337 /* rsh $dstle,$srcle */
340 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
341 & ifmt_addrle
, { 0x7f }
343 /* rsh32 $dstle,$imm32 */
346 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
347 & ifmt_addile
, { 0x74 }
349 /* rsh32 $dstle,$srcle */
352 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
353 & ifmt_addrle
, { 0x7c }
355 /* mod $dstle,$imm32 */
358 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
359 & ifmt_addile
, { 0x97 }
361 /* mod $dstle,$srcle */
364 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
365 & ifmt_addrle
, { 0x9f }
367 /* mod32 $dstle,$imm32 */
370 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
371 & ifmt_addile
, { 0x94 }
373 /* mod32 $dstle,$srcle */
376 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
377 & ifmt_addrle
, { 0x9c }
379 /* xor $dstle,$imm32 */
382 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
383 & ifmt_addile
, { 0xa7 }
385 /* xor $dstle,$srcle */
388 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
389 & ifmt_addrle
, { 0xaf }
391 /* xor32 $dstle,$imm32 */
394 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
395 & ifmt_addile
, { 0xa4 }
397 /* xor32 $dstle,$srcle */
400 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
401 & ifmt_addrle
, { 0xac }
403 /* mov $dstle,$imm32 */
406 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
407 & ifmt_addile
, { 0xb7 }
409 /* mov $dstle,$srcle */
412 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
413 & ifmt_addrle
, { 0xbf }
415 /* mov32 $dstle,$imm32 */
418 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
419 & ifmt_addile
, { 0xb4 }
421 /* mov32 $dstle,$srcle */
424 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
425 & ifmt_addrle
, { 0xbc }
427 /* arsh $dstle,$imm32 */
430 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
431 & ifmt_addile
, { 0xc7 }
433 /* arsh $dstle,$srcle */
436 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
437 & ifmt_addrle
, { 0xcf }
439 /* arsh32 $dstle,$imm32 */
442 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
443 & ifmt_addile
, { 0xc4 }
445 /* arsh32 $dstle,$srcle */
448 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
449 & ifmt_addrle
, { 0xcc }
454 { { MNEM
, ' ', OP (DSTLE
), 0 } },
455 & ifmt_negle
, { 0x8f }
460 { { MNEM
, ' ', OP (DSTLE
), 0 } },
461 & ifmt_negle
, { 0x8c }
463 /* add $dstbe,$imm32 */
466 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
467 & ifmt_addibe
, { 0x7 }
469 /* add $dstbe,$srcbe */
472 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
473 & ifmt_addrbe
, { 0xf }
475 /* add32 $dstbe,$imm32 */
478 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
479 & ifmt_addibe
, { 0x4 }
481 /* add32 $dstbe,$srcbe */
484 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
485 & ifmt_addrbe
, { 0xc }
487 /* sub $dstbe,$imm32 */
490 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
491 & ifmt_addibe
, { 0x17 }
493 /* sub $dstbe,$srcbe */
496 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
497 & ifmt_addrbe
, { 0x1f }
499 /* sub32 $dstbe,$imm32 */
502 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
503 & ifmt_addibe
, { 0x14 }
505 /* sub32 $dstbe,$srcbe */
508 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
509 & ifmt_addrbe
, { 0x1c }
511 /* mul $dstbe,$imm32 */
514 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
515 & ifmt_addibe
, { 0x27 }
517 /* mul $dstbe,$srcbe */
520 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
521 & ifmt_addrbe
, { 0x2f }
523 /* mul32 $dstbe,$imm32 */
526 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
527 & ifmt_addibe
, { 0x24 }
529 /* mul32 $dstbe,$srcbe */
532 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
533 & ifmt_addrbe
, { 0x2c }
535 /* div $dstbe,$imm32 */
538 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
539 & ifmt_addibe
, { 0x37 }
541 /* div $dstbe,$srcbe */
544 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
545 & ifmt_addrbe
, { 0x3f }
547 /* div32 $dstbe,$imm32 */
550 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
551 & ifmt_addibe
, { 0x34 }
553 /* div32 $dstbe,$srcbe */
556 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
557 & ifmt_addrbe
, { 0x3c }
559 /* or $dstbe,$imm32 */
562 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
563 & ifmt_addibe
, { 0x47 }
565 /* or $dstbe,$srcbe */
568 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
569 & ifmt_addrbe
, { 0x4f }
571 /* or32 $dstbe,$imm32 */
574 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
575 & ifmt_addibe
, { 0x44 }
577 /* or32 $dstbe,$srcbe */
580 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
581 & ifmt_addrbe
, { 0x4c }
583 /* and $dstbe,$imm32 */
586 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
587 & ifmt_addibe
, { 0x57 }
589 /* and $dstbe,$srcbe */
592 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
593 & ifmt_addrbe
, { 0x5f }
595 /* and32 $dstbe,$imm32 */
598 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
599 & ifmt_addibe
, { 0x54 }
601 /* and32 $dstbe,$srcbe */
604 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
605 & ifmt_addrbe
, { 0x5c }
607 /* lsh $dstbe,$imm32 */
610 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
611 & ifmt_addibe
, { 0x67 }
613 /* lsh $dstbe,$srcbe */
616 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
617 & ifmt_addrbe
, { 0x6f }
619 /* lsh32 $dstbe,$imm32 */
622 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
623 & ifmt_addibe
, { 0x64 }
625 /* lsh32 $dstbe,$srcbe */
628 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
629 & ifmt_addrbe
, { 0x6c }
631 /* rsh $dstbe,$imm32 */
634 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
635 & ifmt_addibe
, { 0x77 }
637 /* rsh $dstbe,$srcbe */
640 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
641 & ifmt_addrbe
, { 0x7f }
643 /* rsh32 $dstbe,$imm32 */
646 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
647 & ifmt_addibe
, { 0x74 }
649 /* rsh32 $dstbe,$srcbe */
652 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
653 & ifmt_addrbe
, { 0x7c }
655 /* mod $dstbe,$imm32 */
658 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
659 & ifmt_addibe
, { 0x97 }
661 /* mod $dstbe,$srcbe */
664 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
665 & ifmt_addrbe
, { 0x9f }
667 /* mod32 $dstbe,$imm32 */
670 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
671 & ifmt_addibe
, { 0x94 }
673 /* mod32 $dstbe,$srcbe */
676 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
677 & ifmt_addrbe
, { 0x9c }
679 /* xor $dstbe,$imm32 */
682 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
683 & ifmt_addibe
, { 0xa7 }
685 /* xor $dstbe,$srcbe */
688 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
689 & ifmt_addrbe
, { 0xaf }
691 /* xor32 $dstbe,$imm32 */
694 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
695 & ifmt_addibe
, { 0xa4 }
697 /* xor32 $dstbe,$srcbe */
700 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
701 & ifmt_addrbe
, { 0xac }
703 /* mov $dstbe,$imm32 */
706 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
707 & ifmt_addibe
, { 0xb7 }
709 /* mov $dstbe,$srcbe */
712 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
713 & ifmt_addrbe
, { 0xbf }
715 /* mov32 $dstbe,$imm32 */
718 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
719 & ifmt_addibe
, { 0xb4 }
721 /* mov32 $dstbe,$srcbe */
724 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
725 & ifmt_addrbe
, { 0xbc }
727 /* arsh $dstbe,$imm32 */
730 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
731 & ifmt_addibe
, { 0xc7 }
733 /* arsh $dstbe,$srcbe */
736 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
737 & ifmt_addrbe
, { 0xcf }
739 /* arsh32 $dstbe,$imm32 */
742 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
743 & ifmt_addibe
, { 0xc4 }
745 /* arsh32 $dstbe,$srcbe */
748 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
749 & ifmt_addrbe
, { 0xcc }
754 { { MNEM
, ' ', OP (DSTBE
), 0 } },
755 & ifmt_negbe
, { 0x8f }
760 { { MNEM
, ' ', OP (DSTBE
), 0 } },
761 & ifmt_negbe
, { 0x8c }
763 /* endle $dstle,$endsize */
766 { { MNEM
, ' ', OP (DSTLE
), ',', OP (ENDSIZE
), 0 } },
767 & ifmt_endlele
, { 0xd4 }
769 /* endbe $dstle,$endsize */
772 { { MNEM
, ' ', OP (DSTLE
), ',', OP (ENDSIZE
), 0 } },
773 & ifmt_endlele
, { 0xdc }
775 /* endle $dstbe,$endsize */
778 { { MNEM
, ' ', OP (DSTBE
), ',', OP (ENDSIZE
), 0 } },
779 & ifmt_endlebe
, { 0xd4 }
781 /* endbe $dstbe,$endsize */
784 { { MNEM
, ' ', OP (DSTBE
), ',', OP (ENDSIZE
), 0 } },
785 & ifmt_endlebe
, { 0xdc }
787 /* lddw $dstle,$imm64 */
790 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM64
), 0 } },
791 & ifmt_lddwle
, { 0x18 }
793 /* lddw $dstbe,$imm64 */
796 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM64
), 0 } },
797 & ifmt_lddwbe
, { 0x18 }
802 { { MNEM
, ' ', OP (IMM32
), 0 } },
803 & ifmt_ldabsw
, { 0x20 }
808 { { MNEM
, ' ', OP (IMM32
), 0 } },
809 & ifmt_ldabsw
, { 0x28 }
814 { { MNEM
, ' ', OP (IMM32
), 0 } },
815 & ifmt_ldabsw
, { 0x30 }
820 { { MNEM
, ' ', OP (IMM32
), 0 } },
821 & ifmt_ldabsw
, { 0x38 }
823 /* ldindw $srcle,$imm32 */
826 { { MNEM
, ' ', OP (SRCLE
), ',', OP (IMM32
), 0 } },
827 & ifmt_ldindwle
, { 0x40 }
829 /* ldindh $srcle,$imm32 */
832 { { MNEM
, ' ', OP (SRCLE
), ',', OP (IMM32
), 0 } },
833 & ifmt_ldindwle
, { 0x48 }
835 /* ldindb $srcle,$imm32 */
838 { { MNEM
, ' ', OP (SRCLE
), ',', OP (IMM32
), 0 } },
839 & ifmt_ldindwle
, { 0x50 }
841 /* ldinddw $srcle,$imm32 */
844 { { MNEM
, ' ', OP (SRCLE
), ',', OP (IMM32
), 0 } },
845 & ifmt_ldindwle
, { 0x58 }
847 /* ldindw $srcbe,$imm32 */
850 { { MNEM
, ' ', OP (SRCBE
), ',', OP (IMM32
), 0 } },
851 & ifmt_ldindwbe
, { 0x40 }
853 /* ldindh $srcbe,$imm32 */
856 { { MNEM
, ' ', OP (SRCBE
), ',', OP (IMM32
), 0 } },
857 & ifmt_ldindwbe
, { 0x48 }
859 /* ldindb $srcbe,$imm32 */
862 { { MNEM
, ' ', OP (SRCBE
), ',', OP (IMM32
), 0 } },
863 & ifmt_ldindwbe
, { 0x50 }
865 /* ldinddw $srcbe,$imm32 */
868 { { MNEM
, ' ', OP (SRCBE
), ',', OP (IMM32
), 0 } },
869 & ifmt_ldindwbe
, { 0x58 }
871 /* ldxw $dstle,[$srcle+$offset16] */
874 { { MNEM
, ' ', OP (DSTLE
), ',', '[', OP (SRCLE
), '+', OP (OFFSET16
), ']', 0 } },
875 & ifmt_ldxwle
, { 0x61 }
877 /* ldxh $dstle,[$srcle+$offset16] */
880 { { MNEM
, ' ', OP (DSTLE
), ',', '[', OP (SRCLE
), '+', OP (OFFSET16
), ']', 0 } },
881 & ifmt_ldxwle
, { 0x69 }
883 /* ldxb $dstle,[$srcle+$offset16] */
886 { { MNEM
, ' ', OP (DSTLE
), ',', '[', OP (SRCLE
), '+', OP (OFFSET16
), ']', 0 } },
887 & ifmt_ldxwle
, { 0x71 }
889 /* ldxdw $dstle,[$srcle+$offset16] */
892 { { MNEM
, ' ', OP (DSTLE
), ',', '[', OP (SRCLE
), '+', OP (OFFSET16
), ']', 0 } },
893 & ifmt_ldxwle
, { 0x79 }
895 /* stxw [$dstle+$offset16],$srcle */
898 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (SRCLE
), 0 } },
899 & ifmt_ldxwle
, { 0x63 }
901 /* stxh [$dstle+$offset16],$srcle */
904 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (SRCLE
), 0 } },
905 & ifmt_ldxwle
, { 0x6b }
907 /* stxb [$dstle+$offset16],$srcle */
910 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (SRCLE
), 0 } },
911 & ifmt_ldxwle
, { 0x73 }
913 /* stxdw [$dstle+$offset16],$srcle */
916 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (SRCLE
), 0 } },
917 & ifmt_ldxwle
, { 0x7b }
919 /* ldxw $dstbe,[$srcbe+$offset16] */
922 { { MNEM
, ' ', OP (DSTBE
), ',', '[', OP (SRCBE
), '+', OP (OFFSET16
), ']', 0 } },
923 & ifmt_ldxwbe
, { 0x61 }
925 /* ldxh $dstbe,[$srcbe+$offset16] */
928 { { MNEM
, ' ', OP (DSTBE
), ',', '[', OP (SRCBE
), '+', OP (OFFSET16
), ']', 0 } },
929 & ifmt_ldxwbe
, { 0x69 }
931 /* ldxb $dstbe,[$srcbe+$offset16] */
934 { { MNEM
, ' ', OP (DSTBE
), ',', '[', OP (SRCBE
), '+', OP (OFFSET16
), ']', 0 } },
935 & ifmt_ldxwbe
, { 0x71 }
937 /* ldxdw $dstbe,[$srcbe+$offset16] */
940 { { MNEM
, ' ', OP (DSTBE
), ',', '[', OP (SRCBE
), '+', OP (OFFSET16
), ']', 0 } },
941 & ifmt_ldxwbe
, { 0x79 }
943 /* stxw [$dstbe+$offset16],$srcbe */
946 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (SRCBE
), 0 } },
947 & ifmt_ldxwbe
, { 0x63 }
949 /* stxh [$dstbe+$offset16],$srcbe */
952 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (SRCBE
), 0 } },
953 & ifmt_ldxwbe
, { 0x6b }
955 /* stxb [$dstbe+$offset16],$srcbe */
958 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (SRCBE
), 0 } },
959 & ifmt_ldxwbe
, { 0x73 }
961 /* stxdw [$dstbe+$offset16],$srcbe */
964 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (SRCBE
), 0 } },
965 & ifmt_ldxwbe
, { 0x7b }
967 /* stb [$dstle+$offset16],$imm32 */
970 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
971 & ifmt_stble
, { 0x72 }
973 /* sth [$dstle+$offset16],$imm32 */
976 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
977 & ifmt_stble
, { 0x6a }
979 /* stw [$dstle+$offset16],$imm32 */
982 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
983 & ifmt_stble
, { 0x62 }
985 /* stdw [$dstle+$offset16],$imm32 */
988 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
989 & ifmt_stble
, { 0x7a }
991 /* stb [$dstbe+$offset16],$imm32 */
994 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
995 & ifmt_stbbe
, { 0x72 }
997 /* sth [$dstbe+$offset16],$imm32 */
1000 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
1001 & ifmt_stbbe
, { 0x6a }
1003 /* stw [$dstbe+$offset16],$imm32 */
1006 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
1007 & ifmt_stbbe
, { 0x62 }
1009 /* stdw [$dstbe+$offset16],$imm32 */
1012 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
1013 & ifmt_stbbe
, { 0x7a }
1015 /* jeq $dstle,$imm32,$disp16 */
1018 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1019 & ifmt_jeqile
, { 0x15 }
1021 /* jeq $dstle,$srcle,$disp16 */
1024 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1025 & ifmt_jeqrle
, { 0x1d }
1027 /* jgt $dstle,$imm32,$disp16 */
1030 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1031 & ifmt_jeqile
, { 0x25 }
1033 /* jgt $dstle,$srcle,$disp16 */
1036 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1037 & ifmt_jeqrle
, { 0x2d }
1039 /* jge $dstle,$imm32,$disp16 */
1042 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1043 & ifmt_jeqile
, { 0x35 }
1045 /* jge $dstle,$srcle,$disp16 */
1048 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1049 & ifmt_jeqrle
, { 0x3d }
1051 /* jlt $dstle,$imm32,$disp16 */
1054 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1055 & ifmt_jeqile
, { 0xa5 }
1057 /* jlt $dstle,$srcle,$disp16 */
1060 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1061 & ifmt_jeqrle
, { 0xad }
1063 /* jle $dstle,$imm32,$disp16 */
1066 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1067 & ifmt_jeqile
, { 0xb5 }
1069 /* jle $dstle,$srcle,$disp16 */
1072 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1073 & ifmt_jeqrle
, { 0xbd }
1075 /* jset $dstle,$imm32,$disp16 */
1078 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1079 & ifmt_jeqile
, { 0x45 }
1081 /* jset $dstle,$srcle,$disp16 */
1084 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1085 & ifmt_jeqrle
, { 0x4d }
1087 /* jne $dstle,$imm32,$disp16 */
1090 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1091 & ifmt_jeqile
, { 0x55 }
1093 /* jne $dstle,$srcle,$disp16 */
1096 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1097 & ifmt_jeqrle
, { 0x5d }
1099 /* jsgt $dstle,$imm32,$disp16 */
1102 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1103 & ifmt_jeqile
, { 0x65 }
1105 /* jsgt $dstle,$srcle,$disp16 */
1108 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1109 & ifmt_jeqrle
, { 0x6d }
1111 /* jsge $dstle,$imm32,$disp16 */
1114 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1115 & ifmt_jeqile
, { 0x75 }
1117 /* jsge $dstle,$srcle,$disp16 */
1120 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1121 & ifmt_jeqrle
, { 0x7d }
1123 /* jslt $dstle,$imm32,$disp16 */
1126 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1127 & ifmt_jeqile
, { 0xc5 }
1129 /* jslt $dstle,$srcle,$disp16 */
1132 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1133 & ifmt_jeqrle
, { 0xcd }
1135 /* jsle $dstle,$imm32,$disp16 */
1138 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1139 & ifmt_jeqile
, { 0xd5 }
1141 /* jsle $dstle,$srcle,$disp16 */
1144 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1145 & ifmt_jeqrle
, { 0xdd }
1147 /* jeq $dstbe,$imm32,$disp16 */
1150 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1151 & ifmt_jeqibe
, { 0x15 }
1153 /* jeq $dstbe,$srcbe,$disp16 */
1156 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1157 & ifmt_jeqrbe
, { 0x1d }
1159 /* jgt $dstbe,$imm32,$disp16 */
1162 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1163 & ifmt_jeqibe
, { 0x25 }
1165 /* jgt $dstbe,$srcbe,$disp16 */
1168 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1169 & ifmt_jeqrbe
, { 0x2d }
1171 /* jge $dstbe,$imm32,$disp16 */
1174 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1175 & ifmt_jeqibe
, { 0x35 }
1177 /* jge $dstbe,$srcbe,$disp16 */
1180 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1181 & ifmt_jeqrbe
, { 0x3d }
1183 /* jlt $dstbe,$imm32,$disp16 */
1186 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1187 & ifmt_jeqibe
, { 0xa5 }
1189 /* jlt $dstbe,$srcbe,$disp16 */
1192 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1193 & ifmt_jeqrbe
, { 0xad }
1195 /* jle $dstbe,$imm32,$disp16 */
1198 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1199 & ifmt_jeqibe
, { 0xb5 }
1201 /* jle $dstbe,$srcbe,$disp16 */
1204 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1205 & ifmt_jeqrbe
, { 0xbd }
1207 /* jset $dstbe,$imm32,$disp16 */
1210 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1211 & ifmt_jeqibe
, { 0x45 }
1213 /* jset $dstbe,$srcbe,$disp16 */
1216 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1217 & ifmt_jeqrbe
, { 0x4d }
1219 /* jne $dstbe,$imm32,$disp16 */
1222 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1223 & ifmt_jeqibe
, { 0x55 }
1225 /* jne $dstbe,$srcbe,$disp16 */
1228 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1229 & ifmt_jeqrbe
, { 0x5d }
1231 /* jsgt $dstbe,$imm32,$disp16 */
1234 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1235 & ifmt_jeqibe
, { 0x65 }
1237 /* jsgt $dstbe,$srcbe,$disp16 */
1240 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1241 & ifmt_jeqrbe
, { 0x6d }
1243 /* jsge $dstbe,$imm32,$disp16 */
1246 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1247 & ifmt_jeqibe
, { 0x75 }
1249 /* jsge $dstbe,$srcbe,$disp16 */
1252 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1253 & ifmt_jeqrbe
, { 0x7d }
1255 /* jslt $dstbe,$imm32,$disp16 */
1258 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1259 & ifmt_jeqibe
, { 0xc5 }
1261 /* jslt $dstbe,$srcbe,$disp16 */
1264 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1265 & ifmt_jeqrbe
, { 0xcd }
1267 /* jsle $dstbe,$imm32,$disp16 */
1270 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1271 & ifmt_jeqibe
, { 0xd5 }
1273 /* jsle $dstbe,$srcbe,$disp16 */
1276 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1277 & ifmt_jeqrbe
, { 0xdd }
1282 { { MNEM
, ' ', OP (DISP16
), 0 } },
1288 { { MNEM
, ' ', OP (DISP32
), 0 } },
1289 & ifmt_call
, { 0x85 }
1295 & ifmt_exit
, { 0x95 }
1297 /* xadddw [$dstle+$offset16],$srcle */
1300 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (SRCLE
), 0 } },
1301 & ifmt_ldxwle
, { 0xdb }
1303 /* xaddw [$dstle+$offset16],$srcle */
1306 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (SRCLE
), 0 } },
1307 & ifmt_ldxwle
, { 0xc3 }
1309 /* xadddw [$dstbe+$offset16],$srcbe */
1312 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (SRCBE
), 0 } },
1313 & ifmt_ldxwbe
, { 0xdb }
1315 /* xaddw [$dstbe+$offset16],$srcbe */
1318 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (SRCBE
), 0 } },
1319 & ifmt_ldxwbe
, { 0xc3 }
1328 /* Formats for ALIAS macro-insns. */
1330 #define F(f) & bpf_cgen_ifld_table[BPF_##f]
1333 /* Each non-simple macro entry points to an array of expansion possibilities. */
1335 #define A(a) (1 << CGEN_INSN_##a)
1336 #define OPERAND(op) BPF_OPERAND_##op
1337 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1338 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1340 /* The macro instruction table. */
1342 static const CGEN_IBASE bpf_cgen_macro_insn_table
[] =
1346 /* The macro instruction opcode table. */
1348 static const CGEN_OPCODE bpf_cgen_macro_insn_opcode_table
[] =
1357 #ifndef CGEN_ASM_HASH_P
1358 #define CGEN_ASM_HASH_P(insn) 1
1361 #ifndef CGEN_DIS_HASH_P
1362 #define CGEN_DIS_HASH_P(insn) 1
1365 /* Return non-zero if INSN is to be added to the hash table.
1366 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
1369 asm_hash_insn_p (const CGEN_INSN
*insn ATTRIBUTE_UNUSED
)
1371 return CGEN_ASM_HASH_P (insn
);
1375 dis_hash_insn_p (const CGEN_INSN
*insn
)
1377 /* If building the hash table and the NO-DIS attribute is present,
1379 if (CGEN_INSN_ATTR_VALUE (insn
, CGEN_INSN_NO_DIS
))
1381 return CGEN_DIS_HASH_P (insn
);
1384 #ifndef CGEN_ASM_HASH
1385 #define CGEN_ASM_HASH_SIZE 127
1386 #ifdef CGEN_MNEMONIC_OPERANDS
1387 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
1389 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
1393 /* It doesn't make much sense to provide a default here,
1394 but while this is under development we do.
1395 BUFFER is a pointer to the bytes of the insn, target order.
1396 VALUE is the first base_insn_bitsize bits as an int in host order. */
1398 #ifndef CGEN_DIS_HASH
1399 #define CGEN_DIS_HASH_SIZE 256
1400 #define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
1403 /* The result is the hash value of the insn.
1404 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
1407 asm_hash_insn (const char *mnem
)
1409 return CGEN_ASM_HASH (mnem
);
1412 /* BUF is a pointer to the bytes of the insn, target order.
1413 VALUE is the first base_insn_bitsize bits as an int in host order. */
1416 dis_hash_insn (const char *buf ATTRIBUTE_UNUSED
,
1417 CGEN_INSN_INT value ATTRIBUTE_UNUSED
)
1419 return CGEN_DIS_HASH (buf
, value
);
1422 /* Set the recorded length of the insn in the CGEN_FIELDS struct. */
1425 set_fields_bitsize (CGEN_FIELDS
*fields
, int size
)
1427 CGEN_FIELDS_BITSIZE (fields
) = size
;
1430 /* Function to call before using the operand instance table.
1431 This plugs the opcode entries and macro instructions into the cpu table. */
1434 bpf_cgen_init_opcode_table (CGEN_CPU_DESC cd
)
1437 int num_macros
= (sizeof (bpf_cgen_macro_insn_table
) /
1438 sizeof (bpf_cgen_macro_insn_table
[0]));
1439 const CGEN_IBASE
*ib
= & bpf_cgen_macro_insn_table
[0];
1440 const CGEN_OPCODE
*oc
= & bpf_cgen_macro_insn_opcode_table
[0];
1441 CGEN_INSN
*insns
= xmalloc (num_macros
* sizeof (CGEN_INSN
));
1443 /* This test has been added to avoid a warning generated
1444 if memset is called with a third argument of value zero. */
1445 if (num_macros
>= 1)
1446 memset (insns
, 0, num_macros
* sizeof (CGEN_INSN
));
1447 for (i
= 0; i
< num_macros
; ++i
)
1449 insns
[i
].base
= &ib
[i
];
1450 insns
[i
].opcode
= &oc
[i
];
1451 bpf_cgen_build_insn_regex (& insns
[i
]);
1453 cd
->macro_insn_table
.init_entries
= insns
;
1454 cd
->macro_insn_table
.entry_size
= sizeof (CGEN_IBASE
);
1455 cd
->macro_insn_table
.num_init_entries
= num_macros
;
1457 oc
= & bpf_cgen_insn_opcode_table
[0];
1458 insns
= (CGEN_INSN
*) cd
->insn_table
.init_entries
;
1459 for (i
= 0; i
< MAX_INSNS
; ++i
)
1461 insns
[i
].opcode
= &oc
[i
];
1462 bpf_cgen_build_insn_regex (& insns
[i
]);
1465 cd
->sizeof_fields
= sizeof (CGEN_FIELDS
);
1466 cd
->set_fields_bitsize
= set_fields_bitsize
;
1468 cd
->asm_hash_p
= asm_hash_insn_p
;
1469 cd
->asm_hash
= asm_hash_insn
;
1470 cd
->asm_hash_size
= CGEN_ASM_HASH_SIZE
;
1472 cd
->dis_hash_p
= dis_hash_insn_p
;
1473 cd
->dis_hash
= dis_hash_insn
;
1474 cd
->dis_hash_size
= CGEN_DIS_HASH_SIZE
;