1 /* d10v-opc.c -- D10V opcode list
2 Copyright 1996 Free Software Foundation, Inc.
3 Written by Martin Hunt, Cygnus Support
5 This file is part of GDB, GAS, and the GNU binutils.
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 2, or (at your option) any later version.
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23 #include "opcode/d10v.h"
26 /* The table is sorted. Suitable for searching by a binary search. */
27 const struct pd_reg pre_defined_registers
[] =
29 { "a0", NULL
, OPERAND_ACC
+0 },
30 { "a1", NULL
, OPERAND_ACC
+1 },
31 { "bpc", NULL
, OPERAND_CONTROL
+3 },
32 { "bpsw", NULL
, OPERAND_CONTROL
+1 },
33 { "c", NULL
, OPERAND_FLAG
+3 },
34 { "f0", NULL
, OPERAND_FLAG
+0 },
35 { "f1", NULL
, OPERAND_FLAG
+1 },
36 { "iba", NULL
, OPERAND_CONTROL
+14 },
37 { "mod_e", NULL
, OPERAND_CONTROL
+11 },
38 { "mod_s", NULL
, OPERAND_CONTROL
+10 },
39 { "pc", NULL
, OPERAND_CONTROL
+2 },
40 { "psw", NULL
, OPERAND_CONTROL
+0 },
57 { "rpt_c", NULL
, OPERAND_CONTROL
+7 },
58 { "rpt_e", NULL
, OPERAND_CONTROL
+9 },
59 { "rpt_s", NULL
, OPERAND_CONTROL
+8 },
66 return (sizeof(pre_defined_registers
) / sizeof(struct pd_reg
));
69 const struct d10v_operand d10v_operands
[] =
73 #define RSRC (UNUSED + 1)
74 { 4, 1, OPERAND_REG
},
75 #define RDST (RSRC + 1)
76 { 4, 5, OPERAND_DEST
|OPERAND_REG
},
77 #define ASRC (RDST + 1)
78 { 1, 4, OPERAND_ACC
|OPERAND_REG
},
79 #define ADST (ASRC + 1)
80 { 1, 8, OPERAND_DEST
|OPERAND_ACC
|OPERAND_REG
},
81 #define RSRCE (ADST + 1)
82 { 4, 1, OPERAND_EVEN
|OPERAND_REG
},
83 #define RDSTE (RSRCE + 1)
84 { 4, 5, OPERAND_EVEN
|OPERAND_DEST
|OPERAND_REG
},
85 #define NUM16 (RDSTE + 1)
86 { 16, 0, OPERAND_NUM
|OPERAND_SIGNED
},
87 #define NUM3 (NUM16 + 1) /* rac, rachi */
88 { 3, 1, OPERAND_NUM
|OPERAND_SIGNED
},
89 #define NUM4 (NUM3 + 1)
90 { 4, 1, OPERAND_NUM
|OPERAND_SIGNED
},
91 #define UNUM4 (NUM4 + 1)
92 { 4, 1, OPERAND_NUM
},
93 #define UNUM4S (UNUM4 + 1) /* slli, srai, srli, subi */
94 { 4, 1, OPERAND_NUM
|OPERAND_SHIFT
},
95 #define UNUM8 (UNUM4S + 1) /* repi */
96 { 8, 16, OPERAND_NUM
},
97 #define UNUM16 (UNUM8 + 1) /* cmpui */
98 { 16, 0, OPERAND_NUM
},
99 #define ANUM16 (UNUM16 + 1)
100 { 16, 0, OPERAND_ADDR
|OPERAND_SIGNED
},
101 #define ANUM8 (ANUM16 + 1)
102 { 8, 0, OPERAND_ADDR
|OPERAND_SIGNED
},
103 #define ASRC2 (ANUM8 + 1)
104 { 1, 8, OPERAND_ACC
|OPERAND_REG
},
105 #define RSRC2 (ASRC2 + 1)
106 { 4, 5, OPERAND_REG
},
107 #define RSRC2E (RSRC2 + 1)
108 { 4, 5, OPERAND_REG
|OPERAND_EVEN
},
109 #define ASRC0 (RSRC2E + 1)
110 { 1, 0, OPERAND_ACC
|OPERAND_REG
},
111 #define ADST0 (ASRC0 + 1)
112 { 1, 0, OPERAND_ACC
|OPERAND_REG
|OPERAND_DEST
},
113 #define FSRC (ADST0 + 1)
114 { 2, 1, OPERAND_REG
| OPERAND_FLAG
},
115 #define FDST (FSRC + 1)
116 { 1, 5, OPERAND_REG
| OPERAND_FLAG
| OPERAND_DEST
},
117 #define ATSIGN (FDST + 1)
118 { 0, 0, OPERAND_ATSIGN
},
119 #define ATPAR (ATSIGN + 1) /* "@(" */
120 { 0, 0, OPERAND_ATPAR
},
121 #define PLUS (ATPAR + 1) /* postincrement */
122 { 0, 0, OPERAND_PLUS
},
123 #define MINUS (PLUS + 1) /* postdecrement */
124 { 0, 0, OPERAND_MINUS
},
125 #define ATMINUS (MINUS + 1) /* predecrement */
126 { 0, 0, OPERAND_ATMINUS
},
127 #define CSRC (ATMINUS + 1) /* control register */
128 { 4, 1, OPERAND_REG
|OPERAND_CONTROL
},
129 #define CDST (CSRC + 1) /* control register */
130 { 4, 5, OPERAND_REG
|OPERAND_CONTROL
|OPERAND_DEST
},
133 const struct d10v_opcode d10v_opcodes
[] = {
134 { "abs", SHORT_2
, 1, EITHER
, PAR
, 0x4607, 0x7e1f, { RDST
} },
135 { "abs", SHORT_2
, 1, IU
, PAR
, 0x5607, 0x7eff, { ADST
} },
136 { "add", SHORT_2
, 1, EITHER
, PAR
, 0x0200, 0x7e01, { RDST
, RSRC
} },
137 { "add", SHORT_2
, 1, IU
, PAR
, 0x1201, 0x7ee3, { ADST
, RSRCE
} },
138 { "add", SHORT_2
, 1, IU
, PAR
, 0x1203, 0x7eef, { ADST
, ASRC
} },
139 { "add2w", SHORT_2
, 2, IU
, PAR
, 0x1200, 0x7e23, { RDSTE
, RSRCE
} },
140 { "add3", LONG_L
, 1, MU
, SEQ
, 0x1000000, 0x3f000000, { RDST
, RSRC
, NUM16
} },
141 { "addac3", LONG_R
, 1, IU
, SEQ
, 0x17000200, 0x3ffffe22, { RDSTE
, RSRCE
, ASRC0
} },
142 { "addac3", LONG_R
, 1, IU
, SEQ
, 0x17000202, 0x3ffffe2e, { RDSTE
, ASRC
, ASRC0
} },
143 { "addac3s", LONG_R
, 1, IU
, SEQ
, 0x17001200, 0x3ffffe22, { RDSTE
, RSRCE
, ASRC0
} },
144 { "addac3s", LONG_R
, 1, IU
, SEQ
, 0x17001202, 0x3ffffe2e, { RDSTE
, ASRC
, ASRC0
} },
145 { "addi", SHORT_2
, 1, EITHER
, PAR
, 0x201, 0x7e01, { RDST
, UNUM4
} },
146 { "and", SHORT_2
, 1, EITHER
, PAR
, 0xc00, 0x7e01, { RDST
, RSRC
} },
147 { "and3", LONG_L
, 1, MU
, SEQ
, 0x6000000, 0x3f000000, { RDST
, RSRC
, NUM16
} },
148 { "bclri", SHORT_2
, 1, IU
, PAR
, 0xc01, 0x7e01, { RDST
, UNUM4
} },
149 { "bl", OPCODE_FAKE
, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
150 { "bl.s", SHORT_B
, 3, MU
, BRANCH_LINK
, 0x4900, 0x7f00, { ANUM8
} },
151 { "bl.l", LONG_B
, 3, MU
, BRANCH_LINK
, 0x24800000, 0x3fff8000, { ANUM16
} },
152 { "bnoti", SHORT_2
, 1, IU
, PAR
, 0xa01, 0x7e01, { RDST
, UNUM4
} },
153 { "bra", OPCODE_FAKE
, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
154 { "bra.s", SHORT_B
, 3, MU
, PAR
, 0x4800, 0x7f00, { ANUM8
} },
155 { "bra.l", LONG_B
, 3, MU
, SEQ
, 0x24000000, 0x3fff0000, { ANUM16
} },
156 { "brf0f", OPCODE_FAKE
, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
157 { "brf0f.s", SHORT_B
, 3, MU
, PAR
, 0x4a00, 0x7f00, { ANUM8
} },
158 { "brf0f.l", LONG_B
, 3, MU
, SEQ
, 0x25000000, 0x3fff0000, { ANUM16
} },
159 { "brf0t", OPCODE_FAKE
, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
160 { "brf0t.s", SHORT_B
, 3, MU
, PAR
, 0x4b00, 0x7f00, { ANUM8
} },
161 { "brf0t.l", LONG_B
, 3, MU
, SEQ
, 0x25800000, 0x3fff0000, { ANUM16
} },
162 { "bseti", SHORT_2
, 1, IU
, PAR
, 0x801, 0x7e01, { RDST
, UNUM4
} },
163 { "btsti", SHORT_2
, 1, IU
, PAR
, 0xe01, 0x7e01, { RDST
, UNUM4
} },
164 { "clrac", SHORT_2
, 1, IU
, PAR
, 0x5601, 0x7eff, { ADST
} },
165 { "cmp", SHORT_2
, 1, EITHER
, PAR
, 0x600, 0x7e01, { RSRC2
, RSRC
} },
166 { "cmp", SHORT_2
, 1, IU
, PAR
, 0x1603, 0x7eef, { ASRC2
, ASRC
} },
167 { "cmpeq", SHORT_2
, 1, EITHER
, PAR
, 0x400, 0x7e01, { RSRC2
, RSRC
} },
168 { "cmpeq", SHORT_2
, 1, IU
, PAR
, 0x1403, 0x7eef, { ASRC2
, ASRC
} },
169 { "cmpeqi", OPCODE_FAKE
, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } },
170 { "cmpeqi.s", SHORT_2
, 1, EITHER
, PAR
, 0x401, 0x7e01, { RSRC2
, NUM4
} },
171 { "cmpeqi.l", LONG_L
, 1, MU
, SEQ
, 0x2000000, 0x3f0f0000, { RSRC2
, NUM16
} },
172 { "cmpi", OPCODE_FAKE
, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } },
173 { "cmpi.s", SHORT_2
, 1, EITHER
, PAR
, 0x601, 0x7e01, { RSRC2
, NUM4
} },
174 { "cmpi.l", LONG_L
, 1, MU
, SEQ
, 0x3000000, 0x3f0f0000, { RSRC2
, NUM16
} },
175 { "cmpu", SHORT_2
, 1, EITHER
, PAR
, 0x4600, 0x7e01, { RSRC2
, RSRC
} },
176 { "cmpui", LONG_L
, 1, MU
, SEQ
, 0x23000000, 0x3f0f0000, { RSRC2
, UNUM16
} },
177 { "cpfg", SHORT_2
, 1, MU
, PAR
, 0x4e09, 0x7fd9, { FDST
, FSRC
} },
178 { "dbt", SHORT_2
, 5, MU
, PAR
, 0x5f20, 0x7fff, { 0 } },
179 { "divs", LONG_L
, 1, BOTH
, SEQ
, 0x14002800, 0x3f10fe21, { RDSTE
, RSRC
} },
180 { "exef0f", SHORT_2
, 1, EITHER
, PARONLY
, 0x4e04, 0x7fff, { 0 } },
181 { "exef0t", SHORT_2
, 1, EITHER
, PARONLY
, 0x4e24, 0x7fff, { 0 } },
182 { "exef1f", SHORT_2
, 1, EITHER
, PARONLY
, 0x4e40, 0x7fff, { 0 } },
183 { "exef1t", SHORT_2
, 1, EITHER
, PARONLY
, 0x4e42, 0x7fff, { 0 } },
184 { "exefaf", SHORT_2
, 1, EITHER
, PARONLY
, 0x4e00, 0x7fff, { 0 } },
185 { "exefat", SHORT_2
, 1, EITHER
, PARONLY
, 0x4e02, 0x7fff, { 0 } },
186 { "exetaf", SHORT_2
, 1, EITHER
, PARONLY
, 0x4e20, 0x7fff, { 0 } },
187 { "exetat", SHORT_2
, 1, EITHER
, PARONLY
, 0x4e22, 0x7fff, { 0 } },
188 { "exp", LONG_R
, 1, IU
, SEQ
, 0x15002a00, 0x3ffffe03, { RDST
, RSRCE
} },
189 { "exp", LONG_R
, 1, IU
, SEQ
, 0x15002a02, 0x3ffffe0f, { RDST
, ASRC
} },
190 { "jl", SHORT_2
, 3, MU
, BRANCH_LINK
, 0x4d00, 0x7fe1, { RSRC
} },
191 { "jmp", SHORT_2
, 3, MU
, PAR
, 0x4c00, 0x7fe1, { RSRC
} },
192 { "ld", LONG_L
, 1, MU
, SEQ
, 0x30000000, 0x3f000000, { RDST
, ATPAR
, NUM16
, RSRC
} },
193 { "ld", SHORT_2
, 1, MU
, PAR
, 0x6401, 0x7e01, { RDST
, ATSIGN
, RSRC
, MINUS
} },
194 { "ld", SHORT_2
, 1, MU
, PAR
, 0x6001, 0x7e01, { RDST
, ATSIGN
, RSRC
, PLUS
} },
195 { "ld", SHORT_2
, 1, MU
, PAR
, 0x6000, 0x7e01, { RDST
, ATSIGN
, RSRC
} },
196 { "ld2w", LONG_L
, 1, MU
, SEQ
, 0x31000000, 0x3f100000, { RDSTE
, ATPAR
, NUM16
, RSRC
} },
197 { "ld2w", SHORT_2
, 1, MU
, PAR
, 0x6601, 0x7e21, { RDSTE
, ATSIGN
, RSRC
, MINUS
} },
198 { "ld2w", SHORT_2
, 1, MU
, PAR
, 0x6201, 0x7e21, { RDSTE
, ATSIGN
, RSRC
, PLUS
} },
199 { "ld2w", SHORT_2
, 1, MU
, PAR
, 0x6200, 0x7e21, { RDSTE
, ATSIGN
, RSRC
} },
200 { "ldb", LONG_L
, 1, MU
, SEQ
, 0x38000000, 0x3f000000, { RDST
, ATPAR
, NUM16
, RSRC
} },
201 { "ldb", SHORT_2
, 1, MU
, PAR
, 0x7000, 0x7e01, { RDST
, ATSIGN
, RSRC
} },
202 { "ldi", OPCODE_FAKE
, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } },
203 { "ldi.s", SHORT_2
, 1, EITHER
, PAR
,0x4001, 0x7e01 , { RDST
, NUM4
} },
204 { "ldi.l", LONG_L
, 1, MU
, SEQ
, 0x20000000, 0x3f0f0000, { RDST
, NUM16
} },
205 { "ldub", LONG_L
, 1, MU
, SEQ
, 0x39000000, 0x3f000000, { RDST
, ATPAR
, NUM16
, RSRC
} },
206 { "ldub", SHORT_2
, 1, MU
, PAR
, 0x7200, 0x7e01, { RDST
, ATSIGN
, RSRC
} },
207 { "mac", SHORT_2
, 1, IU
, PAR
, 0x2a00, 0x7e00, { ADST0
, RSRC2
, RSRC
} },
208 { "macsu", SHORT_2
, 1, IU
, PAR
, 0x1a00, 0x7e00, { ADST0
, RSRC2
, RSRC
} },
209 { "macu", SHORT_2
, 1, IU
, PAR
, 0x3a00, 0x7e00, { ADST0
, RSRC2
, RSRC
} },
210 { "max", SHORT_2
, 1, IU
, PAR
, 0x2600, 0x7e01, { RDST
, RSRC
} },
211 { "max", SHORT_2
, 1, IU
, PAR
, 0x3600, 0x7ee3, { ADST
, RSRCE
} },
212 { "max", SHORT_2
, 1, IU
, PAR
, 0x3602, 0x7eef, { ADST
, ASRC
} },
213 { "min", SHORT_2
, 1, IU
, PAR
, 0x2601, 0x7e01 , { RDST
, RSRC
} },
214 { "min", SHORT_2
, 1, IU
, PAR
, 0x3601, 0x7ee3 , { ADST
, RSRCE
} },
215 { "min", SHORT_2
, 1, IU
, PAR
, 0x3603, 0x7eef, { ADST
, ASRC
} },
216 { "msb", SHORT_2
, 1, IU
, PAR
, 0x2800, 0x7e00, { ADST0
, RSRC2
, RSRC
} },
217 { "msbsu", SHORT_2
, 1, IU
, PAR
, 0x1800, 0x7e00, { ADST0
, RSRC2
, RSRC
} },
218 { "msbu", SHORT_2
, 1, IU
, PAR
, 0x3800, 0x7e00, { ADST0
, RSRC2
, RSRC
} },
219 { "mul", SHORT_2
, 1, IU
, PAR
, 0x2e00, 0x7e01 , { RDST
, RSRC
} },
220 { "mulx", SHORT_2
, 1, IU
, PAR
, 0x2c00, 0x7e00, { ADST0
, RSRC2
, RSRC
} },
221 { "mulxsu", SHORT_2
, 1, IU
, PAR
, 0x1c00, 0x7e00, { ADST0
, RSRC2
, RSRC
} },
222 { "mulxu", SHORT_2
, 1, IU
, PAR
, 0x3c00, 0x7e00, { ADST0
, RSRC2
, RSRC
} },
223 { "mv", SHORT_2
, 1, EITHER
, PAR
, 0x4000, 0x7e01, { RDST
, RSRC
} },
224 { "mv2w", SHORT_2
, 1, IU
, PAR
, 0x5000, 0x7e23, { RDSTE
, RSRCE
} },
225 { "mv2wfac", SHORT_2
, 1, IU
, PAR
, 0x3e00, 0x7e2f, { RDSTE
, ASRC
} },
226 { "mv2wtac", SHORT_2
, 1, IU
, PAR
, 0x3e01, 0x7ee3, { RSRCE
, ADST
} },
227 { "mvac", SHORT_2
, 1, IU
, PAR
, 0x3e03, 0x7eef, { ADST
, ASRC
} },
228 { "mvb", SHORT_2
, 1, IU
, PAR
, 0x5400, 0x7e01, { RDST
, RSRC
} },
229 { "mvf0f", SHORT_2
, 1, EITHER
, PAR
, 0x4400, 0x7e01, { RDST
, RSRC
} },
230 { "mvf0t", SHORT_2
, 1, EITHER
, PAR
, 0x4401, 0x7e01, { RDST
, RSRC
} },
231 { "mvfacg", SHORT_2
, 1, IU
, PAR
, 0x1e04, 0x7e0f, { RDST
, ASRC
} },
232 { "mvfachi", SHORT_2
, 1, IU
, PAR
, 0x1e00, 0x7e0f, { RDST
, ASRC
} },
233 { "mvfaclo", SHORT_2
, 1, IU
, PAR
, 0x1e02, 0x7e0f, { RDST
, ASRC
} },
234 { "mvfc", SHORT_2
, 1, MU
, PAR
, 0x5200, 0x7e01, { RDST
, CSRC
} },
235 { "mvtacg", SHORT_2
, 1, IU
, PAR
, 0x1e41, 0x7ee1, { RSRC
, ADST
} },
236 { "mvtachi", SHORT_2
, 1, IU
, PAR
, 0x1e01, 0x7ee1, { RSRC
, ADST
} },
237 { "mvtaclo", SHORT_2
, 1, IU
, PAR
, 0x1e21, 0x7ee1, { RSRC
, ADST
} },
238 { "mvtc", SHORT_2
, 1, MU
, PAR
, 0x5600, 0x7e01, { RSRC
, CDST
} },
239 { "mvub", SHORT_2
, 1, IU
, PAR
, 0x5401, 0x7e01, { RDST
, RSRC
} },
240 { "neg", SHORT_2
, 1, EITHER
, PAR
, 0x4605, 0x7e1f, { RDST
} },
241 { "neg", SHORT_2
, 1, IU
, PAR
, 0x5605, 0x7eff, { ADST
} },
242 { "nop", SHORT_2
, 1, EITHER
, PAR
, 0x5e00, 0x7fff, { 0 } },
243 { "not", SHORT_2
, 1, EITHER
, PAR
, 0x4603, 0x7e1f, { RDST
} },
244 { "or", SHORT_2
, 1, EITHER
, PAR
, 0x800, 0x7e01, { RDST
, RSRC
} },
245 { "or3", LONG_L
, 1, MU
, SEQ
, 0x4000000, 0x3f000000, { RDST
, RSRC
, NUM16
} },
246 { "rac", SHORT_2
, 1, IU
, PAR
, 0x5201, 0x7e21, { RDSTE
, ASRC
, NUM3
} },
247 { "rachi", SHORT_2
, 1, IU
, PAR
, 0x4201, 0x7e01, { RDST
, ASRC
, NUM3
} },
248 { "rep", LONG_L
, 2, MU
, SEQ
, 0x27000000, 0x3ff00000, { RSRC
, ANUM16
} },
249 { "repi", LONG_L
, 2, MU
, SEQ
, 0x2f000000, 0x3f000000, { UNUM8
, ANUM16
} },
250 { "rtd", SHORT_2
, 3, MU
, PAR
, 0x5f60, 0x7fff, { 0 } },
251 { "rte", SHORT_2
, 3, MU
, PAR
, 0x5f40, 0x7ff, { 0 } },
252 { "sadd", SHORT_2
, 1, IU
, PAR
, 0x1223, 0x7eef, { ADST
, ASRC
} },
253 { "setf0f", SHORT_2
, 1, MU
, PAR
, 0x4611, 0x7e1f, { RDST
} },
254 { "setf0t", SHORT_2
, 1, MU
, PAR
, 0x4613, 0x7e1f, { RDST
} },
255 { "sleep", SHORT_2
, 1, MU
, PAR
, 0x5fc0, 0x7fff, { 0 } },
256 { "sll", SHORT_2
, 1, IU
, PAR
, 0x2200, 0x7e01, { RDST
, RSRC
} },
257 { "sll", SHORT_2
, 1, IU
, PAR
, 0x3200, 0x7ee1, { ADST
, RSRC
} },
258 { "slli", SHORT_2
, 1, IU
, PAR
, 0x2201, 0x7e01, { RDST
, UNUM4
} },
259 { "slli", SHORT_2
, 1, IU
, PAR
, 0x3201, 0x7ee1, { ADST
, UNUM4S
} },
260 { "slx", SHORT_2
, 1, IU
, PAR
, 0x460b, 0x7e1f, { RDST
} },
261 { "sra", SHORT_2
, 1, IU
, PAR
, 0x2400, 0x7e01, { RDST
, RSRC
} },
262 { "sra", SHORT_2
, 1, IU
, PAR
, 0x3400, 0x7ee1, { ADST
, RSRC
} },
263 { "srai", SHORT_2
, 1, IU
, PAR
, 0x2401, 0x7e01, { RDST
, UNUM4
} },
264 { "srai", SHORT_2
, 1, IU
, PAR
, 0x3401, 0x7ee1, { ADST
, UNUM4S
} },
265 { "srl", SHORT_2
, 1, IU
, PAR
, 0x2000, 0x7e01, { RDST
, RSRC
} },
266 { "srl", SHORT_2
, 1, IU
, PAR
, 0x3000, 0x7ee1, { ADST
, RSRC
} },
267 { "srli", SHORT_2
, 1, IU
, PAR
, 0x2001, 0x7e01, { RDST
, UNUM4
} },
268 { "srli", SHORT_2
, 1, IU
, PAR
, 0x3001, 0x7ee1, { ADST
, UNUM4S
} },
269 { "srx", SHORT_2
, 1, IU
, PAR
, 0x4609, 0x7e1f, { RDST
} },
270 { "st", LONG_L
, 1, MU
, SEQ
, 0x34000000, 0x3f000000, { RSRC2
, ATPAR
, NUM16
, RSRC
} },
271 { "st", SHORT_2
, 1, MU
, PAR
, 0x6800, 0x7e01, { RSRC2
, ATSIGN
, RSRC
} },
272 { "st", SHORT_2
, 1, MU
, PAR
, 0x6c1f, 0x7e1f, { RSRC2
, ATMINUS
, RSRC
} },
273 { "st", SHORT_2
, 1, MU
, PAR
, 0x6801, 0x7e01, { RSRC2
, ATSIGN
, RSRC
, PLUS
} },
274 { "st", SHORT_2
, 1, MU
, PAR
, 0x6c01, 0x7e01, { RSRC2
, ATSIGN
, RSRC
, MINUS
} },
275 { "st2w", LONG_L
, 1, MU
, SEQ
, 0x35000000, 0x3f100000, { RSRC2E
, ATPAR
, NUM16
, RSRC
} },
276 { "st2w", SHORT_2
, 1, MU
, PAR
, 0x6a00, 0x7e21, { RSRC2E
, ATSIGN
, RSRC
} },
277 { "st2w", SHORT_2
, 1, MU
, PAR
, 0x6e1f, 0x7e3f, { RSRC2E
, ATMINUS
, RSRC
} },
278 { "st2w", SHORT_2
, 1, MU
, PAR
, 0x6a01, 0x7e21, { RSRC2E
, ATSIGN
, RSRC
, PLUS
} },
279 { "st2w", SHORT_2
, 1, MU
, PAR
, 0x6e01, 0x7e21, { RSRC2E
, ATSIGN
, RSRC
, MINUS
} },
280 { "stb", LONG_L
, 1, MU
, SEQ
, 0x3c000000, 0x3f000000, { RSRC2
, ATPAR
, NUM16
, RSRC
} },
281 { "stb", SHORT_2
, 1, MU
, PAR
, 0x7800, 0x7e01, { RSRC2
, ATSIGN
, RSRC
} },
282 { "stop", SHORT_2
, 1, MU
, PAR
, 0x5fe0, 0x7fff, { 0 } },
283 { "sub", SHORT_2
, 1, EITHER
, PAR
, 0x0, 0x7e01, { RDST
, RSRC
} },
284 { "sub", SHORT_2
, 1, IU
, PAR
, 0x1001, 0x7ee3, { ADST
, RSRC
} },
285 { "sub", SHORT_2
, 1, IU
, PAR
, 0x1003, 0x7eef, { ADST
, ASRC
} },
286 { "sub2w", SHORT_2
, 1, IU
, PAR
, 0x1000, 0x7e23, { RDSTE
, RSRCE
} },
287 { "subac3", LONG_R
, 1, IU
, SEQ
, 0x17000000, 0x3ffffe22, { RDSTE
, RSRCE
, ASRC0
} },
288 { "subac3", LONG_R
, 1, IU
, SEQ
, 0x17000002, 0x3ffffe2e, { RDSTE
, ASRC
, ASRC0
} },
289 { "subac3s", LONG_R
, 1, IU
, SEQ
, 0x17001000, 0x3ffffe22, { RDSTE
, RSRCE
, ASRC0
} },
290 { "subac3s", LONG_R
, 1, IU
, SEQ
, 0x17001002, 0x3ffffe2e, { RDSTE
, ASRC
, ASRC0
} },
291 { "subi", SHORT_2
, 1, EITHER
, PAR
, 0x1, 0x7e01, { RDST
, UNUM4S
} },
292 { "trap", SHORT_2
, 5, MU
, PAR
, 0x5f00, 0x7fe1, { UNUM4
} },
293 { "tst0i", LONG_L
, 1, MU
, SEQ
, 0x7000000, 0x3f0f0000, { RSRC2
, NUM16
} },
294 { "tst1i", LONG_L
, 1, MU
, SEQ
, 0xf000000, 0x3f0f0000, { RSRC2
, NUM16
} },
295 { "wait", SHORT_2
, 1, MU
, PAR
, 0x5f80, 0x7fff, { 0 } },
296 { "xor", SHORT_2
, 1, EITHER
, PAR
, 0xa00, 0x7e01, { RDST
, RSRC
} },
297 { "xor3", LONG_L
, 1, MU
, SEQ
, 0x5000000, 0x3f000000, { RDST
, RSRC
, NUM16
} },
298 { 0, 0, 0, 0, 0, 0, 0, { 0 } },