1 /* Instruction printing code for the DLX Microprocessor
2 Copyright 2002 Free Software Foundation, Inc.
3 Contributed by Kuang Hwa Lin. Written by Kuang Hwa Lin, 03/2002.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 #include "opcode/dlx.h"
33 #define OPC(x) ((x >> 26) & 0x3F)
34 #define FUNC(x) (x & 0x7FF)
36 unsigned char opc
, rs1
, rs2
, rd
;
37 unsigned long imm26
, imm16
, func
, current_insn_addr
;
39 static unsigned char dlx_get_opcode
PARAMS ((unsigned long));
40 static unsigned char dlx_get_rs1
PARAMS ((unsigned long));
41 static unsigned char dlx_get_rs2
PARAMS ((unsigned long));
42 static unsigned char dlx_get_rdR
PARAMS ((unsigned long));
43 static unsigned long dlx_get_func
PARAMS ((unsigned long));
44 static unsigned long dlx_get_imm16
PARAMS ((unsigned long));
45 static unsigned long dlx_get_imm26
PARAMS ((unsigned long));
46 static void operand_deliminator
PARAMS ((struct disassemble_info
*, char *));
47 static unsigned char dlx_r_type
PARAMS ((struct disassemble_info
*));
48 static unsigned char dlx_load_type
PARAMS ((struct disassemble_info
*));
49 static unsigned char dlx_store_type
PARAMS ((struct disassemble_info
*));
50 static unsigned char dlx_aluI_type
PARAMS ((struct disassemble_info
*));
51 static unsigned char dlx_br_type
PARAMS ((struct disassemble_info
*));
52 static unsigned char dlx_jmp_type
PARAMS ((struct disassemble_info
*));
53 static unsigned char dlx_jr_type
PARAMS ((struct disassemble_info
*));
55 /* Print one instruction from MEMADDR on INFO->STREAM.
56 Return the size of the instruction (always 4 on dlx). */
59 dlx_get_opcode (opcode
)
62 return (unsigned char) ((opcode
>> 26) & 0x3F);
69 return (unsigned char) ((opcode
>> 21) & 0x1F);
76 return (unsigned char) ((opcode
>> 16) & 0x1F);
83 return (unsigned char) ((opcode
>> 11) & 0x1F);
90 return (unsigned char) (opcode
& 0x7FF);
94 dlx_get_imm16 (opcode
)
97 return (unsigned long) (opcode
& 0xFFFF);
101 dlx_get_imm26 (opcode
)
102 unsigned long opcode
;
104 return (unsigned long) (opcode
& 0x03FFFFFF);
107 /* Fill the opcode to the max length. */
109 operand_deliminator (info
, ptr
)
110 struct disassemble_info
*info
;
113 int difft
= 8 - (int) strlen (ptr
);
117 (*info
->fprintf_func
) (info
->stream
, "%c", ' ');
122 /* Process the R-type opcode. */
125 struct disassemble_info
*info
;
127 unsigned char r_opc
[] = { OPC(ALUOP
) }; /* Fix ME */
128 int r_opc_num
= (sizeof r_opc
) / (sizeof (char));
136 { NOPF
, "nop" }, /* NOP */
137 { ADDF
, "add" }, /* Add */
138 { ADDUF
, "addu" }, /* Add Unsigned */
139 { SUBF
, "sub" }, /* SUB */
140 { SUBUF
, "subu" }, /* Sub Unsigned */
141 { MULTF
, "mult" }, /* MULTIPLY */
142 { MULTUF
, "multu" }, /* MULTIPLY Unsigned */
143 { DIVF
, "div" }, /* DIVIDE */
144 { DIVUF
, "divu" }, /* DIVIDE Unsigned */
145 { ANDF
, "and" }, /* AND */
146 { ORF
, "or" }, /* OR */
147 { XORF
, "xor" }, /* Exclusive OR */
148 { SLLF
, "sll" }, /* SHIFT LEFT LOGICAL */
149 { SRAF
, "sra" }, /* SHIFT RIGHT ARITHMETIC */
150 { SRLF
, "srl" }, /* SHIFT RIGHT LOGICAL */
151 { SEQF
, "seq" }, /* Set if equal */
152 { SNEF
, "sne" }, /* Set if not equal */
153 { SLTF
, "slt" }, /* Set if less */
154 { SGTF
, "sgt" }, /* Set if greater */
155 { SLEF
, "sle" }, /* Set if less or equal */
156 { SGEF
, "sge" }, /* Set if greater or equal */
157 { SEQUF
, "sequ" }, /* Set if equal */
158 { SNEUF
, "sneu" }, /* Set if not equal */
159 { SLTUF
, "sltu" }, /* Set if less */
160 { SGTUF
, "sgtu" }, /* Set if greater */
161 { SLEUF
, "sleu" }, /* Set if less or equal */
162 { SGEUF
, "sgeu" }, /* Set if greater or equal */
163 { MVTSF
, "mvts" }, /* Move to special register */
164 { MVFSF
, "mvfs" }, /* Move from special register */
165 { BSWAPF
, "bswap" }, /* Byte swap ?? */
166 { LUTF
, "lut" } /* ????????? ?? */
168 int dlx_r_opcode_num
= (sizeof dlx_r_opcode
) / (sizeof dlx_r_opcode
[0]);
171 for (idx
= 0; idx
< r_opc_num
; idx
++)
173 if (r_opc
[idx
] != opc
)
179 if (idx
== r_opc_num
)
182 for (idx
= 0 ; idx
< dlx_r_opcode_num
; idx
++)
183 if (dlx_r_opcode
[idx
].func
== func
)
185 (*info
->fprintf_func
) (info
->stream
, "%s", dlx_r_opcode
[idx
].name
);
189 /* This is not a nop. */
190 operand_deliminator (info
, dlx_r_opcode
[idx
].name
);
191 (*info
->fprintf_func
) (info
->stream
, "r%d,", (int)rd
);
192 (*info
->fprintf_func
) (info
->stream
, "r%d", (int)rs1
);
193 if (func
!= MVTSF
&& func
!= MVFSF
)
194 (*info
->fprintf_func
) (info
->stream
, ",r%d", (int)rs2
);
196 return (unsigned char) R_TYPE
;
199 return (unsigned char) R_ERROR
;
202 /* Process the memory read opcode. */
206 struct disassemble_info
* info
;
210 unsigned long opcode
;
215 { OPC(LHIOP
), "lhi" }, /* Load HI to register. */
216 { OPC(LBOP
), "lb" }, /* load byte sign extended. */
217 { OPC(LBUOP
), "lbu" }, /* load byte unsigned. */
218 { OPC(LSBUOP
),"ldstbu"}, /* load store byte unsigned. */
219 { OPC(LHOP
), "lh" }, /* load halfword sign extended. */
220 { OPC(LHUOP
), "lhu" }, /* load halfword unsigned. */
221 { OPC(LSHUOP
),"ldsthu"}, /* load store halfword unsigned. */
222 { OPC(LWOP
), "lw" }, /* load word. */
223 { OPC(LSWOP
), "ldstw" } /* load store word. */
225 int dlx_load_opcode_num
=
226 (sizeof dlx_load_opcode
) / (sizeof dlx_load_opcode
[0]);
229 for (idx
= 0 ; idx
< dlx_load_opcode_num
; idx
++)
230 if (dlx_load_opcode
[idx
].opcode
== opc
)
232 if (opc
== OPC (LHIOP
))
234 (*info
->fprintf_func
) (info
->stream
, "%s", dlx_load_opcode
[idx
].name
);
235 operand_deliminator (info
, dlx_load_opcode
[idx
].name
);
236 (*info
->fprintf_func
) (info
->stream
, "r%d,", (int)rs2
);
237 (*info
->fprintf_func
) (info
->stream
, "0x%04x", (int)imm16
);
241 (*info
->fprintf_func
) (info
->stream
, "%s", dlx_load_opcode
[idx
].name
);
242 operand_deliminator (info
, dlx_load_opcode
[idx
].name
);
243 (*info
->fprintf_func
) (info
->stream
, "r%d,", (int)rs2
);
244 (*info
->fprintf_func
) (info
->stream
, "0x%04x[r%d]", (int)imm16
, (int)rs1
);
247 return (unsigned char) ILD_TYPE
;
250 return (unsigned char) NIL
;
253 /* Process the memory store opcode. */
256 dlx_store_type (info
)
257 struct disassemble_info
* info
;
261 unsigned long opcode
;
266 { OPC(SBOP
), "sb" }, /* Store byte. */
267 { OPC(SHOP
), "sh" }, /* Store halfword. */
268 { OPC(SWOP
), "sw" }, /* Store word. */
270 int dlx_store_opcode_num
=
271 (sizeof dlx_store_opcode
) / (sizeof dlx_store_opcode
[0]);
274 for (idx
= 0 ; idx
< dlx_store_opcode_num
; idx
++)
275 if (dlx_store_opcode
[idx
].opcode
== opc
)
277 (*info
->fprintf_func
) (info
->stream
, "%s", dlx_store_opcode
[idx
].name
);
278 operand_deliminator (info
, dlx_store_opcode
[idx
].name
);
279 (*info
->fprintf_func
) (info
->stream
, "0x%04x[r%d],", (int)imm16
, (int)rs1
);
280 (*info
->fprintf_func
) (info
->stream
, "r%d", (int)rs2
);
281 return (unsigned char) IST_TYPE
;
284 return (unsigned char) NIL
;
287 /* Process the Arithmetic and Logical I-TYPE opcode. */
291 struct disassemble_info
* info
;
295 unsigned long opcode
;
300 { OPC(ADDIOP
), "addi" }, /* Store byte. */
301 { OPC(ADDUIOP
), "addui" }, /* Store halfword. */
302 { OPC(SUBIOP
), "subi" }, /* Store word. */
303 { OPC(SUBUIOP
), "subui" }, /* Store word. */
304 { OPC(ANDIOP
), "andi" }, /* Store word. */
305 { OPC(ORIOP
), "ori" }, /* Store word. */
306 { OPC(XORIOP
), "xori" }, /* Store word. */
307 { OPC(SLLIOP
), "slli" }, /* Store word. */
308 { OPC(SRAIOP
), "srai" }, /* Store word. */
309 { OPC(SRLIOP
), "srli" }, /* Store word. */
310 { OPC(SEQIOP
), "seqi" }, /* Store word. */
311 { OPC(SNEIOP
), "snei" }, /* Store word. */
312 { OPC(SLTIOP
), "slti" }, /* Store word. */
313 { OPC(SGTIOP
), "sgti" }, /* Store word. */
314 { OPC(SLEIOP
), "slei" }, /* Store word. */
315 { OPC(SGEIOP
), "sgei" }, /* Store word. */
316 { OPC(SEQUIOP
), "sequi" }, /* Store word. */
317 { OPC(SNEUIOP
), "sneui" }, /* Store word. */
318 { OPC(SLTUIOP
), "sltui" }, /* Store word. */
319 { OPC(SGTUIOP
), "sgtui" }, /* Store word. */
320 { OPC(SLEUIOP
), "sleui" }, /* Store word. */
321 { OPC(SGEUIOP
), "sgeui" }, /* Store word. */
323 { OPC(MVTSOP
), "mvts" }, /* Store word. */
324 { OPC(MVFSOP
), "mvfs" }, /* Store word. */
327 int dlx_aluI_opcode_num
=
328 (sizeof dlx_aluI_opcode
) / (sizeof dlx_aluI_opcode
[0]);
331 for (idx
= 0 ; idx
< dlx_aluI_opcode_num
; idx
++)
332 if (dlx_aluI_opcode
[idx
].opcode
== opc
)
334 (*info
->fprintf_func
) (info
->stream
, "%s", dlx_aluI_opcode
[idx
].name
);
335 operand_deliminator (info
, dlx_aluI_opcode
[idx
].name
);
336 (*info
->fprintf_func
) (info
->stream
, "r%d,", (int)rs2
);
337 (*info
->fprintf_func
) (info
->stream
, "r%d,", (int)rs1
);
338 (*info
->fprintf_func
) (info
->stream
, "0x%04x", (int)imm16
);
340 return (unsigned char) IAL_TYPE
;
343 return (unsigned char) NIL
;
346 /* Process the branch instruction. */
350 struct disassemble_info
* info
;
354 unsigned long opcode
;
359 { OPC(BEQOP
), "beqz" }, /* Store byte. */
360 { OPC(BNEOP
), "bnez" } /* Store halfword. */
362 int dlx_br_opcode_num
=
363 (sizeof dlx_br_opcode
) / (sizeof dlx_br_opcode
[0]);
366 for (idx
= 0 ; idx
< dlx_br_opcode_num
; idx
++)
367 if (dlx_br_opcode
[idx
].opcode
== opc
)
369 if (imm16
& 0x00008000)
372 imm16
+= (current_insn_addr
+ 4);
373 (*info
->fprintf_func
) (info
->stream
, "%s", dlx_br_opcode
[idx
].name
);
374 operand_deliminator (info
, dlx_br_opcode
[idx
].name
);
375 (*info
->fprintf_func
) (info
->stream
, "r%d,", (int)rs1
);
376 (*info
->fprintf_func
) (info
->stream
, "0x%08x", (int)imm16
);
378 return (unsigned char) IBR_TYPE
;
381 return (unsigned char) NIL
;
384 /* Process the jump instruction. */
388 struct disassemble_info
* info
;
392 unsigned long opcode
;
397 { OPC(JOP
), "j" }, /* Store byte. */
398 { OPC(JALOP
), "jal" }, /* Store halfword. */
399 { OPC(BREAKOP
), "break" }, /* Store halfword. */
400 { OPC(TRAPOP
), "trap" }, /* Store halfword. */
401 { OPC(RFEOP
), "rfe" } /* Store halfword. */
403 int dlx_jmp_opcode_num
=
404 (sizeof dlx_jmp_opcode
) / (sizeof dlx_jmp_opcode
[0]);
407 for (idx
= 0 ; idx
< dlx_jmp_opcode_num
; idx
++)
408 if (dlx_jmp_opcode
[idx
].opcode
== opc
)
410 if (imm26
& 0x02000000)
413 imm26
+= (current_insn_addr
+ 4);
415 (*info
->fprintf_func
) (info
->stream
, "%s", dlx_jmp_opcode
[idx
].name
);
416 operand_deliminator (info
, dlx_jmp_opcode
[idx
].name
);
417 (*info
->fprintf_func
) (info
->stream
, "0x%08x", (int)imm26
);
419 return (unsigned char) IJ_TYPE
;
422 return (unsigned char) NIL
;
425 /* Process the jump register instruction. */
429 struct disassemble_info
* info
;
433 unsigned long opcode
;
437 { OPC(JROP
), "jr" }, /* Store byte. */
438 { OPC(JALROP
), "jalr" } /* Store halfword. */
440 int dlx_jr_opcode_num
=
441 (sizeof dlx_jr_opcode
) / (sizeof dlx_jr_opcode
[0]);
444 for (idx
= 0 ; idx
< dlx_jr_opcode_num
; idx
++)
445 if (dlx_jr_opcode
[idx
].opcode
== opc
)
447 (*info
->fprintf_func
) (info
->stream
, "%s", dlx_jr_opcode
[idx
].name
);
448 operand_deliminator (info
, dlx_jr_opcode
[idx
].name
);
449 (*info
->fprintf_func
) (info
->stream
, "r%d", (int)rs1
);
450 return (unsigned char) IJR_TYPE
;
453 return (unsigned char) NIL
;
456 typedef unsigned char (* dlx_insn
) PARAMS ((struct disassemble_info
*));
458 /* This is the main DLX insn handling routine. */
461 print_insn_dlx (memaddr
, info
)
463 struct disassemble_info
* info
;
467 unsigned long insn_word
;
468 unsigned char rtn_code
;
469 unsigned long dlx_insn_type
[] =
471 (unsigned long) dlx_r_type
,
472 (unsigned long) dlx_load_type
,
473 (unsigned long) dlx_store_type
,
474 (unsigned long) dlx_aluI_type
,
475 (unsigned long) dlx_br_type
,
476 (unsigned long) dlx_jmp_type
,
477 (unsigned long) dlx_jr_type
,
480 int dlx_insn_type_num
= ((sizeof dlx_insn_type
) / (sizeof (unsigned long))) - 1;
482 (*info
->read_memory_func
) (memaddr
, (bfd_byte
*) &buffer
[0], 4, info
);
486 (*info
->memory_error_func
) (status
, memaddr
, info
);
490 /* Now decode the insn */
491 insn_word
= bfd_getb32 (buffer
);
492 opc
= dlx_get_opcode (insn_word
);
493 rs1
= dlx_get_rs1 (insn_word
);
494 rs2
= dlx_get_rs2 (insn_word
);
495 rd
= dlx_get_rdR (insn_word
);
496 func
= dlx_get_func (insn_word
);
497 imm16
= dlx_get_imm16 (insn_word
);
498 imm26
= dlx_get_imm26 (insn_word
);
501 printf ("print_insn_big_dlx: opc = 0x%02x\n"
508 opc
, rs1
, rs2
, rd
, func
, imm16
, imm26
);
511 /* Scan through all the insn type and print the insn out. */
513 current_insn_addr
= (unsigned long) memaddr
;
515 for (insn_idx
= 0; dlx_insn_type
[insn_idx
] != 0x0; insn_idx
++)
516 switch (((dlx_insn
) (dlx_insn_type
[insn_idx
])) (info
))
518 /* Found the correct opcode */
528 /* Wrong insn type check next one. */
533 /* All rest of the return code are not recongnized, treat it as error */
534 /* we should never get here, I hope! */
539 if (insn_idx
== dlx_insn_type_num
)
540 /* Well, does not recoganize this opcode. */
541 (*info
->fprintf_func
) (info
->stream
, "<%s>", "Unrecognized Opcode");
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