opcodes/fr30-desc.c

   1 /* CPU data for fr30.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include "ansidecl.h"
  29 #include "bfd.h"
  30 #include "symcat.h"
  31 #include "fr30-desc.h"
  32 #include "fr30-opc.h"
  33 #include "opintl.h"
  34 #include "libiberty.h"
  35
  36 /* Attributes.  */
  37
  38 static const CGEN_ATTR_ENTRY bool_attr[] =
  39 {
  40   { "#f", 0 },
  41   { "#t", 1 },
  42   { 0, 0 }
  43 };
  44
  45 static const CGEN_ATTR_ENTRY MACH_attr[] =
  46 {
  47   { "base", MACH_BASE },
  48   { "fr30", MACH_FR30 },
  49   { "max", MACH_MAX },
  50   { 0, 0 }
  51 };
  52
  53 static const CGEN_ATTR_ENTRY ISA_attr[] =
  54 {
  55   { "fr30", ISA_FR30 },
  56   { "max", ISA_MAX },
  57   { 0, 0 }
  58 };
  59
  60 const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
  61 {
  62   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  63   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  64   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  65   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  66   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  67   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  68   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  69   { 0, 0, 0 }
  70 };
  71
  72 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
  73 {
  74   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  75   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  76   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  77   { "PC", &bool_attr[0], &bool_attr[0] },
  78   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  79   { 0, 0, 0 }
  80 };
  81
  82 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
  83 {
  84   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  85   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  86   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  87   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  88   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  89   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  90   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
  91   { "RELAX", &bool_attr[0], &bool_attr[0] },
  92   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
  93   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
  94   { 0, 0, 0 }
  95 };
  96
  97 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
  98 {
  99   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 100   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 101   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 102   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 103   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 104   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 105   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 106   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 107   { "RELAX", &bool_attr[0], &bool_attr[0] },
 108   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 109   { "PBB", &bool_attr[0], &bool_attr[0] },
 110   { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 111   { 0, 0, 0 }
 112 };
 113
 114 /* Instruction set variants.  */
 115
 116 static const CGEN_ISA fr30_cgen_isa_table[] = {
 117   { "fr30", 16, 16, 16, 48 },
 118   { 0, 0, 0, 0, 0 }
 119 };
 120
 121 /* Machine variants.  */
 122
 123 static const CGEN_MACH fr30_cgen_mach_table[] = {
 124   { "fr30", "fr30", MACH_FR30, 0 },
 125   { 0, 0, 0, 0 }
 126 };
 127
 128 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
 129 {
 130   { "r0", 0, {0, {0}}, 0, 0 },
 131   { "r1", 1, {0, {0}}, 0, 0 },
 132   { "r2", 2, {0, {0}}, 0, 0 },
 133   { "r3", 3, {0, {0}}, 0, 0 },
 134   { "r4", 4, {0, {0}}, 0, 0 },
 135   { "r5", 5, {0, {0}}, 0, 0 },
 136   { "r6", 6, {0, {0}}, 0, 0 },
 137   { "r7", 7, {0, {0}}, 0, 0 },
 138   { "r8", 8, {0, {0}}, 0, 0 },
 139   { "r9", 9, {0, {0}}, 0, 0 },
 140   { "r10", 10, {0, {0}}, 0, 0 },
 141   { "r11", 11, {0, {0}}, 0, 0 },
 142   { "r12", 12, {0, {0}}, 0, 0 },
 143   { "r13", 13, {0, {0}}, 0, 0 },
 144   { "r14", 14, {0, {0}}, 0, 0 },
 145   { "r15", 15, {0, {0}}, 0, 0 },
 146   { "ac", 13, {0, {0}}, 0, 0 },
 147   { "fp", 14, {0, {0}}, 0, 0 },
 148   { "sp", 15, {0, {0}}, 0, 0 }
 149 };
 150
 151 CGEN_KEYWORD fr30_cgen_opval_gr_names =
 152 {
 153   & fr30_cgen_opval_gr_names_entries[0],
 154   19,
 155   0, 0, 0, 0, ""
 156 };
 157
 158 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
 159 {
 160   { "cr0", 0, {0, {0}}, 0, 0 },
 161   { "cr1", 1, {0, {0}}, 0, 0 },
 162   { "cr2", 2, {0, {0}}, 0, 0 },
 163   { "cr3", 3, {0, {0}}, 0, 0 },
 164   { "cr4", 4, {0, {0}}, 0, 0 },
 165   { "cr5", 5, {0, {0}}, 0, 0 },
 166   { "cr6", 6, {0, {0}}, 0, 0 },
 167   { "cr7", 7, {0, {0}}, 0, 0 },
 168   { "cr8", 8, {0, {0}}, 0, 0 },
 169   { "cr9", 9, {0, {0}}, 0, 0 },
 170   { "cr10", 10, {0, {0}}, 0, 0 },
 171   { "cr11", 11, {0, {0}}, 0, 0 },
 172   { "cr12", 12, {0, {0}}, 0, 0 },
 173   { "cr13", 13, {0, {0}}, 0, 0 },
 174   { "cr14", 14, {0, {0}}, 0, 0 },
 175   { "cr15", 15, {0, {0}}, 0, 0 }
 176 };
 177
 178 CGEN_KEYWORD fr30_cgen_opval_cr_names =
 179 {
 180   & fr30_cgen_opval_cr_names_entries[0],
 181   16,
 182   0, 0, 0, 0, ""
 183 };
 184
 185 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
 186 {
 187   { "tbr", 0, {0, {0}}, 0, 0 },
 188   { "rp", 1, {0, {0}}, 0, 0 },
 189   { "ssp", 2, {0, {0}}, 0, 0 },
 190   { "usp", 3, {0, {0}}, 0, 0 },
 191   { "mdh", 4, {0, {0}}, 0, 0 },
 192   { "mdl", 5, {0, {0}}, 0, 0 }
 193 };
 194
 195 CGEN_KEYWORD fr30_cgen_opval_dr_names =
 196 {
 197   & fr30_cgen_opval_dr_names_entries[0],
 198   6,
 199   0, 0, 0, 0, ""
 200 };
 201
 202 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
 203 {
 204   { "ps", 0, {0, {0}}, 0, 0 }
 205 };
 206
 207 CGEN_KEYWORD fr30_cgen_opval_h_ps =
 208 {
 209   & fr30_cgen_opval_h_ps_entries[0],
 210   1,
 211   0, 0, 0, 0, ""
 212 };
 213
 214 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
 215 {
 216   { "r13", 0, {0, {0}}, 0, 0 }
 217 };
 218
 219 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
 220 {
 221   & fr30_cgen_opval_h_r13_entries[0],
 222   1,
 223   0, 0, 0, 0, ""
 224 };
 225
 226 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
 227 {
 228   { "r14", 0, {0, {0}}, 0, 0 }
 229 };
 230
 231 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
 232 {
 233   & fr30_cgen_opval_h_r14_entries[0],
 234   1,
 235   0, 0, 0, 0, ""
 236 };
 237
 238 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
 239 {
 240   { "r15", 0, {0, {0}}, 0, 0 }
 241 };
 242
 243 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
 244 {
 245   & fr30_cgen_opval_h_r15_entries[0],
 246   1,
 247   0, 0, 0, 0, ""
 248 };
 249
 250
 251 /* The hardware table.  */
 252
 253 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 254 #define A(a) (1 << CGEN_HW_##a)
 255 #else
 256 #define A(a) (1 << CGEN_HW_/**/a)
 257 #endif
 258
 259 const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
 260 {
 261   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 262   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 263   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 264   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 265   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 266   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
 267   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
 268   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
 269   { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { (1<<MACH_BASE) } } },
 270   { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { (1<<MACH_BASE) } } },
 271   { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { (1<<MACH_BASE) } } },
 272   { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { (1<<MACH_BASE) } } },
 273   { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { (1<<MACH_BASE) } } },
 274   { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 275   { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 276   { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 277   { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 278   { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 279   { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 280   { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 281   { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 282   { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 283   { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 284   { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 285   { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 286   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
 287 };
 288
 289 #undef A
 290
 291
 292 /* The instruction field table.  */
 293
 294 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 295 #define A(a) (1 << CGEN_IFLD_##a)
 296 #else
 297 #define A(a) (1 << CGEN_IFLD_/**/a)
 298 #endif
 299
 300 const CGEN_IFLD fr30_cgen_ifld_table[] =
 301 {
 302   { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 303   { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 304   { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { (1<<MACH_BASE) } }  },
 305   { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } }  },
 306   { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 307   { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 308   { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { (1<<MACH_BASE) } }  },
 309   { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } }  },
 310   { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { (1<<MACH_BASE) } }  },
 311   { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 312   { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 313   { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 314   { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 315   { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 316   { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 317   { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 318   { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 319   { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 320   { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 321   { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 322   { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 323   { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 324   { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
 325   { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 326   { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { (1<<MACH_BASE) } }  },
 327   { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 328   { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 329   { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
 330   { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
 331   { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
 332   { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 333   { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 334   { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 335   { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 336   { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 337   { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 338   { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 339   { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 340   { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 341   { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 342   { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 343   { 0, 0, 0, 0, 0, 0, {0, {0}} }
 344 };
 345
 346 #undef A
 347
 348
 349 /* The operand table.  */
 350
 351 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 352 #define A(a) (1 << CGEN_OPERAND_##a)
 353 #else
 354 #define A(a) (1 << CGEN_OPERAND_/**/a)
 355 #endif
 356 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 357 #define OPERAND(op) FR30_OPERAND_##op
 358 #else
 359 #define OPERAND(op) FR30_OPERAND_/**/op
 360 #endif
 361
 362 const CGEN_OPERAND fr30_cgen_operand_table[] =
 363 {
 364 /* pc: program counter */
 365   { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
 366     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 367 /* Ri: destination register */
 368   { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
 369     { 0, { (1<<MACH_BASE) } }  },
 370 /* Rj: source register */
 371   { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
 372     { 0, { (1<<MACH_BASE) } }  },
 373 /* Ric: target register coproc insn */
 374   { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
 375     { 0, { (1<<MACH_BASE) } }  },
 376 /* Rjc: source register coproc insn */
 377   { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
 378     { 0, { (1<<MACH_BASE) } }  },
 379 /* CRi: coprocessor register */
 380   { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
 381     { 0, { (1<<MACH_BASE) } }  },
 382 /* CRj: coprocessor register */
 383   { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
 384     { 0, { (1<<MACH_BASE) } }  },
 385 /* Rs1: dedicated register */
 386   { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
 387     { 0, { (1<<MACH_BASE) } }  },
 388 /* Rs2: dedicated register */
 389   { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
 390     { 0, { (1<<MACH_BASE) } }  },
 391 /* R13: General Register 13 */
 392   { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
 393     { 0, { (1<<MACH_BASE) } }  },
 394 /* R14: General Register 14 */
 395   { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
 396     { 0, { (1<<MACH_BASE) } }  },
 397 /* R15: General Register 15 */
 398   { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
 399     { 0, { (1<<MACH_BASE) } }  },
 400 /* ps: Program Status register */
 401   { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
 402     { 0, { (1<<MACH_BASE) } }  },
 403 /* u4: 4  bit unsigned immediate */
 404   { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
 405     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 406 /* u4c: 4  bit unsigned immediate */
 407   { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
 408     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 409 /* u8: 8  bit unsigned immediate */
 410   { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
 411     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 412 /* i8: 8  bit unsigned immediate */
 413   { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
 414     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 415 /* udisp6: 6  bit unsigned immediate */
 416   { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
 417     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 418 /* disp8: 8  bit signed   immediate */
 419   { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
 420     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 421 /* disp9: 9  bit signed   immediate */
 422   { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
 423     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 424 /* disp10: 10 bit signed   immediate */
 425   { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
 426     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 427 /* s10: 10 bit signed   immediate */
 428   { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
 429     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 430 /* u10: 10 bit unsigned immediate */
 431   { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
 432     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 433 /* i32: 32 bit immediate */
 434   { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
 435     { 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 436 /* m4: 4  bit negative immediate */
 437   { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
 438     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 439 /* i20: 20 bit immediate */
 440   { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
 441     { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
 442 /* dir8: 8  bit direct address */
 443   { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
 444     { 0, { (1<<MACH_BASE) } }  },
 445 /* dir9: 9  bit direct address */
 446   { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
 447     { 0, { (1<<MACH_BASE) } }  },
 448 /* dir10: 10 bit direct address */
 449   { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
 450     { 0, { (1<<MACH_BASE) } }  },
 451 /* label9: 9  bit pc relative address */
 452   { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
 453     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 454 /* label12: 12 bit pc relative address */
 455   { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
 456     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 457 /* reglist_low_ld: 8 bit low register mask for ldm */
 458   { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
 459     { 0, { (1<<MACH_BASE) } }  },
 460 /* reglist_hi_ld: 8 bit high register mask for ldm */
 461   { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
 462     { 0, { (1<<MACH_BASE) } }  },
 463 /* reglist_low_st: 8 bit low register mask for stm */
 464   { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
 465     { 0, { (1<<MACH_BASE) } }  },
 466 /* reglist_hi_st: 8 bit high register mask for stm */
 467   { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
 468     { 0, { (1<<MACH_BASE) } }  },
 469 /* cc: condition codes */
 470   { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
 471     { 0, { (1<<MACH_BASE) } }  },
 472 /* ccc: coprocessor calc */
 473   { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
 474     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 475 /* nbit: negative   bit */
 476   { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
 477     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 478 /* vbit: overflow   bit */
 479   { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
 480     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 481 /* zbit: zero       bit */
 482   { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
 483     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 484 /* cbit: carry      bit */
 485   { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
 486     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 487 /* ibit: interrupt  bit */
 488   { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
 489     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 490 /* sbit: stack      bit */
 491   { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
 492     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 493 /* tbit: trace trap bit */
 494   { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
 495     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 496 /* d0bit: division 0 bit */
 497   { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
 498     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 499 /* d1bit: division 1 bit */
 500   { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
 501     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 502 /* ccr: condition code bits */
 503   { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
 504     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 505 /* scr: system condition bits */
 506   { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
 507     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 508 /* ilm: interrupt level mask */
 509   { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
 510     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 511   { 0, 0, 0, 0, 0, {0, {0}} }
 512 };
 513
 514 #undef A
 515
 516
 517 /* The instruction table.  */
 518
 519 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 520 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 521 #define A(a) (1 << CGEN_INSN_##a)
 522 #else
 523 #define A(a) (1 << CGEN_INSN_/**/a)
 524 #endif
 525
 526 static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
 527 {
 528   /* Special null first entry.
 529      A `num' value of zero is thus invalid.
 530      Also, the special `invalid' insn resides here.  */
 531   { 0, 0, 0, 0, {0, {0}} },
 532 /* add $Rj,$Ri */
 533   {
 534     FR30_INSN_ADD, "add", "add", 16,
 535     { 0, { (1<<MACH_BASE) } }
 536   },
 537 /* add $u4,$Ri */
 538   {
 539     FR30_INSN_ADDI, "addi", "add", 16,
 540     { 0, { (1<<MACH_BASE) } }
 541   },
 542 /* add2 $m4,$Ri */
 543   {
 544     FR30_INSN_ADD2, "add2", "add2", 16,
 545     { 0, { (1<<MACH_BASE) } }
 546   },
 547 /* addc $Rj,$Ri */
 548   {
 549     FR30_INSN_ADDC, "addc", "addc", 16,
 550     { 0, { (1<<MACH_BASE) } }
 551   },
 552 /* addn $Rj,$Ri */
 553   {
 554     FR30_INSN_ADDN, "addn", "addn", 16,
 555     { 0, { (1<<MACH_BASE) } }
 556   },
 557 /* addn $u4,$Ri */
 558   {
 559     FR30_INSN_ADDNI, "addni", "addn", 16,
 560     { 0, { (1<<MACH_BASE) } }
 561   },
 562 /* addn2 $m4,$Ri */
 563   {
 564     FR30_INSN_ADDN2, "addn2", "addn2", 16,
 565     { 0, { (1<<MACH_BASE) } }
 566   },
 567 /* sub $Rj,$Ri */
 568   {
 569     FR30_INSN_SUB, "sub", "sub", 16,
 570     { 0, { (1<<MACH_BASE) } }
 571   },
 572 /* subc $Rj,$Ri */
 573   {
 574     FR30_INSN_SUBC, "subc", "subc", 16,
 575     { 0, { (1<<MACH_BASE) } }
 576   },
 577 /* subn $Rj,$Ri */
 578   {
 579     FR30_INSN_SUBN, "subn", "subn", 16,
 580     { 0, { (1<<MACH_BASE) } }
 581   },
 582 /* cmp $Rj,$Ri */
 583   {
 584     FR30_INSN_CMP, "cmp", "cmp", 16,
 585     { 0, { (1<<MACH_BASE) } }
 586   },
 587 /* cmp $u4,$Ri */
 588   {
 589     FR30_INSN_CMPI, "cmpi", "cmp", 16,
 590     { 0, { (1<<MACH_BASE) } }
 591   },
 592 /* cmp2 $m4,$Ri */
 593   {
 594     FR30_INSN_CMP2, "cmp2", "cmp2", 16,
 595     { 0, { (1<<MACH_BASE) } }
 596   },
 597 /* and $Rj,$Ri */
 598   {
 599     FR30_INSN_AND, "and", "and", 16,
 600     { 0, { (1<<MACH_BASE) } }
 601   },
 602 /* or $Rj,$Ri */
 603   {
 604     FR30_INSN_OR, "or", "or", 16,
 605     { 0, { (1<<MACH_BASE) } }
 606   },
 607 /* eor $Rj,$Ri */
 608   {
 609     FR30_INSN_EOR, "eor", "eor", 16,
 610     { 0, { (1<<MACH_BASE) } }
 611   },
 612 /* and $Rj,@$Ri */
 613   {
 614     FR30_INSN_ANDM, "andm", "and", 16,
 615     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 616   },
 617 /* andh $Rj,@$Ri */
 618   {
 619     FR30_INSN_ANDH, "andh", "andh", 16,
 620     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 621   },
 622 /* andb $Rj,@$Ri */
 623   {
 624     FR30_INSN_ANDB, "andb", "andb", 16,
 625     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 626   },
 627 /* or $Rj,@$Ri */
 628   {
 629     FR30_INSN_ORM, "orm", "or", 16,
 630     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 631   },
 632 /* orh $Rj,@$Ri */
 633   {
 634     FR30_INSN_ORH, "orh", "orh", 16,
 635     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 636   },
 637 /* orb $Rj,@$Ri */
 638   {
 639     FR30_INSN_ORB, "orb", "orb", 16,
 640     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 641   },
 642 /* eor $Rj,@$Ri */
 643   {
 644     FR30_INSN_EORM, "eorm", "eor", 16,
 645     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 646   },
 647 /* eorh $Rj,@$Ri */
 648   {
 649     FR30_INSN_EORH, "eorh", "eorh", 16,
 650     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 651   },
 652 /* eorb $Rj,@$Ri */
 653   {
 654     FR30_INSN_EORB, "eorb", "eorb", 16,
 655     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 656   },
 657 /* bandl $u4,@$Ri */
 658   {
 659     FR30_INSN_BANDL, "bandl", "bandl", 16,
 660     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 661   },
 662 /* borl $u4,@$Ri */
 663   {
 664     FR30_INSN_BORL, "borl", "borl", 16,
 665     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 666   },
 667 /* beorl $u4,@$Ri */
 668   {
 669     FR30_INSN_BEORL, "beorl", "beorl", 16,
 670     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 671   },
 672 /* bandh $u4,@$Ri */
 673   {
 674     FR30_INSN_BANDH, "bandh", "bandh", 16,
 675     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 676   },
 677 /* borh $u4,@$Ri */
 678   {
 679     FR30_INSN_BORH, "borh", "borh", 16,
 680     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 681   },
 682 /* beorh $u4,@$Ri */
 683   {
 684     FR30_INSN_BEORH, "beorh", "beorh", 16,
 685     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 686   },
 687 /* btstl $u4,@$Ri */
 688   {
 689     FR30_INSN_BTSTL, "btstl", "btstl", 16,
 690     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 691   },
 692 /* btsth $u4,@$Ri */
 693   {
 694     FR30_INSN_BTSTH, "btsth", "btsth", 16,
 695     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 696   },
 697 /* mul $Rj,$Ri */
 698   {
 699     FR30_INSN_MUL, "mul", "mul", 16,
 700     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 701   },
 702 /* mulu $Rj,$Ri */
 703   {
 704     FR30_INSN_MULU, "mulu", "mulu", 16,
 705     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 706   },
 707 /* mulh $Rj,$Ri */
 708   {
 709     FR30_INSN_MULH, "mulh", "mulh", 16,
 710     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 711   },
 712 /* muluh $Rj,$Ri */
 713   {
 714     FR30_INSN_MULUH, "muluh", "muluh", 16,
 715     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 716   },
 717 /* div0s $Ri */
 718   {
 719     FR30_INSN_DIV0S, "div0s", "div0s", 16,
 720     { 0, { (1<<MACH_BASE) } }
 721   },
 722 /* div0u $Ri */
 723   {
 724     FR30_INSN_DIV0U, "div0u", "div0u", 16,
 725     { 0, { (1<<MACH_BASE) } }
 726   },
 727 /* div1 $Ri */
 728   {
 729     FR30_INSN_DIV1, "div1", "div1", 16,
 730     { 0, { (1<<MACH_BASE) } }
 731   },
 732 /* div2 $Ri */
 733   {
 734     FR30_INSN_DIV2, "div2", "div2", 16,
 735     { 0, { (1<<MACH_BASE) } }
 736   },
 737 /* div3 */
 738   {
 739     FR30_INSN_DIV3, "div3", "div3", 16,
 740     { 0, { (1<<MACH_BASE) } }
 741   },
 742 /* div4s */
 743   {
 744     FR30_INSN_DIV4S, "div4s", "div4s", 16,
 745     { 0, { (1<<MACH_BASE) } }
 746   },
 747 /* lsl $Rj,$Ri */
 748   {
 749     FR30_INSN_LSL, "lsl", "lsl", 16,
 750     { 0, { (1<<MACH_BASE) } }
 751   },
 752 /* lsl $u4,$Ri */
 753   {
 754     FR30_INSN_LSLI, "lsli", "lsl", 16,
 755     { 0, { (1<<MACH_BASE) } }
 756   },
 757 /* lsl2 $u4,$Ri */
 758   {
 759     FR30_INSN_LSL2, "lsl2", "lsl2", 16,
 760     { 0, { (1<<MACH_BASE) } }
 761   },
 762 /* lsr $Rj,$Ri */
 763   {
 764     FR30_INSN_LSR, "lsr", "lsr", 16,
 765     { 0, { (1<<MACH_BASE) } }
 766   },
 767 /* lsr $u4,$Ri */
 768   {
 769     FR30_INSN_LSRI, "lsri", "lsr", 16,
 770     { 0, { (1<<MACH_BASE) } }
 771   },
 772 /* lsr2 $u4,$Ri */
 773   {
 774     FR30_INSN_LSR2, "lsr2", "lsr2", 16,
 775     { 0, { (1<<MACH_BASE) } }
 776   },
 777 /* asr $Rj,$Ri */
 778   {
 779     FR30_INSN_ASR, "asr", "asr", 16,
 780     { 0, { (1<<MACH_BASE) } }
 781   },
 782 /* asr $u4,$Ri */
 783   {
 784     FR30_INSN_ASRI, "asri", "asr", 16,
 785     { 0, { (1<<MACH_BASE) } }
 786   },
 787 /* asr2 $u4,$Ri */
 788   {
 789     FR30_INSN_ASR2, "asr2", "asr2", 16,
 790     { 0, { (1<<MACH_BASE) } }
 791   },
 792 /* ldi:8 $i8,$Ri */
 793   {
 794     FR30_INSN_LDI8, "ldi8", "ldi:8", 16,
 795     { 0, { (1<<MACH_BASE) } }
 796   },
 797 /* ldi:20 $i20,$Ri */
 798   {
 799     FR30_INSN_LDI20, "ldi20", "ldi:20", 32,
 800     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 801   },
 802 /* ldi:32 $i32,$Ri */
 803   {
 804     FR30_INSN_LDI32, "ldi32", "ldi:32", 48,
 805     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 806   },
 807 /* ld @$Rj,$Ri */
 808   {
 809     FR30_INSN_LD, "ld", "ld", 16,
 810     { 0, { (1<<MACH_BASE) } }
 811   },
 812 /* lduh @$Rj,$Ri */
 813   {
 814     FR30_INSN_LDUH, "lduh", "lduh", 16,
 815     { 0, { (1<<MACH_BASE) } }
 816   },
 817 /* ldub @$Rj,$Ri */
 818   {
 819     FR30_INSN_LDUB, "ldub", "ldub", 16,
 820     { 0, { (1<<MACH_BASE) } }
 821   },
 822 /* ld @($R13,$Rj),$Ri */
 823   {
 824     FR30_INSN_LDR13, "ldr13", "ld", 16,
 825     { 0, { (1<<MACH_BASE) } }
 826   },
 827 /* lduh @($R13,$Rj),$Ri */
 828   {
 829     FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16,
 830     { 0, { (1<<MACH_BASE) } }
 831   },
 832 /* ldub @($R13,$Rj),$Ri */
 833   {
 834     FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16,
 835     { 0, { (1<<MACH_BASE) } }
 836   },
 837 /* ld @($R14,$disp10),$Ri */
 838   {
 839     FR30_INSN_LDR14, "ldr14", "ld", 16,
 840     { 0, { (1<<MACH_BASE) } }
 841   },
 842 /* lduh @($R14,$disp9),$Ri */
 843   {
 844     FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16,
 845     { 0, { (1<<MACH_BASE) } }
 846   },
 847 /* ldub @($R14,$disp8),$Ri */
 848   {
 849     FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16,
 850     { 0, { (1<<MACH_BASE) } }
 851   },
 852 /* ld @($R15,$udisp6),$Ri */
 853   {
 854     FR30_INSN_LDR15, "ldr15", "ld", 16,
 855     { 0, { (1<<MACH_BASE) } }
 856   },
 857 /* ld @$R15+,$Ri */
 858   {
 859     FR30_INSN_LDR15GR, "ldr15gr", "ld", 16,
 860     { 0, { (1<<MACH_BASE) } }
 861   },
 862 /* ld @$R15+,$Rs2 */
 863   {
 864     FR30_INSN_LDR15DR, "ldr15dr", "ld", 16,
 865     { 0, { (1<<MACH_BASE) } }
 866   },
 867 /* ld @$R15+,$ps */
 868   {
 869     FR30_INSN_LDR15PS, "ldr15ps", "ld", 16,
 870     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 871   },
 872 /* st $Ri,@$Rj */
 873   {
 874     FR30_INSN_ST, "st", "st", 16,
 875     { 0, { (1<<MACH_BASE) } }
 876   },
 877 /* sth $Ri,@$Rj */
 878   {
 879     FR30_INSN_STH, "sth", "sth", 16,
 880     { 0, { (1<<MACH_BASE) } }
 881   },
 882 /* stb $Ri,@$Rj */
 883   {
 884     FR30_INSN_STB, "stb", "stb", 16,
 885     { 0, { (1<<MACH_BASE) } }
 886   },
 887 /* st $Ri,@($R13,$Rj) */
 888   {
 889     FR30_INSN_STR13, "str13", "st", 16,
 890     { 0, { (1<<MACH_BASE) } }
 891   },
 892 /* sth $Ri,@($R13,$Rj) */
 893   {
 894     FR30_INSN_STR13H, "str13h", "sth", 16,
 895     { 0, { (1<<MACH_BASE) } }
 896   },
 897 /* stb $Ri,@($R13,$Rj) */
 898   {
 899     FR30_INSN_STR13B, "str13b", "stb", 16,
 900     { 0, { (1<<MACH_BASE) } }
 901   },
 902 /* st $Ri,@($R14,$disp10) */
 903   {
 904     FR30_INSN_STR14, "str14", "st", 16,
 905     { 0, { (1<<MACH_BASE) } }
 906   },
 907 /* sth $Ri,@($R14,$disp9) */
 908   {
 909     FR30_INSN_STR14H, "str14h", "sth", 16,
 910     { 0, { (1<<MACH_BASE) } }
 911   },
 912 /* stb $Ri,@($R14,$disp8) */
 913   {
 914     FR30_INSN_STR14B, "str14b", "stb", 16,
 915     { 0, { (1<<MACH_BASE) } }
 916   },
 917 /* st $Ri,@($R15,$udisp6) */
 918   {
 919     FR30_INSN_STR15, "str15", "st", 16,
 920     { 0, { (1<<MACH_BASE) } }
 921   },
 922 /* st $Ri,@-$R15 */
 923   {
 924     FR30_INSN_STR15GR, "str15gr", "st", 16,
 925     { 0, { (1<<MACH_BASE) } }
 926   },
 927 /* st $Rs2,@-$R15 */
 928   {
 929     FR30_INSN_STR15DR, "str15dr", "st", 16,
 930     { 0, { (1<<MACH_BASE) } }
 931   },
 932 /* st $ps,@-$R15 */
 933   {
 934     FR30_INSN_STR15PS, "str15ps", "st", 16,
 935     { 0, { (1<<MACH_BASE) } }
 936   },
 937 /* mov $Rj,$Ri */
 938   {
 939     FR30_INSN_MOV, "mov", "mov", 16,
 940     { 0, { (1<<MACH_BASE) } }
 941   },
 942 /* mov $Rs1,$Ri */
 943   {
 944     FR30_INSN_MOVDR, "movdr", "mov", 16,
 945     { 0, { (1<<MACH_BASE) } }
 946   },
 947 /* mov $ps,$Ri */
 948   {
 949     FR30_INSN_MOVPS, "movps", "mov", 16,
 950     { 0, { (1<<MACH_BASE) } }
 951   },
 952 /* mov $Ri,$Rs1 */
 953   {
 954     FR30_INSN_MOV2DR, "mov2dr", "mov", 16,
 955     { 0, { (1<<MACH_BASE) } }
 956   },
 957 /* mov $Ri,$ps */
 958   {
 959     FR30_INSN_MOV2PS, "mov2ps", "mov", 16,
 960     { 0, { (1<<MACH_BASE) } }
 961   },
 962 /* jmp @$Ri */
 963   {
 964     FR30_INSN_JMP, "jmp", "jmp", 16,
 965     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
 966   },
 967 /* jmp:d @$Ri */
 968   {
 969     FR30_INSN_JMPD, "jmpd", "jmp:d", 16,
 970     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 971   },
 972 /* call @$Ri */
 973   {
 974     FR30_INSN_CALLR, "callr", "call", 16,
 975     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
 976   },
 977 /* call:d @$Ri */
 978   {
 979     FR30_INSN_CALLRD, "callrd", "call:d", 16,
 980     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 981   },
 982 /* call $label12 */
 983   {
 984     FR30_INSN_CALL, "call", "call", 16,
 985     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
 986   },
 987 /* call:d $label12 */
 988   {
 989     FR30_INSN_CALLD, "calld", "call:d", 16,
 990     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 991   },
 992 /* ret */
 993   {
 994     FR30_INSN_RET, "ret", "ret", 16,
 995     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
 996   },
 997 /* ret:d */
 998   {
 999     FR30_INSN_RET_D, "ret:d", "ret:d", 16,
1000     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1001   },
1002 /* int $u8 */
1003   {
1004     FR30_INSN_INT, "int", "int", 16,
1005     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1006   },
1007 /* inte */
1008   {
1009     FR30_INSN_INTE, "inte", "inte", 16,
1010     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1011   },
1012 /* reti */
1013   {
1014     FR30_INSN_RETI, "reti", "reti", 16,
1015     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1016   },
1017 /* bra:d $label9 */
1018   {
1019     FR30_INSN_BRAD, "brad", "bra:d", 16,
1020     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1021   },
1022 /* bra $label9 */
1023   {
1024     FR30_INSN_BRA, "bra", "bra", 16,
1025     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1026   },
1027 /* bno:d $label9 */
1028   {
1029     FR30_INSN_BNOD, "bnod", "bno:d", 16,
1030     { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1031   },
1032 /* bno $label9 */
1033   {
1034     FR30_INSN_BNO, "bno", "bno", 16,
1035     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1036   },
1037 /* beq:d $label9 */
1038   {
1039     FR30_INSN_BEQD, "beqd", "beq:d", 16,
1040     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1041   },
1042 /* beq $label9 */
1043   {
1044     FR30_INSN_BEQ, "beq", "beq", 16,
1045     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1046   },
1047 /* bne:d $label9 */
1048   {
1049     FR30_INSN_BNED, "bned", "bne:d", 16,
1050     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1051   },
1052 /* bne $label9 */
1053   {
1054     FR30_INSN_BNE, "bne", "bne", 16,
1055     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1056   },
1057 /* bc:d $label9 */
1058   {
1059     FR30_INSN_BCD, "bcd", "bc:d", 16,
1060     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1061   },
1062 /* bc $label9 */
1063   {
1064     FR30_INSN_BC, "bc", "bc", 16,
1065     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1066   },
1067 /* bnc:d $label9 */
1068   {
1069     FR30_INSN_BNCD, "bncd", "bnc:d", 16,
1070     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1071   },
1072 /* bnc $label9 */
1073   {
1074     FR30_INSN_BNC, "bnc", "bnc", 16,
1075     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1076   },
1077 /* bn:d $label9 */
1078   {
1079     FR30_INSN_BND, "bnd", "bn:d", 16,
1080     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1081   },
1082 /* bn $label9 */
1083   {
1084     FR30_INSN_BN, "bn", "bn", 16,
1085     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1086   },
1087 /* bp:d $label9 */
1088   {
1089     FR30_INSN_BPD, "bpd", "bp:d", 16,
1090     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1091   },
1092 /* bp $label9 */
1093   {
1094     FR30_INSN_BP, "bp", "bp", 16,
1095     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1096   },
1097 /* bv:d $label9 */
1098   {
1099     FR30_INSN_BVD, "bvd", "bv:d", 16,
1100     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1101   },
1102 /* bv $label9 */
1103   {
1104     FR30_INSN_BV, "bv", "bv", 16,
1105     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1106   },
1107 /* bnv:d $label9 */
1108   {
1109     FR30_INSN_BNVD, "bnvd", "bnv:d", 16,
1110     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1111   },
1112 /* bnv $label9 */
1113   {
1114     FR30_INSN_BNV, "bnv", "bnv", 16,
1115     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1116   },
1117 /* blt:d $label9 */
1118   {
1119     FR30_INSN_BLTD, "bltd", "blt:d", 16,
1120     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1121   },
1122 /* blt $label9 */
1123   {
1124     FR30_INSN_BLT, "blt", "blt", 16,
1125     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1126   },
1127 /* bge:d $label9 */
1128   {
1129     FR30_INSN_BGED, "bged", "bge:d", 16,
1130     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1131   },
1132 /* bge $label9 */
1133   {
1134     FR30_INSN_BGE, "bge", "bge", 16,
1135     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1136   },
1137 /* ble:d $label9 */
1138   {
1139     FR30_INSN_BLED, "bled", "ble:d", 16,
1140     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1141   },
1142 /* ble $label9 */
1143   {
1144     FR30_INSN_BLE, "ble", "ble", 16,
1145     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1146   },
1147 /* bgt:d $label9 */
1148   {
1149     FR30_INSN_BGTD, "bgtd", "bgt:d", 16,
1150     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1151   },
1152 /* bgt $label9 */
1153   {
1154     FR30_INSN_BGT, "bgt", "bgt", 16,
1155     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1156   },
1157 /* bls:d $label9 */
1158   {
1159     FR30_INSN_BLSD, "blsd", "bls:d", 16,
1160     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1161   },
1162 /* bls $label9 */
1163   {
1164     FR30_INSN_BLS, "bls", "bls", 16,
1165     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1166   },
1167 /* bhi:d $label9 */
1168   {
1169     FR30_INSN_BHID, "bhid", "bhi:d", 16,
1170     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1171   },
1172 /* bhi $label9 */
1173   {
1174     FR30_INSN_BHI, "bhi", "bhi", 16,
1175     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1176   },
1177 /* dmov $R13,@$dir10 */
1178   {
1179     FR30_INSN_DMOVR13, "dmovr13", "dmov", 16,
1180     { 0, { (1<<MACH_BASE) } }
1181   },
1182 /* dmovh $R13,@$dir9 */
1183   {
1184     FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", 16,
1185     { 0, { (1<<MACH_BASE) } }
1186   },
1187 /* dmovb $R13,@$dir8 */
1188   {
1189     FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", 16,
1190     { 0, { (1<<MACH_BASE) } }
1191   },
1192 /* dmov @$R13+,@$dir10 */
1193   {
1194     FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", 16,
1195     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1196   },
1197 /* dmovh @$R13+,@$dir9 */
1198   {
1199     FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", 16,
1200     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1201   },
1202 /* dmovb @$R13+,@$dir8 */
1203   {
1204     FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", 16,
1205     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1206   },
1207 /* dmov @$R15+,@$dir10 */
1208   {
1209     FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", 16,
1210     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1211   },
1212 /* dmov @$dir10,$R13 */
1213   {
1214     FR30_INSN_DMOV2R13, "dmov2r13", "dmov", 16,
1215     { 0, { (1<<MACH_BASE) } }
1216   },
1217 /* dmovh @$dir9,$R13 */
1218   {
1219     FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", 16,
1220     { 0, { (1<<MACH_BASE) } }
1221   },
1222 /* dmovb @$dir8,$R13 */
1223   {
1224     FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", 16,
1225     { 0, { (1<<MACH_BASE) } }
1226   },
1227 /* dmov @$dir10,@$R13+ */
1228   {
1229     FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", 16,
1230     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1231   },
1232 /* dmovh @$dir9,@$R13+ */
1233   {
1234     FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", 16,
1235     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1236   },
1237 /* dmovb @$dir8,@$R13+ */
1238   {
1239     FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", 16,
1240     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1241   },
1242 /* dmov @$dir10,@-$R15 */
1243   {
1244     FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", 16,
1245     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1246   },
1247 /* ldres @$Ri+,$u4 */
1248   {
1249     FR30_INSN_LDRES, "ldres", "ldres", 16,
1250     { 0, { (1<<MACH_BASE) } }
1251   },
1252 /* stres $u4,@$Ri+ */
1253   {
1254     FR30_INSN_STRES, "stres", "stres", 16,
1255     { 0, { (1<<MACH_BASE) } }
1256   },
1257 /* copop $u4c,$ccc,$CRj,$CRi */
1258   {
1259     FR30_INSN_COPOP, "copop", "copop", 32,
1260     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1261   },
1262 /* copld $u4c,$ccc,$Rjc,$CRi */
1263   {
1264     FR30_INSN_COPLD, "copld", "copld", 32,
1265     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1266   },
1267 /* copst $u4c,$ccc,$CRj,$Ric */
1268   {
1269     FR30_INSN_COPST, "copst", "copst", 32,
1270     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1271   },
1272 /* copsv $u4c,$ccc,$CRj,$Ric */
1273   {
1274     FR30_INSN_COPSV, "copsv", "copsv", 32,
1275     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1276   },
1277 /* nop */
1278   {
1279     FR30_INSN_NOP, "nop", "nop", 16,
1280     { 0, { (1<<MACH_BASE) } }
1281   },
1282 /* andccr $u8 */
1283   {
1284     FR30_INSN_ANDCCR, "andccr", "andccr", 16,
1285     { 0, { (1<<MACH_BASE) } }
1286   },
1287 /* orccr $u8 */
1288   {
1289     FR30_INSN_ORCCR, "orccr", "orccr", 16,
1290     { 0, { (1<<MACH_BASE) } }
1291   },
1292 /* stilm $u8 */
1293   {
1294     FR30_INSN_STILM, "stilm", "stilm", 16,
1295     { 0, { (1<<MACH_BASE) } }
1296   },
1297 /* addsp $s10 */
1298   {
1299     FR30_INSN_ADDSP, "addsp", "addsp", 16,
1300     { 0, { (1<<MACH_BASE) } }
1301   },
1302 /* extsb $Ri */
1303   {
1304     FR30_INSN_EXTSB, "extsb", "extsb", 16,
1305     { 0, { (1<<MACH_BASE) } }
1306   },
1307 /* extub $Ri */
1308   {
1309     FR30_INSN_EXTUB, "extub", "extub", 16,
1310     { 0, { (1<<MACH_BASE) } }
1311   },
1312 /* extsh $Ri */
1313   {
1314     FR30_INSN_EXTSH, "extsh", "extsh", 16,
1315     { 0, { (1<<MACH_BASE) } }
1316   },
1317 /* extuh $Ri */
1318   {
1319     FR30_INSN_EXTUH, "extuh", "extuh", 16,
1320     { 0, { (1<<MACH_BASE) } }
1321   },
1322 /* ldm0 ($reglist_low_ld) */
1323   {
1324     FR30_INSN_LDM0, "ldm0", "ldm0", 16,
1325     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1326   },
1327 /* ldm1 ($reglist_hi_ld) */
1328   {
1329     FR30_INSN_LDM1, "ldm1", "ldm1", 16,
1330     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1331   },
1332 /* stm0 ($reglist_low_st) */
1333   {
1334     FR30_INSN_STM0, "stm0", "stm0", 16,
1335     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1336   },
1337 /* stm1 ($reglist_hi_st) */
1338   {
1339     FR30_INSN_STM1, "stm1", "stm1", 16,
1340     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1341   },
1342 /* enter $u10 */
1343   {
1344     FR30_INSN_ENTER, "enter", "enter", 16,
1345     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1346   },
1347 /* leave */
1348   {
1349     FR30_INSN_LEAVE, "leave", "leave", 16,
1350     { 0, { (1<<MACH_BASE) } }
1351   },
1352 /* xchb @$Rj,$Ri */
1353   {
1354     FR30_INSN_XCHB, "xchb", "xchb", 16,
1355     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1356   },
1357 };
1358
1359 #undef OP
1360 #undef A
1361
1362 /* Initialize anything needed to be done once, before any cpu_open call.  */
1363 static void init_tables PARAMS ((void));
1364
1365 static void
1366 init_tables ()
1367 {
1368 }
1369
1370 static const CGEN_MACH * lookup_mach_via_bfd_name
1371   PARAMS ((const CGEN_MACH *, const char *));
1372 static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
1373 static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
1374 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
1375 static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
1376 static void fr30_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
1377
1378 /* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name.  */
1379
1380 static const CGEN_MACH *
1381 lookup_mach_via_bfd_name (table, name)
1382      const CGEN_MACH *table;
1383      const char *name;
1384 {
1385   while (table->name)
1386     {
1387       if (strcmp (name, table->bfd_name) == 0)
1388         return table;
1389       ++table;
1390     }
1391   abort ();
1392 }
1393
1394 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1395
1396 static void
1397 build_hw_table (cd)
1398      CGEN_CPU_TABLE *cd;
1399 {
1400   int i;
1401   int machs = cd->machs;
1402   const CGEN_HW_ENTRY *init = & fr30_cgen_hw_table[0];
1403   /* MAX_HW is only an upper bound on the number of selected entries.
1404      However each entry is indexed by it's enum so there can be holes in
1405      the table.  */
1406   const CGEN_HW_ENTRY **selected =
1407     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1408
1409   cd->hw_table.init_entries = init;
1410   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1411   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1412   /* ??? For now we just use machs to determine which ones we want.  */
1413   for (i = 0; init[i].name != NULL; ++i)
1414     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1415         & machs)
1416       selected[init[i].type] = &init[i];
1417   cd->hw_table.entries = selected;
1418   cd->hw_table.num_entries = MAX_HW;
1419 }
1420
1421 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1422
1423 static void
1424 build_ifield_table (cd)
1425      CGEN_CPU_TABLE *cd;
1426 {
1427   cd->ifld_table = & fr30_cgen_ifld_table[0];
1428 }
1429
1430 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1431
1432 static void
1433 build_operand_table (cd)
1434      CGEN_CPU_TABLE *cd;
1435 {
1436   int i;
1437   int machs = cd->machs;
1438   const CGEN_OPERAND *init = & fr30_cgen_operand_table[0];
1439   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1440      However each entry is indexed by it's enum so there can be holes in
1441      the table.  */
1442   const CGEN_OPERAND **selected =
1443     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1444
1445   cd->operand_table.init_entries = init;
1446   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1447   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1448   /* ??? For now we just use mach to determine which ones we want.  */
1449   for (i = 0; init[i].name != NULL; ++i)
1450     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1451         & machs)
1452       selected[init[i].type] = &init[i];
1453   cd->operand_table.entries = selected;
1454   cd->operand_table.num_entries = MAX_OPERANDS;
1455 }
1456
1457 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.
1458    ??? This could leave out insns not supported by the specified mach/isa,
1459    but that would cause errors like "foo only supported by bar" to become
1460    "unknown insn", so for now we include all insns and require the app to
1461    do the checking later.
1462    ??? On the other hand, parsing of such insns may require their hardware or
1463    operand elements to be in the table [which they mightn't be].  */
1464
1465 static void
1466 build_insn_table (cd)
1467      CGEN_CPU_TABLE *cd;
1468 {
1469   int i;
1470   const CGEN_IBASE *ib = & fr30_cgen_insn_table[0];
1471   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1472
1473   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1474   for (i = 0; i < MAX_INSNS; ++i)
1475     insns[i].base = &ib[i];
1476   cd->insn_table.init_entries = insns;
1477   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1478   cd->insn_table.num_init_entries = MAX_INSNS;
1479 }
1480
1481 /* Subroutine of fr30_cgen_cpu_open to rebuild the tables.  */
1482
1483 static void
1484 fr30_cgen_rebuild_tables (cd)
1485      CGEN_CPU_TABLE *cd;
1486 {
1487   int i;
1488   unsigned int isas = cd->isas;
1489   unsigned int machs = cd->machs;
1490
1491   cd->int_insn_p = CGEN_INT_INSN_P;
1492
1493   /* Data derived from the isa spec.  */
1494 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1495   cd->default_insn_bitsize = UNSET;
1496   cd->base_insn_bitsize = UNSET;
1497   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1498   cd->max_insn_bitsize = 0;
1499   for (i = 0; i < MAX_ISAS; ++i)
1500     if (((1 << i) & isas) != 0)
1501       {
1502         const CGEN_ISA *isa = & fr30_cgen_isa_table[i];
1503
1504         /* Default insn sizes of all selected isas must be equal or we set
1505            the result to 0, meaning "unknown".  */
1506         if (cd->default_insn_bitsize == UNSET)
1507           cd->default_insn_bitsize = isa->default_insn_bitsize;
1508         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1509           ; /* this is ok */
1510         else
1511           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1512
1513         /* Base insn sizes of all selected isas must be equal or we set
1514            the result to 0, meaning "unknown".  */
1515         if (cd->base_insn_bitsize == UNSET)
1516           cd->base_insn_bitsize = isa->base_insn_bitsize;
1517         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1518           ; /* this is ok */
1519         else
1520           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1521
1522         /* Set min,max insn sizes.  */
1523         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1524           cd->min_insn_bitsize = isa->min_insn_bitsize;
1525         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1526           cd->max_insn_bitsize = isa->max_insn_bitsize;
1527       }
1528
1529   /* Data derived from the mach spec.  */
1530   for (i = 0; i < MAX_MACHS; ++i)
1531     if (((1 << i) & machs) != 0)
1532       {
1533         const CGEN_MACH *mach = & fr30_cgen_mach_table[i];
1534
1535         if (mach->insn_chunk_bitsize != 0)
1536         {
1537           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1538             {
1539               fprintf (stderr, "fr30_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1540                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1541               abort ();
1542             }
1543
1544           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1545         }
1546       }
1547
1548   /* Determine which hw elements are used by MACH.  */
1549   build_hw_table (cd);
1550
1551   /* Build the ifield table.  */
1552   build_ifield_table (cd);
1553
1554   /* Determine which operands are used by MACH/ISA.  */
1555   build_operand_table (cd);
1556
1557   /* Build the instruction table.  */
1558   build_insn_table (cd);
1559 }
1560
1561 /* Initialize a cpu table and return a descriptor.
1562    It's much like opening a file, and must be the first function called.
1563    The arguments are a set of (type/value) pairs, terminated with
1564    CGEN_CPU_OPEN_END.
1565
1566    Currently supported values:
1567    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1568    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1569    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1570    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1571    CGEN_CPU_OPEN_END:     terminates arguments
1572
1573    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1574    precluded.
1575
1576    ??? We only support ISO C stdargs here, not K&R.
1577    Laziness, plus experiment to see if anything requires K&R - eventually
1578    K&R will no longer be supported - e.g. GDB is currently trying this.  */
1579
1580 CGEN_CPU_DESC
1581 fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1582 {
1583   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1584   static int init_p;
1585   unsigned int isas = 0;  /* 0 = "unspecified" */
1586   unsigned int machs = 0; /* 0 = "unspecified" */
1587   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1588   va_list ap;
1589
1590   if (! init_p)
1591     {
1592       init_tables ();
1593       init_p = 1;
1594     }
1595
1596   memset (cd, 0, sizeof (*cd));
1597
1598   va_start (ap, arg_type);
1599   while (arg_type != CGEN_CPU_OPEN_END)
1600     {
1601       switch (arg_type)
1602         {
1603         case CGEN_CPU_OPEN_ISAS :
1604           isas = va_arg (ap, unsigned int);
1605           break;
1606         case CGEN_CPU_OPEN_MACHS :
1607           machs = va_arg (ap, unsigned int);
1608           break;
1609         case CGEN_CPU_OPEN_BFDMACH :
1610           {
1611             const char *name = va_arg (ap, const char *);
1612             const CGEN_MACH *mach =
1613               lookup_mach_via_bfd_name (fr30_cgen_mach_table, name);
1614
1615             machs |= 1 << mach->num;
1616             break;
1617           }
1618         case CGEN_CPU_OPEN_ENDIAN :
1619           endian = va_arg (ap, enum cgen_endian);
1620           break;
1621         default :
1622           fprintf (stderr, "fr30_cgen_cpu_open: unsupported argument `%d'\n",
1623                    arg_type);
1624           abort (); /* ??? return NULL? */
1625         }
1626       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1627     }
1628   va_end (ap);
1629
1630   /* mach unspecified means "all" */
1631   if (machs == 0)
1632     machs = (1 << MAX_MACHS) - 1;
1633   /* base mach is always selected */
1634   machs |= 1;
1635   /* isa unspecified means "all" */
1636   if (isas == 0)
1637     isas = (1 << MAX_ISAS) - 1;
1638   if (endian == CGEN_ENDIAN_UNKNOWN)
1639     {
1640       /* ??? If target has only one, could have a default.  */
1641       fprintf (stderr, "fr30_cgen_cpu_open: no endianness specified\n");
1642       abort ();
1643     }
1644
1645   cd->isas = isas;
1646   cd->machs = machs;
1647   cd->endian = endian;
1648   /* FIXME: for the sparc case we can determine insn-endianness statically.
1649      The worry here is where both data and insn endian can be independently
1650      chosen, in which case this function will need another argument.
1651      Actually, will want to allow for more arguments in the future anyway.  */
1652   cd->insn_endian = endian;
1653
1654   /* Table (re)builder.  */
1655   cd->rebuild_tables = fr30_cgen_rebuild_tables;
1656   fr30_cgen_rebuild_tables (cd);
1657
1658   /* Default to not allowing signed overflow.  */
1659   cd->signed_overflow_ok_p = 0;
1660
1661   return (CGEN_CPU_DESC) cd;
1662 }
1663
1664 /* Cover fn to fr30_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1665    MACH_NAME is the bfd name of the mach.  */
1666
1667 CGEN_CPU_DESC
1668 fr30_cgen_cpu_open_1 (mach_name, endian)
1669      const char *mach_name;
1670      enum cgen_endian endian;
1671 {
1672   return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1673                                CGEN_CPU_OPEN_ENDIAN, endian,
1674                                CGEN_CPU_OPEN_END);
1675 }
1676
1677 /* Close a cpu table.
1678    ??? This can live in a machine independent file, but there's currently
1679    no place to put this file (there's no libcgen).  libopcodes is the wrong
1680    place as some simulator ports use this but they don't use libopcodes.  */
1681
1682 void
1683 fr30_cgen_cpu_close (cd)
1684      CGEN_CPU_DESC cd;
1685 {
1686   if (cd->insn_table.init_entries)
1687     free ((CGEN_INSN *) cd->insn_table.init_entries);
1688   if (cd->hw_table.entries)
1689     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1690   free (cd);
1691 }
1692