1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS USED TO GENERATE fr30-opc.c.
6 Copyright (C) 1998 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "libiberty.h"
33 /* The hash functions are recorded here to help keep assembler code out of
34 the disassembler and vice versa. */
36 static int asm_hash_insn_p
PARAMS ((const CGEN_INSN
*));
37 static unsigned int asm_hash_insn
PARAMS ((const char *));
38 static int dis_hash_insn_p
PARAMS ((const CGEN_INSN
*));
39 static unsigned int dis_hash_insn
PARAMS ((const char *, unsigned long));
41 /* Cover function to read and properly byteswap an insn value. */
44 cgen_get_insn_value (od
, buf
, length
)
57 if (CGEN_OPCODE_INSN_ENDIAN (od
) == CGEN_ENDIAN_BIG
)
58 value
= bfd_getb16 (buf
);
60 value
= bfd_getl16 (buf
);
63 if (CGEN_OPCODE_INSN_ENDIAN (od
) == CGEN_ENDIAN_BIG
)
64 value
= bfd_getb32 (buf
);
66 value
= bfd_getl32 (buf
);
75 /* Cover function to store an insn value properly byteswapped. */
78 cgen_put_insn_value (od
, buf
, length
, value
)
90 if (CGEN_OPCODE_INSN_ENDIAN (od
) == CGEN_ENDIAN_BIG
)
91 bfd_putb16 (value
, buf
);
93 bfd_putl16 (value
, buf
);
96 if (CGEN_OPCODE_INSN_ENDIAN (od
) == CGEN_ENDIAN_BIG
)
97 bfd_putb32 (value
, buf
);
99 bfd_putl32 (value
, buf
);
106 /* Look up instruction INSN_VALUE and extract its fields.
107 INSN, if non-null, is the insn table entry.
108 Otherwise INSN_VALUE is examined to compute it.
109 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
110 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
111 If INSN != NULL, LENGTH must be valid.
112 ALIAS_P is non-zero if alias insns are to be included in the search.
114 The result a pointer to the insn table entry, or NULL if the instruction
115 wasn't recognized. */
118 fr30_cgen_lookup_insn (od
, insn
, insn_value
, length
, fields
, alias_p
)
120 const CGEN_INSN
*insn
;
121 CGEN_INSN_BYTES insn_value
;
126 unsigned char buf
[16];
128 unsigned int base_insn
;
130 CGEN_EXTRACT_INFO
*info
= NULL
;
132 CGEN_EXTRACT_INFO ex_info
;
133 CGEN_EXTRACT_INFO
*info
= &ex_info
;
136 #if ! CGEN_INT_INSN_P
137 ex_info
.dis_info
= NULL
;
138 ex_info
.bytes
= insn_value
;
144 const CGEN_INSN_LIST
*insn_list
;
147 cgen_put_insn_value (od
, buf
, length
, insn_value
);
149 base_insn
= insn_value
; /*???*/
151 base_insn
= cgen_get_insn_value (od
, buf
, length
);
155 /* The instructions are stored in hash lists.
156 Pick the first one and keep trying until we find the right one. */
158 insn_list
= CGEN_DIS_LOOKUP_INSN (od
, bufp
, base_insn
);
159 while (insn_list
!= NULL
)
161 insn
= insn_list
->insn
;
164 || ! CGEN_INSN_ATTR (insn
, CGEN_INSN_ALIAS
))
166 /* Basic bit mask must be correct. */
167 /* ??? May wish to allow target to defer this check until the
169 if ((insn_value
& CGEN_INSN_MASK (insn
)) == CGEN_INSN_VALUE (insn
))
171 /* ??? 0 is passed for `pc' */
172 int elength
= (*CGEN_EXTRACT_FN (insn
)) (od
, insn
, info
,
178 if (length
!= 0 && length
!= elength
)
185 insn_list
= CGEN_DIS_NEXT_INSN (insn_list
);
190 /* Sanity check: can't pass an alias insn if ! alias_p. */
192 && CGEN_INSN_ATTR (insn
, CGEN_INSN_ALIAS
))
194 /* Sanity check: length must be correct. */
195 if (length
!= CGEN_INSN_BITSIZE (insn
))
198 /* ??? 0 is passed for `pc' */
199 length
= (*CGEN_EXTRACT_FN (insn
)) (od
, insn
, info
, insn_value
, fields
,
201 /* Sanity check: must succeed.
202 Could relax this later if it ever proves useful. */
211 /* Fill in the operand instances used by INSN whose operands are FIELDS.
212 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
216 fr30_cgen_get_insn_operands (od
, insn
, fields
, indices
)
218 const CGEN_INSN
* insn
;
219 const CGEN_FIELDS
* fields
;
222 const CGEN_OPERAND_INSTANCE
*opinst
;
225 for (i
= 0, opinst
= CGEN_INSN_OPERANDS (insn
);
227 && CGEN_OPERAND_INSTANCE_TYPE (opinst
) != CGEN_OPERAND_INSTANCE_END
;
230 const CGEN_OPERAND
*op
= CGEN_OPERAND_INSTANCE_OPERAND (opinst
);
232 indices
[i
] = CGEN_OPERAND_INSTANCE_INDEX (opinst
);
234 indices
[i
] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op
),
239 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
241 The INSN, INSN_VALUE, and LENGTH arguments are passed to
242 fr30_cgen_lookup_insn unchanged.
244 The result is the insn table entry or NULL if the instruction wasn't
248 fr30_cgen_lookup_get_insn_operands (od
, insn
, insn_value
, length
, indices
)
250 const CGEN_INSN
*insn
;
251 CGEN_INSN_BYTES insn_value
;
257 /* Pass non-zero for ALIAS_P only if INSN != NULL.
258 If INSN == NULL, we want a real insn. */
259 insn
= fr30_cgen_lookup_insn (od
, insn
, insn_value
, length
, &fields
,
264 fr30_cgen_get_insn_operands (od
, insn
, &fields
, indices
);
269 static const CGEN_ATTR_ENTRY MACH_attr
[] =
271 { "base", MACH_BASE
},
272 { "fr30", MACH_FR30
},
277 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table
[] =
279 { "CACHE-ADDR", NULL
},
285 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table
[] =
287 { "ABS-ADDR", NULL
},
288 { "HASH-PREFIX", NULL
},
289 { "NEGATIVE", NULL
},
290 { "PCREL-ADDR", NULL
},
292 { "SEM-ONLY", NULL
},
293 { "SIGN-OPT", NULL
},
295 { "UNSIGNED", NULL
},
299 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table
[] =
302 { "COND-CTI", NULL
},
305 { "RELAXABLE", NULL
},
306 { "SKIP-CTI", NULL
},
307 { "UNCOND-CTI", NULL
},
312 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries
[] =
335 CGEN_KEYWORD fr30_cgen_opval_h_gr
=
337 & fr30_cgen_opval_h_gr_entries
[0],
341 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries
[] =
351 CGEN_KEYWORD fr30_cgen_opval_h_dr
=
353 & fr30_cgen_opval_h_dr_entries
[0],
357 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries
[] =
363 CGEN_KEYWORD fr30_cgen_opval_h_cr
=
365 & fr30_cgen_opval_h_cr_entries
[0],
370 /* The hardware table. */
372 #define HW_ENT(n) fr30_cgen_hw_entries[n]
373 static const CGEN_HW_ENTRY fr30_cgen_hw_entries
[] =
375 { HW_H_PC
, & HW_ENT (HW_H_PC
+ 1), "h-pc", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0|(1<<CGEN_HW_PROFILE
)|(1<<CGEN_HW_PC
), { 0 } } },
376 { HW_H_MEMORY
, & HW_ENT (HW_H_MEMORY
+ 1), "h-memory", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
377 { HW_H_SINT
, & HW_ENT (HW_H_SINT
+ 1), "h-sint", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
378 { HW_H_UINT
, & HW_ENT (HW_H_UINT
+ 1), "h-uint", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
379 { HW_H_ADDR
, & HW_ENT (HW_H_ADDR
+ 1), "h-addr", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
380 { HW_H_IADDR
, & HW_ENT (HW_H_IADDR
+ 1), "h-iaddr", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
381 { HW_H_GR
, & HW_ENT (HW_H_GR
+ 1), "h-gr", CGEN_ASM_KEYWORD
, (PTR
) & fr30_cgen_opval_h_gr
, { 0, 0|(1<<CGEN_HW_CACHE_ADDR
)|(1<<CGEN_HW_PROFILE
), { 0 } } },
382 { HW_H_DR
, & HW_ENT (HW_H_DR
+ 1), "h-dr", CGEN_ASM_KEYWORD
, (PTR
) & fr30_cgen_opval_h_dr
, { 0, 0, { 0 } } },
383 { HW_H_CR
, & HW_ENT (HW_H_CR
+ 1), "h-cr", CGEN_ASM_KEYWORD
, (PTR
) & fr30_cgen_opval_h_cr
, { 0, 0, { 0 } } },
384 { HW_H_NBIT
, & HW_ENT (HW_H_NBIT
+ 1), "h-nbit", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
385 { HW_H_ZBIT
, & HW_ENT (HW_H_ZBIT
+ 1), "h-zbit", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
386 { HW_H_VBIT
, & HW_ENT (HW_H_VBIT
+ 1), "h-vbit", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
387 { HW_H_CBIT
, & HW_ENT (HW_H_CBIT
+ 1), "h-cbit", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
391 /* The operand table. */
393 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
394 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
396 const CGEN_OPERAND fr30_cgen_operand_table
[MAX_OPERANDS
] =
398 /* pc: program counter */
399 { "pc", & HW_ENT (HW_H_PC
), 0, 0,
400 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
401 /* Ri: destination register */
402 { "Ri", & HW_ENT (HW_H_GR
), 12, 4,
403 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
404 /* Rj: source register */
405 { "Rj", & HW_ENT (HW_H_GR
), 8, 4,
406 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
407 /* Rs1: dedicated register */
408 { "Rs1", & HW_ENT (HW_H_DR
), 8, 4,
409 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
410 /* Rs2: dedicated register */
411 { "Rs2", & HW_ENT (HW_H_DR
), 12, 4,
412 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
413 /* ps: Program Status register */
414 { "ps", & HW_ENT (HW_H_CR
), 0, 0,
415 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
416 /* u4: 4 bit unsigned immediate */
417 { "u4", & HW_ENT (HW_H_UINT
), 8, 4,
418 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
419 /* m4: 4 bit negative immediate */
420 { "m4", & HW_ENT (HW_H_UINT
), 8, 4,
421 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
422 /* i8: 8 bit unsigned immediate */
423 { "i8", & HW_ENT (HW_H_UINT
), 4, 8,
424 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
425 /* u8: 8 bit unsigned immediate */
426 { "u8", & HW_ENT (HW_H_UINT
), 8, 8,
427 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
428 /* o8: 8 bit signed immediate */
429 { "o8", & HW_ENT (HW_H_SINT
), 4, 8,
430 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
431 /* s10: 10 bit signed immediate */
432 { "s10", & HW_ENT (HW_H_SINT
), 8, 8,
433 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_SIGNED
), { 0 } } },
434 /* u10: 10 bit unsigned immediate */
435 { "u10", & HW_ENT (HW_H_UINT
), 8, 8,
436 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
437 /* dir8: 8 bit direct address */
438 { "dir8", & HW_ENT (HW_H_UINT
), 8, 8,
439 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
440 /* dir9: 9 bit direct address */
441 { "dir9", & HW_ENT (HW_H_UINT
), 8, 8,
442 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
443 /* dir10: 10 bit direct address */
444 { "dir10", & HW_ENT (HW_H_UINT
), 8, 8,
445 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
446 /* label9: 9 bit pc relative address */
447 { "label9", & HW_ENT (HW_H_SINT
), 8, 8,
448 { 0, 0|(1<<CGEN_OPERAND_SIGNED
), { 0 } } },
449 /* label12: 12 bit pc relative address */
450 { "label12", & HW_ENT (HW_H_SINT
), 5, 11,
451 { 0, 0|(1<<CGEN_OPERAND_SIGNED
), { 0 } } },
452 /* cc: condition codes */
453 { "cc", & HW_ENT (HW_H_UINT
), 4, 4,
454 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
455 /* nbit: negative bit */
456 { "nbit", & HW_ENT (HW_H_NBIT
), 0, 0,
457 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
458 /* vbit: overflow bit */
459 { "vbit", & HW_ENT (HW_H_VBIT
), 0, 0,
460 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
462 { "zbit", & HW_ENT (HW_H_ZBIT
), 0, 0,
463 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
464 /* cbit: carry bit */
465 { "cbit", & HW_ENT (HW_H_CBIT
), 0, 0,
466 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
469 /* Operand references. */
471 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
472 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
474 static const CGEN_OPERAND_INSTANCE fmt_add_ops
[] = {
475 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
476 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0 },
477 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0 },
478 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0 },
479 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
480 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0 },
481 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0 },
485 static const CGEN_OPERAND_INSTANCE fmt_addi_ops
[] = {
486 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
487 { INPUT
, "u4", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (U4
), 0 },
488 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0 },
489 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0 },
490 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
491 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0 },
492 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0 },
496 static const CGEN_OPERAND_INSTANCE fmt_add2_ops
[] = {
497 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
498 { INPUT
, "m4", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (M4
), 0 },
499 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0 },
500 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0 },
501 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
502 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0 },
503 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0 },
507 static const CGEN_OPERAND_INSTANCE fmt_addc_ops
[] = {
508 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
509 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0 },
510 { INPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0 },
511 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0 },
512 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0 },
513 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
514 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0 },
515 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0 },
519 static const CGEN_OPERAND_INSTANCE fmt_addn_ops
[] = {
520 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
521 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0 },
522 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
526 static const CGEN_OPERAND_INSTANCE fmt_addni_ops
[] = {
527 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
528 { INPUT
, "u4", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (U4
), 0 },
529 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
533 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops
[] = {
534 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
535 { INPUT
, "m4", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (M4
), 0 },
536 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
540 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops
[] = {
541 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
542 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0 },
543 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0 },
544 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0 },
545 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0 },
546 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0 },
550 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops
[] = {
551 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
552 { INPUT
, "u4", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (U4
), 0 },
553 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0 },
554 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0 },
555 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0 },
556 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0 },
560 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops
[] = {
561 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
562 { INPUT
, "m4", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (M4
), 0 },
563 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0 },
564 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0 },
565 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0 },
566 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0 },
570 static const CGEN_OPERAND_INSTANCE fmt_and_ops
[] = {
571 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
572 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0 },
573 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0 },
574 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0 },
575 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0 },
579 static const CGEN_OPERAND_INSTANCE fmt_andm_ops
[] = {
580 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RI
), 0 },
581 { INPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
582 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0 },
583 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0 },
584 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0 },
585 { OUTPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
589 static const CGEN_OPERAND_INSTANCE fmt_andh_ops
[] = {
590 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RI
), 0 },
591 { INPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0 },
592 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_HI
, & OP_ENT (RJ
), 0 },
593 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0 },
594 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0 },
595 { OUTPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0 },
599 static const CGEN_OPERAND_INSTANCE fmt_andb_ops
[] = {
600 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RI
), 0 },
601 { INPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0 },
602 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_QI
, & OP_ENT (RJ
), 0 },
603 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0 },
604 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0 },
605 { OUTPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0 },
612 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
613 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
614 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
616 /* The instruction table.
617 This is currently non-static because the simulator accesses it
620 const CGEN_INSN fr30_cgen_insn_table_entries
[MAX_INSNS
] =
622 /* Special null first entry.
623 A `num' value of zero is thus invalid.
624 Also, the special `invalid' insn resides here. */
629 FR30_INSN_ADD
, "add", "add",
630 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
631 { 16, 16, 0xff00 }, 0xa600,
632 (PTR
) & fmt_add_ops
[0],
638 FR30_INSN_ADDI
, "addi", "add",
639 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
640 { 16, 16, 0xff00 }, 0xa400,
641 (PTR
) & fmt_addi_ops
[0],
647 FR30_INSN_ADD2
, "add2", "add2",
648 { { MNEM
, ' ', OP (M4
), ',', OP (RI
), 0 } },
649 { 16, 16, 0xff00 }, 0xa500,
650 (PTR
) & fmt_add2_ops
[0],
656 FR30_INSN_ADDC
, "addc", "addc",
657 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
658 { 16, 16, 0xff00 }, 0xa700,
659 (PTR
) & fmt_addc_ops
[0],
665 FR30_INSN_ADDN
, "addn", "addn",
666 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
667 { 16, 16, 0xff00 }, 0xa200,
668 (PTR
) & fmt_addn_ops
[0],
674 FR30_INSN_ADDNI
, "addni", "addn",
675 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
676 { 16, 16, 0xff00 }, 0xa000,
677 (PTR
) & fmt_addni_ops
[0],
683 FR30_INSN_ADDN2
, "addn2", "addn2",
684 { { MNEM
, ' ', OP (M4
), ',', OP (RI
), 0 } },
685 { 16, 16, 0xff00 }, 0xa100,
686 (PTR
) & fmt_addn2_ops
[0],
692 FR30_INSN_SUB
, "sub", "sub",
693 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
694 { 16, 16, 0xff00 }, 0xac00,
695 (PTR
) & fmt_add_ops
[0],
701 FR30_INSN_SUBC
, "subc", "subc",
702 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
703 { 16, 16, 0xff00 }, 0xad00,
704 (PTR
) & fmt_addc_ops
[0],
710 FR30_INSN_SUBN
, "subn", "subn",
711 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
712 { 16, 16, 0xff00 }, 0xae00,
713 (PTR
) & fmt_addn_ops
[0],
719 FR30_INSN_CMP
, "cmp", "cmp",
720 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
721 { 16, 16, 0xff00 }, 0xaa00,
722 (PTR
) & fmt_cmp_ops
[0],
728 FR30_INSN_CMPI
, "cmpi", "cmp",
729 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
730 { 16, 16, 0xff00 }, 0xa800,
731 (PTR
) & fmt_cmpi_ops
[0],
737 FR30_INSN_CMP2
, "cmp2", "cmp2",
738 { { MNEM
, ' ', OP (M4
), ',', OP (RI
), 0 } },
739 { 16, 16, 0xff00 }, 0xa900,
740 (PTR
) & fmt_cmp2_ops
[0],
746 FR30_INSN_AND
, "and", "and",
747 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
748 { 16, 16, 0xff00 }, 0x8200,
749 (PTR
) & fmt_and_ops
[0],
755 FR30_INSN_OR
, "or", "or",
756 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
757 { 16, 16, 0xff00 }, 0x9200,
758 (PTR
) & fmt_and_ops
[0],
764 FR30_INSN_EOR
, "eor", "eor",
765 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
766 { 16, 16, 0xff00 }, 0x9a00,
767 (PTR
) & fmt_and_ops
[0],
773 FR30_INSN_ANDM
, "andm", "and",
774 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
775 { 16, 16, 0xff00 }, 0x8400,
776 (PTR
) & fmt_andm_ops
[0],
782 FR30_INSN_ANDH
, "andh", "andh",
783 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
784 { 16, 16, 0xff00 }, 0x8500,
785 (PTR
) & fmt_andh_ops
[0],
791 FR30_INSN_ANDB
, "andb", "andb",
792 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
793 { 16, 16, 0xff00 }, 0x8600,
794 (PTR
) & fmt_andb_ops
[0],
800 FR30_INSN_ORM
, "orm", "or",
801 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
802 { 16, 16, 0xff00 }, 0x9400,
803 (PTR
) & fmt_andm_ops
[0],
809 FR30_INSN_ORH
, "orh", "orh",
810 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
811 { 16, 16, 0xff00 }, 0x9500,
812 (PTR
) & fmt_andh_ops
[0],
818 FR30_INSN_ORB
, "orb", "orb",
819 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
820 { 16, 16, 0xff00 }, 0x9600,
821 (PTR
) & fmt_andb_ops
[0],
827 FR30_INSN_EORM
, "eorm", "eor",
828 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
829 { 16, 16, 0xff00 }, 0x9c00,
830 (PTR
) & fmt_andm_ops
[0],
836 FR30_INSN_EORH
, "eorh", "eorh",
837 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
838 { 16, 16, 0xff00 }, 0x9d00,
839 (PTR
) & fmt_andh_ops
[0],
845 FR30_INSN_EORB
, "eorb", "eorb",
846 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
847 { 16, 16, 0xff00 }, 0x9e00,
848 (PTR
) & fmt_andb_ops
[0],
854 FR30_INSN_BANDL
, "bandl", "bandl",
855 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
856 { 16, 16, 0xff00 }, 0x8000,
863 FR30_INSN_BORL
, "borl", "borl",
864 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
865 { 16, 16, 0xff00 }, 0x9000,
872 FR30_INSN_BEORL
, "beorl", "beorl",
873 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
874 { 16, 16, 0xff00 }, 0x9800,
881 FR30_INSN_BANDH
, "bandh", "bandh",
882 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
883 { 16, 16, 0xff00 }, 0x8100,
890 FR30_INSN_BORH
, "borh", "borh",
891 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
892 { 16, 16, 0xff00 }, 0x9100,
899 FR30_INSN_BEORH
, "beorh", "beorh",
900 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
901 { 16, 16, 0xff00 }, 0x9900,
908 FR30_INSN_BTSTL
, "btstl", "btstl",
909 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
910 { 16, 16, 0xff00 }, 0x8800,
917 FR30_INSN_BTSTH
, "btsth", "btsth",
918 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
919 { 16, 16, 0xff00 }, 0x8900,
926 FR30_INSN_MUL
, "mul", "mul",
927 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
928 { 16, 16, 0xff00 }, 0xaf00,
935 FR30_INSN_MULU
, "mulu", "mulu",
936 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
937 { 16, 16, 0xff00 }, 0xab00,
944 FR30_INSN_MULH
, "mulh", "mulh",
945 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
946 { 16, 16, 0xff00 }, 0xbf00,
953 FR30_INSN_MULUH
, "muluh", "muluh",
954 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
955 { 16, 16, 0xff00 }, 0xbb00,
962 FR30_INSN_DIV0S
, "div0s", "div0s",
963 { { MNEM
, ' ', OP (RI
), 0 } },
964 { 16, 16, 0xfff0 }, 0x9740,
971 FR30_INSN_DIV0U
, "div0u", "div0u",
972 { { MNEM
, ' ', OP (RI
), 0 } },
973 { 16, 16, 0xfff0 }, 0x9750,
980 FR30_INSN_DIV1
, "div1", "div1",
981 { { MNEM
, ' ', OP (RI
), 0 } },
982 { 16, 16, 0xfff0 }, 0x9760,
989 FR30_INSN_DIV2
, "div2", "div2",
990 { { MNEM
, ' ', OP (RI
), 0 } },
991 { 16, 16, 0xfff0 }, 0x9770,
998 FR30_INSN_DIV3
, "div3", "div3",
1000 { 16, 16, 0xffff }, 0x9f60,
1007 FR30_INSN_DIV4S
, "div4s", "div4s",
1009 { 16, 16, 0xffff }, 0x9f70,
1016 FR30_INSN_LSL
, "lsl", "lsl",
1017 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
1018 { 16, 16, 0xff00 }, 0xb600,
1025 FR30_INSN_LSLI
, "lsli", "lsl",
1026 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
1027 { 16, 16, 0xff00 }, 0xb400,
1034 FR30_INSN_LSL2
, "lsl2", "lsl2",
1035 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
1036 { 16, 16, 0xff00 }, 0xb500,
1043 FR30_INSN_LSR
, "lsr", "lsr",
1044 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
1045 { 16, 16, 0xff00 }, 0xb200,
1052 FR30_INSN_LSRI
, "lsri", "lsr",
1053 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
1054 { 16, 16, 0xff00 }, 0xb000,
1061 FR30_INSN_LSR2
, "lsr2", "lsr2",
1062 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
1063 { 16, 16, 0xff00 }, 0xb100,
1070 FR30_INSN_ASR
, "asr", "asr",
1071 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
1072 { 16, 16, 0xff00 }, 0xba00,
1079 FR30_INSN_ASRI
, "asri", "asr",
1080 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
1081 { 16, 16, 0xff00 }, 0xb800,
1088 FR30_INSN_ASR2
, "asr2", "asr2",
1089 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
1090 { 16, 16, 0xff00 }, 0xb900,
1097 FR30_INSN_LDI_8
, "ldi:8", "ldi:8",
1098 { { MNEM
, ' ', OP (I8
), ',', OP (RI
), 0 } },
1099 { 16, 16, 0xf000 }, 0xc000,
1106 FR30_INSN_LD
, "ld", "ld",
1107 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
1108 { 16, 16, 0xff00 }, 0x400,
1115 FR30_INSN_LDUH
, "lduh", "lduh",
1116 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
1117 { 16, 16, 0xff00 }, 0x500,
1124 FR30_INSN_LDUB
, "ldub", "ldub",
1125 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
1126 { 16, 16, 0xff00 }, 0x600,
1130 /* ld @(R13,$Rj),$Ri */
1133 FR30_INSN_LDR13
, "ldr13", "ld",
1134 { { MNEM
, ' ', '@', '(', 'R', '1', '3', ',', OP (RJ
), ')', ',', OP (RI
), 0 } },
1135 { 16, 16, 0xff00 }, 0x0,
1139 /* lduh @(R13,$Rj),$Ri */
1142 FR30_INSN_LDR13UH
, "ldr13uh", "lduh",
1143 { { MNEM
, ' ', '@', '(', 'R', '1', '3', ',', OP (RJ
), ')', ',', OP (RI
), 0 } },
1144 { 16, 16, 0xff00 }, 0x100,
1148 /* ldub @(R13,$Rj),$Ri */
1151 FR30_INSN_LDR13UB
, "ldr13ub", "ldub",
1152 { { MNEM
, ' ', '@', '(', 'R', '1', '3', ',', OP (RJ
), ')', ',', OP (RI
), 0 } },
1153 { 16, 16, 0xff00 }, 0x200,
1157 /* ld @(R14,$o8),$Ri */
1160 FR30_INSN_LDR14
, "ldr14", "ld",
1161 { { MNEM
, ' ', '@', '(', 'R', '1', '4', ',', OP (O8
), ')', ',', OP (RI
), 0 } },
1162 { 16, 16, 0xf000 }, 0x2000,
1166 /* lduh @(R14,$o8),$Ri */
1169 FR30_INSN_LDR14UH
, "ldr14uh", "lduh",
1170 { { MNEM
, ' ', '@', '(', 'R', '1', '4', ',', OP (O8
), ')', ',', OP (RI
), 0 } },
1171 { 16, 16, 0xf000 }, 0x4000,
1175 /* ldub @(R14,$o8),$Ri */
1178 FR30_INSN_LDR14UB
, "ldr14ub", "ldub",
1179 { { MNEM
, ' ', '@', '(', 'R', '1', '4', ',', OP (O8
), ')', ',', OP (RI
), 0 } },
1180 { 16, 16, 0xf000 }, 0x6000,
1184 /* ld @(R15,$u4),$Ri */
1187 FR30_INSN_LDR15
, "ldr15", "ld",
1188 { { MNEM
, ' ', '@', '(', 'R', '1', '5', ',', OP (U4
), ')', ',', OP (RI
), 0 } },
1189 { 16, 16, 0xff00 }, 0x300,
1196 FR30_INSN_LDR15GR
, "ldr15gr", "ld",
1197 { { MNEM
, ' ', '@', 'R', '1', '5', '+', ',', OP (RI
), 0 } },
1198 { 16, 16, 0xfff0 }, 0x700,
1205 FR30_INSN_LDR15DR
, "ldr15dr", "ld",
1206 { { MNEM
, ' ', '@', 'R', '1', '5', '+', ',', OP (RS2
), 0 } },
1207 { 16, 16, 0xfff0 }, 0x780,
1214 FR30_INSN_LDR15PS
, "ldr15ps", "ld",
1215 { { MNEM
, ' ', '@', 'R', '1', '5', '+', ',', 'p', 's', 0 } },
1216 { 16, 16, 0xffff }, 0x790,
1223 FR30_INSN_ST
, "st", "st",
1224 { { MNEM
, ' ', OP (RI
), ',', '@', 'R', 'j', 0 } },
1225 { 16, 16, 0xff00 }, 0x1400,
1232 FR30_INSN_STH
, "sth", "sth",
1233 { { MNEM
, ' ', OP (RI
), ',', '@', 'R', 'j', 0 } },
1234 { 16, 16, 0xff00 }, 0x1500,
1241 FR30_INSN_STB
, "stb", "stb",
1242 { { MNEM
, ' ', OP (RI
), ',', '@', 'R', 'j', 0 } },
1243 { 16, 16, 0xff00 }, 0x1600,
1247 /* st $Ri,@(R13,$Rj) */
1250 FR30_INSN_STR13
, "str13", "st",
1251 { { MNEM
, ' ', OP (RI
), ',', '@', '(', 'R', '1', '3', ',', OP (RJ
), ')', 0 } },
1252 { 16, 16, 0xff00 }, 0x1000,
1256 /* sth $Ri,@(R13,$Rj) */
1259 FR30_INSN_STR13H
, "str13h", "sth",
1260 { { MNEM
, ' ', OP (RI
), ',', '@', '(', 'R', '1', '3', ',', OP (RJ
), ')', 0 } },
1261 { 16, 16, 0xff00 }, 0x1100,
1265 /* stb $Ri,@(R13,$Rj) */
1268 FR30_INSN_STR13B
, "str13b", "stb",
1269 { { MNEM
, ' ', OP (RI
), ',', '@', '(', 'R', '1', '3', ',', OP (RJ
), ')', 0 } },
1270 { 16, 16, 0xff00 }, 0x1200,
1274 /* st $Ri,@(R14,$o8) */
1277 FR30_INSN_STR14
, "str14", "st",
1278 { { MNEM
, ' ', OP (RI
), ',', '@', '(', 'R', '1', '4', ',', OP (O8
), ')', 0 } },
1279 { 16, 16, 0xf000 }, 0x3000,
1283 /* sth $Ri,@(R14,$o8) */
1286 FR30_INSN_STR14H
, "str14h", "sth",
1287 { { MNEM
, ' ', OP (RI
), ',', '@', '(', 'R', '1', '4', ',', OP (O8
), ')', 0 } },
1288 { 16, 16, 0xf000 }, 0x5000,
1292 /* stb $Ri,@(R14,$o8) */
1295 FR30_INSN_STR14B
, "str14b", "stb",
1296 { { MNEM
, ' ', OP (RI
), ',', '@', '(', 'R', '1', '4', ',', OP (O8
), ')', 0 } },
1297 { 16, 16, 0xf000 }, 0x7000,
1301 /* st $Ri,@(R15,$u4) */
1304 FR30_INSN_STR15
, "str15", "st",
1305 { { MNEM
, ' ', OP (RI
), ',', '@', '(', 'R', '1', '5', ',', OP (U4
), ')', 0 } },
1306 { 16, 16, 0xff00 }, 0x1300,
1313 FR30_INSN_STR15GR
, "str15gr", "st",
1314 { { MNEM
, ' ', OP (RI
), ',', '@', '-', 'R', '1', '5', 0 } },
1315 { 16, 16, 0xfff0 }, 0x1700,
1322 FR30_INSN_STR15DR
, "str15dr", "st",
1323 { { MNEM
, ' ', OP (RS2
), ',', '@', '-', 'R', '1', '5', 0 } },
1324 { 16, 16, 0xfff0 }, 0x1780,
1331 FR30_INSN_STR15PS
, "str15ps", "st",
1332 { { MNEM
, ' ', 'p', 's', ',', '@', '-', 'R', '1', '5', 0 } },
1333 { 16, 16, 0xffff }, 0x1790,
1340 FR30_INSN_MOV
, "mov", "mov",
1341 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
1342 { 16, 16, 0xff00 }, 0x8b00,
1349 FR30_INSN_MOVDR
, "movdr", "mov",
1350 { { MNEM
, ' ', OP (RS1
), ',', OP (RI
), 0 } },
1351 { 16, 16, 0xff00 }, 0xb700,
1358 FR30_INSN_MOVPS
, "movps", "mov",
1359 { { MNEM
, ' ', 'p', 's', ',', OP (RI
), 0 } },
1360 { 16, 16, 0xfff0 }, 0x1710,
1367 FR30_INSN_MOV2DR
, "mov2dr", "mov",
1368 { { MNEM
, ' ', OP (RI
), ',', OP (RS1
), 0 } },
1369 { 16, 16, 0xff00 }, 0xb300,
1376 FR30_INSN_MOV2PS
, "mov2ps", "mov",
1377 { { MNEM
, ' ', OP (RI
), ',', 'p', 's', 0 } },
1378 { 16, 16, 0xfff0 }, 0x710,
1385 FR30_INSN_JMP
, "jmp", "jmp",
1386 { { MNEM
, ' ', '@', OP (RI
), 0 } },
1387 { 16, 16, 0xfff0 }, 0x9700,
1394 FR30_INSN_CALL
, "call", "call",
1395 { { MNEM
, ' ', OP (LABEL12
), 0 } },
1396 { 16, 16, 0xf400 }, 0xd000,
1403 FR30_INSN_CALLR
, "callr", "call",
1404 { { MNEM
, ' ', '@', OP (RI
), 0 } },
1405 { 16, 16, 0xfff0 }, 0x9710,
1412 FR30_INSN_RET
, "ret", "ret",
1414 { 16, 16, 0xffff }, 0x9720,
1421 FR30_INSN_INT
, "int", "int",
1422 { { MNEM
, ' ', OP (U8
), 0 } },
1423 { 16, 16, 0xff00 }, 0x1f00,
1430 FR30_INSN_INTE
, "inte", "int3",
1432 { 16, 16, 0xffff }, 0x9f30,
1439 FR30_INSN_RETI
, "reti", "reti",
1441 { 16, 16, 0xffff }, 0x9730,
1448 FR30_INSN_BRA
, "bra", "bra:D",
1449 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1450 { 16, 16, 0xff00 }, 0xe000,
1457 FR30_INSN_BNO
, "bno", "bno:D",
1458 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1459 { 16, 16, 0xff00 }, 0xe100,
1466 FR30_INSN_BEQ
, "beq", "beq:D",
1467 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1468 { 16, 16, 0xff00 }, 0xe200,
1475 FR30_INSN_BNE
, "bne", "bne:D",
1476 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1477 { 16, 16, 0xff00 }, 0xe300,
1484 FR30_INSN_BC
, "bc", "bc:D",
1485 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1486 { 16, 16, 0xff00 }, 0xe400,
1493 FR30_INSN_BNC
, "bnc", "bnc:D",
1494 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1495 { 16, 16, 0xff00 }, 0xe500,
1502 FR30_INSN_BN
, "bn", "bn:D",
1503 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1504 { 16, 16, 0xff00 }, 0xe600,
1511 FR30_INSN_BP
, "bp", "bp:D",
1512 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1513 { 16, 16, 0xff00 }, 0xe700,
1520 FR30_INSN_BV
, "bv", "bv:D",
1521 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1522 { 16, 16, 0xff00 }, 0xe800,
1529 FR30_INSN_BNV
, "bnv", "bnv:D",
1530 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1531 { 16, 16, 0xff00 }, 0xe900,
1538 FR30_INSN_BLT
, "blt", "blt:D",
1539 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1540 { 16, 16, 0xff00 }, 0xea00,
1547 FR30_INSN_BGE
, "bge", "bge:D",
1548 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1549 { 16, 16, 0xff00 }, 0xeb00,
1556 FR30_INSN_BLE
, "ble", "ble:D",
1557 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1558 { 16, 16, 0xff00 }, 0xec00,
1565 FR30_INSN_BGT
, "bgt", "bgt:D",
1566 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1567 { 16, 16, 0xff00 }, 0xed00,
1574 FR30_INSN_BLS
, "bls", "bls:D",
1575 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1576 { 16, 16, 0xff00 }, 0xee00,
1583 FR30_INSN_BHI
, "bhi", "bhi:D",
1584 { { MNEM
, ' ', OP (LABEL9
), 0 } },
1585 { 16, 16, 0xff00 }, 0xef00,
1589 /* dmov @$dir10,R13 */
1592 FR30_INSN_DMOV2R13
, "dmov2r13", "dmov",
1593 { { MNEM
, ' ', '@', OP (DIR10
), ',', 'R', '1', '3', 0 } },
1594 { 16, 16, 0xff00 }, 0x800,
1598 /* dmovh @$dir10,R13 */
1601 FR30_INSN_DMOV2R13H
, "dmov2r13h", "dmovh",
1602 { { MNEM
, ' ', '@', OP (DIR10
), ',', 'R', '1', '3', 0 } },
1603 { 16, 16, 0xff00 }, 0x900,
1607 /* dmovb @$dir10,R13 */
1610 FR30_INSN_DMOV2R13B
, "dmov2r13b", "dmovb",
1611 { { MNEM
, ' ', '@', OP (DIR10
), ',', 'R', '1', '3', 0 } },
1612 { 16, 16, 0xff00 }, 0xa00,
1616 /* dmov R13,@$dir10 */
1619 FR30_INSN_DMOVR13
, "dmovr13", "dmov",
1620 { { MNEM
, ' ', 'R', '1', '3', ',', '@', OP (DIR10
), 0 } },
1621 { 16, 16, 0xff00 }, 0x1800,
1625 /* dmovh R13,@$dir10 */
1628 FR30_INSN_DMOVR13H
, "dmovr13h", "dmovh",
1629 { { MNEM
, ' ', 'R', '1', '3', ',', '@', OP (DIR10
), 0 } },
1630 { 16, 16, 0xff00 }, 0x1900,
1634 /* dmovb R13,@$dir10 */
1637 FR30_INSN_DMOVR13B
, "dmovr13b", "dmovb",
1638 { { MNEM
, ' ', 'R', '1', '3', ',', '@', OP (DIR10
), 0 } },
1639 { 16, 16, 0xff00 }, 0x1a00,
1643 /* dmov @$dir10,R13+ */
1646 FR30_INSN_DMOV2R13PI
, "dmov2r13pi", "dmov",
1647 { { MNEM
, ' ', '@', OP (DIR10
), ',', 'R', '1', '3', '+', 0 } },
1648 { 16, 16, 0xff00 }, 0xc00,
1652 /* dmovh @$dir10,R13+ */
1655 FR30_INSN_DMOV2R13PIH
, "dmov2r13pih", "dmovh",
1656 { { MNEM
, ' ', '@', OP (DIR10
), ',', 'R', '1', '3', '+', 0 } },
1657 { 16, 16, 0xff00 }, 0xd00,
1661 /* dmovb @$dir10,R13+ */
1664 FR30_INSN_DMOV2R13PIB
, "dmov2r13pib", "dmovb",
1665 { { MNEM
, ' ', '@', OP (DIR10
), ',', 'R', '1', '3', '+', 0 } },
1666 { 16, 16, 0xff00 }, 0xe00,
1670 /* dmov R13+,@$dir10 */
1673 FR30_INSN_DMOV13PI
, "dmov13pi", "dmov",
1674 { { MNEM
, ' ', 'R', '1', '3', '+', ',', '@', OP (DIR10
), 0 } },
1675 { 16, 16, 0xff00 }, 0x1c00,
1679 /* dmovh R13+,@$dir10 */
1682 FR30_INSN_DMOV13PIH
, "dmov13pih", "dmovh",
1683 { { MNEM
, ' ', 'R', '1', '3', '+', ',', '@', OP (DIR10
), 0 } },
1684 { 16, 16, 0xff00 }, 0x1d00,
1688 /* dmovb R13+,@$dir10 */
1691 FR30_INSN_DMOV13PIB
, "dmov13pib", "dmovb",
1692 { { MNEM
, ' ', 'R', '1', '3', '+', ',', '@', OP (DIR10
), 0 } },
1693 { 16, 16, 0xff00 }, 0x1e00,
1697 /* dmov @$dir10,-R15 */
1700 FR30_INSN_DMOV2R15PD
, "dmov2r15pd", "dmov",
1701 { { MNEM
, ' ', '@', OP (DIR10
), ',', '-', 'R', '1', '5', 0 } },
1702 { 16, 16, 0xff00 }, 0xb00,
1706 /* dmov R15+,@$dir10 */
1709 FR30_INSN_DMOV15PI
, "dmov15pi", "dmov",
1710 { { MNEM
, ' ', 'R', '1', '5', '+', ',', '@', OP (DIR10
), 0 } },
1711 { 16, 16, 0xff00 }, 0x1b00,
1715 /* ldres @$Ri+,$u4 */
1718 FR30_INSN_LDRES
, "ldres", "ldres",
1719 { { MNEM
, ' ', '@', OP (RI
), '+', ',', OP (U4
), 0 } },
1720 { 16, 16, 0xff00 }, 0xbc00,
1724 /* ldres $u4,@$Ri+ */
1727 FR30_INSN_STRES
, "stres", "ldres",
1728 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), '+', 0 } },
1729 { 16, 16, 0xff00 }, 0xbd00,
1736 FR30_INSN_NOP
, "nop", "nop",
1738 { 16, 16, 0xffff }, 0x9fa0,
1745 FR30_INSN_ANDCCR
, "andccr", "andccr",
1746 { { MNEM
, ' ', OP (U8
), 0 } },
1747 { 16, 16, 0xff00 }, 0x8300,
1754 FR30_INSN_ORCCR
, "orccr", "orccr",
1755 { { MNEM
, ' ', OP (U8
), 0 } },
1756 { 16, 16, 0xff00 }, 0x9300,
1763 FR30_INSN_STILM
, "stilm", "stilm",
1764 { { MNEM
, ' ', OP (U8
), 0 } },
1765 { 16, 16, 0xff00 }, 0x8700,
1772 FR30_INSN_ADDSP
, "addsp", "addsp",
1773 { { MNEM
, ' ', OP (S10
), 0 } },
1774 { 16, 16, 0xff00 }, 0xa300,
1781 FR30_INSN_EXTSB
, "extsb", "extsb",
1782 { { MNEM
, ' ', OP (RI
), 0 } },
1783 { 16, 16, 0xfff0 }, 0x9780,
1790 FR30_INSN_EXTUB
, "extub", "extub",
1791 { { MNEM
, ' ', OP (RI
), 0 } },
1792 { 16, 16, 0xfff0 }, 0x9790,
1799 FR30_INSN_EXTSH
, "extsh", "extsh",
1800 { { MNEM
, ' ', OP (RI
), 0 } },
1801 { 16, 16, 0xfff0 }, 0x97a0,
1808 FR30_INSN_EXTUH
, "extuh", "extuh",
1809 { { MNEM
, ' ', OP (RI
), 0 } },
1810 { 16, 16, 0xfff0 }, 0x97b0,
1817 FR30_INSN_ENTER
, "enter", "enter",
1818 { { MNEM
, ' ', OP (U10
), 0 } },
1819 { 16, 16, 0xff00 }, 0xf00,
1826 FR30_INSN_LEAVE
, "leave", "leave",
1828 { 16, 16, 0xffff }, 0x9f90,
1835 FR30_INSN_XCHB
, "xchb", "xchb",
1836 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
1837 { 16, 16, 0xff00 }, 0x8a00,
1847 static const CGEN_INSN_TABLE insn_table
=
1849 & fr30_cgen_insn_table_entries
[0],
1855 /* Each non-simple macro entry points to an array of expansion possibilities. */
1857 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1858 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1859 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1861 /* The macro instruction table. */
1863 static const CGEN_INSN macro_insn_table_entries
[] =
1871 static const CGEN_INSN_TABLE macro_insn_table
=
1873 & macro_insn_table_entries
[0],
1875 (sizeof (macro_insn_table_entries
) /
1876 sizeof (macro_insn_table_entries
[0])),
1885 /* Return non-zero if INSN is to be added to the hash table.
1886 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
1889 asm_hash_insn_p (insn
)
1890 const CGEN_INSN
* insn
;
1892 return CGEN_ASM_HASH_P (insn
);
1896 dis_hash_insn_p (insn
)
1897 const CGEN_INSN
* insn
;
1899 /* If building the hash table and the NO-DIS attribute is present,
1901 if (CGEN_INSN_ATTR (insn
, CGEN_INSN_NO_DIS
))
1903 return CGEN_DIS_HASH_P (insn
);
1906 /* The result is the hash value of the insn.
1907 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
1910 asm_hash_insn (mnem
)
1913 return CGEN_ASM_HASH (mnem
);
1916 /* BUF is a pointer to the insn's bytes in target order.
1917 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
1921 dis_hash_insn (buf
, value
)
1923 unsigned long value
;
1925 return CGEN_DIS_HASH (buf
, value
);
1928 /* Initialize an opcode table and return a descriptor.
1929 It's much like opening a file, and must be the first function called. */
1932 fr30_cgen_opcode_open (mach
, endian
)
1934 enum cgen_endian endian
;
1936 CGEN_OPCODE_TABLE
* table
= (CGEN_OPCODE_TABLE
*) xmalloc (sizeof (CGEN_OPCODE_TABLE
));
1945 memset (table
, 0, sizeof (*table
));
1947 CGEN_OPCODE_MACH (table
) = mach
;
1948 CGEN_OPCODE_ENDIAN (table
) = endian
;
1949 /* FIXME: for the sparc case we can determine insn-endianness statically.
1950 The worry here is where both data and insn endian can be independently
1951 chosen, in which case this function will need another argument.
1952 Actually, will want to allow for more arguments in the future anyway. */
1953 CGEN_OPCODE_INSN_ENDIAN (table
) = endian
;
1955 CGEN_OPCODE_HW_LIST (table
) = & fr30_cgen_hw_entries
[0];
1957 CGEN_OPCODE_OPERAND_TABLE (table
) = & fr30_cgen_operand_table
[0];
1959 * CGEN_OPCODE_INSN_TABLE (table
) = insn_table
;
1961 * CGEN_OPCODE_MACRO_INSN_TABLE (table
) = macro_insn_table
;
1963 CGEN_OPCODE_ASM_HASH_P (table
) = asm_hash_insn_p
;
1964 CGEN_OPCODE_ASM_HASH (table
) = asm_hash_insn
;
1965 CGEN_OPCODE_ASM_HASH_SIZE (table
) = CGEN_ASM_HASH_SIZE
;
1967 CGEN_OPCODE_DIS_HASH_P (table
) = dis_hash_insn_p
;
1968 CGEN_OPCODE_DIS_HASH (table
) = dis_hash_insn
;
1969 CGEN_OPCODE_DIS_HASH_SIZE (table
) = CGEN_DIS_HASH_SIZE
;
1971 return (CGEN_OPCODE_DESC
) table
;
1974 /* Close an opcode table. */
1977 fr30_cgen_opcode_close (desc
)
1978 CGEN_OPCODE_DESC desc
;
1983 /* Getting values from cgen_fields is handled by a collection of functions.
1984 They are distinguished by the type of the VALUE argument they return.
1985 TODO: floating point, inlining support, remove cases where result type
1989 fr30_cgen_get_int_operand (opindex
, fields
)
1991 const CGEN_FIELDS
* fields
;
1997 case FR30_OPERAND_RI
:
1998 value
= fields
->f_Ri
;
2000 case FR30_OPERAND_RJ
:
2001 value
= fields
->f_Rj
;
2003 case FR30_OPERAND_RS1
:
2004 value
= fields
->f_Rs1
;
2006 case FR30_OPERAND_RS2
:
2007 value
= fields
->f_Rs2
;
2009 case FR30_OPERAND_U4
:
2010 value
= fields
->f_u4
;
2012 case FR30_OPERAND_M4
:
2013 value
= fields
->f_m4
;
2015 case FR30_OPERAND_I8
:
2016 value
= fields
->f_i8
;
2018 case FR30_OPERAND_U8
:
2019 value
= fields
->f_u8
;
2021 case FR30_OPERAND_O8
:
2022 value
= fields
->f_o8
;
2024 case FR30_OPERAND_S10
:
2025 value
= fields
->f_s10
;
2027 case FR30_OPERAND_U10
:
2028 value
= fields
->f_u10
;
2030 case FR30_OPERAND_DIR8
:
2031 value
= fields
->f_dir8
;
2033 case FR30_OPERAND_DIR9
:
2034 value
= fields
->f_dir9
;
2036 case FR30_OPERAND_DIR10
:
2037 value
= fields
->f_dir10
;
2039 case FR30_OPERAND_LABEL9
:
2040 value
= fields
->f_rel8
;
2042 case FR30_OPERAND_LABEL12
:
2043 value
= fields
->f_rel11
;
2045 case FR30_OPERAND_CC
:
2046 value
= fields
->f_cc
;
2050 /* xgettext:c-format */
2051 fprintf (stderr
, _("Unrecognized field %d while getting int operand.\n"),
2060 fr30_cgen_get_vma_operand (opindex
, fields
)
2062 const CGEN_FIELDS
* fields
;
2068 case FR30_OPERAND_RI
:
2069 value
= fields
->f_Ri
;
2071 case FR30_OPERAND_RJ
:
2072 value
= fields
->f_Rj
;
2074 case FR30_OPERAND_RS1
:
2075 value
= fields
->f_Rs1
;
2077 case FR30_OPERAND_RS2
:
2078 value
= fields
->f_Rs2
;
2080 case FR30_OPERAND_U4
:
2081 value
= fields
->f_u4
;
2083 case FR30_OPERAND_M4
:
2084 value
= fields
->f_m4
;
2086 case FR30_OPERAND_I8
:
2087 value
= fields
->f_i8
;
2089 case FR30_OPERAND_U8
:
2090 value
= fields
->f_u8
;
2092 case FR30_OPERAND_O8
:
2093 value
= fields
->f_o8
;
2095 case FR30_OPERAND_S10
:
2096 value
= fields
->f_s10
;
2098 case FR30_OPERAND_U10
:
2099 value
= fields
->f_u10
;
2101 case FR30_OPERAND_DIR8
:
2102 value
= fields
->f_dir8
;
2104 case FR30_OPERAND_DIR9
:
2105 value
= fields
->f_dir9
;
2107 case FR30_OPERAND_DIR10
:
2108 value
= fields
->f_dir10
;
2110 case FR30_OPERAND_LABEL9
:
2111 value
= fields
->f_rel8
;
2113 case FR30_OPERAND_LABEL12
:
2114 value
= fields
->f_rel11
;
2116 case FR30_OPERAND_CC
:
2117 value
= fields
->f_cc
;
2121 /* xgettext:c-format */
2122 fprintf (stderr
, _("Unrecognized field %d while getting vma operand.\n"),
2130 /* Stuffing values in cgen_fields is handled by a collection of functions.
2131 They are distinguished by the type of the VALUE argument they accept.
2132 TODO: floating point, inlining support, remove cases where argument type
2136 fr30_cgen_set_int_operand (opindex
, fields
, value
)
2138 CGEN_FIELDS
* fields
;
2143 case FR30_OPERAND_RI
:
2144 fields
->f_Ri
= value
;
2146 case FR30_OPERAND_RJ
:
2147 fields
->f_Rj
= value
;
2149 case FR30_OPERAND_RS1
:
2150 fields
->f_Rs1
= value
;
2152 case FR30_OPERAND_RS2
:
2153 fields
->f_Rs2
= value
;
2155 case FR30_OPERAND_U4
:
2156 fields
->f_u4
= value
;
2158 case FR30_OPERAND_M4
:
2159 fields
->f_m4
= value
;
2161 case FR30_OPERAND_I8
:
2162 fields
->f_i8
= value
;
2164 case FR30_OPERAND_U8
:
2165 fields
->f_u8
= value
;
2167 case FR30_OPERAND_O8
:
2168 fields
->f_o8
= value
;
2170 case FR30_OPERAND_S10
:
2171 fields
->f_s10
= value
;
2173 case FR30_OPERAND_U10
:
2174 fields
->f_u10
= value
;
2176 case FR30_OPERAND_DIR8
:
2177 fields
->f_dir8
= value
;
2179 case FR30_OPERAND_DIR9
:
2180 fields
->f_dir9
= value
;
2182 case FR30_OPERAND_DIR10
:
2183 fields
->f_dir10
= value
;
2185 case FR30_OPERAND_LABEL9
:
2186 fields
->f_rel8
= value
;
2188 case FR30_OPERAND_LABEL12
:
2189 fields
->f_rel11
= value
;
2191 case FR30_OPERAND_CC
:
2192 fields
->f_cc
= value
;
2196 /* xgettext:c-format */
2197 fprintf (stderr
, _("Unrecognized field %d while setting int operand.\n"),
2204 fr30_cgen_set_vma_operand (opindex
, fields
, value
)
2206 CGEN_FIELDS
* fields
;
2211 case FR30_OPERAND_RI
:
2212 fields
->f_Ri
= value
;
2214 case FR30_OPERAND_RJ
:
2215 fields
->f_Rj
= value
;
2217 case FR30_OPERAND_RS1
:
2218 fields
->f_Rs1
= value
;
2220 case FR30_OPERAND_RS2
:
2221 fields
->f_Rs2
= value
;
2223 case FR30_OPERAND_U4
:
2224 fields
->f_u4
= value
;
2226 case FR30_OPERAND_M4
:
2227 fields
->f_m4
= value
;
2229 case FR30_OPERAND_I8
:
2230 fields
->f_i8
= value
;
2232 case FR30_OPERAND_U8
:
2233 fields
->f_u8
= value
;
2235 case FR30_OPERAND_O8
:
2236 fields
->f_o8
= value
;
2238 case FR30_OPERAND_S10
:
2239 fields
->f_s10
= value
;
2241 case FR30_OPERAND_U10
:
2242 fields
->f_u10
= value
;
2244 case FR30_OPERAND_DIR8
:
2245 fields
->f_dir8
= value
;
2247 case FR30_OPERAND_DIR9
:
2248 fields
->f_dir9
= value
;
2250 case FR30_OPERAND_DIR10
:
2251 fields
->f_dir10
= value
;
2253 case FR30_OPERAND_LABEL9
:
2254 fields
->f_rel8
= value
;
2256 case FR30_OPERAND_LABEL12
:
2257 fields
->f_rel11
= value
;
2259 case FR30_OPERAND_CC
:
2260 fields
->f_cc
= value
;
2264 /* xgettext:c-format */
2265 fprintf (stderr
, _("Unrecognized field %d while setting vma operand.\n"),