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Thu Dec 3 14:26:20 1998 Dave Brolley <brolley@cygnus.com>
[deliverable/binutils-gdb.git] / opcodes / fr30-opc.c
1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 THIS FILE IS USED TO GENERATE fr30-opc.c.
5
6 Copyright (C) 1998 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include "ansidecl.h"
27 #include "libiberty.h"
28 #include "bfd.h"
29 #include "symcat.h"
30 #include "fr30-opc.h"
31 #include "opintl.h"
32
33 /* Used by the ifield rtx function. */
34 #define FLD(f) (fields->f)
35
36 /* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
38
39 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
40 static unsigned int asm_hash_insn PARAMS ((const char *));
41 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
42 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
43
44 /* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
51
52 The result is a pointer to the insn table entry, or NULL if the instruction
53 wasn't recognized. */
54
55 const CGEN_INSN *
56 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
57 CGEN_OPCODE_DESC od;
58 const CGEN_INSN *insn;
59 CGEN_INSN_BYTES insn_value;
60 int length;
61 CGEN_FIELDS *fields;
62 int alias_p;
63 {
64 unsigned char buf[CGEN_MAX_INSN_SIZE];
65 unsigned char *bufp;
66 CGEN_INSN_INT base_insn;
67 #if CGEN_INT_INSN_P
68 CGEN_EXTRACT_INFO *info = NULL;
69 #else
70 CGEN_EXTRACT_INFO ex_info;
71 CGEN_EXTRACT_INFO *info = &ex_info;
72 #endif
73
74 #if CGEN_INT_INSN_P
75 cgen_put_insn_value (od, buf, length, insn_value);
76 bufp = buf;
77 base_insn = insn_value; /*???*/
78 #else
79 ex_info.dis_info = NULL;
80 ex_info.insn_bytes = insn_value;
81 ex_info.valid = -1;
82 base_insn = cgen_get_insn_value (od, buf, length);
83 bufp = insn_value;
84 #endif
85
86 if (!insn)
87 {
88 const CGEN_INSN_LIST *insn_list;
89
90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
92
93 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
94 while (insn_list != NULL)
95 {
96 insn = insn_list->insn;
97
98 if (alias_p
99 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
100 {
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
103 extract handler. */
104 if ((base_insn & CGEN_INSN_BASE_MASK (insn))
105 == CGEN_INSN_BASE_VALUE (insn))
106 {
107 /* ??? 0 is passed for `pc' */
108 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
109 base_insn, fields,
110 (bfd_vma) 0);
111 if (elength > 0)
112 {
113 /* sanity check */
114 if (length != 0 && length != elength)
115 abort ();
116 return insn;
117 }
118 }
119 }
120
121 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
122 }
123 }
124 else
125 {
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
127 if (! alias_p
128 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
129 abort ();
130 /* Sanity check: length must be correct. */
131 if (length != CGEN_INSN_BITSIZE (insn))
132 abort ();
133
134 /* ??? 0 is passed for `pc' */
135 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
136 (bfd_vma) 0);
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
139 if (length == 0)
140 abort ();
141 return insn;
142 }
143
144 return NULL;
145 }
146
147 /* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
149 in. */
150
151 void
152 fr30_cgen_get_insn_operands (od, insn, fields, indices)
153 CGEN_OPCODE_DESC od;
154 const CGEN_INSN * insn;
155 const CGEN_FIELDS * fields;
156 int *indices;
157 {
158 const CGEN_OPERAND_INSTANCE *opinst;
159 int i;
160
161 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
162 opinst != NULL
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
164 ++i, ++opinst)
165 {
166 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
167 if (op == NULL)
168 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
169 else
170 indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
171 fields);
172 }
173 }
174
175 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
176 isn't known.
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 fr30_cgen_lookup_insn unchanged.
179
180 The result is the insn table entry or NULL if the instruction wasn't
181 recognized. */
182
183 const CGEN_INSN *
184 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
185 CGEN_OPCODE_DESC od;
186 const CGEN_INSN *insn;
187 CGEN_INSN_BYTES insn_value;
188 int length;
189 int *indices;
190 {
191 CGEN_FIELDS fields;
192
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
196 insn != NULL);
197 if (! insn)
198 return NULL;
199
200 fr30_cgen_get_insn_operands (od, insn, &fields, indices);
201 return insn;
202 }
203 /* Attributes. */
204
205 static const CGEN_ATTR_ENTRY MACH_attr[] =
206 {
207 { "base", MACH_BASE },
208 { "fr30", MACH_FR30 },
209 { "max", MACH_MAX },
210 { 0, 0 }
211 };
212
213 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
214 {
215 { "CACHE-ADDR", NULL },
216 { "FUN-ACCESS", NULL },
217 { "PC", NULL },
218 { "PROFILE", NULL },
219 { 0, 0 }
220 };
221
222 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
223 {
224 { "ABS-ADDR", NULL },
225 { "HASH-PREFIX", NULL },
226 { "NEGATIVE", NULL },
227 { "PCREL-ADDR", NULL },
228 { "RELAX", NULL },
229 { "SEM-ONLY", NULL },
230 { "SIGN-OPT", NULL },
231 { "SIGNED", NULL },
232 { "UNSIGNED", NULL },
233 { "VIRTUAL", NULL },
234 { 0, 0 }
235 };
236
237 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
238 {
239 { "ALIAS", NULL },
240 { "COND-CTI", NULL },
241 { "DELAY-SLOT", NULL },
242 { "NO-DIS", NULL },
243 { "NOT-IN-DELAY-SLOT", NULL },
244 { "RELAX", NULL },
245 { "RELAXABLE", NULL },
246 { "SKIP-CTI", NULL },
247 { "UNCOND-CTI", NULL },
248 { "VIRTUAL", NULL },
249 { 0, 0 }
250 };
251
252 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
253 {
254 { "ac", 13 },
255 { "fp", 14 },
256 { "sp", 15 },
257 { "r0", 0 },
258 { "r1", 1 },
259 { "r2", 2 },
260 { "r3", 3 },
261 { "r4", 4 },
262 { "r5", 5 },
263 { "r6", 6 },
264 { "r7", 7 },
265 { "r8", 8 },
266 { "r9", 9 },
267 { "r10", 10 },
268 { "r11", 11 },
269 { "r12", 12 },
270 { "r13", 13 },
271 { "r14", 14 },
272 { "r15", 15 }
273 };
274
275 CGEN_KEYWORD fr30_cgen_opval_h_gr =
276 {
277 & fr30_cgen_opval_h_gr_entries[0],
278 19
279 };
280
281 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
282 {
283 { "cr0", 0 },
284 { "cr1", 1 },
285 { "cr2", 2 },
286 { "cr3", 3 },
287 { "cr4", 4 },
288 { "cr5", 5 },
289 { "cr6", 6 },
290 { "cr7", 7 },
291 { "cr8", 8 },
292 { "cr9", 9 },
293 { "cr10", 10 },
294 { "cr11", 11 },
295 { "cr12", 12 },
296 { "cr13", 13 },
297 { "cr14", 14 },
298 { "cr15", 15 }
299 };
300
301 CGEN_KEYWORD fr30_cgen_opval_h_cr =
302 {
303 & fr30_cgen_opval_h_cr_entries[0],
304 16
305 };
306
307 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
308 {
309 { "tbr", 0 },
310 { "rp", 1 },
311 { "ssp", 2 },
312 { "usp", 3 },
313 { "mdh", 4 },
314 { "mdl", 5 }
315 };
316
317 CGEN_KEYWORD fr30_cgen_opval_h_dr =
318 {
319 & fr30_cgen_opval_h_dr_entries[0],
320 6
321 };
322
323 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
324 {
325 { "ps", 0 }
326 };
327
328 CGEN_KEYWORD fr30_cgen_opval_h_ps =
329 {
330 & fr30_cgen_opval_h_ps_entries[0],
331 1
332 };
333
334 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
335 {
336 { "r13", 0 }
337 };
338
339 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
340 {
341 & fr30_cgen_opval_h_r13_entries[0],
342 1
343 };
344
345 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
346 {
347 { "r14", 0 }
348 };
349
350 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
351 {
352 & fr30_cgen_opval_h_r14_entries[0],
353 1
354 };
355
356 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
357 {
358 { "r15", 0 }
359 };
360
361 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
362 {
363 & fr30_cgen_opval_h_r15_entries[0],
364 1
365 };
366
367
368 /* The hardware table. */
369
370 #define HW_ENT(n) fr30_cgen_hw_entries[n]
371 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
372 {
373 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
374 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
375 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
376 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
377 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
378 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
379 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
380 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0, { 0 } } },
381 { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
382 { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
383 { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
384 { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
385 { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
386 { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
387 { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
388 { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
389 { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
390 { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
391 { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
392 { HW_H_CCR, & HW_ENT (HW_H_CCR + 1), "h-ccr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
393 { 0 }
394 };
395
396 /* The instruction field table. */
397
398 static const CGEN_IFLD fr30_cgen_ifld_table[] =
399 {
400 { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, 0, { 0 } } },
401 { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
402 { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
403 { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
404 { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
405 { FR30_F_OP5, "f-op5", 0, 16, 5, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
406 { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
407 { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
408 { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
409 { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
410 { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
411 { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
412 { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
413 { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
414 { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
415 { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
416 { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
417 { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
418 { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
419 { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
420 { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
421 { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
422 { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
423 { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
424 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
425 { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
426 { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
427 { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
428 { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
429 { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
430 { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
431 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
432 { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
433 { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
434 { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
435 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
436 { FR30_F_REGLIST_HI, "f-reglist_hi", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
437 { FR30_F_REGLIST_LOW, "f-reglist_low", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
438 { 0 }
439 };
440
441 /* The operand table. */
442
443 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
444 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
445
446 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
447 {
448 /* pc: program counter */
449 { "pc", & HW_ENT (HW_H_PC), 0, 0,
450 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
451 /* Ri: destination register */
452 { "Ri", & HW_ENT (HW_H_GR), 12, 4,
453 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
454 /* Rj: source register */
455 { "Rj", & HW_ENT (HW_H_GR), 8, 4,
456 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
457 /* Ric: target register coproc insn */
458 { "Ric", & HW_ENT (HW_H_GR), 12, 4,
459 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
460 /* Rjc: source register coproc insn */
461 { "Rjc", & HW_ENT (HW_H_GR), 8, 4,
462 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
463 /* CRi: coprocessor register */
464 { "CRi", & HW_ENT (HW_H_CR), 12, 4,
465 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
466 /* CRj: coprocessor register */
467 { "CRj", & HW_ENT (HW_H_CR), 8, 4,
468 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
469 /* Rs1: dedicated register */
470 { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
471 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
472 /* Rs2: dedicated register */
473 { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
474 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
475 /* R13: General Register 13 */
476 { "R13", & HW_ENT (HW_H_R13), 0, 0,
477 { 0, 0, { 0 } } },
478 /* R14: General Register 14 */
479 { "R14", & HW_ENT (HW_H_R14), 0, 0,
480 { 0, 0, { 0 } } },
481 /* R15: General Register 15 */
482 { "R15", & HW_ENT (HW_H_R15), 0, 0,
483 { 0, 0, { 0 } } },
484 /* ps: Program Status register */
485 { "ps", & HW_ENT (HW_H_PS), 0, 0,
486 { 0, 0, { 0 } } },
487 /* u4: 4 bit unsigned immediate */
488 { "u4", & HW_ENT (HW_H_UINT), 8, 4,
489 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
490 /* u4c: 4 bit unsigned immediate */
491 { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
492 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
493 /* u8: 8 bit unsigned immediate */
494 { "u8", & HW_ENT (HW_H_UINT), 8, 8,
495 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
496 /* i8: 8 bit unsigned immediate */
497 { "i8", & HW_ENT (HW_H_UINT), 4, 8,
498 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
499 /* udisp6: 6 bit unsigned immediate */
500 { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
501 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
502 /* disp8: 8 bit signed immediate */
503 { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
504 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
505 /* disp9: 9 bit signed immediate */
506 { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
507 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
508 /* disp10: 10 bit signed immediate */
509 { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
510 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
511 /* s10: 10 bit signed immediate */
512 { "s10", & HW_ENT (HW_H_SINT), 8, 8,
513 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
514 /* u10: 10 bit unsigned immediate */
515 { "u10", & HW_ENT (HW_H_UINT), 8, 8,
516 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
517 /* i32: 32 bit immediate */
518 { "i32", & HW_ENT (HW_H_UINT), 0, 32,
519 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
520 /* m4: 4 bit negative immediate */
521 { "m4", & HW_ENT (HW_H_SINT), 8, 4,
522 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
523 /* i20: 20 bit immediate */
524 { "i20", & HW_ENT (HW_H_UINT), 0, 20,
525 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), { 0 } } },
526 /* label9: 9 bit pc relative address */
527 { "label9", & HW_ENT (HW_H_IADDR), 8, 8,
528 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
529 /* dir8: 8 bit direct address */
530 { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
531 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
532 /* dir9: 9 bit direct address */
533 { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
534 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
535 /* dir10: 10 bit direct address */
536 { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
537 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
538 /* label12: 12 bit pc relative address */
539 { "label12", & HW_ENT (HW_H_IADDR), 5, 11,
540 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
541 /* reglist_low: 8 bit register mask */
542 { "reglist_low", & HW_ENT (HW_H_UINT), 8, 8,
543 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
544 /* reglist_hi: 8 bit register mask */
545 { "reglist_hi", & HW_ENT (HW_H_UINT), 8, 8,
546 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
547 /* cc: condition codes */
548 { "cc", & HW_ENT (HW_H_UINT), 4, 4,
549 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
550 /* ccc: coprocessor calc */
551 { "ccc", & HW_ENT (HW_H_UINT), 0, 8,
552 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
553 /* nbit: negative bit */
554 { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
555 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
556 /* vbit: overflow bit */
557 { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
558 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
559 /* zbit: zero bit */
560 { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
561 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
562 /* cbit: carry bit */
563 { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
564 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
565 /* ibit: interrupt bit */
566 { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
567 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
568 /* sbit: stack bit */
569 { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
570 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
571 /* ccr: condition code bits */
572 { "ccr", & HW_ENT (HW_H_CCR), 0, 0,
573 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
574 };
575
576 /* Operand references. */
577
578 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
579 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
580 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
581
582 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
583 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
584 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
585 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
586 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
587 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
588 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
589 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
590 { 0 }
591 };
592
593 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
594 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
595 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
596 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
597 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
598 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
599 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
600 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
601 { 0 }
602 };
603
604 static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
605 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
606 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
607 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
608 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
609 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
610 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
611 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
612 { 0 }
613 };
614
615 static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
616 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
617 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
618 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
619 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
620 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
621 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
622 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
623 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
624 { 0 }
625 };
626
627 static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
628 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
629 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
630 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
631 { 0 }
632 };
633
634 static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
635 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
636 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
637 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
638 { 0 }
639 };
640
641 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
642 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
643 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
644 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
645 { 0 }
646 };
647
648 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
649 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
650 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
651 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
652 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
653 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
654 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
655 { 0 }
656 };
657
658 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
659 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
660 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
661 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
662 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
663 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
664 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
665 { 0 }
666 };
667
668 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
669 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
670 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
671 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
672 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
673 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
674 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
675 { 0 }
676 };
677
678 static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
679 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
680 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
681 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
682 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
683 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
684 { 0 }
685 };
686
687 static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
688 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
689 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
690 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
691 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
692 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
693 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
694 { 0 }
695 };
696
697 static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
698 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
699 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
700 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
701 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
702 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
703 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
704 { 0 }
705 };
706
707 static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
708 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
709 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
710 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
711 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
712 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
713 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
714 { 0 }
715 };
716
717 static const CGEN_OPERAND_INSTANCE fmt_bandl_ops[] = {
718 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
719 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
720 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
721 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
722 { 0 }
723 };
724
725 static const CGEN_OPERAND_INSTANCE fmt_btstl_ops[] = {
726 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
727 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
728 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
729 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
730 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
731 { 0 }
732 };
733
734 static const CGEN_OPERAND_INSTANCE fmt_mul_ops[] = {
735 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
736 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
737 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
738 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
739 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
740 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
741 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
742 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
743 { 0 }
744 };
745
746 static const CGEN_OPERAND_INSTANCE fmt_mulu_ops[] = {
747 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
748 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
749 { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
750 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
751 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
752 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
753 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
754 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
755 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
756 { 0 }
757 };
758
759 static const CGEN_OPERAND_INSTANCE fmt_mulh_ops[] = {
760 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
761 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
762 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
763 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
764 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
765 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
766 { 0 }
767 };
768
769 static const CGEN_OPERAND_INSTANCE fmt_lsl_ops[] = {
770 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
771 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
772 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
773 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
774 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
775 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
776 { 0 }
777 };
778
779 static const CGEN_OPERAND_INSTANCE fmt_lsli_ops[] = {
780 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
781 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
782 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
783 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
784 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
785 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
786 { 0 }
787 };
788
789 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
790 { INPUT, "i8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I8), 0, 0 },
791 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
792 { 0 }
793 };
794
795 static const CGEN_OPERAND_INSTANCE fmt_ldi20_ops[] = {
796 { INPUT, "i20", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I20), 0, 0 },
797 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
798 { 0 }
799 };
800
801 static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
802 { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
803 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
804 { 0 }
805 };
806
807 static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
808 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
809 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
810 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
811 { 0 }
812 };
813
814 static const CGEN_OPERAND_INSTANCE fmt_lduh_ops[] = {
815 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
816 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
817 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
818 { 0 }
819 };
820
821 static const CGEN_OPERAND_INSTANCE fmt_ldub_ops[] = {
822 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
823 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
824 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
825 { 0 }
826 };
827
828 static const CGEN_OPERAND_INSTANCE fmt_ldr13_ops[] = {
829 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
830 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
831 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
832 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
833 { 0 }
834 };
835
836 static const CGEN_OPERAND_INSTANCE fmt_ldr13uh_ops[] = {
837 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
838 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
839 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
840 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
841 { 0 }
842 };
843
844 static const CGEN_OPERAND_INSTANCE fmt_ldr13ub_ops[] = {
845 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
846 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
847 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
848 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
849 { 0 }
850 };
851
852 static const CGEN_OPERAND_INSTANCE fmt_ldr14_ops[] = {
853 { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
854 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
855 { INPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
856 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
857 { 0 }
858 };
859
860 static const CGEN_OPERAND_INSTANCE fmt_ldr14uh_ops[] = {
861 { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
862 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
863 { INPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
864 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
865 { 0 }
866 };
867
868 static const CGEN_OPERAND_INSTANCE fmt_ldr14ub_ops[] = {
869 { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
870 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
871 { INPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
872 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
873 { 0 }
874 };
875
876 static const CGEN_OPERAND_INSTANCE fmt_ldr15_ops[] = {
877 { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
878 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
879 { INPUT, "h_memory_add__VM_udisp6_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
880 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
881 { 0 }
882 };
883
884 static const CGEN_OPERAND_INSTANCE fmt_ldr15gr_ops[] = {
885 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
886 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
887 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
888 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
889 { 0 }
890 };
891
892 static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
893 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
894 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
895 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
896 { 0 }
897 };
898
899 static const CGEN_OPERAND_INSTANCE fmt_mov_ops[] = {
900 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
901 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
902 { 0 }
903 };
904
905 static const CGEN_OPERAND_INSTANCE fmt_movdr_ops[] = {
906 { INPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
907 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
908 { 0 }
909 };
910
911 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
912 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
913 { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
914 { 0 }
915 };
916
917 static const CGEN_OPERAND_INSTANCE fmt_jmpd_ops[] = {
918 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
919 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
920 { 0 }
921 };
922
923 static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
924 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
925 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
926 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, 0 },
927 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
928 { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
929 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
930 { 0 }
931 };
932
933 static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
934 { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
935 { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
936 { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
937 { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
938 { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
939 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
940 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
941 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
942 { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
943 { 0 }
944 };
945
946 static const CGEN_OPERAND_INSTANCE fmt_bra_ops[] = {
947 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
948 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
949 { 0 }
950 };
951
952 static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
953 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
954 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
955 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
956 { 0 }
957 };
958
959 static const CGEN_OPERAND_INSTANCE fmt_bc_ops[] = {
960 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
961 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
962 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
963 { 0 }
964 };
965
966 static const CGEN_OPERAND_INSTANCE fmt_bn_ops[] = {
967 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
968 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
969 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
970 { 0 }
971 };
972
973 static const CGEN_OPERAND_INSTANCE fmt_bv_ops[] = {
974 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
975 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
976 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
977 { 0 }
978 };
979
980 static const CGEN_OPERAND_INSTANCE fmt_blt_ops[] = {
981 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
982 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
983 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
984 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
985 { 0 }
986 };
987
988 static const CGEN_OPERAND_INSTANCE fmt_ble_ops[] = {
989 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
990 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
991 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
992 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
993 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
994 { 0 }
995 };
996
997 static const CGEN_OPERAND_INSTANCE fmt_bls_ops[] = {
998 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
999 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1000 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1001 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1002 { 0 }
1003 };
1004
1005 static const CGEN_OPERAND_INSTANCE fmt_andccr_ops[] = {
1006 { INPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
1007 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U8), 0, 0 },
1008 { OUTPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
1009 { 0 }
1010 };
1011
1012 #undef INPUT
1013 #undef OUTPUT
1014 #undef COND_REF
1015
1016 /* Instruction formats. */
1017
1018 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
1019
1020 static const CGEN_IFMT fmt_add = {
1021 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1022 };
1023
1024 static const CGEN_IFMT fmt_addi = {
1025 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1026 };
1027
1028 static const CGEN_IFMT fmt_add2 = {
1029 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1030 };
1031
1032 static const CGEN_IFMT fmt_addc = {
1033 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1034 };
1035
1036 static const CGEN_IFMT fmt_addn = {
1037 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1038 };
1039
1040 static const CGEN_IFMT fmt_addni = {
1041 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1042 };
1043
1044 static const CGEN_IFMT fmt_addn2 = {
1045 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1046 };
1047
1048 static const CGEN_IFMT fmt_cmp = {
1049 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1050 };
1051
1052 static const CGEN_IFMT fmt_cmpi = {
1053 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1054 };
1055
1056 static const CGEN_IFMT fmt_cmp2 = {
1057 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1058 };
1059
1060 static const CGEN_IFMT fmt_and = {
1061 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1062 };
1063
1064 static const CGEN_IFMT fmt_andm = {
1065 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1066 };
1067
1068 static const CGEN_IFMT fmt_andh = {
1069 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1070 };
1071
1072 static const CGEN_IFMT fmt_andb = {
1073 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1074 };
1075
1076 static const CGEN_IFMT fmt_bandl = {
1077 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1078 };
1079
1080 static const CGEN_IFMT fmt_btstl = {
1081 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1082 };
1083
1084 static const CGEN_IFMT fmt_mul = {
1085 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1086 };
1087
1088 static const CGEN_IFMT fmt_mulu = {
1089 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1090 };
1091
1092 static const CGEN_IFMT fmt_mulh = {
1093 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1094 };
1095
1096 static const CGEN_IFMT fmt_div0s = {
1097 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1098 };
1099
1100 static const CGEN_IFMT fmt_div3 = {
1101 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1102 };
1103
1104 static const CGEN_IFMT fmt_lsl = {
1105 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1106 };
1107
1108 static const CGEN_IFMT fmt_lsli = {
1109 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1110 };
1111
1112 static const CGEN_IFMT fmt_ldi8 = {
1113 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
1114 };
1115
1116 static const CGEN_IFMT fmt_ldi20 = {
1117 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
1118 };
1119
1120 static const CGEN_IFMT fmt_ldi32 = {
1121 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1122 };
1123
1124 static const CGEN_IFMT fmt_ld = {
1125 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1126 };
1127
1128 static const CGEN_IFMT fmt_lduh = {
1129 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1130 };
1131
1132 static const CGEN_IFMT fmt_ldub = {
1133 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1134 };
1135
1136 static const CGEN_IFMT fmt_ldr13 = {
1137 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1138 };
1139
1140 static const CGEN_IFMT fmt_ldr13uh = {
1141 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1142 };
1143
1144 static const CGEN_IFMT fmt_ldr13ub = {
1145 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1146 };
1147
1148 static const CGEN_IFMT fmt_ldr14 = {
1149 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
1150 };
1151
1152 static const CGEN_IFMT fmt_ldr14uh = {
1153 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
1154 };
1155
1156 static const CGEN_IFMT fmt_ldr14ub = {
1157 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
1158 };
1159
1160 static const CGEN_IFMT fmt_ldr15 = {
1161 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
1162 };
1163
1164 static const CGEN_IFMT fmt_ldr15gr = {
1165 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1166 };
1167
1168 static const CGEN_IFMT fmt_ldr15dr = {
1169 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
1170 };
1171
1172 static const CGEN_IFMT fmt_st = {
1173 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1174 };
1175
1176 static const CGEN_IFMT fmt_sth = {
1177 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1178 };
1179
1180 static const CGEN_IFMT fmt_str14 = {
1181 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
1182 };
1183
1184 static const CGEN_IFMT fmt_str14h = {
1185 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
1186 };
1187
1188 static const CGEN_IFMT fmt_str14b = {
1189 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
1190 };
1191
1192 static const CGEN_IFMT fmt_str15 = {
1193 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
1194 };
1195
1196 static const CGEN_IFMT fmt_mov = {
1197 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1198 };
1199
1200 static const CGEN_IFMT fmt_movdr = {
1201 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
1202 };
1203
1204 static const CGEN_IFMT fmt_mov2dr = {
1205 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
1206 };
1207
1208 static const CGEN_IFMT fmt_jmpd = {
1209 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1210 };
1211
1212 static const CGEN_IFMT fmt_call = {
1213 16, 16, 0xf400, { F (F_OP1), F (F_OP5), F (F_REL12), 0 }
1214 };
1215
1216 static const CGEN_IFMT fmt_int = {
1217 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1218 };
1219
1220 static const CGEN_IFMT fmt_reti = {
1221 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1222 };
1223
1224 static const CGEN_IFMT fmt_bra = {
1225 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1226 };
1227
1228 static const CGEN_IFMT fmt_beq = {
1229 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1230 };
1231
1232 static const CGEN_IFMT fmt_bc = {
1233 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1234 };
1235
1236 static const CGEN_IFMT fmt_bn = {
1237 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1238 };
1239
1240 static const CGEN_IFMT fmt_bv = {
1241 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1242 };
1243
1244 static const CGEN_IFMT fmt_blt = {
1245 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1246 };
1247
1248 static const CGEN_IFMT fmt_ble = {
1249 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1250 };
1251
1252 static const CGEN_IFMT fmt_bls = {
1253 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1254 };
1255
1256 static const CGEN_IFMT fmt_dmovr13 = {
1257 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1258 };
1259
1260 static const CGEN_IFMT fmt_dmovr13h = {
1261 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1262 };
1263
1264 static const CGEN_IFMT fmt_dmovr13b = {
1265 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1266 };
1267
1268 static const CGEN_IFMT fmt_ldres = {
1269 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1270 };
1271
1272 static const CGEN_IFMT fmt_copop = {
1273 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_CRI), 0 }
1274 };
1275
1276 static const CGEN_IFMT fmt_copld = {
1277 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_RJC), F (F_U4C), F (F_CRI), 0 }
1278 };
1279
1280 static const CGEN_IFMT fmt_copst = {
1281 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_RIC), 0 }
1282 };
1283
1284 static const CGEN_IFMT fmt_andccr = {
1285 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1286 };
1287
1288 static const CGEN_IFMT fmt_stilm = {
1289 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1290 };
1291
1292 static const CGEN_IFMT fmt_addsp = {
1293 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_S10), 0 }
1294 };
1295
1296 static const CGEN_IFMT fmt_ldm0 = {
1297 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW), 0 }
1298 };
1299
1300 static const CGEN_IFMT fmt_ldm1 = {
1301 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI), 0 }
1302 };
1303
1304 static const CGEN_IFMT fmt_enter = {
1305 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U10), 0 }
1306 };
1307
1308 #undef F
1309
1310 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1311 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1312 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1313
1314 /* The instruction table.
1315 This is currently non-static because the simulator accesses it
1316 directly. */
1317
1318 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
1319 {
1320 /* Special null first entry.
1321 A `num' value of zero is thus invalid.
1322 Also, the special `invalid' insn resides here. */
1323 { { 0 }, 0 },
1324 /* add $Rj,$Ri */
1325 {
1326 { 1, 1, 1, 1 },
1327 FR30_INSN_ADD, "add", "add",
1328 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1329 & fmt_add, { 0xa600 },
1330 (PTR) & fmt_add_ops[0],
1331 { 0, 0, { 0 } }
1332 },
1333 /* add $u4,$Ri */
1334 {
1335 { 1, 1, 1, 1 },
1336 FR30_INSN_ADDI, "addi", "add",
1337 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1338 & fmt_addi, { 0xa400 },
1339 (PTR) & fmt_addi_ops[0],
1340 { 0, 0, { 0 } }
1341 },
1342 /* add2 $m4,$Ri */
1343 {
1344 { 1, 1, 1, 1 },
1345 FR30_INSN_ADD2, "add2", "add2",
1346 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1347 & fmt_add2, { 0xa500 },
1348 (PTR) & fmt_add2_ops[0],
1349 { 0, 0, { 0 } }
1350 },
1351 /* addc $Rj,$Ri */
1352 {
1353 { 1, 1, 1, 1 },
1354 FR30_INSN_ADDC, "addc", "addc",
1355 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1356 & fmt_addc, { 0xa700 },
1357 (PTR) & fmt_addc_ops[0],
1358 { 0, 0, { 0 } }
1359 },
1360 /* addn $Rj,$Ri */
1361 {
1362 { 1, 1, 1, 1 },
1363 FR30_INSN_ADDN, "addn", "addn",
1364 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1365 & fmt_addn, { 0xa200 },
1366 (PTR) & fmt_addn_ops[0],
1367 { 0, 0, { 0 } }
1368 },
1369 /* addn $u4,$Ri */
1370 {
1371 { 1, 1, 1, 1 },
1372 FR30_INSN_ADDNI, "addni", "addn",
1373 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1374 & fmt_addni, { 0xa000 },
1375 (PTR) & fmt_addni_ops[0],
1376 { 0, 0, { 0 } }
1377 },
1378 /* addn2 $m4,$Ri */
1379 {
1380 { 1, 1, 1, 1 },
1381 FR30_INSN_ADDN2, "addn2", "addn2",
1382 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1383 & fmt_addn2, { 0xa100 },
1384 (PTR) & fmt_addn2_ops[0],
1385 { 0, 0, { 0 } }
1386 },
1387 /* sub $Rj,$Ri */
1388 {
1389 { 1, 1, 1, 1 },
1390 FR30_INSN_SUB, "sub", "sub",
1391 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1392 & fmt_add, { 0xac00 },
1393 (PTR) & fmt_add_ops[0],
1394 { 0, 0, { 0 } }
1395 },
1396 /* subc $Rj,$Ri */
1397 {
1398 { 1, 1, 1, 1 },
1399 FR30_INSN_SUBC, "subc", "subc",
1400 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1401 & fmt_addc, { 0xad00 },
1402 (PTR) & fmt_addc_ops[0],
1403 { 0, 0, { 0 } }
1404 },
1405 /* subn $Rj,$Ri */
1406 {
1407 { 1, 1, 1, 1 },
1408 FR30_INSN_SUBN, "subn", "subn",
1409 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1410 & fmt_addn, { 0xae00 },
1411 (PTR) & fmt_addn_ops[0],
1412 { 0, 0, { 0 } }
1413 },
1414 /* cmp $Rj,$Ri */
1415 {
1416 { 1, 1, 1, 1 },
1417 FR30_INSN_CMP, "cmp", "cmp",
1418 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1419 & fmt_cmp, { 0xaa00 },
1420 (PTR) & fmt_cmp_ops[0],
1421 { 0, 0, { 0 } }
1422 },
1423 /* cmp $u4,$Ri */
1424 {
1425 { 1, 1, 1, 1 },
1426 FR30_INSN_CMPI, "cmpi", "cmp",
1427 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1428 & fmt_cmpi, { 0xa800 },
1429 (PTR) & fmt_cmpi_ops[0],
1430 { 0, 0, { 0 } }
1431 },
1432 /* cmp2 $m4,$Ri */
1433 {
1434 { 1, 1, 1, 1 },
1435 FR30_INSN_CMP2, "cmp2", "cmp2",
1436 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1437 & fmt_cmp2, { 0xa900 },
1438 (PTR) & fmt_cmp2_ops[0],
1439 { 0, 0, { 0 } }
1440 },
1441 /* and $Rj,$Ri */
1442 {
1443 { 1, 1, 1, 1 },
1444 FR30_INSN_AND, "and", "and",
1445 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1446 & fmt_and, { 0x8200 },
1447 (PTR) & fmt_and_ops[0],
1448 { 0, 0, { 0 } }
1449 },
1450 /* or $Rj,$Ri */
1451 {
1452 { 1, 1, 1, 1 },
1453 FR30_INSN_OR, "or", "or",
1454 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1455 & fmt_and, { 0x9200 },
1456 (PTR) & fmt_and_ops[0],
1457 { 0, 0, { 0 } }
1458 },
1459 /* eor $Rj,$Ri */
1460 {
1461 { 1, 1, 1, 1 },
1462 FR30_INSN_EOR, "eor", "eor",
1463 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1464 & fmt_and, { 0x9a00 },
1465 (PTR) & fmt_and_ops[0],
1466 { 0, 0, { 0 } }
1467 },
1468 /* and $Rj,@$Ri */
1469 {
1470 { 1, 1, 1, 1 },
1471 FR30_INSN_ANDM, "andm", "and",
1472 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1473 & fmt_andm, { 0x8400 },
1474 (PTR) & fmt_andm_ops[0],
1475 { 0, 0, { 0 } }
1476 },
1477 /* andh $Rj,@$Ri */
1478 {
1479 { 1, 1, 1, 1 },
1480 FR30_INSN_ANDH, "andh", "andh",
1481 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1482 & fmt_andh, { 0x8500 },
1483 (PTR) & fmt_andh_ops[0],
1484 { 0, 0, { 0 } }
1485 },
1486 /* andb $Rj,@$Ri */
1487 {
1488 { 1, 1, 1, 1 },
1489 FR30_INSN_ANDB, "andb", "andb",
1490 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1491 & fmt_andb, { 0x8600 },
1492 (PTR) & fmt_andb_ops[0],
1493 { 0, 0, { 0 } }
1494 },
1495 /* or $Rj,@$Ri */
1496 {
1497 { 1, 1, 1, 1 },
1498 FR30_INSN_ORM, "orm", "or",
1499 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1500 & fmt_andm, { 0x9400 },
1501 (PTR) & fmt_andm_ops[0],
1502 { 0, 0, { 0 } }
1503 },
1504 /* orh $Rj,@$Ri */
1505 {
1506 { 1, 1, 1, 1 },
1507 FR30_INSN_ORH, "orh", "orh",
1508 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1509 & fmt_andh, { 0x9500 },
1510 (PTR) & fmt_andh_ops[0],
1511 { 0, 0, { 0 } }
1512 },
1513 /* orb $Rj,@$Ri */
1514 {
1515 { 1, 1, 1, 1 },
1516 FR30_INSN_ORB, "orb", "orb",
1517 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1518 & fmt_andb, { 0x9600 },
1519 (PTR) & fmt_andb_ops[0],
1520 { 0, 0, { 0 } }
1521 },
1522 /* eor $Rj,@$Ri */
1523 {
1524 { 1, 1, 1, 1 },
1525 FR30_INSN_EORM, "eorm", "eor",
1526 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1527 & fmt_andm, { 0x9c00 },
1528 (PTR) & fmt_andm_ops[0],
1529 { 0, 0, { 0 } }
1530 },
1531 /* eorh $Rj,@$Ri */
1532 {
1533 { 1, 1, 1, 1 },
1534 FR30_INSN_EORH, "eorh", "eorh",
1535 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1536 & fmt_andh, { 0x9d00 },
1537 (PTR) & fmt_andh_ops[0],
1538 { 0, 0, { 0 } }
1539 },
1540 /* eorb $Rj,@$Ri */
1541 {
1542 { 1, 1, 1, 1 },
1543 FR30_INSN_EORB, "eorb", "eorb",
1544 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1545 & fmt_andb, { 0x9e00 },
1546 (PTR) & fmt_andb_ops[0],
1547 { 0, 0, { 0 } }
1548 },
1549 /* bandl $u4,@$Ri */
1550 {
1551 { 1, 1, 1, 1 },
1552 FR30_INSN_BANDL, "bandl", "bandl",
1553 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1554 & fmt_bandl, { 0x8000 },
1555 (PTR) & fmt_bandl_ops[0],
1556 { 0, 0, { 0 } }
1557 },
1558 /* borl $u4,@$Ri */
1559 {
1560 { 1, 1, 1, 1 },
1561 FR30_INSN_BORL, "borl", "borl",
1562 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1563 & fmt_bandl, { 0x9000 },
1564 (PTR) & fmt_bandl_ops[0],
1565 { 0, 0, { 0 } }
1566 },
1567 /* beorl $u4,@$Ri */
1568 {
1569 { 1, 1, 1, 1 },
1570 FR30_INSN_BEORL, "beorl", "beorl",
1571 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1572 & fmt_bandl, { 0x9800 },
1573 (PTR) & fmt_bandl_ops[0],
1574 { 0, 0, { 0 } }
1575 },
1576 /* bandh $u4,@$Ri */
1577 {
1578 { 1, 1, 1, 1 },
1579 FR30_INSN_BANDH, "bandh", "bandh",
1580 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1581 & fmt_bandl, { 0x8100 },
1582 (PTR) & fmt_bandl_ops[0],
1583 { 0, 0, { 0 } }
1584 },
1585 /* borh $u4,@$Ri */
1586 {
1587 { 1, 1, 1, 1 },
1588 FR30_INSN_BORH, "borh", "borh",
1589 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1590 & fmt_bandl, { 0x9100 },
1591 (PTR) & fmt_bandl_ops[0],
1592 { 0, 0, { 0 } }
1593 },
1594 /* beorh $u4,@$Ri */
1595 {
1596 { 1, 1, 1, 1 },
1597 FR30_INSN_BEORH, "beorh", "beorh",
1598 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1599 & fmt_bandl, { 0x9900 },
1600 (PTR) & fmt_bandl_ops[0],
1601 { 0, 0, { 0 } }
1602 },
1603 /* btstl $u4,@$Ri */
1604 {
1605 { 1, 1, 1, 1 },
1606 FR30_INSN_BTSTL, "btstl", "btstl",
1607 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1608 & fmt_btstl, { 0x8800 },
1609 (PTR) & fmt_btstl_ops[0],
1610 { 0, 0, { 0 } }
1611 },
1612 /* btsth $u4,@$Ri */
1613 {
1614 { 1, 1, 1, 1 },
1615 FR30_INSN_BTSTH, "btsth", "btsth",
1616 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1617 & fmt_btstl, { 0x8900 },
1618 (PTR) & fmt_btstl_ops[0],
1619 { 0, 0, { 0 } }
1620 },
1621 /* mul $Rj,$Ri */
1622 {
1623 { 1, 1, 1, 1 },
1624 FR30_INSN_MUL, "mul", "mul",
1625 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1626 & fmt_mul, { 0xaf00 },
1627 (PTR) & fmt_mul_ops[0],
1628 { 0, 0, { 0 } }
1629 },
1630 /* mulu $Rj,$Ri */
1631 {
1632 { 1, 1, 1, 1 },
1633 FR30_INSN_MULU, "mulu", "mulu",
1634 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1635 & fmt_mulu, { 0xab00 },
1636 (PTR) & fmt_mulu_ops[0],
1637 { 0, 0, { 0 } }
1638 },
1639 /* mulh $Rj,$Ri */
1640 {
1641 { 1, 1, 1, 1 },
1642 FR30_INSN_MULH, "mulh", "mulh",
1643 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1644 & fmt_mulh, { 0xbf00 },
1645 (PTR) & fmt_mulh_ops[0],
1646 { 0, 0, { 0 } }
1647 },
1648 /* muluh $Rj,$Ri */
1649 {
1650 { 1, 1, 1, 1 },
1651 FR30_INSN_MULUH, "muluh", "muluh",
1652 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1653 & fmt_mulh, { 0xbb00 },
1654 (PTR) & fmt_mulh_ops[0],
1655 { 0, 0, { 0 } }
1656 },
1657 /* div0s $Ri */
1658 {
1659 { 1, 1, 1, 1 },
1660 FR30_INSN_DIV0S, "div0s", "div0s",
1661 { { MNEM, ' ', OP (RI), 0 } },
1662 & fmt_div0s, { 0x9740 },
1663 (PTR) 0,
1664 { 0, 0, { 0 } }
1665 },
1666 /* div0u $Ri */
1667 {
1668 { 1, 1, 1, 1 },
1669 FR30_INSN_DIV0U, "div0u", "div0u",
1670 { { MNEM, ' ', OP (RI), 0 } },
1671 & fmt_div0s, { 0x9750 },
1672 (PTR) 0,
1673 { 0, 0, { 0 } }
1674 },
1675 /* div1 $Ri */
1676 {
1677 { 1, 1, 1, 1 },
1678 FR30_INSN_DIV1, "div1", "div1",
1679 { { MNEM, ' ', OP (RI), 0 } },
1680 & fmt_div0s, { 0x9760 },
1681 (PTR) 0,
1682 { 0, 0, { 0 } }
1683 },
1684 /* div2 $Ri */
1685 {
1686 { 1, 1, 1, 1 },
1687 FR30_INSN_DIV2, "div2", "div2",
1688 { { MNEM, ' ', OP (RI), 0 } },
1689 & fmt_div0s, { 0x9770 },
1690 (PTR) 0,
1691 { 0, 0, { 0 } }
1692 },
1693 /* div3 */
1694 {
1695 { 1, 1, 1, 1 },
1696 FR30_INSN_DIV3, "div3", "div3",
1697 { { MNEM, 0 } },
1698 & fmt_div3, { 0x9f60 },
1699 (PTR) 0,
1700 { 0, 0, { 0 } }
1701 },
1702 /* div4s */
1703 {
1704 { 1, 1, 1, 1 },
1705 FR30_INSN_DIV4S, "div4s", "div4s",
1706 { { MNEM, 0 } },
1707 & fmt_div3, { 0x9f70 },
1708 (PTR) 0,
1709 { 0, 0, { 0 } }
1710 },
1711 /* lsl $Rj,$Ri */
1712 {
1713 { 1, 1, 1, 1 },
1714 FR30_INSN_LSL, "lsl", "lsl",
1715 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1716 & fmt_lsl, { 0xb600 },
1717 (PTR) & fmt_lsl_ops[0],
1718 { 0, 0, { 0 } }
1719 },
1720 /* lsl $u4,$Ri */
1721 {
1722 { 1, 1, 1, 1 },
1723 FR30_INSN_LSLI, "lsli", "lsl",
1724 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1725 & fmt_lsli, { 0xb400 },
1726 (PTR) & fmt_lsli_ops[0],
1727 { 0, 0, { 0 } }
1728 },
1729 /* lsl2 $u4,$Ri */
1730 {
1731 { 1, 1, 1, 1 },
1732 FR30_INSN_LSL2, "lsl2", "lsl2",
1733 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1734 & fmt_lsli, { 0xb500 },
1735 (PTR) & fmt_lsli_ops[0],
1736 { 0, 0, { 0 } }
1737 },
1738 /* lsr $Rj,$Ri */
1739 {
1740 { 1, 1, 1, 1 },
1741 FR30_INSN_LSR, "lsr", "lsr",
1742 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1743 & fmt_lsl, { 0xb200 },
1744 (PTR) & fmt_lsl_ops[0],
1745 { 0, 0, { 0 } }
1746 },
1747 /* lsr $u4,$Ri */
1748 {
1749 { 1, 1, 1, 1 },
1750 FR30_INSN_LSRI, "lsri", "lsr",
1751 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1752 & fmt_lsli, { 0xb000 },
1753 (PTR) & fmt_lsli_ops[0],
1754 { 0, 0, { 0 } }
1755 },
1756 /* lsr2 $u4,$Ri */
1757 {
1758 { 1, 1, 1, 1 },
1759 FR30_INSN_LSR2, "lsr2", "lsr2",
1760 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1761 & fmt_lsli, { 0xb100 },
1762 (PTR) & fmt_lsli_ops[0],
1763 { 0, 0, { 0 } }
1764 },
1765 /* asr $Rj,$Ri */
1766 {
1767 { 1, 1, 1, 1 },
1768 FR30_INSN_ASR, "asr", "asr",
1769 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1770 & fmt_lsl, { 0xba00 },
1771 (PTR) & fmt_lsl_ops[0],
1772 { 0, 0, { 0 } }
1773 },
1774 /* asr $u4,$Ri */
1775 {
1776 { 1, 1, 1, 1 },
1777 FR30_INSN_ASRI, "asri", "asr",
1778 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1779 & fmt_lsli, { 0xb800 },
1780 (PTR) & fmt_lsli_ops[0],
1781 { 0, 0, { 0 } }
1782 },
1783 /* asr2 $u4,$Ri */
1784 {
1785 { 1, 1, 1, 1 },
1786 FR30_INSN_ASR2, "asr2", "asr2",
1787 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1788 & fmt_lsli, { 0xb900 },
1789 (PTR) & fmt_lsli_ops[0],
1790 { 0, 0, { 0 } }
1791 },
1792 /* ldi:8 $i8,$Ri */
1793 {
1794 { 1, 1, 1, 1 },
1795 FR30_INSN_LDI8, "ldi8", "ldi:8",
1796 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
1797 & fmt_ldi8, { 0xc000 },
1798 (PTR) & fmt_ldi8_ops[0],
1799 { 0, 0, { 0 } }
1800 },
1801 /* ldi:20 $i20,$Ri */
1802 {
1803 { 1, 1, 1, 1 },
1804 FR30_INSN_LDI20, "ldi20", "ldi:20",
1805 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
1806 & fmt_ldi20, { 0x9b00 },
1807 (PTR) & fmt_ldi20_ops[0],
1808 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
1809 },
1810 /* ldi:32 $i32,$Ri */
1811 {
1812 { 1, 1, 1, 1 },
1813 FR30_INSN_LDI32, "ldi32", "ldi:32",
1814 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
1815 & fmt_ldi32, { 0x9f80 },
1816 (PTR) & fmt_ldi32_ops[0],
1817 { 0, 0, { 0 } }
1818 },
1819 /* ld @$Rj,$Ri */
1820 {
1821 { 1, 1, 1, 1 },
1822 FR30_INSN_LD, "ld", "ld",
1823 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1824 & fmt_ld, { 0x400 },
1825 (PTR) & fmt_ld_ops[0],
1826 { 0, 0, { 0 } }
1827 },
1828 /* lduh @$Rj,$Ri */
1829 {
1830 { 1, 1, 1, 1 },
1831 FR30_INSN_LDUH, "lduh", "lduh",
1832 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1833 & fmt_lduh, { 0x500 },
1834 (PTR) & fmt_lduh_ops[0],
1835 { 0, 0, { 0 } }
1836 },
1837 /* ldub @$Rj,$Ri */
1838 {
1839 { 1, 1, 1, 1 },
1840 FR30_INSN_LDUB, "ldub", "ldub",
1841 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1842 & fmt_ldub, { 0x600 },
1843 (PTR) & fmt_ldub_ops[0],
1844 { 0, 0, { 0 } }
1845 },
1846 /* ld @($R13,$Rj),$Ri */
1847 {
1848 { 1, 1, 1, 1 },
1849 FR30_INSN_LDR13, "ldr13", "ld",
1850 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1851 & fmt_ldr13, { 0x0 },
1852 (PTR) & fmt_ldr13_ops[0],
1853 { 0, 0, { 0 } }
1854 },
1855 /* lduh @($R13,$Rj),$Ri */
1856 {
1857 { 1, 1, 1, 1 },
1858 FR30_INSN_LDR13UH, "ldr13uh", "lduh",
1859 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1860 & fmt_ldr13uh, { 0x100 },
1861 (PTR) & fmt_ldr13uh_ops[0],
1862 { 0, 0, { 0 } }
1863 },
1864 /* ldub @($R13,$Rj),$Ri */
1865 {
1866 { 1, 1, 1, 1 },
1867 FR30_INSN_LDR13UB, "ldr13ub", "ldub",
1868 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1869 & fmt_ldr13ub, { 0x200 },
1870 (PTR) & fmt_ldr13ub_ops[0],
1871 { 0, 0, { 0 } }
1872 },
1873 /* ld @($R14,$disp10),$Ri */
1874 {
1875 { 1, 1, 1, 1 },
1876 FR30_INSN_LDR14, "ldr14", "ld",
1877 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
1878 & fmt_ldr14, { 0x2000 },
1879 (PTR) & fmt_ldr14_ops[0],
1880 { 0, 0, { 0 } }
1881 },
1882 /* lduh @($R14,$disp9),$Ri */
1883 {
1884 { 1, 1, 1, 1 },
1885 FR30_INSN_LDR14UH, "ldr14uh", "lduh",
1886 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
1887 & fmt_ldr14uh, { 0x4000 },
1888 (PTR) & fmt_ldr14uh_ops[0],
1889 { 0, 0, { 0 } }
1890 },
1891 /* ldub @($R14,$disp8),$Ri */
1892 {
1893 { 1, 1, 1, 1 },
1894 FR30_INSN_LDR14UB, "ldr14ub", "ldub",
1895 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
1896 & fmt_ldr14ub, { 0x6000 },
1897 (PTR) & fmt_ldr14ub_ops[0],
1898 { 0, 0, { 0 } }
1899 },
1900 /* ld @($R15,$udisp6),$Ri */
1901 {
1902 { 1, 1, 1, 1 },
1903 FR30_INSN_LDR15, "ldr15", "ld",
1904 { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
1905 & fmt_ldr15, { 0x300 },
1906 (PTR) & fmt_ldr15_ops[0],
1907 { 0, 0, { 0 } }
1908 },
1909 /* ld @$R15+,$Ri */
1910 {
1911 { 1, 1, 1, 1 },
1912 FR30_INSN_LDR15GR, "ldr15gr", "ld",
1913 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
1914 & fmt_ldr15gr, { 0x700 },
1915 (PTR) & fmt_ldr15gr_ops[0],
1916 { 0, 0, { 0 } }
1917 },
1918 /* ld @$R15+,$Rs2 */
1919 {
1920 { 1, 1, 1, 1 },
1921 FR30_INSN_LDR15DR, "ldr15dr", "ld",
1922 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
1923 & fmt_ldr15dr, { 0x780 },
1924 (PTR) 0,
1925 { 0, 0, { 0 } }
1926 },
1927 /* ld @$R15+,$ps */
1928 {
1929 { 1, 1, 1, 1 },
1930 FR30_INSN_LDR15PS, "ldr15ps", "ld",
1931 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
1932 & fmt_div3, { 0x790 },
1933 (PTR) 0,
1934 { 0, 0, { 0 } }
1935 },
1936 /* st $Ri,@$Rj */
1937 {
1938 { 1, 1, 1, 1 },
1939 FR30_INSN_ST, "st", "st",
1940 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1941 & fmt_st, { 0x1400 },
1942 (PTR) & fmt_st_ops[0],
1943 { 0, 0, { 0 } }
1944 },
1945 /* sth $Ri,@$Rj */
1946 {
1947 { 1, 1, 1, 1 },
1948 FR30_INSN_STH, "sth", "sth",
1949 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1950 & fmt_sth, { 0x1500 },
1951 (PTR) 0,
1952 { 0, 0, { 0 } }
1953 },
1954 /* stb $Ri,@$Rj */
1955 {
1956 { 1, 1, 1, 1 },
1957 FR30_INSN_STB, "stb", "stb",
1958 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1959 & fmt_sth, { 0x1600 },
1960 (PTR) 0,
1961 { 0, 0, { 0 } }
1962 },
1963 /* st $Ri,@($R13,$Rj) */
1964 {
1965 { 1, 1, 1, 1 },
1966 FR30_INSN_STR13, "str13", "st",
1967 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1968 & fmt_sth, { 0x1000 },
1969 (PTR) 0,
1970 { 0, 0, { 0 } }
1971 },
1972 /* sth $Ri,@($R13,$Rj) */
1973 {
1974 { 1, 1, 1, 1 },
1975 FR30_INSN_STR13H, "str13h", "sth",
1976 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1977 & fmt_sth, { 0x1100 },
1978 (PTR) 0,
1979 { 0, 0, { 0 } }
1980 },
1981 /* stb $Ri,@($R13,$Rj) */
1982 {
1983 { 1, 1, 1, 1 },
1984 FR30_INSN_STR13B, "stR13b", "stb",
1985 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1986 & fmt_sth, { 0x1200 },
1987 (PTR) 0,
1988 { 0, 0, { 0 } }
1989 },
1990 /* st $Ri,@($R14,$disp10) */
1991 {
1992 { 1, 1, 1, 1 },
1993 FR30_INSN_STR14, "str14", "st",
1994 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
1995 & fmt_str14, { 0x3000 },
1996 (PTR) 0,
1997 { 0, 0, { 0 } }
1998 },
1999 /* sth $Ri,@($R14,$disp9) */
2000 {
2001 { 1, 1, 1, 1 },
2002 FR30_INSN_STR14H, "str14h", "sth",
2003 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
2004 & fmt_str14h, { 0x5000 },
2005 (PTR) 0,
2006 { 0, 0, { 0 } }
2007 },
2008 /* stb $Ri,@($R14,$disp8) */
2009 {
2010 { 1, 1, 1, 1 },
2011 FR30_INSN_STR14B, "str14b", "stb",
2012 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
2013 & fmt_str14b, { 0x7000 },
2014 (PTR) 0,
2015 { 0, 0, { 0 } }
2016 },
2017 /* st $Ri,@($R15,$udisp6) */
2018 {
2019 { 1, 1, 1, 1 },
2020 FR30_INSN_STR15, "str15", "st",
2021 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
2022 & fmt_str15, { 0x1300 },
2023 (PTR) 0,
2024 { 0, 0, { 0 } }
2025 },
2026 /* st $Ri,@-$R15 */
2027 {
2028 { 1, 1, 1, 1 },
2029 FR30_INSN_STR15GR, "str15gr", "st",
2030 { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
2031 & fmt_div0s, { 0x1700 },
2032 (PTR) 0,
2033 { 0, 0, { 0 } }
2034 },
2035 /* st $Rs2,@-$R15 */
2036 {
2037 { 1, 1, 1, 1 },
2038 FR30_INSN_STR15DR, "str15dr", "st",
2039 { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
2040 & fmt_ldr15dr, { 0x1780 },
2041 (PTR) 0,
2042 { 0, 0, { 0 } }
2043 },
2044 /* st $ps,@-$R15 */
2045 {
2046 { 1, 1, 1, 1 },
2047 FR30_INSN_STR15PS, "str15ps", "st",
2048 { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
2049 & fmt_div3, { 0x1790 },
2050 (PTR) 0,
2051 { 0, 0, { 0 } }
2052 },
2053 /* mov $Rj,$Ri */
2054 {
2055 { 1, 1, 1, 1 },
2056 FR30_INSN_MOV, "mov", "mov",
2057 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2058 & fmt_mov, { 0x8b00 },
2059 (PTR) & fmt_mov_ops[0],
2060 { 0, 0, { 0 } }
2061 },
2062 /* mov $Rs1,$Ri */
2063 {
2064 { 1, 1, 1, 1 },
2065 FR30_INSN_MOVDR, "movdr", "mov",
2066 { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
2067 & fmt_movdr, { 0xb700 },
2068 (PTR) & fmt_movdr_ops[0],
2069 { 0, 0, { 0 } }
2070 },
2071 /* mov $ps,$Ri */
2072 {
2073 { 1, 1, 1, 1 },
2074 FR30_INSN_MOVPS, "movps", "mov",
2075 { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
2076 & fmt_div0s, { 0x1710 },
2077 (PTR) 0,
2078 { 0, 0, { 0 } }
2079 },
2080 /* mov $Ri,$Rs1 */
2081 {
2082 { 1, 1, 1, 1 },
2083 FR30_INSN_MOV2DR, "mov2dr", "mov",
2084 { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
2085 & fmt_mov2dr, { 0xb300 },
2086 (PTR) & fmt_mov2dr_ops[0],
2087 { 0, 0, { 0 } }
2088 },
2089 /* mov $Ri,$ps */
2090 {
2091 { 1, 1, 1, 1 },
2092 FR30_INSN_MOV2PS, "mov2ps", "mov",
2093 { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
2094 & fmt_div0s, { 0x710 },
2095 (PTR) 0,
2096 { 0, 0, { 0 } }
2097 },
2098 /* jmp @$Ri */
2099 {
2100 { 1, 1, 1, 1 },
2101 FR30_INSN_JMP, "jmp", "jmp",
2102 { { MNEM, ' ', '@', OP (RI), 0 } },
2103 & fmt_div0s, { 0x9700 },
2104 (PTR) 0,
2105 { 0, 0, { 0 } }
2106 },
2107 /* jmp:d @$Ri */
2108 {
2109 { 1, 1, 1, 1 },
2110 FR30_INSN_JMPD, "jmpd", "jmp:d",
2111 { { MNEM, ' ', '@', OP (RI), 0 } },
2112 & fmt_jmpd, { 0x9f00 },
2113 (PTR) & fmt_jmpd_ops[0],
2114 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2115 },
2116 /* call @$Ri */
2117 {
2118 { 1, 1, 1, 1 },
2119 FR30_INSN_CALLR, "callr", "call",
2120 { { MNEM, ' ', '@', OP (RI), 0 } },
2121 & fmt_div0s, { 0x9710 },
2122 (PTR) 0,
2123 { 0, 0, { 0 } }
2124 },
2125 /* call:D @$Ri */
2126 {
2127 { 1, 1, 1, 1 },
2128 FR30_INSN_CALLRD, "callrd", "call:D",
2129 { { MNEM, ' ', '@', OP (RI), 0 } },
2130 & fmt_div0s, { 0x9f10 },
2131 (PTR) 0,
2132 { 0, 0, { 0 } }
2133 },
2134 /* call $label12 */
2135 {
2136 { 1, 1, 1, 1 },
2137 FR30_INSN_CALL, "call", "call",
2138 { { MNEM, ' ', OP (LABEL12), 0 } },
2139 & fmt_call, { 0xd000 },
2140 (PTR) 0,
2141 { 0, 0, { 0 } }
2142 },
2143 /* call:D $label12 */
2144 {
2145 { 1, 1, 1, 1 },
2146 FR30_INSN_CALLD, "calld", "call:D",
2147 { { MNEM, ' ', OP (LABEL12), 0 } },
2148 & fmt_call, { 0xd400 },
2149 (PTR) 0,
2150 { 0, 0, { 0 } }
2151 },
2152 /* ret */
2153 {
2154 { 1, 1, 1, 1 },
2155 FR30_INSN_RET, "ret", "ret",
2156 { { MNEM, 0 } },
2157 & fmt_div3, { 0x9720 },
2158 (PTR) 0,
2159 { 0, 0, { 0 } }
2160 },
2161 /* ret:D */
2162 {
2163 { 1, 1, 1, 1 },
2164 FR30_INSN_RETD, "retd", "ret:D",
2165 { { MNEM, 0 } },
2166 & fmt_div3, { 0x9f20 },
2167 (PTR) 0,
2168 { 0, 0, { 0 } }
2169 },
2170 /* int $u8 */
2171 {
2172 { 1, 1, 1, 1 },
2173 FR30_INSN_INT, "int", "int",
2174 { { MNEM, ' ', OP (U8), 0 } },
2175 & fmt_int, { 0x1f00 },
2176 (PTR) & fmt_int_ops[0],
2177 { 0, 0|A(UNCOND_CTI), { 0 } }
2178 },
2179 /* inte */
2180 {
2181 { 1, 1, 1, 1 },
2182 FR30_INSN_INTE, "inte", "inte",
2183 { { MNEM, 0 } },
2184 & fmt_div3, { 0x9f30 },
2185 (PTR) 0,
2186 { 0, 0, { 0 } }
2187 },
2188 /* reti */
2189 {
2190 { 1, 1, 1, 1 },
2191 FR30_INSN_RETI, "reti", "reti",
2192 { { MNEM, 0 } },
2193 & fmt_reti, { 0x9730 },
2194 (PTR) & fmt_reti_ops[0],
2195 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2196 },
2197 /* bra $label9 */
2198 {
2199 { 1, 1, 1, 1 },
2200 FR30_INSN_BRA, "bra", "bra",
2201 { { MNEM, ' ', OP (LABEL9), 0 } },
2202 & fmt_bra, { 0xe000 },
2203 (PTR) & fmt_bra_ops[0],
2204 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2205 },
2206 /* bra:D $label9 */
2207 {
2208 { 1, 1, 1, 1 },
2209 FR30_INSN_BRAD, "brad", "bra:D",
2210 { { MNEM, ' ', OP (LABEL9), 0 } },
2211 & fmt_bra, { 0xf000 },
2212 (PTR) & fmt_bra_ops[0],
2213 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2214 },
2215 /* bno $label9 */
2216 {
2217 { 1, 1, 1, 1 },
2218 FR30_INSN_BNO, "bno", "bno",
2219 { { MNEM, ' ', OP (LABEL9), 0 } },
2220 & fmt_bra, { 0xe100 },
2221 (PTR) & fmt_bra_ops[0],
2222 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2223 },
2224 /* bno:D $label9 */
2225 {
2226 { 1, 1, 1, 1 },
2227 FR30_INSN_BNOD, "bnod", "bno:D",
2228 { { MNEM, ' ', OP (LABEL9), 0 } },
2229 & fmt_bra, { 0xf100 },
2230 (PTR) & fmt_bra_ops[0],
2231 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2232 },
2233 /* beq $label9 */
2234 {
2235 { 1, 1, 1, 1 },
2236 FR30_INSN_BEQ, "beq", "beq",
2237 { { MNEM, ' ', OP (LABEL9), 0 } },
2238 & fmt_beq, { 0xe200 },
2239 (PTR) & fmt_beq_ops[0],
2240 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2241 },
2242 /* beq:D $label9 */
2243 {
2244 { 1, 1, 1, 1 },
2245 FR30_INSN_BEQD, "beqd", "beq:D",
2246 { { MNEM, ' ', OP (LABEL9), 0 } },
2247 & fmt_beq, { 0xf200 },
2248 (PTR) & fmt_beq_ops[0],
2249 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2250 },
2251 /* bne $label9 */
2252 {
2253 { 1, 1, 1, 1 },
2254 FR30_INSN_BNE, "bne", "bne",
2255 { { MNEM, ' ', OP (LABEL9), 0 } },
2256 & fmt_beq, { 0xe300 },
2257 (PTR) & fmt_beq_ops[0],
2258 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2259 },
2260 /* bne:D $label9 */
2261 {
2262 { 1, 1, 1, 1 },
2263 FR30_INSN_BNED, "bned", "bne:D",
2264 { { MNEM, ' ', OP (LABEL9), 0 } },
2265 & fmt_beq, { 0xf300 },
2266 (PTR) & fmt_beq_ops[0],
2267 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2268 },
2269 /* bc $label9 */
2270 {
2271 { 1, 1, 1, 1 },
2272 FR30_INSN_BC, "bc", "bc",
2273 { { MNEM, ' ', OP (LABEL9), 0 } },
2274 & fmt_bc, { 0xe400 },
2275 (PTR) & fmt_bc_ops[0],
2276 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2277 },
2278 /* bc:D $label9 */
2279 {
2280 { 1, 1, 1, 1 },
2281 FR30_INSN_BCD, "bcd", "bc:D",
2282 { { MNEM, ' ', OP (LABEL9), 0 } },
2283 & fmt_bc, { 0xf400 },
2284 (PTR) & fmt_bc_ops[0],
2285 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2286 },
2287 /* bnc $label9 */
2288 {
2289 { 1, 1, 1, 1 },
2290 FR30_INSN_BNC, "bnc", "bnc",
2291 { { MNEM, ' ', OP (LABEL9), 0 } },
2292 & fmt_bc, { 0xe500 },
2293 (PTR) & fmt_bc_ops[0],
2294 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2295 },
2296 /* bnc:D $label9 */
2297 {
2298 { 1, 1, 1, 1 },
2299 FR30_INSN_BNCD, "bncd", "bnc:D",
2300 { { MNEM, ' ', OP (LABEL9), 0 } },
2301 & fmt_bc, { 0xf500 },
2302 (PTR) & fmt_bc_ops[0],
2303 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2304 },
2305 /* bn $label9 */
2306 {
2307 { 1, 1, 1, 1 },
2308 FR30_INSN_BN, "bn", "bn",
2309 { { MNEM, ' ', OP (LABEL9), 0 } },
2310 & fmt_bn, { 0xe600 },
2311 (PTR) & fmt_bn_ops[0],
2312 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2313 },
2314 /* bn:D $label9 */
2315 {
2316 { 1, 1, 1, 1 },
2317 FR30_INSN_BND, "bnd", "bn:D",
2318 { { MNEM, ' ', OP (LABEL9), 0 } },
2319 & fmt_bn, { 0xf600 },
2320 (PTR) & fmt_bn_ops[0],
2321 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2322 },
2323 /* bp $label9 */
2324 {
2325 { 1, 1, 1, 1 },
2326 FR30_INSN_BP, "bp", "bp",
2327 { { MNEM, ' ', OP (LABEL9), 0 } },
2328 & fmt_bn, { 0xe700 },
2329 (PTR) & fmt_bn_ops[0],
2330 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2331 },
2332 /* bp:D $label9 */
2333 {
2334 { 1, 1, 1, 1 },
2335 FR30_INSN_BPD, "bpd", "bp:D",
2336 { { MNEM, ' ', OP (LABEL9), 0 } },
2337 & fmt_bn, { 0xf700 },
2338 (PTR) & fmt_bn_ops[0],
2339 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2340 },
2341 /* bv $label9 */
2342 {
2343 { 1, 1, 1, 1 },
2344 FR30_INSN_BV, "bv", "bv",
2345 { { MNEM, ' ', OP (LABEL9), 0 } },
2346 & fmt_bv, { 0xe800 },
2347 (PTR) & fmt_bv_ops[0],
2348 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2349 },
2350 /* bv:D $label9 */
2351 {
2352 { 1, 1, 1, 1 },
2353 FR30_INSN_BVD, "bvd", "bv:D",
2354 { { MNEM, ' ', OP (LABEL9), 0 } },
2355 & fmt_bv, { 0xf800 },
2356 (PTR) & fmt_bv_ops[0],
2357 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2358 },
2359 /* bnv $label9 */
2360 {
2361 { 1, 1, 1, 1 },
2362 FR30_INSN_BNV, "bnv", "bnv",
2363 { { MNEM, ' ', OP (LABEL9), 0 } },
2364 & fmt_bv, { 0xe900 },
2365 (PTR) & fmt_bv_ops[0],
2366 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2367 },
2368 /* bnv:D $label9 */
2369 {
2370 { 1, 1, 1, 1 },
2371 FR30_INSN_BNVD, "bnvd", "bnv:D",
2372 { { MNEM, ' ', OP (LABEL9), 0 } },
2373 & fmt_bv, { 0xf900 },
2374 (PTR) & fmt_bv_ops[0],
2375 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2376 },
2377 /* blt $label9 */
2378 {
2379 { 1, 1, 1, 1 },
2380 FR30_INSN_BLT, "blt", "blt",
2381 { { MNEM, ' ', OP (LABEL9), 0 } },
2382 & fmt_blt, { 0xea00 },
2383 (PTR) & fmt_blt_ops[0],
2384 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2385 },
2386 /* blt:D $label9 */
2387 {
2388 { 1, 1, 1, 1 },
2389 FR30_INSN_BLTD, "bltd", "blt:D",
2390 { { MNEM, ' ', OP (LABEL9), 0 } },
2391 & fmt_blt, { 0xfa00 },
2392 (PTR) & fmt_blt_ops[0],
2393 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2394 },
2395 /* bge $label9 */
2396 {
2397 { 1, 1, 1, 1 },
2398 FR30_INSN_BGE, "bge", "bge",
2399 { { MNEM, ' ', OP (LABEL9), 0 } },
2400 & fmt_blt, { 0xeb00 },
2401 (PTR) & fmt_blt_ops[0],
2402 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2403 },
2404 /* bge:D $label9 */
2405 {
2406 { 1, 1, 1, 1 },
2407 FR30_INSN_BGED, "bged", "bge:D",
2408 { { MNEM, ' ', OP (LABEL9), 0 } },
2409 & fmt_blt, { 0xfb00 },
2410 (PTR) & fmt_blt_ops[0],
2411 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2412 },
2413 /* ble $label9 */
2414 {
2415 { 1, 1, 1, 1 },
2416 FR30_INSN_BLE, "ble", "ble",
2417 { { MNEM, ' ', OP (LABEL9), 0 } },
2418 & fmt_ble, { 0xec00 },
2419 (PTR) & fmt_ble_ops[0],
2420 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2421 },
2422 /* ble:D $label9 */
2423 {
2424 { 1, 1, 1, 1 },
2425 FR30_INSN_BLED, "bled", "ble:D",
2426 { { MNEM, ' ', OP (LABEL9), 0 } },
2427 & fmt_ble, { 0xfc00 },
2428 (PTR) & fmt_ble_ops[0],
2429 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2430 },
2431 /* bgt $label9 */
2432 {
2433 { 1, 1, 1, 1 },
2434 FR30_INSN_BGT, "bgt", "bgt",
2435 { { MNEM, ' ', OP (LABEL9), 0 } },
2436 & fmt_ble, { 0xed00 },
2437 (PTR) & fmt_ble_ops[0],
2438 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2439 },
2440 /* bgt:D $label9 */
2441 {
2442 { 1, 1, 1, 1 },
2443 FR30_INSN_BGTD, "bgtd", "bgt:D",
2444 { { MNEM, ' ', OP (LABEL9), 0 } },
2445 & fmt_ble, { 0xfd00 },
2446 (PTR) & fmt_ble_ops[0],
2447 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2448 },
2449 /* bls $label9 */
2450 {
2451 { 1, 1, 1, 1 },
2452 FR30_INSN_BLS, "bls", "bls",
2453 { { MNEM, ' ', OP (LABEL9), 0 } },
2454 & fmt_bls, { 0xee00 },
2455 (PTR) & fmt_bls_ops[0],
2456 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2457 },
2458 /* bls:D $label9 */
2459 {
2460 { 1, 1, 1, 1 },
2461 FR30_INSN_BLSD, "blsd", "bls:D",
2462 { { MNEM, ' ', OP (LABEL9), 0 } },
2463 & fmt_bls, { 0xfe00 },
2464 (PTR) & fmt_bls_ops[0],
2465 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2466 },
2467 /* bhi $label9 */
2468 {
2469 { 1, 1, 1, 1 },
2470 FR30_INSN_BHI, "bhi", "bhi",
2471 { { MNEM, ' ', OP (LABEL9), 0 } },
2472 & fmt_bls, { 0xef00 },
2473 (PTR) & fmt_bls_ops[0],
2474 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2475 },
2476 /* bhi:D $label9 */
2477 {
2478 { 1, 1, 1, 1 },
2479 FR30_INSN_BHID, "bhid", "bhi:D",
2480 { { MNEM, ' ', OP (LABEL9), 0 } },
2481 & fmt_bls, { 0xff00 },
2482 (PTR) & fmt_bls_ops[0],
2483 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2484 },
2485 /* dmov $R13,@$dir10 */
2486 {
2487 { 1, 1, 1, 1 },
2488 FR30_INSN_DMOVR13, "dmovr13", "dmov",
2489 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
2490 & fmt_dmovr13, { 0x1800 },
2491 (PTR) 0,
2492 { 0, 0, { 0 } }
2493 },
2494 /* dmovh $R13,@$dir9 */
2495 {
2496 { 1, 1, 1, 1 },
2497 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
2498 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
2499 & fmt_dmovr13h, { 0x1900 },
2500 (PTR) 0,
2501 { 0, 0, { 0 } }
2502 },
2503 /* dmovb $R13,@$dir8 */
2504 {
2505 { 1, 1, 1, 1 },
2506 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
2507 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
2508 & fmt_dmovr13b, { 0x1a00 },
2509 (PTR) 0,
2510 { 0, 0, { 0 } }
2511 },
2512 /* dmov @$R13+,@$dir10 */
2513 {
2514 { 1, 1, 1, 1 },
2515 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
2516 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
2517 & fmt_dmovr13, { 0x1c00 },
2518 (PTR) 0,
2519 { 0, 0, { 0 } }
2520 },
2521 /* dmovh @$R13+,@$dir9 */
2522 {
2523 { 1, 1, 1, 1 },
2524 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
2525 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
2526 & fmt_dmovr13h, { 0x1d00 },
2527 (PTR) 0,
2528 { 0, 0, { 0 } }
2529 },
2530 /* dmovb @$R13+,@$dir8 */
2531 {
2532 { 1, 1, 1, 1 },
2533 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
2534 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
2535 & fmt_dmovr13b, { 0x1e00 },
2536 (PTR) 0,
2537 { 0, 0, { 0 } }
2538 },
2539 /* dmov @$R15+,@$dir10 */
2540 {
2541 { 1, 1, 1, 1 },
2542 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
2543 { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
2544 & fmt_dmovr13, { 0x1b00 },
2545 (PTR) 0,
2546 { 0, 0, { 0 } }
2547 },
2548 /* dmov @$dir10,$R13 */
2549 {
2550 { 1, 1, 1, 1 },
2551 FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
2552 { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
2553 & fmt_dmovr13, { 0x800 },
2554 (PTR) 0,
2555 { 0, 0, { 0 } }
2556 },
2557 /* dmovh @$dir9,$R13 */
2558 {
2559 { 1, 1, 1, 1 },
2560 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
2561 { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
2562 & fmt_dmovr13h, { 0x900 },
2563 (PTR) 0,
2564 { 0, 0, { 0 } }
2565 },
2566 /* dmovb @$dir8,$R13 */
2567 {
2568 { 1, 1, 1, 1 },
2569 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
2570 { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
2571 & fmt_dmovr13b, { 0xa00 },
2572 (PTR) 0,
2573 { 0, 0, { 0 } }
2574 },
2575 /* dmov @$dir10,@$R13+ */
2576 {
2577 { 1, 1, 1, 1 },
2578 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
2579 { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
2580 & fmt_dmovr13, { 0xc00 },
2581 (PTR) 0,
2582 { 0, 0, { 0 } }
2583 },
2584 /* dmovh @$dir9,@$R13+ */
2585 {
2586 { 1, 1, 1, 1 },
2587 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
2588 { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
2589 & fmt_dmovr13h, { 0xd00 },
2590 (PTR) 0,
2591 { 0, 0, { 0 } }
2592 },
2593 /* dmovb @$dir8,@$R13+ */
2594 {
2595 { 1, 1, 1, 1 },
2596 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
2597 { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
2598 & fmt_dmovr13b, { 0xe00 },
2599 (PTR) 0,
2600 { 0, 0, { 0 } }
2601 },
2602 /* dmov @$dir10,@-$R15 */
2603 {
2604 { 1, 1, 1, 1 },
2605 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
2606 { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
2607 & fmt_dmovr13, { 0xb00 },
2608 (PTR) 0,
2609 { 0, 0, { 0 } }
2610 },
2611 /* ldres @$Ri+,$u4 */
2612 {
2613 { 1, 1, 1, 1 },
2614 FR30_INSN_LDRES, "ldres", "ldres",
2615 { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
2616 & fmt_ldres, { 0xbc00 },
2617 (PTR) 0,
2618 { 0, 0, { 0 } }
2619 },
2620 /* stres $u4,@$Ri+ */
2621 {
2622 { 1, 1, 1, 1 },
2623 FR30_INSN_STRES, "stres", "stres",
2624 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
2625 & fmt_ldres, { 0xbd00 },
2626 (PTR) 0,
2627 { 0, 0, { 0 } }
2628 },
2629 /* copop $u4c,$ccc,$CRj,$CRi */
2630 {
2631 { 1, 1, 1, 1 },
2632 FR30_INSN_COPOP, "copop", "copop",
2633 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
2634 & fmt_copop, { 0x9fc0 },
2635 (PTR) 0,
2636 { 0, 0, { 0 } }
2637 },
2638 /* copld $u4c,$ccc,$Rjc,$CRi */
2639 {
2640 { 1, 1, 1, 1 },
2641 FR30_INSN_COPLD, "copld", "copld",
2642 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
2643 & fmt_copld, { 0x9fd0 },
2644 (PTR) 0,
2645 { 0, 0, { 0 } }
2646 },
2647 /* copst $u4c,$ccc,$CRj,$Ric */
2648 {
2649 { 1, 1, 1, 1 },
2650 FR30_INSN_COPST, "copst", "copst",
2651 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2652 & fmt_copst, { 0x9fe0 },
2653 (PTR) 0,
2654 { 0, 0, { 0 } }
2655 },
2656 /* copsv $u4c,$ccc,$CRj,$Ric */
2657 {
2658 { 1, 1, 1, 1 },
2659 FR30_INSN_COPSV, "copsv", "copsv",
2660 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2661 & fmt_copst, { 0x9ff0 },
2662 (PTR) 0,
2663 { 0, 0, { 0 } }
2664 },
2665 /* nop */
2666 {
2667 { 1, 1, 1, 1 },
2668 FR30_INSN_NOP, "nop", "nop",
2669 { { MNEM, 0 } },
2670 & fmt_div3, { 0x9fa0 },
2671 (PTR) 0,
2672 { 0, 0, { 0 } }
2673 },
2674 /* andccr $u8 */
2675 {
2676 { 1, 1, 1, 1 },
2677 FR30_INSN_ANDCCR, "andccr", "andccr",
2678 { { MNEM, ' ', OP (U8), 0 } },
2679 & fmt_andccr, { 0x8300 },
2680 (PTR) & fmt_andccr_ops[0],
2681 { 0, 0, { 0 } }
2682 },
2683 /* orccr $u8 */
2684 {
2685 { 1, 1, 1, 1 },
2686 FR30_INSN_ORCCR, "orccr", "orccr",
2687 { { MNEM, ' ', OP (U8), 0 } },
2688 & fmt_andccr, { 0x9300 },
2689 (PTR) & fmt_andccr_ops[0],
2690 { 0, 0, { 0 } }
2691 },
2692 /* stilm $u8 */
2693 {
2694 { 1, 1, 1, 1 },
2695 FR30_INSN_STILM, "stilm", "stilm",
2696 { { MNEM, ' ', OP (U8), 0 } },
2697 & fmt_stilm, { 0x8700 },
2698 (PTR) 0,
2699 { 0, 0, { 0 } }
2700 },
2701 /* addsp $s10 */
2702 {
2703 { 1, 1, 1, 1 },
2704 FR30_INSN_ADDSP, "addsp", "addsp",
2705 { { MNEM, ' ', OP (S10), 0 } },
2706 & fmt_addsp, { 0xa300 },
2707 (PTR) 0,
2708 { 0, 0, { 0 } }
2709 },
2710 /* extsb $Ri */
2711 {
2712 { 1, 1, 1, 1 },
2713 FR30_INSN_EXTSB, "extsb", "extsb",
2714 { { MNEM, ' ', OP (RI), 0 } },
2715 & fmt_div0s, { 0x9780 },
2716 (PTR) 0,
2717 { 0, 0, { 0 } }
2718 },
2719 /* extub $Ri */
2720 {
2721 { 1, 1, 1, 1 },
2722 FR30_INSN_EXTUB, "extub", "extub",
2723 { { MNEM, ' ', OP (RI), 0 } },
2724 & fmt_div0s, { 0x9790 },
2725 (PTR) 0,
2726 { 0, 0, { 0 } }
2727 },
2728 /* extsh $Ri */
2729 {
2730 { 1, 1, 1, 1 },
2731 FR30_INSN_EXTSH, "extsh", "extsh",
2732 { { MNEM, ' ', OP (RI), 0 } },
2733 & fmt_div0s, { 0x97a0 },
2734 (PTR) 0,
2735 { 0, 0, { 0 } }
2736 },
2737 /* extuh $Ri */
2738 {
2739 { 1, 1, 1, 1 },
2740 FR30_INSN_EXTUH, "extuh", "extuh",
2741 { { MNEM, ' ', OP (RI), 0 } },
2742 & fmt_div0s, { 0x97b0 },
2743 (PTR) 0,
2744 { 0, 0, { 0 } }
2745 },
2746 /* ldm0 ($reglist_low) */
2747 {
2748 { 1, 1, 1, 1 },
2749 FR30_INSN_LDM0, "ldm0", "ldm0",
2750 { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
2751 & fmt_ldm0, { 0x8c00 },
2752 (PTR) 0,
2753 { 0, 0, { 0 } }
2754 },
2755 /* ldm1 ($reglist_hi) */
2756 {
2757 { 1, 1, 1, 1 },
2758 FR30_INSN_LDM1, "ldm1", "ldm1",
2759 { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
2760 & fmt_ldm1, { 0x8d00 },
2761 (PTR) 0,
2762 { 0, 0, { 0 } }
2763 },
2764 /* stm0 ($reglist_low) */
2765 {
2766 { 1, 1, 1, 1 },
2767 FR30_INSN_STM0, "stm0", "stm0",
2768 { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
2769 & fmt_ldm0, { 0x8e00 },
2770 (PTR) 0,
2771 { 0, 0, { 0 } }
2772 },
2773 /* stm1 ($reglist_hi) */
2774 {
2775 { 1, 1, 1, 1 },
2776 FR30_INSN_STM1, "stm1", "stm1",
2777 { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
2778 & fmt_ldm1, { 0x8f00 },
2779 (PTR) 0,
2780 { 0, 0, { 0 } }
2781 },
2782 /* enter $u10 */
2783 {
2784 { 1, 1, 1, 1 },
2785 FR30_INSN_ENTER, "enter", "enter",
2786 { { MNEM, ' ', OP (U10), 0 } },
2787 & fmt_enter, { 0xf00 },
2788 (PTR) 0,
2789 { 0, 0, { 0 } }
2790 },
2791 /* leave */
2792 {
2793 { 1, 1, 1, 1 },
2794 FR30_INSN_LEAVE, "leave", "leave",
2795 { { MNEM, 0 } },
2796 & fmt_div3, { 0x9f90 },
2797 (PTR) 0,
2798 { 0, 0, { 0 } }
2799 },
2800 /* xchb @$Rj,$Ri */
2801 {
2802 { 1, 1, 1, 1 },
2803 FR30_INSN_XCHB, "xchb", "xchb",
2804 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2805 & fmt_sth, { 0x8a00 },
2806 (PTR) 0,
2807 { 0, 0, { 0 } }
2808 },
2809 };
2810
2811 #undef A
2812 #undef MNEM
2813 #undef OP
2814
2815 static const CGEN_INSN_TABLE insn_table =
2816 {
2817 & fr30_cgen_insn_table_entries[0],
2818 sizeof (CGEN_INSN),
2819 MAX_INSNS,
2820 NULL
2821 };
2822
2823 /* Formats for ALIAS macro-insns. */
2824
2825 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
2826
2827 static const CGEN_IFMT fmt_ldi8m = {
2828 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
2829 };
2830
2831 static const CGEN_IFMT fmt_ldi20m = {
2832 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
2833 };
2834
2835 static const CGEN_IFMT fmt_ldi32m = {
2836 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
2837 };
2838
2839 #undef F
2840
2841 /* Each non-simple macro entry points to an array of expansion possibilities. */
2842
2843 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2844 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2845 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2846
2847 /* The macro instruction table. */
2848
2849 static const CGEN_INSN macro_insn_table_entries[] =
2850 {
2851 /* ldi8 $i8,$Ri */
2852 {
2853 { 1, 1, 1, 1 },
2854 -1, "ldi8m", "ldi8",
2855 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
2856 & fmt_ldi8m, { 0xc000 },
2857 (PTR) 0,
2858 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
2859 },
2860 /* ldi20 $i20,$Ri */
2861 {
2862 { 1, 1, 1, 1 },
2863 -1, "ldi20m", "ldi20",
2864 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
2865 & fmt_ldi20m, { 0x9b00 },
2866 (PTR) 0,
2867 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
2868 },
2869 /* ldi32 $i32,$Ri */
2870 {
2871 { 1, 1, 1, 1 },
2872 -1, "ldi32m", "ldi32",
2873 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
2874 & fmt_ldi32m, { 0x9f80 },
2875 (PTR) 0,
2876 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
2877 },
2878 };
2879
2880 #undef A
2881 #undef MNEM
2882 #undef OP
2883
2884 static const CGEN_INSN_TABLE macro_insn_table =
2885 {
2886 & macro_insn_table_entries[0],
2887 sizeof (CGEN_INSN),
2888 (sizeof (macro_insn_table_entries) /
2889 sizeof (macro_insn_table_entries[0])),
2890 NULL
2891 };
2892
2893 static void
2894 init_tables ()
2895 {
2896 }
2897
2898 /* Return non-zero if INSN is to be added to the hash table.
2899 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
2900
2901 static int
2902 asm_hash_insn_p (insn)
2903 const CGEN_INSN * insn;
2904 {
2905 return CGEN_ASM_HASH_P (insn);
2906 }
2907
2908 static int
2909 dis_hash_insn_p (insn)
2910 const CGEN_INSN * insn;
2911 {
2912 /* If building the hash table and the NO-DIS attribute is present,
2913 ignore. */
2914 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2915 return 0;
2916 return CGEN_DIS_HASH_P (insn);
2917 }
2918
2919 /* The result is the hash value of the insn.
2920 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
2921
2922 static unsigned int
2923 asm_hash_insn (mnem)
2924 const char * mnem;
2925 {
2926 return CGEN_ASM_HASH (mnem);
2927 }
2928
2929 /* BUF is a pointer to the insn's bytes in target order.
2930 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
2931 host order. */
2932
2933 static unsigned int
2934 dis_hash_insn (buf, value)
2935 const char * buf;
2936 CGEN_INSN_INT value;
2937 {
2938 return CGEN_DIS_HASH (buf, value);
2939 }
2940
2941 /* Initialize an opcode table and return a descriptor.
2942 It's much like opening a file, and must be the first function called. */
2943
2944 CGEN_OPCODE_DESC
2945 fr30_cgen_opcode_open (mach, endian)
2946 int mach;
2947 enum cgen_endian endian;
2948 {
2949 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2950 static int init_p;
2951
2952 if (! init_p)
2953 {
2954 init_tables ();
2955 init_p = 1;
2956 }
2957
2958 memset (table, 0, sizeof (*table));
2959
2960 CGEN_OPCODE_MACH (table) = mach;
2961 CGEN_OPCODE_ENDIAN (table) = endian;
2962 /* FIXME: for the sparc case we can determine insn-endianness statically.
2963 The worry here is where both data and insn endian can be independently
2964 chosen, in which case this function will need another argument.
2965 Actually, will want to allow for more arguments in the future anyway. */
2966 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
2967
2968 CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
2969
2970 CGEN_OPCODE_IFLD_TABLE (table) = & fr30_cgen_ifld_table[0];
2971
2972 CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
2973
2974 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2975
2976 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2977
2978 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2979 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2980 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2981
2982 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2983 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2984 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2985
2986 return (CGEN_OPCODE_DESC) table;
2987 }
2988
2989 /* Close an opcode table. */
2990
2991 void
2992 fr30_cgen_opcode_close (desc)
2993 CGEN_OPCODE_DESC desc;
2994 {
2995 free (desc);
2996 }
2997
2998 /* Getting values from cgen_fields is handled by a collection of functions.
2999 They are distinguished by the type of the VALUE argument they return.
3000 TODO: floating point, inlining support, remove cases where result type
3001 not appropriate. */
3002
3003 int
3004 fr30_cgen_get_int_operand (opindex, fields)
3005 int opindex;
3006 const CGEN_FIELDS * fields;
3007 {
3008 int value;
3009
3010 switch (opindex)
3011 {
3012 case FR30_OPERAND_RI :
3013 value = fields->f_Ri;
3014 break;
3015 case FR30_OPERAND_RJ :
3016 value = fields->f_Rj;
3017 break;
3018 case FR30_OPERAND_RIC :
3019 value = fields->f_Ric;
3020 break;
3021 case FR30_OPERAND_RJC :
3022 value = fields->f_Rjc;
3023 break;
3024 case FR30_OPERAND_CRI :
3025 value = fields->f_CRi;
3026 break;
3027 case FR30_OPERAND_CRJ :
3028 value = fields->f_CRj;
3029 break;
3030 case FR30_OPERAND_RS1 :
3031 value = fields->f_Rs1;
3032 break;
3033 case FR30_OPERAND_RS2 :
3034 value = fields->f_Rs2;
3035 break;
3036 case FR30_OPERAND_R13 :
3037 value = fields->f_nil;
3038 break;
3039 case FR30_OPERAND_R14 :
3040 value = fields->f_nil;
3041 break;
3042 case FR30_OPERAND_R15 :
3043 value = fields->f_nil;
3044 break;
3045 case FR30_OPERAND_PS :
3046 value = fields->f_nil;
3047 break;
3048 case FR30_OPERAND_U4 :
3049 value = fields->f_u4;
3050 break;
3051 case FR30_OPERAND_U4C :
3052 value = fields->f_u4c;
3053 break;
3054 case FR30_OPERAND_U8 :
3055 value = fields->f_u8;
3056 break;
3057 case FR30_OPERAND_I8 :
3058 value = fields->f_i8;
3059 break;
3060 case FR30_OPERAND_UDISP6 :
3061 value = fields->f_udisp6;
3062 break;
3063 case FR30_OPERAND_DISP8 :
3064 value = fields->f_disp8;
3065 break;
3066 case FR30_OPERAND_DISP9 :
3067 value = fields->f_disp9;
3068 break;
3069 case FR30_OPERAND_DISP10 :
3070 value = fields->f_disp10;
3071 break;
3072 case FR30_OPERAND_S10 :
3073 value = fields->f_s10;
3074 break;
3075 case FR30_OPERAND_U10 :
3076 value = fields->f_u10;
3077 break;
3078 case FR30_OPERAND_I32 :
3079 value = fields->f_i32;
3080 break;
3081 case FR30_OPERAND_M4 :
3082 value = fields->f_m4;
3083 break;
3084 case FR30_OPERAND_I20 :
3085 value = fields->f_i20;
3086 break;
3087 case FR30_OPERAND_LABEL9 :
3088 value = fields->f_rel9;
3089 break;
3090 case FR30_OPERAND_DIR8 :
3091 value = fields->f_dir8;
3092 break;
3093 case FR30_OPERAND_DIR9 :
3094 value = fields->f_dir9;
3095 break;
3096 case FR30_OPERAND_DIR10 :
3097 value = fields->f_dir10;
3098 break;
3099 case FR30_OPERAND_LABEL12 :
3100 value = fields->f_rel12;
3101 break;
3102 case FR30_OPERAND_REGLIST_LOW :
3103 value = fields->f_reglist_low;
3104 break;
3105 case FR30_OPERAND_REGLIST_HI :
3106 value = fields->f_reglist_hi;
3107 break;
3108 case FR30_OPERAND_CC :
3109 value = fields->f_cc;
3110 break;
3111 case FR30_OPERAND_CCC :
3112 value = fields->f_ccc;
3113 break;
3114
3115 default :
3116 /* xgettext:c-format */
3117 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
3118 opindex);
3119 abort ();
3120 }
3121
3122 return value;
3123 }
3124
3125 bfd_vma
3126 fr30_cgen_get_vma_operand (opindex, fields)
3127 int opindex;
3128 const CGEN_FIELDS * fields;
3129 {
3130 bfd_vma value;
3131
3132 switch (opindex)
3133 {
3134 case FR30_OPERAND_RI :
3135 value = fields->f_Ri;
3136 break;
3137 case FR30_OPERAND_RJ :
3138 value = fields->f_Rj;
3139 break;
3140 case FR30_OPERAND_RIC :
3141 value = fields->f_Ric;
3142 break;
3143 case FR30_OPERAND_RJC :
3144 value = fields->f_Rjc;
3145 break;
3146 case FR30_OPERAND_CRI :
3147 value = fields->f_CRi;
3148 break;
3149 case FR30_OPERAND_CRJ :
3150 value = fields->f_CRj;
3151 break;
3152 case FR30_OPERAND_RS1 :
3153 value = fields->f_Rs1;
3154 break;
3155 case FR30_OPERAND_RS2 :
3156 value = fields->f_Rs2;
3157 break;
3158 case FR30_OPERAND_R13 :
3159 value = fields->f_nil;
3160 break;
3161 case FR30_OPERAND_R14 :
3162 value = fields->f_nil;
3163 break;
3164 case FR30_OPERAND_R15 :
3165 value = fields->f_nil;
3166 break;
3167 case FR30_OPERAND_PS :
3168 value = fields->f_nil;
3169 break;
3170 case FR30_OPERAND_U4 :
3171 value = fields->f_u4;
3172 break;
3173 case FR30_OPERAND_U4C :
3174 value = fields->f_u4c;
3175 break;
3176 case FR30_OPERAND_U8 :
3177 value = fields->f_u8;
3178 break;
3179 case FR30_OPERAND_I8 :
3180 value = fields->f_i8;
3181 break;
3182 case FR30_OPERAND_UDISP6 :
3183 value = fields->f_udisp6;
3184 break;
3185 case FR30_OPERAND_DISP8 :
3186 value = fields->f_disp8;
3187 break;
3188 case FR30_OPERAND_DISP9 :
3189 value = fields->f_disp9;
3190 break;
3191 case FR30_OPERAND_DISP10 :
3192 value = fields->f_disp10;
3193 break;
3194 case FR30_OPERAND_S10 :
3195 value = fields->f_s10;
3196 break;
3197 case FR30_OPERAND_U10 :
3198 value = fields->f_u10;
3199 break;
3200 case FR30_OPERAND_I32 :
3201 value = fields->f_i32;
3202 break;
3203 case FR30_OPERAND_M4 :
3204 value = fields->f_m4;
3205 break;
3206 case FR30_OPERAND_I20 :
3207 value = fields->f_i20;
3208 break;
3209 case FR30_OPERAND_LABEL9 :
3210 value = fields->f_rel9;
3211 break;
3212 case FR30_OPERAND_DIR8 :
3213 value = fields->f_dir8;
3214 break;
3215 case FR30_OPERAND_DIR9 :
3216 value = fields->f_dir9;
3217 break;
3218 case FR30_OPERAND_DIR10 :
3219 value = fields->f_dir10;
3220 break;
3221 case FR30_OPERAND_LABEL12 :
3222 value = fields->f_rel12;
3223 break;
3224 case FR30_OPERAND_REGLIST_LOW :
3225 value = fields->f_reglist_low;
3226 break;
3227 case FR30_OPERAND_REGLIST_HI :
3228 value = fields->f_reglist_hi;
3229 break;
3230 case FR30_OPERAND_CC :
3231 value = fields->f_cc;
3232 break;
3233 case FR30_OPERAND_CCC :
3234 value = fields->f_ccc;
3235 break;
3236
3237 default :
3238 /* xgettext:c-format */
3239 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
3240 opindex);
3241 abort ();
3242 }
3243
3244 return value;
3245 }
3246
3247 /* Stuffing values in cgen_fields is handled by a collection of functions.
3248 They are distinguished by the type of the VALUE argument they accept.
3249 TODO: floating point, inlining support, remove cases where argument type
3250 not appropriate. */
3251
3252 void
3253 fr30_cgen_set_int_operand (opindex, fields, value)
3254 int opindex;
3255 CGEN_FIELDS * fields;
3256 int value;
3257 {
3258 switch (opindex)
3259 {
3260 case FR30_OPERAND_RI :
3261 fields->f_Ri = value;
3262 break;
3263 case FR30_OPERAND_RJ :
3264 fields->f_Rj = value;
3265 break;
3266 case FR30_OPERAND_RIC :
3267 fields->f_Ric = value;
3268 break;
3269 case FR30_OPERAND_RJC :
3270 fields->f_Rjc = value;
3271 break;
3272 case FR30_OPERAND_CRI :
3273 fields->f_CRi = value;
3274 break;
3275 case FR30_OPERAND_CRJ :
3276 fields->f_CRj = value;
3277 break;
3278 case FR30_OPERAND_RS1 :
3279 fields->f_Rs1 = value;
3280 break;
3281 case FR30_OPERAND_RS2 :
3282 fields->f_Rs2 = value;
3283 break;
3284 case FR30_OPERAND_R13 :
3285 fields->f_nil = value;
3286 break;
3287 case FR30_OPERAND_R14 :
3288 fields->f_nil = value;
3289 break;
3290 case FR30_OPERAND_R15 :
3291 fields->f_nil = value;
3292 break;
3293 case FR30_OPERAND_PS :
3294 fields->f_nil = value;
3295 break;
3296 case FR30_OPERAND_U4 :
3297 fields->f_u4 = value;
3298 break;
3299 case FR30_OPERAND_U4C :
3300 fields->f_u4c = value;
3301 break;
3302 case FR30_OPERAND_U8 :
3303 fields->f_u8 = value;
3304 break;
3305 case FR30_OPERAND_I8 :
3306 fields->f_i8 = value;
3307 break;
3308 case FR30_OPERAND_UDISP6 :
3309 fields->f_udisp6 = value;
3310 break;
3311 case FR30_OPERAND_DISP8 :
3312 fields->f_disp8 = value;
3313 break;
3314 case FR30_OPERAND_DISP9 :
3315 fields->f_disp9 = value;
3316 break;
3317 case FR30_OPERAND_DISP10 :
3318 fields->f_disp10 = value;
3319 break;
3320 case FR30_OPERAND_S10 :
3321 fields->f_s10 = value;
3322 break;
3323 case FR30_OPERAND_U10 :
3324 fields->f_u10 = value;
3325 break;
3326 case FR30_OPERAND_I32 :
3327 fields->f_i32 = value;
3328 break;
3329 case FR30_OPERAND_M4 :
3330 fields->f_m4 = value;
3331 break;
3332 case FR30_OPERAND_I20 :
3333 fields->f_i20 = value;
3334 break;
3335 case FR30_OPERAND_LABEL9 :
3336 fields->f_rel9 = value;
3337 break;
3338 case FR30_OPERAND_DIR8 :
3339 fields->f_dir8 = value;
3340 break;
3341 case FR30_OPERAND_DIR9 :
3342 fields->f_dir9 = value;
3343 break;
3344 case FR30_OPERAND_DIR10 :
3345 fields->f_dir10 = value;
3346 break;
3347 case FR30_OPERAND_LABEL12 :
3348 fields->f_rel12 = value;
3349 break;
3350 case FR30_OPERAND_REGLIST_LOW :
3351 fields->f_reglist_low = value;
3352 break;
3353 case FR30_OPERAND_REGLIST_HI :
3354 fields->f_reglist_hi = value;
3355 break;
3356 case FR30_OPERAND_CC :
3357 fields->f_cc = value;
3358 break;
3359 case FR30_OPERAND_CCC :
3360 fields->f_ccc = value;
3361 break;
3362
3363 default :
3364 /* xgettext:c-format */
3365 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
3366 opindex);
3367 abort ();
3368 }
3369 }
3370
3371 void
3372 fr30_cgen_set_vma_operand (opindex, fields, value)
3373 int opindex;
3374 CGEN_FIELDS * fields;
3375 bfd_vma value;
3376 {
3377 switch (opindex)
3378 {
3379 case FR30_OPERAND_RI :
3380 fields->f_Ri = value;
3381 break;
3382 case FR30_OPERAND_RJ :
3383 fields->f_Rj = value;
3384 break;
3385 case FR30_OPERAND_RIC :
3386 fields->f_Ric = value;
3387 break;
3388 case FR30_OPERAND_RJC :
3389 fields->f_Rjc = value;
3390 break;
3391 case FR30_OPERAND_CRI :
3392 fields->f_CRi = value;
3393 break;
3394 case FR30_OPERAND_CRJ :
3395 fields->f_CRj = value;
3396 break;
3397 case FR30_OPERAND_RS1 :
3398 fields->f_Rs1 = value;
3399 break;
3400 case FR30_OPERAND_RS2 :
3401 fields->f_Rs2 = value;
3402 break;
3403 case FR30_OPERAND_R13 :
3404 fields->f_nil = value;
3405 break;
3406 case FR30_OPERAND_R14 :
3407 fields->f_nil = value;
3408 break;
3409 case FR30_OPERAND_R15 :
3410 fields->f_nil = value;
3411 break;
3412 case FR30_OPERAND_PS :
3413 fields->f_nil = value;
3414 break;
3415 case FR30_OPERAND_U4 :
3416 fields->f_u4 = value;
3417 break;
3418 case FR30_OPERAND_U4C :
3419 fields->f_u4c = value;
3420 break;
3421 case FR30_OPERAND_U8 :
3422 fields->f_u8 = value;
3423 break;
3424 case FR30_OPERAND_I8 :
3425 fields->f_i8 = value;
3426 break;
3427 case FR30_OPERAND_UDISP6 :
3428 fields->f_udisp6 = value;
3429 break;
3430 case FR30_OPERAND_DISP8 :
3431 fields->f_disp8 = value;
3432 break;
3433 case FR30_OPERAND_DISP9 :
3434 fields->f_disp9 = value;
3435 break;
3436 case FR30_OPERAND_DISP10 :
3437 fields->f_disp10 = value;
3438 break;
3439 case FR30_OPERAND_S10 :
3440 fields->f_s10 = value;
3441 break;
3442 case FR30_OPERAND_U10 :
3443 fields->f_u10 = value;
3444 break;
3445 case FR30_OPERAND_I32 :
3446 fields->f_i32 = value;
3447 break;
3448 case FR30_OPERAND_M4 :
3449 fields->f_m4 = value;
3450 break;
3451 case FR30_OPERAND_I20 :
3452 fields->f_i20 = value;
3453 break;
3454 case FR30_OPERAND_LABEL9 :
3455 fields->f_rel9 = value;
3456 break;
3457 case FR30_OPERAND_DIR8 :
3458 fields->f_dir8 = value;
3459 break;
3460 case FR30_OPERAND_DIR9 :
3461 fields->f_dir9 = value;
3462 break;
3463 case FR30_OPERAND_DIR10 :
3464 fields->f_dir10 = value;
3465 break;
3466 case FR30_OPERAND_LABEL12 :
3467 fields->f_rel12 = value;
3468 break;
3469 case FR30_OPERAND_REGLIST_LOW :
3470 fields->f_reglist_low = value;
3471 break;
3472 case FR30_OPERAND_REGLIST_HI :
3473 fields->f_reglist_hi = value;
3474 break;
3475 case FR30_OPERAND_CC :
3476 fields->f_cc = value;
3477 break;
3478 case FR30_OPERAND_CCC :
3479 fields->f_ccc = value;
3480 break;
3481
3482 default :
3483 /* xgettext:c-format */
3484 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3485 opindex);
3486 abort ();
3487 }
3488 }
3489
GDB Binutils - Deliverables
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