opcodes/fr30-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS USED TO GENERATE fr30-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software Foundation, Inc.,
  22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "fr30-opc.h"
  31 #include "opintl.h"
  32
  33 /* The hash functions are recorded here to help keep assembler code out of
  34    the disassembler and vice versa.  */
  35
  36 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
  37 static unsigned int asm_hash_insn PARAMS ((const char *));
  38 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
  39 static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
  40
  41 /* Cover function to read and properly byteswap an insn value.  */
  42
  43 CGEN_INSN_INT
  44 cgen_get_insn_value (od, buf, length)
  45      CGEN_OPCODE_DESC od;
  46      unsigned char *buf;
  47      int length;
  48 {
  49   CGEN_INSN_INT value;
  50
  51   switch (length)
  52     {
  53     case 8:
  54       value = *buf;
  55       break;
  56     case 16:
  57       if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
  58         value = bfd_getb16 (buf);
  59       else
  60         value = bfd_getl16 (buf);
  61       break;
  62     case 32:
  63       if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
  64         value = bfd_getb32 (buf);
  65       else
  66         value = bfd_getl32 (buf);
  67       break;
  68     default:
  69       abort ();
  70     }
  71
  72   return value;
  73 }
  74
  75 /* Cover function to store an insn value properly byteswapped.  */
  76
  77 void
  78 cgen_put_insn_value (od, buf, length, value)
  79      CGEN_OPCODE_DESC od;
  80      unsigned char *buf;
  81      int length;
  82      CGEN_INSN_INT value;
  83 {
  84   switch (length)
  85     {
  86     case 8:
  87       buf[0] = value;
  88       break;
  89     case 16:
  90       if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
  91         bfd_putb16 (value, buf);
  92       else
  93         bfd_putl16 (value, buf);
  94       break;
  95     case 32:
  96       if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
  97         bfd_putb32 (value, buf);
  98       else
  99         bfd_putl32 (value, buf);
 100       break;
 101     default:
 102       abort ();
 103     }
 104 }
 105
 106 /* Look up instruction INSN_VALUE and extract its fields.
 107    INSN, if non-null, is the insn table entry.
 108    Otherwise INSN_VALUE is examined to compute it.
 109    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
 110    0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
 111    If INSN != NULL, LENGTH must be valid.
 112    ALIAS_P is non-zero if alias insns are to be included in the search.
 113
 114    The result a pointer to the insn table entry, or NULL if the instruction
 115    wasn't recognized.  */
 116
 117 const CGEN_INSN *
 118 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
 119      CGEN_OPCODE_DESC od;
 120      const CGEN_INSN *insn;
 121      CGEN_INSN_BYTES insn_value;
 122      int length;
 123      CGEN_FIELDS *fields;
 124      int alias_p;
 125 {
 126   unsigned char buf[16];
 127   unsigned char *bufp;
 128   unsigned int base_insn;
 129 #if CGEN_INT_INSN_P
 130   CGEN_EXTRACT_INFO *info = NULL;
 131 #else
 132   CGEN_EXTRACT_INFO ex_info;
 133   CGEN_EXTRACT_INFO *info = &ex_info;
 134 #endif
 135
 136 #if ! CGEN_INT_INSN_P
 137   ex_info.dis_info = NULL;
 138   ex_info.bytes = insn_value;
 139   ex_info.valid = -1;
 140 #endif
 141
 142   if (!insn)
 143     {
 144       const CGEN_INSN_LIST *insn_list;
 145
 146 #if CGEN_INT_INSN_P
 147       cgen_put_insn_value (od, buf, length, insn_value);
 148       bufp = buf;
 149       base_insn = insn_value; /*???*/
 150 #else
 151       base_insn = cgen_get_insn_value (od, buf, length);
 152       bufp = insn_value;
 153 #endif
 154
 155       /* The instructions are stored in hash lists.
 156          Pick the first one and keep trying until we find the right one.  */
 157
 158       insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
 159       while (insn_list != NULL)
 160         {
 161           insn = insn_list->insn;
 162
 163           if (alias_p
 164               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 165             {
 166               /* Basic bit mask must be correct.  */
 167               /* ??? May wish to allow target to defer this check until the
 168                  extract handler.  */
 169               if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
 170                 {
 171                   /* ??? 0 is passed for `pc' */
 172                   int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
 173                                                            insn_value, fields,
 174                                                            (bfd_vma) 0);
 175                   if (elength > 0)
 176                     {
 177                       /* sanity check */
 178                       if (length != 0 && length != elength)
 179                         abort ();
 180                       return insn;
 181                     }
 182                 }
 183             }
 184
 185           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 186         }
 187     }
 188   else
 189     {
 190       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 191       if (! alias_p
 192           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 193         abort ();
 194       /* Sanity check: length must be correct.  */
 195       if (length != CGEN_INSN_BITSIZE (insn))
 196         abort ();
 197
 198       /* ??? 0 is passed for `pc' */
 199       length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, insn_value, fields,
 200                                           (bfd_vma) 0);
 201       /* Sanity check: must succeed.
 202          Could relax this later if it ever proves useful.  */
 203       if (length == 0)
 204         abort ();
 205       return insn;
 206     }
 207
 208   return NULL;
 209 }
 210
 211 /* Fill in the operand instances used by INSN whose operands are FIELDS.
 212    INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
 213    in.  */
 214
 215 void
 216 fr30_cgen_get_insn_operands (od, insn, fields, indices)
 217      CGEN_OPCODE_DESC od;
 218      const CGEN_INSN * insn;
 219      const CGEN_FIELDS * fields;
 220      int *indices;
 221 {
 222   const CGEN_OPERAND_INSTANCE *opinst;
 223   int i;
 224
 225   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 226        opinst != NULL
 227          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 228        ++i, ++opinst)
 229     {
 230       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 231       if (op == NULL)
 232         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 233       else
 234         indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
 235                                                   fields);
 236     }
 237 }
 238
 239 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
 240    isn't known.
 241    The INSN, INSN_VALUE, and LENGTH arguments are passed to
 242    fr30_cgen_lookup_insn unchanged.
 243
 244    The result is the insn table entry or NULL if the instruction wasn't
 245    recognized.  */
 246
 247 const CGEN_INSN *
 248 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
 249      CGEN_OPCODE_DESC od;
 250      const CGEN_INSN *insn;
 251      CGEN_INSN_BYTES insn_value;
 252      int length;
 253      int *indices;
 254 {
 255   CGEN_FIELDS fields;
 256
 257   /* Pass non-zero for ALIAS_P only if INSN != NULL.
 258      If INSN == NULL, we want a real insn.  */
 259   insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
 260                                   insn != NULL);
 261   if (! insn)
 262     return NULL;
 263
 264   fr30_cgen_get_insn_operands (od, insn, &fields, indices);
 265   return insn;
 266 }
 267 /* Attributes.  */
 268
 269 static const CGEN_ATTR_ENTRY MACH_attr[] =
 270 {
 271   { "base", MACH_BASE },
 272   { "fr30", MACH_FR30 },
 273   { "max", MACH_MAX },
 274   { 0, 0 }
 275 };
 276
 277 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
 278 {
 279   { "CACHE-ADDR", NULL },
 280   { "PC", NULL },
 281   { "PROFILE", NULL },
 282   { 0, 0 }
 283 };
 284
 285 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
 286 {
 287   { "ABS-ADDR", NULL },
 288   { "HASH-PREFIX", NULL },
 289   { "NEGATIVE", NULL },
 290   { "PCREL-ADDR", NULL },
 291   { "RELAX", NULL },
 292   { "SEM-ONLY", NULL },
 293   { "SIGN-OPT", NULL },
 294   { "SIGNED", NULL },
 295   { "UNSIGNED", NULL },
 296   { 0, 0 }
 297 };
 298
 299 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
 300 {
 301   { "ALIAS", NULL },
 302   { "COND-CTI", NULL },
 303   { "NO-DIS", NULL },
 304   { "RELAX", NULL },
 305   { "RELAXABLE", NULL },
 306   { "SKIP-CTI", NULL },
 307   { "UNCOND-CTI", NULL },
 308   { "VIRTUAL", NULL },
 309   { 0, 0 }
 310 };
 311
 312 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
 313 {
 314   { "ac", 13 },
 315   { "fp", 14 },
 316   { "sp", 15 },
 317   { "r0", 0 },
 318   { "r1", 1 },
 319   { "r2", 2 },
 320   { "r3", 3 },
 321   { "r4", 4 },
 322   { "r5", 5 },
 323   { "r6", 6 },
 324   { "r7", 7 },
 325   { "r8", 8 },
 326   { "r9", 9 },
 327   { "r10", 10 },
 328   { "r11", 11 },
 329   { "r12", 12 },
 330   { "r13", 13 },
 331   { "r14", 14 },
 332   { "r15", 15 }
 333 };
 334
 335 CGEN_KEYWORD fr30_cgen_opval_h_gr =
 336 {
 337   & fr30_cgen_opval_h_gr_entries[0],
 338   19
 339 };
 340
 341 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
 342 {
 343   { "tbr", 0 },
 344   { "rp", 1 },
 345   { "ssp", 2 },
 346   { "usp", 3 },
 347   { "mdh", 4 },
 348   { "mdl", 5 }
 349 };
 350
 351 CGEN_KEYWORD fr30_cgen_opval_h_dr =
 352 {
 353   & fr30_cgen_opval_h_dr_entries[0],
 354   6
 355 };
 356
 357 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
 358 {
 359   { "pc", 0 },
 360   { "ps", 1 }
 361 };
 362
 363 CGEN_KEYWORD fr30_cgen_opval_h_cr =
 364 {
 365   & fr30_cgen_opval_h_cr_entries[0],
 366   2
 367 };
 368
 369
 370 /* The hardware table.  */
 371
 372 #define HW_ENT(n) fr30_cgen_hw_entries[n]
 373 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
 374 {
 375   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
 376   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 377   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 378   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 379   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 380   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 381   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
 382   { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0, { 0 } } },
 383   { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0, { 0 } } },
 384   { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 385   { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 386   { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 387   { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 388   { 0 }
 389 };
 390
 391 /* The operand table.  */
 392
 393 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
 394 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
 395
 396 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
 397 {
 398 /* pc: program counter */
 399   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 400     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 401 /* Ri: destination register */
 402   { "Ri", & HW_ENT (HW_H_GR), 12, 4,
 403     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 404 /* Rj: source register */
 405   { "Rj", & HW_ENT (HW_H_GR), 8, 4,
 406     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 407 /* Rs1: dedicated register */
 408   { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
 409     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 410 /* Rs2: dedicated register */
 411   { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
 412     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 413 /* ps: Program Status register */
 414   { "ps", & HW_ENT (HW_H_CR), 0, 0,
 415     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 416 /* u4: 4  bit unsigned immediate */
 417   { "u4", & HW_ENT (HW_H_UINT), 8, 4,
 418     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 419 /* m4: 4  bit negative immediate */
 420   { "m4", & HW_ENT (HW_H_UINT), 8, 4,
 421     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 422 /* i8: 8  bit unsigned immediate */
 423   { "i8", & HW_ENT (HW_H_UINT), 4, 8,
 424     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 425 /* u8: 8  bit unsigned immediate */
 426   { "u8", & HW_ENT (HW_H_UINT), 8, 8,
 427     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 428 /* o8: 8  bit signed   immediate */
 429   { "o8", & HW_ENT (HW_H_SINT), 4, 8,
 430     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 431 /* s10: 10 bit signed   immediate */
 432   { "s10", & HW_ENT (HW_H_SINT), 8, 8,
 433     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 434 /* u10: 10 bit unsigned immediate */
 435   { "u10", & HW_ENT (HW_H_UINT), 8, 8,
 436     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 437 /* dir8: 8  bit direct address */
 438   { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
 439     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 440 /* dir9: 9  bit direct address */
 441   { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
 442     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 443 /* dir10: 10 bit direct address */
 444   { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
 445     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 446 /* label9: 9  bit pc relative address */
 447   { "label9", & HW_ENT (HW_H_SINT), 8, 8,
 448     { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 449 /* label12: 12 bit pc relative address */
 450   { "label12", & HW_ENT (HW_H_SINT), 5, 11,
 451     { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 452 /* cc: condition codes */
 453   { "cc", & HW_ENT (HW_H_UINT), 4, 4,
 454     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 455 /* nbit: negative bit */
 456   { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
 457     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 458 /* vbit: overflow bit */
 459   { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
 460     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 461 /* zbit: zero     bit */
 462   { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
 463     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 464 /* cbit: carry    bit */
 465   { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
 466     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 467 };
 468
 469 /* Operand references.  */
 470
 471 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 472 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 473
 474 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
 475   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 476   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
 477   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
 478   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
 479   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 480   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
 481   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
 482   { 0 }
 483 };
 484
 485 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
 486   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 487   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0 },
 488   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
 489   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
 490   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 491   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
 492   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
 493   { 0 }
 494 };
 495
 496 static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
 497   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 498   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0 },
 499   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
 500   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
 501   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 502   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
 503   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
 504   { 0 }
 505 };
 506
 507 static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
 508   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 509   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
 510   { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
 511   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
 512   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
 513   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 514   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
 515   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
 516   { 0 }
 517 };
 518
 519 static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
 520   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 521   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
 522   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 523   { 0 }
 524 };
 525
 526 static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
 527   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 528   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0 },
 529   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 530   { 0 }
 531 };
 532
 533 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
 534   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 535   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0 },
 536   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 537   { 0 }
 538 };
 539
 540 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
 541   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 542   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
 543   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
 544   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
 545   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
 546   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
 547   { 0 }
 548 };
 549
 550 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
 551   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 552   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0 },
 553   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
 554   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
 555   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
 556   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
 557   { 0 }
 558 };
 559
 560 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
 561   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 562   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0 },
 563   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
 564   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
 565   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
 566   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
 567   { 0 }
 568 };
 569
 570 static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
 571   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 572   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
 573   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
 574   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
 575   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
 576   { 0 }
 577 };
 578
 579 static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
 580   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0 },
 581   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 582   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
 583   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
 584   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
 585   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 586   { 0 }
 587 };
 588
 589 static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
 590   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0 },
 591   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 592   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0 },
 593   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
 594   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
 595   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 596   { 0 }
 597 };
 598
 599 static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
 600   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0 },
 601   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 602   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0 },
 603   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
 604   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
 605   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 606   { 0 }
 607 };
 608
 609 #undef INPUT
 610 #undef OUTPUT
 611
 612 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
 613 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
 614 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 615
 616 /* The instruction table.
 617    This is currently non-static because the simulator accesses it
 618    directly.  */
 619
 620 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
 621 {
 622   /* Special null first entry.
 623      A `num' value of zero is thus invalid.
 624      Also, the special `invalid' insn resides here.  */
 625   { { 0 }, 0 },
 626 /* add $Rj,$Ri */
 627   {
 628     { 1, 1, 1, 1 },
 629     FR30_INSN_ADD, "add", "add",
 630     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 631     { 16, 16, 0xff00 }, 0xa600,
 632     (PTR) & fmt_add_ops[0],
 633     { 0, 0, { 0 } }
 634   },
 635 /* add $u4,$Ri */
 636   {
 637     { 1, 1, 1, 1 },
 638     FR30_INSN_ADDI, "addi", "add",
 639     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 640     { 16, 16, 0xff00 }, 0xa400,
 641     (PTR) & fmt_addi_ops[0],
 642     { 0, 0, { 0 } }
 643   },
 644 /* add2 $m4,$Ri */
 645   {
 646     { 1, 1, 1, 1 },
 647     FR30_INSN_ADD2, "add2", "add2",
 648     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 649     { 16, 16, 0xff00 }, 0xa500,
 650     (PTR) & fmt_add2_ops[0],
 651     { 0, 0, { 0 } }
 652   },
 653 /* addc $Rj,$Ri */
 654   {
 655     { 1, 1, 1, 1 },
 656     FR30_INSN_ADDC, "addc", "addc",
 657     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 658     { 16, 16, 0xff00 }, 0xa700,
 659     (PTR) & fmt_addc_ops[0],
 660     { 0, 0, { 0 } }
 661   },
 662 /* addn $Rj,$Ri */
 663   {
 664     { 1, 1, 1, 1 },
 665     FR30_INSN_ADDN, "addn", "addn",
 666     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 667     { 16, 16, 0xff00 }, 0xa200,
 668     (PTR) & fmt_addn_ops[0],
 669     { 0, 0, { 0 } }
 670   },
 671 /* addn $u4,$Ri */
 672   {
 673     { 1, 1, 1, 1 },
 674     FR30_INSN_ADDNI, "addni", "addn",
 675     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 676     { 16, 16, 0xff00 }, 0xa000,
 677     (PTR) & fmt_addni_ops[0],
 678     { 0, 0, { 0 } }
 679   },
 680 /* addn2 $m4,$Ri */
 681   {
 682     { 1, 1, 1, 1 },
 683     FR30_INSN_ADDN2, "addn2", "addn2",
 684     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 685     { 16, 16, 0xff00 }, 0xa100,
 686     (PTR) & fmt_addn2_ops[0],
 687     { 0, 0, { 0 } }
 688   },
 689 /* sub $Rj,$Ri */
 690   {
 691     { 1, 1, 1, 1 },
 692     FR30_INSN_SUB, "sub", "sub",
 693     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 694     { 16, 16, 0xff00 }, 0xac00,
 695     (PTR) & fmt_add_ops[0],
 696     { 0, 0, { 0 } }
 697   },
 698 /* subc $Rj,$Ri */
 699   {
 700     { 1, 1, 1, 1 },
 701     FR30_INSN_SUBC, "subc", "subc",
 702     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 703     { 16, 16, 0xff00 }, 0xad00,
 704     (PTR) & fmt_addc_ops[0],
 705     { 0, 0, { 0 } }
 706   },
 707 /* subn $Rj,$Ri */
 708   {
 709     { 1, 1, 1, 1 },
 710     FR30_INSN_SUBN, "subn", "subn",
 711     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 712     { 16, 16, 0xff00 }, 0xae00,
 713     (PTR) & fmt_addn_ops[0],
 714     { 0, 0, { 0 } }
 715   },
 716 /* cmp $Rj,$Ri */
 717   {
 718     { 1, 1, 1, 1 },
 719     FR30_INSN_CMP, "cmp", "cmp",
 720     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 721     { 16, 16, 0xff00 }, 0xaa00,
 722     (PTR) & fmt_cmp_ops[0],
 723     { 0, 0, { 0 } }
 724   },
 725 /* cmp $u4,$Ri */
 726   {
 727     { 1, 1, 1, 1 },
 728     FR30_INSN_CMPI, "cmpi", "cmp",
 729     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 730     { 16, 16, 0xff00 }, 0xa800,
 731     (PTR) & fmt_cmpi_ops[0],
 732     { 0, 0, { 0 } }
 733   },
 734 /* cmp2 $m4,$Ri */
 735   {
 736     { 1, 1, 1, 1 },
 737     FR30_INSN_CMP2, "cmp2", "cmp2",
 738     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 739     { 16, 16, 0xff00 }, 0xa900,
 740     (PTR) & fmt_cmp2_ops[0],
 741     { 0, 0, { 0 } }
 742   },
 743 /* and $Rj,$Ri */
 744   {
 745     { 1, 1, 1, 1 },
 746     FR30_INSN_AND, "and", "and",
 747     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 748     { 16, 16, 0xff00 }, 0x8200,
 749     (PTR) & fmt_and_ops[0],
 750     { 0, 0, { 0 } }
 751   },
 752 /* or $Rj,$Ri */
 753   {
 754     { 1, 1, 1, 1 },
 755     FR30_INSN_OR, "or", "or",
 756     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 757     { 16, 16, 0xff00 }, 0x9200,
 758     (PTR) & fmt_and_ops[0],
 759     { 0, 0, { 0 } }
 760   },
 761 /* eor $Rj,$Ri */
 762   {
 763     { 1, 1, 1, 1 },
 764     FR30_INSN_EOR, "eor", "eor",
 765     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 766     { 16, 16, 0xff00 }, 0x9a00,
 767     (PTR) & fmt_and_ops[0],
 768     { 0, 0, { 0 } }
 769   },
 770 /* and $Rj,@$Ri */
 771   {
 772     { 1, 1, 1, 1 },
 773     FR30_INSN_ANDM, "andm", "and",
 774     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 775     { 16, 16, 0xff00 }, 0x8400,
 776     (PTR) & fmt_andm_ops[0],
 777     { 0, 0, { 0 } }
 778   },
 779 /* andh $Rj,@$Ri */
 780   {
 781     { 1, 1, 1, 1 },
 782     FR30_INSN_ANDH, "andh", "andh",
 783     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 784     { 16, 16, 0xff00 }, 0x8500,
 785     (PTR) & fmt_andh_ops[0],
 786     { 0, 0, { 0 } }
 787   },
 788 /* andb $Rj,@$Ri */
 789   {
 790     { 1, 1, 1, 1 },
 791     FR30_INSN_ANDB, "andb", "andb",
 792     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 793     { 16, 16, 0xff00 }, 0x8600,
 794     (PTR) & fmt_andb_ops[0],
 795     { 0, 0, { 0 } }
 796   },
 797 /* or $Rj,@$Ri */
 798   {
 799     { 1, 1, 1, 1 },
 800     FR30_INSN_ORM, "orm", "or",
 801     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 802     { 16, 16, 0xff00 }, 0x9400,
 803     (PTR) & fmt_andm_ops[0],
 804     { 0, 0, { 0 } }
 805   },
 806 /* orh $Rj,@$Ri */
 807   {
 808     { 1, 1, 1, 1 },
 809     FR30_INSN_ORH, "orh", "orh",
 810     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 811     { 16, 16, 0xff00 }, 0x9500,
 812     (PTR) & fmt_andh_ops[0],
 813     { 0, 0, { 0 } }
 814   },
 815 /* orb $Rj,@$Ri */
 816   {
 817     { 1, 1, 1, 1 },
 818     FR30_INSN_ORB, "orb", "orb",
 819     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 820     { 16, 16, 0xff00 }, 0x9600,
 821     (PTR) & fmt_andb_ops[0],
 822     { 0, 0, { 0 } }
 823   },
 824 /* eor $Rj,@$Ri */
 825   {
 826     { 1, 1, 1, 1 },
 827     FR30_INSN_EORM, "eorm", "eor",
 828     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 829     { 16, 16, 0xff00 }, 0x9c00,
 830     (PTR) & fmt_andm_ops[0],
 831     { 0, 0, { 0 } }
 832   },
 833 /* eorh $Rj,@$Ri */
 834   {
 835     { 1, 1, 1, 1 },
 836     FR30_INSN_EORH, "eorh", "eorh",
 837     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 838     { 16, 16, 0xff00 }, 0x9d00,
 839     (PTR) & fmt_andh_ops[0],
 840     { 0, 0, { 0 } }
 841   },
 842 /* eorb $Rj,@$Ri */
 843   {
 844     { 1, 1, 1, 1 },
 845     FR30_INSN_EORB, "eorb", "eorb",
 846     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 847     { 16, 16, 0xff00 }, 0x9e00,
 848     (PTR) & fmt_andb_ops[0],
 849     { 0, 0, { 0 } }
 850   },
 851 /* bandl $u4,@$Ri */
 852   {
 853     { 1, 1, 1, 1 },
 854     FR30_INSN_BANDL, "bandl", "bandl",
 855     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 856     { 16, 16, 0xff00 }, 0x8000,
 857     (PTR) 0,
 858     { 0, 0, { 0 } }
 859   },
 860 /* borl $u4,@$Ri */
 861   {
 862     { 1, 1, 1, 1 },
 863     FR30_INSN_BORL, "borl", "borl",
 864     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 865     { 16, 16, 0xff00 }, 0x9000,
 866     (PTR) 0,
 867     { 0, 0, { 0 } }
 868   },
 869 /* beorl $u4,@$Ri */
 870   {
 871     { 1, 1, 1, 1 },
 872     FR30_INSN_BEORL, "beorl", "beorl",
 873     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 874     { 16, 16, 0xff00 }, 0x9800,
 875     (PTR) 0,
 876     { 0, 0, { 0 } }
 877   },
 878 /* bandh $u4,@$Ri */
 879   {
 880     { 1, 1, 1, 1 },
 881     FR30_INSN_BANDH, "bandh", "bandh",
 882     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 883     { 16, 16, 0xff00 }, 0x8100,
 884     (PTR) 0,
 885     { 0, 0, { 0 } }
 886   },
 887 /* borh $u4,@$Ri */
 888   {
 889     { 1, 1, 1, 1 },
 890     FR30_INSN_BORH, "borh", "borh",
 891     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 892     { 16, 16, 0xff00 }, 0x9100,
 893     (PTR) 0,
 894     { 0, 0, { 0 } }
 895   },
 896 /* beorh $u4,@$Ri */
 897   {
 898     { 1, 1, 1, 1 },
 899     FR30_INSN_BEORH, "beorh", "beorh",
 900     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 901     { 16, 16, 0xff00 }, 0x9900,
 902     (PTR) 0,
 903     { 0, 0, { 0 } }
 904   },
 905 /* btstl $u4,@$Ri */
 906   {
 907     { 1, 1, 1, 1 },
 908     FR30_INSN_BTSTL, "btstl", "btstl",
 909     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 910     { 16, 16, 0xff00 }, 0x8800,
 911     (PTR) 0,
 912     { 0, 0, { 0 } }
 913   },
 914 /* btsth $u4,@$Ri */
 915   {
 916     { 1, 1, 1, 1 },
 917     FR30_INSN_BTSTH, "btsth", "btsth",
 918     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 919     { 16, 16, 0xff00 }, 0x8900,
 920     (PTR) 0,
 921     { 0, 0, { 0 } }
 922   },
 923 /* mul $Rj,$Ri */
 924   {
 925     { 1, 1, 1, 1 },
 926     FR30_INSN_MUL, "mul", "mul",
 927     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 928     { 16, 16, 0xff00 }, 0xaf00,
 929     (PTR) 0,
 930     { 0, 0, { 0 } }
 931   },
 932 /* mulu $Rj,$Ri */
 933   {
 934     { 1, 1, 1, 1 },
 935     FR30_INSN_MULU, "mulu", "mulu",
 936     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 937     { 16, 16, 0xff00 }, 0xab00,
 938     (PTR) 0,
 939     { 0, 0, { 0 } }
 940   },
 941 /* mulh $Rj,$Ri */
 942   {
 943     { 1, 1, 1, 1 },
 944     FR30_INSN_MULH, "mulh", "mulh",
 945     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 946     { 16, 16, 0xff00 }, 0xbf00,
 947     (PTR) 0,
 948     { 0, 0, { 0 } }
 949   },
 950 /* muluh $Rj,$Ri */
 951   {
 952     { 1, 1, 1, 1 },
 953     FR30_INSN_MULUH, "muluh", "muluh",
 954     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 955     { 16, 16, 0xff00 }, 0xbb00,
 956     (PTR) 0,
 957     { 0, 0, { 0 } }
 958   },
 959 /* div0s $Ri */
 960   {
 961     { 1, 1, 1, 1 },
 962     FR30_INSN_DIV0S, "div0s", "div0s",
 963     { { MNEM, ' ', OP (RI), 0 } },
 964     { 16, 16, 0xfff0 }, 0x9740,
 965     (PTR) 0,
 966     { 0, 0, { 0 } }
 967   },
 968 /* div0u $Ri */
 969   {
 970     { 1, 1, 1, 1 },
 971     FR30_INSN_DIV0U, "div0u", "div0u",
 972     { { MNEM, ' ', OP (RI), 0 } },
 973     { 16, 16, 0xfff0 }, 0x9750,
 974     (PTR) 0,
 975     { 0, 0, { 0 } }
 976   },
 977 /* div1 $Ri */
 978   {
 979     { 1, 1, 1, 1 },
 980     FR30_INSN_DIV1, "div1", "div1",
 981     { { MNEM, ' ', OP (RI), 0 } },
 982     { 16, 16, 0xfff0 }, 0x9760,
 983     (PTR) 0,
 984     { 0, 0, { 0 } }
 985   },
 986 /* div2 $Ri */
 987   {
 988     { 1, 1, 1, 1 },
 989     FR30_INSN_DIV2, "div2", "div2",
 990     { { MNEM, ' ', OP (RI), 0 } },
 991     { 16, 16, 0xfff0 }, 0x9770,
 992     (PTR) 0,
 993     { 0, 0, { 0 } }
 994   },
 995 /* div3 */
 996   {
 997     { 1, 1, 1, 1 },
 998     FR30_INSN_DIV3, "div3", "div3",
 999     { { MNEM, 0 } },
1000     { 16, 16, 0xffff }, 0x9f60,
1001     (PTR) 0,
1002     { 0, 0, { 0 } }
1003   },
1004 /* div4s */
1005   {
1006     { 1, 1, 1, 1 },
1007     FR30_INSN_DIV4S, "div4s", "div4s",
1008     { { MNEM, 0 } },
1009     { 16, 16, 0xffff }, 0x9f70,
1010     (PTR) 0,
1011     { 0, 0, { 0 } }
1012   },
1013 /* lsl $Rj,$Ri */
1014   {
1015     { 1, 1, 1, 1 },
1016     FR30_INSN_LSL, "lsl", "lsl",
1017     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1018     { 16, 16, 0xff00 }, 0xb600,
1019     (PTR) 0,
1020     { 0, 0, { 0 } }
1021   },
1022 /* lsl $u4,$Ri */
1023   {
1024     { 1, 1, 1, 1 },
1025     FR30_INSN_LSLI, "lsli", "lsl",
1026     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1027     { 16, 16, 0xff00 }, 0xb400,
1028     (PTR) 0,
1029     { 0, 0, { 0 } }
1030   },
1031 /* lsl2 $u4,$Ri */
1032   {
1033     { 1, 1, 1, 1 },
1034     FR30_INSN_LSL2, "lsl2", "lsl2",
1035     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1036     { 16, 16, 0xff00 }, 0xb500,
1037     (PTR) 0,
1038     { 0, 0, { 0 } }
1039   },
1040 /* lsr $Rj,$Ri */
1041   {
1042     { 1, 1, 1, 1 },
1043     FR30_INSN_LSR, "lsr", "lsr",
1044     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1045     { 16, 16, 0xff00 }, 0xb200,
1046     (PTR) 0,
1047     { 0, 0, { 0 } }
1048   },
1049 /* lsr $u4,$Ri */
1050   {
1051     { 1, 1, 1, 1 },
1052     FR30_INSN_LSRI, "lsri", "lsr",
1053     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1054     { 16, 16, 0xff00 }, 0xb000,
1055     (PTR) 0,
1056     { 0, 0, { 0 } }
1057   },
1058 /* lsr2 $u4,$Ri */
1059   {
1060     { 1, 1, 1, 1 },
1061     FR30_INSN_LSR2, "lsr2", "lsr2",
1062     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1063     { 16, 16, 0xff00 }, 0xb100,
1064     (PTR) 0,
1065     { 0, 0, { 0 } }
1066   },
1067 /* asr $Rj,$Ri */
1068   {
1069     { 1, 1, 1, 1 },
1070     FR30_INSN_ASR, "asr", "asr",
1071     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1072     { 16, 16, 0xff00 }, 0xba00,
1073     (PTR) 0,
1074     { 0, 0, { 0 } }
1075   },
1076 /* asr $u4,$Ri */
1077   {
1078     { 1, 1, 1, 1 },
1079     FR30_INSN_ASRI, "asri", "asr",
1080     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1081     { 16, 16, 0xff00 }, 0xb800,
1082     (PTR) 0,
1083     { 0, 0, { 0 } }
1084   },
1085 /* asr2 $u4,$Ri */
1086   {
1087     { 1, 1, 1, 1 },
1088     FR30_INSN_ASR2, "asr2", "asr2",
1089     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1090     { 16, 16, 0xff00 }, 0xb900,
1091     (PTR) 0,
1092     { 0, 0, { 0 } }
1093   },
1094 /* ldi:8 $i8,$Ri */
1095   {
1096     { 1, 1, 1, 1 },
1097     FR30_INSN_LDI_8, "ldi:8", "ldi:8",
1098     { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
1099     { 16, 16, 0xf000 }, 0xc000,
1100     (PTR) 0,
1101     { 0, 0, { 0 } }
1102   },
1103 /* ld @$Rj,$Ri */
1104   {
1105     { 1, 1, 1, 1 },
1106     FR30_INSN_LD, "ld", "ld",
1107     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1108     { 16, 16, 0xff00 }, 0x400,
1109     (PTR) 0,
1110     { 0, 0, { 0 } }
1111   },
1112 /* lduh @$Rj,$Ri */
1113   {
1114     { 1, 1, 1, 1 },
1115     FR30_INSN_LDUH, "lduh", "lduh",
1116     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1117     { 16, 16, 0xff00 }, 0x500,
1118     (PTR) 0,
1119     { 0, 0, { 0 } }
1120   },
1121 /* ldub @$Rj,$Ri */
1122   {
1123     { 1, 1, 1, 1 },
1124     FR30_INSN_LDUB, "ldub", "ldub",
1125     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1126     { 16, 16, 0xff00 }, 0x600,
1127     (PTR) 0,
1128     { 0, 0, { 0 } }
1129   },
1130 /* ld @(R13,$Rj),$Ri */
1131   {
1132     { 1, 1, 1, 1 },
1133     FR30_INSN_LDR13, "ldr13", "ld",
1134     { { MNEM, ' ', '@', '(', 'R', '1', '3', ',', OP (RJ), ')', ',', OP (RI), 0 } },
1135     { 16, 16, 0xff00 }, 0x0,
1136     (PTR) 0,
1137     { 0, 0, { 0 } }
1138   },
1139 /* lduh @(R13,$Rj),$Ri */
1140   {
1141     { 1, 1, 1, 1 },
1142     FR30_INSN_LDR13UH, "ldr13uh", "lduh",
1143     { { MNEM, ' ', '@', '(', 'R', '1', '3', ',', OP (RJ), ')', ',', OP (RI), 0 } },
1144     { 16, 16, 0xff00 }, 0x100,
1145     (PTR) 0,
1146     { 0, 0, { 0 } }
1147   },
1148 /* ldub @(R13,$Rj),$Ri */
1149   {
1150     { 1, 1, 1, 1 },
1151     FR30_INSN_LDR13UB, "ldr13ub", "ldub",
1152     { { MNEM, ' ', '@', '(', 'R', '1', '3', ',', OP (RJ), ')', ',', OP (RI), 0 } },
1153     { 16, 16, 0xff00 }, 0x200,
1154     (PTR) 0,
1155     { 0, 0, { 0 } }
1156   },
1157 /* ld @(R14,$o8),$Ri */
1158   {
1159     { 1, 1, 1, 1 },
1160     FR30_INSN_LDR14, "ldr14", "ld",
1161     { { MNEM, ' ', '@', '(', 'R', '1', '4', ',', OP (O8), ')', ',', OP (RI), 0 } },
1162     { 16, 16, 0xf000 }, 0x2000,
1163     (PTR) 0,
1164     { 0, 0, { 0 } }
1165   },
1166 /* lduh @(R14,$o8),$Ri */
1167   {
1168     { 1, 1, 1, 1 },
1169     FR30_INSN_LDR14UH, "ldr14uh", "lduh",
1170     { { MNEM, ' ', '@', '(', 'R', '1', '4', ',', OP (O8), ')', ',', OP (RI), 0 } },
1171     { 16, 16, 0xf000 }, 0x4000,
1172     (PTR) 0,
1173     { 0, 0, { 0 } }
1174   },
1175 /* ldub @(R14,$o8),$Ri */
1176   {
1177     { 1, 1, 1, 1 },
1178     FR30_INSN_LDR14UB, "ldr14ub", "ldub",
1179     { { MNEM, ' ', '@', '(', 'R', '1', '4', ',', OP (O8), ')', ',', OP (RI), 0 } },
1180     { 16, 16, 0xf000 }, 0x6000,
1181     (PTR) 0,
1182     { 0, 0, { 0 } }
1183   },
1184 /* ld @(R15,$u4),$Ri */
1185   {
1186     { 1, 1, 1, 1 },
1187     FR30_INSN_LDR15, "ldr15", "ld",
1188     { { MNEM, ' ', '@', '(', 'R', '1', '5', ',', OP (U4), ')', ',', OP (RI), 0 } },
1189     { 16, 16, 0xff00 }, 0x300,
1190     (PTR) 0,
1191     { 0, 0, { 0 } }
1192   },
1193 /* ld @R15+,$Ri */
1194   {
1195     { 1, 1, 1, 1 },
1196     FR30_INSN_LDR15GR, "ldr15gr", "ld",
1197     { { MNEM, ' ', '@', 'R', '1', '5', '+', ',', OP (RI), 0 } },
1198     { 16, 16, 0xfff0 }, 0x700,
1199     (PTR) 0,
1200     { 0, 0, { 0 } }
1201   },
1202 /* ld @R15+,$Rs2 */
1203   {
1204     { 1, 1, 1, 1 },
1205     FR30_INSN_LDR15DR, "ldr15dr", "ld",
1206     { { MNEM, ' ', '@', 'R', '1', '5', '+', ',', OP (RS2), 0 } },
1207     { 16, 16, 0xfff0 }, 0x780,
1208     (PTR) 0,
1209     { 0, 0, { 0 } }
1210   },
1211 /* ld @R15+,ps */
1212   {
1213     { 1, 1, 1, 1 },
1214     FR30_INSN_LDR15PS, "ldr15ps", "ld",
1215     { { MNEM, ' ', '@', 'R', '1', '5', '+', ',', 'p', 's', 0 } },
1216     { 16, 16, 0xffff }, 0x790,
1217     (PTR) 0,
1218     { 0, 0, { 0 } }
1219   },
1220 /* st $Ri,@Rj */
1221   {
1222     { 1, 1, 1, 1 },
1223     FR30_INSN_ST, "st", "st",
1224     { { MNEM, ' ', OP (RI), ',', '@', 'R', 'j', 0 } },
1225     { 16, 16, 0xff00 }, 0x1400,
1226     (PTR) 0,
1227     { 0, 0, { 0 } }
1228   },
1229 /* sth $Ri,@Rj */
1230   {
1231     { 1, 1, 1, 1 },
1232     FR30_INSN_STH, "sth", "sth",
1233     { { MNEM, ' ', OP (RI), ',', '@', 'R', 'j', 0 } },
1234     { 16, 16, 0xff00 }, 0x1500,
1235     (PTR) 0,
1236     { 0, 0, { 0 } }
1237   },
1238 /* stb $Ri,@Rj */
1239   {
1240     { 1, 1, 1, 1 },
1241     FR30_INSN_STB, "stb", "stb",
1242     { { MNEM, ' ', OP (RI), ',', '@', 'R', 'j', 0 } },
1243     { 16, 16, 0xff00 }, 0x1600,
1244     (PTR) 0,
1245     { 0, 0, { 0 } }
1246   },
1247 /* st $Ri,@(R13,$Rj) */
1248   {
1249     { 1, 1, 1, 1 },
1250     FR30_INSN_STR13, "str13", "st",
1251     { { MNEM, ' ', OP (RI), ',', '@', '(', 'R', '1', '3', ',', OP (RJ), ')', 0 } },
1252     { 16, 16, 0xff00 }, 0x1000,
1253     (PTR) 0,
1254     { 0, 0, { 0 } }
1255   },
1256 /* sth $Ri,@(R13,$Rj) */
1257   {
1258     { 1, 1, 1, 1 },
1259     FR30_INSN_STR13H, "str13h", "sth",
1260     { { MNEM, ' ', OP (RI), ',', '@', '(', 'R', '1', '3', ',', OP (RJ), ')', 0 } },
1261     { 16, 16, 0xff00 }, 0x1100,
1262     (PTR) 0,
1263     { 0, 0, { 0 } }
1264   },
1265 /* stb $Ri,@(R13,$Rj) */
1266   {
1267     { 1, 1, 1, 1 },
1268     FR30_INSN_STR13B, "str13b", "stb",
1269     { { MNEM, ' ', OP (RI), ',', '@', '(', 'R', '1', '3', ',', OP (RJ), ')', 0 } },
1270     { 16, 16, 0xff00 }, 0x1200,
1271     (PTR) 0,
1272     { 0, 0, { 0 } }
1273   },
1274 /* st $Ri,@(R14,$o8) */
1275   {
1276     { 1, 1, 1, 1 },
1277     FR30_INSN_STR14, "str14", "st",
1278     { { MNEM, ' ', OP (RI), ',', '@', '(', 'R', '1', '4', ',', OP (O8), ')', 0 } },
1279     { 16, 16, 0xf000 }, 0x3000,
1280     (PTR) 0,
1281     { 0, 0, { 0 } }
1282   },
1283 /* sth $Ri,@(R14,$o8) */
1284   {
1285     { 1, 1, 1, 1 },
1286     FR30_INSN_STR14H, "str14h", "sth",
1287     { { MNEM, ' ', OP (RI), ',', '@', '(', 'R', '1', '4', ',', OP (O8), ')', 0 } },
1288     { 16, 16, 0xf000 }, 0x5000,
1289     (PTR) 0,
1290     { 0, 0, { 0 } }
1291   },
1292 /* stb $Ri,@(R14,$o8) */
1293   {
1294     { 1, 1, 1, 1 },
1295     FR30_INSN_STR14B, "str14b", "stb",
1296     { { MNEM, ' ', OP (RI), ',', '@', '(', 'R', '1', '4', ',', OP (O8), ')', 0 } },
1297     { 16, 16, 0xf000 }, 0x7000,
1298     (PTR) 0,
1299     { 0, 0, { 0 } }
1300   },
1301 /* st $Ri,@(R15,$u4) */
1302   {
1303     { 1, 1, 1, 1 },
1304     FR30_INSN_STR15, "str15", "st",
1305     { { MNEM, ' ', OP (RI), ',', '@', '(', 'R', '1', '5', ',', OP (U4), ')', 0 } },
1306     { 16, 16, 0xff00 }, 0x1300,
1307     (PTR) 0,
1308     { 0, 0, { 0 } }
1309   },
1310 /* st $Ri,@-R15 */
1311   {
1312     { 1, 1, 1, 1 },
1313     FR30_INSN_STR15GR, "str15gr", "st",
1314     { { MNEM, ' ', OP (RI), ',', '@', '-', 'R', '1', '5', 0 } },
1315     { 16, 16, 0xfff0 }, 0x1700,
1316     (PTR) 0,
1317     { 0, 0, { 0 } }
1318   },
1319 /* st $Rs2,@-R15 */
1320   {
1321     { 1, 1, 1, 1 },
1322     FR30_INSN_STR15DR, "str15dr", "st",
1323     { { MNEM, ' ', OP (RS2), ',', '@', '-', 'R', '1', '5', 0 } },
1324     { 16, 16, 0xfff0 }, 0x1780,
1325     (PTR) 0,
1326     { 0, 0, { 0 } }
1327   },
1328 /* st ps,@-R15 */
1329   {
1330     { 1, 1, 1, 1 },
1331     FR30_INSN_STR15PS, "str15ps", "st",
1332     { { MNEM, ' ', 'p', 's', ',', '@', '-', 'R', '1', '5', 0 } },
1333     { 16, 16, 0xffff }, 0x1790,
1334     (PTR) 0,
1335     { 0, 0, { 0 } }
1336   },
1337 /* mov $Rj,$Ri */
1338   {
1339     { 1, 1, 1, 1 },
1340     FR30_INSN_MOV, "mov", "mov",
1341     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1342     { 16, 16, 0xff00 }, 0x8b00,
1343     (PTR) 0,
1344     { 0, 0, { 0 } }
1345   },
1346 /* mov $Rs1,$Ri */
1347   {
1348     { 1, 1, 1, 1 },
1349     FR30_INSN_MOVDR, "movdr", "mov",
1350     { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
1351     { 16, 16, 0xff00 }, 0xb700,
1352     (PTR) 0,
1353     { 0, 0, { 0 } }
1354   },
1355 /* mov ps,$Ri */
1356   {
1357     { 1, 1, 1, 1 },
1358     FR30_INSN_MOVPS, "movps", "mov",
1359     { { MNEM, ' ', 'p', 's', ',', OP (RI), 0 } },
1360     { 16, 16, 0xfff0 }, 0x1710,
1361     (PTR) 0,
1362     { 0, 0, { 0 } }
1363   },
1364 /* mov $Ri,$Rs1 */
1365   {
1366     { 1, 1, 1, 1 },
1367     FR30_INSN_MOV2DR, "mov2dr", "mov",
1368     { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
1369     { 16, 16, 0xff00 }, 0xb300,
1370     (PTR) 0,
1371     { 0, 0, { 0 } }
1372   },
1373 /* mov $Ri,ps */
1374   {
1375     { 1, 1, 1, 1 },
1376     FR30_INSN_MOV2PS, "mov2ps", "mov",
1377     { { MNEM, ' ', OP (RI), ',', 'p', 's', 0 } },
1378     { 16, 16, 0xfff0 }, 0x710,
1379     (PTR) 0,
1380     { 0, 0, { 0 } }
1381   },
1382 /* jmp @$Ri */
1383   {
1384     { 1, 1, 1, 1 },
1385     FR30_INSN_JMP, "jmp", "jmp",
1386     { { MNEM, ' ', '@', OP (RI), 0 } },
1387     { 16, 16, 0xfff0 }, 0x9700,
1388     (PTR) 0,
1389     { 0, 0, { 0 } }
1390   },
1391 /* call $label12 */
1392   {
1393     { 1, 1, 1, 1 },
1394     FR30_INSN_CALL, "call", "call",
1395     { { MNEM, ' ', OP (LABEL12), 0 } },
1396     { 16, 16, 0xf400 }, 0xd000,
1397     (PTR) 0,
1398     { 0, 0, { 0 } }
1399   },
1400 /* call @$Ri */
1401   {
1402     { 1, 1, 1, 1 },
1403     FR30_INSN_CALLR, "callr", "call",
1404     { { MNEM, ' ', '@', OP (RI), 0 } },
1405     { 16, 16, 0xfff0 }, 0x9710,
1406     (PTR) 0,
1407     { 0, 0, { 0 } }
1408   },
1409 /* ret */
1410   {
1411     { 1, 1, 1, 1 },
1412     FR30_INSN_RET, "ret", "ret",
1413     { { MNEM, 0 } },
1414     { 16, 16, 0xffff }, 0x9720,
1415     (PTR) 0,
1416     { 0, 0, { 0 } }
1417   },
1418 /* int $u8 */
1419   {
1420     { 1, 1, 1, 1 },
1421     FR30_INSN_INT, "int", "int",
1422     { { MNEM, ' ', OP (U8), 0 } },
1423     { 16, 16, 0xff00 }, 0x1f00,
1424     (PTR) 0,
1425     { 0, 0, { 0 } }
1426   },
1427 /* int3 */
1428   {
1429     { 1, 1, 1, 1 },
1430     FR30_INSN_INTE, "inte", "int3",
1431     { { MNEM, 0 } },
1432     { 16, 16, 0xffff }, 0x9f30,
1433     (PTR) 0,
1434     { 0, 0, { 0 } }
1435   },
1436 /* reti */
1437   {
1438     { 1, 1, 1, 1 },
1439     FR30_INSN_RETI, "reti", "reti",
1440     { { MNEM, 0 } },
1441     { 16, 16, 0xffff }, 0x9730,
1442     (PTR) 0,
1443     { 0, 0, { 0 } }
1444   },
1445 /* bra:D $label9 */
1446   {
1447     { 1, 1, 1, 1 },
1448     FR30_INSN_BRA, "bra", "bra:D",
1449     { { MNEM, ' ', OP (LABEL9), 0 } },
1450     { 16, 16, 0xff00 }, 0xe000,
1451     (PTR) 0,
1452     { 0, 0, { 0 } }
1453   },
1454 /* bno:D $label9 */
1455   {
1456     { 1, 1, 1, 1 },
1457     FR30_INSN_BNO, "bno", "bno:D",
1458     { { MNEM, ' ', OP (LABEL9), 0 } },
1459     { 16, 16, 0xff00 }, 0xe100,
1460     (PTR) 0,
1461     { 0, 0, { 0 } }
1462   },
1463 /* beq:D $label9 */
1464   {
1465     { 1, 1, 1, 1 },
1466     FR30_INSN_BEQ, "beq", "beq:D",
1467     { { MNEM, ' ', OP (LABEL9), 0 } },
1468     { 16, 16, 0xff00 }, 0xe200,
1469     (PTR) 0,
1470     { 0, 0, { 0 } }
1471   },
1472 /* bne:D $label9 */
1473   {
1474     { 1, 1, 1, 1 },
1475     FR30_INSN_BNE, "bne", "bne:D",
1476     { { MNEM, ' ', OP (LABEL9), 0 } },
1477     { 16, 16, 0xff00 }, 0xe300,
1478     (PTR) 0,
1479     { 0, 0, { 0 } }
1480   },
1481 /* bc:D $label9 */
1482   {
1483     { 1, 1, 1, 1 },
1484     FR30_INSN_BC, "bc", "bc:D",
1485     { { MNEM, ' ', OP (LABEL9), 0 } },
1486     { 16, 16, 0xff00 }, 0xe400,
1487     (PTR) 0,
1488     { 0, 0, { 0 } }
1489   },
1490 /* bnc:D $label9 */
1491   {
1492     { 1, 1, 1, 1 },
1493     FR30_INSN_BNC, "bnc", "bnc:D",
1494     { { MNEM, ' ', OP (LABEL9), 0 } },
1495     { 16, 16, 0xff00 }, 0xe500,
1496     (PTR) 0,
1497     { 0, 0, { 0 } }
1498   },
1499 /* bn:D $label9 */
1500   {
1501     { 1, 1, 1, 1 },
1502     FR30_INSN_BN, "bn", "bn:D",
1503     { { MNEM, ' ', OP (LABEL9), 0 } },
1504     { 16, 16, 0xff00 }, 0xe600,
1505     (PTR) 0,
1506     { 0, 0, { 0 } }
1507   },
1508 /* bp:D $label9 */
1509   {
1510     { 1, 1, 1, 1 },
1511     FR30_INSN_BP, "bp", "bp:D",
1512     { { MNEM, ' ', OP (LABEL9), 0 } },
1513     { 16, 16, 0xff00 }, 0xe700,
1514     (PTR) 0,
1515     { 0, 0, { 0 } }
1516   },
1517 /* bv:D $label9 */
1518   {
1519     { 1, 1, 1, 1 },
1520     FR30_INSN_BV, "bv", "bv:D",
1521     { { MNEM, ' ', OP (LABEL9), 0 } },
1522     { 16, 16, 0xff00 }, 0xe800,
1523     (PTR) 0,
1524     { 0, 0, { 0 } }
1525   },
1526 /* bnv:D $label9 */
1527   {
1528     { 1, 1, 1, 1 },
1529     FR30_INSN_BNV, "bnv", "bnv:D",
1530     { { MNEM, ' ', OP (LABEL9), 0 } },
1531     { 16, 16, 0xff00 }, 0xe900,
1532     (PTR) 0,
1533     { 0, 0, { 0 } }
1534   },
1535 /* blt:D $label9 */
1536   {
1537     { 1, 1, 1, 1 },
1538     FR30_INSN_BLT, "blt", "blt:D",
1539     { { MNEM, ' ', OP (LABEL9), 0 } },
1540     { 16, 16, 0xff00 }, 0xea00,
1541     (PTR) 0,
1542     { 0, 0, { 0 } }
1543   },
1544 /* bge:D $label9 */
1545   {
1546     { 1, 1, 1, 1 },
1547     FR30_INSN_BGE, "bge", "bge:D",
1548     { { MNEM, ' ', OP (LABEL9), 0 } },
1549     { 16, 16, 0xff00 }, 0xeb00,
1550     (PTR) 0,
1551     { 0, 0, { 0 } }
1552   },
1553 /* ble:D $label9 */
1554   {
1555     { 1, 1, 1, 1 },
1556     FR30_INSN_BLE, "ble", "ble:D",
1557     { { MNEM, ' ', OP (LABEL9), 0 } },
1558     { 16, 16, 0xff00 }, 0xec00,
1559     (PTR) 0,
1560     { 0, 0, { 0 } }
1561   },
1562 /* bgt:D $label9 */
1563   {
1564     { 1, 1, 1, 1 },
1565     FR30_INSN_BGT, "bgt", "bgt:D",
1566     { { MNEM, ' ', OP (LABEL9), 0 } },
1567     { 16, 16, 0xff00 }, 0xed00,
1568     (PTR) 0,
1569     { 0, 0, { 0 } }
1570   },
1571 /* bls:D $label9 */
1572   {
1573     { 1, 1, 1, 1 },
1574     FR30_INSN_BLS, "bls", "bls:D",
1575     { { MNEM, ' ', OP (LABEL9), 0 } },
1576     { 16, 16, 0xff00 }, 0xee00,
1577     (PTR) 0,
1578     { 0, 0, { 0 } }
1579   },
1580 /* bhi:D $label9 */
1581   {
1582     { 1, 1, 1, 1 },
1583     FR30_INSN_BHI, "bhi", "bhi:D",
1584     { { MNEM, ' ', OP (LABEL9), 0 } },
1585     { 16, 16, 0xff00 }, 0xef00,
1586     (PTR) 0,
1587     { 0, 0, { 0 } }
1588   },
1589 /* dmov @$dir10,R13 */
1590   {
1591     { 1, 1, 1, 1 },
1592     FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
1593     { { MNEM, ' ', '@', OP (DIR10), ',', 'R', '1', '3', 0 } },
1594     { 16, 16, 0xff00 }, 0x800,
1595     (PTR) 0,
1596     { 0, 0, { 0 } }
1597   },
1598 /* dmovh @$dir10,R13 */
1599   {
1600     { 1, 1, 1, 1 },
1601     FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
1602     { { MNEM, ' ', '@', OP (DIR10), ',', 'R', '1', '3', 0 } },
1603     { 16, 16, 0xff00 }, 0x900,
1604     (PTR) 0,
1605     { 0, 0, { 0 } }
1606   },
1607 /* dmovb @$dir10,R13 */
1608   {
1609     { 1, 1, 1, 1 },
1610     FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
1611     { { MNEM, ' ', '@', OP (DIR10), ',', 'R', '1', '3', 0 } },
1612     { 16, 16, 0xff00 }, 0xa00,
1613     (PTR) 0,
1614     { 0, 0, { 0 } }
1615   },
1616 /* dmov R13,@$dir10 */
1617   {
1618     { 1, 1, 1, 1 },
1619     FR30_INSN_DMOVR13, "dmovr13", "dmov",
1620     { { MNEM, ' ', 'R', '1', '3', ',', '@', OP (DIR10), 0 } },
1621     { 16, 16, 0xff00 }, 0x1800,
1622     (PTR) 0,
1623     { 0, 0, { 0 } }
1624   },
1625 /* dmovh R13,@$dir10 */
1626   {
1627     { 1, 1, 1, 1 },
1628     FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
1629     { { MNEM, ' ', 'R', '1', '3', ',', '@', OP (DIR10), 0 } },
1630     { 16, 16, 0xff00 }, 0x1900,
1631     (PTR) 0,
1632     { 0, 0, { 0 } }
1633   },
1634 /* dmovb R13,@$dir10 */
1635   {
1636     { 1, 1, 1, 1 },
1637     FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
1638     { { MNEM, ' ', 'R', '1', '3', ',', '@', OP (DIR10), 0 } },
1639     { 16, 16, 0xff00 }, 0x1a00,
1640     (PTR) 0,
1641     { 0, 0, { 0 } }
1642   },
1643 /* dmov @$dir10,R13+ */
1644   {
1645     { 1, 1, 1, 1 },
1646     FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
1647     { { MNEM, ' ', '@', OP (DIR10), ',', 'R', '1', '3', '+', 0 } },
1648     { 16, 16, 0xff00 }, 0xc00,
1649     (PTR) 0,
1650     { 0, 0, { 0 } }
1651   },
1652 /* dmovh @$dir10,R13+ */
1653   {
1654     { 1, 1, 1, 1 },
1655     FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
1656     { { MNEM, ' ', '@', OP (DIR10), ',', 'R', '1', '3', '+', 0 } },
1657     { 16, 16, 0xff00 }, 0xd00,
1658     (PTR) 0,
1659     { 0, 0, { 0 } }
1660   },
1661 /* dmovb @$dir10,R13+ */
1662   {
1663     { 1, 1, 1, 1 },
1664     FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
1665     { { MNEM, ' ', '@', OP (DIR10), ',', 'R', '1', '3', '+', 0 } },
1666     { 16, 16, 0xff00 }, 0xe00,
1667     (PTR) 0,
1668     { 0, 0, { 0 } }
1669   },
1670 /* dmov R13+,@$dir10 */
1671   {
1672     { 1, 1, 1, 1 },
1673     FR30_INSN_DMOV13PI, "dmov13pi", "dmov",
1674     { { MNEM, ' ', 'R', '1', '3', '+', ',', '@', OP (DIR10), 0 } },
1675     { 16, 16, 0xff00 }, 0x1c00,
1676     (PTR) 0,
1677     { 0, 0, { 0 } }
1678   },
1679 /* dmovh R13+,@$dir10 */
1680   {
1681     { 1, 1, 1, 1 },
1682     FR30_INSN_DMOV13PIH, "dmov13pih", "dmovh",
1683     { { MNEM, ' ', 'R', '1', '3', '+', ',', '@', OP (DIR10), 0 } },
1684     { 16, 16, 0xff00 }, 0x1d00,
1685     (PTR) 0,
1686     { 0, 0, { 0 } }
1687   },
1688 /* dmovb R13+,@$dir10 */
1689   {
1690     { 1, 1, 1, 1 },
1691     FR30_INSN_DMOV13PIB, "dmov13pib", "dmovb",
1692     { { MNEM, ' ', 'R', '1', '3', '+', ',', '@', OP (DIR10), 0 } },
1693     { 16, 16, 0xff00 }, 0x1e00,
1694     (PTR) 0,
1695     { 0, 0, { 0 } }
1696   },
1697 /* dmov @$dir10,-R15 */
1698   {
1699     { 1, 1, 1, 1 },
1700     FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
1701     { { MNEM, ' ', '@', OP (DIR10), ',', '-', 'R', '1', '5', 0 } },
1702     { 16, 16, 0xff00 }, 0xb00,
1703     (PTR) 0,
1704     { 0, 0, { 0 } }
1705   },
1706 /* dmov R15+,@$dir10 */
1707   {
1708     { 1, 1, 1, 1 },
1709     FR30_INSN_DMOV15PI, "dmov15pi", "dmov",
1710     { { MNEM, ' ', 'R', '1', '5', '+', ',', '@', OP (DIR10), 0 } },
1711     { 16, 16, 0xff00 }, 0x1b00,
1712     (PTR) 0,
1713     { 0, 0, { 0 } }
1714   },
1715 /* ldres @$Ri+,$u4 */
1716   {
1717     { 1, 1, 1, 1 },
1718     FR30_INSN_LDRES, "ldres", "ldres",
1719     { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
1720     { 16, 16, 0xff00 }, 0xbc00,
1721     (PTR) 0,
1722     { 0, 0, { 0 } }
1723   },
1724 /* ldres $u4,@$Ri+ */
1725   {
1726     { 1, 1, 1, 1 },
1727     FR30_INSN_STRES, "stres", "ldres",
1728     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
1729     { 16, 16, 0xff00 }, 0xbd00,
1730     (PTR) 0,
1731     { 0, 0, { 0 } }
1732   },
1733 /* nop */
1734   {
1735     { 1, 1, 1, 1 },
1736     FR30_INSN_NOP, "nop", "nop",
1737     { { MNEM, 0 } },
1738     { 16, 16, 0xffff }, 0x9fa0,
1739     (PTR) 0,
1740     { 0, 0, { 0 } }
1741   },
1742 /* andccr $u8 */
1743   {
1744     { 1, 1, 1, 1 },
1745     FR30_INSN_ANDCCR, "andccr", "andccr",
1746     { { MNEM, ' ', OP (U8), 0 } },
1747     { 16, 16, 0xff00 }, 0x8300,
1748     (PTR) 0,
1749     { 0, 0, { 0 } }
1750   },
1751 /* orccr $u8 */
1752   {
1753     { 1, 1, 1, 1 },
1754     FR30_INSN_ORCCR, "orccr", "orccr",
1755     { { MNEM, ' ', OP (U8), 0 } },
1756     { 16, 16, 0xff00 }, 0x9300,
1757     (PTR) 0,
1758     { 0, 0, { 0 } }
1759   },
1760 /* stilm $u8 */
1761   {
1762     { 1, 1, 1, 1 },
1763     FR30_INSN_STILM, "stilm", "stilm",
1764     { { MNEM, ' ', OP (U8), 0 } },
1765     { 16, 16, 0xff00 }, 0x8700,
1766     (PTR) 0,
1767     { 0, 0, { 0 } }
1768   },
1769 /* addsp $s10 */
1770   {
1771     { 1, 1, 1, 1 },
1772     FR30_INSN_ADDSP, "addsp", "addsp",
1773     { { MNEM, ' ', OP (S10), 0 } },
1774     { 16, 16, 0xff00 }, 0xa300,
1775     (PTR) 0,
1776     { 0, 0, { 0 } }
1777   },
1778 /* extsb $Ri */
1779   {
1780     { 1, 1, 1, 1 },
1781     FR30_INSN_EXTSB, "extsb", "extsb",
1782     { { MNEM, ' ', OP (RI), 0 } },
1783     { 16, 16, 0xfff0 }, 0x9780,
1784     (PTR) 0,
1785     { 0, 0, { 0 } }
1786   },
1787 /* extub $Ri */
1788   {
1789     { 1, 1, 1, 1 },
1790     FR30_INSN_EXTUB, "extub", "extub",
1791     { { MNEM, ' ', OP (RI), 0 } },
1792     { 16, 16, 0xfff0 }, 0x9790,
1793     (PTR) 0,
1794     { 0, 0, { 0 } }
1795   },
1796 /* extsh $Ri */
1797   {
1798     { 1, 1, 1, 1 },
1799     FR30_INSN_EXTSH, "extsh", "extsh",
1800     { { MNEM, ' ', OP (RI), 0 } },
1801     { 16, 16, 0xfff0 }, 0x97a0,
1802     (PTR) 0,
1803     { 0, 0, { 0 } }
1804   },
1805 /* extuh $Ri */
1806   {
1807     { 1, 1, 1, 1 },
1808     FR30_INSN_EXTUH, "extuh", "extuh",
1809     { { MNEM, ' ', OP (RI), 0 } },
1810     { 16, 16, 0xfff0 }, 0x97b0,
1811     (PTR) 0,
1812     { 0, 0, { 0 } }
1813   },
1814 /* enter $u10 */
1815   {
1816     { 1, 1, 1, 1 },
1817     FR30_INSN_ENTER, "enter", "enter",
1818     { { MNEM, ' ', OP (U10), 0 } },
1819     { 16, 16, 0xff00 }, 0xf00,
1820     (PTR) 0,
1821     { 0, 0, { 0 } }
1822   },
1823 /* leave */
1824   {
1825     { 1, 1, 1, 1 },
1826     FR30_INSN_LEAVE, "leave", "leave",
1827     { { MNEM, 0 } },
1828     { 16, 16, 0xffff }, 0x9f90,
1829     (PTR) 0,
1830     { 0, 0, { 0 } }
1831   },
1832 /* xchb @$Rj,$Ri */
1833   {
1834     { 1, 1, 1, 1 },
1835     FR30_INSN_XCHB, "xchb", "xchb",
1836     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1837     { 16, 16, 0xff00 }, 0x8a00,
1838     (PTR) 0,
1839     { 0, 0, { 0 } }
1840   },
1841 };
1842
1843 #undef A
1844 #undef MNEM
1845 #undef OP
1846
1847 static const CGEN_INSN_TABLE insn_table =
1848 {
1849   & fr30_cgen_insn_table_entries[0],
1850   sizeof (CGEN_INSN),
1851   MAX_INSNS,
1852   NULL
1853 };
1854
1855 /* Each non-simple macro entry points to an array of expansion possibilities.  */
1856
1857 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1858 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1859 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1860
1861 /* The macro instruction table.  */
1862
1863 static const CGEN_INSN macro_insn_table_entries[] =
1864 {
1865 };
1866
1867 #undef A
1868 #undef MNEM
1869 #undef OP
1870
1871 static const CGEN_INSN_TABLE macro_insn_table =
1872 {
1873   & macro_insn_table_entries[0],
1874   sizeof (CGEN_INSN),
1875   (sizeof (macro_insn_table_entries) /
1876    sizeof (macro_insn_table_entries[0])),
1877   NULL
1878 };
1879
1880 static void
1881 init_tables ()
1882 {
1883 }
1884
1885 /* Return non-zero if INSN is to be added to the hash table.
1886    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
1887
1888 static int
1889 asm_hash_insn_p (insn)
1890      const CGEN_INSN * insn;
1891 {
1892   return CGEN_ASM_HASH_P (insn);
1893 }
1894
1895 static int
1896 dis_hash_insn_p (insn)
1897      const CGEN_INSN * insn;
1898 {
1899   /* If building the hash table and the NO-DIS attribute is present,
1900      ignore.  */
1901   if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
1902     return 0;
1903   return CGEN_DIS_HASH_P (insn);
1904 }
1905
1906 /* The result is the hash value of the insn.
1907    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
1908
1909 static unsigned int
1910 asm_hash_insn (mnem)
1911      const char * mnem;
1912 {
1913   return CGEN_ASM_HASH (mnem);
1914 }
1915
1916 /* BUF is a pointer to the insn's bytes in target order.
1917    VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
1918    host order.  */
1919
1920 static unsigned int
1921 dis_hash_insn (buf, value)
1922      const char * buf;
1923      unsigned long value;
1924 {
1925   return CGEN_DIS_HASH (buf, value);
1926 }
1927
1928 /* Initialize an opcode table and return a descriptor.
1929    It's much like opening a file, and must be the first function called.  */
1930
1931 CGEN_OPCODE_DESC
1932 fr30_cgen_opcode_open (mach, endian)
1933      int mach;
1934      enum cgen_endian endian;
1935 {
1936   CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
1937   static int init_p;
1938
1939   if (! init_p)
1940     {
1941       init_tables ();
1942       init_p = 1;
1943     }
1944
1945   memset (table, 0, sizeof (*table));
1946
1947   CGEN_OPCODE_MACH (table) = mach;
1948   CGEN_OPCODE_ENDIAN (table) = endian;
1949   /* FIXME: for the sparc case we can determine insn-endianness statically.
1950      The worry here is where both data and insn endian can be independently
1951      chosen, in which case this function will need another argument.
1952      Actually, will want to allow for more arguments in the future anyway.  */
1953   CGEN_OPCODE_INSN_ENDIAN (table) = endian;
1954
1955   CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
1956
1957   CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
1958
1959   * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
1960
1961   * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
1962
1963   CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
1964   CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
1965   CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
1966
1967   CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
1968   CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
1969   CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
1970
1971   return (CGEN_OPCODE_DESC) table;
1972 }
1973
1974 /* Close an opcode table.  */
1975
1976 void
1977 fr30_cgen_opcode_close (desc)
1978      CGEN_OPCODE_DESC desc;
1979 {
1980   free (desc);
1981 }
1982
1983 /* Getting values from cgen_fields is handled by a collection of functions.
1984    They are distinguished by the type of the VALUE argument they return.
1985    TODO: floating point, inlining support, remove cases where result type
1986    not appropriate.  */
1987
1988 int
1989 fr30_cgen_get_int_operand (opindex, fields)
1990      int opindex;
1991      const CGEN_FIELDS * fields;
1992 {
1993   int value;
1994
1995   switch (opindex)
1996     {
1997     case FR30_OPERAND_RI :
1998       value = fields->f_Ri;
1999       break;
2000     case FR30_OPERAND_RJ :
2001       value = fields->f_Rj;
2002       break;
2003     case FR30_OPERAND_RS1 :
2004       value = fields->f_Rs1;
2005       break;
2006     case FR30_OPERAND_RS2 :
2007       value = fields->f_Rs2;
2008       break;
2009     case FR30_OPERAND_U4 :
2010       value = fields->f_u4;
2011       break;
2012     case FR30_OPERAND_M4 :
2013       value = fields->f_m4;
2014       break;
2015     case FR30_OPERAND_I8 :
2016       value = fields->f_i8;
2017       break;
2018     case FR30_OPERAND_U8 :
2019       value = fields->f_u8;
2020       break;
2021     case FR30_OPERAND_O8 :
2022       value = fields->f_o8;
2023       break;
2024     case FR30_OPERAND_S10 :
2025       value = fields->f_s10;
2026       break;
2027     case FR30_OPERAND_U10 :
2028       value = fields->f_u10;
2029       break;
2030     case FR30_OPERAND_DIR8 :
2031       value = fields->f_dir8;
2032       break;
2033     case FR30_OPERAND_DIR9 :
2034       value = fields->f_dir9;
2035       break;
2036     case FR30_OPERAND_DIR10 :
2037       value = fields->f_dir10;
2038       break;
2039     case FR30_OPERAND_LABEL9 :
2040       value = fields->f_rel8;
2041       break;
2042     case FR30_OPERAND_LABEL12 :
2043       value = fields->f_rel11;
2044       break;
2045     case FR30_OPERAND_CC :
2046       value = fields->f_cc;
2047       break;
2048
2049     default :
2050       /* xgettext:c-format */
2051       fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2052                        opindex);
2053       abort ();
2054   }
2055
2056   return value;
2057 }
2058
2059 bfd_vma
2060 fr30_cgen_get_vma_operand (opindex, fields)
2061      int opindex;
2062      const CGEN_FIELDS * fields;
2063 {
2064   bfd_vma value;
2065
2066   switch (opindex)
2067     {
2068     case FR30_OPERAND_RI :
2069       value = fields->f_Ri;
2070       break;
2071     case FR30_OPERAND_RJ :
2072       value = fields->f_Rj;
2073       break;
2074     case FR30_OPERAND_RS1 :
2075       value = fields->f_Rs1;
2076       break;
2077     case FR30_OPERAND_RS2 :
2078       value = fields->f_Rs2;
2079       break;
2080     case FR30_OPERAND_U4 :
2081       value = fields->f_u4;
2082       break;
2083     case FR30_OPERAND_M4 :
2084       value = fields->f_m4;
2085       break;
2086     case FR30_OPERAND_I8 :
2087       value = fields->f_i8;
2088       break;
2089     case FR30_OPERAND_U8 :
2090       value = fields->f_u8;
2091       break;
2092     case FR30_OPERAND_O8 :
2093       value = fields->f_o8;
2094       break;
2095     case FR30_OPERAND_S10 :
2096       value = fields->f_s10;
2097       break;
2098     case FR30_OPERAND_U10 :
2099       value = fields->f_u10;
2100       break;
2101     case FR30_OPERAND_DIR8 :
2102       value = fields->f_dir8;
2103       break;
2104     case FR30_OPERAND_DIR9 :
2105       value = fields->f_dir9;
2106       break;
2107     case FR30_OPERAND_DIR10 :
2108       value = fields->f_dir10;
2109       break;
2110     case FR30_OPERAND_LABEL9 :
2111       value = fields->f_rel8;
2112       break;
2113     case FR30_OPERAND_LABEL12 :
2114       value = fields->f_rel11;
2115       break;
2116     case FR30_OPERAND_CC :
2117       value = fields->f_cc;
2118       break;
2119
2120     default :
2121       /* xgettext:c-format */
2122       fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
2123                        opindex);
2124       abort ();
2125   }
2126
2127   return value;
2128 }
2129
2130 /* Stuffing values in cgen_fields is handled by a collection of functions.
2131    They are distinguished by the type of the VALUE argument they accept.
2132    TODO: floating point, inlining support, remove cases where argument type
2133    not appropriate.  */
2134
2135 void
2136 fr30_cgen_set_int_operand (opindex, fields, value)
2137      int opindex;
2138      CGEN_FIELDS * fields;
2139      int value;
2140 {
2141   switch (opindex)
2142     {
2143     case FR30_OPERAND_RI :
2144       fields->f_Ri = value;
2145       break;
2146     case FR30_OPERAND_RJ :
2147       fields->f_Rj = value;
2148       break;
2149     case FR30_OPERAND_RS1 :
2150       fields->f_Rs1 = value;
2151       break;
2152     case FR30_OPERAND_RS2 :
2153       fields->f_Rs2 = value;
2154       break;
2155     case FR30_OPERAND_U4 :
2156       fields->f_u4 = value;
2157       break;
2158     case FR30_OPERAND_M4 :
2159       fields->f_m4 = value;
2160       break;
2161     case FR30_OPERAND_I8 :
2162       fields->f_i8 = value;
2163       break;
2164     case FR30_OPERAND_U8 :
2165       fields->f_u8 = value;
2166       break;
2167     case FR30_OPERAND_O8 :
2168       fields->f_o8 = value;
2169       break;
2170     case FR30_OPERAND_S10 :
2171       fields->f_s10 = value;
2172       break;
2173     case FR30_OPERAND_U10 :
2174       fields->f_u10 = value;
2175       break;
2176     case FR30_OPERAND_DIR8 :
2177       fields->f_dir8 = value;
2178       break;
2179     case FR30_OPERAND_DIR9 :
2180       fields->f_dir9 = value;
2181       break;
2182     case FR30_OPERAND_DIR10 :
2183       fields->f_dir10 = value;
2184       break;
2185     case FR30_OPERAND_LABEL9 :
2186       fields->f_rel8 = value;
2187       break;
2188     case FR30_OPERAND_LABEL12 :
2189       fields->f_rel11 = value;
2190       break;
2191     case FR30_OPERAND_CC :
2192       fields->f_cc = value;
2193       break;
2194
2195     default :
2196       /* xgettext:c-format */
2197       fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2198                        opindex);
2199       abort ();
2200   }
2201 }
2202
2203 void
2204 fr30_cgen_set_vma_operand (opindex, fields, value)
2205      int opindex;
2206      CGEN_FIELDS * fields;
2207      bfd_vma value;
2208 {
2209   switch (opindex)
2210     {
2211     case FR30_OPERAND_RI :
2212       fields->f_Ri = value;
2213       break;
2214     case FR30_OPERAND_RJ :
2215       fields->f_Rj = value;
2216       break;
2217     case FR30_OPERAND_RS1 :
2218       fields->f_Rs1 = value;
2219       break;
2220     case FR30_OPERAND_RS2 :
2221       fields->f_Rs2 = value;
2222       break;
2223     case FR30_OPERAND_U4 :
2224       fields->f_u4 = value;
2225       break;
2226     case FR30_OPERAND_M4 :
2227       fields->f_m4 = value;
2228       break;
2229     case FR30_OPERAND_I8 :
2230       fields->f_i8 = value;
2231       break;
2232     case FR30_OPERAND_U8 :
2233       fields->f_u8 = value;
2234       break;
2235     case FR30_OPERAND_O8 :
2236       fields->f_o8 = value;
2237       break;
2238     case FR30_OPERAND_S10 :
2239       fields->f_s10 = value;
2240       break;
2241     case FR30_OPERAND_U10 :
2242       fields->f_u10 = value;
2243       break;
2244     case FR30_OPERAND_DIR8 :
2245       fields->f_dir8 = value;
2246       break;
2247     case FR30_OPERAND_DIR9 :
2248       fields->f_dir9 = value;
2249       break;
2250     case FR30_OPERAND_DIR10 :
2251       fields->f_dir10 = value;
2252       break;
2253     case FR30_OPERAND_LABEL9 :
2254       fields->f_rel8 = value;
2255       break;
2256     case FR30_OPERAND_LABEL12 :
2257       fields->f_rel11 = value;
2258       break;
2259     case FR30_OPERAND_CC :
2260       fields->f_cc = value;
2261       break;
2262
2263     default :
2264       /* xgettext:c-format */
2265       fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
2266                        opindex);
2267       abort ();
2268   }
2269 }
2270