opcodes/fr30-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS USED TO GENERATE fr30-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software Foundation, Inc.,
  22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "fr30-opc.h"
  31 #include "opintl.h"
  32
  33 /* The hash functions are recorded here to help keep assembler code out of
  34    the disassembler and vice versa.  */
  35
  36 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
  37 static unsigned int asm_hash_insn PARAMS ((const char *));
  38 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
  39 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
  40
  41 /* Look up instruction INSN_VALUE and extract its fields.
  42    INSN, if non-null, is the insn table entry.
  43    Otherwise INSN_VALUE is examined to compute it.
  44    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
  45    0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
  46    If INSN != NULL, LENGTH must be valid.
  47    ALIAS_P is non-zero if alias insns are to be included in the search.
  48
  49    The result is a pointer to the insn table entry, or NULL if the instruction
  50    wasn't recognized.  */
  51
  52 const CGEN_INSN *
  53 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
  54      CGEN_OPCODE_DESC od;
  55      const CGEN_INSN *insn;
  56      CGEN_INSN_BYTES insn_value;
  57      int length;
  58      CGEN_FIELDS *fields;
  59      int alias_p;
  60 {
  61   unsigned char buf[CGEN_MAX_INSN_SIZE];
  62   unsigned char *bufp;
  63   CGEN_INSN_INT base_insn;
  64 #if CGEN_INT_INSN_P
  65   CGEN_EXTRACT_INFO *info = NULL;
  66 #else
  67   CGEN_EXTRACT_INFO ex_info;
  68   CGEN_EXTRACT_INFO *info = &ex_info;
  69 #endif
  70
  71 #if CGEN_INT_INSN_P
  72   cgen_put_insn_value (od, buf, length, insn_value);
  73   bufp = buf;
  74   base_insn = insn_value; /*???*/
  75 #else
  76   ex_info.dis_info = NULL;
  77   ex_info.insn_bytes = insn_value;
  78   ex_info.valid = -1;
  79   base_insn = cgen_get_insn_value (od, buf, length);
  80   bufp = insn_value;
  81 #endif
  82
  83   if (!insn)
  84     {
  85       const CGEN_INSN_LIST *insn_list;
  86
  87       /* The instructions are stored in hash lists.
  88          Pick the first one and keep trying until we find the right one.  */
  89
  90       insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
  91       while (insn_list != NULL)
  92         {
  93           insn = insn_list->insn;
  94
  95           if (alias_p
  96               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
  97             {
  98               /* Basic bit mask must be correct.  */
  99               /* ??? May wish to allow target to defer this check until the
 100                  extract handler.  */
 101               if ((base_insn & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
 102                 {
 103                   /* ??? 0 is passed for `pc' */
 104                   int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
 105                                                            base_insn, fields,
 106                                                            (bfd_vma) 0);
 107                   if (elength > 0)
 108                     {
 109                       /* sanity check */
 110                       if (length != 0 && length != elength)
 111                         abort ();
 112                       return insn;
 113                     }
 114                 }
 115             }
 116
 117           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 118         }
 119     }
 120   else
 121     {
 122       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 123       if (! alias_p
 124           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 125         abort ();
 126       /* Sanity check: length must be correct.  */
 127       if (length != CGEN_INSN_BITSIZE (insn))
 128         abort ();
 129
 130       /* ??? 0 is passed for `pc' */
 131       length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
 132                                           (bfd_vma) 0);
 133       /* Sanity check: must succeed.
 134          Could relax this later if it ever proves useful.  */
 135       if (length == 0)
 136         abort ();
 137       return insn;
 138     }
 139
 140   return NULL;
 141 }
 142
 143 /* Fill in the operand instances used by INSN whose operands are FIELDS.
 144    INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
 145    in.  */
 146
 147 void
 148 fr30_cgen_get_insn_operands (od, insn, fields, indices)
 149      CGEN_OPCODE_DESC od;
 150      const CGEN_INSN * insn;
 151      const CGEN_FIELDS * fields;
 152      int *indices;
 153 {
 154   const CGEN_OPERAND_INSTANCE *opinst;
 155   int i;
 156
 157   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 158        opinst != NULL
 159          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 160        ++i, ++opinst)
 161     {
 162       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 163       if (op == NULL)
 164         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 165       else
 166         indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
 167                                                   fields);
 168     }
 169 }
 170
 171 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
 172    isn't known.
 173    The INSN, INSN_VALUE, and LENGTH arguments are passed to
 174    fr30_cgen_lookup_insn unchanged.
 175
 176    The result is the insn table entry or NULL if the instruction wasn't
 177    recognized.  */
 178
 179 const CGEN_INSN *
 180 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
 181      CGEN_OPCODE_DESC od;
 182      const CGEN_INSN *insn;
 183      CGEN_INSN_BYTES insn_value;
 184      int length;
 185      int *indices;
 186 {
 187   CGEN_FIELDS fields;
 188
 189   /* Pass non-zero for ALIAS_P only if INSN != NULL.
 190      If INSN == NULL, we want a real insn.  */
 191   insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
 192                                   insn != NULL);
 193   if (! insn)
 194     return NULL;
 195
 196   fr30_cgen_get_insn_operands (od, insn, &fields, indices);
 197   return insn;
 198 }
 199 /* Attributes.  */
 200
 201 static const CGEN_ATTR_ENTRY MACH_attr[] =
 202 {
 203   { "base", MACH_BASE },
 204   { "fr30", MACH_FR30 },
 205   { "max", MACH_MAX },
 206   { 0, 0 }
 207 };
 208
 209 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
 210 {
 211   { "CACHE-ADDR", NULL },
 212   { "FUN-ACCESS", NULL },
 213   { "PC", NULL },
 214   { "PROFILE", NULL },
 215   { 0, 0 }
 216 };
 217
 218 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
 219 {
 220   { "ABS-ADDR", NULL },
 221   { "HASH-PREFIX", NULL },
 222   { "NEGATIVE", NULL },
 223   { "PCREL-ADDR", NULL },
 224   { "RELAX", NULL },
 225   { "SEM-ONLY", NULL },
 226   { "SIGN-OPT", NULL },
 227   { "SIGNED", NULL },
 228   { "UNSIGNED", NULL },
 229   { 0, 0 }
 230 };
 231
 232 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
 233 {
 234   { "ALIAS", NULL },
 235   { "COND-CTI", NULL },
 236   { "NO-DIS", NULL },
 237   { "RELAX", NULL },
 238   { "RELAXABLE", NULL },
 239   { "SKIP-CTI", NULL },
 240   { "UNCOND-CTI", NULL },
 241   { "VIRTUAL", NULL },
 242   { 0, 0 }
 243 };
 244
 245 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
 246 {
 247   { "ac", 13 },
 248   { "fp", 14 },
 249   { "sp", 15 },
 250   { "r0", 0 },
 251   { "r1", 1 },
 252   { "r2", 2 },
 253   { "r3", 3 },
 254   { "r4", 4 },
 255   { "r5", 5 },
 256   { "r6", 6 },
 257   { "r7", 7 },
 258   { "r8", 8 },
 259   { "r9", 9 },
 260   { "r10", 10 },
 261   { "r11", 11 },
 262   { "r12", 12 },
 263   { "r13", 13 },
 264   { "r14", 14 },
 265   { "r15", 15 }
 266 };
 267
 268 CGEN_KEYWORD fr30_cgen_opval_h_gr =
 269 {
 270   & fr30_cgen_opval_h_gr_entries[0],
 271   19
 272 };
 273
 274 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
 275 {
 276   { "cr0", 0 },
 277   { "cr1", 1 },
 278   { "cr2", 2 },
 279   { "cr3", 3 },
 280   { "cr4", 4 },
 281   { "cr5", 5 },
 282   { "cr6", 6 },
 283   { "cr7", 7 },
 284   { "cr8", 8 },
 285   { "cr9", 9 },
 286   { "cr10", 10 },
 287   { "cr11", 11 },
 288   { "cr12", 12 },
 289   { "cr13", 13 },
 290   { "cr14", 14 },
 291   { "cr15", 15 }
 292 };
 293
 294 CGEN_KEYWORD fr30_cgen_opval_h_cr =
 295 {
 296   & fr30_cgen_opval_h_cr_entries[0],
 297   16
 298 };
 299
 300 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
 301 {
 302   { "tbr", 0 },
 303   { "rp", 1 },
 304   { "ssp", 2 },
 305   { "usp", 3 },
 306   { "mdh", 4 },
 307   { "mdl", 5 }
 308 };
 309
 310 CGEN_KEYWORD fr30_cgen_opval_h_dr =
 311 {
 312   & fr30_cgen_opval_h_dr_entries[0],
 313   6
 314 };
 315
 316 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
 317 {
 318   { "ps", 0 }
 319 };
 320
 321 CGEN_KEYWORD fr30_cgen_opval_h_ps =
 322 {
 323   & fr30_cgen_opval_h_ps_entries[0],
 324   1
 325 };
 326
 327 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
 328 {
 329   { "r13", 0 }
 330 };
 331
 332 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
 333 {
 334   & fr30_cgen_opval_h_r13_entries[0],
 335   1
 336 };
 337
 338 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
 339 {
 340   { "r14", 0 }
 341 };
 342
 343 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
 344 {
 345   & fr30_cgen_opval_h_r14_entries[0],
 346   1
 347 };
 348
 349 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
 350 {
 351   { "r15", 0 }
 352 };
 353
 354 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
 355 {
 356   & fr30_cgen_opval_h_r15_entries[0],
 357   1
 358 };
 359
 360
 361 /* The hardware table.  */
 362
 363 #define HW_ENT(n) fr30_cgen_hw_entries[n]
 364 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
 365 {
 366   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
 367   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 368   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 369   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 370   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 371   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 372   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
 373   { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0, { 0 } } },
 374   { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
 375   { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
 376   { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
 377   { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
 378   { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
 379   { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 380   { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 381   { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 382   { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 383   { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 384   { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 385   { 0 }
 386 };
 387
 388 /* The operand table.  */
 389
 390 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
 391 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
 392
 393 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
 394 {
 395 /* pc: program counter */
 396   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 397     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 398 /* Ri: destination register */
 399   { "Ri", & HW_ENT (HW_H_GR), 12, 4,
 400     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 401 /* Rj: source register */
 402   { "Rj", & HW_ENT (HW_H_GR), 8, 4,
 403     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 404 /* Ric: target register coproc insn */
 405   { "Ric", & HW_ENT (HW_H_GR), 28, 4,
 406     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 407 /* Rjc: source register coproc insn */
 408   { "Rjc", & HW_ENT (HW_H_GR), 24, 4,
 409     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 410 /* CRi: coprocessor register */
 411   { "CRi", & HW_ENT (HW_H_CR), 28, 4,
 412     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 413 /* CRj: coprocessor register */
 414   { "CRj", & HW_ENT (HW_H_CR), 24, 4,
 415     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 416 /* Rs1: dedicated register */
 417   { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
 418     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 419 /* Rs2: dedicated register */
 420   { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
 421     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 422 /* R13: General Register 13 */
 423   { "R13", & HW_ENT (HW_H_R13), 0, 0,
 424     { 0, 0, { 0 } }  },
 425 /* R14: General Register 14 */
 426   { "R14", & HW_ENT (HW_H_R14), 0, 0,
 427     { 0, 0, { 0 } }  },
 428 /* R15: General Register 15 */
 429   { "R15", & HW_ENT (HW_H_R15), 0, 0,
 430     { 0, 0, { 0 } }  },
 431 /* ps: Program Status register */
 432   { "ps", & HW_ENT (HW_H_PS), 0, 0,
 433     { 0, 0, { 0 } }  },
 434 /* u4: 4  bit unsigned immediate */
 435   { "u4", & HW_ENT (HW_H_UINT), 8, 4,
 436     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 437 /* u4c: 4  bit unsigned immediate */
 438   { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
 439     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 440 /* m4: 4  bit negative immediate */
 441   { "m4", & HW_ENT (HW_H_UINT), 8, 4,
 442     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 443 /* u8: 8  bit unsigned immediate */
 444   { "u8", & HW_ENT (HW_H_UINT), 8, 8,
 445     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 446 /* i8: 8  bit unsigned immediate */
 447   { "i8", & HW_ENT (HW_H_UINT), 4, 8,
 448     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 449 /* udisp6: 6  bit unsigned immediate */
 450   { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
 451     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 452 /* disp8: 8  bit signed   immediate */
 453   { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
 454     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 455 /* disp9: 9  bit signed   immediate */
 456   { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
 457     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 458 /* disp10: 10 bit signed   immediate */
 459   { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
 460     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 461 /* s10: 10 bit signed   immediate */
 462   { "s10", & HW_ENT (HW_H_SINT), 8, 8,
 463     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 464 /* u10: 10 bit unsigned immediate */
 465   { "u10", & HW_ENT (HW_H_UINT), 8, 8,
 466     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 467 /* i32: 32 bit immediate */
 468   { "i32", & HW_ENT (HW_H_UINT), 16, 32,
 469     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 470 /* dir8: 8  bit direct address */
 471   { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
 472     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 473 /* dir9: 9  bit direct address */
 474   { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
 475     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 476 /* dir10: 10 bit direct address */
 477   { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
 478     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 479 /* label9: 9  bit pc relative address */
 480   { "label9", & HW_ENT (HW_H_SINT), 8, 8,
 481     { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 482 /* label12: 12 bit pc relative address */
 483   { "label12", & HW_ENT (HW_H_SINT), 5, 11,
 484     { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 485 /* reglist_low: 8 bit register mask */
 486   { "reglist_low", & HW_ENT (HW_H_UINT), 8, 8,
 487     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 488 /* reglist_hi: 8 bit register mask */
 489   { "reglist_hi", & HW_ENT (HW_H_UINT), 8, 8,
 490     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 491 /* cc: condition codes */
 492   { "cc", & HW_ENT (HW_H_UINT), 4, 4,
 493     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 494 /* ccc: coprocessor calc */
 495   { "ccc", & HW_ENT (HW_H_UINT), 16, 8,
 496     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 497 /* nbit: negative  bit */
 498   { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
 499     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 500 /* vbit: overflow  bit */
 501   { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
 502     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 503 /* zbit: zero      bit */
 504   { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
 505     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 506 /* cbit: carry     bit */
 507   { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
 508     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 509 /* ibit: interrupt bit */
 510   { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
 511     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 512 /* sbit: stack     bit */
 513   { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
 514     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 515 };
 516
 517 /* Operand references.  */
 518
 519 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 520 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 521 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
 522
 523 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
 524   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 525   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 526   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 527   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 528   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 529   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 530   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 531   { 0 }
 532 };
 533
 534 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
 535   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 536   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
 537   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 538   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 539   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 540   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 541   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 542   { 0 }
 543 };
 544
 545 static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
 546   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 547   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
 548   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 549   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 550   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 551   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 552   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 553   { 0 }
 554 };
 555
 556 static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
 557   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 558   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 559   { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 560   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 561   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 562   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 563   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 564   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 565   { 0 }
 566 };
 567
 568 static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
 569   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 570   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 571   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 572   { 0 }
 573 };
 574
 575 static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
 576   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 577   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
 578   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 579   { 0 }
 580 };
 581
 582 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
 583   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 584   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
 585   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 586   { 0 }
 587 };
 588
 589 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
 590   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 591   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 592   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 593   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 594   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 595   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 596   { 0 }
 597 };
 598
 599 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
 600   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 601   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
 602   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 603   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 604   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 605   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 606   { 0 }
 607 };
 608
 609 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
 610   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 611   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
 612   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 613   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 614   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 615   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 616   { 0 }
 617 };
 618
 619 static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
 620   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 621   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 622   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 623   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 624   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 625   { 0 }
 626 };
 627
 628 static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
 629   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
 630   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
 631   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 632   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 633   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 634   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
 635   { 0 }
 636 };
 637
 638 static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
 639   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
 640   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
 641   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
 642   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 643   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 644   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
 645   { 0 }
 646 };
 647
 648 static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
 649   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
 650   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
 651   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
 652   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 653   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 654   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
 655   { 0 }
 656 };
 657
 658 static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
 659   { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
 660   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 661   { 0 }
 662 };
 663
 664 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
 665   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 666   { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_USI, & OP_ENT (RS1), 0, 0 },
 667   { 0 }
 668 };
 669
 670 static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
 671   { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
 672   { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
 673   { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, 0 },
 674   { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
 675   { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
 676   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
 677   { 0 }
 678 };
 679
 680 static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
 681   { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
 682   { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, COND_REF },
 683   { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
 684   { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 3, COND_REF },
 685   { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
 686   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
 687   { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, COND_REF },
 688   { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
 689   { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 3, COND_REF },
 690   { 0 }
 691 };
 692
 693 #undef INPUT
 694 #undef OUTPUT
 695 #undef COND_REF
 696
 697 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
 698 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
 699 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 700
 701 /* The instruction table.
 702    This is currently non-static because the simulator accesses it
 703    directly.  */
 704
 705 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
 706 {
 707   /* Special null first entry.
 708      A `num' value of zero is thus invalid.
 709      Also, the special `invalid' insn resides here.  */
 710   { { 0 }, 0 },
 711 /* add $Rj,$Ri */
 712   {
 713     { 1, 1, 1, 1 },
 714     FR30_INSN_ADD, "add", "add",
 715     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 716     { 16, 16, 0xff00 }, 0xa600,
 717     (PTR) & fmt_add_ops[0],
 718     { 0, 0, { 0 } }
 719   },
 720 /* add $u4,$Ri */
 721   {
 722     { 1, 1, 1, 1 },
 723     FR30_INSN_ADDI, "addi", "add",
 724     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 725     { 16, 16, 0xff00 }, 0xa400,
 726     (PTR) & fmt_addi_ops[0],
 727     { 0, 0, { 0 } }
 728   },
 729 /* add2 $m4,$Ri */
 730   {
 731     { 1, 1, 1, 1 },
 732     FR30_INSN_ADD2, "add2", "add2",
 733     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 734     { 16, 16, 0xff00 }, 0xa500,
 735     (PTR) & fmt_add2_ops[0],
 736     { 0, 0, { 0 } }
 737   },
 738 /* addc $Rj,$Ri */
 739   {
 740     { 1, 1, 1, 1 },
 741     FR30_INSN_ADDC, "addc", "addc",
 742     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 743     { 16, 16, 0xff00 }, 0xa700,
 744     (PTR) & fmt_addc_ops[0],
 745     { 0, 0, { 0 } }
 746   },
 747 /* addn $Rj,$Ri */
 748   {
 749     { 1, 1, 1, 1 },
 750     FR30_INSN_ADDN, "addn", "addn",
 751     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 752     { 16, 16, 0xff00 }, 0xa200,
 753     (PTR) & fmt_addn_ops[0],
 754     { 0, 0, { 0 } }
 755   },
 756 /* addn $u4,$Ri */
 757   {
 758     { 1, 1, 1, 1 },
 759     FR30_INSN_ADDNI, "addni", "addn",
 760     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 761     { 16, 16, 0xff00 }, 0xa000,
 762     (PTR) & fmt_addni_ops[0],
 763     { 0, 0, { 0 } }
 764   },
 765 /* addn2 $m4,$Ri */
 766   {
 767     { 1, 1, 1, 1 },
 768     FR30_INSN_ADDN2, "addn2", "addn2",
 769     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 770     { 16, 16, 0xff00 }, 0xa100,
 771     (PTR) & fmt_addn2_ops[0],
 772     { 0, 0, { 0 } }
 773   },
 774 /* sub $Rj,$Ri */
 775   {
 776     { 1, 1, 1, 1 },
 777     FR30_INSN_SUB, "sub", "sub",
 778     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 779     { 16, 16, 0xff00 }, 0xac00,
 780     (PTR) & fmt_add_ops[0],
 781     { 0, 0, { 0 } }
 782   },
 783 /* subc $Rj,$Ri */
 784   {
 785     { 1, 1, 1, 1 },
 786     FR30_INSN_SUBC, "subc", "subc",
 787     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 788     { 16, 16, 0xff00 }, 0xad00,
 789     (PTR) & fmt_addc_ops[0],
 790     { 0, 0, { 0 } }
 791   },
 792 /* subn $Rj,$Ri */
 793   {
 794     { 1, 1, 1, 1 },
 795     FR30_INSN_SUBN, "subn", "subn",
 796     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 797     { 16, 16, 0xff00 }, 0xae00,
 798     (PTR) & fmt_addn_ops[0],
 799     { 0, 0, { 0 } }
 800   },
 801 /* cmp $Rj,$Ri */
 802   {
 803     { 1, 1, 1, 1 },
 804     FR30_INSN_CMP, "cmp", "cmp",
 805     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 806     { 16, 16, 0xff00 }, 0xaa00,
 807     (PTR) & fmt_cmp_ops[0],
 808     { 0, 0, { 0 } }
 809   },
 810 /* cmp $u4,$Ri */
 811   {
 812     { 1, 1, 1, 1 },
 813     FR30_INSN_CMPI, "cmpi", "cmp",
 814     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 815     { 16, 16, 0xff00 }, 0xa800,
 816     (PTR) & fmt_cmpi_ops[0],
 817     { 0, 0, { 0 } }
 818   },
 819 /* cmp2 $m4,$Ri */
 820   {
 821     { 1, 1, 1, 1 },
 822     FR30_INSN_CMP2, "cmp2", "cmp2",
 823     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 824     { 16, 16, 0xff00 }, 0xa900,
 825     (PTR) & fmt_cmp2_ops[0],
 826     { 0, 0, { 0 } }
 827   },
 828 /* and $Rj,$Ri */
 829   {
 830     { 1, 1, 1, 1 },
 831     FR30_INSN_AND, "and", "and",
 832     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 833     { 16, 16, 0xff00 }, 0x8200,
 834     (PTR) & fmt_and_ops[0],
 835     { 0, 0, { 0 } }
 836   },
 837 /* or $Rj,$Ri */
 838   {
 839     { 1, 1, 1, 1 },
 840     FR30_INSN_OR, "or", "or",
 841     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 842     { 16, 16, 0xff00 }, 0x9200,
 843     (PTR) & fmt_and_ops[0],
 844     { 0, 0, { 0 } }
 845   },
 846 /* eor $Rj,$Ri */
 847   {
 848     { 1, 1, 1, 1 },
 849     FR30_INSN_EOR, "eor", "eor",
 850     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 851     { 16, 16, 0xff00 }, 0x9a00,
 852     (PTR) & fmt_and_ops[0],
 853     { 0, 0, { 0 } }
 854   },
 855 /* and $Rj,@$Ri */
 856   {
 857     { 1, 1, 1, 1 },
 858     FR30_INSN_ANDM, "andm", "and",
 859     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 860     { 16, 16, 0xff00 }, 0x8400,
 861     (PTR) & fmt_andm_ops[0],
 862     { 0, 0, { 0 } }
 863   },
 864 /* andh $Rj,@$Ri */
 865   {
 866     { 1, 1, 1, 1 },
 867     FR30_INSN_ANDH, "andh", "andh",
 868     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 869     { 16, 16, 0xff00 }, 0x8500,
 870     (PTR) & fmt_andh_ops[0],
 871     { 0, 0, { 0 } }
 872   },
 873 /* andb $Rj,@$Ri */
 874   {
 875     { 1, 1, 1, 1 },
 876     FR30_INSN_ANDB, "andb", "andb",
 877     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 878     { 16, 16, 0xff00 }, 0x8600,
 879     (PTR) & fmt_andb_ops[0],
 880     { 0, 0, { 0 } }
 881   },
 882 /* or $Rj,@$Ri */
 883   {
 884     { 1, 1, 1, 1 },
 885     FR30_INSN_ORM, "orm", "or",
 886     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 887     { 16, 16, 0xff00 }, 0x9400,
 888     (PTR) & fmt_andm_ops[0],
 889     { 0, 0, { 0 } }
 890   },
 891 /* orh $Rj,@$Ri */
 892   {
 893     { 1, 1, 1, 1 },
 894     FR30_INSN_ORH, "orh", "orh",
 895     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 896     { 16, 16, 0xff00 }, 0x9500,
 897     (PTR) & fmt_andh_ops[0],
 898     { 0, 0, { 0 } }
 899   },
 900 /* orb $Rj,@$Ri */
 901   {
 902     { 1, 1, 1, 1 },
 903     FR30_INSN_ORB, "orb", "orb",
 904     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 905     { 16, 16, 0xff00 }, 0x9600,
 906     (PTR) & fmt_andb_ops[0],
 907     { 0, 0, { 0 } }
 908   },
 909 /* eor $Rj,@$Ri */
 910   {
 911     { 1, 1, 1, 1 },
 912     FR30_INSN_EORM, "eorm", "eor",
 913     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 914     { 16, 16, 0xff00 }, 0x9c00,
 915     (PTR) & fmt_andm_ops[0],
 916     { 0, 0, { 0 } }
 917   },
 918 /* eorh $Rj,@$Ri */
 919   {
 920     { 1, 1, 1, 1 },
 921     FR30_INSN_EORH, "eorh", "eorh",
 922     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 923     { 16, 16, 0xff00 }, 0x9d00,
 924     (PTR) & fmt_andh_ops[0],
 925     { 0, 0, { 0 } }
 926   },
 927 /* eorb $Rj,@$Ri */
 928   {
 929     { 1, 1, 1, 1 },
 930     FR30_INSN_EORB, "eorb", "eorb",
 931     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 932     { 16, 16, 0xff00 }, 0x9e00,
 933     (PTR) & fmt_andb_ops[0],
 934     { 0, 0, { 0 } }
 935   },
 936 /* bandl $u4,@$Ri */
 937   {
 938     { 1, 1, 1, 1 },
 939     FR30_INSN_BANDL, "bandl", "bandl",
 940     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 941     { 16, 16, 0xff00 }, 0x8000,
 942     (PTR) 0,
 943     { 0, 0, { 0 } }
 944   },
 945 /* borl $u4,@$Ri */
 946   {
 947     { 1, 1, 1, 1 },
 948     FR30_INSN_BORL, "borl", "borl",
 949     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 950     { 16, 16, 0xff00 }, 0x9000,
 951     (PTR) 0,
 952     { 0, 0, { 0 } }
 953   },
 954 /* beorl $u4,@$Ri */
 955   {
 956     { 1, 1, 1, 1 },
 957     FR30_INSN_BEORL, "beorl", "beorl",
 958     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 959     { 16, 16, 0xff00 }, 0x9800,
 960     (PTR) 0,
 961     { 0, 0, { 0 } }
 962   },
 963 /* bandh $u4,@$Ri */
 964   {
 965     { 1, 1, 1, 1 },
 966     FR30_INSN_BANDH, "bandh", "bandh",
 967     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 968     { 16, 16, 0xff00 }, 0x8100,
 969     (PTR) 0,
 970     { 0, 0, { 0 } }
 971   },
 972 /* borh $u4,@$Ri */
 973   {
 974     { 1, 1, 1, 1 },
 975     FR30_INSN_BORH, "borh", "borh",
 976     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 977     { 16, 16, 0xff00 }, 0x9100,
 978     (PTR) 0,
 979     { 0, 0, { 0 } }
 980   },
 981 /* beorh $u4,@$Ri */
 982   {
 983     { 1, 1, 1, 1 },
 984     FR30_INSN_BEORH, "beorh", "beorh",
 985     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 986     { 16, 16, 0xff00 }, 0x9900,
 987     (PTR) 0,
 988     { 0, 0, { 0 } }
 989   },
 990 /* btstl $u4,@$Ri */
 991   {
 992     { 1, 1, 1, 1 },
 993     FR30_INSN_BTSTL, "btstl", "btstl",
 994     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 995     { 16, 16, 0xff00 }, 0x8800,
 996     (PTR) 0,
 997     { 0, 0, { 0 } }
 998   },
 999 /* btsth $u4,@$Ri */
1000   {
1001     { 1, 1, 1, 1 },
1002     FR30_INSN_BTSTH, "btsth", "btsth",
1003     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1004     { 16, 16, 0xff00 }, 0x8900,
1005     (PTR) 0,
1006     { 0, 0, { 0 } }
1007   },
1008 /* mul $Rj,$Ri */
1009   {
1010     { 1, 1, 1, 1 },
1011     FR30_INSN_MUL, "mul", "mul",
1012     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1013     { 16, 16, 0xff00 }, 0xaf00,
1014     (PTR) 0,
1015     { 0, 0, { 0 } }
1016   },
1017 /* mulu $Rj,$Ri */
1018   {
1019     { 1, 1, 1, 1 },
1020     FR30_INSN_MULU, "mulu", "mulu",
1021     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1022     { 16, 16, 0xff00 }, 0xab00,
1023     (PTR) 0,
1024     { 0, 0, { 0 } }
1025   },
1026 /* mulh $Rj,$Ri */
1027   {
1028     { 1, 1, 1, 1 },
1029     FR30_INSN_MULH, "mulh", "mulh",
1030     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1031     { 16, 16, 0xff00 }, 0xbf00,
1032     (PTR) 0,
1033     { 0, 0, { 0 } }
1034   },
1035 /* muluh $Rj,$Ri */
1036   {
1037     { 1, 1, 1, 1 },
1038     FR30_INSN_MULUH, "muluh", "muluh",
1039     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1040     { 16, 16, 0xff00 }, 0xbb00,
1041     (PTR) 0,
1042     { 0, 0, { 0 } }
1043   },
1044 /* div0s $Ri */
1045   {
1046     { 1, 1, 1, 1 },
1047     FR30_INSN_DIV0S, "div0s", "div0s",
1048     { { MNEM, ' ', OP (RI), 0 } },
1049     { 16, 16, 0xfff0 }, 0x9740,
1050     (PTR) 0,
1051     { 0, 0, { 0 } }
1052   },
1053 /* div0u $Ri */
1054   {
1055     { 1, 1, 1, 1 },
1056     FR30_INSN_DIV0U, "div0u", "div0u",
1057     { { MNEM, ' ', OP (RI), 0 } },
1058     { 16, 16, 0xfff0 }, 0x9750,
1059     (PTR) 0,
1060     { 0, 0, { 0 } }
1061   },
1062 /* div1 $Ri */
1063   {
1064     { 1, 1, 1, 1 },
1065     FR30_INSN_DIV1, "div1", "div1",
1066     { { MNEM, ' ', OP (RI), 0 } },
1067     { 16, 16, 0xfff0 }, 0x9760,
1068     (PTR) 0,
1069     { 0, 0, { 0 } }
1070   },
1071 /* div2 $Ri */
1072   {
1073     { 1, 1, 1, 1 },
1074     FR30_INSN_DIV2, "div2", "div2",
1075     { { MNEM, ' ', OP (RI), 0 } },
1076     { 16, 16, 0xfff0 }, 0x9770,
1077     (PTR) 0,
1078     { 0, 0, { 0 } }
1079   },
1080 /* div3 */
1081   {
1082     { 1, 1, 1, 1 },
1083     FR30_INSN_DIV3, "div3", "div3",
1084     { { MNEM, 0 } },
1085     { 16, 16, 0xffff }, 0x9f60,
1086     (PTR) 0,
1087     { 0, 0, { 0 } }
1088   },
1089 /* div4s */
1090   {
1091     { 1, 1, 1, 1 },
1092     FR30_INSN_DIV4S, "div4s", "div4s",
1093     { { MNEM, 0 } },
1094     { 16, 16, 0xffff }, 0x9f70,
1095     (PTR) 0,
1096     { 0, 0, { 0 } }
1097   },
1098 /* lsl $Rj,$Ri */
1099   {
1100     { 1, 1, 1, 1 },
1101     FR30_INSN_LSL, "lsl", "lsl",
1102     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1103     { 16, 16, 0xff00 }, 0xb600,
1104     (PTR) 0,
1105     { 0, 0, { 0 } }
1106   },
1107 /* lsl $u4,$Ri */
1108   {
1109     { 1, 1, 1, 1 },
1110     FR30_INSN_LSLI, "lsli", "lsl",
1111     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1112     { 16, 16, 0xff00 }, 0xb400,
1113     (PTR) 0,
1114     { 0, 0, { 0 } }
1115   },
1116 /* lsl2 $u4,$Ri */
1117   {
1118     { 1, 1, 1, 1 },
1119     FR30_INSN_LSL2, "lsl2", "lsl2",
1120     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1121     { 16, 16, 0xff00 }, 0xb500,
1122     (PTR) 0,
1123     { 0, 0, { 0 } }
1124   },
1125 /* lsr $Rj,$Ri */
1126   {
1127     { 1, 1, 1, 1 },
1128     FR30_INSN_LSR, "lsr", "lsr",
1129     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1130     { 16, 16, 0xff00 }, 0xb200,
1131     (PTR) 0,
1132     { 0, 0, { 0 } }
1133   },
1134 /* lsr $u4,$Ri */
1135   {
1136     { 1, 1, 1, 1 },
1137     FR30_INSN_LSRI, "lsri", "lsr",
1138     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1139     { 16, 16, 0xff00 }, 0xb000,
1140     (PTR) 0,
1141     { 0, 0, { 0 } }
1142   },
1143 /* lsr2 $u4,$Ri */
1144   {
1145     { 1, 1, 1, 1 },
1146     FR30_INSN_LSR2, "lsr2", "lsr2",
1147     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1148     { 16, 16, 0xff00 }, 0xb100,
1149     (PTR) 0,
1150     { 0, 0, { 0 } }
1151   },
1152 /* asr $Rj,$Ri */
1153   {
1154     { 1, 1, 1, 1 },
1155     FR30_INSN_ASR, "asr", "asr",
1156     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1157     { 16, 16, 0xff00 }, 0xba00,
1158     (PTR) 0,
1159     { 0, 0, { 0 } }
1160   },
1161 /* asr $u4,$Ri */
1162   {
1163     { 1, 1, 1, 1 },
1164     FR30_INSN_ASRI, "asri", "asr",
1165     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1166     { 16, 16, 0xff00 }, 0xb800,
1167     (PTR) 0,
1168     { 0, 0, { 0 } }
1169   },
1170 /* asr2 $u4,$Ri */
1171   {
1172     { 1, 1, 1, 1 },
1173     FR30_INSN_ASR2, "asr2", "asr2",
1174     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1175     { 16, 16, 0xff00 }, 0xb900,
1176     (PTR) 0,
1177     { 0, 0, { 0 } }
1178   },
1179 /* ldi:8 $i8,$Ri */
1180   {
1181     { 1, 1, 1, 1 },
1182     FR30_INSN_LDI_8, "ldi:8", "ldi:8",
1183     { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
1184     { 16, 16, 0xf000 }, 0xc000,
1185     (PTR) 0,
1186     { 0, 0, { 0 } }
1187   },
1188 /* ldi:32 $i32,$Ri */
1189   {
1190     { 1, 1, 1, 1 },
1191     FR30_INSN_LDI32, "ldi32", "ldi:32",
1192     { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
1193     { 16, 48, 0xfff0 }, 0x9f80,
1194     (PTR) & fmt_ldi32_ops[0],
1195     { 0, 0, { 0 } }
1196   },
1197 /* ld @$Rj,$Ri */
1198   {
1199     { 1, 1, 1, 1 },
1200     FR30_INSN_LD, "ld", "ld",
1201     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1202     { 16, 16, 0xff00 }, 0x400,
1203     (PTR) 0,
1204     { 0, 0, { 0 } }
1205   },
1206 /* lduh @$Rj,$Ri */
1207   {
1208     { 1, 1, 1, 1 },
1209     FR30_INSN_LDUH, "lduh", "lduh",
1210     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1211     { 16, 16, 0xff00 }, 0x500,
1212     (PTR) 0,
1213     { 0, 0, { 0 } }
1214   },
1215 /* ldub @$Rj,$Ri */
1216   {
1217     { 1, 1, 1, 1 },
1218     FR30_INSN_LDUB, "ldub", "ldub",
1219     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1220     { 16, 16, 0xff00 }, 0x600,
1221     (PTR) 0,
1222     { 0, 0, { 0 } }
1223   },
1224 /* ld @($r13,$Rj),$Ri */
1225   {
1226     { 1, 1, 1, 1 },
1227     FR30_INSN_LDR13, "ldr13", "ld",
1228     { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1229     { 16, 16, 0xff00 }, 0x0,
1230     (PTR) 0,
1231     { 0, 0, { 0 } }
1232   },
1233 /* lduh @($r13,$Rj),$Ri */
1234   {
1235     { 1, 1, 1, 1 },
1236     FR30_INSN_LDR13UH, "ldr13uh", "lduh",
1237     { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1238     { 16, 16, 0xff00 }, 0x100,
1239     (PTR) 0,
1240     { 0, 0, { 0 } }
1241   },
1242 /* ldub @($r13,$Rj),$Ri */
1243   {
1244     { 1, 1, 1, 1 },
1245     FR30_INSN_LDR13UB, "ldr13ub", "ldub",
1246     { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1247     { 16, 16, 0xff00 }, 0x200,
1248     (PTR) 0,
1249     { 0, 0, { 0 } }
1250   },
1251 /* ld @($r14,$disp10),$Ri */
1252   {
1253     { 1, 1, 1, 1 },
1254     FR30_INSN_LDR14, "ldr14", "ld",
1255     { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
1256     { 16, 16, 0xf000 }, 0x2000,
1257     (PTR) 0,
1258     { 0, 0, { 0 } }
1259   },
1260 /* lduh @($r14,$disp9),$Ri */
1261   {
1262     { 1, 1, 1, 1 },
1263     FR30_INSN_LDR14UH, "ldr14uh", "lduh",
1264     { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
1265     { 16, 16, 0xf000 }, 0x4000,
1266     (PTR) 0,
1267     { 0, 0, { 0 } }
1268   },
1269 /* ldub @($r14,$disp8),$Ri */
1270   {
1271     { 1, 1, 1, 1 },
1272     FR30_INSN_LDR14UB, "ldr14ub", "ldub",
1273     { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
1274     { 16, 16, 0xf000 }, 0x6000,
1275     (PTR) 0,
1276     { 0, 0, { 0 } }
1277   },
1278 /* ld @($r15,$udisp6),$Ri */
1279   {
1280     { 1, 1, 1, 1 },
1281     FR30_INSN_LDR15, "ldr15", "ld",
1282     { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
1283     { 16, 16, 0xff00 }, 0x300,
1284     (PTR) 0,
1285     { 0, 0, { 0 } }
1286   },
1287 /* ld @$r15+,$Ri */
1288   {
1289     { 1, 1, 1, 1 },
1290     FR30_INSN_LDR15GR, "ldr15gr", "ld",
1291     { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
1292     { 16, 16, 0xfff0 }, 0x700,
1293     (PTR) 0,
1294     { 0, 0, { 0 } }
1295   },
1296 /* ld @$r15+,$Rs2 */
1297   {
1298     { 1, 1, 1, 1 },
1299     FR30_INSN_LDR15DR, "ldr15dr", "ld",
1300     { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
1301     { 16, 16, 0xfff0 }, 0x780,
1302     (PTR) 0,
1303     { 0, 0, { 0 } }
1304   },
1305 /* ld @$r15+,$ps */
1306   {
1307     { 1, 1, 1, 1 },
1308     FR30_INSN_LDR15PS, "ldr15ps", "ld",
1309     { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
1310     { 16, 16, 0xffff }, 0x790,
1311     (PTR) 0,
1312     { 0, 0, { 0 } }
1313   },
1314 /* st $Ri,@$Rj */
1315   {
1316     { 1, 1, 1, 1 },
1317     FR30_INSN_ST, "st", "st",
1318     { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1319     { 16, 16, 0xff00 }, 0x1400,
1320     (PTR) 0,
1321     { 0, 0, { 0 } }
1322   },
1323 /* sth $Ri,@$Rj */
1324   {
1325     { 1, 1, 1, 1 },
1326     FR30_INSN_STH, "sth", "sth",
1327     { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1328     { 16, 16, 0xff00 }, 0x1500,
1329     (PTR) 0,
1330     { 0, 0, { 0 } }
1331   },
1332 /* stb $Ri,@$Rj */
1333   {
1334     { 1, 1, 1, 1 },
1335     FR30_INSN_STB, "stb", "stb",
1336     { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1337     { 16, 16, 0xff00 }, 0x1600,
1338     (PTR) 0,
1339     { 0, 0, { 0 } }
1340   },
1341 /* st $Ri,@($r13,$Rj) */
1342   {
1343     { 1, 1, 1, 1 },
1344     FR30_INSN_STR13, "str13", "st",
1345     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1346     { 16, 16, 0xff00 }, 0x1000,
1347     (PTR) 0,
1348     { 0, 0, { 0 } }
1349   },
1350 /* sth $Ri,@($r13,$Rj) */
1351   {
1352     { 1, 1, 1, 1 },
1353     FR30_INSN_STR13H, "str13h", "sth",
1354     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1355     { 16, 16, 0xff00 }, 0x1100,
1356     (PTR) 0,
1357     { 0, 0, { 0 } }
1358   },
1359 /* stb $Ri,@($r13,$Rj) */
1360   {
1361     { 1, 1, 1, 1 },
1362     FR30_INSN_STR13B, "stR13b", "stb",
1363     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1364     { 16, 16, 0xff00 }, 0x1200,
1365     (PTR) 0,
1366     { 0, 0, { 0 } }
1367   },
1368 /* st $Ri,@($r14,$disp10) */
1369   {
1370     { 1, 1, 1, 1 },
1371     FR30_INSN_STR14, "str14", "st",
1372     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
1373     { 16, 16, 0xf000 }, 0x3000,
1374     (PTR) 0,
1375     { 0, 0, { 0 } }
1376   },
1377 /* sth $Ri,@($r14,$disp9) */
1378   {
1379     { 1, 1, 1, 1 },
1380     FR30_INSN_STR14H, "str14h", "sth",
1381     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
1382     { 16, 16, 0xf000 }, 0x5000,
1383     (PTR) 0,
1384     { 0, 0, { 0 } }
1385   },
1386 /* stb $Ri,@($r14,$disp8) */
1387   {
1388     { 1, 1, 1, 1 },
1389     FR30_INSN_STR14B, "str14b", "stb",
1390     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
1391     { 16, 16, 0xf000 }, 0x7000,
1392     (PTR) 0,
1393     { 0, 0, { 0 } }
1394   },
1395 /* st $Ri,@($r15,$udisp6) */
1396   {
1397     { 1, 1, 1, 1 },
1398     FR30_INSN_STR15, "str15", "st",
1399     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
1400     { 16, 16, 0xff00 }, 0x1300,
1401     (PTR) 0,
1402     { 0, 0, { 0 } }
1403   },
1404 /* st $Ri,@-$r15 */
1405   {
1406     { 1, 1, 1, 1 },
1407     FR30_INSN_STR15GR, "str15gr", "st",
1408     { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
1409     { 16, 16, 0xfff0 }, 0x1700,
1410     (PTR) 0,
1411     { 0, 0, { 0 } }
1412   },
1413 /* st $Rs2,@-$r15 */
1414   {
1415     { 1, 1, 1, 1 },
1416     FR30_INSN_STR15DR, "str15dr", "st",
1417     { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
1418     { 16, 16, 0xfff0 }, 0x1780,
1419     (PTR) 0,
1420     { 0, 0, { 0 } }
1421   },
1422 /* st $ps,@-$r15 */
1423   {
1424     { 1, 1, 1, 1 },
1425     FR30_INSN_STR15PS, "str15ps", "st",
1426     { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
1427     { 16, 16, 0xffff }, 0x1790,
1428     (PTR) 0,
1429     { 0, 0, { 0 } }
1430   },
1431 /* mov $Rj,$Ri */
1432   {
1433     { 1, 1, 1, 1 },
1434     FR30_INSN_MOV, "mov", "mov",
1435     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1436     { 16, 16, 0xff00 }, 0x8b00,
1437     (PTR) 0,
1438     { 0, 0, { 0 } }
1439   },
1440 /* mov $Rs1,$Ri */
1441   {
1442     { 1, 1, 1, 1 },
1443     FR30_INSN_MOVDR, "movdr", "mov",
1444     { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
1445     { 16, 16, 0xff00 }, 0xb700,
1446     (PTR) 0,
1447     { 0, 0, { 0 } }
1448   },
1449 /* mov $ps,$Ri */
1450   {
1451     { 1, 1, 1, 1 },
1452     FR30_INSN_MOVPS, "movps", "mov",
1453     { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
1454     { 16, 16, 0xfff0 }, 0x1710,
1455     (PTR) 0,
1456     { 0, 0, { 0 } }
1457   },
1458 /* mov $Ri,$Rs1 */
1459   {
1460     { 1, 1, 1, 1 },
1461     FR30_INSN_MOV2DR, "mov2dr", "mov",
1462     { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
1463     { 16, 16, 0xff00 }, 0xb300,
1464     (PTR) & fmt_mov2dr_ops[0],
1465     { 0, 0, { 0 } }
1466   },
1467 /* mov $Ri,$ps */
1468   {
1469     { 1, 1, 1, 1 },
1470     FR30_INSN_MOV2PS, "mov2ps", "mov",
1471     { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
1472     { 16, 16, 0xfff0 }, 0x710,
1473     (PTR) 0,
1474     { 0, 0, { 0 } }
1475   },
1476 /* jmp @$Ri */
1477   {
1478     { 1, 1, 1, 1 },
1479     FR30_INSN_JMP, "jmp", "jmp",
1480     { { MNEM, ' ', '@', OP (RI), 0 } },
1481     { 16, 16, 0xfff0 }, 0x9700,
1482     (PTR) 0,
1483     { 0, 0, { 0 } }
1484   },
1485 /* jmp:D @$Ri */
1486   {
1487     { 1, 1, 1, 1 },
1488     FR30_INSN_JMPD, "jmpd", "jmp:D",
1489     { { MNEM, ' ', '@', OP (RI), 0 } },
1490     { 16, 16, 0xfff0 }, 0x9f00,
1491     (PTR) 0,
1492     { 0, 0, { 0 } }
1493   },
1494 /* call @$Ri */
1495   {
1496     { 1, 1, 1, 1 },
1497     FR30_INSN_CALLR, "callr", "call",
1498     { { MNEM, ' ', '@', OP (RI), 0 } },
1499     { 16, 16, 0xfff0 }, 0x9710,
1500     (PTR) 0,
1501     { 0, 0, { 0 } }
1502   },
1503 /* call:D @$Ri */
1504   {
1505     { 1, 1, 1, 1 },
1506     FR30_INSN_CALLRD, "callrd", "call:D",
1507     { { MNEM, ' ', '@', OP (RI), 0 } },
1508     { 16, 16, 0xfff0 }, 0x9f10,
1509     (PTR) 0,
1510     { 0, 0, { 0 } }
1511   },
1512 /* call $label12 */
1513   {
1514     { 1, 1, 1, 1 },
1515     FR30_INSN_CALL, "call", "call",
1516     { { MNEM, ' ', OP (LABEL12), 0 } },
1517     { 16, 16, 0xf400 }, 0xd000,
1518     (PTR) 0,
1519     { 0, 0, { 0 } }
1520   },
1521 /* call:D $label12 */
1522   {
1523     { 1, 1, 1, 1 },
1524     FR30_INSN_CALLD, "calld", "call:D",
1525     { { MNEM, ' ', OP (LABEL12), 0 } },
1526     { 16, 16, 0xf400 }, 0xd400,
1527     (PTR) 0,
1528     { 0, 0, { 0 } }
1529   },
1530 /* ret */
1531   {
1532     { 1, 1, 1, 1 },
1533     FR30_INSN_RET, "ret", "ret",
1534     { { MNEM, 0 } },
1535     { 16, 16, 0xffff }, 0x9720,
1536     (PTR) 0,
1537     { 0, 0, { 0 } }
1538   },
1539 /* ret:D */
1540   {
1541     { 1, 1, 1, 1 },
1542     FR30_INSN_RETD, "retd", "ret:D",
1543     { { MNEM, 0 } },
1544     { 16, 16, 0xffff }, 0x9f20,
1545     (PTR) 0,
1546     { 0, 0, { 0 } }
1547   },
1548 /* int $u8 */
1549   {
1550     { 1, 1, 1, 1 },
1551     FR30_INSN_INT, "int", "int",
1552     { { MNEM, ' ', OP (U8), 0 } },
1553     { 16, 16, 0xff00 }, 0x1f00,
1554     (PTR) & fmt_int_ops[0],
1555     { 0, 0|A(UNCOND_CTI), { 0 } }
1556   },
1557 /* inte */
1558   {
1559     { 1, 1, 1, 1 },
1560     FR30_INSN_INTE, "inte", "inte",
1561     { { MNEM, 0 } },
1562     { 16, 16, 0xffff }, 0x9f30,
1563     (PTR) 0,
1564     { 0, 0, { 0 } }
1565   },
1566 /* reti */
1567   {
1568     { 1, 1, 1, 1 },
1569     FR30_INSN_RETI, "reti", "reti",
1570     { { MNEM, 0 } },
1571     { 16, 16, 0xffff }, 0x9730,
1572     (PTR) & fmt_reti_ops[0],
1573     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
1574   },
1575 /* bra $label9 */
1576   {
1577     { 1, 1, 1, 1 },
1578     FR30_INSN_BRA, "bra", "bra",
1579     { { MNEM, ' ', OP (LABEL9), 0 } },
1580     { 16, 16, 0xff00 }, 0xe000,
1581     (PTR) 0,
1582     { 0, 0, { 0 } }
1583   },
1584 /* bno $label9 */
1585   {
1586     { 1, 1, 1, 1 },
1587     FR30_INSN_BNO, "bno", "bno",
1588     { { MNEM, ' ', OP (LABEL9), 0 } },
1589     { 16, 16, 0xff00 }, 0xe100,
1590     (PTR) 0,
1591     { 0, 0, { 0 } }
1592   },
1593 /* beq $label9 */
1594   {
1595     { 1, 1, 1, 1 },
1596     FR30_INSN_BEQ, "beq", "beq",
1597     { { MNEM, ' ', OP (LABEL9), 0 } },
1598     { 16, 16, 0xff00 }, 0xe200,
1599     (PTR) 0,
1600     { 0, 0, { 0 } }
1601   },
1602 /* bne $label9 */
1603   {
1604     { 1, 1, 1, 1 },
1605     FR30_INSN_BNE, "bne", "bne",
1606     { { MNEM, ' ', OP (LABEL9), 0 } },
1607     { 16, 16, 0xff00 }, 0xe300,
1608     (PTR) 0,
1609     { 0, 0, { 0 } }
1610   },
1611 /* bc $label9 */
1612   {
1613     { 1, 1, 1, 1 },
1614     FR30_INSN_BC, "bc", "bc",
1615     { { MNEM, ' ', OP (LABEL9), 0 } },
1616     { 16, 16, 0xff00 }, 0xe400,
1617     (PTR) 0,
1618     { 0, 0, { 0 } }
1619   },
1620 /* bnc $label9 */
1621   {
1622     { 1, 1, 1, 1 },
1623     FR30_INSN_BNC, "bnc", "bnc",
1624     { { MNEM, ' ', OP (LABEL9), 0 } },
1625     { 16, 16, 0xff00 }, 0xe500,
1626     (PTR) 0,
1627     { 0, 0, { 0 } }
1628   },
1629 /* bn $label9 */
1630   {
1631     { 1, 1, 1, 1 },
1632     FR30_INSN_BN, "bn", "bn",
1633     { { MNEM, ' ', OP (LABEL9), 0 } },
1634     { 16, 16, 0xff00 }, 0xe600,
1635     (PTR) 0,
1636     { 0, 0, { 0 } }
1637   },
1638 /* bp $label9 */
1639   {
1640     { 1, 1, 1, 1 },
1641     FR30_INSN_BP, "bp", "bp",
1642     { { MNEM, ' ', OP (LABEL9), 0 } },
1643     { 16, 16, 0xff00 }, 0xe700,
1644     (PTR) 0,
1645     { 0, 0, { 0 } }
1646   },
1647 /* bv $label9 */
1648   {
1649     { 1, 1, 1, 1 },
1650     FR30_INSN_BV, "bv", "bv",
1651     { { MNEM, ' ', OP (LABEL9), 0 } },
1652     { 16, 16, 0xff00 }, 0xe800,
1653     (PTR) 0,
1654     { 0, 0, { 0 } }
1655   },
1656 /* bnv $label9 */
1657   {
1658     { 1, 1, 1, 1 },
1659     FR30_INSN_BNV, "bnv", "bnv",
1660     { { MNEM, ' ', OP (LABEL9), 0 } },
1661     { 16, 16, 0xff00 }, 0xe900,
1662     (PTR) 0,
1663     { 0, 0, { 0 } }
1664   },
1665 /* blt $label9 */
1666   {
1667     { 1, 1, 1, 1 },
1668     FR30_INSN_BLT, "blt", "blt",
1669     { { MNEM, ' ', OP (LABEL9), 0 } },
1670     { 16, 16, 0xff00 }, 0xea00,
1671     (PTR) 0,
1672     { 0, 0, { 0 } }
1673   },
1674 /* bge $label9 */
1675   {
1676     { 1, 1, 1, 1 },
1677     FR30_INSN_BGE, "bge", "bge",
1678     { { MNEM, ' ', OP (LABEL9), 0 } },
1679     { 16, 16, 0xff00 }, 0xeb00,
1680     (PTR) 0,
1681     { 0, 0, { 0 } }
1682   },
1683 /* ble $label9 */
1684   {
1685     { 1, 1, 1, 1 },
1686     FR30_INSN_BLE, "ble", "ble",
1687     { { MNEM, ' ', OP (LABEL9), 0 } },
1688     { 16, 16, 0xff00 }, 0xec00,
1689     (PTR) 0,
1690     { 0, 0, { 0 } }
1691   },
1692 /* bgt $label9 */
1693   {
1694     { 1, 1, 1, 1 },
1695     FR30_INSN_BGT, "bgt", "bgt",
1696     { { MNEM, ' ', OP (LABEL9), 0 } },
1697     { 16, 16, 0xff00 }, 0xed00,
1698     (PTR) 0,
1699     { 0, 0, { 0 } }
1700   },
1701 /* bls $label9 */
1702   {
1703     { 1, 1, 1, 1 },
1704     FR30_INSN_BLS, "bls", "bls",
1705     { { MNEM, ' ', OP (LABEL9), 0 } },
1706     { 16, 16, 0xff00 }, 0xee00,
1707     (PTR) 0,
1708     { 0, 0, { 0 } }
1709   },
1710 /* bhi $label9 */
1711   {
1712     { 1, 1, 1, 1 },
1713     FR30_INSN_BHI, "bhi", "bhi",
1714     { { MNEM, ' ', OP (LABEL9), 0 } },
1715     { 16, 16, 0xff00 }, 0xef00,
1716     (PTR) 0,
1717     { 0, 0, { 0 } }
1718   },
1719 /* bra:D $label9 */
1720   {
1721     { 1, 1, 1, 1 },
1722     FR30_INSN_BRAD, "brad", "bra:D",
1723     { { MNEM, ' ', OP (LABEL9), 0 } },
1724     { 16, 16, 0xff00 }, 0xf000,
1725     (PTR) 0,
1726     { 0, 0, { 0 } }
1727   },
1728 /* bno:D $label9 */
1729   {
1730     { 1, 1, 1, 1 },
1731     FR30_INSN_BNOD, "bnod", "bno:D",
1732     { { MNEM, ' ', OP (LABEL9), 0 } },
1733     { 16, 16, 0xff00 }, 0xf100,
1734     (PTR) 0,
1735     { 0, 0, { 0 } }
1736   },
1737 /* beq:D $label9 */
1738   {
1739     { 1, 1, 1, 1 },
1740     FR30_INSN_BEQD, "beqd", "beq:D",
1741     { { MNEM, ' ', OP (LABEL9), 0 } },
1742     { 16, 16, 0xff00 }, 0xf200,
1743     (PTR) 0,
1744     { 0, 0, { 0 } }
1745   },
1746 /* bne:D $label9 */
1747   {
1748     { 1, 1, 1, 1 },
1749     FR30_INSN_BNED, "bned", "bne:D",
1750     { { MNEM, ' ', OP (LABEL9), 0 } },
1751     { 16, 16, 0xff00 }, 0xf300,
1752     (PTR) 0,
1753     { 0, 0, { 0 } }
1754   },
1755 /* bc:D $label9 */
1756   {
1757     { 1, 1, 1, 1 },
1758     FR30_INSN_BCD, "bcd", "bc:D",
1759     { { MNEM, ' ', OP (LABEL9), 0 } },
1760     { 16, 16, 0xff00 }, 0xf400,
1761     (PTR) 0,
1762     { 0, 0, { 0 } }
1763   },
1764 /* bnc:D $label9 */
1765   {
1766     { 1, 1, 1, 1 },
1767     FR30_INSN_BNCD, "bncd", "bnc:D",
1768     { { MNEM, ' ', OP (LABEL9), 0 } },
1769     { 16, 16, 0xff00 }, 0xf500,
1770     (PTR) 0,
1771     { 0, 0, { 0 } }
1772   },
1773 /* bn:D $label9 */
1774   {
1775     { 1, 1, 1, 1 },
1776     FR30_INSN_BND, "bnd", "bn:D",
1777     { { MNEM, ' ', OP (LABEL9), 0 } },
1778     { 16, 16, 0xff00 }, 0xf600,
1779     (PTR) 0,
1780     { 0, 0, { 0 } }
1781   },
1782 /* bp:D $label9 */
1783   {
1784     { 1, 1, 1, 1 },
1785     FR30_INSN_BPD, "bpd", "bp:D",
1786     { { MNEM, ' ', OP (LABEL9), 0 } },
1787     { 16, 16, 0xff00 }, 0xf700,
1788     (PTR) 0,
1789     { 0, 0, { 0 } }
1790   },
1791 /* bv:D $label9 */
1792   {
1793     { 1, 1, 1, 1 },
1794     FR30_INSN_BVD, "bvd", "bv:D",
1795     { { MNEM, ' ', OP (LABEL9), 0 } },
1796     { 16, 16, 0xff00 }, 0xf800,
1797     (PTR) 0,
1798     { 0, 0, { 0 } }
1799   },
1800 /* bnv:D $label9 */
1801   {
1802     { 1, 1, 1, 1 },
1803     FR30_INSN_BNVD, "bnvd", "bnv:D",
1804     { { MNEM, ' ', OP (LABEL9), 0 } },
1805     { 16, 16, 0xff00 }, 0xf900,
1806     (PTR) 0,
1807     { 0, 0, { 0 } }
1808   },
1809 /* blt:D $label9 */
1810   {
1811     { 1, 1, 1, 1 },
1812     FR30_INSN_BLTD, "bltd", "blt:D",
1813     { { MNEM, ' ', OP (LABEL9), 0 } },
1814     { 16, 16, 0xff00 }, 0xfa00,
1815     (PTR) 0,
1816     { 0, 0, { 0 } }
1817   },
1818 /* bge:D $label9 */
1819   {
1820     { 1, 1, 1, 1 },
1821     FR30_INSN_BGED, "bged", "bge:D",
1822     { { MNEM, ' ', OP (LABEL9), 0 } },
1823     { 16, 16, 0xff00 }, 0xfb00,
1824     (PTR) 0,
1825     { 0, 0, { 0 } }
1826   },
1827 /* ble:D $label9 */
1828   {
1829     { 1, 1, 1, 1 },
1830     FR30_INSN_BLED, "bled", "ble:D",
1831     { { MNEM, ' ', OP (LABEL9), 0 } },
1832     { 16, 16, 0xff00 }, 0xfc00,
1833     (PTR) 0,
1834     { 0, 0, { 0 } }
1835   },
1836 /* bgt:D $label9 */
1837   {
1838     { 1, 1, 1, 1 },
1839     FR30_INSN_BGTD, "bgtd", "bgt:D",
1840     { { MNEM, ' ', OP (LABEL9), 0 } },
1841     { 16, 16, 0xff00 }, 0xfd00,
1842     (PTR) 0,
1843     { 0, 0, { 0 } }
1844   },
1845 /* bls:D $label9 */
1846   {
1847     { 1, 1, 1, 1 },
1848     FR30_INSN_BLSD, "blsd", "bls:D",
1849     { { MNEM, ' ', OP (LABEL9), 0 } },
1850     { 16, 16, 0xff00 }, 0xfe00,
1851     (PTR) 0,
1852     { 0, 0, { 0 } }
1853   },
1854 /* bhi:D $label9 */
1855   {
1856     { 1, 1, 1, 1 },
1857     FR30_INSN_BHID, "bhid", "bhi:D",
1858     { { MNEM, ' ', OP (LABEL9), 0 } },
1859     { 16, 16, 0xff00 }, 0xff00,
1860     (PTR) 0,
1861     { 0, 0, { 0 } }
1862   },
1863 /* dmov $R13,@$dir10 */
1864   {
1865     { 1, 1, 1, 1 },
1866     FR30_INSN_DMOVR13, "dmovr13", "dmov",
1867     { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
1868     { 16, 16, 0xff00 }, 0x1800,
1869     (PTR) 0,
1870     { 0, 0, { 0 } }
1871   },
1872 /* dmovh $R13,@$dir9 */
1873   {
1874     { 1, 1, 1, 1 },
1875     FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
1876     { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
1877     { 16, 16, 0xff00 }, 0x1900,
1878     (PTR) 0,
1879     { 0, 0, { 0 } }
1880   },
1881 /* dmovb $R13,@$dir8 */
1882   {
1883     { 1, 1, 1, 1 },
1884     FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
1885     { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
1886     { 16, 16, 0xff00 }, 0x1a00,
1887     (PTR) 0,
1888     { 0, 0, { 0 } }
1889   },
1890 /* dmov @$R13+,@$dir10 */
1891   {
1892     { 1, 1, 1, 1 },
1893     FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
1894     { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
1895     { 16, 16, 0xff00 }, 0x1c00,
1896     (PTR) 0,
1897     { 0, 0, { 0 } }
1898   },
1899 /* dmovh @$R13+,@$dir9 */
1900   {
1901     { 1, 1, 1, 1 },
1902     FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
1903     { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
1904     { 16, 16, 0xff00 }, 0x1d00,
1905     (PTR) 0,
1906     { 0, 0, { 0 } }
1907   },
1908 /* dmovb @$R13+,@$dir8 */
1909   {
1910     { 1, 1, 1, 1 },
1911     FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
1912     { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
1913     { 16, 16, 0xff00 }, 0x1e00,
1914     (PTR) 0,
1915     { 0, 0, { 0 } }
1916   },
1917 /* dmov @$R15+,@$dir10 */
1918   {
1919     { 1, 1, 1, 1 },
1920     FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
1921     { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
1922     { 16, 16, 0xff00 }, 0x1b00,
1923     (PTR) 0,
1924     { 0, 0, { 0 } }
1925   },
1926 /* dmov @$dir10,$R13 */
1927   {
1928     { 1, 1, 1, 1 },
1929     FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
1930     { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
1931     { 16, 16, 0xff00 }, 0x800,
1932     (PTR) 0,
1933     { 0, 0, { 0 } }
1934   },
1935 /* dmovh @$dir9,$R13 */
1936   {
1937     { 1, 1, 1, 1 },
1938     FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
1939     { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
1940     { 16, 16, 0xff00 }, 0x900,
1941     (PTR) 0,
1942     { 0, 0, { 0 } }
1943   },
1944 /* dmovb @$dir8,$R13 */
1945   {
1946     { 1, 1, 1, 1 },
1947     FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
1948     { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
1949     { 16, 16, 0xff00 }, 0xa00,
1950     (PTR) 0,
1951     { 0, 0, { 0 } }
1952   },
1953 /* dmov @$dir10,@$R13+ */
1954   {
1955     { 1, 1, 1, 1 },
1956     FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
1957     { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
1958     { 16, 16, 0xff00 }, 0xc00,
1959     (PTR) 0,
1960     { 0, 0, { 0 } }
1961   },
1962 /* dmovh @$dir9,@$R13+ */
1963   {
1964     { 1, 1, 1, 1 },
1965     FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
1966     { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
1967     { 16, 16, 0xff00 }, 0xd00,
1968     (PTR) 0,
1969     { 0, 0, { 0 } }
1970   },
1971 /* dmovb @$dir8,@$R13+ */
1972   {
1973     { 1, 1, 1, 1 },
1974     FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
1975     { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
1976     { 16, 16, 0xff00 }, 0xe00,
1977     (PTR) 0,
1978     { 0, 0, { 0 } }
1979   },
1980 /* dmov @$dir10,@-$R15 */
1981   {
1982     { 1, 1, 1, 1 },
1983     FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
1984     { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
1985     { 16, 16, 0xff00 }, 0xb00,
1986     (PTR) 0,
1987     { 0, 0, { 0 } }
1988   },
1989 /* ldres @$Ri+,$u4 */
1990   {
1991     { 1, 1, 1, 1 },
1992     FR30_INSN_LDRES, "ldres", "ldres",
1993     { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
1994     { 16, 16, 0xff00 }, 0xbc00,
1995     (PTR) 0,
1996     { 0, 0, { 0 } }
1997   },
1998 /* stres $u4,@$Ri+ */
1999   {
2000     { 1, 1, 1, 1 },
2001     FR30_INSN_STRES, "stres", "stres",
2002     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
2003     { 16, 16, 0xff00 }, 0xbd00,
2004     (PTR) 0,
2005     { 0, 0, { 0 } }
2006   },
2007 /* copop $u4c,$ccc,$CRj,$CRi */
2008   {
2009     { 1, 1, 1, 1 },
2010     FR30_INSN_COPOP, "copop", "copop",
2011     { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
2012     { 16, 32, 0xfff0 }, 0x9fc0,
2013     (PTR) 0,
2014     { 0, 0, { 0 } }
2015   },
2016 /* copld $u4c,$ccc,$Rjc,$CRi */
2017   {
2018     { 1, 1, 1, 1 },
2019     FR30_INSN_COPLD, "copld", "copld",
2020     { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
2021     { 16, 32, 0xfff0 }, 0x9fd0,
2022     (PTR) 0,
2023     { 0, 0, { 0 } }
2024   },
2025 /* copst $u4c,$ccc,$CRj,$Ric */
2026   {
2027     { 1, 1, 1, 1 },
2028     FR30_INSN_COPST, "copst", "copst",
2029     { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2030     { 16, 32, 0xfff0 }, 0x9fe0,
2031     (PTR) 0,
2032     { 0, 0, { 0 } }
2033   },
2034 /* copsv $u4c,$ccc,$CRj,$Ric */
2035   {
2036     { 1, 1, 1, 1 },
2037     FR30_INSN_COPSV, "copsv", "copsv",
2038     { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2039     { 16, 32, 0xfff0 }, 0x9ff0,
2040     (PTR) 0,
2041     { 0, 0, { 0 } }
2042   },
2043 /* nop */
2044   {
2045     { 1, 1, 1, 1 },
2046     FR30_INSN_NOP, "nop", "nop",
2047     { { MNEM, 0 } },
2048     { 16, 16, 0xffff }, 0x9fa0,
2049     (PTR) 0,
2050     { 0, 0, { 0 } }
2051   },
2052 /* andccr $u8 */
2053   {
2054     { 1, 1, 1, 1 },
2055     FR30_INSN_ANDCCR, "andccr", "andccr",
2056     { { MNEM, ' ', OP (U8), 0 } },
2057     { 16, 16, 0xff00 }, 0x8300,
2058     (PTR) 0,
2059     { 0, 0, { 0 } }
2060   },
2061 /* orccr $u8 */
2062   {
2063     { 1, 1, 1, 1 },
2064     FR30_INSN_ORCCR, "orccr", "orccr",
2065     { { MNEM, ' ', OP (U8), 0 } },
2066     { 16, 16, 0xff00 }, 0x9300,
2067     (PTR) 0,
2068     { 0, 0, { 0 } }
2069   },
2070 /* stilm $u8 */
2071   {
2072     { 1, 1, 1, 1 },
2073     FR30_INSN_STILM, "stilm", "stilm",
2074     { { MNEM, ' ', OP (U8), 0 } },
2075     { 16, 16, 0xff00 }, 0x8700,
2076     (PTR) 0,
2077     { 0, 0, { 0 } }
2078   },
2079 /* addsp $s10 */
2080   {
2081     { 1, 1, 1, 1 },
2082     FR30_INSN_ADDSP, "addsp", "addsp",
2083     { { MNEM, ' ', OP (S10), 0 } },
2084     { 16, 16, 0xff00 }, 0xa300,
2085     (PTR) 0,
2086     { 0, 0, { 0 } }
2087   },
2088 /* extsb $Ri */
2089   {
2090     { 1, 1, 1, 1 },
2091     FR30_INSN_EXTSB, "extsb", "extsb",
2092     { { MNEM, ' ', OP (RI), 0 } },
2093     { 16, 16, 0xfff0 }, 0x9780,
2094     (PTR) 0,
2095     { 0, 0, { 0 } }
2096   },
2097 /* extub $Ri */
2098   {
2099     { 1, 1, 1, 1 },
2100     FR30_INSN_EXTUB, "extub", "extub",
2101     { { MNEM, ' ', OP (RI), 0 } },
2102     { 16, 16, 0xfff0 }, 0x9790,
2103     (PTR) 0,
2104     { 0, 0, { 0 } }
2105   },
2106 /* extsh $Ri */
2107   {
2108     { 1, 1, 1, 1 },
2109     FR30_INSN_EXTSH, "extsh", "extsh",
2110     { { MNEM, ' ', OP (RI), 0 } },
2111     { 16, 16, 0xfff0 }, 0x97a0,
2112     (PTR) 0,
2113     { 0, 0, { 0 } }
2114   },
2115 /* extuh $Ri */
2116   {
2117     { 1, 1, 1, 1 },
2118     FR30_INSN_EXTUH, "extuh", "extuh",
2119     { { MNEM, ' ', OP (RI), 0 } },
2120     { 16, 16, 0xfff0 }, 0x97b0,
2121     (PTR) 0,
2122     { 0, 0, { 0 } }
2123   },
2124 /* ldm0 ($reglist_low) */
2125   {
2126     { 1, 1, 1, 1 },
2127     FR30_INSN_LDM0, "ldm0", "ldm0",
2128     { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
2129     { 16, 16, 0xff00 }, 0x8c00,
2130     (PTR) 0,
2131     { 0, 0, { 0 } }
2132   },
2133 /* ldm1 ($reglist_hi) */
2134   {
2135     { 1, 1, 1, 1 },
2136     FR30_INSN_LDM1, "ldm1", "ldm1",
2137     { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
2138     { 16, 16, 0xff00 }, 0x8d00,
2139     (PTR) 0,
2140     { 0, 0, { 0 } }
2141   },
2142 /* stm0 ($reglist_low) */
2143   {
2144     { 1, 1, 1, 1 },
2145     FR30_INSN_STM0, "stm0", "stm0",
2146     { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
2147     { 16, 16, 0xff00 }, 0x8e00,
2148     (PTR) 0,
2149     { 0, 0, { 0 } }
2150   },
2151 /* stm1 ($reglist_hi) */
2152   {
2153     { 1, 1, 1, 1 },
2154     FR30_INSN_STM1, "stm1", "stm1",
2155     { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
2156     { 16, 16, 0xff00 }, 0x8f00,
2157     (PTR) 0,
2158     { 0, 0, { 0 } }
2159   },
2160 /* enter $u10 */
2161   {
2162     { 1, 1, 1, 1 },
2163     FR30_INSN_ENTER, "enter", "enter",
2164     { { MNEM, ' ', OP (U10), 0 } },
2165     { 16, 16, 0xff00 }, 0xf00,
2166     (PTR) 0,
2167     { 0, 0, { 0 } }
2168   },
2169 /* leave */
2170   {
2171     { 1, 1, 1, 1 },
2172     FR30_INSN_LEAVE, "leave", "leave",
2173     { { MNEM, 0 } },
2174     { 16, 16, 0xffff }, 0x9f90,
2175     (PTR) 0,
2176     { 0, 0, { 0 } }
2177   },
2178 /* xchb @$Rj,$Ri */
2179   {
2180     { 1, 1, 1, 1 },
2181     FR30_INSN_XCHB, "xchb", "xchb",
2182     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2183     { 16, 16, 0xff00 }, 0x8a00,
2184     (PTR) 0,
2185     { 0, 0, { 0 } }
2186   },
2187 };
2188
2189 #undef A
2190 #undef MNEM
2191 #undef OP
2192
2193 static const CGEN_INSN_TABLE insn_table =
2194 {
2195   & fr30_cgen_insn_table_entries[0],
2196   sizeof (CGEN_INSN),
2197   MAX_INSNS,
2198   NULL
2199 };
2200
2201 /* Each non-simple macro entry points to an array of expansion possibilities.  */
2202
2203 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2204 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2205 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2206
2207 /* The macro instruction table.  */
2208
2209 static const CGEN_INSN macro_insn_table_entries[] =
2210 {
2211 /* ldi32 $i32,$Ri */
2212   {
2213     { 1, 1, 1, 1 },
2214     -1, "ldi32m", "ldi32",
2215     { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
2216     { 16, 48, 0xfff0 }, 0x9f80,
2217     (PTR) 0,
2218     { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
2219   },
2220 };
2221
2222 #undef A
2223 #undef MNEM
2224 #undef OP
2225
2226 static const CGEN_INSN_TABLE macro_insn_table =
2227 {
2228   & macro_insn_table_entries[0],
2229   sizeof (CGEN_INSN),
2230   (sizeof (macro_insn_table_entries) /
2231    sizeof (macro_insn_table_entries[0])),
2232   NULL
2233 };
2234
2235 static void
2236 init_tables ()
2237 {
2238 }
2239
2240 /* Return non-zero if INSN is to be added to the hash table.
2241    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
2242
2243 static int
2244 asm_hash_insn_p (insn)
2245      const CGEN_INSN * insn;
2246 {
2247   return CGEN_ASM_HASH_P (insn);
2248 }
2249
2250 static int
2251 dis_hash_insn_p (insn)
2252      const CGEN_INSN * insn;
2253 {
2254   /* If building the hash table and the NO-DIS attribute is present,
2255      ignore.  */
2256   if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2257     return 0;
2258   return CGEN_DIS_HASH_P (insn);
2259 }
2260
2261 /* The result is the hash value of the insn.
2262    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
2263
2264 static unsigned int
2265 asm_hash_insn (mnem)
2266      const char * mnem;
2267 {
2268   return CGEN_ASM_HASH (mnem);
2269 }
2270
2271 /* BUF is a pointer to the insn's bytes in target order.
2272    VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
2273    host order.  */
2274
2275 static unsigned int
2276 dis_hash_insn (buf, value)
2277      const char * buf;
2278      CGEN_INSN_INT value;
2279 {
2280   return CGEN_DIS_HASH (buf, value);
2281 }
2282
2283 /* Initialize an opcode table and return a descriptor.
2284    It's much like opening a file, and must be the first function called.  */
2285
2286 CGEN_OPCODE_DESC
2287 fr30_cgen_opcode_open (mach, endian)
2288      int mach;
2289      enum cgen_endian endian;
2290 {
2291   CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2292   static int init_p;
2293
2294   if (! init_p)
2295     {
2296       init_tables ();
2297       init_p = 1;
2298     }
2299
2300   memset (table, 0, sizeof (*table));
2301
2302   CGEN_OPCODE_MACH (table) = mach;
2303   CGEN_OPCODE_ENDIAN (table) = endian;
2304   /* FIXME: for the sparc case we can determine insn-endianness statically.
2305      The worry here is where both data and insn endian can be independently
2306      chosen, in which case this function will need another argument.
2307      Actually, will want to allow for more arguments in the future anyway.  */
2308   CGEN_OPCODE_INSN_ENDIAN (table) = endian;
2309
2310   CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
2311
2312   CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
2313
2314   * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2315
2316   * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2317
2318   CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2319   CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2320   CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2321
2322   CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2323   CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2324   CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2325
2326   return (CGEN_OPCODE_DESC) table;
2327 }
2328
2329 /* Close an opcode table.  */
2330
2331 void
2332 fr30_cgen_opcode_close (desc)
2333      CGEN_OPCODE_DESC desc;
2334 {
2335   free (desc);
2336 }
2337
2338 /* Getting values from cgen_fields is handled by a collection of functions.
2339    They are distinguished by the type of the VALUE argument they return.
2340    TODO: floating point, inlining support, remove cases where result type
2341    not appropriate.  */
2342
2343 int
2344 fr30_cgen_get_int_operand (opindex, fields)
2345      int opindex;
2346      const CGEN_FIELDS * fields;
2347 {
2348   int value;
2349
2350   switch (opindex)
2351     {
2352     case FR30_OPERAND_RI :
2353       value = fields->f_Ri;
2354       break;
2355     case FR30_OPERAND_RJ :
2356       value = fields->f_Rj;
2357       break;
2358     case FR30_OPERAND_RIC :
2359       value = fields->f_Ric;
2360       break;
2361     case FR30_OPERAND_RJC :
2362       value = fields->f_Rjc;
2363       break;
2364     case FR30_OPERAND_CRI :
2365       value = fields->f_CRi;
2366       break;
2367     case FR30_OPERAND_CRJ :
2368       value = fields->f_CRj;
2369       break;
2370     case FR30_OPERAND_RS1 :
2371       value = fields->f_Rs1;
2372       break;
2373     case FR30_OPERAND_RS2 :
2374       value = fields->f_Rs2;
2375       break;
2376     case FR30_OPERAND_R13 :
2377       value = fields->f_nil;
2378       break;
2379     case FR30_OPERAND_R14 :
2380       value = fields->f_nil;
2381       break;
2382     case FR30_OPERAND_R15 :
2383       value = fields->f_nil;
2384       break;
2385     case FR30_OPERAND_PS :
2386       value = fields->f_nil;
2387       break;
2388     case FR30_OPERAND_U4 :
2389       value = fields->f_u4;
2390       break;
2391     case FR30_OPERAND_U4C :
2392       value = fields->f_u4c;
2393       break;
2394     case FR30_OPERAND_M4 :
2395       value = fields->f_m4;
2396       break;
2397     case FR30_OPERAND_U8 :
2398       value = fields->f_u8;
2399       break;
2400     case FR30_OPERAND_I8 :
2401       value = fields->f_i8;
2402       break;
2403     case FR30_OPERAND_UDISP6 :
2404       value = fields->f_udisp6;
2405       break;
2406     case FR30_OPERAND_DISP8 :
2407       value = fields->f_disp8;
2408       break;
2409     case FR30_OPERAND_DISP9 :
2410       value = fields->f_disp9;
2411       break;
2412     case FR30_OPERAND_DISP10 :
2413       value = fields->f_disp10;
2414       break;
2415     case FR30_OPERAND_S10 :
2416       value = fields->f_s10;
2417       break;
2418     case FR30_OPERAND_U10 :
2419       value = fields->f_u10;
2420       break;
2421     case FR30_OPERAND_I32 :
2422       value = fields->f_i32;
2423       break;
2424     case FR30_OPERAND_DIR8 :
2425       value = fields->f_dir8;
2426       break;
2427     case FR30_OPERAND_DIR9 :
2428       value = fields->f_dir9;
2429       break;
2430     case FR30_OPERAND_DIR10 :
2431       value = fields->f_dir10;
2432       break;
2433     case FR30_OPERAND_LABEL9 :
2434       value = fields->f_rel9;
2435       break;
2436     case FR30_OPERAND_LABEL12 :
2437       value = fields->f_rel12;
2438       break;
2439     case FR30_OPERAND_REGLIST_LOW :
2440       value = fields->f_reglist_low;
2441       break;
2442     case FR30_OPERAND_REGLIST_HI :
2443       value = fields->f_reglist_hi;
2444       break;
2445     case FR30_OPERAND_CC :
2446       value = fields->f_cc;
2447       break;
2448     case FR30_OPERAND_CCC :
2449       value = fields->f_ccc;
2450       break;
2451
2452     default :
2453       /* xgettext:c-format */
2454       fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2455                        opindex);
2456       abort ();
2457   }
2458
2459   return value;
2460 }
2461
2462 bfd_vma
2463 fr30_cgen_get_vma_operand (opindex, fields)
2464      int opindex;
2465      const CGEN_FIELDS * fields;
2466 {
2467   bfd_vma value;
2468
2469   switch (opindex)
2470     {
2471     case FR30_OPERAND_RI :
2472       value = fields->f_Ri;
2473       break;
2474     case FR30_OPERAND_RJ :
2475       value = fields->f_Rj;
2476       break;
2477     case FR30_OPERAND_RIC :
2478       value = fields->f_Ric;
2479       break;
2480     case FR30_OPERAND_RJC :
2481       value = fields->f_Rjc;
2482       break;
2483     case FR30_OPERAND_CRI :
2484       value = fields->f_CRi;
2485       break;
2486     case FR30_OPERAND_CRJ :
2487       value = fields->f_CRj;
2488       break;
2489     case FR30_OPERAND_RS1 :
2490       value = fields->f_Rs1;
2491       break;
2492     case FR30_OPERAND_RS2 :
2493       value = fields->f_Rs2;
2494       break;
2495     case FR30_OPERAND_R13 :
2496       value = fields->f_nil;
2497       break;
2498     case FR30_OPERAND_R14 :
2499       value = fields->f_nil;
2500       break;
2501     case FR30_OPERAND_R15 :
2502       value = fields->f_nil;
2503       break;
2504     case FR30_OPERAND_PS :
2505       value = fields->f_nil;
2506       break;
2507     case FR30_OPERAND_U4 :
2508       value = fields->f_u4;
2509       break;
2510     case FR30_OPERAND_U4C :
2511       value = fields->f_u4c;
2512       break;
2513     case FR30_OPERAND_M4 :
2514       value = fields->f_m4;
2515       break;
2516     case FR30_OPERAND_U8 :
2517       value = fields->f_u8;
2518       break;
2519     case FR30_OPERAND_I8 :
2520       value = fields->f_i8;
2521       break;
2522     case FR30_OPERAND_UDISP6 :
2523       value = fields->f_udisp6;
2524       break;
2525     case FR30_OPERAND_DISP8 :
2526       value = fields->f_disp8;
2527       break;
2528     case FR30_OPERAND_DISP9 :
2529       value = fields->f_disp9;
2530       break;
2531     case FR30_OPERAND_DISP10 :
2532       value = fields->f_disp10;
2533       break;
2534     case FR30_OPERAND_S10 :
2535       value = fields->f_s10;
2536       break;
2537     case FR30_OPERAND_U10 :
2538       value = fields->f_u10;
2539       break;
2540     case FR30_OPERAND_I32 :
2541       value = fields->f_i32;
2542       break;
2543     case FR30_OPERAND_DIR8 :
2544       value = fields->f_dir8;
2545       break;
2546     case FR30_OPERAND_DIR9 :
2547       value = fields->f_dir9;
2548       break;
2549     case FR30_OPERAND_DIR10 :
2550       value = fields->f_dir10;
2551       break;
2552     case FR30_OPERAND_LABEL9 :
2553       value = fields->f_rel9;
2554       break;
2555     case FR30_OPERAND_LABEL12 :
2556       value = fields->f_rel12;
2557       break;
2558     case FR30_OPERAND_REGLIST_LOW :
2559       value = fields->f_reglist_low;
2560       break;
2561     case FR30_OPERAND_REGLIST_HI :
2562       value = fields->f_reglist_hi;
2563       break;
2564     case FR30_OPERAND_CC :
2565       value = fields->f_cc;
2566       break;
2567     case FR30_OPERAND_CCC :
2568       value = fields->f_ccc;
2569       break;
2570
2571     default :
2572       /* xgettext:c-format */
2573       fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
2574                        opindex);
2575       abort ();
2576   }
2577
2578   return value;
2579 }
2580
2581 /* Stuffing values in cgen_fields is handled by a collection of functions.
2582    They are distinguished by the type of the VALUE argument they accept.
2583    TODO: floating point, inlining support, remove cases where argument type
2584    not appropriate.  */
2585
2586 void
2587 fr30_cgen_set_int_operand (opindex, fields, value)
2588      int opindex;
2589      CGEN_FIELDS * fields;
2590      int value;
2591 {
2592   switch (opindex)
2593     {
2594     case FR30_OPERAND_RI :
2595       fields->f_Ri = value;
2596       break;
2597     case FR30_OPERAND_RJ :
2598       fields->f_Rj = value;
2599       break;
2600     case FR30_OPERAND_RIC :
2601       fields->f_Ric = value;
2602       break;
2603     case FR30_OPERAND_RJC :
2604       fields->f_Rjc = value;
2605       break;
2606     case FR30_OPERAND_CRI :
2607       fields->f_CRi = value;
2608       break;
2609     case FR30_OPERAND_CRJ :
2610       fields->f_CRj = value;
2611       break;
2612     case FR30_OPERAND_RS1 :
2613       fields->f_Rs1 = value;
2614       break;
2615     case FR30_OPERAND_RS2 :
2616       fields->f_Rs2 = value;
2617       break;
2618     case FR30_OPERAND_R13 :
2619       fields->f_nil = value;
2620       break;
2621     case FR30_OPERAND_R14 :
2622       fields->f_nil = value;
2623       break;
2624     case FR30_OPERAND_R15 :
2625       fields->f_nil = value;
2626       break;
2627     case FR30_OPERAND_PS :
2628       fields->f_nil = value;
2629       break;
2630     case FR30_OPERAND_U4 :
2631       fields->f_u4 = value;
2632       break;
2633     case FR30_OPERAND_U4C :
2634       fields->f_u4c = value;
2635       break;
2636     case FR30_OPERAND_M4 :
2637       fields->f_m4 = value;
2638       break;
2639     case FR30_OPERAND_U8 :
2640       fields->f_u8 = value;
2641       break;
2642     case FR30_OPERAND_I8 :
2643       fields->f_i8 = value;
2644       break;
2645     case FR30_OPERAND_UDISP6 :
2646       fields->f_udisp6 = value;
2647       break;
2648     case FR30_OPERAND_DISP8 :
2649       fields->f_disp8 = value;
2650       break;
2651     case FR30_OPERAND_DISP9 :
2652       fields->f_disp9 = value;
2653       break;
2654     case FR30_OPERAND_DISP10 :
2655       fields->f_disp10 = value;
2656       break;
2657     case FR30_OPERAND_S10 :
2658       fields->f_s10 = value;
2659       break;
2660     case FR30_OPERAND_U10 :
2661       fields->f_u10 = value;
2662       break;
2663     case FR30_OPERAND_I32 :
2664       fields->f_i32 = value;
2665       break;
2666     case FR30_OPERAND_DIR8 :
2667       fields->f_dir8 = value;
2668       break;
2669     case FR30_OPERAND_DIR9 :
2670       fields->f_dir9 = value;
2671       break;
2672     case FR30_OPERAND_DIR10 :
2673       fields->f_dir10 = value;
2674       break;
2675     case FR30_OPERAND_LABEL9 :
2676       fields->f_rel9 = value;
2677       break;
2678     case FR30_OPERAND_LABEL12 :
2679       fields->f_rel12 = value;
2680       break;
2681     case FR30_OPERAND_REGLIST_LOW :
2682       fields->f_reglist_low = value;
2683       break;
2684     case FR30_OPERAND_REGLIST_HI :
2685       fields->f_reglist_hi = value;
2686       break;
2687     case FR30_OPERAND_CC :
2688       fields->f_cc = value;
2689       break;
2690     case FR30_OPERAND_CCC :
2691       fields->f_ccc = value;
2692       break;
2693
2694     default :
2695       /* xgettext:c-format */
2696       fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2697                        opindex);
2698       abort ();
2699   }
2700 }
2701
2702 void
2703 fr30_cgen_set_vma_operand (opindex, fields, value)
2704      int opindex;
2705      CGEN_FIELDS * fields;
2706      bfd_vma value;
2707 {
2708   switch (opindex)
2709     {
2710     case FR30_OPERAND_RI :
2711       fields->f_Ri = value;
2712       break;
2713     case FR30_OPERAND_RJ :
2714       fields->f_Rj = value;
2715       break;
2716     case FR30_OPERAND_RIC :
2717       fields->f_Ric = value;
2718       break;
2719     case FR30_OPERAND_RJC :
2720       fields->f_Rjc = value;
2721       break;
2722     case FR30_OPERAND_CRI :
2723       fields->f_CRi = value;
2724       break;
2725     case FR30_OPERAND_CRJ :
2726       fields->f_CRj = value;
2727       break;
2728     case FR30_OPERAND_RS1 :
2729       fields->f_Rs1 = value;
2730       break;
2731     case FR30_OPERAND_RS2 :
2732       fields->f_Rs2 = value;
2733       break;
2734     case FR30_OPERAND_R13 :
2735       fields->f_nil = value;
2736       break;
2737     case FR30_OPERAND_R14 :
2738       fields->f_nil = value;
2739       break;
2740     case FR30_OPERAND_R15 :
2741       fields->f_nil = value;
2742       break;
2743     case FR30_OPERAND_PS :
2744       fields->f_nil = value;
2745       break;
2746     case FR30_OPERAND_U4 :
2747       fields->f_u4 = value;
2748       break;
2749     case FR30_OPERAND_U4C :
2750       fields->f_u4c = value;
2751       break;
2752     case FR30_OPERAND_M4 :
2753       fields->f_m4 = value;
2754       break;
2755     case FR30_OPERAND_U8 :
2756       fields->f_u8 = value;
2757       break;
2758     case FR30_OPERAND_I8 :
2759       fields->f_i8 = value;
2760       break;
2761     case FR30_OPERAND_UDISP6 :
2762       fields->f_udisp6 = value;
2763       break;
2764     case FR30_OPERAND_DISP8 :
2765       fields->f_disp8 = value;
2766       break;
2767     case FR30_OPERAND_DISP9 :
2768       fields->f_disp9 = value;
2769       break;
2770     case FR30_OPERAND_DISP10 :
2771       fields->f_disp10 = value;
2772       break;
2773     case FR30_OPERAND_S10 :
2774       fields->f_s10 = value;
2775       break;
2776     case FR30_OPERAND_U10 :
2777       fields->f_u10 = value;
2778       break;
2779     case FR30_OPERAND_I32 :
2780       fields->f_i32 = value;
2781       break;
2782     case FR30_OPERAND_DIR8 :
2783       fields->f_dir8 = value;
2784       break;
2785     case FR30_OPERAND_DIR9 :
2786       fields->f_dir9 = value;
2787       break;
2788     case FR30_OPERAND_DIR10 :
2789       fields->f_dir10 = value;
2790       break;
2791     case FR30_OPERAND_LABEL9 :
2792       fields->f_rel9 = value;
2793       break;
2794     case FR30_OPERAND_LABEL12 :
2795       fields->f_rel12 = value;
2796       break;
2797     case FR30_OPERAND_REGLIST_LOW :
2798       fields->f_reglist_low = value;
2799       break;
2800     case FR30_OPERAND_REGLIST_HI :
2801       fields->f_reglist_hi = value;
2802       break;
2803     case FR30_OPERAND_CC :
2804       fields->f_cc = value;
2805       break;
2806     case FR30_OPERAND_CCC :
2807       fields->f_ccc = value;
2808       break;
2809
2810     default :
2811       /* xgettext:c-format */
2812       fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
2813                        opindex);
2814       abort ();
2815   }
2816 }
2817