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* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerate.
[deliverable/binutils-gdb.git] / opcodes / fr30-opc.c
1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 THIS FILE IS USED TO GENERATE fr30-opc.c.
5
6 Copyright (C) 1998 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include "ansidecl.h"
27 #include "libiberty.h"
28 #include "bfd.h"
29 #include "symcat.h"
30 #include "fr30-opc.h"
31 #include "opintl.h"
32
33 /* Used by the ifield rtx function. */
34 #define FLD(f) (fields->f)
35
36 /* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
38
39 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
40 static unsigned int asm_hash_insn PARAMS ((const char *));
41 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
42 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
43
44 /* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
51
52 The result is a pointer to the insn table entry, or NULL if the instruction
53 wasn't recognized. */
54
55 const CGEN_INSN *
56 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
57 CGEN_OPCODE_DESC od;
58 const CGEN_INSN *insn;
59 CGEN_INSN_BYTES insn_value;
60 int length;
61 CGEN_FIELDS *fields;
62 int alias_p;
63 {
64 unsigned char buf[CGEN_MAX_INSN_SIZE];
65 unsigned char *bufp;
66 CGEN_INSN_INT base_insn;
67 #if CGEN_INT_INSN_P
68 CGEN_EXTRACT_INFO *info = NULL;
69 #else
70 CGEN_EXTRACT_INFO ex_info;
71 CGEN_EXTRACT_INFO *info = &ex_info;
72 #endif
73
74 #if CGEN_INT_INSN_P
75 cgen_put_insn_value (od, buf, length, insn_value);
76 bufp = buf;
77 base_insn = insn_value; /*???*/
78 #else
79 ex_info.dis_info = NULL;
80 ex_info.insn_bytes = insn_value;
81 ex_info.valid = -1;
82 base_insn = cgen_get_insn_value (od, buf, length);
83 bufp = insn_value;
84 #endif
85
86 if (!insn)
87 {
88 const CGEN_INSN_LIST *insn_list;
89
90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
92
93 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
94 while (insn_list != NULL)
95 {
96 insn = insn_list->insn;
97
98 if (alias_p
99 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
100 {
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
103 extract handler. */
104 if ((base_insn & CGEN_INSN_BASE_MASK (insn))
105 == CGEN_INSN_BASE_VALUE (insn))
106 {
107 /* ??? 0 is passed for `pc' */
108 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
109 base_insn, fields,
110 (bfd_vma) 0);
111 if (elength > 0)
112 {
113 /* sanity check */
114 if (length != 0 && length != elength)
115 abort ();
116 return insn;
117 }
118 }
119 }
120
121 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
122 }
123 }
124 else
125 {
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
127 if (! alias_p
128 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
129 abort ();
130 /* Sanity check: length must be correct. */
131 if (length != CGEN_INSN_BITSIZE (insn))
132 abort ();
133
134 /* ??? 0 is passed for `pc' */
135 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
136 (bfd_vma) 0);
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
139 if (length == 0)
140 abort ();
141 return insn;
142 }
143
144 return NULL;
145 }
146
147 /* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
149 in. */
150
151 void
152 fr30_cgen_get_insn_operands (od, insn, fields, indices)
153 CGEN_OPCODE_DESC od;
154 const CGEN_INSN * insn;
155 const CGEN_FIELDS * fields;
156 int *indices;
157 {
158 const CGEN_OPERAND_INSTANCE *opinst;
159 int i;
160
161 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
162 opinst != NULL
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
164 ++i, ++opinst)
165 {
166 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
167 if (op == NULL)
168 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
169 else
170 indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
171 fields);
172 }
173 }
174
175 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
176 isn't known.
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 fr30_cgen_lookup_insn unchanged.
179
180 The result is the insn table entry or NULL if the instruction wasn't
181 recognized. */
182
183 const CGEN_INSN *
184 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
185 CGEN_OPCODE_DESC od;
186 const CGEN_INSN *insn;
187 CGEN_INSN_BYTES insn_value;
188 int length;
189 int *indices;
190 {
191 CGEN_FIELDS fields;
192
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
196 insn != NULL);
197 if (! insn)
198 return NULL;
199
200 fr30_cgen_get_insn_operands (od, insn, &fields, indices);
201 return insn;
202 }
203 /* Attributes. */
204
205 static const CGEN_ATTR_ENTRY MACH_attr[] =
206 {
207 { "base", MACH_BASE },
208 { "fr30", MACH_FR30 },
209 { "max", MACH_MAX },
210 { 0, 0 }
211 };
212
213 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
214 {
215 { "CACHE-ADDR", NULL },
216 { "FUN-ACCESS", NULL },
217 { "PC", NULL },
218 { "PROFILE", NULL },
219 { 0, 0 }
220 };
221
222 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
223 {
224 { "ABS-ADDR", NULL },
225 { "HASH-PREFIX", NULL },
226 { "NEGATIVE", NULL },
227 { "PCREL-ADDR", NULL },
228 { "RELAX", NULL },
229 { "SEM-ONLY", NULL },
230 { "SIGN-OPT", NULL },
231 { "SIGNED", NULL },
232 { "UNSIGNED", NULL },
233 { "VIRTUAL", NULL },
234 { 0, 0 }
235 };
236
237 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
238 {
239 { "ALIAS", NULL },
240 { "COND-CTI", NULL },
241 { "DELAY-SLOT", NULL },
242 { "NO-DIS", NULL },
243 { "NOT-IN-DELAY-SLOT", NULL },
244 { "RELAX", NULL },
245 { "RELAXABLE", NULL },
246 { "SKIP-CTI", NULL },
247 { "UNCOND-CTI", NULL },
248 { "VIRTUAL", NULL },
249 { 0, 0 }
250 };
251
252 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
253 {
254 { "ac", 13 },
255 { "fp", 14 },
256 { "sp", 15 },
257 { "r0", 0 },
258 { "r1", 1 },
259 { "r2", 2 },
260 { "r3", 3 },
261 { "r4", 4 },
262 { "r5", 5 },
263 { "r6", 6 },
264 { "r7", 7 },
265 { "r8", 8 },
266 { "r9", 9 },
267 { "r10", 10 },
268 { "r11", 11 },
269 { "r12", 12 },
270 { "r13", 13 },
271 { "r14", 14 },
272 { "r15", 15 }
273 };
274
275 CGEN_KEYWORD fr30_cgen_opval_h_gr =
276 {
277 & fr30_cgen_opval_h_gr_entries[0],
278 19
279 };
280
281 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
282 {
283 { "cr0", 0 },
284 { "cr1", 1 },
285 { "cr2", 2 },
286 { "cr3", 3 },
287 { "cr4", 4 },
288 { "cr5", 5 },
289 { "cr6", 6 },
290 { "cr7", 7 },
291 { "cr8", 8 },
292 { "cr9", 9 },
293 { "cr10", 10 },
294 { "cr11", 11 },
295 { "cr12", 12 },
296 { "cr13", 13 },
297 { "cr14", 14 },
298 { "cr15", 15 }
299 };
300
301 CGEN_KEYWORD fr30_cgen_opval_h_cr =
302 {
303 & fr30_cgen_opval_h_cr_entries[0],
304 16
305 };
306
307 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
308 {
309 { "tbr", 0 },
310 { "rp", 1 },
311 { "ssp", 2 },
312 { "usp", 3 },
313 { "mdh", 4 },
314 { "mdl", 5 }
315 };
316
317 CGEN_KEYWORD fr30_cgen_opval_h_dr =
318 {
319 & fr30_cgen_opval_h_dr_entries[0],
320 6
321 };
322
323 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
324 {
325 { "ps", 0 }
326 };
327
328 CGEN_KEYWORD fr30_cgen_opval_h_ps =
329 {
330 & fr30_cgen_opval_h_ps_entries[0],
331 1
332 };
333
334 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
335 {
336 { "r13", 0 }
337 };
338
339 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
340 {
341 & fr30_cgen_opval_h_r13_entries[0],
342 1
343 };
344
345 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
346 {
347 { "r14", 0 }
348 };
349
350 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
351 {
352 & fr30_cgen_opval_h_r14_entries[0],
353 1
354 };
355
356 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
357 {
358 { "r15", 0 }
359 };
360
361 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
362 {
363 & fr30_cgen_opval_h_r15_entries[0],
364 1
365 };
366
367
368 /* The hardware table. */
369
370 #define HW_ENT(n) fr30_cgen_hw_entries[n]
371 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
372 {
373 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
374 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
375 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
376 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
377 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
378 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
379 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
380 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0, { 0 } } },
381 { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
382 { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
383 { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
384 { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
385 { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
386 { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
387 { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
388 { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
389 { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
390 { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
391 { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
392 { 0 }
393 };
394
395 /* The instruction field table. */
396
397 static const CGEN_IFLD fr30_cgen_ifld_table[] =
398 {
399 { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, 0, { 0 } } },
400 { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
401 { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
402 { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
403 { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
404 { FR30_F_OP5, "f-op5", 0, 16, 5, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
405 { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
406 { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
407 { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
408 { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
409 { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
410 { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
411 { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
412 { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
413 { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
414 { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
415 { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
416 { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
417 { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
418 { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
419 { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
420 { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
421 { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
422 { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
423 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
424 { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
425 { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
426 { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
427 { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
428 { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
429 { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
430 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
431 { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
432 { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
433 { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
434 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
435 { FR30_F_REGLIST_HI, "f-reglist_hi", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
436 { FR30_F_REGLIST_LOW, "f-reglist_low", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
437 { 0 }
438 };
439
440 /* The operand table. */
441
442 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
443 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
444
445 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
446 {
447 /* pc: program counter */
448 { "pc", & HW_ENT (HW_H_PC), 0, 0,
449 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
450 /* Ri: destination register */
451 { "Ri", & HW_ENT (HW_H_GR), 12, 4,
452 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
453 /* Rj: source register */
454 { "Rj", & HW_ENT (HW_H_GR), 8, 4,
455 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
456 /* Ric: target register coproc insn */
457 { "Ric", & HW_ENT (HW_H_GR), 12, 4,
458 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
459 /* Rjc: source register coproc insn */
460 { "Rjc", & HW_ENT (HW_H_GR), 8, 4,
461 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
462 /* CRi: coprocessor register */
463 { "CRi", & HW_ENT (HW_H_CR), 12, 4,
464 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
465 /* CRj: coprocessor register */
466 { "CRj", & HW_ENT (HW_H_CR), 8, 4,
467 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
468 /* Rs1: dedicated register */
469 { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
470 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
471 /* Rs2: dedicated register */
472 { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
473 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
474 /* R13: General Register 13 */
475 { "R13", & HW_ENT (HW_H_R13), 0, 0,
476 { 0, 0, { 0 } } },
477 /* R14: General Register 14 */
478 { "R14", & HW_ENT (HW_H_R14), 0, 0,
479 { 0, 0, { 0 } } },
480 /* R15: General Register 15 */
481 { "R15", & HW_ENT (HW_H_R15), 0, 0,
482 { 0, 0, { 0 } } },
483 /* ps: Program Status register */
484 { "ps", & HW_ENT (HW_H_PS), 0, 0,
485 { 0, 0, { 0 } } },
486 /* u4: 4 bit unsigned immediate */
487 { "u4", & HW_ENT (HW_H_UINT), 8, 4,
488 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
489 /* u4c: 4 bit unsigned immediate */
490 { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
491 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
492 /* m4: 4 bit negative immediate */
493 { "m4", & HW_ENT (HW_H_UINT), 8, 4,
494 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
495 /* u8: 8 bit unsigned immediate */
496 { "u8", & HW_ENT (HW_H_UINT), 8, 8,
497 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
498 /* i8: 8 bit unsigned immediate */
499 { "i8", & HW_ENT (HW_H_UINT), 4, 8,
500 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
501 /* udisp6: 6 bit unsigned immediate */
502 { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
503 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
504 /* disp8: 8 bit signed immediate */
505 { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
506 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
507 /* disp9: 9 bit signed immediate */
508 { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
509 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
510 /* disp10: 10 bit signed immediate */
511 { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
512 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
513 /* s10: 10 bit signed immediate */
514 { "s10", & HW_ENT (HW_H_SINT), 8, 8,
515 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
516 /* u10: 10 bit unsigned immediate */
517 { "u10", & HW_ENT (HW_H_UINT), 8, 8,
518 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
519 /* i32: 32 bit immediate */
520 { "i32", & HW_ENT (HW_H_UINT), 0, 32,
521 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
522 /* i20: 20 bit immediate */
523 { "i20", & HW_ENT (HW_H_UINT), 0, 20,
524 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), { 0 } } },
525 /* label9: 9 bit pc relative address */
526 { "label9", & HW_ENT (HW_H_IADDR), 8, 8,
527 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
528 /* dir8: 8 bit direct address */
529 { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
530 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
531 /* dir9: 9 bit direct address */
532 { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
533 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
534 /* dir10: 10 bit direct address */
535 { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
536 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
537 /* label12: 12 bit pc relative address */
538 { "label12", & HW_ENT (HW_H_IADDR), 5, 11,
539 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
540 /* reglist_low: 8 bit register mask */
541 { "reglist_low", & HW_ENT (HW_H_UINT), 8, 8,
542 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
543 /* reglist_hi: 8 bit register mask */
544 { "reglist_hi", & HW_ENT (HW_H_UINT), 8, 8,
545 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
546 /* cc: condition codes */
547 { "cc", & HW_ENT (HW_H_UINT), 4, 4,
548 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
549 /* ccc: coprocessor calc */
550 { "ccc", & HW_ENT (HW_H_UINT), 0, 8,
551 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
552 /* nbit: negative bit */
553 { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
554 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
555 /* vbit: overflow bit */
556 { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
557 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
558 /* zbit: zero bit */
559 { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
560 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
561 /* cbit: carry bit */
562 { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
563 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
564 /* ibit: interrupt bit */
565 { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
566 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
567 /* sbit: stack bit */
568 { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
569 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
570 };
571
572 /* Operand references. */
573
574 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
575 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
576 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
577
578 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
579 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
580 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
581 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
582 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
583 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
584 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
585 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
586 { 0 }
587 };
588
589 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
590 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
591 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
592 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
593 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
594 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
595 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
596 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
597 { 0 }
598 };
599
600 static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
601 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
602 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
603 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
604 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
605 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
606 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
607 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
608 { 0 }
609 };
610
611 static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
612 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
613 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
614 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
615 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
616 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
617 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
618 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
619 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
620 { 0 }
621 };
622
623 static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
624 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
625 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
626 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
627 { 0 }
628 };
629
630 static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
631 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
632 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
633 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
634 { 0 }
635 };
636
637 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
638 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
639 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
640 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
641 { 0 }
642 };
643
644 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
645 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
646 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
647 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
648 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
649 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
650 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
651 { 0 }
652 };
653
654 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
655 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
656 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
657 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
658 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
659 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
660 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
661 { 0 }
662 };
663
664 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
665 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
666 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
667 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
668 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
669 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
670 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
671 { 0 }
672 };
673
674 static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
675 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
676 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
677 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
678 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
679 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
680 { 0 }
681 };
682
683 static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
684 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
685 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
686 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
687 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
688 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
689 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
690 { 0 }
691 };
692
693 static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
694 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
695 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
696 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
697 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
698 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
699 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
700 { 0 }
701 };
702
703 static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
704 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
705 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
706 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
707 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
708 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
709 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
710 { 0 }
711 };
712
713 static const CGEN_OPERAND_INSTANCE fmt_bandl_ops[] = {
714 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
715 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
716 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
717 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
718 { 0 }
719 };
720
721 static const CGEN_OPERAND_INSTANCE fmt_btstl_ops[] = {
722 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
723 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
724 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
725 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
726 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
727 { 0 }
728 };
729
730 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
731 { INPUT, "i8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I8), 0, 0 },
732 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
733 { 0 }
734 };
735
736 static const CGEN_OPERAND_INSTANCE fmt_ldi20_ops[] = {
737 { INPUT, "i20", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I20), 0, 0 },
738 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
739 { 0 }
740 };
741
742 static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
743 { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
744 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
745 { 0 }
746 };
747
748 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
749 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
750 { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_USI, & OP_ENT (RS1), 0, 0 },
751 { 0 }
752 };
753
754 static const CGEN_OPERAND_INSTANCE fmt_jmpd_ops[] = {
755 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
756 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
757 { 0 }
758 };
759
760 static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
761 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
762 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
763 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, 0 },
764 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
765 { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
766 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
767 { 0 }
768 };
769
770 static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
771 { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
772 { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, COND_REF },
773 { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
774 { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 3, COND_REF },
775 { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
776 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
777 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, COND_REF },
778 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
779 { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 3, COND_REF },
780 { 0 }
781 };
782
783 static const CGEN_OPERAND_INSTANCE fmt_bra_ops[] = {
784 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, 0 },
785 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
786 { 0 }
787 };
788
789 #undef INPUT
790 #undef OUTPUT
791 #undef COND_REF
792
793 /* Instruction formats. */
794
795 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
796
797 static const CGEN_IFMT fmt_add = {
798 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
799 };
800
801 static const CGEN_IFMT fmt_addi = {
802 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
803 };
804
805 static const CGEN_IFMT fmt_add2 = {
806 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
807 };
808
809 static const CGEN_IFMT fmt_addc = {
810 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
811 };
812
813 static const CGEN_IFMT fmt_addn = {
814 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
815 };
816
817 static const CGEN_IFMT fmt_addni = {
818 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
819 };
820
821 static const CGEN_IFMT fmt_addn2 = {
822 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
823 };
824
825 static const CGEN_IFMT fmt_cmp = {
826 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
827 };
828
829 static const CGEN_IFMT fmt_cmpi = {
830 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
831 };
832
833 static const CGEN_IFMT fmt_cmp2 = {
834 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
835 };
836
837 static const CGEN_IFMT fmt_and = {
838 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
839 };
840
841 static const CGEN_IFMT fmt_andm = {
842 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
843 };
844
845 static const CGEN_IFMT fmt_andh = {
846 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
847 };
848
849 static const CGEN_IFMT fmt_andb = {
850 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
851 };
852
853 static const CGEN_IFMT fmt_bandl = {
854 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
855 };
856
857 static const CGEN_IFMT fmt_btstl = {
858 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
859 };
860
861 static const CGEN_IFMT fmt_mul = {
862 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
863 };
864
865 static const CGEN_IFMT fmt_div0s = {
866 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
867 };
868
869 static const CGEN_IFMT fmt_div3 = {
870 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
871 };
872
873 static const CGEN_IFMT fmt_lsli = {
874 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
875 };
876
877 static const CGEN_IFMT fmt_ldi8 = {
878 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
879 };
880
881 static const CGEN_IFMT fmt_ldi20 = {
882 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
883 };
884
885 static const CGEN_IFMT fmt_ldi32 = {
886 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
887 };
888
889 static const CGEN_IFMT fmt_ldr14 = {
890 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
891 };
892
893 static const CGEN_IFMT fmt_ldr14uh = {
894 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
895 };
896
897 static const CGEN_IFMT fmt_ldr14ub = {
898 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
899 };
900
901 static const CGEN_IFMT fmt_ldr15 = {
902 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
903 };
904
905 static const CGEN_IFMT fmt_ldr15dr = {
906 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
907 };
908
909 static const CGEN_IFMT fmt_movdr = {
910 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
911 };
912
913 static const CGEN_IFMT fmt_mov2dr = {
914 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
915 };
916
917 static const CGEN_IFMT fmt_jmpd = {
918 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
919 };
920
921 static const CGEN_IFMT fmt_call = {
922 16, 16, 0xf400, { F (F_OP1), F (F_OP5), F (F_REL12), 0 }
923 };
924
925 static const CGEN_IFMT fmt_int = {
926 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
927 };
928
929 static const CGEN_IFMT fmt_reti = {
930 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
931 };
932
933 static const CGEN_IFMT fmt_bra = {
934 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
935 };
936
937 static const CGEN_IFMT fmt_dmovr13 = {
938 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
939 };
940
941 static const CGEN_IFMT fmt_dmovr13h = {
942 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
943 };
944
945 static const CGEN_IFMT fmt_dmovr13b = {
946 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
947 };
948
949 static const CGEN_IFMT fmt_copop = {
950 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_CRI), 0 }
951 };
952
953 static const CGEN_IFMT fmt_copld = {
954 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_RJC), F (F_U4C), F (F_CRI), 0 }
955 };
956
957 static const CGEN_IFMT fmt_copst = {
958 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_RIC), 0 }
959 };
960
961 static const CGEN_IFMT fmt_andccr = {
962 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
963 };
964
965 static const CGEN_IFMT fmt_addsp = {
966 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_S10), 0 }
967 };
968
969 static const CGEN_IFMT fmt_ldm0 = {
970 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW), 0 }
971 };
972
973 static const CGEN_IFMT fmt_ldm1 = {
974 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI), 0 }
975 };
976
977 static const CGEN_IFMT fmt_enter = {
978 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U10), 0 }
979 };
980
981 #undef F
982
983 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
984 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
985 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
986
987 /* The instruction table.
988 This is currently non-static because the simulator accesses it
989 directly. */
990
991 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
992 {
993 /* Special null first entry.
994 A `num' value of zero is thus invalid.
995 Also, the special `invalid' insn resides here. */
996 { { 0 }, 0 },
997 /* add $Rj,$Ri */
998 {
999 { 1, 1, 1, 1 },
1000 FR30_INSN_ADD, "add", "add",
1001 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1002 & fmt_add, { 0xa600 },
1003 (PTR) & fmt_add_ops[0],
1004 { 0, 0, { 0 } }
1005 },
1006 /* add $u4,$Ri */
1007 {
1008 { 1, 1, 1, 1 },
1009 FR30_INSN_ADDI, "addi", "add",
1010 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1011 & fmt_addi, { 0xa400 },
1012 (PTR) & fmt_addi_ops[0],
1013 { 0, 0, { 0 } }
1014 },
1015 /* add2 $m4,$Ri */
1016 {
1017 { 1, 1, 1, 1 },
1018 FR30_INSN_ADD2, "add2", "add2",
1019 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1020 & fmt_add2, { 0xa500 },
1021 (PTR) & fmt_add2_ops[0],
1022 { 0, 0, { 0 } }
1023 },
1024 /* addc $Rj,$Ri */
1025 {
1026 { 1, 1, 1, 1 },
1027 FR30_INSN_ADDC, "addc", "addc",
1028 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1029 & fmt_addc, { 0xa700 },
1030 (PTR) & fmt_addc_ops[0],
1031 { 0, 0, { 0 } }
1032 },
1033 /* addn $Rj,$Ri */
1034 {
1035 { 1, 1, 1, 1 },
1036 FR30_INSN_ADDN, "addn", "addn",
1037 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1038 & fmt_addn, { 0xa200 },
1039 (PTR) & fmt_addn_ops[0],
1040 { 0, 0, { 0 } }
1041 },
1042 /* addn $u4,$Ri */
1043 {
1044 { 1, 1, 1, 1 },
1045 FR30_INSN_ADDNI, "addni", "addn",
1046 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1047 & fmt_addni, { 0xa000 },
1048 (PTR) & fmt_addni_ops[0],
1049 { 0, 0, { 0 } }
1050 },
1051 /* addn2 $m4,$Ri */
1052 {
1053 { 1, 1, 1, 1 },
1054 FR30_INSN_ADDN2, "addn2", "addn2",
1055 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1056 & fmt_addn2, { 0xa100 },
1057 (PTR) & fmt_addn2_ops[0],
1058 { 0, 0, { 0 } }
1059 },
1060 /* sub $Rj,$Ri */
1061 {
1062 { 1, 1, 1, 1 },
1063 FR30_INSN_SUB, "sub", "sub",
1064 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1065 & fmt_add, { 0xac00 },
1066 (PTR) & fmt_add_ops[0],
1067 { 0, 0, { 0 } }
1068 },
1069 /* subc $Rj,$Ri */
1070 {
1071 { 1, 1, 1, 1 },
1072 FR30_INSN_SUBC, "subc", "subc",
1073 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1074 & fmt_addc, { 0xad00 },
1075 (PTR) & fmt_addc_ops[0],
1076 { 0, 0, { 0 } }
1077 },
1078 /* subn $Rj,$Ri */
1079 {
1080 { 1, 1, 1, 1 },
1081 FR30_INSN_SUBN, "subn", "subn",
1082 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1083 & fmt_addn, { 0xae00 },
1084 (PTR) & fmt_addn_ops[0],
1085 { 0, 0, { 0 } }
1086 },
1087 /* cmp $Rj,$Ri */
1088 {
1089 { 1, 1, 1, 1 },
1090 FR30_INSN_CMP, "cmp", "cmp",
1091 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1092 & fmt_cmp, { 0xaa00 },
1093 (PTR) & fmt_cmp_ops[0],
1094 { 0, 0, { 0 } }
1095 },
1096 /* cmp $u4,$Ri */
1097 {
1098 { 1, 1, 1, 1 },
1099 FR30_INSN_CMPI, "cmpi", "cmp",
1100 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1101 & fmt_cmpi, { 0xa800 },
1102 (PTR) & fmt_cmpi_ops[0],
1103 { 0, 0, { 0 } }
1104 },
1105 /* cmp2 $m4,$Ri */
1106 {
1107 { 1, 1, 1, 1 },
1108 FR30_INSN_CMP2, "cmp2", "cmp2",
1109 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1110 & fmt_cmp2, { 0xa900 },
1111 (PTR) & fmt_cmp2_ops[0],
1112 { 0, 0, { 0 } }
1113 },
1114 /* and $Rj,$Ri */
1115 {
1116 { 1, 1, 1, 1 },
1117 FR30_INSN_AND, "and", "and",
1118 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1119 & fmt_and, { 0x8200 },
1120 (PTR) & fmt_and_ops[0],
1121 { 0, 0, { 0 } }
1122 },
1123 /* or $Rj,$Ri */
1124 {
1125 { 1, 1, 1, 1 },
1126 FR30_INSN_OR, "or", "or",
1127 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1128 & fmt_and, { 0x9200 },
1129 (PTR) & fmt_and_ops[0],
1130 { 0, 0, { 0 } }
1131 },
1132 /* eor $Rj,$Ri */
1133 {
1134 { 1, 1, 1, 1 },
1135 FR30_INSN_EOR, "eor", "eor",
1136 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1137 & fmt_and, { 0x9a00 },
1138 (PTR) & fmt_and_ops[0],
1139 { 0, 0, { 0 } }
1140 },
1141 /* and $Rj,@$Ri */
1142 {
1143 { 1, 1, 1, 1 },
1144 FR30_INSN_ANDM, "andm", "and",
1145 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1146 & fmt_andm, { 0x8400 },
1147 (PTR) & fmt_andm_ops[0],
1148 { 0, 0, { 0 } }
1149 },
1150 /* andh $Rj,@$Ri */
1151 {
1152 { 1, 1, 1, 1 },
1153 FR30_INSN_ANDH, "andh", "andh",
1154 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1155 & fmt_andh, { 0x8500 },
1156 (PTR) & fmt_andh_ops[0],
1157 { 0, 0, { 0 } }
1158 },
1159 /* andb $Rj,@$Ri */
1160 {
1161 { 1, 1, 1, 1 },
1162 FR30_INSN_ANDB, "andb", "andb",
1163 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1164 & fmt_andb, { 0x8600 },
1165 (PTR) & fmt_andb_ops[0],
1166 { 0, 0, { 0 } }
1167 },
1168 /* or $Rj,@$Ri */
1169 {
1170 { 1, 1, 1, 1 },
1171 FR30_INSN_ORM, "orm", "or",
1172 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1173 & fmt_andm, { 0x9400 },
1174 (PTR) & fmt_andm_ops[0],
1175 { 0, 0, { 0 } }
1176 },
1177 /* orh $Rj,@$Ri */
1178 {
1179 { 1, 1, 1, 1 },
1180 FR30_INSN_ORH, "orh", "orh",
1181 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1182 & fmt_andh, { 0x9500 },
1183 (PTR) & fmt_andh_ops[0],
1184 { 0, 0, { 0 } }
1185 },
1186 /* orb $Rj,@$Ri */
1187 {
1188 { 1, 1, 1, 1 },
1189 FR30_INSN_ORB, "orb", "orb",
1190 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1191 & fmt_andb, { 0x9600 },
1192 (PTR) & fmt_andb_ops[0],
1193 { 0, 0, { 0 } }
1194 },
1195 /* eor $Rj,@$Ri */
1196 {
1197 { 1, 1, 1, 1 },
1198 FR30_INSN_EORM, "eorm", "eor",
1199 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1200 & fmt_andm, { 0x9c00 },
1201 (PTR) & fmt_andm_ops[0],
1202 { 0, 0, { 0 } }
1203 },
1204 /* eorh $Rj,@$Ri */
1205 {
1206 { 1, 1, 1, 1 },
1207 FR30_INSN_EORH, "eorh", "eorh",
1208 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1209 & fmt_andh, { 0x9d00 },
1210 (PTR) & fmt_andh_ops[0],
1211 { 0, 0, { 0 } }
1212 },
1213 /* eorb $Rj,@$Ri */
1214 {
1215 { 1, 1, 1, 1 },
1216 FR30_INSN_EORB, "eorb", "eorb",
1217 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1218 & fmt_andb, { 0x9e00 },
1219 (PTR) & fmt_andb_ops[0],
1220 { 0, 0, { 0 } }
1221 },
1222 /* bandl $u4,@$Ri */
1223 {
1224 { 1, 1, 1, 1 },
1225 FR30_INSN_BANDL, "bandl", "bandl",
1226 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1227 & fmt_bandl, { 0x8000 },
1228 (PTR) & fmt_bandl_ops[0],
1229 { 0, 0, { 0 } }
1230 },
1231 /* borl $u4,@$Ri */
1232 {
1233 { 1, 1, 1, 1 },
1234 FR30_INSN_BORL, "borl", "borl",
1235 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1236 & fmt_bandl, { 0x9000 },
1237 (PTR) & fmt_bandl_ops[0],
1238 { 0, 0, { 0 } }
1239 },
1240 /* beorl $u4,@$Ri */
1241 {
1242 { 1, 1, 1, 1 },
1243 FR30_INSN_BEORL, "beorl", "beorl",
1244 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1245 & fmt_bandl, { 0x9800 },
1246 (PTR) & fmt_bandl_ops[0],
1247 { 0, 0, { 0 } }
1248 },
1249 /* bandh $u4,@$Ri */
1250 {
1251 { 1, 1, 1, 1 },
1252 FR30_INSN_BANDH, "bandh", "bandh",
1253 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1254 & fmt_bandl, { 0x8100 },
1255 (PTR) & fmt_bandl_ops[0],
1256 { 0, 0, { 0 } }
1257 },
1258 /* borh $u4,@$Ri */
1259 {
1260 { 1, 1, 1, 1 },
1261 FR30_INSN_BORH, "borh", "borh",
1262 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1263 & fmt_bandl, { 0x9100 },
1264 (PTR) & fmt_bandl_ops[0],
1265 { 0, 0, { 0 } }
1266 },
1267 /* beorh $u4,@$Ri */
1268 {
1269 { 1, 1, 1, 1 },
1270 FR30_INSN_BEORH, "beorh", "beorh",
1271 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1272 & fmt_bandl, { 0x9900 },
1273 (PTR) & fmt_bandl_ops[0],
1274 { 0, 0, { 0 } }
1275 },
1276 /* btstl $u4,@$Ri */
1277 {
1278 { 1, 1, 1, 1 },
1279 FR30_INSN_BTSTL, "btstl", "btstl",
1280 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1281 & fmt_btstl, { 0x8800 },
1282 (PTR) & fmt_btstl_ops[0],
1283 { 0, 0, { 0 } }
1284 },
1285 /* btsth $u4,@$Ri */
1286 {
1287 { 1, 1, 1, 1 },
1288 FR30_INSN_BTSTH, "btsth", "btsth",
1289 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1290 & fmt_btstl, { 0x8900 },
1291 (PTR) & fmt_btstl_ops[0],
1292 { 0, 0, { 0 } }
1293 },
1294 /* mul $Rj,$Ri */
1295 {
1296 { 1, 1, 1, 1 },
1297 FR30_INSN_MUL, "mul", "mul",
1298 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1299 & fmt_mul, { 0xaf00 },
1300 (PTR) 0,
1301 { 0, 0, { 0 } }
1302 },
1303 /* mulu $Rj,$Ri */
1304 {
1305 { 1, 1, 1, 1 },
1306 FR30_INSN_MULU, "mulu", "mulu",
1307 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1308 & fmt_mul, { 0xab00 },
1309 (PTR) 0,
1310 { 0, 0, { 0 } }
1311 },
1312 /* mulh $Rj,$Ri */
1313 {
1314 { 1, 1, 1, 1 },
1315 FR30_INSN_MULH, "mulh", "mulh",
1316 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1317 & fmt_mul, { 0xbf00 },
1318 (PTR) 0,
1319 { 0, 0, { 0 } }
1320 },
1321 /* muluh $Rj,$Ri */
1322 {
1323 { 1, 1, 1, 1 },
1324 FR30_INSN_MULUH, "muluh", "muluh",
1325 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1326 & fmt_mul, { 0xbb00 },
1327 (PTR) 0,
1328 { 0, 0, { 0 } }
1329 },
1330 /* div0s $Ri */
1331 {
1332 { 1, 1, 1, 1 },
1333 FR30_INSN_DIV0S, "div0s", "div0s",
1334 { { MNEM, ' ', OP (RI), 0 } },
1335 & fmt_div0s, { 0x9740 },
1336 (PTR) 0,
1337 { 0, 0, { 0 } }
1338 },
1339 /* div0u $Ri */
1340 {
1341 { 1, 1, 1, 1 },
1342 FR30_INSN_DIV0U, "div0u", "div0u",
1343 { { MNEM, ' ', OP (RI), 0 } },
1344 & fmt_div0s, { 0x9750 },
1345 (PTR) 0,
1346 { 0, 0, { 0 } }
1347 },
1348 /* div1 $Ri */
1349 {
1350 { 1, 1, 1, 1 },
1351 FR30_INSN_DIV1, "div1", "div1",
1352 { { MNEM, ' ', OP (RI), 0 } },
1353 & fmt_div0s, { 0x9760 },
1354 (PTR) 0,
1355 { 0, 0, { 0 } }
1356 },
1357 /* div2 $Ri */
1358 {
1359 { 1, 1, 1, 1 },
1360 FR30_INSN_DIV2, "div2", "div2",
1361 { { MNEM, ' ', OP (RI), 0 } },
1362 & fmt_div0s, { 0x9770 },
1363 (PTR) 0,
1364 { 0, 0, { 0 } }
1365 },
1366 /* div3 */
1367 {
1368 { 1, 1, 1, 1 },
1369 FR30_INSN_DIV3, "div3", "div3",
1370 { { MNEM, 0 } },
1371 & fmt_div3, { 0x9f60 },
1372 (PTR) 0,
1373 { 0, 0, { 0 } }
1374 },
1375 /* div4s */
1376 {
1377 { 1, 1, 1, 1 },
1378 FR30_INSN_DIV4S, "div4s", "div4s",
1379 { { MNEM, 0 } },
1380 & fmt_div3, { 0x9f70 },
1381 (PTR) 0,
1382 { 0, 0, { 0 } }
1383 },
1384 /* lsl $Rj,$Ri */
1385 {
1386 { 1, 1, 1, 1 },
1387 FR30_INSN_LSL, "lsl", "lsl",
1388 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1389 & fmt_mul, { 0xb600 },
1390 (PTR) 0,
1391 { 0, 0, { 0 } }
1392 },
1393 /* lsl $u4,$Ri */
1394 {
1395 { 1, 1, 1, 1 },
1396 FR30_INSN_LSLI, "lsli", "lsl",
1397 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1398 & fmt_lsli, { 0xb400 },
1399 (PTR) 0,
1400 { 0, 0, { 0 } }
1401 },
1402 /* lsl2 $u4,$Ri */
1403 {
1404 { 1, 1, 1, 1 },
1405 FR30_INSN_LSL2, "lsl2", "lsl2",
1406 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1407 & fmt_lsli, { 0xb500 },
1408 (PTR) 0,
1409 { 0, 0, { 0 } }
1410 },
1411 /* lsr $Rj,$Ri */
1412 {
1413 { 1, 1, 1, 1 },
1414 FR30_INSN_LSR, "lsr", "lsr",
1415 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1416 & fmt_mul, { 0xb200 },
1417 (PTR) 0,
1418 { 0, 0, { 0 } }
1419 },
1420 /* lsr $u4,$Ri */
1421 {
1422 { 1, 1, 1, 1 },
1423 FR30_INSN_LSRI, "lsri", "lsr",
1424 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1425 & fmt_lsli, { 0xb000 },
1426 (PTR) 0,
1427 { 0, 0, { 0 } }
1428 },
1429 /* lsr2 $u4,$Ri */
1430 {
1431 { 1, 1, 1, 1 },
1432 FR30_INSN_LSR2, "lsr2", "lsr2",
1433 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1434 & fmt_lsli, { 0xb100 },
1435 (PTR) 0,
1436 { 0, 0, { 0 } }
1437 },
1438 /* asr $Rj,$Ri */
1439 {
1440 { 1, 1, 1, 1 },
1441 FR30_INSN_ASR, "asr", "asr",
1442 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1443 & fmt_mul, { 0xba00 },
1444 (PTR) 0,
1445 { 0, 0, { 0 } }
1446 },
1447 /* asr $u4,$Ri */
1448 {
1449 { 1, 1, 1, 1 },
1450 FR30_INSN_ASRI, "asri", "asr",
1451 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1452 & fmt_lsli, { 0xb800 },
1453 (PTR) 0,
1454 { 0, 0, { 0 } }
1455 },
1456 /* asr2 $u4,$Ri */
1457 {
1458 { 1, 1, 1, 1 },
1459 FR30_INSN_ASR2, "asr2", "asr2",
1460 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1461 & fmt_lsli, { 0xb900 },
1462 (PTR) 0,
1463 { 0, 0, { 0 } }
1464 },
1465 /* ldi:8 $i8,$Ri */
1466 {
1467 { 1, 1, 1, 1 },
1468 FR30_INSN_LDI8, "ldi8", "ldi:8",
1469 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
1470 & fmt_ldi8, { 0xc000 },
1471 (PTR) & fmt_ldi8_ops[0],
1472 { 0, 0, { 0 } }
1473 },
1474 /* ldi:20 $i20,$Ri */
1475 {
1476 { 1, 1, 1, 1 },
1477 FR30_INSN_LDI20, "ldi20", "ldi:20",
1478 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
1479 & fmt_ldi20, { 0x9b00 },
1480 (PTR) & fmt_ldi20_ops[0],
1481 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
1482 },
1483 /* ldi:32 $i32,$Ri */
1484 {
1485 { 1, 1, 1, 1 },
1486 FR30_INSN_LDI32, "ldi32", "ldi:32",
1487 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
1488 & fmt_ldi32, { 0x9f80 },
1489 (PTR) & fmt_ldi32_ops[0],
1490 { 0, 0, { 0 } }
1491 },
1492 /* ld @$Rj,$Ri */
1493 {
1494 { 1, 1, 1, 1 },
1495 FR30_INSN_LD, "ld", "ld",
1496 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1497 & fmt_mul, { 0x400 },
1498 (PTR) 0,
1499 { 0, 0, { 0 } }
1500 },
1501 /* lduh @$Rj,$Ri */
1502 {
1503 { 1, 1, 1, 1 },
1504 FR30_INSN_LDUH, "lduh", "lduh",
1505 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1506 & fmt_mul, { 0x500 },
1507 (PTR) 0,
1508 { 0, 0, { 0 } }
1509 },
1510 /* ldub @$Rj,$Ri */
1511 {
1512 { 1, 1, 1, 1 },
1513 FR30_INSN_LDUB, "ldub", "ldub",
1514 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1515 & fmt_mul, { 0x600 },
1516 (PTR) 0,
1517 { 0, 0, { 0 } }
1518 },
1519 /* ld @($R13,$Rj),$Ri */
1520 {
1521 { 1, 1, 1, 1 },
1522 FR30_INSN_LDR13, "ldr13", "ld",
1523 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1524 & fmt_mul, { 0x0 },
1525 (PTR) 0,
1526 { 0, 0, { 0 } }
1527 },
1528 /* lduh @($R13,$Rj),$Ri */
1529 {
1530 { 1, 1, 1, 1 },
1531 FR30_INSN_LDR13UH, "ldr13uh", "lduh",
1532 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1533 & fmt_mul, { 0x100 },
1534 (PTR) 0,
1535 { 0, 0, { 0 } }
1536 },
1537 /* ldub @($R13,$Rj),$Ri */
1538 {
1539 { 1, 1, 1, 1 },
1540 FR30_INSN_LDR13UB, "ldr13ub", "ldub",
1541 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1542 & fmt_mul, { 0x200 },
1543 (PTR) 0,
1544 { 0, 0, { 0 } }
1545 },
1546 /* ld @($R14,$disp10),$Ri */
1547 {
1548 { 1, 1, 1, 1 },
1549 FR30_INSN_LDR14, "ldr14", "ld",
1550 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
1551 & fmt_ldr14, { 0x2000 },
1552 (PTR) 0,
1553 { 0, 0, { 0 } }
1554 },
1555 /* lduh @($R14,$disp9),$Ri */
1556 {
1557 { 1, 1, 1, 1 },
1558 FR30_INSN_LDR14UH, "ldr14uh", "lduh",
1559 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
1560 & fmt_ldr14uh, { 0x4000 },
1561 (PTR) 0,
1562 { 0, 0, { 0 } }
1563 },
1564 /* ldub @($R14,$disp8),$Ri */
1565 {
1566 { 1, 1, 1, 1 },
1567 FR30_INSN_LDR14UB, "ldr14ub", "ldub",
1568 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
1569 & fmt_ldr14ub, { 0x6000 },
1570 (PTR) 0,
1571 { 0, 0, { 0 } }
1572 },
1573 /* ld @($R15,$udisp6),$Ri */
1574 {
1575 { 1, 1, 1, 1 },
1576 FR30_INSN_LDR15, "ldr15", "ld",
1577 { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
1578 & fmt_ldr15, { 0x300 },
1579 (PTR) 0,
1580 { 0, 0, { 0 } }
1581 },
1582 /* ld @$R15+,$Ri */
1583 {
1584 { 1, 1, 1, 1 },
1585 FR30_INSN_LDR15GR, "ldr15gr", "ld",
1586 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
1587 & fmt_div0s, { 0x700 },
1588 (PTR) 0,
1589 { 0, 0, { 0 } }
1590 },
1591 /* ld @$R15+,$Rs2 */
1592 {
1593 { 1, 1, 1, 1 },
1594 FR30_INSN_LDR15DR, "ldr15dr", "ld",
1595 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
1596 & fmt_ldr15dr, { 0x780 },
1597 (PTR) 0,
1598 { 0, 0, { 0 } }
1599 },
1600 /* ld @$R15+,$ps */
1601 {
1602 { 1, 1, 1, 1 },
1603 FR30_INSN_LDR15PS, "ldr15ps", "ld",
1604 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
1605 & fmt_div3, { 0x790 },
1606 (PTR) 0,
1607 { 0, 0, { 0 } }
1608 },
1609 /* st $Ri,@$Rj */
1610 {
1611 { 1, 1, 1, 1 },
1612 FR30_INSN_ST, "st", "st",
1613 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1614 & fmt_mul, { 0x1400 },
1615 (PTR) 0,
1616 { 0, 0, { 0 } }
1617 },
1618 /* sth $Ri,@$Rj */
1619 {
1620 { 1, 1, 1, 1 },
1621 FR30_INSN_STH, "sth", "sth",
1622 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1623 & fmt_mul, { 0x1500 },
1624 (PTR) 0,
1625 { 0, 0, { 0 } }
1626 },
1627 /* stb $Ri,@$Rj */
1628 {
1629 { 1, 1, 1, 1 },
1630 FR30_INSN_STB, "stb", "stb",
1631 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1632 & fmt_mul, { 0x1600 },
1633 (PTR) 0,
1634 { 0, 0, { 0 } }
1635 },
1636 /* st $Ri,@($R13,$Rj) */
1637 {
1638 { 1, 1, 1, 1 },
1639 FR30_INSN_STR13, "str13", "st",
1640 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1641 & fmt_mul, { 0x1000 },
1642 (PTR) 0,
1643 { 0, 0, { 0 } }
1644 },
1645 /* sth $Ri,@($R13,$Rj) */
1646 {
1647 { 1, 1, 1, 1 },
1648 FR30_INSN_STR13H, "str13h", "sth",
1649 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1650 & fmt_mul, { 0x1100 },
1651 (PTR) 0,
1652 { 0, 0, { 0 } }
1653 },
1654 /* stb $Ri,@($R13,$Rj) */
1655 {
1656 { 1, 1, 1, 1 },
1657 FR30_INSN_STR13B, "stR13b", "stb",
1658 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1659 & fmt_mul, { 0x1200 },
1660 (PTR) 0,
1661 { 0, 0, { 0 } }
1662 },
1663 /* st $Ri,@($R14,$disp10) */
1664 {
1665 { 1, 1, 1, 1 },
1666 FR30_INSN_STR14, "str14", "st",
1667 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
1668 & fmt_ldr14, { 0x3000 },
1669 (PTR) 0,
1670 { 0, 0, { 0 } }
1671 },
1672 /* sth $Ri,@($R14,$disp9) */
1673 {
1674 { 1, 1, 1, 1 },
1675 FR30_INSN_STR14H, "str14h", "sth",
1676 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
1677 & fmt_ldr14uh, { 0x5000 },
1678 (PTR) 0,
1679 { 0, 0, { 0 } }
1680 },
1681 /* stb $Ri,@($R14,$disp8) */
1682 {
1683 { 1, 1, 1, 1 },
1684 FR30_INSN_STR14B, "str14b", "stb",
1685 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
1686 & fmt_ldr14ub, { 0x7000 },
1687 (PTR) 0,
1688 { 0, 0, { 0 } }
1689 },
1690 /* st $Ri,@($R15,$udisp6) */
1691 {
1692 { 1, 1, 1, 1 },
1693 FR30_INSN_STR15, "str15", "st",
1694 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
1695 & fmt_ldr15, { 0x1300 },
1696 (PTR) 0,
1697 { 0, 0, { 0 } }
1698 },
1699 /* st $Ri,@-$R15 */
1700 {
1701 { 1, 1, 1, 1 },
1702 FR30_INSN_STR15GR, "str15gr", "st",
1703 { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
1704 & fmt_div0s, { 0x1700 },
1705 (PTR) 0,
1706 { 0, 0, { 0 } }
1707 },
1708 /* st $Rs2,@-$R15 */
1709 {
1710 { 1, 1, 1, 1 },
1711 FR30_INSN_STR15DR, "str15dr", "st",
1712 { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
1713 & fmt_ldr15dr, { 0x1780 },
1714 (PTR) 0,
1715 { 0, 0, { 0 } }
1716 },
1717 /* st $ps,@-$R15 */
1718 {
1719 { 1, 1, 1, 1 },
1720 FR30_INSN_STR15PS, "str15ps", "st",
1721 { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
1722 & fmt_div3, { 0x1790 },
1723 (PTR) 0,
1724 { 0, 0, { 0 } }
1725 },
1726 /* mov $Rj,$Ri */
1727 {
1728 { 1, 1, 1, 1 },
1729 FR30_INSN_MOV, "mov", "mov",
1730 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1731 & fmt_mul, { 0x8b00 },
1732 (PTR) 0,
1733 { 0, 0, { 0 } }
1734 },
1735 /* mov $Rs1,$Ri */
1736 {
1737 { 1, 1, 1, 1 },
1738 FR30_INSN_MOVDR, "movdr", "mov",
1739 { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
1740 & fmt_movdr, { 0xb700 },
1741 (PTR) 0,
1742 { 0, 0, { 0 } }
1743 },
1744 /* mov $ps,$Ri */
1745 {
1746 { 1, 1, 1, 1 },
1747 FR30_INSN_MOVPS, "movps", "mov",
1748 { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
1749 & fmt_div0s, { 0x1710 },
1750 (PTR) 0,
1751 { 0, 0, { 0 } }
1752 },
1753 /* mov $Ri,$Rs1 */
1754 {
1755 { 1, 1, 1, 1 },
1756 FR30_INSN_MOV2DR, "mov2dr", "mov",
1757 { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
1758 & fmt_mov2dr, { 0xb300 },
1759 (PTR) & fmt_mov2dr_ops[0],
1760 { 0, 0, { 0 } }
1761 },
1762 /* mov $Ri,$ps */
1763 {
1764 { 1, 1, 1, 1 },
1765 FR30_INSN_MOV2PS, "mov2ps", "mov",
1766 { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
1767 & fmt_div0s, { 0x710 },
1768 (PTR) 0,
1769 { 0, 0, { 0 } }
1770 },
1771 /* jmp @$Ri */
1772 {
1773 { 1, 1, 1, 1 },
1774 FR30_INSN_JMP, "jmp", "jmp",
1775 { { MNEM, ' ', '@', OP (RI), 0 } },
1776 & fmt_div0s, { 0x9700 },
1777 (PTR) 0,
1778 { 0, 0, { 0 } }
1779 },
1780 /* jmp:d @$Ri */
1781 {
1782 { 1, 1, 1, 1 },
1783 FR30_INSN_JMPD, "jmpd", "jmp:d",
1784 { { MNEM, ' ', '@', OP (RI), 0 } },
1785 & fmt_jmpd, { 0x9f00 },
1786 (PTR) & fmt_jmpd_ops[0],
1787 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
1788 },
1789 /* call @$Ri */
1790 {
1791 { 1, 1, 1, 1 },
1792 FR30_INSN_CALLR, "callr", "call",
1793 { { MNEM, ' ', '@', OP (RI), 0 } },
1794 & fmt_div0s, { 0x9710 },
1795 (PTR) 0,
1796 { 0, 0, { 0 } }
1797 },
1798 /* call:D @$Ri */
1799 {
1800 { 1, 1, 1, 1 },
1801 FR30_INSN_CALLRD, "callrd", "call:D",
1802 { { MNEM, ' ', '@', OP (RI), 0 } },
1803 & fmt_div0s, { 0x9f10 },
1804 (PTR) 0,
1805 { 0, 0, { 0 } }
1806 },
1807 /* call $label12 */
1808 {
1809 { 1, 1, 1, 1 },
1810 FR30_INSN_CALL, "call", "call",
1811 { { MNEM, ' ', OP (LABEL12), 0 } },
1812 & fmt_call, { 0xd000 },
1813 (PTR) 0,
1814 { 0, 0, { 0 } }
1815 },
1816 /* call:D $label12 */
1817 {
1818 { 1, 1, 1, 1 },
1819 FR30_INSN_CALLD, "calld", "call:D",
1820 { { MNEM, ' ', OP (LABEL12), 0 } },
1821 & fmt_call, { 0xd400 },
1822 (PTR) 0,
1823 { 0, 0, { 0 } }
1824 },
1825 /* ret */
1826 {
1827 { 1, 1, 1, 1 },
1828 FR30_INSN_RET, "ret", "ret",
1829 { { MNEM, 0 } },
1830 & fmt_div3, { 0x9720 },
1831 (PTR) 0,
1832 { 0, 0, { 0 } }
1833 },
1834 /* ret:D */
1835 {
1836 { 1, 1, 1, 1 },
1837 FR30_INSN_RETD, "retd", "ret:D",
1838 { { MNEM, 0 } },
1839 & fmt_div3, { 0x9f20 },
1840 (PTR) 0,
1841 { 0, 0, { 0 } }
1842 },
1843 /* int $u8 */
1844 {
1845 { 1, 1, 1, 1 },
1846 FR30_INSN_INT, "int", "int",
1847 { { MNEM, ' ', OP (U8), 0 } },
1848 & fmt_int, { 0x1f00 },
1849 (PTR) & fmt_int_ops[0],
1850 { 0, 0|A(UNCOND_CTI), { 0 } }
1851 },
1852 /* inte */
1853 {
1854 { 1, 1, 1, 1 },
1855 FR30_INSN_INTE, "inte", "inte",
1856 { { MNEM, 0 } },
1857 & fmt_div3, { 0x9f30 },
1858 (PTR) 0,
1859 { 0, 0, { 0 } }
1860 },
1861 /* reti */
1862 {
1863 { 1, 1, 1, 1 },
1864 FR30_INSN_RETI, "reti", "reti",
1865 { { MNEM, 0 } },
1866 & fmt_reti, { 0x9730 },
1867 (PTR) & fmt_reti_ops[0],
1868 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
1869 },
1870 /* bra $label9 */
1871 {
1872 { 1, 1, 1, 1 },
1873 FR30_INSN_BRA, "bra", "bra",
1874 { { MNEM, ' ', OP (LABEL9), 0 } },
1875 & fmt_bra, { 0xe000 },
1876 (PTR) & fmt_bra_ops[0],
1877 { 0, 0|A(UNCOND_CTI), { 0 } }
1878 },
1879 /* bno $label9 */
1880 {
1881 { 1, 1, 1, 1 },
1882 FR30_INSN_BNO, "bno", "bno",
1883 { { MNEM, ' ', OP (LABEL9), 0 } },
1884 & fmt_bra, { 0xe100 },
1885 (PTR) & fmt_bra_ops[0],
1886 { 0, 0|A(UNCOND_CTI), { 0 } }
1887 },
1888 /* beq $label9 */
1889 {
1890 { 1, 1, 1, 1 },
1891 FR30_INSN_BEQ, "beq", "beq",
1892 { { MNEM, ' ', OP (LABEL9), 0 } },
1893 & fmt_bra, { 0xe200 },
1894 (PTR) & fmt_bra_ops[0],
1895 { 0, 0|A(UNCOND_CTI), { 0 } }
1896 },
1897 /* bne $label9 */
1898 {
1899 { 1, 1, 1, 1 },
1900 FR30_INSN_BNE, "bne", "bne",
1901 { { MNEM, ' ', OP (LABEL9), 0 } },
1902 & fmt_bra, { 0xe300 },
1903 (PTR) & fmt_bra_ops[0],
1904 { 0, 0|A(UNCOND_CTI), { 0 } }
1905 },
1906 /* bc $label9 */
1907 {
1908 { 1, 1, 1, 1 },
1909 FR30_INSN_BC, "bc", "bc",
1910 { { MNEM, ' ', OP (LABEL9), 0 } },
1911 & fmt_bra, { 0xe400 },
1912 (PTR) & fmt_bra_ops[0],
1913 { 0, 0|A(UNCOND_CTI), { 0 } }
1914 },
1915 /* bnc $label9 */
1916 {
1917 { 1, 1, 1, 1 },
1918 FR30_INSN_BNC, "bnc", "bnc",
1919 { { MNEM, ' ', OP (LABEL9), 0 } },
1920 & fmt_bra, { 0xe500 },
1921 (PTR) & fmt_bra_ops[0],
1922 { 0, 0|A(UNCOND_CTI), { 0 } }
1923 },
1924 /* bn $label9 */
1925 {
1926 { 1, 1, 1, 1 },
1927 FR30_INSN_BN, "bn", "bn",
1928 { { MNEM, ' ', OP (LABEL9), 0 } },
1929 & fmt_bra, { 0xe600 },
1930 (PTR) & fmt_bra_ops[0],
1931 { 0, 0|A(UNCOND_CTI), { 0 } }
1932 },
1933 /* bp $label9 */
1934 {
1935 { 1, 1, 1, 1 },
1936 FR30_INSN_BP, "bp", "bp",
1937 { { MNEM, ' ', OP (LABEL9), 0 } },
1938 & fmt_bra, { 0xe700 },
1939 (PTR) & fmt_bra_ops[0],
1940 { 0, 0|A(UNCOND_CTI), { 0 } }
1941 },
1942 /* bv $label9 */
1943 {
1944 { 1, 1, 1, 1 },
1945 FR30_INSN_BV, "bv", "bv",
1946 { { MNEM, ' ', OP (LABEL9), 0 } },
1947 & fmt_bra, { 0xe800 },
1948 (PTR) & fmt_bra_ops[0],
1949 { 0, 0|A(UNCOND_CTI), { 0 } }
1950 },
1951 /* bnv $label9 */
1952 {
1953 { 1, 1, 1, 1 },
1954 FR30_INSN_BNV, "bnv", "bnv",
1955 { { MNEM, ' ', OP (LABEL9), 0 } },
1956 & fmt_bra, { 0xe900 },
1957 (PTR) & fmt_bra_ops[0],
1958 { 0, 0|A(UNCOND_CTI), { 0 } }
1959 },
1960 /* blt $label9 */
1961 {
1962 { 1, 1, 1, 1 },
1963 FR30_INSN_BLT, "blt", "blt",
1964 { { MNEM, ' ', OP (LABEL9), 0 } },
1965 & fmt_bra, { 0xea00 },
1966 (PTR) & fmt_bra_ops[0],
1967 { 0, 0|A(UNCOND_CTI), { 0 } }
1968 },
1969 /* bge $label9 */
1970 {
1971 { 1, 1, 1, 1 },
1972 FR30_INSN_BGE, "bge", "bge",
1973 { { MNEM, ' ', OP (LABEL9), 0 } },
1974 & fmt_bra, { 0xeb00 },
1975 (PTR) & fmt_bra_ops[0],
1976 { 0, 0|A(UNCOND_CTI), { 0 } }
1977 },
1978 /* ble $label9 */
1979 {
1980 { 1, 1, 1, 1 },
1981 FR30_INSN_BLE, "ble", "ble",
1982 { { MNEM, ' ', OP (LABEL9), 0 } },
1983 & fmt_bra, { 0xec00 },
1984 (PTR) & fmt_bra_ops[0],
1985 { 0, 0|A(UNCOND_CTI), { 0 } }
1986 },
1987 /* bgt $label9 */
1988 {
1989 { 1, 1, 1, 1 },
1990 FR30_INSN_BGT, "bgt", "bgt",
1991 { { MNEM, ' ', OP (LABEL9), 0 } },
1992 & fmt_bra, { 0xed00 },
1993 (PTR) & fmt_bra_ops[0],
1994 { 0, 0|A(UNCOND_CTI), { 0 } }
1995 },
1996 /* bls $label9 */
1997 {
1998 { 1, 1, 1, 1 },
1999 FR30_INSN_BLS, "bls", "bls",
2000 { { MNEM, ' ', OP (LABEL9), 0 } },
2001 & fmt_bra, { 0xee00 },
2002 (PTR) & fmt_bra_ops[0],
2003 { 0, 0|A(UNCOND_CTI), { 0 } }
2004 },
2005 /* bhi $label9 */
2006 {
2007 { 1, 1, 1, 1 },
2008 FR30_INSN_BHI, "bhi", "bhi",
2009 { { MNEM, ' ', OP (LABEL9), 0 } },
2010 & fmt_bra, { 0xef00 },
2011 (PTR) & fmt_bra_ops[0],
2012 { 0, 0|A(UNCOND_CTI), { 0 } }
2013 },
2014 /* bra:D $label9 */
2015 {
2016 { 1, 1, 1, 1 },
2017 FR30_INSN_BRAD, "brad", "bra:D",
2018 { { MNEM, ' ', OP (LABEL9), 0 } },
2019 & fmt_bra, { 0xf000 },
2020 (PTR) & fmt_bra_ops[0],
2021 { 0, 0|A(UNCOND_CTI), { 0 } }
2022 },
2023 /* bno:D $label9 */
2024 {
2025 { 1, 1, 1, 1 },
2026 FR30_INSN_BNOD, "bnod", "bno:D",
2027 { { MNEM, ' ', OP (LABEL9), 0 } },
2028 & fmt_bra, { 0xf100 },
2029 (PTR) & fmt_bra_ops[0],
2030 { 0, 0|A(UNCOND_CTI), { 0 } }
2031 },
2032 /* beq:D $label9 */
2033 {
2034 { 1, 1, 1, 1 },
2035 FR30_INSN_BEQD, "beqd", "beq:D",
2036 { { MNEM, ' ', OP (LABEL9), 0 } },
2037 & fmt_bra, { 0xf200 },
2038 (PTR) & fmt_bra_ops[0],
2039 { 0, 0|A(UNCOND_CTI), { 0 } }
2040 },
2041 /* bne:D $label9 */
2042 {
2043 { 1, 1, 1, 1 },
2044 FR30_INSN_BNED, "bned", "bne:D",
2045 { { MNEM, ' ', OP (LABEL9), 0 } },
2046 & fmt_bra, { 0xf300 },
2047 (PTR) & fmt_bra_ops[0],
2048 { 0, 0|A(UNCOND_CTI), { 0 } }
2049 },
2050 /* bc:D $label9 */
2051 {
2052 { 1, 1, 1, 1 },
2053 FR30_INSN_BCD, "bcd", "bc:D",
2054 { { MNEM, ' ', OP (LABEL9), 0 } },
2055 & fmt_bra, { 0xf400 },
2056 (PTR) & fmt_bra_ops[0],
2057 { 0, 0|A(UNCOND_CTI), { 0 } }
2058 },
2059 /* bnc:D $label9 */
2060 {
2061 { 1, 1, 1, 1 },
2062 FR30_INSN_BNCD, "bncd", "bnc:D",
2063 { { MNEM, ' ', OP (LABEL9), 0 } },
2064 & fmt_bra, { 0xf500 },
2065 (PTR) & fmt_bra_ops[0],
2066 { 0, 0|A(UNCOND_CTI), { 0 } }
2067 },
2068 /* bn:D $label9 */
2069 {
2070 { 1, 1, 1, 1 },
2071 FR30_INSN_BND, "bnd", "bn:D",
2072 { { MNEM, ' ', OP (LABEL9), 0 } },
2073 & fmt_bra, { 0xf600 },
2074 (PTR) & fmt_bra_ops[0],
2075 { 0, 0|A(UNCOND_CTI), { 0 } }
2076 },
2077 /* bp:D $label9 */
2078 {
2079 { 1, 1, 1, 1 },
2080 FR30_INSN_BPD, "bpd", "bp:D",
2081 { { MNEM, ' ', OP (LABEL9), 0 } },
2082 & fmt_bra, { 0xf700 },
2083 (PTR) & fmt_bra_ops[0],
2084 { 0, 0|A(UNCOND_CTI), { 0 } }
2085 },
2086 /* bv:D $label9 */
2087 {
2088 { 1, 1, 1, 1 },
2089 FR30_INSN_BVD, "bvd", "bv:D",
2090 { { MNEM, ' ', OP (LABEL9), 0 } },
2091 & fmt_bra, { 0xf800 },
2092 (PTR) & fmt_bra_ops[0],
2093 { 0, 0|A(UNCOND_CTI), { 0 } }
2094 },
2095 /* bnv:D $label9 */
2096 {
2097 { 1, 1, 1, 1 },
2098 FR30_INSN_BNVD, "bnvd", "bnv:D",
2099 { { MNEM, ' ', OP (LABEL9), 0 } },
2100 & fmt_bra, { 0xf900 },
2101 (PTR) & fmt_bra_ops[0],
2102 { 0, 0|A(UNCOND_CTI), { 0 } }
2103 },
2104 /* blt:D $label9 */
2105 {
2106 { 1, 1, 1, 1 },
2107 FR30_INSN_BLTD, "bltd", "blt:D",
2108 { { MNEM, ' ', OP (LABEL9), 0 } },
2109 & fmt_bra, { 0xfa00 },
2110 (PTR) & fmt_bra_ops[0],
2111 { 0, 0|A(UNCOND_CTI), { 0 } }
2112 },
2113 /* bge:D $label9 */
2114 {
2115 { 1, 1, 1, 1 },
2116 FR30_INSN_BGED, "bged", "bge:D",
2117 { { MNEM, ' ', OP (LABEL9), 0 } },
2118 & fmt_bra, { 0xfb00 },
2119 (PTR) & fmt_bra_ops[0],
2120 { 0, 0|A(UNCOND_CTI), { 0 } }
2121 },
2122 /* ble:D $label9 */
2123 {
2124 { 1, 1, 1, 1 },
2125 FR30_INSN_BLED, "bled", "ble:D",
2126 { { MNEM, ' ', OP (LABEL9), 0 } },
2127 & fmt_bra, { 0xfc00 },
2128 (PTR) & fmt_bra_ops[0],
2129 { 0, 0|A(UNCOND_CTI), { 0 } }
2130 },
2131 /* bgt:D $label9 */
2132 {
2133 { 1, 1, 1, 1 },
2134 FR30_INSN_BGTD, "bgtd", "bgt:D",
2135 { { MNEM, ' ', OP (LABEL9), 0 } },
2136 & fmt_bra, { 0xfd00 },
2137 (PTR) & fmt_bra_ops[0],
2138 { 0, 0|A(UNCOND_CTI), { 0 } }
2139 },
2140 /* bls:D $label9 */
2141 {
2142 { 1, 1, 1, 1 },
2143 FR30_INSN_BLSD, "blsd", "bls:D",
2144 { { MNEM, ' ', OP (LABEL9), 0 } },
2145 & fmt_bra, { 0xfe00 },
2146 (PTR) & fmt_bra_ops[0],
2147 { 0, 0|A(UNCOND_CTI), { 0 } }
2148 },
2149 /* bhi:D $label9 */
2150 {
2151 { 1, 1, 1, 1 },
2152 FR30_INSN_BHID, "bhid", "bhi:D",
2153 { { MNEM, ' ', OP (LABEL9), 0 } },
2154 & fmt_bra, { 0xff00 },
2155 (PTR) & fmt_bra_ops[0],
2156 { 0, 0|A(UNCOND_CTI), { 0 } }
2157 },
2158 /* dmov $R13,@$dir10 */
2159 {
2160 { 1, 1, 1, 1 },
2161 FR30_INSN_DMOVR13, "dmovr13", "dmov",
2162 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
2163 & fmt_dmovr13, { 0x1800 },
2164 (PTR) 0,
2165 { 0, 0, { 0 } }
2166 },
2167 /* dmovh $R13,@$dir9 */
2168 {
2169 { 1, 1, 1, 1 },
2170 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
2171 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
2172 & fmt_dmovr13h, { 0x1900 },
2173 (PTR) 0,
2174 { 0, 0, { 0 } }
2175 },
2176 /* dmovb $R13,@$dir8 */
2177 {
2178 { 1, 1, 1, 1 },
2179 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
2180 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
2181 & fmt_dmovr13b, { 0x1a00 },
2182 (PTR) 0,
2183 { 0, 0, { 0 } }
2184 },
2185 /* dmov @$R13+,@$dir10 */
2186 {
2187 { 1, 1, 1, 1 },
2188 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
2189 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
2190 & fmt_dmovr13, { 0x1c00 },
2191 (PTR) 0,
2192 { 0, 0, { 0 } }
2193 },
2194 /* dmovh @$R13+,@$dir9 */
2195 {
2196 { 1, 1, 1, 1 },
2197 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
2198 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
2199 & fmt_dmovr13h, { 0x1d00 },
2200 (PTR) 0,
2201 { 0, 0, { 0 } }
2202 },
2203 /* dmovb @$R13+,@$dir8 */
2204 {
2205 { 1, 1, 1, 1 },
2206 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
2207 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
2208 & fmt_dmovr13b, { 0x1e00 },
2209 (PTR) 0,
2210 { 0, 0, { 0 } }
2211 },
2212 /* dmov @$R15+,@$dir10 */
2213 {
2214 { 1, 1, 1, 1 },
2215 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
2216 { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
2217 & fmt_dmovr13, { 0x1b00 },
2218 (PTR) 0,
2219 { 0, 0, { 0 } }
2220 },
2221 /* dmov @$dir10,$R13 */
2222 {
2223 { 1, 1, 1, 1 },
2224 FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
2225 { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
2226 & fmt_dmovr13, { 0x800 },
2227 (PTR) 0,
2228 { 0, 0, { 0 } }
2229 },
2230 /* dmovh @$dir9,$R13 */
2231 {
2232 { 1, 1, 1, 1 },
2233 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
2234 { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
2235 & fmt_dmovr13h, { 0x900 },
2236 (PTR) 0,
2237 { 0, 0, { 0 } }
2238 },
2239 /* dmovb @$dir8,$R13 */
2240 {
2241 { 1, 1, 1, 1 },
2242 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
2243 { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
2244 & fmt_dmovr13b, { 0xa00 },
2245 (PTR) 0,
2246 { 0, 0, { 0 } }
2247 },
2248 /* dmov @$dir10,@$R13+ */
2249 {
2250 { 1, 1, 1, 1 },
2251 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
2252 { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
2253 & fmt_dmovr13, { 0xc00 },
2254 (PTR) 0,
2255 { 0, 0, { 0 } }
2256 },
2257 /* dmovh @$dir9,@$R13+ */
2258 {
2259 { 1, 1, 1, 1 },
2260 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
2261 { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
2262 & fmt_dmovr13h, { 0xd00 },
2263 (PTR) 0,
2264 { 0, 0, { 0 } }
2265 },
2266 /* dmovb @$dir8,@$R13+ */
2267 {
2268 { 1, 1, 1, 1 },
2269 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
2270 { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
2271 & fmt_dmovr13b, { 0xe00 },
2272 (PTR) 0,
2273 { 0, 0, { 0 } }
2274 },
2275 /* dmov @$dir10,@-$R15 */
2276 {
2277 { 1, 1, 1, 1 },
2278 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
2279 { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
2280 & fmt_dmovr13, { 0xb00 },
2281 (PTR) 0,
2282 { 0, 0, { 0 } }
2283 },
2284 /* ldres @$Ri+,$u4 */
2285 {
2286 { 1, 1, 1, 1 },
2287 FR30_INSN_LDRES, "ldres", "ldres",
2288 { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
2289 & fmt_lsli, { 0xbc00 },
2290 (PTR) 0,
2291 { 0, 0, { 0 } }
2292 },
2293 /* stres $u4,@$Ri+ */
2294 {
2295 { 1, 1, 1, 1 },
2296 FR30_INSN_STRES, "stres", "stres",
2297 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
2298 & fmt_lsli, { 0xbd00 },
2299 (PTR) 0,
2300 { 0, 0, { 0 } }
2301 },
2302 /* copop $u4c,$ccc,$CRj,$CRi */
2303 {
2304 { 1, 1, 1, 1 },
2305 FR30_INSN_COPOP, "copop", "copop",
2306 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
2307 & fmt_copop, { 0x9fc0 },
2308 (PTR) 0,
2309 { 0, 0, { 0 } }
2310 },
2311 /* copld $u4c,$ccc,$Rjc,$CRi */
2312 {
2313 { 1, 1, 1, 1 },
2314 FR30_INSN_COPLD, "copld", "copld",
2315 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
2316 & fmt_copld, { 0x9fd0 },
2317 (PTR) 0,
2318 { 0, 0, { 0 } }
2319 },
2320 /* copst $u4c,$ccc,$CRj,$Ric */
2321 {
2322 { 1, 1, 1, 1 },
2323 FR30_INSN_COPST, "copst", "copst",
2324 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2325 & fmt_copst, { 0x9fe0 },
2326 (PTR) 0,
2327 { 0, 0, { 0 } }
2328 },
2329 /* copsv $u4c,$ccc,$CRj,$Ric */
2330 {
2331 { 1, 1, 1, 1 },
2332 FR30_INSN_COPSV, "copsv", "copsv",
2333 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2334 & fmt_copst, { 0x9ff0 },
2335 (PTR) 0,
2336 { 0, 0, { 0 } }
2337 },
2338 /* nop */
2339 {
2340 { 1, 1, 1, 1 },
2341 FR30_INSN_NOP, "nop", "nop",
2342 { { MNEM, 0 } },
2343 & fmt_div3, { 0x9fa0 },
2344 (PTR) 0,
2345 { 0, 0, { 0 } }
2346 },
2347 /* andccr $u8 */
2348 {
2349 { 1, 1, 1, 1 },
2350 FR30_INSN_ANDCCR, "andccr", "andccr",
2351 { { MNEM, ' ', OP (U8), 0 } },
2352 & fmt_andccr, { 0x8300 },
2353 (PTR) 0,
2354 { 0, 0, { 0 } }
2355 },
2356 /* orccr $u8 */
2357 {
2358 { 1, 1, 1, 1 },
2359 FR30_INSN_ORCCR, "orccr", "orccr",
2360 { { MNEM, ' ', OP (U8), 0 } },
2361 & fmt_andccr, { 0x9300 },
2362 (PTR) 0,
2363 { 0, 0, { 0 } }
2364 },
2365 /* stilm $u8 */
2366 {
2367 { 1, 1, 1, 1 },
2368 FR30_INSN_STILM, "stilm", "stilm",
2369 { { MNEM, ' ', OP (U8), 0 } },
2370 & fmt_andccr, { 0x8700 },
2371 (PTR) 0,
2372 { 0, 0, { 0 } }
2373 },
2374 /* addsp $s10 */
2375 {
2376 { 1, 1, 1, 1 },
2377 FR30_INSN_ADDSP, "addsp", "addsp",
2378 { { MNEM, ' ', OP (S10), 0 } },
2379 & fmt_addsp, { 0xa300 },
2380 (PTR) 0,
2381 { 0, 0, { 0 } }
2382 },
2383 /* extsb $Ri */
2384 {
2385 { 1, 1, 1, 1 },
2386 FR30_INSN_EXTSB, "extsb", "extsb",
2387 { { MNEM, ' ', OP (RI), 0 } },
2388 & fmt_div0s, { 0x9780 },
2389 (PTR) 0,
2390 { 0, 0, { 0 } }
2391 },
2392 /* extub $Ri */
2393 {
2394 { 1, 1, 1, 1 },
2395 FR30_INSN_EXTUB, "extub", "extub",
2396 { { MNEM, ' ', OP (RI), 0 } },
2397 & fmt_div0s, { 0x9790 },
2398 (PTR) 0,
2399 { 0, 0, { 0 } }
2400 },
2401 /* extsh $Ri */
2402 {
2403 { 1, 1, 1, 1 },
2404 FR30_INSN_EXTSH, "extsh", "extsh",
2405 { { MNEM, ' ', OP (RI), 0 } },
2406 & fmt_div0s, { 0x97a0 },
2407 (PTR) 0,
2408 { 0, 0, { 0 } }
2409 },
2410 /* extuh $Ri */
2411 {
2412 { 1, 1, 1, 1 },
2413 FR30_INSN_EXTUH, "extuh", "extuh",
2414 { { MNEM, ' ', OP (RI), 0 } },
2415 & fmt_div0s, { 0x97b0 },
2416 (PTR) 0,
2417 { 0, 0, { 0 } }
2418 },
2419 /* ldm0 ($reglist_low) */
2420 {
2421 { 1, 1, 1, 1 },
2422 FR30_INSN_LDM0, "ldm0", "ldm0",
2423 { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
2424 & fmt_ldm0, { 0x8c00 },
2425 (PTR) 0,
2426 { 0, 0, { 0 } }
2427 },
2428 /* ldm1 ($reglist_hi) */
2429 {
2430 { 1, 1, 1, 1 },
2431 FR30_INSN_LDM1, "ldm1", "ldm1",
2432 { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
2433 & fmt_ldm1, { 0x8d00 },
2434 (PTR) 0,
2435 { 0, 0, { 0 } }
2436 },
2437 /* stm0 ($reglist_low) */
2438 {
2439 { 1, 1, 1, 1 },
2440 FR30_INSN_STM0, "stm0", "stm0",
2441 { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
2442 & fmt_ldm0, { 0x8e00 },
2443 (PTR) 0,
2444 { 0, 0, { 0 } }
2445 },
2446 /* stm1 ($reglist_hi) */
2447 {
2448 { 1, 1, 1, 1 },
2449 FR30_INSN_STM1, "stm1", "stm1",
2450 { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
2451 & fmt_ldm1, { 0x8f00 },
2452 (PTR) 0,
2453 { 0, 0, { 0 } }
2454 },
2455 /* enter $u10 */
2456 {
2457 { 1, 1, 1, 1 },
2458 FR30_INSN_ENTER, "enter", "enter",
2459 { { MNEM, ' ', OP (U10), 0 } },
2460 & fmt_enter, { 0xf00 },
2461 (PTR) 0,
2462 { 0, 0, { 0 } }
2463 },
2464 /* leave */
2465 {
2466 { 1, 1, 1, 1 },
2467 FR30_INSN_LEAVE, "leave", "leave",
2468 { { MNEM, 0 } },
2469 & fmt_div3, { 0x9f90 },
2470 (PTR) 0,
2471 { 0, 0, { 0 } }
2472 },
2473 /* xchb @$Rj,$Ri */
2474 {
2475 { 1, 1, 1, 1 },
2476 FR30_INSN_XCHB, "xchb", "xchb",
2477 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2478 & fmt_mul, { 0x8a00 },
2479 (PTR) 0,
2480 { 0, 0, { 0 } }
2481 },
2482 };
2483
2484 #undef A
2485 #undef MNEM
2486 #undef OP
2487
2488 static const CGEN_INSN_TABLE insn_table =
2489 {
2490 & fr30_cgen_insn_table_entries[0],
2491 sizeof (CGEN_INSN),
2492 MAX_INSNS,
2493 NULL
2494 };
2495
2496 /* Formats for ALIAS macro-insns. */
2497
2498 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
2499
2500 #undef F
2501
2502 /* Each non-simple macro entry points to an array of expansion possibilities. */
2503
2504 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2505 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2506 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2507
2508 /* The macro instruction table. */
2509
2510 static const CGEN_INSN macro_insn_table_entries[] =
2511 {
2512 };
2513
2514 #undef A
2515 #undef MNEM
2516 #undef OP
2517
2518 static const CGEN_INSN_TABLE macro_insn_table =
2519 {
2520 & macro_insn_table_entries[0],
2521 sizeof (CGEN_INSN),
2522 (sizeof (macro_insn_table_entries) /
2523 sizeof (macro_insn_table_entries[0])),
2524 NULL
2525 };
2526
2527 static void
2528 init_tables ()
2529 {
2530 }
2531
2532 /* Return non-zero if INSN is to be added to the hash table.
2533 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
2534
2535 static int
2536 asm_hash_insn_p (insn)
2537 const CGEN_INSN * insn;
2538 {
2539 return CGEN_ASM_HASH_P (insn);
2540 }
2541
2542 static int
2543 dis_hash_insn_p (insn)
2544 const CGEN_INSN * insn;
2545 {
2546 /* If building the hash table and the NO-DIS attribute is present,
2547 ignore. */
2548 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2549 return 0;
2550 return CGEN_DIS_HASH_P (insn);
2551 }
2552
2553 /* The result is the hash value of the insn.
2554 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
2555
2556 static unsigned int
2557 asm_hash_insn (mnem)
2558 const char * mnem;
2559 {
2560 return CGEN_ASM_HASH (mnem);
2561 }
2562
2563 /* BUF is a pointer to the insn's bytes in target order.
2564 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
2565 host order. */
2566
2567 static unsigned int
2568 dis_hash_insn (buf, value)
2569 const char * buf;
2570 CGEN_INSN_INT value;
2571 {
2572 return CGEN_DIS_HASH (buf, value);
2573 }
2574
2575 /* Initialize an opcode table and return a descriptor.
2576 It's much like opening a file, and must be the first function called. */
2577
2578 CGEN_OPCODE_DESC
2579 fr30_cgen_opcode_open (mach, endian)
2580 int mach;
2581 enum cgen_endian endian;
2582 {
2583 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2584 static int init_p;
2585
2586 if (! init_p)
2587 {
2588 init_tables ();
2589 init_p = 1;
2590 }
2591
2592 memset (table, 0, sizeof (*table));
2593
2594 CGEN_OPCODE_MACH (table) = mach;
2595 CGEN_OPCODE_ENDIAN (table) = endian;
2596 /* FIXME: for the sparc case we can determine insn-endianness statically.
2597 The worry here is where both data and insn endian can be independently
2598 chosen, in which case this function will need another argument.
2599 Actually, will want to allow for more arguments in the future anyway. */
2600 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
2601
2602 CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
2603
2604 CGEN_OPCODE_IFLD_TABLE (table) = & fr30_cgen_ifld_table[0];
2605
2606 CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
2607
2608 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2609
2610 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2611
2612 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2613 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2614 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2615
2616 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2617 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2618 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2619
2620 return (CGEN_OPCODE_DESC) table;
2621 }
2622
2623 /* Close an opcode table. */
2624
2625 void
2626 fr30_cgen_opcode_close (desc)
2627 CGEN_OPCODE_DESC desc;
2628 {
2629 free (desc);
2630 }
2631
2632 /* Getting values from cgen_fields is handled by a collection of functions.
2633 They are distinguished by the type of the VALUE argument they return.
2634 TODO: floating point, inlining support, remove cases where result type
2635 not appropriate. */
2636
2637 int
2638 fr30_cgen_get_int_operand (opindex, fields)
2639 int opindex;
2640 const CGEN_FIELDS * fields;
2641 {
2642 int value;
2643
2644 switch (opindex)
2645 {
2646 case FR30_OPERAND_RI :
2647 value = fields->f_Ri;
2648 break;
2649 case FR30_OPERAND_RJ :
2650 value = fields->f_Rj;
2651 break;
2652 case FR30_OPERAND_RIC :
2653 value = fields->f_Ric;
2654 break;
2655 case FR30_OPERAND_RJC :
2656 value = fields->f_Rjc;
2657 break;
2658 case FR30_OPERAND_CRI :
2659 value = fields->f_CRi;
2660 break;
2661 case FR30_OPERAND_CRJ :
2662 value = fields->f_CRj;
2663 break;
2664 case FR30_OPERAND_RS1 :
2665 value = fields->f_Rs1;
2666 break;
2667 case FR30_OPERAND_RS2 :
2668 value = fields->f_Rs2;
2669 break;
2670 case FR30_OPERAND_R13 :
2671 value = fields->f_nil;
2672 break;
2673 case FR30_OPERAND_R14 :
2674 value = fields->f_nil;
2675 break;
2676 case FR30_OPERAND_R15 :
2677 value = fields->f_nil;
2678 break;
2679 case FR30_OPERAND_PS :
2680 value = fields->f_nil;
2681 break;
2682 case FR30_OPERAND_U4 :
2683 value = fields->f_u4;
2684 break;
2685 case FR30_OPERAND_U4C :
2686 value = fields->f_u4c;
2687 break;
2688 case FR30_OPERAND_M4 :
2689 value = fields->f_m4;
2690 break;
2691 case FR30_OPERAND_U8 :
2692 value = fields->f_u8;
2693 break;
2694 case FR30_OPERAND_I8 :
2695 value = fields->f_i8;
2696 break;
2697 case FR30_OPERAND_UDISP6 :
2698 value = fields->f_udisp6;
2699 break;
2700 case FR30_OPERAND_DISP8 :
2701 value = fields->f_disp8;
2702 break;
2703 case FR30_OPERAND_DISP9 :
2704 value = fields->f_disp9;
2705 break;
2706 case FR30_OPERAND_DISP10 :
2707 value = fields->f_disp10;
2708 break;
2709 case FR30_OPERAND_S10 :
2710 value = fields->f_s10;
2711 break;
2712 case FR30_OPERAND_U10 :
2713 value = fields->f_u10;
2714 break;
2715 case FR30_OPERAND_I32 :
2716 value = fields->f_i32;
2717 break;
2718 case FR30_OPERAND_I20 :
2719 value = fields->f_i20;
2720 break;
2721 case FR30_OPERAND_LABEL9 :
2722 value = fields->f_rel9;
2723 break;
2724 case FR30_OPERAND_DIR8 :
2725 value = fields->f_dir8;
2726 break;
2727 case FR30_OPERAND_DIR9 :
2728 value = fields->f_dir9;
2729 break;
2730 case FR30_OPERAND_DIR10 :
2731 value = fields->f_dir10;
2732 break;
2733 case FR30_OPERAND_LABEL12 :
2734 value = fields->f_rel12;
2735 break;
2736 case FR30_OPERAND_REGLIST_LOW :
2737 value = fields->f_reglist_low;
2738 break;
2739 case FR30_OPERAND_REGLIST_HI :
2740 value = fields->f_reglist_hi;
2741 break;
2742 case FR30_OPERAND_CC :
2743 value = fields->f_cc;
2744 break;
2745 case FR30_OPERAND_CCC :
2746 value = fields->f_ccc;
2747 break;
2748
2749 default :
2750 /* xgettext:c-format */
2751 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2752 opindex);
2753 abort ();
2754 }
2755
2756 return value;
2757 }
2758
2759 bfd_vma
2760 fr30_cgen_get_vma_operand (opindex, fields)
2761 int opindex;
2762 const CGEN_FIELDS * fields;
2763 {
2764 bfd_vma value;
2765
2766 switch (opindex)
2767 {
2768 case FR30_OPERAND_RI :
2769 value = fields->f_Ri;
2770 break;
2771 case FR30_OPERAND_RJ :
2772 value = fields->f_Rj;
2773 break;
2774 case FR30_OPERAND_RIC :
2775 value = fields->f_Ric;
2776 break;
2777 case FR30_OPERAND_RJC :
2778 value = fields->f_Rjc;
2779 break;
2780 case FR30_OPERAND_CRI :
2781 value = fields->f_CRi;
2782 break;
2783 case FR30_OPERAND_CRJ :
2784 value = fields->f_CRj;
2785 break;
2786 case FR30_OPERAND_RS1 :
2787 value = fields->f_Rs1;
2788 break;
2789 case FR30_OPERAND_RS2 :
2790 value = fields->f_Rs2;
2791 break;
2792 case FR30_OPERAND_R13 :
2793 value = fields->f_nil;
2794 break;
2795 case FR30_OPERAND_R14 :
2796 value = fields->f_nil;
2797 break;
2798 case FR30_OPERAND_R15 :
2799 value = fields->f_nil;
2800 break;
2801 case FR30_OPERAND_PS :
2802 value = fields->f_nil;
2803 break;
2804 case FR30_OPERAND_U4 :
2805 value = fields->f_u4;
2806 break;
2807 case FR30_OPERAND_U4C :
2808 value = fields->f_u4c;
2809 break;
2810 case FR30_OPERAND_M4 :
2811 value = fields->f_m4;
2812 break;
2813 case FR30_OPERAND_U8 :
2814 value = fields->f_u8;
2815 break;
2816 case FR30_OPERAND_I8 :
2817 value = fields->f_i8;
2818 break;
2819 case FR30_OPERAND_UDISP6 :
2820 value = fields->f_udisp6;
2821 break;
2822 case FR30_OPERAND_DISP8 :
2823 value = fields->f_disp8;
2824 break;
2825 case FR30_OPERAND_DISP9 :
2826 value = fields->f_disp9;
2827 break;
2828 case FR30_OPERAND_DISP10 :
2829 value = fields->f_disp10;
2830 break;
2831 case FR30_OPERAND_S10 :
2832 value = fields->f_s10;
2833 break;
2834 case FR30_OPERAND_U10 :
2835 value = fields->f_u10;
2836 break;
2837 case FR30_OPERAND_I32 :
2838 value = fields->f_i32;
2839 break;
2840 case FR30_OPERAND_I20 :
2841 value = fields->f_i20;
2842 break;
2843 case FR30_OPERAND_LABEL9 :
2844 value = fields->f_rel9;
2845 break;
2846 case FR30_OPERAND_DIR8 :
2847 value = fields->f_dir8;
2848 break;
2849 case FR30_OPERAND_DIR9 :
2850 value = fields->f_dir9;
2851 break;
2852 case FR30_OPERAND_DIR10 :
2853 value = fields->f_dir10;
2854 break;
2855 case FR30_OPERAND_LABEL12 :
2856 value = fields->f_rel12;
2857 break;
2858 case FR30_OPERAND_REGLIST_LOW :
2859 value = fields->f_reglist_low;
2860 break;
2861 case FR30_OPERAND_REGLIST_HI :
2862 value = fields->f_reglist_hi;
2863 break;
2864 case FR30_OPERAND_CC :
2865 value = fields->f_cc;
2866 break;
2867 case FR30_OPERAND_CCC :
2868 value = fields->f_ccc;
2869 break;
2870
2871 default :
2872 /* xgettext:c-format */
2873 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
2874 opindex);
2875 abort ();
2876 }
2877
2878 return value;
2879 }
2880
2881 /* Stuffing values in cgen_fields is handled by a collection of functions.
2882 They are distinguished by the type of the VALUE argument they accept.
2883 TODO: floating point, inlining support, remove cases where argument type
2884 not appropriate. */
2885
2886 void
2887 fr30_cgen_set_int_operand (opindex, fields, value)
2888 int opindex;
2889 CGEN_FIELDS * fields;
2890 int value;
2891 {
2892 switch (opindex)
2893 {
2894 case FR30_OPERAND_RI :
2895 fields->f_Ri = value;
2896 break;
2897 case FR30_OPERAND_RJ :
2898 fields->f_Rj = value;
2899 break;
2900 case FR30_OPERAND_RIC :
2901 fields->f_Ric = value;
2902 break;
2903 case FR30_OPERAND_RJC :
2904 fields->f_Rjc = value;
2905 break;
2906 case FR30_OPERAND_CRI :
2907 fields->f_CRi = value;
2908 break;
2909 case FR30_OPERAND_CRJ :
2910 fields->f_CRj = value;
2911 break;
2912 case FR30_OPERAND_RS1 :
2913 fields->f_Rs1 = value;
2914 break;
2915 case FR30_OPERAND_RS2 :
2916 fields->f_Rs2 = value;
2917 break;
2918 case FR30_OPERAND_R13 :
2919 fields->f_nil = value;
2920 break;
2921 case FR30_OPERAND_R14 :
2922 fields->f_nil = value;
2923 break;
2924 case FR30_OPERAND_R15 :
2925 fields->f_nil = value;
2926 break;
2927 case FR30_OPERAND_PS :
2928 fields->f_nil = value;
2929 break;
2930 case FR30_OPERAND_U4 :
2931 fields->f_u4 = value;
2932 break;
2933 case FR30_OPERAND_U4C :
2934 fields->f_u4c = value;
2935 break;
2936 case FR30_OPERAND_M4 :
2937 fields->f_m4 = value;
2938 break;
2939 case FR30_OPERAND_U8 :
2940 fields->f_u8 = value;
2941 break;
2942 case FR30_OPERAND_I8 :
2943 fields->f_i8 = value;
2944 break;
2945 case FR30_OPERAND_UDISP6 :
2946 fields->f_udisp6 = value;
2947 break;
2948 case FR30_OPERAND_DISP8 :
2949 fields->f_disp8 = value;
2950 break;
2951 case FR30_OPERAND_DISP9 :
2952 fields->f_disp9 = value;
2953 break;
2954 case FR30_OPERAND_DISP10 :
2955 fields->f_disp10 = value;
2956 break;
2957 case FR30_OPERAND_S10 :
2958 fields->f_s10 = value;
2959 break;
2960 case FR30_OPERAND_U10 :
2961 fields->f_u10 = value;
2962 break;
2963 case FR30_OPERAND_I32 :
2964 fields->f_i32 = value;
2965 break;
2966 case FR30_OPERAND_I20 :
2967 fields->f_i20 = value;
2968 break;
2969 case FR30_OPERAND_LABEL9 :
2970 fields->f_rel9 = value;
2971 break;
2972 case FR30_OPERAND_DIR8 :
2973 fields->f_dir8 = value;
2974 break;
2975 case FR30_OPERAND_DIR9 :
2976 fields->f_dir9 = value;
2977 break;
2978 case FR30_OPERAND_DIR10 :
2979 fields->f_dir10 = value;
2980 break;
2981 case FR30_OPERAND_LABEL12 :
2982 fields->f_rel12 = value;
2983 break;
2984 case FR30_OPERAND_REGLIST_LOW :
2985 fields->f_reglist_low = value;
2986 break;
2987 case FR30_OPERAND_REGLIST_HI :
2988 fields->f_reglist_hi = value;
2989 break;
2990 case FR30_OPERAND_CC :
2991 fields->f_cc = value;
2992 break;
2993 case FR30_OPERAND_CCC :
2994 fields->f_ccc = value;
2995 break;
2996
2997 default :
2998 /* xgettext:c-format */
2999 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
3000 opindex);
3001 abort ();
3002 }
3003 }
3004
3005 void
3006 fr30_cgen_set_vma_operand (opindex, fields, value)
3007 int opindex;
3008 CGEN_FIELDS * fields;
3009 bfd_vma value;
3010 {
3011 switch (opindex)
3012 {
3013 case FR30_OPERAND_RI :
3014 fields->f_Ri = value;
3015 break;
3016 case FR30_OPERAND_RJ :
3017 fields->f_Rj = value;
3018 break;
3019 case FR30_OPERAND_RIC :
3020 fields->f_Ric = value;
3021 break;
3022 case FR30_OPERAND_RJC :
3023 fields->f_Rjc = value;
3024 break;
3025 case FR30_OPERAND_CRI :
3026 fields->f_CRi = value;
3027 break;
3028 case FR30_OPERAND_CRJ :
3029 fields->f_CRj = value;
3030 break;
3031 case FR30_OPERAND_RS1 :
3032 fields->f_Rs1 = value;
3033 break;
3034 case FR30_OPERAND_RS2 :
3035 fields->f_Rs2 = value;
3036 break;
3037 case FR30_OPERAND_R13 :
3038 fields->f_nil = value;
3039 break;
3040 case FR30_OPERAND_R14 :
3041 fields->f_nil = value;
3042 break;
3043 case FR30_OPERAND_R15 :
3044 fields->f_nil = value;
3045 break;
3046 case FR30_OPERAND_PS :
3047 fields->f_nil = value;
3048 break;
3049 case FR30_OPERAND_U4 :
3050 fields->f_u4 = value;
3051 break;
3052 case FR30_OPERAND_U4C :
3053 fields->f_u4c = value;
3054 break;
3055 case FR30_OPERAND_M4 :
3056 fields->f_m4 = value;
3057 break;
3058 case FR30_OPERAND_U8 :
3059 fields->f_u8 = value;
3060 break;
3061 case FR30_OPERAND_I8 :
3062 fields->f_i8 = value;
3063 break;
3064 case FR30_OPERAND_UDISP6 :
3065 fields->f_udisp6 = value;
3066 break;
3067 case FR30_OPERAND_DISP8 :
3068 fields->f_disp8 = value;
3069 break;
3070 case FR30_OPERAND_DISP9 :
3071 fields->f_disp9 = value;
3072 break;
3073 case FR30_OPERAND_DISP10 :
3074 fields->f_disp10 = value;
3075 break;
3076 case FR30_OPERAND_S10 :
3077 fields->f_s10 = value;
3078 break;
3079 case FR30_OPERAND_U10 :
3080 fields->f_u10 = value;
3081 break;
3082 case FR30_OPERAND_I32 :
3083 fields->f_i32 = value;
3084 break;
3085 case FR30_OPERAND_I20 :
3086 fields->f_i20 = value;
3087 break;
3088 case FR30_OPERAND_LABEL9 :
3089 fields->f_rel9 = value;
3090 break;
3091 case FR30_OPERAND_DIR8 :
3092 fields->f_dir8 = value;
3093 break;
3094 case FR30_OPERAND_DIR9 :
3095 fields->f_dir9 = value;
3096 break;
3097 case FR30_OPERAND_DIR10 :
3098 fields->f_dir10 = value;
3099 break;
3100 case FR30_OPERAND_LABEL12 :
3101 fields->f_rel12 = value;
3102 break;
3103 case FR30_OPERAND_REGLIST_LOW :
3104 fields->f_reglist_low = value;
3105 break;
3106 case FR30_OPERAND_REGLIST_HI :
3107 fields->f_reglist_hi = value;
3108 break;
3109 case FR30_OPERAND_CC :
3110 fields->f_cc = value;
3111 break;
3112 case FR30_OPERAND_CCC :
3113 fields->f_ccc = value;
3114 break;
3115
3116 default :
3117 /* xgettext:c-format */
3118 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3119 opindex);
3120 abort ();
3121 }
3122 }
3123
GDB Binutils - Deliverables
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