opcodes/fr30-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS USED TO GENERATE fr30-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software Foundation, Inc.,
  22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "fr30-opc.h"
  31 #include "opintl.h"
  32
  33 /* The hash functions are recorded here to help keep assembler code out of
  34    the disassembler and vice versa.  */
  35
  36 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
  37 static unsigned int asm_hash_insn PARAMS ((const char *));
  38 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
  39 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
  40
  41 /* Look up instruction INSN_VALUE and extract its fields.
  42    INSN, if non-null, is the insn table entry.
  43    Otherwise INSN_VALUE is examined to compute it.
  44    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
  45    0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
  46    If INSN != NULL, LENGTH must be valid.
  47    ALIAS_P is non-zero if alias insns are to be included in the search.
  48
  49    The result is a pointer to the insn table entry, or NULL if the instruction
  50    wasn't recognized.  */
  51
  52 const CGEN_INSN *
  53 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
  54      CGEN_OPCODE_DESC od;
  55      const CGEN_INSN *insn;
  56      CGEN_INSN_BYTES insn_value;
  57      int length;
  58      CGEN_FIELDS *fields;
  59      int alias_p;
  60 {
  61   unsigned char buf[CGEN_MAX_INSN_SIZE];
  62   unsigned char *bufp;
  63   CGEN_INSN_INT base_insn;
  64 #if CGEN_INT_INSN_P
  65   CGEN_EXTRACT_INFO *info = NULL;
  66 #else
  67   CGEN_EXTRACT_INFO ex_info;
  68   CGEN_EXTRACT_INFO *info = &ex_info;
  69 #endif
  70
  71 #if CGEN_INT_INSN_P
  72   cgen_put_insn_value (od, buf, length, insn_value);
  73   bufp = buf;
  74   base_insn = insn_value; /*???*/
  75 #else
  76   ex_info.dis_info = NULL;
  77   ex_info.insn_bytes = insn_value;
  78   ex_info.valid = -1;
  79   base_insn = cgen_get_insn_value (od, buf, length);
  80   bufp = insn_value;
  81 #endif
  82
  83   if (!insn)
  84     {
  85       const CGEN_INSN_LIST *insn_list;
  86
  87       /* The instructions are stored in hash lists.
  88          Pick the first one and keep trying until we find the right one.  */
  89
  90       insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
  91       while (insn_list != NULL)
  92         {
  93           insn = insn_list->insn;
  94
  95           if (alias_p
  96               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
  97             {
  98               /* Basic bit mask must be correct.  */
  99               /* ??? May wish to allow target to defer this check until the
 100                  extract handler.  */
 101               if ((base_insn & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
 102                 {
 103                   /* ??? 0 is passed for `pc' */
 104                   int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
 105                                                            base_insn, fields,
 106                                                            (bfd_vma) 0);
 107                   if (elength > 0)
 108                     {
 109                       /* sanity check */
 110                       if (length != 0 && length != elength)
 111                         abort ();
 112                       return insn;
 113                     }
 114                 }
 115             }
 116
 117           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 118         }
 119     }
 120   else
 121     {
 122       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 123       if (! alias_p
 124           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 125         abort ();
 126       /* Sanity check: length must be correct.  */
 127       if (length != CGEN_INSN_BITSIZE (insn))
 128         abort ();
 129
 130       /* ??? 0 is passed for `pc' */
 131       length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
 132                                           (bfd_vma) 0);
 133       /* Sanity check: must succeed.
 134          Could relax this later if it ever proves useful.  */
 135       if (length == 0)
 136         abort ();
 137       return insn;
 138     }
 139
 140   return NULL;
 141 }
 142
 143 /* Fill in the operand instances used by INSN whose operands are FIELDS.
 144    INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
 145    in.  */
 146
 147 void
 148 fr30_cgen_get_insn_operands (od, insn, fields, indices)
 149      CGEN_OPCODE_DESC od;
 150      const CGEN_INSN * insn;
 151      const CGEN_FIELDS * fields;
 152      int *indices;
 153 {
 154   const CGEN_OPERAND_INSTANCE *opinst;
 155   int i;
 156
 157   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 158        opinst != NULL
 159          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 160        ++i, ++opinst)
 161     {
 162       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 163       if (op == NULL)
 164         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 165       else
 166         indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
 167                                                   fields);
 168     }
 169 }
 170
 171 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
 172    isn't known.
 173    The INSN, INSN_VALUE, and LENGTH arguments are passed to
 174    fr30_cgen_lookup_insn unchanged.
 175
 176    The result is the insn table entry or NULL if the instruction wasn't
 177    recognized.  */
 178
 179 const CGEN_INSN *
 180 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
 181      CGEN_OPCODE_DESC od;
 182      const CGEN_INSN *insn;
 183      CGEN_INSN_BYTES insn_value;
 184      int length;
 185      int *indices;
 186 {
 187   CGEN_FIELDS fields;
 188
 189   /* Pass non-zero for ALIAS_P only if INSN != NULL.
 190      If INSN == NULL, we want a real insn.  */
 191   insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
 192                                   insn != NULL);
 193   if (! insn)
 194     return NULL;
 195
 196   fr30_cgen_get_insn_operands (od, insn, &fields, indices);
 197   return insn;
 198 }
 199 /* Attributes.  */
 200
 201 static const CGEN_ATTR_ENTRY MACH_attr[] =
 202 {
 203   { "base", MACH_BASE },
 204   { "fr30", MACH_FR30 },
 205   { "max", MACH_MAX },
 206   { 0, 0 }
 207 };
 208
 209 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
 210 {
 211   { "CACHE-ADDR", NULL },
 212   { "FUN-ACCESS", NULL },
 213   { "PC", NULL },
 214   { "PROFILE", NULL },
 215   { 0, 0 }
 216 };
 217
 218 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
 219 {
 220   { "ABS-ADDR", NULL },
 221   { "HASH-PREFIX", NULL },
 222   { "NEGATIVE", NULL },
 223   { "PCREL-ADDR", NULL },
 224   { "RELAX", NULL },
 225   { "RELOC", NULL },
 226   { "SEM-ONLY", NULL },
 227   { "SIGN-OPT", NULL },
 228   { "SIGNED", NULL },
 229   { "UNSIGNED", NULL },
 230   { 0, 0 }
 231 };
 232
 233 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
 234 {
 235   { "ALIAS", NULL },
 236   { "COND-CTI", NULL },
 237   { "NO-DIS", NULL },
 238   { "RELAX", NULL },
 239   { "RELAXABLE", NULL },
 240   { "SKIP-CTI", NULL },
 241   { "UNCOND-CTI", NULL },
 242   { "VIRTUAL", NULL },
 243   { 0, 0 }
 244 };
 245
 246 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
 247 {
 248   { "ac", 13 },
 249   { "fp", 14 },
 250   { "sp", 15 },
 251   { "r0", 0 },
 252   { "r1", 1 },
 253   { "r2", 2 },
 254   { "r3", 3 },
 255   { "r4", 4 },
 256   { "r5", 5 },
 257   { "r6", 6 },
 258   { "r7", 7 },
 259   { "r8", 8 },
 260   { "r9", 9 },
 261   { "r10", 10 },
 262   { "r11", 11 },
 263   { "r12", 12 },
 264   { "r13", 13 },
 265   { "r14", 14 },
 266   { "r15", 15 }
 267 };
 268
 269 CGEN_KEYWORD fr30_cgen_opval_h_gr =
 270 {
 271   & fr30_cgen_opval_h_gr_entries[0],
 272   19
 273 };
 274
 275 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
 276 {
 277   { "cr0", 0 },
 278   { "cr1", 1 },
 279   { "cr2", 2 },
 280   { "cr3", 3 },
 281   { "cr4", 4 },
 282   { "cr5", 5 },
 283   { "cr6", 6 },
 284   { "cr7", 7 },
 285   { "cr8", 8 },
 286   { "cr9", 9 },
 287   { "cr10", 10 },
 288   { "cr11", 11 },
 289   { "cr12", 12 },
 290   { "cr13", 13 },
 291   { "cr14", 14 },
 292   { "cr15", 15 }
 293 };
 294
 295 CGEN_KEYWORD fr30_cgen_opval_h_cr =
 296 {
 297   & fr30_cgen_opval_h_cr_entries[0],
 298   16
 299 };
 300
 301 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
 302 {
 303   { "tbr", 0 },
 304   { "rp", 1 },
 305   { "ssp", 2 },
 306   { "usp", 3 },
 307   { "mdh", 4 },
 308   { "mdl", 5 }
 309 };
 310
 311 CGEN_KEYWORD fr30_cgen_opval_h_dr =
 312 {
 313   & fr30_cgen_opval_h_dr_entries[0],
 314   6
 315 };
 316
 317 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
 318 {
 319   { "ps", 0 }
 320 };
 321
 322 CGEN_KEYWORD fr30_cgen_opval_h_ps =
 323 {
 324   & fr30_cgen_opval_h_ps_entries[0],
 325   1
 326 };
 327
 328 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
 329 {
 330   { "r13", 0 }
 331 };
 332
 333 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
 334 {
 335   & fr30_cgen_opval_h_r13_entries[0],
 336   1
 337 };
 338
 339 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
 340 {
 341   { "r14", 0 }
 342 };
 343
 344 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
 345 {
 346   & fr30_cgen_opval_h_r14_entries[0],
 347   1
 348 };
 349
 350 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
 351 {
 352   { "r15", 0 }
 353 };
 354
 355 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
 356 {
 357   & fr30_cgen_opval_h_r15_entries[0],
 358   1
 359 };
 360
 361
 362 /* The hardware table.  */
 363
 364 #define HW_ENT(n) fr30_cgen_hw_entries[n]
 365 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
 366 {
 367   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
 368   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 369   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 370   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 371   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 372   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 373   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
 374   { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0, { 0 } } },
 375   { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
 376   { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
 377   { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
 378   { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
 379   { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
 380   { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 381   { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 382   { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 383   { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 384   { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 385   { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 386   { 0 }
 387 };
 388
 389 /* The operand table.  */
 390
 391 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
 392 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
 393
 394 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
 395 {
 396 /* pc: program counter */
 397   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 398     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 399 /* Ri: destination register */
 400   { "Ri", & HW_ENT (HW_H_GR), 12, 4,
 401     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 402 /* Rj: source register */
 403   { "Rj", & HW_ENT (HW_H_GR), 8, 4,
 404     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 405 /* Ric: target register coproc insn */
 406   { "Ric", & HW_ENT (HW_H_GR), 28, 4,
 407     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 408 /* Rjc: source register coproc insn */
 409   { "Rjc", & HW_ENT (HW_H_GR), 24, 4,
 410     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 411 /* CRi: coprocessor register */
 412   { "CRi", & HW_ENT (HW_H_CR), 28, 4,
 413     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 414 /* CRj: coprocessor register */
 415   { "CRj", & HW_ENT (HW_H_CR), 24, 4,
 416     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 417 /* Rs1: dedicated register */
 418   { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
 419     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 420 /* Rs2: dedicated register */
 421   { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
 422     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 423 /* R13: General Register 13 */
 424   { "R13", & HW_ENT (HW_H_R13), 0, 0,
 425     { 0, 0, { 0 } }  },
 426 /* R14: General Register 14 */
 427   { "R14", & HW_ENT (HW_H_R14), 0, 0,
 428     { 0, 0, { 0 } }  },
 429 /* R15: General Register 15 */
 430   { "R15", & HW_ENT (HW_H_R15), 0, 0,
 431     { 0, 0, { 0 } }  },
 432 /* ps: Program Status register */
 433   { "ps", & HW_ENT (HW_H_PS), 0, 0,
 434     { 0, 0, { 0 } }  },
 435 /* u4: 4  bit unsigned immediate */
 436   { "u4", & HW_ENT (HW_H_UINT), 8, 4,
 437     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 438 /* u4c: 4  bit unsigned immediate */
 439   { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
 440     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 441 /* m4: 4  bit negative immediate */
 442   { "m4", & HW_ENT (HW_H_UINT), 8, 4,
 443     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 444 /* u8: 8  bit unsigned immediate */
 445   { "u8", & HW_ENT (HW_H_UINT), 8, 8,
 446     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 447 /* i8: 8  bit unsigned immediate */
 448   { "i8", & HW_ENT (HW_H_UINT), 4, 8,
 449     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 450 /* udisp6: 6  bit unsigned immediate */
 451   { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
 452     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 453 /* disp8: 8  bit signed   immediate */
 454   { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
 455     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 456 /* disp9: 9  bit signed   immediate */
 457   { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
 458     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 459 /* disp10: 10 bit signed   immediate */
 460   { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
 461     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 462 /* s10: 10 bit signed   immediate */
 463   { "s10", & HW_ENT (HW_H_SINT), 8, 8,
 464     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 465 /* u10: 10 bit unsigned immediate */
 466   { "u10", & HW_ENT (HW_H_UINT), 8, 8,
 467     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 468 /* i32: 32 bit immediate */
 469   { "i32", & HW_ENT (HW_H_UINT), 16, 32,
 470     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 471 /* dir8: 8  bit direct address */
 472   { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
 473     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 474 /* dir9: 9  bit direct address */
 475   { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
 476     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 477 /* dir10: 10 bit direct address */
 478   { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
 479     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 480 /* label9: 9  bit pc relative address */
 481   { "label9", & HW_ENT (HW_H_UINT), 8, 8,
 482     { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 483 /* label12: 12 bit pc relative address */
 484   { "label12", & HW_ENT (HW_H_SINT), 5, 11,
 485     { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 486 /* reglist_low: 8 bit register mask */
 487   { "reglist_low", & HW_ENT (HW_H_UINT), 8, 8,
 488     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 489 /* reglist_hi: 8 bit register mask */
 490   { "reglist_hi", & HW_ENT (HW_H_UINT), 8, 8,
 491     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 492 /* cc: condition codes */
 493   { "cc", & HW_ENT (HW_H_UINT), 4, 4,
 494     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 495 /* ccc: coprocessor calc */
 496   { "ccc", & HW_ENT (HW_H_UINT), 16, 8,
 497     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 498 /* nbit: negative  bit */
 499   { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
 500     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 501 /* vbit: overflow  bit */
 502   { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
 503     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 504 /* zbit: zero      bit */
 505   { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
 506     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 507 /* cbit: carry     bit */
 508   { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
 509     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 510 /* ibit: interrupt bit */
 511   { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
 512     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 513 /* sbit: stack     bit */
 514   { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
 515     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 516 };
 517
 518 /* Operand references.  */
 519
 520 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 521 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 522 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
 523
 524 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
 525   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 526   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 527   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 528   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 529   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 530   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 531   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 532   { 0 }
 533 };
 534
 535 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
 536   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 537   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
 538   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 539   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 540   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 541   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 542   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 543   { 0 }
 544 };
 545
 546 static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
 547   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 548   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
 549   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 550   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 551   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 552   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 553   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 554   { 0 }
 555 };
 556
 557 static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
 558   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 559   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 560   { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 561   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 562   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 563   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 564   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 565   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 566   { 0 }
 567 };
 568
 569 static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
 570   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 571   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 572   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 573   { 0 }
 574 };
 575
 576 static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
 577   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 578   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
 579   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 580   { 0 }
 581 };
 582
 583 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
 584   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 585   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
 586   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 587   { 0 }
 588 };
 589
 590 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
 591   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 592   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 593   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 594   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 595   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 596   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 597   { 0 }
 598 };
 599
 600 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
 601   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 602   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
 603   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 604   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 605   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 606   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 607   { 0 }
 608 };
 609
 610 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
 611   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 612   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
 613   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 614   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 615   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 616   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 617   { 0 }
 618 };
 619
 620 static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
 621   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 622   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 623   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 624   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 625   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 626   { 0 }
 627 };
 628
 629 static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
 630   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
 631   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
 632   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 633   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 634   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 635   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
 636   { 0 }
 637 };
 638
 639 static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
 640   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
 641   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
 642   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
 643   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 644   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 645   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
 646   { 0 }
 647 };
 648
 649 static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
 650   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
 651   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
 652   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
 653   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 654   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 655   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
 656   { 0 }
 657 };
 658
 659 static const CGEN_OPERAND_INSTANCE fmt_bandl_ops[] = {
 660   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
 661   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
 662   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
 663   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
 664   { 0 }
 665 };
 666
 667 static const CGEN_OPERAND_INSTANCE fmt_btstl_ops[] = {
 668   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
 669   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
 670   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
 671   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 672   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 673   { 0 }
 674 };
 675
 676 static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
 677   { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
 678   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 679   { 0 }
 680 };
 681
 682 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
 683   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 684   { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_USI, & OP_ENT (RS1), 0, 0 },
 685   { 0 }
 686 };
 687
 688 static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
 689   { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
 690   { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
 691   { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, 0 },
 692   { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
 693   { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
 694   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
 695   { 0 }
 696 };
 697
 698 static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
 699   { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
 700   { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, COND_REF },
 701   { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
 702   { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 3, COND_REF },
 703   { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
 704   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
 705   { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, COND_REF },
 706   { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
 707   { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 3, COND_REF },
 708   { 0 }
 709 };
 710
 711 static const CGEN_OPERAND_INSTANCE fmt_bra_ops[] = {
 712   { INPUT, "label9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, 0 },
 713   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
 714   { 0 }
 715 };
 716
 717 #undef INPUT
 718 #undef OUTPUT
 719 #undef COND_REF
 720
 721 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
 722 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
 723 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 724
 725 /* The instruction table.
 726    This is currently non-static because the simulator accesses it
 727    directly.  */
 728
 729 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
 730 {
 731   /* Special null first entry.
 732      A `num' value of zero is thus invalid.
 733      Also, the special `invalid' insn resides here.  */
 734   { { 0 }, 0 },
 735 /* add $Rj,$Ri */
 736   {
 737     { 1, 1, 1, 1 },
 738     FR30_INSN_ADD, "add", "add",
 739     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 740     { 16, 16, 0xff00 }, 0xa600,
 741     (PTR) & fmt_add_ops[0],
 742     { 0, 0, { 0 } }
 743   },
 744 /* add $u4,$Ri */
 745   {
 746     { 1, 1, 1, 1 },
 747     FR30_INSN_ADDI, "addi", "add",
 748     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 749     { 16, 16, 0xff00 }, 0xa400,
 750     (PTR) & fmt_addi_ops[0],
 751     { 0, 0, { 0 } }
 752   },
 753 /* add2 $m4,$Ri */
 754   {
 755     { 1, 1, 1, 1 },
 756     FR30_INSN_ADD2, "add2", "add2",
 757     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 758     { 16, 16, 0xff00 }, 0xa500,
 759     (PTR) & fmt_add2_ops[0],
 760     { 0, 0, { 0 } }
 761   },
 762 /* addc $Rj,$Ri */
 763   {
 764     { 1, 1, 1, 1 },
 765     FR30_INSN_ADDC, "addc", "addc",
 766     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 767     { 16, 16, 0xff00 }, 0xa700,
 768     (PTR) & fmt_addc_ops[0],
 769     { 0, 0, { 0 } }
 770   },
 771 /* addn $Rj,$Ri */
 772   {
 773     { 1, 1, 1, 1 },
 774     FR30_INSN_ADDN, "addn", "addn",
 775     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 776     { 16, 16, 0xff00 }, 0xa200,
 777     (PTR) & fmt_addn_ops[0],
 778     { 0, 0, { 0 } }
 779   },
 780 /* addn $u4,$Ri */
 781   {
 782     { 1, 1, 1, 1 },
 783     FR30_INSN_ADDNI, "addni", "addn",
 784     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 785     { 16, 16, 0xff00 }, 0xa000,
 786     (PTR) & fmt_addni_ops[0],
 787     { 0, 0, { 0 } }
 788   },
 789 /* addn2 $m4,$Ri */
 790   {
 791     { 1, 1, 1, 1 },
 792     FR30_INSN_ADDN2, "addn2", "addn2",
 793     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 794     { 16, 16, 0xff00 }, 0xa100,
 795     (PTR) & fmt_addn2_ops[0],
 796     { 0, 0, { 0 } }
 797   },
 798 /* sub $Rj,$Ri */
 799   {
 800     { 1, 1, 1, 1 },
 801     FR30_INSN_SUB, "sub", "sub",
 802     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 803     { 16, 16, 0xff00 }, 0xac00,
 804     (PTR) & fmt_add_ops[0],
 805     { 0, 0, { 0 } }
 806   },
 807 /* subc $Rj,$Ri */
 808   {
 809     { 1, 1, 1, 1 },
 810     FR30_INSN_SUBC, "subc", "subc",
 811     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 812     { 16, 16, 0xff00 }, 0xad00,
 813     (PTR) & fmt_addc_ops[0],
 814     { 0, 0, { 0 } }
 815   },
 816 /* subn $Rj,$Ri */
 817   {
 818     { 1, 1, 1, 1 },
 819     FR30_INSN_SUBN, "subn", "subn",
 820     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 821     { 16, 16, 0xff00 }, 0xae00,
 822     (PTR) & fmt_addn_ops[0],
 823     { 0, 0, { 0 } }
 824   },
 825 /* cmp $Rj,$Ri */
 826   {
 827     { 1, 1, 1, 1 },
 828     FR30_INSN_CMP, "cmp", "cmp",
 829     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 830     { 16, 16, 0xff00 }, 0xaa00,
 831     (PTR) & fmt_cmp_ops[0],
 832     { 0, 0, { 0 } }
 833   },
 834 /* cmp $u4,$Ri */
 835   {
 836     { 1, 1, 1, 1 },
 837     FR30_INSN_CMPI, "cmpi", "cmp",
 838     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 839     { 16, 16, 0xff00 }, 0xa800,
 840     (PTR) & fmt_cmpi_ops[0],
 841     { 0, 0, { 0 } }
 842   },
 843 /* cmp2 $m4,$Ri */
 844   {
 845     { 1, 1, 1, 1 },
 846     FR30_INSN_CMP2, "cmp2", "cmp2",
 847     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 848     { 16, 16, 0xff00 }, 0xa900,
 849     (PTR) & fmt_cmp2_ops[0],
 850     { 0, 0, { 0 } }
 851   },
 852 /* and $Rj,$Ri */
 853   {
 854     { 1, 1, 1, 1 },
 855     FR30_INSN_AND, "and", "and",
 856     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 857     { 16, 16, 0xff00 }, 0x8200,
 858     (PTR) & fmt_and_ops[0],
 859     { 0, 0, { 0 } }
 860   },
 861 /* or $Rj,$Ri */
 862   {
 863     { 1, 1, 1, 1 },
 864     FR30_INSN_OR, "or", "or",
 865     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 866     { 16, 16, 0xff00 }, 0x9200,
 867     (PTR) & fmt_and_ops[0],
 868     { 0, 0, { 0 } }
 869   },
 870 /* eor $Rj,$Ri */
 871   {
 872     { 1, 1, 1, 1 },
 873     FR30_INSN_EOR, "eor", "eor",
 874     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 875     { 16, 16, 0xff00 }, 0x9a00,
 876     (PTR) & fmt_and_ops[0],
 877     { 0, 0, { 0 } }
 878   },
 879 /* and $Rj,@$Ri */
 880   {
 881     { 1, 1, 1, 1 },
 882     FR30_INSN_ANDM, "andm", "and",
 883     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 884     { 16, 16, 0xff00 }, 0x8400,
 885     (PTR) & fmt_andm_ops[0],
 886     { 0, 0, { 0 } }
 887   },
 888 /* andh $Rj,@$Ri */
 889   {
 890     { 1, 1, 1, 1 },
 891     FR30_INSN_ANDH, "andh", "andh",
 892     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 893     { 16, 16, 0xff00 }, 0x8500,
 894     (PTR) & fmt_andh_ops[0],
 895     { 0, 0, { 0 } }
 896   },
 897 /* andb $Rj,@$Ri */
 898   {
 899     { 1, 1, 1, 1 },
 900     FR30_INSN_ANDB, "andb", "andb",
 901     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 902     { 16, 16, 0xff00 }, 0x8600,
 903     (PTR) & fmt_andb_ops[0],
 904     { 0, 0, { 0 } }
 905   },
 906 /* or $Rj,@$Ri */
 907   {
 908     { 1, 1, 1, 1 },
 909     FR30_INSN_ORM, "orm", "or",
 910     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 911     { 16, 16, 0xff00 }, 0x9400,
 912     (PTR) & fmt_andm_ops[0],
 913     { 0, 0, { 0 } }
 914   },
 915 /* orh $Rj,@$Ri */
 916   {
 917     { 1, 1, 1, 1 },
 918     FR30_INSN_ORH, "orh", "orh",
 919     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 920     { 16, 16, 0xff00 }, 0x9500,
 921     (PTR) & fmt_andh_ops[0],
 922     { 0, 0, { 0 } }
 923   },
 924 /* orb $Rj,@$Ri */
 925   {
 926     { 1, 1, 1, 1 },
 927     FR30_INSN_ORB, "orb", "orb",
 928     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 929     { 16, 16, 0xff00 }, 0x9600,
 930     (PTR) & fmt_andb_ops[0],
 931     { 0, 0, { 0 } }
 932   },
 933 /* eor $Rj,@$Ri */
 934   {
 935     { 1, 1, 1, 1 },
 936     FR30_INSN_EORM, "eorm", "eor",
 937     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 938     { 16, 16, 0xff00 }, 0x9c00,
 939     (PTR) & fmt_andm_ops[0],
 940     { 0, 0, { 0 } }
 941   },
 942 /* eorh $Rj,@$Ri */
 943   {
 944     { 1, 1, 1, 1 },
 945     FR30_INSN_EORH, "eorh", "eorh",
 946     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 947     { 16, 16, 0xff00 }, 0x9d00,
 948     (PTR) & fmt_andh_ops[0],
 949     { 0, 0, { 0 } }
 950   },
 951 /* eorb $Rj,@$Ri */
 952   {
 953     { 1, 1, 1, 1 },
 954     FR30_INSN_EORB, "eorb", "eorb",
 955     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 956     { 16, 16, 0xff00 }, 0x9e00,
 957     (PTR) & fmt_andb_ops[0],
 958     { 0, 0, { 0 } }
 959   },
 960 /* bandl $u4,@$Ri */
 961   {
 962     { 1, 1, 1, 1 },
 963     FR30_INSN_BANDL, "bandl", "bandl",
 964     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 965     { 16, 16, 0xff00 }, 0x8000,
 966     (PTR) & fmt_bandl_ops[0],
 967     { 0, 0, { 0 } }
 968   },
 969 /* borl $u4,@$Ri */
 970   {
 971     { 1, 1, 1, 1 },
 972     FR30_INSN_BORL, "borl", "borl",
 973     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 974     { 16, 16, 0xff00 }, 0x9000,
 975     (PTR) & fmt_bandl_ops[0],
 976     { 0, 0, { 0 } }
 977   },
 978 /* beorl $u4,@$Ri */
 979   {
 980     { 1, 1, 1, 1 },
 981     FR30_INSN_BEORL, "beorl", "beorl",
 982     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 983     { 16, 16, 0xff00 }, 0x9800,
 984     (PTR) & fmt_bandl_ops[0],
 985     { 0, 0, { 0 } }
 986   },
 987 /* bandh $u4,@$Ri */
 988   {
 989     { 1, 1, 1, 1 },
 990     FR30_INSN_BANDH, "bandh", "bandh",
 991     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 992     { 16, 16, 0xff00 }, 0x8100,
 993     (PTR) & fmt_bandl_ops[0],
 994     { 0, 0, { 0 } }
 995   },
 996 /* borh $u4,@$Ri */
 997   {
 998     { 1, 1, 1, 1 },
 999     FR30_INSN_BORH, "borh", "borh",
1000     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1001     { 16, 16, 0xff00 }, 0x9100,
1002     (PTR) & fmt_bandl_ops[0],
1003     { 0, 0, { 0 } }
1004   },
1005 /* beorh $u4,@$Ri */
1006   {
1007     { 1, 1, 1, 1 },
1008     FR30_INSN_BEORH, "beorh", "beorh",
1009     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1010     { 16, 16, 0xff00 }, 0x9900,
1011     (PTR) & fmt_bandl_ops[0],
1012     { 0, 0, { 0 } }
1013   },
1014 /* btstl $u4,@$Ri */
1015   {
1016     { 1, 1, 1, 1 },
1017     FR30_INSN_BTSTL, "btstl", "btstl",
1018     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1019     { 16, 16, 0xff00 }, 0x8800,
1020     (PTR) & fmt_btstl_ops[0],
1021     { 0, 0, { 0 } }
1022   },
1023 /* btsth $u4,@$Ri */
1024   {
1025     { 1, 1, 1, 1 },
1026     FR30_INSN_BTSTH, "btsth", "btsth",
1027     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1028     { 16, 16, 0xff00 }, 0x8900,
1029     (PTR) & fmt_btstl_ops[0],
1030     { 0, 0, { 0 } }
1031   },
1032 /* mul $Rj,$Ri */
1033   {
1034     { 1, 1, 1, 1 },
1035     FR30_INSN_MUL, "mul", "mul",
1036     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1037     { 16, 16, 0xff00 }, 0xaf00,
1038     (PTR) 0,
1039     { 0, 0, { 0 } }
1040   },
1041 /* mulu $Rj,$Ri */
1042   {
1043     { 1, 1, 1, 1 },
1044     FR30_INSN_MULU, "mulu", "mulu",
1045     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1046     { 16, 16, 0xff00 }, 0xab00,
1047     (PTR) 0,
1048     { 0, 0, { 0 } }
1049   },
1050 /* mulh $Rj,$Ri */
1051   {
1052     { 1, 1, 1, 1 },
1053     FR30_INSN_MULH, "mulh", "mulh",
1054     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1055     { 16, 16, 0xff00 }, 0xbf00,
1056     (PTR) 0,
1057     { 0, 0, { 0 } }
1058   },
1059 /* muluh $Rj,$Ri */
1060   {
1061     { 1, 1, 1, 1 },
1062     FR30_INSN_MULUH, "muluh", "muluh",
1063     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1064     { 16, 16, 0xff00 }, 0xbb00,
1065     (PTR) 0,
1066     { 0, 0, { 0 } }
1067   },
1068 /* div0s $Ri */
1069   {
1070     { 1, 1, 1, 1 },
1071     FR30_INSN_DIV0S, "div0s", "div0s",
1072     { { MNEM, ' ', OP (RI), 0 } },
1073     { 16, 16, 0xfff0 }, 0x9740,
1074     (PTR) 0,
1075     { 0, 0, { 0 } }
1076   },
1077 /* div0u $Ri */
1078   {
1079     { 1, 1, 1, 1 },
1080     FR30_INSN_DIV0U, "div0u", "div0u",
1081     { { MNEM, ' ', OP (RI), 0 } },
1082     { 16, 16, 0xfff0 }, 0x9750,
1083     (PTR) 0,
1084     { 0, 0, { 0 } }
1085   },
1086 /* div1 $Ri */
1087   {
1088     { 1, 1, 1, 1 },
1089     FR30_INSN_DIV1, "div1", "div1",
1090     { { MNEM, ' ', OP (RI), 0 } },
1091     { 16, 16, 0xfff0 }, 0x9760,
1092     (PTR) 0,
1093     { 0, 0, { 0 } }
1094   },
1095 /* div2 $Ri */
1096   {
1097     { 1, 1, 1, 1 },
1098     FR30_INSN_DIV2, "div2", "div2",
1099     { { MNEM, ' ', OP (RI), 0 } },
1100     { 16, 16, 0xfff0 }, 0x9770,
1101     (PTR) 0,
1102     { 0, 0, { 0 } }
1103   },
1104 /* div3 */
1105   {
1106     { 1, 1, 1, 1 },
1107     FR30_INSN_DIV3, "div3", "div3",
1108     { { MNEM, 0 } },
1109     { 16, 16, 0xffff }, 0x9f60,
1110     (PTR) 0,
1111     { 0, 0, { 0 } }
1112   },
1113 /* div4s */
1114   {
1115     { 1, 1, 1, 1 },
1116     FR30_INSN_DIV4S, "div4s", "div4s",
1117     { { MNEM, 0 } },
1118     { 16, 16, 0xffff }, 0x9f70,
1119     (PTR) 0,
1120     { 0, 0, { 0 } }
1121   },
1122 /* lsl $Rj,$Ri */
1123   {
1124     { 1, 1, 1, 1 },
1125     FR30_INSN_LSL, "lsl", "lsl",
1126     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1127     { 16, 16, 0xff00 }, 0xb600,
1128     (PTR) 0,
1129     { 0, 0, { 0 } }
1130   },
1131 /* lsl $u4,$Ri */
1132   {
1133     { 1, 1, 1, 1 },
1134     FR30_INSN_LSLI, "lsli", "lsl",
1135     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1136     { 16, 16, 0xff00 }, 0xb400,
1137     (PTR) 0,
1138     { 0, 0, { 0 } }
1139   },
1140 /* lsl2 $u4,$Ri */
1141   {
1142     { 1, 1, 1, 1 },
1143     FR30_INSN_LSL2, "lsl2", "lsl2",
1144     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1145     { 16, 16, 0xff00 }, 0xb500,
1146     (PTR) 0,
1147     { 0, 0, { 0 } }
1148   },
1149 /* lsr $Rj,$Ri */
1150   {
1151     { 1, 1, 1, 1 },
1152     FR30_INSN_LSR, "lsr", "lsr",
1153     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1154     { 16, 16, 0xff00 }, 0xb200,
1155     (PTR) 0,
1156     { 0, 0, { 0 } }
1157   },
1158 /* lsr $u4,$Ri */
1159   {
1160     { 1, 1, 1, 1 },
1161     FR30_INSN_LSRI, "lsri", "lsr",
1162     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1163     { 16, 16, 0xff00 }, 0xb000,
1164     (PTR) 0,
1165     { 0, 0, { 0 } }
1166   },
1167 /* lsr2 $u4,$Ri */
1168   {
1169     { 1, 1, 1, 1 },
1170     FR30_INSN_LSR2, "lsr2", "lsr2",
1171     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1172     { 16, 16, 0xff00 }, 0xb100,
1173     (PTR) 0,
1174     { 0, 0, { 0 } }
1175   },
1176 /* asr $Rj,$Ri */
1177   {
1178     { 1, 1, 1, 1 },
1179     FR30_INSN_ASR, "asr", "asr",
1180     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1181     { 16, 16, 0xff00 }, 0xba00,
1182     (PTR) 0,
1183     { 0, 0, { 0 } }
1184   },
1185 /* asr $u4,$Ri */
1186   {
1187     { 1, 1, 1, 1 },
1188     FR30_INSN_ASRI, "asri", "asr",
1189     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1190     { 16, 16, 0xff00 }, 0xb800,
1191     (PTR) 0,
1192     { 0, 0, { 0 } }
1193   },
1194 /* asr2 $u4,$Ri */
1195   {
1196     { 1, 1, 1, 1 },
1197     FR30_INSN_ASR2, "asr2", "asr2",
1198     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1199     { 16, 16, 0xff00 }, 0xb900,
1200     (PTR) 0,
1201     { 0, 0, { 0 } }
1202   },
1203 /* ldi:8 $i8,$Ri */
1204   {
1205     { 1, 1, 1, 1 },
1206     FR30_INSN_LDI_8, "ldi:8", "ldi:8",
1207     { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
1208     { 16, 16, 0xf000 }, 0xc000,
1209     (PTR) 0,
1210     { 0, 0, { 0 } }
1211   },
1212 /* ldi:32 $i32,$Ri */
1213   {
1214     { 1, 1, 1, 1 },
1215     FR30_INSN_LDI32, "ldi32", "ldi:32",
1216     { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
1217     { 16, 48, 0xfff0 }, 0x9f80,
1218     (PTR) & fmt_ldi32_ops[0],
1219     { 0, 0, { 0 } }
1220   },
1221 /* ld @$Rj,$Ri */
1222   {
1223     { 1, 1, 1, 1 },
1224     FR30_INSN_LD, "ld", "ld",
1225     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1226     { 16, 16, 0xff00 }, 0x400,
1227     (PTR) 0,
1228     { 0, 0, { 0 } }
1229   },
1230 /* lduh @$Rj,$Ri */
1231   {
1232     { 1, 1, 1, 1 },
1233     FR30_INSN_LDUH, "lduh", "lduh",
1234     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1235     { 16, 16, 0xff00 }, 0x500,
1236     (PTR) 0,
1237     { 0, 0, { 0 } }
1238   },
1239 /* ldub @$Rj,$Ri */
1240   {
1241     { 1, 1, 1, 1 },
1242     FR30_INSN_LDUB, "ldub", "ldub",
1243     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1244     { 16, 16, 0xff00 }, 0x600,
1245     (PTR) 0,
1246     { 0, 0, { 0 } }
1247   },
1248 /* ld @($R13,$Rj),$Ri */
1249   {
1250     { 1, 1, 1, 1 },
1251     FR30_INSN_LDR13, "ldr13", "ld",
1252     { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1253     { 16, 16, 0xff00 }, 0x0,
1254     (PTR) 0,
1255     { 0, 0, { 0 } }
1256   },
1257 /* lduh @($R13,$Rj),$Ri */
1258   {
1259     { 1, 1, 1, 1 },
1260     FR30_INSN_LDR13UH, "ldr13uh", "lduh",
1261     { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1262     { 16, 16, 0xff00 }, 0x100,
1263     (PTR) 0,
1264     { 0, 0, { 0 } }
1265   },
1266 /* ldub @($R13,$Rj),$Ri */
1267   {
1268     { 1, 1, 1, 1 },
1269     FR30_INSN_LDR13UB, "ldr13ub", "ldub",
1270     { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1271     { 16, 16, 0xff00 }, 0x200,
1272     (PTR) 0,
1273     { 0, 0, { 0 } }
1274   },
1275 /* ld @($R14,$disp10),$Ri */
1276   {
1277     { 1, 1, 1, 1 },
1278     FR30_INSN_LDR14, "ldr14", "ld",
1279     { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
1280     { 16, 16, 0xf000 }, 0x2000,
1281     (PTR) 0,
1282     { 0, 0, { 0 } }
1283   },
1284 /* lduh @($R14,$disp9),$Ri */
1285   {
1286     { 1, 1, 1, 1 },
1287     FR30_INSN_LDR14UH, "ldr14uh", "lduh",
1288     { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
1289     { 16, 16, 0xf000 }, 0x4000,
1290     (PTR) 0,
1291     { 0, 0, { 0 } }
1292   },
1293 /* ldub @($R14,$disp8),$Ri */
1294   {
1295     { 1, 1, 1, 1 },
1296     FR30_INSN_LDR14UB, "ldr14ub", "ldub",
1297     { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
1298     { 16, 16, 0xf000 }, 0x6000,
1299     (PTR) 0,
1300     { 0, 0, { 0 } }
1301   },
1302 /* ld @($R15,$udisp6),$Ri */
1303   {
1304     { 1, 1, 1, 1 },
1305     FR30_INSN_LDR15, "ldr15", "ld",
1306     { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
1307     { 16, 16, 0xff00 }, 0x300,
1308     (PTR) 0,
1309     { 0, 0, { 0 } }
1310   },
1311 /* ld @$R15+,$Ri */
1312   {
1313     { 1, 1, 1, 1 },
1314     FR30_INSN_LDR15GR, "ldr15gr", "ld",
1315     { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
1316     { 16, 16, 0xfff0 }, 0x700,
1317     (PTR) 0,
1318     { 0, 0, { 0 } }
1319   },
1320 /* ld @$R15+,$Rs2 */
1321   {
1322     { 1, 1, 1, 1 },
1323     FR30_INSN_LDR15DR, "ldr15dr", "ld",
1324     { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
1325     { 16, 16, 0xfff0 }, 0x780,
1326     (PTR) 0,
1327     { 0, 0, { 0 } }
1328   },
1329 /* ld @$R15+,$ps */
1330   {
1331     { 1, 1, 1, 1 },
1332     FR30_INSN_LDR15PS, "ldr15ps", "ld",
1333     { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
1334     { 16, 16, 0xffff }, 0x790,
1335     (PTR) 0,
1336     { 0, 0, { 0 } }
1337   },
1338 /* st $Ri,@$Rj */
1339   {
1340     { 1, 1, 1, 1 },
1341     FR30_INSN_ST, "st", "st",
1342     { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1343     { 16, 16, 0xff00 }, 0x1400,
1344     (PTR) 0,
1345     { 0, 0, { 0 } }
1346   },
1347 /* sth $Ri,@$Rj */
1348   {
1349     { 1, 1, 1, 1 },
1350     FR30_INSN_STH, "sth", "sth",
1351     { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1352     { 16, 16, 0xff00 }, 0x1500,
1353     (PTR) 0,
1354     { 0, 0, { 0 } }
1355   },
1356 /* stb $Ri,@$Rj */
1357   {
1358     { 1, 1, 1, 1 },
1359     FR30_INSN_STB, "stb", "stb",
1360     { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1361     { 16, 16, 0xff00 }, 0x1600,
1362     (PTR) 0,
1363     { 0, 0, { 0 } }
1364   },
1365 /* st $Ri,@($R13,$Rj) */
1366   {
1367     { 1, 1, 1, 1 },
1368     FR30_INSN_STR13, "str13", "st",
1369     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1370     { 16, 16, 0xff00 }, 0x1000,
1371     (PTR) 0,
1372     { 0, 0, { 0 } }
1373   },
1374 /* sth $Ri,@($R13,$Rj) */
1375   {
1376     { 1, 1, 1, 1 },
1377     FR30_INSN_STR13H, "str13h", "sth",
1378     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1379     { 16, 16, 0xff00 }, 0x1100,
1380     (PTR) 0,
1381     { 0, 0, { 0 } }
1382   },
1383 /* stb $Ri,@($R13,$Rj) */
1384   {
1385     { 1, 1, 1, 1 },
1386     FR30_INSN_STR13B, "stR13b", "stb",
1387     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1388     { 16, 16, 0xff00 }, 0x1200,
1389     (PTR) 0,
1390     { 0, 0, { 0 } }
1391   },
1392 /* st $Ri,@($R14,$disp10) */
1393   {
1394     { 1, 1, 1, 1 },
1395     FR30_INSN_STR14, "str14", "st",
1396     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
1397     { 16, 16, 0xf000 }, 0x3000,
1398     (PTR) 0,
1399     { 0, 0, { 0 } }
1400   },
1401 /* sth $Ri,@($R14,$disp9) */
1402   {
1403     { 1, 1, 1, 1 },
1404     FR30_INSN_STR14H, "str14h", "sth",
1405     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
1406     { 16, 16, 0xf000 }, 0x5000,
1407     (PTR) 0,
1408     { 0, 0, { 0 } }
1409   },
1410 /* stb $Ri,@($R14,$disp8) */
1411   {
1412     { 1, 1, 1, 1 },
1413     FR30_INSN_STR14B, "str14b", "stb",
1414     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
1415     { 16, 16, 0xf000 }, 0x7000,
1416     (PTR) 0,
1417     { 0, 0, { 0 } }
1418   },
1419 /* st $Ri,@($R15,$udisp6) */
1420   {
1421     { 1, 1, 1, 1 },
1422     FR30_INSN_STR15, "str15", "st",
1423     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
1424     { 16, 16, 0xff00 }, 0x1300,
1425     (PTR) 0,
1426     { 0, 0, { 0 } }
1427   },
1428 /* st $Ri,@-$R15 */
1429   {
1430     { 1, 1, 1, 1 },
1431     FR30_INSN_STR15GR, "str15gr", "st",
1432     { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
1433     { 16, 16, 0xfff0 }, 0x1700,
1434     (PTR) 0,
1435     { 0, 0, { 0 } }
1436   },
1437 /* st $Rs2,@-$R15 */
1438   {
1439     { 1, 1, 1, 1 },
1440     FR30_INSN_STR15DR, "str15dr", "st",
1441     { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
1442     { 16, 16, 0xfff0 }, 0x1780,
1443     (PTR) 0,
1444     { 0, 0, { 0 } }
1445   },
1446 /* st $ps,@-$R15 */
1447   {
1448     { 1, 1, 1, 1 },
1449     FR30_INSN_STR15PS, "str15ps", "st",
1450     { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
1451     { 16, 16, 0xffff }, 0x1790,
1452     (PTR) 0,
1453     { 0, 0, { 0 } }
1454   },
1455 /* mov $Rj,$Ri */
1456   {
1457     { 1, 1, 1, 1 },
1458     FR30_INSN_MOV, "mov", "mov",
1459     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1460     { 16, 16, 0xff00 }, 0x8b00,
1461     (PTR) 0,
1462     { 0, 0, { 0 } }
1463   },
1464 /* mov $Rs1,$Ri */
1465   {
1466     { 1, 1, 1, 1 },
1467     FR30_INSN_MOVDR, "movdr", "mov",
1468     { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
1469     { 16, 16, 0xff00 }, 0xb700,
1470     (PTR) 0,
1471     { 0, 0, { 0 } }
1472   },
1473 /* mov $ps,$Ri */
1474   {
1475     { 1, 1, 1, 1 },
1476     FR30_INSN_MOVPS, "movps", "mov",
1477     { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
1478     { 16, 16, 0xfff0 }, 0x1710,
1479     (PTR) 0,
1480     { 0, 0, { 0 } }
1481   },
1482 /* mov $Ri,$Rs1 */
1483   {
1484     { 1, 1, 1, 1 },
1485     FR30_INSN_MOV2DR, "mov2dr", "mov",
1486     { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
1487     { 16, 16, 0xff00 }, 0xb300,
1488     (PTR) & fmt_mov2dr_ops[0],
1489     { 0, 0, { 0 } }
1490   },
1491 /* mov $Ri,$ps */
1492   {
1493     { 1, 1, 1, 1 },
1494     FR30_INSN_MOV2PS, "mov2ps", "mov",
1495     { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
1496     { 16, 16, 0xfff0 }, 0x710,
1497     (PTR) 0,
1498     { 0, 0, { 0 } }
1499   },
1500 /* jmp @$Ri */
1501   {
1502     { 1, 1, 1, 1 },
1503     FR30_INSN_JMP, "jmp", "jmp",
1504     { { MNEM, ' ', '@', OP (RI), 0 } },
1505     { 16, 16, 0xfff0 }, 0x9700,
1506     (PTR) 0,
1507     { 0, 0, { 0 } }
1508   },
1509 /* jmp:D @$Ri */
1510   {
1511     { 1, 1, 1, 1 },
1512     FR30_INSN_JMPD, "jmpd", "jmp:D",
1513     { { MNEM, ' ', '@', OP (RI), 0 } },
1514     { 16, 16, 0xfff0 }, 0x9f00,
1515     (PTR) 0,
1516     { 0, 0, { 0 } }
1517   },
1518 /* call @$Ri */
1519   {
1520     { 1, 1, 1, 1 },
1521     FR30_INSN_CALLR, "callr", "call",
1522     { { MNEM, ' ', '@', OP (RI), 0 } },
1523     { 16, 16, 0xfff0 }, 0x9710,
1524     (PTR) 0,
1525     { 0, 0, { 0 } }
1526   },
1527 /* call:D @$Ri */
1528   {
1529     { 1, 1, 1, 1 },
1530     FR30_INSN_CALLRD, "callrd", "call:D",
1531     { { MNEM, ' ', '@', OP (RI), 0 } },
1532     { 16, 16, 0xfff0 }, 0x9f10,
1533     (PTR) 0,
1534     { 0, 0, { 0 } }
1535   },
1536 /* call $label12 */
1537   {
1538     { 1, 1, 1, 1 },
1539     FR30_INSN_CALL, "call", "call",
1540     { { MNEM, ' ', OP (LABEL12), 0 } },
1541     { 16, 16, 0xf400 }, 0xd000,
1542     (PTR) 0,
1543     { 0, 0, { 0 } }
1544   },
1545 /* call:D $label12 */
1546   {
1547     { 1, 1, 1, 1 },
1548     FR30_INSN_CALLD, "calld", "call:D",
1549     { { MNEM, ' ', OP (LABEL12), 0 } },
1550     { 16, 16, 0xf400 }, 0xd400,
1551     (PTR) 0,
1552     { 0, 0, { 0 } }
1553   },
1554 /* ret */
1555   {
1556     { 1, 1, 1, 1 },
1557     FR30_INSN_RET, "ret", "ret",
1558     { { MNEM, 0 } },
1559     { 16, 16, 0xffff }, 0x9720,
1560     (PTR) 0,
1561     { 0, 0, { 0 } }
1562   },
1563 /* ret:D */
1564   {
1565     { 1, 1, 1, 1 },
1566     FR30_INSN_RETD, "retd", "ret:D",
1567     { { MNEM, 0 } },
1568     { 16, 16, 0xffff }, 0x9f20,
1569     (PTR) 0,
1570     { 0, 0, { 0 } }
1571   },
1572 /* int $u8 */
1573   {
1574     { 1, 1, 1, 1 },
1575     FR30_INSN_INT, "int", "int",
1576     { { MNEM, ' ', OP (U8), 0 } },
1577     { 16, 16, 0xff00 }, 0x1f00,
1578     (PTR) & fmt_int_ops[0],
1579     { 0, 0|A(UNCOND_CTI), { 0 } }
1580   },
1581 /* inte */
1582   {
1583     { 1, 1, 1, 1 },
1584     FR30_INSN_INTE, "inte", "inte",
1585     { { MNEM, 0 } },
1586     { 16, 16, 0xffff }, 0x9f30,
1587     (PTR) 0,
1588     { 0, 0, { 0 } }
1589   },
1590 /* reti */
1591   {
1592     { 1, 1, 1, 1 },
1593     FR30_INSN_RETI, "reti", "reti",
1594     { { MNEM, 0 } },
1595     { 16, 16, 0xffff }, 0x9730,
1596     (PTR) & fmt_reti_ops[0],
1597     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
1598   },
1599 /* bra $label9 */
1600   {
1601     { 1, 1, 1, 1 },
1602     FR30_INSN_BRA, "bra", "bra",
1603     { { MNEM, ' ', OP (LABEL9), 0 } },
1604     { 16, 16, 0xff00 }, 0xe000,
1605     (PTR) & fmt_bra_ops[0],
1606     { 0, 0|A(UNCOND_CTI), { 0 } }
1607   },
1608 /* bno $label9 */
1609   {
1610     { 1, 1, 1, 1 },
1611     FR30_INSN_BNO, "bno", "bno",
1612     { { MNEM, ' ', OP (LABEL9), 0 } },
1613     { 16, 16, 0xff00 }, 0xe100,
1614     (PTR) & fmt_bra_ops[0],
1615     { 0, 0|A(UNCOND_CTI), { 0 } }
1616   },
1617 /* beq $label9 */
1618   {
1619     { 1, 1, 1, 1 },
1620     FR30_INSN_BEQ, "beq", "beq",
1621     { { MNEM, ' ', OP (LABEL9), 0 } },
1622     { 16, 16, 0xff00 }, 0xe200,
1623     (PTR) & fmt_bra_ops[0],
1624     { 0, 0|A(UNCOND_CTI), { 0 } }
1625   },
1626 /* bne $label9 */
1627   {
1628     { 1, 1, 1, 1 },
1629     FR30_INSN_BNE, "bne", "bne",
1630     { { MNEM, ' ', OP (LABEL9), 0 } },
1631     { 16, 16, 0xff00 }, 0xe300,
1632     (PTR) & fmt_bra_ops[0],
1633     { 0, 0|A(UNCOND_CTI), { 0 } }
1634   },
1635 /* bc $label9 */
1636   {
1637     { 1, 1, 1, 1 },
1638     FR30_INSN_BC, "bc", "bc",
1639     { { MNEM, ' ', OP (LABEL9), 0 } },
1640     { 16, 16, 0xff00 }, 0xe400,
1641     (PTR) & fmt_bra_ops[0],
1642     { 0, 0|A(UNCOND_CTI), { 0 } }
1643   },
1644 /* bnc $label9 */
1645   {
1646     { 1, 1, 1, 1 },
1647     FR30_INSN_BNC, "bnc", "bnc",
1648     { { MNEM, ' ', OP (LABEL9), 0 } },
1649     { 16, 16, 0xff00 }, 0xe500,
1650     (PTR) & fmt_bra_ops[0],
1651     { 0, 0|A(UNCOND_CTI), { 0 } }
1652   },
1653 /* bn $label9 */
1654   {
1655     { 1, 1, 1, 1 },
1656     FR30_INSN_BN, "bn", "bn",
1657     { { MNEM, ' ', OP (LABEL9), 0 } },
1658     { 16, 16, 0xff00 }, 0xe600,
1659     (PTR) & fmt_bra_ops[0],
1660     { 0, 0|A(UNCOND_CTI), { 0 } }
1661   },
1662 /* bp $label9 */
1663   {
1664     { 1, 1, 1, 1 },
1665     FR30_INSN_BP, "bp", "bp",
1666     { { MNEM, ' ', OP (LABEL9), 0 } },
1667     { 16, 16, 0xff00 }, 0xe700,
1668     (PTR) & fmt_bra_ops[0],
1669     { 0, 0|A(UNCOND_CTI), { 0 } }
1670   },
1671 /* bv $label9 */
1672   {
1673     { 1, 1, 1, 1 },
1674     FR30_INSN_BV, "bv", "bv",
1675     { { MNEM, ' ', OP (LABEL9), 0 } },
1676     { 16, 16, 0xff00 }, 0xe800,
1677     (PTR) & fmt_bra_ops[0],
1678     { 0, 0|A(UNCOND_CTI), { 0 } }
1679   },
1680 /* bnv $label9 */
1681   {
1682     { 1, 1, 1, 1 },
1683     FR30_INSN_BNV, "bnv", "bnv",
1684     { { MNEM, ' ', OP (LABEL9), 0 } },
1685     { 16, 16, 0xff00 }, 0xe900,
1686     (PTR) & fmt_bra_ops[0],
1687     { 0, 0|A(UNCOND_CTI), { 0 } }
1688   },
1689 /* blt $label9 */
1690   {
1691     { 1, 1, 1, 1 },
1692     FR30_INSN_BLT, "blt", "blt",
1693     { { MNEM, ' ', OP (LABEL9), 0 } },
1694     { 16, 16, 0xff00 }, 0xea00,
1695     (PTR) & fmt_bra_ops[0],
1696     { 0, 0|A(UNCOND_CTI), { 0 } }
1697   },
1698 /* bge $label9 */
1699   {
1700     { 1, 1, 1, 1 },
1701     FR30_INSN_BGE, "bge", "bge",
1702     { { MNEM, ' ', OP (LABEL9), 0 } },
1703     { 16, 16, 0xff00 }, 0xeb00,
1704     (PTR) & fmt_bra_ops[0],
1705     { 0, 0|A(UNCOND_CTI), { 0 } }
1706   },
1707 /* ble $label9 */
1708   {
1709     { 1, 1, 1, 1 },
1710     FR30_INSN_BLE, "ble", "ble",
1711     { { MNEM, ' ', OP (LABEL9), 0 } },
1712     { 16, 16, 0xff00 }, 0xec00,
1713     (PTR) & fmt_bra_ops[0],
1714     { 0, 0|A(UNCOND_CTI), { 0 } }
1715   },
1716 /* bgt $label9 */
1717   {
1718     { 1, 1, 1, 1 },
1719     FR30_INSN_BGT, "bgt", "bgt",
1720     { { MNEM, ' ', OP (LABEL9), 0 } },
1721     { 16, 16, 0xff00 }, 0xed00,
1722     (PTR) & fmt_bra_ops[0],
1723     { 0, 0|A(UNCOND_CTI), { 0 } }
1724   },
1725 /* bls $label9 */
1726   {
1727     { 1, 1, 1, 1 },
1728     FR30_INSN_BLS, "bls", "bls",
1729     { { MNEM, ' ', OP (LABEL9), 0 } },
1730     { 16, 16, 0xff00 }, 0xee00,
1731     (PTR) & fmt_bra_ops[0],
1732     { 0, 0|A(UNCOND_CTI), { 0 } }
1733   },
1734 /* bhi $label9 */
1735   {
1736     { 1, 1, 1, 1 },
1737     FR30_INSN_BHI, "bhi", "bhi",
1738     { { MNEM, ' ', OP (LABEL9), 0 } },
1739     { 16, 16, 0xff00 }, 0xef00,
1740     (PTR) & fmt_bra_ops[0],
1741     { 0, 0|A(UNCOND_CTI), { 0 } }
1742   },
1743 /* bra:D $label9 */
1744   {
1745     { 1, 1, 1, 1 },
1746     FR30_INSN_BRAD, "brad", "bra:D",
1747     { { MNEM, ' ', OP (LABEL9), 0 } },
1748     { 16, 16, 0xff00 }, 0xf000,
1749     (PTR) & fmt_bra_ops[0],
1750     { 0, 0|A(UNCOND_CTI), { 0 } }
1751   },
1752 /* bno:D $label9 */
1753   {
1754     { 1, 1, 1, 1 },
1755     FR30_INSN_BNOD, "bnod", "bno:D",
1756     { { MNEM, ' ', OP (LABEL9), 0 } },
1757     { 16, 16, 0xff00 }, 0xf100,
1758     (PTR) & fmt_bra_ops[0],
1759     { 0, 0|A(UNCOND_CTI), { 0 } }
1760   },
1761 /* beq:D $label9 */
1762   {
1763     { 1, 1, 1, 1 },
1764     FR30_INSN_BEQD, "beqd", "beq:D",
1765     { { MNEM, ' ', OP (LABEL9), 0 } },
1766     { 16, 16, 0xff00 }, 0xf200,
1767     (PTR) & fmt_bra_ops[0],
1768     { 0, 0|A(UNCOND_CTI), { 0 } }
1769   },
1770 /* bne:D $label9 */
1771   {
1772     { 1, 1, 1, 1 },
1773     FR30_INSN_BNED, "bned", "bne:D",
1774     { { MNEM, ' ', OP (LABEL9), 0 } },
1775     { 16, 16, 0xff00 }, 0xf300,
1776     (PTR) & fmt_bra_ops[0],
1777     { 0, 0|A(UNCOND_CTI), { 0 } }
1778   },
1779 /* bc:D $label9 */
1780   {
1781     { 1, 1, 1, 1 },
1782     FR30_INSN_BCD, "bcd", "bc:D",
1783     { { MNEM, ' ', OP (LABEL9), 0 } },
1784     { 16, 16, 0xff00 }, 0xf400,
1785     (PTR) & fmt_bra_ops[0],
1786     { 0, 0|A(UNCOND_CTI), { 0 } }
1787   },
1788 /* bnc:D $label9 */
1789   {
1790     { 1, 1, 1, 1 },
1791     FR30_INSN_BNCD, "bncd", "bnc:D",
1792     { { MNEM, ' ', OP (LABEL9), 0 } },
1793     { 16, 16, 0xff00 }, 0xf500,
1794     (PTR) & fmt_bra_ops[0],
1795     { 0, 0|A(UNCOND_CTI), { 0 } }
1796   },
1797 /* bn:D $label9 */
1798   {
1799     { 1, 1, 1, 1 },
1800     FR30_INSN_BND, "bnd", "bn:D",
1801     { { MNEM, ' ', OP (LABEL9), 0 } },
1802     { 16, 16, 0xff00 }, 0xf600,
1803     (PTR) & fmt_bra_ops[0],
1804     { 0, 0|A(UNCOND_CTI), { 0 } }
1805   },
1806 /* bp:D $label9 */
1807   {
1808     { 1, 1, 1, 1 },
1809     FR30_INSN_BPD, "bpd", "bp:D",
1810     { { MNEM, ' ', OP (LABEL9), 0 } },
1811     { 16, 16, 0xff00 }, 0xf700,
1812     (PTR) & fmt_bra_ops[0],
1813     { 0, 0|A(UNCOND_CTI), { 0 } }
1814   },
1815 /* bv:D $label9 */
1816   {
1817     { 1, 1, 1, 1 },
1818     FR30_INSN_BVD, "bvd", "bv:D",
1819     { { MNEM, ' ', OP (LABEL9), 0 } },
1820     { 16, 16, 0xff00 }, 0xf800,
1821     (PTR) & fmt_bra_ops[0],
1822     { 0, 0|A(UNCOND_CTI), { 0 } }
1823   },
1824 /* bnv:D $label9 */
1825   {
1826     { 1, 1, 1, 1 },
1827     FR30_INSN_BNVD, "bnvd", "bnv:D",
1828     { { MNEM, ' ', OP (LABEL9), 0 } },
1829     { 16, 16, 0xff00 }, 0xf900,
1830     (PTR) & fmt_bra_ops[0],
1831     { 0, 0|A(UNCOND_CTI), { 0 } }
1832   },
1833 /* blt:D $label9 */
1834   {
1835     { 1, 1, 1, 1 },
1836     FR30_INSN_BLTD, "bltd", "blt:D",
1837     { { MNEM, ' ', OP (LABEL9), 0 } },
1838     { 16, 16, 0xff00 }, 0xfa00,
1839     (PTR) & fmt_bra_ops[0],
1840     { 0, 0|A(UNCOND_CTI), { 0 } }
1841   },
1842 /* bge:D $label9 */
1843   {
1844     { 1, 1, 1, 1 },
1845     FR30_INSN_BGED, "bged", "bge:D",
1846     { { MNEM, ' ', OP (LABEL9), 0 } },
1847     { 16, 16, 0xff00 }, 0xfb00,
1848     (PTR) & fmt_bra_ops[0],
1849     { 0, 0|A(UNCOND_CTI), { 0 } }
1850   },
1851 /* ble:D $label9 */
1852   {
1853     { 1, 1, 1, 1 },
1854     FR30_INSN_BLED, "bled", "ble:D",
1855     { { MNEM, ' ', OP (LABEL9), 0 } },
1856     { 16, 16, 0xff00 }, 0xfc00,
1857     (PTR) & fmt_bra_ops[0],
1858     { 0, 0|A(UNCOND_CTI), { 0 } }
1859   },
1860 /* bgt:D $label9 */
1861   {
1862     { 1, 1, 1, 1 },
1863     FR30_INSN_BGTD, "bgtd", "bgt:D",
1864     { { MNEM, ' ', OP (LABEL9), 0 } },
1865     { 16, 16, 0xff00 }, 0xfd00,
1866     (PTR) & fmt_bra_ops[0],
1867     { 0, 0|A(UNCOND_CTI), { 0 } }
1868   },
1869 /* bls:D $label9 */
1870   {
1871     { 1, 1, 1, 1 },
1872     FR30_INSN_BLSD, "blsd", "bls:D",
1873     { { MNEM, ' ', OP (LABEL9), 0 } },
1874     { 16, 16, 0xff00 }, 0xfe00,
1875     (PTR) & fmt_bra_ops[0],
1876     { 0, 0|A(UNCOND_CTI), { 0 } }
1877   },
1878 /* bhi:D $label9 */
1879   {
1880     { 1, 1, 1, 1 },
1881     FR30_INSN_BHID, "bhid", "bhi:D",
1882     { { MNEM, ' ', OP (LABEL9), 0 } },
1883     { 16, 16, 0xff00 }, 0xff00,
1884     (PTR) & fmt_bra_ops[0],
1885     { 0, 0|A(UNCOND_CTI), { 0 } }
1886   },
1887 /* dmov $R13,@$dir10 */
1888   {
1889     { 1, 1, 1, 1 },
1890     FR30_INSN_DMOVR13, "dmovr13", "dmov",
1891     { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
1892     { 16, 16, 0xff00 }, 0x1800,
1893     (PTR) 0,
1894     { 0, 0, { 0 } }
1895   },
1896 /* dmovh $R13,@$dir9 */
1897   {
1898     { 1, 1, 1, 1 },
1899     FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
1900     { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
1901     { 16, 16, 0xff00 }, 0x1900,
1902     (PTR) 0,
1903     { 0, 0, { 0 } }
1904   },
1905 /* dmovb $R13,@$dir8 */
1906   {
1907     { 1, 1, 1, 1 },
1908     FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
1909     { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
1910     { 16, 16, 0xff00 }, 0x1a00,
1911     (PTR) 0,
1912     { 0, 0, { 0 } }
1913   },
1914 /* dmov @$R13+,@$dir10 */
1915   {
1916     { 1, 1, 1, 1 },
1917     FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
1918     { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
1919     { 16, 16, 0xff00 }, 0x1c00,
1920     (PTR) 0,
1921     { 0, 0, { 0 } }
1922   },
1923 /* dmovh @$R13+,@$dir9 */
1924   {
1925     { 1, 1, 1, 1 },
1926     FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
1927     { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
1928     { 16, 16, 0xff00 }, 0x1d00,
1929     (PTR) 0,
1930     { 0, 0, { 0 } }
1931   },
1932 /* dmovb @$R13+,@$dir8 */
1933   {
1934     { 1, 1, 1, 1 },
1935     FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
1936     { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
1937     { 16, 16, 0xff00 }, 0x1e00,
1938     (PTR) 0,
1939     { 0, 0, { 0 } }
1940   },
1941 /* dmov @$R15+,@$dir10 */
1942   {
1943     { 1, 1, 1, 1 },
1944     FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
1945     { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
1946     { 16, 16, 0xff00 }, 0x1b00,
1947     (PTR) 0,
1948     { 0, 0, { 0 } }
1949   },
1950 /* dmov @$dir10,$R13 */
1951   {
1952     { 1, 1, 1, 1 },
1953     FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
1954     { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
1955     { 16, 16, 0xff00 }, 0x800,
1956     (PTR) 0,
1957     { 0, 0, { 0 } }
1958   },
1959 /* dmovh @$dir9,$R13 */
1960   {
1961     { 1, 1, 1, 1 },
1962     FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
1963     { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
1964     { 16, 16, 0xff00 }, 0x900,
1965     (PTR) 0,
1966     { 0, 0, { 0 } }
1967   },
1968 /* dmovb @$dir8,$R13 */
1969   {
1970     { 1, 1, 1, 1 },
1971     FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
1972     { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
1973     { 16, 16, 0xff00 }, 0xa00,
1974     (PTR) 0,
1975     { 0, 0, { 0 } }
1976   },
1977 /* dmov @$dir10,@$R13+ */
1978   {
1979     { 1, 1, 1, 1 },
1980     FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
1981     { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
1982     { 16, 16, 0xff00 }, 0xc00,
1983     (PTR) 0,
1984     { 0, 0, { 0 } }
1985   },
1986 /* dmovh @$dir9,@$R13+ */
1987   {
1988     { 1, 1, 1, 1 },
1989     FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
1990     { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
1991     { 16, 16, 0xff00 }, 0xd00,
1992     (PTR) 0,
1993     { 0, 0, { 0 } }
1994   },
1995 /* dmovb @$dir8,@$R13+ */
1996   {
1997     { 1, 1, 1, 1 },
1998     FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
1999     { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
2000     { 16, 16, 0xff00 }, 0xe00,
2001     (PTR) 0,
2002     { 0, 0, { 0 } }
2003   },
2004 /* dmov @$dir10,@-$R15 */
2005   {
2006     { 1, 1, 1, 1 },
2007     FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
2008     { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
2009     { 16, 16, 0xff00 }, 0xb00,
2010     (PTR) 0,
2011     { 0, 0, { 0 } }
2012   },
2013 /* ldres @$Ri+,$u4 */
2014   {
2015     { 1, 1, 1, 1 },
2016     FR30_INSN_LDRES, "ldres", "ldres",
2017     { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
2018     { 16, 16, 0xff00 }, 0xbc00,
2019     (PTR) 0,
2020     { 0, 0, { 0 } }
2021   },
2022 /* stres $u4,@$Ri+ */
2023   {
2024     { 1, 1, 1, 1 },
2025     FR30_INSN_STRES, "stres", "stres",
2026     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
2027     { 16, 16, 0xff00 }, 0xbd00,
2028     (PTR) 0,
2029     { 0, 0, { 0 } }
2030   },
2031 /* copop $u4c,$ccc,$CRj,$CRi */
2032   {
2033     { 1, 1, 1, 1 },
2034     FR30_INSN_COPOP, "copop", "copop",
2035     { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
2036     { 16, 32, 0xfff0 }, 0x9fc0,
2037     (PTR) 0,
2038     { 0, 0, { 0 } }
2039   },
2040 /* copld $u4c,$ccc,$Rjc,$CRi */
2041   {
2042     { 1, 1, 1, 1 },
2043     FR30_INSN_COPLD, "copld", "copld",
2044     { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
2045     { 16, 32, 0xfff0 }, 0x9fd0,
2046     (PTR) 0,
2047     { 0, 0, { 0 } }
2048   },
2049 /* copst $u4c,$ccc,$CRj,$Ric */
2050   {
2051     { 1, 1, 1, 1 },
2052     FR30_INSN_COPST, "copst", "copst",
2053     { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2054     { 16, 32, 0xfff0 }, 0x9fe0,
2055     (PTR) 0,
2056     { 0, 0, { 0 } }
2057   },
2058 /* copsv $u4c,$ccc,$CRj,$Ric */
2059   {
2060     { 1, 1, 1, 1 },
2061     FR30_INSN_COPSV, "copsv", "copsv",
2062     { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2063     { 16, 32, 0xfff0 }, 0x9ff0,
2064     (PTR) 0,
2065     { 0, 0, { 0 } }
2066   },
2067 /* nop */
2068   {
2069     { 1, 1, 1, 1 },
2070     FR30_INSN_NOP, "nop", "nop",
2071     { { MNEM, 0 } },
2072     { 16, 16, 0xffff }, 0x9fa0,
2073     (PTR) 0,
2074     { 0, 0, { 0 } }
2075   },
2076 /* andccr $u8 */
2077   {
2078     { 1, 1, 1, 1 },
2079     FR30_INSN_ANDCCR, "andccr", "andccr",
2080     { { MNEM, ' ', OP (U8), 0 } },
2081     { 16, 16, 0xff00 }, 0x8300,
2082     (PTR) 0,
2083     { 0, 0, { 0 } }
2084   },
2085 /* orccr $u8 */
2086   {
2087     { 1, 1, 1, 1 },
2088     FR30_INSN_ORCCR, "orccr", "orccr",
2089     { { MNEM, ' ', OP (U8), 0 } },
2090     { 16, 16, 0xff00 }, 0x9300,
2091     (PTR) 0,
2092     { 0, 0, { 0 } }
2093   },
2094 /* stilm $u8 */
2095   {
2096     { 1, 1, 1, 1 },
2097     FR30_INSN_STILM, "stilm", "stilm",
2098     { { MNEM, ' ', OP (U8), 0 } },
2099     { 16, 16, 0xff00 }, 0x8700,
2100     (PTR) 0,
2101     { 0, 0, { 0 } }
2102   },
2103 /* addsp $s10 */
2104   {
2105     { 1, 1, 1, 1 },
2106     FR30_INSN_ADDSP, "addsp", "addsp",
2107     { { MNEM, ' ', OP (S10), 0 } },
2108     { 16, 16, 0xff00 }, 0xa300,
2109     (PTR) 0,
2110     { 0, 0, { 0 } }
2111   },
2112 /* extsb $Ri */
2113   {
2114     { 1, 1, 1, 1 },
2115     FR30_INSN_EXTSB, "extsb", "extsb",
2116     { { MNEM, ' ', OP (RI), 0 } },
2117     { 16, 16, 0xfff0 }, 0x9780,
2118     (PTR) 0,
2119     { 0, 0, { 0 } }
2120   },
2121 /* extub $Ri */
2122   {
2123     { 1, 1, 1, 1 },
2124     FR30_INSN_EXTUB, "extub", "extub",
2125     { { MNEM, ' ', OP (RI), 0 } },
2126     { 16, 16, 0xfff0 }, 0x9790,
2127     (PTR) 0,
2128     { 0, 0, { 0 } }
2129   },
2130 /* extsh $Ri */
2131   {
2132     { 1, 1, 1, 1 },
2133     FR30_INSN_EXTSH, "extsh", "extsh",
2134     { { MNEM, ' ', OP (RI), 0 } },
2135     { 16, 16, 0xfff0 }, 0x97a0,
2136     (PTR) 0,
2137     { 0, 0, { 0 } }
2138   },
2139 /* extuh $Ri */
2140   {
2141     { 1, 1, 1, 1 },
2142     FR30_INSN_EXTUH, "extuh", "extuh",
2143     { { MNEM, ' ', OP (RI), 0 } },
2144     { 16, 16, 0xfff0 }, 0x97b0,
2145     (PTR) 0,
2146     { 0, 0, { 0 } }
2147   },
2148 /* ldm0 ($reglist_low) */
2149   {
2150     { 1, 1, 1, 1 },
2151     FR30_INSN_LDM0, "ldm0", "ldm0",
2152     { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
2153     { 16, 16, 0xff00 }, 0x8c00,
2154     (PTR) 0,
2155     { 0, 0, { 0 } }
2156   },
2157 /* ldm1 ($reglist_hi) */
2158   {
2159     { 1, 1, 1, 1 },
2160     FR30_INSN_LDM1, "ldm1", "ldm1",
2161     { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
2162     { 16, 16, 0xff00 }, 0x8d00,
2163     (PTR) 0,
2164     { 0, 0, { 0 } }
2165   },
2166 /* stm0 ($reglist_low) */
2167   {
2168     { 1, 1, 1, 1 },
2169     FR30_INSN_STM0, "stm0", "stm0",
2170     { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
2171     { 16, 16, 0xff00 }, 0x8e00,
2172     (PTR) 0,
2173     { 0, 0, { 0 } }
2174   },
2175 /* stm1 ($reglist_hi) */
2176   {
2177     { 1, 1, 1, 1 },
2178     FR30_INSN_STM1, "stm1", "stm1",
2179     { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
2180     { 16, 16, 0xff00 }, 0x8f00,
2181     (PTR) 0,
2182     { 0, 0, { 0 } }
2183   },
2184 /* enter $u10 */
2185   {
2186     { 1, 1, 1, 1 },
2187     FR30_INSN_ENTER, "enter", "enter",
2188     { { MNEM, ' ', OP (U10), 0 } },
2189     { 16, 16, 0xff00 }, 0xf00,
2190     (PTR) 0,
2191     { 0, 0, { 0 } }
2192   },
2193 /* leave */
2194   {
2195     { 1, 1, 1, 1 },
2196     FR30_INSN_LEAVE, "leave", "leave",
2197     { { MNEM, 0 } },
2198     { 16, 16, 0xffff }, 0x9f90,
2199     (PTR) 0,
2200     { 0, 0, { 0 } }
2201   },
2202 /* xchb @$Rj,$Ri */
2203   {
2204     { 1, 1, 1, 1 },
2205     FR30_INSN_XCHB, "xchb", "xchb",
2206     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2207     { 16, 16, 0xff00 }, 0x8a00,
2208     (PTR) 0,
2209     { 0, 0, { 0 } }
2210   },
2211 };
2212
2213 #undef A
2214 #undef MNEM
2215 #undef OP
2216
2217 static const CGEN_INSN_TABLE insn_table =
2218 {
2219   & fr30_cgen_insn_table_entries[0],
2220   sizeof (CGEN_INSN),
2221   MAX_INSNS,
2222   NULL
2223 };
2224
2225 /* Each non-simple macro entry points to an array of expansion possibilities.  */
2226
2227 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2228 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2229 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2230
2231 /* The macro instruction table.  */
2232
2233 static const CGEN_INSN macro_insn_table_entries[] =
2234 {
2235 /* ldi32 $i32,$Ri */
2236   {
2237     { 1, 1, 1, 1 },
2238     -1, "ldi32m", "ldi32",
2239     { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
2240     { 16, 48, 0xfff0 }, 0x9f80,
2241     (PTR) 0,
2242     { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
2243   },
2244 };
2245
2246 #undef A
2247 #undef MNEM
2248 #undef OP
2249
2250 static const CGEN_INSN_TABLE macro_insn_table =
2251 {
2252   & macro_insn_table_entries[0],
2253   sizeof (CGEN_INSN),
2254   (sizeof (macro_insn_table_entries) /
2255    sizeof (macro_insn_table_entries[0])),
2256   NULL
2257 };
2258
2259 static void
2260 init_tables ()
2261 {
2262 }
2263
2264 /* Return non-zero if INSN is to be added to the hash table.
2265    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
2266
2267 static int
2268 asm_hash_insn_p (insn)
2269      const CGEN_INSN * insn;
2270 {
2271   return CGEN_ASM_HASH_P (insn);
2272 }
2273
2274 static int
2275 dis_hash_insn_p (insn)
2276      const CGEN_INSN * insn;
2277 {
2278   /* If building the hash table and the NO-DIS attribute is present,
2279      ignore.  */
2280   if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2281     return 0;
2282   return CGEN_DIS_HASH_P (insn);
2283 }
2284
2285 /* The result is the hash value of the insn.
2286    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
2287
2288 static unsigned int
2289 asm_hash_insn (mnem)
2290      const char * mnem;
2291 {
2292   return CGEN_ASM_HASH (mnem);
2293 }
2294
2295 /* BUF is a pointer to the insn's bytes in target order.
2296    VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
2297    host order.  */
2298
2299 static unsigned int
2300 dis_hash_insn (buf, value)
2301      const char * buf;
2302      CGEN_INSN_INT value;
2303 {
2304   return CGEN_DIS_HASH (buf, value);
2305 }
2306
2307 /* Initialize an opcode table and return a descriptor.
2308    It's much like opening a file, and must be the first function called.  */
2309
2310 CGEN_OPCODE_DESC
2311 fr30_cgen_opcode_open (mach, endian)
2312      int mach;
2313      enum cgen_endian endian;
2314 {
2315   CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2316   static int init_p;
2317
2318   if (! init_p)
2319     {
2320       init_tables ();
2321       init_p = 1;
2322     }
2323
2324   memset (table, 0, sizeof (*table));
2325
2326   CGEN_OPCODE_MACH (table) = mach;
2327   CGEN_OPCODE_ENDIAN (table) = endian;
2328   /* FIXME: for the sparc case we can determine insn-endianness statically.
2329      The worry here is where both data and insn endian can be independently
2330      chosen, in which case this function will need another argument.
2331      Actually, will want to allow for more arguments in the future anyway.  */
2332   CGEN_OPCODE_INSN_ENDIAN (table) = endian;
2333
2334   CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
2335
2336   CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
2337
2338   * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2339
2340   * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2341
2342   CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2343   CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2344   CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2345
2346   CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2347   CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2348   CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2349
2350   return (CGEN_OPCODE_DESC) table;
2351 }
2352
2353 /* Close an opcode table.  */
2354
2355 void
2356 fr30_cgen_opcode_close (desc)
2357      CGEN_OPCODE_DESC desc;
2358 {
2359   free (desc);
2360 }
2361
2362 /* Getting values from cgen_fields is handled by a collection of functions.
2363    They are distinguished by the type of the VALUE argument they return.
2364    TODO: floating point, inlining support, remove cases where result type
2365    not appropriate.  */
2366
2367 int
2368 fr30_cgen_get_int_operand (opindex, fields)
2369      int opindex;
2370      const CGEN_FIELDS * fields;
2371 {
2372   int value;
2373
2374   switch (opindex)
2375     {
2376     case FR30_OPERAND_RI :
2377       value = fields->f_Ri;
2378       break;
2379     case FR30_OPERAND_RJ :
2380       value = fields->f_Rj;
2381       break;
2382     case FR30_OPERAND_RIC :
2383       value = fields->f_Ric;
2384       break;
2385     case FR30_OPERAND_RJC :
2386       value = fields->f_Rjc;
2387       break;
2388     case FR30_OPERAND_CRI :
2389       value = fields->f_CRi;
2390       break;
2391     case FR30_OPERAND_CRJ :
2392       value = fields->f_CRj;
2393       break;
2394     case FR30_OPERAND_RS1 :
2395       value = fields->f_Rs1;
2396       break;
2397     case FR30_OPERAND_RS2 :
2398       value = fields->f_Rs2;
2399       break;
2400     case FR30_OPERAND_R13 :
2401       value = fields->f_nil;
2402       break;
2403     case FR30_OPERAND_R14 :
2404       value = fields->f_nil;
2405       break;
2406     case FR30_OPERAND_R15 :
2407       value = fields->f_nil;
2408       break;
2409     case FR30_OPERAND_PS :
2410       value = fields->f_nil;
2411       break;
2412     case FR30_OPERAND_U4 :
2413       value = fields->f_u4;
2414       break;
2415     case FR30_OPERAND_U4C :
2416       value = fields->f_u4c;
2417       break;
2418     case FR30_OPERAND_M4 :
2419       value = fields->f_m4;
2420       break;
2421     case FR30_OPERAND_U8 :
2422       value = fields->f_u8;
2423       break;
2424     case FR30_OPERAND_I8 :
2425       value = fields->f_i8;
2426       break;
2427     case FR30_OPERAND_UDISP6 :
2428       value = fields->f_udisp6;
2429       break;
2430     case FR30_OPERAND_DISP8 :
2431       value = fields->f_disp8;
2432       break;
2433     case FR30_OPERAND_DISP9 :
2434       value = fields->f_disp9;
2435       break;
2436     case FR30_OPERAND_DISP10 :
2437       value = fields->f_disp10;
2438       break;
2439     case FR30_OPERAND_S10 :
2440       value = fields->f_s10;
2441       break;
2442     case FR30_OPERAND_U10 :
2443       value = fields->f_u10;
2444       break;
2445     case FR30_OPERAND_I32 :
2446       value = fields->f_i32;
2447       break;
2448     case FR30_OPERAND_DIR8 :
2449       value = fields->f_dir8;
2450       break;
2451     case FR30_OPERAND_DIR9 :
2452       value = fields->f_dir9;
2453       break;
2454     case FR30_OPERAND_DIR10 :
2455       value = fields->f_dir10;
2456       break;
2457     case FR30_OPERAND_LABEL9 :
2458       value = fields->f_rel9;
2459       break;
2460     case FR30_OPERAND_LABEL12 :
2461       value = fields->f_rel12;
2462       break;
2463     case FR30_OPERAND_REGLIST_LOW :
2464       value = fields->f_reglist_low;
2465       break;
2466     case FR30_OPERAND_REGLIST_HI :
2467       value = fields->f_reglist_hi;
2468       break;
2469     case FR30_OPERAND_CC :
2470       value = fields->f_cc;
2471       break;
2472     case FR30_OPERAND_CCC :
2473       value = fields->f_ccc;
2474       break;
2475
2476     default :
2477       /* xgettext:c-format */
2478       fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2479                        opindex);
2480       abort ();
2481   }
2482
2483   return value;
2484 }
2485
2486 bfd_vma
2487 fr30_cgen_get_vma_operand (opindex, fields)
2488      int opindex;
2489      const CGEN_FIELDS * fields;
2490 {
2491   bfd_vma value;
2492
2493   switch (opindex)
2494     {
2495     case FR30_OPERAND_RI :
2496       value = fields->f_Ri;
2497       break;
2498     case FR30_OPERAND_RJ :
2499       value = fields->f_Rj;
2500       break;
2501     case FR30_OPERAND_RIC :
2502       value = fields->f_Ric;
2503       break;
2504     case FR30_OPERAND_RJC :
2505       value = fields->f_Rjc;
2506       break;
2507     case FR30_OPERAND_CRI :
2508       value = fields->f_CRi;
2509       break;
2510     case FR30_OPERAND_CRJ :
2511       value = fields->f_CRj;
2512       break;
2513     case FR30_OPERAND_RS1 :
2514       value = fields->f_Rs1;
2515       break;
2516     case FR30_OPERAND_RS2 :
2517       value = fields->f_Rs2;
2518       break;
2519     case FR30_OPERAND_R13 :
2520       value = fields->f_nil;
2521       break;
2522     case FR30_OPERAND_R14 :
2523       value = fields->f_nil;
2524       break;
2525     case FR30_OPERAND_R15 :
2526       value = fields->f_nil;
2527       break;
2528     case FR30_OPERAND_PS :
2529       value = fields->f_nil;
2530       break;
2531     case FR30_OPERAND_U4 :
2532       value = fields->f_u4;
2533       break;
2534     case FR30_OPERAND_U4C :
2535       value = fields->f_u4c;
2536       break;
2537     case FR30_OPERAND_M4 :
2538       value = fields->f_m4;
2539       break;
2540     case FR30_OPERAND_U8 :
2541       value = fields->f_u8;
2542       break;
2543     case FR30_OPERAND_I8 :
2544       value = fields->f_i8;
2545       break;
2546     case FR30_OPERAND_UDISP6 :
2547       value = fields->f_udisp6;
2548       break;
2549     case FR30_OPERAND_DISP8 :
2550       value = fields->f_disp8;
2551       break;
2552     case FR30_OPERAND_DISP9 :
2553       value = fields->f_disp9;
2554       break;
2555     case FR30_OPERAND_DISP10 :
2556       value = fields->f_disp10;
2557       break;
2558     case FR30_OPERAND_S10 :
2559       value = fields->f_s10;
2560       break;
2561     case FR30_OPERAND_U10 :
2562       value = fields->f_u10;
2563       break;
2564     case FR30_OPERAND_I32 :
2565       value = fields->f_i32;
2566       break;
2567     case FR30_OPERAND_DIR8 :
2568       value = fields->f_dir8;
2569       break;
2570     case FR30_OPERAND_DIR9 :
2571       value = fields->f_dir9;
2572       break;
2573     case FR30_OPERAND_DIR10 :
2574       value = fields->f_dir10;
2575       break;
2576     case FR30_OPERAND_LABEL9 :
2577       value = fields->f_rel9;
2578       break;
2579     case FR30_OPERAND_LABEL12 :
2580       value = fields->f_rel12;
2581       break;
2582     case FR30_OPERAND_REGLIST_LOW :
2583       value = fields->f_reglist_low;
2584       break;
2585     case FR30_OPERAND_REGLIST_HI :
2586       value = fields->f_reglist_hi;
2587       break;
2588     case FR30_OPERAND_CC :
2589       value = fields->f_cc;
2590       break;
2591     case FR30_OPERAND_CCC :
2592       value = fields->f_ccc;
2593       break;
2594
2595     default :
2596       /* xgettext:c-format */
2597       fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
2598                        opindex);
2599       abort ();
2600   }
2601
2602   return value;
2603 }
2604
2605 /* Stuffing values in cgen_fields is handled by a collection of functions.
2606    They are distinguished by the type of the VALUE argument they accept.
2607    TODO: floating point, inlining support, remove cases where argument type
2608    not appropriate.  */
2609
2610 void
2611 fr30_cgen_set_int_operand (opindex, fields, value)
2612      int opindex;
2613      CGEN_FIELDS * fields;
2614      int value;
2615 {
2616   switch (opindex)
2617     {
2618     case FR30_OPERAND_RI :
2619       fields->f_Ri = value;
2620       break;
2621     case FR30_OPERAND_RJ :
2622       fields->f_Rj = value;
2623       break;
2624     case FR30_OPERAND_RIC :
2625       fields->f_Ric = value;
2626       break;
2627     case FR30_OPERAND_RJC :
2628       fields->f_Rjc = value;
2629       break;
2630     case FR30_OPERAND_CRI :
2631       fields->f_CRi = value;
2632       break;
2633     case FR30_OPERAND_CRJ :
2634       fields->f_CRj = value;
2635       break;
2636     case FR30_OPERAND_RS1 :
2637       fields->f_Rs1 = value;
2638       break;
2639     case FR30_OPERAND_RS2 :
2640       fields->f_Rs2 = value;
2641       break;
2642     case FR30_OPERAND_R13 :
2643       fields->f_nil = value;
2644       break;
2645     case FR30_OPERAND_R14 :
2646       fields->f_nil = value;
2647       break;
2648     case FR30_OPERAND_R15 :
2649       fields->f_nil = value;
2650       break;
2651     case FR30_OPERAND_PS :
2652       fields->f_nil = value;
2653       break;
2654     case FR30_OPERAND_U4 :
2655       fields->f_u4 = value;
2656       break;
2657     case FR30_OPERAND_U4C :
2658       fields->f_u4c = value;
2659       break;
2660     case FR30_OPERAND_M4 :
2661       fields->f_m4 = value;
2662       break;
2663     case FR30_OPERAND_U8 :
2664       fields->f_u8 = value;
2665       break;
2666     case FR30_OPERAND_I8 :
2667       fields->f_i8 = value;
2668       break;
2669     case FR30_OPERAND_UDISP6 :
2670       fields->f_udisp6 = value;
2671       break;
2672     case FR30_OPERAND_DISP8 :
2673       fields->f_disp8 = value;
2674       break;
2675     case FR30_OPERAND_DISP9 :
2676       fields->f_disp9 = value;
2677       break;
2678     case FR30_OPERAND_DISP10 :
2679       fields->f_disp10 = value;
2680       break;
2681     case FR30_OPERAND_S10 :
2682       fields->f_s10 = value;
2683       break;
2684     case FR30_OPERAND_U10 :
2685       fields->f_u10 = value;
2686       break;
2687     case FR30_OPERAND_I32 :
2688       fields->f_i32 = value;
2689       break;
2690     case FR30_OPERAND_DIR8 :
2691       fields->f_dir8 = value;
2692       break;
2693     case FR30_OPERAND_DIR9 :
2694       fields->f_dir9 = value;
2695       break;
2696     case FR30_OPERAND_DIR10 :
2697       fields->f_dir10 = value;
2698       break;
2699     case FR30_OPERAND_LABEL9 :
2700       fields->f_rel9 = value;
2701       break;
2702     case FR30_OPERAND_LABEL12 :
2703       fields->f_rel12 = value;
2704       break;
2705     case FR30_OPERAND_REGLIST_LOW :
2706       fields->f_reglist_low = value;
2707       break;
2708     case FR30_OPERAND_REGLIST_HI :
2709       fields->f_reglist_hi = value;
2710       break;
2711     case FR30_OPERAND_CC :
2712       fields->f_cc = value;
2713       break;
2714     case FR30_OPERAND_CCC :
2715       fields->f_ccc = value;
2716       break;
2717
2718     default :
2719       /* xgettext:c-format */
2720       fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2721                        opindex);
2722       abort ();
2723   }
2724 }
2725
2726 void
2727 fr30_cgen_set_vma_operand (opindex, fields, value)
2728      int opindex;
2729      CGEN_FIELDS * fields;
2730      bfd_vma value;
2731 {
2732   switch (opindex)
2733     {
2734     case FR30_OPERAND_RI :
2735       fields->f_Ri = value;
2736       break;
2737     case FR30_OPERAND_RJ :
2738       fields->f_Rj = value;
2739       break;
2740     case FR30_OPERAND_RIC :
2741       fields->f_Ric = value;
2742       break;
2743     case FR30_OPERAND_RJC :
2744       fields->f_Rjc = value;
2745       break;
2746     case FR30_OPERAND_CRI :
2747       fields->f_CRi = value;
2748       break;
2749     case FR30_OPERAND_CRJ :
2750       fields->f_CRj = value;
2751       break;
2752     case FR30_OPERAND_RS1 :
2753       fields->f_Rs1 = value;
2754       break;
2755     case FR30_OPERAND_RS2 :
2756       fields->f_Rs2 = value;
2757       break;
2758     case FR30_OPERAND_R13 :
2759       fields->f_nil = value;
2760       break;
2761     case FR30_OPERAND_R14 :
2762       fields->f_nil = value;
2763       break;
2764     case FR30_OPERAND_R15 :
2765       fields->f_nil = value;
2766       break;
2767     case FR30_OPERAND_PS :
2768       fields->f_nil = value;
2769       break;
2770     case FR30_OPERAND_U4 :
2771       fields->f_u4 = value;
2772       break;
2773     case FR30_OPERAND_U4C :
2774       fields->f_u4c = value;
2775       break;
2776     case FR30_OPERAND_M4 :
2777       fields->f_m4 = value;
2778       break;
2779     case FR30_OPERAND_U8 :
2780       fields->f_u8 = value;
2781       break;
2782     case FR30_OPERAND_I8 :
2783       fields->f_i8 = value;
2784       break;
2785     case FR30_OPERAND_UDISP6 :
2786       fields->f_udisp6 = value;
2787       break;
2788     case FR30_OPERAND_DISP8 :
2789       fields->f_disp8 = value;
2790       break;
2791     case FR30_OPERAND_DISP9 :
2792       fields->f_disp9 = value;
2793       break;
2794     case FR30_OPERAND_DISP10 :
2795       fields->f_disp10 = value;
2796       break;
2797     case FR30_OPERAND_S10 :
2798       fields->f_s10 = value;
2799       break;
2800     case FR30_OPERAND_U10 :
2801       fields->f_u10 = value;
2802       break;
2803     case FR30_OPERAND_I32 :
2804       fields->f_i32 = value;
2805       break;
2806     case FR30_OPERAND_DIR8 :
2807       fields->f_dir8 = value;
2808       break;
2809     case FR30_OPERAND_DIR9 :
2810       fields->f_dir9 = value;
2811       break;
2812     case FR30_OPERAND_DIR10 :
2813       fields->f_dir10 = value;
2814       break;
2815     case FR30_OPERAND_LABEL9 :
2816       fields->f_rel9 = value;
2817       break;
2818     case FR30_OPERAND_LABEL12 :
2819       fields->f_rel12 = value;
2820       break;
2821     case FR30_OPERAND_REGLIST_LOW :
2822       fields->f_reglist_low = value;
2823       break;
2824     case FR30_OPERAND_REGLIST_HI :
2825       fields->f_reglist_hi = value;
2826       break;
2827     case FR30_OPERAND_CC :
2828       fields->f_cc = value;
2829       break;
2830     case FR30_OPERAND_CCC :
2831       fields->f_ccc = value;
2832       break;
2833
2834     default :
2835       /* xgettext:c-format */
2836       fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
2837                        opindex);
2838       abort ();
2839   }
2840 }
2841