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Tue Dec 8 13:12:44 1998 Dave Brolley <brolley@cygnus.com>
[deliverable/binutils-gdb.git] / opcodes / fr30-opc.c
1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 THIS FILE IS USED TO GENERATE fr30-opc.c.
5
6 Copyright (C) 1998 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include "ansidecl.h"
27 #include "libiberty.h"
28 #include "bfd.h"
29 #include "symcat.h"
30 #include "fr30-opc.h"
31 #include "opintl.h"
32
33 /* Used by the ifield rtx function. */
34 #define FLD(f) (fields->f)
35
36 /* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
38
39 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
40 static unsigned int asm_hash_insn PARAMS ((const char *));
41 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
42 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
43
44 /* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
51
52 The result is a pointer to the insn table entry, or NULL if the instruction
53 wasn't recognized. */
54
55 const CGEN_INSN *
56 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
57 CGEN_OPCODE_DESC od;
58 const CGEN_INSN *insn;
59 CGEN_INSN_BYTES insn_value;
60 int length;
61 CGEN_FIELDS *fields;
62 int alias_p;
63 {
64 unsigned char buf[CGEN_MAX_INSN_SIZE];
65 unsigned char *bufp;
66 CGEN_INSN_INT base_insn;
67 #if CGEN_INT_INSN_P
68 CGEN_EXTRACT_INFO *info = NULL;
69 #else
70 CGEN_EXTRACT_INFO ex_info;
71 CGEN_EXTRACT_INFO *info = &ex_info;
72 #endif
73
74 #if CGEN_INT_INSN_P
75 cgen_put_insn_value (od, buf, length, insn_value);
76 bufp = buf;
77 base_insn = insn_value; /*???*/
78 #else
79 ex_info.dis_info = NULL;
80 ex_info.insn_bytes = insn_value;
81 ex_info.valid = -1;
82 base_insn = cgen_get_insn_value (od, buf, length);
83 bufp = insn_value;
84 #endif
85
86 if (!insn)
87 {
88 const CGEN_INSN_LIST *insn_list;
89
90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
92
93 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
94 while (insn_list != NULL)
95 {
96 insn = insn_list->insn;
97
98 if (alias_p
99 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
100 {
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
103 extract handler. */
104 if ((base_insn & CGEN_INSN_BASE_MASK (insn))
105 == CGEN_INSN_BASE_VALUE (insn))
106 {
107 /* ??? 0 is passed for `pc' */
108 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
109 base_insn, fields,
110 (bfd_vma) 0);
111 if (elength > 0)
112 {
113 /* sanity check */
114 if (length != 0 && length != elength)
115 abort ();
116 return insn;
117 }
118 }
119 }
120
121 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
122 }
123 }
124 else
125 {
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
127 if (! alias_p
128 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
129 abort ();
130 /* Sanity check: length must be correct. */
131 if (length != CGEN_INSN_BITSIZE (insn))
132 abort ();
133
134 /* ??? 0 is passed for `pc' */
135 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
136 (bfd_vma) 0);
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
139 if (length == 0)
140 abort ();
141 return insn;
142 }
143
144 return NULL;
145 }
146
147 /* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
149 in. */
150
151 void
152 fr30_cgen_get_insn_operands (od, insn, fields, indices)
153 CGEN_OPCODE_DESC od;
154 const CGEN_INSN * insn;
155 const CGEN_FIELDS * fields;
156 int *indices;
157 {
158 const CGEN_OPERAND_INSTANCE *opinst;
159 int i;
160
161 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
162 opinst != NULL
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
164 ++i, ++opinst)
165 {
166 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
167 if (op == NULL)
168 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
169 else
170 indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
171 fields);
172 }
173 }
174
175 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
176 isn't known.
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 fr30_cgen_lookup_insn unchanged.
179
180 The result is the insn table entry or NULL if the instruction wasn't
181 recognized. */
182
183 const CGEN_INSN *
184 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
185 CGEN_OPCODE_DESC od;
186 const CGEN_INSN *insn;
187 CGEN_INSN_BYTES insn_value;
188 int length;
189 int *indices;
190 {
191 CGEN_FIELDS fields;
192
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
196 insn != NULL);
197 if (! insn)
198 return NULL;
199
200 fr30_cgen_get_insn_operands (od, insn, &fields, indices);
201 return insn;
202 }
203 /* Attributes. */
204
205 static const CGEN_ATTR_ENTRY MACH_attr[] =
206 {
207 { "base", MACH_BASE },
208 { "fr30", MACH_FR30 },
209 { "max", MACH_MAX },
210 { 0, 0 }
211 };
212
213 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
214 {
215 { "CACHE-ADDR", NULL },
216 { "FUN-ACCESS", NULL },
217 { "PC", NULL },
218 { "PROFILE", NULL },
219 { 0, 0 }
220 };
221
222 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
223 {
224 { "ABS-ADDR", NULL },
225 { "HASH-PREFIX", NULL },
226 { "NEGATIVE", NULL },
227 { "PCREL-ADDR", NULL },
228 { "RELAX", NULL },
229 { "SEM-ONLY", NULL },
230 { "SIGN-OPT", NULL },
231 { "SIGNED", NULL },
232 { "UNSIGNED", NULL },
233 { "VIRTUAL", NULL },
234 { 0, 0 }
235 };
236
237 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
238 {
239 { "ALIAS", NULL },
240 { "COND-CTI", NULL },
241 { "DELAY-SLOT", NULL },
242 { "NO-DIS", NULL },
243 { "NOT-IN-DELAY-SLOT", NULL },
244 { "RELAX", NULL },
245 { "RELAXABLE", NULL },
246 { "SKIP-CTI", NULL },
247 { "UNCOND-CTI", NULL },
248 { "VIRTUAL", NULL },
249 { 0, 0 }
250 };
251
252 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
253 {
254 { "ac", 13 },
255 { "fp", 14 },
256 { "sp", 15 },
257 { "r0", 0 },
258 { "r1", 1 },
259 { "r2", 2 },
260 { "r3", 3 },
261 { "r4", 4 },
262 { "r5", 5 },
263 { "r6", 6 },
264 { "r7", 7 },
265 { "r8", 8 },
266 { "r9", 9 },
267 { "r10", 10 },
268 { "r11", 11 },
269 { "r12", 12 },
270 { "r13", 13 },
271 { "r14", 14 },
272 { "r15", 15 }
273 };
274
275 CGEN_KEYWORD fr30_cgen_opval_h_gr =
276 {
277 & fr30_cgen_opval_h_gr_entries[0],
278 19
279 };
280
281 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
282 {
283 { "cr0", 0 },
284 { "cr1", 1 },
285 { "cr2", 2 },
286 { "cr3", 3 },
287 { "cr4", 4 },
288 { "cr5", 5 },
289 { "cr6", 6 },
290 { "cr7", 7 },
291 { "cr8", 8 },
292 { "cr9", 9 },
293 { "cr10", 10 },
294 { "cr11", 11 },
295 { "cr12", 12 },
296 { "cr13", 13 },
297 { "cr14", 14 },
298 { "cr15", 15 }
299 };
300
301 CGEN_KEYWORD fr30_cgen_opval_h_cr =
302 {
303 & fr30_cgen_opval_h_cr_entries[0],
304 16
305 };
306
307 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
308 {
309 { "tbr", 0 },
310 { "rp", 1 },
311 { "ssp", 2 },
312 { "usp", 3 },
313 { "mdh", 4 },
314 { "mdl", 5 }
315 };
316
317 CGEN_KEYWORD fr30_cgen_opval_h_dr =
318 {
319 & fr30_cgen_opval_h_dr_entries[0],
320 6
321 };
322
323 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
324 {
325 { "ps", 0 }
326 };
327
328 CGEN_KEYWORD fr30_cgen_opval_h_ps =
329 {
330 & fr30_cgen_opval_h_ps_entries[0],
331 1
332 };
333
334 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
335 {
336 { "r13", 0 }
337 };
338
339 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
340 {
341 & fr30_cgen_opval_h_r13_entries[0],
342 1
343 };
344
345 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
346 {
347 { "r14", 0 }
348 };
349
350 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
351 {
352 & fr30_cgen_opval_h_r14_entries[0],
353 1
354 };
355
356 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
357 {
358 { "r15", 0 }
359 };
360
361 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
362 {
363 & fr30_cgen_opval_h_r15_entries[0],
364 1
365 };
366
367
368 /* The hardware table. */
369
370 #define HW_ENT(n) fr30_cgen_hw_entries[n]
371 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
372 {
373 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
374 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
375 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
376 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
377 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
378 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
379 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
380 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0, { 0 } } },
381 { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
382 { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
383 { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
384 { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
385 { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
386 { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
387 { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
388 { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
389 { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
390 { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
391 { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
392 { HW_H_CCR, & HW_ENT (HW_H_CCR + 1), "h-ccr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
393 { HW_H_SCR, & HW_ENT (HW_H_SCR + 1), "h-scr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
394 { HW_H_ILM, & HW_ENT (HW_H_ILM + 1), "h-ilm", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
395 { 0 }
396 };
397
398 /* The instruction field table. */
399
400 static const CGEN_IFLD fr30_cgen_ifld_table[] =
401 {
402 { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, 0, { 0 } } },
403 { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
404 { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
405 { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
406 { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
407 { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
408 { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
409 { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
410 { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
411 { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
412 { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
413 { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
414 { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
415 { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
416 { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
417 { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
418 { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
419 { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
420 { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
421 { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
422 { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
423 { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
424 { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
425 { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
426 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
427 { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
428 { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
429 { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
430 { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
431 { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
432 { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
433 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
434 { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
435 { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
436 { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
437 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
438 { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
439 { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
440 { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
441 { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
442 { 0 }
443 };
444
445 /* The operand table. */
446
447 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
448 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
449
450 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
451 {
452 /* pc: program counter */
453 { "pc", & HW_ENT (HW_H_PC), 0, 0,
454 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
455 /* Ri: destination register */
456 { "Ri", & HW_ENT (HW_H_GR), 12, 4,
457 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
458 /* Rj: source register */
459 { "Rj", & HW_ENT (HW_H_GR), 8, 4,
460 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
461 /* Ric: target register coproc insn */
462 { "Ric", & HW_ENT (HW_H_GR), 12, 4,
463 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
464 /* Rjc: source register coproc insn */
465 { "Rjc", & HW_ENT (HW_H_GR), 8, 4,
466 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
467 /* CRi: coprocessor register */
468 { "CRi", & HW_ENT (HW_H_CR), 12, 4,
469 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
470 /* CRj: coprocessor register */
471 { "CRj", & HW_ENT (HW_H_CR), 8, 4,
472 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
473 /* Rs1: dedicated register */
474 { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
475 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
476 /* Rs2: dedicated register */
477 { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
478 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
479 /* R13: General Register 13 */
480 { "R13", & HW_ENT (HW_H_R13), 0, 0,
481 { 0, 0, { 0 } } },
482 /* R14: General Register 14 */
483 { "R14", & HW_ENT (HW_H_R14), 0, 0,
484 { 0, 0, { 0 } } },
485 /* R15: General Register 15 */
486 { "R15", & HW_ENT (HW_H_R15), 0, 0,
487 { 0, 0, { 0 } } },
488 /* ps: Program Status register */
489 { "ps", & HW_ENT (HW_H_PS), 0, 0,
490 { 0, 0, { 0 } } },
491 /* u4: 4 bit unsigned immediate */
492 { "u4", & HW_ENT (HW_H_UINT), 8, 4,
493 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
494 /* u4c: 4 bit unsigned immediate */
495 { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
496 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
497 /* u8: 8 bit unsigned immediate */
498 { "u8", & HW_ENT (HW_H_UINT), 8, 8,
499 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
500 /* i8: 8 bit unsigned immediate */
501 { "i8", & HW_ENT (HW_H_UINT), 4, 8,
502 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
503 /* udisp6: 6 bit unsigned immediate */
504 { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
505 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
506 /* disp8: 8 bit signed immediate */
507 { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
508 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
509 /* disp9: 9 bit signed immediate */
510 { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
511 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
512 /* disp10: 10 bit signed immediate */
513 { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
514 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
515 /* s10: 10 bit signed immediate */
516 { "s10", & HW_ENT (HW_H_SINT), 8, 8,
517 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
518 /* u10: 10 bit unsigned immediate */
519 { "u10", & HW_ENT (HW_H_UINT), 8, 8,
520 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
521 /* i32: 32 bit immediate */
522 { "i32", & HW_ENT (HW_H_UINT), 0, 32,
523 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
524 /* m4: 4 bit negative immediate */
525 { "m4", & HW_ENT (HW_H_SINT), 8, 4,
526 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
527 /* i20: 20 bit immediate */
528 { "i20", & HW_ENT (HW_H_UINT), 0, 20,
529 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), { 0 } } },
530 /* dir8: 8 bit direct address */
531 { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
532 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
533 /* dir9: 9 bit direct address */
534 { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
535 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
536 /* dir10: 10 bit direct address */
537 { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
538 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
539 /* label9: 9 bit pc relative address */
540 { "label9", & HW_ENT (HW_H_IADDR), 8, 8,
541 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
542 /* label12: 12 bit pc relative address */
543 { "label12", & HW_ENT (HW_H_IADDR), 5, 11,
544 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
545 /* reglist_low_ld: 8 bit register mask for ldm */
546 { "reglist_low_ld", & HW_ENT (HW_H_UINT), 8, 8,
547 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
548 /* reglist_hi_ld: 8 bit register mask for ldm */
549 { "reglist_hi_ld", & HW_ENT (HW_H_UINT), 8, 8,
550 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
551 /* reglist_low_st: 8 bit register mask for ldm */
552 { "reglist_low_st", & HW_ENT (HW_H_UINT), 8, 8,
553 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
554 /* reglist_hi_st: 8 bit register mask for ldm */
555 { "reglist_hi_st", & HW_ENT (HW_H_UINT), 8, 8,
556 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
557 /* cc: condition codes */
558 { "cc", & HW_ENT (HW_H_UINT), 4, 4,
559 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
560 /* ccc: coprocessor calc */
561 { "ccc", & HW_ENT (HW_H_UINT), 0, 8,
562 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
563 /* nbit: negative bit */
564 { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
565 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
566 /* vbit: overflow bit */
567 { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
568 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
569 /* zbit: zero bit */
570 { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
571 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
572 /* cbit: carry bit */
573 { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
574 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
575 /* ibit: interrupt bit */
576 { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
577 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
578 /* sbit: stack bit */
579 { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
580 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
581 /* ccr: condition code bits */
582 { "ccr", & HW_ENT (HW_H_CCR), 0, 0,
583 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
584 /* scr: system condition bits */
585 { "scr", & HW_ENT (HW_H_SCR), 0, 0,
586 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
587 /* ilm: condition code bits */
588 { "ilm", & HW_ENT (HW_H_ILM), 0, 0,
589 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
590 };
591
592 /* Operand references. */
593
594 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
595 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
596 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
597
598 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
599 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
600 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
601 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
602 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
603 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
604 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
605 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
606 { 0 }
607 };
608
609 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
610 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
611 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
612 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
613 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
614 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
615 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
616 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
617 { 0 }
618 };
619
620 static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
621 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
622 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
623 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
624 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
625 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
626 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
627 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
628 { 0 }
629 };
630
631 static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
632 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
633 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
634 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
635 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
636 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
637 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
638 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
639 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
640 { 0 }
641 };
642
643 static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
644 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
645 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
646 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
647 { 0 }
648 };
649
650 static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
651 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
652 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
653 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
654 { 0 }
655 };
656
657 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
658 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
659 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
660 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
661 { 0 }
662 };
663
664 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
665 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
666 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
667 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
668 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
669 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
670 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
671 { 0 }
672 };
673
674 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
675 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
676 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
677 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
678 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
679 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
680 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
681 { 0 }
682 };
683
684 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
685 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
686 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
687 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
688 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
689 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
690 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
691 { 0 }
692 };
693
694 static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
695 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
696 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
697 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
698 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
699 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
700 { 0 }
701 };
702
703 static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
704 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
705 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
706 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
707 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
708 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
709 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
710 { 0 }
711 };
712
713 static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
714 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
715 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
716 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
717 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
718 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
719 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
720 { 0 }
721 };
722
723 static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
724 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
725 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
726 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
727 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
728 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
729 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
730 { 0 }
731 };
732
733 static const CGEN_OPERAND_INSTANCE fmt_bandl_ops[] = {
734 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
735 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
736 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
737 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
738 { 0 }
739 };
740
741 static const CGEN_OPERAND_INSTANCE fmt_btstl_ops[] = {
742 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
743 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
744 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
745 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
746 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
747 { 0 }
748 };
749
750 static const CGEN_OPERAND_INSTANCE fmt_mul_ops[] = {
751 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
752 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
753 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
754 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
755 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
756 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
757 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
758 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
759 { 0 }
760 };
761
762 static const CGEN_OPERAND_INSTANCE fmt_mulu_ops[] = {
763 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
764 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
765 { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
766 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
767 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
768 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
769 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
770 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
771 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
772 { 0 }
773 };
774
775 static const CGEN_OPERAND_INSTANCE fmt_mulh_ops[] = {
776 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
777 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
778 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
779 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
780 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
781 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
782 { 0 }
783 };
784
785 static const CGEN_OPERAND_INSTANCE fmt_lsl_ops[] = {
786 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
787 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
788 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
789 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
790 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
791 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
792 { 0 }
793 };
794
795 static const CGEN_OPERAND_INSTANCE fmt_lsli_ops[] = {
796 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
797 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
798 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
799 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
800 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
801 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
802 { 0 }
803 };
804
805 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
806 { INPUT, "i8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I8), 0, 0 },
807 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
808 { 0 }
809 };
810
811 static const CGEN_OPERAND_INSTANCE fmt_ldi20_ops[] = {
812 { INPUT, "i20", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I20), 0, 0 },
813 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
814 { 0 }
815 };
816
817 static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
818 { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
819 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
820 { 0 }
821 };
822
823 static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
824 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
825 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
826 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
827 { 0 }
828 };
829
830 static const CGEN_OPERAND_INSTANCE fmt_lduh_ops[] = {
831 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
832 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
833 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
834 { 0 }
835 };
836
837 static const CGEN_OPERAND_INSTANCE fmt_ldub_ops[] = {
838 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
839 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
840 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
841 { 0 }
842 };
843
844 static const CGEN_OPERAND_INSTANCE fmt_ldr13_ops[] = {
845 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
846 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
847 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
848 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
849 { 0 }
850 };
851
852 static const CGEN_OPERAND_INSTANCE fmt_ldr13uh_ops[] = {
853 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
854 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
855 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
856 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
857 { 0 }
858 };
859
860 static const CGEN_OPERAND_INSTANCE fmt_ldr13ub_ops[] = {
861 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
862 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
863 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
864 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
865 { 0 }
866 };
867
868 static const CGEN_OPERAND_INSTANCE fmt_ldr14_ops[] = {
869 { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
870 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
871 { INPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
872 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
873 { 0 }
874 };
875
876 static const CGEN_OPERAND_INSTANCE fmt_ldr14uh_ops[] = {
877 { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
878 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
879 { INPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
880 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
881 { 0 }
882 };
883
884 static const CGEN_OPERAND_INSTANCE fmt_ldr14ub_ops[] = {
885 { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
886 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
887 { INPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
888 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
889 { 0 }
890 };
891
892 static const CGEN_OPERAND_INSTANCE fmt_ldr15_ops[] = {
893 { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
894 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
895 { INPUT, "h_memory_add__VM_udisp6_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
896 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
897 { 0 }
898 };
899
900 static const CGEN_OPERAND_INSTANCE fmt_ldr15gr_ops[] = {
901 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
902 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
903 { INPUT, "f_Ri", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
904 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
905 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
906 { 0 }
907 };
908
909 static const CGEN_OPERAND_INSTANCE fmt_ldr15dr_ops[] = {
910 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
911 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
912 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
913 { OUTPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
914 { 0 }
915 };
916
917 static const CGEN_OPERAND_INSTANCE fmt_ldr15ps_ops[] = {
918 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
919 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
920 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
921 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
922 { 0 }
923 };
924
925 static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
926 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
927 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
928 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
929 { 0 }
930 };
931
932 static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
933 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
934 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
935 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
936 { 0 }
937 };
938
939 static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
940 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
941 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
942 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
943 { 0 }
944 };
945
946 static const CGEN_OPERAND_INSTANCE fmt_str13_ops[] = {
947 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
948 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
949 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
950 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
951 { 0 }
952 };
953
954 static const CGEN_OPERAND_INSTANCE fmt_str13h_ops[] = {
955 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
956 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
957 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
958 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
959 { 0 }
960 };
961
962 static const CGEN_OPERAND_INSTANCE fmt_str13b_ops[] = {
963 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
964 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
965 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
966 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
967 { 0 }
968 };
969
970 static const CGEN_OPERAND_INSTANCE fmt_str14_ops[] = {
971 { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
972 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
973 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
974 { OUTPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
975 { 0 }
976 };
977
978 static const CGEN_OPERAND_INSTANCE fmt_str14h_ops[] = {
979 { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
980 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
981 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
982 { OUTPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
983 { 0 }
984 };
985
986 static const CGEN_OPERAND_INSTANCE fmt_str14b_ops[] = {
987 { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
988 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
989 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
990 { OUTPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
991 { 0 }
992 };
993
994 static const CGEN_OPERAND_INSTANCE fmt_str15_ops[] = {
995 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
996 { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
997 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
998 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_15_udisp6", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
999 { 0 }
1000 };
1001
1002 static const CGEN_OPERAND_INSTANCE fmt_str15gr_ops[] = {
1003 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1004 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1005 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1006 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1007 { 0 }
1008 };
1009
1010 static const CGEN_OPERAND_INSTANCE fmt_str15dr_ops[] = {
1011 { INPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
1012 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1013 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1014 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1015 { 0 }
1016 };
1017
1018 static const CGEN_OPERAND_INSTANCE fmt_str15ps_ops[] = {
1019 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1020 { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1021 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1022 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1023 { 0 }
1024 };
1025
1026 static const CGEN_OPERAND_INSTANCE fmt_mov_ops[] = {
1027 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1028 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1029 { 0 }
1030 };
1031
1032 static const CGEN_OPERAND_INSTANCE fmt_movdr_ops[] = {
1033 { INPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
1034 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1035 { 0 }
1036 };
1037
1038 static const CGEN_OPERAND_INSTANCE fmt_movps_ops[] = {
1039 { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1040 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1041 { 0 }
1042 };
1043
1044 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
1045 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1046 { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
1047 { 0 }
1048 };
1049
1050 static const CGEN_OPERAND_INSTANCE fmt_mov2ps_ops[] = {
1051 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1052 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1053 { 0 }
1054 };
1055
1056 static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
1057 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1058 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1059 { 0 }
1060 };
1061
1062 static const CGEN_OPERAND_INSTANCE fmt_callr_ops[] = {
1063 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1064 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1065 { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1066 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1067 { 0 }
1068 };
1069
1070 static const CGEN_OPERAND_INSTANCE fmt_call_ops[] = {
1071 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1072 { INPUT, "label12", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL12), 0, 0 },
1073 { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1074 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1075 { 0 }
1076 };
1077
1078 static const CGEN_OPERAND_INSTANCE fmt_ret_ops[] = {
1079 { INPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1080 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1081 { 0 }
1082 };
1083
1084 static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
1085 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1086 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
1087 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, 0 },
1088 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
1089 { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
1090 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1091 { 0 }
1092 };
1093
1094 static const CGEN_OPERAND_INSTANCE fmt_inte_ops[] = {
1095 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1096 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, 0 },
1097 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
1098 { OUTPUT, "ilm", & HW_ENT (HW_H_ILM), CGEN_MODE_UQI, 0, 0, 0 },
1099 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1100 { 0 }
1101 };
1102
1103 static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
1104 { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
1105 { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
1106 { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
1107 { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
1108 { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
1109 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1110 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
1111 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
1112 { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
1113 { 0 }
1114 };
1115
1116 static const CGEN_OPERAND_INSTANCE fmt_bra_ops[] = {
1117 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1118 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1119 { 0 }
1120 };
1121
1122 static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
1123 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1124 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1125 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1126 { 0 }
1127 };
1128
1129 static const CGEN_OPERAND_INSTANCE fmt_bc_ops[] = {
1130 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
1131 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1132 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1133 { 0 }
1134 };
1135
1136 static const CGEN_OPERAND_INSTANCE fmt_bn_ops[] = {
1137 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1138 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1139 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1140 { 0 }
1141 };
1142
1143 static const CGEN_OPERAND_INSTANCE fmt_bv_ops[] = {
1144 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1145 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1146 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1147 { 0 }
1148 };
1149
1150 static const CGEN_OPERAND_INSTANCE fmt_blt_ops[] = {
1151 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1152 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1153 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1154 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1155 { 0 }
1156 };
1157
1158 static const CGEN_OPERAND_INSTANCE fmt_ble_ops[] = {
1159 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1160 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1161 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1162 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1163 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1164 { 0 }
1165 };
1166
1167 static const CGEN_OPERAND_INSTANCE fmt_bls_ops[] = {
1168 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
1169 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1170 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1171 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1172 { 0 }
1173 };
1174
1175 static const CGEN_OPERAND_INSTANCE fmt_dmovr13_ops[] = {
1176 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1177 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1178 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1179 { 0 }
1180 };
1181
1182 static const CGEN_OPERAND_INSTANCE fmt_dmovr13h_ops[] = {
1183 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1184 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1185 { OUTPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1186 { 0 }
1187 };
1188
1189 static const CGEN_OPERAND_INSTANCE fmt_dmovr13b_ops[] = {
1190 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1191 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1192 { OUTPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1193 { 0 }
1194 };
1195
1196 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pi_ops[] = {
1197 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1198 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1199 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1200 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1201 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1202 { 0 }
1203 };
1204
1205 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pih_ops[] = {
1206 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1207 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1208 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1209 { OUTPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1210 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1211 { 0 }
1212 };
1213
1214 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pib_ops[] = {
1215 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1216 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1217 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1218 { OUTPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1219 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1220 { 0 }
1221 };
1222
1223 static const CGEN_OPERAND_INSTANCE fmt_dmovr15pi_ops[] = {
1224 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1225 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1226 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1227 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1228 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1229 { 0 }
1230 };
1231
1232 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13_ops[] = {
1233 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1234 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1235 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1236 { 0 }
1237 };
1238
1239 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13h_ops[] = {
1240 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1241 { INPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1242 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1243 { 0 }
1244 };
1245
1246 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13b_ops[] = {
1247 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1248 { INPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1249 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1250 { 0 }
1251 };
1252
1253 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pi_ops[] = {
1254 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1255 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1256 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1257 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1258 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1259 { 0 }
1260 };
1261
1262 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pih_ops[] = {
1263 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1264 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1265 { INPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1266 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1267 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1268 { 0 }
1269 };
1270
1271 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pib_ops[] = {
1272 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1273 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1274 { INPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1275 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1276 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1277 { 0 }
1278 };
1279
1280 static const CGEN_OPERAND_INSTANCE fmt_dmov2r15pd_ops[] = {
1281 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1282 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1283 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1284 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1285 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1286 { 0 }
1287 };
1288
1289 static const CGEN_OPERAND_INSTANCE fmt_andccr_ops[] = {
1290 { INPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
1291 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U8), 0, 0 },
1292 { OUTPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
1293 { 0 }
1294 };
1295
1296 static const CGEN_OPERAND_INSTANCE fmt_stilm_ops[] = {
1297 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U8), 0, 0 },
1298 { OUTPUT, "ilm", & HW_ENT (HW_H_ILM), CGEN_MODE_UQI, 0, 0, 0 },
1299 { 0 }
1300 };
1301
1302 static const CGEN_OPERAND_INSTANCE fmt_addsp_ops[] = {
1303 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1304 { INPUT, "s10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (S10), 0, 0 },
1305 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1306 { 0 }
1307 };
1308
1309 static const CGEN_OPERAND_INSTANCE fmt_extsb_ops[] = {
1310 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RI), 0, 0 },
1311 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1312 { 0 }
1313 };
1314
1315 static const CGEN_OPERAND_INSTANCE fmt_extub_ops[] = {
1316 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_UQI, & OP_ENT (RI), 0, 0 },
1317 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1318 { 0 }
1319 };
1320
1321 static const CGEN_OPERAND_INSTANCE fmt_extsh_ops[] = {
1322 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RI), 0, 0 },
1323 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1324 { 0 }
1325 };
1326
1327 static const CGEN_OPERAND_INSTANCE fmt_extuh_ops[] = {
1328 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_UHI, & OP_ENT (RI), 0, 0 },
1329 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1330 { 0 }
1331 };
1332
1333 static const CGEN_OPERAND_INSTANCE fmt_ldm0_ops[] = {
1334 { INPUT, "reglist_low_ld", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_LOW_LD), 0, 0 },
1335 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1336 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1337 { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, COND_REF },
1338 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1339 { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, COND_REF },
1340 { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, COND_REF },
1341 { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, COND_REF },
1342 { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, COND_REF },
1343 { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, COND_REF },
1344 { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, COND_REF },
1345 { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, COND_REF },
1346 { 0 }
1347 };
1348
1349 static const CGEN_OPERAND_INSTANCE fmt_ldm1_ops[] = {
1350 { INPUT, "reglist_hi_ld", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_HI_LD), 0, 0 },
1351 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1352 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1353 { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, COND_REF },
1354 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1355 { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, COND_REF },
1356 { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, COND_REF },
1357 { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, COND_REF },
1358 { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, COND_REF },
1359 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, COND_REF },
1360 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
1361 { 0 }
1362 };
1363
1364 static const CGEN_OPERAND_INSTANCE fmt_stm0_ops[] = {
1365 { INPUT, "reglist_low_st", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_LOW_ST), 0, 0 },
1366 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1367 { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, COND_REF },
1368 { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, COND_REF },
1369 { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, COND_REF },
1370 { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, COND_REF },
1371 { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, COND_REF },
1372 { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, COND_REF },
1373 { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, COND_REF },
1374 { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, COND_REF },
1375 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1376 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1377 { 0 }
1378 };
1379
1380 static const CGEN_OPERAND_INSTANCE fmt_stm1_ops[] = {
1381 { INPUT, "reglist_hi_st", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_HI_ST), 0, 0 },
1382 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1383 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
1384 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, COND_REF },
1385 { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, COND_REF },
1386 { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, COND_REF },
1387 { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, COND_REF },
1388 { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, COND_REF },
1389 { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, COND_REF },
1390 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1391 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1392 { 0 }
1393 };
1394
1395 static const CGEN_OPERAND_INSTANCE fmt_enter_ops[] = {
1396 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1397 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1398 { INPUT, "u10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U10), 0, 0 },
1399 { OUTPUT, "h_memory_tmp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1400 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1401 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1402 { 0 }
1403 };
1404
1405 static const CGEN_OPERAND_INSTANCE fmt_leave_ops[] = {
1406 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1407 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1408 { INPUT, "h_memory_sub__VM_reg__VM_h_gr_15_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1409 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1410 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1411 { 0 }
1412 };
1413
1414 static const CGEN_OPERAND_INSTANCE fmt_xchb_ops[] = {
1415 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1416 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
1417 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
1418 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1419 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
1420 { 0 }
1421 };
1422
1423 #undef INPUT
1424 #undef OUTPUT
1425 #undef COND_REF
1426
1427 /* Instruction formats. */
1428
1429 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
1430
1431 static const CGEN_IFMT fmt_add = {
1432 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1433 };
1434
1435 static const CGEN_IFMT fmt_addi = {
1436 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1437 };
1438
1439 static const CGEN_IFMT fmt_add2 = {
1440 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1441 };
1442
1443 static const CGEN_IFMT fmt_addc = {
1444 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1445 };
1446
1447 static const CGEN_IFMT fmt_addn = {
1448 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1449 };
1450
1451 static const CGEN_IFMT fmt_addni = {
1452 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1453 };
1454
1455 static const CGEN_IFMT fmt_addn2 = {
1456 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1457 };
1458
1459 static const CGEN_IFMT fmt_cmp = {
1460 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1461 };
1462
1463 static const CGEN_IFMT fmt_cmpi = {
1464 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1465 };
1466
1467 static const CGEN_IFMT fmt_cmp2 = {
1468 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1469 };
1470
1471 static const CGEN_IFMT fmt_and = {
1472 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1473 };
1474
1475 static const CGEN_IFMT fmt_andm = {
1476 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1477 };
1478
1479 static const CGEN_IFMT fmt_andh = {
1480 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1481 };
1482
1483 static const CGEN_IFMT fmt_andb = {
1484 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1485 };
1486
1487 static const CGEN_IFMT fmt_bandl = {
1488 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1489 };
1490
1491 static const CGEN_IFMT fmt_btstl = {
1492 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1493 };
1494
1495 static const CGEN_IFMT fmt_mul = {
1496 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1497 };
1498
1499 static const CGEN_IFMT fmt_mulu = {
1500 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1501 };
1502
1503 static const CGEN_IFMT fmt_mulh = {
1504 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1505 };
1506
1507 static const CGEN_IFMT fmt_div0s = {
1508 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1509 };
1510
1511 static const CGEN_IFMT fmt_div3 = {
1512 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1513 };
1514
1515 static const CGEN_IFMT fmt_lsl = {
1516 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1517 };
1518
1519 static const CGEN_IFMT fmt_lsli = {
1520 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1521 };
1522
1523 static const CGEN_IFMT fmt_ldi8 = {
1524 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
1525 };
1526
1527 static const CGEN_IFMT fmt_ldi20 = {
1528 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
1529 };
1530
1531 static const CGEN_IFMT fmt_ldi32 = {
1532 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1533 };
1534
1535 static const CGEN_IFMT fmt_ld = {
1536 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1537 };
1538
1539 static const CGEN_IFMT fmt_lduh = {
1540 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1541 };
1542
1543 static const CGEN_IFMT fmt_ldub = {
1544 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1545 };
1546
1547 static const CGEN_IFMT fmt_ldr13 = {
1548 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1549 };
1550
1551 static const CGEN_IFMT fmt_ldr13uh = {
1552 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1553 };
1554
1555 static const CGEN_IFMT fmt_ldr13ub = {
1556 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1557 };
1558
1559 static const CGEN_IFMT fmt_ldr14 = {
1560 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
1561 };
1562
1563 static const CGEN_IFMT fmt_ldr14uh = {
1564 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
1565 };
1566
1567 static const CGEN_IFMT fmt_ldr14ub = {
1568 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
1569 };
1570
1571 static const CGEN_IFMT fmt_ldr15 = {
1572 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
1573 };
1574
1575 static const CGEN_IFMT fmt_ldr15gr = {
1576 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1577 };
1578
1579 static const CGEN_IFMT fmt_ldr15dr = {
1580 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
1581 };
1582
1583 static const CGEN_IFMT fmt_ldr15ps = {
1584 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1585 };
1586
1587 static const CGEN_IFMT fmt_st = {
1588 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1589 };
1590
1591 static const CGEN_IFMT fmt_sth = {
1592 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1593 };
1594
1595 static const CGEN_IFMT fmt_stb = {
1596 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1597 };
1598
1599 static const CGEN_IFMT fmt_str13 = {
1600 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1601 };
1602
1603 static const CGEN_IFMT fmt_str13h = {
1604 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1605 };
1606
1607 static const CGEN_IFMT fmt_str13b = {
1608 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1609 };
1610
1611 static const CGEN_IFMT fmt_str14 = {
1612 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
1613 };
1614
1615 static const CGEN_IFMT fmt_str14h = {
1616 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
1617 };
1618
1619 static const CGEN_IFMT fmt_str14b = {
1620 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
1621 };
1622
1623 static const CGEN_IFMT fmt_str15 = {
1624 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
1625 };
1626
1627 static const CGEN_IFMT fmt_str15gr = {
1628 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1629 };
1630
1631 static const CGEN_IFMT fmt_str15dr = {
1632 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
1633 };
1634
1635 static const CGEN_IFMT fmt_str15ps = {
1636 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1637 };
1638
1639 static const CGEN_IFMT fmt_mov = {
1640 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1641 };
1642
1643 static const CGEN_IFMT fmt_movdr = {
1644 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
1645 };
1646
1647 static const CGEN_IFMT fmt_movps = {
1648 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1649 };
1650
1651 static const CGEN_IFMT fmt_mov2dr = {
1652 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
1653 };
1654
1655 static const CGEN_IFMT fmt_mov2ps = {
1656 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1657 };
1658
1659 static const CGEN_IFMT fmt_jmp = {
1660 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1661 };
1662
1663 static const CGEN_IFMT fmt_callr = {
1664 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1665 };
1666
1667 static const CGEN_IFMT fmt_call = {
1668 16, 16, 0xf800, { F (F_OP1), F (F_OP5), F (F_REL12), 0 }
1669 };
1670
1671 static const CGEN_IFMT fmt_ret = {
1672 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1673 };
1674
1675 static const CGEN_IFMT fmt_int = {
1676 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1677 };
1678
1679 static const CGEN_IFMT fmt_inte = {
1680 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1681 };
1682
1683 static const CGEN_IFMT fmt_reti = {
1684 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1685 };
1686
1687 static const CGEN_IFMT fmt_bra = {
1688 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1689 };
1690
1691 static const CGEN_IFMT fmt_beq = {
1692 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1693 };
1694
1695 static const CGEN_IFMT fmt_bc = {
1696 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1697 };
1698
1699 static const CGEN_IFMT fmt_bn = {
1700 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1701 };
1702
1703 static const CGEN_IFMT fmt_bv = {
1704 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1705 };
1706
1707 static const CGEN_IFMT fmt_blt = {
1708 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1709 };
1710
1711 static const CGEN_IFMT fmt_ble = {
1712 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1713 };
1714
1715 static const CGEN_IFMT fmt_bls = {
1716 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1717 };
1718
1719 static const CGEN_IFMT fmt_dmovr13 = {
1720 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1721 };
1722
1723 static const CGEN_IFMT fmt_dmovr13h = {
1724 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1725 };
1726
1727 static const CGEN_IFMT fmt_dmovr13b = {
1728 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1729 };
1730
1731 static const CGEN_IFMT fmt_dmovr13pi = {
1732 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1733 };
1734
1735 static const CGEN_IFMT fmt_dmovr13pih = {
1736 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1737 };
1738
1739 static const CGEN_IFMT fmt_dmovr13pib = {
1740 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1741 };
1742
1743 static const CGEN_IFMT fmt_dmovr15pi = {
1744 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1745 };
1746
1747 static const CGEN_IFMT fmt_dmov2r13 = {
1748 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1749 };
1750
1751 static const CGEN_IFMT fmt_dmov2r13h = {
1752 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1753 };
1754
1755 static const CGEN_IFMT fmt_dmov2r13b = {
1756 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1757 };
1758
1759 static const CGEN_IFMT fmt_dmov2r13pi = {
1760 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1761 };
1762
1763 static const CGEN_IFMT fmt_dmov2r13pih = {
1764 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1765 };
1766
1767 static const CGEN_IFMT fmt_dmov2r13pib = {
1768 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1769 };
1770
1771 static const CGEN_IFMT fmt_dmov2r15pd = {
1772 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1773 };
1774
1775 static const CGEN_IFMT fmt_ldres = {
1776 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1777 };
1778
1779 static const CGEN_IFMT fmt_copop = {
1780 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_CRI), 0 }
1781 };
1782
1783 static const CGEN_IFMT fmt_copld = {
1784 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_RJC), F (F_U4C), F (F_CRI), 0 }
1785 };
1786
1787 static const CGEN_IFMT fmt_copst = {
1788 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_RIC), 0 }
1789 };
1790
1791 static const CGEN_IFMT fmt_andccr = {
1792 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1793 };
1794
1795 static const CGEN_IFMT fmt_stilm = {
1796 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1797 };
1798
1799 static const CGEN_IFMT fmt_addsp = {
1800 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_S10), 0 }
1801 };
1802
1803 static const CGEN_IFMT fmt_extsb = {
1804 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1805 };
1806
1807 static const CGEN_IFMT fmt_extub = {
1808 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1809 };
1810
1811 static const CGEN_IFMT fmt_extsh = {
1812 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1813 };
1814
1815 static const CGEN_IFMT fmt_extuh = {
1816 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1817 };
1818
1819 static const CGEN_IFMT fmt_ldm0 = {
1820 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_LD), 0 }
1821 };
1822
1823 static const CGEN_IFMT fmt_ldm1 = {
1824 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_LD), 0 }
1825 };
1826
1827 static const CGEN_IFMT fmt_stm0 = {
1828 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_ST), 0 }
1829 };
1830
1831 static const CGEN_IFMT fmt_stm1 = {
1832 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_ST), 0 }
1833 };
1834
1835 static const CGEN_IFMT fmt_enter = {
1836 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U10), 0 }
1837 };
1838
1839 static const CGEN_IFMT fmt_leave = {
1840 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1841 };
1842
1843 static const CGEN_IFMT fmt_xchb = {
1844 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1845 };
1846
1847 #undef F
1848
1849 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1850 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1851 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1852
1853 /* The instruction table.
1854 This is currently non-static because the simulator accesses it
1855 directly. */
1856
1857 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
1858 {
1859 /* Special null first entry.
1860 A `num' value of zero is thus invalid.
1861 Also, the special `invalid' insn resides here. */
1862 { { 0 }, 0 },
1863 /* add $Rj,$Ri */
1864 {
1865 { 1, 1, 1, 1 },
1866 FR30_INSN_ADD, "add", "add",
1867 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1868 & fmt_add, { 0xa600 },
1869 (PTR) & fmt_add_ops[0],
1870 { 0, 0, { 0 } }
1871 },
1872 /* add $u4,$Ri */
1873 {
1874 { 1, 1, 1, 1 },
1875 FR30_INSN_ADDI, "addi", "add",
1876 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1877 & fmt_addi, { 0xa400 },
1878 (PTR) & fmt_addi_ops[0],
1879 { 0, 0, { 0 } }
1880 },
1881 /* add2 $m4,$Ri */
1882 {
1883 { 1, 1, 1, 1 },
1884 FR30_INSN_ADD2, "add2", "add2",
1885 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1886 & fmt_add2, { 0xa500 },
1887 (PTR) & fmt_add2_ops[0],
1888 { 0, 0, { 0 } }
1889 },
1890 /* addc $Rj,$Ri */
1891 {
1892 { 1, 1, 1, 1 },
1893 FR30_INSN_ADDC, "addc", "addc",
1894 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1895 & fmt_addc, { 0xa700 },
1896 (PTR) & fmt_addc_ops[0],
1897 { 0, 0, { 0 } }
1898 },
1899 /* addn $Rj,$Ri */
1900 {
1901 { 1, 1, 1, 1 },
1902 FR30_INSN_ADDN, "addn", "addn",
1903 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1904 & fmt_addn, { 0xa200 },
1905 (PTR) & fmt_addn_ops[0],
1906 { 0, 0, { 0 } }
1907 },
1908 /* addn $u4,$Ri */
1909 {
1910 { 1, 1, 1, 1 },
1911 FR30_INSN_ADDNI, "addni", "addn",
1912 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1913 & fmt_addni, { 0xa000 },
1914 (PTR) & fmt_addni_ops[0],
1915 { 0, 0, { 0 } }
1916 },
1917 /* addn2 $m4,$Ri */
1918 {
1919 { 1, 1, 1, 1 },
1920 FR30_INSN_ADDN2, "addn2", "addn2",
1921 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1922 & fmt_addn2, { 0xa100 },
1923 (PTR) & fmt_addn2_ops[0],
1924 { 0, 0, { 0 } }
1925 },
1926 /* sub $Rj,$Ri */
1927 {
1928 { 1, 1, 1, 1 },
1929 FR30_INSN_SUB, "sub", "sub",
1930 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1931 & fmt_add, { 0xac00 },
1932 (PTR) & fmt_add_ops[0],
1933 { 0, 0, { 0 } }
1934 },
1935 /* subc $Rj,$Ri */
1936 {
1937 { 1, 1, 1, 1 },
1938 FR30_INSN_SUBC, "subc", "subc",
1939 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1940 & fmt_addc, { 0xad00 },
1941 (PTR) & fmt_addc_ops[0],
1942 { 0, 0, { 0 } }
1943 },
1944 /* subn $Rj,$Ri */
1945 {
1946 { 1, 1, 1, 1 },
1947 FR30_INSN_SUBN, "subn", "subn",
1948 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1949 & fmt_addn, { 0xae00 },
1950 (PTR) & fmt_addn_ops[0],
1951 { 0, 0, { 0 } }
1952 },
1953 /* cmp $Rj,$Ri */
1954 {
1955 { 1, 1, 1, 1 },
1956 FR30_INSN_CMP, "cmp", "cmp",
1957 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1958 & fmt_cmp, { 0xaa00 },
1959 (PTR) & fmt_cmp_ops[0],
1960 { 0, 0, { 0 } }
1961 },
1962 /* cmp $u4,$Ri */
1963 {
1964 { 1, 1, 1, 1 },
1965 FR30_INSN_CMPI, "cmpi", "cmp",
1966 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1967 & fmt_cmpi, { 0xa800 },
1968 (PTR) & fmt_cmpi_ops[0],
1969 { 0, 0, { 0 } }
1970 },
1971 /* cmp2 $m4,$Ri */
1972 {
1973 { 1, 1, 1, 1 },
1974 FR30_INSN_CMP2, "cmp2", "cmp2",
1975 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1976 & fmt_cmp2, { 0xa900 },
1977 (PTR) & fmt_cmp2_ops[0],
1978 { 0, 0, { 0 } }
1979 },
1980 /* and $Rj,$Ri */
1981 {
1982 { 1, 1, 1, 1 },
1983 FR30_INSN_AND, "and", "and",
1984 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1985 & fmt_and, { 0x8200 },
1986 (PTR) & fmt_and_ops[0],
1987 { 0, 0, { 0 } }
1988 },
1989 /* or $Rj,$Ri */
1990 {
1991 { 1, 1, 1, 1 },
1992 FR30_INSN_OR, "or", "or",
1993 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1994 & fmt_and, { 0x9200 },
1995 (PTR) & fmt_and_ops[0],
1996 { 0, 0, { 0 } }
1997 },
1998 /* eor $Rj,$Ri */
1999 {
2000 { 1, 1, 1, 1 },
2001 FR30_INSN_EOR, "eor", "eor",
2002 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2003 & fmt_and, { 0x9a00 },
2004 (PTR) & fmt_and_ops[0],
2005 { 0, 0, { 0 } }
2006 },
2007 /* and $Rj,@$Ri */
2008 {
2009 { 1, 1, 1, 1 },
2010 FR30_INSN_ANDM, "andm", "and",
2011 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2012 & fmt_andm, { 0x8400 },
2013 (PTR) & fmt_andm_ops[0],
2014 { 0, 0, { 0 } }
2015 },
2016 /* andh $Rj,@$Ri */
2017 {
2018 { 1, 1, 1, 1 },
2019 FR30_INSN_ANDH, "andh", "andh",
2020 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2021 & fmt_andh, { 0x8500 },
2022 (PTR) & fmt_andh_ops[0],
2023 { 0, 0, { 0 } }
2024 },
2025 /* andb $Rj,@$Ri */
2026 {
2027 { 1, 1, 1, 1 },
2028 FR30_INSN_ANDB, "andb", "andb",
2029 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2030 & fmt_andb, { 0x8600 },
2031 (PTR) & fmt_andb_ops[0],
2032 { 0, 0, { 0 } }
2033 },
2034 /* or $Rj,@$Ri */
2035 {
2036 { 1, 1, 1, 1 },
2037 FR30_INSN_ORM, "orm", "or",
2038 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2039 & fmt_andm, { 0x9400 },
2040 (PTR) & fmt_andm_ops[0],
2041 { 0, 0, { 0 } }
2042 },
2043 /* orh $Rj,@$Ri */
2044 {
2045 { 1, 1, 1, 1 },
2046 FR30_INSN_ORH, "orh", "orh",
2047 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2048 & fmt_andh, { 0x9500 },
2049 (PTR) & fmt_andh_ops[0],
2050 { 0, 0, { 0 } }
2051 },
2052 /* orb $Rj,@$Ri */
2053 {
2054 { 1, 1, 1, 1 },
2055 FR30_INSN_ORB, "orb", "orb",
2056 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2057 & fmt_andb, { 0x9600 },
2058 (PTR) & fmt_andb_ops[0],
2059 { 0, 0, { 0 } }
2060 },
2061 /* eor $Rj,@$Ri */
2062 {
2063 { 1, 1, 1, 1 },
2064 FR30_INSN_EORM, "eorm", "eor",
2065 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2066 & fmt_andm, { 0x9c00 },
2067 (PTR) & fmt_andm_ops[0],
2068 { 0, 0, { 0 } }
2069 },
2070 /* eorh $Rj,@$Ri */
2071 {
2072 { 1, 1, 1, 1 },
2073 FR30_INSN_EORH, "eorh", "eorh",
2074 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2075 & fmt_andh, { 0x9d00 },
2076 (PTR) & fmt_andh_ops[0],
2077 { 0, 0, { 0 } }
2078 },
2079 /* eorb $Rj,@$Ri */
2080 {
2081 { 1, 1, 1, 1 },
2082 FR30_INSN_EORB, "eorb", "eorb",
2083 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2084 & fmt_andb, { 0x9e00 },
2085 (PTR) & fmt_andb_ops[0],
2086 { 0, 0, { 0 } }
2087 },
2088 /* bandl $u4,@$Ri */
2089 {
2090 { 1, 1, 1, 1 },
2091 FR30_INSN_BANDL, "bandl", "bandl",
2092 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2093 & fmt_bandl, { 0x8000 },
2094 (PTR) & fmt_bandl_ops[0],
2095 { 0, 0, { 0 } }
2096 },
2097 /* borl $u4,@$Ri */
2098 {
2099 { 1, 1, 1, 1 },
2100 FR30_INSN_BORL, "borl", "borl",
2101 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2102 & fmt_bandl, { 0x9000 },
2103 (PTR) & fmt_bandl_ops[0],
2104 { 0, 0, { 0 } }
2105 },
2106 /* beorl $u4,@$Ri */
2107 {
2108 { 1, 1, 1, 1 },
2109 FR30_INSN_BEORL, "beorl", "beorl",
2110 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2111 & fmt_bandl, { 0x9800 },
2112 (PTR) & fmt_bandl_ops[0],
2113 { 0, 0, { 0 } }
2114 },
2115 /* bandh $u4,@$Ri */
2116 {
2117 { 1, 1, 1, 1 },
2118 FR30_INSN_BANDH, "bandh", "bandh",
2119 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2120 & fmt_bandl, { 0x8100 },
2121 (PTR) & fmt_bandl_ops[0],
2122 { 0, 0, { 0 } }
2123 },
2124 /* borh $u4,@$Ri */
2125 {
2126 { 1, 1, 1, 1 },
2127 FR30_INSN_BORH, "borh", "borh",
2128 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2129 & fmt_bandl, { 0x9100 },
2130 (PTR) & fmt_bandl_ops[0],
2131 { 0, 0, { 0 } }
2132 },
2133 /* beorh $u4,@$Ri */
2134 {
2135 { 1, 1, 1, 1 },
2136 FR30_INSN_BEORH, "beorh", "beorh",
2137 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2138 & fmt_bandl, { 0x9900 },
2139 (PTR) & fmt_bandl_ops[0],
2140 { 0, 0, { 0 } }
2141 },
2142 /* btstl $u4,@$Ri */
2143 {
2144 { 1, 1, 1, 1 },
2145 FR30_INSN_BTSTL, "btstl", "btstl",
2146 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2147 & fmt_btstl, { 0x8800 },
2148 (PTR) & fmt_btstl_ops[0],
2149 { 0, 0, { 0 } }
2150 },
2151 /* btsth $u4,@$Ri */
2152 {
2153 { 1, 1, 1, 1 },
2154 FR30_INSN_BTSTH, "btsth", "btsth",
2155 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2156 & fmt_btstl, { 0x8900 },
2157 (PTR) & fmt_btstl_ops[0],
2158 { 0, 0, { 0 } }
2159 },
2160 /* mul $Rj,$Ri */
2161 {
2162 { 1, 1, 1, 1 },
2163 FR30_INSN_MUL, "mul", "mul",
2164 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2165 & fmt_mul, { 0xaf00 },
2166 (PTR) & fmt_mul_ops[0],
2167 { 0, 0, { 0 } }
2168 },
2169 /* mulu $Rj,$Ri */
2170 {
2171 { 1, 1, 1, 1 },
2172 FR30_INSN_MULU, "mulu", "mulu",
2173 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2174 & fmt_mulu, { 0xab00 },
2175 (PTR) & fmt_mulu_ops[0],
2176 { 0, 0, { 0 } }
2177 },
2178 /* mulh $Rj,$Ri */
2179 {
2180 { 1, 1, 1, 1 },
2181 FR30_INSN_MULH, "mulh", "mulh",
2182 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2183 & fmt_mulh, { 0xbf00 },
2184 (PTR) & fmt_mulh_ops[0],
2185 { 0, 0, { 0 } }
2186 },
2187 /* muluh $Rj,$Ri */
2188 {
2189 { 1, 1, 1, 1 },
2190 FR30_INSN_MULUH, "muluh", "muluh",
2191 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2192 & fmt_mulh, { 0xbb00 },
2193 (PTR) & fmt_mulh_ops[0],
2194 { 0, 0, { 0 } }
2195 },
2196 /* div0s $Ri */
2197 {
2198 { 1, 1, 1, 1 },
2199 FR30_INSN_DIV0S, "div0s", "div0s",
2200 { { MNEM, ' ', OP (RI), 0 } },
2201 & fmt_div0s, { 0x9740 },
2202 (PTR) 0,
2203 { 0, 0, { 0 } }
2204 },
2205 /* div0u $Ri */
2206 {
2207 { 1, 1, 1, 1 },
2208 FR30_INSN_DIV0U, "div0u", "div0u",
2209 { { MNEM, ' ', OP (RI), 0 } },
2210 & fmt_div0s, { 0x9750 },
2211 (PTR) 0,
2212 { 0, 0, { 0 } }
2213 },
2214 /* div1 $Ri */
2215 {
2216 { 1, 1, 1, 1 },
2217 FR30_INSN_DIV1, "div1", "div1",
2218 { { MNEM, ' ', OP (RI), 0 } },
2219 & fmt_div0s, { 0x9760 },
2220 (PTR) 0,
2221 { 0, 0, { 0 } }
2222 },
2223 /* div2 $Ri */
2224 {
2225 { 1, 1, 1, 1 },
2226 FR30_INSN_DIV2, "div2", "div2",
2227 { { MNEM, ' ', OP (RI), 0 } },
2228 & fmt_div0s, { 0x9770 },
2229 (PTR) 0,
2230 { 0, 0, { 0 } }
2231 },
2232 /* div3 */
2233 {
2234 { 1, 1, 1, 1 },
2235 FR30_INSN_DIV3, "div3", "div3",
2236 { { MNEM, 0 } },
2237 & fmt_div3, { 0x9f60 },
2238 (PTR) 0,
2239 { 0, 0, { 0 } }
2240 },
2241 /* div4s */
2242 {
2243 { 1, 1, 1, 1 },
2244 FR30_INSN_DIV4S, "div4s", "div4s",
2245 { { MNEM, 0 } },
2246 & fmt_div3, { 0x9f70 },
2247 (PTR) 0,
2248 { 0, 0, { 0 } }
2249 },
2250 /* lsl $Rj,$Ri */
2251 {
2252 { 1, 1, 1, 1 },
2253 FR30_INSN_LSL, "lsl", "lsl",
2254 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2255 & fmt_lsl, { 0xb600 },
2256 (PTR) & fmt_lsl_ops[0],
2257 { 0, 0, { 0 } }
2258 },
2259 /* lsl $u4,$Ri */
2260 {
2261 { 1, 1, 1, 1 },
2262 FR30_INSN_LSLI, "lsli", "lsl",
2263 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2264 & fmt_lsli, { 0xb400 },
2265 (PTR) & fmt_lsli_ops[0],
2266 { 0, 0, { 0 } }
2267 },
2268 /* lsl2 $u4,$Ri */
2269 {
2270 { 1, 1, 1, 1 },
2271 FR30_INSN_LSL2, "lsl2", "lsl2",
2272 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2273 & fmt_lsli, { 0xb500 },
2274 (PTR) & fmt_lsli_ops[0],
2275 { 0, 0, { 0 } }
2276 },
2277 /* lsr $Rj,$Ri */
2278 {
2279 { 1, 1, 1, 1 },
2280 FR30_INSN_LSR, "lsr", "lsr",
2281 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2282 & fmt_lsl, { 0xb200 },
2283 (PTR) & fmt_lsl_ops[0],
2284 { 0, 0, { 0 } }
2285 },
2286 /* lsr $u4,$Ri */
2287 {
2288 { 1, 1, 1, 1 },
2289 FR30_INSN_LSRI, "lsri", "lsr",
2290 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2291 & fmt_lsli, { 0xb000 },
2292 (PTR) & fmt_lsli_ops[0],
2293 { 0, 0, { 0 } }
2294 },
2295 /* lsr2 $u4,$Ri */
2296 {
2297 { 1, 1, 1, 1 },
2298 FR30_INSN_LSR2, "lsr2", "lsr2",
2299 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2300 & fmt_lsli, { 0xb100 },
2301 (PTR) & fmt_lsli_ops[0],
2302 { 0, 0, { 0 } }
2303 },
2304 /* asr $Rj,$Ri */
2305 {
2306 { 1, 1, 1, 1 },
2307 FR30_INSN_ASR, "asr", "asr",
2308 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2309 & fmt_lsl, { 0xba00 },
2310 (PTR) & fmt_lsl_ops[0],
2311 { 0, 0, { 0 } }
2312 },
2313 /* asr $u4,$Ri */
2314 {
2315 { 1, 1, 1, 1 },
2316 FR30_INSN_ASRI, "asri", "asr",
2317 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2318 & fmt_lsli, { 0xb800 },
2319 (PTR) & fmt_lsli_ops[0],
2320 { 0, 0, { 0 } }
2321 },
2322 /* asr2 $u4,$Ri */
2323 {
2324 { 1, 1, 1, 1 },
2325 FR30_INSN_ASR2, "asr2", "asr2",
2326 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2327 & fmt_lsli, { 0xb900 },
2328 (PTR) & fmt_lsli_ops[0],
2329 { 0, 0, { 0 } }
2330 },
2331 /* ldi:8 $i8,$Ri */
2332 {
2333 { 1, 1, 1, 1 },
2334 FR30_INSN_LDI8, "ldi8", "ldi:8",
2335 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
2336 & fmt_ldi8, { 0xc000 },
2337 (PTR) & fmt_ldi8_ops[0],
2338 { 0, 0, { 0 } }
2339 },
2340 /* ldi:20 $i20,$Ri */
2341 {
2342 { 1, 1, 1, 1 },
2343 FR30_INSN_LDI20, "ldi20", "ldi:20",
2344 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
2345 & fmt_ldi20, { 0x9b00 },
2346 (PTR) & fmt_ldi20_ops[0],
2347 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
2348 },
2349 /* ldi:32 $i32,$Ri */
2350 {
2351 { 1, 1, 1, 1 },
2352 FR30_INSN_LDI32, "ldi32", "ldi:32",
2353 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
2354 & fmt_ldi32, { 0x9f80 },
2355 (PTR) & fmt_ldi32_ops[0],
2356 { 0, 0, { 0 } }
2357 },
2358 /* ld @$Rj,$Ri */
2359 {
2360 { 1, 1, 1, 1 },
2361 FR30_INSN_LD, "ld", "ld",
2362 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2363 & fmt_ld, { 0x400 },
2364 (PTR) & fmt_ld_ops[0],
2365 { 0, 0, { 0 } }
2366 },
2367 /* lduh @$Rj,$Ri */
2368 {
2369 { 1, 1, 1, 1 },
2370 FR30_INSN_LDUH, "lduh", "lduh",
2371 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2372 & fmt_lduh, { 0x500 },
2373 (PTR) & fmt_lduh_ops[0],
2374 { 0, 0, { 0 } }
2375 },
2376 /* ldub @$Rj,$Ri */
2377 {
2378 { 1, 1, 1, 1 },
2379 FR30_INSN_LDUB, "ldub", "ldub",
2380 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2381 & fmt_ldub, { 0x600 },
2382 (PTR) & fmt_ldub_ops[0],
2383 { 0, 0, { 0 } }
2384 },
2385 /* ld @($R13,$Rj),$Ri */
2386 {
2387 { 1, 1, 1, 1 },
2388 FR30_INSN_LDR13, "ldr13", "ld",
2389 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2390 & fmt_ldr13, { 0x0 },
2391 (PTR) & fmt_ldr13_ops[0],
2392 { 0, 0, { 0 } }
2393 },
2394 /* lduh @($R13,$Rj),$Ri */
2395 {
2396 { 1, 1, 1, 1 },
2397 FR30_INSN_LDR13UH, "ldr13uh", "lduh",
2398 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2399 & fmt_ldr13uh, { 0x100 },
2400 (PTR) & fmt_ldr13uh_ops[0],
2401 { 0, 0, { 0 } }
2402 },
2403 /* ldub @($R13,$Rj),$Ri */
2404 {
2405 { 1, 1, 1, 1 },
2406 FR30_INSN_LDR13UB, "ldr13ub", "ldub",
2407 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2408 & fmt_ldr13ub, { 0x200 },
2409 (PTR) & fmt_ldr13ub_ops[0],
2410 { 0, 0, { 0 } }
2411 },
2412 /* ld @($R14,$disp10),$Ri */
2413 {
2414 { 1, 1, 1, 1 },
2415 FR30_INSN_LDR14, "ldr14", "ld",
2416 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
2417 & fmt_ldr14, { 0x2000 },
2418 (PTR) & fmt_ldr14_ops[0],
2419 { 0, 0, { 0 } }
2420 },
2421 /* lduh @($R14,$disp9),$Ri */
2422 {
2423 { 1, 1, 1, 1 },
2424 FR30_INSN_LDR14UH, "ldr14uh", "lduh",
2425 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
2426 & fmt_ldr14uh, { 0x4000 },
2427 (PTR) & fmt_ldr14uh_ops[0],
2428 { 0, 0, { 0 } }
2429 },
2430 /* ldub @($R14,$disp8),$Ri */
2431 {
2432 { 1, 1, 1, 1 },
2433 FR30_INSN_LDR14UB, "ldr14ub", "ldub",
2434 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
2435 & fmt_ldr14ub, { 0x6000 },
2436 (PTR) & fmt_ldr14ub_ops[0],
2437 { 0, 0, { 0 } }
2438 },
2439 /* ld @($R15,$udisp6),$Ri */
2440 {
2441 { 1, 1, 1, 1 },
2442 FR30_INSN_LDR15, "ldr15", "ld",
2443 { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
2444 & fmt_ldr15, { 0x300 },
2445 (PTR) & fmt_ldr15_ops[0],
2446 { 0, 0, { 0 } }
2447 },
2448 /* ld @$R15+,$Ri */
2449 {
2450 { 1, 1, 1, 1 },
2451 FR30_INSN_LDR15GR, "ldr15gr", "ld",
2452 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
2453 & fmt_ldr15gr, { 0x700 },
2454 (PTR) & fmt_ldr15gr_ops[0],
2455 { 0, 0, { 0 } }
2456 },
2457 /* ld @$R15+,$Rs2 */
2458 {
2459 { 1, 1, 1, 1 },
2460 FR30_INSN_LDR15DR, "ldr15dr", "ld",
2461 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
2462 & fmt_ldr15dr, { 0x780 },
2463 (PTR) & fmt_ldr15dr_ops[0],
2464 { 0, 0, { 0 } }
2465 },
2466 /* ld @$R15+,$ps */
2467 {
2468 { 1, 1, 1, 1 },
2469 FR30_INSN_LDR15PS, "ldr15ps", "ld",
2470 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
2471 & fmt_ldr15ps, { 0x790 },
2472 (PTR) & fmt_ldr15ps_ops[0],
2473 { 0, 0, { 0 } }
2474 },
2475 /* st $Ri,@$Rj */
2476 {
2477 { 1, 1, 1, 1 },
2478 FR30_INSN_ST, "st", "st",
2479 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2480 & fmt_st, { 0x1400 },
2481 (PTR) & fmt_st_ops[0],
2482 { 0, 0, { 0 } }
2483 },
2484 /* sth $Ri,@$Rj */
2485 {
2486 { 1, 1, 1, 1 },
2487 FR30_INSN_STH, "sth", "sth",
2488 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2489 & fmt_sth, { 0x1500 },
2490 (PTR) & fmt_sth_ops[0],
2491 { 0, 0, { 0 } }
2492 },
2493 /* stb $Ri,@$Rj */
2494 {
2495 { 1, 1, 1, 1 },
2496 FR30_INSN_STB, "stb", "stb",
2497 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2498 & fmt_stb, { 0x1600 },
2499 (PTR) & fmt_stb_ops[0],
2500 { 0, 0, { 0 } }
2501 },
2502 /* st $Ri,@($R13,$Rj) */
2503 {
2504 { 1, 1, 1, 1 },
2505 FR30_INSN_STR13, "str13", "st",
2506 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2507 & fmt_str13, { 0x1000 },
2508 (PTR) & fmt_str13_ops[0],
2509 { 0, 0, { 0 } }
2510 },
2511 /* sth $Ri,@($R13,$Rj) */
2512 {
2513 { 1, 1, 1, 1 },
2514 FR30_INSN_STR13H, "str13h", "sth",
2515 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2516 & fmt_str13h, { 0x1100 },
2517 (PTR) & fmt_str13h_ops[0],
2518 { 0, 0, { 0 } }
2519 },
2520 /* stb $Ri,@($R13,$Rj) */
2521 {
2522 { 1, 1, 1, 1 },
2523 FR30_INSN_STR13B, "str13b", "stb",
2524 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2525 & fmt_str13b, { 0x1200 },
2526 (PTR) & fmt_str13b_ops[0],
2527 { 0, 0, { 0 } }
2528 },
2529 /* st $Ri,@($R14,$disp10) */
2530 {
2531 { 1, 1, 1, 1 },
2532 FR30_INSN_STR14, "str14", "st",
2533 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
2534 & fmt_str14, { 0x3000 },
2535 (PTR) & fmt_str14_ops[0],
2536 { 0, 0, { 0 } }
2537 },
2538 /* sth $Ri,@($R14,$disp9) */
2539 {
2540 { 1, 1, 1, 1 },
2541 FR30_INSN_STR14H, "str14h", "sth",
2542 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
2543 & fmt_str14h, { 0x5000 },
2544 (PTR) & fmt_str14h_ops[0],
2545 { 0, 0, { 0 } }
2546 },
2547 /* stb $Ri,@($R14,$disp8) */
2548 {
2549 { 1, 1, 1, 1 },
2550 FR30_INSN_STR14B, "str14b", "stb",
2551 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
2552 & fmt_str14b, { 0x7000 },
2553 (PTR) & fmt_str14b_ops[0],
2554 { 0, 0, { 0 } }
2555 },
2556 /* st $Ri,@($R15,$udisp6) */
2557 {
2558 { 1, 1, 1, 1 },
2559 FR30_INSN_STR15, "str15", "st",
2560 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
2561 & fmt_str15, { 0x1300 },
2562 (PTR) & fmt_str15_ops[0],
2563 { 0, 0, { 0 } }
2564 },
2565 /* st $Ri,@-$R15 */
2566 {
2567 { 1, 1, 1, 1 },
2568 FR30_INSN_STR15GR, "str15gr", "st",
2569 { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
2570 & fmt_str15gr, { 0x1700 },
2571 (PTR) & fmt_str15gr_ops[0],
2572 { 0, 0, { 0 } }
2573 },
2574 /* st $Rs2,@-$R15 */
2575 {
2576 { 1, 1, 1, 1 },
2577 FR30_INSN_STR15DR, "str15dr", "st",
2578 { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
2579 & fmt_str15dr, { 0x1780 },
2580 (PTR) & fmt_str15dr_ops[0],
2581 { 0, 0, { 0 } }
2582 },
2583 /* st $ps,@-$R15 */
2584 {
2585 { 1, 1, 1, 1 },
2586 FR30_INSN_STR15PS, "str15ps", "st",
2587 { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
2588 & fmt_str15ps, { 0x1790 },
2589 (PTR) & fmt_str15ps_ops[0],
2590 { 0, 0, { 0 } }
2591 },
2592 /* mov $Rj,$Ri */
2593 {
2594 { 1, 1, 1, 1 },
2595 FR30_INSN_MOV, "mov", "mov",
2596 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2597 & fmt_mov, { 0x8b00 },
2598 (PTR) & fmt_mov_ops[0],
2599 { 0, 0, { 0 } }
2600 },
2601 /* mov $Rs1,$Ri */
2602 {
2603 { 1, 1, 1, 1 },
2604 FR30_INSN_MOVDR, "movdr", "mov",
2605 { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
2606 & fmt_movdr, { 0xb700 },
2607 (PTR) & fmt_movdr_ops[0],
2608 { 0, 0, { 0 } }
2609 },
2610 /* mov $ps,$Ri */
2611 {
2612 { 1, 1, 1, 1 },
2613 FR30_INSN_MOVPS, "movps", "mov",
2614 { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
2615 & fmt_movps, { 0x1710 },
2616 (PTR) & fmt_movps_ops[0],
2617 { 0, 0, { 0 } }
2618 },
2619 /* mov $Ri,$Rs1 */
2620 {
2621 { 1, 1, 1, 1 },
2622 FR30_INSN_MOV2DR, "mov2dr", "mov",
2623 { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
2624 & fmt_mov2dr, { 0xb300 },
2625 (PTR) & fmt_mov2dr_ops[0],
2626 { 0, 0, { 0 } }
2627 },
2628 /* mov $Ri,$ps */
2629 {
2630 { 1, 1, 1, 1 },
2631 FR30_INSN_MOV2PS, "mov2ps", "mov",
2632 { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
2633 & fmt_mov2ps, { 0x710 },
2634 (PTR) & fmt_mov2ps_ops[0],
2635 { 0, 0, { 0 } }
2636 },
2637 /* jmp @$Ri */
2638 {
2639 { 1, 1, 1, 1 },
2640 FR30_INSN_JMP, "jmp", "jmp",
2641 { { MNEM, ' ', '@', OP (RI), 0 } },
2642 & fmt_jmp, { 0x9700 },
2643 (PTR) & fmt_jmp_ops[0],
2644 { 0, 0|A(UNCOND_CTI), { 0 } }
2645 },
2646 /* jmp:d @$Ri */
2647 {
2648 { 1, 1, 1, 1 },
2649 FR30_INSN_JMPD, "jmpd", "jmp:d",
2650 { { MNEM, ' ', '@', OP (RI), 0 } },
2651 & fmt_jmp, { 0x9f00 },
2652 (PTR) & fmt_jmp_ops[0],
2653 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2654 },
2655 /* call @$Ri */
2656 {
2657 { 1, 1, 1, 1 },
2658 FR30_INSN_CALLR, "callr", "call",
2659 { { MNEM, ' ', '@', OP (RI), 0 } },
2660 & fmt_callr, { 0x9710 },
2661 (PTR) & fmt_callr_ops[0],
2662 { 0, 0|A(UNCOND_CTI), { 0 } }
2663 },
2664 /* call:d @$Ri */
2665 {
2666 { 1, 1, 1, 1 },
2667 FR30_INSN_CALLRD, "callrd", "call:d",
2668 { { MNEM, ' ', '@', OP (RI), 0 } },
2669 & fmt_callr, { 0x9f10 },
2670 (PTR) & fmt_callr_ops[0],
2671 { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2672 },
2673 /* call $label12 */
2674 {
2675 { 1, 1, 1, 1 },
2676 FR30_INSN_CALL, "call", "call",
2677 { { MNEM, ' ', OP (LABEL12), 0 } },
2678 & fmt_call, { 0xd000 },
2679 (PTR) & fmt_call_ops[0],
2680 { 0, 0|A(UNCOND_CTI), { 0 } }
2681 },
2682 /* call:d $label12 */
2683 {
2684 { 1, 1, 1, 1 },
2685 FR30_INSN_CALLD, "calld", "call:d",
2686 { { MNEM, ' ', OP (LABEL12), 0 } },
2687 & fmt_call, { 0xd800 },
2688 (PTR) & fmt_call_ops[0],
2689 { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2690 },
2691 /* ret */
2692 {
2693 { 1, 1, 1, 1 },
2694 FR30_INSN_RET, "ret", "ret",
2695 { { MNEM, 0 } },
2696 & fmt_ret, { 0x9720 },
2697 (PTR) & fmt_ret_ops[0],
2698 { 0, 0|A(UNCOND_CTI), { 0 } }
2699 },
2700 /* ret:d */
2701 {
2702 { 1, 1, 1, 1 },
2703 FR30_INSN_RET_D, "ret:d", "ret:d",
2704 { { MNEM, 0 } },
2705 & fmt_ret, { 0x9f20 },
2706 (PTR) & fmt_ret_ops[0],
2707 { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2708 },
2709 /* int $u8 */
2710 {
2711 { 1, 1, 1, 1 },
2712 FR30_INSN_INT, "int", "int",
2713 { { MNEM, ' ', OP (U8), 0 } },
2714 & fmt_int, { 0x1f00 },
2715 (PTR) & fmt_int_ops[0],
2716 { 0, 0|A(UNCOND_CTI), { 0 } }
2717 },
2718 /* inte */
2719 {
2720 { 1, 1, 1, 1 },
2721 FR30_INSN_INTE, "inte", "inte",
2722 { { MNEM, 0 } },
2723 & fmt_inte, { 0x9f30 },
2724 (PTR) & fmt_inte_ops[0],
2725 { 0, 0|A(UNCOND_CTI), { 0 } }
2726 },
2727 /* reti */
2728 {
2729 { 1, 1, 1, 1 },
2730 FR30_INSN_RETI, "reti", "reti",
2731 { { MNEM, 0 } },
2732 & fmt_reti, { 0x9730 },
2733 (PTR) & fmt_reti_ops[0],
2734 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2735 },
2736 /* bra $label9 */
2737 {
2738 { 1, 1, 1, 1 },
2739 FR30_INSN_BRA, "bra", "bra",
2740 { { MNEM, ' ', OP (LABEL9), 0 } },
2741 & fmt_bra, { 0xe000 },
2742 (PTR) & fmt_bra_ops[0],
2743 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2744 },
2745 /* bra:d $label9 */
2746 {
2747 { 1, 1, 1, 1 },
2748 FR30_INSN_BRAD, "brad", "bra:d",
2749 { { MNEM, ' ', OP (LABEL9), 0 } },
2750 & fmt_bra, { 0xf000 },
2751 (PTR) & fmt_bra_ops[0],
2752 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2753 },
2754 /* bno $label9 */
2755 {
2756 { 1, 1, 1, 1 },
2757 FR30_INSN_BNO, "bno", "bno",
2758 { { MNEM, ' ', OP (LABEL9), 0 } },
2759 & fmt_bra, { 0xe100 },
2760 (PTR) & fmt_bra_ops[0],
2761 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2762 },
2763 /* bno:d $label9 */
2764 {
2765 { 1, 1, 1, 1 },
2766 FR30_INSN_BNOD, "bnod", "bno:d",
2767 { { MNEM, ' ', OP (LABEL9), 0 } },
2768 & fmt_bra, { 0xf100 },
2769 (PTR) & fmt_bra_ops[0],
2770 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2771 },
2772 /* beq $label9 */
2773 {
2774 { 1, 1, 1, 1 },
2775 FR30_INSN_BEQ, "beq", "beq",
2776 { { MNEM, ' ', OP (LABEL9), 0 } },
2777 & fmt_beq, { 0xe200 },
2778 (PTR) & fmt_beq_ops[0],
2779 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2780 },
2781 /* beq:d $label9 */
2782 {
2783 { 1, 1, 1, 1 },
2784 FR30_INSN_BEQD, "beqd", "beq:d",
2785 { { MNEM, ' ', OP (LABEL9), 0 } },
2786 & fmt_beq, { 0xf200 },
2787 (PTR) & fmt_beq_ops[0],
2788 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2789 },
2790 /* bne $label9 */
2791 {
2792 { 1, 1, 1, 1 },
2793 FR30_INSN_BNE, "bne", "bne",
2794 { { MNEM, ' ', OP (LABEL9), 0 } },
2795 & fmt_beq, { 0xe300 },
2796 (PTR) & fmt_beq_ops[0],
2797 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2798 },
2799 /* bne:d $label9 */
2800 {
2801 { 1, 1, 1, 1 },
2802 FR30_INSN_BNED, "bned", "bne:d",
2803 { { MNEM, ' ', OP (LABEL9), 0 } },
2804 & fmt_beq, { 0xf300 },
2805 (PTR) & fmt_beq_ops[0],
2806 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2807 },
2808 /* bc $label9 */
2809 {
2810 { 1, 1, 1, 1 },
2811 FR30_INSN_BC, "bc", "bc",
2812 { { MNEM, ' ', OP (LABEL9), 0 } },
2813 & fmt_bc, { 0xe400 },
2814 (PTR) & fmt_bc_ops[0],
2815 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2816 },
2817 /* bc:d $label9 */
2818 {
2819 { 1, 1, 1, 1 },
2820 FR30_INSN_BCD, "bcd", "bc:d",
2821 { { MNEM, ' ', OP (LABEL9), 0 } },
2822 & fmt_bc, { 0xf400 },
2823 (PTR) & fmt_bc_ops[0],
2824 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2825 },
2826 /* bnc $label9 */
2827 {
2828 { 1, 1, 1, 1 },
2829 FR30_INSN_BNC, "bnc", "bnc",
2830 { { MNEM, ' ', OP (LABEL9), 0 } },
2831 & fmt_bc, { 0xe500 },
2832 (PTR) & fmt_bc_ops[0],
2833 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2834 },
2835 /* bnc:d $label9 */
2836 {
2837 { 1, 1, 1, 1 },
2838 FR30_INSN_BNCD, "bncd", "bnc:d",
2839 { { MNEM, ' ', OP (LABEL9), 0 } },
2840 & fmt_bc, { 0xf500 },
2841 (PTR) & fmt_bc_ops[0],
2842 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2843 },
2844 /* bn $label9 */
2845 {
2846 { 1, 1, 1, 1 },
2847 FR30_INSN_BN, "bn", "bn",
2848 { { MNEM, ' ', OP (LABEL9), 0 } },
2849 & fmt_bn, { 0xe600 },
2850 (PTR) & fmt_bn_ops[0],
2851 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2852 },
2853 /* bn:d $label9 */
2854 {
2855 { 1, 1, 1, 1 },
2856 FR30_INSN_BND, "bnd", "bn:d",
2857 { { MNEM, ' ', OP (LABEL9), 0 } },
2858 & fmt_bn, { 0xf600 },
2859 (PTR) & fmt_bn_ops[0],
2860 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2861 },
2862 /* bp $label9 */
2863 {
2864 { 1, 1, 1, 1 },
2865 FR30_INSN_BP, "bp", "bp",
2866 { { MNEM, ' ', OP (LABEL9), 0 } },
2867 & fmt_bn, { 0xe700 },
2868 (PTR) & fmt_bn_ops[0],
2869 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2870 },
2871 /* bp:d $label9 */
2872 {
2873 { 1, 1, 1, 1 },
2874 FR30_INSN_BPD, "bpd", "bp:d",
2875 { { MNEM, ' ', OP (LABEL9), 0 } },
2876 & fmt_bn, { 0xf700 },
2877 (PTR) & fmt_bn_ops[0],
2878 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2879 },
2880 /* bv $label9 */
2881 {
2882 { 1, 1, 1, 1 },
2883 FR30_INSN_BV, "bv", "bv",
2884 { { MNEM, ' ', OP (LABEL9), 0 } },
2885 & fmt_bv, { 0xe800 },
2886 (PTR) & fmt_bv_ops[0],
2887 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2888 },
2889 /* bv:d $label9 */
2890 {
2891 { 1, 1, 1, 1 },
2892 FR30_INSN_BVD, "bvd", "bv:d",
2893 { { MNEM, ' ', OP (LABEL9), 0 } },
2894 & fmt_bv, { 0xf800 },
2895 (PTR) & fmt_bv_ops[0],
2896 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2897 },
2898 /* bnv $label9 */
2899 {
2900 { 1, 1, 1, 1 },
2901 FR30_INSN_BNV, "bnv", "bnv",
2902 { { MNEM, ' ', OP (LABEL9), 0 } },
2903 & fmt_bv, { 0xe900 },
2904 (PTR) & fmt_bv_ops[0],
2905 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2906 },
2907 /* bnv:d $label9 */
2908 {
2909 { 1, 1, 1, 1 },
2910 FR30_INSN_BNVD, "bnvd", "bnv:d",
2911 { { MNEM, ' ', OP (LABEL9), 0 } },
2912 & fmt_bv, { 0xf900 },
2913 (PTR) & fmt_bv_ops[0],
2914 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2915 },
2916 /* blt $label9 */
2917 {
2918 { 1, 1, 1, 1 },
2919 FR30_INSN_BLT, "blt", "blt",
2920 { { MNEM, ' ', OP (LABEL9), 0 } },
2921 & fmt_blt, { 0xea00 },
2922 (PTR) & fmt_blt_ops[0],
2923 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2924 },
2925 /* blt:d $label9 */
2926 {
2927 { 1, 1, 1, 1 },
2928 FR30_INSN_BLTD, "bltd", "blt:d",
2929 { { MNEM, ' ', OP (LABEL9), 0 } },
2930 & fmt_blt, { 0xfa00 },
2931 (PTR) & fmt_blt_ops[0],
2932 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2933 },
2934 /* bge $label9 */
2935 {
2936 { 1, 1, 1, 1 },
2937 FR30_INSN_BGE, "bge", "bge",
2938 { { MNEM, ' ', OP (LABEL9), 0 } },
2939 & fmt_blt, { 0xeb00 },
2940 (PTR) & fmt_blt_ops[0],
2941 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2942 },
2943 /* bge:d $label9 */
2944 {
2945 { 1, 1, 1, 1 },
2946 FR30_INSN_BGED, "bged", "bge:d",
2947 { { MNEM, ' ', OP (LABEL9), 0 } },
2948 & fmt_blt, { 0xfb00 },
2949 (PTR) & fmt_blt_ops[0],
2950 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2951 },
2952 /* ble $label9 */
2953 {
2954 { 1, 1, 1, 1 },
2955 FR30_INSN_BLE, "ble", "ble",
2956 { { MNEM, ' ', OP (LABEL9), 0 } },
2957 & fmt_ble, { 0xec00 },
2958 (PTR) & fmt_ble_ops[0],
2959 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2960 },
2961 /* ble:d $label9 */
2962 {
2963 { 1, 1, 1, 1 },
2964 FR30_INSN_BLED, "bled", "ble:d",
2965 { { MNEM, ' ', OP (LABEL9), 0 } },
2966 & fmt_ble, { 0xfc00 },
2967 (PTR) & fmt_ble_ops[0],
2968 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2969 },
2970 /* bgt $label9 */
2971 {
2972 { 1, 1, 1, 1 },
2973 FR30_INSN_BGT, "bgt", "bgt",
2974 { { MNEM, ' ', OP (LABEL9), 0 } },
2975 & fmt_ble, { 0xed00 },
2976 (PTR) & fmt_ble_ops[0],
2977 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2978 },
2979 /* bgt:d $label9 */
2980 {
2981 { 1, 1, 1, 1 },
2982 FR30_INSN_BGTD, "bgtd", "bgt:d",
2983 { { MNEM, ' ', OP (LABEL9), 0 } },
2984 & fmt_ble, { 0xfd00 },
2985 (PTR) & fmt_ble_ops[0],
2986 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2987 },
2988 /* bls $label9 */
2989 {
2990 { 1, 1, 1, 1 },
2991 FR30_INSN_BLS, "bls", "bls",
2992 { { MNEM, ' ', OP (LABEL9), 0 } },
2993 & fmt_bls, { 0xee00 },
2994 (PTR) & fmt_bls_ops[0],
2995 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2996 },
2997 /* bls:d $label9 */
2998 {
2999 { 1, 1, 1, 1 },
3000 FR30_INSN_BLSD, "blsd", "bls:d",
3001 { { MNEM, ' ', OP (LABEL9), 0 } },
3002 & fmt_bls, { 0xfe00 },
3003 (PTR) & fmt_bls_ops[0],
3004 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
3005 },
3006 /* bhi $label9 */
3007 {
3008 { 1, 1, 1, 1 },
3009 FR30_INSN_BHI, "bhi", "bhi",
3010 { { MNEM, ' ', OP (LABEL9), 0 } },
3011 & fmt_bls, { 0xef00 },
3012 (PTR) & fmt_bls_ops[0],
3013 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
3014 },
3015 /* bhi:d $label9 */
3016 {
3017 { 1, 1, 1, 1 },
3018 FR30_INSN_BHID, "bhid", "bhi:d",
3019 { { MNEM, ' ', OP (LABEL9), 0 } },
3020 & fmt_bls, { 0xff00 },
3021 (PTR) & fmt_bls_ops[0],
3022 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
3023 },
3024 /* dmov $R13,@$dir10 */
3025 {
3026 { 1, 1, 1, 1 },
3027 FR30_INSN_DMOVR13, "dmovr13", "dmov",
3028 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
3029 & fmt_dmovr13, { 0x1800 },
3030 (PTR) & fmt_dmovr13_ops[0],
3031 { 0, 0, { 0 } }
3032 },
3033 /* dmovh $R13,@$dir9 */
3034 {
3035 { 1, 1, 1, 1 },
3036 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
3037 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
3038 & fmt_dmovr13h, { 0x1900 },
3039 (PTR) & fmt_dmovr13h_ops[0],
3040 { 0, 0, { 0 } }
3041 },
3042 /* dmovb $R13,@$dir8 */
3043 {
3044 { 1, 1, 1, 1 },
3045 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
3046 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
3047 & fmt_dmovr13b, { 0x1a00 },
3048 (PTR) & fmt_dmovr13b_ops[0],
3049 { 0, 0, { 0 } }
3050 },
3051 /* dmov @$R13+,@$dir10 */
3052 {
3053 { 1, 1, 1, 1 },
3054 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
3055 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
3056 & fmt_dmovr13pi, { 0x1c00 },
3057 (PTR) & fmt_dmovr13pi_ops[0],
3058 { 0, 0, { 0 } }
3059 },
3060 /* dmovh @$R13+,@$dir9 */
3061 {
3062 { 1, 1, 1, 1 },
3063 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
3064 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
3065 & fmt_dmovr13pih, { 0x1d00 },
3066 (PTR) & fmt_dmovr13pih_ops[0],
3067 { 0, 0, { 0 } }
3068 },
3069 /* dmovb @$R13+,@$dir8 */
3070 {
3071 { 1, 1, 1, 1 },
3072 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
3073 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
3074 & fmt_dmovr13pib, { 0x1e00 },
3075 (PTR) & fmt_dmovr13pib_ops[0],
3076 { 0, 0, { 0 } }
3077 },
3078 /* dmov @$R15+,@$dir10 */
3079 {
3080 { 1, 1, 1, 1 },
3081 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
3082 { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
3083 & fmt_dmovr15pi, { 0x1b00 },
3084 (PTR) & fmt_dmovr15pi_ops[0],
3085 { 0, 0, { 0 } }
3086 },
3087 /* dmov @$dir10,$R13 */
3088 {
3089 { 1, 1, 1, 1 },
3090 FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
3091 { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
3092 & fmt_dmov2r13, { 0x800 },
3093 (PTR) & fmt_dmov2r13_ops[0],
3094 { 0, 0, { 0 } }
3095 },
3096 /* dmovh @$dir9,$R13 */
3097 {
3098 { 1, 1, 1, 1 },
3099 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
3100 { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
3101 & fmt_dmov2r13h, { 0x900 },
3102 (PTR) & fmt_dmov2r13h_ops[0],
3103 { 0, 0, { 0 } }
3104 },
3105 /* dmovb @$dir8,$R13 */
3106 {
3107 { 1, 1, 1, 1 },
3108 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
3109 { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
3110 & fmt_dmov2r13b, { 0xa00 },
3111 (PTR) & fmt_dmov2r13b_ops[0],
3112 { 0, 0, { 0 } }
3113 },
3114 /* dmov @$dir10,@$R13+ */
3115 {
3116 { 1, 1, 1, 1 },
3117 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
3118 { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
3119 & fmt_dmov2r13pi, { 0xc00 },
3120 (PTR) & fmt_dmov2r13pi_ops[0],
3121 { 0, 0, { 0 } }
3122 },
3123 /* dmovh @$dir9,@$R13+ */
3124 {
3125 { 1, 1, 1, 1 },
3126 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
3127 { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
3128 & fmt_dmov2r13pih, { 0xd00 },
3129 (PTR) & fmt_dmov2r13pih_ops[0],
3130 { 0, 0, { 0 } }
3131 },
3132 /* dmovb @$dir8,@$R13+ */
3133 {
3134 { 1, 1, 1, 1 },
3135 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
3136 { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
3137 & fmt_dmov2r13pib, { 0xe00 },
3138 (PTR) & fmt_dmov2r13pib_ops[0],
3139 { 0, 0, { 0 } }
3140 },
3141 /* dmov @$dir10,@-$R15 */
3142 {
3143 { 1, 1, 1, 1 },
3144 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
3145 { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
3146 & fmt_dmov2r15pd, { 0xb00 },
3147 (PTR) & fmt_dmov2r15pd_ops[0],
3148 { 0, 0, { 0 } }
3149 },
3150 /* ldres @$Ri+,$u4 */
3151 {
3152 { 1, 1, 1, 1 },
3153 FR30_INSN_LDRES, "ldres", "ldres",
3154 { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
3155 & fmt_ldres, { 0xbc00 },
3156 (PTR) 0,
3157 { 0, 0, { 0 } }
3158 },
3159 /* stres $u4,@$Ri+ */
3160 {
3161 { 1, 1, 1, 1 },
3162 FR30_INSN_STRES, "stres", "stres",
3163 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
3164 & fmt_ldres, { 0xbd00 },
3165 (PTR) 0,
3166 { 0, 0, { 0 } }
3167 },
3168 /* copop $u4c,$ccc,$CRj,$CRi */
3169 {
3170 { 1, 1, 1, 1 },
3171 FR30_INSN_COPOP, "copop", "copop",
3172 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
3173 & fmt_copop, { 0x9fc0 },
3174 (PTR) 0,
3175 { 0, 0, { 0 } }
3176 },
3177 /* copld $u4c,$ccc,$Rjc,$CRi */
3178 {
3179 { 1, 1, 1, 1 },
3180 FR30_INSN_COPLD, "copld", "copld",
3181 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
3182 & fmt_copld, { 0x9fd0 },
3183 (PTR) 0,
3184 { 0, 0, { 0 } }
3185 },
3186 /* copst $u4c,$ccc,$CRj,$Ric */
3187 {
3188 { 1, 1, 1, 1 },
3189 FR30_INSN_COPST, "copst", "copst",
3190 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
3191 & fmt_copst, { 0x9fe0 },
3192 (PTR) 0,
3193 { 0, 0, { 0 } }
3194 },
3195 /* copsv $u4c,$ccc,$CRj,$Ric */
3196 {
3197 { 1, 1, 1, 1 },
3198 FR30_INSN_COPSV, "copsv", "copsv",
3199 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
3200 & fmt_copst, { 0x9ff0 },
3201 (PTR) 0,
3202 { 0, 0, { 0 } }
3203 },
3204 /* nop */
3205 {
3206 { 1, 1, 1, 1 },
3207 FR30_INSN_NOP, "nop", "nop",
3208 { { MNEM, 0 } },
3209 & fmt_div3, { 0x9fa0 },
3210 (PTR) 0,
3211 { 0, 0, { 0 } }
3212 },
3213 /* andccr $u8 */
3214 {
3215 { 1, 1, 1, 1 },
3216 FR30_INSN_ANDCCR, "andccr", "andccr",
3217 { { MNEM, ' ', OP (U8), 0 } },
3218 & fmt_andccr, { 0x8300 },
3219 (PTR) & fmt_andccr_ops[0],
3220 { 0, 0, { 0 } }
3221 },
3222 /* orccr $u8 */
3223 {
3224 { 1, 1, 1, 1 },
3225 FR30_INSN_ORCCR, "orccr", "orccr",
3226 { { MNEM, ' ', OP (U8), 0 } },
3227 & fmt_andccr, { 0x9300 },
3228 (PTR) & fmt_andccr_ops[0],
3229 { 0, 0, { 0 } }
3230 },
3231 /* stilm $u8 */
3232 {
3233 { 1, 1, 1, 1 },
3234 FR30_INSN_STILM, "stilm", "stilm",
3235 { { MNEM, ' ', OP (U8), 0 } },
3236 & fmt_stilm, { 0x8700 },
3237 (PTR) & fmt_stilm_ops[0],
3238 { 0, 0, { 0 } }
3239 },
3240 /* addsp $s10 */
3241 {
3242 { 1, 1, 1, 1 },
3243 FR30_INSN_ADDSP, "addsp", "addsp",
3244 { { MNEM, ' ', OP (S10), 0 } },
3245 & fmt_addsp, { 0xa300 },
3246 (PTR) & fmt_addsp_ops[0],
3247 { 0, 0, { 0 } }
3248 },
3249 /* extsb $Ri */
3250 {
3251 { 1, 1, 1, 1 },
3252 FR30_INSN_EXTSB, "extsb", "extsb",
3253 { { MNEM, ' ', OP (RI), 0 } },
3254 & fmt_extsb, { 0x9780 },
3255 (PTR) & fmt_extsb_ops[0],
3256 { 0, 0, { 0 } }
3257 },
3258 /* extub $Ri */
3259 {
3260 { 1, 1, 1, 1 },
3261 FR30_INSN_EXTUB, "extub", "extub",
3262 { { MNEM, ' ', OP (RI), 0 } },
3263 & fmt_extub, { 0x9790 },
3264 (PTR) & fmt_extub_ops[0],
3265 { 0, 0, { 0 } }
3266 },
3267 /* extsh $Ri */
3268 {
3269 { 1, 1, 1, 1 },
3270 FR30_INSN_EXTSH, "extsh", "extsh",
3271 { { MNEM, ' ', OP (RI), 0 } },
3272 & fmt_extsh, { 0x97a0 },
3273 (PTR) & fmt_extsh_ops[0],
3274 { 0, 0, { 0 } }
3275 },
3276 /* extuh $Ri */
3277 {
3278 { 1, 1, 1, 1 },
3279 FR30_INSN_EXTUH, "extuh", "extuh",
3280 { { MNEM, ' ', OP (RI), 0 } },
3281 & fmt_extuh, { 0x97b0 },
3282 (PTR) & fmt_extuh_ops[0],
3283 { 0, 0, { 0 } }
3284 },
3285 /* ldm0 ($reglist_low_ld) */
3286 {
3287 { 1, 1, 1, 1 },
3288 FR30_INSN_LDM0, "ldm0", "ldm0",
3289 { { MNEM, ' ', '(', OP (REGLIST_LOW_LD), ')', 0 } },
3290 & fmt_ldm0, { 0x8c00 },
3291 (PTR) & fmt_ldm0_ops[0],
3292 { 0, 0, { 0 } }
3293 },
3294 /* ldm1 ($reglist_hi_ld) */
3295 {
3296 { 1, 1, 1, 1 },
3297 FR30_INSN_LDM1, "ldm1", "ldm1",
3298 { { MNEM, ' ', '(', OP (REGLIST_HI_LD), ')', 0 } },
3299 & fmt_ldm1, { 0x8d00 },
3300 (PTR) & fmt_ldm1_ops[0],
3301 { 0, 0, { 0 } }
3302 },
3303 /* stm0 ($reglist_low_st) */
3304 {
3305 { 1, 1, 1, 1 },
3306 FR30_INSN_STM0, "stm0", "stm0",
3307 { { MNEM, ' ', '(', OP (REGLIST_LOW_ST), ')', 0 } },
3308 & fmt_stm0, { 0x8e00 },
3309 (PTR) & fmt_stm0_ops[0],
3310 { 0, 0, { 0 } }
3311 },
3312 /* stm1 ($reglist_hi_st) */
3313 {
3314 { 1, 1, 1, 1 },
3315 FR30_INSN_STM1, "stm1", "stm1",
3316 { { MNEM, ' ', '(', OP (REGLIST_HI_ST), ')', 0 } },
3317 & fmt_stm1, { 0x8f00 },
3318 (PTR) & fmt_stm1_ops[0],
3319 { 0, 0, { 0 } }
3320 },
3321 /* enter $u10 */
3322 {
3323 { 1, 1, 1, 1 },
3324 FR30_INSN_ENTER, "enter", "enter",
3325 { { MNEM, ' ', OP (U10), 0 } },
3326 & fmt_enter, { 0xf00 },
3327 (PTR) & fmt_enter_ops[0],
3328 { 0, 0, { 0 } }
3329 },
3330 /* leave */
3331 {
3332 { 1, 1, 1, 1 },
3333 FR30_INSN_LEAVE, "leave", "leave",
3334 { { MNEM, 0 } },
3335 & fmt_leave, { 0x9f90 },
3336 (PTR) & fmt_leave_ops[0],
3337 { 0, 0, { 0 } }
3338 },
3339 /* xchb @$Rj,$Ri */
3340 {
3341 { 1, 1, 1, 1 },
3342 FR30_INSN_XCHB, "xchb", "xchb",
3343 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
3344 & fmt_xchb, { 0x8a00 },
3345 (PTR) & fmt_xchb_ops[0],
3346 { 0, 0, { 0 } }
3347 },
3348 };
3349
3350 #undef A
3351 #undef MNEM
3352 #undef OP
3353
3354 static const CGEN_INSN_TABLE insn_table =
3355 {
3356 & fr30_cgen_insn_table_entries[0],
3357 sizeof (CGEN_INSN),
3358 MAX_INSNS,
3359 NULL
3360 };
3361
3362 /* Formats for ALIAS macro-insns. */
3363
3364 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
3365
3366 static const CGEN_IFMT fmt_ldi8m = {
3367 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
3368 };
3369
3370 static const CGEN_IFMT fmt_ldi20m = {
3371 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
3372 };
3373
3374 static const CGEN_IFMT fmt_ldi32m = {
3375 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
3376 };
3377
3378 #undef F
3379
3380 /* Each non-simple macro entry points to an array of expansion possibilities. */
3381
3382 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
3383 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
3384 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
3385
3386 /* The macro instruction table. */
3387
3388 static const CGEN_INSN macro_insn_table_entries[] =
3389 {
3390 /* ldi8 $i8,$Ri */
3391 {
3392 { 1, 1, 1, 1 },
3393 -1, "ldi8m", "ldi8",
3394 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
3395 & fmt_ldi8m, { 0xc000 },
3396 (PTR) 0,
3397 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3398 },
3399 /* ldi20 $i20,$Ri */
3400 {
3401 { 1, 1, 1, 1 },
3402 -1, "ldi20m", "ldi20",
3403 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
3404 & fmt_ldi20m, { 0x9b00 },
3405 (PTR) 0,
3406 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3407 },
3408 /* ldi32 $i32,$Ri */
3409 {
3410 { 1, 1, 1, 1 },
3411 -1, "ldi32m", "ldi32",
3412 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
3413 & fmt_ldi32m, { 0x9f80 },
3414 (PTR) 0,
3415 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3416 },
3417 };
3418
3419 #undef A
3420 #undef MNEM
3421 #undef OP
3422
3423 static const CGEN_INSN_TABLE macro_insn_table =
3424 {
3425 & macro_insn_table_entries[0],
3426 sizeof (CGEN_INSN),
3427 (sizeof (macro_insn_table_entries) /
3428 sizeof (macro_insn_table_entries[0])),
3429 NULL
3430 };
3431
3432 static void
3433 init_tables ()
3434 {
3435 }
3436
3437 /* Return non-zero if INSN is to be added to the hash table.
3438 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
3439
3440 static int
3441 asm_hash_insn_p (insn)
3442 const CGEN_INSN * insn;
3443 {
3444 return CGEN_ASM_HASH_P (insn);
3445 }
3446
3447 static int
3448 dis_hash_insn_p (insn)
3449 const CGEN_INSN * insn;
3450 {
3451 /* If building the hash table and the NO-DIS attribute is present,
3452 ignore. */
3453 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
3454 return 0;
3455 return CGEN_DIS_HASH_P (insn);
3456 }
3457
3458 /* The result is the hash value of the insn.
3459 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
3460
3461 static unsigned int
3462 asm_hash_insn (mnem)
3463 const char * mnem;
3464 {
3465 return CGEN_ASM_HASH (mnem);
3466 }
3467
3468 /* BUF is a pointer to the insn's bytes in target order.
3469 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
3470 host order. */
3471
3472 static unsigned int
3473 dis_hash_insn (buf, value)
3474 const char * buf;
3475 CGEN_INSN_INT value;
3476 {
3477 return CGEN_DIS_HASH (buf, value);
3478 }
3479
3480 /* Initialize an opcode table and return a descriptor.
3481 It's much like opening a file, and must be the first function called. */
3482
3483 CGEN_OPCODE_DESC
3484 fr30_cgen_opcode_open (mach, endian)
3485 int mach;
3486 enum cgen_endian endian;
3487 {
3488 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
3489 static int init_p;
3490
3491 if (! init_p)
3492 {
3493 init_tables ();
3494 init_p = 1;
3495 }
3496
3497 memset (table, 0, sizeof (*table));
3498
3499 CGEN_OPCODE_MACH (table) = mach;
3500 CGEN_OPCODE_ENDIAN (table) = endian;
3501 /* FIXME: for the sparc case we can determine insn-endianness statically.
3502 The worry here is where both data and insn endian can be independently
3503 chosen, in which case this function will need another argument.
3504 Actually, will want to allow for more arguments in the future anyway. */
3505 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
3506
3507 CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
3508
3509 CGEN_OPCODE_IFLD_TABLE (table) = & fr30_cgen_ifld_table[0];
3510
3511 CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
3512
3513 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
3514
3515 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
3516
3517 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
3518 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
3519 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
3520
3521 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
3522 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
3523 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
3524
3525 return (CGEN_OPCODE_DESC) table;
3526 }
3527
3528 /* Close an opcode table. */
3529
3530 void
3531 fr30_cgen_opcode_close (desc)
3532 CGEN_OPCODE_DESC desc;
3533 {
3534 free (desc);
3535 }
3536
3537 /* Getting values from cgen_fields is handled by a collection of functions.
3538 They are distinguished by the type of the VALUE argument they return.
3539 TODO: floating point, inlining support, remove cases where result type
3540 not appropriate. */
3541
3542 int
3543 fr30_cgen_get_int_operand (opindex, fields)
3544 int opindex;
3545 const CGEN_FIELDS * fields;
3546 {
3547 int value;
3548
3549 switch (opindex)
3550 {
3551 case FR30_OPERAND_RI :
3552 value = fields->f_Ri;
3553 break;
3554 case FR30_OPERAND_RJ :
3555 value = fields->f_Rj;
3556 break;
3557 case FR30_OPERAND_RIC :
3558 value = fields->f_Ric;
3559 break;
3560 case FR30_OPERAND_RJC :
3561 value = fields->f_Rjc;
3562 break;
3563 case FR30_OPERAND_CRI :
3564 value = fields->f_CRi;
3565 break;
3566 case FR30_OPERAND_CRJ :
3567 value = fields->f_CRj;
3568 break;
3569 case FR30_OPERAND_RS1 :
3570 value = fields->f_Rs1;
3571 break;
3572 case FR30_OPERAND_RS2 :
3573 value = fields->f_Rs2;
3574 break;
3575 case FR30_OPERAND_R13 :
3576 value = fields->f_nil;
3577 break;
3578 case FR30_OPERAND_R14 :
3579 value = fields->f_nil;
3580 break;
3581 case FR30_OPERAND_R15 :
3582 value = fields->f_nil;
3583 break;
3584 case FR30_OPERAND_PS :
3585 value = fields->f_nil;
3586 break;
3587 case FR30_OPERAND_U4 :
3588 value = fields->f_u4;
3589 break;
3590 case FR30_OPERAND_U4C :
3591 value = fields->f_u4c;
3592 break;
3593 case FR30_OPERAND_U8 :
3594 value = fields->f_u8;
3595 break;
3596 case FR30_OPERAND_I8 :
3597 value = fields->f_i8;
3598 break;
3599 case FR30_OPERAND_UDISP6 :
3600 value = fields->f_udisp6;
3601 break;
3602 case FR30_OPERAND_DISP8 :
3603 value = fields->f_disp8;
3604 break;
3605 case FR30_OPERAND_DISP9 :
3606 value = fields->f_disp9;
3607 break;
3608 case FR30_OPERAND_DISP10 :
3609 value = fields->f_disp10;
3610 break;
3611 case FR30_OPERAND_S10 :
3612 value = fields->f_s10;
3613 break;
3614 case FR30_OPERAND_U10 :
3615 value = fields->f_u10;
3616 break;
3617 case FR30_OPERAND_I32 :
3618 value = fields->f_i32;
3619 break;
3620 case FR30_OPERAND_M4 :
3621 value = fields->f_m4;
3622 break;
3623 case FR30_OPERAND_I20 :
3624 value = fields->f_i20;
3625 break;
3626 case FR30_OPERAND_DIR8 :
3627 value = fields->f_dir8;
3628 break;
3629 case FR30_OPERAND_DIR9 :
3630 value = fields->f_dir9;
3631 break;
3632 case FR30_OPERAND_DIR10 :
3633 value = fields->f_dir10;
3634 break;
3635 case FR30_OPERAND_LABEL9 :
3636 value = fields->f_rel9;
3637 break;
3638 case FR30_OPERAND_LABEL12 :
3639 value = fields->f_rel12;
3640 break;
3641 case FR30_OPERAND_REGLIST_LOW_LD :
3642 value = fields->f_reglist_low_ld;
3643 break;
3644 case FR30_OPERAND_REGLIST_HI_LD :
3645 value = fields->f_reglist_hi_ld;
3646 break;
3647 case FR30_OPERAND_REGLIST_LOW_ST :
3648 value = fields->f_reglist_low_st;
3649 break;
3650 case FR30_OPERAND_REGLIST_HI_ST :
3651 value = fields->f_reglist_hi_st;
3652 break;
3653 case FR30_OPERAND_CC :
3654 value = fields->f_cc;
3655 break;
3656 case FR30_OPERAND_CCC :
3657 value = fields->f_ccc;
3658 break;
3659
3660 default :
3661 /* xgettext:c-format */
3662 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
3663 opindex);
3664 abort ();
3665 }
3666
3667 return value;
3668 }
3669
3670 bfd_vma
3671 fr30_cgen_get_vma_operand (opindex, fields)
3672 int opindex;
3673 const CGEN_FIELDS * fields;
3674 {
3675 bfd_vma value;
3676
3677 switch (opindex)
3678 {
3679 case FR30_OPERAND_RI :
3680 value = fields->f_Ri;
3681 break;
3682 case FR30_OPERAND_RJ :
3683 value = fields->f_Rj;
3684 break;
3685 case FR30_OPERAND_RIC :
3686 value = fields->f_Ric;
3687 break;
3688 case FR30_OPERAND_RJC :
3689 value = fields->f_Rjc;
3690 break;
3691 case FR30_OPERAND_CRI :
3692 value = fields->f_CRi;
3693 break;
3694 case FR30_OPERAND_CRJ :
3695 value = fields->f_CRj;
3696 break;
3697 case FR30_OPERAND_RS1 :
3698 value = fields->f_Rs1;
3699 break;
3700 case FR30_OPERAND_RS2 :
3701 value = fields->f_Rs2;
3702 break;
3703 case FR30_OPERAND_R13 :
3704 value = fields->f_nil;
3705 break;
3706 case FR30_OPERAND_R14 :
3707 value = fields->f_nil;
3708 break;
3709 case FR30_OPERAND_R15 :
3710 value = fields->f_nil;
3711 break;
3712 case FR30_OPERAND_PS :
3713 value = fields->f_nil;
3714 break;
3715 case FR30_OPERAND_U4 :
3716 value = fields->f_u4;
3717 break;
3718 case FR30_OPERAND_U4C :
3719 value = fields->f_u4c;
3720 break;
3721 case FR30_OPERAND_U8 :
3722 value = fields->f_u8;
3723 break;
3724 case FR30_OPERAND_I8 :
3725 value = fields->f_i8;
3726 break;
3727 case FR30_OPERAND_UDISP6 :
3728 value = fields->f_udisp6;
3729 break;
3730 case FR30_OPERAND_DISP8 :
3731 value = fields->f_disp8;
3732 break;
3733 case FR30_OPERAND_DISP9 :
3734 value = fields->f_disp9;
3735 break;
3736 case FR30_OPERAND_DISP10 :
3737 value = fields->f_disp10;
3738 break;
3739 case FR30_OPERAND_S10 :
3740 value = fields->f_s10;
3741 break;
3742 case FR30_OPERAND_U10 :
3743 value = fields->f_u10;
3744 break;
3745 case FR30_OPERAND_I32 :
3746 value = fields->f_i32;
3747 break;
3748 case FR30_OPERAND_M4 :
3749 value = fields->f_m4;
3750 break;
3751 case FR30_OPERAND_I20 :
3752 value = fields->f_i20;
3753 break;
3754 case FR30_OPERAND_DIR8 :
3755 value = fields->f_dir8;
3756 break;
3757 case FR30_OPERAND_DIR9 :
3758 value = fields->f_dir9;
3759 break;
3760 case FR30_OPERAND_DIR10 :
3761 value = fields->f_dir10;
3762 break;
3763 case FR30_OPERAND_LABEL9 :
3764 value = fields->f_rel9;
3765 break;
3766 case FR30_OPERAND_LABEL12 :
3767 value = fields->f_rel12;
3768 break;
3769 case FR30_OPERAND_REGLIST_LOW_LD :
3770 value = fields->f_reglist_low_ld;
3771 break;
3772 case FR30_OPERAND_REGLIST_HI_LD :
3773 value = fields->f_reglist_hi_ld;
3774 break;
3775 case FR30_OPERAND_REGLIST_LOW_ST :
3776 value = fields->f_reglist_low_st;
3777 break;
3778 case FR30_OPERAND_REGLIST_HI_ST :
3779 value = fields->f_reglist_hi_st;
3780 break;
3781 case FR30_OPERAND_CC :
3782 value = fields->f_cc;
3783 break;
3784 case FR30_OPERAND_CCC :
3785 value = fields->f_ccc;
3786 break;
3787
3788 default :
3789 /* xgettext:c-format */
3790 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
3791 opindex);
3792 abort ();
3793 }
3794
3795 return value;
3796 }
3797
3798 /* Stuffing values in cgen_fields is handled by a collection of functions.
3799 They are distinguished by the type of the VALUE argument they accept.
3800 TODO: floating point, inlining support, remove cases where argument type
3801 not appropriate. */
3802
3803 void
3804 fr30_cgen_set_int_operand (opindex, fields, value)
3805 int opindex;
3806 CGEN_FIELDS * fields;
3807 int value;
3808 {
3809 switch (opindex)
3810 {
3811 case FR30_OPERAND_RI :
3812 fields->f_Ri = value;
3813 break;
3814 case FR30_OPERAND_RJ :
3815 fields->f_Rj = value;
3816 break;
3817 case FR30_OPERAND_RIC :
3818 fields->f_Ric = value;
3819 break;
3820 case FR30_OPERAND_RJC :
3821 fields->f_Rjc = value;
3822 break;
3823 case FR30_OPERAND_CRI :
3824 fields->f_CRi = value;
3825 break;
3826 case FR30_OPERAND_CRJ :
3827 fields->f_CRj = value;
3828 break;
3829 case FR30_OPERAND_RS1 :
3830 fields->f_Rs1 = value;
3831 break;
3832 case FR30_OPERAND_RS2 :
3833 fields->f_Rs2 = value;
3834 break;
3835 case FR30_OPERAND_R13 :
3836 fields->f_nil = value;
3837 break;
3838 case FR30_OPERAND_R14 :
3839 fields->f_nil = value;
3840 break;
3841 case FR30_OPERAND_R15 :
3842 fields->f_nil = value;
3843 break;
3844 case FR30_OPERAND_PS :
3845 fields->f_nil = value;
3846 break;
3847 case FR30_OPERAND_U4 :
3848 fields->f_u4 = value;
3849 break;
3850 case FR30_OPERAND_U4C :
3851 fields->f_u4c = value;
3852 break;
3853 case FR30_OPERAND_U8 :
3854 fields->f_u8 = value;
3855 break;
3856 case FR30_OPERAND_I8 :
3857 fields->f_i8 = value;
3858 break;
3859 case FR30_OPERAND_UDISP6 :
3860 fields->f_udisp6 = value;
3861 break;
3862 case FR30_OPERAND_DISP8 :
3863 fields->f_disp8 = value;
3864 break;
3865 case FR30_OPERAND_DISP9 :
3866 fields->f_disp9 = value;
3867 break;
3868 case FR30_OPERAND_DISP10 :
3869 fields->f_disp10 = value;
3870 break;
3871 case FR30_OPERAND_S10 :
3872 fields->f_s10 = value;
3873 break;
3874 case FR30_OPERAND_U10 :
3875 fields->f_u10 = value;
3876 break;
3877 case FR30_OPERAND_I32 :
3878 fields->f_i32 = value;
3879 break;
3880 case FR30_OPERAND_M4 :
3881 fields->f_m4 = value;
3882 break;
3883 case FR30_OPERAND_I20 :
3884 fields->f_i20 = value;
3885 break;
3886 case FR30_OPERAND_DIR8 :
3887 fields->f_dir8 = value;
3888 break;
3889 case FR30_OPERAND_DIR9 :
3890 fields->f_dir9 = value;
3891 break;
3892 case FR30_OPERAND_DIR10 :
3893 fields->f_dir10 = value;
3894 break;
3895 case FR30_OPERAND_LABEL9 :
3896 fields->f_rel9 = value;
3897 break;
3898 case FR30_OPERAND_LABEL12 :
3899 fields->f_rel12 = value;
3900 break;
3901 case FR30_OPERAND_REGLIST_LOW_LD :
3902 fields->f_reglist_low_ld = value;
3903 break;
3904 case FR30_OPERAND_REGLIST_HI_LD :
3905 fields->f_reglist_hi_ld = value;
3906 break;
3907 case FR30_OPERAND_REGLIST_LOW_ST :
3908 fields->f_reglist_low_st = value;
3909 break;
3910 case FR30_OPERAND_REGLIST_HI_ST :
3911 fields->f_reglist_hi_st = value;
3912 break;
3913 case FR30_OPERAND_CC :
3914 fields->f_cc = value;
3915 break;
3916 case FR30_OPERAND_CCC :
3917 fields->f_ccc = value;
3918 break;
3919
3920 default :
3921 /* xgettext:c-format */
3922 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
3923 opindex);
3924 abort ();
3925 }
3926 }
3927
3928 void
3929 fr30_cgen_set_vma_operand (opindex, fields, value)
3930 int opindex;
3931 CGEN_FIELDS * fields;
3932 bfd_vma value;
3933 {
3934 switch (opindex)
3935 {
3936 case FR30_OPERAND_RI :
3937 fields->f_Ri = value;
3938 break;
3939 case FR30_OPERAND_RJ :
3940 fields->f_Rj = value;
3941 break;
3942 case FR30_OPERAND_RIC :
3943 fields->f_Ric = value;
3944 break;
3945 case FR30_OPERAND_RJC :
3946 fields->f_Rjc = value;
3947 break;
3948 case FR30_OPERAND_CRI :
3949 fields->f_CRi = value;
3950 break;
3951 case FR30_OPERAND_CRJ :
3952 fields->f_CRj = value;
3953 break;
3954 case FR30_OPERAND_RS1 :
3955 fields->f_Rs1 = value;
3956 break;
3957 case FR30_OPERAND_RS2 :
3958 fields->f_Rs2 = value;
3959 break;
3960 case FR30_OPERAND_R13 :
3961 fields->f_nil = value;
3962 break;
3963 case FR30_OPERAND_R14 :
3964 fields->f_nil = value;
3965 break;
3966 case FR30_OPERAND_R15 :
3967 fields->f_nil = value;
3968 break;
3969 case FR30_OPERAND_PS :
3970 fields->f_nil = value;
3971 break;
3972 case FR30_OPERAND_U4 :
3973 fields->f_u4 = value;
3974 break;
3975 case FR30_OPERAND_U4C :
3976 fields->f_u4c = value;
3977 break;
3978 case FR30_OPERAND_U8 :
3979 fields->f_u8 = value;
3980 break;
3981 case FR30_OPERAND_I8 :
3982 fields->f_i8 = value;
3983 break;
3984 case FR30_OPERAND_UDISP6 :
3985 fields->f_udisp6 = value;
3986 break;
3987 case FR30_OPERAND_DISP8 :
3988 fields->f_disp8 = value;
3989 break;
3990 case FR30_OPERAND_DISP9 :
3991 fields->f_disp9 = value;
3992 break;
3993 case FR30_OPERAND_DISP10 :
3994 fields->f_disp10 = value;
3995 break;
3996 case FR30_OPERAND_S10 :
3997 fields->f_s10 = value;
3998 break;
3999 case FR30_OPERAND_U10 :
4000 fields->f_u10 = value;
4001 break;
4002 case FR30_OPERAND_I32 :
4003 fields->f_i32 = value;
4004 break;
4005 case FR30_OPERAND_M4 :
4006 fields->f_m4 = value;
4007 break;
4008 case FR30_OPERAND_I20 :
4009 fields->f_i20 = value;
4010 break;
4011 case FR30_OPERAND_DIR8 :
4012 fields->f_dir8 = value;
4013 break;
4014 case FR30_OPERAND_DIR9 :
4015 fields->f_dir9 = value;
4016 break;
4017 case FR30_OPERAND_DIR10 :
4018 fields->f_dir10 = value;
4019 break;
4020 case FR30_OPERAND_LABEL9 :
4021 fields->f_rel9 = value;
4022 break;
4023 case FR30_OPERAND_LABEL12 :
4024 fields->f_rel12 = value;
4025 break;
4026 case FR30_OPERAND_REGLIST_LOW_LD :
4027 fields->f_reglist_low_ld = value;
4028 break;
4029 case FR30_OPERAND_REGLIST_HI_LD :
4030 fields->f_reglist_hi_ld = value;
4031 break;
4032 case FR30_OPERAND_REGLIST_LOW_ST :
4033 fields->f_reglist_low_st = value;
4034 break;
4035 case FR30_OPERAND_REGLIST_HI_ST :
4036 fields->f_reglist_hi_st = value;
4037 break;
4038 case FR30_OPERAND_CC :
4039 fields->f_cc = value;
4040 break;
4041 case FR30_OPERAND_CCC :
4042 fields->f_ccc = value;
4043 break;
4044
4045 default :
4046 /* xgettext:c-format */
4047 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
4048 opindex);
4049 abort ();
4050 }
4051 }
4052
GDB Binutils - Deliverables
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