opcodes/fr30-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS USED TO GENERATE fr30-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software Foundation, Inc.,
  22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "fr30-opc.h"
  31 #include "opintl.h"
  32
  33 /* The hash functions are recorded here to help keep assembler code out of
  34    the disassembler and vice versa.  */
  35
  36 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
  37 static unsigned int asm_hash_insn PARAMS ((const char *));
  38 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
  39 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
  40
  41 /* Look up instruction INSN_VALUE and extract its fields.
  42    INSN, if non-null, is the insn table entry.
  43    Otherwise INSN_VALUE is examined to compute it.
  44    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
  45    0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
  46    If INSN != NULL, LENGTH must be valid.
  47    ALIAS_P is non-zero if alias insns are to be included in the search.
  48
  49    The result is a pointer to the insn table entry, or NULL if the instruction
  50    wasn't recognized.  */
  51
  52 const CGEN_INSN *
  53 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
  54      CGEN_OPCODE_DESC od;
  55      const CGEN_INSN *insn;
  56      CGEN_INSN_BYTES insn_value;
  57      int length;
  58      CGEN_FIELDS *fields;
  59      int alias_p;
  60 {
  61   unsigned char buf[CGEN_MAX_INSN_SIZE];
  62   unsigned char *bufp;
  63   CGEN_INSN_INT base_insn;
  64 #if CGEN_INT_INSN_P
  65   CGEN_EXTRACT_INFO *info = NULL;
  66 #else
  67   CGEN_EXTRACT_INFO ex_info;
  68   CGEN_EXTRACT_INFO *info = &ex_info;
  69 #endif
  70
  71 #if CGEN_INT_INSN_P
  72   cgen_put_insn_value (od, buf, length, insn_value);
  73   bufp = buf;
  74   base_insn = insn_value; /*???*/
  75 #else
  76   ex_info.dis_info = NULL;
  77   ex_info.insn_bytes = insn_value;
  78   ex_info.valid = -1;
  79   base_insn = cgen_get_insn_value (od, buf, length);
  80   bufp = insn_value;
  81 #endif
  82
  83   if (!insn)
  84     {
  85       const CGEN_INSN_LIST *insn_list;
  86
  87       /* The instructions are stored in hash lists.
  88          Pick the first one and keep trying until we find the right one.  */
  89
  90       insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
  91       while (insn_list != NULL)
  92         {
  93           insn = insn_list->insn;
  94
  95           if (alias_p
  96               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
  97             {
  98               /* Basic bit mask must be correct.  */
  99               /* ??? May wish to allow target to defer this check until the
 100                  extract handler.  */
 101               if ((base_insn & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
 102                 {
 103                   /* ??? 0 is passed for `pc' */
 104                   int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
 105                                                            base_insn, fields,
 106                                                            (bfd_vma) 0);
 107                   if (elength > 0)
 108                     {
 109                       /* sanity check */
 110                       if (length != 0 && length != elength)
 111                         abort ();
 112                       return insn;
 113                     }
 114                 }
 115             }
 116
 117           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 118         }
 119     }
 120   else
 121     {
 122       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 123       if (! alias_p
 124           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 125         abort ();
 126       /* Sanity check: length must be correct.  */
 127       if (length != CGEN_INSN_BITSIZE (insn))
 128         abort ();
 129
 130       /* ??? 0 is passed for `pc' */
 131       length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
 132                                           (bfd_vma) 0);
 133       /* Sanity check: must succeed.
 134          Could relax this later if it ever proves useful.  */
 135       if (length == 0)
 136         abort ();
 137       return insn;
 138     }
 139
 140   return NULL;
 141 }
 142
 143 /* Fill in the operand instances used by INSN whose operands are FIELDS.
 144    INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
 145    in.  */
 146
 147 void
 148 fr30_cgen_get_insn_operands (od, insn, fields, indices)
 149      CGEN_OPCODE_DESC od;
 150      const CGEN_INSN * insn;
 151      const CGEN_FIELDS * fields;
 152      int *indices;
 153 {
 154   const CGEN_OPERAND_INSTANCE *opinst;
 155   int i;
 156
 157   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 158        opinst != NULL
 159          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 160        ++i, ++opinst)
 161     {
 162       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 163       if (op == NULL)
 164         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 165       else
 166         indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
 167                                                   fields);
 168     }
 169 }
 170
 171 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
 172    isn't known.
 173    The INSN, INSN_VALUE, and LENGTH arguments are passed to
 174    fr30_cgen_lookup_insn unchanged.
 175
 176    The result is the insn table entry or NULL if the instruction wasn't
 177    recognized.  */
 178
 179 const CGEN_INSN *
 180 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
 181      CGEN_OPCODE_DESC od;
 182      const CGEN_INSN *insn;
 183      CGEN_INSN_BYTES insn_value;
 184      int length;
 185      int *indices;
 186 {
 187   CGEN_FIELDS fields;
 188
 189   /* Pass non-zero for ALIAS_P only if INSN != NULL.
 190      If INSN == NULL, we want a real insn.  */
 191   insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
 192                                   insn != NULL);
 193   if (! insn)
 194     return NULL;
 195
 196   fr30_cgen_get_insn_operands (od, insn, &fields, indices);
 197   return insn;
 198 }
 199 /* Attributes.  */
 200
 201 static const CGEN_ATTR_ENTRY MACH_attr[] =
 202 {
 203   { "base", MACH_BASE },
 204   { "fr30", MACH_FR30 },
 205   { "max", MACH_MAX },
 206   { 0, 0 }
 207 };
 208
 209 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
 210 {
 211   { "CACHE-ADDR", NULL },
 212   { "FUN-ACCESS", NULL },
 213   { "PC", NULL },
 214   { "PROFILE", NULL },
 215   { 0, 0 }
 216 };
 217
 218 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
 219 {
 220   { "ABS-ADDR", NULL },
 221   { "HASH-PREFIX", NULL },
 222   { "NEGATIVE", NULL },
 223   { "PCREL-ADDR", NULL },
 224   { "RELAX", NULL },
 225   { "SEM-ONLY", NULL },
 226   { "SIGN-OPT", NULL },
 227   { "SIGNED", NULL },
 228   { "UNSIGNED", NULL },
 229   { 0, 0 }
 230 };
 231
 232 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
 233 {
 234   { "ALIAS", NULL },
 235   { "COND-CTI", NULL },
 236   { "NO-DIS", NULL },
 237   { "RELAX", NULL },
 238   { "RELAXABLE", NULL },
 239   { "SKIP-CTI", NULL },
 240   { "UNCOND-CTI", NULL },
 241   { "VIRTUAL", NULL },
 242   { 0, 0 }
 243 };
 244
 245 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
 246 {
 247   { "ac", 13 },
 248   { "fp", 14 },
 249   { "sp", 15 },
 250   { "r0", 0 },
 251   { "r1", 1 },
 252   { "r2", 2 },
 253   { "r3", 3 },
 254   { "r4", 4 },
 255   { "r5", 5 },
 256   { "r6", 6 },
 257   { "r7", 7 },
 258   { "r8", 8 },
 259   { "r9", 9 },
 260   { "r10", 10 },
 261   { "r11", 11 },
 262   { "r12", 12 },
 263   { "r13", 13 },
 264   { "r14", 14 },
 265   { "r15", 15 }
 266 };
 267
 268 CGEN_KEYWORD fr30_cgen_opval_h_gr =
 269 {
 270   & fr30_cgen_opval_h_gr_entries[0],
 271   19
 272 };
 273
 274 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
 275 {
 276   { "cr0", 0 },
 277   { "cr1", 1 },
 278   { "cr2", 2 },
 279   { "cr3", 3 },
 280   { "cr4", 4 },
 281   { "cr5", 5 },
 282   { "cr6", 6 },
 283   { "cr7", 7 },
 284   { "cr8", 8 },
 285   { "cr9", 9 },
 286   { "cr10", 10 },
 287   { "cr11", 11 },
 288   { "cr12", 12 },
 289   { "cr13", 13 },
 290   { "cr14", 14 },
 291   { "cr15", 15 }
 292 };
 293
 294 CGEN_KEYWORD fr30_cgen_opval_h_cr =
 295 {
 296   & fr30_cgen_opval_h_cr_entries[0],
 297   16
 298 };
 299
 300 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
 301 {
 302   { "tbr", 0 },
 303   { "rp", 1 },
 304   { "ssp", 2 },
 305   { "usp", 3 },
 306   { "mdh", 4 },
 307   { "mdl", 5 }
 308 };
 309
 310 CGEN_KEYWORD fr30_cgen_opval_h_dr =
 311 {
 312   & fr30_cgen_opval_h_dr_entries[0],
 313   6
 314 };
 315
 316 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
 317 {
 318   { "ps", 0 }
 319 };
 320
 321 CGEN_KEYWORD fr30_cgen_opval_h_ps =
 322 {
 323   & fr30_cgen_opval_h_ps_entries[0],
 324   1
 325 };
 326
 327 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
 328 {
 329   { "r13", 0 }
 330 };
 331
 332 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
 333 {
 334   & fr30_cgen_opval_h_r13_entries[0],
 335   1
 336 };
 337
 338 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
 339 {
 340   { "r14", 0 }
 341 };
 342
 343 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
 344 {
 345   & fr30_cgen_opval_h_r14_entries[0],
 346   1
 347 };
 348
 349 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
 350 {
 351   { "r15", 0 }
 352 };
 353
 354 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
 355 {
 356   & fr30_cgen_opval_h_r15_entries[0],
 357   1
 358 };
 359
 360
 361 /* The hardware table.  */
 362
 363 #define HW_ENT(n) fr30_cgen_hw_entries[n]
 364 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
 365 {
 366   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
 367   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 368   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 369   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 370   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 371   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 372   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
 373   { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
 374   { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0, { 0 } } },
 375   { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
 376   { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
 377   { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
 378   { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
 379   { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 380   { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 381   { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 382   { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 383   { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 384   { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 385   { 0 }
 386 };
 387
 388 /* The operand table.  */
 389
 390 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
 391 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
 392
 393 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
 394 {
 395 /* pc: program counter */
 396   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 397     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 398 /* Ri: destination register */
 399   { "Ri", & HW_ENT (HW_H_GR), 12, 4,
 400     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 401 /* Rj: source register */
 402   { "Rj", & HW_ENT (HW_H_GR), 8, 4,
 403     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 404 /* Ric: target register coproc insn */
 405   { "Ric", & HW_ENT (HW_H_GR), 28, 4,
 406     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 407 /* Rjc: source register coproc insn */
 408   { "Rjc", & HW_ENT (HW_H_GR), 24, 4,
 409     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 410 /* CRi: coprocessor register */
 411   { "CRi", & HW_ENT (HW_H_CR), 28, 4,
 412     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 413 /* CRj: coprocessor register */
 414   { "CRj", & HW_ENT (HW_H_CR), 24, 4,
 415     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 416 /* Rs1: dedicated register */
 417   { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
 418     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 419 /* Rs2: dedicated register */
 420   { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
 421     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 422 /* R13: General Register 13 */
 423   { "R13", & HW_ENT (HW_H_R13), 0, 0,
 424     { 0, 0, { 0 } }  },
 425 /* R14: General Register 14 */
 426   { "R14", & HW_ENT (HW_H_R14), 0, 0,
 427     { 0, 0, { 0 } }  },
 428 /* R15: General Register 15 */
 429   { "R15", & HW_ENT (HW_H_R15), 0, 0,
 430     { 0, 0, { 0 } }  },
 431 /* ps: Program Status register */
 432   { "ps", & HW_ENT (HW_H_PS), 0, 0,
 433     { 0, 0, { 0 } }  },
 434 /* u4: 4  bit unsigned immediate */
 435   { "u4", & HW_ENT (HW_H_UINT), 8, 4,
 436     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 437 /* u4c: 4  bit unsigned immediate */
 438   { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
 439     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 440 /* m4: 4  bit negative immediate */
 441   { "m4", & HW_ENT (HW_H_UINT), 8, 4,
 442     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 443 /* u8: 8  bit unsigned immediate */
 444   { "u8", & HW_ENT (HW_H_UINT), 8, 8,
 445     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 446 /* i8: 8  bit unsigned immediate */
 447   { "i8", & HW_ENT (HW_H_UINT), 4, 8,
 448     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 449 /* udisp6: 6  bit unsigned immediate */
 450   { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
 451     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 452 /* disp8: 8  bit signed   immediate */
 453   { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
 454     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 455 /* disp9: 9  bit signed   immediate */
 456   { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
 457     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 458 /* disp10: 10 bit signed   immediate */
 459   { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
 460     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 461 /* s10: 10 bit signed   immediate */
 462   { "s10", & HW_ENT (HW_H_SINT), 8, 8,
 463     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 464 /* u10: 10 bit unsigned immediate */
 465   { "u10", & HW_ENT (HW_H_UINT), 8, 8,
 466     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 467 /* i32: 32 bit immediate */
 468   { "i32", & HW_ENT (HW_H_UINT), 16, 32,
 469     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 470 /* dir8: 8  bit direct address */
 471   { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
 472     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 473 /* dir9: 9  bit direct address */
 474   { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
 475     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 476 /* dir10: 10 bit direct address */
 477   { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
 478     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 479 /* label9: 9  bit pc relative address */
 480   { "label9", & HW_ENT (HW_H_SINT), 8, 8,
 481     { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 482 /* label12: 12 bit pc relative address */
 483   { "label12", & HW_ENT (HW_H_SINT), 5, 11,
 484     { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 485 /* reglist_low: 8 bit register mask */
 486   { "reglist_low", & HW_ENT (HW_H_UINT), 8, 8,
 487     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 488 /* reglist_hi: 8 bit register mask */
 489   { "reglist_hi", & HW_ENT (HW_H_UINT), 8, 8,
 490     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 491 /* cc: condition codes */
 492   { "cc", & HW_ENT (HW_H_UINT), 4, 4,
 493     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 494 /* ccc: coprocessor calc */
 495   { "ccc", & HW_ENT (HW_H_UINT), 16, 8,
 496     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 497 /* nbit: negative  bit */
 498   { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
 499     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 500 /* vbit: overflow  bit */
 501   { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
 502     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 503 /* zbit: zero      bit */
 504   { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
 505     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 506 /* cbit: carry     bit */
 507   { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
 508     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 509 /* ibit: interrupt bit */
 510   { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
 511     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 512 /* sbit: stack     bit */
 513   { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
 514     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 515 };
 516
 517 /* Operand references.  */
 518
 519 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 520 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 521 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
 522
 523 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
 524   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 525   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 526   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 527   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 528   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 529   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 530   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 531   { 0 }
 532 };
 533
 534 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
 535   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 536   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
 537   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 538   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 539   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 540   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 541   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 542   { 0 }
 543 };
 544
 545 static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
 546   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 547   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
 548   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 549   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 550   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 551   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 552   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 553   { 0 }
 554 };
 555
 556 static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
 557   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 558   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 559   { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 560   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 561   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 562   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 563   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 564   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 565   { 0 }
 566 };
 567
 568 static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
 569   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 570   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 571   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 572   { 0 }
 573 };
 574
 575 static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
 576   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 577   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
 578   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 579   { 0 }
 580 };
 581
 582 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
 583   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 584   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
 585   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 586   { 0 }
 587 };
 588
 589 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
 590   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 591   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 592   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 593   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 594   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 595   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 596   { 0 }
 597 };
 598
 599 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
 600   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 601   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
 602   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 603   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 604   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 605   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 606   { 0 }
 607 };
 608
 609 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
 610   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 611   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
 612   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 613   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 614   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 615   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 616   { 0 }
 617 };
 618
 619 static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
 620   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 621   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 622   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 623   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 624   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 625   { 0 }
 626 };
 627
 628 static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
 629   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
 630   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
 631   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 632   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 633   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 634   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
 635   { 0 }
 636 };
 637
 638 static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
 639   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
 640   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
 641   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
 642   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 643   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 644   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
 645   { 0 }
 646 };
 647
 648 static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
 649   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
 650   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
 651   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
 652   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 653   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 654   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
 655   { 0 }
 656 };
 657
 658 static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
 659   { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
 660   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 661   { 0 }
 662 };
 663
 664 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
 665   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 666   { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_USI, & OP_ENT (RS1), 0, 0 },
 667   { 0 }
 668 };
 669
 670 static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
 671   { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, 0 },
 672   { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
 673   { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
 674   { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
 675   { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, 0 },
 676   { OUTPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, 0 },
 677   { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
 678   { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
 679   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
 680   { 0 }
 681 };
 682
 683 static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
 684   { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
 685   { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, COND_REF },
 686   { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
 687   { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 3, COND_REF },
 688   { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
 689   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
 690   { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, COND_REF },
 691   { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
 692   { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 3, COND_REF },
 693   { 0 }
 694 };
 695
 696 #undef INPUT
 697 #undef OUTPUT
 698 #undef COND_REF
 699
 700 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
 701 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
 702 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 703
 704 /* The instruction table.
 705    This is currently non-static because the simulator accesses it
 706    directly.  */
 707
 708 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
 709 {
 710   /* Special null first entry.
 711      A `num' value of zero is thus invalid.
 712      Also, the special `invalid' insn resides here.  */
 713   { { 0 }, 0 },
 714 /* add $Rj,$Ri */
 715   {
 716     { 1, 1, 1, 1 },
 717     FR30_INSN_ADD, "add", "add",
 718     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 719     { 16, 16, 0xff00 }, 0xa600,
 720     (PTR) & fmt_add_ops[0],
 721     { 0, 0, { 0 } }
 722   },
 723 /* add $u4,$Ri */
 724   {
 725     { 1, 1, 1, 1 },
 726     FR30_INSN_ADDI, "addi", "add",
 727     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 728     { 16, 16, 0xff00 }, 0xa400,
 729     (PTR) & fmt_addi_ops[0],
 730     { 0, 0, { 0 } }
 731   },
 732 /* add2 $m4,$Ri */
 733   {
 734     { 1, 1, 1, 1 },
 735     FR30_INSN_ADD2, "add2", "add2",
 736     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 737     { 16, 16, 0xff00 }, 0xa500,
 738     (PTR) & fmt_add2_ops[0],
 739     { 0, 0, { 0 } }
 740   },
 741 /* addc $Rj,$Ri */
 742   {
 743     { 1, 1, 1, 1 },
 744     FR30_INSN_ADDC, "addc", "addc",
 745     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 746     { 16, 16, 0xff00 }, 0xa700,
 747     (PTR) & fmt_addc_ops[0],
 748     { 0, 0, { 0 } }
 749   },
 750 /* addn $Rj,$Ri */
 751   {
 752     { 1, 1, 1, 1 },
 753     FR30_INSN_ADDN, "addn", "addn",
 754     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 755     { 16, 16, 0xff00 }, 0xa200,
 756     (PTR) & fmt_addn_ops[0],
 757     { 0, 0, { 0 } }
 758   },
 759 /* addn $u4,$Ri */
 760   {
 761     { 1, 1, 1, 1 },
 762     FR30_INSN_ADDNI, "addni", "addn",
 763     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 764     { 16, 16, 0xff00 }, 0xa000,
 765     (PTR) & fmt_addni_ops[0],
 766     { 0, 0, { 0 } }
 767   },
 768 /* addn2 $m4,$Ri */
 769   {
 770     { 1, 1, 1, 1 },
 771     FR30_INSN_ADDN2, "addn2", "addn2",
 772     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 773     { 16, 16, 0xff00 }, 0xa100,
 774     (PTR) & fmt_addn2_ops[0],
 775     { 0, 0, { 0 } }
 776   },
 777 /* sub $Rj,$Ri */
 778   {
 779     { 1, 1, 1, 1 },
 780     FR30_INSN_SUB, "sub", "sub",
 781     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 782     { 16, 16, 0xff00 }, 0xac00,
 783     (PTR) & fmt_add_ops[0],
 784     { 0, 0, { 0 } }
 785   },
 786 /* subc $Rj,$Ri */
 787   {
 788     { 1, 1, 1, 1 },
 789     FR30_INSN_SUBC, "subc", "subc",
 790     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 791     { 16, 16, 0xff00 }, 0xad00,
 792     (PTR) & fmt_addc_ops[0],
 793     { 0, 0, { 0 } }
 794   },
 795 /* subn $Rj,$Ri */
 796   {
 797     { 1, 1, 1, 1 },
 798     FR30_INSN_SUBN, "subn", "subn",
 799     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 800     { 16, 16, 0xff00 }, 0xae00,
 801     (PTR) & fmt_addn_ops[0],
 802     { 0, 0, { 0 } }
 803   },
 804 /* cmp $Rj,$Ri */
 805   {
 806     { 1, 1, 1, 1 },
 807     FR30_INSN_CMP, "cmp", "cmp",
 808     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 809     { 16, 16, 0xff00 }, 0xaa00,
 810     (PTR) & fmt_cmp_ops[0],
 811     { 0, 0, { 0 } }
 812   },
 813 /* cmp $u4,$Ri */
 814   {
 815     { 1, 1, 1, 1 },
 816     FR30_INSN_CMPI, "cmpi", "cmp",
 817     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 818     { 16, 16, 0xff00 }, 0xa800,
 819     (PTR) & fmt_cmpi_ops[0],
 820     { 0, 0, { 0 } }
 821   },
 822 /* cmp2 $m4,$Ri */
 823   {
 824     { 1, 1, 1, 1 },
 825     FR30_INSN_CMP2, "cmp2", "cmp2",
 826     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 827     { 16, 16, 0xff00 }, 0xa900,
 828     (PTR) & fmt_cmp2_ops[0],
 829     { 0, 0, { 0 } }
 830   },
 831 /* and $Rj,$Ri */
 832   {
 833     { 1, 1, 1, 1 },
 834     FR30_INSN_AND, "and", "and",
 835     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 836     { 16, 16, 0xff00 }, 0x8200,
 837     (PTR) & fmt_and_ops[0],
 838     { 0, 0, { 0 } }
 839   },
 840 /* or $Rj,$Ri */
 841   {
 842     { 1, 1, 1, 1 },
 843     FR30_INSN_OR, "or", "or",
 844     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 845     { 16, 16, 0xff00 }, 0x9200,
 846     (PTR) & fmt_and_ops[0],
 847     { 0, 0, { 0 } }
 848   },
 849 /* eor $Rj,$Ri */
 850   {
 851     { 1, 1, 1, 1 },
 852     FR30_INSN_EOR, "eor", "eor",
 853     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 854     { 16, 16, 0xff00 }, 0x9a00,
 855     (PTR) & fmt_and_ops[0],
 856     { 0, 0, { 0 } }
 857   },
 858 /* and $Rj,@$Ri */
 859   {
 860     { 1, 1, 1, 1 },
 861     FR30_INSN_ANDM, "andm", "and",
 862     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 863     { 16, 16, 0xff00 }, 0x8400,
 864     (PTR) & fmt_andm_ops[0],
 865     { 0, 0, { 0 } }
 866   },
 867 /* andh $Rj,@$Ri */
 868   {
 869     { 1, 1, 1, 1 },
 870     FR30_INSN_ANDH, "andh", "andh",
 871     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 872     { 16, 16, 0xff00 }, 0x8500,
 873     (PTR) & fmt_andh_ops[0],
 874     { 0, 0, { 0 } }
 875   },
 876 /* andb $Rj,@$Ri */
 877   {
 878     { 1, 1, 1, 1 },
 879     FR30_INSN_ANDB, "andb", "andb",
 880     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 881     { 16, 16, 0xff00 }, 0x8600,
 882     (PTR) & fmt_andb_ops[0],
 883     { 0, 0, { 0 } }
 884   },
 885 /* or $Rj,@$Ri */
 886   {
 887     { 1, 1, 1, 1 },
 888     FR30_INSN_ORM, "orm", "or",
 889     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 890     { 16, 16, 0xff00 }, 0x9400,
 891     (PTR) & fmt_andm_ops[0],
 892     { 0, 0, { 0 } }
 893   },
 894 /* orh $Rj,@$Ri */
 895   {
 896     { 1, 1, 1, 1 },
 897     FR30_INSN_ORH, "orh", "orh",
 898     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 899     { 16, 16, 0xff00 }, 0x9500,
 900     (PTR) & fmt_andh_ops[0],
 901     { 0, 0, { 0 } }
 902   },
 903 /* orb $Rj,@$Ri */
 904   {
 905     { 1, 1, 1, 1 },
 906     FR30_INSN_ORB, "orb", "orb",
 907     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 908     { 16, 16, 0xff00 }, 0x9600,
 909     (PTR) & fmt_andb_ops[0],
 910     { 0, 0, { 0 } }
 911   },
 912 /* eor $Rj,@$Ri */
 913   {
 914     { 1, 1, 1, 1 },
 915     FR30_INSN_EORM, "eorm", "eor",
 916     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 917     { 16, 16, 0xff00 }, 0x9c00,
 918     (PTR) & fmt_andm_ops[0],
 919     { 0, 0, { 0 } }
 920   },
 921 /* eorh $Rj,@$Ri */
 922   {
 923     { 1, 1, 1, 1 },
 924     FR30_INSN_EORH, "eorh", "eorh",
 925     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 926     { 16, 16, 0xff00 }, 0x9d00,
 927     (PTR) & fmt_andh_ops[0],
 928     { 0, 0, { 0 } }
 929   },
 930 /* eorb $Rj,@$Ri */
 931   {
 932     { 1, 1, 1, 1 },
 933     FR30_INSN_EORB, "eorb", "eorb",
 934     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 935     { 16, 16, 0xff00 }, 0x9e00,
 936     (PTR) & fmt_andb_ops[0],
 937     { 0, 0, { 0 } }
 938   },
 939 /* bandl $u4,@$Ri */
 940   {
 941     { 1, 1, 1, 1 },
 942     FR30_INSN_BANDL, "bandl", "bandl",
 943     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 944     { 16, 16, 0xff00 }, 0x8000,
 945     (PTR) 0,
 946     { 0, 0, { 0 } }
 947   },
 948 /* borl $u4,@$Ri */
 949   {
 950     { 1, 1, 1, 1 },
 951     FR30_INSN_BORL, "borl", "borl",
 952     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 953     { 16, 16, 0xff00 }, 0x9000,
 954     (PTR) 0,
 955     { 0, 0, { 0 } }
 956   },
 957 /* beorl $u4,@$Ri */
 958   {
 959     { 1, 1, 1, 1 },
 960     FR30_INSN_BEORL, "beorl", "beorl",
 961     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 962     { 16, 16, 0xff00 }, 0x9800,
 963     (PTR) 0,
 964     { 0, 0, { 0 } }
 965   },
 966 /* bandh $u4,@$Ri */
 967   {
 968     { 1, 1, 1, 1 },
 969     FR30_INSN_BANDH, "bandh", "bandh",
 970     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 971     { 16, 16, 0xff00 }, 0x8100,
 972     (PTR) 0,
 973     { 0, 0, { 0 } }
 974   },
 975 /* borh $u4,@$Ri */
 976   {
 977     { 1, 1, 1, 1 },
 978     FR30_INSN_BORH, "borh", "borh",
 979     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 980     { 16, 16, 0xff00 }, 0x9100,
 981     (PTR) 0,
 982     { 0, 0, { 0 } }
 983   },
 984 /* beorh $u4,@$Ri */
 985   {
 986     { 1, 1, 1, 1 },
 987     FR30_INSN_BEORH, "beorh", "beorh",
 988     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 989     { 16, 16, 0xff00 }, 0x9900,
 990     (PTR) 0,
 991     { 0, 0, { 0 } }
 992   },
 993 /* btstl $u4,@$Ri */
 994   {
 995     { 1, 1, 1, 1 },
 996     FR30_INSN_BTSTL, "btstl", "btstl",
 997     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 998     { 16, 16, 0xff00 }, 0x8800,
 999     (PTR) 0,
1000     { 0, 0, { 0 } }
1001   },
1002 /* btsth $u4,@$Ri */
1003   {
1004     { 1, 1, 1, 1 },
1005     FR30_INSN_BTSTH, "btsth", "btsth",
1006     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1007     { 16, 16, 0xff00 }, 0x8900,
1008     (PTR) 0,
1009     { 0, 0, { 0 } }
1010   },
1011 /* mul $Rj,$Ri */
1012   {
1013     { 1, 1, 1, 1 },
1014     FR30_INSN_MUL, "mul", "mul",
1015     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1016     { 16, 16, 0xff00 }, 0xaf00,
1017     (PTR) 0,
1018     { 0, 0, { 0 } }
1019   },
1020 /* mulu $Rj,$Ri */
1021   {
1022     { 1, 1, 1, 1 },
1023     FR30_INSN_MULU, "mulu", "mulu",
1024     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1025     { 16, 16, 0xff00 }, 0xab00,
1026     (PTR) 0,
1027     { 0, 0, { 0 } }
1028   },
1029 /* mulh $Rj,$Ri */
1030   {
1031     { 1, 1, 1, 1 },
1032     FR30_INSN_MULH, "mulh", "mulh",
1033     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1034     { 16, 16, 0xff00 }, 0xbf00,
1035     (PTR) 0,
1036     { 0, 0, { 0 } }
1037   },
1038 /* muluh $Rj,$Ri */
1039   {
1040     { 1, 1, 1, 1 },
1041     FR30_INSN_MULUH, "muluh", "muluh",
1042     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1043     { 16, 16, 0xff00 }, 0xbb00,
1044     (PTR) 0,
1045     { 0, 0, { 0 } }
1046   },
1047 /* div0s $Ri */
1048   {
1049     { 1, 1, 1, 1 },
1050     FR30_INSN_DIV0S, "div0s", "div0s",
1051     { { MNEM, ' ', OP (RI), 0 } },
1052     { 16, 16, 0xfff0 }, 0x9740,
1053     (PTR) 0,
1054     { 0, 0, { 0 } }
1055   },
1056 /* div0u $Ri */
1057   {
1058     { 1, 1, 1, 1 },
1059     FR30_INSN_DIV0U, "div0u", "div0u",
1060     { { MNEM, ' ', OP (RI), 0 } },
1061     { 16, 16, 0xfff0 }, 0x9750,
1062     (PTR) 0,
1063     { 0, 0, { 0 } }
1064   },
1065 /* div1 $Ri */
1066   {
1067     { 1, 1, 1, 1 },
1068     FR30_INSN_DIV1, "div1", "div1",
1069     { { MNEM, ' ', OP (RI), 0 } },
1070     { 16, 16, 0xfff0 }, 0x9760,
1071     (PTR) 0,
1072     { 0, 0, { 0 } }
1073   },
1074 /* div2 $Ri */
1075   {
1076     { 1, 1, 1, 1 },
1077     FR30_INSN_DIV2, "div2", "div2",
1078     { { MNEM, ' ', OP (RI), 0 } },
1079     { 16, 16, 0xfff0 }, 0x9770,
1080     (PTR) 0,
1081     { 0, 0, { 0 } }
1082   },
1083 /* div3 */
1084   {
1085     { 1, 1, 1, 1 },
1086     FR30_INSN_DIV3, "div3", "div3",
1087     { { MNEM, 0 } },
1088     { 16, 16, 0xffff }, 0x9f60,
1089     (PTR) 0,
1090     { 0, 0, { 0 } }
1091   },
1092 /* div4s */
1093   {
1094     { 1, 1, 1, 1 },
1095     FR30_INSN_DIV4S, "div4s", "div4s",
1096     { { MNEM, 0 } },
1097     { 16, 16, 0xffff }, 0x9f70,
1098     (PTR) 0,
1099     { 0, 0, { 0 } }
1100   },
1101 /* lsl $Rj,$Ri */
1102   {
1103     { 1, 1, 1, 1 },
1104     FR30_INSN_LSL, "lsl", "lsl",
1105     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1106     { 16, 16, 0xff00 }, 0xb600,
1107     (PTR) 0,
1108     { 0, 0, { 0 } }
1109   },
1110 /* lsl $u4,$Ri */
1111   {
1112     { 1, 1, 1, 1 },
1113     FR30_INSN_LSLI, "lsli", "lsl",
1114     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1115     { 16, 16, 0xff00 }, 0xb400,
1116     (PTR) 0,
1117     { 0, 0, { 0 } }
1118   },
1119 /* lsl2 $u4,$Ri */
1120   {
1121     { 1, 1, 1, 1 },
1122     FR30_INSN_LSL2, "lsl2", "lsl2",
1123     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1124     { 16, 16, 0xff00 }, 0xb500,
1125     (PTR) 0,
1126     { 0, 0, { 0 } }
1127   },
1128 /* lsr $Rj,$Ri */
1129   {
1130     { 1, 1, 1, 1 },
1131     FR30_INSN_LSR, "lsr", "lsr",
1132     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1133     { 16, 16, 0xff00 }, 0xb200,
1134     (PTR) 0,
1135     { 0, 0, { 0 } }
1136   },
1137 /* lsr $u4,$Ri */
1138   {
1139     { 1, 1, 1, 1 },
1140     FR30_INSN_LSRI, "lsri", "lsr",
1141     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1142     { 16, 16, 0xff00 }, 0xb000,
1143     (PTR) 0,
1144     { 0, 0, { 0 } }
1145   },
1146 /* lsr2 $u4,$Ri */
1147   {
1148     { 1, 1, 1, 1 },
1149     FR30_INSN_LSR2, "lsr2", "lsr2",
1150     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1151     { 16, 16, 0xff00 }, 0xb100,
1152     (PTR) 0,
1153     { 0, 0, { 0 } }
1154   },
1155 /* asr $Rj,$Ri */
1156   {
1157     { 1, 1, 1, 1 },
1158     FR30_INSN_ASR, "asr", "asr",
1159     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1160     { 16, 16, 0xff00 }, 0xba00,
1161     (PTR) 0,
1162     { 0, 0, { 0 } }
1163   },
1164 /* asr $u4,$Ri */
1165   {
1166     { 1, 1, 1, 1 },
1167     FR30_INSN_ASRI, "asri", "asr",
1168     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1169     { 16, 16, 0xff00 }, 0xb800,
1170     (PTR) 0,
1171     { 0, 0, { 0 } }
1172   },
1173 /* asr2 $u4,$Ri */
1174   {
1175     { 1, 1, 1, 1 },
1176     FR30_INSN_ASR2, "asr2", "asr2",
1177     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1178     { 16, 16, 0xff00 }, 0xb900,
1179     (PTR) 0,
1180     { 0, 0, { 0 } }
1181   },
1182 /* ldi:8 $i8,$Ri */
1183   {
1184     { 1, 1, 1, 1 },
1185     FR30_INSN_LDI_8, "ldi:8", "ldi:8",
1186     { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
1187     { 16, 16, 0xf000 }, 0xc000,
1188     (PTR) 0,
1189     { 0, 0, { 0 } }
1190   },
1191 /* ldi:32 $i32,$Ri */
1192   {
1193     { 1, 1, 1, 1 },
1194     FR30_INSN_LDI32, "ldi32", "ldi:32",
1195     { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
1196     { 16, 48, 0xfff0 }, 0x9f80,
1197     (PTR) & fmt_ldi32_ops[0],
1198     { 0, 0, { 0 } }
1199   },
1200 /* ld @$Rj,$Ri */
1201   {
1202     { 1, 1, 1, 1 },
1203     FR30_INSN_LD, "ld", "ld",
1204     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1205     { 16, 16, 0xff00 }, 0x400,
1206     (PTR) 0,
1207     { 0, 0, { 0 } }
1208   },
1209 /* lduh @$Rj,$Ri */
1210   {
1211     { 1, 1, 1, 1 },
1212     FR30_INSN_LDUH, "lduh", "lduh",
1213     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1214     { 16, 16, 0xff00 }, 0x500,
1215     (PTR) 0,
1216     { 0, 0, { 0 } }
1217   },
1218 /* ldub @$Rj,$Ri */
1219   {
1220     { 1, 1, 1, 1 },
1221     FR30_INSN_LDUB, "ldub", "ldub",
1222     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1223     { 16, 16, 0xff00 }, 0x600,
1224     (PTR) 0,
1225     { 0, 0, { 0 } }
1226   },
1227 /* ld @($r13,$Rj),$Ri */
1228   {
1229     { 1, 1, 1, 1 },
1230     FR30_INSN_LDR13, "ldr13", "ld",
1231     { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1232     { 16, 16, 0xff00 }, 0x0,
1233     (PTR) 0,
1234     { 0, 0, { 0 } }
1235   },
1236 /* lduh @($r13,$Rj),$Ri */
1237   {
1238     { 1, 1, 1, 1 },
1239     FR30_INSN_LDR13UH, "ldr13uh", "lduh",
1240     { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1241     { 16, 16, 0xff00 }, 0x100,
1242     (PTR) 0,
1243     { 0, 0, { 0 } }
1244   },
1245 /* ldub @($r13,$Rj),$Ri */
1246   {
1247     { 1, 1, 1, 1 },
1248     FR30_INSN_LDR13UB, "ldr13ub", "ldub",
1249     { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1250     { 16, 16, 0xff00 }, 0x200,
1251     (PTR) 0,
1252     { 0, 0, { 0 } }
1253   },
1254 /* ld @($r14,$disp10),$Ri */
1255   {
1256     { 1, 1, 1, 1 },
1257     FR30_INSN_LDR14, "ldr14", "ld",
1258     { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
1259     { 16, 16, 0xf000 }, 0x2000,
1260     (PTR) 0,
1261     { 0, 0, { 0 } }
1262   },
1263 /* lduh @($r14,$disp9),$Ri */
1264   {
1265     { 1, 1, 1, 1 },
1266     FR30_INSN_LDR14UH, "ldr14uh", "lduh",
1267     { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
1268     { 16, 16, 0xf000 }, 0x4000,
1269     (PTR) 0,
1270     { 0, 0, { 0 } }
1271   },
1272 /* ldub @($r14,$disp8),$Ri */
1273   {
1274     { 1, 1, 1, 1 },
1275     FR30_INSN_LDR14UB, "ldr14ub", "ldub",
1276     { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
1277     { 16, 16, 0xf000 }, 0x6000,
1278     (PTR) 0,
1279     { 0, 0, { 0 } }
1280   },
1281 /* ld @($r15,$udisp6),$Ri */
1282   {
1283     { 1, 1, 1, 1 },
1284     FR30_INSN_LDR15, "ldr15", "ld",
1285     { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
1286     { 16, 16, 0xff00 }, 0x300,
1287     (PTR) 0,
1288     { 0, 0, { 0 } }
1289   },
1290 /* ld @$r15+,$Ri */
1291   {
1292     { 1, 1, 1, 1 },
1293     FR30_INSN_LDR15GR, "ldr15gr", "ld",
1294     { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
1295     { 16, 16, 0xfff0 }, 0x700,
1296     (PTR) 0,
1297     { 0, 0, { 0 } }
1298   },
1299 /* ld @$r15+,$Rs2 */
1300   {
1301     { 1, 1, 1, 1 },
1302     FR30_INSN_LDR15DR, "ldr15dr", "ld",
1303     { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
1304     { 16, 16, 0xfff0 }, 0x780,
1305     (PTR) 0,
1306     { 0, 0, { 0 } }
1307   },
1308 /* ld @$r15+,$ps */
1309   {
1310     { 1, 1, 1, 1 },
1311     FR30_INSN_LDR15PS, "ldr15ps", "ld",
1312     { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
1313     { 16, 16, 0xffff }, 0x790,
1314     (PTR) 0,
1315     { 0, 0, { 0 } }
1316   },
1317 /* st $Ri,@$Rj */
1318   {
1319     { 1, 1, 1, 1 },
1320     FR30_INSN_ST, "st", "st",
1321     { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1322     { 16, 16, 0xff00 }, 0x1400,
1323     (PTR) 0,
1324     { 0, 0, { 0 } }
1325   },
1326 /* sth $Ri,@$Rj */
1327   {
1328     { 1, 1, 1, 1 },
1329     FR30_INSN_STH, "sth", "sth",
1330     { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1331     { 16, 16, 0xff00 }, 0x1500,
1332     (PTR) 0,
1333     { 0, 0, { 0 } }
1334   },
1335 /* stb $Ri,@$Rj */
1336   {
1337     { 1, 1, 1, 1 },
1338     FR30_INSN_STB, "stb", "stb",
1339     { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1340     { 16, 16, 0xff00 }, 0x1600,
1341     (PTR) 0,
1342     { 0, 0, { 0 } }
1343   },
1344 /* st $Ri,@($r13,$Rj) */
1345   {
1346     { 1, 1, 1, 1 },
1347     FR30_INSN_STR13, "str13", "st",
1348     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1349     { 16, 16, 0xff00 }, 0x1000,
1350     (PTR) 0,
1351     { 0, 0, { 0 } }
1352   },
1353 /* sth $Ri,@($r13,$Rj) */
1354   {
1355     { 1, 1, 1, 1 },
1356     FR30_INSN_STR13H, "str13h", "sth",
1357     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1358     { 16, 16, 0xff00 }, 0x1100,
1359     (PTR) 0,
1360     { 0, 0, { 0 } }
1361   },
1362 /* stb $Ri,@($r13,$Rj) */
1363   {
1364     { 1, 1, 1, 1 },
1365     FR30_INSN_STR13B, "stR13b", "stb",
1366     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1367     { 16, 16, 0xff00 }, 0x1200,
1368     (PTR) 0,
1369     { 0, 0, { 0 } }
1370   },
1371 /* st $Ri,@($r14,$disp10) */
1372   {
1373     { 1, 1, 1, 1 },
1374     FR30_INSN_STR14, "str14", "st",
1375     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
1376     { 16, 16, 0xf000 }, 0x3000,
1377     (PTR) 0,
1378     { 0, 0, { 0 } }
1379   },
1380 /* sth $Ri,@($r14,$disp9) */
1381   {
1382     { 1, 1, 1, 1 },
1383     FR30_INSN_STR14H, "str14h", "sth",
1384     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
1385     { 16, 16, 0xf000 }, 0x5000,
1386     (PTR) 0,
1387     { 0, 0, { 0 } }
1388   },
1389 /* stb $Ri,@($r14,$disp8) */
1390   {
1391     { 1, 1, 1, 1 },
1392     FR30_INSN_STR14B, "str14b", "stb",
1393     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
1394     { 16, 16, 0xf000 }, 0x7000,
1395     (PTR) 0,
1396     { 0, 0, { 0 } }
1397   },
1398 /* st $Ri,@($r15,$udisp6) */
1399   {
1400     { 1, 1, 1, 1 },
1401     FR30_INSN_STR15, "str15", "st",
1402     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
1403     { 16, 16, 0xff00 }, 0x1300,
1404     (PTR) 0,
1405     { 0, 0, { 0 } }
1406   },
1407 /* st $Ri,@-$r15 */
1408   {
1409     { 1, 1, 1, 1 },
1410     FR30_INSN_STR15GR, "str15gr", "st",
1411     { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
1412     { 16, 16, 0xfff0 }, 0x1700,
1413     (PTR) 0,
1414     { 0, 0, { 0 } }
1415   },
1416 /* st $Rs2,@-$r15 */
1417   {
1418     { 1, 1, 1, 1 },
1419     FR30_INSN_STR15DR, "str15dr", "st",
1420     { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
1421     { 16, 16, 0xfff0 }, 0x1780,
1422     (PTR) 0,
1423     { 0, 0, { 0 } }
1424   },
1425 /* st $ps,@-$r15 */
1426   {
1427     { 1, 1, 1, 1 },
1428     FR30_INSN_STR15PS, "str15ps", "st",
1429     { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
1430     { 16, 16, 0xffff }, 0x1790,
1431     (PTR) 0,
1432     { 0, 0, { 0 } }
1433   },
1434 /* mov $Rj,$Ri */
1435   {
1436     { 1, 1, 1, 1 },
1437     FR30_INSN_MOV, "mov", "mov",
1438     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1439     { 16, 16, 0xff00 }, 0x8b00,
1440     (PTR) 0,
1441     { 0, 0, { 0 } }
1442   },
1443 /* mov $Rs1,$Ri */
1444   {
1445     { 1, 1, 1, 1 },
1446     FR30_INSN_MOVDR, "movdr", "mov",
1447     { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
1448     { 16, 16, 0xff00 }, 0xb700,
1449     (PTR) 0,
1450     { 0, 0, { 0 } }
1451   },
1452 /* mov $ps,$Ri */
1453   {
1454     { 1, 1, 1, 1 },
1455     FR30_INSN_MOVPS, "movps", "mov",
1456     { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
1457     { 16, 16, 0xfff0 }, 0x1710,
1458     (PTR) 0,
1459     { 0, 0, { 0 } }
1460   },
1461 /* mov $Ri,$Rs1 */
1462   {
1463     { 1, 1, 1, 1 },
1464     FR30_INSN_MOV2DR, "mov2dr", "mov",
1465     { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
1466     { 16, 16, 0xff00 }, 0xb300,
1467     (PTR) & fmt_mov2dr_ops[0],
1468     { 0, 0, { 0 } }
1469   },
1470 /* mov $Ri,$ps */
1471   {
1472     { 1, 1, 1, 1 },
1473     FR30_INSN_MOV2PS, "mov2ps", "mov",
1474     { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
1475     { 16, 16, 0xfff0 }, 0x710,
1476     (PTR) 0,
1477     { 0, 0, { 0 } }
1478   },
1479 /* jmp @$Ri */
1480   {
1481     { 1, 1, 1, 1 },
1482     FR30_INSN_JMP, "jmp", "jmp",
1483     { { MNEM, ' ', '@', OP (RI), 0 } },
1484     { 16, 16, 0xfff0 }, 0x9700,
1485     (PTR) 0,
1486     { 0, 0, { 0 } }
1487   },
1488 /* jmp:D @$Ri */
1489   {
1490     { 1, 1, 1, 1 },
1491     FR30_INSN_JMPD, "jmpd", "jmp:D",
1492     { { MNEM, ' ', '@', OP (RI), 0 } },
1493     { 16, 16, 0xfff0 }, 0x9f00,
1494     (PTR) 0,
1495     { 0, 0, { 0 } }
1496   },
1497 /* call @$Ri */
1498   {
1499     { 1, 1, 1, 1 },
1500     FR30_INSN_CALLR, "callr", "call",
1501     { { MNEM, ' ', '@', OP (RI), 0 } },
1502     { 16, 16, 0xfff0 }, 0x9710,
1503     (PTR) 0,
1504     { 0, 0, { 0 } }
1505   },
1506 /* call:D @$Ri */
1507   {
1508     { 1, 1, 1, 1 },
1509     FR30_INSN_CALLRD, "callrd", "call:D",
1510     { { MNEM, ' ', '@', OP (RI), 0 } },
1511     { 16, 16, 0xfff0 }, 0x9f10,
1512     (PTR) 0,
1513     { 0, 0, { 0 } }
1514   },
1515 /* call $label12 */
1516   {
1517     { 1, 1, 1, 1 },
1518     FR30_INSN_CALL, "call", "call",
1519     { { MNEM, ' ', OP (LABEL12), 0 } },
1520     { 16, 16, 0xf400 }, 0xd000,
1521     (PTR) 0,
1522     { 0, 0, { 0 } }
1523   },
1524 /* call:D $label12 */
1525   {
1526     { 1, 1, 1, 1 },
1527     FR30_INSN_CALLD, "calld", "call:D",
1528     { { MNEM, ' ', OP (LABEL12), 0 } },
1529     { 16, 16, 0xf400 }, 0xd400,
1530     (PTR) 0,
1531     { 0, 0, { 0 } }
1532   },
1533 /* ret */
1534   {
1535     { 1, 1, 1, 1 },
1536     FR30_INSN_RET, "ret", "ret",
1537     { { MNEM, 0 } },
1538     { 16, 16, 0xffff }, 0x9720,
1539     (PTR) 0,
1540     { 0, 0, { 0 } }
1541   },
1542 /* ret:D */
1543   {
1544     { 1, 1, 1, 1 },
1545     FR30_INSN_RETD, "retd", "ret:D",
1546     { { MNEM, 0 } },
1547     { 16, 16, 0xffff }, 0x9f20,
1548     (PTR) 0,
1549     { 0, 0, { 0 } }
1550   },
1551 /* int $u8 */
1552   {
1553     { 1, 1, 1, 1 },
1554     FR30_INSN_INT, "int", "int",
1555     { { MNEM, ' ', OP (U8), 0 } },
1556     { 16, 16, 0xff00 }, 0x1f00,
1557     (PTR) & fmt_int_ops[0],
1558     { 0, 0|A(UNCOND_CTI), { 0 } }
1559   },
1560 /* inte */
1561   {
1562     { 1, 1, 1, 1 },
1563     FR30_INSN_INTE, "inte", "inte",
1564     { { MNEM, 0 } },
1565     { 16, 16, 0xffff }, 0x9f30,
1566     (PTR) 0,
1567     { 0, 0, { 0 } }
1568   },
1569 /* reti */
1570   {
1571     { 1, 1, 1, 1 },
1572     FR30_INSN_RETI, "reti", "reti",
1573     { { MNEM, 0 } },
1574     { 16, 16, 0xffff }, 0x9730,
1575     (PTR) & fmt_reti_ops[0],
1576     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
1577   },
1578 /* bra $label9 */
1579   {
1580     { 1, 1, 1, 1 },
1581     FR30_INSN_BRA, "bra", "bra",
1582     { { MNEM, ' ', OP (LABEL9), 0 } },
1583     { 16, 16, 0xff00 }, 0xe000,
1584     (PTR) 0,
1585     { 0, 0, { 0 } }
1586   },
1587 /* bno $label9 */
1588   {
1589     { 1, 1, 1, 1 },
1590     FR30_INSN_BNO, "bno", "bno",
1591     { { MNEM, ' ', OP (LABEL9), 0 } },
1592     { 16, 16, 0xff00 }, 0xe100,
1593     (PTR) 0,
1594     { 0, 0, { 0 } }
1595   },
1596 /* beq $label9 */
1597   {
1598     { 1, 1, 1, 1 },
1599     FR30_INSN_BEQ, "beq", "beq",
1600     { { MNEM, ' ', OP (LABEL9), 0 } },
1601     { 16, 16, 0xff00 }, 0xe200,
1602     (PTR) 0,
1603     { 0, 0, { 0 } }
1604   },
1605 /* bne $label9 */
1606   {
1607     { 1, 1, 1, 1 },
1608     FR30_INSN_BNE, "bne", "bne",
1609     { { MNEM, ' ', OP (LABEL9), 0 } },
1610     { 16, 16, 0xff00 }, 0xe300,
1611     (PTR) 0,
1612     { 0, 0, { 0 } }
1613   },
1614 /* bc $label9 */
1615   {
1616     { 1, 1, 1, 1 },
1617     FR30_INSN_BC, "bc", "bc",
1618     { { MNEM, ' ', OP (LABEL9), 0 } },
1619     { 16, 16, 0xff00 }, 0xe400,
1620     (PTR) 0,
1621     { 0, 0, { 0 } }
1622   },
1623 /* bnc $label9 */
1624   {
1625     { 1, 1, 1, 1 },
1626     FR30_INSN_BNC, "bnc", "bnc",
1627     { { MNEM, ' ', OP (LABEL9), 0 } },
1628     { 16, 16, 0xff00 }, 0xe500,
1629     (PTR) 0,
1630     { 0, 0, { 0 } }
1631   },
1632 /* bn $label9 */
1633   {
1634     { 1, 1, 1, 1 },
1635     FR30_INSN_BN, "bn", "bn",
1636     { { MNEM, ' ', OP (LABEL9), 0 } },
1637     { 16, 16, 0xff00 }, 0xe600,
1638     (PTR) 0,
1639     { 0, 0, { 0 } }
1640   },
1641 /* bp $label9 */
1642   {
1643     { 1, 1, 1, 1 },
1644     FR30_INSN_BP, "bp", "bp",
1645     { { MNEM, ' ', OP (LABEL9), 0 } },
1646     { 16, 16, 0xff00 }, 0xe700,
1647     (PTR) 0,
1648     { 0, 0, { 0 } }
1649   },
1650 /* bv $label9 */
1651   {
1652     { 1, 1, 1, 1 },
1653     FR30_INSN_BV, "bv", "bv",
1654     { { MNEM, ' ', OP (LABEL9), 0 } },
1655     { 16, 16, 0xff00 }, 0xe800,
1656     (PTR) 0,
1657     { 0, 0, { 0 } }
1658   },
1659 /* bnv $label9 */
1660   {
1661     { 1, 1, 1, 1 },
1662     FR30_INSN_BNV, "bnv", "bnv",
1663     { { MNEM, ' ', OP (LABEL9), 0 } },
1664     { 16, 16, 0xff00 }, 0xe900,
1665     (PTR) 0,
1666     { 0, 0, { 0 } }
1667   },
1668 /* blt $label9 */
1669   {
1670     { 1, 1, 1, 1 },
1671     FR30_INSN_BLT, "blt", "blt",
1672     { { MNEM, ' ', OP (LABEL9), 0 } },
1673     { 16, 16, 0xff00 }, 0xea00,
1674     (PTR) 0,
1675     { 0, 0, { 0 } }
1676   },
1677 /* bge $label9 */
1678   {
1679     { 1, 1, 1, 1 },
1680     FR30_INSN_BGE, "bge", "bge",
1681     { { MNEM, ' ', OP (LABEL9), 0 } },
1682     { 16, 16, 0xff00 }, 0xeb00,
1683     (PTR) 0,
1684     { 0, 0, { 0 } }
1685   },
1686 /* ble $label9 */
1687   {
1688     { 1, 1, 1, 1 },
1689     FR30_INSN_BLE, "ble", "ble",
1690     { { MNEM, ' ', OP (LABEL9), 0 } },
1691     { 16, 16, 0xff00 }, 0xec00,
1692     (PTR) 0,
1693     { 0, 0, { 0 } }
1694   },
1695 /* bgt $label9 */
1696   {
1697     { 1, 1, 1, 1 },
1698     FR30_INSN_BGT, "bgt", "bgt",
1699     { { MNEM, ' ', OP (LABEL9), 0 } },
1700     { 16, 16, 0xff00 }, 0xed00,
1701     (PTR) 0,
1702     { 0, 0, { 0 } }
1703   },
1704 /* bls $label9 */
1705   {
1706     { 1, 1, 1, 1 },
1707     FR30_INSN_BLS, "bls", "bls",
1708     { { MNEM, ' ', OP (LABEL9), 0 } },
1709     { 16, 16, 0xff00 }, 0xee00,
1710     (PTR) 0,
1711     { 0, 0, { 0 } }
1712   },
1713 /* bhi $label9 */
1714   {
1715     { 1, 1, 1, 1 },
1716     FR30_INSN_BHI, "bhi", "bhi",
1717     { { MNEM, ' ', OP (LABEL9), 0 } },
1718     { 16, 16, 0xff00 }, 0xef00,
1719     (PTR) 0,
1720     { 0, 0, { 0 } }
1721   },
1722 /* bra:D $label9 */
1723   {
1724     { 1, 1, 1, 1 },
1725     FR30_INSN_BRAD, "brad", "bra:D",
1726     { { MNEM, ' ', OP (LABEL9), 0 } },
1727     { 16, 16, 0xff00 }, 0xf000,
1728     (PTR) 0,
1729     { 0, 0, { 0 } }
1730   },
1731 /* bno:D $label9 */
1732   {
1733     { 1, 1, 1, 1 },
1734     FR30_INSN_BNOD, "bnod", "bno:D",
1735     { { MNEM, ' ', OP (LABEL9), 0 } },
1736     { 16, 16, 0xff00 }, 0xf100,
1737     (PTR) 0,
1738     { 0, 0, { 0 } }
1739   },
1740 /* beq:D $label9 */
1741   {
1742     { 1, 1, 1, 1 },
1743     FR30_INSN_BEQD, "beqd", "beq:D",
1744     { { MNEM, ' ', OP (LABEL9), 0 } },
1745     { 16, 16, 0xff00 }, 0xf200,
1746     (PTR) 0,
1747     { 0, 0, { 0 } }
1748   },
1749 /* bne:D $label9 */
1750   {
1751     { 1, 1, 1, 1 },
1752     FR30_INSN_BNED, "bned", "bne:D",
1753     { { MNEM, ' ', OP (LABEL9), 0 } },
1754     { 16, 16, 0xff00 }, 0xf300,
1755     (PTR) 0,
1756     { 0, 0, { 0 } }
1757   },
1758 /* bc:D $label9 */
1759   {
1760     { 1, 1, 1, 1 },
1761     FR30_INSN_BCD, "bcd", "bc:D",
1762     { { MNEM, ' ', OP (LABEL9), 0 } },
1763     { 16, 16, 0xff00 }, 0xf400,
1764     (PTR) 0,
1765     { 0, 0, { 0 } }
1766   },
1767 /* bnc:D $label9 */
1768   {
1769     { 1, 1, 1, 1 },
1770     FR30_INSN_BNCD, "bncd", "bnc:D",
1771     { { MNEM, ' ', OP (LABEL9), 0 } },
1772     { 16, 16, 0xff00 }, 0xf500,
1773     (PTR) 0,
1774     { 0, 0, { 0 } }
1775   },
1776 /* bn:D $label9 */
1777   {
1778     { 1, 1, 1, 1 },
1779     FR30_INSN_BND, "bnd", "bn:D",
1780     { { MNEM, ' ', OP (LABEL9), 0 } },
1781     { 16, 16, 0xff00 }, 0xf600,
1782     (PTR) 0,
1783     { 0, 0, { 0 } }
1784   },
1785 /* bp:D $label9 */
1786   {
1787     { 1, 1, 1, 1 },
1788     FR30_INSN_BPD, "bpd", "bp:D",
1789     { { MNEM, ' ', OP (LABEL9), 0 } },
1790     { 16, 16, 0xff00 }, 0xf700,
1791     (PTR) 0,
1792     { 0, 0, { 0 } }
1793   },
1794 /* bv:D $label9 */
1795   {
1796     { 1, 1, 1, 1 },
1797     FR30_INSN_BVD, "bvd", "bv:D",
1798     { { MNEM, ' ', OP (LABEL9), 0 } },
1799     { 16, 16, 0xff00 }, 0xf800,
1800     (PTR) 0,
1801     { 0, 0, { 0 } }
1802   },
1803 /* bnv:D $label9 */
1804   {
1805     { 1, 1, 1, 1 },
1806     FR30_INSN_BNVD, "bnvd", "bnv:D",
1807     { { MNEM, ' ', OP (LABEL9), 0 } },
1808     { 16, 16, 0xff00 }, 0xf900,
1809     (PTR) 0,
1810     { 0, 0, { 0 } }
1811   },
1812 /* blt:D $label9 */
1813   {
1814     { 1, 1, 1, 1 },
1815     FR30_INSN_BLTD, "bltd", "blt:D",
1816     { { MNEM, ' ', OP (LABEL9), 0 } },
1817     { 16, 16, 0xff00 }, 0xfa00,
1818     (PTR) 0,
1819     { 0, 0, { 0 } }
1820   },
1821 /* bge:D $label9 */
1822   {
1823     { 1, 1, 1, 1 },
1824     FR30_INSN_BGED, "bged", "bge:D",
1825     { { MNEM, ' ', OP (LABEL9), 0 } },
1826     { 16, 16, 0xff00 }, 0xfb00,
1827     (PTR) 0,
1828     { 0, 0, { 0 } }
1829   },
1830 /* ble:D $label9 */
1831   {
1832     { 1, 1, 1, 1 },
1833     FR30_INSN_BLED, "bled", "ble:D",
1834     { { MNEM, ' ', OP (LABEL9), 0 } },
1835     { 16, 16, 0xff00 }, 0xfc00,
1836     (PTR) 0,
1837     { 0, 0, { 0 } }
1838   },
1839 /* bgt:D $label9 */
1840   {
1841     { 1, 1, 1, 1 },
1842     FR30_INSN_BGTD, "bgtd", "bgt:D",
1843     { { MNEM, ' ', OP (LABEL9), 0 } },
1844     { 16, 16, 0xff00 }, 0xfd00,
1845     (PTR) 0,
1846     { 0, 0, { 0 } }
1847   },
1848 /* bls:D $label9 */
1849   {
1850     { 1, 1, 1, 1 },
1851     FR30_INSN_BLSD, "blsd", "bls:D",
1852     { { MNEM, ' ', OP (LABEL9), 0 } },
1853     { 16, 16, 0xff00 }, 0xfe00,
1854     (PTR) 0,
1855     { 0, 0, { 0 } }
1856   },
1857 /* bhi:D $label9 */
1858   {
1859     { 1, 1, 1, 1 },
1860     FR30_INSN_BHID, "bhid", "bhi:D",
1861     { { MNEM, ' ', OP (LABEL9), 0 } },
1862     { 16, 16, 0xff00 }, 0xff00,
1863     (PTR) 0,
1864     { 0, 0, { 0 } }
1865   },
1866 /* dmov $R13,@$dir10 */
1867   {
1868     { 1, 1, 1, 1 },
1869     FR30_INSN_DMOVR13, "dmovr13", "dmov",
1870     { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
1871     { 16, 16, 0xff00 }, 0x1800,
1872     (PTR) 0,
1873     { 0, 0, { 0 } }
1874   },
1875 /* dmovh $R13,@$dir9 */
1876   {
1877     { 1, 1, 1, 1 },
1878     FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
1879     { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
1880     { 16, 16, 0xff00 }, 0x1900,
1881     (PTR) 0,
1882     { 0, 0, { 0 } }
1883   },
1884 /* dmovb $R13,@$dir8 */
1885   {
1886     { 1, 1, 1, 1 },
1887     FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
1888     { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
1889     { 16, 16, 0xff00 }, 0x1a00,
1890     (PTR) 0,
1891     { 0, 0, { 0 } }
1892   },
1893 /* dmov @$R13+,@$dir10 */
1894   {
1895     { 1, 1, 1, 1 },
1896     FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
1897     { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
1898     { 16, 16, 0xff00 }, 0x1c00,
1899     (PTR) 0,
1900     { 0, 0, { 0 } }
1901   },
1902 /* dmovh @$R13+,@$dir9 */
1903   {
1904     { 1, 1, 1, 1 },
1905     FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
1906     { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
1907     { 16, 16, 0xff00 }, 0x1d00,
1908     (PTR) 0,
1909     { 0, 0, { 0 } }
1910   },
1911 /* dmovb @$R13+,@$dir8 */
1912   {
1913     { 1, 1, 1, 1 },
1914     FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
1915     { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
1916     { 16, 16, 0xff00 }, 0x1e00,
1917     (PTR) 0,
1918     { 0, 0, { 0 } }
1919   },
1920 /* dmov @$R15+,@$dir10 */
1921   {
1922     { 1, 1, 1, 1 },
1923     FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
1924     { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
1925     { 16, 16, 0xff00 }, 0x1b00,
1926     (PTR) 0,
1927     { 0, 0, { 0 } }
1928   },
1929 /* dmov @$dir10,$R13 */
1930   {
1931     { 1, 1, 1, 1 },
1932     FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
1933     { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
1934     { 16, 16, 0xff00 }, 0x800,
1935     (PTR) 0,
1936     { 0, 0, { 0 } }
1937   },
1938 /* dmovh @$dir9,$R13 */
1939   {
1940     { 1, 1, 1, 1 },
1941     FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
1942     { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
1943     { 16, 16, 0xff00 }, 0x900,
1944     (PTR) 0,
1945     { 0, 0, { 0 } }
1946   },
1947 /* dmovb @$dir8,$R13 */
1948   {
1949     { 1, 1, 1, 1 },
1950     FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
1951     { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
1952     { 16, 16, 0xff00 }, 0xa00,
1953     (PTR) 0,
1954     { 0, 0, { 0 } }
1955   },
1956 /* dmov @$dir10,@$R13+ */
1957   {
1958     { 1, 1, 1, 1 },
1959     FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
1960     { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
1961     { 16, 16, 0xff00 }, 0xc00,
1962     (PTR) 0,
1963     { 0, 0, { 0 } }
1964   },
1965 /* dmovh @$dir9,@$R13+ */
1966   {
1967     { 1, 1, 1, 1 },
1968     FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
1969     { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
1970     { 16, 16, 0xff00 }, 0xd00,
1971     (PTR) 0,
1972     { 0, 0, { 0 } }
1973   },
1974 /* dmovb @$dir8,@$R13+ */
1975   {
1976     { 1, 1, 1, 1 },
1977     FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
1978     { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
1979     { 16, 16, 0xff00 }, 0xe00,
1980     (PTR) 0,
1981     { 0, 0, { 0 } }
1982   },
1983 /* dmov @$dir10,@-$R15 */
1984   {
1985     { 1, 1, 1, 1 },
1986     FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
1987     { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
1988     { 16, 16, 0xff00 }, 0xb00,
1989     (PTR) 0,
1990     { 0, 0, { 0 } }
1991   },
1992 /* ldres @$Ri+,$u4 */
1993   {
1994     { 1, 1, 1, 1 },
1995     FR30_INSN_LDRES, "ldres", "ldres",
1996     { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
1997     { 16, 16, 0xff00 }, 0xbc00,
1998     (PTR) 0,
1999     { 0, 0, { 0 } }
2000   },
2001 /* stres $u4,@$Ri+ */
2002   {
2003     { 1, 1, 1, 1 },
2004     FR30_INSN_STRES, "stres", "stres",
2005     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
2006     { 16, 16, 0xff00 }, 0xbd00,
2007     (PTR) 0,
2008     { 0, 0, { 0 } }
2009   },
2010 /* copop $u4c,$ccc,$CRj,$CRi */
2011   {
2012     { 1, 1, 1, 1 },
2013     FR30_INSN_COPOP, "copop", "copop",
2014     { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
2015     { 16, 32, 0xfff0 }, 0x9fc0,
2016     (PTR) 0,
2017     { 0, 0, { 0 } }
2018   },
2019 /* copld $u4c,$ccc,$Rjc,$CRi */
2020   {
2021     { 1, 1, 1, 1 },
2022     FR30_INSN_COPLD, "copld", "copld",
2023     { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
2024     { 16, 32, 0xfff0 }, 0x9fd0,
2025     (PTR) 0,
2026     { 0, 0, { 0 } }
2027   },
2028 /* copst $u4c,$ccc,$CRj,$Ric */
2029   {
2030     { 1, 1, 1, 1 },
2031     FR30_INSN_COPST, "copst", "copst",
2032     { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2033     { 16, 32, 0xfff0 }, 0x9fe0,
2034     (PTR) 0,
2035     { 0, 0, { 0 } }
2036   },
2037 /* copsv $u4c,$ccc,$CRj,$Ric */
2038   {
2039     { 1, 1, 1, 1 },
2040     FR30_INSN_COPSV, "copsv", "copsv",
2041     { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2042     { 16, 32, 0xfff0 }, 0x9ff0,
2043     (PTR) 0,
2044     { 0, 0, { 0 } }
2045   },
2046 /* nop */
2047   {
2048     { 1, 1, 1, 1 },
2049     FR30_INSN_NOP, "nop", "nop",
2050     { { MNEM, 0 } },
2051     { 16, 16, 0xffff }, 0x9fa0,
2052     (PTR) 0,
2053     { 0, 0, { 0 } }
2054   },
2055 /* andccr $u8 */
2056   {
2057     { 1, 1, 1, 1 },
2058     FR30_INSN_ANDCCR, "andccr", "andccr",
2059     { { MNEM, ' ', OP (U8), 0 } },
2060     { 16, 16, 0xff00 }, 0x8300,
2061     (PTR) 0,
2062     { 0, 0, { 0 } }
2063   },
2064 /* orccr $u8 */
2065   {
2066     { 1, 1, 1, 1 },
2067     FR30_INSN_ORCCR, "orccr", "orccr",
2068     { { MNEM, ' ', OP (U8), 0 } },
2069     { 16, 16, 0xff00 }, 0x9300,
2070     (PTR) 0,
2071     { 0, 0, { 0 } }
2072   },
2073 /* stilm $u8 */
2074   {
2075     { 1, 1, 1, 1 },
2076     FR30_INSN_STILM, "stilm", "stilm",
2077     { { MNEM, ' ', OP (U8), 0 } },
2078     { 16, 16, 0xff00 }, 0x8700,
2079     (PTR) 0,
2080     { 0, 0, { 0 } }
2081   },
2082 /* addsp $s10 */
2083   {
2084     { 1, 1, 1, 1 },
2085     FR30_INSN_ADDSP, "addsp", "addsp",
2086     { { MNEM, ' ', OP (S10), 0 } },
2087     { 16, 16, 0xff00 }, 0xa300,
2088     (PTR) 0,
2089     { 0, 0, { 0 } }
2090   },
2091 /* extsb $Ri */
2092   {
2093     { 1, 1, 1, 1 },
2094     FR30_INSN_EXTSB, "extsb", "extsb",
2095     { { MNEM, ' ', OP (RI), 0 } },
2096     { 16, 16, 0xfff0 }, 0x9780,
2097     (PTR) 0,
2098     { 0, 0, { 0 } }
2099   },
2100 /* extub $Ri */
2101   {
2102     { 1, 1, 1, 1 },
2103     FR30_INSN_EXTUB, "extub", "extub",
2104     { { MNEM, ' ', OP (RI), 0 } },
2105     { 16, 16, 0xfff0 }, 0x9790,
2106     (PTR) 0,
2107     { 0, 0, { 0 } }
2108   },
2109 /* extsh $Ri */
2110   {
2111     { 1, 1, 1, 1 },
2112     FR30_INSN_EXTSH, "extsh", "extsh",
2113     { { MNEM, ' ', OP (RI), 0 } },
2114     { 16, 16, 0xfff0 }, 0x97a0,
2115     (PTR) 0,
2116     { 0, 0, { 0 } }
2117   },
2118 /* extuh $Ri */
2119   {
2120     { 1, 1, 1, 1 },
2121     FR30_INSN_EXTUH, "extuh", "extuh",
2122     { { MNEM, ' ', OP (RI), 0 } },
2123     { 16, 16, 0xfff0 }, 0x97b0,
2124     (PTR) 0,
2125     { 0, 0, { 0 } }
2126   },
2127 /* ldm0 ($reglist_low) */
2128   {
2129     { 1, 1, 1, 1 },
2130     FR30_INSN_LDM0, "ldm0", "ldm0",
2131     { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
2132     { 16, 16, 0xff00 }, 0x8c00,
2133     (PTR) 0,
2134     { 0, 0, { 0 } }
2135   },
2136 /* ldm1 ($reglist_hi) */
2137   {
2138     { 1, 1, 1, 1 },
2139     FR30_INSN_LDM1, "ldm1", "ldm1",
2140     { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
2141     { 16, 16, 0xff00 }, 0x8d00,
2142     (PTR) 0,
2143     { 0, 0, { 0 } }
2144   },
2145 /* stm0 ($reglist_low) */
2146   {
2147     { 1, 1, 1, 1 },
2148     FR30_INSN_STM0, "stm0", "stm0",
2149     { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
2150     { 16, 16, 0xff00 }, 0x8e00,
2151     (PTR) 0,
2152     { 0, 0, { 0 } }
2153   },
2154 /* stm1 ($reglist_hi) */
2155   {
2156     { 1, 1, 1, 1 },
2157     FR30_INSN_STM1, "stm1", "stm1",
2158     { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
2159     { 16, 16, 0xff00 }, 0x8f00,
2160     (PTR) 0,
2161     { 0, 0, { 0 } }
2162   },
2163 /* enter $u10 */
2164   {
2165     { 1, 1, 1, 1 },
2166     FR30_INSN_ENTER, "enter", "enter",
2167     { { MNEM, ' ', OP (U10), 0 } },
2168     { 16, 16, 0xff00 }, 0xf00,
2169     (PTR) 0,
2170     { 0, 0, { 0 } }
2171   },
2172 /* leave */
2173   {
2174     { 1, 1, 1, 1 },
2175     FR30_INSN_LEAVE, "leave", "leave",
2176     { { MNEM, 0 } },
2177     { 16, 16, 0xffff }, 0x9f90,
2178     (PTR) 0,
2179     { 0, 0, { 0 } }
2180   },
2181 /* xchb @$Rj,$Ri */
2182   {
2183     { 1, 1, 1, 1 },
2184     FR30_INSN_XCHB, "xchb", "xchb",
2185     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2186     { 16, 16, 0xff00 }, 0x8a00,
2187     (PTR) 0,
2188     { 0, 0, { 0 } }
2189   },
2190 };
2191
2192 #undef A
2193 #undef MNEM
2194 #undef OP
2195
2196 static const CGEN_INSN_TABLE insn_table =
2197 {
2198   & fr30_cgen_insn_table_entries[0],
2199   sizeof (CGEN_INSN),
2200   MAX_INSNS,
2201   NULL
2202 };
2203
2204 /* Each non-simple macro entry points to an array of expansion possibilities.  */
2205
2206 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2207 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2208 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2209
2210 /* The macro instruction table.  */
2211
2212 static const CGEN_INSN macro_insn_table_entries[] =
2213 {
2214 /* ldi32 $i32,$Ri */
2215   {
2216     { 1, 1, 1, 1 },
2217     -1, "ldi32m", "ldi32",
2218     { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
2219     { 16, 48, 0xfff0 }, 0x9f80,
2220     (PTR) 0,
2221     { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
2222   },
2223 };
2224
2225 #undef A
2226 #undef MNEM
2227 #undef OP
2228
2229 static const CGEN_INSN_TABLE macro_insn_table =
2230 {
2231   & macro_insn_table_entries[0],
2232   sizeof (CGEN_INSN),
2233   (sizeof (macro_insn_table_entries) /
2234    sizeof (macro_insn_table_entries[0])),
2235   NULL
2236 };
2237
2238 static void
2239 init_tables ()
2240 {
2241 }
2242
2243 /* Return non-zero if INSN is to be added to the hash table.
2244    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
2245
2246 static int
2247 asm_hash_insn_p (insn)
2248      const CGEN_INSN * insn;
2249 {
2250   return CGEN_ASM_HASH_P (insn);
2251 }
2252
2253 static int
2254 dis_hash_insn_p (insn)
2255      const CGEN_INSN * insn;
2256 {
2257   /* If building the hash table and the NO-DIS attribute is present,
2258      ignore.  */
2259   if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2260     return 0;
2261   return CGEN_DIS_HASH_P (insn);
2262 }
2263
2264 /* The result is the hash value of the insn.
2265    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
2266
2267 static unsigned int
2268 asm_hash_insn (mnem)
2269      const char * mnem;
2270 {
2271   return CGEN_ASM_HASH (mnem);
2272 }
2273
2274 /* BUF is a pointer to the insn's bytes in target order.
2275    VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
2276    host order.  */
2277
2278 static unsigned int
2279 dis_hash_insn (buf, value)
2280      const char * buf;
2281      CGEN_INSN_INT value;
2282 {
2283   return CGEN_DIS_HASH (buf, value);
2284 }
2285
2286 /* Initialize an opcode table and return a descriptor.
2287    It's much like opening a file, and must be the first function called.  */
2288
2289 CGEN_OPCODE_DESC
2290 fr30_cgen_opcode_open (mach, endian)
2291      int mach;
2292      enum cgen_endian endian;
2293 {
2294   CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2295   static int init_p;
2296
2297   if (! init_p)
2298     {
2299       init_tables ();
2300       init_p = 1;
2301     }
2302
2303   memset (table, 0, sizeof (*table));
2304
2305   CGEN_OPCODE_MACH (table) = mach;
2306   CGEN_OPCODE_ENDIAN (table) = endian;
2307   /* FIXME: for the sparc case we can determine insn-endianness statically.
2308      The worry here is where both data and insn endian can be independently
2309      chosen, in which case this function will need another argument.
2310      Actually, will want to allow for more arguments in the future anyway.  */
2311   CGEN_OPCODE_INSN_ENDIAN (table) = endian;
2312
2313   CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
2314
2315   CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
2316
2317   * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2318
2319   * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2320
2321   CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2322   CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2323   CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2324
2325   CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2326   CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2327   CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2328
2329   return (CGEN_OPCODE_DESC) table;
2330 }
2331
2332 /* Close an opcode table.  */
2333
2334 void
2335 fr30_cgen_opcode_close (desc)
2336      CGEN_OPCODE_DESC desc;
2337 {
2338   free (desc);
2339 }
2340
2341 /* Getting values from cgen_fields is handled by a collection of functions.
2342    They are distinguished by the type of the VALUE argument they return.
2343    TODO: floating point, inlining support, remove cases where result type
2344    not appropriate.  */
2345
2346 int
2347 fr30_cgen_get_int_operand (opindex, fields)
2348      int opindex;
2349      const CGEN_FIELDS * fields;
2350 {
2351   int value;
2352
2353   switch (opindex)
2354     {
2355     case FR30_OPERAND_RI :
2356       value = fields->f_Ri;
2357       break;
2358     case FR30_OPERAND_RJ :
2359       value = fields->f_Rj;
2360       break;
2361     case FR30_OPERAND_RIC :
2362       value = fields->f_Ric;
2363       break;
2364     case FR30_OPERAND_RJC :
2365       value = fields->f_Rjc;
2366       break;
2367     case FR30_OPERAND_CRI :
2368       value = fields->f_CRi;
2369       break;
2370     case FR30_OPERAND_CRJ :
2371       value = fields->f_CRj;
2372       break;
2373     case FR30_OPERAND_RS1 :
2374       value = fields->f_Rs1;
2375       break;
2376     case FR30_OPERAND_RS2 :
2377       value = fields->f_Rs2;
2378       break;
2379     case FR30_OPERAND_R13 :
2380       value = fields->f_nil;
2381       break;
2382     case FR30_OPERAND_R14 :
2383       value = fields->f_nil;
2384       break;
2385     case FR30_OPERAND_R15 :
2386       value = fields->f_nil;
2387       break;
2388     case FR30_OPERAND_PS :
2389       value = fields->f_nil;
2390       break;
2391     case FR30_OPERAND_U4 :
2392       value = fields->f_u4;
2393       break;
2394     case FR30_OPERAND_U4C :
2395       value = fields->f_u4c;
2396       break;
2397     case FR30_OPERAND_M4 :
2398       value = fields->f_m4;
2399       break;
2400     case FR30_OPERAND_U8 :
2401       value = fields->f_u8;
2402       break;
2403     case FR30_OPERAND_I8 :
2404       value = fields->f_i8;
2405       break;
2406     case FR30_OPERAND_UDISP6 :
2407       value = fields->f_udisp6;
2408       break;
2409     case FR30_OPERAND_DISP8 :
2410       value = fields->f_disp8;
2411       break;
2412     case FR30_OPERAND_DISP9 :
2413       value = fields->f_disp9;
2414       break;
2415     case FR30_OPERAND_DISP10 :
2416       value = fields->f_disp10;
2417       break;
2418     case FR30_OPERAND_S10 :
2419       value = fields->f_s10;
2420       break;
2421     case FR30_OPERAND_U10 :
2422       value = fields->f_u10;
2423       break;
2424     case FR30_OPERAND_I32 :
2425       value = fields->f_i32;
2426       break;
2427     case FR30_OPERAND_DIR8 :
2428       value = fields->f_dir8;
2429       break;
2430     case FR30_OPERAND_DIR9 :
2431       value = fields->f_dir9;
2432       break;
2433     case FR30_OPERAND_DIR10 :
2434       value = fields->f_dir10;
2435       break;
2436     case FR30_OPERAND_LABEL9 :
2437       value = fields->f_rel9;
2438       break;
2439     case FR30_OPERAND_LABEL12 :
2440       value = fields->f_rel12;
2441       break;
2442     case FR30_OPERAND_REGLIST_LOW :
2443       value = fields->f_reglist_low;
2444       break;
2445     case FR30_OPERAND_REGLIST_HI :
2446       value = fields->f_reglist_hi;
2447       break;
2448     case FR30_OPERAND_CC :
2449       value = fields->f_cc;
2450       break;
2451     case FR30_OPERAND_CCC :
2452       value = fields->f_ccc;
2453       break;
2454
2455     default :
2456       /* xgettext:c-format */
2457       fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2458                        opindex);
2459       abort ();
2460   }
2461
2462   return value;
2463 }
2464
2465 bfd_vma
2466 fr30_cgen_get_vma_operand (opindex, fields)
2467      int opindex;
2468      const CGEN_FIELDS * fields;
2469 {
2470   bfd_vma value;
2471
2472   switch (opindex)
2473     {
2474     case FR30_OPERAND_RI :
2475       value = fields->f_Ri;
2476       break;
2477     case FR30_OPERAND_RJ :
2478       value = fields->f_Rj;
2479       break;
2480     case FR30_OPERAND_RIC :
2481       value = fields->f_Ric;
2482       break;
2483     case FR30_OPERAND_RJC :
2484       value = fields->f_Rjc;
2485       break;
2486     case FR30_OPERAND_CRI :
2487       value = fields->f_CRi;
2488       break;
2489     case FR30_OPERAND_CRJ :
2490       value = fields->f_CRj;
2491       break;
2492     case FR30_OPERAND_RS1 :
2493       value = fields->f_Rs1;
2494       break;
2495     case FR30_OPERAND_RS2 :
2496       value = fields->f_Rs2;
2497       break;
2498     case FR30_OPERAND_R13 :
2499       value = fields->f_nil;
2500       break;
2501     case FR30_OPERAND_R14 :
2502       value = fields->f_nil;
2503       break;
2504     case FR30_OPERAND_R15 :
2505       value = fields->f_nil;
2506       break;
2507     case FR30_OPERAND_PS :
2508       value = fields->f_nil;
2509       break;
2510     case FR30_OPERAND_U4 :
2511       value = fields->f_u4;
2512       break;
2513     case FR30_OPERAND_U4C :
2514       value = fields->f_u4c;
2515       break;
2516     case FR30_OPERAND_M4 :
2517       value = fields->f_m4;
2518       break;
2519     case FR30_OPERAND_U8 :
2520       value = fields->f_u8;
2521       break;
2522     case FR30_OPERAND_I8 :
2523       value = fields->f_i8;
2524       break;
2525     case FR30_OPERAND_UDISP6 :
2526       value = fields->f_udisp6;
2527       break;
2528     case FR30_OPERAND_DISP8 :
2529       value = fields->f_disp8;
2530       break;
2531     case FR30_OPERAND_DISP9 :
2532       value = fields->f_disp9;
2533       break;
2534     case FR30_OPERAND_DISP10 :
2535       value = fields->f_disp10;
2536       break;
2537     case FR30_OPERAND_S10 :
2538       value = fields->f_s10;
2539       break;
2540     case FR30_OPERAND_U10 :
2541       value = fields->f_u10;
2542       break;
2543     case FR30_OPERAND_I32 :
2544       value = fields->f_i32;
2545       break;
2546     case FR30_OPERAND_DIR8 :
2547       value = fields->f_dir8;
2548       break;
2549     case FR30_OPERAND_DIR9 :
2550       value = fields->f_dir9;
2551       break;
2552     case FR30_OPERAND_DIR10 :
2553       value = fields->f_dir10;
2554       break;
2555     case FR30_OPERAND_LABEL9 :
2556       value = fields->f_rel9;
2557       break;
2558     case FR30_OPERAND_LABEL12 :
2559       value = fields->f_rel12;
2560       break;
2561     case FR30_OPERAND_REGLIST_LOW :
2562       value = fields->f_reglist_low;
2563       break;
2564     case FR30_OPERAND_REGLIST_HI :
2565       value = fields->f_reglist_hi;
2566       break;
2567     case FR30_OPERAND_CC :
2568       value = fields->f_cc;
2569       break;
2570     case FR30_OPERAND_CCC :
2571       value = fields->f_ccc;
2572       break;
2573
2574     default :
2575       /* xgettext:c-format */
2576       fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
2577                        opindex);
2578       abort ();
2579   }
2580
2581   return value;
2582 }
2583
2584 /* Stuffing values in cgen_fields is handled by a collection of functions.
2585    They are distinguished by the type of the VALUE argument they accept.
2586    TODO: floating point, inlining support, remove cases where argument type
2587    not appropriate.  */
2588
2589 void
2590 fr30_cgen_set_int_operand (opindex, fields, value)
2591      int opindex;
2592      CGEN_FIELDS * fields;
2593      int value;
2594 {
2595   switch (opindex)
2596     {
2597     case FR30_OPERAND_RI :
2598       fields->f_Ri = value;
2599       break;
2600     case FR30_OPERAND_RJ :
2601       fields->f_Rj = value;
2602       break;
2603     case FR30_OPERAND_RIC :
2604       fields->f_Ric = value;
2605       break;
2606     case FR30_OPERAND_RJC :
2607       fields->f_Rjc = value;
2608       break;
2609     case FR30_OPERAND_CRI :
2610       fields->f_CRi = value;
2611       break;
2612     case FR30_OPERAND_CRJ :
2613       fields->f_CRj = value;
2614       break;
2615     case FR30_OPERAND_RS1 :
2616       fields->f_Rs1 = value;
2617       break;
2618     case FR30_OPERAND_RS2 :
2619       fields->f_Rs2 = value;
2620       break;
2621     case FR30_OPERAND_R13 :
2622       fields->f_nil = value;
2623       break;
2624     case FR30_OPERAND_R14 :
2625       fields->f_nil = value;
2626       break;
2627     case FR30_OPERAND_R15 :
2628       fields->f_nil = value;
2629       break;
2630     case FR30_OPERAND_PS :
2631       fields->f_nil = value;
2632       break;
2633     case FR30_OPERAND_U4 :
2634       fields->f_u4 = value;
2635       break;
2636     case FR30_OPERAND_U4C :
2637       fields->f_u4c = value;
2638       break;
2639     case FR30_OPERAND_M4 :
2640       fields->f_m4 = value;
2641       break;
2642     case FR30_OPERAND_U8 :
2643       fields->f_u8 = value;
2644       break;
2645     case FR30_OPERAND_I8 :
2646       fields->f_i8 = value;
2647       break;
2648     case FR30_OPERAND_UDISP6 :
2649       fields->f_udisp6 = value;
2650       break;
2651     case FR30_OPERAND_DISP8 :
2652       fields->f_disp8 = value;
2653       break;
2654     case FR30_OPERAND_DISP9 :
2655       fields->f_disp9 = value;
2656       break;
2657     case FR30_OPERAND_DISP10 :
2658       fields->f_disp10 = value;
2659       break;
2660     case FR30_OPERAND_S10 :
2661       fields->f_s10 = value;
2662       break;
2663     case FR30_OPERAND_U10 :
2664       fields->f_u10 = value;
2665       break;
2666     case FR30_OPERAND_I32 :
2667       fields->f_i32 = value;
2668       break;
2669     case FR30_OPERAND_DIR8 :
2670       fields->f_dir8 = value;
2671       break;
2672     case FR30_OPERAND_DIR9 :
2673       fields->f_dir9 = value;
2674       break;
2675     case FR30_OPERAND_DIR10 :
2676       fields->f_dir10 = value;
2677       break;
2678     case FR30_OPERAND_LABEL9 :
2679       fields->f_rel9 = value;
2680       break;
2681     case FR30_OPERAND_LABEL12 :
2682       fields->f_rel12 = value;
2683       break;
2684     case FR30_OPERAND_REGLIST_LOW :
2685       fields->f_reglist_low = value;
2686       break;
2687     case FR30_OPERAND_REGLIST_HI :
2688       fields->f_reglist_hi = value;
2689       break;
2690     case FR30_OPERAND_CC :
2691       fields->f_cc = value;
2692       break;
2693     case FR30_OPERAND_CCC :
2694       fields->f_ccc = value;
2695       break;
2696
2697     default :
2698       /* xgettext:c-format */
2699       fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2700                        opindex);
2701       abort ();
2702   }
2703 }
2704
2705 void
2706 fr30_cgen_set_vma_operand (opindex, fields, value)
2707      int opindex;
2708      CGEN_FIELDS * fields;
2709      bfd_vma value;
2710 {
2711   switch (opindex)
2712     {
2713     case FR30_OPERAND_RI :
2714       fields->f_Ri = value;
2715       break;
2716     case FR30_OPERAND_RJ :
2717       fields->f_Rj = value;
2718       break;
2719     case FR30_OPERAND_RIC :
2720       fields->f_Ric = value;
2721       break;
2722     case FR30_OPERAND_RJC :
2723       fields->f_Rjc = value;
2724       break;
2725     case FR30_OPERAND_CRI :
2726       fields->f_CRi = value;
2727       break;
2728     case FR30_OPERAND_CRJ :
2729       fields->f_CRj = value;
2730       break;
2731     case FR30_OPERAND_RS1 :
2732       fields->f_Rs1 = value;
2733       break;
2734     case FR30_OPERAND_RS2 :
2735       fields->f_Rs2 = value;
2736       break;
2737     case FR30_OPERAND_R13 :
2738       fields->f_nil = value;
2739       break;
2740     case FR30_OPERAND_R14 :
2741       fields->f_nil = value;
2742       break;
2743     case FR30_OPERAND_R15 :
2744       fields->f_nil = value;
2745       break;
2746     case FR30_OPERAND_PS :
2747       fields->f_nil = value;
2748       break;
2749     case FR30_OPERAND_U4 :
2750       fields->f_u4 = value;
2751       break;
2752     case FR30_OPERAND_U4C :
2753       fields->f_u4c = value;
2754       break;
2755     case FR30_OPERAND_M4 :
2756       fields->f_m4 = value;
2757       break;
2758     case FR30_OPERAND_U8 :
2759       fields->f_u8 = value;
2760       break;
2761     case FR30_OPERAND_I8 :
2762       fields->f_i8 = value;
2763       break;
2764     case FR30_OPERAND_UDISP6 :
2765       fields->f_udisp6 = value;
2766       break;
2767     case FR30_OPERAND_DISP8 :
2768       fields->f_disp8 = value;
2769       break;
2770     case FR30_OPERAND_DISP9 :
2771       fields->f_disp9 = value;
2772       break;
2773     case FR30_OPERAND_DISP10 :
2774       fields->f_disp10 = value;
2775       break;
2776     case FR30_OPERAND_S10 :
2777       fields->f_s10 = value;
2778       break;
2779     case FR30_OPERAND_U10 :
2780       fields->f_u10 = value;
2781       break;
2782     case FR30_OPERAND_I32 :
2783       fields->f_i32 = value;
2784       break;
2785     case FR30_OPERAND_DIR8 :
2786       fields->f_dir8 = value;
2787       break;
2788     case FR30_OPERAND_DIR9 :
2789       fields->f_dir9 = value;
2790       break;
2791     case FR30_OPERAND_DIR10 :
2792       fields->f_dir10 = value;
2793       break;
2794     case FR30_OPERAND_LABEL9 :
2795       fields->f_rel9 = value;
2796       break;
2797     case FR30_OPERAND_LABEL12 :
2798       fields->f_rel12 = value;
2799       break;
2800     case FR30_OPERAND_REGLIST_LOW :
2801       fields->f_reglist_low = value;
2802       break;
2803     case FR30_OPERAND_REGLIST_HI :
2804       fields->f_reglist_hi = value;
2805       break;
2806     case FR30_OPERAND_CC :
2807       fields->f_cc = value;
2808       break;
2809     case FR30_OPERAND_CCC :
2810       fields->f_ccc = value;
2811       break;
2812
2813     default :
2814       /* xgettext:c-format */
2815       fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
2816                        opindex);
2817       abort ();
2818   }
2819 }
2820