opcodes/frv-desc.c

   1 /* CPU data for frv.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include "ansidecl.h"
  29 #include "bfd.h"
  30 #include "symcat.h"
  31 #include "frv-desc.h"
  32 #include "frv-opc.h"
  33 #include "opintl.h"
  34 #include "libiberty.h"
  35 #include "xregex.h"
  36
  37 /* Attributes.  */
  38
  39 static const CGEN_ATTR_ENTRY bool_attr[] =
  40 {
  41   { "#f", 0 },
  42   { "#t", 1 },
  43   { 0, 0 }
  44 };
  45
  46 static const CGEN_ATTR_ENTRY MACH_attr[] =
  47 {
  48   { "base", MACH_BASE },
  49   { "frv", MACH_FRV },
  50   { "fr500", MACH_FR500 },
  51   { "fr400", MACH_FR400 },
  52   { "tomcat", MACH_TOMCAT },
  53   { "simple", MACH_SIMPLE },
  54   { "max", MACH_MAX },
  55   { 0, 0 }
  56 };
  57
  58 static const CGEN_ATTR_ENTRY ISA_attr[] =
  59 {
  60   { "frv", ISA_FRV },
  61   { "max", ISA_MAX },
  62   { 0, 0 }
  63 };
  64
  65 static const CGEN_ATTR_ENTRY UNIT_attr[] =
  66 {
  67   { "NIL", UNIT_NIL },
  68   { "I0", UNIT_I0 },
  69   { "I1", UNIT_I1 },
  70   { "I01", UNIT_I01 },
  71   { "IALL", UNIT_IALL },
  72   { "FM0", UNIT_FM0 },
  73   { "FM1", UNIT_FM1 },
  74   { "FM01", UNIT_FM01 },
  75   { "FMALL", UNIT_FMALL },
  76   { "FMLOW", UNIT_FMLOW },
  77   { "B0", UNIT_B0 },
  78   { "B1", UNIT_B1 },
  79   { "B01", UNIT_B01 },
  80   { "C", UNIT_C },
  81   { "MULT_DIV", UNIT_MULT_DIV },
  82   { "LOAD", UNIT_LOAD },
  83   { "STORE", UNIT_STORE },
  84   { "SCAN", UNIT_SCAN },
  85   { "DCPL", UNIT_DCPL },
  86   { "MDUALACC", UNIT_MDUALACC },
  87   { "MCLRACC_1", UNIT_MCLRACC_1 },
  88   { "NUM_UNITS", UNIT_NUM_UNITS },
  89   { 0, 0 }
  90 };
  91
  92 static const CGEN_ATTR_ENTRY FR400_MAJOR_attr[] =
  93 {
  94   { "NONE", FR400_MAJOR_NONE },
  95   { "I_1", FR400_MAJOR_I_1 },
  96   { "I_2", FR400_MAJOR_I_2 },
  97   { "I_3", FR400_MAJOR_I_3 },
  98   { "I_4", FR400_MAJOR_I_4 },
  99   { "I_5", FR400_MAJOR_I_5 },
 100   { "B_1", FR400_MAJOR_B_1 },
 101   { "B_2", FR400_MAJOR_B_2 },
 102   { "B_3", FR400_MAJOR_B_3 },
 103   { "B_4", FR400_MAJOR_B_4 },
 104   { "B_5", FR400_MAJOR_B_5 },
 105   { "B_6", FR400_MAJOR_B_6 },
 106   { "C_1", FR400_MAJOR_C_1 },
 107   { "C_2", FR400_MAJOR_C_2 },
 108   { "M_1", FR400_MAJOR_M_1 },
 109   { "M_2", FR400_MAJOR_M_2 },
 110   { 0, 0 }
 111 };
 112
 113 static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] =
 114 {
 115   { "NONE", FR500_MAJOR_NONE },
 116   { "I_1", FR500_MAJOR_I_1 },
 117   { "I_2", FR500_MAJOR_I_2 },
 118   { "I_3", FR500_MAJOR_I_3 },
 119   { "I_4", FR500_MAJOR_I_4 },
 120   { "I_5", FR500_MAJOR_I_5 },
 121   { "I_6", FR500_MAJOR_I_6 },
 122   { "B_1", FR500_MAJOR_B_1 },
 123   { "B_2", FR500_MAJOR_B_2 },
 124   { "B_3", FR500_MAJOR_B_3 },
 125   { "B_4", FR500_MAJOR_B_4 },
 126   { "B_5", FR500_MAJOR_B_5 },
 127   { "B_6", FR500_MAJOR_B_6 },
 128   { "C_1", FR500_MAJOR_C_1 },
 129   { "C_2", FR500_MAJOR_C_2 },
 130   { "F_1", FR500_MAJOR_F_1 },
 131   { "F_2", FR500_MAJOR_F_2 },
 132   { "F_3", FR500_MAJOR_F_3 },
 133   { "F_4", FR500_MAJOR_F_4 },
 134   { "F_5", FR500_MAJOR_F_5 },
 135   { "F_6", FR500_MAJOR_F_6 },
 136   { "F_7", FR500_MAJOR_F_7 },
 137   { "F_8", FR500_MAJOR_F_8 },
 138   { "M_1", FR500_MAJOR_M_1 },
 139   { "M_2", FR500_MAJOR_M_2 },
 140   { "M_3", FR500_MAJOR_M_3 },
 141   { "M_4", FR500_MAJOR_M_4 },
 142   { "M_5", FR500_MAJOR_M_5 },
 143   { "M_6", FR500_MAJOR_M_6 },
 144   { "M_7", FR500_MAJOR_M_7 },
 145   { "M_8", FR500_MAJOR_M_8 },
 146   { 0, 0 }
 147 };
 148
 149 const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[] =
 150 {
 151   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 152   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 153   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 154   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 155   { "RESERVED", &bool_attr[0], &bool_attr[0] },
 156   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 157   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 158   { 0, 0, 0 }
 159 };
 160
 161 const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[] =
 162 {
 163   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 164   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 165   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
 166   { "PC", &bool_attr[0], &bool_attr[0] },
 167   { "PROFILE", &bool_attr[0], &bool_attr[0] },
 168   { 0, 0, 0 }
 169 };
 170
 171 const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[] =
 172 {
 173   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 174   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 175   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 176   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 177   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 178   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 179   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 180   { "RELAX", &bool_attr[0], &bool_attr[0] },
 181   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 182   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
 183   { 0, 0, 0 }
 184 };
 185
 186 const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] =
 187 {
 188   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 189   { "UNIT", & UNIT_attr[0], & UNIT_attr[0] },
 190   { "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] },
 191   { "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] },
 192   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 193   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 194   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 195   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 196   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 197   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 198   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 199   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 200   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 201   { "PBB", &bool_attr[0], &bool_attr[0] },
 202   { "PRIVILEGED", &bool_attr[0], &bool_attr[0] },
 203   { "NON-EXCEPTING", &bool_attr[0], &bool_attr[0] },
 204   { "CONDITIONAL", &bool_attr[0], &bool_attr[0] },
 205   { "FR-ACCESS", &bool_attr[0], &bool_attr[0] },
 206   { "PRESERVE-OVF", &bool_attr[0], &bool_attr[0] },
 207   { 0, 0, 0 }
 208 };
 209
 210 /* Instruction set variants.  */
 211
 212 static const CGEN_ISA frv_cgen_isa_table[] = {
 213   { "frv", 32, 32, 32, 32 },
 214   { 0, 0, 0, 0, 0 }
 215 };
 216
 217 /* Machine variants.  */
 218
 219 static const CGEN_MACH frv_cgen_mach_table[] = {
 220   { "frv", "frv", MACH_FRV, 0 },
 221   { "fr500", "fr500", MACH_FR500, 0 },
 222   { "tomcat", "tomcat", MACH_TOMCAT, 0 },
 223   { "fr400", "fr400", MACH_FR400, 0 },
 224   { "simple", "simple", MACH_SIMPLE, 0 },
 225   { 0, 0, 0, 0 }
 226 };
 227
 228 static CGEN_KEYWORD_ENTRY frv_cgen_opval_gr_names_entries[] =
 229 {
 230   { "sp", 1, {0, {0}}, 0, 0 },
 231   { "fp", 2, {0, {0}}, 0, 0 },
 232   { "gr0", 0, {0, {0}}, 0, 0 },
 233   { "gr1", 1, {0, {0}}, 0, 0 },
 234   { "gr2", 2, {0, {0}}, 0, 0 },
 235   { "gr3", 3, {0, {0}}, 0, 0 },
 236   { "gr4", 4, {0, {0}}, 0, 0 },
 237   { "gr5", 5, {0, {0}}, 0, 0 },
 238   { "gr6", 6, {0, {0}}, 0, 0 },
 239   { "gr7", 7, {0, {0}}, 0, 0 },
 240   { "gr8", 8, {0, {0}}, 0, 0 },
 241   { "gr9", 9, {0, {0}}, 0, 0 },
 242   { "gr10", 10, {0, {0}}, 0, 0 },
 243   { "gr11", 11, {0, {0}}, 0, 0 },
 244   { "gr12", 12, {0, {0}}, 0, 0 },
 245   { "gr13", 13, {0, {0}}, 0, 0 },
 246   { "gr14", 14, {0, {0}}, 0, 0 },
 247   { "gr15", 15, {0, {0}}, 0, 0 },
 248   { "gr16", 16, {0, {0}}, 0, 0 },
 249   { "gr17", 17, {0, {0}}, 0, 0 },
 250   { "gr18", 18, {0, {0}}, 0, 0 },
 251   { "gr19", 19, {0, {0}}, 0, 0 },
 252   { "gr20", 20, {0, {0}}, 0, 0 },
 253   { "gr21", 21, {0, {0}}, 0, 0 },
 254   { "gr22", 22, {0, {0}}, 0, 0 },
 255   { "gr23", 23, {0, {0}}, 0, 0 },
 256   { "gr24", 24, {0, {0}}, 0, 0 },
 257   { "gr25", 25, {0, {0}}, 0, 0 },
 258   { "gr26", 26, {0, {0}}, 0, 0 },
 259   { "gr27", 27, {0, {0}}, 0, 0 },
 260   { "gr28", 28, {0, {0}}, 0, 0 },
 261   { "gr29", 29, {0, {0}}, 0, 0 },
 262   { "gr30", 30, {0, {0}}, 0, 0 },
 263   { "gr31", 31, {0, {0}}, 0, 0 },
 264   { "gr32", 32, {0, {0}}, 0, 0 },
 265   { "gr33", 33, {0, {0}}, 0, 0 },
 266   { "gr34", 34, {0, {0}}, 0, 0 },
 267   { "gr35", 35, {0, {0}}, 0, 0 },
 268   { "gr36", 36, {0, {0}}, 0, 0 },
 269   { "gr37", 37, {0, {0}}, 0, 0 },
 270   { "gr38", 38, {0, {0}}, 0, 0 },
 271   { "gr39", 39, {0, {0}}, 0, 0 },
 272   { "gr40", 40, {0, {0}}, 0, 0 },
 273   { "gr41", 41, {0, {0}}, 0, 0 },
 274   { "gr42", 42, {0, {0}}, 0, 0 },
 275   { "gr43", 43, {0, {0}}, 0, 0 },
 276   { "gr44", 44, {0, {0}}, 0, 0 },
 277   { "gr45", 45, {0, {0}}, 0, 0 },
 278   { "gr46", 46, {0, {0}}, 0, 0 },
 279   { "gr47", 47, {0, {0}}, 0, 0 },
 280   { "gr48", 48, {0, {0}}, 0, 0 },
 281   { "gr49", 49, {0, {0}}, 0, 0 },
 282   { "gr50", 50, {0, {0}}, 0, 0 },
 283   { "gr51", 51, {0, {0}}, 0, 0 },
 284   { "gr52", 52, {0, {0}}, 0, 0 },
 285   { "gr53", 53, {0, {0}}, 0, 0 },
 286   { "gr54", 54, {0, {0}}, 0, 0 },
 287   { "gr55", 55, {0, {0}}, 0, 0 },
 288   { "gr56", 56, {0, {0}}, 0, 0 },
 289   { "gr57", 57, {0, {0}}, 0, 0 },
 290   { "gr58", 58, {0, {0}}, 0, 0 },
 291   { "gr59", 59, {0, {0}}, 0, 0 },
 292   { "gr60", 60, {0, {0}}, 0, 0 },
 293   { "gr61", 61, {0, {0}}, 0, 0 },
 294   { "gr62", 62, {0, {0}}, 0, 0 },
 295   { "gr63", 63, {0, {0}}, 0, 0 }
 296 };
 297
 298 CGEN_KEYWORD frv_cgen_opval_gr_names =
 299 {
 300   & frv_cgen_opval_gr_names_entries[0],
 301   66,
 302   0, 0, 0, 0, ""
 303 };
 304
 305 static CGEN_KEYWORD_ENTRY frv_cgen_opval_fr_names_entries[] =
 306 {
 307   { "fr0", 0, {0, {0}}, 0, 0 },
 308   { "fr1", 1, {0, {0}}, 0, 0 },
 309   { "fr2", 2, {0, {0}}, 0, 0 },
 310   { "fr3", 3, {0, {0}}, 0, 0 },
 311   { "fr4", 4, {0, {0}}, 0, 0 },
 312   { "fr5", 5, {0, {0}}, 0, 0 },
 313   { "fr6", 6, {0, {0}}, 0, 0 },
 314   { "fr7", 7, {0, {0}}, 0, 0 },
 315   { "fr8", 8, {0, {0}}, 0, 0 },
 316   { "fr9", 9, {0, {0}}, 0, 0 },
 317   { "fr10", 10, {0, {0}}, 0, 0 },
 318   { "fr11", 11, {0, {0}}, 0, 0 },
 319   { "fr12", 12, {0, {0}}, 0, 0 },
 320   { "fr13", 13, {0, {0}}, 0, 0 },
 321   { "fr14", 14, {0, {0}}, 0, 0 },
 322   { "fr15", 15, {0, {0}}, 0, 0 },
 323   { "fr16", 16, {0, {0}}, 0, 0 },
 324   { "fr17", 17, {0, {0}}, 0, 0 },
 325   { "fr18", 18, {0, {0}}, 0, 0 },
 326   { "fr19", 19, {0, {0}}, 0, 0 },
 327   { "fr20", 20, {0, {0}}, 0, 0 },
 328   { "fr21", 21, {0, {0}}, 0, 0 },
 329   { "fr22", 22, {0, {0}}, 0, 0 },
 330   { "fr23", 23, {0, {0}}, 0, 0 },
 331   { "fr24", 24, {0, {0}}, 0, 0 },
 332   { "fr25", 25, {0, {0}}, 0, 0 },
 333   { "fr26", 26, {0, {0}}, 0, 0 },
 334   { "fr27", 27, {0, {0}}, 0, 0 },
 335   { "fr28", 28, {0, {0}}, 0, 0 },
 336   { "fr29", 29, {0, {0}}, 0, 0 },
 337   { "fr30", 30, {0, {0}}, 0, 0 },
 338   { "fr31", 31, {0, {0}}, 0, 0 },
 339   { "fr32", 32, {0, {0}}, 0, 0 },
 340   { "fr33", 33, {0, {0}}, 0, 0 },
 341   { "fr34", 34, {0, {0}}, 0, 0 },
 342   { "fr35", 35, {0, {0}}, 0, 0 },
 343   { "fr36", 36, {0, {0}}, 0, 0 },
 344   { "fr37", 37, {0, {0}}, 0, 0 },
 345   { "fr38", 38, {0, {0}}, 0, 0 },
 346   { "fr39", 39, {0, {0}}, 0, 0 },
 347   { "fr40", 40, {0, {0}}, 0, 0 },
 348   { "fr41", 41, {0, {0}}, 0, 0 },
 349   { "fr42", 42, {0, {0}}, 0, 0 },
 350   { "fr43", 43, {0, {0}}, 0, 0 },
 351   { "fr44", 44, {0, {0}}, 0, 0 },
 352   { "fr45", 45, {0, {0}}, 0, 0 },
 353   { "fr46", 46, {0, {0}}, 0, 0 },
 354   { "fr47", 47, {0, {0}}, 0, 0 },
 355   { "fr48", 48, {0, {0}}, 0, 0 },
 356   { "fr49", 49, {0, {0}}, 0, 0 },
 357   { "fr50", 50, {0, {0}}, 0, 0 },
 358   { "fr51", 51, {0, {0}}, 0, 0 },
 359   { "fr52", 52, {0, {0}}, 0, 0 },
 360   { "fr53", 53, {0, {0}}, 0, 0 },
 361   { "fr54", 54, {0, {0}}, 0, 0 },
 362   { "fr55", 55, {0, {0}}, 0, 0 },
 363   { "fr56", 56, {0, {0}}, 0, 0 },
 364   { "fr57", 57, {0, {0}}, 0, 0 },
 365   { "fr58", 58, {0, {0}}, 0, 0 },
 366   { "fr59", 59, {0, {0}}, 0, 0 },
 367   { "fr60", 60, {0, {0}}, 0, 0 },
 368   { "fr61", 61, {0, {0}}, 0, 0 },
 369   { "fr62", 62, {0, {0}}, 0, 0 },
 370   { "fr63", 63, {0, {0}}, 0, 0 }
 371 };
 372
 373 CGEN_KEYWORD frv_cgen_opval_fr_names =
 374 {
 375   & frv_cgen_opval_fr_names_entries[0],
 376   64,
 377   0, 0, 0, 0, ""
 378 };
 379
 380 static CGEN_KEYWORD_ENTRY frv_cgen_opval_cpr_names_entries[] =
 381 {
 382   { "cpr0", 0, {0, {0}}, 0, 0 },
 383   { "cpr1", 1, {0, {0}}, 0, 0 },
 384   { "cpr2", 2, {0, {0}}, 0, 0 },
 385   { "cpr3", 3, {0, {0}}, 0, 0 },
 386   { "cpr4", 4, {0, {0}}, 0, 0 },
 387   { "cpr5", 5, {0, {0}}, 0, 0 },
 388   { "cpr6", 6, {0, {0}}, 0, 0 },
 389   { "cpr7", 7, {0, {0}}, 0, 0 },
 390   { "cpr8", 8, {0, {0}}, 0, 0 },
 391   { "cpr9", 9, {0, {0}}, 0, 0 },
 392   { "cpr10", 10, {0, {0}}, 0, 0 },
 393   { "cpr11", 11, {0, {0}}, 0, 0 },
 394   { "cpr12", 12, {0, {0}}, 0, 0 },
 395   { "cpr13", 13, {0, {0}}, 0, 0 },
 396   { "cpr14", 14, {0, {0}}, 0, 0 },
 397   { "cpr15", 15, {0, {0}}, 0, 0 },
 398   { "cpr16", 16, {0, {0}}, 0, 0 },
 399   { "cpr17", 17, {0, {0}}, 0, 0 },
 400   { "cpr18", 18, {0, {0}}, 0, 0 },
 401   { "cpr19", 19, {0, {0}}, 0, 0 },
 402   { "cpr20", 20, {0, {0}}, 0, 0 },
 403   { "cpr21", 21, {0, {0}}, 0, 0 },
 404   { "cpr22", 22, {0, {0}}, 0, 0 },
 405   { "cpr23", 23, {0, {0}}, 0, 0 },
 406   { "cpr24", 24, {0, {0}}, 0, 0 },
 407   { "cpr25", 25, {0, {0}}, 0, 0 },
 408   { "cpr26", 26, {0, {0}}, 0, 0 },
 409   { "cpr27", 27, {0, {0}}, 0, 0 },
 410   { "cpr28", 28, {0, {0}}, 0, 0 },
 411   { "cpr29", 29, {0, {0}}, 0, 0 },
 412   { "cpr30", 30, {0, {0}}, 0, 0 },
 413   { "cpr31", 31, {0, {0}}, 0, 0 },
 414   { "cpr32", 32, {0, {0}}, 0, 0 },
 415   { "cpr33", 33, {0, {0}}, 0, 0 },
 416   { "cpr34", 34, {0, {0}}, 0, 0 },
 417   { "cpr35", 35, {0, {0}}, 0, 0 },
 418   { "cpr36", 36, {0, {0}}, 0, 0 },
 419   { "cpr37", 37, {0, {0}}, 0, 0 },
 420   { "cpr38", 38, {0, {0}}, 0, 0 },
 421   { "cpr39", 39, {0, {0}}, 0, 0 },
 422   { "cpr40", 40, {0, {0}}, 0, 0 },
 423   { "cpr41", 41, {0, {0}}, 0, 0 },
 424   { "cpr42", 42, {0, {0}}, 0, 0 },
 425   { "cpr43", 43, {0, {0}}, 0, 0 },
 426   { "cpr44", 44, {0, {0}}, 0, 0 },
 427   { "cpr45", 45, {0, {0}}, 0, 0 },
 428   { "cpr46", 46, {0, {0}}, 0, 0 },
 429   { "cpr47", 47, {0, {0}}, 0, 0 },
 430   { "cpr48", 48, {0, {0}}, 0, 0 },
 431   { "cpr49", 49, {0, {0}}, 0, 0 },
 432   { "cpr50", 50, {0, {0}}, 0, 0 },
 433   { "cpr51", 51, {0, {0}}, 0, 0 },
 434   { "cpr52", 52, {0, {0}}, 0, 0 },
 435   { "cpr53", 53, {0, {0}}, 0, 0 },
 436   { "cpr54", 54, {0, {0}}, 0, 0 },
 437   { "cpr55", 55, {0, {0}}, 0, 0 },
 438   { "cpr56", 56, {0, {0}}, 0, 0 },
 439   { "cpr57", 57, {0, {0}}, 0, 0 },
 440   { "cpr58", 58, {0, {0}}, 0, 0 },
 441   { "cpr59", 59, {0, {0}}, 0, 0 },
 442   { "cpr60", 60, {0, {0}}, 0, 0 },
 443   { "cpr61", 61, {0, {0}}, 0, 0 },
 444   { "cpr62", 62, {0, {0}}, 0, 0 },
 445   { "cpr63", 63, {0, {0}}, 0, 0 }
 446 };
 447
 448 CGEN_KEYWORD frv_cgen_opval_cpr_names =
 449 {
 450   & frv_cgen_opval_cpr_names_entries[0],
 451   64,
 452   0, 0, 0, 0, ""
 453 };
 454
 455 static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] =
 456 {
 457   { "psr", 0, {0, {0}}, 0, 0 },
 458   { "pcsr", 1, {0, {0}}, 0, 0 },
 459   { "bpcsr", 2, {0, {0}}, 0, 0 },
 460   { "tbr", 3, {0, {0}}, 0, 0 },
 461   { "bpsr", 4, {0, {0}}, 0, 0 },
 462   { "hsr0", 16, {0, {0}}, 0, 0 },
 463   { "hsr1", 17, {0, {0}}, 0, 0 },
 464   { "hsr2", 18, {0, {0}}, 0, 0 },
 465   { "hsr3", 19, {0, {0}}, 0, 0 },
 466   { "hsr4", 20, {0, {0}}, 0, 0 },
 467   { "hsr5", 21, {0, {0}}, 0, 0 },
 468   { "hsr6", 22, {0, {0}}, 0, 0 },
 469   { "hsr7", 23, {0, {0}}, 0, 0 },
 470   { "hsr8", 24, {0, {0}}, 0, 0 },
 471   { "hsr9", 25, {0, {0}}, 0, 0 },
 472   { "hsr10", 26, {0, {0}}, 0, 0 },
 473   { "hsr11", 27, {0, {0}}, 0, 0 },
 474   { "hsr12", 28, {0, {0}}, 0, 0 },
 475   { "hsr13", 29, {0, {0}}, 0, 0 },
 476   { "hsr14", 30, {0, {0}}, 0, 0 },
 477   { "hsr15", 31, {0, {0}}, 0, 0 },
 478   { "hsr16", 32, {0, {0}}, 0, 0 },
 479   { "hsr17", 33, {0, {0}}, 0, 0 },
 480   { "hsr18", 34, {0, {0}}, 0, 0 },
 481   { "hsr19", 35, {0, {0}}, 0, 0 },
 482   { "hsr20", 36, {0, {0}}, 0, 0 },
 483   { "hsr21", 37, {0, {0}}, 0, 0 },
 484   { "hsr22", 38, {0, {0}}, 0, 0 },
 485   { "hsr23", 39, {0, {0}}, 0, 0 },
 486   { "hsr24", 40, {0, {0}}, 0, 0 },
 487   { "hsr25", 41, {0, {0}}, 0, 0 },
 488   { "hsr26", 42, {0, {0}}, 0, 0 },
 489   { "hsr27", 43, {0, {0}}, 0, 0 },
 490   { "hsr28", 44, {0, {0}}, 0, 0 },
 491   { "hsr29", 45, {0, {0}}, 0, 0 },
 492   { "hsr30", 46, {0, {0}}, 0, 0 },
 493   { "hsr31", 47, {0, {0}}, 0, 0 },
 494   { "hsr32", 48, {0, {0}}, 0, 0 },
 495   { "hsr33", 49, {0, {0}}, 0, 0 },
 496   { "hsr34", 50, {0, {0}}, 0, 0 },
 497   { "hsr35", 51, {0, {0}}, 0, 0 },
 498   { "hsr36", 52, {0, {0}}, 0, 0 },
 499   { "hsr37", 53, {0, {0}}, 0, 0 },
 500   { "hsr38", 54, {0, {0}}, 0, 0 },
 501   { "hsr39", 55, {0, {0}}, 0, 0 },
 502   { "hsr40", 56, {0, {0}}, 0, 0 },
 503   { "hsr41", 57, {0, {0}}, 0, 0 },
 504   { "hsr42", 58, {0, {0}}, 0, 0 },
 505   { "hsr43", 59, {0, {0}}, 0, 0 },
 506   { "hsr44", 60, {0, {0}}, 0, 0 },
 507   { "hsr45", 61, {0, {0}}, 0, 0 },
 508   { "hsr46", 62, {0, {0}}, 0, 0 },
 509   { "hsr47", 63, {0, {0}}, 0, 0 },
 510   { "hsr48", 64, {0, {0}}, 0, 0 },
 511   { "hsr49", 65, {0, {0}}, 0, 0 },
 512   { "hsr50", 66, {0, {0}}, 0, 0 },
 513   { "hsr51", 67, {0, {0}}, 0, 0 },
 514   { "hsr52", 68, {0, {0}}, 0, 0 },
 515   { "hsr53", 69, {0, {0}}, 0, 0 },
 516   { "hsr54", 70, {0, {0}}, 0, 0 },
 517   { "hsr55", 71, {0, {0}}, 0, 0 },
 518   { "hsr56", 72, {0, {0}}, 0, 0 },
 519   { "hsr57", 73, {0, {0}}, 0, 0 },
 520   { "hsr58", 74, {0, {0}}, 0, 0 },
 521   { "hsr59", 75, {0, {0}}, 0, 0 },
 522   { "hsr60", 76, {0, {0}}, 0, 0 },
 523   { "hsr61", 77, {0, {0}}, 0, 0 },
 524   { "hsr62", 78, {0, {0}}, 0, 0 },
 525   { "hsr63", 79, {0, {0}}, 0, 0 },
 526   { "ccr", 256, {0, {0}}, 0, 0 },
 527   { "cccr", 263, {0, {0}}, 0, 0 },
 528   { "lr", 272, {0, {0}}, 0, 0 },
 529   { "lcr", 273, {0, {0}}, 0, 0 },
 530   { "isr", 288, {0, {0}}, 0, 0 },
 531   { "neear0", 352, {0, {0}}, 0, 0 },
 532   { "neear1", 353, {0, {0}}, 0, 0 },
 533   { "neear2", 354, {0, {0}}, 0, 0 },
 534   { "neear3", 355, {0, {0}}, 0, 0 },
 535   { "neear4", 356, {0, {0}}, 0, 0 },
 536   { "neear5", 357, {0, {0}}, 0, 0 },
 537   { "neear6", 358, {0, {0}}, 0, 0 },
 538   { "neear7", 359, {0, {0}}, 0, 0 },
 539   { "neear8", 360, {0, {0}}, 0, 0 },
 540   { "neear9", 361, {0, {0}}, 0, 0 },
 541   { "neear10", 362, {0, {0}}, 0, 0 },
 542   { "neear11", 363, {0, {0}}, 0, 0 },
 543   { "neear12", 364, {0, {0}}, 0, 0 },
 544   { "neear13", 365, {0, {0}}, 0, 0 },
 545   { "neear14", 366, {0, {0}}, 0, 0 },
 546   { "neear15", 367, {0, {0}}, 0, 0 },
 547   { "neear16", 368, {0, {0}}, 0, 0 },
 548   { "neear17", 369, {0, {0}}, 0, 0 },
 549   { "neear18", 370, {0, {0}}, 0, 0 },
 550   { "neear19", 371, {0, {0}}, 0, 0 },
 551   { "neear20", 372, {0, {0}}, 0, 0 },
 552   { "neear21", 373, {0, {0}}, 0, 0 },
 553   { "neear22", 374, {0, {0}}, 0, 0 },
 554   { "neear23", 375, {0, {0}}, 0, 0 },
 555   { "neear24", 376, {0, {0}}, 0, 0 },
 556   { "neear25", 377, {0, {0}}, 0, 0 },
 557   { "neear26", 378, {0, {0}}, 0, 0 },
 558   { "neear27", 379, {0, {0}}, 0, 0 },
 559   { "neear28", 380, {0, {0}}, 0, 0 },
 560   { "neear29", 381, {0, {0}}, 0, 0 },
 561   { "neear30", 382, {0, {0}}, 0, 0 },
 562   { "neear31", 383, {0, {0}}, 0, 0 },
 563   { "nesr0", 384, {0, {0}}, 0, 0 },
 564   { "nesr1", 385, {0, {0}}, 0, 0 },
 565   { "nesr2", 386, {0, {0}}, 0, 0 },
 566   { "nesr3", 387, {0, {0}}, 0, 0 },
 567   { "nesr4", 388, {0, {0}}, 0, 0 },
 568   { "nesr5", 389, {0, {0}}, 0, 0 },
 569   { "nesr6", 390, {0, {0}}, 0, 0 },
 570   { "nesr7", 391, {0, {0}}, 0, 0 },
 571   { "nesr8", 392, {0, {0}}, 0, 0 },
 572   { "nesr9", 393, {0, {0}}, 0, 0 },
 573   { "nesr10", 394, {0, {0}}, 0, 0 },
 574   { "nesr11", 395, {0, {0}}, 0, 0 },
 575   { "nesr12", 396, {0, {0}}, 0, 0 },
 576   { "nesr13", 397, {0, {0}}, 0, 0 },
 577   { "nesr14", 398, {0, {0}}, 0, 0 },
 578   { "nesr15", 399, {0, {0}}, 0, 0 },
 579   { "nesr16", 400, {0, {0}}, 0, 0 },
 580   { "nesr17", 401, {0, {0}}, 0, 0 },
 581   { "nesr18", 402, {0, {0}}, 0, 0 },
 582   { "nesr19", 403, {0, {0}}, 0, 0 },
 583   { "nesr20", 404, {0, {0}}, 0, 0 },
 584   { "nesr21", 405, {0, {0}}, 0, 0 },
 585   { "nesr22", 406, {0, {0}}, 0, 0 },
 586   { "nesr23", 407, {0, {0}}, 0, 0 },
 587   { "nesr24", 408, {0, {0}}, 0, 0 },
 588   { "nesr25", 409, {0, {0}}, 0, 0 },
 589   { "nesr26", 410, {0, {0}}, 0, 0 },
 590   { "nesr27", 411, {0, {0}}, 0, 0 },
 591   { "nesr28", 412, {0, {0}}, 0, 0 },
 592   { "nesr29", 413, {0, {0}}, 0, 0 },
 593   { "nesr30", 414, {0, {0}}, 0, 0 },
 594   { "nesr31", 415, {0, {0}}, 0, 0 },
 595   { "necr", 416, {0, {0}}, 0, 0 },
 596   { "gner0", 432, {0, {0}}, 0, 0 },
 597   { "gner1", 433, {0, {0}}, 0, 0 },
 598   { "fner0", 434, {0, {0}}, 0, 0 },
 599   { "fner1", 435, {0, {0}}, 0, 0 },
 600   { "epcr0", 512, {0, {0}}, 0, 0 },
 601   { "epcr1", 513, {0, {0}}, 0, 0 },
 602   { "epcr2", 514, {0, {0}}, 0, 0 },
 603   { "epcr3", 515, {0, {0}}, 0, 0 },
 604   { "epcr4", 516, {0, {0}}, 0, 0 },
 605   { "epcr5", 517, {0, {0}}, 0, 0 },
 606   { "epcr6", 518, {0, {0}}, 0, 0 },
 607   { "epcr7", 519, {0, {0}}, 0, 0 },
 608   { "epcr8", 520, {0, {0}}, 0, 0 },
 609   { "epcr9", 521, {0, {0}}, 0, 0 },
 610   { "epcr10", 522, {0, {0}}, 0, 0 },
 611   { "epcr11", 523, {0, {0}}, 0, 0 },
 612   { "epcr12", 524, {0, {0}}, 0, 0 },
 613   { "epcr13", 525, {0, {0}}, 0, 0 },
 614   { "epcr14", 526, {0, {0}}, 0, 0 },
 615   { "epcr15", 527, {0, {0}}, 0, 0 },
 616   { "epcr16", 528, {0, {0}}, 0, 0 },
 617   { "epcr17", 529, {0, {0}}, 0, 0 },
 618   { "epcr18", 530, {0, {0}}, 0, 0 },
 619   { "epcr19", 531, {0, {0}}, 0, 0 },
 620   { "epcr20", 532, {0, {0}}, 0, 0 },
 621   { "epcr21", 533, {0, {0}}, 0, 0 },
 622   { "epcr22", 534, {0, {0}}, 0, 0 },
 623   { "epcr23", 535, {0, {0}}, 0, 0 },
 624   { "epcr24", 536, {0, {0}}, 0, 0 },
 625   { "epcr25", 537, {0, {0}}, 0, 0 },
 626   { "epcr26", 538, {0, {0}}, 0, 0 },
 627   { "epcr27", 539, {0, {0}}, 0, 0 },
 628   { "epcr28", 540, {0, {0}}, 0, 0 },
 629   { "epcr29", 541, {0, {0}}, 0, 0 },
 630   { "epcr30", 542, {0, {0}}, 0, 0 },
 631   { "epcr31", 543, {0, {0}}, 0, 0 },
 632   { "epcr32", 544, {0, {0}}, 0, 0 },
 633   { "epcr33", 545, {0, {0}}, 0, 0 },
 634   { "epcr34", 546, {0, {0}}, 0, 0 },
 635   { "epcr35", 547, {0, {0}}, 0, 0 },
 636   { "epcr36", 548, {0, {0}}, 0, 0 },
 637   { "epcr37", 549, {0, {0}}, 0, 0 },
 638   { "epcr38", 550, {0, {0}}, 0, 0 },
 639   { "epcr39", 551, {0, {0}}, 0, 0 },
 640   { "epcr40", 552, {0, {0}}, 0, 0 },
 641   { "epcr41", 553, {0, {0}}, 0, 0 },
 642   { "epcr42", 554, {0, {0}}, 0, 0 },
 643   { "epcr43", 555, {0, {0}}, 0, 0 },
 644   { "epcr44", 556, {0, {0}}, 0, 0 },
 645   { "epcr45", 557, {0, {0}}, 0, 0 },
 646   { "epcr46", 558, {0, {0}}, 0, 0 },
 647   { "epcr47", 559, {0, {0}}, 0, 0 },
 648   { "epcr48", 560, {0, {0}}, 0, 0 },
 649   { "epcr49", 561, {0, {0}}, 0, 0 },
 650   { "epcr50", 562, {0, {0}}, 0, 0 },
 651   { "epcr51", 563, {0, {0}}, 0, 0 },
 652   { "epcr52", 564, {0, {0}}, 0, 0 },
 653   { "epcr53", 565, {0, {0}}, 0, 0 },
 654   { "epcr54", 566, {0, {0}}, 0, 0 },
 655   { "epcr55", 567, {0, {0}}, 0, 0 },
 656   { "epcr56", 568, {0, {0}}, 0, 0 },
 657   { "epcr57", 569, {0, {0}}, 0, 0 },
 658   { "epcr58", 570, {0, {0}}, 0, 0 },
 659   { "epcr59", 571, {0, {0}}, 0, 0 },
 660   { "epcr60", 572, {0, {0}}, 0, 0 },
 661   { "epcr61", 573, {0, {0}}, 0, 0 },
 662   { "epcr62", 574, {0, {0}}, 0, 0 },
 663   { "epcr63", 575, {0, {0}}, 0, 0 },
 664   { "esr0", 576, {0, {0}}, 0, 0 },
 665   { "esr1", 577, {0, {0}}, 0, 0 },
 666   { "esr2", 578, {0, {0}}, 0, 0 },
 667   { "esr3", 579, {0, {0}}, 0, 0 },
 668   { "esr4", 580, {0, {0}}, 0, 0 },
 669   { "esr5", 581, {0, {0}}, 0, 0 },
 670   { "esr6", 582, {0, {0}}, 0, 0 },
 671   { "esr7", 583, {0, {0}}, 0, 0 },
 672   { "esr8", 584, {0, {0}}, 0, 0 },
 673   { "esr9", 585, {0, {0}}, 0, 0 },
 674   { "esr10", 586, {0, {0}}, 0, 0 },
 675   { "esr11", 587, {0, {0}}, 0, 0 },
 676   { "esr12", 588, {0, {0}}, 0, 0 },
 677   { "esr13", 589, {0, {0}}, 0, 0 },
 678   { "esr14", 590, {0, {0}}, 0, 0 },
 679   { "esr15", 591, {0, {0}}, 0, 0 },
 680   { "esr16", 592, {0, {0}}, 0, 0 },
 681   { "esr17", 593, {0, {0}}, 0, 0 },
 682   { "esr18", 594, {0, {0}}, 0, 0 },
 683   { "esr19", 595, {0, {0}}, 0, 0 },
 684   { "esr20", 596, {0, {0}}, 0, 0 },
 685   { "esr21", 597, {0, {0}}, 0, 0 },
 686   { "esr22", 598, {0, {0}}, 0, 0 },
 687   { "esr23", 599, {0, {0}}, 0, 0 },
 688   { "esr24", 600, {0, {0}}, 0, 0 },
 689   { "esr25", 601, {0, {0}}, 0, 0 },
 690   { "esr26", 602, {0, {0}}, 0, 0 },
 691   { "esr27", 603, {0, {0}}, 0, 0 },
 692   { "esr28", 604, {0, {0}}, 0, 0 },
 693   { "esr29", 605, {0, {0}}, 0, 0 },
 694   { "esr30", 606, {0, {0}}, 0, 0 },
 695   { "esr31", 607, {0, {0}}, 0, 0 },
 696   { "esr32", 608, {0, {0}}, 0, 0 },
 697   { "esr33", 609, {0, {0}}, 0, 0 },
 698   { "esr34", 610, {0, {0}}, 0, 0 },
 699   { "esr35", 611, {0, {0}}, 0, 0 },
 700   { "esr36", 612, {0, {0}}, 0, 0 },
 701   { "esr37", 613, {0, {0}}, 0, 0 },
 702   { "esr38", 614, {0, {0}}, 0, 0 },
 703   { "esr39", 615, {0, {0}}, 0, 0 },
 704   { "esr40", 616, {0, {0}}, 0, 0 },
 705   { "esr41", 617, {0, {0}}, 0, 0 },
 706   { "esr42", 618, {0, {0}}, 0, 0 },
 707   { "esr43", 619, {0, {0}}, 0, 0 },
 708   { "esr44", 620, {0, {0}}, 0, 0 },
 709   { "esr45", 621, {0, {0}}, 0, 0 },
 710   { "esr46", 622, {0, {0}}, 0, 0 },
 711   { "esr47", 623, {0, {0}}, 0, 0 },
 712   { "esr48", 624, {0, {0}}, 0, 0 },
 713   { "esr49", 625, {0, {0}}, 0, 0 },
 714   { "esr50", 626, {0, {0}}, 0, 0 },
 715   { "esr51", 627, {0, {0}}, 0, 0 },
 716   { "esr52", 628, {0, {0}}, 0, 0 },
 717   { "esr53", 629, {0, {0}}, 0, 0 },
 718   { "esr54", 630, {0, {0}}, 0, 0 },
 719   { "esr55", 631, {0, {0}}, 0, 0 },
 720   { "esr56", 632, {0, {0}}, 0, 0 },
 721   { "esr57", 633, {0, {0}}, 0, 0 },
 722   { "esr58", 634, {0, {0}}, 0, 0 },
 723   { "esr59", 635, {0, {0}}, 0, 0 },
 724   { "esr60", 636, {0, {0}}, 0, 0 },
 725   { "esr61", 637, {0, {0}}, 0, 0 },
 726   { "esr62", 638, {0, {0}}, 0, 0 },
 727   { "esr63", 639, {0, {0}}, 0, 0 },
 728   { "eir0", 640, {0, {0}}, 0, 0 },
 729   { "eir1", 641, {0, {0}}, 0, 0 },
 730   { "eir2", 642, {0, {0}}, 0, 0 },
 731   { "eir3", 643, {0, {0}}, 0, 0 },
 732   { "eir4", 644, {0, {0}}, 0, 0 },
 733   { "eir5", 645, {0, {0}}, 0, 0 },
 734   { "eir6", 646, {0, {0}}, 0, 0 },
 735   { "eir7", 647, {0, {0}}, 0, 0 },
 736   { "eir8", 648, {0, {0}}, 0, 0 },
 737   { "eir9", 649, {0, {0}}, 0, 0 },
 738   { "eir10", 650, {0, {0}}, 0, 0 },
 739   { "eir11", 651, {0, {0}}, 0, 0 },
 740   { "eir12", 652, {0, {0}}, 0, 0 },
 741   { "eir13", 653, {0, {0}}, 0, 0 },
 742   { "eir14", 654, {0, {0}}, 0, 0 },
 743   { "eir15", 655, {0, {0}}, 0, 0 },
 744   { "eir16", 656, {0, {0}}, 0, 0 },
 745   { "eir17", 657, {0, {0}}, 0, 0 },
 746   { "eir18", 658, {0, {0}}, 0, 0 },
 747   { "eir19", 659, {0, {0}}, 0, 0 },
 748   { "eir20", 660, {0, {0}}, 0, 0 },
 749   { "eir21", 661, {0, {0}}, 0, 0 },
 750   { "eir22", 662, {0, {0}}, 0, 0 },
 751   { "eir23", 663, {0, {0}}, 0, 0 },
 752   { "eir24", 664, {0, {0}}, 0, 0 },
 753   { "eir25", 665, {0, {0}}, 0, 0 },
 754   { "eir26", 666, {0, {0}}, 0, 0 },
 755   { "eir27", 667, {0, {0}}, 0, 0 },
 756   { "eir28", 668, {0, {0}}, 0, 0 },
 757   { "eir29", 669, {0, {0}}, 0, 0 },
 758   { "eir30", 670, {0, {0}}, 0, 0 },
 759   { "eir31", 671, {0, {0}}, 0, 0 },
 760   { "esfr0", 672, {0, {0}}, 0, 0 },
 761   { "esfr1", 673, {0, {0}}, 0, 0 },
 762   { "sr0", 768, {0, {0}}, 0, 0 },
 763   { "sr1", 769, {0, {0}}, 0, 0 },
 764   { "sr2", 770, {0, {0}}, 0, 0 },
 765   { "sr3", 771, {0, {0}}, 0, 0 },
 766   { "fsr0", 1024, {0, {0}}, 0, 0 },
 767   { "fsr1", 1025, {0, {0}}, 0, 0 },
 768   { "fsr2", 1026, {0, {0}}, 0, 0 },
 769   { "fsr3", 1027, {0, {0}}, 0, 0 },
 770   { "fsr4", 1028, {0, {0}}, 0, 0 },
 771   { "fsr5", 1029, {0, {0}}, 0, 0 },
 772   { "fsr6", 1030, {0, {0}}, 0, 0 },
 773   { "fsr7", 1031, {0, {0}}, 0, 0 },
 774   { "fsr8", 1032, {0, {0}}, 0, 0 },
 775   { "fsr9", 1033, {0, {0}}, 0, 0 },
 776   { "fsr10", 1034, {0, {0}}, 0, 0 },
 777   { "fsr11", 1035, {0, {0}}, 0, 0 },
 778   { "fsr12", 1036, {0, {0}}, 0, 0 },
 779   { "fsr13", 1037, {0, {0}}, 0, 0 },
 780   { "fsr14", 1038, {0, {0}}, 0, 0 },
 781   { "fsr15", 1039, {0, {0}}, 0, 0 },
 782   { "fsr16", 1040, {0, {0}}, 0, 0 },
 783   { "fsr17", 1041, {0, {0}}, 0, 0 },
 784   { "fsr18", 1042, {0, {0}}, 0, 0 },
 785   { "fsr19", 1043, {0, {0}}, 0, 0 },
 786   { "fsr20", 1044, {0, {0}}, 0, 0 },
 787   { "fsr21", 1045, {0, {0}}, 0, 0 },
 788   { "fsr22", 1046, {0, {0}}, 0, 0 },
 789   { "fsr23", 1047, {0, {0}}, 0, 0 },
 790   { "fsr24", 1048, {0, {0}}, 0, 0 },
 791   { "fsr25", 1049, {0, {0}}, 0, 0 },
 792   { "fsr26", 1050, {0, {0}}, 0, 0 },
 793   { "fsr27", 1051, {0, {0}}, 0, 0 },
 794   { "fsr28", 1052, {0, {0}}, 0, 0 },
 795   { "fsr29", 1053, {0, {0}}, 0, 0 },
 796   { "fsr30", 1054, {0, {0}}, 0, 0 },
 797   { "fsr31", 1055, {0, {0}}, 0, 0 },
 798   { "fsr32", 1056, {0, {0}}, 0, 0 },
 799   { "fsr33", 1057, {0, {0}}, 0, 0 },
 800   { "fsr34", 1058, {0, {0}}, 0, 0 },
 801   { "fsr35", 1059, {0, {0}}, 0, 0 },
 802   { "fsr36", 1060, {0, {0}}, 0, 0 },
 803   { "fsr37", 1061, {0, {0}}, 0, 0 },
 804   { "fsr38", 1062, {0, {0}}, 0, 0 },
 805   { "fsr39", 1063, {0, {0}}, 0, 0 },
 806   { "fsr40", 1064, {0, {0}}, 0, 0 },
 807   { "fsr41", 1065, {0, {0}}, 0, 0 },
 808   { "fsr42", 1066, {0, {0}}, 0, 0 },
 809   { "fsr43", 1067, {0, {0}}, 0, 0 },
 810   { "fsr44", 1068, {0, {0}}, 0, 0 },
 811   { "fsr45", 1069, {0, {0}}, 0, 0 },
 812   { "fsr46", 1070, {0, {0}}, 0, 0 },
 813   { "fsr47", 1071, {0, {0}}, 0, 0 },
 814   { "fsr48", 1072, {0, {0}}, 0, 0 },
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 820   { "fsr54", 1078, {0, {0}}, 0, 0 },
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 822   { "fsr56", 1080, {0, {0}}, 0, 0 },
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 826   { "fsr60", 1084, {0, {0}}, 0, 0 },
 827   { "fsr61", 1085, {0, {0}}, 0, 0 },
 828   { "fsr62", 1086, {0, {0}}, 0, 0 },
 829   { "fsr63", 1087, {0, {0}}, 0, 0 },
 830   { "fqop0", 1088, {0, {0}}, 0, 0 },
 831   { "fqop1", 1090, {0, {0}}, 0, 0 },
 832   { "fqop2", 1092, {0, {0}}, 0, 0 },
 833   { "fqop3", 1094, {0, {0}}, 0, 0 },
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 835   { "fqop5", 1098, {0, {0}}, 0, 0 },
 836   { "fqop6", 1100, {0, {0}}, 0, 0 },
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 895   { "mcilr1", 1273, {0, {0}}, 0, 0 },
 896   { "msr0", 1280, {0, {0}}, 0, 0 },
 897   { "msr1", 1281, {0, {0}}, 0, 0 },
 898   { "msr2", 1282, {0, {0}}, 0, 0 },
 899   { "msr3", 1283, {0, {0}}, 0, 0 },
 900   { "msr4", 1284, {0, {0}}, 0, 0 },
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 902   { "msr6", 1286, {0, {0}}, 0, 0 },
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 905   { "msr9", 1289, {0, {0}}, 0, 0 },
 906   { "msr10", 1290, {0, {0}}, 0, 0 },
 907   { "msr11", 1291, {0, {0}}, 0, 0 },
 908   { "msr12", 1292, {0, {0}}, 0, 0 },
 909   { "msr13", 1293, {0, {0}}, 0, 0 },
 910   { "msr14", 1294, {0, {0}}, 0, 0 },
 911   { "msr15", 1295, {0, {0}}, 0, 0 },
 912   { "msr16", 1296, {0, {0}}, 0, 0 },
 913   { "msr17", 1297, {0, {0}}, 0, 0 },
 914   { "msr18", 1298, {0, {0}}, 0, 0 },
 915   { "msr19", 1299, {0, {0}}, 0, 0 },
 916   { "msr20", 1300, {0, {0}}, 0, 0 },
 917   { "msr21", 1301, {0, {0}}, 0, 0 },
 918   { "msr22", 1302, {0, {0}}, 0, 0 },
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 920   { "msr24", 1304, {0, {0}}, 0, 0 },
 921   { "msr25", 1305, {0, {0}}, 0, 0 },
 922   { "msr26", 1306, {0, {0}}, 0, 0 },
 923   { "msr27", 1307, {0, {0}}, 0, 0 },
 924   { "msr28", 1308, {0, {0}}, 0, 0 },
 925   { "msr29", 1309, {0, {0}}, 0, 0 },
 926   { "msr30", 1310, {0, {0}}, 0, 0 },
 927   { "msr31", 1311, {0, {0}}, 0, 0 },
 928   { "msr32", 1312, {0, {0}}, 0, 0 },
 929   { "msr33", 1313, {0, {0}}, 0, 0 },
 930   { "msr34", 1314, {0, {0}}, 0, 0 },
 931   { "msr35", 1315, {0, {0}}, 0, 0 },
 932   { "msr36", 1316, {0, {0}}, 0, 0 },
 933   { "msr37", 1317, {0, {0}}, 0, 0 },
 934   { "msr38", 1318, {0, {0}}, 0, 0 },
 935   { "msr39", 1319, {0, {0}}, 0, 0 },
 936   { "msr40", 1320, {0, {0}}, 0, 0 },
 937   { "msr41", 1321, {0, {0}}, 0, 0 },
 938   { "msr42", 1322, {0, {0}}, 0, 0 },
 939   { "msr43", 1323, {0, {0}}, 0, 0 },
 940   { "msr44", 1324, {0, {0}}, 0, 0 },
 941   { "msr45", 1325, {0, {0}}, 0, 0 },
 942   { "msr46", 1326, {0, {0}}, 0, 0 },
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 944   { "msr48", 1328, {0, {0}}, 0, 0 },
 945   { "msr49", 1329, {0, {0}}, 0, 0 },
 946   { "msr50", 1330, {0, {0}}, 0, 0 },
 947   { "msr51", 1331, {0, {0}}, 0, 0 },
 948   { "msr52", 1332, {0, {0}}, 0, 0 },
 949   { "msr53", 1333, {0, {0}}, 0, 0 },
 950   { "msr54", 1334, {0, {0}}, 0, 0 },
 951   { "msr55", 1335, {0, {0}}, 0, 0 },
 952   { "msr56", 1336, {0, {0}}, 0, 0 },
 953   { "msr57", 1337, {0, {0}}, 0, 0 },
 954   { "msr58", 1338, {0, {0}}, 0, 0 },
 955   { "msr59", 1339, {0, {0}}, 0, 0 },
 956   { "msr60", 1340, {0, {0}}, 0, 0 },
 957   { "msr61", 1341, {0, {0}}, 0, 0 },
 958   { "msr62", 1342, {0, {0}}, 0, 0 },
 959   { "msr63", 1343, {0, {0}}, 0, 0 },
 960   { "mqop0", 1344, {0, {0}}, 0, 0 },
 961   { "mqop1", 1346, {0, {0}}, 0, 0 },
 962   { "mqop2", 1348, {0, {0}}, 0, 0 },
 963   { "mqop3", 1350, {0, {0}}, 0, 0 },
 964   { "mqop4", 1352, {0, {0}}, 0, 0 },
 965   { "mqop5", 1354, {0, {0}}, 0, 0 },
 966   { "mqop6", 1356, {0, {0}}, 0, 0 },
 967   { "mqop7", 1358, {0, {0}}, 0, 0 },
 968   { "mqop8", 1360, {0, {0}}, 0, 0 },
 969   { "mqop9", 1362, {0, {0}}, 0, 0 },
 970   { "mqop10", 1364, {0, {0}}, 0, 0 },
 971   { "mqop11", 1366, {0, {0}}, 0, 0 },
 972   { "mqop12", 1368, {0, {0}}, 0, 0 },
 973   { "mqop13", 1370, {0, {0}}, 0, 0 },
 974   { "mqop14", 1372, {0, {0}}, 0, 0 },
 975   { "mqop15", 1374, {0, {0}}, 0, 0 },
 976   { "mqop16", 1376, {0, {0}}, 0, 0 },
 977   { "mqop17", 1378, {0, {0}}, 0, 0 },
 978   { "mqop18", 1380, {0, {0}}, 0, 0 },
 979   { "mqop19", 1382, {0, {0}}, 0, 0 },
 980   { "mqop20", 1384, {0, {0}}, 0, 0 },
 981   { "mqop21", 1386, {0, {0}}, 0, 0 },
 982   { "mqop22", 1388, {0, {0}}, 0, 0 },
 983   { "mqop23", 1390, {0, {0}}, 0, 0 },
 984   { "mqop24", 1392, {0, {0}}, 0, 0 },
 985   { "mqop25", 1394, {0, {0}}, 0, 0 },
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 987   { "mqop27", 1398, {0, {0}}, 0, 0 },
 988   { "mqop28", 1400, {0, {0}}, 0, 0 },
 989   { "mqop29", 1402, {0, {0}}, 0, 0 },
 990   { "mqop30", 1404, {0, {0}}, 0, 0 },
 991   { "mqop31", 1406, {0, {0}}, 0, 0 },
 992   { "mqst0", 1345, {0, {0}}, 0, 0 },
 993   { "mqst1", 1347, {0, {0}}, 0, 0 },
 994   { "mqst2", 1349, {0, {0}}, 0, 0 },
 995   { "mqst3", 1351, {0, {0}}, 0, 0 },
 996   { "mqst4", 1353, {0, {0}}, 0, 0 },
 997   { "mqst5", 1355, {0, {0}}, 0, 0 },
 998   { "mqst6", 1357, {0, {0}}, 0, 0 },
 999   { "mqst7", 1359, {0, {0}}, 0, 0 },
1000   { "mqst8", 1361, {0, {0}}, 0, 0 },
1001   { "mqst9", 1363, {0, {0}}, 0, 0 },
1002   { "mqst10", 1365, {0, {0}}, 0, 0 },
1003   { "mqst11", 1367, {0, {0}}, 0, 0 },
1004   { "mqst12", 1369, {0, {0}}, 0, 0 },
1005   { "mqst13", 1371, {0, {0}}, 0, 0 },
1006   { "mqst14", 1373, {0, {0}}, 0, 0 },
1007   { "mqst15", 1375, {0, {0}}, 0, 0 },
1008   { "mqst16", 1377, {0, {0}}, 0, 0 },
1009   { "mqst17", 1379, {0, {0}}, 0, 0 },
1010   { "mqst18", 1381, {0, {0}}, 0, 0 },
1011   { "mqst19", 1383, {0, {0}}, 0, 0 },
1012   { "mqst20", 1385, {0, {0}}, 0, 0 },
1013   { "mqst21", 1387, {0, {0}}, 0, 0 },
1014   { "mqst22", 1389, {0, {0}}, 0, 0 },
1015   { "mqst23", 1391, {0, {0}}, 0, 0 },
1016   { "mqst24", 1393, {0, {0}}, 0, 0 },
1017   { "mqst25", 1395, {0, {0}}, 0, 0 },
1018   { "mqst26", 1397, {0, {0}}, 0, 0 },
1019   { "mqst27", 1399, {0, {0}}, 0, 0 },
1020   { "mqst28", 1401, {0, {0}}, 0, 0 },
1021   { "mqst29", 1403, {0, {0}}, 0, 0 },
1022   { "mqst30", 1405, {0, {0}}, 0, 0 },
1023   { "mqst31", 1407, {0, {0}}, 0, 0 },
1024   { "ear0", 1536, {0, {0}}, 0, 0 },
1025   { "ear1", 1537, {0, {0}}, 0, 0 },
1026   { "ear2", 1538, {0, {0}}, 0, 0 },
1027   { "ear3", 1539, {0, {0}}, 0, 0 },
1028   { "ear4", 1540, {0, {0}}, 0, 0 },
1029   { "ear5", 1541, {0, {0}}, 0, 0 },
1030   { "ear6", 1542, {0, {0}}, 0, 0 },
1031   { "ear7", 1543, {0, {0}}, 0, 0 },
1032   { "ear8", 1544, {0, {0}}, 0, 0 },
1033   { "ear9", 1545, {0, {0}}, 0, 0 },
1034   { "ear10", 1546, {0, {0}}, 0, 0 },
1035   { "ear11", 1547, {0, {0}}, 0, 0 },
1036   { "ear12", 1548, {0, {0}}, 0, 0 },
1037   { "ear13", 1549, {0, {0}}, 0, 0 },
1038   { "ear14", 1550, {0, {0}}, 0, 0 },
1039   { "ear15", 1551, {0, {0}}, 0, 0 },
1040   { "ear16", 1552, {0, {0}}, 0, 0 },
1041   { "ear17", 1553, {0, {0}}, 0, 0 },
1042   { "ear18", 1554, {0, {0}}, 0, 0 },
1043   { "ear19", 1555, {0, {0}}, 0, 0 },
1044   { "ear20", 1556, {0, {0}}, 0, 0 },
1045   { "ear21", 1557, {0, {0}}, 0, 0 },
1046   { "ear22", 1558, {0, {0}}, 0, 0 },
1047   { "ear23", 1559, {0, {0}}, 0, 0 },
1048   { "ear24", 1560, {0, {0}}, 0, 0 },
1049   { "ear25", 1561, {0, {0}}, 0, 0 },
1050   { "ear26", 1562, {0, {0}}, 0, 0 },
1051   { "ear27", 1563, {0, {0}}, 0, 0 },
1052   { "ear28", 1564, {0, {0}}, 0, 0 },
1053   { "ear29", 1565, {0, {0}}, 0, 0 },
1054   { "ear30", 1566, {0, {0}}, 0, 0 },
1055   { "ear31", 1567, {0, {0}}, 0, 0 },
1056   { "ear32", 1568, {0, {0}}, 0, 0 },
1057   { "ear33", 1569, {0, {0}}, 0, 0 },
1058   { "ear34", 1570, {0, {0}}, 0, 0 },
1059   { "ear35", 1571, {0, {0}}, 0, 0 },
1060   { "ear36", 1572, {0, {0}}, 0, 0 },
1061   { "ear37", 1573, {0, {0}}, 0, 0 },
1062   { "ear38", 1574, {0, {0}}, 0, 0 },
1063   { "ear39", 1575, {0, {0}}, 0, 0 },
1064   { "ear40", 1576, {0, {0}}, 0, 0 },
1065   { "ear41", 1577, {0, {0}}, 0, 0 },
1066   { "ear42", 1578, {0, {0}}, 0, 0 },
1067   { "ear43", 1579, {0, {0}}, 0, 0 },
1068   { "ear44", 1580, {0, {0}}, 0, 0 },
1069   { "ear45", 1581, {0, {0}}, 0, 0 },
1070   { "ear46", 1582, {0, {0}}, 0, 0 },
1071   { "ear47", 1583, {0, {0}}, 0, 0 },
1072   { "ear48", 1584, {0, {0}}, 0, 0 },
1073   { "ear49", 1585, {0, {0}}, 0, 0 },
1074   { "ear50", 1586, {0, {0}}, 0, 0 },
1075   { "ear51", 1587, {0, {0}}, 0, 0 },
1076   { "ear52", 1588, {0, {0}}, 0, 0 },
1077   { "ear53", 1589, {0, {0}}, 0, 0 },
1078   { "ear54", 1590, {0, {0}}, 0, 0 },
1079   { "ear55", 1591, {0, {0}}, 0, 0 },
1080   { "ear56", 1592, {0, {0}}, 0, 0 },
1081   { "ear57", 1593, {0, {0}}, 0, 0 },
1082   { "ear58", 1594, {0, {0}}, 0, 0 },
1083   { "ear59", 1595, {0, {0}}, 0, 0 },
1084   { "ear60", 1596, {0, {0}}, 0, 0 },
1085   { "ear61", 1597, {0, {0}}, 0, 0 },
1086   { "ear62", 1598, {0, {0}}, 0, 0 },
1087   { "ear63", 1599, {0, {0}}, 0, 0 },
1088   { "edr0", 1600, {0, {0}}, 0, 0 },
1089   { "edr1", 1601, {0, {0}}, 0, 0 },
1090   { "edr2", 1602, {0, {0}}, 0, 0 },
1091   { "edr3", 1603, {0, {0}}, 0, 0 },
1092   { "edr4", 1604, {0, {0}}, 0, 0 },
1093   { "edr5", 1605, {0, {0}}, 0, 0 },
1094   { "edr6", 1606, {0, {0}}, 0, 0 },
1095   { "edr7", 1607, {0, {0}}, 0, 0 },
1096   { "edr8", 1608, {0, {0}}, 0, 0 },
1097   { "edr9", 1609, {0, {0}}, 0, 0 },
1098   { "edr10", 1610, {0, {0}}, 0, 0 },
1099   { "edr11", 1611, {0, {0}}, 0, 0 },
1100   { "edr12", 1612, {0, {0}}, 0, 0 },
1101   { "edr13", 1613, {0, {0}}, 0, 0 },
1102   { "edr14", 1614, {0, {0}}, 0, 0 },
1103   { "edr15", 1615, {0, {0}}, 0, 0 },
1104   { "edr16", 1616, {0, {0}}, 0, 0 },
1105   { "edr17", 1617, {0, {0}}, 0, 0 },
1106   { "edr18", 1618, {0, {0}}, 0, 0 },
1107   { "edr19", 1619, {0, {0}}, 0, 0 },
1108   { "edr20", 1620, {0, {0}}, 0, 0 },
1109   { "edr21", 1621, {0, {0}}, 0, 0 },
1110   { "edr22", 1622, {0, {0}}, 0, 0 },
1111   { "edr23", 1623, {0, {0}}, 0, 0 },
1112   { "edr24", 1624, {0, {0}}, 0, 0 },
1113   { "edr25", 1625, {0, {0}}, 0, 0 },
1114   { "edr26", 1626, {0, {0}}, 0, 0 },
1115   { "edr27", 1627, {0, {0}}, 0, 0 },
1116   { "edr28", 1628, {0, {0}}, 0, 0 },
1117   { "edr29", 1629, {0, {0}}, 0, 0 },
1118   { "edr30", 1630, {0, {0}}, 0, 0 },
1119   { "edr31", 1631, {0, {0}}, 0, 0 },
1120   { "edr32", 1632, {0, {0}}, 0, 0 },
1121   { "edr33", 1636, {0, {0}}, 0, 0 },
1122   { "edr34", 1634, {0, {0}}, 0, 0 },
1123   { "edr35", 1635, {0, {0}}, 0, 0 },
1124   { "edr36", 1636, {0, {0}}, 0, 0 },
1125   { "edr37", 1637, {0, {0}}, 0, 0 },
1126   { "edr38", 1638, {0, {0}}, 0, 0 },
1127   { "edr39", 1639, {0, {0}}, 0, 0 },
1128   { "edr40", 1640, {0, {0}}, 0, 0 },
1129   { "edr41", 1641, {0, {0}}, 0, 0 },
1130   { "edr42", 1642, {0, {0}}, 0, 0 },
1131   { "edr43", 1643, {0, {0}}, 0, 0 },
1132   { "edr44", 1644, {0, {0}}, 0, 0 },
1133   { "edr45", 1645, {0, {0}}, 0, 0 },
1134   { "edr46", 1646, {0, {0}}, 0, 0 },
1135   { "edr47", 1647, {0, {0}}, 0, 0 },
1136   { "edr48", 1648, {0, {0}}, 0, 0 },
1137   { "edr49", 1649, {0, {0}}, 0, 0 },
1138   { "edr50", 1650, {0, {0}}, 0, 0 },
1139   { "edr51", 1651, {0, {0}}, 0, 0 },
1140   { "edr52", 1652, {0, {0}}, 0, 0 },
1141   { "edr53", 1653, {0, {0}}, 0, 0 },
1142   { "edr54", 1654, {0, {0}}, 0, 0 },
1143   { "edr55", 1655, {0, {0}}, 0, 0 },
1144   { "edr56", 1656, {0, {0}}, 0, 0 },
1145   { "edr57", 1657, {0, {0}}, 0, 0 },
1146   { "edr58", 1658, {0, {0}}, 0, 0 },
1147   { "edr59", 1659, {0, {0}}, 0, 0 },
1148   { "edr60", 1660, {0, {0}}, 0, 0 },
1149   { "edr61", 1661, {0, {0}}, 0, 0 },
1150   { "edr62", 1662, {0, {0}}, 0, 0 },
1151   { "edr63", 1663, {0, {0}}, 0, 0 },
1152   { "iamlr0", 1664, {0, {0}}, 0, 0 },
1153   { "iamlr1", 1665, {0, {0}}, 0, 0 },
1154   { "iamlr2", 1666, {0, {0}}, 0, 0 },
1155   { "iamlr3", 1667, {0, {0}}, 0, 0 },
1156   { "iamlr4", 1668, {0, {0}}, 0, 0 },
1157   { "iamlr5", 1669, {0, {0}}, 0, 0 },
1158   { "iamlr6", 1670, {0, {0}}, 0, 0 },
1159   { "iamlr7", 1671, {0, {0}}, 0, 0 },
1160   { "iamlr8", 1672, {0, {0}}, 0, 0 },
1161   { "iamlr9", 1673, {0, {0}}, 0, 0 },
1162   { "iamlr10", 1674, {0, {0}}, 0, 0 },
1163   { "iamlr11", 1675, {0, {0}}, 0, 0 },
1164   { "iamlr12", 1676, {0, {0}}, 0, 0 },
1165   { "iamlr13", 1677, {0, {0}}, 0, 0 },
1166   { "iamlr14", 1678, {0, {0}}, 0, 0 },
1167   { "iamlr15", 1679, {0, {0}}, 0, 0 },
1168   { "iamlr16", 1680, {0, {0}}, 0, 0 },
1169   { "iamlr17", 1681, {0, {0}}, 0, 0 },
1170   { "iamlr18", 1682, {0, {0}}, 0, 0 },
1171   { "iamlr19", 1683, {0, {0}}, 0, 0 },
1172   { "iamlr20", 1684, {0, {0}}, 0, 0 },
1173   { "iamlr21", 1685, {0, {0}}, 0, 0 },
1174   { "iamlr22", 1686, {0, {0}}, 0, 0 },
1175   { "iamlr23", 1687, {0, {0}}, 0, 0 },
1176   { "iamlr24", 1688, {0, {0}}, 0, 0 },
1177   { "iamlr25", 1689, {0, {0}}, 0, 0 },
1178   { "iamlr26", 1690, {0, {0}}, 0, 0 },
1179   { "iamlr27", 1691, {0, {0}}, 0, 0 },
1180   { "iamlr28", 1692, {0, {0}}, 0, 0 },
1181   { "iamlr29", 1693, {0, {0}}, 0, 0 },
1182   { "iamlr30", 1694, {0, {0}}, 0, 0 },
1183   { "iamlr31", 1695, {0, {0}}, 0, 0 },
1184   { "iamlr32", 1696, {0, {0}}, 0, 0 },
1185   { "iamlr33", 1697, {0, {0}}, 0, 0 },
1186   { "iamlr34", 1698, {0, {0}}, 0, 0 },
1187   { "iamlr35", 1699, {0, {0}}, 0, 0 },
1188   { "iamlr36", 1700, {0, {0}}, 0, 0 },
1189   { "iamlr37", 1701, {0, {0}}, 0, 0 },
1190   { "iamlr38", 1702, {0, {0}}, 0, 0 },
1191   { "iamlr39", 1703, {0, {0}}, 0, 0 },
1192   { "iamlr40", 1704, {0, {0}}, 0, 0 },
1193   { "iamlr41", 1705, {0, {0}}, 0, 0 },
1194   { "iamlr42", 1706, {0, {0}}, 0, 0 },
1195   { "iamlr43", 1707, {0, {0}}, 0, 0 },
1196   { "iamlr44", 1708, {0, {0}}, 0, 0 },
1197   { "iamlr45", 1709, {0, {0}}, 0, 0 },
1198   { "iamlr46", 1710, {0, {0}}, 0, 0 },
1199   { "iamlr47", 1711, {0, {0}}, 0, 0 },
1200   { "iamlr48", 1712, {0, {0}}, 0, 0 },
1201   { "iamlr49", 1713, {0, {0}}, 0, 0 },
1202   { "iamlr50", 1714, {0, {0}}, 0, 0 },
1203   { "iamlr51", 1715, {0, {0}}, 0, 0 },
1204   { "iamlr52", 1716, {0, {0}}, 0, 0 },
1205   { "iamlr53", 1717, {0, {0}}, 0, 0 },
1206   { "iamlr54", 1718, {0, {0}}, 0, 0 },
1207   { "iamlr55", 1719, {0, {0}}, 0, 0 },
1208   { "iamlr56", 1720, {0, {0}}, 0, 0 },
1209   { "iamlr57", 1721, {0, {0}}, 0, 0 },
1210   { "iamlr58", 1722, {0, {0}}, 0, 0 },
1211   { "iamlr59", 1723, {0, {0}}, 0, 0 },
1212   { "iamlr60", 1724, {0, {0}}, 0, 0 },
1213   { "iamlr61", 1725, {0, {0}}, 0, 0 },
1214   { "iamlr62", 1726, {0, {0}}, 0, 0 },
1215   { "iamlr63", 1727, {0, {0}}, 0, 0 },
1216   { "iampr0", 1728, {0, {0}}, 0, 0 },
1217   { "iampr1", 1729, {0, {0}}, 0, 0 },
1218   { "iampr2", 1730, {0, {0}}, 0, 0 },
1219   { "iampr3", 1731, {0, {0}}, 0, 0 },
1220   { "iampr4", 1732, {0, {0}}, 0, 0 },
1221   { "iampr5", 1733, {0, {0}}, 0, 0 },
1222   { "iampr6", 1734, {0, {0}}, 0, 0 },
1223   { "iampr7", 1735, {0, {0}}, 0, 0 },
1224   { "iampr8", 1736, {0, {0}}, 0, 0 },
1225   { "iampr9", 1737, {0, {0}}, 0, 0 },
1226   { "iampr10", 1738, {0, {0}}, 0, 0 },
1227   { "iampr11", 1739, {0, {0}}, 0, 0 },
1228   { "iampr12", 1740, {0, {0}}, 0, 0 },
1229   { "iampr13", 1741, {0, {0}}, 0, 0 },
1230   { "iampr14", 1742, {0, {0}}, 0, 0 },
1231   { "iampr15", 1743, {0, {0}}, 0, 0 },
1232   { "iampr16", 1744, {0, {0}}, 0, 0 },
1233   { "iampr17", 1745, {0, {0}}, 0, 0 },
1234   { "iampr18", 1746, {0, {0}}, 0, 0 },
1235   { "iampr19", 1747, {0, {0}}, 0, 0 },
1236   { "iampr20", 1748, {0, {0}}, 0, 0 },
1237   { "iampr21", 1749, {0, {0}}, 0, 0 },
1238   { "iampr22", 1750, {0, {0}}, 0, 0 },
1239   { "iampr23", 1751, {0, {0}}, 0, 0 },
1240   { "iampr24", 1752, {0, {0}}, 0, 0 },
1241   { "iampr25", 1753, {0, {0}}, 0, 0 },
1242   { "iampr26", 1754, {0, {0}}, 0, 0 },
1243   { "iampr27", 1755, {0, {0}}, 0, 0 },
1244   { "iampr28", 1756, {0, {0}}, 0, 0 },
1245   { "iampr29", 1757, {0, {0}}, 0, 0 },
1246   { "iampr30", 1758, {0, {0}}, 0, 0 },
1247   { "iampr31", 1759, {0, {0}}, 0, 0 },
1248   { "iampr32", 1760, {0, {0}}, 0, 0 },
1249   { "iampr33", 1761, {0, {0}}, 0, 0 },
1250   { "iampr34", 1762, {0, {0}}, 0, 0 },
1251   { "iampr35", 1763, {0, {0}}, 0, 0 },
1252   { "iampr36", 1764, {0, {0}}, 0, 0 },
1253   { "iampr37", 1765, {0, {0}}, 0, 0 },
1254   { "iampr38", 1766, {0, {0}}, 0, 0 },
1255   { "iampr39", 1767, {0, {0}}, 0, 0 },
1256   { "iampr40", 1768, {0, {0}}, 0, 0 },
1257   { "iampr41", 1769, {0, {0}}, 0, 0 },
1258   { "iampr42", 1770, {0, {0}}, 0, 0 },
1259   { "iampr43", 1771, {0, {0}}, 0, 0 },
1260   { "iampr44", 1772, {0, {0}}, 0, 0 },
1261   { "iampr45", 1773, {0, {0}}, 0, 0 },
1262   { "iampr46", 1774, {0, {0}}, 0, 0 },
1263   { "iampr47", 1775, {0, {0}}, 0, 0 },
1264   { "iampr48", 1776, {0, {0}}, 0, 0 },
1265   { "iampr49", 1777, {0, {0}}, 0, 0 },
1266   { "iampr50", 1778, {0, {0}}, 0, 0 },
1267   { "iampr51", 1779, {0, {0}}, 0, 0 },
1268   { "iampr52", 1780, {0, {0}}, 0, 0 },
1269   { "iampr53", 1781, {0, {0}}, 0, 0 },
1270   { "iampr54", 1782, {0, {0}}, 0, 0 },
1271   { "iampr55", 1783, {0, {0}}, 0, 0 },
1272   { "iampr56", 1784, {0, {0}}, 0, 0 },
1273   { "iampr57", 1785, {0, {0}}, 0, 0 },
1274   { "iampr58", 1786, {0, {0}}, 0, 0 },
1275   { "iampr59", 1787, {0, {0}}, 0, 0 },
1276   { "iampr60", 1788, {0, {0}}, 0, 0 },
1277   { "iampr61", 1789, {0, {0}}, 0, 0 },
1278   { "iampr62", 1790, {0, {0}}, 0, 0 },
1279   { "iampr63", 1791, {0, {0}}, 0, 0 },
1280   { "damlr0", 1792, {0, {0}}, 0, 0 },
1281   { "damlr1", 1793, {0, {0}}, 0, 0 },
1282   { "damlr2", 1794, {0, {0}}, 0, 0 },
1283   { "damlr3", 1795, {0, {0}}, 0, 0 },
1284   { "damlr4", 1796, {0, {0}}, 0, 0 },
1285   { "damlr5", 1797, {0, {0}}, 0, 0 },
1286   { "damlr6", 1798, {0, {0}}, 0, 0 },
1287   { "damlr7", 1799, {0, {0}}, 0, 0 },
1288   { "damlr8", 1800, {0, {0}}, 0, 0 },
1289   { "damlr9", 1801, {0, {0}}, 0, 0 },
1290   { "damlr10", 1802, {0, {0}}, 0, 0 },
1291   { "damlr11", 1803, {0, {0}}, 0, 0 },
1292   { "damlr12", 1804, {0, {0}}, 0, 0 },
1293   { "damlr13", 1805, {0, {0}}, 0, 0 },
1294   { "damlr14", 1806, {0, {0}}, 0, 0 },
1295   { "damlr15", 1807, {0, {0}}, 0, 0 },
1296   { "damlr16", 1808, {0, {0}}, 0, 0 },
1297   { "damlr17", 1809, {0, {0}}, 0, 0 },
1298   { "damlr18", 1810, {0, {0}}, 0, 0 },
1299   { "damlr19", 1811, {0, {0}}, 0, 0 },
1300   { "damlr20", 1812, {0, {0}}, 0, 0 },
1301   { "damlr21", 1813, {0, {0}}, 0, 0 },
1302   { "damlr22", 1814, {0, {0}}, 0, 0 },
1303   { "damlr23", 1815, {0, {0}}, 0, 0 },
1304   { "damlr24", 1816, {0, {0}}, 0, 0 },
1305   { "damlr25", 1817, {0, {0}}, 0, 0 },
1306   { "damlr26", 1818, {0, {0}}, 0, 0 },
1307   { "damlr27", 1819, {0, {0}}, 0, 0 },
1308   { "damlr28", 1820, {0, {0}}, 0, 0 },
1309   { "damlr29", 1821, {0, {0}}, 0, 0 },
1310   { "damlr30", 1822, {0, {0}}, 0, 0 },
1311   { "damlr31", 1823, {0, {0}}, 0, 0 },
1312   { "damlr32", 1824, {0, {0}}, 0, 0 },
1313   { "damlr33", 1825, {0, {0}}, 0, 0 },
1314   { "damlr34", 1826, {0, {0}}, 0, 0 },
1315   { "damlr35", 1827, {0, {0}}, 0, 0 },
1316   { "damlr36", 1828, {0, {0}}, 0, 0 },
1317   { "damlr37", 1829, {0, {0}}, 0, 0 },
1318   { "damlr38", 1830, {0, {0}}, 0, 0 },
1319   { "damlr39", 1831, {0, {0}}, 0, 0 },
1320   { "damlr40", 1832, {0, {0}}, 0, 0 },
1321   { "damlr41", 1833, {0, {0}}, 0, 0 },
1322   { "damlr42", 1834, {0, {0}}, 0, 0 },
1323   { "damlr43", 1835, {0, {0}}, 0, 0 },
1324   { "damlr44", 1836, {0, {0}}, 0, 0 },
1325   { "damlr45", 1837, {0, {0}}, 0, 0 },
1326   { "damlr46", 1838, {0, {0}}, 0, 0 },
1327   { "damlr47", 1839, {0, {0}}, 0, 0 },
1328   { "damlr48", 1840, {0, {0}}, 0, 0 },
1329   { "damlr49", 1841, {0, {0}}, 0, 0 },
1330   { "damlr50", 1842, {0, {0}}, 0, 0 },
1331   { "damlr51", 1843, {0, {0}}, 0, 0 },
1332   { "damlr52", 1844, {0, {0}}, 0, 0 },
1333   { "damlr53", 1845, {0, {0}}, 0, 0 },
1334   { "damlr54", 1846, {0, {0}}, 0, 0 },
1335   { "damlr55", 1847, {0, {0}}, 0, 0 },
1336   { "damlr56", 1848, {0, {0}}, 0, 0 },
1337   { "damlr57", 1849, {0, {0}}, 0, 0 },
1338   { "damlr58", 1850, {0, {0}}, 0, 0 },
1339   { "damlr59", 1851, {0, {0}}, 0, 0 },
1340   { "damlr60", 1852, {0, {0}}, 0, 0 },
1341   { "damlr61", 1853, {0, {0}}, 0, 0 },
1342   { "damlr62", 1854, {0, {0}}, 0, 0 },
1343   { "damlr63", 1855, {0, {0}}, 0, 0 },
1344   { "dampr0", 1856, {0, {0}}, 0, 0 },
1345   { "dampr1", 1857, {0, {0}}, 0, 0 },
1346   { "dampr2", 1858, {0, {0}}, 0, 0 },
1347   { "dampr3", 1859, {0, {0}}, 0, 0 },
1348   { "dampr4", 1860, {0, {0}}, 0, 0 },
1349   { "dampr5", 1861, {0, {0}}, 0, 0 },
1350   { "dampr6", 1862, {0, {0}}, 0, 0 },
1351   { "dampr7", 1863, {0, {0}}, 0, 0 },
1352   { "dampr8", 1864, {0, {0}}, 0, 0 },
1353   { "dampr9", 1865, {0, {0}}, 0, 0 },
1354   { "dampr10", 1866, {0, {0}}, 0, 0 },
1355   { "dampr11", 1867, {0, {0}}, 0, 0 },
1356   { "dampr12", 1868, {0, {0}}, 0, 0 },
1357   { "dampr13", 1869, {0, {0}}, 0, 0 },
1358   { "dampr14", 1870, {0, {0}}, 0, 0 },
1359   { "dampr15", 1871, {0, {0}}, 0, 0 },
1360   { "dampr16", 1872, {0, {0}}, 0, 0 },
1361   { "dampr17", 1873, {0, {0}}, 0, 0 },
1362   { "dampr18", 1874, {0, {0}}, 0, 0 },
1363   { "dampr19", 1875, {0, {0}}, 0, 0 },
1364   { "dampr20", 1876, {0, {0}}, 0, 0 },
1365   { "dampr21", 1877, {0, {0}}, 0, 0 },
1366   { "dampr22", 1878, {0, {0}}, 0, 0 },
1367   { "dampr23", 1879, {0, {0}}, 0, 0 },
1368   { "dampr24", 1880, {0, {0}}, 0, 0 },
1369   { "dampr25", 1881, {0, {0}}, 0, 0 },
1370   { "dampr26", 1882, {0, {0}}, 0, 0 },
1371   { "dampr27", 1883, {0, {0}}, 0, 0 },
1372   { "dampr28", 1884, {0, {0}}, 0, 0 },
1373   { "dampr29", 1885, {0, {0}}, 0, 0 },
1374   { "dampr30", 1886, {0, {0}}, 0, 0 },
1375   { "dampr31", 1887, {0, {0}}, 0, 0 },
1376   { "dampr32", 1888, {0, {0}}, 0, 0 },
1377   { "dampr33", 1889, {0, {0}}, 0, 0 },
1378   { "dampr34", 1890, {0, {0}}, 0, 0 },
1379   { "dampr35", 1891, {0, {0}}, 0, 0 },
1380   { "dampr36", 1892, {0, {0}}, 0, 0 },
1381   { "dampr37", 1893, {0, {0}}, 0, 0 },
1382   { "dampr38", 1894, {0, {0}}, 0, 0 },
1383   { "dampr39", 1895, {0, {0}}, 0, 0 },
1384   { "dampr40", 1896, {0, {0}}, 0, 0 },
1385   { "dampr41", 1897, {0, {0}}, 0, 0 },
1386   { "dampr42", 1898, {0, {0}}, 0, 0 },
1387   { "dampr43", 1899, {0, {0}}, 0, 0 },
1388   { "dampr44", 1900, {0, {0}}, 0, 0 },
1389   { "dampr45", 1901, {0, {0}}, 0, 0 },
1390   { "dampr46", 1902, {0, {0}}, 0, 0 },
1391   { "dampr47", 1903, {0, {0}}, 0, 0 },
1392   { "dampr48", 1904, {0, {0}}, 0, 0 },
1393   { "dampr49", 1905, {0, {0}}, 0, 0 },
1394   { "dampr50", 1906, {0, {0}}, 0, 0 },
1395   { "dampr51", 1907, {0, {0}}, 0, 0 },
1396   { "dampr52", 1908, {0, {0}}, 0, 0 },
1397   { "dampr53", 1909, {0, {0}}, 0, 0 },
1398   { "dampr54", 1910, {0, {0}}, 0, 0 },
1399   { "dampr55", 1911, {0, {0}}, 0, 0 },
1400   { "dampr56", 1912, {0, {0}}, 0, 0 },
1401   { "dampr57", 1913, {0, {0}}, 0, 0 },
1402   { "dampr58", 1914, {0, {0}}, 0, 0 },
1403   { "dampr59", 1915, {0, {0}}, 0, 0 },
1404   { "dampr60", 1916, {0, {0}}, 0, 0 },
1405   { "dampr61", 1917, {0, {0}}, 0, 0 },
1406   { "dampr62", 1918, {0, {0}}, 0, 0 },
1407   { "dampr63", 1919, {0, {0}}, 0, 0 },
1408   { "amcr", 1920, {0, {0}}, 0, 0 },
1409   { "stbar", 1921, {0, {0}}, 0, 0 },
1410   { "mmcr", 1922, {0, {0}}, 0, 0 },
1411   { "dcr", 2048, {0, {0}}, 0, 0 },
1412   { "brr", 2049, {0, {0}}, 0, 0 },
1413   { "nmar", 2050, {0, {0}}, 0, 0 },
1414   { "ibar0", 2052, {0, {0}}, 0, 0 },
1415   { "ibar1", 2053, {0, {0}}, 0, 0 },
1416   { "ibar2", 2054, {0, {0}}, 0, 0 },
1417   { "ibar3", 2055, {0, {0}}, 0, 0 },
1418   { "dbar0", 2056, {0, {0}}, 0, 0 },
1419   { "dbar1", 2057, {0, {0}}, 0, 0 },
1420   { "dbar2", 2058, {0, {0}}, 0, 0 },
1421   { "dbar3", 2059, {0, {0}}, 0, 0 },
1422   { "dbdr00", 2060, {0, {0}}, 0, 0 },
1423   { "dbdr01", 2061, {0, {0}}, 0, 0 },
1424   { "dbdr02", 2062, {0, {0}}, 0, 0 },
1425   { "dbdr03", 2063, {0, {0}}, 0, 0 },
1426   { "dbdr10", 2064, {0, {0}}, 0, 0 },
1427   { "dbdr11", 2065, {0, {0}}, 0, 0 },
1428   { "dbdr12", 2066, {0, {0}}, 0, 0 },
1429   { "dbdr13", 2067, {0, {0}}, 0, 0 },
1430   { "dbdr20", 2068, {0, {0}}, 0, 0 },
1431   { "dbdr21", 2069, {0, {0}}, 0, 0 },
1432   { "dbdr22", 2070, {0, {0}}, 0, 0 },
1433   { "dbdr23", 2071, {0, {0}}, 0, 0 },
1434   { "dbdr30", 2072, {0, {0}}, 0, 0 },
1435   { "dbdr31", 2073, {0, {0}}, 0, 0 },
1436   { "dbdr32", 2074, {0, {0}}, 0, 0 },
1437   { "dbdr33", 2075, {0, {0}}, 0, 0 },
1438   { "dbmr00", 2076, {0, {0}}, 0, 0 },
1439   { "dbmr01", 2077, {0, {0}}, 0, 0 },
1440   { "dbmr02", 2078, {0, {0}}, 0, 0 },
1441   { "dbmr03", 2079, {0, {0}}, 0, 0 },
1442   { "dbmr10", 2080, {0, {0}}, 0, 0 },
1443   { "dbmr11", 2081, {0, {0}}, 0, 0 },
1444   { "dbmr12", 2082, {0, {0}}, 0, 0 },
1445   { "dbmr13", 2083, {0, {0}}, 0, 0 },
1446   { "dbmr20", 2084, {0, {0}}, 0, 0 },
1447   { "dbmr21", 2085, {0, {0}}, 0, 0 },
1448   { "dbmr22", 2086, {0, {0}}, 0, 0 },
1449   { "dbmr23", 2087, {0, {0}}, 0, 0 },
1450   { "dbmr30", 2088, {0, {0}}, 0, 0 },
1451   { "dbmr31", 2089, {0, {0}}, 0, 0 },
1452   { "dbmr32", 2090, {0, {0}}, 0, 0 },
1453   { "dbmr33", 2091, {0, {0}}, 0, 0 },
1454   { "cpcfr", 2092, {0, {0}}, 0, 0 },
1455   { "cpcr", 2093, {0, {0}}, 0, 0 },
1456   { "cpsr", 2094, {0, {0}}, 0, 0 },
1457   { "cpesr0", 2096, {0, {0}}, 0, 0 },
1458   { "cpesr1", 2097, {0, {0}}, 0, 0 },
1459   { "cpemr0", 2098, {0, {0}}, 0, 0 },
1460   { "cpemr1", 2099, {0, {0}}, 0, 0 },
1461   { "ihsr8", 3848, {0, {0}}, 0, 0 }
1462 };
1463
1464 CGEN_KEYWORD frv_cgen_opval_spr_names =
1465 {
1466   & frv_cgen_opval_spr_names_entries[0],
1467   1005,
1468   0, 0, 0, 0, ""
1469 };
1470
1471 static CGEN_KEYWORD_ENTRY frv_cgen_opval_accg_names_entries[] =
1472 {
1473   { "accg0", 0, {0, {0}}, 0, 0 },
1474   { "accg1", 1, {0, {0}}, 0, 0 },
1475   { "accg2", 2, {0, {0}}, 0, 0 },
1476   { "accg3", 3, {0, {0}}, 0, 0 },
1477   { "accg4", 4, {0, {0}}, 0, 0 },
1478   { "accg5", 5, {0, {0}}, 0, 0 },
1479   { "accg6", 6, {0, {0}}, 0, 0 },
1480   { "accg7", 7, {0, {0}}, 0, 0 },
1481   { "accg8", 8, {0, {0}}, 0, 0 },
1482   { "accg9", 9, {0, {0}}, 0, 0 },
1483   { "accg10", 10, {0, {0}}, 0, 0 },
1484   { "accg11", 11, {0, {0}}, 0, 0 },
1485   { "accg12", 12, {0, {0}}, 0, 0 },
1486   { "accg13", 13, {0, {0}}, 0, 0 },
1487   { "accg14", 14, {0, {0}}, 0, 0 },
1488   { "accg15", 15, {0, {0}}, 0, 0 },
1489   { "accg16", 16, {0, {0}}, 0, 0 },
1490   { "accg17", 17, {0, {0}}, 0, 0 },
1491   { "accg18", 18, {0, {0}}, 0, 0 },
1492   { "accg19", 19, {0, {0}}, 0, 0 },
1493   { "accg20", 20, {0, {0}}, 0, 0 },
1494   { "accg21", 21, {0, {0}}, 0, 0 },
1495   { "accg22", 22, {0, {0}}, 0, 0 },
1496   { "accg23", 23, {0, {0}}, 0, 0 },
1497   { "accg24", 24, {0, {0}}, 0, 0 },
1498   { "accg25", 25, {0, {0}}, 0, 0 },
1499   { "accg26", 26, {0, {0}}, 0, 0 },
1500   { "accg27", 27, {0, {0}}, 0, 0 },
1501   { "accg28", 28, {0, {0}}, 0, 0 },
1502   { "accg29", 29, {0, {0}}, 0, 0 },
1503   { "accg30", 30, {0, {0}}, 0, 0 },
1504   { "accg31", 31, {0, {0}}, 0, 0 },
1505   { "accg32", 32, {0, {0}}, 0, 0 },
1506   { "accg33", 33, {0, {0}}, 0, 0 },
1507   { "accg34", 34, {0, {0}}, 0, 0 },
1508   { "accg35", 35, {0, {0}}, 0, 0 },
1509   { "accg36", 36, {0, {0}}, 0, 0 },
1510   { "accg37", 37, {0, {0}}, 0, 0 },
1511   { "accg38", 38, {0, {0}}, 0, 0 },
1512   { "accg39", 39, {0, {0}}, 0, 0 },
1513   { "accg40", 40, {0, {0}}, 0, 0 },
1514   { "accg41", 41, {0, {0}}, 0, 0 },
1515   { "accg42", 42, {0, {0}}, 0, 0 },
1516   { "accg43", 43, {0, {0}}, 0, 0 },
1517   { "accg44", 44, {0, {0}}, 0, 0 },
1518   { "accg45", 45, {0, {0}}, 0, 0 },
1519   { "accg46", 46, {0, {0}}, 0, 0 },
1520   { "accg47", 47, {0, {0}}, 0, 0 },
1521   { "accg48", 48, {0, {0}}, 0, 0 },
1522   { "accg49", 49, {0, {0}}, 0, 0 },
1523   { "accg50", 50, {0, {0}}, 0, 0 },
1524   { "accg51", 51, {0, {0}}, 0, 0 },
1525   { "accg52", 52, {0, {0}}, 0, 0 },
1526   { "accg53", 53, {0, {0}}, 0, 0 },
1527   { "accg54", 54, {0, {0}}, 0, 0 },
1528   { "accg55", 55, {0, {0}}, 0, 0 },
1529   { "accg56", 56, {0, {0}}, 0, 0 },
1530   { "accg57", 57, {0, {0}}, 0, 0 },
1531   { "accg58", 58, {0, {0}}, 0, 0 },
1532   { "accg59", 59, {0, {0}}, 0, 0 },
1533   { "accg60", 60, {0, {0}}, 0, 0 },
1534   { "accg61", 61, {0, {0}}, 0, 0 },
1535   { "accg62", 62, {0, {0}}, 0, 0 },
1536   { "accg63", 63, {0, {0}}, 0, 0 }
1537 };
1538
1539 CGEN_KEYWORD frv_cgen_opval_accg_names =
1540 {
1541   & frv_cgen_opval_accg_names_entries[0],
1542   64,
1543   0, 0, 0, 0, ""
1544 };
1545
1546 static CGEN_KEYWORD_ENTRY frv_cgen_opval_acc_names_entries[] =
1547 {
1548   { "acc0", 0, {0, {0}}, 0, 0 },
1549   { "acc1", 1, {0, {0}}, 0, 0 },
1550   { "acc2", 2, {0, {0}}, 0, 0 },
1551   { "acc3", 3, {0, {0}}, 0, 0 },
1552   { "acc4", 4, {0, {0}}, 0, 0 },
1553   { "acc5", 5, {0, {0}}, 0, 0 },
1554   { "acc6", 6, {0, {0}}, 0, 0 },
1555   { "acc7", 7, {0, {0}}, 0, 0 },
1556   { "acc8", 8, {0, {0}}, 0, 0 },
1557   { "acc9", 9, {0, {0}}, 0, 0 },
1558   { "acc10", 10, {0, {0}}, 0, 0 },
1559   { "acc11", 11, {0, {0}}, 0, 0 },
1560   { "acc12", 12, {0, {0}}, 0, 0 },
1561   { "acc13", 13, {0, {0}}, 0, 0 },
1562   { "acc14", 14, {0, {0}}, 0, 0 },
1563   { "acc15", 15, {0, {0}}, 0, 0 },
1564   { "acc16", 16, {0, {0}}, 0, 0 },
1565   { "acc17", 17, {0, {0}}, 0, 0 },
1566   { "acc18", 18, {0, {0}}, 0, 0 },
1567   { "acc19", 19, {0, {0}}, 0, 0 },
1568   { "acc20", 20, {0, {0}}, 0, 0 },
1569   { "acc21", 21, {0, {0}}, 0, 0 },
1570   { "acc22", 22, {0, {0}}, 0, 0 },
1571   { "acc23", 23, {0, {0}}, 0, 0 },
1572   { "acc24", 24, {0, {0}}, 0, 0 },
1573   { "acc25", 25, {0, {0}}, 0, 0 },
1574   { "acc26", 26, {0, {0}}, 0, 0 },
1575   { "acc27", 27, {0, {0}}, 0, 0 },
1576   { "acc28", 28, {0, {0}}, 0, 0 },
1577   { "acc29", 29, {0, {0}}, 0, 0 },
1578   { "acc30", 30, {0, {0}}, 0, 0 },
1579   { "acc31", 31, {0, {0}}, 0, 0 },
1580   { "acc32", 32, {0, {0}}, 0, 0 },
1581   { "acc33", 33, {0, {0}}, 0, 0 },
1582   { "acc34", 34, {0, {0}}, 0, 0 },
1583   { "acc35", 35, {0, {0}}, 0, 0 },
1584   { "acc36", 36, {0, {0}}, 0, 0 },
1585   { "acc37", 37, {0, {0}}, 0, 0 },
1586   { "acc38", 38, {0, {0}}, 0, 0 },
1587   { "acc39", 39, {0, {0}}, 0, 0 },
1588   { "acc40", 40, {0, {0}}, 0, 0 },
1589   { "acc41", 41, {0, {0}}, 0, 0 },
1590   { "acc42", 42, {0, {0}}, 0, 0 },
1591   { "acc43", 43, {0, {0}}, 0, 0 },
1592   { "acc44", 44, {0, {0}}, 0, 0 },
1593   { "acc45", 45, {0, {0}}, 0, 0 },
1594   { "acc46", 46, {0, {0}}, 0, 0 },
1595   { "acc47", 47, {0, {0}}, 0, 0 },
1596   { "acc48", 48, {0, {0}}, 0, 0 },
1597   { "acc49", 49, {0, {0}}, 0, 0 },
1598   { "acc50", 50, {0, {0}}, 0, 0 },
1599   { "acc51", 51, {0, {0}}, 0, 0 },
1600   { "acc52", 52, {0, {0}}, 0, 0 },
1601   { "acc53", 53, {0, {0}}, 0, 0 },
1602   { "acc54", 54, {0, {0}}, 0, 0 },
1603   { "acc55", 55, {0, {0}}, 0, 0 },
1604   { "acc56", 56, {0, {0}}, 0, 0 },
1605   { "acc57", 57, {0, {0}}, 0, 0 },
1606   { "acc58", 58, {0, {0}}, 0, 0 },
1607   { "acc59", 59, {0, {0}}, 0, 0 },
1608   { "acc60", 60, {0, {0}}, 0, 0 },
1609   { "acc61", 61, {0, {0}}, 0, 0 },
1610   { "acc62", 62, {0, {0}}, 0, 0 },
1611   { "acc63", 63, {0, {0}}, 0, 0 }
1612 };
1613
1614 CGEN_KEYWORD frv_cgen_opval_acc_names =
1615 {
1616   & frv_cgen_opval_acc_names_entries[0],
1617   64,
1618   0, 0, 0, 0, ""
1619 };
1620
1621 static CGEN_KEYWORD_ENTRY frv_cgen_opval_iccr_names_entries[] =
1622 {
1623   { "icc0", 0, {0, {0}}, 0, 0 },
1624   { "icc1", 1, {0, {0}}, 0, 0 },
1625   { "icc2", 2, {0, {0}}, 0, 0 },
1626   { "icc3", 3, {0, {0}}, 0, 0 }
1627 };
1628
1629 CGEN_KEYWORD frv_cgen_opval_iccr_names =
1630 {
1631   & frv_cgen_opval_iccr_names_entries[0],
1632   4,
1633   0, 0, 0, 0, ""
1634 };
1635
1636 static CGEN_KEYWORD_ENTRY frv_cgen_opval_fccr_names_entries[] =
1637 {
1638   { "fcc0", 0, {0, {0}}, 0, 0 },
1639   { "fcc1", 1, {0, {0}}, 0, 0 },
1640   { "fcc2", 2, {0, {0}}, 0, 0 },
1641   { "fcc3", 3, {0, {0}}, 0, 0 }
1642 };
1643
1644 CGEN_KEYWORD frv_cgen_opval_fccr_names =
1645 {
1646   & frv_cgen_opval_fccr_names_entries[0],
1647   4,
1648   0, 0, 0, 0, ""
1649 };
1650
1651 static CGEN_KEYWORD_ENTRY frv_cgen_opval_cccr_names_entries[] =
1652 {
1653   { "cc0", 0, {0, {0}}, 0, 0 },
1654   { "cc1", 1, {0, {0}}, 0, 0 },
1655   { "cc2", 2, {0, {0}}, 0, 0 },
1656   { "cc3", 3, {0, {0}}, 0, 0 },
1657   { "cc4", 4, {0, {0}}, 0, 0 },
1658   { "cc5", 5, {0, {0}}, 0, 0 },
1659   { "cc6", 6, {0, {0}}, 0, 0 },
1660   { "cc7", 7, {0, {0}}, 0, 0 }
1661 };
1662
1663 CGEN_KEYWORD frv_cgen_opval_cccr_names =
1664 {
1665   & frv_cgen_opval_cccr_names_entries[0],
1666   8,
1667   0, 0, 0, 0, ""
1668 };
1669
1670 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_pack_entries[] =
1671 {
1672   { "", 1, {0, {0}}, 0, 0 },
1673   { ".p", 0, {0, {0}}, 0, 0 },
1674   { ".P", 0, {0, {0}}, 0, 0 }
1675 };
1676
1677 CGEN_KEYWORD frv_cgen_opval_h_pack =
1678 {
1679   & frv_cgen_opval_h_pack_entries[0],
1680   3,
1681   0, 0, 0, 0, ""
1682 };
1683
1684 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_taken_entries[] =
1685 {
1686   { "", 2, {0, {0}}, 0, 0 },
1687   { "", 0, {0, {0}}, 0, 0 },
1688   { "", 1, {0, {0}}, 0, 0 },
1689   { "", 3, {0, {0}}, 0, 0 }
1690 };
1691
1692 CGEN_KEYWORD frv_cgen_opval_h_hint_taken =
1693 {
1694   & frv_cgen_opval_h_hint_taken_entries[0],
1695   4,
1696   0, 0, 0, 0, ""
1697 };
1698
1699 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_not_taken_entries[] =
1700 {
1701   { "", 0, {0, {0}}, 0, 0 },
1702   { "", 1, {0, {0}}, 0, 0 },
1703   { "", 2, {0, {0}}, 0, 0 },
1704   { "", 3, {0, {0}}, 0, 0 }
1705 };
1706
1707 CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken =
1708 {
1709   & frv_cgen_opval_h_hint_not_taken_entries[0],
1710   4,
1711   0, 0, 0, 0, ""
1712 };
1713
1714
1715 /* The hardware table.  */
1716
1717 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1718 #define A(a) (1 << CGEN_HW_##a)
1719 #else
1720 #define A(a) (1 << CGEN_HW_/**/a)
1721 #endif
1722
1723 const CGEN_HW_ENTRY frv_cgen_hw_table[] =
1724 {
1725   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1726   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1727   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1728   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1729   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1730   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
1731   { "h-psr_imple", HW_H_PSR_IMPLE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1732   { "h-psr_ver", HW_H_PSR_VER, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1733   { "h-psr_ice", HW_H_PSR_ICE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1734   { "h-psr_nem", HW_H_PSR_NEM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1735   { "h-psr_cm", HW_H_PSR_CM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1736   { "h-psr_be", HW_H_PSR_BE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1737   { "h-psr_esr", HW_H_PSR_ESR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1738   { "h-psr_ef", HW_H_PSR_EF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1739   { "h-psr_em", HW_H_PSR_EM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1740   { "h-psr_pil", HW_H_PSR_PIL, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1741   { "h-psr_ps", HW_H_PSR_PS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1742   { "h-psr_et", HW_H_PSR_ET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1743   { "h-psr_s", HW_H_PSR_S, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1744   { "h-tbr_tba", HW_H_TBR_TBA, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1745   { "h-tbr_tt", HW_H_TBR_TT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1746   { "h-bpsr_bs", HW_H_BPSR_BS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1747   { "h-bpsr_bet", HW_H_BPSR_BET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1748   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1749   { "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1750   { "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1751   { "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1752   { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1753   { "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1754   { "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1755   { "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1756   { "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1757   { "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1758   { "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1759   { "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1760   { "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1761   { "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { (1<<MACH_FRV) } } },
1762   { "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FRV) } } },
1763   { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_spr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1764   { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1765   { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1766   { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1767   { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1768   { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1769   { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1770   { "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_pack, { 0, { (1<<MACH_BASE) } } },
1771   { "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_taken, { 0, { (1<<MACH_BASE) } } },
1772   { "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_not_taken, { 0, { (1<<MACH_BASE) } } },
1773   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
1774 };
1775
1776 #undef A
1777
1778
1779 /* The instruction field table.  */
1780
1781 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1782 #define A(a) (1 << CGEN_IFLD_##a)
1783 #else
1784 #define A(a) (1 << CGEN_IFLD_/**/a)
1785 #endif
1786
1787 const CGEN_IFLD frv_cgen_ifld_table[] =
1788 {
1789   { FRV_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
1790   { FRV_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
1791   { FRV_F_PACK, "f-pack", 0, 32, 31, 1, { 0, { (1<<MACH_BASE) } }  },
1792   { FRV_F_OP, "f-op", 0, 32, 24, 7, { 0, { (1<<MACH_BASE) } }  },
1793   { FRV_F_OPE1, "f-ope1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } }  },
1794   { FRV_F_OPE2, "f-ope2", 0, 32, 9, 4, { 0, { (1<<MACH_BASE) } }  },
1795   { FRV_F_OPE3, "f-ope3", 0, 32, 15, 3, { 0, { (1<<MACH_BASE) } }  },
1796   { FRV_F_OPE4, "f-ope4", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } }  },
1797   { FRV_F_GRI, "f-GRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1798   { FRV_F_GRJ, "f-GRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1799   { FRV_F_GRK, "f-GRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1800   { FRV_F_FRI, "f-FRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1801   { FRV_F_FRJ, "f-FRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1802   { FRV_F_FRK, "f-FRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1803   { FRV_F_CPRI, "f-CPRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1804   { FRV_F_CPRJ, "f-CPRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1805   { FRV_F_CPRK, "f-CPRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1806   { FRV_F_ACCGI, "f-ACCGi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1807   { FRV_F_ACCGK, "f-ACCGk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1808   { FRV_F_ACC40SI, "f-ACC40Si", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1809   { FRV_F_ACC40UI, "f-ACC40Ui", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1810   { FRV_F_ACC40SK, "f-ACC40Sk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1811   { FRV_F_ACC40UK, "f-ACC40Uk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1812   { FRV_F_CRI, "f-CRi", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } }  },
1813   { FRV_F_CRJ, "f-CRj", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } }  },
1814   { FRV_F_CRK, "f-CRk", 0, 32, 27, 3, { 0, { (1<<MACH_BASE) } }  },
1815   { FRV_F_CCI, "f-CCi", 0, 32, 11, 3, { 0, { (1<<MACH_BASE) } }  },
1816   { FRV_F_CRJ_INT, "f-CRj_int", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1817   { FRV_F_CRJ_FLOAT, "f-CRj_float", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1818   { FRV_F_ICCI_1, "f-ICCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } }  },
1819   { FRV_F_ICCI_2, "f-ICCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1820   { FRV_F_ICCI_3, "f-ICCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } }  },
1821   { FRV_F_FCCI_1, "f-FCCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } }  },
1822   { FRV_F_FCCI_2, "f-FCCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1823   { FRV_F_FCCI_3, "f-FCCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } }  },
1824   { FRV_F_FCCK, "f-FCCk", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1825   { FRV_F_EIR, "f-eir", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1826   { FRV_F_S10, "f-s10", 0, 32, 9, 10, { 0, { (1<<MACH_BASE) } }  },
1827   { FRV_F_S12, "f-s12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
1828   { FRV_F_D12, "f-d12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
1829   { FRV_F_U16, "f-u16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
1830   { FRV_F_S16, "f-s16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
1831   { FRV_F_S6, "f-s6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1832   { FRV_F_S6_1, "f-s6_1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } }  },
1833   { FRV_F_U6, "f-u6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1834   { FRV_F_S5, "f-s5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } }  },
1835   { FRV_F_U12_H, "f-u12-h", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1836   { FRV_F_U12_L, "f-u12-l", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1837   { FRV_F_U12, "f-u12", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
1838   { FRV_F_INT_CC, "f-int-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } }  },
1839   { FRV_F_FLT_CC, "f-flt-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } }  },
1840   { FRV_F_COND, "f-cond", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
1841   { FRV_F_CCOND, "f-ccond", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } }  },
1842   { FRV_F_HINT, "f-hint", 0, 32, 17, 2, { 0, { (1<<MACH_BASE) } }  },
1843   { FRV_F_LI, "f-LI", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1844   { FRV_F_LOCK, "f-lock", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1845   { FRV_F_DEBUG, "f-debug", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1846   { FRV_F_A, "f-A", 0, 32, 17, 1, { 0, { (1<<MACH_BASE) } }  },
1847   { FRV_F_AE, "f-ae", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1848   { FRV_F_SPR_H, "f-spr-h", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1849   { FRV_F_SPR_L, "f-spr-l", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1850   { FRV_F_SPR, "f-spr", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
1851   { FRV_F_LABEL16, "f-label16", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
1852   { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1853   { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { (1<<MACH_BASE) } }  },
1854   { FRV_F_LABEL24, "f-label24", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
1855   { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1856   { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1857   { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1858   { FRV_F_FCCI_1_NULL, "f-FCCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1859   { FRV_F_FCCI_2_NULL, "f-FCCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1860   { FRV_F_FCCI_3_NULL, "f-FCCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1861   { FRV_F_RS_NULL, "f-rs-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1862   { FRV_F_GRI_NULL, "f-GRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1863   { FRV_F_GRJ_NULL, "f-GRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1864   { FRV_F_GRK_NULL, "f-GRk-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1865   { FRV_F_FRI_NULL, "f-FRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1866   { FRV_F_FRJ_NULL, "f-FRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1867   { FRV_F_ACCJ_NULL, "f-ACCj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1868   { FRV_F_RD_NULL, "f-rd-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1869   { FRV_F_COND_NULL, "f-cond-null", 0, 32, 30, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1870   { FRV_F_CCOND_NULL, "f-ccond-null", 0, 32, 12, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1871   { FRV_F_S12_NULL, "f-s12-null", 0, 32, 11, 12, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1872   { FRV_F_LABEL16_NULL, "f-label16-null", 0, 32, 15, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1873   { FRV_F_MISC_NULL_1, "f-misc-null-1", 0, 32, 30, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1874   { FRV_F_MISC_NULL_2, "f-misc-null-2", 0, 32, 11, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1875   { FRV_F_MISC_NULL_3, "f-misc-null-3", 0, 32, 11, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1876   { FRV_F_MISC_NULL_4, "f-misc-null-4", 0, 32, 17, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1877   { FRV_F_MISC_NULL_5, "f-misc-null-5", 0, 32, 17, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1878   { FRV_F_MISC_NULL_6, "f-misc-null-6", 0, 32, 30, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1879   { FRV_F_MISC_NULL_7, "f-misc-null-7", 0, 32, 17, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1880   { FRV_F_MISC_NULL_8, "f-misc-null-8", 0, 32, 5, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1881   { FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1882   { FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1883   { FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1884   { FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1885   { FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1886   { 0, 0, 0, 0, 0, 0, {0, {0}} }
1887 };
1888
1889 #undef A
1890
1891
1892
1893 /* multi ifield declarations */
1894
1895 const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [];
1896 const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [];
1897 const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [];
1898
1899
1900 /* multi ifield definitions */
1901
1902 const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [] =
1903 {
1904     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U12_H] } },
1905     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U12_L] } },
1906     { 0, { (const PTR) 0 } }
1907 };
1908 const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [] =
1909 {
1910     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_SPR_H] } },
1911     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_SPR_L] } },
1912     { 0, { (const PTR) 0 } }
1913 };
1914 const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [] =
1915 {
1916     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABELH6] } },
1917     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABELL18] } },
1918     { 0, { (const PTR) 0 } }
1919 };
1920
1921 /* The operand table.  */
1922
1923 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1924 #define A(a) (1 << CGEN_OPERAND_##a)
1925 #else
1926 #define A(a) (1 << CGEN_OPERAND_/**/a)
1927 #endif
1928 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1929 #define OPERAND(op) FRV_OPERAND_##op
1930 #else
1931 #define OPERAND(op) FRV_OPERAND_/**/op
1932 #endif
1933
1934 const CGEN_OPERAND frv_cgen_operand_table[] =
1935 {
1936 /* pc: program counter */
1937   { "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0,
1938     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_NIL] } },
1939     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
1940 /* pack: packing bit */
1941   { "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1,
1942     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_PACK] } },
1943     { 0, { (1<<MACH_BASE) } }  },
1944 /* GRi: source register 1 */
1945   { "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6,
1946     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRI] } },
1947     { 0, { (1<<MACH_BASE) } }  },
1948 /* GRj: source register 2 */
1949   { "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6,
1950     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRJ] } },
1951     { 0, { (1<<MACH_BASE) } }  },
1952 /* GRk: destination register */
1953   { "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6,
1954     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
1955     { 0, { (1<<MACH_BASE) } }  },
1956 /* GRkhi: destination register */
1957   { "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6,
1958     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
1959     { 0, { (1<<MACH_BASE) } }  },
1960 /* GRklo: destination register */
1961   { "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6,
1962     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
1963     { 0, { (1<<MACH_BASE) } }  },
1964 /* GRdoublek: destination register */
1965   { "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6,
1966     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
1967     { 0, { (1<<MACH_BASE) } }  },
1968 /* ACC40Si: signed accumulator */
1969   { "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6,
1970     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SI] } },
1971     { 0, { (1<<MACH_BASE) } }  },
1972 /* ACC40Ui: unsigned accumulator */
1973   { "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6,
1974     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UI] } },
1975     { 0, { (1<<MACH_BASE) } }  },
1976 /* ACC40Sk: target accumulator */
1977   { "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6,
1978     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SK] } },
1979     { 0, { (1<<MACH_BASE) } }  },
1980 /* ACC40Uk: target accumulator */
1981   { "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6,
1982     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UK] } },
1983     { 0, { (1<<MACH_BASE) } }  },
1984 /* ACCGi: source register */
1985   { "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6,
1986     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGI] } },
1987     { 0, { (1<<MACH_BASE) } }  },
1988 /* ACCGk: target register */
1989   { "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6,
1990     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGK] } },
1991     { 0, { (1<<MACH_BASE) } }  },
1992 /* CPRi: source register */
1993   { "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6,
1994     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRI] } },
1995     { 0, { (1<<MACH_FRV) } }  },
1996 /* CPRj: source register */
1997   { "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6,
1998     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRJ] } },
1999     { 0, { (1<<MACH_FRV) } }  },
2000 /* CPRk: destination register */
2001   { "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6,
2002     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
2003     { 0, { (1<<MACH_FRV) } }  },
2004 /* CPRdoublek: destination register */
2005   { "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6,
2006     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
2007     { 0, { (1<<MACH_FRV) } }  },
2008 /* FRinti: source register 1 */
2009   { "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6,
2010     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
2011     { 0, { (1<<MACH_BASE) } }  },
2012 /* FRintj: source register 2 */
2013   { "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6,
2014     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
2015     { 0, { (1<<MACH_BASE) } }  },
2016 /* FRintk: target register */
2017   { "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6,
2018     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2019     { 0, { (1<<MACH_BASE) } }  },
2020 /* FRi: source register 1 */
2021   { "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6,
2022     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
2023     { 0, { (1<<MACH_BASE) } }  },
2024 /* FRj: source register 2 */
2025   { "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6,
2026     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
2027     { 0, { (1<<MACH_BASE) } }  },
2028 /* FRk: destination register */
2029   { "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6,
2030     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2031     { 0, { (1<<MACH_BASE) } }  },
2032 /* FRkhi: destination register */
2033   { "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6,
2034     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2035     { 0, { (1<<MACH_BASE) } }  },
2036 /* FRklo: destination register */
2037   { "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6,
2038     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2039     { 0, { (1<<MACH_BASE) } }  },
2040 /* FRdoublei: source register 1 */
2041   { "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6,
2042     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
2043     { 0, { (1<<MACH_BASE) } }  },
2044 /* FRdoublej: source register 2 */
2045   { "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6,
2046     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
2047     { 0, { (1<<MACH_BASE) } }  },
2048 /* FRdoublek: target register */
2049   { "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6,
2050     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2051     { 0, { (1<<MACH_BASE) } }  },
2052 /* CRi: source register 1 */
2053   { "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3,
2054     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRI] } },
2055     { 0, { (1<<MACH_BASE) } }  },
2056 /* CRj: source register 2 */
2057   { "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3,
2058     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ] } },
2059     { 0, { (1<<MACH_BASE) } }  },
2060 /* CRj_int: destination register */
2061   { "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2,
2062     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_INT] } },
2063     { 0, { (1<<MACH_BASE) } }  },
2064 /* CRj_float: destination register */
2065   { "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2,
2066     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } },
2067     { 0, { (1<<MACH_BASE) } }  },
2068 /* CRk: destination register */
2069   { "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3,
2070     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRK] } },
2071     { 0, { (1<<MACH_BASE) } }  },
2072 /* CCi: condition   register */
2073   { "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3,
2074     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCI] } },
2075     { 0, { (1<<MACH_BASE) } }  },
2076 /* ICCi_1: condition   register */
2077   { "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2,
2078     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_1] } },
2079     { 0, { (1<<MACH_BASE) } }  },
2080 /* ICCi_2: condition   register */
2081   { "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2,
2082     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_2] } },
2083     { 0, { (1<<MACH_BASE) } }  },
2084 /* ICCi_3: condition   register */
2085   { "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2,
2086     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_3] } },
2087     { 0, { (1<<MACH_BASE) } }  },
2088 /* FCCi_1: condition   register */
2089   { "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2,
2090     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_1] } },
2091     { 0, { (1<<MACH_BASE) } }  },
2092 /* FCCi_2: condition   register */
2093   { "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2,
2094     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_2] } },
2095     { 0, { (1<<MACH_BASE) } }  },
2096 /* FCCi_3: condition   register */
2097   { "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2,
2098     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_3] } },
2099     { 0, { (1<<MACH_BASE) } }  },
2100 /* FCCk: condition   register */
2101   { "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2,
2102     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCK] } },
2103     { 0, { (1<<MACH_BASE) } }  },
2104 /* eir: exception insn reg */
2105   { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
2106     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_EIR] } },
2107     { 0, { (1<<MACH_BASE) } }  },
2108 /* s10: 10 bit signed immediate */
2109   { "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10,
2110     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S10] } },
2111     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2112 /* u16: 16 bit unsigned immediate */
2113   { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
2114     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
2115     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2116 /* s16: 16 bit signed   immediate */
2117   { "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16,
2118     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
2119     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2120 /* s6: 6  bit signed   immediate */
2121   { "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6,
2122     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6] } },
2123     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2124 /* s6_1: 6  bit signed   immediate */
2125   { "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6,
2126     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6_1] } },
2127     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2128 /* u6: 6  bit unsigned immediate */
2129   { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
2130     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U6] } },
2131     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2132 /* s5: 5  bit signed   immediate */
2133   { "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5,
2134     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S5] } },
2135     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2136 /* cond: conditional arithmetic */
2137   { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
2138     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_COND] } },
2139     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2140 /* ccond: lr branch condition */
2141   { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
2142     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCOND] } },
2143     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2144 /* hint: 2 bit branch predictor */
2145   { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
2146     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
2147     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2148 /* hint_taken: 2 bit branch predictor */
2149   { "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2,
2150     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
2151     { 0, { (1<<MACH_BASE) } }  },
2152 /* hint_not_taken: 2 bit branch predictor */
2153   { "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2,
2154     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
2155     { 0, { (1<<MACH_BASE) } }  },
2156 /* LI: link indicator */
2157   { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
2158     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LI] } },
2159     { 0, { (1<<MACH_BASE) } }  },
2160 /* lock: cache lock indicator */
2161   { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
2162     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LOCK] } },
2163     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2164 /* debug: debug mode indicator */
2165   { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
2166     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } },
2167     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2168 /* ae: all entries indicator */
2169   { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1,
2170     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } },
2171     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2172 /* label16: 18 bit pc relative address */
2173   { "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16,
2174     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABEL16] } },
2175     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
2176 /* label24: 26 bit pc relative address */
2177   { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
2178     { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } },
2179     { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
2180 /* A0: A==0 operand of mclracc */
2181   { "A0", FRV_OPERAND_A0, HW_H_UINT, 17, 1,
2182     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
2183     { 0, { (1<<MACH_BASE) } }  },
2184 /* A1: A==1 operand of mclracc */
2185   { "A1", FRV_OPERAND_A1, HW_H_UINT, 17, 1,
2186     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
2187     { 0, { (1<<MACH_BASE) } }  },
2188 /* FRintieven: (even) source register 1 */
2189   { "FRintieven", FRV_OPERAND_FRINTIEVEN, HW_H_FR_INT, 17, 6,
2190     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
2191     { 0, { (1<<MACH_BASE) } }  },
2192 /* FRintjeven: (even) source register 2 */
2193   { "FRintjeven", FRV_OPERAND_FRINTJEVEN, HW_H_FR_INT, 5, 6,
2194     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
2195     { 0, { (1<<MACH_BASE) } }  },
2196 /* FRintkeven: (even) target register */
2197   { "FRintkeven", FRV_OPERAND_FRINTKEVEN, HW_H_FR_INT, 30, 6,
2198     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2199     { 0, { (1<<MACH_BASE) } }  },
2200 /* d12: 12 bit signed immediate */
2201   { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12,
2202     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
2203     { 0, { (1<<MACH_BASE) } }  },
2204 /* s12: 12 bit signed immediate */
2205   { "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12,
2206     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
2207     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2208 /* u12: 12 bit signed immediate */
2209   { "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12,
2210     { 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } },
2211     { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
2212 /* spr: special purpose register */
2213   { "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12,
2214     { 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } },
2215     { 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
2216 /* ulo16: 16 bit unsigned immediate, for #lo() */
2217   { "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16,
2218     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
2219     { 0, { (1<<MACH_BASE) } }  },
2220 /* slo16: 16 bit unsigned immediate, for #lo() */
2221   { "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16,
2222     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
2223     { 0, { (1<<MACH_BASE) } }  },
2224 /* uhi16: 16 bit unsigned immediate, for #hi() */
2225   { "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16,
2226     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
2227     { 0, { (1<<MACH_BASE) } }  },
2228 /* psr_esr: PSR.ESR bit */
2229   { "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0,
2230     { 0, { (const PTR) 0 } },
2231     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2232 /* psr_s: PSR.S   bit */
2233   { "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0,
2234     { 0, { (const PTR) 0 } },
2235     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2236 /* psr_ps: PSR.PS  bit */
2237   { "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0,
2238     { 0, { (const PTR) 0 } },
2239     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2240 /* psr_et: PSR.ET  bit */
2241   { "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0,
2242     { 0, { (const PTR) 0 } },
2243     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2244 /* bpsr_bs: BPSR.BS  bit */
2245   { "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0,
2246     { 0, { (const PTR) 0 } },
2247     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2248 /* bpsr_bet: BPSR.BET bit */
2249   { "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0,
2250     { 0, { (const PTR) 0 } },
2251     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2252 /* tbr_tba: TBR.TBA */
2253   { "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0,
2254     { 0, { (const PTR) 0 } },
2255     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2256 /* tbr_tt: TBR.TT */
2257   { "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0,
2258     { 0, { (const PTR) 0 } },
2259     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2260 /* sentinel */
2261   { 0, 0, 0, 0, 0,
2262     { 0, { (const PTR) 0 } },
2263     { 0, { 0 } } }
2264 };
2265
2266 #undef A
2267
2268
2269 /* The instruction table.  */
2270
2271 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2272 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
2273 #define A(a) (1 << CGEN_INSN_##a)
2274 #else
2275 #define A(a) (1 << CGEN_INSN_/**/a)
2276 #endif
2277
2278 static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
2279 {
2280   /* Special null first entry.
2281      A `num' value of zero is thus invalid.
2282      Also, the special `invalid' insn resides here.  */
2283   { 0, 0, 0, 0, {0, {0}} },
2284 /* add$pack $GRi,$GRj,$GRk */
2285   {
2286     FRV_INSN_ADD, "add", "add", 32,
2287     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2288   },
2289 /* sub$pack $GRi,$GRj,$GRk */
2290   {
2291     FRV_INSN_SUB, "sub", "sub", 32,
2292     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2293   },
2294 /* and$pack $GRi,$GRj,$GRk */
2295   {
2296     FRV_INSN_AND, "and", "and", 32,
2297     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2298   },
2299 /* or$pack $GRi,$GRj,$GRk */
2300   {
2301     FRV_INSN_OR, "or", "or", 32,
2302     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2303   },
2304 /* xor$pack $GRi,$GRj,$GRk */
2305   {
2306     FRV_INSN_XOR, "xor", "xor", 32,
2307     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2308   },
2309 /* not$pack $GRj,$GRk */
2310   {
2311     FRV_INSN_NOT, "not", "not", 32,
2312     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2313   },
2314 /* sdiv$pack $GRi,$GRj,$GRk */
2315   {
2316     FRV_INSN_SDIV, "sdiv", "sdiv", 32,
2317     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2318   },
2319 /* nsdiv$pack $GRi,$GRj,$GRk */
2320   {
2321     FRV_INSN_NSDIV, "nsdiv", "nsdiv", 32,
2322     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2323   },
2324 /* udiv$pack $GRi,$GRj,$GRk */
2325   {
2326     FRV_INSN_UDIV, "udiv", "udiv", 32,
2327     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2328   },
2329 /* nudiv$pack $GRi,$GRj,$GRk */
2330   {
2331     FRV_INSN_NUDIV, "nudiv", "nudiv", 32,
2332     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2333   },
2334 /* smul$pack $GRi,$GRj,$GRdoublek */
2335   {
2336     FRV_INSN_SMUL, "smul", "smul", 32,
2337     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2338   },
2339 /* umul$pack $GRi,$GRj,$GRdoublek */
2340   {
2341     FRV_INSN_UMUL, "umul", "umul", 32,
2342     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2343   },
2344 /* sll$pack $GRi,$GRj,$GRk */
2345   {
2346     FRV_INSN_SLL, "sll", "sll", 32,
2347     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2348   },
2349 /* srl$pack $GRi,$GRj,$GRk */
2350   {
2351     FRV_INSN_SRL, "srl", "srl", 32,
2352     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2353   },
2354 /* sra$pack $GRi,$GRj,$GRk */
2355   {
2356     FRV_INSN_SRA, "sra", "sra", 32,
2357     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2358   },
2359 /* scan$pack $GRi,$GRj,$GRk */
2360   {
2361     FRV_INSN_SCAN, "scan", "scan", 32,
2362     { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2363   },
2364 /* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */
2365   {
2366     FRV_INSN_CADD, "cadd", "cadd", 32,
2367     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2368   },
2369 /* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */
2370   {
2371     FRV_INSN_CSUB, "csub", "csub", 32,
2372     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2373   },
2374 /* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */
2375   {
2376     FRV_INSN_CAND, "cand", "cand", 32,
2377     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2378   },
2379 /* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */
2380   {
2381     FRV_INSN_COR, "cor", "cor", 32,
2382     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2383   },
2384 /* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */
2385   {
2386     FRV_INSN_CXOR, "cxor", "cxor", 32,
2387     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2388   },
2389 /* cnot$pack $GRj,$GRk,$CCi,$cond */
2390   {
2391     FRV_INSN_CNOT, "cnot", "cnot", 32,
2392     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2393   },
2394 /* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
2395   {
2396     FRV_INSN_CSMUL, "csmul", "csmul", 32,
2397     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2398   },
2399 /* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
2400   {
2401     FRV_INSN_CSDIV, "csdiv", "csdiv", 32,
2402     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2403   },
2404 /* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
2405   {
2406     FRV_INSN_CUDIV, "cudiv", "cudiv", 32,
2407     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2408   },
2409 /* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */
2410   {
2411     FRV_INSN_CSLL, "csll", "csll", 32,
2412     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2413   },
2414 /* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */
2415   {
2416     FRV_INSN_CSRL, "csrl", "csrl", 32,
2417     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2418   },
2419 /* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */
2420   {
2421     FRV_INSN_CSRA, "csra", "csra", 32,
2422     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2423   },
2424 /* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */
2425   {
2426     FRV_INSN_CSCAN, "cscan", "cscan", 32,
2427     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2428   },
2429 /* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2430   {
2431     FRV_INSN_ADDCC, "addcc", "addcc", 32,
2432     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2433   },
2434 /* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2435   {
2436     FRV_INSN_SUBCC, "subcc", "subcc", 32,
2437     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2438   },
2439 /* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2440   {
2441     FRV_INSN_ANDCC, "andcc", "andcc", 32,
2442     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2443   },
2444 /* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2445   {
2446     FRV_INSN_ORCC, "orcc", "orcc", 32,
2447     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2448   },
2449 /* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2450   {
2451     FRV_INSN_XORCC, "xorcc", "xorcc", 32,
2452     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2453   },
2454 /* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2455   {
2456     FRV_INSN_SLLCC, "sllcc", "sllcc", 32,
2457     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2458   },
2459 /* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2460   {
2461     FRV_INSN_SRLCC, "srlcc", "srlcc", 32,
2462     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2463   },
2464 /* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2465   {
2466     FRV_INSN_SRACC, "sracc", "sracc", 32,
2467     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2468   },
2469 /* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
2470   {
2471     FRV_INSN_SMULCC, "smulcc", "smulcc", 32,
2472     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2473   },
2474 /* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
2475   {
2476     FRV_INSN_UMULCC, "umulcc", "umulcc", 32,
2477     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2478   },
2479 /* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2480   {
2481     FRV_INSN_CADDCC, "caddcc", "caddcc", 32,
2482     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2483   },
2484 /* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2485   {
2486     FRV_INSN_CSUBCC, "csubcc", "csubcc", 32,
2487     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2488   },
2489 /* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
2490   {
2491     FRV_INSN_CSMULCC, "csmulcc", "csmulcc", 32,
2492     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2493   },
2494 /* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2495   {
2496     FRV_INSN_CANDCC, "candcc", "candcc", 32,
2497     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2498   },
2499 /* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2500   {
2501     FRV_INSN_CORCC, "corcc", "corcc", 32,
2502     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2503   },
2504 /* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2505   {
2506     FRV_INSN_CXORCC, "cxorcc", "cxorcc", 32,
2507     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2508   },
2509 /* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2510   {
2511     FRV_INSN_CSLLCC, "csllcc", "csllcc", 32,
2512     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2513   },
2514 /* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2515   {
2516     FRV_INSN_CSRLCC, "csrlcc", "csrlcc", 32,
2517     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2518   },
2519 /* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2520   {
2521     FRV_INSN_CSRACC, "csracc", "csracc", 32,
2522     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2523   },
2524 /* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */
2525   {
2526     FRV_INSN_ADDX, "addx", "addx", 32,
2527     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2528   },
2529 /* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */
2530   {
2531     FRV_INSN_SUBX, "subx", "subx", 32,
2532     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2533   },
2534 /* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2535   {
2536     FRV_INSN_ADDXCC, "addxcc", "addxcc", 32,
2537     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2538   },
2539 /* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2540   {
2541     FRV_INSN_SUBXCC, "subxcc", "subxcc", 32,
2542     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2543   },
2544 /* addi$pack $GRi,$s12,$GRk */
2545   {
2546     FRV_INSN_ADDI, "addi", "addi", 32,
2547     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2548   },
2549 /* subi$pack $GRi,$s12,$GRk */
2550   {
2551     FRV_INSN_SUBI, "subi", "subi", 32,
2552     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2553   },
2554 /* andi$pack $GRi,$s12,$GRk */
2555   {
2556     FRV_INSN_ANDI, "andi", "andi", 32,
2557     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2558   },
2559 /* ori$pack $GRi,$s12,$GRk */
2560   {
2561     FRV_INSN_ORI, "ori", "ori", 32,
2562     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2563   },
2564 /* xori$pack $GRi,$s12,$GRk */
2565   {
2566     FRV_INSN_XORI, "xori", "xori", 32,
2567     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2568   },
2569 /* sdivi$pack $GRi,$s12,$GRk */
2570   {
2571     FRV_INSN_SDIVI, "sdivi", "sdivi", 32,
2572     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2573   },
2574 /* nsdivi$pack $GRi,$s12,$GRk */
2575   {
2576     FRV_INSN_NSDIVI, "nsdivi", "nsdivi", 32,
2577     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2578   },
2579 /* udivi$pack $GRi,$s12,$GRk */
2580   {
2581     FRV_INSN_UDIVI, "udivi", "udivi", 32,
2582     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2583   },
2584 /* nudivi$pack $GRi,$s12,$GRk */
2585   {
2586     FRV_INSN_NUDIVI, "nudivi", "nudivi", 32,
2587     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2588   },
2589 /* smuli$pack $GRi,$s12,$GRdoublek */
2590   {
2591     FRV_INSN_SMULI, "smuli", "smuli", 32,
2592     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2593   },
2594 /* umuli$pack $GRi,$s12,$GRdoublek */
2595   {
2596     FRV_INSN_UMULI, "umuli", "umuli", 32,
2597     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2598   },
2599 /* slli$pack $GRi,$s12,$GRk */
2600   {
2601     FRV_INSN_SLLI, "slli", "slli", 32,
2602     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2603   },
2604 /* srli$pack $GRi,$s12,$GRk */
2605   {
2606     FRV_INSN_SRLI, "srli", "srli", 32,
2607     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2608   },
2609 /* srai$pack $GRi,$s12,$GRk */
2610   {
2611     FRV_INSN_SRAI, "srai", "srai", 32,
2612     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2613   },
2614 /* scani$pack $GRi,$s12,$GRk */
2615   {
2616     FRV_INSN_SCANI, "scani", "scani", 32,
2617     { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2618   },
2619 /* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2620   {
2621     FRV_INSN_ADDICC, "addicc", "addicc", 32,
2622     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2623   },
2624 /* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2625   {
2626     FRV_INSN_SUBICC, "subicc", "subicc", 32,
2627     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2628   },
2629 /* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2630   {
2631     FRV_INSN_ANDICC, "andicc", "andicc", 32,
2632     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2633   },
2634 /* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */
2635   {
2636     FRV_INSN_ORICC, "oricc", "oricc", 32,
2637     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2638   },
2639 /* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */
2640   {
2641     FRV_INSN_XORICC, "xoricc", "xoricc", 32,
2642     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2643   },
2644 /* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
2645   {
2646     FRV_INSN_SMULICC, "smulicc", "smulicc", 32,
2647     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2648   },
2649 /* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
2650   {
2651     FRV_INSN_UMULICC, "umulicc", "umulicc", 32,
2652     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2653   },
2654 /* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2655   {
2656     FRV_INSN_SLLICC, "sllicc", "sllicc", 32,
2657     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2658   },
2659 /* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2660   {
2661     FRV_INSN_SRLICC, "srlicc", "srlicc", 32,
2662     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2663   },
2664 /* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2665   {
2666     FRV_INSN_SRAICC, "sraicc", "sraicc", 32,
2667     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2668   },
2669 /* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */
2670   {
2671     FRV_INSN_ADDXI, "addxi", "addxi", 32,
2672     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2673   },
2674 /* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */
2675   {
2676     FRV_INSN_SUBXI, "subxi", "subxi", 32,
2677     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2678   },
2679 /* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2680   {
2681     FRV_INSN_ADDXICC, "addxicc", "addxicc", 32,
2682     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2683   },
2684 /* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2685   {
2686     FRV_INSN_SUBXICC, "subxicc", "subxicc", 32,
2687     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2688   },
2689 /* cmpb$pack $GRi,$GRj,$ICCi_1 */
2690   {
2691     FRV_INSN_CMPB, "cmpb", "cmpb", 32,
2692     { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE } }
2693   },
2694 /* cmpba$pack $GRi,$GRj,$ICCi_1 */
2695   {
2696     FRV_INSN_CMPBA, "cmpba", "cmpba", 32,
2697     { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE } }
2698   },
2699 /* setlo$pack $ulo16,$GRklo */
2700   {
2701     FRV_INSN_SETLO, "setlo", "setlo", 32,
2702     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2703   },
2704 /* sethi$pack $uhi16,$GRkhi */
2705   {
2706     FRV_INSN_SETHI, "sethi", "sethi", 32,
2707     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2708   },
2709 /* setlos$pack $slo16,$GRk */
2710   {
2711     FRV_INSN_SETLOS, "setlos", "setlos", 32,
2712     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2713   },
2714 /* ldsb$pack @($GRi,$GRj),$GRk */
2715   {
2716     FRV_INSN_LDSB, "ldsb", "ldsb", 32,
2717     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2718   },
2719 /* ldub$pack @($GRi,$GRj),$GRk */
2720   {
2721     FRV_INSN_LDUB, "ldub", "ldub", 32,
2722     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2723   },
2724 /* ldsh$pack @($GRi,$GRj),$GRk */
2725   {
2726     FRV_INSN_LDSH, "ldsh", "ldsh", 32,
2727     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2728   },
2729 /* lduh$pack @($GRi,$GRj),$GRk */
2730   {
2731     FRV_INSN_LDUH, "lduh", "lduh", 32,
2732     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2733   },
2734 /* ld$pack @($GRi,$GRj),$GRk */
2735   {
2736     FRV_INSN_LD, "ld", "ld", 32,
2737     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2738   },
2739 /* ldbf$pack @($GRi,$GRj),$FRintk */
2740   {
2741     FRV_INSN_LDBF, "ldbf", "ldbf", 32,
2742     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2743   },
2744 /* ldhf$pack @($GRi,$GRj),$FRintk */
2745   {
2746     FRV_INSN_LDHF, "ldhf", "ldhf", 32,
2747     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2748   },
2749 /* ldf$pack @($GRi,$GRj),$FRintk */
2750   {
2751     FRV_INSN_LDF, "ldf", "ldf", 32,
2752     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2753   },
2754 /* ldc$pack @($GRi,$GRj),$CPRk */
2755   {
2756     FRV_INSN_LDC, "ldc", "ldc", 32,
2757     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2758   },
2759 /* nldsb$pack @($GRi,$GRj),$GRk */
2760   {
2761     FRV_INSN_NLDSB, "nldsb", "nldsb", 32,
2762     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2763   },
2764 /* nldub$pack @($GRi,$GRj),$GRk */
2765   {
2766     FRV_INSN_NLDUB, "nldub", "nldub", 32,
2767     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2768   },
2769 /* nldsh$pack @($GRi,$GRj),$GRk */
2770   {
2771     FRV_INSN_NLDSH, "nldsh", "nldsh", 32,
2772     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2773   },
2774 /* nlduh$pack @($GRi,$GRj),$GRk */
2775   {
2776     FRV_INSN_NLDUH, "nlduh", "nlduh", 32,
2777     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2778   },
2779 /* nld$pack @($GRi,$GRj),$GRk */
2780   {
2781     FRV_INSN_NLD, "nld", "nld", 32,
2782     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2783   },
2784 /* nldbf$pack @($GRi,$GRj),$FRintk */
2785   {
2786     FRV_INSN_NLDBF, "nldbf", "nldbf", 32,
2787     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2788   },
2789 /* nldhf$pack @($GRi,$GRj),$FRintk */
2790   {
2791     FRV_INSN_NLDHF, "nldhf", "nldhf", 32,
2792     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2793   },
2794 /* nldf$pack @($GRi,$GRj),$FRintk */
2795   {
2796     FRV_INSN_NLDF, "nldf", "nldf", 32,
2797     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2798   },
2799 /* ldd$pack @($GRi,$GRj),$GRdoublek */
2800   {
2801     FRV_INSN_LDD, "ldd", "ldd", 32,
2802     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2803   },
2804 /* lddf$pack @($GRi,$GRj),$FRdoublek */
2805   {
2806     FRV_INSN_LDDF, "lddf", "lddf", 32,
2807     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2808   },
2809 /* lddc$pack @($GRi,$GRj),$CPRdoublek */
2810   {
2811     FRV_INSN_LDDC, "lddc", "lddc", 32,
2812     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2813   },
2814 /* nldd$pack @($GRi,$GRj),$GRdoublek */
2815   {
2816     FRV_INSN_NLDD, "nldd", "nldd", 32,
2817     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2818   },
2819 /* nlddf$pack @($GRi,$GRj),$FRdoublek */
2820   {
2821     FRV_INSN_NLDDF, "nlddf", "nlddf", 32,
2822     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2823   },
2824 /* ldq$pack @($GRi,$GRj),$GRk */
2825   {
2826     FRV_INSN_LDQ, "ldq", "ldq", 32,
2827     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2828   },
2829 /* ldqf$pack @($GRi,$GRj),$FRintk */
2830   {
2831     FRV_INSN_LDQF, "ldqf", "ldqf", 32,
2832     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2833   },
2834 /* ldqc$pack @($GRi,$GRj),$CPRk */
2835   {
2836     FRV_INSN_LDQC, "ldqc", "ldqc", 32,
2837     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2838   },
2839 /* nldq$pack @($GRi,$GRj),$GRk */
2840   {
2841     FRV_INSN_NLDQ, "nldq", "nldq", 32,
2842     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2843   },
2844 /* nldqf$pack @($GRi,$GRj),$FRintk */
2845   {
2846     FRV_INSN_NLDQF, "nldqf", "nldqf", 32,
2847     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2848   },
2849 /* ldsbu$pack @($GRi,$GRj),$GRk */
2850   {
2851     FRV_INSN_LDSBU, "ldsbu", "ldsbu", 32,
2852     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2853   },
2854 /* ldubu$pack @($GRi,$GRj),$GRk */
2855   {
2856     FRV_INSN_LDUBU, "ldubu", "ldubu", 32,
2857     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2858   },
2859 /* ldshu$pack @($GRi,$GRj),$GRk */
2860   {
2861     FRV_INSN_LDSHU, "ldshu", "ldshu", 32,
2862     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2863   },
2864 /* lduhu$pack @($GRi,$GRj),$GRk */
2865   {
2866     FRV_INSN_LDUHU, "lduhu", "lduhu", 32,
2867     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2868   },
2869 /* ldu$pack @($GRi,$GRj),$GRk */
2870   {
2871     FRV_INSN_LDU, "ldu", "ldu", 32,
2872     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2873   },
2874 /* nldsbu$pack @($GRi,$GRj),$GRk */
2875   {
2876     FRV_INSN_NLDSBU, "nldsbu", "nldsbu", 32,
2877     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2878   },
2879 /* nldubu$pack @($GRi,$GRj),$GRk */
2880   {
2881     FRV_INSN_NLDUBU, "nldubu", "nldubu", 32,
2882     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2883   },
2884 /* nldshu$pack @($GRi,$GRj),$GRk */
2885   {
2886     FRV_INSN_NLDSHU, "nldshu", "nldshu", 32,
2887     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2888   },
2889 /* nlduhu$pack @($GRi,$GRj),$GRk */
2890   {
2891     FRV_INSN_NLDUHU, "nlduhu", "nlduhu", 32,
2892     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2893   },
2894 /* nldu$pack @($GRi,$GRj),$GRk */
2895   {
2896     FRV_INSN_NLDU, "nldu", "nldu", 32,
2897     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2898   },
2899 /* ldbfu$pack @($GRi,$GRj),$FRintk */
2900   {
2901     FRV_INSN_LDBFU, "ldbfu", "ldbfu", 32,
2902     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2903   },
2904 /* ldhfu$pack @($GRi,$GRj),$FRintk */
2905   {
2906     FRV_INSN_LDHFU, "ldhfu", "ldhfu", 32,
2907     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2908   },
2909 /* ldfu$pack @($GRi,$GRj),$FRintk */
2910   {
2911     FRV_INSN_LDFU, "ldfu", "ldfu", 32,
2912     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2913   },
2914 /* ldcu$pack @($GRi,$GRj),$CPRk */
2915   {
2916     FRV_INSN_LDCU, "ldcu", "ldcu", 32,
2917     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2918   },
2919 /* nldbfu$pack @($GRi,$GRj),$FRintk */
2920   {
2921     FRV_INSN_NLDBFU, "nldbfu", "nldbfu", 32,
2922     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2923   },
2924 /* nldhfu$pack @($GRi,$GRj),$FRintk */
2925   {
2926     FRV_INSN_NLDHFU, "nldhfu", "nldhfu", 32,
2927     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2928   },
2929 /* nldfu$pack @($GRi,$GRj),$FRintk */
2930   {
2931     FRV_INSN_NLDFU, "nldfu", "nldfu", 32,
2932     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2933   },
2934 /* lddu$pack @($GRi,$GRj),$GRdoublek */
2935   {
2936     FRV_INSN_LDDU, "lddu", "lddu", 32,
2937     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2938   },
2939 /* nlddu$pack @($GRi,$GRj),$GRdoublek */
2940   {
2941     FRV_INSN_NLDDU, "nlddu", "nlddu", 32,
2942     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2943   },
2944 /* lddfu$pack @($GRi,$GRj),$FRdoublek */
2945   {
2946     FRV_INSN_LDDFU, "lddfu", "lddfu", 32,
2947     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2948   },
2949 /* lddcu$pack @($GRi,$GRj),$CPRdoublek */
2950   {
2951     FRV_INSN_LDDCU, "lddcu", "lddcu", 32,
2952     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2953   },
2954 /* nlddfu$pack @($GRi,$GRj),$FRdoublek */
2955   {
2956     FRV_INSN_NLDDFU, "nlddfu", "nlddfu", 32,
2957     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2958   },
2959 /* ldqu$pack @($GRi,$GRj),$GRk */
2960   {
2961     FRV_INSN_LDQU, "ldqu", "ldqu", 32,
2962     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2963   },
2964 /* nldqu$pack @($GRi,$GRj),$GRk */
2965   {
2966     FRV_INSN_NLDQU, "nldqu", "nldqu", 32,
2967     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2968   },
2969 /* ldqfu$pack @($GRi,$GRj),$FRintk */
2970   {
2971     FRV_INSN_LDQFU, "ldqfu", "ldqfu", 32,
2972     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2973   },
2974 /* ldqcu$pack @($GRi,$GRj),$CPRk */
2975   {
2976     FRV_INSN_LDQCU, "ldqcu", "ldqcu", 32,
2977     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2978   },
2979 /* nldqfu$pack @($GRi,$GRj),$FRintk */
2980   {
2981     FRV_INSN_NLDQFU, "nldqfu", "nldqfu", 32,
2982     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2983   },
2984 /* ldsbi$pack @($GRi,$d12),$GRk */
2985   {
2986     FRV_INSN_LDSBI, "ldsbi", "ldsbi", 32,
2987     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2988   },
2989 /* ldshi$pack @($GRi,$d12),$GRk */
2990   {
2991     FRV_INSN_LDSHI, "ldshi", "ldshi", 32,
2992     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2993   },
2994 /* ldi$pack @($GRi,$d12),$GRk */
2995   {
2996     FRV_INSN_LDI, "ldi", "ldi", 32,
2997     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2998   },
2999 /* ldubi$pack @($GRi,$d12),$GRk */
3000   {
3001     FRV_INSN_LDUBI, "ldubi", "ldubi", 32,
3002     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3003   },
3004 /* lduhi$pack @($GRi,$d12),$GRk */
3005   {
3006     FRV_INSN_LDUHI, "lduhi", "lduhi", 32,
3007     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3008   },
3009 /* ldbfi$pack @($GRi,$d12),$FRintk */
3010   {
3011     FRV_INSN_LDBFI, "ldbfi", "ldbfi", 32,
3012     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3013   },
3014 /* ldhfi$pack @($GRi,$d12),$FRintk */
3015   {
3016     FRV_INSN_LDHFI, "ldhfi", "ldhfi", 32,
3017     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3018   },
3019 /* ldfi$pack @($GRi,$d12),$FRintk */
3020   {
3021     FRV_INSN_LDFI, "ldfi", "ldfi", 32,
3022     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3023   },
3024 /* nldsbi$pack @($GRi,$d12),$GRk */
3025   {
3026     FRV_INSN_NLDSBI, "nldsbi", "nldsbi", 32,
3027     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3028   },
3029 /* nldubi$pack @($GRi,$d12),$GRk */
3030   {
3031     FRV_INSN_NLDUBI, "nldubi", "nldubi", 32,
3032     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3033   },
3034 /* nldshi$pack @($GRi,$d12),$GRk */
3035   {
3036     FRV_INSN_NLDSHI, "nldshi", "nldshi", 32,
3037     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3038   },
3039 /* nlduhi$pack @($GRi,$d12),$GRk */
3040   {
3041     FRV_INSN_NLDUHI, "nlduhi", "nlduhi", 32,
3042     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3043   },
3044 /* nldi$pack @($GRi,$d12),$GRk */
3045   {
3046     FRV_INSN_NLDI, "nldi", "nldi", 32,
3047     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3048   },
3049 /* nldbfi$pack @($GRi,$d12),$FRintk */
3050   {
3051     FRV_INSN_NLDBFI, "nldbfi", "nldbfi", 32,
3052     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3053   },
3054 /* nldhfi$pack @($GRi,$d12),$FRintk */
3055   {
3056     FRV_INSN_NLDHFI, "nldhfi", "nldhfi", 32,
3057     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3058   },
3059 /* nldfi$pack @($GRi,$d12),$FRintk */
3060   {
3061     FRV_INSN_NLDFI, "nldfi", "nldfi", 32,
3062     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3063   },
3064 /* lddi$pack @($GRi,$d12),$GRdoublek */
3065   {
3066     FRV_INSN_LDDI, "lddi", "lddi", 32,
3067     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3068   },
3069 /* lddfi$pack @($GRi,$d12),$FRdoublek */
3070   {
3071     FRV_INSN_LDDFI, "lddfi", "lddfi", 32,
3072     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3073   },
3074 /* nlddi$pack @($GRi,$d12),$GRdoublek */
3075   {
3076     FRV_INSN_NLDDI, "nlddi", "nlddi", 32,
3077     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3078   },
3079 /* nlddfi$pack @($GRi,$d12),$FRdoublek */
3080   {
3081     FRV_INSN_NLDDFI, "nlddfi", "nlddfi", 32,
3082     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3083   },
3084 /* ldqi$pack @($GRi,$d12),$GRk */
3085   {
3086     FRV_INSN_LDQI, "ldqi", "ldqi", 32,
3087     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3088   },
3089 /* ldqfi$pack @($GRi,$d12),$FRintk */
3090   {
3091     FRV_INSN_LDQFI, "ldqfi", "ldqfi", 32,
3092     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3093   },
3094 /* nldqfi$pack @($GRi,$d12),$FRintk */
3095   {
3096     FRV_INSN_NLDQFI, "nldqfi", "nldqfi", 32,
3097     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3098   },
3099 /* stb$pack $GRk,@($GRi,$GRj) */
3100   {
3101     FRV_INSN_STB, "stb", "stb", 32,
3102     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3103   },
3104 /* sth$pack $GRk,@($GRi,$GRj) */
3105   {
3106     FRV_INSN_STH, "sth", "sth", 32,
3107     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3108   },
3109 /* st$pack $GRk,@($GRi,$GRj) */
3110   {
3111     FRV_INSN_ST, "st", "st", 32,
3112     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3113   },
3114 /* stbf$pack $FRintk,@($GRi,$GRj) */
3115   {
3116     FRV_INSN_STBF, "stbf", "stbf", 32,
3117     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3118   },
3119 /* sthf$pack $FRintk,@($GRi,$GRj) */
3120   {
3121     FRV_INSN_STHF, "sthf", "sthf", 32,
3122     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3123   },
3124 /* stf$pack $FRintk,@($GRi,$GRj) */
3125   {
3126     FRV_INSN_STF, "stf", "stf", 32,
3127     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3128   },
3129 /* stc$pack $CPRk,@($GRi,$GRj) */
3130   {
3131     FRV_INSN_STC, "stc", "stc", 32,
3132     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3133   },
3134 /* rstb$pack $GRk,@($GRi,$GRj) */
3135   {
3136     FRV_INSN_RSTB, "rstb", "rstb", 32,
3137     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3138   },
3139 /* rsth$pack $GRk,@($GRi,$GRj) */
3140   {
3141     FRV_INSN_RSTH, "rsth", "rsth", 32,
3142     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3143   },
3144 /* rst$pack $GRk,@($GRi,$GRj) */
3145   {
3146     FRV_INSN_RST, "rst", "rst", 32,
3147     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3148   },
3149 /* rstbf$pack $FRintk,@($GRi,$GRj) */
3150   {
3151     FRV_INSN_RSTBF, "rstbf", "rstbf", 32,
3152     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3153   },
3154 /* rsthf$pack $FRintk,@($GRi,$GRj) */
3155   {
3156     FRV_INSN_RSTHF, "rsthf", "rsthf", 32,
3157     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3158   },
3159 /* rstf$pack $FRintk,@($GRi,$GRj) */
3160   {
3161     FRV_INSN_RSTF, "rstf", "rstf", 32,
3162     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3163   },
3164 /* std$pack $GRk,@($GRi,$GRj) */
3165   {
3166     FRV_INSN_STD, "std", "std", 32,
3167     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3168   },
3169 /* stdf$pack $FRk,@($GRi,$GRj) */
3170   {
3171     FRV_INSN_STDF, "stdf", "stdf", 32,
3172     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3173   },
3174 /* stdc$pack $CPRk,@($GRi,$GRj) */
3175   {
3176     FRV_INSN_STDC, "stdc", "stdc", 32,
3177     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3178   },
3179 /* rstd$pack $GRk,@($GRi,$GRj) */
3180   {
3181     FRV_INSN_RSTD, "rstd", "rstd", 32,
3182     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3183   },
3184 /* rstdf$pack $FRk,@($GRi,$GRj) */
3185   {
3186     FRV_INSN_RSTDF, "rstdf", "rstdf", 32,
3187     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3188   },
3189 /* stq$pack $GRk,@($GRi,$GRj) */
3190   {
3191     FRV_INSN_STQ, "stq", "stq", 32,
3192     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3193   },
3194 /* stqf$pack $FRintk,@($GRi,$GRj) */
3195   {
3196     FRV_INSN_STQF, "stqf", "stqf", 32,
3197     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3198   },
3199 /* stqc$pack $CPRk,@($GRi,$GRj) */
3200   {
3201     FRV_INSN_STQC, "stqc", "stqc", 32,
3202     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3203   },
3204 /* rstq$pack $GRk,@($GRi,$GRj) */
3205   {
3206     FRV_INSN_RSTQ, "rstq", "rstq", 32,
3207     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3208   },
3209 /* rstqf$pack $FRintk,@($GRi,$GRj) */
3210   {
3211     FRV_INSN_RSTQF, "rstqf", "rstqf", 32,
3212     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3213   },
3214 /* stbu$pack $GRk,@($GRi,$GRj) */
3215   {
3216     FRV_INSN_STBU, "stbu", "stbu", 32,
3217     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3218   },
3219 /* sthu$pack $GRk,@($GRi,$GRj) */
3220   {
3221     FRV_INSN_STHU, "sthu", "sthu", 32,
3222     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3223   },
3224 /* stu$pack $GRk,@($GRi,$GRj) */
3225   {
3226     FRV_INSN_STU, "stu", "stu", 32,
3227     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3228   },
3229 /* stbfu$pack $FRintk,@($GRi,$GRj) */
3230   {
3231     FRV_INSN_STBFU, "stbfu", "stbfu", 32,
3232     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3233   },
3234 /* sthfu$pack $FRintk,@($GRi,$GRj) */
3235   {
3236     FRV_INSN_STHFU, "sthfu", "sthfu", 32,
3237     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3238   },
3239 /* stfu$pack $FRintk,@($GRi,$GRj) */
3240   {
3241     FRV_INSN_STFU, "stfu", "stfu", 32,
3242     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3243   },
3244 /* stcu$pack $CPRk,@($GRi,$GRj) */
3245   {
3246     FRV_INSN_STCU, "stcu", "stcu", 32,
3247     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3248   },
3249 /* stdu$pack $GRk,@($GRi,$GRj) */
3250   {
3251     FRV_INSN_STDU, "stdu", "stdu", 32,
3252     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3253   },
3254 /* stdfu$pack $FRk,@($GRi,$GRj) */
3255   {
3256     FRV_INSN_STDFU, "stdfu", "stdfu", 32,
3257     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3258   },
3259 /* stdcu$pack $CPRk,@($GRi,$GRj) */
3260   {
3261     FRV_INSN_STDCU, "stdcu", "stdcu", 32,
3262     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3263   },
3264 /* stqu$pack $GRk,@($GRi,$GRj) */
3265   {
3266     FRV_INSN_STQU, "stqu", "stqu", 32,
3267     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3268   },
3269 /* stqfu$pack $FRintk,@($GRi,$GRj) */
3270   {
3271     FRV_INSN_STQFU, "stqfu", "stqfu", 32,
3272     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3273   },
3274 /* stqcu$pack $CPRk,@($GRi,$GRj) */
3275   {
3276     FRV_INSN_STQCU, "stqcu", "stqcu", 32,
3277     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3278   },
3279 /* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3280   {
3281     FRV_INSN_CLDSB, "cldsb", "cldsb", 32,
3282     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3283   },
3284 /* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3285   {
3286     FRV_INSN_CLDUB, "cldub", "cldub", 32,
3287     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3288   },
3289 /* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3290   {
3291     FRV_INSN_CLDSH, "cldsh", "cldsh", 32,
3292     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3293   },
3294 /* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3295   {
3296     FRV_INSN_CLDUH, "clduh", "clduh", 32,
3297     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3298   },
3299 /* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3300   {
3301     FRV_INSN_CLD, "cld", "cld", 32,
3302     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3303   },
3304 /* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3305   {
3306     FRV_INSN_CLDBF, "cldbf", "cldbf", 32,
3307     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3308   },
3309 /* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3310   {
3311     FRV_INSN_CLDHF, "cldhf", "cldhf", 32,
3312     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3313   },
3314 /* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3315   {
3316     FRV_INSN_CLDF, "cldf", "cldf", 32,
3317     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3318   },
3319 /* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
3320   {
3321     FRV_INSN_CLDD, "cldd", "cldd", 32,
3322     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3323   },
3324 /* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
3325   {
3326     FRV_INSN_CLDDF, "clddf", "clddf", 32,
3327     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3328   },
3329 /* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3330   {
3331     FRV_INSN_CLDQ, "cldq", "cldq", 32,
3332     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3333   },
3334 /* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3335   {
3336     FRV_INSN_CLDSBU, "cldsbu", "cldsbu", 32,
3337     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3338   },
3339 /* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3340   {
3341     FRV_INSN_CLDUBU, "cldubu", "cldubu", 32,
3342     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3343   },
3344 /* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3345   {
3346     FRV_INSN_CLDSHU, "cldshu", "cldshu", 32,
3347     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3348   },
3349 /* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3350   {
3351     FRV_INSN_CLDUHU, "clduhu", "clduhu", 32,
3352     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3353   },
3354 /* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3355   {
3356     FRV_INSN_CLDU, "cldu", "cldu", 32,
3357     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3358   },
3359 /* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3360   {
3361     FRV_INSN_CLDBFU, "cldbfu", "cldbfu", 32,
3362     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3363   },
3364 /* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3365   {
3366     FRV_INSN_CLDHFU, "cldhfu", "cldhfu", 32,
3367     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3368   },
3369 /* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3370   {
3371     FRV_INSN_CLDFU, "cldfu", "cldfu", 32,
3372     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3373   },
3374 /* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
3375   {
3376     FRV_INSN_CLDDU, "clddu", "clddu", 32,
3377     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3378   },
3379 /* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
3380   {
3381     FRV_INSN_CLDDFU, "clddfu", "clddfu", 32,
3382     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3383   },
3384 /* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3385   {
3386     FRV_INSN_CLDQU, "cldqu", "cldqu", 32,
3387     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3388   },
3389 /* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3390   {
3391     FRV_INSN_CSTB, "cstb", "cstb", 32,
3392     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3393   },
3394 /* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3395   {
3396     FRV_INSN_CSTH, "csth", "csth", 32,
3397     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3398   },
3399 /* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3400   {
3401     FRV_INSN_CST, "cst", "cst", 32,
3402     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3403   },
3404 /* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3405   {
3406     FRV_INSN_CSTBF, "cstbf", "cstbf", 32,
3407     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3408   },
3409 /* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3410   {
3411     FRV_INSN_CSTHF, "csthf", "csthf", 32,
3412     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3413   },
3414 /* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3415   {
3416     FRV_INSN_CSTF, "cstf", "cstf", 32,
3417     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3418   },
3419 /* cstd$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3420   {
3421     FRV_INSN_CSTD, "cstd", "cstd", 32,
3422     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3423   },
3424 /* cstdf$pack $FRk,@($GRi,$GRj),$CCi,$cond */
3425   {
3426     FRV_INSN_CSTDF, "cstdf", "cstdf", 32,
3427     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3428   },
3429 /* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3430   {
3431     FRV_INSN_CSTQ, "cstq", "cstq", 32,
3432     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3433   },
3434 /* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3435   {
3436     FRV_INSN_CSTBU, "cstbu", "cstbu", 32,
3437     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3438   },
3439 /* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3440   {
3441     FRV_INSN_CSTHU, "csthu", "csthu", 32,
3442     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3443   },
3444 /* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3445   {
3446     FRV_INSN_CSTU, "cstu", "cstu", 32,
3447     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3448   },
3449 /* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3450   {
3451     FRV_INSN_CSTBFU, "cstbfu", "cstbfu", 32,
3452     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3453   },
3454 /* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3455   {
3456     FRV_INSN_CSTHFU, "csthfu", "csthfu", 32,
3457     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3458   },
3459 /* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3460   {
3461     FRV_INSN_CSTFU, "cstfu", "cstfu", 32,
3462     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3463   },
3464 /* cstdu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3465   {
3466     FRV_INSN_CSTDU, "cstdu", "cstdu", 32,
3467     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3468   },
3469 /* cstdfu$pack $FRk,@($GRi,$GRj),$CCi,$cond */
3470   {
3471     FRV_INSN_CSTDFU, "cstdfu", "cstdfu", 32,
3472     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3473   },
3474 /* stbi$pack $GRk,@($GRi,$d12) */
3475   {
3476     FRV_INSN_STBI, "stbi", "stbi", 32,
3477     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3478   },
3479 /* sthi$pack $GRk,@($GRi,$d12) */
3480   {
3481     FRV_INSN_STHI, "sthi", "sthi", 32,
3482     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3483   },
3484 /* sti$pack $GRk,@($GRi,$d12) */
3485   {
3486     FRV_INSN_STI, "sti", "sti", 32,
3487     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3488   },
3489 /* stbfi$pack $FRintk,@($GRi,$d12) */
3490   {
3491     FRV_INSN_STBFI, "stbfi", "stbfi", 32,
3492     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3493   },
3494 /* sthfi$pack $FRintk,@($GRi,$d12) */
3495   {
3496     FRV_INSN_STHFI, "sthfi", "sthfi", 32,
3497     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3498   },
3499 /* stfi$pack $FRintk,@($GRi,$d12) */
3500   {
3501     FRV_INSN_STFI, "stfi", "stfi", 32,
3502     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3503   },
3504 /* stdi$pack $GRk,@($GRi,$d12) */
3505   {
3506     FRV_INSN_STDI, "stdi", "stdi", 32,
3507     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3508   },
3509 /* stdfi$pack $FRk,@($GRi,$d12) */
3510   {
3511     FRV_INSN_STDFI, "stdfi", "stdfi", 32,
3512     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3513   },
3514 /* stqi$pack $GRk,@($GRi,$d12) */
3515   {
3516     FRV_INSN_STQI, "stqi", "stqi", 32,
3517     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3518   },
3519 /* stqfi$pack $FRintk,@($GRi,$d12) */
3520   {
3521     FRV_INSN_STQFI, "stqfi", "stqfi", 32,
3522     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3523   },
3524 /* swap$pack @($GRi,$GRj),$GRk */
3525   {
3526     FRV_INSN_SWAP, "swap", "swap", 32,
3527     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3528   },
3529 /* swapi$pack @($GRi,$d12),$GRk */
3530   {
3531     FRV_INSN_SWAPI, "swapi", "swapi", 32,
3532     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3533   },
3534 /* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3535   {
3536     FRV_INSN_CSWAP, "cswap", "cswap", 32,
3537     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3538   },
3539 /* movgf$pack $GRj,$FRintk */
3540   {
3541     FRV_INSN_MOVGF, "movgf", "movgf", 32,
3542     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3543   },
3544 /* movfg$pack $FRintk,$GRj */
3545   {
3546     FRV_INSN_MOVFG, "movfg", "movfg", 32,
3547     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3548   },
3549 /* movgfd$pack $GRj,$FRintk */
3550   {
3551     FRV_INSN_MOVGFD, "movgfd", "movgfd", 32,
3552     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3553   },
3554 /* movfgd$pack $FRintk,$GRj */
3555   {
3556     FRV_INSN_MOVFGD, "movfgd", "movfgd", 32,
3557     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3558   },
3559 /* movgfq$pack $GRj,$FRintk */
3560   {
3561     FRV_INSN_MOVGFQ, "movgfq", "movgfq", 32,
3562     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } }
3563   },
3564 /* movfgq$pack $FRintk,$GRj */
3565   {
3566     FRV_INSN_MOVFGQ, "movfgq", "movfgq", 32,
3567     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } }
3568   },
3569 /* cmovgf$pack $GRj,$FRintk,$CCi,$cond */
3570   {
3571     FRV_INSN_CMOVGF, "cmovgf", "cmovgf", 32,
3572     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3573   },
3574 /* cmovfg$pack $FRintk,$GRj,$CCi,$cond */
3575   {
3576     FRV_INSN_CMOVFG, "cmovfg", "cmovfg", 32,
3577     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3578   },
3579 /* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */
3580   {
3581     FRV_INSN_CMOVGFD, "cmovgfd", "cmovgfd", 32,
3582     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3583   },
3584 /* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */
3585   {
3586     FRV_INSN_CMOVFGD, "cmovfgd", "cmovfgd", 32,
3587     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3588   },
3589 /* movgs$pack $GRj,$spr */
3590   {
3591     FRV_INSN_MOVGS, "movgs", "movgs", 32,
3592     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3593   },
3594 /* movsg$pack $spr,$GRj */
3595   {
3596     FRV_INSN_MOVSG, "movsg", "movsg", 32,
3597     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3598   },
3599 /* bra$pack $hint_taken$label16 */
3600   {
3601     FRV_INSN_BRA, "bra", "bra", 32,
3602     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3603   },
3604 /* bno$pack$hint_not_taken */
3605   {
3606     FRV_INSN_BNO, "bno", "bno", 32,
3607     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3608   },
3609 /* beq$pack $ICCi_2,$hint,$label16 */
3610   {
3611     FRV_INSN_BEQ, "beq", "beq", 32,
3612     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3613   },
3614 /* bne$pack $ICCi_2,$hint,$label16 */
3615   {
3616     FRV_INSN_BNE, "bne", "bne", 32,
3617     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3618   },
3619 /* ble$pack $ICCi_2,$hint,$label16 */
3620   {
3621     FRV_INSN_BLE, "ble", "ble", 32,
3622     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3623   },
3624 /* bgt$pack $ICCi_2,$hint,$label16 */
3625   {
3626     FRV_INSN_BGT, "bgt", "bgt", 32,
3627     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3628   },
3629 /* blt$pack $ICCi_2,$hint,$label16 */
3630   {
3631     FRV_INSN_BLT, "blt", "blt", 32,
3632     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3633   },
3634 /* bge$pack $ICCi_2,$hint,$label16 */
3635   {
3636     FRV_INSN_BGE, "bge", "bge", 32,
3637     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3638   },
3639 /* bls$pack $ICCi_2,$hint,$label16 */
3640   {
3641     FRV_INSN_BLS, "bls", "bls", 32,
3642     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3643   },
3644 /* bhi$pack $ICCi_2,$hint,$label16 */
3645   {
3646     FRV_INSN_BHI, "bhi", "bhi", 32,
3647     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3648   },
3649 /* bc$pack $ICCi_2,$hint,$label16 */
3650   {
3651     FRV_INSN_BC, "bc", "bc", 32,
3652     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3653   },
3654 /* bnc$pack $ICCi_2,$hint,$label16 */
3655   {
3656     FRV_INSN_BNC, "bnc", "bnc", 32,
3657     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3658   },
3659 /* bn$pack $ICCi_2,$hint,$label16 */
3660   {
3661     FRV_INSN_BN, "bn", "bn", 32,
3662     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3663   },
3664 /* bp$pack $ICCi_2,$hint,$label16 */
3665   {
3666     FRV_INSN_BP, "bp", "bp", 32,
3667     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3668   },
3669 /* bv$pack $ICCi_2,$hint,$label16 */
3670   {
3671     FRV_INSN_BV, "bv", "bv", 32,
3672     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3673   },
3674 /* bnv$pack $ICCi_2,$hint,$label16 */
3675   {
3676     FRV_INSN_BNV, "bnv", "bnv", 32,
3677     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3678   },
3679 /* fbra$pack $hint_taken$label16 */
3680   {
3681     FRV_INSN_FBRA, "fbra", "fbra", 32,
3682     { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3683   },
3684 /* fbno$pack$hint_not_taken */
3685   {
3686     FRV_INSN_FBNO, "fbno", "fbno", 32,
3687     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3688   },
3689 /* fbne$pack $FCCi_2,$hint,$label16 */
3690   {
3691     FRV_INSN_FBNE, "fbne", "fbne", 32,
3692     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3693   },
3694 /* fbeq$pack $FCCi_2,$hint,$label16 */
3695   {
3696     FRV_INSN_FBEQ, "fbeq", "fbeq", 32,
3697     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3698   },
3699 /* fblg$pack $FCCi_2,$hint,$label16 */
3700   {
3701     FRV_INSN_FBLG, "fblg", "fblg", 32,
3702     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3703   },
3704 /* fbue$pack $FCCi_2,$hint,$label16 */
3705   {
3706     FRV_INSN_FBUE, "fbue", "fbue", 32,
3707     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3708   },
3709 /* fbul$pack $FCCi_2,$hint,$label16 */
3710   {
3711     FRV_INSN_FBUL, "fbul", "fbul", 32,
3712     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3713   },
3714 /* fbge$pack $FCCi_2,$hint,$label16 */
3715   {
3716     FRV_INSN_FBGE, "fbge", "fbge", 32,
3717     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3718   },
3719 /* fblt$pack $FCCi_2,$hint,$label16 */
3720   {
3721     FRV_INSN_FBLT, "fblt", "fblt", 32,
3722     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3723   },
3724 /* fbuge$pack $FCCi_2,$hint,$label16 */
3725   {
3726     FRV_INSN_FBUGE, "fbuge", "fbuge", 32,
3727     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3728   },
3729 /* fbug$pack $FCCi_2,$hint,$label16 */
3730   {
3731     FRV_INSN_FBUG, "fbug", "fbug", 32,
3732     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3733   },
3734 /* fble$pack $FCCi_2,$hint,$label16 */
3735   {
3736     FRV_INSN_FBLE, "fble", "fble", 32,
3737     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3738   },
3739 /* fbgt$pack $FCCi_2,$hint,$label16 */
3740   {
3741     FRV_INSN_FBGT, "fbgt", "fbgt", 32,
3742     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3743   },
3744 /* fbule$pack $FCCi_2,$hint,$label16 */
3745   {
3746     FRV_INSN_FBULE, "fbule", "fbule", 32,
3747     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3748   },
3749 /* fbu$pack $FCCi_2,$hint,$label16 */
3750   {
3751     FRV_INSN_FBU, "fbu", "fbu", 32,
3752     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3753   },
3754 /* fbo$pack $FCCi_2,$hint,$label16 */
3755   {
3756     FRV_INSN_FBO, "fbo", "fbo", 32,
3757     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3758   },
3759 /* bctrlr$pack $ccond,$hint */
3760   {
3761     FRV_INSN_BCTRLR, "bctrlr", "bctrlr", 32,
3762     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3763   },
3764 /* bralr$pack$hint_taken */
3765   {
3766     FRV_INSN_BRALR, "bralr", "bralr", 32,
3767     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3768   },
3769 /* bnolr$pack$hint_not_taken */
3770   {
3771     FRV_INSN_BNOLR, "bnolr", "bnolr", 32,
3772     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3773   },
3774 /* beqlr$pack $ICCi_2,$hint */
3775   {
3776     FRV_INSN_BEQLR, "beqlr", "beqlr", 32,
3777     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3778   },
3779 /* bnelr$pack $ICCi_2,$hint */
3780   {
3781     FRV_INSN_BNELR, "bnelr", "bnelr", 32,
3782     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3783   },
3784 /* blelr$pack $ICCi_2,$hint */
3785   {
3786     FRV_INSN_BLELR, "blelr", "blelr", 32,
3787     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3788   },
3789 /* bgtlr$pack $ICCi_2,$hint */
3790   {
3791     FRV_INSN_BGTLR, "bgtlr", "bgtlr", 32,
3792     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3793   },
3794 /* bltlr$pack $ICCi_2,$hint */
3795   {
3796     FRV_INSN_BLTLR, "bltlr", "bltlr", 32,
3797     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3798   },
3799 /* bgelr$pack $ICCi_2,$hint */
3800   {
3801     FRV_INSN_BGELR, "bgelr", "bgelr", 32,
3802     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3803   },
3804 /* blslr$pack $ICCi_2,$hint */
3805   {
3806     FRV_INSN_BLSLR, "blslr", "blslr", 32,
3807     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3808   },
3809 /* bhilr$pack $ICCi_2,$hint */
3810   {
3811     FRV_INSN_BHILR, "bhilr", "bhilr", 32,
3812     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3813   },
3814 /* bclr$pack $ICCi_2,$hint */
3815   {
3816     FRV_INSN_BCLR, "bclr", "bclr", 32,
3817     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3818   },
3819 /* bnclr$pack $ICCi_2,$hint */
3820   {
3821     FRV_INSN_BNCLR, "bnclr", "bnclr", 32,
3822     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3823   },
3824 /* bnlr$pack $ICCi_2,$hint */
3825   {
3826     FRV_INSN_BNLR, "bnlr", "bnlr", 32,
3827     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3828   },
3829 /* bplr$pack $ICCi_2,$hint */
3830   {
3831     FRV_INSN_BPLR, "bplr", "bplr", 32,
3832     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3833   },
3834 /* bvlr$pack $ICCi_2,$hint */
3835   {
3836     FRV_INSN_BVLR, "bvlr", "bvlr", 32,
3837     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3838   },
3839 /* bnvlr$pack $ICCi_2,$hint */
3840   {
3841     FRV_INSN_BNVLR, "bnvlr", "bnvlr", 32,
3842     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3843   },
3844 /* fbralr$pack$hint_taken */
3845   {
3846     FRV_INSN_FBRALR, "fbralr", "fbralr", 32,
3847     { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3848   },
3849 /* fbnolr$pack$hint_not_taken */
3850   {
3851     FRV_INSN_FBNOLR, "fbnolr", "fbnolr", 32,
3852     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3853   },
3854 /* fbeqlr$pack $FCCi_2,$hint */
3855   {
3856     FRV_INSN_FBEQLR, "fbeqlr", "fbeqlr", 32,
3857     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3858   },
3859 /* fbnelr$pack $FCCi_2,$hint */
3860   {
3861     FRV_INSN_FBNELR, "fbnelr", "fbnelr", 32,
3862     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3863   },
3864 /* fblglr$pack $FCCi_2,$hint */
3865   {
3866     FRV_INSN_FBLGLR, "fblglr", "fblglr", 32,
3867     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3868   },
3869 /* fbuelr$pack $FCCi_2,$hint */
3870   {
3871     FRV_INSN_FBUELR, "fbuelr", "fbuelr", 32,
3872     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3873   },
3874 /* fbullr$pack $FCCi_2,$hint */
3875   {
3876     FRV_INSN_FBULLR, "fbullr", "fbullr", 32,
3877     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3878   },
3879 /* fbgelr$pack $FCCi_2,$hint */
3880   {
3881     FRV_INSN_FBGELR, "fbgelr", "fbgelr", 32,
3882     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3883   },
3884 /* fbltlr$pack $FCCi_2,$hint */
3885   {
3886     FRV_INSN_FBLTLR, "fbltlr", "fbltlr", 32,
3887     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3888   },
3889 /* fbugelr$pack $FCCi_2,$hint */
3890   {
3891     FRV_INSN_FBUGELR, "fbugelr", "fbugelr", 32,
3892     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3893   },
3894 /* fbuglr$pack $FCCi_2,$hint */
3895   {
3896     FRV_INSN_FBUGLR, "fbuglr", "fbuglr", 32,
3897     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3898   },
3899 /* fblelr$pack $FCCi_2,$hint */
3900   {
3901     FRV_INSN_FBLELR, "fblelr", "fblelr", 32,
3902     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3903   },
3904 /* fbgtlr$pack $FCCi_2,$hint */
3905   {
3906     FRV_INSN_FBGTLR, "fbgtlr", "fbgtlr", 32,
3907     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3908   },
3909 /* fbulelr$pack $FCCi_2,$hint */
3910   {
3911     FRV_INSN_FBULELR, "fbulelr", "fbulelr", 32,
3912     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3913   },
3914 /* fbulr$pack $FCCi_2,$hint */
3915   {
3916     FRV_INSN_FBULR, "fbulr", "fbulr", 32,
3917     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3918   },
3919 /* fbolr$pack $FCCi_2,$hint */
3920   {
3921     FRV_INSN_FBOLR, "fbolr", "fbolr", 32,
3922     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3923   },
3924 /* bcralr$pack $ccond$hint_taken */
3925   {
3926     FRV_INSN_BCRALR, "bcralr", "bcralr", 32,
3927     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3928   },
3929 /* bcnolr$pack$hint_not_taken */
3930   {
3931     FRV_INSN_BCNOLR, "bcnolr", "bcnolr", 32,
3932     { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3933   },
3934 /* bceqlr$pack $ICCi_2,$ccond,$hint */
3935   {
3936     FRV_INSN_BCEQLR, "bceqlr", "bceqlr", 32,
3937     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3938   },
3939 /* bcnelr$pack $ICCi_2,$ccond,$hint */
3940   {
3941     FRV_INSN_BCNELR, "bcnelr", "bcnelr", 32,
3942     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3943   },
3944 /* bclelr$pack $ICCi_2,$ccond,$hint */
3945   {
3946     FRV_INSN_BCLELR, "bclelr", "bclelr", 32,
3947     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3948   },
3949 /* bcgtlr$pack $ICCi_2,$ccond,$hint */
3950   {
3951     FRV_INSN_BCGTLR, "bcgtlr", "bcgtlr", 32,
3952     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3953   },
3954 /* bcltlr$pack $ICCi_2,$ccond,$hint */
3955   {
3956     FRV_INSN_BCLTLR, "bcltlr", "bcltlr", 32,
3957     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3958   },
3959 /* bcgelr$pack $ICCi_2,$ccond,$hint */
3960   {
3961     FRV_INSN_BCGELR, "bcgelr", "bcgelr", 32,
3962     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3963   },
3964 /* bclslr$pack $ICCi_2,$ccond,$hint */
3965   {
3966     FRV_INSN_BCLSLR, "bclslr", "bclslr", 32,
3967     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3968   },
3969 /* bchilr$pack $ICCi_2,$ccond,$hint */
3970   {
3971     FRV_INSN_BCHILR, "bchilr", "bchilr", 32,
3972     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3973   },
3974 /* bcclr$pack $ICCi_2,$ccond,$hint */
3975   {
3976     FRV_INSN_BCCLR, "bcclr", "bcclr", 32,
3977     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3978   },
3979 /* bcnclr$pack $ICCi_2,$ccond,$hint */
3980   {
3981     FRV_INSN_BCNCLR, "bcnclr", "bcnclr", 32,
3982     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3983   },
3984 /* bcnlr$pack $ICCi_2,$ccond,$hint */
3985   {
3986     FRV_INSN_BCNLR, "bcnlr", "bcnlr", 32,
3987     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3988   },
3989 /* bcplr$pack $ICCi_2,$ccond,$hint */
3990   {
3991     FRV_INSN_BCPLR, "bcplr", "bcplr", 32,
3992     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3993   },
3994 /* bcvlr$pack $ICCi_2,$ccond,$hint */
3995   {
3996     FRV_INSN_BCVLR, "bcvlr", "bcvlr", 32,
3997     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3998   },
3999 /* bcnvlr$pack $ICCi_2,$ccond,$hint */
4000   {
4001     FRV_INSN_BCNVLR, "bcnvlr", "bcnvlr", 32,
4002     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4003   },
4004 /* fcbralr$pack $ccond$hint_taken */
4005   {
4006     FRV_INSN_FCBRALR, "fcbralr", "fcbralr", 32,
4007     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4008   },
4009 /* fcbnolr$pack$hint_not_taken */
4010   {
4011     FRV_INSN_FCBNOLR, "fcbnolr", "fcbnolr", 32,
4012     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4013   },
4014 /* fcbeqlr$pack $FCCi_2,$ccond,$hint */
4015   {
4016     FRV_INSN_FCBEQLR, "fcbeqlr", "fcbeqlr", 32,
4017     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4018   },
4019 /* fcbnelr$pack $FCCi_2,$ccond,$hint */
4020   {
4021     FRV_INSN_FCBNELR, "fcbnelr", "fcbnelr", 32,
4022     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4023   },
4024 /* fcblglr$pack $FCCi_2,$ccond,$hint */
4025   {
4026     FRV_INSN_FCBLGLR, "fcblglr", "fcblglr", 32,
4027     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4028   },
4029 /* fcbuelr$pack $FCCi_2,$ccond,$hint */
4030   {
4031     FRV_INSN_FCBUELR, "fcbuelr", "fcbuelr", 32,
4032     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4033   },
4034 /* fcbullr$pack $FCCi_2,$ccond,$hint */
4035   {
4036     FRV_INSN_FCBULLR, "fcbullr", "fcbullr", 32,
4037     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4038   },
4039 /* fcbgelr$pack $FCCi_2,$ccond,$hint */
4040   {
4041     FRV_INSN_FCBGELR, "fcbgelr", "fcbgelr", 32,
4042     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4043   },
4044 /* fcbltlr$pack $FCCi_2,$ccond,$hint */
4045   {
4046     FRV_INSN_FCBLTLR, "fcbltlr", "fcbltlr", 32,
4047     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4048   },
4049 /* fcbugelr$pack $FCCi_2,$ccond,$hint */
4050   {
4051     FRV_INSN_FCBUGELR, "fcbugelr", "fcbugelr", 32,
4052     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4053   },
4054 /* fcbuglr$pack $FCCi_2,$ccond,$hint */
4055   {
4056     FRV_INSN_FCBUGLR, "fcbuglr", "fcbuglr", 32,
4057     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4058   },
4059 /* fcblelr$pack $FCCi_2,$ccond,$hint */
4060   {
4061     FRV_INSN_FCBLELR, "fcblelr", "fcblelr", 32,
4062     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4063   },
4064 /* fcbgtlr$pack $FCCi_2,$ccond,$hint */
4065   {
4066     FRV_INSN_FCBGTLR, "fcbgtlr", "fcbgtlr", 32,
4067     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4068   },
4069 /* fcbulelr$pack $FCCi_2,$ccond,$hint */
4070   {
4071     FRV_INSN_FCBULELR, "fcbulelr", "fcbulelr", 32,
4072     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4073   },
4074 /* fcbulr$pack $FCCi_2,$ccond,$hint */
4075   {
4076     FRV_INSN_FCBULR, "fcbulr", "fcbulr", 32,
4077     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4078   },
4079 /* fcbolr$pack $FCCi_2,$ccond,$hint */
4080   {
4081     FRV_INSN_FCBOLR, "fcbolr", "fcbolr", 32,
4082     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4083   },
4084 /* jmpl$pack @($GRi,$GRj) */
4085   {
4086     FRV_INSN_JMPL, "jmpl", "jmpl", 32,
4087     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4088   },
4089 /* calll$pack @($GRi,$GRj) */
4090   {
4091     FRV_INSN_CALLL, "calll", "calll", 32,
4092     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4093   },
4094 /* jmpil$pack @($GRi,$s12) */
4095   {
4096     FRV_INSN_JMPIL, "jmpil", "jmpil", 32,
4097     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4098   },
4099 /* callil$pack @($GRi,$s12) */
4100   {
4101     FRV_INSN_CALLIL, "callil", "callil", 32,
4102     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4103   },
4104 /* call$pack $label24 */
4105   {
4106     FRV_INSN_CALL, "call", "call", 32,
4107     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR500_MAJOR_B_4 } }
4108   },
4109 /* rett$pack $debug */
4110   {
4111     FRV_INSN_RETT, "rett", "rett", 32,
4112     { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4113   },
4114 /* rei$pack $eir */
4115   {
4116     FRV_INSN_REI, "rei", "rei", 32,
4117     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_1 } }
4118   },
4119 /* tra$pack $GRi,$GRj */
4120   {
4121     FRV_INSN_TRA, "tra", "tra", 32,
4122     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4123   },
4124 /* tno$pack */
4125   {
4126     FRV_INSN_TNO, "tno", "tno", 32,
4127     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4128   },
4129 /* teq$pack $ICCi_2,$GRi,$GRj */
4130   {
4131     FRV_INSN_TEQ, "teq", "teq", 32,
4132     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4133   },
4134 /* tne$pack $ICCi_2,$GRi,$GRj */
4135   {
4136     FRV_INSN_TNE, "tne", "tne", 32,
4137     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4138   },
4139 /* tle$pack $ICCi_2,$GRi,$GRj */
4140   {
4141     FRV_INSN_TLE, "tle", "tle", 32,
4142     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4143   },
4144 /* tgt$pack $ICCi_2,$GRi,$GRj */
4145   {
4146     FRV_INSN_TGT, "tgt", "tgt", 32,
4147     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4148   },
4149 /* tlt$pack $ICCi_2,$GRi,$GRj */
4150   {
4151     FRV_INSN_TLT, "tlt", "tlt", 32,
4152     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4153   },
4154 /* tge$pack $ICCi_2,$GRi,$GRj */
4155   {
4156     FRV_INSN_TGE, "tge", "tge", 32,
4157     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4158   },
4159 /* tls$pack $ICCi_2,$GRi,$GRj */
4160   {
4161     FRV_INSN_TLS, "tls", "tls", 32,
4162     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4163   },
4164 /* thi$pack $ICCi_2,$GRi,$GRj */
4165   {
4166     FRV_INSN_THI, "thi", "thi", 32,
4167     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4168   },
4169 /* tc$pack $ICCi_2,$GRi,$GRj */
4170   {
4171     FRV_INSN_TC, "tc", "tc", 32,
4172     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4173   },
4174 /* tnc$pack $ICCi_2,$GRi,$GRj */
4175   {
4176     FRV_INSN_TNC, "tnc", "tnc", 32,
4177     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4178   },
4179 /* tn$pack $ICCi_2,$GRi,$GRj */
4180   {
4181     FRV_INSN_TN, "tn", "tn", 32,
4182     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4183   },
4184 /* tp$pack $ICCi_2,$GRi,$GRj */
4185   {
4186     FRV_INSN_TP, "tp", "tp", 32,
4187     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4188   },
4189 /* tv$pack $ICCi_2,$GRi,$GRj */
4190   {
4191     FRV_INSN_TV, "tv", "tv", 32,
4192     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4193   },
4194 /* tnv$pack $ICCi_2,$GRi,$GRj */
4195   {
4196     FRV_INSN_TNV, "tnv", "tnv", 32,
4197     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4198   },
4199 /* ftra$pack $GRi,$GRj */
4200   {
4201     FRV_INSN_FTRA, "ftra", "ftra", 32,
4202     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4203   },
4204 /* ftno$pack */
4205   {
4206     FRV_INSN_FTNO, "ftno", "ftno", 32,
4207     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4208   },
4209 /* ftne$pack $FCCi_2,$GRi,$GRj */
4210   {
4211     FRV_INSN_FTNE, "ftne", "ftne", 32,
4212     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4213   },
4214 /* fteq$pack $FCCi_2,$GRi,$GRj */
4215   {
4216     FRV_INSN_FTEQ, "fteq", "fteq", 32,
4217     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4218   },
4219 /* ftlg$pack $FCCi_2,$GRi,$GRj */
4220   {
4221     FRV_INSN_FTLG, "ftlg", "ftlg", 32,
4222     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4223   },
4224 /* ftue$pack $FCCi_2,$GRi,$GRj */
4225   {
4226     FRV_INSN_FTUE, "ftue", "ftue", 32,
4227     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4228   },
4229 /* ftul$pack $FCCi_2,$GRi,$GRj */
4230   {
4231     FRV_INSN_FTUL, "ftul", "ftul", 32,
4232     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4233   },
4234 /* ftge$pack $FCCi_2,$GRi,$GRj */
4235   {
4236     FRV_INSN_FTGE, "ftge", "ftge", 32,
4237     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4238   },
4239 /* ftlt$pack $FCCi_2,$GRi,$GRj */
4240   {
4241     FRV_INSN_FTLT, "ftlt", "ftlt", 32,
4242     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4243   },
4244 /* ftuge$pack $FCCi_2,$GRi,$GRj */
4245   {
4246     FRV_INSN_FTUGE, "ftuge", "ftuge", 32,
4247     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4248   },
4249 /* ftug$pack $FCCi_2,$GRi,$GRj */
4250   {
4251     FRV_INSN_FTUG, "ftug", "ftug", 32,
4252     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4253   },
4254 /* ftle$pack $FCCi_2,$GRi,$GRj */
4255   {
4256     FRV_INSN_FTLE, "ftle", "ftle", 32,
4257     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4258   },
4259 /* ftgt$pack $FCCi_2,$GRi,$GRj */
4260   {
4261     FRV_INSN_FTGT, "ftgt", "ftgt", 32,
4262     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4263   },
4264 /* ftule$pack $FCCi_2,$GRi,$GRj */
4265   {
4266     FRV_INSN_FTULE, "ftule", "ftule", 32,
4267     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4268   },
4269 /* ftu$pack $FCCi_2,$GRi,$GRj */
4270   {
4271     FRV_INSN_FTU, "ftu", "ftu", 32,
4272     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4273   },
4274 /* fto$pack $FCCi_2,$GRi,$GRj */
4275   {
4276     FRV_INSN_FTO, "fto", "fto", 32,
4277     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4278   },
4279 /* tira$pack $GRi,$s12 */
4280   {
4281     FRV_INSN_TIRA, "tira", "tira", 32,
4282     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4283   },
4284 /* tino$pack */
4285   {
4286     FRV_INSN_TINO, "tino", "tino", 32,
4287     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4288   },
4289 /* tieq$pack $ICCi_2,$GRi,$s12 */
4290   {
4291     FRV_INSN_TIEQ, "tieq", "tieq", 32,
4292     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4293   },
4294 /* tine$pack $ICCi_2,$GRi,$s12 */
4295   {
4296     FRV_INSN_TINE, "tine", "tine", 32,
4297     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4298   },
4299 /* tile$pack $ICCi_2,$GRi,$s12 */
4300   {
4301     FRV_INSN_TILE, "tile", "tile", 32,
4302     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4303   },
4304 /* tigt$pack $ICCi_2,$GRi,$s12 */
4305   {
4306     FRV_INSN_TIGT, "tigt", "tigt", 32,
4307     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4308   },
4309 /* tilt$pack $ICCi_2,$GRi,$s12 */
4310   {
4311     FRV_INSN_TILT, "tilt", "tilt", 32,
4312     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4313   },
4314 /* tige$pack $ICCi_2,$GRi,$s12 */
4315   {
4316     FRV_INSN_TIGE, "tige", "tige", 32,
4317     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4318   },
4319 /* tils$pack $ICCi_2,$GRi,$s12 */
4320   {
4321     FRV_INSN_TILS, "tils", "tils", 32,
4322     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4323   },
4324 /* tihi$pack $ICCi_2,$GRi,$s12 */
4325   {
4326     FRV_INSN_TIHI, "tihi", "tihi", 32,
4327     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4328   },
4329 /* tic$pack $ICCi_2,$GRi,$s12 */
4330   {
4331     FRV_INSN_TIC, "tic", "tic", 32,
4332     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4333   },
4334 /* tinc$pack $ICCi_2,$GRi,$s12 */
4335   {
4336     FRV_INSN_TINC, "tinc", "tinc", 32,
4337     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4338   },
4339 /* tin$pack $ICCi_2,$GRi,$s12 */
4340   {
4341     FRV_INSN_TIN, "tin", "tin", 32,
4342     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4343   },
4344 /* tip$pack $ICCi_2,$GRi,$s12 */
4345   {
4346     FRV_INSN_TIP, "tip", "tip", 32,
4347     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4348   },
4349 /* tiv$pack $ICCi_2,$GRi,$s12 */
4350   {
4351     FRV_INSN_TIV, "tiv", "tiv", 32,
4352     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4353   },
4354 /* tinv$pack $ICCi_2,$GRi,$s12 */
4355   {
4356     FRV_INSN_TINV, "tinv", "tinv", 32,
4357     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4358   },
4359 /* ftira$pack $GRi,$s12 */
4360   {
4361     FRV_INSN_FTIRA, "ftira", "ftira", 32,
4362     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4363   },
4364 /* ftino$pack */
4365   {
4366     FRV_INSN_FTINO, "ftino", "ftino", 32,
4367     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4368   },
4369 /* ftine$pack $FCCi_2,$GRi,$s12 */
4370   {
4371     FRV_INSN_FTINE, "ftine", "ftine", 32,
4372     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4373   },
4374 /* ftieq$pack $FCCi_2,$GRi,$s12 */
4375   {
4376     FRV_INSN_FTIEQ, "ftieq", "ftieq", 32,
4377     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4378   },
4379 /* ftilg$pack $FCCi_2,$GRi,$s12 */
4380   {
4381     FRV_INSN_FTILG, "ftilg", "ftilg", 32,
4382     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4383   },
4384 /* ftiue$pack $FCCi_2,$GRi,$s12 */
4385   {
4386     FRV_INSN_FTIUE, "ftiue", "ftiue", 32,
4387     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4388   },
4389 /* ftiul$pack $FCCi_2,$GRi,$s12 */
4390   {
4391     FRV_INSN_FTIUL, "ftiul", "ftiul", 32,
4392     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4393   },
4394 /* ftige$pack $FCCi_2,$GRi,$s12 */
4395   {
4396     FRV_INSN_FTIGE, "ftige", "ftige", 32,
4397     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4398   },
4399 /* ftilt$pack $FCCi_2,$GRi,$s12 */
4400   {
4401     FRV_INSN_FTILT, "ftilt", "ftilt", 32,
4402     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4403   },
4404 /* ftiuge$pack $FCCi_2,$GRi,$s12 */
4405   {
4406     FRV_INSN_FTIUGE, "ftiuge", "ftiuge", 32,
4407     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4408   },
4409 /* ftiug$pack $FCCi_2,$GRi,$s12 */
4410   {
4411     FRV_INSN_FTIUG, "ftiug", "ftiug", 32,
4412     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4413   },
4414 /* ftile$pack $FCCi_2,$GRi,$s12 */
4415   {
4416     FRV_INSN_FTILE, "ftile", "ftile", 32,
4417     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4418   },
4419 /* ftigt$pack $FCCi_2,$GRi,$s12 */
4420   {
4421     FRV_INSN_FTIGT, "ftigt", "ftigt", 32,
4422     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4423   },
4424 /* ftiule$pack $FCCi_2,$GRi,$s12 */
4425   {
4426     FRV_INSN_FTIULE, "ftiule", "ftiule", 32,
4427     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4428   },
4429 /* ftiu$pack $FCCi_2,$GRi,$s12 */
4430   {
4431     FRV_INSN_FTIU, "ftiu", "ftiu", 32,
4432     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4433   },
4434 /* ftio$pack $FCCi_2,$GRi,$s12 */
4435   {
4436     FRV_INSN_FTIO, "ftio", "ftio", 32,
4437     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4438   },
4439 /* break$pack */
4440   {
4441     FRV_INSN_BREAK, "break", "break", 32,
4442     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4443   },
4444 /* mtrap$pack */
4445   {
4446     FRV_INSN_MTRAP, "mtrap", "mtrap", 32,
4447     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4448   },
4449 /* andcr$pack $CRi,$CRj,$CRk */
4450   {
4451     FRV_INSN_ANDCR, "andcr", "andcr", 32,
4452     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4453   },
4454 /* orcr$pack $CRi,$CRj,$CRk */
4455   {
4456     FRV_INSN_ORCR, "orcr", "orcr", 32,
4457     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4458   },
4459 /* xorcr$pack $CRi,$CRj,$CRk */
4460   {
4461     FRV_INSN_XORCR, "xorcr", "xorcr", 32,
4462     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4463   },
4464 /* nandcr$pack $CRi,$CRj,$CRk */
4465   {
4466     FRV_INSN_NANDCR, "nandcr", "nandcr", 32,
4467     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4468   },
4469 /* norcr$pack $CRi,$CRj,$CRk */
4470   {
4471     FRV_INSN_NORCR, "norcr", "norcr", 32,
4472     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4473   },
4474 /* andncr$pack $CRi,$CRj,$CRk */
4475   {
4476     FRV_INSN_ANDNCR, "andncr", "andncr", 32,
4477     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4478   },
4479 /* orncr$pack $CRi,$CRj,$CRk */
4480   {
4481     FRV_INSN_ORNCR, "orncr", "orncr", 32,
4482     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4483   },
4484 /* nandncr$pack $CRi,$CRj,$CRk */
4485   {
4486     FRV_INSN_NANDNCR, "nandncr", "nandncr", 32,
4487     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4488   },
4489 /* norncr$pack $CRi,$CRj,$CRk */
4490   {
4491     FRV_INSN_NORNCR, "norncr", "norncr", 32,
4492     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4493   },
4494 /* notcr$pack $CRj,$CRk */
4495   {
4496     FRV_INSN_NOTCR, "notcr", "notcr", 32,
4497     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4498   },
4499 /* ckra$pack $CRj_int */
4500   {
4501     FRV_INSN_CKRA, "ckra", "ckra", 32,
4502     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4503   },
4504 /* ckno$pack $CRj_int */
4505   {
4506     FRV_INSN_CKNO, "ckno", "ckno", 32,
4507     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4508   },
4509 /* ckeq$pack $ICCi_3,$CRj_int */
4510   {
4511     FRV_INSN_CKEQ, "ckeq", "ckeq", 32,
4512     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4513   },
4514 /* ckne$pack $ICCi_3,$CRj_int */
4515   {
4516     FRV_INSN_CKNE, "ckne", "ckne", 32,
4517     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4518   },
4519 /* ckle$pack $ICCi_3,$CRj_int */
4520   {
4521     FRV_INSN_CKLE, "ckle", "ckle", 32,
4522     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4523   },
4524 /* ckgt$pack $ICCi_3,$CRj_int */
4525   {
4526     FRV_INSN_CKGT, "ckgt", "ckgt", 32,
4527     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4528   },
4529 /* cklt$pack $ICCi_3,$CRj_int */
4530   {
4531     FRV_INSN_CKLT, "cklt", "cklt", 32,
4532     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4533   },
4534 /* ckge$pack $ICCi_3,$CRj_int */
4535   {
4536     FRV_INSN_CKGE, "ckge", "ckge", 32,
4537     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4538   },
4539 /* ckls$pack $ICCi_3,$CRj_int */
4540   {
4541     FRV_INSN_CKLS, "ckls", "ckls", 32,
4542     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4543   },
4544 /* ckhi$pack $ICCi_3,$CRj_int */
4545   {
4546     FRV_INSN_CKHI, "ckhi", "ckhi", 32,
4547     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4548   },
4549 /* ckc$pack $ICCi_3,$CRj_int */
4550   {
4551     FRV_INSN_CKC, "ckc", "ckc", 32,
4552     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4553   },
4554 /* cknc$pack $ICCi_3,$CRj_int */
4555   {
4556     FRV_INSN_CKNC, "cknc", "cknc", 32,
4557     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4558   },
4559 /* ckn$pack $ICCi_3,$CRj_int */
4560   {
4561     FRV_INSN_CKN, "ckn", "ckn", 32,
4562     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4563   },
4564 /* ckp$pack $ICCi_3,$CRj_int */
4565   {
4566     FRV_INSN_CKP, "ckp", "ckp", 32,
4567     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4568   },
4569 /* ckv$pack $ICCi_3,$CRj_int */
4570   {
4571     FRV_INSN_CKV, "ckv", "ckv", 32,
4572     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4573   },
4574 /* cknv$pack $ICCi_3,$CRj_int */
4575   {
4576     FRV_INSN_CKNV, "cknv", "cknv", 32,
4577     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4578   },
4579 /* fckra$pack $CRj_float */
4580   {
4581     FRV_INSN_FCKRA, "fckra", "fckra", 32,
4582     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4583   },
4584 /* fckno$pack $CRj_float */
4585   {
4586     FRV_INSN_FCKNO, "fckno", "fckno", 32,
4587     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4588   },
4589 /* fckne$pack $FCCi_3,$CRj_float */
4590   {
4591     FRV_INSN_FCKNE, "fckne", "fckne", 32,
4592     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4593   },
4594 /* fckeq$pack $FCCi_3,$CRj_float */
4595   {
4596     FRV_INSN_FCKEQ, "fckeq", "fckeq", 32,
4597     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4598   },
4599 /* fcklg$pack $FCCi_3,$CRj_float */
4600   {
4601     FRV_INSN_FCKLG, "fcklg", "fcklg", 32,
4602     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4603   },
4604 /* fckue$pack $FCCi_3,$CRj_float */
4605   {
4606     FRV_INSN_FCKUE, "fckue", "fckue", 32,
4607     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4608   },
4609 /* fckul$pack $FCCi_3,$CRj_float */
4610   {
4611     FRV_INSN_FCKUL, "fckul", "fckul", 32,
4612     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4613   },
4614 /* fckge$pack $FCCi_3,$CRj_float */
4615   {
4616     FRV_INSN_FCKGE, "fckge", "fckge", 32,
4617     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4618   },
4619 /* fcklt$pack $FCCi_3,$CRj_float */
4620   {
4621     FRV_INSN_FCKLT, "fcklt", "fcklt", 32,
4622     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4623   },
4624 /* fckuge$pack $FCCi_3,$CRj_float */
4625   {
4626     FRV_INSN_FCKUGE, "fckuge", "fckuge", 32,
4627     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4628   },
4629 /* fckug$pack $FCCi_3,$CRj_float */
4630   {
4631     FRV_INSN_FCKUG, "fckug", "fckug", 32,
4632     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4633   },
4634 /* fckle$pack $FCCi_3,$CRj_float */
4635   {
4636     FRV_INSN_FCKLE, "fckle", "fckle", 32,
4637     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4638   },
4639 /* fckgt$pack $FCCi_3,$CRj_float */
4640   {
4641     FRV_INSN_FCKGT, "fckgt", "fckgt", 32,
4642     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4643   },
4644 /* fckule$pack $FCCi_3,$CRj_float */
4645   {
4646     FRV_INSN_FCKULE, "fckule", "fckule", 32,
4647     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4648   },
4649 /* fcku$pack $FCCi_3,$CRj_float */
4650   {
4651     FRV_INSN_FCKU, "fcku", "fcku", 32,
4652     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4653   },
4654 /* fcko$pack $FCCi_3,$CRj_float */
4655   {
4656     FRV_INSN_FCKO, "fcko", "fcko", 32,
4657     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4658   },
4659 /* cckra$pack $CRj_int,$CCi,$cond */
4660   {
4661     FRV_INSN_CCKRA, "cckra", "cckra", 32,
4662     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4663   },
4664 /* cckno$pack $CRj_int,$CCi,$cond */
4665   {
4666     FRV_INSN_CCKNO, "cckno", "cckno", 32,
4667     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4668   },
4669 /* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */
4670   {
4671     FRV_INSN_CCKEQ, "cckeq", "cckeq", 32,
4672     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4673   },
4674 /* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */
4675   {
4676     FRV_INSN_CCKNE, "cckne", "cckne", 32,
4677     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4678   },
4679 /* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */
4680   {
4681     FRV_INSN_CCKLE, "cckle", "cckle", 32,
4682     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4683   },
4684 /* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */
4685   {
4686     FRV_INSN_CCKGT, "cckgt", "cckgt", 32,
4687     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4688   },
4689 /* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */
4690   {
4691     FRV_INSN_CCKLT, "ccklt", "ccklt", 32,
4692     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4693   },
4694 /* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */
4695   {
4696     FRV_INSN_CCKGE, "cckge", "cckge", 32,
4697     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4698   },
4699 /* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */
4700   {
4701     FRV_INSN_CCKLS, "cckls", "cckls", 32,
4702     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4703   },
4704 /* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */
4705   {
4706     FRV_INSN_CCKHI, "cckhi", "cckhi", 32,
4707     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4708   },
4709 /* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */
4710   {
4711     FRV_INSN_CCKC, "cckc", "cckc", 32,
4712     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4713   },
4714 /* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */
4715   {
4716     FRV_INSN_CCKNC, "ccknc", "ccknc", 32,
4717     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4718   },
4719 /* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */
4720   {
4721     FRV_INSN_CCKN, "cckn", "cckn", 32,
4722     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4723   },
4724 /* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */
4725   {
4726     FRV_INSN_CCKP, "cckp", "cckp", 32,
4727     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4728   },
4729 /* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */
4730   {
4731     FRV_INSN_CCKV, "cckv", "cckv", 32,
4732     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4733   },
4734 /* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */
4735   {
4736     FRV_INSN_CCKNV, "ccknv", "ccknv", 32,
4737     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4738   },
4739 /* cfckra$pack $CRj_float,$CCi,$cond */
4740   {
4741     FRV_INSN_CFCKRA, "cfckra", "cfckra", 32,
4742     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4743   },
4744 /* cfckno$pack $CRj_float,$CCi,$cond */
4745   {
4746     FRV_INSN_CFCKNO, "cfckno", "cfckno", 32,
4747     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4748   },
4749 /* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */
4750   {
4751     FRV_INSN_CFCKNE, "cfckne", "cfckne", 32,
4752     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4753   },
4754 /* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */
4755   {
4756     FRV_INSN_CFCKEQ, "cfckeq", "cfckeq", 32,
4757     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4758   },
4759 /* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */
4760   {
4761     FRV_INSN_CFCKLG, "cfcklg", "cfcklg", 32,
4762     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4763   },
4764 /* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */
4765   {
4766     FRV_INSN_CFCKUE, "cfckue", "cfckue", 32,
4767     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4768   },
4769 /* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */
4770   {
4771     FRV_INSN_CFCKUL, "cfckul", "cfckul", 32,
4772     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4773   },
4774 /* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */
4775   {
4776     FRV_INSN_CFCKGE, "cfckge", "cfckge", 32,
4777     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4778   },
4779 /* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */
4780   {
4781     FRV_INSN_CFCKLT, "cfcklt", "cfcklt", 32,
4782     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4783   },
4784 /* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */
4785   {
4786     FRV_INSN_CFCKUGE, "cfckuge", "cfckuge", 32,
4787     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4788   },
4789 /* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */
4790   {
4791     FRV_INSN_CFCKUG, "cfckug", "cfckug", 32,
4792     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4793   },
4794 /* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */
4795   {
4796     FRV_INSN_CFCKLE, "cfckle", "cfckle", 32,
4797     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4798   },
4799 /* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */
4800   {
4801     FRV_INSN_CFCKGT, "cfckgt", "cfckgt", 32,
4802     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4803   },
4804 /* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */
4805   {
4806     FRV_INSN_CFCKULE, "cfckule", "cfckule", 32,
4807     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4808   },
4809 /* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */
4810   {
4811     FRV_INSN_CFCKU, "cfcku", "cfcku", 32,
4812     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4813   },
4814 /* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */
4815   {
4816     FRV_INSN_CFCKO, "cfcko", "cfcko", 32,
4817     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4818   },
4819 /* cjmpl$pack @($GRi,$GRj),$CCi,$cond */
4820   {
4821     FRV_INSN_CJMPL, "cjmpl", "cjmpl", 32,
4822     { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4823   },
4824 /* ccalll$pack @($GRi,$GRj),$CCi,$cond */
4825   {
4826     FRV_INSN_CCALLL, "ccalll", "ccalll", 32,
4827     { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4828   },
4829 /* ici$pack @($GRi,$GRj) */
4830   {
4831     FRV_INSN_ICI, "ici", "ici", 32,
4832     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4833   },
4834 /* dci$pack @($GRi,$GRj) */
4835   {
4836     FRV_INSN_DCI, "dci", "dci", 32,
4837     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4838   },
4839 /* icei$pack @($GRi,$GRj),$ae */
4840   {
4841     FRV_INSN_ICEI, "icei", "icei", 32,
4842     { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
4843   },
4844 /* dcei$pack @($GRi,$GRj),$ae */
4845   {
4846     FRV_INSN_DCEI, "dcei", "dcei", 32,
4847     { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
4848   },
4849 /* dcf$pack @($GRi,$GRj) */
4850   {
4851     FRV_INSN_DCF, "dcf", "dcf", 32,
4852     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4853   },
4854 /* dcef$pack @($GRi,$GRj),$ae */
4855   {
4856     FRV_INSN_DCEF, "dcef", "dcef", 32,
4857     { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
4858   },
4859 /* witlb$pack $GRk,@($GRi,$GRj) */
4860   {
4861     FRV_INSN_WITLB, "witlb", "witlb", 32,
4862     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4863   },
4864 /* wdtlb$pack $GRk,@($GRi,$GRj) */
4865   {
4866     FRV_INSN_WDTLB, "wdtlb", "wdtlb", 32,
4867     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4868   },
4869 /* itlbi$pack @($GRi,$GRj) */
4870   {
4871     FRV_INSN_ITLBI, "itlbi", "itlbi", 32,
4872     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4873   },
4874 /* dtlbi$pack @($GRi,$GRj) */
4875   {
4876     FRV_INSN_DTLBI, "dtlbi", "dtlbi", 32,
4877     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4878   },
4879 /* icpl$pack $GRi,$GRj,$lock */
4880   {
4881     FRV_INSN_ICPL, "icpl", "icpl", 32,
4882     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4883   },
4884 /* dcpl$pack $GRi,$GRj,$lock */
4885   {
4886     FRV_INSN_DCPL, "dcpl", "dcpl", 32,
4887     { 0, { (1<<MACH_BASE), UNIT_DCPL, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4888   },
4889 /* icul$pack $GRi */
4890   {
4891     FRV_INSN_ICUL, "icul", "icul", 32,
4892     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4893   },
4894 /* dcul$pack $GRi */
4895   {
4896     FRV_INSN_DCUL, "dcul", "dcul", 32,
4897     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4898   },
4899 /* bar$pack */
4900   {
4901     FRV_INSN_BAR, "bar", "bar", 32,
4902     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4903   },
4904 /* membar$pack */
4905   {
4906     FRV_INSN_MEMBAR, "membar", "membar", 32,
4907     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4908   },
4909 /* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
4910   {
4911     FRV_INSN_COP1, "cop1", "cop1", 32,
4912     { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4913   },
4914 /* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */
4915   {
4916     FRV_INSN_COP2, "cop2", "cop2", 32,
4917     { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4918   },
4919 /* clrgr$pack $GRk */
4920   {
4921     FRV_INSN_CLRGR, "clrgr", "clrgr", 32,
4922     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4923   },
4924 /* clrfr$pack $FRk */
4925   {
4926     FRV_INSN_CLRFR, "clrfr", "clrfr", 32,
4927     { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4928   },
4929 /* clrga$pack */
4930   {
4931     FRV_INSN_CLRGA, "clrga", "clrga", 32,
4932     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4933   },
4934 /* clrfa$pack */
4935   {
4936     FRV_INSN_CLRFA, "clrfa", "clrfa", 32,
4937     { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4938   },
4939 /* commitgr$pack $GRk */
4940   {
4941     FRV_INSN_COMMITGR, "commitgr", "commitgr", 32,
4942     { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4943   },
4944 /* commitfr$pack $FRk */
4945   {
4946     FRV_INSN_COMMITFR, "commitfr", "commitfr", 32,
4947     { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4948   },
4949 /* commitga$pack */
4950   {
4951     FRV_INSN_COMMITGA, "commitga", "commitga", 32,
4952     { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4953   },
4954 /* commitfa$pack */
4955   {
4956     FRV_INSN_COMMITFA, "commitfa", "commitfa", 32,
4957     { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4958   },
4959 /* fitos$pack $FRintj,$FRk */
4960   {
4961     FRV_INSN_FITOS, "fitos", "fitos", 32,
4962     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4963   },
4964 /* fstoi$pack $FRj,$FRintk */
4965   {
4966     FRV_INSN_FSTOI, "fstoi", "fstoi", 32,
4967     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4968   },
4969 /* fitod$pack $FRintj,$FRdoublek */
4970   {
4971     FRV_INSN_FITOD, "fitod", "fitod", 32,
4972     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4973   },
4974 /* fdtoi$pack $FRdoublej,$FRintk */
4975   {
4976     FRV_INSN_FDTOI, "fdtoi", "fdtoi", 32,
4977     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4978   },
4979 /* fditos$pack $FRintj,$FRk */
4980   {
4981     FRV_INSN_FDITOS, "fditos", "fditos", 32,
4982     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4983   },
4984 /* fdstoi$pack $FRj,$FRintk */
4985   {
4986     FRV_INSN_FDSTOI, "fdstoi", "fdstoi", 32,
4987     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4988   },
4989 /* nfditos$pack $FRintj,$FRk */
4990   {
4991     FRV_INSN_NFDITOS, "nfditos", "nfditos", 32,
4992     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4993   },
4994 /* nfdstoi$pack $FRj,$FRintk */
4995   {
4996     FRV_INSN_NFDSTOI, "nfdstoi", "nfdstoi", 32,
4997     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4998   },
4999 /* cfitos$pack $FRintj,$FRk,$CCi,$cond */
5000   {
5001     FRV_INSN_CFITOS, "cfitos", "cfitos", 32,
5002     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5003   },
5004 /* cfstoi$pack $FRj,$FRintk,$CCi,$cond */
5005   {
5006     FRV_INSN_CFSTOI, "cfstoi", "cfstoi", 32,
5007     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5008   },
5009 /* nfitos$pack $FRintj,$FRk */
5010   {
5011     FRV_INSN_NFITOS, "nfitos", "nfitos", 32,
5012     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5013   },
5014 /* nfstoi$pack $FRj,$FRintk */
5015   {
5016     FRV_INSN_NFSTOI, "nfstoi", "nfstoi", 32,
5017     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5018   },
5019 /* fmovs$pack $FRj,$FRk */
5020   {
5021     FRV_INSN_FMOVS, "fmovs", "fmovs", 32,
5022     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5023   },
5024 /* fmovd$pack $FRdoublej,$FRdoublek */
5025   {
5026     FRV_INSN_FMOVD, "fmovd", "fmovd", 32,
5027     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5028   },
5029 /* fdmovs$pack $FRj,$FRk */
5030   {
5031     FRV_INSN_FDMOVS, "fdmovs", "fdmovs", 32,
5032     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5033   },
5034 /* cfmovs$pack $FRj,$FRk,$CCi,$cond */
5035   {
5036     FRV_INSN_CFMOVS, "cfmovs", "cfmovs", 32,
5037     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5038   },
5039 /* fnegs$pack $FRj,$FRk */
5040   {
5041     FRV_INSN_FNEGS, "fnegs", "fnegs", 32,
5042     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5043   },
5044 /* fnegd$pack $FRdoublej,$FRdoublek */
5045   {
5046     FRV_INSN_FNEGD, "fnegd", "fnegd", 32,
5047     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5048   },
5049 /* fdnegs$pack $FRj,$FRk */
5050   {
5051     FRV_INSN_FDNEGS, "fdnegs", "fdnegs", 32,
5052     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5053   },
5054 /* cfnegs$pack $FRj,$FRk,$CCi,$cond */
5055   {
5056     FRV_INSN_CFNEGS, "cfnegs", "cfnegs", 32,
5057     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5058   },
5059 /* fabss$pack $FRj,$FRk */
5060   {
5061     FRV_INSN_FABSS, "fabss", "fabss", 32,
5062     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5063   },
5064 /* fabsd$pack $FRdoublej,$FRdoublek */
5065   {
5066     FRV_INSN_FABSD, "fabsd", "fabsd", 32,
5067     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5068   },
5069 /* fdabss$pack $FRj,$FRk */
5070   {
5071     FRV_INSN_FDABSS, "fdabss", "fdabss", 32,
5072     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5073   },
5074 /* cfabss$pack $FRj,$FRk,$CCi,$cond */
5075   {
5076     FRV_INSN_CFABSS, "cfabss", "cfabss", 32,
5077     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5078   },
5079 /* fsqrts$pack $FRj,$FRk */
5080   {
5081     FRV_INSN_FSQRTS, "fsqrts", "fsqrts", 32,
5082     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5083   },
5084 /* fdsqrts$pack $FRj,$FRk */
5085   {
5086     FRV_INSN_FDSQRTS, "fdsqrts", "fdsqrts", 32,
5087     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5088   },
5089 /* nfdsqrts$pack $FRj,$FRk */
5090   {
5091     FRV_INSN_NFDSQRTS, "nfdsqrts", "nfdsqrts", 32,
5092     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5093   },
5094 /* fsqrtd$pack $FRdoublej,$FRdoublek */
5095   {
5096     FRV_INSN_FSQRTD, "fsqrtd", "fsqrtd", 32,
5097     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5098   },
5099 /* cfsqrts$pack $FRj,$FRk,$CCi,$cond */
5100   {
5101     FRV_INSN_CFSQRTS, "cfsqrts", "cfsqrts", 32,
5102     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5103   },
5104 /* nfsqrts$pack $FRj,$FRk */
5105   {
5106     FRV_INSN_NFSQRTS, "nfsqrts", "nfsqrts", 32,
5107     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5108   },
5109 /* fadds$pack $FRi,$FRj,$FRk */
5110   {
5111     FRV_INSN_FADDS, "fadds", "fadds", 32,
5112     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5113   },
5114 /* fsubs$pack $FRi,$FRj,$FRk */
5115   {
5116     FRV_INSN_FSUBS, "fsubs", "fsubs", 32,
5117     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5118   },
5119 /* fmuls$pack $FRi,$FRj,$FRk */
5120   {
5121     FRV_INSN_FMULS, "fmuls", "fmuls", 32,
5122     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5123   },
5124 /* fdivs$pack $FRi,$FRj,$FRk */
5125   {
5126     FRV_INSN_FDIVS, "fdivs", "fdivs", 32,
5127     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5128   },
5129 /* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5130   {
5131     FRV_INSN_FADDD, "faddd", "faddd", 32,
5132     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5133   },
5134 /* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5135   {
5136     FRV_INSN_FSUBD, "fsubd", "fsubd", 32,
5137     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5138   },
5139 /* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */
5140   {
5141     FRV_INSN_FMULD, "fmuld", "fmuld", 32,
5142     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5143   },
5144 /* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5145   {
5146     FRV_INSN_FDIVD, "fdivd", "fdivd", 32,
5147     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5148   },
5149 /* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
5150   {
5151     FRV_INSN_CFADDS, "cfadds", "cfadds", 32,
5152     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5153   },
5154 /* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5155   {
5156     FRV_INSN_CFSUBS, "cfsubs", "cfsubs", 32,
5157     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5158   },
5159 /* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */
5160   {
5161     FRV_INSN_CFMULS, "cfmuls", "cfmuls", 32,
5162     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5163   },
5164 /* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5165   {
5166     FRV_INSN_CFDIVS, "cfdivs", "cfdivs", 32,
5167     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5168   },
5169 /* nfadds$pack $FRi,$FRj,$FRk */
5170   {
5171     FRV_INSN_NFADDS, "nfadds", "nfadds", 32,
5172     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5173   },
5174 /* nfsubs$pack $FRi,$FRj,$FRk */
5175   {
5176     FRV_INSN_NFSUBS, "nfsubs", "nfsubs", 32,
5177     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5178   },
5179 /* nfmuls$pack $FRi,$FRj,$FRk */
5180   {
5181     FRV_INSN_NFMULS, "nfmuls", "nfmuls", 32,
5182     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5183   },
5184 /* nfdivs$pack $FRi,$FRj,$FRk */
5185   {
5186     FRV_INSN_NFDIVS, "nfdivs", "nfdivs", 32,
5187     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5188   },
5189 /* fcmps$pack $FRi,$FRj,$FCCi_2 */
5190   {
5191     FRV_INSN_FCMPS, "fcmps", "fcmps", 32,
5192     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5193   },
5194 /* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */
5195   {
5196     FRV_INSN_FCMPD, "fcmpd", "fcmpd", 32,
5197     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5198   },
5199 /* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */
5200   {
5201     FRV_INSN_CFCMPS, "cfcmps", "cfcmps", 32,
5202     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5203   },
5204 /* fdcmps$pack $FRi,$FRj,$FCCi_2 */
5205   {
5206     FRV_INSN_FDCMPS, "fdcmps", "fdcmps", 32,
5207     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5208   },
5209 /* fmadds$pack $FRi,$FRj,$FRk */
5210   {
5211     FRV_INSN_FMADDS, "fmadds", "fmadds", 32,
5212     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5213   },
5214 /* fmsubs$pack $FRi,$FRj,$FRk */
5215   {
5216     FRV_INSN_FMSUBS, "fmsubs", "fmsubs", 32,
5217     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5218   },
5219 /* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5220   {
5221     FRV_INSN_FMADDD, "fmaddd", "fmaddd", 32,
5222     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5223   },
5224 /* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5225   {
5226     FRV_INSN_FMSUBD, "fmsubd", "fmsubd", 32,
5227     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5228   },
5229 /* fdmadds$pack $FRi,$FRj,$FRk */
5230   {
5231     FRV_INSN_FDMADDS, "fdmadds", "fdmadds", 32,
5232     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5233   },
5234 /* nfdmadds$pack $FRi,$FRj,$FRk */
5235   {
5236     FRV_INSN_NFDMADDS, "nfdmadds", "nfdmadds", 32,
5237     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5238   },
5239 /* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
5240   {
5241     FRV_INSN_CFMADDS, "cfmadds", "cfmadds", 32,
5242     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5243   },
5244 /* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5245   {
5246     FRV_INSN_CFMSUBS, "cfmsubs", "cfmsubs", 32,
5247     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5248   },
5249 /* nfmadds$pack $FRi,$FRj,$FRk */
5250   {
5251     FRV_INSN_NFMADDS, "nfmadds", "nfmadds", 32,
5252     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5253   },
5254 /* nfmsubs$pack $FRi,$FRj,$FRk */
5255   {
5256     FRV_INSN_NFMSUBS, "nfmsubs", "nfmsubs", 32,
5257     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5258   },
5259 /* fmas$pack $FRi,$FRj,$FRk */
5260   {
5261     FRV_INSN_FMAS, "fmas", "fmas", 32,
5262     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5263   },
5264 /* fmss$pack $FRi,$FRj,$FRk */
5265   {
5266     FRV_INSN_FMSS, "fmss", "fmss", 32,
5267     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5268   },
5269 /* fdmas$pack $FRi,$FRj,$FRk */
5270   {
5271     FRV_INSN_FDMAS, "fdmas", "fdmas", 32,
5272     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5273   },
5274 /* fdmss$pack $FRi,$FRj,$FRk */
5275   {
5276     FRV_INSN_FDMSS, "fdmss", "fdmss", 32,
5277     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5278   },
5279 /* nfdmas$pack $FRi,$FRj,$FRk */
5280   {
5281     FRV_INSN_NFDMAS, "nfdmas", "nfdmas", 32,
5282     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5283   },
5284 /* nfdmss$pack $FRi,$FRj,$FRk */
5285   {
5286     FRV_INSN_NFDMSS, "nfdmss", "nfdmss", 32,
5287     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5288   },
5289 /* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */
5290   {
5291     FRV_INSN_CFMAS, "cfmas", "cfmas", 32,
5292     { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5293   },
5294 /* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */
5295   {
5296     FRV_INSN_CFMSS, "cfmss", "cfmss", 32,
5297     { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5298   },
5299 /* fmad$pack $FRi,$FRj,$FRk */
5300   {
5301     FRV_INSN_FMAD, "fmad", "fmad", 32,
5302     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5303   },
5304 /* fmsd$pack $FRi,$FRj,$FRk */
5305   {
5306     FRV_INSN_FMSD, "fmsd", "fmsd", 32,
5307     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5308   },
5309 /* nfmas$pack $FRi,$FRj,$FRk */
5310   {
5311     FRV_INSN_NFMAS, "nfmas", "nfmas", 32,
5312     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5313   },
5314 /* nfmss$pack $FRi,$FRj,$FRk */
5315   {
5316     FRV_INSN_NFMSS, "nfmss", "nfmss", 32,
5317     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5318   },
5319 /* fdadds$pack $FRi,$FRj,$FRk */
5320   {
5321     FRV_INSN_FDADDS, "fdadds", "fdadds", 32,
5322     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5323   },
5324 /* fdsubs$pack $FRi,$FRj,$FRk */
5325   {
5326     FRV_INSN_FDSUBS, "fdsubs", "fdsubs", 32,
5327     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5328   },
5329 /* fdmuls$pack $FRi,$FRj,$FRk */
5330   {
5331     FRV_INSN_FDMULS, "fdmuls", "fdmuls", 32,
5332     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5333   },
5334 /* fddivs$pack $FRi,$FRj,$FRk */
5335   {
5336     FRV_INSN_FDDIVS, "fddivs", "fddivs", 32,
5337     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5338   },
5339 /* fdsads$pack $FRi,$FRj,$FRk */
5340   {
5341     FRV_INSN_FDSADS, "fdsads", "fdsads", 32,
5342     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5343   },
5344 /* fdmulcs$pack $FRi,$FRj,$FRk */
5345   {
5346     FRV_INSN_FDMULCS, "fdmulcs", "fdmulcs", 32,
5347     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5348   },
5349 /* nfdmulcs$pack $FRi,$FRj,$FRk */
5350   {
5351     FRV_INSN_NFDMULCS, "nfdmulcs", "nfdmulcs", 32,
5352     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5353   },
5354 /* nfdadds$pack $FRi,$FRj,$FRk */
5355   {
5356     FRV_INSN_NFDADDS, "nfdadds", "nfdadds", 32,
5357     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5358   },
5359 /* nfdsubs$pack $FRi,$FRj,$FRk */
5360   {
5361     FRV_INSN_NFDSUBS, "nfdsubs", "nfdsubs", 32,
5362     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5363   },
5364 /* nfdmuls$pack $FRi,$FRj,$FRk */
5365   {
5366     FRV_INSN_NFDMULS, "nfdmuls", "nfdmuls", 32,
5367     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5368   },
5369 /* nfddivs$pack $FRi,$FRj,$FRk */
5370   {
5371     FRV_INSN_NFDDIVS, "nfddivs", "nfddivs", 32,
5372     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5373   },
5374 /* nfdsads$pack $FRi,$FRj,$FRk */
5375   {
5376     FRV_INSN_NFDSADS, "nfdsads", "nfdsads", 32,
5377     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5378   },
5379 /* nfdcmps$pack $FRi,$FRj,$FCCi_2 */
5380   {
5381     FRV_INSN_NFDCMPS, "nfdcmps", "nfdcmps", 32,
5382     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5383   },
5384 /* mhsetlos$pack $u12,$FRklo */
5385   {
5386     FRV_INSN_MHSETLOS, "mhsetlos", "mhsetlos", 32,
5387     { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5388   },
5389 /* mhsethis$pack $u12,$FRkhi */
5390   {
5391     FRV_INSN_MHSETHIS, "mhsethis", "mhsethis", 32,
5392     { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5393   },
5394 /* mhdsets$pack $u12,$FRintk */
5395   {
5396     FRV_INSN_MHDSETS, "mhdsets", "mhdsets", 32,
5397     { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5398   },
5399 /* mhsetloh$pack $s5,$FRklo */
5400   {
5401     FRV_INSN_MHSETLOH, "mhsetloh", "mhsetloh", 32,
5402     { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5403   },
5404 /* mhsethih$pack $s5,$FRkhi */
5405   {
5406     FRV_INSN_MHSETHIH, "mhsethih", "mhsethih", 32,
5407     { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5408   },
5409 /* mhdseth$pack $s5,$FRintk */
5410   {
5411     FRV_INSN_MHDSETH, "mhdseth", "mhdseth", 32,
5412     { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5413   },
5414 /* mand$pack $FRinti,$FRintj,$FRintk */
5415   {
5416     FRV_INSN_MAND, "mand", "mand", 32,
5417     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5418   },
5419 /* mor$pack $FRinti,$FRintj,$FRintk */
5420   {
5421     FRV_INSN_MOR, "mor", "mor", 32,
5422     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5423   },
5424 /* mxor$pack $FRinti,$FRintj,$FRintk */
5425   {
5426     FRV_INSN_MXOR, "mxor", "mxor", 32,
5427     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5428   },
5429 /* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5430   {
5431     FRV_INSN_CMAND, "cmand", "cmand", 32,
5432     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5433   },
5434 /* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5435   {
5436     FRV_INSN_CMOR, "cmor", "cmor", 32,
5437     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5438   },
5439 /* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5440   {
5441     FRV_INSN_CMXOR, "cmxor", "cmxor", 32,
5442     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5443   },
5444 /* mnot$pack $FRintj,$FRintk */
5445   {
5446     FRV_INSN_MNOT, "mnot", "mnot", 32,
5447     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5448   },
5449 /* cmnot$pack $FRintj,$FRintk,$CCi,$cond */
5450   {
5451     FRV_INSN_CMNOT, "cmnot", "cmnot", 32,
5452     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5453   },
5454 /* mrotli$pack $FRinti,$u6,$FRintk */
5455   {
5456     FRV_INSN_MROTLI, "mrotli", "mrotli", 32,
5457     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5458   },
5459 /* mrotri$pack $FRinti,$u6,$FRintk */
5460   {
5461     FRV_INSN_MROTRI, "mrotri", "mrotri", 32,
5462     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5463   },
5464 /* mwcut$pack $FRinti,$FRintj,$FRintk */
5465   {
5466     FRV_INSN_MWCUT, "mwcut", "mwcut", 32,
5467     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5468   },
5469 /* mwcuti$pack $FRinti,$u6,$FRintk */
5470   {
5471     FRV_INSN_MWCUTI, "mwcuti", "mwcuti", 32,
5472     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5473   },
5474 /* mcut$pack $ACC40Si,$FRintj,$FRintk */
5475   {
5476     FRV_INSN_MCUT, "mcut", "mcut", 32,
5477     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5478   },
5479 /* mcuti$pack $ACC40Si,$s6,$FRintk */
5480   {
5481     FRV_INSN_MCUTI, "mcuti", "mcuti", 32,
5482     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5483   },
5484 /* mcutss$pack $ACC40Si,$FRintj,$FRintk */
5485   {
5486     FRV_INSN_MCUTSS, "mcutss", "mcutss", 32,
5487     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5488   },
5489 /* mcutssi$pack $ACC40Si,$s6,$FRintk */
5490   {
5491     FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32,
5492     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5493   },
5494 /* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */
5495   {
5496     FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32,
5497     { 0, { (1<<MACH_FR400), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5498   },
5499 /* maveh$pack $FRinti,$FRintj,$FRintk */
5500   {
5501     FRV_INSN_MAVEH, "maveh", "maveh", 32,
5502     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5503   },
5504 /* msllhi$pack $FRinti,$u6,$FRintk */
5505   {
5506     FRV_INSN_MSLLHI, "msllhi", "msllhi", 32,
5507     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5508   },
5509 /* msrlhi$pack $FRinti,$u6,$FRintk */
5510   {
5511     FRV_INSN_MSRLHI, "msrlhi", "msrlhi", 32,
5512     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5513   },
5514 /* msrahi$pack $FRinti,$u6,$FRintk */
5515   {
5516     FRV_INSN_MSRAHI, "msrahi", "msrahi", 32,
5517     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5518   },
5519 /* mdrotli$pack $FRintieven,$s6,$FRintkeven */
5520   {
5521     FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32,
5522     { 0, { (1<<MACH_FR400), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5523   },
5524 /* mcplhi$pack $FRinti,$u6,$FRintk */
5525   {
5526     FRV_INSN_MCPLHI, "mcplhi", "mcplhi", 32,
5527     { 0, { (1<<MACH_FR400), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5528   },
5529 /* mcpli$pack $FRinti,$u6,$FRintk */
5530   {
5531     FRV_INSN_MCPLI, "mcpli", "mcpli", 32,
5532     { 0, { (1<<MACH_FR400), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5533   },
5534 /* msaths$pack $FRinti,$FRintj,$FRintk */
5535   {
5536     FRV_INSN_MSATHS, "msaths", "msaths", 32,
5537     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5538   },
5539 /* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */
5540   {
5541     FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32,
5542     { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5543   },
5544 /* msathu$pack $FRinti,$FRintj,$FRintk */
5545   {
5546     FRV_INSN_MSATHU, "msathu", "msathu", 32,
5547     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5548   },
5549 /* mcmpsh$pack $FRinti,$FRintj,$FCCk */
5550   {
5551     FRV_INSN_MCMPSH, "mcmpsh", "mcmpsh", 32,
5552     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5553   },
5554 /* mcmpuh$pack $FRinti,$FRintj,$FCCk */
5555   {
5556     FRV_INSN_MCMPUH, "mcmpuh", "mcmpuh", 32,
5557     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5558   },
5559 /* mabshs$pack $FRintj,$FRintk */
5560   {
5561     FRV_INSN_MABSHS, "mabshs", "mabshs", 32,
5562     { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5563   },
5564 /* maddhss$pack $FRinti,$FRintj,$FRintk */
5565   {
5566     FRV_INSN_MADDHSS, "maddhss", "maddhss", 32,
5567     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5568   },
5569 /* maddhus$pack $FRinti,$FRintj,$FRintk */
5570   {
5571     FRV_INSN_MADDHUS, "maddhus", "maddhus", 32,
5572     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5573   },
5574 /* msubhss$pack $FRinti,$FRintj,$FRintk */
5575   {
5576     FRV_INSN_MSUBHSS, "msubhss", "msubhss", 32,
5577     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5578   },
5579 /* msubhus$pack $FRinti,$FRintj,$FRintk */
5580   {
5581     FRV_INSN_MSUBHUS, "msubhus", "msubhus", 32,
5582     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5583   },
5584 /* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5585   {
5586     FRV_INSN_CMADDHSS, "cmaddhss", "cmaddhss", 32,
5587     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5588   },
5589 /* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5590   {
5591     FRV_INSN_CMADDHUS, "cmaddhus", "cmaddhus", 32,
5592     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5593   },
5594 /* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5595   {
5596     FRV_INSN_CMSUBHSS, "cmsubhss", "cmsubhss", 32,
5597     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5598   },
5599 /* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5600   {
5601     FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32,
5602     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5603   },
5604 /* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */
5605   {
5606     FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32,
5607     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5608   },
5609 /* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */
5610   {
5611     FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32,
5612     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5613   },
5614 /* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */
5615   {
5616     FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32,
5617     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5618   },
5619 /* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */
5620   {
5621     FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32,
5622     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5623   },
5624 /* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
5625   {
5626     FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32,
5627     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5628   },
5629 /* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
5630   {
5631     FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32,
5632     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5633   },
5634 /* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
5635   {
5636     FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32,
5637     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5638   },
5639 /* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
5640   {
5641     FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32,
5642     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5643   },
5644 /* maddaccs$pack $ACC40Si,$ACC40Sk */
5645   {
5646     FRV_INSN_MADDACCS, "maddaccs", "maddaccs", 32,
5647     { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5648   },
5649 /* msubaccs$pack $ACC40Si,$ACC40Sk */
5650   {
5651     FRV_INSN_MSUBACCS, "msubaccs", "msubaccs", 32,
5652     { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5653   },
5654 /* mdaddaccs$pack $ACC40Si,$ACC40Sk */
5655   {
5656     FRV_INSN_MDADDACCS, "mdaddaccs", "mdaddaccs", 32,
5657     { 0, { (1<<MACH_FR400), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5658   },
5659 /* mdsubaccs$pack $ACC40Si,$ACC40Sk */
5660   {
5661     FRV_INSN_MDSUBACCS, "mdsubaccs", "mdsubaccs", 32,
5662     { 0, { (1<<MACH_FR400), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5663   },
5664 /* masaccs$pack $ACC40Si,$ACC40Sk */
5665   {
5666     FRV_INSN_MASACCS, "masaccs", "masaccs", 32,
5667     { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5668   },
5669 /* mdasaccs$pack $ACC40Si,$ACC40Sk */
5670   {
5671     FRV_INSN_MDASACCS, "mdasaccs", "mdasaccs", 32,
5672     { 0, { (1<<MACH_FR400), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5673   },
5674 /* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */
5675   {
5676     FRV_INSN_MMULHS, "mmulhs", "mmulhs", 32,
5677     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5678   },
5679 /* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */
5680   {
5681     FRV_INSN_MMULHU, "mmulhu", "mmulhu", 32,
5682     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5683   },
5684 /* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
5685   {
5686     FRV_INSN_MMULXHS, "mmulxhs", "mmulxhs", 32,
5687     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5688   },
5689 /* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
5690   {
5691     FRV_INSN_MMULXHU, "mmulxhu", "mmulxhu", 32,
5692     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5693   },
5694 /* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5695   {
5696     FRV_INSN_CMMULHS, "cmmulhs", "cmmulhs", 32,
5697     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5698   },
5699 /* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5700   {
5701     FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32,
5702     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5703   },
5704 /* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5705   {
5706     FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32,
5707     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5708   },
5709 /* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
5710   {
5711     FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32,
5712     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5713   },
5714 /* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5715   {
5716     FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32,
5717     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5718   },
5719 /* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
5720   {
5721     FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32,
5722     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5723   },
5724 /* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
5725   {
5726     FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32,
5727     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5728   },
5729 /* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
5730   {
5731     FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32,
5732     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5733   },
5734 /* mmachs$pack $FRinti,$FRintj,$ACC40Sk */
5735   {
5736     FRV_INSN_MMACHS, "mmachs", "mmachs", 32,
5737     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5738   },
5739 /* mmachu$pack $FRinti,$FRintj,$ACC40Uk */
5740   {
5741     FRV_INSN_MMACHU, "mmachu", "mmachu", 32,
5742     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5743   },
5744 /* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */
5745   {
5746     FRV_INSN_MMRDHS, "mmrdhs", "mmrdhs", 32,
5747     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5748   },
5749 /* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */
5750   {
5751     FRV_INSN_MMRDHU, "mmrdhu", "mmrdhu", 32,
5752     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5753   },
5754 /* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5755   {
5756     FRV_INSN_CMMACHS, "cmmachs", "cmmachs", 32,
5757     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5758   },
5759 /* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
5760   {
5761     FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32,
5762     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5763   },
5764 /* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5765   {
5766     FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32,
5767     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5768   },
5769 /* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */
5770   {
5771     FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32,
5772     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5773   },
5774 /* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
5775   {
5776     FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32,
5777     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5778   },
5779 /* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */
5780   {
5781     FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32,
5782     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5783   },
5784 /* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5785   {
5786     FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32,
5787     { 0, { (1<<MACH_FR400), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5788   },
5789 /* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5790   {
5791     FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32,
5792     { 0, { (1<<MACH_FR400), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5793   },
5794 /* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5795   {
5796     FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32,
5797     { 0, { (1<<MACH_FR400), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5798   },
5799 /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
5800   {
5801     FRV_INSN_MCPXRS, "mcpxrs", "mcpxrs", 32,
5802     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5803   },
5804 /* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */
5805   {
5806     FRV_INSN_MCPXRU, "mcpxru", "mcpxru", 32,
5807     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5808   },
5809 /* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */
5810   {
5811     FRV_INSN_MCPXIS, "mcpxis", "mcpxis", 32,
5812     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5813   },
5814 /* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
5815   {
5816     FRV_INSN_MCPXIU, "mcpxiu", "mcpxiu", 32,
5817     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5818   },
5819 /* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5820   {
5821     FRV_INSN_CMCPXRS, "cmcpxrs", "cmcpxrs", 32,
5822     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5823   },
5824 /* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5825   {
5826     FRV_INSN_CMCPXRU, "cmcpxru", "cmcpxru", 32,
5827     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5828   },
5829 /* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5830   {
5831     FRV_INSN_CMCPXIS, "cmcpxis", "cmcpxis", 32,
5832     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5833   },
5834 /* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5835   {
5836     FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32,
5837     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5838   },
5839 /* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5840   {
5841     FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32,
5842     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5843   },
5844 /* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */
5845   {
5846     FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32,
5847     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5848   },
5849 /* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */
5850   {
5851     FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32,
5852     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5853   },
5854 /* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */
5855   {
5856     FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32,
5857     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5858   },
5859 /* mexpdhw$pack $FRinti,$u6,$FRintk */
5860   {
5861     FRV_INSN_MEXPDHW, "mexpdhw", "mexpdhw", 32,
5862     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5863   },
5864 /* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */
5865   {
5866     FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32,
5867     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5868   },
5869 /* mexpdhd$pack $FRinti,$u6,$FRintkeven */
5870   {
5871     FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32,
5872     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5873   },
5874 /* cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */
5875   {
5876     FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32,
5877     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5878   },
5879 /* mpackh$pack $FRinti,$FRintj,$FRintk */
5880   {
5881     FRV_INSN_MPACKH, "mpackh", "mpackh", 32,
5882     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5883   },
5884 /* mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */
5885   {
5886     FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32,
5887     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_5 } }
5888   },
5889 /* munpackh$pack $FRinti,$FRintkeven */
5890   {
5891     FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32,
5892     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5893   },
5894 /* mdunpackh$pack $FRintieven,$FRintk */
5895   {
5896     FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32,
5897     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
5898   },
5899 /* mbtoh$pack $FRintj,$FRintkeven */
5900   {
5901     FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32,
5902     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5903   },
5904 /* cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */
5905   {
5906     FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32,
5907     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5908   },
5909 /* mhtob$pack $FRintjeven,$FRintk */
5910   {
5911     FRV_INSN_MHTOB, "mhtob", "mhtob", 32,
5912     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5913   },
5914 /* cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */
5915   {
5916     FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32,
5917     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5918   },
5919 /* mbtohe$pack $FRintj,$FRintk */
5920   {
5921     FRV_INSN_MBTOHE, "mbtohe", "mbtohe", 32,
5922     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
5923   },
5924 /* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */
5925   {
5926     FRV_INSN_CMBTOHE, "cmbtohe", "cmbtohe", 32,
5927     { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
5928   },
5929 /* mnop$pack */
5930   {
5931     FRV_INSN_MNOP, "mnop", "mnop", 32,
5932     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5933   },
5934 /* mclracc$pack $ACC40Sk,$A0 */
5935   {
5936     FRV_INSN_MCLRACC_0, "mclracc-0", "mclracc", 32,
5937     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
5938   },
5939 /* mclracc$pack $ACC40Sk,$A1 */
5940   {
5941     FRV_INSN_MCLRACC_1, "mclracc-1", "mclracc", 32,
5942     { 0, { (1<<MACH_BASE), UNIT_MCLRACC_1, FR400_MAJOR_M_2, FR500_MAJOR_M_6 } }
5943   },
5944 /* mrdacc$pack $ACC40Si,$FRintk */
5945   {
5946     FRV_INSN_MRDACC, "mrdacc", "mrdacc", 32,
5947     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5948   },
5949 /* mrdaccg$pack $ACCGi,$FRintk */
5950   {
5951     FRV_INSN_MRDACCG, "mrdaccg", "mrdaccg", 32,
5952     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5953   },
5954 /* mwtacc$pack $FRinti,$ACC40Sk */
5955   {
5956     FRV_INSN_MWTACC, "mwtacc", "mwtacc", 32,
5957     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
5958   },
5959 /* mwtaccg$pack $FRinti,$ACCGk */
5960   {
5961     FRV_INSN_MWTACCG, "mwtaccg", "mwtaccg", 32,
5962     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
5963   },
5964 /* mcop1$pack $FRi,$FRj,$FRk */
5965   {
5966     FRV_INSN_MCOP1, "mcop1", "mcop1", 32,
5967     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } }
5968   },
5969 /* mcop2$pack $FRi,$FRj,$FRk */
5970   {
5971     FRV_INSN_MCOP2, "mcop2", "mcop2", 32,
5972     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } }
5973   },
5974 /* fnop$pack */
5975   {
5976     FRV_INSN_FNOP, "fnop", "fnop", 32,
5977     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_8 } }
5978   },
5979 };
5980
5981 #undef OP
5982 #undef A
5983
5984 /* Initialize anything needed to be done once, before any cpu_open call.  */
5985 static void init_tables PARAMS ((void));
5986
5987 static void
5988 init_tables ()
5989 {
5990 }
5991
5992 static const CGEN_MACH * lookup_mach_via_bfd_name
5993   PARAMS ((const CGEN_MACH *, const char *));
5994 static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
5995 static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
5996 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
5997 static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
5998 static void frv_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
5999
6000 /* Subroutine of frv_cgen_cpu_open to look up a mach via its bfd name.  */
6001
6002 static const CGEN_MACH *
6003 lookup_mach_via_bfd_name (table, name)
6004      const CGEN_MACH *table;
6005      const char *name;
6006 {
6007   while (table->name)
6008     {
6009       if (strcmp (name, table->bfd_name) == 0)
6010         return table;
6011       ++table;
6012     }
6013   abort ();
6014 }
6015
6016 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
6017
6018 static void
6019 build_hw_table (cd)
6020      CGEN_CPU_TABLE *cd;
6021 {
6022   int i;
6023   int machs = cd->machs;
6024   const CGEN_HW_ENTRY *init = & frv_cgen_hw_table[0];
6025   /* MAX_HW is only an upper bound on the number of selected entries.
6026      However each entry is indexed by it's enum so there can be holes in
6027      the table.  */
6028   const CGEN_HW_ENTRY **selected =
6029     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
6030
6031   cd->hw_table.init_entries = init;
6032   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
6033   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
6034   /* ??? For now we just use machs to determine which ones we want.  */
6035   for (i = 0; init[i].name != NULL; ++i)
6036     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
6037         & machs)
6038       selected[init[i].type] = &init[i];
6039   cd->hw_table.entries = selected;
6040   cd->hw_table.num_entries = MAX_HW;
6041 }
6042
6043 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
6044
6045 static void
6046 build_ifield_table (cd)
6047      CGEN_CPU_TABLE *cd;
6048 {
6049   cd->ifld_table = & frv_cgen_ifld_table[0];
6050 }
6051
6052 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
6053
6054 static void
6055 build_operand_table (cd)
6056      CGEN_CPU_TABLE *cd;
6057 {
6058   int i;
6059   int machs = cd->machs;
6060   const CGEN_OPERAND *init = & frv_cgen_operand_table[0];
6061   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
6062      However each entry is indexed by it's enum so there can be holes in
6063      the table.  */
6064   const CGEN_OPERAND **selected =
6065     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
6066
6067   cd->operand_table.init_entries = init;
6068   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
6069   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
6070   /* ??? For now we just use mach to determine which ones we want.  */
6071   for (i = 0; init[i].name != NULL; ++i)
6072     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
6073         & machs)
6074       selected[init[i].type] = &init[i];
6075   cd->operand_table.entries = selected;
6076   cd->operand_table.num_entries = MAX_OPERANDS;
6077 }
6078
6079 /* Subroutine of frv_cgen_cpu_open to build the hardware table.
6080    ??? This could leave out insns not supported by the specified mach/isa,
6081    but that would cause errors like "foo only supported by bar" to become
6082    "unknown insn", so for now we include all insns and require the app to
6083    do the checking later.
6084    ??? On the other hand, parsing of such insns may require their hardware or
6085    operand elements to be in the table [which they mightn't be].  */
6086
6087 static void
6088 build_insn_table (cd)
6089      CGEN_CPU_TABLE *cd;
6090 {
6091   int i;
6092   const CGEN_IBASE *ib = & frv_cgen_insn_table[0];
6093   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
6094
6095   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
6096   for (i = 0; i < MAX_INSNS; ++i)
6097     insns[i].base = &ib[i];
6098   cd->insn_table.init_entries = insns;
6099   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
6100   cd->insn_table.num_init_entries = MAX_INSNS;
6101 }
6102
6103 /* Subroutine of frv_cgen_cpu_open to rebuild the tables.  */
6104
6105 static void
6106 frv_cgen_rebuild_tables (cd)
6107      CGEN_CPU_TABLE *cd;
6108 {
6109   int i;
6110   unsigned int isas = cd->isas;
6111   unsigned int machs = cd->machs;
6112
6113   cd->int_insn_p = CGEN_INT_INSN_P;
6114
6115   /* Data derived from the isa spec.  */
6116 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
6117   cd->default_insn_bitsize = UNSET;
6118   cd->base_insn_bitsize = UNSET;
6119   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
6120   cd->max_insn_bitsize = 0;
6121   for (i = 0; i < MAX_ISAS; ++i)
6122     if (((1 << i) & isas) != 0)
6123       {
6124         const CGEN_ISA *isa = & frv_cgen_isa_table[i];
6125
6126         /* Default insn sizes of all selected isas must be
6127            equal or we set the result to 0, meaning "unknown".  */
6128         if (cd->default_insn_bitsize == UNSET)
6129           cd->default_insn_bitsize = isa->default_insn_bitsize;
6130         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
6131           ; /* this is ok */
6132         else
6133           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
6134
6135         /* Base insn sizes of all selected isas must be equal
6136            or we set the result to 0, meaning "unknown".  */
6137         if (cd->base_insn_bitsize == UNSET)
6138           cd->base_insn_bitsize = isa->base_insn_bitsize;
6139         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
6140           ; /* this is ok */
6141         else
6142           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
6143
6144         /* Set min,max insn sizes.  */
6145         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
6146           cd->min_insn_bitsize = isa->min_insn_bitsize;
6147         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
6148           cd->max_insn_bitsize = isa->max_insn_bitsize;
6149       }
6150
6151   /* Data derived from the mach spec.  */
6152   for (i = 0; i < MAX_MACHS; ++i)
6153     if (((1 << i) & machs) != 0)
6154       {
6155         const CGEN_MACH *mach = & frv_cgen_mach_table[i];
6156
6157         if (mach->insn_chunk_bitsize != 0)
6158         {
6159           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
6160             {
6161               fprintf (stderr, "frv_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
6162                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
6163               abort ();
6164             }
6165
6166           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
6167         }
6168       }
6169
6170   /* Determine which hw elements are used by MACH.  */
6171   build_hw_table (cd);
6172
6173   /* Build the ifield table.  */
6174   build_ifield_table (cd);
6175
6176   /* Determine which operands are used by MACH/ISA.  */
6177   build_operand_table (cd);
6178
6179   /* Build the instruction table.  */
6180   build_insn_table (cd);
6181 }
6182
6183 /* Initialize a cpu table and return a descriptor.
6184    It's much like opening a file, and must be the first function called.
6185    The arguments are a set of (type/value) pairs, terminated with
6186    CGEN_CPU_OPEN_END.
6187
6188    Currently supported values:
6189    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
6190    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
6191    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
6192    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
6193    CGEN_CPU_OPEN_END:     terminates arguments
6194
6195    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
6196    precluded.
6197
6198    ??? We only support ISO C stdargs here, not K&R.
6199    Laziness, plus experiment to see if anything requires K&R - eventually
6200    K&R will no longer be supported - e.g. GDB is currently trying this.  */
6201
6202 CGEN_CPU_DESC
6203 frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
6204 {
6205   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
6206   static int init_p;
6207   unsigned int isas = 0;  /* 0 = "unspecified" */
6208   unsigned int machs = 0; /* 0 = "unspecified" */
6209   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
6210   va_list ap;
6211
6212   if (! init_p)
6213     {
6214       init_tables ();
6215       init_p = 1;
6216     }
6217
6218   memset (cd, 0, sizeof (*cd));
6219
6220   va_start (ap, arg_type);
6221   while (arg_type != CGEN_CPU_OPEN_END)
6222     {
6223       switch (arg_type)
6224         {
6225         case CGEN_CPU_OPEN_ISAS :
6226           isas = va_arg (ap, unsigned int);
6227           break;
6228         case CGEN_CPU_OPEN_MACHS :
6229           machs = va_arg (ap, unsigned int);
6230           break;
6231         case CGEN_CPU_OPEN_BFDMACH :
6232           {
6233             const char *name = va_arg (ap, const char *);
6234             const CGEN_MACH *mach =
6235               lookup_mach_via_bfd_name (frv_cgen_mach_table, name);
6236
6237             machs |= 1 << mach->num;
6238             break;
6239           }
6240         case CGEN_CPU_OPEN_ENDIAN :
6241           endian = va_arg (ap, enum cgen_endian);
6242           break;
6243         default :
6244           fprintf (stderr, "frv_cgen_cpu_open: unsupported argument `%d'\n",
6245                    arg_type);
6246           abort (); /* ??? return NULL? */
6247         }
6248       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
6249     }
6250   va_end (ap);
6251
6252   /* mach unspecified means "all" */
6253   if (machs == 0)
6254     machs = (1 << MAX_MACHS) - 1;
6255   /* base mach is always selected */
6256   machs |= 1;
6257   /* isa unspecified means "all" */
6258   if (isas == 0)
6259     isas = (1 << MAX_ISAS) - 1;
6260   if (endian == CGEN_ENDIAN_UNKNOWN)
6261     {
6262       /* ??? If target has only one, could have a default.  */
6263       fprintf (stderr, "frv_cgen_cpu_open: no endianness specified\n");
6264       abort ();
6265     }
6266
6267   cd->isas = isas;
6268   cd->machs = machs;
6269   cd->endian = endian;
6270   /* FIXME: for the sparc case we can determine insn-endianness statically.
6271      The worry here is where both data and insn endian can be independently
6272      chosen, in which case this function will need another argument.
6273      Actually, will want to allow for more arguments in the future anyway.  */
6274   cd->insn_endian = endian;
6275
6276   /* Table (re)builder.  */
6277   cd->rebuild_tables = frv_cgen_rebuild_tables;
6278   frv_cgen_rebuild_tables (cd);
6279
6280   /* Default to not allowing signed overflow.  */
6281   cd->signed_overflow_ok_p = 0;
6282
6283   return (CGEN_CPU_DESC) cd;
6284 }
6285
6286 /* Cover fn to frv_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
6287    MACH_NAME is the bfd name of the mach.  */
6288
6289 CGEN_CPU_DESC
6290 frv_cgen_cpu_open_1 (mach_name, endian)
6291      const char *mach_name;
6292      enum cgen_endian endian;
6293 {
6294   return frv_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
6295                                CGEN_CPU_OPEN_ENDIAN, endian,
6296                                CGEN_CPU_OPEN_END);
6297 }
6298
6299 /* Close a cpu table.
6300    ??? This can live in a machine independent file, but there's currently
6301    no place to put this file (there's no libcgen).  libopcodes is the wrong
6302    place as some simulator ports use this but they don't use libopcodes.  */
6303
6304 void
6305 frv_cgen_cpu_close (cd)
6306      CGEN_CPU_DESC cd;
6307 {
6308   unsigned int i;
6309   const CGEN_INSN *insns;
6310
6311   if (cd->macro_insn_table.init_entries)
6312     {
6313       insns = cd->macro_insn_table.init_entries;
6314       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
6315         {
6316           if (CGEN_INSN_RX ((insns)))
6317             regfree (CGEN_INSN_RX (insns));
6318         }
6319     }
6320
6321   if (cd->insn_table.init_entries)
6322     {
6323       insns = cd->insn_table.init_entries;
6324       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
6325         {
6326           if (CGEN_INSN_RX (insns))
6327             regfree (CGEN_INSN_RX (insns));
6328         }
6329     }
6330
6331
6332
6333   if (cd->macro_insn_table.init_entries)
6334     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
6335
6336   if (cd->insn_table.init_entries)
6337     free ((CGEN_INSN *) cd->insn_table.init_entries);
6338
6339   if (cd->hw_table.entries)
6340     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
6341
6342   if (cd->operand_table.entries)
6343     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
6344
6345   free (cd);
6346 }
6347