opcodes/frv-dis.c

   1 /* Disassembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5 - the resultant file is machine generated, cgen-dis.in isn't
   6
   7 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
   8 Free Software Foundation, Inc.
   9
  10 This file is part of the GNU Binutils and GDB, the GNU debugger.
  11
  12 This program is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2, or (at your option)
  15 any later version.
  16
  17 This program is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with this program; if not, write to the Free Software Foundation, Inc.,
  24 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  25
  26 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  27    Keep that in mind.  */
  28
  29 #include "sysdep.h"
  30 #include <stdio.h>
  31 #include "ansidecl.h"
  32 #include "dis-asm.h"
  33 #include "bfd.h"
  34 #include "symcat.h"
  35 #include "libiberty.h"
  36 #include "frv-desc.h"
  37 #include "frv-opc.h"
  38 #include "opintl.h"
  39
  40 /* Default text to print if an instruction isn't recognized.  */
  41 #define UNKNOWN_INSN_MSG _("*unknown*")
  42
  43 static void print_normal
  44   (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
  45 static void print_address
  46   (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int);
  47 static void print_keyword
  48   (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int);
  49 static void print_insn_normal
  50   (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
  51 static int print_insn
  52   (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned);
  53 static int default_print_insn
  54   (CGEN_CPU_DESC, bfd_vma, disassemble_info *);
  55 static int read_insn
  56   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *,
  57    unsigned long *);
  58 \f
  59 /* -- disassembler routines inserted here */
  60
  61 /* -- dis.c */
  62 static void print_spr
  63   PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned));
  64 static void print_hi
  65   PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
  66 static void print_lo
  67   PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
  68
  69 static void
  70 print_spr (cd, dis_info, names, regno, attrs)
  71      CGEN_CPU_DESC cd;
  72      PTR dis_info;
  73      CGEN_KEYWORD *names;
  74      long regno;
  75      unsigned int attrs;
  76 {
  77   /* Use the register index format for any unnamed registers.  */
  78   if (cgen_keyword_lookup_value (names, regno) == NULL)
  79     {
  80       disassemble_info *info = (disassemble_info *) dis_info;
  81       (*info->fprintf_func) (info->stream, "spr[%ld]", regno);
  82     }
  83   else
  84     print_keyword (cd, dis_info, names, regno, attrs);
  85 }
  86
  87 static void
  88 print_hi (cd, dis_info, value, attrs, pc, length)
  89      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
  90      PTR dis_info;
  91      long value;
  92      unsigned int attrs ATTRIBUTE_UNUSED;
  93      bfd_vma pc ATTRIBUTE_UNUSED;
  94      int length ATTRIBUTE_UNUSED;
  95 {
  96   disassemble_info *info = (disassemble_info *) dis_info;
  97   if (value)
  98     (*info->fprintf_func) (info->stream, "0x%lx", value);
  99   else
 100     (*info->fprintf_func) (info->stream, "hi(0x%lx)", value);
 101 }
 102
 103 static void
 104 print_lo (cd, dis_info, value, attrs, pc, length)
 105      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 106      PTR dis_info;
 107      long value;
 108      unsigned int attrs ATTRIBUTE_UNUSED;
 109      bfd_vma pc ATTRIBUTE_UNUSED;
 110      int length ATTRIBUTE_UNUSED;
 111 {
 112   disassemble_info *info = (disassemble_info *) dis_info;
 113   if (value)
 114     (*info->fprintf_func) (info->stream, "0x%lx", value);
 115   else
 116     (*info->fprintf_func) (info->stream, "lo(0x%lx)", value);
 117 }
 118
 119 /* -- */
 120
 121 void frv_cgen_print_operand
 122   PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
 123            void const *, bfd_vma, int));
 124
 125 /* Main entry point for printing operands.
 126    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
 127    of dis-asm.h on cgen.h.
 128
 129    This function is basically just a big switch statement.  Earlier versions
 130    used tables to look up the function to use, but
 131    - if the table contains both assembler and disassembler functions then
 132      the disassembler contains much of the assembler and vice-versa,
 133    - there's a lot of inlining possibilities as things grow,
 134    - using a switch statement avoids the function call overhead.
 135
 136    This function could be moved into `print_insn_normal', but keeping it
 137    separate makes clear the interface between `print_insn_normal' and each of
 138    the handlers.  */
 139
 140 void
 141 frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
 142      CGEN_CPU_DESC cd;
 143      int opindex;
 144      PTR xinfo;
 145      CGEN_FIELDS *fields;
 146      void const *attrs ATTRIBUTE_UNUSED;
 147      bfd_vma pc;
 148      int length;
 149 {
 150  disassemble_info *info = (disassemble_info *) xinfo;
 151
 152   switch (opindex)
 153     {
 154     case FRV_OPERAND_A :
 155       print_normal (cd, info, fields->f_A, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 156       break;
 157     case FRV_OPERAND_ACC40SI :
 158       print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Si, 0);
 159       break;
 160     case FRV_OPERAND_ACC40SK :
 161       print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Sk, 0);
 162       break;
 163     case FRV_OPERAND_ACC40UI :
 164       print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Ui, 0);
 165       break;
 166     case FRV_OPERAND_ACC40UK :
 167       print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Uk, 0);
 168       break;
 169     case FRV_OPERAND_ACCGI :
 170       print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGi, 0);
 171       break;
 172     case FRV_OPERAND_ACCGK :
 173       print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGk, 0);
 174       break;
 175     case FRV_OPERAND_CCI :
 176       print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CCi, 0);
 177       break;
 178     case FRV_OPERAND_CPRDOUBLEK :
 179       print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0);
 180       break;
 181     case FRV_OPERAND_CPRI :
 182       print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRi, 0);
 183       break;
 184     case FRV_OPERAND_CPRJ :
 185       print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRj, 0);
 186       break;
 187     case FRV_OPERAND_CPRK :
 188       print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0);
 189       break;
 190     case FRV_OPERAND_CRI :
 191       print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRi, 0);
 192       break;
 193     case FRV_OPERAND_CRJ :
 194       print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj, 0);
 195       break;
 196     case FRV_OPERAND_CRJ_FLOAT :
 197       print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_float, 0);
 198       break;
 199     case FRV_OPERAND_CRJ_INT :
 200       print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_int, 0);
 201       break;
 202     case FRV_OPERAND_CRK :
 203       print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRk, 0);
 204       break;
 205     case FRV_OPERAND_FCCI_1 :
 206       print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_1, 0);
 207       break;
 208     case FRV_OPERAND_FCCI_2 :
 209       print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_2, 0);
 210       break;
 211     case FRV_OPERAND_FCCI_3 :
 212       print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_3, 0);
 213       break;
 214     case FRV_OPERAND_FCCK :
 215       print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCk, 0);
 216       break;
 217     case FRV_OPERAND_FRDOUBLEI :
 218       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
 219       break;
 220     case FRV_OPERAND_FRDOUBLEJ :
 221       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
 222       break;
 223     case FRV_OPERAND_FRDOUBLEK :
 224       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
 225       break;
 226     case FRV_OPERAND_FRI :
 227       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
 228       break;
 229     case FRV_OPERAND_FRINTI :
 230       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
 231       break;
 232     case FRV_OPERAND_FRINTIEVEN :
 233       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
 234       break;
 235     case FRV_OPERAND_FRINTJ :
 236       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
 237       break;
 238     case FRV_OPERAND_FRINTJEVEN :
 239       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
 240       break;
 241     case FRV_OPERAND_FRINTK :
 242       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
 243       break;
 244     case FRV_OPERAND_FRINTKEVEN :
 245       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
 246       break;
 247     case FRV_OPERAND_FRJ :
 248       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
 249       break;
 250     case FRV_OPERAND_FRK :
 251       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
 252       break;
 253     case FRV_OPERAND_FRKHI :
 254       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
 255       break;
 256     case FRV_OPERAND_FRKLO :
 257       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
 258       break;
 259     case FRV_OPERAND_GRDOUBLEK :
 260       print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
 261       break;
 262     case FRV_OPERAND_GRI :
 263       print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRi, 0);
 264       break;
 265     case FRV_OPERAND_GRJ :
 266       print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRj, 0);
 267       break;
 268     case FRV_OPERAND_GRK :
 269       print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
 270       break;
 271     case FRV_OPERAND_GRKHI :
 272       print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
 273       break;
 274     case FRV_OPERAND_GRKLO :
 275       print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
 276       break;
 277     case FRV_OPERAND_ICCI_1 :
 278       print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_1, 0);
 279       break;
 280     case FRV_OPERAND_ICCI_2 :
 281       print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_2, 0);
 282       break;
 283     case FRV_OPERAND_ICCI_3 :
 284       print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_3, 0);
 285       break;
 286     case FRV_OPERAND_LI :
 287       print_normal (cd, info, fields->f_LI, 0, pc, length);
 288       break;
 289     case FRV_OPERAND_AE :
 290       print_normal (cd, info, fields->f_ae, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 291       break;
 292     case FRV_OPERAND_CCOND :
 293       print_normal (cd, info, fields->f_ccond, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 294       break;
 295     case FRV_OPERAND_COND :
 296       print_normal (cd, info, fields->f_cond, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 297       break;
 298     case FRV_OPERAND_D12 :
 299       print_normal (cd, info, fields->f_d12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 300       break;
 301     case FRV_OPERAND_DEBUG :
 302       print_normal (cd, info, fields->f_debug, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 303       break;
 304     case FRV_OPERAND_EIR :
 305       print_normal (cd, info, fields->f_eir, 0, pc, length);
 306       break;
 307     case FRV_OPERAND_HINT :
 308       print_normal (cd, info, fields->f_hint, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 309       break;
 310     case FRV_OPERAND_HINT_NOT_TAKEN :
 311       print_keyword (cd, info, & frv_cgen_opval_h_hint_not_taken, fields->f_hint, 0);
 312       break;
 313     case FRV_OPERAND_HINT_TAKEN :
 314       print_keyword (cd, info, & frv_cgen_opval_h_hint_taken, fields->f_hint, 0);
 315       break;
 316     case FRV_OPERAND_LABEL16 :
 317       print_address (cd, info, fields->f_label16, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 318       break;
 319     case FRV_OPERAND_LABEL24 :
 320       print_address (cd, info, fields->f_label24, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
 321       break;
 322     case FRV_OPERAND_LOCK :
 323       print_normal (cd, info, fields->f_lock, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 324       break;
 325     case FRV_OPERAND_PACK :
 326       print_keyword (cd, info, & frv_cgen_opval_h_pack, fields->f_pack, 0);
 327       break;
 328     case FRV_OPERAND_S10 :
 329       print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 330       break;
 331     case FRV_OPERAND_S12 :
 332       print_normal (cd, info, fields->f_d12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 333       break;
 334     case FRV_OPERAND_S16 :
 335       print_normal (cd, info, fields->f_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 336       break;
 337     case FRV_OPERAND_S5 :
 338       print_normal (cd, info, fields->f_s5, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 339       break;
 340     case FRV_OPERAND_S6 :
 341       print_normal (cd, info, fields->f_s6, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 342       break;
 343     case FRV_OPERAND_S6_1 :
 344       print_normal (cd, info, fields->f_s6_1, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 345       break;
 346     case FRV_OPERAND_SLO16 :
 347       print_lo (cd, info, fields->f_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 348       break;
 349     case FRV_OPERAND_SPR :
 350       print_spr (cd, info, & frv_cgen_opval_spr_names, fields->f_spr, 0|(1<<CGEN_OPERAND_VIRTUAL));
 351       break;
 352     case FRV_OPERAND_U12 :
 353       print_normal (cd, info, fields->f_u12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
 354       break;
 355     case FRV_OPERAND_U16 :
 356       print_normal (cd, info, fields->f_u16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 357       break;
 358     case FRV_OPERAND_U6 :
 359       print_normal (cd, info, fields->f_u6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 360       break;
 361     case FRV_OPERAND_UHI16 :
 362       print_hi (cd, info, fields->f_u16, 0, pc, length);
 363       break;
 364     case FRV_OPERAND_ULO16 :
 365       print_lo (cd, info, fields->f_u16, 0, pc, length);
 366       break;
 367
 368     default :
 369       /* xgettext:c-format */
 370       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
 371                opindex);
 372     abort ();
 373   }
 374 }
 375
 376 cgen_print_fn * const frv_cgen_print_handlers[] =
 377 {
 378   print_insn_normal,
 379 };
 380
 381
 382 void
 383 frv_cgen_init_dis (cd)
 384      CGEN_CPU_DESC cd;
 385 {
 386   frv_cgen_init_opcode_table (cd);
 387   frv_cgen_init_ibld_table (cd);
 388   cd->print_handlers = & frv_cgen_print_handlers[0];
 389   cd->print_operand = frv_cgen_print_operand;
 390 }
 391
 392 \f
 393 /* Default print handler.  */
 394
 395 static void
 396 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 397               void *dis_info,
 398               long value,
 399               unsigned int attrs,
 400               bfd_vma pc ATTRIBUTE_UNUSED,
 401               int length ATTRIBUTE_UNUSED)
 402 {
 403   disassemble_info *info = (disassemble_info *) dis_info;
 404
 405 #ifdef CGEN_PRINT_NORMAL
 406   CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
 407 #endif
 408
 409   /* Print the operand as directed by the attributes.  */
 410   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 411     ; /* nothing to do */
 412   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 413     (*info->fprintf_func) (info->stream, "%ld", value);
 414   else
 415     (*info->fprintf_func) (info->stream, "0x%lx", value);
 416 }
 417
 418 /* Default address handler.  */
 419
 420 static void
 421 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 422                void *dis_info,
 423                bfd_vma value,
 424                unsigned int attrs,
 425                bfd_vma pc ATTRIBUTE_UNUSED,
 426                int length ATTRIBUTE_UNUSED)
 427 {
 428   disassemble_info *info = (disassemble_info *) dis_info;
 429
 430 #ifdef CGEN_PRINT_ADDRESS
 431   CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
 432 #endif
 433
 434   /* Print the operand as directed by the attributes.  */
 435   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 436     ; /* nothing to do */
 437   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
 438     (*info->print_address_func) (value, info);
 439   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
 440     (*info->print_address_func) (value, info);
 441   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 442     (*info->fprintf_func) (info->stream, "%ld", (long) value);
 443   else
 444     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
 445 }
 446
 447 /* Keyword print handler.  */
 448
 449 static void
 450 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 451                void *dis_info,
 452                CGEN_KEYWORD *keyword_table,
 453                long value,
 454                unsigned int attrs ATTRIBUTE_UNUSED)
 455 {
 456   disassemble_info *info = (disassemble_info *) dis_info;
 457   const CGEN_KEYWORD_ENTRY *ke;
 458
 459   ke = cgen_keyword_lookup_value (keyword_table, value);
 460   if (ke != NULL)
 461     (*info->fprintf_func) (info->stream, "%s", ke->name);
 462   else
 463     (*info->fprintf_func) (info->stream, "???");
 464 }
 465 \f
 466 /* Default insn printer.
 467
 468    DIS_INFO is defined as `void *' so the disassembler needn't know anything
 469    about disassemble_info.  */
 470
 471 static void
 472 print_insn_normal (CGEN_CPU_DESC cd,
 473                    void *dis_info,
 474                    const CGEN_INSN *insn,
 475                    CGEN_FIELDS *fields,
 476                    bfd_vma pc,
 477                    int length)
 478 {
 479   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 480   disassemble_info *info = (disassemble_info *) dis_info;
 481   const CGEN_SYNTAX_CHAR_TYPE *syn;
 482
 483   CGEN_INIT_PRINT (cd);
 484
 485   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 486     {
 487       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 488         {
 489           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 490           continue;
 491         }
 492       if (CGEN_SYNTAX_CHAR_P (*syn))
 493         {
 494           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 495           continue;
 496         }
 497
 498       /* We have an operand.  */
 499       frv_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
 500                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
 501     }
 502 }
 503 \f
 504 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
 505    the extract info.
 506    Returns 0 if all is well, non-zero otherwise.  */
 507
 508 static int
 509 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 510            bfd_vma pc,
 511            disassemble_info *info,
 512            char *buf,
 513            int buflen,
 514            CGEN_EXTRACT_INFO *ex_info,
 515            unsigned long *insn_value)
 516 {
 517   int status = (*info->read_memory_func) (pc, buf, buflen, info);
 518   if (status != 0)
 519     {
 520       (*info->memory_error_func) (status, pc, info);
 521       return -1;
 522     }
 523
 524   ex_info->dis_info = info;
 525   ex_info->valid = (1 << buflen) - 1;
 526   ex_info->insn_bytes = buf;
 527
 528   *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
 529   return 0;
 530 }
 531
 532 /* Utility to print an insn.
 533    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
 534    The result is the size of the insn in bytes or zero for an unknown insn
 535    or -1 if an error occurs fetching data (memory_error_func will have
 536    been called).  */
 537
 538 static int
 539 print_insn (CGEN_CPU_DESC cd,
 540             bfd_vma pc,
 541             disassemble_info *info,
 542             char *buf,
 543             unsigned int buflen)
 544 {
 545   CGEN_INSN_INT insn_value;
 546   const CGEN_INSN_LIST *insn_list;
 547   CGEN_EXTRACT_INFO ex_info;
 548   int basesize;
 549
 550   /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
 551   basesize = cd->base_insn_bitsize < buflen * 8 ?
 552                                      cd->base_insn_bitsize : buflen * 8;
 553   insn_value = cgen_get_insn_value (cd, buf, basesize);
 554
 555
 556   /* Fill in ex_info fields like read_insn would.  Don't actually call
 557      read_insn, since the incoming buffer is already read (and possibly
 558      modified a la m32r).  */
 559   ex_info.valid = (1 << buflen) - 1;
 560   ex_info.dis_info = info;
 561   ex_info.insn_bytes = buf;
 562
 563   /* The instructions are stored in hash lists.
 564      Pick the first one and keep trying until we find the right one.  */
 565
 566   insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
 567   while (insn_list != NULL)
 568     {
 569       const CGEN_INSN *insn = insn_list->insn;
 570       CGEN_FIELDS fields;
 571       int length;
 572       unsigned long insn_value_cropped;
 573
 574 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
 575       /* Not needed as insn shouldn't be in hash lists if not supported.  */
 576       /* Supported by this cpu?  */
 577       if (! frv_cgen_insn_supported (cd, insn))
 578         {
 579           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 580           continue;
 581         }
 582 #endif
 583
 584       /* Basic bit mask must be correct.  */
 585       /* ??? May wish to allow target to defer this check until the extract
 586          handler.  */
 587
 588       /* Base size may exceed this instruction's size.  Extract the
 589          relevant part from the buffer. */
 590       if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
 591           (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 592         insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
 593                                            info->endian == BFD_ENDIAN_BIG);
 594       else
 595         insn_value_cropped = insn_value;
 596
 597       if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
 598           == CGEN_INSN_BASE_VALUE (insn))
 599         {
 600           /* Printing is handled in two passes.  The first pass parses the
 601              machine insn and extracts the fields.  The second pass prints
 602              them.  */
 603
 604           /* Make sure the entire insn is loaded into insn_value, if it
 605              can fit.  */
 606           if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
 607               (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 608             {
 609               unsigned long full_insn_value;
 610               int rc = read_insn (cd, pc, info, buf,
 611                                   CGEN_INSN_BITSIZE (insn) / 8,
 612                                   & ex_info, & full_insn_value);
 613               if (rc != 0)
 614                 return rc;
 615               length = CGEN_EXTRACT_FN (cd, insn)
 616                 (cd, insn, &ex_info, full_insn_value, &fields, pc);
 617             }
 618           else
 619             length = CGEN_EXTRACT_FN (cd, insn)
 620               (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 621
 622           /* length < 0 -> error */
 623           if (length < 0)
 624             return length;
 625           if (length > 0)
 626             {
 627               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 628               /* length is in bits, result is in bytes */
 629               return length / 8;
 630             }
 631         }
 632
 633       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 634     }
 635
 636   return 0;
 637 }
 638
 639 /* Default value for CGEN_PRINT_INSN.
 640    The result is the size of the insn in bytes or zero for an unknown insn
 641    or -1 if an error occured fetching bytes.  */
 642
 643 #ifndef CGEN_PRINT_INSN
 644 #define CGEN_PRINT_INSN default_print_insn
 645 #endif
 646
 647 static int
 648 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 649 {
 650   char buf[CGEN_MAX_INSN_SIZE];
 651   int buflen;
 652   int status;
 653
 654   /* Attempt to read the base part of the insn.  */
 655   buflen = cd->base_insn_bitsize / 8;
 656   status = (*info->read_memory_func) (pc, buf, buflen, info);
 657
 658   /* Try again with the minimum part, if min < base.  */
 659   if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
 660     {
 661       buflen = cd->min_insn_bitsize / 8;
 662       status = (*info->read_memory_func) (pc, buf, buflen, info);
 663     }
 664
 665   if (status != 0)
 666     {
 667       (*info->memory_error_func) (status, pc, info);
 668       return -1;
 669     }
 670
 671   return print_insn (cd, pc, info, buf, buflen);
 672 }
 673
 674 /* Main entry point.
 675    Print one instruction from PC on INFO->STREAM.
 676    Return the size of the instruction (in bytes).  */
 677
 678 typedef struct cpu_desc_list {
 679   struct cpu_desc_list *next;
 680   int isa;
 681   int mach;
 682   int endian;
 683   CGEN_CPU_DESC cd;
 684 } cpu_desc_list;
 685
 686 int
 687 print_insn_frv (bfd_vma pc, disassemble_info *info)
 688 {
 689   static cpu_desc_list *cd_list = 0;
 690   cpu_desc_list *cl = 0;
 691   static CGEN_CPU_DESC cd = 0;
 692   static int prev_isa;
 693   static int prev_mach;
 694   static int prev_endian;
 695   int length;
 696   int isa,mach;
 697   int endian = (info->endian == BFD_ENDIAN_BIG
 698                 ? CGEN_ENDIAN_BIG
 699                 : CGEN_ENDIAN_LITTLE);
 700   enum bfd_architecture arch;
 701
 702   /* ??? gdb will set mach but leave the architecture as "unknown" */
 703 #ifndef CGEN_BFD_ARCH
 704 #define CGEN_BFD_ARCH bfd_arch_frv
 705 #endif
 706   arch = info->arch;
 707   if (arch == bfd_arch_unknown)
 708     arch = CGEN_BFD_ARCH;
 709
 710   /* There's no standard way to compute the machine or isa number
 711      so we leave it to the target.  */
 712 #ifdef CGEN_COMPUTE_MACH
 713   mach = CGEN_COMPUTE_MACH (info);
 714 #else
 715   mach = info->mach;
 716 #endif
 717
 718 #ifdef CGEN_COMPUTE_ISA
 719   isa = CGEN_COMPUTE_ISA (info);
 720 #else
 721   isa = info->insn_sets;
 722 #endif
 723
 724   /* If we've switched cpu's, try to find a handle we've used before */
 725   if (cd
 726       && (isa != prev_isa
 727           || mach != prev_mach
 728           || endian != prev_endian))
 729     {
 730       cd = 0;
 731       for (cl = cd_list; cl; cl = cl->next)
 732         {
 733           if (cl->isa == isa &&
 734               cl->mach == mach &&
 735               cl->endian == endian)
 736             {
 737               cd = cl->cd;
 738               break;
 739             }
 740         }
 741     }
 742
 743   /* If we haven't initialized yet, initialize the opcode table.  */
 744   if (! cd)
 745     {
 746       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
 747       const char *mach_name;
 748
 749       if (!arch_type)
 750         abort ();
 751       mach_name = arch_type->printable_name;
 752
 753       prev_isa = isa;
 754       prev_mach = mach;
 755       prev_endian = endian;
 756       cd = frv_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
 757                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
 758                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
 759                                  CGEN_CPU_OPEN_END);
 760       if (!cd)
 761         abort ();
 762
 763       /* save this away for future reference */
 764       cl = xmalloc (sizeof (struct cpu_desc_list));
 765       cl->cd = cd;
 766       cl->isa = isa;
 767       cl->mach = mach;
 768       cl->endian = endian;
 769       cl->next = cd_list;
 770       cd_list = cl;
 771
 772       frv_cgen_init_dis (cd);
 773     }
 774
 775   /* We try to have as much common code as possible.
 776      But at this point some targets need to take over.  */
 777   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
 778      but if not possible try to move this hook elsewhere rather than
 779      have two hooks.  */
 780   length = CGEN_PRINT_INSN (cd, pc, info);
 781   if (length > 0)
 782     return length;
 783   if (length < 0)
 784     return -1;
 785
 786   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 787   return cd->default_insn_bitsize / 8;
 788 }