3 { "vmovupX", { XM
, EXEvexXNoBcst
}, PREFIX_OPCODE
},
4 { VEX_W_TABLE (EVEX_W_0F10_P_1
) },
5 { "vmovupX", { XM
, EXEvexXNoBcst
}, PREFIX_OPCODE
},
6 { VEX_W_TABLE (EVEX_W_0F10_P_3
) },
10 { "vmovupX", { EXxS
, XM
}, PREFIX_OPCODE
},
11 { VEX_W_TABLE (EVEX_W_0F11_P_1
) },
12 { "vmovupX", { EXxS
, XM
}, PREFIX_OPCODE
},
13 { VEX_W_TABLE (EVEX_W_0F11_P_3
) },
15 /* PREFIX_EVEX_0F12 */
17 { MOD_TABLE (MOD_EVEX_0F12_PREFIX_0
) },
18 { VEX_W_TABLE (EVEX_W_0F12_P_1
) },
19 { MOD_TABLE (MOD_EVEX_0F12_PREFIX_2
) },
20 { VEX_W_TABLE (EVEX_W_0F12_P_3
) },
22 /* PREFIX_EVEX_0F16 */
24 { MOD_TABLE (MOD_EVEX_0F16_PREFIX_0
) },
25 { VEX_W_TABLE (EVEX_W_0F16_P_1
) },
26 { MOD_TABLE (MOD_EVEX_0F16_PREFIX_2
) },
28 /* PREFIX_EVEX_0F2A */
31 { "vcvtsi2ss{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
33 { VEX_W_TABLE (EVEX_W_0F2A_P_3
) },
35 /* PREFIX_EVEX_0F51 */
37 { "vsqrtpX", { XM
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
38 { VEX_W_TABLE (EVEX_W_0F51_P_1
) },
39 { "vsqrtpX", { XM
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
40 { VEX_W_TABLE (EVEX_W_0F51_P_3
) },
42 /* PREFIX_EVEX_0F58 */
44 { "vaddpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
45 { VEX_W_TABLE (EVEX_W_0F58_P_1
) },
46 { "vaddpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
47 { VEX_W_TABLE (EVEX_W_0F58_P_3
) },
49 /* PREFIX_EVEX_0F59 */
51 { "vmulpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
52 { VEX_W_TABLE (EVEX_W_0F59_P_1
) },
53 { "vmulpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
54 { VEX_W_TABLE (EVEX_W_0F59_P_3
) },
56 /* PREFIX_EVEX_0F5A */
58 { VEX_W_TABLE (EVEX_W_0F5A_P_0
) },
59 { VEX_W_TABLE (EVEX_W_0F5A_P_1
) },
60 { VEX_W_TABLE (EVEX_W_0F5A_P_2
) },
61 { VEX_W_TABLE (EVEX_W_0F5A_P_3
) },
63 /* PREFIX_EVEX_0F5B */
65 { VEX_W_TABLE (EVEX_W_0F5B_P_0
) },
66 { VEX_W_TABLE (EVEX_W_0F5B_P_1
) },
67 { VEX_W_TABLE (EVEX_W_0F5B_P_2
) },
69 /* PREFIX_EVEX_0F5C */
71 { "vsubpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
72 { VEX_W_TABLE (EVEX_W_0F5C_P_1
) },
73 { "vsubpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
74 { VEX_W_TABLE (EVEX_W_0F5C_P_3
) },
76 /* PREFIX_EVEX_0F5D */
78 { "vminpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
79 { VEX_W_TABLE (EVEX_W_0F5D_P_1
) },
80 { "vminpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
81 { VEX_W_TABLE (EVEX_W_0F5D_P_3
) },
83 /* PREFIX_EVEX_0F5E */
85 { "vdivpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
86 { VEX_W_TABLE (EVEX_W_0F5E_P_1
) },
87 { "vdivpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
88 { VEX_W_TABLE (EVEX_W_0F5E_P_3
) },
90 /* PREFIX_EVEX_0F5F */
92 { "vmaxpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
93 { VEX_W_TABLE (EVEX_W_0F5F_P_1
) },
94 { "vmaxpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
95 { VEX_W_TABLE (EVEX_W_0F5F_P_3
) },
97 /* PREFIX_EVEX_0F64 */
101 { "vpcmpgtb", { XMask
, Vex
, EXx
}, 0 },
103 /* PREFIX_EVEX_0F65 */
107 { "vpcmpgtw", { XMask
, Vex
, EXx
}, 0 },
109 /* PREFIX_EVEX_0F66 */
113 { VEX_W_TABLE (EVEX_W_0F66_P_2
) },
115 /* PREFIX_EVEX_0F6E */
119 { EVEX_LEN_TABLE (EVEX_LEN_0F6E_P_2
) },
121 /* PREFIX_EVEX_0F6F */
124 { VEX_W_TABLE (EVEX_W_0F6F_P_1
) },
125 { VEX_W_TABLE (EVEX_W_0F6F_P_2
) },
126 { VEX_W_TABLE (EVEX_W_0F6F_P_3
) },
128 /* PREFIX_EVEX_0F70 */
131 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
132 { VEX_W_TABLE (EVEX_W_0F70_P_2
) },
133 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
135 /* PREFIX_EVEX_0F71_REG_2 */
139 { "vpsrlw", { Vex
, EXx
, Ib
}, 0 },
141 /* PREFIX_EVEX_0F71_REG_4 */
145 { "vpsraw", { Vex
, EXx
, Ib
}, 0 },
147 /* PREFIX_EVEX_0F71_REG_6 */
151 { "vpsllw", { Vex
, EXx
, Ib
}, 0 },
153 /* PREFIX_EVEX_0F72_REG_0 */
157 { "vpror%DQ", { Vex
, EXx
, Ib
}, 0 },
159 /* PREFIX_EVEX_0F72_REG_1 */
163 { "vprol%DQ", { Vex
, EXx
, Ib
}, 0 },
165 /* PREFIX_EVEX_0F72_REG_2 */
169 { VEX_W_TABLE (EVEX_W_0F72_R_2_P_2
) },
171 /* PREFIX_EVEX_0F72_REG_4 */
175 { "vpsra%DQ", { Vex
, EXx
, Ib
}, 0 },
177 /* PREFIX_EVEX_0F72_REG_6 */
181 { VEX_W_TABLE (EVEX_W_0F72_R_6_P_2
) },
183 /* PREFIX_EVEX_0F73_REG_2 */
187 { VEX_W_TABLE (EVEX_W_0F73_R_2_P_2
) },
189 /* PREFIX_EVEX_0F73_REG_3 */
193 { "vpsrldq", { Vex
, EXx
, Ib
}, 0 },
195 /* PREFIX_EVEX_0F73_REG_6 */
199 { VEX_W_TABLE (EVEX_W_0F73_R_6_P_2
) },
201 /* PREFIX_EVEX_0F73_REG_7 */
205 { "vpslldq", { Vex
, EXx
, Ib
}, 0 },
207 /* PREFIX_EVEX_0F74 */
211 { "vpcmpeqb", { XMask
, Vex
, EXx
}, 0 },
213 /* PREFIX_EVEX_0F75 */
217 { "vpcmpeqw", { XMask
, Vex
, EXx
}, 0 },
219 /* PREFIX_EVEX_0F76 */
223 { VEX_W_TABLE (EVEX_W_0F76_P_2
) },
225 /* PREFIX_EVEX_0F78 */
227 { VEX_W_TABLE (EVEX_W_0F78_P_0
) },
228 { "vcvttss2usi", { Gdq
, EXxmm_md
, EXxEVexS
}, 0 },
229 { VEX_W_TABLE (EVEX_W_0F78_P_2
) },
230 { "vcvttsd2usi", { Gdq
, EXxmm_mq
, EXxEVexS
}, 0 },
232 /* PREFIX_EVEX_0F79 */
234 { VEX_W_TABLE (EVEX_W_0F79_P_0
) },
235 { "vcvtss2usi", { Gdq
, EXxmm_md
, EXxEVexR
}, 0 },
236 { VEX_W_TABLE (EVEX_W_0F79_P_2
) },
237 { "vcvtsd2usi", { Gdq
, EXxmm_mq
, EXxEVexR
}, 0 },
239 /* PREFIX_EVEX_0F7A */
242 { VEX_W_TABLE (EVEX_W_0F7A_P_1
) },
243 { VEX_W_TABLE (EVEX_W_0F7A_P_2
) },
244 { VEX_W_TABLE (EVEX_W_0F7A_P_3
) },
246 /* PREFIX_EVEX_0F7B */
249 { "vcvtusi2ss{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
250 { VEX_W_TABLE (EVEX_W_0F7B_P_2
) },
251 { VEX_W_TABLE (EVEX_W_0F7B_P_3
) },
253 /* PREFIX_EVEX_0F7E */
256 { EVEX_LEN_TABLE (EVEX_LEN_0F7E_P_1
) },
257 { EVEX_LEN_TABLE (EVEX_LEN_0F7E_P_2
) },
259 /* PREFIX_EVEX_0F7F */
262 { VEX_W_TABLE (EVEX_W_0F7F_P_1
) },
263 { VEX_W_TABLE (EVEX_W_0F7F_P_2
) },
264 { VEX_W_TABLE (EVEX_W_0F7F_P_3
) },
266 /* PREFIX_EVEX_0FC2 */
268 { "vcmppX", { XMask
, Vex
, EXx
, EXxEVexS
, CMP
}, PREFIX_OPCODE
},
269 { VEX_W_TABLE (EVEX_W_0FC2_P_1
) },
270 { "vcmppX", { XMask
, Vex
, EXx
, EXxEVexS
, CMP
}, PREFIX_OPCODE
},
271 { VEX_W_TABLE (EVEX_W_0FC2_P_3
) },
273 /* PREFIX_EVEX_0FC4 */
277 { EVEX_LEN_TABLE (EVEX_LEN_0FC4_P_2
) },
279 /* PREFIX_EVEX_0FC5 */
283 { EVEX_LEN_TABLE (EVEX_LEN_0FC5_P_2
) },
285 /* PREFIX_EVEX_0FD6 */
289 { EVEX_LEN_TABLE (EVEX_LEN_0FD6_P_2
) },
291 /* PREFIX_EVEX_0FDB */
295 { "vpand%DQ", { XM
, Vex
, EXx
}, 0 },
297 /* PREFIX_EVEX_0FDF */
301 { "vpandn%DQ", { XM
, Vex
, EXx
}, 0 },
303 /* PREFIX_EVEX_0FE2 */
307 { "vpsra%DQ", { XM
, Vex
, EXxmm
}, 0 },
309 /* PREFIX_EVEX_0FE6 */
312 { VEX_W_TABLE (EVEX_W_0FE6_P_1
) },
313 { VEX_W_TABLE (EVEX_W_0FE6_P_2
) },
314 { VEX_W_TABLE (EVEX_W_0FE6_P_3
) },
316 /* PREFIX_EVEX_0FE7 */
320 { VEX_W_TABLE (EVEX_W_0FE7_P_2
) },
322 /* PREFIX_EVEX_0FEB */
326 { "vpor%DQ", { XM
, Vex
, EXx
}, 0 },
328 /* PREFIX_EVEX_0FEF */
332 { "vpxor%DQ", { XM
, Vex
, EXx
}, 0 },
334 /* PREFIX_EVEX_0F380D */
338 { VEX_W_TABLE (EVEX_W_0F380D_P_2
) },
340 /* PREFIX_EVEX_0F3810 */
343 { VEX_W_TABLE (EVEX_W_0F3810_P_1
) },
344 { VEX_W_TABLE (EVEX_W_0F3810_P_2
) },
346 /* PREFIX_EVEX_0F3811 */
349 { VEX_W_TABLE (EVEX_W_0F3811_P_1
) },
350 { VEX_W_TABLE (EVEX_W_0F3811_P_2
) },
352 /* PREFIX_EVEX_0F3812 */
355 { VEX_W_TABLE (EVEX_W_0F3812_P_1
) },
356 { VEX_W_TABLE (EVEX_W_0F3812_P_2
) },
358 /* PREFIX_EVEX_0F3813 */
361 { VEX_W_TABLE (EVEX_W_0F3813_P_1
) },
362 { VEX_W_TABLE (EVEX_W_0F3813_P_2
) },
364 /* PREFIX_EVEX_0F3814 */
367 { VEX_W_TABLE (EVEX_W_0F3814_P_1
) },
368 { "vprorv%DQ", { XM
, Vex
, EXx
}, 0 },
370 /* PREFIX_EVEX_0F3815 */
373 { VEX_W_TABLE (EVEX_W_0F3815_P_1
) },
374 { "vprolv%DQ", { XM
, Vex
, EXx
}, 0 },
376 /* PREFIX_EVEX_0F3816 */
380 { EVEX_LEN_TABLE (EVEX_LEN_0F3816_P_2
) },
382 /* PREFIX_EVEX_0F3819 */
386 { VEX_W_TABLE (EVEX_W_0F3819_P_2
) },
388 /* PREFIX_EVEX_0F381A */
392 { VEX_W_TABLE (EVEX_W_0F381A_P_2
) },
394 /* PREFIX_EVEX_0F381B */
398 { VEX_W_TABLE (EVEX_W_0F381B_P_2
) },
400 /* PREFIX_EVEX_0F381E */
404 { VEX_W_TABLE (EVEX_W_0F381E_P_2
) },
406 /* PREFIX_EVEX_0F381F */
410 { VEX_W_TABLE (EVEX_W_0F381F_P_2
) },
412 /* PREFIX_EVEX_0F3820 */
415 { VEX_W_TABLE (EVEX_W_0F3820_P_1
) },
416 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
418 /* PREFIX_EVEX_0F3821 */
421 { VEX_W_TABLE (EVEX_W_0F3821_P_1
) },
422 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
424 /* PREFIX_EVEX_0F3822 */
427 { VEX_W_TABLE (EVEX_W_0F3822_P_1
) },
428 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
430 /* PREFIX_EVEX_0F3823 */
433 { VEX_W_TABLE (EVEX_W_0F3823_P_1
) },
434 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
436 /* PREFIX_EVEX_0F3824 */
439 { VEX_W_TABLE (EVEX_W_0F3824_P_1
) },
440 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
442 /* PREFIX_EVEX_0F3825 */
445 { VEX_W_TABLE (EVEX_W_0F3825_P_1
) },
446 { VEX_W_TABLE (EVEX_W_0F3825_P_2
) },
448 /* PREFIX_EVEX_0F3826 */
451 { "vptestnm%BW", { XMask
, Vex
, EXx
}, 0 },
452 { "vptestm%BW", { XMask
, Vex
, EXx
}, 0 },
454 /* PREFIX_EVEX_0F3827 */
457 { "vptestnm%DQ", { XMask
, Vex
, EXx
}, 0 },
458 { "vptestm%DQ", { XMask
, Vex
, EXx
}, 0 },
460 /* PREFIX_EVEX_0F3828 */
463 { "vpmovm2%BW", { XM
, MaskR
}, 0 },
464 { VEX_W_TABLE (EVEX_W_0F3828_P_2
) },
466 /* PREFIX_EVEX_0F3829 */
469 { "vpmov%BW2m", { XMask
, EXx
}, 0 },
470 { VEX_W_TABLE (EVEX_W_0F3829_P_2
) },
472 /* PREFIX_EVEX_0F382A */
475 { VEX_W_TABLE (EVEX_W_0F382A_P_1
) },
476 { VEX_W_TABLE (EVEX_W_0F382A_P_2
) },
478 /* PREFIX_EVEX_0F382C */
482 { "vscalefp%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
484 /* PREFIX_EVEX_0F382D */
488 { "vscalefs%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
490 /* PREFIX_EVEX_0F3830 */
493 { VEX_W_TABLE (EVEX_W_0F3830_P_1
) },
494 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
496 /* PREFIX_EVEX_0F3831 */
499 { VEX_W_TABLE (EVEX_W_0F3831_P_1
) },
500 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
502 /* PREFIX_EVEX_0F3832 */
505 { VEX_W_TABLE (EVEX_W_0F3832_P_1
) },
506 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
508 /* PREFIX_EVEX_0F3833 */
511 { VEX_W_TABLE (EVEX_W_0F3833_P_1
) },
512 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
514 /* PREFIX_EVEX_0F3834 */
517 { VEX_W_TABLE (EVEX_W_0F3834_P_1
) },
518 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
520 /* PREFIX_EVEX_0F3835 */
523 { VEX_W_TABLE (EVEX_W_0F3835_P_1
) },
524 { VEX_W_TABLE (EVEX_W_0F3835_P_2
) },
526 /* PREFIX_EVEX_0F3836 */
530 { EVEX_LEN_TABLE (EVEX_LEN_0F3836_P_2
) },
532 /* PREFIX_EVEX_0F3837 */
536 { VEX_W_TABLE (EVEX_W_0F3837_P_2
) },
538 /* PREFIX_EVEX_0F3838 */
541 { "vpmovm2%DQ", { XM
, MaskR
}, 0 },
542 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
544 /* PREFIX_EVEX_0F3839 */
547 { "vpmov%DQ2m", { XMask
, EXx
}, 0 },
548 { "vpmins%DQ", { XM
, Vex
, EXx
}, 0 },
550 /* PREFIX_EVEX_0F383A */
553 { VEX_W_TABLE (EVEX_W_0F383A_P_1
) },
554 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
556 /* PREFIX_EVEX_0F383B */
560 { "vpminu%DQ", { XM
, Vex
, EXx
}, 0 },
562 /* PREFIX_EVEX_0F383D */
566 { "vpmaxs%DQ", { XM
, Vex
, EXx
}, 0 },
568 /* PREFIX_EVEX_0F383F */
572 { "vpmaxu%DQ", { XM
, Vex
, EXx
}, 0 },
574 /* PREFIX_EVEX_0F3840 */
578 { "vpmull%DQ", { XM
, Vex
, EXx
}, 0 },
580 /* PREFIX_EVEX_0F3842 */
584 { "vgetexpp%XW", { XM
, EXx
, EXxEVexS
}, 0 },
586 /* PREFIX_EVEX_0F3843 */
590 { "vgetexps%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
}, 0 },
592 /* PREFIX_EVEX_0F3844 */
596 { "vplzcnt%DQ", { XM
, EXx
}, 0 },
598 /* PREFIX_EVEX_0F3845 */
602 { "vpsrlv%DQ", { XM
, Vex
, EXx
}, 0 },
604 /* PREFIX_EVEX_0F3846 */
608 { "vpsrav%DQ", { XM
, Vex
, EXx
}, 0 },
610 /* PREFIX_EVEX_0F3847 */
614 { "vpsllv%DQ", { XM
, Vex
, EXx
}, 0 },
616 /* PREFIX_EVEX_0F384C */
620 { "vrcp14p%XW", { XM
, EXx
}, 0 },
622 /* PREFIX_EVEX_0F384D */
626 { "vrcp14s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
628 /* PREFIX_EVEX_0F384E */
632 { "vrsqrt14p%XW", { XM
, EXx
}, 0 },
634 /* PREFIX_EVEX_0F384F */
638 { "vrsqrt14s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
640 /* PREFIX_EVEX_0F3850 */
644 { "vpdpbusd", { XM
, Vex
, EXx
}, 0 },
646 /* PREFIX_EVEX_0F3851 */
650 { "vpdpbusds", { XM
, Vex
, EXx
}, 0 },
652 /* PREFIX_EVEX_0F3852 */
655 { VEX_W_TABLE (EVEX_W_0F3852_P_1
) },
656 { "vpdpwssd", { XM
, Vex
, EXx
}, 0 },
657 { "vp4dpwssd", { XM
, Vex
, EXxmm
}, 0 },
659 /* PREFIX_EVEX_0F3853 */
663 { "vpdpwssds", { XM
, Vex
, EXx
}, 0 },
664 { "vp4dpwssds", { XM
, Vex
, EXxmm
}, 0 },
666 /* PREFIX_EVEX_0F3854 */
670 { "vpopcnt%BW", { XM
, EXx
}, 0 },
672 /* PREFIX_EVEX_0F3855 */
676 { "vpopcnt%DQ", { XM
, EXx
}, 0 },
678 /* PREFIX_EVEX_0F3859 */
682 { VEX_W_TABLE (EVEX_W_0F3859_P_2
) },
684 /* PREFIX_EVEX_0F385A */
688 { VEX_W_TABLE (EVEX_W_0F385A_P_2
) },
690 /* PREFIX_EVEX_0F385B */
694 { VEX_W_TABLE (EVEX_W_0F385B_P_2
) },
696 /* PREFIX_EVEX_0F3862 */
700 { "vpexpand%BW", { XM
, EXbwUnit
}, 0 },
702 /* PREFIX_EVEX_0F3863 */
706 { "vpcompress%BW", { EXbwUnit
, XM
}, 0 },
708 /* PREFIX_EVEX_0F3864 */
712 { "vpblendm%DQ", { XM
, Vex
, EXx
}, 0 },
714 /* PREFIX_EVEX_0F3865 */
718 { "vblendmp%XW", { XM
, Vex
, EXx
}, 0 },
720 /* PREFIX_EVEX_0F3866 */
724 { "vpblendm%BW", { XM
, Vex
, EXx
}, 0 },
726 /* PREFIX_EVEX_0F3868 */
731 { "vp2intersect%DQ", { XMask
, Vex
, EXx
, EXxEVexS
}, 0 },
733 /* PREFIX_EVEX_0F3870 */
737 { VEX_W_TABLE (EVEX_W_0F3870_P_2
) },
739 /* PREFIX_EVEX_0F3871 */
743 { "vpshldv%DQ", { XM
, Vex
, EXx
}, 0 },
745 /* PREFIX_EVEX_0F3872 */
748 { VEX_W_TABLE (EVEX_W_0F3872_P_1
) },
749 { VEX_W_TABLE (EVEX_W_0F3872_P_2
) },
750 { VEX_W_TABLE (EVEX_W_0F3872_P_3
) },
752 /* PREFIX_EVEX_0F3873 */
756 { "vpshrdv%DQ", { XM
, Vex
, EXx
}, 0 },
758 /* PREFIX_EVEX_0F3875 */
762 { "vpermi2%BW", { XM
, Vex
, EXx
}, 0 },
764 /* PREFIX_EVEX_0F3876 */
768 { "vpermi2%DQ", { XM
, Vex
, EXx
}, 0 },
770 /* PREFIX_EVEX_0F3877 */
774 { "vpermi2p%XW", { XM
, Vex
, EXx
}, 0 },
776 /* PREFIX_EVEX_0F387A */
780 { VEX_W_TABLE (EVEX_W_0F387A_P_2
) },
782 /* PREFIX_EVEX_0F387B */
786 { VEX_W_TABLE (EVEX_W_0F387B_P_2
) },
788 /* PREFIX_EVEX_0F387C */
792 { "vpbroadcastK", { XM
, Rdq
}, 0 },
794 /* PREFIX_EVEX_0F387D */
798 { "vpermt2%BW", { XM
, Vex
, EXx
}, 0 },
800 /* PREFIX_EVEX_0F387E */
804 { "vpermt2%DQ", { XM
, Vex
, EXx
}, 0 },
806 /* PREFIX_EVEX_0F387F */
810 { "vpermt2p%XW", { XM
, Vex
, EXx
}, 0 },
812 /* PREFIX_EVEX_0F3883 */
816 { VEX_W_TABLE (EVEX_W_0F3883_P_2
) },
818 /* PREFIX_EVEX_0F3888 */
822 { "vexpandp%XW", { XM
, EXEvexXGscat
}, 0 },
824 /* PREFIX_EVEX_0F3889 */
828 { "vpexpand%DQ", { XM
, EXEvexXGscat
}, 0 },
830 /* PREFIX_EVEX_0F388A */
834 { "vcompressp%XW", { EXEvexXGscat
, XM
}, 0 },
836 /* PREFIX_EVEX_0F388B */
840 { "vpcompress%DQ", { EXEvexXGscat
, XM
}, 0 },
842 /* PREFIX_EVEX_0F388D */
846 { "vperm%BW", { XM
, Vex
, EXx
}, 0 },
848 /* PREFIX_EVEX_0F388F */
852 { "vpshufbitqmb", { XMask
, Vex
, EXx
}, 0 },
854 /* PREFIX_EVEX_0F3890 */
858 { "vpgatherd%DQ", { XM
, MVexVSIBDWpX
}, 0 },
860 /* PREFIX_EVEX_0F3891 */
864 { VEX_W_TABLE (EVEX_W_0F3891_P_2
) },
866 /* PREFIX_EVEX_0F3892 */
870 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
}, 0 },
872 /* PREFIX_EVEX_0F3893 */
876 { VEX_W_TABLE (EVEX_W_0F3893_P_2
) },
878 /* PREFIX_EVEX_0F389A */
882 { "vfmsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
883 { "v4fmaddps", { XM
, Vex
, Mxmm
}, 0 },
885 /* PREFIX_EVEX_0F389B */
889 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
890 { "v4fmaddss", { XMScalar
, VexScalar
, Mxmm
}, 0 },
892 /* PREFIX_EVEX_0F38A0 */
896 { "vpscatterd%DQ", { MVexVSIBDWpX
, XM
}, 0 },
898 /* PREFIX_EVEX_0F38A1 */
902 { VEX_W_TABLE (EVEX_W_0F38A1_P_2
) },
904 /* PREFIX_EVEX_0F38A2 */
908 { "vscatterdp%XW", { MVexVSIBDWpX
, XM
}, 0 },
910 /* PREFIX_EVEX_0F38A3 */
914 { VEX_W_TABLE (EVEX_W_0F38A3_P_2
) },
916 /* PREFIX_EVEX_0F38AA */
920 { "vfmsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
921 { "v4fnmaddps", { XM
, Vex
, Mxmm
}, 0 },
923 /* PREFIX_EVEX_0F38AB */
927 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
928 { "v4fnmaddss", { XMScalar
, VexScalar
, Mxmm
}, 0 },
930 /* PREFIX_EVEX_0F38B4 */
934 { "vpmadd52luq", { XM
, Vex
, EXx
}, 0 },
936 /* PREFIX_EVEX_0F38B5 */
940 { "vpmadd52huq", { XM
, Vex
, EXx
}, 0 },
942 /* PREFIX_EVEX_0F38C4 */
946 { "vpconflict%DQ", { XM
, EXx
}, 0 },
948 /* PREFIX_EVEX_0F38C6_REG_1 */
952 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_1_PREFIX_2
) },
954 /* PREFIX_EVEX_0F38C6_REG_2 */
958 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_2_PREFIX_2
) },
960 /* PREFIX_EVEX_0F38C6_REG_5 */
964 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_5_PREFIX_2
) },
966 /* PREFIX_EVEX_0F38C6_REG_6 */
970 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_6_PREFIX_2
) },
972 /* PREFIX_EVEX_0F38C7_REG_1 */
976 { VEX_W_TABLE (EVEX_W_0F38C7_R_1_P_2
) },
978 /* PREFIX_EVEX_0F38C7_REG_2 */
982 { VEX_W_TABLE (EVEX_W_0F38C7_R_2_P_2
) },
984 /* PREFIX_EVEX_0F38C7_REG_5 */
988 { VEX_W_TABLE (EVEX_W_0F38C7_R_5_P_2
) },
990 /* PREFIX_EVEX_0F38C7_REG_6 */
994 { VEX_W_TABLE (EVEX_W_0F38C7_R_6_P_2
) },
996 /* PREFIX_EVEX_0F38C8 */
1000 { "vexp2p%XW", { XM
, EXx
, EXxEVexS
}, 0 },
1002 /* PREFIX_EVEX_0F38CA */
1006 { "vrcp28p%XW", { XM
, EXx
, EXxEVexS
}, 0 },
1008 /* PREFIX_EVEX_0F38CB */
1012 { "vrcp28s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
}, 0 },
1014 /* PREFIX_EVEX_0F38CC */
1018 { "vrsqrt28p%XW", { XM
, EXx
, EXxEVexS
}, 0 },
1020 /* PREFIX_EVEX_0F38CD */
1024 { "vrsqrt28s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
}, 0 },
1026 /* PREFIX_EVEX_0F3A00 */
1030 { VEX_W_TABLE (EVEX_W_0F3A00_P_2
) },
1032 /* PREFIX_EVEX_0F3A01 */
1036 { VEX_W_TABLE (EVEX_W_0F3A01_P_2
) },
1038 /* PREFIX_EVEX_0F3A03 */
1042 { "valign%DQ", { XM
, Vex
, EXx
, Ib
}, 0 },
1044 /* PREFIX_EVEX_0F3A05 */
1048 { VEX_W_TABLE (EVEX_W_0F3A05_P_2
) },
1050 /* PREFIX_EVEX_0F3A08 */
1054 { VEX_W_TABLE (EVEX_W_0F3A08_P_2
) },
1056 /* PREFIX_EVEX_0F3A09 */
1060 { VEX_W_TABLE (EVEX_W_0F3A09_P_2
) },
1062 /* PREFIX_EVEX_0F3A0A */
1066 { VEX_W_TABLE (EVEX_W_0F3A0A_P_2
) },
1068 /* PREFIX_EVEX_0F3A0B */
1072 { VEX_W_TABLE (EVEX_W_0F3A0B_P_2
) },
1074 /* PREFIX_EVEX_0F3A14 */
1078 { EVEX_LEN_TABLE (EVEX_LEN_0F3A14_P_2
) },
1080 /* PREFIX_EVEX_0F3A15 */
1084 { EVEX_LEN_TABLE (EVEX_LEN_0F3A15_P_2
) },
1086 /* PREFIX_EVEX_0F3A16 */
1090 { EVEX_LEN_TABLE (EVEX_LEN_0F3A16_P_2
) },
1092 /* PREFIX_EVEX_0F3A17 */
1096 { EVEX_LEN_TABLE (EVEX_LEN_0F3A17_P_2
) },
1098 /* PREFIX_EVEX_0F3A18 */
1102 { VEX_W_TABLE (EVEX_W_0F3A18_P_2
) },
1104 /* PREFIX_EVEX_0F3A19 */
1108 { VEX_W_TABLE (EVEX_W_0F3A19_P_2
) },
1110 /* PREFIX_EVEX_0F3A1A */
1114 { VEX_W_TABLE (EVEX_W_0F3A1A_P_2
) },
1116 /* PREFIX_EVEX_0F3A1B */
1120 { VEX_W_TABLE (EVEX_W_0F3A1B_P_2
) },
1122 /* PREFIX_EVEX_0F3A1E */
1126 { "vpcmpu%DQ", { XMask
, Vex
, EXx
, VPCMP
}, 0 },
1128 /* PREFIX_EVEX_0F3A1F */
1132 { "vpcmp%DQ", { XMask
, Vex
, EXx
, VPCMP
}, 0 },
1134 /* PREFIX_EVEX_0F3A20 */
1138 { EVEX_LEN_TABLE (EVEX_LEN_0F3A20_P_2
) },
1140 /* PREFIX_EVEX_0F3A21 */
1144 { VEX_W_TABLE (EVEX_W_0F3A21_P_2
) },
1146 /* PREFIX_EVEX_0F3A22 */
1150 { EVEX_LEN_TABLE (EVEX_LEN_0F3A22_P_2
) },
1152 /* PREFIX_EVEX_0F3A23 */
1156 { VEX_W_TABLE (EVEX_W_0F3A23_P_2
) },
1158 /* PREFIX_EVEX_0F3A25 */
1162 { "vpternlog%DQ", { XM
, Vex
, EXx
, Ib
}, 0 },
1164 /* PREFIX_EVEX_0F3A26 */
1168 { "vgetmantp%XW", { XM
, EXx
, EXxEVexS
, Ib
}, 0 },
1170 /* PREFIX_EVEX_0F3A27 */
1174 { "vgetmants%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
, Ib
}, 0 },
1176 /* PREFIX_EVEX_0F3A38 */
1180 { VEX_W_TABLE (EVEX_W_0F3A38_P_2
) },
1182 /* PREFIX_EVEX_0F3A39 */
1186 { VEX_W_TABLE (EVEX_W_0F3A39_P_2
) },
1188 /* PREFIX_EVEX_0F3A3A */
1192 { VEX_W_TABLE (EVEX_W_0F3A3A_P_2
) },
1194 /* PREFIX_EVEX_0F3A3B */
1198 { VEX_W_TABLE (EVEX_W_0F3A3B_P_2
) },
1200 /* PREFIX_EVEX_0F3A3E */
1204 { "vpcmpu%BW", { XMask
, Vex
, EXx
, VPCMP
}, 0 },
1206 /* PREFIX_EVEX_0F3A3F */
1210 { "vpcmp%BW", { XMask
, Vex
, EXx
, VPCMP
}, 0 },
1212 /* PREFIX_EVEX_0F3A42 */
1216 { VEX_W_TABLE (EVEX_W_0F3A42_P_2
) },
1218 /* PREFIX_EVEX_0F3A43 */
1222 { VEX_W_TABLE (EVEX_W_0F3A43_P_2
) },
1224 /* PREFIX_EVEX_0F3A50 */
1228 { "vrangep%XW", { XM
, Vex
, EXx
, EXxEVexS
, Ib
}, 0 },
1230 /* PREFIX_EVEX_0F3A51 */
1234 { "vranges%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
, Ib
}, 0 },
1236 /* PREFIX_EVEX_0F3A54 */
1240 { "vfixupimmp%XW", { XM
, Vex
, EXx
, EXxEVexS
, Ib
}, 0 },
1242 /* PREFIX_EVEX_0F3A55 */
1246 { "vfixupimms%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
, Ib
}, 0 },
1248 /* PREFIX_EVEX_0F3A56 */
1252 { "vreducep%XW", { XM
, EXx
, EXxEVexS
, Ib
}, 0 },
1254 /* PREFIX_EVEX_0F3A57 */
1258 { "vreduces%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
, Ib
}, 0 },
1260 /* PREFIX_EVEX_0F3A66 */
1264 { "vfpclassp%XW%XZ", { XMask
, EXx
, Ib
}, 0 },
1266 /* PREFIX_EVEX_0F3A67 */
1270 { "vfpclasss%XW", { XMask
, EXVexWdqScalar
, Ib
}, 0 },
1272 /* PREFIX_EVEX_0F3A70 */
1276 { VEX_W_TABLE (EVEX_W_0F3A70_P_2
) },
1278 /* PREFIX_EVEX_0F3A71 */
1282 { "vpshld%DQ", { XM
, Vex
, EXx
, Ib
}, 0 },
1284 /* PREFIX_EVEX_0F3A72 */
1288 { VEX_W_TABLE (EVEX_W_0F3A72_P_2
) },
1290 /* PREFIX_EVEX_0F3A73 */
1294 { "vpshrd%DQ", { XM
, Vex
, EXx
, Ib
}, 0 },