3 { "vmovupX", { XM
, EXEvexXNoBcst
}, PREFIX_OPCODE
},
4 { VEX_W_TABLE (EVEX_W_0F10_P_1
) },
5 { "vmovupX", { XM
, EXEvexXNoBcst
}, PREFIX_OPCODE
},
6 { VEX_W_TABLE (EVEX_W_0F10_P_3
) },
10 { "vmovupX", { EXxS
, XM
}, PREFIX_OPCODE
},
11 { VEX_W_TABLE (EVEX_W_0F11_P_1
) },
12 { "vmovupX", { EXxS
, XM
}, PREFIX_OPCODE
},
13 { VEX_W_TABLE (EVEX_W_0F11_P_3
) },
15 /* PREFIX_EVEX_0F12 */
17 { MOD_TABLE (MOD_EVEX_0F12_PREFIX_0
) },
18 { VEX_W_TABLE (EVEX_W_0F12_P_1
) },
19 { MOD_TABLE (MOD_EVEX_0F12_PREFIX_2
) },
20 { VEX_W_TABLE (EVEX_W_0F12_P_3
) },
22 /* PREFIX_EVEX_0F16 */
24 { MOD_TABLE (MOD_EVEX_0F16_PREFIX_0
) },
25 { VEX_W_TABLE (EVEX_W_0F16_P_1
) },
26 { MOD_TABLE (MOD_EVEX_0F16_PREFIX_2
) },
28 /* PREFIX_EVEX_0F2A */
31 { "vcvtsi2ss{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
33 { VEX_W_TABLE (EVEX_W_0F2A_P_3
) },
35 /* PREFIX_EVEX_0F2C */
38 { "vcvttss2si", { Gdq
, EXxmm_md
, EXxEVexS
}, 0 },
40 { "vcvttsd2si", { Gdq
, EXxmm_mq
, EXxEVexS
}, 0 },
42 /* PREFIX_EVEX_0F2D */
45 { "vcvtss2si", { Gdq
, EXxmm_md
, EXxEVexR
}, 0 },
47 { "vcvtsd2si", { Gdq
, EXxmm_mq
, EXxEVexR
}, 0 },
49 /* PREFIX_EVEX_0F2E */
51 { "vucomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
53 { "vucomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
55 /* PREFIX_EVEX_0F2F */
57 { "vcomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
59 { "vcomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
61 /* PREFIX_EVEX_0F51 */
63 { "vsqrtpX", { XM
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
64 { VEX_W_TABLE (EVEX_W_0F51_P_1
) },
65 { "vsqrtpX", { XM
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
66 { VEX_W_TABLE (EVEX_W_0F51_P_3
) },
68 /* PREFIX_EVEX_0F58 */
70 { "vaddpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
71 { VEX_W_TABLE (EVEX_W_0F58_P_1
) },
72 { "vaddpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
73 { VEX_W_TABLE (EVEX_W_0F58_P_3
) },
75 /* PREFIX_EVEX_0F59 */
77 { "vmulpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
78 { VEX_W_TABLE (EVEX_W_0F59_P_1
) },
79 { "vmulpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
80 { VEX_W_TABLE (EVEX_W_0F59_P_3
) },
82 /* PREFIX_EVEX_0F5A */
84 { VEX_W_TABLE (EVEX_W_0F5A_P_0
) },
85 { VEX_W_TABLE (EVEX_W_0F5A_P_1
) },
86 { VEX_W_TABLE (EVEX_W_0F5A_P_2
) },
87 { VEX_W_TABLE (EVEX_W_0F5A_P_3
) },
89 /* PREFIX_EVEX_0F5B */
91 { VEX_W_TABLE (EVEX_W_0F5B_P_0
) },
92 { VEX_W_TABLE (EVEX_W_0F5B_P_1
) },
93 { VEX_W_TABLE (EVEX_W_0F5B_P_2
) },
95 /* PREFIX_EVEX_0F5C */
97 { "vsubpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
98 { VEX_W_TABLE (EVEX_W_0F5C_P_1
) },
99 { "vsubpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
100 { VEX_W_TABLE (EVEX_W_0F5C_P_3
) },
102 /* PREFIX_EVEX_0F5D */
104 { "vminpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
105 { VEX_W_TABLE (EVEX_W_0F5D_P_1
) },
106 { "vminpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
107 { VEX_W_TABLE (EVEX_W_0F5D_P_3
) },
109 /* PREFIX_EVEX_0F5E */
111 { "vdivpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
112 { VEX_W_TABLE (EVEX_W_0F5E_P_1
) },
113 { "vdivpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
114 { VEX_W_TABLE (EVEX_W_0F5E_P_3
) },
116 /* PREFIX_EVEX_0F5F */
118 { "vmaxpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
119 { VEX_W_TABLE (EVEX_W_0F5F_P_1
) },
120 { "vmaxpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
121 { VEX_W_TABLE (EVEX_W_0F5F_P_3
) },
123 /* PREFIX_EVEX_0F64 */
127 { "vpcmpgtb", { XMask
, Vex
, EXx
}, 0 },
129 /* PREFIX_EVEX_0F65 */
133 { "vpcmpgtw", { XMask
, Vex
, EXx
}, 0 },
135 /* PREFIX_EVEX_0F66 */
139 { VEX_W_TABLE (EVEX_W_0F66_P_2
) },
141 /* PREFIX_EVEX_0F6E */
145 { EVEX_LEN_TABLE (EVEX_LEN_0F6E_P_2
) },
147 /* PREFIX_EVEX_0F6F */
150 { VEX_W_TABLE (EVEX_W_0F6F_P_1
) },
151 { VEX_W_TABLE (EVEX_W_0F6F_P_2
) },
152 { VEX_W_TABLE (EVEX_W_0F6F_P_3
) },
154 /* PREFIX_EVEX_0F70 */
157 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
158 { VEX_W_TABLE (EVEX_W_0F70_P_2
) },
159 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
161 /* PREFIX_EVEX_0F71_REG_2 */
165 { "vpsrlw", { Vex
, EXx
, Ib
}, 0 },
167 /* PREFIX_EVEX_0F71_REG_4 */
171 { "vpsraw", { Vex
, EXx
, Ib
}, 0 },
173 /* PREFIX_EVEX_0F71_REG_6 */
177 { "vpsllw", { Vex
, EXx
, Ib
}, 0 },
179 /* PREFIX_EVEX_0F72_REG_0 */
183 { "vpror%LW", { Vex
, EXx
, Ib
}, 0 },
185 /* PREFIX_EVEX_0F72_REG_1 */
189 { "vprol%LW", { Vex
, EXx
, Ib
}, 0 },
191 /* PREFIX_EVEX_0F72_REG_2 */
195 { VEX_W_TABLE (EVEX_W_0F72_R_2_P_2
) },
197 /* PREFIX_EVEX_0F72_REG_4 */
201 { "vpsra%LW", { Vex
, EXx
, Ib
}, 0 },
203 /* PREFIX_EVEX_0F72_REG_6 */
207 { VEX_W_TABLE (EVEX_W_0F72_R_6_P_2
) },
209 /* PREFIX_EVEX_0F73_REG_2 */
213 { VEX_W_TABLE (EVEX_W_0F73_R_2_P_2
) },
215 /* PREFIX_EVEX_0F73_REG_3 */
219 { "vpsrldq", { Vex
, EXx
, Ib
}, 0 },
221 /* PREFIX_EVEX_0F73_REG_6 */
225 { VEX_W_TABLE (EVEX_W_0F73_R_6_P_2
) },
227 /* PREFIX_EVEX_0F73_REG_7 */
231 { "vpslldq", { Vex
, EXx
, Ib
}, 0 },
233 /* PREFIX_EVEX_0F74 */
237 { "vpcmpeqb", { XMask
, Vex
, EXx
}, 0 },
239 /* PREFIX_EVEX_0F75 */
243 { "vpcmpeqw", { XMask
, Vex
, EXx
}, 0 },
245 /* PREFIX_EVEX_0F76 */
249 { VEX_W_TABLE (EVEX_W_0F76_P_2
) },
251 /* PREFIX_EVEX_0F78 */
253 { VEX_W_TABLE (EVEX_W_0F78_P_0
) },
254 { "vcvttss2usi", { Gdq
, EXxmm_md
, EXxEVexS
}, 0 },
255 { VEX_W_TABLE (EVEX_W_0F78_P_2
) },
256 { "vcvttsd2usi", { Gdq
, EXxmm_mq
, EXxEVexS
}, 0 },
258 /* PREFIX_EVEX_0F79 */
260 { VEX_W_TABLE (EVEX_W_0F79_P_0
) },
261 { "vcvtss2usi", { Gdq
, EXxmm_md
, EXxEVexR
}, 0 },
262 { VEX_W_TABLE (EVEX_W_0F79_P_2
) },
263 { "vcvtsd2usi", { Gdq
, EXxmm_mq
, EXxEVexR
}, 0 },
265 /* PREFIX_EVEX_0F7A */
268 { VEX_W_TABLE (EVEX_W_0F7A_P_1
) },
269 { VEX_W_TABLE (EVEX_W_0F7A_P_2
) },
270 { VEX_W_TABLE (EVEX_W_0F7A_P_3
) },
272 /* PREFIX_EVEX_0F7B */
275 { "vcvtusi2ss{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
276 { VEX_W_TABLE (EVEX_W_0F7B_P_2
) },
277 { VEX_W_TABLE (EVEX_W_0F7B_P_3
) },
279 /* PREFIX_EVEX_0F7E */
282 { EVEX_LEN_TABLE (EVEX_LEN_0F7E_P_1
) },
283 { EVEX_LEN_TABLE (EVEX_LEN_0F7E_P_2
) },
285 /* PREFIX_EVEX_0F7F */
288 { VEX_W_TABLE (EVEX_W_0F7F_P_1
) },
289 { VEX_W_TABLE (EVEX_W_0F7F_P_2
) },
290 { VEX_W_TABLE (EVEX_W_0F7F_P_3
) },
292 /* PREFIX_EVEX_0FC2 */
294 { "vcmppX", { XMask
, Vex
, EXx
, EXxEVexS
, CMP
}, PREFIX_OPCODE
},
295 { VEX_W_TABLE (EVEX_W_0FC2_P_1
) },
296 { "vcmppX", { XMask
, Vex
, EXx
, EXxEVexS
, CMP
}, PREFIX_OPCODE
},
297 { VEX_W_TABLE (EVEX_W_0FC2_P_3
) },
299 /* PREFIX_EVEX_0FC4 */
303 { EVEX_LEN_TABLE (EVEX_LEN_0FC4_P_2
) },
305 /* PREFIX_EVEX_0FC5 */
309 { EVEX_LEN_TABLE (EVEX_LEN_0FC5_P_2
) },
311 /* PREFIX_EVEX_0FD6 */
315 { EVEX_LEN_TABLE (EVEX_LEN_0FD6_P_2
) },
317 /* PREFIX_EVEX_0FDB */
321 { "vpand%LW", { XM
, Vex
, EXx
}, 0 },
323 /* PREFIX_EVEX_0FDF */
327 { "vpandn%LW", { XM
, Vex
, EXx
}, 0 },
329 /* PREFIX_EVEX_0FE2 */
333 { "vpsra%LW", { XM
, Vex
, EXxmm
}, 0 },
335 /* PREFIX_EVEX_0FE6 */
338 { VEX_W_TABLE (EVEX_W_0FE6_P_1
) },
339 { VEX_W_TABLE (EVEX_W_0FE6_P_2
) },
340 { VEX_W_TABLE (EVEX_W_0FE6_P_3
) },
342 /* PREFIX_EVEX_0FE7 */
346 { VEX_W_TABLE (EVEX_W_0FE7_P_2
) },
348 /* PREFIX_EVEX_0FEB */
352 { "vpor%LW", { XM
, Vex
, EXx
}, 0 },
354 /* PREFIX_EVEX_0FEF */
358 { "vpxor%LW", { XM
, Vex
, EXx
}, 0 },
360 /* PREFIX_EVEX_0F380D */
364 { VEX_W_TABLE (EVEX_W_0F380D_P_2
) },
366 /* PREFIX_EVEX_0F3810 */
369 { VEX_W_TABLE (EVEX_W_0F3810_P_1
) },
370 { VEX_W_TABLE (EVEX_W_0F3810_P_2
) },
372 /* PREFIX_EVEX_0F3811 */
375 { VEX_W_TABLE (EVEX_W_0F3811_P_1
) },
376 { VEX_W_TABLE (EVEX_W_0F3811_P_2
) },
378 /* PREFIX_EVEX_0F3812 */
381 { VEX_W_TABLE (EVEX_W_0F3812_P_1
) },
382 { VEX_W_TABLE (EVEX_W_0F3812_P_2
) },
384 /* PREFIX_EVEX_0F3813 */
387 { VEX_W_TABLE (EVEX_W_0F3813_P_1
) },
388 { VEX_W_TABLE (EVEX_W_0F3813_P_2
) },
390 /* PREFIX_EVEX_0F3814 */
393 { VEX_W_TABLE (EVEX_W_0F3814_P_1
) },
394 { "vprorv%LW", { XM
, Vex
, EXx
}, 0 },
396 /* PREFIX_EVEX_0F3815 */
399 { VEX_W_TABLE (EVEX_W_0F3815_P_1
) },
400 { "vprolv%LW", { XM
, Vex
, EXx
}, 0 },
402 /* PREFIX_EVEX_0F3816 */
406 { EVEX_LEN_TABLE (EVEX_LEN_0F3816_P_2
) },
408 /* PREFIX_EVEX_0F3819 */
412 { VEX_W_TABLE (EVEX_W_0F3819_P_2
) },
414 /* PREFIX_EVEX_0F381A */
418 { VEX_W_TABLE (EVEX_W_0F381A_P_2
) },
420 /* PREFIX_EVEX_0F381B */
424 { VEX_W_TABLE (EVEX_W_0F381B_P_2
) },
426 /* PREFIX_EVEX_0F381E */
430 { VEX_W_TABLE (EVEX_W_0F381E_P_2
) },
432 /* PREFIX_EVEX_0F381F */
436 { VEX_W_TABLE (EVEX_W_0F381F_P_2
) },
438 /* PREFIX_EVEX_0F3820 */
441 { VEX_W_TABLE (EVEX_W_0F3820_P_1
) },
442 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
444 /* PREFIX_EVEX_0F3821 */
447 { VEX_W_TABLE (EVEX_W_0F3821_P_1
) },
448 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
450 /* PREFIX_EVEX_0F3822 */
453 { VEX_W_TABLE (EVEX_W_0F3822_P_1
) },
454 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
456 /* PREFIX_EVEX_0F3823 */
459 { VEX_W_TABLE (EVEX_W_0F3823_P_1
) },
460 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
462 /* PREFIX_EVEX_0F3824 */
465 { VEX_W_TABLE (EVEX_W_0F3824_P_1
) },
466 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
468 /* PREFIX_EVEX_0F3825 */
471 { VEX_W_TABLE (EVEX_W_0F3825_P_1
) },
472 { VEX_W_TABLE (EVEX_W_0F3825_P_2
) },
474 /* PREFIX_EVEX_0F3826 */
477 { "vptestnm%BW", { XMask
, Vex
, EXx
}, 0 },
478 { "vptestm%BW", { XMask
, Vex
, EXx
}, 0 },
480 /* PREFIX_EVEX_0F3827 */
483 { "vptestnm%LW", { XMask
, Vex
, EXx
}, 0 },
484 { "vptestm%LW", { XMask
, Vex
, EXx
}, 0 },
486 /* PREFIX_EVEX_0F3828 */
489 { "vpmovm2%BW", { XM
, MaskR
}, 0 },
490 { VEX_W_TABLE (EVEX_W_0F3828_P_2
) },
492 /* PREFIX_EVEX_0F3829 */
495 { "vpmov%BW2m", { XMask
, EXx
}, 0 },
496 { VEX_W_TABLE (EVEX_W_0F3829_P_2
) },
498 /* PREFIX_EVEX_0F382A */
501 { VEX_W_TABLE (EVEX_W_0F382A_P_1
) },
502 { VEX_W_TABLE (EVEX_W_0F382A_P_2
) },
504 /* PREFIX_EVEX_0F382C */
508 { "vscalefp%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
510 /* PREFIX_EVEX_0F382D */
514 { "vscalefs%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
516 /* PREFIX_EVEX_0F3830 */
519 { VEX_W_TABLE (EVEX_W_0F3830_P_1
) },
520 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
522 /* PREFIX_EVEX_0F3831 */
525 { VEX_W_TABLE (EVEX_W_0F3831_P_1
) },
526 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
528 /* PREFIX_EVEX_0F3832 */
531 { VEX_W_TABLE (EVEX_W_0F3832_P_1
) },
532 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
534 /* PREFIX_EVEX_0F3833 */
537 { VEX_W_TABLE (EVEX_W_0F3833_P_1
) },
538 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
540 /* PREFIX_EVEX_0F3834 */
543 { VEX_W_TABLE (EVEX_W_0F3834_P_1
) },
544 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
546 /* PREFIX_EVEX_0F3835 */
549 { VEX_W_TABLE (EVEX_W_0F3835_P_1
) },
550 { VEX_W_TABLE (EVEX_W_0F3835_P_2
) },
552 /* PREFIX_EVEX_0F3836 */
556 { EVEX_LEN_TABLE (EVEX_LEN_0F3836_P_2
) },
558 /* PREFIX_EVEX_0F3837 */
562 { VEX_W_TABLE (EVEX_W_0F3837_P_2
) },
564 /* PREFIX_EVEX_0F3838 */
567 { "vpmovm2%LW", { XM
, MaskR
}, 0 },
568 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
570 /* PREFIX_EVEX_0F3839 */
573 { "vpmov%LW2m", { XMask
, EXx
}, 0 },
574 { "vpmins%LW", { XM
, Vex
, EXx
}, 0 },
576 /* PREFIX_EVEX_0F383A */
579 { VEX_W_TABLE (EVEX_W_0F383A_P_1
) },
580 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
582 /* PREFIX_EVEX_0F383B */
586 { "vpminu%LW", { XM
, Vex
, EXx
}, 0 },
588 /* PREFIX_EVEX_0F383D */
592 { "vpmaxs%LW", { XM
, Vex
, EXx
}, 0 },
594 /* PREFIX_EVEX_0F383F */
598 { "vpmaxu%LW", { XM
, Vex
, EXx
}, 0 },
600 /* PREFIX_EVEX_0F3840 */
604 { "vpmull%LW", { XM
, Vex
, EXx
}, 0 },
606 /* PREFIX_EVEX_0F3842 */
610 { "vgetexpp%XW", { XM
, EXx
, EXxEVexS
}, 0 },
612 /* PREFIX_EVEX_0F3843 */
616 { "vgetexps%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
}, 0 },
618 /* PREFIX_EVEX_0F3844 */
622 { "vplzcnt%LW", { XM
, EXx
}, 0 },
624 /* PREFIX_EVEX_0F3845 */
628 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
630 /* PREFIX_EVEX_0F3846 */
634 { "vpsrav%LW", { XM
, Vex
, EXx
}, 0 },
636 /* PREFIX_EVEX_0F3847 */
640 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
642 /* PREFIX_EVEX_0F384C */
646 { "vrcp14p%XW", { XM
, EXx
}, 0 },
648 /* PREFIX_EVEX_0F384D */
652 { "vrcp14s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
654 /* PREFIX_EVEX_0F384E */
658 { "vrsqrt14p%XW", { XM
, EXx
}, 0 },
660 /* PREFIX_EVEX_0F384F */
664 { "vrsqrt14s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
666 /* PREFIX_EVEX_0F3850 */
670 { "vpdpbusd", { XM
, Vex
, EXx
}, 0 },
672 /* PREFIX_EVEX_0F3851 */
676 { "vpdpbusds", { XM
, Vex
, EXx
}, 0 },
678 /* PREFIX_EVEX_0F3852 */
681 { VEX_W_TABLE (EVEX_W_0F3852_P_1
) },
682 { "vpdpwssd", { XM
, Vex
, EXx
}, 0 },
683 { "vp4dpwssd", { XM
, Vex
, EXxmm
}, 0 },
685 /* PREFIX_EVEX_0F3853 */
689 { "vpdpwssds", { XM
, Vex
, EXx
}, 0 },
690 { "vp4dpwssds", { XM
, Vex
, EXxmm
}, 0 },
692 /* PREFIX_EVEX_0F3854 */
696 { "vpopcnt%BW", { XM
, EXx
}, 0 },
698 /* PREFIX_EVEX_0F3855 */
702 { "vpopcnt%LW", { XM
, EXx
}, 0 },
704 /* PREFIX_EVEX_0F3859 */
708 { VEX_W_TABLE (EVEX_W_0F3859_P_2
) },
710 /* PREFIX_EVEX_0F385A */
714 { VEX_W_TABLE (EVEX_W_0F385A_P_2
) },
716 /* PREFIX_EVEX_0F385B */
720 { VEX_W_TABLE (EVEX_W_0F385B_P_2
) },
722 /* PREFIX_EVEX_0F3862 */
726 { VEX_W_TABLE (EVEX_W_0F3862_P_2
) },
728 /* PREFIX_EVEX_0F3863 */
732 { VEX_W_TABLE (EVEX_W_0F3863_P_2
) },
734 /* PREFIX_EVEX_0F3864 */
738 { "vpblendm%LW", { XM
, Vex
, EXx
}, 0 },
740 /* PREFIX_EVEX_0F3865 */
744 { "vblendmp%XW", { XM
, Vex
, EXx
}, 0 },
746 /* PREFIX_EVEX_0F3866 */
750 { "vpblendm%BW", { XM
, Vex
, EXx
}, 0 },
752 /* PREFIX_EVEX_0F3868 */
757 { "vp2intersect%LW", { XMask
, Vex
, EXx
, EXxEVexS
}, 0 },
759 /* PREFIX_EVEX_0F3870 */
763 { VEX_W_TABLE (EVEX_W_0F3870_P_2
) },
765 /* PREFIX_EVEX_0F3871 */
769 { "vpshldv%LW", { XM
, Vex
, EXx
}, 0 },
771 /* PREFIX_EVEX_0F3872 */
774 { VEX_W_TABLE (EVEX_W_0F3872_P_1
) },
775 { VEX_W_TABLE (EVEX_W_0F3872_P_2
) },
776 { VEX_W_TABLE (EVEX_W_0F3872_P_3
) },
778 /* PREFIX_EVEX_0F3873 */
782 { "vpshrdv%LW", { XM
, Vex
, EXx
}, 0 },
784 /* PREFIX_EVEX_0F3875 */
788 { "vpermi2%BW", { XM
, Vex
, EXx
}, 0 },
790 /* PREFIX_EVEX_0F3876 */
794 { "vpermi2%LW", { XM
, Vex
, EXx
}, 0 },
796 /* PREFIX_EVEX_0F3877 */
800 { "vpermi2p%XW", { XM
, Vex
, EXx
}, 0 },
802 /* PREFIX_EVEX_0F387A */
806 { VEX_W_TABLE (EVEX_W_0F387A_P_2
) },
808 /* PREFIX_EVEX_0F387B */
812 { VEX_W_TABLE (EVEX_W_0F387B_P_2
) },
814 /* PREFIX_EVEX_0F387C */
818 { "vpbroadcastK", { XM
, Rdq
}, 0 },
820 /* PREFIX_EVEX_0F387D */
824 { "vpermt2%BW", { XM
, Vex
, EXx
}, 0 },
826 /* PREFIX_EVEX_0F387E */
830 { "vpermt2%LW", { XM
, Vex
, EXx
}, 0 },
832 /* PREFIX_EVEX_0F387F */
836 { "vpermt2p%XW", { XM
, Vex
, EXx
}, 0 },
838 /* PREFIX_EVEX_0F3883 */
842 { VEX_W_TABLE (EVEX_W_0F3883_P_2
) },
844 /* PREFIX_EVEX_0F3888 */
848 { "vexpandp%XW", { XM
, EXEvexXGscat
}, 0 },
850 /* PREFIX_EVEX_0F3889 */
854 { "vpexpand%LW", { XM
, EXEvexXGscat
}, 0 },
856 /* PREFIX_EVEX_0F388A */
860 { "vcompressp%XW", { EXEvexXGscat
, XM
}, 0 },
862 /* PREFIX_EVEX_0F388B */
866 { "vpcompress%LW", { EXEvexXGscat
, XM
}, 0 },
868 /* PREFIX_EVEX_0F388D */
872 { "vperm%BW", { XM
, Vex
, EXx
}, 0 },
874 /* PREFIX_EVEX_0F388F */
878 { "vpshufbitqmb", { XMask
, Vex
, EXx
}, 0 },
880 /* PREFIX_EVEX_0F3890 */
884 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
}, 0 },
886 /* PREFIX_EVEX_0F3891 */
890 { VEX_W_TABLE (EVEX_W_0F3891_P_2
) },
892 /* PREFIX_EVEX_0F3892 */
896 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
}, 0 },
898 /* PREFIX_EVEX_0F3893 */
902 { VEX_W_TABLE (EVEX_W_0F3893_P_2
) },
904 /* PREFIX_EVEX_0F389A */
908 { "vfmsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
909 { "v4fmaddps", { XM
, Vex
, Mxmm
}, 0 },
911 /* PREFIX_EVEX_0F389B */
915 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
916 { "v4fmaddss", { XMScalar
, VexScalar
, Mxmm
}, 0 },
918 /* PREFIX_EVEX_0F38A0 */
922 { "vpscatterd%LW", { MVexVSIBDWpX
, XM
}, 0 },
924 /* PREFIX_EVEX_0F38A1 */
928 { VEX_W_TABLE (EVEX_W_0F38A1_P_2
) },
930 /* PREFIX_EVEX_0F38A2 */
934 { "vscatterdp%XW", { MVexVSIBDWpX
, XM
}, 0 },
936 /* PREFIX_EVEX_0F38A3 */
940 { VEX_W_TABLE (EVEX_W_0F38A3_P_2
) },
942 /* PREFIX_EVEX_0F38AA */
946 { "vfmsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
947 { "v4fnmaddps", { XM
, Vex
, Mxmm
}, 0 },
949 /* PREFIX_EVEX_0F38AB */
953 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
954 { "v4fnmaddss", { XMScalar
, VexScalar
, Mxmm
}, 0 },
956 /* PREFIX_EVEX_0F38B4 */
960 { "vpmadd52luq", { XM
, Vex
, EXx
}, 0 },
962 /* PREFIX_EVEX_0F38B5 */
966 { "vpmadd52huq", { XM
, Vex
, EXx
}, 0 },
968 /* PREFIX_EVEX_0F38C4 */
972 { "vpconflict%LW", { XM
, EXx
}, 0 },
974 /* PREFIX_EVEX_0F38C6_REG_1 */
978 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_1_PREFIX_2
) },
980 /* PREFIX_EVEX_0F38C6_REG_2 */
984 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_2_PREFIX_2
) },
986 /* PREFIX_EVEX_0F38C6_REG_5 */
990 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_5_PREFIX_2
) },
992 /* PREFIX_EVEX_0F38C6_REG_6 */
996 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_6_PREFIX_2
) },
998 /* PREFIX_EVEX_0F38C7_REG_1 */
1002 { VEX_W_TABLE (EVEX_W_0F38C7_R_1_P_2
) },
1004 /* PREFIX_EVEX_0F38C7_REG_2 */
1008 { VEX_W_TABLE (EVEX_W_0F38C7_R_2_P_2
) },
1010 /* PREFIX_EVEX_0F38C7_REG_5 */
1014 { VEX_W_TABLE (EVEX_W_0F38C7_R_5_P_2
) },
1016 /* PREFIX_EVEX_0F38C7_REG_6 */
1020 { VEX_W_TABLE (EVEX_W_0F38C7_R_6_P_2
) },
1022 /* PREFIX_EVEX_0F38C8 */
1026 { "vexp2p%XW", { XM
, EXx
, EXxEVexS
}, 0 },
1028 /* PREFIX_EVEX_0F38CA */
1032 { "vrcp28p%XW", { XM
, EXx
, EXxEVexS
}, 0 },
1034 /* PREFIX_EVEX_0F38CB */
1038 { "vrcp28s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
}, 0 },
1040 /* PREFIX_EVEX_0F38CC */
1044 { "vrsqrt28p%XW", { XM
, EXx
, EXxEVexS
}, 0 },
1046 /* PREFIX_EVEX_0F38CD */
1050 { "vrsqrt28s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
}, 0 },
1052 /* PREFIX_EVEX_0F3A00 */
1056 { VEX_W_TABLE (EVEX_W_0F3A00_P_2
) },
1058 /* PREFIX_EVEX_0F3A01 */
1062 { VEX_W_TABLE (EVEX_W_0F3A01_P_2
) },
1064 /* PREFIX_EVEX_0F3A03 */
1068 { "valign%LW", { XM
, Vex
, EXx
, Ib
}, 0 },
1070 /* PREFIX_EVEX_0F3A05 */
1074 { VEX_W_TABLE (EVEX_W_0F3A05_P_2
) },
1076 /* PREFIX_EVEX_0F3A08 */
1080 { VEX_W_TABLE (EVEX_W_0F3A08_P_2
) },
1082 /* PREFIX_EVEX_0F3A09 */
1086 { VEX_W_TABLE (EVEX_W_0F3A09_P_2
) },
1088 /* PREFIX_EVEX_0F3A0A */
1092 { VEX_W_TABLE (EVEX_W_0F3A0A_P_2
) },
1094 /* PREFIX_EVEX_0F3A0B */
1098 { VEX_W_TABLE (EVEX_W_0F3A0B_P_2
) },
1100 /* PREFIX_EVEX_0F3A14 */
1104 { EVEX_LEN_TABLE (EVEX_LEN_0F3A14_P_2
) },
1106 /* PREFIX_EVEX_0F3A15 */
1110 { EVEX_LEN_TABLE (EVEX_LEN_0F3A15_P_2
) },
1112 /* PREFIX_EVEX_0F3A16 */
1116 { EVEX_LEN_TABLE (EVEX_LEN_0F3A16_P_2
) },
1118 /* PREFIX_EVEX_0F3A17 */
1122 { EVEX_LEN_TABLE (EVEX_LEN_0F3A17_P_2
) },
1124 /* PREFIX_EVEX_0F3A18 */
1128 { VEX_W_TABLE (EVEX_W_0F3A18_P_2
) },
1130 /* PREFIX_EVEX_0F3A19 */
1134 { VEX_W_TABLE (EVEX_W_0F3A19_P_2
) },
1136 /* PREFIX_EVEX_0F3A1A */
1140 { VEX_W_TABLE (EVEX_W_0F3A1A_P_2
) },
1142 /* PREFIX_EVEX_0F3A1B */
1146 { VEX_W_TABLE (EVEX_W_0F3A1B_P_2
) },
1148 /* PREFIX_EVEX_0F3A1E */
1152 { "vpcmpu%LW", { XMask
, Vex
, EXx
, VPCMP
}, 0 },
1154 /* PREFIX_EVEX_0F3A1F */
1158 { "vpcmp%LW", { XMask
, Vex
, EXx
, VPCMP
}, 0 },
1160 /* PREFIX_EVEX_0F3A20 */
1164 { EVEX_LEN_TABLE (EVEX_LEN_0F3A20_P_2
) },
1166 /* PREFIX_EVEX_0F3A21 */
1170 { VEX_W_TABLE (EVEX_W_0F3A21_P_2
) },
1172 /* PREFIX_EVEX_0F3A22 */
1176 { EVEX_LEN_TABLE (EVEX_LEN_0F3A22_P_2
) },
1178 /* PREFIX_EVEX_0F3A23 */
1182 { VEX_W_TABLE (EVEX_W_0F3A23_P_2
) },
1184 /* PREFIX_EVEX_0F3A25 */
1188 { "vpternlog%LW", { XM
, Vex
, EXx
, Ib
}, 0 },
1190 /* PREFIX_EVEX_0F3A26 */
1194 { "vgetmantp%XW", { XM
, EXx
, EXxEVexS
, Ib
}, 0 },
1196 /* PREFIX_EVEX_0F3A27 */
1200 { "vgetmants%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
, Ib
}, 0 },
1202 /* PREFIX_EVEX_0F3A38 */
1206 { VEX_W_TABLE (EVEX_W_0F3A38_P_2
) },
1208 /* PREFIX_EVEX_0F3A39 */
1212 { VEX_W_TABLE (EVEX_W_0F3A39_P_2
) },
1214 /* PREFIX_EVEX_0F3A3A */
1218 { VEX_W_TABLE (EVEX_W_0F3A3A_P_2
) },
1220 /* PREFIX_EVEX_0F3A3B */
1224 { VEX_W_TABLE (EVEX_W_0F3A3B_P_2
) },
1226 /* PREFIX_EVEX_0F3A3E */
1230 { "vpcmpu%BW", { XMask
, Vex
, EXx
, VPCMP
}, 0 },
1232 /* PREFIX_EVEX_0F3A3F */
1236 { "vpcmp%BW", { XMask
, Vex
, EXx
, VPCMP
}, 0 },
1238 /* PREFIX_EVEX_0F3A42 */
1242 { VEX_W_TABLE (EVEX_W_0F3A42_P_2
) },
1244 /* PREFIX_EVEX_0F3A43 */
1248 { VEX_W_TABLE (EVEX_W_0F3A43_P_2
) },
1250 /* PREFIX_EVEX_0F3A50 */
1254 { "vrangep%XW", { XM
, Vex
, EXx
, EXxEVexS
, Ib
}, 0 },
1256 /* PREFIX_EVEX_0F3A51 */
1260 { "vranges%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
, Ib
}, 0 },
1262 /* PREFIX_EVEX_0F3A54 */
1266 { "vfixupimmp%XW", { XM
, Vex
, EXx
, EXxEVexS
, Ib
}, 0 },
1268 /* PREFIX_EVEX_0F3A55 */
1272 { "vfixupimms%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
, Ib
}, 0 },
1274 /* PREFIX_EVEX_0F3A56 */
1278 { "vreducep%XW", { XM
, EXx
, EXxEVexS
, Ib
}, 0 },
1280 /* PREFIX_EVEX_0F3A57 */
1284 { "vreduces%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
, Ib
}, 0 },
1286 /* PREFIX_EVEX_0F3A66 */
1290 { "vfpclassp%XW%XZ", { XMask
, EXx
, Ib
}, 0 },
1292 /* PREFIX_EVEX_0F3A67 */
1296 { "vfpclasss%XW", { XMask
, EXVexWdqScalar
, Ib
}, 0 },
1298 /* PREFIX_EVEX_0F3A70 */
1302 { VEX_W_TABLE (EVEX_W_0F3A70_P_2
) },
1304 /* PREFIX_EVEX_0F3A71 */
1308 { "vpshld%LW", { XM
, Vex
, EXx
, Ib
}, 0 },
1310 /* PREFIX_EVEX_0F3A72 */
1314 { VEX_W_TABLE (EVEX_W_0F3A72_P_2
) },
1316 /* PREFIX_EVEX_0F3A73 */
1320 { "vpshrd%LW", { XM
, Vex
, EXx
, Ib
}, 0 },