opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int fetch_data (struct disassemble_info *, bfd_byte *);
  46 static void ckprefix (void);
  47 static const char *prefix_name (int, int);
  48 static int print_insn (bfd_vma, disassemble_info *);
  49 static void dofloat (int);
  50 static void OP_ST (int, int);
  51 static void OP_STi (int, int);
  52 static int putop (const char *, int);
  53 static void oappend (const char *);
  54 static void append_seg (void);
  55 static void OP_indirE (int, int);
  56 static void print_operand_value (char *, int, bfd_vma);
  57 static void OP_E_register (int, int);
  58 static void OP_E_memory (int, int, int);
  59 static void OP_E_extended (int, int, int);
  60 static void print_displacement (char *, bfd_vma);
  61 static void OP_E (int, int);
  62 static void OP_G (int, int);
  63 static bfd_vma get64 (void);
  64 static bfd_signed_vma get32 (void);
  65 static bfd_signed_vma get32s (void);
  66 static int get16 (void);
  67 static void set_op (bfd_vma, int);
  68 static void OP_Skip_MODRM (int, int);
  69 static void OP_REG (int, int);
  70 static void OP_IMREG (int, int);
  71 static void OP_I (int, int);
  72 static void OP_I64 (int, int);
  73 static void OP_sI (int, int);
  74 static void OP_J (int, int);
  75 static void OP_SEG (int, int);
  76 static void OP_DIR (int, int);
  77 static void OP_OFF (int, int);
  78 static void OP_OFF64 (int, int);
  79 static void ptr_reg (int, int);
  80 static void OP_ESreg (int, int);
  81 static void OP_DSreg (int, int);
  82 static void OP_C (int, int);
  83 static void OP_D (int, int);
  84 static void OP_T (int, int);
  85 static void OP_R (int, int);
  86 static void OP_MMX (int, int);
  87 static void OP_XMM (int, int);
  88 static void OP_EM (int, int);
  89 static void OP_EX (int, int);
  90 static void OP_EMC (int,int);
  91 static void OP_MXC (int,int);
  92 static void OP_MS (int, int);
  93 static void OP_XS (int, int);
  94 static void OP_M (int, int);
  95 static void OP_VEX (int, int);
  96 static void OP_VEX_FMA (int, int);
  97 static void OP_EX_Vex (int, int);
  98 static void OP_EX_VexW (int, int);
  99 static void OP_EX_VexImmW (int, int);
 100 static void OP_XMM_Vex (int, int);
 101 static void OP_XMM_VexW (int, int);
 102 static void OP_REG_VexI4 (int, int);
 103 static void PCLMUL_Fixup (int, int);
 104 static void VEXI4_Fixup (int, int);
 105 static void VZERO_Fixup (int, int);
 106 static void VCMP_Fixup (int, int);
 107 static void VPERMIL2_Fixup (int, int);
 108 static void OP_0f07 (int, int);
 109 static void OP_Monitor (int, int);
 110 static void OP_Mwait (int, int);
 111 static void NOP_Fixup1 (int, int);
 112 static void NOP_Fixup2 (int, int);
 113 static void OP_3DNowSuffix (int, int);
 114 static void CMP_Fixup (int, int);
 115 static void BadOp (void);
 116 static void REP_Fixup (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void print_drex_arg (unsigned int, int, int);
 121 static void OP_DREX4 (int, int);
 122 static void OP_DREX3 (int, int);
 123 static void OP_DREX_ICMP (int, int);
 124 static void OP_DREX_FCMP (int, int);
 125 static void MOVBE_Fixup (int, int);
 126
 127 struct dis_private {
 128   /* Points to first byte not fetched.  */
 129   bfd_byte *max_fetched;
 130   bfd_byte the_buffer[MAX_MNEM_SIZE];
 131   bfd_vma insn_start;
 132   int orig_sizeflag;
 133   jmp_buf bailout;
 134 };
 135
 136 enum address_mode
 137 {
 138   mode_16bit,
 139   mode_32bit,
 140   mode_64bit
 141 };
 142
 143 enum address_mode address_mode;
 144
 145 /* Flags for the prefixes for the current instruction.  See below.  */
 146 static int prefixes;
 147
 148 /* REX prefix the current instruction.  See below.  */
 149 static int rex;
 150 /* Bits of REX we've already used.  */
 151 static int rex_used;
 152 /* Original REX prefix.  */
 153 static int rex_original;
 154 /* REX bits in original REX prefix ignored.  It may not be the same
 155    as rex_original since some bits may not be ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Special 'registers' for DREX handling */
 173 #define DREX_REG_UNKNOWN        1000    /* not initialized */
 174 #define DREX_REG_MEMORY         1001    /* use MODRM/SIB/OFFSET memory */
 175
 176 /* The DREX byte has the following fields:
 177    Bits 7-4 -- DREX.Dest, xmm destination register
 178    Bit 3    -- DREX.OC0, operand config bit defines operand order
 179    Bit 2    -- DREX.R, equivalent to REX_R bit, to extend ModRM register
 180    Bit 1    -- DREX.X, equivalent to REX_X bit, to extend SIB index field
 181    Bit 0    -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
 182                SIB base field, or opcode reg field.  */
 183 #define DREX_XMM(drex) ((drex >> 4) & 0xf)
 184 #define DREX_OC0(drex) ((drex >> 3) & 0x1)
 185
 186 /* Flags for prefixes which we somehow handled when printing the
 187    current instruction.  */
 188 static int used_prefixes;
 189
 190 /* Flags stored in PREFIXES.  */
 191 #define PREFIX_REPZ 1
 192 #define PREFIX_REPNZ 2
 193 #define PREFIX_LOCK 4
 194 #define PREFIX_CS 8
 195 #define PREFIX_SS 0x10
 196 #define PREFIX_DS 0x20
 197 #define PREFIX_ES 0x40
 198 #define PREFIX_FS 0x80
 199 #define PREFIX_GS 0x100
 200 #define PREFIX_DATA 0x200
 201 #define PREFIX_ADDR 0x400
 202 #define PREFIX_FWAIT 0x800
 203
 204 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 205    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 206    on error.  */
 207 #define FETCH_DATA(info, addr) \
 208   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 209    ? 1 : fetch_data ((info), (addr)))
 210
 211 static int
 212 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 213 {
 214   int status;
 215   struct dis_private *priv = (struct dis_private *) info->private_data;
 216   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 217
 218   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 219     status = (*info->read_memory_func) (start,
 220                                         priv->max_fetched,
 221                                         addr - priv->max_fetched,
 222                                         info);
 223   else
 224     status = -1;
 225   if (status != 0)
 226     {
 227       /* If we did manage to read at least one byte, then
 228          print_insn_i386 will do something sensible.  Otherwise, print
 229          an error.  We do that here because this is where we know
 230          STATUS.  */
 231       if (priv->max_fetched == priv->the_buffer)
 232         (*info->memory_error_func) (status, start, info);
 233       longjmp (priv->bailout, 1);
 234     }
 235   else
 236     priv->max_fetched = addr;
 237   return 1;
 238 }
 239
 240 #define XX { NULL, 0 }
 241
 242 #define Eb { OP_E, b_mode }
 243 #define Ev { OP_E, v_mode }
 244 #define Ed { OP_E, d_mode }
 245 #define Edq { OP_E, dq_mode }
 246 #define Edqw { OP_E, dqw_mode }
 247 #define Edqb { OP_E, dqb_mode }
 248 #define Edqd { OP_E, dqd_mode }
 249 #define Eq { OP_E, q_mode }
 250 #define indirEv { OP_indirE, stack_v_mode }
 251 #define indirEp { OP_indirE, f_mode }
 252 #define stackEv { OP_E, stack_v_mode }
 253 #define Em { OP_E, m_mode }
 254 #define Ew { OP_E, w_mode }
 255 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 256 #define Ma { OP_M, a_mode }
 257 #define Mb { OP_M, b_mode }
 258 #define Md { OP_M, d_mode }
 259 #define Mo { OP_M, o_mode }
 260 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 261 #define Mq { OP_M, q_mode }
 262 #define Mx { OP_M, x_mode }
 263 #define Mxmm { OP_M, xmm_mode }
 264 #define Gb { OP_G, b_mode }
 265 #define Gv { OP_G, v_mode }
 266 #define Gd { OP_G, d_mode }
 267 #define Gdq { OP_G, dq_mode }
 268 #define Gm { OP_G, m_mode }
 269 #define Gw { OP_G, w_mode }
 270 #define Rd { OP_R, d_mode }
 271 #define Rm { OP_R, m_mode }
 272 #define Ib { OP_I, b_mode }
 273 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 274 #define Iv { OP_I, v_mode }
 275 #define Iq { OP_I, q_mode }
 276 #define Iv64 { OP_I64, v_mode }
 277 #define Iw { OP_I, w_mode }
 278 #define I1 { OP_I, const_1_mode }
 279 #define Jb { OP_J, b_mode }
 280 #define Jv { OP_J, v_mode }
 281 #define Cm { OP_C, m_mode }
 282 #define Dm { OP_D, m_mode }
 283 #define Td { OP_T, d_mode }
 284 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 285
 286 #define RMeAX { OP_REG, eAX_reg }
 287 #define RMeBX { OP_REG, eBX_reg }
 288 #define RMeCX { OP_REG, eCX_reg }
 289 #define RMeDX { OP_REG, eDX_reg }
 290 #define RMeSP { OP_REG, eSP_reg }
 291 #define RMeBP { OP_REG, eBP_reg }
 292 #define RMeSI { OP_REG, eSI_reg }
 293 #define RMeDI { OP_REG, eDI_reg }
 294 #define RMrAX { OP_REG, rAX_reg }
 295 #define RMrBX { OP_REG, rBX_reg }
 296 #define RMrCX { OP_REG, rCX_reg }
 297 #define RMrDX { OP_REG, rDX_reg }
 298 #define RMrSP { OP_REG, rSP_reg }
 299 #define RMrBP { OP_REG, rBP_reg }
 300 #define RMrSI { OP_REG, rSI_reg }
 301 #define RMrDI { OP_REG, rDI_reg }
 302 #define RMAL { OP_REG, al_reg }
 303 #define RMAL { OP_REG, al_reg }
 304 #define RMCL { OP_REG, cl_reg }
 305 #define RMDL { OP_REG, dl_reg }
 306 #define RMBL { OP_REG, bl_reg }
 307 #define RMAH { OP_REG, ah_reg }
 308 #define RMCH { OP_REG, ch_reg }
 309 #define RMDH { OP_REG, dh_reg }
 310 #define RMBH { OP_REG, bh_reg }
 311 #define RMAX { OP_REG, ax_reg }
 312 #define RMDX { OP_REG, dx_reg }
 313
 314 #define eAX { OP_IMREG, eAX_reg }
 315 #define eBX { OP_IMREG, eBX_reg }
 316 #define eCX { OP_IMREG, eCX_reg }
 317 #define eDX { OP_IMREG, eDX_reg }
 318 #define eSP { OP_IMREG, eSP_reg }
 319 #define eBP { OP_IMREG, eBP_reg }
 320 #define eSI { OP_IMREG, eSI_reg }
 321 #define eDI { OP_IMREG, eDI_reg }
 322 #define AL { OP_IMREG, al_reg }
 323 #define CL { OP_IMREG, cl_reg }
 324 #define DL { OP_IMREG, dl_reg }
 325 #define BL { OP_IMREG, bl_reg }
 326 #define AH { OP_IMREG, ah_reg }
 327 #define CH { OP_IMREG, ch_reg }
 328 #define DH { OP_IMREG, dh_reg }
 329 #define BH { OP_IMREG, bh_reg }
 330 #define AX { OP_IMREG, ax_reg }
 331 #define DX { OP_IMREG, dx_reg }
 332 #define zAX { OP_IMREG, z_mode_ax_reg }
 333 #define indirDX { OP_IMREG, indir_dx_reg }
 334
 335 #define Sw { OP_SEG, w_mode }
 336 #define Sv { OP_SEG, v_mode }
 337 #define Ap { OP_DIR, 0 }
 338 #define Ob { OP_OFF64, b_mode }
 339 #define Ov { OP_OFF64, v_mode }
 340 #define Xb { OP_DSreg, eSI_reg }
 341 #define Xv { OP_DSreg, eSI_reg }
 342 #define Xz { OP_DSreg, eSI_reg }
 343 #define Yb { OP_ESreg, eDI_reg }
 344 #define Yv { OP_ESreg, eDI_reg }
 345 #define DSBX { OP_DSreg, eBX_reg }
 346
 347 #define es { OP_REG, es_reg }
 348 #define ss { OP_REG, ss_reg }
 349 #define cs { OP_REG, cs_reg }
 350 #define ds { OP_REG, ds_reg }
 351 #define fs { OP_REG, fs_reg }
 352 #define gs { OP_REG, gs_reg }
 353
 354 #define MX { OP_MMX, 0 }
 355 #define XM { OP_XMM, 0 }
 356 #define XMM { OP_XMM, xmm_mode }
 357 #define EM { OP_EM, v_mode }
 358 #define EMd { OP_EM, d_mode }
 359 #define EMx { OP_EM, x_mode }
 360 #define EXw { OP_EX, w_mode }
 361 #define EXd { OP_EX, d_mode }
 362 #define EXq { OP_EX, q_mode }
 363 #define EXx { OP_EX, x_mode }
 364 #define EXxmm { OP_EX, xmm_mode }
 365 #define EXxmmq { OP_EX, xmmq_mode }
 366 #define EXymmq { OP_EX, ymmq_mode }
 367 #define MS { OP_MS, v_mode }
 368 #define XS { OP_XS, v_mode }
 369 #define EMCq { OP_EMC, q_mode }
 370 #define MXC { OP_MXC, 0 }
 371 #define OPSUF { OP_3DNowSuffix, 0 }
 372 #define CMP { CMP_Fixup, 0 }
 373 #define XMM0 { XMM_Fixup, 0 }
 374
 375 #define Vex { OP_VEX, vex_mode }
 376 #define Vex128 { OP_VEX, vex128_mode }
 377 #define Vex256 { OP_VEX, vex256_mode }
 378 #define VexI4 { VEXI4_Fixup, 0}
 379 #define VexFMA { OP_VEX_FMA, vex_mode }
 380 #define Vex128FMA { OP_VEX_FMA, vex128_mode }
 381 #define EXdVex { OP_EX_Vex, d_mode }
 382 #define EXqVex { OP_EX_Vex, q_mode }
 383 #define EXVexW { OP_EX_VexW, x_mode }
 384 #define EXdVexW { OP_EX_VexW, d_mode }
 385 #define EXqVexW { OP_EX_VexW, q_mode }
 386 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 387 #define XMVex { OP_XMM_Vex, 0 }
 388 #define XMVexW { OP_XMM_VexW, 0 }
 389 #define XMVexI4 { OP_REG_VexI4, x_mode }
 390 #define PCLMUL { PCLMUL_Fixup, 0 }
 391 #define VZERO { VZERO_Fixup, 0 }
 392 #define VCMP { VCMP_Fixup, 0 }
 393 #define VPERMIL2 { VPERMIL2_Fixup, 0 }
 394
 395 /* Used handle "rep" prefix for string instructions.  */
 396 #define Xbr { REP_Fixup, eSI_reg }
 397 #define Xvr { REP_Fixup, eSI_reg }
 398 #define Ybr { REP_Fixup, eDI_reg }
 399 #define Yvr { REP_Fixup, eDI_reg }
 400 #define Yzr { REP_Fixup, eDI_reg }
 401 #define indirDXr { REP_Fixup, indir_dx_reg }
 402 #define ALr { REP_Fixup, al_reg }
 403 #define eAXr { REP_Fixup, eAX_reg }
 404
 405 #define cond_jump_flag { NULL, cond_jump_mode }
 406 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 407
 408 /* bits in sizeflag */
 409 #define SUFFIX_ALWAYS 4
 410 #define AFLAG 2
 411 #define DFLAG 1
 412
 413 /* byte operand */
 414 #define b_mode                  1
 415 /* operand size depends on prefixes */
 416 #define v_mode                  (b_mode + 1)
 417 /* word operand */
 418 #define w_mode                  (v_mode + 1)
 419 /* double word operand  */
 420 #define d_mode                  (w_mode + 1)
 421 /* quad word operand */
 422 #define q_mode                  (d_mode + 1)
 423 /* ten-byte operand */
 424 #define t_mode                  (q_mode + 1)
 425 /* 16-byte XMM or 32-byte YMM operand */
 426 #define x_mode                  (t_mode + 1)
 427 /* 16-byte XMM operand */
 428 #define xmm_mode                (x_mode + 1)
 429 /* 16-byte XMM or quad word operand */
 430 #define xmmq_mode               (xmm_mode + 1)
 431 /* 32-byte YMM or quad word operand */
 432 #define ymmq_mode               (xmmq_mode + 1)
 433 /* d_mode in 32bit, q_mode in 64bit mode.  */
 434 #define m_mode                  (ymmq_mode + 1)
 435 /* pair of v_mode operands */
 436 #define a_mode                  (m_mode + 1)
 437 #define cond_jump_mode          (a_mode + 1)
 438 #define loop_jcxz_mode          (cond_jump_mode + 1)
 439 /* operand size depends on REX prefixes.  */
 440 #define dq_mode                 (loop_jcxz_mode + 1)
 441 /* registers like dq_mode, memory like w_mode.  */
 442 #define dqw_mode                (dq_mode + 1)
 443 /* 4- or 6-byte pointer operand */
 444 #define f_mode                  (dqw_mode + 1)
 445 #define const_1_mode            (f_mode + 1)
 446 /* v_mode for stack-related opcodes.  */
 447 #define stack_v_mode            (const_1_mode + 1)
 448 /* non-quad operand size depends on prefixes */
 449 #define z_mode                  (stack_v_mode + 1)
 450 /* 16-byte operand */
 451 #define o_mode                  (z_mode + 1)
 452 /* registers like dq_mode, memory like b_mode.  */
 453 #define dqb_mode                (o_mode + 1)
 454 /* registers like dq_mode, memory like d_mode.  */
 455 #define dqd_mode                (dqb_mode + 1)
 456 /* normal vex mode */
 457 #define vex_mode                (dqd_mode + 1)
 458 /* 128bit vex mode */
 459 #define vex128_mode             (vex_mode + 1)
 460 /* 256bit vex mode */
 461 #define vex256_mode             (vex128_mode + 1)
 462
 463 #define es_reg                  (vex256_mode + 1)
 464 #define cs_reg                  (es_reg + 1)
 465 #define ss_reg                  (cs_reg + 1)
 466 #define ds_reg                  (ss_reg + 1)
 467 #define fs_reg                  (ds_reg + 1)
 468 #define gs_reg                  (fs_reg + 1)
 469
 470 #define eAX_reg                 (gs_reg + 1)
 471 #define eCX_reg                 (eAX_reg + 1)
 472 #define eDX_reg                 (eCX_reg + 1)
 473 #define eBX_reg                 (eDX_reg + 1)
 474 #define eSP_reg                 (eBX_reg + 1)
 475 #define eBP_reg                 (eSP_reg + 1)
 476 #define eSI_reg                 (eBP_reg + 1)
 477 #define eDI_reg                 (eSI_reg + 1)
 478
 479 #define al_reg                  (eDI_reg + 1)
 480 #define cl_reg                  (al_reg + 1)
 481 #define dl_reg                  (cl_reg + 1)
 482 #define bl_reg                  (dl_reg + 1)
 483 #define ah_reg                  (bl_reg + 1)
 484 #define ch_reg                  (ah_reg + 1)
 485 #define dh_reg                  (ch_reg + 1)
 486 #define bh_reg                  (dh_reg + 1)
 487
 488 #define ax_reg                  (bh_reg + 1)
 489 #define cx_reg                  (ax_reg + 1)
 490 #define dx_reg                  (cx_reg + 1)
 491 #define bx_reg                  (dx_reg + 1)
 492 #define sp_reg                  (bx_reg + 1)
 493 #define bp_reg                  (sp_reg + 1)
 494 #define si_reg                  (bp_reg + 1)
 495 #define di_reg                  (si_reg + 1)
 496
 497 #define rAX_reg                 (di_reg + 1)
 498 #define rCX_reg                 (rAX_reg + 1)
 499 #define rDX_reg                 (rCX_reg + 1)
 500 #define rBX_reg                 (rDX_reg + 1)
 501 #define rSP_reg                 (rBX_reg + 1)
 502 #define rBP_reg                 (rSP_reg + 1)
 503 #define rSI_reg                 (rBP_reg + 1)
 504 #define rDI_reg                 (rSI_reg + 1)
 505
 506 #define z_mode_ax_reg           (rDI_reg + 1)
 507 #define indir_dx_reg            (z_mode_ax_reg + 1)
 508
 509 #define MAX_BYTEMODE    indir_dx_reg
 510
 511 /* Flags that are OR'ed into the bytemode field to pass extra
 512    information.  */
 513 #define DREX_OC1                0x10000 /* OC1 bit set */
 514 #define DREX_NO_OC0             0x20000 /* OC0 bit not used */
 515 #define DREX_MASK               0x40000 /* mask to delete */
 516
 517 #if MAX_BYTEMODE >= DREX_OC1
 518 #error MAX_BYTEMODE must be less than DREX_OC1
 519 #endif
 520
 521 #define FLOATCODE               1
 522 #define USE_REG_TABLE           (FLOATCODE + 1)
 523 #define USE_MOD_TABLE           (USE_REG_TABLE + 1)
 524 #define USE_RM_TABLE            (USE_MOD_TABLE + 1)
 525 #define USE_PREFIX_TABLE        (USE_RM_TABLE + 1)
 526 #define USE_X86_64_TABLE        (USE_PREFIX_TABLE + 1)
 527 #define USE_3BYTE_TABLE         (USE_X86_64_TABLE + 1)
 528 #define USE_VEX_C4_TABLE        (USE_3BYTE_TABLE + 1)
 529 #define USE_VEX_C5_TABLE        (USE_VEX_C4_TABLE + 1)
 530 #define USE_VEX_LEN_TABLE       (USE_VEX_C5_TABLE + 1)
 531
 532 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 533
 534 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 535 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 536 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 537 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 538 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 539 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 540 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 541 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 542 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 543 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 544
 545 #define REG_80                  0
 546 #define REG_81                  (REG_80 + 1)
 547 #define REG_82                  (REG_81 + 1)
 548 #define REG_8F                  (REG_82 + 1)
 549 #define REG_C0                  (REG_8F + 1)
 550 #define REG_C1                  (REG_C0 + 1)
 551 #define REG_C6                  (REG_C1 + 1)
 552 #define REG_C7                  (REG_C6 + 1)
 553 #define REG_D0                  (REG_C7 + 1)
 554 #define REG_D1                  (REG_D0 + 1)
 555 #define REG_D2                  (REG_D1 + 1)
 556 #define REG_D3                  (REG_D2 + 1)
 557 #define REG_F6                  (REG_D3 + 1)
 558 #define REG_F7                  (REG_F6 + 1)
 559 #define REG_FE                  (REG_F7 + 1)
 560 #define REG_FF                  (REG_FE + 1)
 561 #define REG_0F00                (REG_FF + 1)
 562 #define REG_0F01                (REG_0F00 + 1)
 563 #define REG_0F0D                (REG_0F01 + 1)
 564 #define REG_0F18                (REG_0F0D + 1)
 565 #define REG_0F71                (REG_0F18 + 1)
 566 #define REG_0F72                (REG_0F71 + 1)
 567 #define REG_0F73                (REG_0F72 + 1)
 568 #define REG_0FA6                (REG_0F73 + 1)
 569 #define REG_0FA7                (REG_0FA6 + 1)
 570 #define REG_0FAE                (REG_0FA7 + 1)
 571 #define REG_0FBA                (REG_0FAE + 1)
 572 #define REG_0FC7                (REG_0FBA + 1)
 573 #define REG_VEX_71              (REG_0FC7 + 1)
 574 #define REG_VEX_72              (REG_VEX_71 + 1)
 575 #define REG_VEX_73              (REG_VEX_72 + 1)
 576 #define REG_VEX_AE              (REG_VEX_73 + 1)
 577
 578 #define MOD_8D                  0
 579 #define MOD_0F01_REG_0          (MOD_8D + 1)
 580 #define MOD_0F01_REG_1          (MOD_0F01_REG_0 + 1)
 581 #define MOD_0F01_REG_2          (MOD_0F01_REG_1 + 1)
 582 #define MOD_0F01_REG_3          (MOD_0F01_REG_2 + 1)
 583 #define MOD_0F01_REG_7          (MOD_0F01_REG_3 + 1)
 584 #define MOD_0F12_PREFIX_0       (MOD_0F01_REG_7 + 1)
 585 #define MOD_0F13                (MOD_0F12_PREFIX_0 + 1)
 586 #define MOD_0F16_PREFIX_0       (MOD_0F13 + 1)
 587 #define MOD_0F17                (MOD_0F16_PREFIX_0 + 1)
 588 #define MOD_0F18_REG_0          (MOD_0F17 + 1)
 589 #define MOD_0F18_REG_1          (MOD_0F18_REG_0 + 1)
 590 #define MOD_0F18_REG_2          (MOD_0F18_REG_1 + 1)
 591 #define MOD_0F18_REG_3          (MOD_0F18_REG_2 + 1)
 592 #define MOD_0F20                (MOD_0F18_REG_3 + 1)
 593 #define MOD_0F21                (MOD_0F20 + 1)
 594 #define MOD_0F22                (MOD_0F21 + 1)
 595 #define MOD_0F23                (MOD_0F22 + 1)
 596 #define MOD_0F24                (MOD_0F23 + 1)
 597 #define MOD_0F26                (MOD_0F24 + 1)
 598 #define MOD_0F2B_PREFIX_0       (MOD_0F26 + 1)
 599 #define MOD_0F2B_PREFIX_1       (MOD_0F2B_PREFIX_0 + 1)
 600 #define MOD_0F2B_PREFIX_2       (MOD_0F2B_PREFIX_1 + 1)
 601 #define MOD_0F2B_PREFIX_3       (MOD_0F2B_PREFIX_2 + 1)
 602 #define MOD_0F51                (MOD_0F2B_PREFIX_3 + 1)
 603 #define MOD_0F71_REG_2          (MOD_0F51 + 1)
 604 #define MOD_0F71_REG_4          (MOD_0F71_REG_2 + 1)
 605 #define MOD_0F71_REG_6          (MOD_0F71_REG_4 + 1)
 606 #define MOD_0F72_REG_2          (MOD_0F71_REG_6 + 1)
 607 #define MOD_0F72_REG_4          (MOD_0F72_REG_2 + 1)
 608 #define MOD_0F72_REG_6          (MOD_0F72_REG_4 + 1)
 609 #define MOD_0F73_REG_2          (MOD_0F72_REG_6 + 1)
 610 #define MOD_0F73_REG_3          (MOD_0F73_REG_2 + 1)
 611 #define MOD_0F73_REG_6          (MOD_0F73_REG_3 + 1)
 612 #define MOD_0F73_REG_7          (MOD_0F73_REG_6 + 1)
 613 #define MOD_0FAE_REG_0          (MOD_0F73_REG_7 + 1)
 614 #define MOD_0FAE_REG_1          (MOD_0FAE_REG_0 + 1)
 615 #define MOD_0FAE_REG_2          (MOD_0FAE_REG_1 + 1)
 616 #define MOD_0FAE_REG_3          (MOD_0FAE_REG_2 + 1)
 617 #define MOD_0FAE_REG_4          (MOD_0FAE_REG_3 + 1)
 618 #define MOD_0FAE_REG_5          (MOD_0FAE_REG_4 + 1)
 619 #define MOD_0FAE_REG_6          (MOD_0FAE_REG_5 + 1)
 620 #define MOD_0FAE_REG_7          (MOD_0FAE_REG_6 + 1)
 621 #define MOD_0FB2                (MOD_0FAE_REG_7 + 1)
 622 #define MOD_0FB4                (MOD_0FB2 + 1)
 623 #define MOD_0FB5                (MOD_0FB4 + 1)
 624 #define MOD_0FC7_REG_6          (MOD_0FB5 + 1)
 625 #define MOD_0FC7_REG_7          (MOD_0FC7_REG_6 + 1)
 626 #define MOD_0FD7                (MOD_0FC7_REG_7 + 1)
 627 #define MOD_0FE7_PREFIX_2       (MOD_0FD7 + 1)
 628 #define MOD_0FF0_PREFIX_3       (MOD_0FE7_PREFIX_2 + 1)
 629 #define MOD_0F382A_PREFIX_2     (MOD_0FF0_PREFIX_3 + 1)
 630 #define MOD_62_32BIT            (MOD_0F382A_PREFIX_2 + 1)
 631 #define MOD_C4_32BIT            (MOD_62_32BIT + 1)
 632 #define MOD_C5_32BIT            (MOD_C4_32BIT + 1)
 633 #define MOD_VEX_12_PREFIX_0     (MOD_C5_32BIT + 1)
 634 #define MOD_VEX_13              (MOD_VEX_12_PREFIX_0 + 1)
 635 #define MOD_VEX_16_PREFIX_0     (MOD_VEX_13 + 1)
 636 #define MOD_VEX_17              (MOD_VEX_16_PREFIX_0 + 1)
 637 #define MOD_VEX_2B              (MOD_VEX_17 + 1)
 638 #define MOD_VEX_51              (MOD_VEX_2B + 1)
 639 #define MOD_VEX_71_REG_2        (MOD_VEX_51 + 1)
 640 #define MOD_VEX_71_REG_4        (MOD_VEX_71_REG_2 + 1)
 641 #define MOD_VEX_71_REG_6        (MOD_VEX_71_REG_4 + 1)
 642 #define MOD_VEX_72_REG_2        (MOD_VEX_71_REG_6 + 1)
 643 #define MOD_VEX_72_REG_4        (MOD_VEX_72_REG_2 + 1)
 644 #define MOD_VEX_72_REG_6        (MOD_VEX_72_REG_4 + 1)
 645 #define MOD_VEX_73_REG_2        (MOD_VEX_72_REG_6 + 1)
 646 #define MOD_VEX_73_REG_3        (MOD_VEX_73_REG_2 + 1)
 647 #define MOD_VEX_73_REG_6        (MOD_VEX_73_REG_3 + 1)
 648 #define MOD_VEX_73_REG_7        (MOD_VEX_73_REG_6 + 1)
 649 #define MOD_VEX_AE_REG_2        (MOD_VEX_73_REG_7 + 1)
 650 #define MOD_VEX_AE_REG_3        (MOD_VEX_AE_REG_2 + 1)
 651 #define MOD_VEX_D7_PREFIX_2     (MOD_VEX_AE_REG_3 + 1)
 652 #define MOD_VEX_E7_PREFIX_2     (MOD_VEX_D7_PREFIX_2 + 1)
 653 #define MOD_VEX_F0_PREFIX_3     (MOD_VEX_E7_PREFIX_2 + 1)
 654 #define MOD_VEX_3818_PREFIX_2   (MOD_VEX_F0_PREFIX_3 + 1)
 655 #define MOD_VEX_3819_PREFIX_2   (MOD_VEX_3818_PREFIX_2 + 1)
 656 #define MOD_VEX_381A_PREFIX_2   (MOD_VEX_3819_PREFIX_2 + 1)
 657 #define MOD_VEX_382A_PREFIX_2   (MOD_VEX_381A_PREFIX_2 + 1)
 658 #define MOD_VEX_382C_PREFIX_2   (MOD_VEX_382A_PREFIX_2 + 1)
 659 #define MOD_VEX_382D_PREFIX_2   (MOD_VEX_382C_PREFIX_2 + 1)
 660 #define MOD_VEX_382E_PREFIX_2   (MOD_VEX_382D_PREFIX_2 + 1)
 661 #define MOD_VEX_382F_PREFIX_2   (MOD_VEX_382E_PREFIX_2 + 1)
 662
 663 #define RM_0F01_REG_0           0
 664 #define RM_0F01_REG_1           (RM_0F01_REG_0 + 1)
 665 #define RM_0F01_REG_2           (RM_0F01_REG_1 + 1)
 666 #define RM_0F01_REG_3           (RM_0F01_REG_2 + 1)
 667 #define RM_0F01_REG_7           (RM_0F01_REG_3 + 1)
 668 #define RM_0FAE_REG_5           (RM_0F01_REG_7 + 1)
 669 #define RM_0FAE_REG_6           (RM_0FAE_REG_5 + 1)
 670 #define RM_0FAE_REG_7           (RM_0FAE_REG_6 + 1)
 671
 672 #define PREFIX_90               0
 673 #define PREFIX_0F10             (PREFIX_90 + 1)
 674 #define PREFIX_0F11             (PREFIX_0F10 + 1)
 675 #define PREFIX_0F12             (PREFIX_0F11 + 1)
 676 #define PREFIX_0F16             (PREFIX_0F12 + 1)
 677 #define PREFIX_0F2A             (PREFIX_0F16 + 1)
 678 #define PREFIX_0F2B             (PREFIX_0F2A + 1)
 679 #define PREFIX_0F2C             (PREFIX_0F2B + 1)
 680 #define PREFIX_0F2D             (PREFIX_0F2C + 1)
 681 #define PREFIX_0F2E             (PREFIX_0F2D + 1)
 682 #define PREFIX_0F2F             (PREFIX_0F2E + 1)
 683 #define PREFIX_0F51             (PREFIX_0F2F + 1)
 684 #define PREFIX_0F52             (PREFIX_0F51 + 1)
 685 #define PREFIX_0F53             (PREFIX_0F52 + 1)
 686 #define PREFIX_0F58             (PREFIX_0F53 + 1)
 687 #define PREFIX_0F59             (PREFIX_0F58 + 1)
 688 #define PREFIX_0F5A             (PREFIX_0F59 + 1)
 689 #define PREFIX_0F5B             (PREFIX_0F5A + 1)
 690 #define PREFIX_0F5C             (PREFIX_0F5B + 1)
 691 #define PREFIX_0F5D             (PREFIX_0F5C + 1)
 692 #define PREFIX_0F5E             (PREFIX_0F5D + 1)
 693 #define PREFIX_0F5F             (PREFIX_0F5E + 1)
 694 #define PREFIX_0F60             (PREFIX_0F5F + 1)
 695 #define PREFIX_0F61             (PREFIX_0F60 + 1)
 696 #define PREFIX_0F62             (PREFIX_0F61 + 1)
 697 #define PREFIX_0F6C             (PREFIX_0F62 + 1)
 698 #define PREFIX_0F6D             (PREFIX_0F6C + 1)
 699 #define PREFIX_0F6F             (PREFIX_0F6D + 1)
 700 #define PREFIX_0F70             (PREFIX_0F6F + 1)
 701 #define PREFIX_0F73_REG_3       (PREFIX_0F70 + 1)
 702 #define PREFIX_0F73_REG_7       (PREFIX_0F73_REG_3 + 1)
 703 #define PREFIX_0F78             (PREFIX_0F73_REG_7 + 1)
 704 #define PREFIX_0F79             (PREFIX_0F78 + 1)
 705 #define PREFIX_0F7C             (PREFIX_0F79 + 1)
 706 #define PREFIX_0F7D             (PREFIX_0F7C + 1)
 707 #define PREFIX_0F7E             (PREFIX_0F7D + 1)
 708 #define PREFIX_0F7F             (PREFIX_0F7E + 1)
 709 #define PREFIX_0FB8             (PREFIX_0F7F + 1)
 710 #define PREFIX_0FBD             (PREFIX_0FB8 + 1)
 711 #define PREFIX_0FC2             (PREFIX_0FBD + 1)
 712 #define PREFIX_0FC3             (PREFIX_0FC2 + 1)
 713 #define PREFIX_0FC7_REG_6       (PREFIX_0FC3 + 1)
 714 #define PREFIX_0FD0             (PREFIX_0FC7_REG_6 + 1)
 715 #define PREFIX_0FD6             (PREFIX_0FD0 + 1)
 716 #define PREFIX_0FE6             (PREFIX_0FD6 + 1)
 717 #define PREFIX_0FE7             (PREFIX_0FE6 + 1)
 718 #define PREFIX_0FF0             (PREFIX_0FE7 + 1)
 719 #define PREFIX_0FF7             (PREFIX_0FF0 + 1)
 720 #define PREFIX_0F3810           (PREFIX_0FF7 + 1)
 721 #define PREFIX_0F3814           (PREFIX_0F3810 + 1)
 722 #define PREFIX_0F3815           (PREFIX_0F3814 + 1)
 723 #define PREFIX_0F3817           (PREFIX_0F3815 + 1)
 724 #define PREFIX_0F3820           (PREFIX_0F3817 + 1)
 725 #define PREFIX_0F3821           (PREFIX_0F3820 + 1)
 726 #define PREFIX_0F3822           (PREFIX_0F3821 + 1)
 727 #define PREFIX_0F3823           (PREFIX_0F3822 + 1)
 728 #define PREFIX_0F3824           (PREFIX_0F3823 + 1)
 729 #define PREFIX_0F3825           (PREFIX_0F3824 + 1)
 730 #define PREFIX_0F3828           (PREFIX_0F3825 + 1)
 731 #define PREFIX_0F3829           (PREFIX_0F3828 + 1)
 732 #define PREFIX_0F382A           (PREFIX_0F3829 + 1)
 733 #define PREFIX_0F382B           (PREFIX_0F382A + 1)
 734 #define PREFIX_0F3830           (PREFIX_0F382B + 1)
 735 #define PREFIX_0F3831           (PREFIX_0F3830 + 1)
 736 #define PREFIX_0F3832           (PREFIX_0F3831 + 1)
 737 #define PREFIX_0F3833           (PREFIX_0F3832 + 1)
 738 #define PREFIX_0F3834           (PREFIX_0F3833 + 1)
 739 #define PREFIX_0F3835           (PREFIX_0F3834 + 1)
 740 #define PREFIX_0F3837           (PREFIX_0F3835 + 1)
 741 #define PREFIX_0F3838           (PREFIX_0F3837 + 1)
 742 #define PREFIX_0F3839           (PREFIX_0F3838 + 1)
 743 #define PREFIX_0F383A           (PREFIX_0F3839 + 1)
 744 #define PREFIX_0F383B           (PREFIX_0F383A + 1)
 745 #define PREFIX_0F383C           (PREFIX_0F383B + 1)
 746 #define PREFIX_0F383D           (PREFIX_0F383C + 1)
 747 #define PREFIX_0F383E           (PREFIX_0F383D + 1)
 748 #define PREFIX_0F383F           (PREFIX_0F383E + 1)
 749 #define PREFIX_0F3840           (PREFIX_0F383F + 1)
 750 #define PREFIX_0F3841           (PREFIX_0F3840 + 1)
 751 #define PREFIX_0F3880           (PREFIX_0F3841 + 1)
 752 #define PREFIX_0F3881           (PREFIX_0F3880 + 1)
 753 #define PREFIX_0F38DB           (PREFIX_0F3881 + 1)
 754 #define PREFIX_0F38DC           (PREFIX_0F38DB + 1)
 755 #define PREFIX_0F38DD           (PREFIX_0F38DC + 1)
 756 #define PREFIX_0F38DE           (PREFIX_0F38DD + 1)
 757 #define PREFIX_0F38DF           (PREFIX_0F38DE + 1)
 758 #define PREFIX_0F38F0           (PREFIX_0F38DF + 1)
 759 #define PREFIX_0F38F1           (PREFIX_0F38F0 + 1)
 760 #define PREFIX_0F3A08           (PREFIX_0F38F1 + 1)
 761 #define PREFIX_0F3A09           (PREFIX_0F3A08 + 1)
 762 #define PREFIX_0F3A0A           (PREFIX_0F3A09 + 1)
 763 #define PREFIX_0F3A0B           (PREFIX_0F3A0A + 1)
 764 #define PREFIX_0F3A0C           (PREFIX_0F3A0B + 1)
 765 #define PREFIX_0F3A0D           (PREFIX_0F3A0C + 1)
 766 #define PREFIX_0F3A0E           (PREFIX_0F3A0D + 1)
 767 #define PREFIX_0F3A14           (PREFIX_0F3A0E + 1)
 768 #define PREFIX_0F3A15           (PREFIX_0F3A14 + 1)
 769 #define PREFIX_0F3A16           (PREFIX_0F3A15 + 1)
 770 #define PREFIX_0F3A17           (PREFIX_0F3A16 + 1)
 771 #define PREFIX_0F3A20           (PREFIX_0F3A17 + 1)
 772 #define PREFIX_0F3A21           (PREFIX_0F3A20 + 1)
 773 #define PREFIX_0F3A22           (PREFIX_0F3A21 + 1)
 774 #define PREFIX_0F3A40           (PREFIX_0F3A22 + 1)
 775 #define PREFIX_0F3A41           (PREFIX_0F3A40 + 1)
 776 #define PREFIX_0F3A42           (PREFIX_0F3A41 + 1)
 777 #define PREFIX_0F3A44           (PREFIX_0F3A42 + 1)
 778 #define PREFIX_0F3A60           (PREFIX_0F3A44 + 1)
 779 #define PREFIX_0F3A61           (PREFIX_0F3A60 + 1)
 780 #define PREFIX_0F3A62           (PREFIX_0F3A61 + 1)
 781 #define PREFIX_0F3A63           (PREFIX_0F3A62 + 1)
 782 #define PREFIX_0F3ADF           (PREFIX_0F3A63 + 1)
 783 #define PREFIX_VEX_10           (PREFIX_0F3ADF + 1)
 784 #define PREFIX_VEX_11           (PREFIX_VEX_10 + 1)
 785 #define PREFIX_VEX_12           (PREFIX_VEX_11 + 1)
 786 #define PREFIX_VEX_16           (PREFIX_VEX_12 + 1)
 787 #define PREFIX_VEX_2A           (PREFIX_VEX_16 + 1)
 788 #define PREFIX_VEX_2C           (PREFIX_VEX_2A + 1)
 789 #define PREFIX_VEX_2D           (PREFIX_VEX_2C + 1)
 790 #define PREFIX_VEX_2E           (PREFIX_VEX_2D + 1)
 791 #define PREFIX_VEX_2F           (PREFIX_VEX_2E + 1)
 792 #define PREFIX_VEX_51           (PREFIX_VEX_2F + 1)
 793 #define PREFIX_VEX_52           (PREFIX_VEX_51 + 1)
 794 #define PREFIX_VEX_53           (PREFIX_VEX_52 + 1)
 795 #define PREFIX_VEX_58           (PREFIX_VEX_53 + 1)
 796 #define PREFIX_VEX_59           (PREFIX_VEX_58 + 1)
 797 #define PREFIX_VEX_5A           (PREFIX_VEX_59 + 1)
 798 #define PREFIX_VEX_5B           (PREFIX_VEX_5A + 1)
 799 #define PREFIX_VEX_5C           (PREFIX_VEX_5B + 1)
 800 #define PREFIX_VEX_5D           (PREFIX_VEX_5C + 1)
 801 #define PREFIX_VEX_5E           (PREFIX_VEX_5D + 1)
 802 #define PREFIX_VEX_5F           (PREFIX_VEX_5E + 1)
 803 #define PREFIX_VEX_60           (PREFIX_VEX_5F + 1)
 804 #define PREFIX_VEX_61           (PREFIX_VEX_60 + 1)
 805 #define PREFIX_VEX_62           (PREFIX_VEX_61 + 1)
 806 #define PREFIX_VEX_63           (PREFIX_VEX_62 + 1)
 807 #define PREFIX_VEX_64           (PREFIX_VEX_63 + 1)
 808 #define PREFIX_VEX_65           (PREFIX_VEX_64 + 1)
 809 #define PREFIX_VEX_66           (PREFIX_VEX_65 + 1)
 810 #define PREFIX_VEX_67           (PREFIX_VEX_66 + 1)
 811 #define PREFIX_VEX_68           (PREFIX_VEX_67 + 1)
 812 #define PREFIX_VEX_69           (PREFIX_VEX_68 + 1)
 813 #define PREFIX_VEX_6A           (PREFIX_VEX_69 + 1)
 814 #define PREFIX_VEX_6B           (PREFIX_VEX_6A + 1)
 815 #define PREFIX_VEX_6C           (PREFIX_VEX_6B + 1)
 816 #define PREFIX_VEX_6D           (PREFIX_VEX_6C + 1)
 817 #define PREFIX_VEX_6E           (PREFIX_VEX_6D + 1)
 818 #define PREFIX_VEX_6F           (PREFIX_VEX_6E + 1)
 819 #define PREFIX_VEX_70           (PREFIX_VEX_6F + 1)
 820 #define PREFIX_VEX_71_REG_2     (PREFIX_VEX_70 + 1)
 821 #define PREFIX_VEX_71_REG_4     (PREFIX_VEX_71_REG_2 + 1)
 822 #define PREFIX_VEX_71_REG_6     (PREFIX_VEX_71_REG_4 + 1)
 823 #define PREFIX_VEX_72_REG_2     (PREFIX_VEX_71_REG_6 + 1)
 824 #define PREFIX_VEX_72_REG_4     (PREFIX_VEX_72_REG_2 + 1)
 825 #define PREFIX_VEX_72_REG_6     (PREFIX_VEX_72_REG_4 + 1)
 826 #define PREFIX_VEX_73_REG_2     (PREFIX_VEX_72_REG_6 + 1)
 827 #define PREFIX_VEX_73_REG_3     (PREFIX_VEX_73_REG_2 + 1)
 828 #define PREFIX_VEX_73_REG_6     (PREFIX_VEX_73_REG_3 + 1)
 829 #define PREFIX_VEX_73_REG_7     (PREFIX_VEX_73_REG_6 + 1)
 830 #define PREFIX_VEX_74           (PREFIX_VEX_73_REG_7 + 1)
 831 #define PREFIX_VEX_75           (PREFIX_VEX_74 + 1)
 832 #define PREFIX_VEX_76           (PREFIX_VEX_75 + 1)
 833 #define PREFIX_VEX_77           (PREFIX_VEX_76 + 1)
 834 #define PREFIX_VEX_7C           (PREFIX_VEX_77 + 1)
 835 #define PREFIX_VEX_7D           (PREFIX_VEX_7C + 1)
 836 #define PREFIX_VEX_7E           (PREFIX_VEX_7D + 1)
 837 #define PREFIX_VEX_7F           (PREFIX_VEX_7E + 1)
 838 #define PREFIX_VEX_C2           (PREFIX_VEX_7F + 1)
 839 #define PREFIX_VEX_C4           (PREFIX_VEX_C2 + 1)
 840 #define PREFIX_VEX_C5           (PREFIX_VEX_C4 + 1)
 841 #define PREFIX_VEX_D0           (PREFIX_VEX_C5 + 1)
 842 #define PREFIX_VEX_D1           (PREFIX_VEX_D0 + 1)
 843 #define PREFIX_VEX_D2           (PREFIX_VEX_D1 + 1)
 844 #define PREFIX_VEX_D3           (PREFIX_VEX_D2 + 1)
 845 #define PREFIX_VEX_D4           (PREFIX_VEX_D3 + 1)
 846 #define PREFIX_VEX_D5           (PREFIX_VEX_D4 + 1)
 847 #define PREFIX_VEX_D6           (PREFIX_VEX_D5 + 1)
 848 #define PREFIX_VEX_D7           (PREFIX_VEX_D6 + 1)
 849 #define PREFIX_VEX_D8           (PREFIX_VEX_D7 + 1)
 850 #define PREFIX_VEX_D9           (PREFIX_VEX_D8 + 1)
 851 #define PREFIX_VEX_DA           (PREFIX_VEX_D9 + 1)
 852 #define PREFIX_VEX_DB           (PREFIX_VEX_DA + 1)
 853 #define PREFIX_VEX_DC           (PREFIX_VEX_DB + 1)
 854 #define PREFIX_VEX_DD           (PREFIX_VEX_DC + 1)
 855 #define PREFIX_VEX_DE           (PREFIX_VEX_DD + 1)
 856 #define PREFIX_VEX_DF           (PREFIX_VEX_DE + 1)
 857 #define PREFIX_VEX_E0           (PREFIX_VEX_DF + 1)
 858 #define PREFIX_VEX_E1           (PREFIX_VEX_E0 + 1)
 859 #define PREFIX_VEX_E2           (PREFIX_VEX_E1 + 1)
 860 #define PREFIX_VEX_E3           (PREFIX_VEX_E2 + 1)
 861 #define PREFIX_VEX_E4           (PREFIX_VEX_E3 + 1)
 862 #define PREFIX_VEX_E5           (PREFIX_VEX_E4 + 1)
 863 #define PREFIX_VEX_E6           (PREFIX_VEX_E5 + 1)
 864 #define PREFIX_VEX_E7           (PREFIX_VEX_E6 + 1)
 865 #define PREFIX_VEX_E8           (PREFIX_VEX_E7 + 1)
 866 #define PREFIX_VEX_E9           (PREFIX_VEX_E8 + 1)
 867 #define PREFIX_VEX_EA           (PREFIX_VEX_E9 + 1)
 868 #define PREFIX_VEX_EB           (PREFIX_VEX_EA + 1)
 869 #define PREFIX_VEX_EC           (PREFIX_VEX_EB + 1)
 870 #define PREFIX_VEX_ED           (PREFIX_VEX_EC + 1)
 871 #define PREFIX_VEX_EE           (PREFIX_VEX_ED + 1)
 872 #define PREFIX_VEX_EF           (PREFIX_VEX_EE + 1)
 873 #define PREFIX_VEX_F0           (PREFIX_VEX_EF + 1)
 874 #define PREFIX_VEX_F1           (PREFIX_VEX_F0 + 1)
 875 #define PREFIX_VEX_F2           (PREFIX_VEX_F1 + 1)
 876 #define PREFIX_VEX_F3           (PREFIX_VEX_F2 + 1)
 877 #define PREFIX_VEX_F4           (PREFIX_VEX_F3 + 1)
 878 #define PREFIX_VEX_F5           (PREFIX_VEX_F4 + 1)
 879 #define PREFIX_VEX_F6           (PREFIX_VEX_F5 + 1)
 880 #define PREFIX_VEX_F7           (PREFIX_VEX_F6 + 1)
 881 #define PREFIX_VEX_F8           (PREFIX_VEX_F7 + 1)
 882 #define PREFIX_VEX_F9           (PREFIX_VEX_F8 + 1)
 883 #define PREFIX_VEX_FA           (PREFIX_VEX_F9 + 1)
 884 #define PREFIX_VEX_FB           (PREFIX_VEX_FA + 1)
 885 #define PREFIX_VEX_FC           (PREFIX_VEX_FB + 1)
 886 #define PREFIX_VEX_FD           (PREFIX_VEX_FC + 1)
 887 #define PREFIX_VEX_FE           (PREFIX_VEX_FD + 1)
 888 #define PREFIX_VEX_3800         (PREFIX_VEX_FE + 1)
 889 #define PREFIX_VEX_3801         (PREFIX_VEX_3800 + 1)
 890 #define PREFIX_VEX_3802         (PREFIX_VEX_3801 + 1)
 891 #define PREFIX_VEX_3803         (PREFIX_VEX_3802 + 1)
 892 #define PREFIX_VEX_3804         (PREFIX_VEX_3803 + 1)
 893 #define PREFIX_VEX_3805         (PREFIX_VEX_3804 + 1)
 894 #define PREFIX_VEX_3806         (PREFIX_VEX_3805 + 1)
 895 #define PREFIX_VEX_3807         (PREFIX_VEX_3806 + 1)
 896 #define PREFIX_VEX_3808         (PREFIX_VEX_3807 + 1)
 897 #define PREFIX_VEX_3809         (PREFIX_VEX_3808 + 1)
 898 #define PREFIX_VEX_380A         (PREFIX_VEX_3809 + 1)
 899 #define PREFIX_VEX_380B         (PREFIX_VEX_380A + 1)
 900 #define PREFIX_VEX_380C         (PREFIX_VEX_380B + 1)
 901 #define PREFIX_VEX_380D         (PREFIX_VEX_380C + 1)
 902 #define PREFIX_VEX_380E         (PREFIX_VEX_380D + 1)
 903 #define PREFIX_VEX_380F         (PREFIX_VEX_380E + 1)
 904 #define PREFIX_VEX_3817         (PREFIX_VEX_380F + 1)
 905 #define PREFIX_VEX_3818         (PREFIX_VEX_3817 + 1)
 906 #define PREFIX_VEX_3819         (PREFIX_VEX_3818 + 1)
 907 #define PREFIX_VEX_381A         (PREFIX_VEX_3819 + 1)
 908 #define PREFIX_VEX_381C         (PREFIX_VEX_381A + 1)
 909 #define PREFIX_VEX_381D         (PREFIX_VEX_381C + 1)
 910 #define PREFIX_VEX_381E         (PREFIX_VEX_381D + 1)
 911 #define PREFIX_VEX_3820         (PREFIX_VEX_381E + 1)
 912 #define PREFIX_VEX_3821         (PREFIX_VEX_3820 + 1)
 913 #define PREFIX_VEX_3822         (PREFIX_VEX_3821 + 1)
 914 #define PREFIX_VEX_3823         (PREFIX_VEX_3822 + 1)
 915 #define PREFIX_VEX_3824         (PREFIX_VEX_3823 + 1)
 916 #define PREFIX_VEX_3825         (PREFIX_VEX_3824 + 1)
 917 #define PREFIX_VEX_3828         (PREFIX_VEX_3825 + 1)
 918 #define PREFIX_VEX_3829         (PREFIX_VEX_3828 + 1)
 919 #define PREFIX_VEX_382A         (PREFIX_VEX_3829 + 1)
 920 #define PREFIX_VEX_382B         (PREFIX_VEX_382A + 1)
 921 #define PREFIX_VEX_382C         (PREFIX_VEX_382B + 1)
 922 #define PREFIX_VEX_382D         (PREFIX_VEX_382C + 1)
 923 #define PREFIX_VEX_382E         (PREFIX_VEX_382D + 1)
 924 #define PREFIX_VEX_382F         (PREFIX_VEX_382E + 1)
 925 #define PREFIX_VEX_3830         (PREFIX_VEX_382F + 1)
 926 #define PREFIX_VEX_3831         (PREFIX_VEX_3830 + 1)
 927 #define PREFIX_VEX_3832         (PREFIX_VEX_3831 + 1)
 928 #define PREFIX_VEX_3833         (PREFIX_VEX_3832 + 1)
 929 #define PREFIX_VEX_3834         (PREFIX_VEX_3833 + 1)
 930 #define PREFIX_VEX_3835         (PREFIX_VEX_3834 + 1)
 931 #define PREFIX_VEX_3837         (PREFIX_VEX_3835 + 1)
 932 #define PREFIX_VEX_3838         (PREFIX_VEX_3837 + 1)
 933 #define PREFIX_VEX_3839         (PREFIX_VEX_3838 + 1)
 934 #define PREFIX_VEX_383A         (PREFIX_VEX_3839 + 1)
 935 #define PREFIX_VEX_383B         (PREFIX_VEX_383A + 1)
 936 #define PREFIX_VEX_383C         (PREFIX_VEX_383B + 1)
 937 #define PREFIX_VEX_383D         (PREFIX_VEX_383C + 1)
 938 #define PREFIX_VEX_383E         (PREFIX_VEX_383D + 1)
 939 #define PREFIX_VEX_383F         (PREFIX_VEX_383E + 1)
 940 #define PREFIX_VEX_3840         (PREFIX_VEX_383F + 1)
 941 #define PREFIX_VEX_3841         (PREFIX_VEX_3840 + 1)
 942 #define PREFIX_VEX_38DB         (PREFIX_VEX_3841 + 1)
 943 #define PREFIX_VEX_38DC         (PREFIX_VEX_38DB + 1)
 944 #define PREFIX_VEX_38DD         (PREFIX_VEX_38DC + 1)
 945 #define PREFIX_VEX_38DE         (PREFIX_VEX_38DD + 1)
 946 #define PREFIX_VEX_38DF         (PREFIX_VEX_38DE + 1)
 947 #define PREFIX_VEX_3A04         (PREFIX_VEX_38DF + 1)
 948 #define PREFIX_VEX_3A05         (PREFIX_VEX_3A04 + 1)
 949 #define PREFIX_VEX_3A06         (PREFIX_VEX_3A05 + 1)
 950 #define PREFIX_VEX_3A08         (PREFIX_VEX_3A06 + 1)
 951 #define PREFIX_VEX_3A09         (PREFIX_VEX_3A08 + 1)
 952 #define PREFIX_VEX_3A0A         (PREFIX_VEX_3A09 + 1)
 953 #define PREFIX_VEX_3A0B         (PREFIX_VEX_3A0A + 1)
 954 #define PREFIX_VEX_3A0C         (PREFIX_VEX_3A0B + 1)
 955 #define PREFIX_VEX_3A0D         (PREFIX_VEX_3A0C + 1)
 956 #define PREFIX_VEX_3A0E         (PREFIX_VEX_3A0D + 1)
 957 #define PREFIX_VEX_3A0F         (PREFIX_VEX_3A0E + 1)
 958 #define PREFIX_VEX_3A14         (PREFIX_VEX_3A0F + 1)
 959 #define PREFIX_VEX_3A15         (PREFIX_VEX_3A14 + 1)
 960 #define PREFIX_VEX_3A16         (PREFIX_VEX_3A15 + 1)
 961 #define PREFIX_VEX_3A17         (PREFIX_VEX_3A16 + 1)
 962 #define PREFIX_VEX_3A18         (PREFIX_VEX_3A17 + 1)
 963 #define PREFIX_VEX_3A19         (PREFIX_VEX_3A18 + 1)
 964 #define PREFIX_VEX_3A20         (PREFIX_VEX_3A19 + 1)
 965 #define PREFIX_VEX_3A21         (PREFIX_VEX_3A20 + 1)
 966 #define PREFIX_VEX_3A22         (PREFIX_VEX_3A21 + 1)
 967 #define PREFIX_VEX_3A40         (PREFIX_VEX_3A22 + 1)
 968 #define PREFIX_VEX_3A41         (PREFIX_VEX_3A40 + 1)
 969 #define PREFIX_VEX_3A42         (PREFIX_VEX_3A41 + 1)
 970 #define PREFIX_VEX_3A48         (PREFIX_VEX_3A42 + 1)
 971 #define PREFIX_VEX_3A49         (PREFIX_VEX_3A48 + 1)
 972 #define PREFIX_VEX_3A4A         (PREFIX_VEX_3A49 + 1)
 973 #define PREFIX_VEX_3A4B         (PREFIX_VEX_3A4A + 1)
 974 #define PREFIX_VEX_3A4C         (PREFIX_VEX_3A4B + 1)
 975 #define PREFIX_VEX_3A5C         (PREFIX_VEX_3A4C + 1)
 976 #define PREFIX_VEX_3A5D         (PREFIX_VEX_3A5C + 1)
 977 #define PREFIX_VEX_3A5E         (PREFIX_VEX_3A5D + 1)
 978 #define PREFIX_VEX_3A5F         (PREFIX_VEX_3A5E + 1)
 979 #define PREFIX_VEX_3A60         (PREFIX_VEX_3A5F + 1)
 980 #define PREFIX_VEX_3A61         (PREFIX_VEX_3A60 + 1)
 981 #define PREFIX_VEX_3A62         (PREFIX_VEX_3A61 + 1)
 982 #define PREFIX_VEX_3A63         (PREFIX_VEX_3A62 + 1)
 983 #define PREFIX_VEX_3A68         (PREFIX_VEX_3A63 + 1)
 984 #define PREFIX_VEX_3A69         (PREFIX_VEX_3A68 + 1)
 985 #define PREFIX_VEX_3A6A         (PREFIX_VEX_3A69 + 1)
 986 #define PREFIX_VEX_3A6B         (PREFIX_VEX_3A6A + 1)
 987 #define PREFIX_VEX_3A6C         (PREFIX_VEX_3A6B + 1)
 988 #define PREFIX_VEX_3A6D         (PREFIX_VEX_3A6C + 1)
 989 #define PREFIX_VEX_3A6E         (PREFIX_VEX_3A6D + 1)
 990 #define PREFIX_VEX_3A6F         (PREFIX_VEX_3A6E + 1)
 991 #define PREFIX_VEX_3A78         (PREFIX_VEX_3A6F + 1)
 992 #define PREFIX_VEX_3A79         (PREFIX_VEX_3A78 + 1)
 993 #define PREFIX_VEX_3A7A         (PREFIX_VEX_3A79 + 1)
 994 #define PREFIX_VEX_3A7B         (PREFIX_VEX_3A7A + 1)
 995 #define PREFIX_VEX_3A7C         (PREFIX_VEX_3A7B + 1)
 996 #define PREFIX_VEX_3A7D         (PREFIX_VEX_3A7C + 1)
 997 #define PREFIX_VEX_3A7E         (PREFIX_VEX_3A7D + 1)
 998 #define PREFIX_VEX_3A7F         (PREFIX_VEX_3A7E + 1)
 999 #define PREFIX_VEX_3ADF         (PREFIX_VEX_3A7F + 1)
1000
1001 #define X86_64_06               0
1002 #define X86_64_07               (X86_64_06 + 1)
1003 #define X86_64_0D               (X86_64_07 + 1)
1004 #define X86_64_16               (X86_64_0D + 1)
1005 #define X86_64_17               (X86_64_16 + 1)
1006 #define X86_64_1E               (X86_64_17 + 1)
1007 #define X86_64_1F               (X86_64_1E + 1)
1008 #define X86_64_27               (X86_64_1F + 1)
1009 #define X86_64_2F               (X86_64_27 + 1)
1010 #define X86_64_37               (X86_64_2F + 1)
1011 #define X86_64_3F               (X86_64_37 + 1)
1012 #define X86_64_60               (X86_64_3F + 1)
1013 #define X86_64_61               (X86_64_60 + 1)
1014 #define X86_64_62               (X86_64_61 + 1)
1015 #define X86_64_63               (X86_64_62 + 1)
1016 #define X86_64_6D               (X86_64_63 + 1)
1017 #define X86_64_6F               (X86_64_6D + 1)
1018 #define X86_64_9A               (X86_64_6F + 1)
1019 #define X86_64_C4               (X86_64_9A + 1)
1020 #define X86_64_C5               (X86_64_C4 + 1)
1021 #define X86_64_CE               (X86_64_C5 + 1)
1022 #define X86_64_D4               (X86_64_CE + 1)
1023 #define X86_64_D5               (X86_64_D4 + 1)
1024 #define X86_64_EA               (X86_64_D5 + 1)
1025 #define X86_64_0F01_REG_0       (X86_64_EA + 1)
1026 #define X86_64_0F01_REG_1       (X86_64_0F01_REG_0 + 1)
1027 #define X86_64_0F01_REG_2       (X86_64_0F01_REG_1 + 1)
1028 #define X86_64_0F01_REG_3       (X86_64_0F01_REG_2 + 1)
1029
1030 #define THREE_BYTE_0F24         0
1031 #define THREE_BYTE_0F25         (THREE_BYTE_0F24 + 1)
1032 #define THREE_BYTE_0F38         (THREE_BYTE_0F25 + 1)
1033 #define THREE_BYTE_0F3A         (THREE_BYTE_0F38 + 1)
1034 #define THREE_BYTE_0F7A         (THREE_BYTE_0F3A + 1)
1035 #define THREE_BYTE_0F7B         (THREE_BYTE_0F7A + 1)
1036
1037 #define VEX_0F                  0
1038 #define VEX_0F38                (VEX_0F + 1)
1039 #define VEX_0F3A                (VEX_0F38 + 1)
1040
1041 #define VEX_LEN_10_P_1  0
1042 #define VEX_LEN_10_P_3  (VEX_LEN_10_P_1 + 1)
1043 #define VEX_LEN_11_P_1  (VEX_LEN_10_P_3 + 1)
1044 #define VEX_LEN_11_P_3  (VEX_LEN_11_P_1 + 1)
1045 #define VEX_LEN_12_P_0_M_0      (VEX_LEN_11_P_3 + 1)
1046 #define VEX_LEN_12_P_0_M_1      (VEX_LEN_12_P_0_M_0 + 1)
1047 #define VEX_LEN_12_P_2  (VEX_LEN_12_P_0_M_1 + 1)
1048 #define VEX_LEN_13_M_0  (VEX_LEN_12_P_2 + 1)
1049 #define VEX_LEN_16_P_0_M_0      (VEX_LEN_13_M_0 + 1)
1050 #define VEX_LEN_16_P_0_M_1      (VEX_LEN_16_P_0_M_0 + 1)
1051 #define VEX_LEN_16_P_2  (VEX_LEN_16_P_0_M_1 + 1)
1052 #define VEX_LEN_17_M_0  (VEX_LEN_16_P_2 + 1)
1053 #define VEX_LEN_2A_P_1  (VEX_LEN_17_M_0 + 1)
1054 #define VEX_LEN_2A_P_3  (VEX_LEN_2A_P_1 + 1)
1055 #define VEX_LEN_2B_M_0  (VEX_LEN_2A_P_3 + 1)
1056 #define VEX_LEN_2C_P_1  (VEX_LEN_2B_M_0 + 1)
1057 #define VEX_LEN_2C_P_3  (VEX_LEN_2C_P_1 + 1)
1058 #define VEX_LEN_2D_P_1  (VEX_LEN_2C_P_3 + 1)
1059 #define VEX_LEN_2D_P_3  (VEX_LEN_2D_P_1 + 1)
1060 #define VEX_LEN_2E_P_0  (VEX_LEN_2D_P_3 + 1)
1061 #define VEX_LEN_2E_P_2  (VEX_LEN_2E_P_0 + 1)
1062 #define VEX_LEN_2F_P_0  (VEX_LEN_2E_P_2 + 1)
1063 #define VEX_LEN_2F_P_2  (VEX_LEN_2F_P_0 + 1)
1064 #define VEX_LEN_51_P_1  (VEX_LEN_2F_P_2 + 1)
1065 #define VEX_LEN_51_P_3  (VEX_LEN_51_P_1 + 1)
1066 #define VEX_LEN_52_P_1  (VEX_LEN_51_P_3 + 1)
1067 #define VEX_LEN_53_P_1  (VEX_LEN_52_P_1 + 1)
1068 #define VEX_LEN_58_P_1  (VEX_LEN_53_P_1 + 1)
1069 #define VEX_LEN_58_P_3  (VEX_LEN_58_P_1 + 1)
1070 #define VEX_LEN_59_P_1  (VEX_LEN_58_P_3 + 1)
1071 #define VEX_LEN_59_P_3  (VEX_LEN_59_P_1 + 1)
1072 #define VEX_LEN_5A_P_1  (VEX_LEN_59_P_3 + 1)
1073 #define VEX_LEN_5A_P_3  (VEX_LEN_5A_P_1 + 1)
1074 #define VEX_LEN_5C_P_1  (VEX_LEN_5A_P_3 + 1)
1075 #define VEX_LEN_5C_P_3  (VEX_LEN_5C_P_1 + 1)
1076 #define VEX_LEN_5D_P_1  (VEX_LEN_5C_P_3 + 1)
1077 #define VEX_LEN_5D_P_3  (VEX_LEN_5D_P_1 + 1)
1078 #define VEX_LEN_5E_P_1  (VEX_LEN_5D_P_3 + 1)
1079 #define VEX_LEN_5E_P_3  (VEX_LEN_5E_P_1 + 1)
1080 #define VEX_LEN_5F_P_1  (VEX_LEN_5E_P_3 + 1)
1081 #define VEX_LEN_5F_P_3  (VEX_LEN_5F_P_1 + 1)
1082 #define VEX_LEN_60_P_2  (VEX_LEN_5F_P_3 + 1)
1083 #define VEX_LEN_61_P_2  (VEX_LEN_60_P_2 + 1)
1084 #define VEX_LEN_62_P_2  (VEX_LEN_61_P_2 + 1)
1085 #define VEX_LEN_63_P_2  (VEX_LEN_62_P_2 + 1)
1086 #define VEX_LEN_64_P_2  (VEX_LEN_63_P_2 + 1)
1087 #define VEX_LEN_65_P_2  (VEX_LEN_64_P_2 + 1)
1088 #define VEX_LEN_66_P_2  (VEX_LEN_65_P_2 + 1)
1089 #define VEX_LEN_67_P_2  (VEX_LEN_66_P_2 + 1)
1090 #define VEX_LEN_68_P_2  (VEX_LEN_67_P_2 + 1)
1091 #define VEX_LEN_69_P_2  (VEX_LEN_68_P_2 + 1)
1092 #define VEX_LEN_6A_P_2  (VEX_LEN_69_P_2 + 1)
1093 #define VEX_LEN_6B_P_2  (VEX_LEN_6A_P_2 + 1)
1094 #define VEX_LEN_6C_P_2  (VEX_LEN_6B_P_2 + 1)
1095 #define VEX_LEN_6D_P_2  (VEX_LEN_6C_P_2 + 1)
1096 #define VEX_LEN_6E_P_2  (VEX_LEN_6D_P_2 + 1)
1097 #define VEX_LEN_70_P_1  (VEX_LEN_6E_P_2 + 1)
1098 #define VEX_LEN_70_P_2  (VEX_LEN_70_P_1 + 1)
1099 #define VEX_LEN_70_P_3  (VEX_LEN_70_P_2 + 1)
1100 #define VEX_LEN_71_R_2_P_2      (VEX_LEN_70_P_3 + 1)
1101 #define VEX_LEN_71_R_4_P_2      (VEX_LEN_71_R_2_P_2 + 1)
1102 #define VEX_LEN_71_R_6_P_2      (VEX_LEN_71_R_4_P_2 + 1)
1103 #define VEX_LEN_72_R_2_P_2      (VEX_LEN_71_R_6_P_2 + 1)
1104 #define VEX_LEN_72_R_4_P_2      (VEX_LEN_72_R_2_P_2 + 1)
1105 #define VEX_LEN_72_R_6_P_2      (VEX_LEN_72_R_4_P_2 + 1)
1106 #define VEX_LEN_73_R_2_P_2      (VEX_LEN_72_R_6_P_2 + 1)
1107 #define VEX_LEN_73_R_3_P_2      (VEX_LEN_73_R_2_P_2 + 1)
1108 #define VEX_LEN_73_R_6_P_2      (VEX_LEN_73_R_3_P_2 + 1)
1109 #define VEX_LEN_73_R_7_P_2      (VEX_LEN_73_R_6_P_2 + 1)
1110 #define VEX_LEN_74_P_2  (VEX_LEN_73_R_7_P_2 + 1)
1111 #define VEX_LEN_75_P_2  (VEX_LEN_74_P_2 + 1)
1112 #define VEX_LEN_76_P_2  (VEX_LEN_75_P_2 + 1)
1113 #define VEX_LEN_7E_P_1  (VEX_LEN_76_P_2 + 1)
1114 #define VEX_LEN_7E_P_2  (VEX_LEN_7E_P_1 + 1)
1115 #define VEX_LEN_AE_R_2_M_0      (VEX_LEN_7E_P_2 + 1)
1116 #define VEX_LEN_AE_R_3_M_0      (VEX_LEN_AE_R_2_M_0 + 1)
1117 #define VEX_LEN_C2_P_1  (VEX_LEN_AE_R_3_M_0 + 1)
1118 #define VEX_LEN_C2_P_3  (VEX_LEN_C2_P_1 + 1)
1119 #define VEX_LEN_C4_P_2  (VEX_LEN_C2_P_3 + 1)
1120 #define VEX_LEN_C5_P_2  (VEX_LEN_C4_P_2 + 1)
1121 #define VEX_LEN_D1_P_2  (VEX_LEN_C5_P_2 + 1)
1122 #define VEX_LEN_D2_P_2  (VEX_LEN_D1_P_2 + 1)
1123 #define VEX_LEN_D3_P_2  (VEX_LEN_D2_P_2 + 1)
1124 #define VEX_LEN_D4_P_2  (VEX_LEN_D3_P_2 + 1)
1125 #define VEX_LEN_D5_P_2  (VEX_LEN_D4_P_2 + 1)
1126 #define VEX_LEN_D6_P_2  (VEX_LEN_D5_P_2 + 1)
1127 #define VEX_LEN_D7_P_2_M_1      (VEX_LEN_D6_P_2 + 1)
1128 #define VEX_LEN_D8_P_2  (VEX_LEN_D7_P_2_M_1 + 1)
1129 #define VEX_LEN_D9_P_2  (VEX_LEN_D8_P_2 + 1)
1130 #define VEX_LEN_DA_P_2  (VEX_LEN_D9_P_2 + 1)
1131 #define VEX_LEN_DB_P_2  (VEX_LEN_DA_P_2 + 1)
1132 #define VEX_LEN_DC_P_2  (VEX_LEN_DB_P_2 + 1)
1133 #define VEX_LEN_DD_P_2  (VEX_LEN_DC_P_2 + 1)
1134 #define VEX_LEN_DE_P_2  (VEX_LEN_DD_P_2 + 1)
1135 #define VEX_LEN_DF_P_2  (VEX_LEN_DE_P_2 + 1)
1136 #define VEX_LEN_E0_P_2  (VEX_LEN_DF_P_2 + 1)
1137 #define VEX_LEN_E1_P_2  (VEX_LEN_E0_P_2 + 1)
1138 #define VEX_LEN_E2_P_2  (VEX_LEN_E1_P_2 + 1)
1139 #define VEX_LEN_E3_P_2  (VEX_LEN_E2_P_2 + 1)
1140 #define VEX_LEN_E4_P_2  (VEX_LEN_E3_P_2 + 1)
1141 #define VEX_LEN_E5_P_2  (VEX_LEN_E4_P_2 + 1)
1142 #define VEX_LEN_E7_P_2_M_0      (VEX_LEN_E5_P_2 + 1)
1143 #define VEX_LEN_E8_P_2  (VEX_LEN_E7_P_2_M_0 + 1)
1144 #define VEX_LEN_E9_P_2  (VEX_LEN_E8_P_2 + 1)
1145 #define VEX_LEN_EA_P_2  (VEX_LEN_E9_P_2 + 1)
1146 #define VEX_LEN_EB_P_2  (VEX_LEN_EA_P_2 + 1)
1147 #define VEX_LEN_EC_P_2  (VEX_LEN_EB_P_2 + 1)
1148 #define VEX_LEN_ED_P_2  (VEX_LEN_EC_P_2 + 1)
1149 #define VEX_LEN_EE_P_2  (VEX_LEN_ED_P_2 + 1)
1150 #define VEX_LEN_EF_P_2  (VEX_LEN_EE_P_2 + 1)
1151 #define VEX_LEN_F1_P_2  (VEX_LEN_EF_P_2 + 1)
1152 #define VEX_LEN_F2_P_2  (VEX_LEN_F1_P_2 + 1)
1153 #define VEX_LEN_F3_P_2  (VEX_LEN_F2_P_2 + 1)
1154 #define VEX_LEN_F4_P_2  (VEX_LEN_F3_P_2 + 1)
1155 #define VEX_LEN_F5_P_2  (VEX_LEN_F4_P_2 + 1)
1156 #define VEX_LEN_F6_P_2  (VEX_LEN_F5_P_2 + 1)
1157 #define VEX_LEN_F7_P_2  (VEX_LEN_F6_P_2 + 1)
1158 #define VEX_LEN_F8_P_2  (VEX_LEN_F7_P_2 + 1)
1159 #define VEX_LEN_F9_P_2  (VEX_LEN_F8_P_2 + 1)
1160 #define VEX_LEN_FA_P_2  (VEX_LEN_F9_P_2 + 1)
1161 #define VEX_LEN_FB_P_2  (VEX_LEN_FA_P_2 + 1)
1162 #define VEX_LEN_FC_P_2  (VEX_LEN_FB_P_2 + 1)
1163 #define VEX_LEN_FD_P_2  (VEX_LEN_FC_P_2 + 1)
1164 #define VEX_LEN_FE_P_2  (VEX_LEN_FD_P_2 + 1)
1165 #define VEX_LEN_3800_P_2        (VEX_LEN_FE_P_2 + 1)
1166 #define VEX_LEN_3801_P_2        (VEX_LEN_3800_P_2 + 1)
1167 #define VEX_LEN_3802_P_2        (VEX_LEN_3801_P_2 + 1)
1168 #define VEX_LEN_3803_P_2        (VEX_LEN_3802_P_2 + 1)
1169 #define VEX_LEN_3804_P_2        (VEX_LEN_3803_P_2 + 1)
1170 #define VEX_LEN_3805_P_2        (VEX_LEN_3804_P_2 + 1)
1171 #define VEX_LEN_3806_P_2        (VEX_LEN_3805_P_2 + 1)
1172 #define VEX_LEN_3807_P_2        (VEX_LEN_3806_P_2 + 1)
1173 #define VEX_LEN_3808_P_2        (VEX_LEN_3807_P_2 + 1)
1174 #define VEX_LEN_3809_P_2        (VEX_LEN_3808_P_2 + 1)
1175 #define VEX_LEN_380A_P_2        (VEX_LEN_3809_P_2 + 1)
1176 #define VEX_LEN_380B_P_2        (VEX_LEN_380A_P_2 + 1)
1177 #define VEX_LEN_3819_P_2_M_0    (VEX_LEN_380B_P_2 + 1)
1178 #define VEX_LEN_381A_P_2_M_0    (VEX_LEN_3819_P_2_M_0 + 1)
1179 #define VEX_LEN_381C_P_2        (VEX_LEN_381A_P_2_M_0 + 1)
1180 #define VEX_LEN_381D_P_2        (VEX_LEN_381C_P_2 + 1)
1181 #define VEX_LEN_381E_P_2        (VEX_LEN_381D_P_2 + 1)
1182 #define VEX_LEN_3820_P_2        (VEX_LEN_381E_P_2 + 1)
1183 #define VEX_LEN_3821_P_2        (VEX_LEN_3820_P_2 + 1)
1184 #define VEX_LEN_3822_P_2        (VEX_LEN_3821_P_2 + 1)
1185 #define VEX_LEN_3823_P_2        (VEX_LEN_3822_P_2 + 1)
1186 #define VEX_LEN_3824_P_2        (VEX_LEN_3823_P_2 + 1)
1187 #define VEX_LEN_3825_P_2        (VEX_LEN_3824_P_2 + 1)
1188 #define VEX_LEN_3828_P_2        (VEX_LEN_3825_P_2 + 1)
1189 #define VEX_LEN_3829_P_2        (VEX_LEN_3828_P_2 + 1)
1190 #define VEX_LEN_382A_P_2_M_0    (VEX_LEN_3829_P_2 + 1)
1191 #define VEX_LEN_382B_P_2        (VEX_LEN_382A_P_2_M_0 + 1)
1192 #define VEX_LEN_3830_P_2        (VEX_LEN_382B_P_2 + 1)
1193 #define VEX_LEN_3831_P_2        (VEX_LEN_3830_P_2 + 1)
1194 #define VEX_LEN_3832_P_2        (VEX_LEN_3831_P_2 + 1)
1195 #define VEX_LEN_3833_P_2        (VEX_LEN_3832_P_2 + 1)
1196 #define VEX_LEN_3834_P_2        (VEX_LEN_3833_P_2 + 1)
1197 #define VEX_LEN_3835_P_2        (VEX_LEN_3834_P_2 + 1)
1198 #define VEX_LEN_3837_P_2        (VEX_LEN_3835_P_2 + 1)
1199 #define VEX_LEN_3838_P_2        (VEX_LEN_3837_P_2 + 1)
1200 #define VEX_LEN_3839_P_2        (VEX_LEN_3838_P_2 + 1)
1201 #define VEX_LEN_383A_P_2        (VEX_LEN_3839_P_2 + 1)
1202 #define VEX_LEN_383B_P_2        (VEX_LEN_383A_P_2 + 1)
1203 #define VEX_LEN_383C_P_2        (VEX_LEN_383B_P_2 + 1)
1204 #define VEX_LEN_383D_P_2        (VEX_LEN_383C_P_2 + 1)
1205 #define VEX_LEN_383E_P_2        (VEX_LEN_383D_P_2 + 1)
1206 #define VEX_LEN_383F_P_2        (VEX_LEN_383E_P_2 + 1)
1207 #define VEX_LEN_3840_P_2        (VEX_LEN_383F_P_2 + 1)
1208 #define VEX_LEN_3841_P_2        (VEX_LEN_3840_P_2 + 1)
1209 #define VEX_LEN_38DB_P_2        (VEX_LEN_3841_P_2 + 1)
1210 #define VEX_LEN_38DC_P_2        (VEX_LEN_38DB_P_2 + 1)
1211 #define VEX_LEN_38DD_P_2        (VEX_LEN_38DC_P_2 + 1)
1212 #define VEX_LEN_38DE_P_2        (VEX_LEN_38DD_P_2 + 1)
1213 #define VEX_LEN_38DF_P_2        (VEX_LEN_38DE_P_2 + 1)
1214 #define VEX_LEN_3A06_P_2        (VEX_LEN_38DF_P_2 + 1)
1215 #define VEX_LEN_3A0A_P_2        (VEX_LEN_3A06_P_2 + 1)
1216 #define VEX_LEN_3A0B_P_2        (VEX_LEN_3A0A_P_2 + 1)
1217 #define VEX_LEN_3A0E_P_2        (VEX_LEN_3A0B_P_2 + 1)
1218 #define VEX_LEN_3A0F_P_2        (VEX_LEN_3A0E_P_2 + 1)
1219 #define VEX_LEN_3A14_P_2        (VEX_LEN_3A0F_P_2 + 1)
1220 #define VEX_LEN_3A15_P_2        (VEX_LEN_3A14_P_2 + 1)
1221 #define VEX_LEN_3A16_P_2        (VEX_LEN_3A15_P_2 + 1)
1222 #define VEX_LEN_3A17_P_2        (VEX_LEN_3A16_P_2 + 1)
1223 #define VEX_LEN_3A18_P_2        (VEX_LEN_3A17_P_2 + 1)
1224 #define VEX_LEN_3A19_P_2        (VEX_LEN_3A18_P_2 + 1)
1225 #define VEX_LEN_3A20_P_2        (VEX_LEN_3A19_P_2 + 1)
1226 #define VEX_LEN_3A21_P_2        (VEX_LEN_3A20_P_2 + 1)
1227 #define VEX_LEN_3A22_P_2        (VEX_LEN_3A21_P_2 + 1)
1228 #define VEX_LEN_3A41_P_2        (VEX_LEN_3A22_P_2 + 1)
1229 #define VEX_LEN_3A42_P_2        (VEX_LEN_3A41_P_2 + 1)
1230 #define VEX_LEN_3A4C_P_2        (VEX_LEN_3A42_P_2 + 1)
1231 #define VEX_LEN_3A60_P_2        (VEX_LEN_3A4C_P_2 + 1)
1232 #define VEX_LEN_3A61_P_2        (VEX_LEN_3A60_P_2 + 1)
1233 #define VEX_LEN_3A62_P_2        (VEX_LEN_3A61_P_2 + 1)
1234 #define VEX_LEN_3A63_P_2        (VEX_LEN_3A62_P_2 + 1)
1235 #define VEX_LEN_3A6A_P_2        (VEX_LEN_3A63_P_2 + 1)
1236 #define VEX_LEN_3A6B_P_2        (VEX_LEN_3A6A_P_2 + 1)
1237 #define VEX_LEN_3A6E_P_2        (VEX_LEN_3A6B_P_2 + 1)
1238 #define VEX_LEN_3A6F_P_2        (VEX_LEN_3A6E_P_2 + 1)
1239 #define VEX_LEN_3A7A_P_2        (VEX_LEN_3A6F_P_2 + 1)
1240 #define VEX_LEN_3A7B_P_2        (VEX_LEN_3A7A_P_2 + 1)
1241 #define VEX_LEN_3A7E_P_2        (VEX_LEN_3A7B_P_2 + 1)
1242 #define VEX_LEN_3A7F_P_2        (VEX_LEN_3A7E_P_2 + 1)
1243 #define VEX_LEN_3ADF_P_2        (VEX_LEN_3A7F_P_2 + 1)
1244
1245 typedef void (*op_rtn) (int bytemode, int sizeflag);
1246
1247 struct dis386 {
1248   const char *name;
1249   struct
1250     {
1251       op_rtn rtn;
1252       int bytemode;
1253     } op[MAX_OPERANDS];
1254 };
1255
1256 /* Upper case letters in the instruction names here are macros.
1257    'A' => print 'b' if no register operands or suffix_always is true
1258    'B' => print 'b' if suffix_always is true
1259    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1260           size prefix
1261    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1262           suffix_always is true
1263    'E' => print 'e' if 32-bit form of jcxz
1264    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1265    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1266    'H' => print ",pt" or ",pn" branch hint
1267    'I' => honor following macro letter even in Intel mode (implemented only
1268           for some of the macro letters)
1269    'J' => print 'l'
1270    'K' => print 'd' or 'q' if rex prefix is present.
1271    'L' => print 'l' if suffix_always is true
1272    'M' => print 'r' if intel_mnemonic is false.
1273    'N' => print 'n' if instruction has no wait "prefix"
1274    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1275    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1276           or suffix_always is true.  print 'q' if rex prefix is present.
1277    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1278           is true
1279    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1280    'S' => print 'w', 'l' or 'q' if suffix_always is true
1281    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1282    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1283    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1284    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1285    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1286    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1287           suffix_always is true.
1288    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1289    '!' => change condition from true to false or from false to true.
1290    '%' => add 1 upper case letter to the macro.
1291
1292    2 upper case letter macros:
1293    "XY" => print 'x' or 'y' if no register operands or suffix_always
1294            is true.
1295    'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
1296            or suffix_always is true
1297
1298    Many of the above letters print nothing in Intel mode.  See "putop"
1299    for the details.
1300
1301    Braces '{' and '}', and vertical bars '|', indicate alternative
1302    mnemonic strings for AT&T and Intel.  */
1303
1304 static const struct dis386 dis386[] = {
1305   /* 00 */
1306   { "addB",             { Eb, Gb } },
1307   { "addS",             { Ev, Gv } },
1308   { "addB",             { Gb, Eb } },
1309   { "addS",             { Gv, Ev } },
1310   { "addB",             { AL, Ib } },
1311   { "addS",             { eAX, Iv } },
1312   { X86_64_TABLE (X86_64_06) },
1313   { X86_64_TABLE (X86_64_07) },
1314   /* 08 */
1315   { "orB",              { Eb, Gb } },
1316   { "orS",              { Ev, Gv } },
1317   { "orB",              { Gb, Eb } },
1318   { "orS",              { Gv, Ev } },
1319   { "orB",              { AL, Ib } },
1320   { "orS",              { eAX, Iv } },
1321   { X86_64_TABLE (X86_64_0D) },
1322   { "(bad)",            { XX } },       /* 0x0f extended opcode escape */
1323   /* 10 */
1324   { "adcB",             { Eb, Gb } },
1325   { "adcS",             { Ev, Gv } },
1326   { "adcB",             { Gb, Eb } },
1327   { "adcS",             { Gv, Ev } },
1328   { "adcB",             { AL, Ib } },
1329   { "adcS",             { eAX, Iv } },
1330   { X86_64_TABLE (X86_64_16) },
1331   { X86_64_TABLE (X86_64_17) },
1332   /* 18 */
1333   { "sbbB",             { Eb, Gb } },
1334   { "sbbS",             { Ev, Gv } },
1335   { "sbbB",             { Gb, Eb } },
1336   { "sbbS",             { Gv, Ev } },
1337   { "sbbB",             { AL, Ib } },
1338   { "sbbS",             { eAX, Iv } },
1339   { X86_64_TABLE (X86_64_1E) },
1340   { X86_64_TABLE (X86_64_1F) },
1341   /* 20 */
1342   { "andB",             { Eb, Gb } },
1343   { "andS",             { Ev, Gv } },
1344   { "andB",             { Gb, Eb } },
1345   { "andS",             { Gv, Ev } },
1346   { "andB",             { AL, Ib } },
1347   { "andS",             { eAX, Iv } },
1348   { "(bad)",            { XX } },       /* SEG ES prefix */
1349   { X86_64_TABLE (X86_64_27) },
1350   /* 28 */
1351   { "subB",             { Eb, Gb } },
1352   { "subS",             { Ev, Gv } },
1353   { "subB",             { Gb, Eb } },
1354   { "subS",             { Gv, Ev } },
1355   { "subB",             { AL, Ib } },
1356   { "subS",             { eAX, Iv } },
1357   { "(bad)",            { XX } },       /* SEG CS prefix */
1358   { X86_64_TABLE (X86_64_2F) },
1359   /* 30 */
1360   { "xorB",             { Eb, Gb } },
1361   { "xorS",             { Ev, Gv } },
1362   { "xorB",             { Gb, Eb } },
1363   { "xorS",             { Gv, Ev } },
1364   { "xorB",             { AL, Ib } },
1365   { "xorS",             { eAX, Iv } },
1366   { "(bad)",            { XX } },       /* SEG SS prefix */
1367   { X86_64_TABLE (X86_64_37) },
1368   /* 38 */
1369   { "cmpB",             { Eb, Gb } },
1370   { "cmpS",             { Ev, Gv } },
1371   { "cmpB",             { Gb, Eb } },
1372   { "cmpS",             { Gv, Ev } },
1373   { "cmpB",             { AL, Ib } },
1374   { "cmpS",             { eAX, Iv } },
1375   { "(bad)",            { XX } },       /* SEG DS prefix */
1376   { X86_64_TABLE (X86_64_3F) },
1377   /* 40 */
1378   { "inc{S|}",          { RMeAX } },
1379   { "inc{S|}",          { RMeCX } },
1380   { "inc{S|}",          { RMeDX } },
1381   { "inc{S|}",          { RMeBX } },
1382   { "inc{S|}",          { RMeSP } },
1383   { "inc{S|}",          { RMeBP } },
1384   { "inc{S|}",          { RMeSI } },
1385   { "inc{S|}",          { RMeDI } },
1386   /* 48 */
1387   { "dec{S|}",          { RMeAX } },
1388   { "dec{S|}",          { RMeCX } },
1389   { "dec{S|}",          { RMeDX } },
1390   { "dec{S|}",          { RMeBX } },
1391   { "dec{S|}",          { RMeSP } },
1392   { "dec{S|}",          { RMeBP } },
1393   { "dec{S|}",          { RMeSI } },
1394   { "dec{S|}",          { RMeDI } },
1395   /* 50 */
1396   { "pushV",            { RMrAX } },
1397   { "pushV",            { RMrCX } },
1398   { "pushV",            { RMrDX } },
1399   { "pushV",            { RMrBX } },
1400   { "pushV",            { RMrSP } },
1401   { "pushV",            { RMrBP } },
1402   { "pushV",            { RMrSI } },
1403   { "pushV",            { RMrDI } },
1404   /* 58 */
1405   { "popV",             { RMrAX } },
1406   { "popV",             { RMrCX } },
1407   { "popV",             { RMrDX } },
1408   { "popV",             { RMrBX } },
1409   { "popV",             { RMrSP } },
1410   { "popV",             { RMrBP } },
1411   { "popV",             { RMrSI } },
1412   { "popV",             { RMrDI } },
1413   /* 60 */
1414   { X86_64_TABLE (X86_64_60) },
1415   { X86_64_TABLE (X86_64_61) },
1416   { X86_64_TABLE (X86_64_62) },
1417   { X86_64_TABLE (X86_64_63) },
1418   { "(bad)",            { XX } },       /* seg fs */
1419   { "(bad)",            { XX } },       /* seg gs */
1420   { "(bad)",            { XX } },       /* op size prefix */
1421   { "(bad)",            { XX } },       /* adr size prefix */
1422   /* 68 */
1423   { "pushT",            { Iq } },
1424   { "imulS",            { Gv, Ev, Iv } },
1425   { "pushT",            { sIb } },
1426   { "imulS",            { Gv, Ev, sIb } },
1427   { "ins{b|}",          { Ybr, indirDX } },
1428   { X86_64_TABLE (X86_64_6D) },
1429   { "outs{b|}",         { indirDXr, Xb } },
1430   { X86_64_TABLE (X86_64_6F) },
1431   /* 70 */
1432   { "joH",              { Jb, XX, cond_jump_flag } },
1433   { "jnoH",             { Jb, XX, cond_jump_flag } },
1434   { "jbH",              { Jb, XX, cond_jump_flag } },
1435   { "jaeH",             { Jb, XX, cond_jump_flag } },
1436   { "jeH",              { Jb, XX, cond_jump_flag } },
1437   { "jneH",             { Jb, XX, cond_jump_flag } },
1438   { "jbeH",             { Jb, XX, cond_jump_flag } },
1439   { "jaH",              { Jb, XX, cond_jump_flag } },
1440   /* 78 */
1441   { "jsH",              { Jb, XX, cond_jump_flag } },
1442   { "jnsH",             { Jb, XX, cond_jump_flag } },
1443   { "jpH",              { Jb, XX, cond_jump_flag } },
1444   { "jnpH",             { Jb, XX, cond_jump_flag } },
1445   { "jlH",              { Jb, XX, cond_jump_flag } },
1446   { "jgeH",             { Jb, XX, cond_jump_flag } },
1447   { "jleH",             { Jb, XX, cond_jump_flag } },
1448   { "jgH",              { Jb, XX, cond_jump_flag } },
1449   /* 80 */
1450   { REG_TABLE (REG_80) },
1451   { REG_TABLE (REG_81) },
1452   { "(bad)",            { XX } },
1453   { REG_TABLE (REG_82) },
1454   { "testB",            { Eb, Gb } },
1455   { "testS",            { Ev, Gv } },
1456   { "xchgB",            { Eb, Gb } },
1457   { "xchgS",            { Ev, Gv } },
1458   /* 88 */
1459   { "movB",             { Eb, Gb } },
1460   { "movS",             { Ev, Gv } },
1461   { "movB",             { Gb, Eb } },
1462   { "movS",             { Gv, Ev } },
1463   { "movD",             { Sv, Sw } },
1464   { MOD_TABLE (MOD_8D) },
1465   { "movD",             { Sw, Sv } },
1466   { REG_TABLE (REG_8F) },
1467   /* 90 */
1468   { PREFIX_TABLE (PREFIX_90) },
1469   { "xchgS",            { RMeCX, eAX } },
1470   { "xchgS",            { RMeDX, eAX } },
1471   { "xchgS",            { RMeBX, eAX } },
1472   { "xchgS",            { RMeSP, eAX } },
1473   { "xchgS",            { RMeBP, eAX } },
1474   { "xchgS",            { RMeSI, eAX } },
1475   { "xchgS",            { RMeDI, eAX } },
1476   /* 98 */
1477   { "cW{t|}R",          { XX } },
1478   { "cR{t|}O",          { XX } },
1479   { X86_64_TABLE (X86_64_9A) },
1480   { "(bad)",            { XX } },       /* fwait */
1481   { "pushfT",           { XX } },
1482   { "popfT",            { XX } },
1483   { "sahf",             { XX } },
1484   { "lahf",             { XX } },
1485   /* a0 */
1486   { "movB",             { AL, Ob } },
1487   { "movS",             { eAX, Ov } },
1488   { "movB",             { Ob, AL } },
1489   { "movS",             { Ov, eAX } },
1490   { "movs{b|}",         { Ybr, Xb } },
1491   { "movs{R|}",         { Yvr, Xv } },
1492   { "cmps{b|}",         { Xb, Yb } },
1493   { "cmps{R|}",         { Xv, Yv } },
1494   /* a8 */
1495   { "testB",            { AL, Ib } },
1496   { "testS",            { eAX, Iv } },
1497   { "stosB",            { Ybr, AL } },
1498   { "stosS",            { Yvr, eAX } },
1499   { "lodsB",            { ALr, Xb } },
1500   { "lodsS",            { eAXr, Xv } },
1501   { "scasB",            { AL, Yb } },
1502   { "scasS",            { eAX, Yv } },
1503   /* b0 */
1504   { "movB",             { RMAL, Ib } },
1505   { "movB",             { RMCL, Ib } },
1506   { "movB",             { RMDL, Ib } },
1507   { "movB",             { RMBL, Ib } },
1508   { "movB",             { RMAH, Ib } },
1509   { "movB",             { RMCH, Ib } },
1510   { "movB",             { RMDH, Ib } },
1511   { "movB",             { RMBH, Ib } },
1512   /* b8 */
1513   { "movS",             { RMeAX, Iv64 } },
1514   { "movS",             { RMeCX, Iv64 } },
1515   { "movS",             { RMeDX, Iv64 } },
1516   { "movS",             { RMeBX, Iv64 } },
1517   { "movS",             { RMeSP, Iv64 } },
1518   { "movS",             { RMeBP, Iv64 } },
1519   { "movS",             { RMeSI, Iv64 } },
1520   { "movS",             { RMeDI, Iv64 } },
1521   /* c0 */
1522   { REG_TABLE (REG_C0) },
1523   { REG_TABLE (REG_C1) },
1524   { "retT",             { Iw } },
1525   { "retT",             { XX } },
1526   { X86_64_TABLE (X86_64_C4) },
1527   { X86_64_TABLE (X86_64_C5) },
1528   { REG_TABLE (REG_C6) },
1529   { REG_TABLE (REG_C7) },
1530   /* c8 */
1531   { "enterT",           { Iw, Ib } },
1532   { "leaveT",           { XX } },
1533   { "Jret{|f}P",        { Iw } },
1534   { "Jret{|f}P",        { XX } },
1535   { "int3",             { XX } },
1536   { "int",              { Ib } },
1537   { X86_64_TABLE (X86_64_CE) },
1538   { "iretP",            { XX } },
1539   /* d0 */
1540   { REG_TABLE (REG_D0) },
1541   { REG_TABLE (REG_D1) },
1542   { REG_TABLE (REG_D2) },
1543   { REG_TABLE (REG_D3) },
1544   { X86_64_TABLE (X86_64_D4) },
1545   { X86_64_TABLE (X86_64_D5) },
1546   { "(bad)",            { XX } },
1547   { "xlat",             { DSBX } },
1548   /* d8 */
1549   { FLOAT },
1550   { FLOAT },
1551   { FLOAT },
1552   { FLOAT },
1553   { FLOAT },
1554   { FLOAT },
1555   { FLOAT },
1556   { FLOAT },
1557   /* e0 */
1558   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1559   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1560   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1561   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1562   { "inB",              { AL, Ib } },
1563   { "inG",              { zAX, Ib } },
1564   { "outB",             { Ib, AL } },
1565   { "outG",             { Ib, zAX } },
1566   /* e8 */
1567   { "callT",            { Jv } },
1568   { "jmpT",             { Jv } },
1569   { X86_64_TABLE (X86_64_EA) },
1570   { "jmp",              { Jb } },
1571   { "inB",              { AL, indirDX } },
1572   { "inG",              { zAX, indirDX } },
1573   { "outB",             { indirDX, AL } },
1574   { "outG",             { indirDX, zAX } },
1575   /* f0 */
1576   { "(bad)",            { XX } },       /* lock prefix */
1577   { "icebp",            { XX } },
1578   { "(bad)",            { XX } },       /* repne */
1579   { "(bad)",            { XX } },       /* repz */
1580   { "hlt",              { XX } },
1581   { "cmc",              { XX } },
1582   { REG_TABLE (REG_F6) },
1583   { REG_TABLE (REG_F7) },
1584   /* f8 */
1585   { "clc",              { XX } },
1586   { "stc",              { XX } },
1587   { "cli",              { XX } },
1588   { "sti",              { XX } },
1589   { "cld",              { XX } },
1590   { "std",              { XX } },
1591   { REG_TABLE (REG_FE) },
1592   { REG_TABLE (REG_FF) },
1593 };
1594
1595 static const struct dis386 dis386_twobyte[] = {
1596   /* 00 */
1597   { REG_TABLE (REG_0F00 ) },
1598   { REG_TABLE (REG_0F01 ) },
1599   { "larS",             { Gv, Ew } },
1600   { "lslS",             { Gv, Ew } },
1601   { "(bad)",            { XX } },
1602   { "syscall",          { XX } },
1603   { "clts",             { XX } },
1604   { "sysretP",          { XX } },
1605   /* 08 */
1606   { "invd",             { XX } },
1607   { "wbinvd",           { XX } },
1608   { "(bad)",            { XX } },
1609   { "ud2a",             { XX } },
1610   { "(bad)",            { XX } },
1611   { REG_TABLE (REG_0F0D) },
1612   { "femms",            { XX } },
1613   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1614   /* 10 */
1615   { PREFIX_TABLE (PREFIX_0F10) },
1616   { PREFIX_TABLE (PREFIX_0F11) },
1617   { PREFIX_TABLE (PREFIX_0F12) },
1618   { MOD_TABLE (MOD_0F13) },
1619   { "unpcklpX",         { XM, EXx } },
1620   { "unpckhpX",         { XM, EXx } },
1621   { PREFIX_TABLE (PREFIX_0F16) },
1622   { MOD_TABLE (MOD_0F17) },
1623   /* 18 */
1624   { REG_TABLE (REG_0F18) },
1625   { "nopQ",             { Ev } },
1626   { "nopQ",             { Ev } },
1627   { "nopQ",             { Ev } },
1628   { "nopQ",             { Ev } },
1629   { "nopQ",             { Ev } },
1630   { "nopQ",             { Ev } },
1631   { "nopQ",             { Ev } },
1632   /* 20 */
1633   { MOD_TABLE (MOD_0F20) },
1634   { MOD_TABLE (MOD_0F21) },
1635   { MOD_TABLE (MOD_0F22) },
1636   { MOD_TABLE (MOD_0F23) },
1637   { MOD_TABLE (MOD_0F24) },
1638   { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1639   { MOD_TABLE (MOD_0F26) },
1640   { "(bad)",            { XX } },
1641   /* 28 */
1642   { "movapX",           { XM, EXx } },
1643   { "movapX",           { EXx, XM } },
1644   { PREFIX_TABLE (PREFIX_0F2A) },
1645   { PREFIX_TABLE (PREFIX_0F2B) },
1646   { PREFIX_TABLE (PREFIX_0F2C) },
1647   { PREFIX_TABLE (PREFIX_0F2D) },
1648   { PREFIX_TABLE (PREFIX_0F2E) },
1649   { PREFIX_TABLE (PREFIX_0F2F) },
1650   /* 30 */
1651   { "wrmsr",            { XX } },
1652   { "rdtsc",            { XX } },
1653   { "rdmsr",            { XX } },
1654   { "rdpmc",            { XX } },
1655   { "sysenter",         { XX } },
1656   { "sysexit",          { XX } },
1657   { "(bad)",            { XX } },
1658   { "getsec",           { XX } },
1659   /* 38 */
1660   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1661   { "(bad)",            { XX } },
1662   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1663   { "(bad)",            { XX } },
1664   { "(bad)",            { XX } },
1665   { "(bad)",            { XX } },
1666   { "(bad)",            { XX } },
1667   { "(bad)",            { XX } },
1668   /* 40 */
1669   { "cmovoS",           { Gv, Ev } },
1670   { "cmovnoS",          { Gv, Ev } },
1671   { "cmovbS",           { Gv, Ev } },
1672   { "cmovaeS",          { Gv, Ev } },
1673   { "cmoveS",           { Gv, Ev } },
1674   { "cmovneS",          { Gv, Ev } },
1675   { "cmovbeS",          { Gv, Ev } },
1676   { "cmovaS",           { Gv, Ev } },
1677   /* 48 */
1678   { "cmovsS",           { Gv, Ev } },
1679   { "cmovnsS",          { Gv, Ev } },
1680   { "cmovpS",           { Gv, Ev } },
1681   { "cmovnpS",          { Gv, Ev } },
1682   { "cmovlS",           { Gv, Ev } },
1683   { "cmovgeS",          { Gv, Ev } },
1684   { "cmovleS",          { Gv, Ev } },
1685   { "cmovgS",           { Gv, Ev } },
1686   /* 50 */
1687   { MOD_TABLE (MOD_0F51) },
1688   { PREFIX_TABLE (PREFIX_0F51) },
1689   { PREFIX_TABLE (PREFIX_0F52) },
1690   { PREFIX_TABLE (PREFIX_0F53) },
1691   { "andpX",            { XM, EXx } },
1692   { "andnpX",           { XM, EXx } },
1693   { "orpX",             { XM, EXx } },
1694   { "xorpX",            { XM, EXx } },
1695   /* 58 */
1696   { PREFIX_TABLE (PREFIX_0F58) },
1697   { PREFIX_TABLE (PREFIX_0F59) },
1698   { PREFIX_TABLE (PREFIX_0F5A) },
1699   { PREFIX_TABLE (PREFIX_0F5B) },
1700   { PREFIX_TABLE (PREFIX_0F5C) },
1701   { PREFIX_TABLE (PREFIX_0F5D) },
1702   { PREFIX_TABLE (PREFIX_0F5E) },
1703   { PREFIX_TABLE (PREFIX_0F5F) },
1704   /* 60 */
1705   { PREFIX_TABLE (PREFIX_0F60) },
1706   { PREFIX_TABLE (PREFIX_0F61) },
1707   { PREFIX_TABLE (PREFIX_0F62) },
1708   { "packsswb",         { MX, EM } },
1709   { "pcmpgtb",          { MX, EM } },
1710   { "pcmpgtw",          { MX, EM } },
1711   { "pcmpgtd",          { MX, EM } },
1712   { "packuswb",         { MX, EM } },
1713   /* 68 */
1714   { "punpckhbw",        { MX, EM } },
1715   { "punpckhwd",        { MX, EM } },
1716   { "punpckhdq",        { MX, EM } },
1717   { "packssdw",         { MX, EM } },
1718   { PREFIX_TABLE (PREFIX_0F6C) },
1719   { PREFIX_TABLE (PREFIX_0F6D) },
1720   { "movK",             { MX, Edq } },
1721   { PREFIX_TABLE (PREFIX_0F6F) },
1722   /* 70 */
1723   { PREFIX_TABLE (PREFIX_0F70) },
1724   { REG_TABLE (REG_0F71) },
1725   { REG_TABLE (REG_0F72) },
1726   { REG_TABLE (REG_0F73) },
1727   { "pcmpeqb",          { MX, EM } },
1728   { "pcmpeqw",          { MX, EM } },
1729   { "pcmpeqd",          { MX, EM } },
1730   { "emms",             { XX } },
1731   /* 78 */
1732   { PREFIX_TABLE (PREFIX_0F78) },
1733   { PREFIX_TABLE (PREFIX_0F79) },
1734   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1735   { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1736   { PREFIX_TABLE (PREFIX_0F7C) },
1737   { PREFIX_TABLE (PREFIX_0F7D) },
1738   { PREFIX_TABLE (PREFIX_0F7E) },
1739   { PREFIX_TABLE (PREFIX_0F7F) },
1740   /* 80 */
1741   { "joH",              { Jv, XX, cond_jump_flag } },
1742   { "jnoH",             { Jv, XX, cond_jump_flag } },
1743   { "jbH",              { Jv, XX, cond_jump_flag } },
1744   { "jaeH",             { Jv, XX, cond_jump_flag } },
1745   { "jeH",              { Jv, XX, cond_jump_flag } },
1746   { "jneH",             { Jv, XX, cond_jump_flag } },
1747   { "jbeH",             { Jv, XX, cond_jump_flag } },
1748   { "jaH",              { Jv, XX, cond_jump_flag } },
1749   /* 88 */
1750   { "jsH",              { Jv, XX, cond_jump_flag } },
1751   { "jnsH",             { Jv, XX, cond_jump_flag } },
1752   { "jpH",              { Jv, XX, cond_jump_flag } },
1753   { "jnpH",             { Jv, XX, cond_jump_flag } },
1754   { "jlH",              { Jv, XX, cond_jump_flag } },
1755   { "jgeH",             { Jv, XX, cond_jump_flag } },
1756   { "jleH",             { Jv, XX, cond_jump_flag } },
1757   { "jgH",              { Jv, XX, cond_jump_flag } },
1758   /* 90 */
1759   { "seto",             { Eb } },
1760   { "setno",            { Eb } },
1761   { "setb",             { Eb } },
1762   { "setae",            { Eb } },
1763   { "sete",             { Eb } },
1764   { "setne",            { Eb } },
1765   { "setbe",            { Eb } },
1766   { "seta",             { Eb } },
1767   /* 98 */
1768   { "sets",             { Eb } },
1769   { "setns",            { Eb } },
1770   { "setp",             { Eb } },
1771   { "setnp",            { Eb } },
1772   { "setl",             { Eb } },
1773   { "setge",            { Eb } },
1774   { "setle",            { Eb } },
1775   { "setg",             { Eb } },
1776   /* a0 */
1777   { "pushT",            { fs } },
1778   { "popT",             { fs } },
1779   { "cpuid",            { XX } },
1780   { "btS",              { Ev, Gv } },
1781   { "shldS",            { Ev, Gv, Ib } },
1782   { "shldS",            { Ev, Gv, CL } },
1783   { REG_TABLE (REG_0FA6) },
1784   { REG_TABLE (REG_0FA7) },
1785   /* a8 */
1786   { "pushT",            { gs } },
1787   { "popT",             { gs } },
1788   { "rsm",              { XX } },
1789   { "btsS",             { Ev, Gv } },
1790   { "shrdS",            { Ev, Gv, Ib } },
1791   { "shrdS",            { Ev, Gv, CL } },
1792   { REG_TABLE (REG_0FAE) },
1793   { "imulS",            { Gv, Ev } },
1794   /* b0 */
1795   { "cmpxchgB",         { Eb, Gb } },
1796   { "cmpxchgS",         { Ev, Gv } },
1797   { MOD_TABLE (MOD_0FB2) },
1798   { "btrS",             { Ev, Gv } },
1799   { MOD_TABLE (MOD_0FB4) },
1800   { MOD_TABLE (MOD_0FB5) },
1801   { "movz{bR|x}",       { Gv, Eb } },
1802   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
1803   /* b8 */
1804   { PREFIX_TABLE (PREFIX_0FB8) },
1805   { "ud2b",             { XX } },
1806   { REG_TABLE (REG_0FBA) },
1807   { "btcS",             { Ev, Gv } },
1808   { "bsfS",             { Gv, Ev } },
1809   { PREFIX_TABLE (PREFIX_0FBD) },
1810   { "movs{bR|x}",       { Gv, Eb } },
1811   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
1812   /* c0 */
1813   { "xaddB",            { Eb, Gb } },
1814   { "xaddS",            { Ev, Gv } },
1815   { PREFIX_TABLE (PREFIX_0FC2) },
1816   { PREFIX_TABLE (PREFIX_0FC3) },
1817   { "pinsrw",           { MX, Edqw, Ib } },
1818   { "pextrw",           { Gdq, MS, Ib } },
1819   { "shufpX",           { XM, EXx, Ib } },
1820   { REG_TABLE (REG_0FC7) },
1821   /* c8 */
1822   { "bswap",            { RMeAX } },
1823   { "bswap",            { RMeCX } },
1824   { "bswap",            { RMeDX } },
1825   { "bswap",            { RMeBX } },
1826   { "bswap",            { RMeSP } },
1827   { "bswap",            { RMeBP } },
1828   { "bswap",            { RMeSI } },
1829   { "bswap",            { RMeDI } },
1830   /* d0 */
1831   { PREFIX_TABLE (PREFIX_0FD0) },
1832   { "psrlw",            { MX, EM } },
1833   { "psrld",            { MX, EM } },
1834   { "psrlq",            { MX, EM } },
1835   { "paddq",            { MX, EM } },
1836   { "pmullw",           { MX, EM } },
1837   { PREFIX_TABLE (PREFIX_0FD6) },
1838   { MOD_TABLE (MOD_0FD7) },
1839   /* d8 */
1840   { "psubusb",          { MX, EM } },
1841   { "psubusw",          { MX, EM } },
1842   { "pminub",           { MX, EM } },
1843   { "pand",             { MX, EM } },
1844   { "paddusb",          { MX, EM } },
1845   { "paddusw",          { MX, EM } },
1846   { "pmaxub",           { MX, EM } },
1847   { "pandn",            { MX, EM } },
1848   /* e0 */
1849   { "pavgb",            { MX, EM } },
1850   { "psraw",            { MX, EM } },
1851   { "psrad",            { MX, EM } },
1852   { "pavgw",            { MX, EM } },
1853   { "pmulhuw",          { MX, EM } },
1854   { "pmulhw",           { MX, EM } },
1855   { PREFIX_TABLE (PREFIX_0FE6) },
1856   { PREFIX_TABLE (PREFIX_0FE7) },
1857   /* e8 */
1858   { "psubsb",           { MX, EM } },
1859   { "psubsw",           { MX, EM } },
1860   { "pminsw",           { MX, EM } },
1861   { "por",              { MX, EM } },
1862   { "paddsb",           { MX, EM } },
1863   { "paddsw",           { MX, EM } },
1864   { "pmaxsw",           { MX, EM } },
1865   { "pxor",             { MX, EM } },
1866   /* f0 */
1867   { PREFIX_TABLE (PREFIX_0FF0) },
1868   { "psllw",            { MX, EM } },
1869   { "pslld",            { MX, EM } },
1870   { "psllq",            { MX, EM } },
1871   { "pmuludq",          { MX, EM } },
1872   { "pmaddwd",          { MX, EM } },
1873   { "psadbw",           { MX, EM } },
1874   { PREFIX_TABLE (PREFIX_0FF7) },
1875   /* f8 */
1876   { "psubb",            { MX, EM } },
1877   { "psubw",            { MX, EM } },
1878   { "psubd",            { MX, EM } },
1879   { "psubq",            { MX, EM } },
1880   { "paddb",            { MX, EM } },
1881   { "paddw",            { MX, EM } },
1882   { "paddd",            { MX, EM } },
1883   { "(bad)",            { XX } },
1884 };
1885
1886 static const unsigned char onebyte_has_modrm[256] = {
1887   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1888   /*       -------------------------------        */
1889   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1890   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1891   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1892   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1893   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1894   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1895   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1896   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1897   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1898   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1899   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1900   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1901   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1902   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1903   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1904   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
1905   /*       -------------------------------        */
1906   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1907 };
1908
1909 static const unsigned char twobyte_has_modrm[256] = {
1910   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1911   /*       -------------------------------        */
1912   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1913   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1914   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1915   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1916   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1917   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1918   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1919   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1920   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1921   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1922   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1923   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1924   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1925   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1926   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1927   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
1928   /*       -------------------------------        */
1929   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1930 };
1931
1932 static char obuf[100];
1933 static char *obufp;
1934 static char *mnemonicendp;
1935 static char scratchbuf[100];
1936 static unsigned char *start_codep;
1937 static unsigned char *insn_codep;
1938 static unsigned char *codep;
1939 static const char *lock_prefix;
1940 static const char *data_prefix;
1941 static const char *addr_prefix;
1942 static const char *repz_prefix;
1943 static const char *repnz_prefix;
1944 static disassemble_info *the_info;
1945 static struct
1946   {
1947     int mod;
1948     int reg;
1949     int rm;
1950   }
1951 modrm;
1952 static unsigned char need_modrm;
1953 static struct
1954   {
1955     int register_specifier;
1956     int length;
1957     int prefix;
1958     int w;
1959   }
1960 vex;
1961 static unsigned char need_vex;
1962 static unsigned char need_vex_reg;
1963 static unsigned char vex_w_done;
1964
1965 struct op
1966   {
1967     const char *name;
1968     unsigned int len;
1969   };
1970
1971 /* If we are accessing mod/rm/reg without need_modrm set, then the
1972    values are stale.  Hitting this abort likely indicates that you
1973    need to update onebyte_has_modrm or twobyte_has_modrm.  */
1974 #define MODRM_CHECK  if (!need_modrm) abort ()
1975
1976 static const char **names64;
1977 static const char **names32;
1978 static const char **names16;
1979 static const char **names8;
1980 static const char **names8rex;
1981 static const char **names_seg;
1982 static const char *index64;
1983 static const char *index32;
1984 static const char **index16;
1985
1986 static const char *intel_names64[] = {
1987   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1988   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1989 };
1990 static const char *intel_names32[] = {
1991   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1992   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1993 };
1994 static const char *intel_names16[] = {
1995   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1996   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1997 };
1998 static const char *intel_names8[] = {
1999   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2000 };
2001 static const char *intel_names8rex[] = {
2002   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2003   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2004 };
2005 static const char *intel_names_seg[] = {
2006   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2007 };
2008 static const char *intel_index64 = "riz";
2009 static const char *intel_index32 = "eiz";
2010 static const char *intel_index16[] = {
2011   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2012 };
2013
2014 static const char *att_names64[] = {
2015   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2016   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2017 };
2018 static const char *att_names32[] = {
2019   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2020   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2021 };
2022 static const char *att_names16[] = {
2023   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2024   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2025 };
2026 static const char *att_names8[] = {
2027   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2028 };
2029 static const char *att_names8rex[] = {
2030   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2031   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2032 };
2033 static const char *att_names_seg[] = {
2034   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2035 };
2036 static const char *att_index64 = "%riz";
2037 static const char *att_index32 = "%eiz";
2038 static const char *att_index16[] = {
2039   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2040 };
2041
2042 static const struct dis386 reg_table[][8] = {
2043   /* REG_80 */
2044   {
2045     { "addA",   { Eb, Ib } },
2046     { "orA",    { Eb, Ib } },
2047     { "adcA",   { Eb, Ib } },
2048     { "sbbA",   { Eb, Ib } },
2049     { "andA",   { Eb, Ib } },
2050     { "subA",   { Eb, Ib } },
2051     { "xorA",   { Eb, Ib } },
2052     { "cmpA",   { Eb, Ib } },
2053   },
2054   /* REG_81 */
2055   {
2056     { "addQ",   { Ev, Iv } },
2057     { "orQ",    { Ev, Iv } },
2058     { "adcQ",   { Ev, Iv } },
2059     { "sbbQ",   { Ev, Iv } },
2060     { "andQ",   { Ev, Iv } },
2061     { "subQ",   { Ev, Iv } },
2062     { "xorQ",   { Ev, Iv } },
2063     { "cmpQ",   { Ev, Iv } },
2064   },
2065   /* REG_82 */
2066   {
2067     { "addQ",   { Ev, sIb } },
2068     { "orQ",    { Ev, sIb } },
2069     { "adcQ",   { Ev, sIb } },
2070     { "sbbQ",   { Ev, sIb } },
2071     { "andQ",   { Ev, sIb } },
2072     { "subQ",   { Ev, sIb } },
2073     { "xorQ",   { Ev, sIb } },
2074     { "cmpQ",   { Ev, sIb } },
2075   },
2076   /* REG_8F */
2077   {
2078     { "popU",   { stackEv } },
2079     { "(bad)",  { XX } },
2080     { "(bad)",  { XX } },
2081     { "(bad)",  { XX } },
2082     { "(bad)",  { XX } },
2083     { "(bad)",  { XX } },
2084     { "(bad)",  { XX } },
2085     { "(bad)",  { XX } },
2086   },
2087   /* REG_C0 */
2088   {
2089     { "rolA",   { Eb, Ib } },
2090     { "rorA",   { Eb, Ib } },
2091     { "rclA",   { Eb, Ib } },
2092     { "rcrA",   { Eb, Ib } },
2093     { "shlA",   { Eb, Ib } },
2094     { "shrA",   { Eb, Ib } },
2095     { "(bad)",  { XX } },
2096     { "sarA",   { Eb, Ib } },
2097   },
2098   /* REG_C1 */
2099   {
2100     { "rolQ",   { Ev, Ib } },
2101     { "rorQ",   { Ev, Ib } },
2102     { "rclQ",   { Ev, Ib } },
2103     { "rcrQ",   { Ev, Ib } },
2104     { "shlQ",   { Ev, Ib } },
2105     { "shrQ",   { Ev, Ib } },
2106     { "(bad)",  { XX } },
2107     { "sarQ",   { Ev, Ib } },
2108   },
2109   /* REG_C6 */
2110   {
2111     { "movA",   { Eb, Ib } },
2112     { "(bad)",  { XX } },
2113     { "(bad)",  { XX } },
2114     { "(bad)",  { XX } },
2115     { "(bad)",  { XX } },
2116     { "(bad)",  { XX } },
2117     { "(bad)",  { XX } },
2118     { "(bad)",  { XX } },
2119   },
2120   /* REG_C7 */
2121   {
2122     { "movQ",   { Ev, Iv } },
2123     { "(bad)",  { XX } },
2124     { "(bad)",  { XX } },
2125     { "(bad)",  { XX } },
2126     { "(bad)",  { XX } },
2127     { "(bad)",  { XX } },
2128     { "(bad)",  { XX } },
2129     { "(bad)",  { XX } },
2130   },
2131   /* REG_D0 */
2132   {
2133     { "rolA",   { Eb, I1 } },
2134     { "rorA",   { Eb, I1 } },
2135     { "rclA",   { Eb, I1 } },
2136     { "rcrA",   { Eb, I1 } },
2137     { "shlA",   { Eb, I1 } },
2138     { "shrA",   { Eb, I1 } },
2139     { "(bad)",  { XX } },
2140     { "sarA",   { Eb, I1 } },
2141   },
2142   /* REG_D1 */
2143   {
2144     { "rolQ",   { Ev, I1 } },
2145     { "rorQ",   { Ev, I1 } },
2146     { "rclQ",   { Ev, I1 } },
2147     { "rcrQ",   { Ev, I1 } },
2148     { "shlQ",   { Ev, I1 } },
2149     { "shrQ",   { Ev, I1 } },
2150     { "(bad)",  { XX } },
2151     { "sarQ",   { Ev, I1 } },
2152   },
2153   /* REG_D2 */
2154   {
2155     { "rolA",   { Eb, CL } },
2156     { "rorA",   { Eb, CL } },
2157     { "rclA",   { Eb, CL } },
2158     { "rcrA",   { Eb, CL } },
2159     { "shlA",   { Eb, CL } },
2160     { "shrA",   { Eb, CL } },
2161     { "(bad)",  { XX } },
2162     { "sarA",   { Eb, CL } },
2163   },
2164   /* REG_D3 */
2165   {
2166     { "rolQ",   { Ev, CL } },
2167     { "rorQ",   { Ev, CL } },
2168     { "rclQ",   { Ev, CL } },
2169     { "rcrQ",   { Ev, CL } },
2170     { "shlQ",   { Ev, CL } },
2171     { "shrQ",   { Ev, CL } },
2172     { "(bad)",  { XX } },
2173     { "sarQ",   { Ev, CL } },
2174   },
2175   /* REG_F6 */
2176   {
2177     { "testA",  { Eb, Ib } },
2178     { "(bad)",  { XX } },
2179     { "notA",   { Eb } },
2180     { "negA",   { Eb } },
2181     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2182     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2183     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2184     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2185   },
2186   /* REG_F7 */
2187   {
2188     { "testQ",  { Ev, Iv } },
2189     { "(bad)",  { XX } },
2190     { "notQ",   { Ev } },
2191     { "negQ",   { Ev } },
2192     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2193     { "imulQ",  { Ev } },
2194     { "divQ",   { Ev } },
2195     { "idivQ",  { Ev } },
2196   },
2197   /* REG_FE */
2198   {
2199     { "incA",   { Eb } },
2200     { "decA",   { Eb } },
2201     { "(bad)",  { XX } },
2202     { "(bad)",  { XX } },
2203     { "(bad)",  { XX } },
2204     { "(bad)",  { XX } },
2205     { "(bad)",  { XX } },
2206     { "(bad)",  { XX } },
2207   },
2208   /* REG_FF */
2209   {
2210     { "incQ",   { Ev } },
2211     { "decQ",   { Ev } },
2212     { "callT",  { indirEv } },
2213     { "JcallT", { indirEp } },
2214     { "jmpT",   { indirEv } },
2215     { "JjmpT",  { indirEp } },
2216     { "pushU",  { stackEv } },
2217     { "(bad)",  { XX } },
2218   },
2219   /* REG_0F00 */
2220   {
2221     { "sldtD",  { Sv } },
2222     { "strD",   { Sv } },
2223     { "lldt",   { Ew } },
2224     { "ltr",    { Ew } },
2225     { "verr",   { Ew } },
2226     { "verw",   { Ew } },
2227     { "(bad)",  { XX } },
2228     { "(bad)",  { XX } },
2229   },
2230   /* REG_0F01 */
2231   {
2232     { MOD_TABLE (MOD_0F01_REG_0) },
2233     { MOD_TABLE (MOD_0F01_REG_1) },
2234     { MOD_TABLE (MOD_0F01_REG_2) },
2235     { MOD_TABLE (MOD_0F01_REG_3) },
2236     { "smswD",  { Sv } },
2237     { "(bad)",  { XX } },
2238     { "lmsw",   { Ew } },
2239     { MOD_TABLE (MOD_0F01_REG_7) },
2240   },
2241   /* REG_0F0D */
2242   {
2243     { "prefetch",       { Eb } },
2244     { "prefetchw",      { Eb } },
2245     { "(bad)",          { XX } },
2246     { "(bad)",          { XX } },
2247     { "(bad)",          { XX } },
2248     { "(bad)",          { XX } },
2249     { "(bad)",          { XX } },
2250     { "(bad)",          { XX } },
2251   },
2252   /* REG_0F18 */
2253   {
2254     { MOD_TABLE (MOD_0F18_REG_0) },
2255     { MOD_TABLE (MOD_0F18_REG_1) },
2256     { MOD_TABLE (MOD_0F18_REG_2) },
2257     { MOD_TABLE (MOD_0F18_REG_3) },
2258     { "(bad)",  { XX } },
2259     { "(bad)",  { XX } },
2260     { "(bad)",  { XX } },
2261     { "(bad)",  { XX } },
2262   },
2263   /* REG_0F71 */
2264   {
2265     { "(bad)",  { XX } },
2266     { "(bad)",  { XX } },
2267     { MOD_TABLE (MOD_0F71_REG_2) },
2268     { "(bad)",  { XX } },
2269     { MOD_TABLE (MOD_0F71_REG_4) },
2270     { "(bad)",  { XX } },
2271     { MOD_TABLE (MOD_0F71_REG_6) },
2272     { "(bad)",  { XX } },
2273   },
2274   /* REG_0F72 */
2275   {
2276     { "(bad)",  { XX } },
2277     { "(bad)",  { XX } },
2278     { MOD_TABLE (MOD_0F72_REG_2) },
2279     { "(bad)",  { XX } },
2280     { MOD_TABLE (MOD_0F72_REG_4) },
2281     { "(bad)",  { XX } },
2282     { MOD_TABLE (MOD_0F72_REG_6) },
2283     { "(bad)",  { XX } },
2284   },
2285   /* REG_0F73 */
2286   {
2287     { "(bad)",  { XX } },
2288     { "(bad)",  { XX } },
2289     { MOD_TABLE (MOD_0F73_REG_2) },
2290     { MOD_TABLE (MOD_0F73_REG_3) },
2291     { "(bad)",  { XX } },
2292     { "(bad)",  { XX } },
2293     { MOD_TABLE (MOD_0F73_REG_6) },
2294     { MOD_TABLE (MOD_0F73_REG_7) },
2295   },
2296   /* REG_0FA6 */
2297   {
2298     { "montmul",        { { OP_0f07, 0 } } },
2299     { "xsha1",          { { OP_0f07, 0 } } },
2300     { "xsha256",        { { OP_0f07, 0 } } },
2301     { "(bad)",          { { OP_0f07, 0 } } },
2302     { "(bad)",          { { OP_0f07, 0 } } },
2303     { "(bad)",          { { OP_0f07, 0 } } },
2304     { "(bad)",          { { OP_0f07, 0 } } },
2305     { "(bad)",          { { OP_0f07, 0 } } },
2306   },
2307   /* REG_0FA7 */
2308   {
2309     { "xstore-rng",     { { OP_0f07, 0 } } },
2310     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2311     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2312     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2313     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2314     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2315     { "(bad)",          { { OP_0f07, 0 } } },
2316     { "(bad)",          { { OP_0f07, 0 } } },
2317   },
2318   /* REG_0FAE */
2319   {
2320     { MOD_TABLE (MOD_0FAE_REG_0) },
2321     { MOD_TABLE (MOD_0FAE_REG_1) },
2322     { MOD_TABLE (MOD_0FAE_REG_2) },
2323     { MOD_TABLE (MOD_0FAE_REG_3) },
2324     { MOD_TABLE (MOD_0FAE_REG_4) },
2325     { MOD_TABLE (MOD_0FAE_REG_5) },
2326     { MOD_TABLE (MOD_0FAE_REG_6) },
2327     { MOD_TABLE (MOD_0FAE_REG_7) },
2328   },
2329   /* REG_0FBA */
2330   {
2331     { "(bad)",  { XX } },
2332     { "(bad)",  { XX } },
2333     { "(bad)",  { XX } },
2334     { "(bad)",  { XX } },
2335     { "btQ",    { Ev, Ib } },
2336     { "btsQ",   { Ev, Ib } },
2337     { "btrQ",   { Ev, Ib } },
2338     { "btcQ",   { Ev, Ib } },
2339   },
2340   /* REG_0FC7 */
2341   {
2342     { "(bad)",  { XX } },
2343     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2344     { "(bad)",  { XX } },
2345     { "(bad)",  { XX } },
2346     { "(bad)",  { XX } },
2347     { "(bad)",  { XX } },
2348     { MOD_TABLE (MOD_0FC7_REG_6) },
2349     { MOD_TABLE (MOD_0FC7_REG_7) },
2350   },
2351   /* REG_VEX_71 */
2352   {
2353     { "(bad)",  { XX } },
2354     { "(bad)",  { XX } },
2355     { MOD_TABLE (MOD_VEX_71_REG_2) },
2356     { "(bad)",  { XX } },
2357     { MOD_TABLE (MOD_VEX_71_REG_4) },
2358     { "(bad)",  { XX } },
2359     { MOD_TABLE (MOD_VEX_71_REG_6) },
2360     { "(bad)",  { XX } },
2361   },
2362   /* REG_VEX_72 */
2363   {
2364     { "(bad)",  { XX } },
2365     { "(bad)",  { XX } },
2366     { MOD_TABLE (MOD_VEX_72_REG_2) },
2367     { "(bad)",  { XX } },
2368     { MOD_TABLE (MOD_VEX_72_REG_4) },
2369     { "(bad)",  { XX } },
2370     { MOD_TABLE (MOD_VEX_72_REG_6) },
2371     { "(bad)",  { XX } },
2372   },
2373   /* REG_VEX_73 */
2374   {
2375     { "(bad)",  { XX } },
2376     { "(bad)",  { XX } },
2377     { MOD_TABLE (MOD_VEX_73_REG_2) },
2378     { MOD_TABLE (MOD_VEX_73_REG_3) },
2379     { "(bad)",  { XX } },
2380     { "(bad)",  { XX } },
2381     { MOD_TABLE (MOD_VEX_73_REG_6) },
2382     { MOD_TABLE (MOD_VEX_73_REG_7) },
2383   },
2384   /* REG_VEX_AE */
2385   {
2386     { "(bad)",  { XX } },
2387     { "(bad)",  { XX } },
2388     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2389     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2390     { "(bad)",  { XX } },
2391     { "(bad)",  { XX } },
2392     { "(bad)",  { XX } },
2393     { "(bad)",  { XX } },
2394   },
2395 };
2396
2397 static const struct dis386 prefix_table[][4] = {
2398   /* PREFIX_90 */
2399   {
2400     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2401     { "pause", { XX } },
2402     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2403     { "(bad)", { XX } },
2404   },
2405
2406   /* PREFIX_0F10 */
2407   {
2408     { "movups", { XM, EXx } },
2409     { "movss",  { XM, EXd } },
2410     { "movupd", { XM, EXx } },
2411     { "movsd",  { XM, EXq } },
2412   },
2413
2414   /* PREFIX_0F11 */
2415   {
2416     { "movups", { EXx, XM } },
2417     { "movss",  { EXd, XM } },
2418     { "movupd", { EXx, XM } },
2419     { "movsd",  { EXq, XM } },
2420   },
2421
2422   /* PREFIX_0F12 */
2423   {
2424     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2425     { "movsldup", { XM, EXx } },
2426     { "movlpd", { XM, EXq } },
2427     { "movddup", { XM, EXq } },
2428   },
2429
2430   /* PREFIX_0F16 */
2431   {
2432     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2433     { "movshdup", { XM, EXx } },
2434     { "movhpd", { XM, EXq } },
2435     { "(bad)",  { XX } },
2436   },
2437
2438   /* PREFIX_0F2A */
2439   {
2440     { "cvtpi2ps", { XM, EMCq } },
2441     { "cvtsi2ss%LQ", { XM, Ev } },
2442     { "cvtpi2pd", { XM, EMCq } },
2443     { "cvtsi2sd%LQ", { XM, Ev } },
2444   },
2445
2446   /* PREFIX_0F2B */
2447   {
2448     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2449     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2450     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2451     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2452   },
2453
2454   /* PREFIX_0F2C */
2455   {
2456     { "cvttps2pi", { MXC, EXq } },
2457     { "cvttss2siY", { Gv, EXd } },
2458     { "cvttpd2pi", { MXC, EXx } },
2459     { "cvttsd2siY", { Gv, EXq } },
2460   },
2461
2462   /* PREFIX_0F2D */
2463   {
2464     { "cvtps2pi", { MXC, EXq } },
2465     { "cvtss2siY", { Gv, EXd } },
2466     { "cvtpd2pi", { MXC, EXx } },
2467     { "cvtsd2siY", { Gv, EXq } },
2468   },
2469
2470   /* PREFIX_0F2E */
2471   {
2472     { "ucomiss",{ XM, EXd } },
2473     { "(bad)",  { XX } },
2474     { "ucomisd",{ XM, EXq } },
2475     { "(bad)",  { XX } },
2476   },
2477
2478   /* PREFIX_0F2F */
2479   {
2480     { "comiss", { XM, EXd } },
2481     { "(bad)",  { XX } },
2482     { "comisd", { XM, EXq } },
2483     { "(bad)",  { XX } },
2484   },
2485
2486   /* PREFIX_0F51 */
2487   {
2488     { "sqrtps", { XM, EXx } },
2489     { "sqrtss", { XM, EXd } },
2490     { "sqrtpd", { XM, EXx } },
2491     { "sqrtsd", { XM, EXq } },
2492   },
2493
2494   /* PREFIX_0F52 */
2495   {
2496     { "rsqrtps",{ XM, EXx } },
2497     { "rsqrtss",{ XM, EXd } },
2498     { "(bad)",  { XX } },
2499     { "(bad)",  { XX } },
2500   },
2501
2502   /* PREFIX_0F53 */
2503   {
2504     { "rcpps",  { XM, EXx } },
2505     { "rcpss",  { XM, EXd } },
2506     { "(bad)",  { XX } },
2507     { "(bad)",  { XX } },
2508   },
2509
2510   /* PREFIX_0F58 */
2511   {
2512     { "addps", { XM, EXx } },
2513     { "addss", { XM, EXd } },
2514     { "addpd", { XM, EXx } },
2515     { "addsd", { XM, EXq } },
2516   },
2517
2518   /* PREFIX_0F59 */
2519   {
2520     { "mulps",  { XM, EXx } },
2521     { "mulss",  { XM, EXd } },
2522     { "mulpd",  { XM, EXx } },
2523     { "mulsd",  { XM, EXq } },
2524   },
2525
2526   /* PREFIX_0F5A */
2527   {
2528     { "cvtps2pd", { XM, EXq } },
2529     { "cvtss2sd", { XM, EXd } },
2530     { "cvtpd2ps", { XM, EXx } },
2531     { "cvtsd2ss", { XM, EXq } },
2532   },
2533
2534   /* PREFIX_0F5B */
2535   {
2536     { "cvtdq2ps", { XM, EXx } },
2537     { "cvttps2dq", { XM, EXx } },
2538     { "cvtps2dq", { XM, EXx } },
2539     { "(bad)",  { XX } },
2540   },
2541
2542   /* PREFIX_0F5C */
2543   {
2544     { "subps",  { XM, EXx } },
2545     { "subss",  { XM, EXd } },
2546     { "subpd",  { XM, EXx } },
2547     { "subsd",  { XM, EXq } },
2548   },
2549
2550   /* PREFIX_0F5D */
2551   {
2552     { "minps",  { XM, EXx } },
2553     { "minss",  { XM, EXd } },
2554     { "minpd",  { XM, EXx } },
2555     { "minsd",  { XM, EXq } },
2556   },
2557
2558   /* PREFIX_0F5E */
2559   {
2560     { "divps",  { XM, EXx } },
2561     { "divss",  { XM, EXd } },
2562     { "divpd",  { XM, EXx } },
2563     { "divsd",  { XM, EXq } },
2564   },
2565
2566   /* PREFIX_0F5F */
2567   {
2568     { "maxps",  { XM, EXx } },
2569     { "maxss",  { XM, EXd } },
2570     { "maxpd",  { XM, EXx } },
2571     { "maxsd",  { XM, EXq } },
2572   },
2573
2574   /* PREFIX_0F60 */
2575   {
2576     { "punpcklbw",{ MX, EMd } },
2577     { "(bad)",  { XX } },
2578     { "punpcklbw",{ MX, EMx } },
2579     { "(bad)",  { XX } },
2580   },
2581
2582   /* PREFIX_0F61 */
2583   {
2584     { "punpcklwd",{ MX, EMd } },
2585     { "(bad)",  { XX } },
2586     { "punpcklwd",{ MX, EMx } },
2587     { "(bad)",  { XX } },
2588   },
2589
2590   /* PREFIX_0F62 */
2591   {
2592     { "punpckldq",{ MX, EMd } },
2593     { "(bad)",  { XX } },
2594     { "punpckldq",{ MX, EMx } },
2595     { "(bad)",  { XX } },
2596   },
2597
2598   /* PREFIX_0F6C */
2599   {
2600     { "(bad)",  { XX } },
2601     { "(bad)",  { XX } },
2602     { "punpcklqdq", { XM, EXx } },
2603     { "(bad)",  { XX } },
2604   },
2605
2606   /* PREFIX_0F6D */
2607   {
2608     { "(bad)",  { XX } },
2609     { "(bad)",  { XX } },
2610     { "punpckhqdq", { XM, EXx } },
2611     { "(bad)",  { XX } },
2612   },
2613
2614   /* PREFIX_0F6F */
2615   {
2616     { "movq",   { MX, EM } },
2617     { "movdqu", { XM, EXx } },
2618     { "movdqa", { XM, EXx } },
2619     { "(bad)",  { XX } },
2620   },
2621
2622   /* PREFIX_0F70 */
2623   {
2624     { "pshufw", { MX, EM, Ib } },
2625     { "pshufhw",{ XM, EXx, Ib } },
2626     { "pshufd", { XM, EXx, Ib } },
2627     { "pshuflw",{ XM, EXx, Ib } },
2628   },
2629
2630   /* PREFIX_0F73_REG_3 */
2631   {
2632     { "(bad)",  { XX } },
2633     { "(bad)",  { XX } },
2634     { "psrldq", { XS, Ib } },
2635     { "(bad)",  { XX } },
2636   },
2637
2638   /* PREFIX_0F73_REG_7 */
2639   {
2640     { "(bad)",  { XX } },
2641     { "(bad)",  { XX } },
2642     { "pslldq", { XS, Ib } },
2643     { "(bad)",  { XX } },
2644   },
2645
2646   /* PREFIX_0F78 */
2647   {
2648     {"vmread",  { Em, Gm } },
2649     {"(bad)",   { XX } },
2650     {"extrq",   { XS, Ib, Ib } },
2651     {"insertq", { XM, XS, Ib, Ib } },
2652   },
2653
2654   /* PREFIX_0F79 */
2655   {
2656     {"vmwrite", { Gm, Em } },
2657     {"(bad)",   { XX } },
2658     {"extrq",   { XM, XS } },
2659     {"insertq", { XM, XS } },
2660   },
2661
2662   /* PREFIX_0F7C */
2663   {
2664     { "(bad)",  { XX } },
2665     { "(bad)",  { XX } },
2666     { "haddpd", { XM, EXx } },
2667     { "haddps", { XM, EXx } },
2668   },
2669
2670   /* PREFIX_0F7D */
2671   {
2672     { "(bad)",  { XX } },
2673     { "(bad)",  { XX } },
2674     { "hsubpd", { XM, EXx } },
2675     { "hsubps", { XM, EXx } },
2676   },
2677
2678   /* PREFIX_0F7E */
2679   {
2680     { "movK",   { Edq, MX } },
2681     { "movq",   { XM, EXq } },
2682     { "movK",   { Edq, XM } },
2683     { "(bad)",  { XX } },
2684   },
2685
2686   /* PREFIX_0F7F */
2687   {
2688     { "movq",   { EM, MX } },
2689     { "movdqu", { EXx, XM } },
2690     { "movdqa", { EXx, XM } },
2691     { "(bad)",  { XX } },
2692   },
2693
2694   /* PREFIX_0FB8 */
2695   {
2696     { "(bad)", { XX } },
2697     { "popcntS", { Gv, Ev } },
2698     { "(bad)", { XX } },
2699     { "(bad)", { XX } },
2700   },
2701
2702   /* PREFIX_0FBD */
2703   {
2704     { "bsrS",   { Gv, Ev } },
2705     { "lzcntS", { Gv, Ev } },
2706     { "bsrS",   { Gv, Ev } },
2707     { "(bad)",  { XX } },
2708   },
2709
2710   /* PREFIX_0FC2 */
2711   {
2712     { "cmpps",  { XM, EXx, CMP } },
2713     { "cmpss",  { XM, EXd, CMP } },
2714     { "cmppd",  { XM, EXx, CMP } },
2715     { "cmpsd",  { XM, EXq, CMP } },
2716   },
2717
2718   /* PREFIX_0FC3 */
2719   {
2720     { "movntiS", { Ma, Gv } },
2721     { "(bad)",  { XX } },
2722     { "(bad)",  { XX } },
2723     { "(bad)",  { XX } },
2724   },
2725
2726   /* PREFIX_0FC7_REG_6 */
2727   {
2728     { "vmptrld",{ Mq } },
2729     { "vmxon",  { Mq } },
2730     { "vmclear",{ Mq } },
2731     { "(bad)",  { XX } },
2732   },
2733
2734   /* PREFIX_0FD0 */
2735   {
2736     { "(bad)",  { XX } },
2737     { "(bad)",  { XX } },
2738     { "addsubpd", { XM, EXx } },
2739     { "addsubps", { XM, EXx } },
2740   },
2741
2742   /* PREFIX_0FD6 */
2743   {
2744     { "(bad)",  { XX } },
2745     { "movq2dq",{ XM, MS } },
2746     { "movq",   { EXq, XM } },
2747     { "movdq2q",{ MX, XS } },
2748   },
2749
2750   /* PREFIX_0FE6 */
2751   {
2752     { "(bad)",  { XX } },
2753     { "cvtdq2pd", { XM, EXq } },
2754     { "cvttpd2dq", { XM, EXx } },
2755     { "cvtpd2dq", { XM, EXx } },
2756   },
2757
2758   /* PREFIX_0FE7 */
2759   {
2760     { "movntq", { Mq, MX } },
2761     { "(bad)",  { XX } },
2762     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2763     { "(bad)",  { XX } },
2764   },
2765
2766   /* PREFIX_0FF0 */
2767   {
2768     { "(bad)",  { XX } },
2769     { "(bad)",  { XX } },
2770     { "(bad)",  { XX } },
2771     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2772   },
2773
2774   /* PREFIX_0FF7 */
2775   {
2776     { "maskmovq", { MX, MS } },
2777     { "(bad)",  { XX } },
2778     { "maskmovdqu", { XM, XS } },
2779     { "(bad)",  { XX } },
2780   },
2781
2782   /* PREFIX_0F3810 */
2783   {
2784     { "(bad)",  { XX } },
2785     { "(bad)",  { XX } },
2786     { "pblendvb", { XM, EXx, XMM0 } },
2787     { "(bad)",  { XX } },
2788   },
2789
2790   /* PREFIX_0F3814 */
2791   {
2792     { "(bad)",  { XX } },
2793     { "(bad)",  { XX } },
2794     { "blendvps", { XM, EXx, XMM0 } },
2795     { "(bad)",  { XX } },
2796   },
2797
2798   /* PREFIX_0F3815 */
2799   {
2800     { "(bad)",  { XX } },
2801     { "(bad)",  { XX } },
2802     { "blendvpd", { XM, EXx, XMM0 } },
2803     { "(bad)",  { XX } },
2804   },
2805
2806   /* PREFIX_0F3817 */
2807   {
2808     { "(bad)",  { XX } },
2809     { "(bad)",  { XX } },
2810     { "ptest",  { XM, EXx } },
2811     { "(bad)",  { XX } },
2812   },
2813
2814   /* PREFIX_0F3820 */
2815   {
2816     { "(bad)",  { XX } },
2817     { "(bad)",  { XX } },
2818     { "pmovsxbw", { XM, EXq } },
2819     { "(bad)",  { XX } },
2820   },
2821
2822   /* PREFIX_0F3821 */
2823   {
2824     { "(bad)",  { XX } },
2825     { "(bad)",  { XX } },
2826     { "pmovsxbd", { XM, EXd } },
2827     { "(bad)",  { XX } },
2828   },
2829
2830   /* PREFIX_0F3822 */
2831   {
2832     { "(bad)",  { XX } },
2833     { "(bad)",  { XX } },
2834     { "pmovsxbq", { XM, EXw } },
2835     { "(bad)",  { XX } },
2836   },
2837
2838   /* PREFIX_0F3823 */
2839   {
2840     { "(bad)",  { XX } },
2841     { "(bad)",  { XX } },
2842     { "pmovsxwd", { XM, EXq } },
2843     { "(bad)",  { XX } },
2844   },
2845
2846   /* PREFIX_0F3824 */
2847   {
2848     { "(bad)",  { XX } },
2849     { "(bad)",  { XX } },
2850     { "pmovsxwq", { XM, EXd } },
2851     { "(bad)",  { XX } },
2852   },
2853
2854   /* PREFIX_0F3825 */
2855   {
2856     { "(bad)",  { XX } },
2857     { "(bad)",  { XX } },
2858     { "pmovsxdq", { XM, EXq } },
2859     { "(bad)",  { XX } },
2860   },
2861
2862   /* PREFIX_0F3828 */
2863   {
2864     { "(bad)",  { XX } },
2865     { "(bad)",  { XX } },
2866     { "pmuldq", { XM, EXx } },
2867     { "(bad)",  { XX } },
2868   },
2869
2870   /* PREFIX_0F3829 */
2871   {
2872     { "(bad)",  { XX } },
2873     { "(bad)",  { XX } },
2874     { "pcmpeqq", { XM, EXx } },
2875     { "(bad)",  { XX } },
2876   },
2877
2878   /* PREFIX_0F382A */
2879   {
2880     { "(bad)",  { XX } },
2881     { "(bad)",  { XX } },
2882     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2883     { "(bad)",  { XX } },
2884   },
2885
2886   /* PREFIX_0F382B */
2887   {
2888     { "(bad)",  { XX } },
2889     { "(bad)",  { XX } },
2890     { "packusdw", { XM, EXx } },
2891     { "(bad)",  { XX } },
2892   },
2893
2894   /* PREFIX_0F3830 */
2895   {
2896     { "(bad)",  { XX } },
2897     { "(bad)",  { XX } },
2898     { "pmovzxbw", { XM, EXq } },
2899     { "(bad)",  { XX } },
2900   },
2901
2902   /* PREFIX_0F3831 */
2903   {
2904     { "(bad)",  { XX } },
2905     { "(bad)",  { XX } },
2906     { "pmovzxbd", { XM, EXd } },
2907     { "(bad)",  { XX } },
2908   },
2909
2910   /* PREFIX_0F3832 */
2911   {
2912     { "(bad)",  { XX } },
2913     { "(bad)",  { XX } },
2914     { "pmovzxbq", { XM, EXw } },
2915     { "(bad)",  { XX } },
2916   },
2917
2918   /* PREFIX_0F3833 */
2919   {
2920     { "(bad)",  { XX } },
2921     { "(bad)",  { XX } },
2922     { "pmovzxwd", { XM, EXq } },
2923     { "(bad)",  { XX } },
2924   },
2925
2926   /* PREFIX_0F3834 */
2927   {
2928     { "(bad)",  { XX } },
2929     { "(bad)",  { XX } },
2930     { "pmovzxwq", { XM, EXd } },
2931     { "(bad)",  { XX } },
2932   },
2933
2934   /* PREFIX_0F3835 */
2935   {
2936     { "(bad)",  { XX } },
2937     { "(bad)",  { XX } },
2938     { "pmovzxdq", { XM, EXq } },
2939     { "(bad)",  { XX } },
2940   },
2941
2942   /* PREFIX_0F3837 */
2943   {
2944     { "(bad)",  { XX } },
2945     { "(bad)",  { XX } },
2946     { "pcmpgtq", { XM, EXx } },
2947     { "(bad)",  { XX } },
2948   },
2949
2950   /* PREFIX_0F3838 */
2951   {
2952     { "(bad)",  { XX } },
2953     { "(bad)",  { XX } },
2954     { "pminsb", { XM, EXx } },
2955     { "(bad)",  { XX } },
2956   },
2957
2958   /* PREFIX_0F3839 */
2959   {
2960     { "(bad)",  { XX } },
2961     { "(bad)",  { XX } },
2962     { "pminsd", { XM, EXx } },
2963     { "(bad)",  { XX } },
2964   },
2965
2966   /* PREFIX_0F383A */
2967   {
2968     { "(bad)",  { XX } },
2969     { "(bad)",  { XX } },
2970     { "pminuw", { XM, EXx } },
2971     { "(bad)",  { XX } },
2972   },
2973
2974   /* PREFIX_0F383B */
2975   {
2976     { "(bad)",  { XX } },
2977     { "(bad)",  { XX } },
2978     { "pminud", { XM, EXx } },
2979     { "(bad)",  { XX } },
2980   },
2981
2982   /* PREFIX_0F383C */
2983   {
2984     { "(bad)",  { XX } },
2985     { "(bad)",  { XX } },
2986     { "pmaxsb", { XM, EXx } },
2987     { "(bad)",  { XX } },
2988   },
2989
2990   /* PREFIX_0F383D */
2991   {
2992     { "(bad)",  { XX } },
2993     { "(bad)",  { XX } },
2994     { "pmaxsd", { XM, EXx } },
2995     { "(bad)",  { XX } },
2996   },
2997
2998   /* PREFIX_0F383E */
2999   {
3000     { "(bad)",  { XX } },
3001     { "(bad)",  { XX } },
3002     { "pmaxuw", { XM, EXx } },
3003     { "(bad)",  { XX } },
3004   },
3005
3006   /* PREFIX_0F383F */
3007   {
3008     { "(bad)",  { XX } },
3009     { "(bad)",  { XX } },
3010     { "pmaxud", { XM, EXx } },
3011     { "(bad)",  { XX } },
3012   },
3013
3014   /* PREFIX_0F3840 */
3015   {
3016     { "(bad)",  { XX } },
3017     { "(bad)",  { XX } },
3018     { "pmulld", { XM, EXx } },
3019     { "(bad)",  { XX } },
3020   },
3021
3022   /* PREFIX_0F3841 */
3023   {
3024     { "(bad)",  { XX } },
3025     { "(bad)",  { XX } },
3026     { "phminposuw", { XM, EXx } },
3027     { "(bad)",  { XX } },
3028   },
3029
3030   /* PREFIX_0F3880 */
3031   {
3032     { "(bad)",  { XX } },
3033     { "(bad)",  { XX } },
3034     { "invept", { Gm, Mo } },
3035     { "(bad)",  { XX } },
3036   },
3037
3038   /* PREFIX_0F3881 */
3039   {
3040     { "(bad)",  { XX } },
3041     { "(bad)",  { XX } },
3042     { "invvpid", { Gm, Mo } },
3043     { "(bad)",  { XX } },
3044   },
3045
3046   /* PREFIX_0F38DB */
3047   {
3048     { "(bad)",  { XX } },
3049     { "(bad)",  { XX } },
3050     { "aesimc", { XM, EXx } },
3051     { "(bad)",  { XX } },
3052   },
3053
3054   /* PREFIX_0F38DC */
3055   {
3056     { "(bad)",  { XX } },
3057     { "(bad)",  { XX } },
3058     { "aesenc", { XM, EXx } },
3059     { "(bad)",  { XX } },
3060   },
3061
3062   /* PREFIX_0F38DD */
3063   {
3064     { "(bad)",  { XX } },
3065     { "(bad)",  { XX } },
3066     { "aesenclast", { XM, EXx } },
3067     { "(bad)",  { XX } },
3068   },
3069
3070   /* PREFIX_0F38DE */
3071   {
3072     { "(bad)",  { XX } },
3073     { "(bad)",  { XX } },
3074     { "aesdec", { XM, EXx } },
3075     { "(bad)",  { XX } },
3076   },
3077
3078   /* PREFIX_0F38DF */
3079   {
3080     { "(bad)",  { XX } },
3081     { "(bad)",  { XX } },
3082     { "aesdeclast", { XM, EXx } },
3083     { "(bad)",  { XX } },
3084   },
3085
3086   /* PREFIX_0F38F0 */
3087   {
3088     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3089     { "(bad)",  { XX } },
3090     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3091     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3092   },
3093
3094   /* PREFIX_0F38F1 */
3095   {
3096     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3097     { "(bad)",  { XX } },
3098     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3099     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3100   },
3101
3102   /* PREFIX_0F3A08 */
3103   {
3104     { "(bad)",  { XX } },
3105     { "(bad)",  { XX } },
3106     { "roundps", { XM, EXx, Ib } },
3107     { "(bad)",  { XX } },
3108   },
3109
3110   /* PREFIX_0F3A09 */
3111   {
3112     { "(bad)",  { XX } },
3113     { "(bad)",  { XX } },
3114     { "roundpd", { XM, EXx, Ib } },
3115     { "(bad)",  { XX } },
3116   },
3117
3118   /* PREFIX_0F3A0A */
3119   {
3120     { "(bad)",  { XX } },
3121     { "(bad)",  { XX } },
3122     { "roundss", { XM, EXd, Ib } },
3123     { "(bad)",  { XX } },
3124   },
3125
3126   /* PREFIX_0F3A0B */
3127   {
3128     { "(bad)",  { XX } },
3129     { "(bad)",  { XX } },
3130     { "roundsd", { XM, EXq, Ib } },
3131     { "(bad)",  { XX } },
3132   },
3133
3134   /* PREFIX_0F3A0C */
3135   {
3136     { "(bad)",  { XX } },
3137     { "(bad)",  { XX } },
3138     { "blendps", { XM, EXx, Ib } },
3139     { "(bad)",  { XX } },
3140   },
3141
3142   /* PREFIX_0F3A0D */
3143   {
3144     { "(bad)",  { XX } },
3145     { "(bad)",  { XX } },
3146     { "blendpd", { XM, EXx, Ib } },
3147     { "(bad)",  { XX } },
3148   },
3149
3150   /* PREFIX_0F3A0E */
3151   {
3152     { "(bad)",  { XX } },
3153     { "(bad)",  { XX } },
3154     { "pblendw", { XM, EXx, Ib } },
3155     { "(bad)",  { XX } },
3156   },
3157
3158   /* PREFIX_0F3A14 */
3159   {
3160     { "(bad)",  { XX } },
3161     { "(bad)",  { XX } },
3162     { "pextrb", { Edqb, XM, Ib } },
3163     { "(bad)",  { XX } },
3164   },
3165
3166   /* PREFIX_0F3A15 */
3167   {
3168     { "(bad)",  { XX } },
3169     { "(bad)",  { XX } },
3170     { "pextrw", { Edqw, XM, Ib } },
3171     { "(bad)",  { XX } },
3172   },
3173
3174   /* PREFIX_0F3A16 */
3175   {
3176     { "(bad)",  { XX } },
3177     { "(bad)",  { XX } },
3178     { "pextrK", { Edq, XM, Ib } },
3179     { "(bad)",  { XX } },
3180   },
3181
3182   /* PREFIX_0F3A17 */
3183   {
3184     { "(bad)",  { XX } },
3185     { "(bad)",  { XX } },
3186     { "extractps", { Edqd, XM, Ib } },
3187     { "(bad)",  { XX } },
3188   },
3189
3190   /* PREFIX_0F3A20 */
3191   {
3192     { "(bad)",  { XX } },
3193     { "(bad)",  { XX } },
3194     { "pinsrb", { XM, Edqb, Ib } },
3195     { "(bad)",  { XX } },
3196   },
3197
3198   /* PREFIX_0F3A21 */
3199   {
3200     { "(bad)",  { XX } },
3201     { "(bad)",  { XX } },
3202     { "insertps", { XM, EXd, Ib } },
3203     { "(bad)",  { XX } },
3204   },
3205
3206   /* PREFIX_0F3A22 */
3207   {
3208     { "(bad)",  { XX } },
3209     { "(bad)",  { XX } },
3210     { "pinsrK", { XM, Edq, Ib } },
3211     { "(bad)",  { XX } },
3212   },
3213
3214   /* PREFIX_0F3A40 */
3215   {
3216     { "(bad)",  { XX } },
3217     { "(bad)",  { XX } },
3218     { "dpps",   { XM, EXx, Ib } },
3219     { "(bad)",  { XX } },
3220   },
3221
3222   /* PREFIX_0F3A41 */
3223   {
3224     { "(bad)",  { XX } },
3225     { "(bad)",  { XX } },
3226     { "dppd",   { XM, EXx, Ib } },
3227     { "(bad)",  { XX } },
3228   },
3229
3230   /* PREFIX_0F3A42 */
3231   {
3232     { "(bad)",  { XX } },
3233     { "(bad)",  { XX } },
3234     { "mpsadbw", { XM, EXx, Ib } },
3235     { "(bad)",  { XX } },
3236   },
3237
3238   /* PREFIX_0F3A44 */
3239   {
3240     { "(bad)",  { XX } },
3241     { "(bad)",  { XX } },
3242     { "pclmulqdq", { XM, EXx, PCLMUL } },
3243     { "(bad)",  { XX } },
3244   },
3245
3246   /* PREFIX_0F3A60 */
3247   {
3248     { "(bad)",  { XX } },
3249     { "(bad)",  { XX } },
3250     { "pcmpestrm", { XM, EXx, Ib } },
3251     { "(bad)",  { XX } },
3252   },
3253
3254   /* PREFIX_0F3A61 */
3255   {
3256     { "(bad)",  { XX } },
3257     { "(bad)",  { XX } },
3258     { "pcmpestri", { XM, EXx, Ib } },
3259     { "(bad)",  { XX } },
3260   },
3261
3262   /* PREFIX_0F3A62 */
3263   {
3264     { "(bad)",  { XX } },
3265     { "(bad)",  { XX } },
3266     { "pcmpistrm", { XM, EXx, Ib } },
3267     { "(bad)",  { XX } },
3268   },
3269
3270   /* PREFIX_0F3A63 */
3271   {
3272     { "(bad)",  { XX } },
3273     { "(bad)",  { XX } },
3274     { "pcmpistri", { XM, EXx, Ib } },
3275     { "(bad)",  { XX } },
3276   },
3277
3278   /* PREFIX_0F3ADF */
3279   {
3280     { "(bad)",  { XX } },
3281     { "(bad)",  { XX } },
3282     { "aeskeygenassist", { XM, EXx, Ib } },
3283     { "(bad)",  { XX } },
3284   },
3285
3286   /* PREFIX_VEX_10 */
3287   {
3288     { "vmovups", { XM, EXx } },
3289     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3290     { "vmovupd", { XM, EXx } },
3291     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3292   },
3293
3294   /* PREFIX_VEX_11 */
3295   {
3296     { "vmovups", { EXx, XM } },
3297     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3298     { "vmovupd", { EXx, XM } },
3299     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3300   },
3301
3302   /* PREFIX_VEX_12 */
3303   {
3304     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3305     { "vmovsldup", { XM, EXx } },
3306     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3307     { "vmovddup", { XM, EXymmq } },
3308   },
3309
3310   /* PREFIX_VEX_16 */
3311   {
3312     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3313     { "vmovshdup", { XM, EXx } },
3314     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3315     { "(bad)",  { XX } },
3316   },
3317
3318   /* PREFIX_VEX_2A */
3319   {
3320     { "(bad)",  { XX } },
3321     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3322     { "(bad)",  { XX } },
3323     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3324   },
3325
3326   /* PREFIX_VEX_2C */
3327   {
3328     { "(bad)",  { XX } },
3329     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3330     { "(bad)",  { XX } },
3331     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3332   },
3333
3334   /* PREFIX_VEX_2D */
3335   {
3336     { "(bad)",  { XX } },
3337     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3338     { "(bad)",  { XX } },
3339     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3340   },
3341
3342   /* PREFIX_VEX_2E */
3343   {
3344     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3345     { "(bad)",  { XX } },
3346     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3347     { "(bad)",  { XX } },
3348   },
3349
3350   /* PREFIX_VEX_2F */
3351   {
3352     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3353     { "(bad)",  { XX } },
3354     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3355     { "(bad)",  { XX } },
3356   },
3357
3358   /* PREFIX_VEX_51 */
3359   {
3360     { "vsqrtps", { XM, EXx } },
3361     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3362     { "vsqrtpd", { XM, EXx } },
3363     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3364   },
3365
3366   /* PREFIX_VEX_52 */
3367   {
3368     { "vrsqrtps", { XM, EXx } },
3369     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3370     { "(bad)",  { XX } },
3371     { "(bad)",  { XX } },
3372   },
3373
3374   /* PREFIX_VEX_53 */
3375   {
3376     { "vrcpps", { XM, EXx } },
3377     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3378     { "(bad)",  { XX } },
3379     { "(bad)",  { XX } },
3380   },
3381
3382   /* PREFIX_VEX_58 */
3383   {
3384     { "vaddps", { XM, Vex, EXx } },
3385     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3386     { "vaddpd", { XM, Vex, EXx } },
3387     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3388   },
3389
3390   /* PREFIX_VEX_59 */
3391   {
3392     { "vmulps", { XM, Vex, EXx } },
3393     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3394     { "vmulpd", { XM, Vex, EXx } },
3395     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3396   },
3397
3398   /* PREFIX_VEX_5A */
3399   {
3400     { "vcvtps2pd", { XM, EXxmmq } },
3401     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3402     { "vcvtpd2ps%XY", { XMM, EXx } },
3403     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3404   },
3405
3406   /* PREFIX_VEX_5B */
3407   {
3408     { "vcvtdq2ps", { XM, EXx } },
3409     { "vcvttps2dq", { XM, EXx } },
3410     { "vcvtps2dq", { XM, EXx } },
3411     { "(bad)",  { XX } },
3412   },
3413
3414   /* PREFIX_VEX_5C */
3415   {
3416     { "vsubps", { XM, Vex, EXx } },
3417     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3418     { "vsubpd", { XM, Vex, EXx } },
3419     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3420   },
3421
3422   /* PREFIX_VEX_5D */
3423   {
3424     { "vminps", { XM, Vex, EXx } },
3425     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3426     { "vminpd", { XM, Vex, EXx } },
3427     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3428   },
3429
3430   /* PREFIX_VEX_5E */
3431   {
3432     { "vdivps", { XM, Vex, EXx } },
3433     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3434     { "vdivpd", { XM, Vex, EXx } },
3435     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3436   },
3437
3438   /* PREFIX_VEX_5F */
3439   {
3440     { "vmaxps", { XM, Vex, EXx } },
3441     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3442     { "vmaxpd", { XM, Vex, EXx } },
3443     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3444   },
3445
3446   /* PREFIX_VEX_60 */
3447   {
3448     { "(bad)",  { XX } },
3449     { "(bad)",  { XX } },
3450     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3451     { "(bad)",  { XX } },
3452   },
3453
3454   /* PREFIX_VEX_61 */
3455   {
3456     { "(bad)",  { XX } },
3457     { "(bad)",  { XX } },
3458     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3459     { "(bad)",  { XX } },
3460   },
3461
3462   /* PREFIX_VEX_62 */
3463   {
3464     { "(bad)",  { XX } },
3465     { "(bad)",  { XX } },
3466     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3467     { "(bad)",  { XX } },
3468   },
3469
3470   /* PREFIX_VEX_63 */
3471   {
3472     { "(bad)",  { XX } },
3473     { "(bad)",  { XX } },
3474     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3475     { "(bad)",  { XX } },
3476   },
3477
3478   /* PREFIX_VEX_64 */
3479   {
3480     { "(bad)",  { XX } },
3481     { "(bad)",  { XX } },
3482     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3483     { "(bad)",  { XX } },
3484   },
3485
3486   /* PREFIX_VEX_65 */
3487   {
3488     { "(bad)",  { XX } },
3489     { "(bad)",  { XX } },
3490     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3491     { "(bad)",  { XX } },
3492   },
3493
3494   /* PREFIX_VEX_66 */
3495   {
3496     { "(bad)",  { XX } },
3497     { "(bad)",  { XX } },
3498     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3499     { "(bad)",  { XX } },
3500   },
3501
3502   /* PREFIX_VEX_67 */
3503   {
3504     { "(bad)",  { XX } },
3505     { "(bad)",  { XX } },
3506     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3507     { "(bad)",  { XX } },
3508   },
3509
3510   /* PREFIX_VEX_68 */
3511   {
3512     { "(bad)",  { XX } },
3513     { "(bad)",  { XX } },
3514     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3515     { "(bad)",  { XX } },
3516   },
3517
3518   /* PREFIX_VEX_69 */
3519   {
3520     { "(bad)",  { XX } },
3521     { "(bad)",  { XX } },
3522     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3523     { "(bad)",  { XX } },
3524   },
3525
3526   /* PREFIX_VEX_6A */
3527   {
3528     { "(bad)",  { XX } },
3529     { "(bad)",  { XX } },
3530     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3531     { "(bad)",  { XX } },
3532   },
3533
3534   /* PREFIX_VEX_6B */
3535   {
3536     { "(bad)",  { XX } },
3537     { "(bad)",  { XX } },
3538     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3539     { "(bad)",  { XX } },
3540   },
3541
3542   /* PREFIX_VEX_6C */
3543   {
3544     { "(bad)",  { XX } },
3545     { "(bad)",  { XX } },
3546     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3547     { "(bad)",  { XX } },
3548   },
3549
3550   /* PREFIX_VEX_6D */
3551   {
3552     { "(bad)",  { XX } },
3553     { "(bad)",  { XX } },
3554     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3555     { "(bad)",  { XX } },
3556   },
3557
3558   /* PREFIX_VEX_6E */
3559   {
3560     { "(bad)",  { XX } },
3561     { "(bad)",  { XX } },
3562     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3563     { "(bad)",  { XX } },
3564   },
3565
3566   /* PREFIX_VEX_6F */
3567   {
3568     { "(bad)",  { XX } },
3569     { "vmovdqu", { XM, EXx } },
3570     { "vmovdqa", { XM, EXx } },
3571     { "(bad)",  { XX } },
3572   },
3573
3574   /* PREFIX_VEX_70 */
3575   {
3576     { "(bad)",  { XX } },
3577     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3578     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3579     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3580   },
3581
3582   /* PREFIX_VEX_71_REG_2 */
3583   {
3584     { "(bad)",  { XX } },
3585     { "(bad)",  { XX } },
3586     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3587     { "(bad)",  { XX } },
3588   },
3589
3590   /* PREFIX_VEX_71_REG_4 */
3591   {
3592     { "(bad)",  { XX } },
3593     { "(bad)",  { XX } },
3594     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3595     { "(bad)",  { XX } },
3596   },
3597
3598   /* PREFIX_VEX_71_REG_6 */
3599   {
3600     { "(bad)",  { XX } },
3601     { "(bad)",  { XX } },
3602     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3603     { "(bad)",  { XX } },
3604   },
3605
3606   /* PREFIX_VEX_72_REG_2 */
3607   {
3608     { "(bad)",  { XX } },
3609     { "(bad)",  { XX } },
3610     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3611     { "(bad)",  { XX } },
3612   },
3613
3614   /* PREFIX_VEX_72_REG_4 */
3615   {
3616     { "(bad)",  { XX } },
3617     { "(bad)",  { XX } },
3618     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3619     { "(bad)",  { XX } },
3620   },
3621
3622   /* PREFIX_VEX_72_REG_6 */
3623   {
3624     { "(bad)",  { XX } },
3625     { "(bad)",  { XX } },
3626     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3627     { "(bad)",  { XX } },
3628   },
3629
3630   /* PREFIX_VEX_73_REG_2 */
3631   {
3632     { "(bad)",  { XX } },
3633     { "(bad)",  { XX } },
3634     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3635     { "(bad)",  { XX } },
3636   },
3637
3638   /* PREFIX_VEX_73_REG_3 */
3639   {
3640     { "(bad)",  { XX } },
3641     { "(bad)",  { XX } },
3642     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3643     { "(bad)",  { XX } },
3644   },
3645
3646   /* PREFIX_VEX_73_REG_6 */
3647   {
3648     { "(bad)",  { XX } },
3649     { "(bad)",  { XX } },
3650     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3651     { "(bad)",  { XX } },
3652   },
3653
3654   /* PREFIX_VEX_73_REG_7 */
3655   {
3656     { "(bad)",  { XX } },
3657     { "(bad)",  { XX } },
3658     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3659     { "(bad)",  { XX } },
3660   },
3661
3662   /* PREFIX_VEX_74 */
3663   {
3664     { "(bad)",  { XX } },
3665     { "(bad)",  { XX } },
3666     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3667     { "(bad)",  { XX } },
3668   },
3669
3670   /* PREFIX_VEX_75 */
3671   {
3672     { "(bad)",  { XX } },
3673     { "(bad)",  { XX } },
3674     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3675     { "(bad)",  { XX } },
3676   },
3677
3678   /* PREFIX_VEX_76 */
3679   {
3680     { "(bad)",  { XX } },
3681     { "(bad)",  { XX } },
3682     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3683     { "(bad)",  { XX } },
3684   },
3685
3686   /* PREFIX_VEX_77 */
3687   {
3688     { "",       { VZERO } },
3689     { "(bad)",  { XX } },
3690     { "(bad)",  { XX } },
3691     { "(bad)",  { XX } },
3692   },
3693
3694   /* PREFIX_VEX_7C */
3695   {
3696     { "(bad)",  { XX } },
3697     { "(bad)",  { XX } },
3698     { "vhaddpd", { XM, Vex, EXx } },
3699     { "vhaddps", { XM, Vex, EXx } },
3700   },
3701
3702   /* PREFIX_VEX_7D */
3703   {
3704     { "(bad)",  { XX } },
3705     { "(bad)",  { XX } },
3706     { "vhsubpd", { XM, Vex, EXx } },
3707     { "vhsubps", { XM, Vex, EXx } },
3708   },
3709
3710   /* PREFIX_VEX_7E */
3711   {
3712     { "(bad)",  { XX } },
3713     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3714     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3715     { "(bad)",  { XX } },
3716   },
3717
3718   /* PREFIX_VEX_7F */
3719   {
3720     { "(bad)",  { XX } },
3721     { "vmovdqu", { EXx, XM } },
3722     { "vmovdqa", { EXx, XM } },
3723     { "(bad)",  { XX } },
3724   },
3725
3726   /* PREFIX_VEX_C2 */
3727   {
3728     { "vcmpps", { XM, Vex, EXx, VCMP } },
3729     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3730     { "vcmppd", { XM, Vex, EXx, VCMP } },
3731     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3732   },
3733
3734   /* PREFIX_VEX_C4 */
3735   {
3736     { "(bad)",  { XX } },
3737     { "(bad)",  { XX } },
3738     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3739     { "(bad)",  { XX } },
3740   },
3741
3742   /* PREFIX_VEX_C5 */
3743   {
3744     { "(bad)",  { XX } },
3745     { "(bad)",  { XX } },
3746     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3747     { "(bad)",  { XX } },
3748   },
3749
3750   /* PREFIX_VEX_D0 */
3751   {
3752     { "(bad)",  { XX } },
3753     { "(bad)",  { XX } },
3754     { "vaddsubpd", { XM, Vex, EXx } },
3755     { "vaddsubps", { XM, Vex, EXx } },
3756   },
3757
3758   /* PREFIX_VEX_D1 */
3759   {
3760     { "(bad)",  { XX } },
3761     { "(bad)",  { XX } },
3762     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3763     { "(bad)",  { XX } },
3764   },
3765
3766   /* PREFIX_VEX_D2 */
3767   {
3768     { "(bad)",  { XX } },
3769     { "(bad)",  { XX } },
3770     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3771     { "(bad)",  { XX } },
3772   },
3773
3774   /* PREFIX_VEX_D3 */
3775   {
3776     { "(bad)",  { XX } },
3777     { "(bad)",  { XX } },
3778     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3779     { "(bad)",  { XX } },
3780   },
3781
3782   /* PREFIX_VEX_D4 */
3783   {
3784     { "(bad)",  { XX } },
3785     { "(bad)",  { XX } },
3786     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3787     { "(bad)",  { XX } },
3788   },
3789
3790   /* PREFIX_VEX_D5 */
3791   {
3792     { "(bad)",  { XX } },
3793     { "(bad)",  { XX } },
3794     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3795     { "(bad)",  { XX } },
3796   },
3797
3798   /* PREFIX_VEX_D6 */
3799   {
3800     { "(bad)",  { XX } },
3801     { "(bad)",  { XX } },
3802     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3803     { "(bad)",  { XX } },
3804   },
3805
3806   /* PREFIX_VEX_D7 */
3807   {
3808     { "(bad)",  { XX } },
3809     { "(bad)",  { XX } },
3810     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3811     { "(bad)",  { XX } },
3812   },
3813
3814   /* PREFIX_VEX_D8 */
3815   {
3816     { "(bad)",  { XX } },
3817     { "(bad)",  { XX } },
3818     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3819     { "(bad)",  { XX } },
3820   },
3821
3822   /* PREFIX_VEX_D9 */
3823   {
3824     { "(bad)",  { XX } },
3825     { "(bad)",  { XX } },
3826     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3827     { "(bad)",  { XX } },
3828   },
3829
3830   /* PREFIX_VEX_DA */
3831   {
3832     { "(bad)",  { XX } },
3833     { "(bad)",  { XX } },
3834     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3835     { "(bad)",  { XX } },
3836   },
3837
3838   /* PREFIX_VEX_DB */
3839   {
3840     { "(bad)",  { XX } },
3841     { "(bad)",  { XX } },
3842     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3843     { "(bad)",  { XX } },
3844   },
3845
3846   /* PREFIX_VEX_DC */
3847   {
3848     { "(bad)",  { XX } },
3849     { "(bad)",  { XX } },
3850     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3851     { "(bad)",  { XX } },
3852   },
3853
3854   /* PREFIX_VEX_DD */
3855   {
3856     { "(bad)",  { XX } },
3857     { "(bad)",  { XX } },
3858     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3859     { "(bad)",  { XX } },
3860   },
3861
3862   /* PREFIX_VEX_DE */
3863   {
3864     { "(bad)",  { XX } },
3865     { "(bad)",  { XX } },
3866     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3867     { "(bad)",  { XX } },
3868   },
3869
3870   /* PREFIX_VEX_DF */
3871   {
3872     { "(bad)",  { XX } },
3873     { "(bad)",  { XX } },
3874     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3875     { "(bad)",  { XX } },
3876   },
3877
3878   /* PREFIX_VEX_E0 */
3879   {
3880     { "(bad)",  { XX } },
3881     { "(bad)",  { XX } },
3882     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3883     { "(bad)",  { XX } },
3884   },
3885
3886   /* PREFIX_VEX_E1 */
3887   {
3888     { "(bad)",  { XX } },
3889     { "(bad)",  { XX } },
3890     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3891     { "(bad)",  { XX } },
3892   },
3893
3894   /* PREFIX_VEX_E2 */
3895   {
3896     { "(bad)",  { XX } },
3897     { "(bad)",  { XX } },
3898     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3899     { "(bad)",  { XX } },
3900   },
3901
3902   /* PREFIX_VEX_E3 */
3903   {
3904     { "(bad)",  { XX } },
3905     { "(bad)",  { XX } },
3906     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3907     { "(bad)",  { XX } },
3908   },
3909
3910   /* PREFIX_VEX_E4 */
3911   {
3912     { "(bad)",  { XX } },
3913     { "(bad)",  { XX } },
3914     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3915     { "(bad)",  { XX } },
3916   },
3917
3918   /* PREFIX_VEX_E5 */
3919   {
3920     { "(bad)",  { XX } },
3921     { "(bad)",  { XX } },
3922     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3923     { "(bad)",  { XX } },
3924   },
3925
3926   /* PREFIX_VEX_E6 */
3927   {
3928     { "(bad)",  { XX } },
3929     { "vcvtdq2pd", { XM, EXxmmq } },
3930     { "vcvttpd2dq%XY", { XMM, EXx } },
3931     { "vcvtpd2dq%XY", { XMM, EXx } },
3932   },
3933
3934   /* PREFIX_VEX_E7 */
3935   {
3936     { "(bad)",  { XX } },
3937     { "(bad)",  { XX } },
3938     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3939     { "(bad)",  { XX } },
3940   },
3941
3942   /* PREFIX_VEX_E8 */
3943   {
3944     { "(bad)",  { XX } },
3945     { "(bad)",  { XX } },
3946     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3947     { "(bad)",  { XX } },
3948   },
3949
3950   /* PREFIX_VEX_E9 */
3951   {
3952     { "(bad)",  { XX } },
3953     { "(bad)",  { XX } },
3954     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3955     { "(bad)",  { XX } },
3956   },
3957
3958   /* PREFIX_VEX_EA */
3959   {
3960     { "(bad)",  { XX } },
3961     { "(bad)",  { XX } },
3962     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
3963     { "(bad)",  { XX } },
3964   },
3965
3966   /* PREFIX_VEX_EB */
3967   {
3968     { "(bad)",  { XX } },
3969     { "(bad)",  { XX } },
3970     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
3971     { "(bad)",  { XX } },
3972   },
3973
3974   /* PREFIX_VEX_EC */
3975   {
3976     { "(bad)",  { XX } },
3977     { "(bad)",  { XX } },
3978     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
3979     { "(bad)",  { XX } },
3980   },
3981
3982   /* PREFIX_VEX_ED */
3983   {
3984     { "(bad)",  { XX } },
3985     { "(bad)",  { XX } },
3986     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
3987     { "(bad)",  { XX } },
3988   },
3989
3990   /* PREFIX_VEX_EE */
3991   {
3992     { "(bad)",  { XX } },
3993     { "(bad)",  { XX } },
3994     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
3995     { "(bad)",  { XX } },
3996   },
3997
3998   /* PREFIX_VEX_EF */
3999   {
4000     { "(bad)",  { XX } },
4001     { "(bad)",  { XX } },
4002     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4003     { "(bad)",  { XX } },
4004   },
4005
4006   /* PREFIX_VEX_F0 */
4007   {
4008     { "(bad)",  { XX } },
4009     { "(bad)",  { XX } },
4010     { "(bad)",  { XX } },
4011     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4012   },
4013
4014   /* PREFIX_VEX_F1 */
4015   {
4016     { "(bad)",  { XX } },
4017     { "(bad)",  { XX } },
4018     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4019     { "(bad)",  { XX } },
4020   },
4021
4022   /* PREFIX_VEX_F2 */
4023   {
4024     { "(bad)",  { XX } },
4025     { "(bad)",  { XX } },
4026     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4027     { "(bad)",  { XX } },
4028   },
4029
4030   /* PREFIX_VEX_F3 */
4031   {
4032     { "(bad)",  { XX } },
4033     { "(bad)",  { XX } },
4034     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4035     { "(bad)",  { XX } },
4036   },
4037
4038   /* PREFIX_VEX_F4 */
4039   {
4040     { "(bad)",  { XX } },
4041     { "(bad)",  { XX } },
4042     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4043     { "(bad)",  { XX } },
4044   },
4045
4046   /* PREFIX_VEX_F5 */
4047   {
4048     { "(bad)",  { XX } },
4049     { "(bad)",  { XX } },
4050     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4051     { "(bad)",  { XX } },
4052   },
4053
4054   /* PREFIX_VEX_F6 */
4055   {
4056     { "(bad)",  { XX } },
4057     { "(bad)",  { XX } },
4058     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4059     { "(bad)",  { XX } },
4060   },
4061
4062   /* PREFIX_VEX_F7 */
4063   {
4064     { "(bad)",  { XX } },
4065     { "(bad)",  { XX } },
4066     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4067     { "(bad)",  { XX } },
4068   },
4069
4070   /* PREFIX_VEX_F8 */
4071   {
4072     { "(bad)",  { XX } },
4073     { "(bad)",  { XX } },
4074     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4075     { "(bad)",  { XX } },
4076   },
4077
4078   /* PREFIX_VEX_F9 */
4079   {
4080     { "(bad)",  { XX } },
4081     { "(bad)",  { XX } },
4082     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4083     { "(bad)",  { XX } },
4084   },
4085
4086   /* PREFIX_VEX_FA */
4087   {
4088     { "(bad)",  { XX } },
4089     { "(bad)",  { XX } },
4090     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4091     { "(bad)",  { XX } },
4092   },
4093
4094   /* PREFIX_VEX_FB */
4095   {
4096     { "(bad)",  { XX } },
4097     { "(bad)",  { XX } },
4098     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4099     { "(bad)",  { XX } },
4100   },
4101
4102   /* PREFIX_VEX_FC */
4103   {
4104     { "(bad)",  { XX } },
4105     { "(bad)",  { XX } },
4106     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4107     { "(bad)",  { XX } },
4108   },
4109
4110   /* PREFIX_VEX_FD */
4111   {
4112     { "(bad)",  { XX } },
4113     { "(bad)",  { XX } },
4114     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4115     { "(bad)",  { XX } },
4116   },
4117
4118   /* PREFIX_VEX_FE */
4119   {
4120     { "(bad)",  { XX } },
4121     { "(bad)",  { XX } },
4122     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4123     { "(bad)",  { XX } },
4124   },
4125
4126   /* PREFIX_VEX_3800 */
4127   {
4128     { "(bad)",  { XX } },
4129     { "(bad)",  { XX } },
4130     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4131     { "(bad)",  { XX } },
4132   },
4133
4134   /* PREFIX_VEX_3801 */
4135   {
4136     { "(bad)",  { XX } },
4137     { "(bad)",  { XX } },
4138     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4139     { "(bad)",  { XX } },
4140   },
4141
4142   /* PREFIX_VEX_3802 */
4143   {
4144     { "(bad)",  { XX } },
4145     { "(bad)",  { XX } },
4146     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4147     { "(bad)",  { XX } },
4148   },
4149
4150   /* PREFIX_VEX_3803 */
4151   {
4152     { "(bad)",  { XX } },
4153     { "(bad)",  { XX } },
4154     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4155     { "(bad)",  { XX } },
4156   },
4157
4158   /* PREFIX_VEX_3804 */
4159   {
4160     { "(bad)",  { XX } },
4161     { "(bad)",  { XX } },
4162     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4163     { "(bad)",  { XX } },
4164   },
4165
4166   /* PREFIX_VEX_3805 */
4167   {
4168     { "(bad)",  { XX } },
4169     { "(bad)",  { XX } },
4170     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4171     { "(bad)",  { XX } },
4172   },
4173
4174   /* PREFIX_VEX_3806 */
4175   {
4176     { "(bad)",  { XX } },
4177     { "(bad)",  { XX } },
4178     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4179     { "(bad)",  { XX } },
4180   },
4181
4182   /* PREFIX_VEX_3807 */
4183   {
4184     { "(bad)",  { XX } },
4185     { "(bad)",  { XX } },
4186     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4187     { "(bad)",  { XX } },
4188   },
4189
4190   /* PREFIX_VEX_3808 */
4191   {
4192     { "(bad)",  { XX } },
4193     { "(bad)",  { XX } },
4194     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4195     { "(bad)",  { XX } },
4196   },
4197
4198   /* PREFIX_VEX_3809 */
4199   {
4200     { "(bad)",  { XX } },
4201     { "(bad)",  { XX } },
4202     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4203     { "(bad)",  { XX } },
4204   },
4205
4206   /* PREFIX_VEX_380A */
4207   {
4208     { "(bad)",  { XX } },
4209     { "(bad)",  { XX } },
4210     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4211     { "(bad)",  { XX } },
4212   },
4213
4214   /* PREFIX_VEX_380B */
4215   {
4216     { "(bad)",  { XX } },
4217     { "(bad)",  { XX } },
4218     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4219     { "(bad)",  { XX } },
4220   },
4221
4222   /* PREFIX_VEX_380C */
4223   {
4224     { "(bad)",  { XX } },
4225     { "(bad)",  { XX } },
4226     { "vpermilps", { XM, Vex, EXx } },
4227     { "(bad)",  { XX } },
4228   },
4229
4230   /* PREFIX_VEX_380D */
4231   {
4232     { "(bad)",  { XX } },
4233     { "(bad)",  { XX } },
4234     { "vpermilpd", { XM, Vex, EXx } },
4235     { "(bad)",  { XX } },
4236   },
4237
4238   /* PREFIX_VEX_380E */
4239   {
4240     { "(bad)",  { XX } },
4241     { "(bad)",  { XX } },
4242     { "vtestps", { XM, EXx } },
4243     { "(bad)",  { XX } },
4244   },
4245
4246   /* PREFIX_VEX_380F */
4247   {
4248     { "(bad)",  { XX } },
4249     { "(bad)",  { XX } },
4250     { "vtestpd", { XM, EXx } },
4251     { "(bad)",  { XX } },
4252   },
4253
4254   /* PREFIX_VEX_3817 */
4255   {
4256     { "(bad)",  { XX } },
4257     { "(bad)",  { XX } },
4258     { "vptest", { XM, EXx } },
4259     { "(bad)",  { XX } },
4260   },
4261
4262   /* PREFIX_VEX_3818 */
4263   {
4264     { "(bad)",  { XX } },
4265     { "(bad)",  { XX } },
4266     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4267     { "(bad)",  { XX } },
4268   },
4269
4270   /* PREFIX_VEX_3819 */
4271   {
4272     { "(bad)",  { XX } },
4273     { "(bad)",  { XX } },
4274     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4275     { "(bad)",  { XX } },
4276   },
4277
4278   /* PREFIX_VEX_381A */
4279   {
4280     { "(bad)",  { XX } },
4281     { "(bad)",  { XX } },
4282     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4283     { "(bad)",  { XX } },
4284   },
4285
4286   /* PREFIX_VEX_381C */
4287   {
4288     { "(bad)",  { XX } },
4289     { "(bad)",  { XX } },
4290     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4291     { "(bad)",  { XX } },
4292   },
4293
4294   /* PREFIX_VEX_381D */
4295   {
4296     { "(bad)",  { XX } },
4297     { "(bad)",  { XX } },
4298     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4299     { "(bad)",  { XX } },
4300   },
4301
4302   /* PREFIX_VEX_381E */
4303   {
4304     { "(bad)",  { XX } },
4305     { "(bad)",  { XX } },
4306     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4307     { "(bad)",  { XX } },
4308   },
4309
4310   /* PREFIX_VEX_3820 */
4311   {
4312     { "(bad)",  { XX } },
4313     { "(bad)",  { XX } },
4314     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4315     { "(bad)",  { XX } },
4316   },
4317
4318   /* PREFIX_VEX_3821 */
4319   {
4320     { "(bad)",  { XX } },
4321     { "(bad)",  { XX } },
4322     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4323     { "(bad)",  { XX } },
4324   },
4325
4326   /* PREFIX_VEX_3822 */
4327   {
4328     { "(bad)",  { XX } },
4329     { "(bad)",  { XX } },
4330     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4331     { "(bad)",  { XX } },
4332   },
4333
4334   /* PREFIX_VEX_3823 */
4335   {
4336     { "(bad)",  { XX } },
4337     { "(bad)",  { XX } },
4338     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4339     { "(bad)",  { XX } },
4340   },
4341
4342   /* PREFIX_VEX_3824 */
4343   {
4344     { "(bad)",  { XX } },
4345     { "(bad)",  { XX } },
4346     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4347     { "(bad)",  { XX } },
4348   },
4349
4350   /* PREFIX_VEX_3825 */
4351   {
4352     { "(bad)",  { XX } },
4353     { "(bad)",  { XX } },
4354     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4355     { "(bad)",  { XX } },
4356   },
4357
4358   /* PREFIX_VEX_3828 */
4359   {
4360     { "(bad)",  { XX } },
4361     { "(bad)",  { XX } },
4362     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4363     { "(bad)",  { XX } },
4364   },
4365
4366   /* PREFIX_VEX_3829 */
4367   {
4368     { "(bad)",  { XX } },
4369     { "(bad)",  { XX } },
4370     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4371     { "(bad)",  { XX } },
4372   },
4373
4374   /* PREFIX_VEX_382A */
4375   {
4376     { "(bad)",  { XX } },
4377     { "(bad)",  { XX } },
4378     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4379     { "(bad)",  { XX } },
4380   },
4381
4382   /* PREFIX_VEX_382B */
4383   {
4384     { "(bad)",  { XX } },
4385     { "(bad)",  { XX } },
4386     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4387     { "(bad)",  { XX } },
4388   },
4389
4390   /* PREFIX_VEX_382C */
4391   {
4392     { "(bad)",  { XX } },
4393     { "(bad)",  { XX } },
4394      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4395     { "(bad)",  { XX } },
4396   },
4397
4398   /* PREFIX_VEX_382D */
4399   {
4400     { "(bad)",  { XX } },
4401     { "(bad)",  { XX } },
4402      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4403     { "(bad)",  { XX } },
4404   },
4405
4406   /* PREFIX_VEX_382E */
4407   {
4408     { "(bad)",  { XX } },
4409     { "(bad)",  { XX } },
4410      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4411     { "(bad)",  { XX } },
4412   },
4413
4414   /* PREFIX_VEX_382F */
4415   {
4416     { "(bad)",  { XX } },
4417     { "(bad)",  { XX } },
4418      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4419     { "(bad)",  { XX } },
4420   },
4421
4422   /* PREFIX_VEX_3830 */
4423   {
4424     { "(bad)",  { XX } },
4425     { "(bad)",  { XX } },
4426     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4427     { "(bad)",  { XX } },
4428   },
4429
4430   /* PREFIX_VEX_3831 */
4431   {
4432     { "(bad)",  { XX } },
4433     { "(bad)",  { XX } },
4434     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4435     { "(bad)",  { XX } },
4436   },
4437
4438   /* PREFIX_VEX_3832 */
4439   {
4440     { "(bad)",  { XX } },
4441     { "(bad)",  { XX } },
4442     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4443     { "(bad)",  { XX } },
4444   },
4445
4446   /* PREFIX_VEX_3833 */
4447   {
4448     { "(bad)",  { XX } },
4449     { "(bad)",  { XX } },
4450     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4451     { "(bad)",  { XX } },
4452   },
4453
4454   /* PREFIX_VEX_3834 */
4455   {
4456     { "(bad)",  { XX } },
4457     { "(bad)",  { XX } },
4458     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4459     { "(bad)",  { XX } },
4460   },
4461
4462   /* PREFIX_VEX_3835 */
4463   {
4464     { "(bad)",  { XX } },
4465     { "(bad)",  { XX } },
4466     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4467     { "(bad)",  { XX } },
4468   },
4469
4470   /* PREFIX_VEX_3837 */
4471   {
4472     { "(bad)",  { XX } },
4473     { "(bad)",  { XX } },
4474     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4475     { "(bad)",  { XX } },
4476   },
4477
4478   /* PREFIX_VEX_3838 */
4479   {
4480     { "(bad)",  { XX } },
4481     { "(bad)",  { XX } },
4482     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4483     { "(bad)",  { XX } },
4484   },
4485
4486   /* PREFIX_VEX_3839 */
4487   {
4488     { "(bad)",  { XX } },
4489     { "(bad)",  { XX } },
4490     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4491     { "(bad)",  { XX } },
4492   },
4493
4494   /* PREFIX_VEX_383A */
4495   {
4496     { "(bad)",  { XX } },
4497     { "(bad)",  { XX } },
4498     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4499     { "(bad)",  { XX } },
4500   },
4501
4502   /* PREFIX_VEX_383B */
4503   {
4504     { "(bad)",  { XX } },
4505     { "(bad)",  { XX } },
4506     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4507     { "(bad)",  { XX } },
4508   },
4509
4510   /* PREFIX_VEX_383C */
4511   {
4512     { "(bad)",  { XX } },
4513     { "(bad)",  { XX } },
4514     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4515     { "(bad)",  { XX } },
4516   },
4517
4518   /* PREFIX_VEX_383D */
4519   {
4520     { "(bad)",  { XX } },
4521     { "(bad)",  { XX } },
4522     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4523     { "(bad)",  { XX } },
4524   },
4525
4526   /* PREFIX_VEX_383E */
4527   {
4528     { "(bad)",  { XX } },
4529     { "(bad)",  { XX } },
4530     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4531     { "(bad)",  { XX } },
4532   },
4533
4534   /* PREFIX_VEX_383F */
4535   {
4536     { "(bad)",  { XX } },
4537     { "(bad)",  { XX } },
4538     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4539     { "(bad)",  { XX } },
4540   },
4541
4542   /* PREFIX_VEX_3840 */
4543   {
4544     { "(bad)",  { XX } },
4545     { "(bad)",  { XX } },
4546     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4547     { "(bad)",  { XX } },
4548   },
4549
4550   /* PREFIX_VEX_3841 */
4551   {
4552     { "(bad)",  { XX } },
4553     { "(bad)",  { XX } },
4554     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4555     { "(bad)",  { XX } },
4556   },
4557
4558   /* PREFIX_VEX_38DB */
4559   {
4560     { "(bad)",  { XX } },
4561     { "(bad)",  { XX } },
4562     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4563     { "(bad)",  { XX } },
4564   },
4565
4566   /* PREFIX_VEX_38DC */
4567   {
4568     { "(bad)",  { XX } },
4569     { "(bad)",  { XX } },
4570     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4571     { "(bad)",  { XX } },
4572   },
4573
4574   /* PREFIX_VEX_38DD */
4575   {
4576     { "(bad)",  { XX } },
4577     { "(bad)",  { XX } },
4578     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4579     { "(bad)",  { XX } },
4580   },
4581
4582   /* PREFIX_VEX_38DE */
4583   {
4584     { "(bad)",  { XX } },
4585     { "(bad)",  { XX } },
4586     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4587     { "(bad)",  { XX } },
4588   },
4589
4590   /* PREFIX_VEX_38DF */
4591   {
4592     { "(bad)",  { XX } },
4593     { "(bad)",  { XX } },
4594     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4595     { "(bad)",  { XX } },
4596   },
4597
4598   /* PREFIX_VEX_3A04 */
4599   {
4600     { "(bad)",  { XX } },
4601     { "(bad)",  { XX } },
4602     { "vpermilps", { XM, EXx, Ib } },
4603     { "(bad)",  { XX } },
4604   },
4605
4606   /* PREFIX_VEX_3A05 */
4607   {
4608     { "(bad)",  { XX } },
4609     { "(bad)",  { XX } },
4610     { "vpermilpd", { XM, EXx, Ib } },
4611     { "(bad)",  { XX } },
4612   },
4613
4614   /* PREFIX_VEX_3A06 */
4615   {
4616     { "(bad)",  { XX } },
4617     { "(bad)",  { XX } },
4618     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4619     { "(bad)",  { XX } },
4620   },
4621
4622   /* PREFIX_VEX_3A08 */
4623   {
4624     { "(bad)",  { XX } },
4625     { "(bad)",  { XX } },
4626     { "vroundps", { XM, EXx, Ib } },
4627     { "(bad)",  { XX } },
4628   },
4629
4630   /* PREFIX_VEX_3A09 */
4631   {
4632     { "(bad)",  { XX } },
4633     { "(bad)",  { XX } },
4634     { "vroundpd", { XM, EXx, Ib } },
4635     { "(bad)",  { XX } },
4636   },
4637
4638   /* PREFIX_VEX_3A0A */
4639   {
4640     { "(bad)",  { XX } },
4641     { "(bad)",  { XX } },
4642     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4643     { "(bad)",  { XX } },
4644   },
4645
4646   /* PREFIX_VEX_3A0B */
4647   {
4648     { "(bad)",  { XX } },
4649     { "(bad)",  { XX } },
4650     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4651     { "(bad)",  { XX } },
4652   },
4653
4654   /* PREFIX_VEX_3A0C */
4655   {
4656     { "(bad)",  { XX } },
4657     { "(bad)",  { XX } },
4658     { "vblendps", { XM, Vex, EXx, Ib } },
4659     { "(bad)",  { XX } },
4660   },
4661
4662   /* PREFIX_VEX_3A0D */
4663   {
4664     { "(bad)",  { XX } },
4665     { "(bad)",  { XX } },
4666     { "vblendpd", { XM, Vex, EXx, Ib } },
4667     { "(bad)",  { XX } },
4668   },
4669
4670   /* PREFIX_VEX_3A0E */
4671   {
4672     { "(bad)",  { XX } },
4673     { "(bad)",  { XX } },
4674     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4675     { "(bad)",  { XX } },
4676   },
4677
4678   /* PREFIX_VEX_3A0F */
4679   {
4680     { "(bad)",  { XX } },
4681     { "(bad)",  { XX } },
4682     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4683     { "(bad)",  { XX } },
4684   },
4685
4686   /* PREFIX_VEX_3A14 */
4687   {
4688     { "(bad)",  { XX } },
4689     { "(bad)",  { XX } },
4690     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4691     { "(bad)",  { XX } },
4692   },
4693
4694   /* PREFIX_VEX_3A15 */
4695   {
4696     { "(bad)",  { XX } },
4697     { "(bad)",  { XX } },
4698     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4699     { "(bad)",  { XX } },
4700   },
4701
4702   /* PREFIX_VEX_3A16 */
4703   {
4704     { "(bad)",  { XX } },
4705     { "(bad)",  { XX } },
4706     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4707     { "(bad)",  { XX } },
4708   },
4709
4710   /* PREFIX_VEX_3A17 */
4711   {
4712     { "(bad)",  { XX } },
4713     { "(bad)",  { XX } },
4714     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
4715     { "(bad)",  { XX } },
4716   },
4717
4718   /* PREFIX_VEX_3A18 */
4719   {
4720     { "(bad)",  { XX } },
4721     { "(bad)",  { XX } },
4722     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
4723     { "(bad)",  { XX } },
4724   },
4725
4726   /* PREFIX_VEX_3A19 */
4727   {
4728     { "(bad)",  { XX } },
4729     { "(bad)",  { XX } },
4730     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
4731     { "(bad)",  { XX } },
4732   },
4733
4734   /* PREFIX_VEX_3A20 */
4735   {
4736     { "(bad)",  { XX } },
4737     { "(bad)",  { XX } },
4738     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
4739     { "(bad)",  { XX } },
4740   },
4741
4742   /* PREFIX_VEX_3A21 */
4743   {
4744     { "(bad)",  { XX } },
4745     { "(bad)",  { XX } },
4746     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
4747     { "(bad)",  { XX } },
4748   },
4749
4750   /* PREFIX_VEX_3A22 */
4751   {
4752     { "(bad)",  { XX } },
4753     { "(bad)",  { XX } },
4754     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
4755     { "(bad)",  { XX } },
4756   },
4757
4758   /* PREFIX_VEX_3A40 */
4759   {
4760     { "(bad)",  { XX } },
4761     { "(bad)",  { XX } },
4762     { "vdpps",  { XM, Vex, EXx, Ib } },
4763     { "(bad)",  { XX } },
4764   },
4765
4766   /* PREFIX_VEX_3A41 */
4767   {
4768     { "(bad)",  { XX } },
4769     { "(bad)",  { XX } },
4770     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
4771     { "(bad)",  { XX } },
4772   },
4773
4774   /* PREFIX_VEX_3A42 */
4775   {
4776     { "(bad)",  { XX } },
4777     { "(bad)",  { XX } },
4778     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
4779     { "(bad)",  { XX } },
4780   },
4781
4782   /* PREFIX_VEX_3A48 */
4783   {
4784     { "(bad)",  { XX } },
4785     { "(bad)",  { XX } },
4786     { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
4787     { "(bad)",  { XX } },
4788   },
4789
4790   /* PREFIX_VEX_3A49 */
4791   {
4792     { "(bad)",  { XX } },
4793     { "(bad)",  { XX } },
4794     { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
4795     { "(bad)",  { XX } },
4796   },
4797
4798   /* PREFIX_VEX_3A4A */
4799   {
4800     { "(bad)",  { XX } },
4801     { "(bad)",  { XX } },
4802     { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
4803     { "(bad)",  { XX } },
4804   },
4805
4806   /* PREFIX_VEX_3A4B */
4807   {
4808     { "(bad)",  { XX } },
4809     { "(bad)",  { XX } },
4810     { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
4811     { "(bad)",  { XX } },
4812   },
4813
4814   /* PREFIX_VEX_3A4C */
4815   {
4816     { "(bad)",  { XX } },
4817     { "(bad)",  { XX } },
4818     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
4819     { "(bad)",  { XX } },
4820   },
4821
4822   /* PREFIX_VEX_3A5C */
4823   {
4824     { "(bad)",  { XX } },
4825     { "(bad)",  { XX } },
4826     { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4827     { "(bad)",  { XX } },
4828   },
4829
4830   /* PREFIX_VEX_3A5D */
4831   {
4832     { "(bad)",  { XX } },
4833     { "(bad)",  { XX } },
4834     { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4835     { "(bad)",  { XX } },
4836   },
4837
4838   /* PREFIX_VEX_3A5E */
4839   {
4840     { "(bad)",  { XX } },
4841     { "(bad)",  { XX } },
4842     { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4843     { "(bad)",  { XX } },
4844   },
4845
4846   /* PREFIX_VEX_3A5F */
4847   {
4848     { "(bad)",  { XX } },
4849     { "(bad)",  { XX } },
4850     { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4851     { "(bad)",  { XX } },
4852   },
4853
4854   /* PREFIX_VEX_3A60 */
4855   {
4856     { "(bad)",  { XX } },
4857     { "(bad)",  { XX } },
4858     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
4859     { "(bad)",  { XX } },
4860   },
4861
4862   /* PREFIX_VEX_3A61 */
4863   {
4864     { "(bad)",  { XX } },
4865     { "(bad)",  { XX } },
4866     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
4867     { "(bad)",  { XX } },
4868   },
4869
4870   /* PREFIX_VEX_3A62 */
4871   {
4872     { "(bad)",  { XX } },
4873     { "(bad)",  { XX } },
4874     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
4875     { "(bad)",  { XX } },
4876   },
4877
4878   /* PREFIX_VEX_3A63 */
4879   {
4880     { "(bad)",  { XX } },
4881     { "(bad)",  { XX } },
4882     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
4883     { "(bad)",  { XX } },
4884   },
4885
4886   /* PREFIX_VEX_3A68 */
4887   {
4888     { "(bad)",  { XX } },
4889     { "(bad)",  { XX } },
4890     { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4891     { "(bad)",  { XX } },
4892   },
4893
4894   /* PREFIX_VEX_3A69 */
4895   {
4896     { "(bad)",  { XX } },
4897     { "(bad)",  { XX } },
4898     { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4899     { "(bad)",  { XX } },
4900   },
4901
4902   /* PREFIX_VEX_3A6A */
4903   {
4904     { "(bad)",  { XX } },
4905     { "(bad)",  { XX } },
4906     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
4907     { "(bad)",  { XX } },
4908   },
4909
4910   /* PREFIX_VEX_3A6B */
4911   {
4912     { "(bad)",  { XX } },
4913     { "(bad)",  { XX } },
4914     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
4915     { "(bad)",  { XX } },
4916   },
4917
4918   /* PREFIX_VEX_3A6C */
4919   {
4920     { "(bad)",  { XX } },
4921     { "(bad)",  { XX } },
4922     { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4923     { "(bad)",  { XX } },
4924   },
4925
4926   /* PREFIX_VEX_3A6D */
4927   {
4928     { "(bad)",  { XX } },
4929     { "(bad)",  { XX } },
4930     { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4931     { "(bad)",  { XX } },
4932   },
4933
4934   /* PREFIX_VEX_3A6E */
4935   {
4936     { "(bad)",  { XX } },
4937     { "(bad)",  { XX } },
4938     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
4939     { "(bad)",  { XX } },
4940   },
4941
4942   /* PREFIX_VEX_3A6F */
4943   {
4944     { "(bad)",  { XX } },
4945     { "(bad)",  { XX } },
4946     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
4947     { "(bad)",  { XX } },
4948   },
4949
4950   /* PREFIX_VEX_3A78 */
4951   {
4952     { "(bad)",  { XX } },
4953     { "(bad)",  { XX } },
4954     { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4955     { "(bad)",  { XX } },
4956   },
4957
4958   /* PREFIX_VEX_3A79 */
4959   {
4960     { "(bad)",  { XX } },
4961     { "(bad)",  { XX } },
4962     { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4963     { "(bad)",  { XX } },
4964   },
4965
4966   /* PREFIX_VEX_3A7A */
4967   {
4968     { "(bad)",  { XX } },
4969     { "(bad)",  { XX } },
4970     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
4971     { "(bad)",  { XX } },
4972   },
4973
4974   /* PREFIX_VEX_3A7B */
4975   {
4976     { "(bad)",  { XX } },
4977     { "(bad)",  { XX } },
4978     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
4979     { "(bad)",  { XX } },
4980   },
4981
4982   /* PREFIX_VEX_3A7C */
4983   {
4984     { "(bad)",  { XX } },
4985     { "(bad)",  { XX } },
4986     { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4987     { "(bad)",  { XX } },
4988   },
4989
4990   /* PREFIX_VEX_3A7D */
4991   {
4992     { "(bad)",  { XX } },
4993     { "(bad)",  { XX } },
4994     { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4995     { "(bad)",  { XX } },
4996   },
4997
4998   /* PREFIX_VEX_3A7E */
4999   {
5000     { "(bad)",  { XX } },
5001     { "(bad)",  { XX } },
5002     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5003     { "(bad)",  { XX } },
5004   },
5005
5006   /* PREFIX_VEX_3A7F */
5007   {
5008     { "(bad)",  { XX } },
5009     { "(bad)",  { XX } },
5010     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5011     { "(bad)",  { XX } },
5012   },
5013
5014   /* PREFIX_VEX_3ADF */
5015   {
5016     { "(bad)",  { XX } },
5017     { "(bad)",  { XX } },
5018     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5019     { "(bad)",  { XX } },
5020   },
5021 };
5022
5023 static const struct dis386 x86_64_table[][2] = {
5024   /* X86_64_06 */
5025   {
5026     { "push{T|}", { es } },
5027     { "(bad)", { XX } },
5028   },
5029
5030   /* X86_64_07 */
5031   {
5032     { "pop{T|}", { es } },
5033     { "(bad)", { XX } },
5034   },
5035
5036   /* X86_64_0D */
5037   {
5038     { "push{T|}", { cs } },
5039     { "(bad)", { XX } },
5040   },
5041
5042   /* X86_64_16 */
5043   {
5044     { "push{T|}", { ss } },
5045     { "(bad)", { XX } },
5046   },
5047
5048   /* X86_64_17 */
5049   {
5050     { "pop{T|}", { ss } },
5051     { "(bad)", { XX } },
5052   },
5053
5054   /* X86_64_1E */
5055   {
5056     { "push{T|}", { ds } },
5057     { "(bad)", { XX } },
5058   },
5059
5060   /* X86_64_1F */
5061   {
5062     { "pop{T|}", { ds } },
5063     { "(bad)", { XX } },
5064   },
5065
5066   /* X86_64_27 */
5067   {
5068     { "daa", { XX } },
5069     { "(bad)", { XX } },
5070   },
5071
5072   /* X86_64_2F */
5073   {
5074     { "das", { XX } },
5075     { "(bad)", { XX } },
5076   },
5077
5078   /* X86_64_37 */
5079   {
5080     { "aaa", { XX } },
5081     { "(bad)", { XX } },
5082   },
5083
5084   /* X86_64_3F */
5085   {
5086     { "aas", { XX } },
5087     { "(bad)", { XX } },
5088   },
5089
5090   /* X86_64_60 */
5091   {
5092     { "pusha{P|}", { XX } },
5093     { "(bad)", { XX } },
5094   },
5095
5096   /* X86_64_61 */
5097   {
5098     { "popa{P|}", { XX } },
5099     { "(bad)", { XX } },
5100   },
5101
5102   /* X86_64_62 */
5103   {
5104     { MOD_TABLE (MOD_62_32BIT) },
5105     { "(bad)", { XX } },
5106   },
5107
5108   /* X86_64_63 */
5109   {
5110     { "arpl", { Ew, Gw } },
5111     { "movs{lq|xd}", { Gv, Ed } },
5112   },
5113
5114   /* X86_64_6D */
5115   {
5116     { "ins{R|}", { Yzr, indirDX } },
5117     { "ins{G|}", { Yzr, indirDX } },
5118   },
5119
5120   /* X86_64_6F */
5121   {
5122     { "outs{R|}", { indirDXr, Xz } },
5123     { "outs{G|}", { indirDXr, Xz } },
5124   },
5125
5126   /* X86_64_9A */
5127   {
5128     { "Jcall{T|}", { Ap } },
5129     { "(bad)", { XX } },
5130   },
5131
5132   /* X86_64_C4 */
5133   {
5134     { MOD_TABLE (MOD_C4_32BIT) },
5135     { VEX_C4_TABLE (VEX_0F) },
5136   },
5137
5138   /* X86_64_C5 */
5139   {
5140     { MOD_TABLE (MOD_C5_32BIT) },
5141     { VEX_C5_TABLE (VEX_0F) },
5142   },
5143
5144   /* X86_64_CE */
5145   {
5146     { "into", { XX } },
5147     { "(bad)", { XX } },
5148   },
5149
5150   /* X86_64_D4 */
5151   {
5152     { "aam", { sIb } },
5153     { "(bad)", { XX } },
5154   },
5155
5156   /* X86_64_D5 */
5157   {
5158     { "aad", { sIb } },
5159     { "(bad)", { XX } },
5160   },
5161
5162   /* X86_64_EA */
5163   {
5164     { "Jjmp{T|}", { Ap } },
5165     { "(bad)", { XX } },
5166   },
5167
5168   /* X86_64_0F01_REG_0 */
5169   {
5170     { "sgdt{Q|IQ}", { M } },
5171     { "sgdt", { M } },
5172   },
5173
5174   /* X86_64_0F01_REG_1 */
5175   {
5176     { "sidt{Q|IQ}", { M } },
5177     { "sidt", { M } },
5178   },
5179
5180   /* X86_64_0F01_REG_2 */
5181   {
5182     { "lgdt{Q|Q}", { M } },
5183     { "lgdt", { M } },
5184   },
5185
5186   /* X86_64_0F01_REG_3 */
5187   {
5188     { "lidt{Q|Q}", { M } },
5189     { "lidt", { M } },
5190   },
5191 };
5192
5193 static const struct dis386 three_byte_table[][256] = {
5194   /* THREE_BYTE_0F24 */
5195   {
5196     /* 00 */
5197     { "fmaddps",        { { OP_DREX4, q_mode } } },
5198     { "fmaddpd",        { { OP_DREX4, q_mode } } },
5199     { "fmaddss",        { { OP_DREX4, w_mode } } },
5200     { "fmaddsd",        { { OP_DREX4, d_mode } } },
5201     { "fmaddps",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5202     { "fmaddpd",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5203     { "fmaddss",        { { OP_DREX4, DREX_OC1 + w_mode } } },
5204     { "fmaddsd",        { { OP_DREX4, DREX_OC1 + d_mode } } },
5205     /* 08 */
5206     { "fmsubps",        { { OP_DREX4, q_mode } } },
5207     { "fmsubpd",        { { OP_DREX4, q_mode } } },
5208     { "fmsubss",        { { OP_DREX4, w_mode } } },
5209     { "fmsubsd",        { { OP_DREX4, d_mode } } },
5210     { "fmsubps",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5211     { "fmsubpd",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5212     { "fmsubss",        { { OP_DREX4, DREX_OC1 + w_mode } } },
5213     { "fmsubsd",        { { OP_DREX4, DREX_OC1 + d_mode } } },
5214     /* 10 */
5215     { "fnmaddps",       { { OP_DREX4, q_mode } } },
5216     { "fnmaddpd",       { { OP_DREX4, q_mode } } },
5217     { "fnmaddss",       { { OP_DREX4, w_mode } } },
5218     { "fnmaddsd",       { { OP_DREX4, d_mode } } },
5219     { "fnmaddps",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5220     { "fnmaddpd",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5221     { "fnmaddss",       { { OP_DREX4, DREX_OC1 + w_mode } } },
5222     { "fnmaddsd",       { { OP_DREX4, DREX_OC1 + d_mode } } },
5223     /* 18 */
5224     { "fnmsubps",       { { OP_DREX4, q_mode } } },
5225     { "fnmsubpd",       { { OP_DREX4, q_mode } } },
5226     { "fnmsubss",       { { OP_DREX4, w_mode } } },
5227     { "fnmsubsd",       { { OP_DREX4, d_mode } } },
5228     { "fnmsubps",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5229     { "fnmsubpd",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5230     { "fnmsubss",       { { OP_DREX4, DREX_OC1 + w_mode } } },
5231     { "fnmsubsd",       { { OP_DREX4, DREX_OC1 + d_mode } } },
5232     /* 20 */
5233     { "permps",         { { OP_DREX4, q_mode } } },
5234     { "permpd",         { { OP_DREX4, q_mode } } },
5235     { "pcmov",          { { OP_DREX4, q_mode } } },
5236     { "pperm",          { { OP_DREX4, q_mode } } },
5237     { "permps",         { { OP_DREX4, DREX_OC1 + q_mode } } },
5238     { "permpd",         { { OP_DREX4, DREX_OC1 + q_mode } } },
5239     { "pcmov",          { { OP_DREX4, DREX_OC1 + w_mode } } },
5240     { "pperm",          { { OP_DREX4, DREX_OC1 + d_mode } } },
5241     /* 28 */
5242     { "(bad)",          { XX } },
5243     { "(bad)",          { XX } },
5244     { "(bad)",          { XX } },
5245     { "(bad)",          { XX } },
5246     { "(bad)",          { XX } },
5247     { "(bad)",          { XX } },
5248     { "(bad)",          { XX } },
5249     { "(bad)",          { XX } },
5250     /* 30 */
5251     { "(bad)",          { XX } },
5252     { "(bad)",          { XX } },
5253     { "(bad)",          { XX } },
5254     { "(bad)",          { XX } },
5255     { "(bad)",          { XX } },
5256     { "(bad)",          { XX } },
5257     { "(bad)",          { XX } },
5258     { "(bad)",          { XX } },
5259     /* 38 */
5260     { "(bad)",          { XX } },
5261     { "(bad)",          { XX } },
5262     { "(bad)",          { XX } },
5263     { "(bad)",          { XX } },
5264     { "(bad)",          { XX } },
5265     { "(bad)",          { XX } },
5266     { "(bad)",          { XX } },
5267     { "(bad)",          { XX } },
5268     /* 40 */
5269     { "protb",          { { OP_DREX3, q_mode } } },
5270     { "protw",          { { OP_DREX3, q_mode } } },
5271     { "protd",          { { OP_DREX3, q_mode } } },
5272     { "protq",          { { OP_DREX3, q_mode } } },
5273     { "pshlb",          { { OP_DREX3, q_mode } } },
5274     { "pshlw",          { { OP_DREX3, q_mode } } },
5275     { "pshld",          { { OP_DREX3, q_mode } } },
5276     { "pshlq",          { { OP_DREX3, q_mode } } },
5277     /* 48 */
5278     { "pshab",          { { OP_DREX3, q_mode } } },
5279     { "pshaw",          { { OP_DREX3, q_mode } } },
5280     { "pshad",          { { OP_DREX3, q_mode } } },
5281     { "pshaq",          { { OP_DREX3, q_mode } } },
5282     { "(bad)",          { XX } },
5283     { "(bad)",          { XX } },
5284     { "(bad)",          { XX } },
5285     { "(bad)",          { XX } },
5286     /* 50 */
5287     { "(bad)",          { XX } },
5288     { "(bad)",          { XX } },
5289     { "(bad)",          { XX } },
5290     { "(bad)",          { XX } },
5291     { "(bad)",          { XX } },
5292     { "(bad)",          { XX } },
5293     { "(bad)",          { XX } },
5294     { "(bad)",          { XX } },
5295     /* 58 */
5296     { "(bad)",          { XX } },
5297     { "(bad)",          { XX } },
5298     { "(bad)",          { XX } },
5299     { "(bad)",          { XX } },
5300     { "(bad)",          { XX } },
5301     { "(bad)",          { XX } },
5302     { "(bad)",          { XX } },
5303     { "(bad)",          { XX } },
5304     /* 60 */
5305     { "(bad)",          { XX } },
5306     { "(bad)",          { XX } },
5307     { "(bad)",          { XX } },
5308     { "(bad)",          { XX } },
5309     { "(bad)",          { XX } },
5310     { "(bad)",          { XX } },
5311     { "(bad)",          { XX } },
5312     { "(bad)",          { XX } },
5313     /* 68 */
5314     { "(bad)",          { XX } },
5315     { "(bad)",          { XX } },
5316     { "(bad)",          { XX } },
5317     { "(bad)",          { XX } },
5318     { "(bad)",          { XX } },
5319     { "(bad)",          { XX } },
5320     { "(bad)",          { XX } },
5321     { "(bad)",          { XX } },
5322     /* 70 */
5323     { "(bad)",          { XX } },
5324     { "(bad)",          { XX } },
5325     { "(bad)",          { XX } },
5326     { "(bad)",          { XX } },
5327     { "(bad)",          { XX } },
5328     { "(bad)",          { XX } },
5329     { "(bad)",          { XX } },
5330     { "(bad)",          { XX } },
5331     /* 78 */
5332     { "(bad)",          { XX } },
5333     { "(bad)",          { XX } },
5334     { "(bad)",          { XX } },
5335     { "(bad)",          { XX } },
5336     { "(bad)",          { XX } },
5337     { "(bad)",          { XX } },
5338     { "(bad)",          { XX } },
5339     { "(bad)",          { XX } },
5340     /* 80 */
5341     { "(bad)",          { XX } },
5342     { "(bad)",          { XX } },
5343     { "(bad)",          { XX } },
5344     { "(bad)",          { XX } },
5345     { "(bad)",          { XX } },
5346     { "pmacssww",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5347     { "pmacsswd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5348     { "pmacssdql",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5349     /* 88 */
5350     { "(bad)",          { XX } },
5351     { "(bad)",          { XX } },
5352     { "(bad)",          { XX } },
5353     { "(bad)",          { XX } },
5354     { "(bad)",          { XX } },
5355     { "(bad)",          { XX } },
5356     { "pmacssdd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5357     { "pmacssdqh",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5358     /* 90 */
5359     { "(bad)",          { XX } },
5360     { "(bad)",          { XX } },
5361     { "(bad)",          { XX } },
5362     { "(bad)",          { XX } },
5363     { "(bad)",          { XX } },
5364     { "pmacsww",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5365     { "pmacswd",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5366     { "pmacsdql",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5367     /* 98 */
5368     { "(bad)",          { XX } },
5369     { "(bad)",          { XX } },
5370     { "(bad)",          { XX } },
5371     { "(bad)",          { XX } },
5372     { "(bad)",          { XX } },
5373     { "(bad)",          { XX } },
5374     { "pmacsdd",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5375     { "pmacsdqh",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5376     /* a0 */
5377     { "(bad)",          { XX } },
5378     { "(bad)",          { XX } },
5379     { "(bad)",          { XX } },
5380     { "(bad)",          { XX } },
5381     { "(bad)",          { XX } },
5382     { "(bad)",          { XX } },
5383     { "pmadcsswd",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5384     { "(bad)",          { XX } },
5385     /* a8 */
5386     { "(bad)",          { XX } },
5387     { "(bad)",          { XX } },
5388     { "(bad)",          { XX } },
5389     { "(bad)",          { XX } },
5390     { "(bad)",          { XX } },
5391     { "(bad)",          { XX } },
5392     { "(bad)",          { XX } },
5393     { "(bad)",          { XX } },
5394     /* b0 */
5395     { "(bad)",          { XX } },
5396     { "(bad)",          { XX } },
5397     { "(bad)",          { XX } },
5398     { "(bad)",          { XX } },
5399     { "(bad)",          { XX } },
5400     { "(bad)",          { XX } },
5401     { "pmadcswd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5402     { "(bad)",          { XX } },
5403     /* b8 */
5404     { "(bad)",          { XX } },
5405     { "(bad)",          { XX } },
5406     { "(bad)",          { XX } },
5407     { "(bad)",          { XX } },
5408     { "(bad)",          { XX } },
5409     { "(bad)",          { XX } },
5410     { "(bad)",          { XX } },
5411     { "(bad)",          { XX } },
5412     /* c0 */
5413     { "(bad)",          { XX } },
5414     { "(bad)",          { XX } },
5415     { "(bad)",          { XX } },
5416     { "(bad)",          { XX } },
5417     { "(bad)",          { XX } },
5418     { "(bad)",          { XX } },
5419     { "(bad)",          { XX } },
5420     { "(bad)",          { XX } },
5421     /* c8 */
5422     { "(bad)",          { XX } },
5423     { "(bad)",          { XX } },
5424     { "(bad)",          { XX } },
5425     { "(bad)",          { XX } },
5426     { "(bad)",          { XX } },
5427     { "(bad)",          { XX } },
5428     { "(bad)",          { XX } },
5429     { "(bad)",          { XX } },
5430     /* d0 */
5431     { "(bad)",          { XX } },
5432     { "(bad)",          { XX } },
5433     { "(bad)",          { XX } },
5434     { "(bad)",          { XX } },
5435     { "(bad)",          { XX } },
5436     { "(bad)",          { XX } },
5437     { "(bad)",          { XX } },
5438     { "(bad)",          { XX } },
5439     /* d8 */
5440     { "(bad)",          { XX } },
5441     { "(bad)",          { XX } },
5442     { "(bad)",          { XX } },
5443     { "(bad)",          { XX } },
5444     { "(bad)",          { XX } },
5445     { "(bad)",          { XX } },
5446     { "(bad)",          { XX } },
5447     { "(bad)",          { XX } },
5448     /* e0 */
5449     { "(bad)",          { XX } },
5450     { "(bad)",          { XX } },
5451     { "(bad)",          { XX } },
5452     { "(bad)",          { XX } },
5453     { "(bad)",          { XX } },
5454     { "(bad)",          { XX } },
5455     { "(bad)",          { XX } },
5456     { "(bad)",          { XX } },
5457     /* e8 */
5458     { "(bad)",          { XX } },
5459     { "(bad)",          { XX } },
5460     { "(bad)",          { XX } },
5461     { "(bad)",          { XX } },
5462     { "(bad)",          { XX } },
5463     { "(bad)",          { XX } },
5464     { "(bad)",          { XX } },
5465     { "(bad)",          { XX } },
5466     /* f0 */
5467     { "(bad)",          { XX } },
5468     { "(bad)",          { XX } },
5469     { "(bad)",          { XX } },
5470     { "(bad)",          { XX } },
5471     { "(bad)",          { XX } },
5472     { "(bad)",          { XX } },
5473     { "(bad)",          { XX } },
5474     { "(bad)",          { XX } },
5475     /* f8 */
5476     { "(bad)",          { XX } },
5477     { "(bad)",          { XX } },
5478     { "(bad)",          { XX } },
5479     { "(bad)",          { XX } },
5480     { "(bad)",          { XX } },
5481     { "(bad)",          { XX } },
5482     { "(bad)",          { XX } },
5483     { "(bad)",          { XX } },
5484   },
5485   /* THREE_BYTE_0F25 */
5486   {
5487     /* 00 */
5488     { "(bad)",          { XX } },
5489     { "(bad)",          { XX } },
5490     { "(bad)",          { XX } },
5491     { "(bad)",          { XX } },
5492     { "(bad)",          { XX } },
5493     { "(bad)",          { XX } },
5494     { "(bad)",          { XX } },
5495     { "(bad)",          { XX } },
5496     /* 08 */
5497     { "(bad)",          { XX } },
5498     { "(bad)",          { XX } },
5499     { "(bad)",          { XX } },
5500     { "(bad)",          { XX } },
5501     { "(bad)",          { XX } },
5502     { "(bad)",          { XX } },
5503     { "(bad)",          { XX } },
5504     { "(bad)",          { XX } },
5505     /* 10 */
5506     { "(bad)",          { XX } },
5507     { "(bad)",          { XX } },
5508     { "(bad)",          { XX } },
5509     { "(bad)",          { XX } },
5510     { "(bad)",          { XX } },
5511     { "(bad)",          { XX } },
5512     { "(bad)",          { XX } },
5513     { "(bad)",          { XX } },
5514     /* 18 */
5515     { "(bad)",          { XX } },
5516     { "(bad)",          { XX } },
5517     { "(bad)",          { XX } },
5518     { "(bad)",          { XX } },
5519     { "(bad)",          { XX } },
5520     { "(bad)",          { XX } },
5521     { "(bad)",          { XX } },
5522     { "(bad)",          { XX } },
5523     /* 20 */
5524     { "(bad)",          { XX } },
5525     { "(bad)",          { XX } },
5526     { "(bad)",          { XX } },
5527     { "(bad)",          { XX } },
5528     { "(bad)",          { XX } },
5529     { "(bad)",          { XX } },
5530     { "(bad)",          { XX } },
5531     { "(bad)",          { XX } },
5532     /* 28 */
5533     { "(bad)",          { XX } },
5534     { "(bad)",          { XX } },
5535     { "(bad)",          { XX } },
5536     { "(bad)",          { XX } },
5537     { "comps",          { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5538     { "compd",          { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5539     { "comss",          { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
5540     { "comsd",          { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
5541     /* 30 */
5542     { "(bad)",          { XX } },
5543     { "(bad)",          { XX } },
5544     { "(bad)",          { XX } },
5545     { "(bad)",          { XX } },
5546     { "(bad)",          { XX } },
5547     { "(bad)",          { XX } },
5548     { "(bad)",          { XX } },
5549     { "(bad)",          { XX } },
5550     /* 38 */
5551     { "(bad)",          { XX } },
5552     { "(bad)",          { XX } },
5553     { "(bad)",          { XX } },
5554     { "(bad)",          { XX } },
5555     { "(bad)",          { XX } },
5556     { "(bad)",          { XX } },
5557     { "(bad)",          { XX } },
5558     { "(bad)",          { XX } },
5559     /* 40 */
5560     { "(bad)",          { XX } },
5561     { "(bad)",          { XX } },
5562     { "(bad)",          { XX } },
5563     { "(bad)",          { XX } },
5564     { "(bad)",          { XX } },
5565     { "(bad)",          { XX } },
5566     { "(bad)",          { XX } },
5567     { "(bad)",          { XX } },
5568     /* 48 */
5569     { "(bad)",          { XX } },
5570     { "(bad)",          { XX } },
5571     { "(bad)",          { XX } },
5572     { "(bad)",          { XX } },
5573     { "pcomb",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5574     { "pcomw",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5575     { "pcomd",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5576     { "pcomq",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5577     /* 50 */
5578     { "(bad)",          { XX } },
5579     { "(bad)",          { XX } },
5580     { "(bad)",          { XX } },
5581     { "(bad)",          { XX } },
5582     { "(bad)",          { XX } },
5583     { "(bad)",          { XX } },
5584     { "(bad)",          { XX } },
5585     { "(bad)",          { XX } },
5586     /* 58 */
5587     { "(bad)",          { XX } },
5588     { "(bad)",          { XX } },
5589     { "(bad)",          { XX } },
5590     { "(bad)",          { XX } },
5591     { "(bad)",          { XX } },
5592     { "(bad)",          { XX } },
5593     { "(bad)",          { XX } },
5594     { "(bad)",          { XX } },
5595     /* 60 */
5596     { "(bad)",          { XX } },
5597     { "(bad)",          { XX } },
5598     { "(bad)",          { XX } },
5599     { "(bad)",          { XX } },
5600     { "(bad)",          { XX } },
5601     { "(bad)",          { XX } },
5602     { "(bad)",          { XX } },
5603     { "(bad)",          { XX } },
5604     /* 68 */
5605     { "(bad)",          { XX } },
5606     { "(bad)",          { XX } },
5607     { "(bad)",          { XX } },
5608     { "(bad)",          { XX } },
5609     { "pcomub",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5610     { "pcomuw",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5611     { "pcomud",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5612     { "pcomuq",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5613     /* 70 */
5614     { "(bad)",          { XX } },
5615     { "(bad)",          { XX } },
5616     { "(bad)",          { XX } },
5617     { "(bad)",          { XX } },
5618     { "(bad)",          { XX } },
5619     { "(bad)",          { XX } },
5620     { "(bad)",          { XX } },
5621     { "(bad)",          { XX } },
5622     /* 78 */
5623     { "(bad)",          { XX } },
5624     { "(bad)",          { XX } },
5625     { "(bad)",          { XX } },
5626     { "(bad)",          { XX } },
5627     { "(bad)",          { XX } },
5628     { "(bad)",          { XX } },
5629     { "(bad)",          { XX } },
5630     { "(bad)",          { XX } },
5631     /* 80 */
5632     { "(bad)",          { XX } },
5633     { "(bad)",          { XX } },
5634     { "(bad)",          { XX } },
5635     { "(bad)",          { XX } },
5636     { "(bad)",          { XX } },
5637     { "(bad)",          { XX } },
5638     { "(bad)",          { XX } },
5639     { "(bad)",          { XX } },
5640     /* 88 */
5641     { "(bad)",          { XX } },
5642     { "(bad)",          { XX } },
5643     { "(bad)",          { XX } },
5644     { "(bad)",          { XX } },
5645     { "(bad)",          { XX } },
5646     { "(bad)",          { XX } },
5647     { "(bad)",          { XX } },
5648     { "(bad)",          { XX } },
5649     /* 90 */
5650     { "(bad)",          { XX } },
5651     { "(bad)",          { XX } },
5652     { "(bad)",          { XX } },
5653     { "(bad)",          { XX } },
5654     { "(bad)",          { XX } },
5655     { "(bad)",          { XX } },
5656     { "(bad)",          { XX } },
5657     { "(bad)",          { XX } },
5658     /* 98 */
5659     { "(bad)",          { XX } },
5660     { "(bad)",          { XX } },
5661     { "(bad)",          { XX } },
5662     { "(bad)",          { XX } },
5663     { "(bad)",          { XX } },
5664     { "(bad)",          { XX } },
5665     { "(bad)",          { XX } },
5666     { "(bad)",          { XX } },
5667     /* a0 */
5668     { "(bad)",          { XX } },
5669     { "(bad)",          { XX } },
5670     { "(bad)",          { XX } },
5671     { "(bad)",          { XX } },
5672     { "(bad)",          { XX } },
5673     { "(bad)",          { XX } },
5674     { "(bad)",          { XX } },
5675     { "(bad)",          { XX } },
5676     /* a8 */
5677     { "(bad)",          { XX } },
5678     { "(bad)",          { XX } },
5679     { "(bad)",          { XX } },
5680     { "(bad)",          { XX } },
5681     { "(bad)",          { XX } },
5682     { "(bad)",          { XX } },
5683     { "(bad)",          { XX } },
5684     { "(bad)",          { XX } },
5685     /* b0 */
5686     { "(bad)",          { XX } },
5687     { "(bad)",          { XX } },
5688     { "(bad)",          { XX } },
5689     { "(bad)",          { XX } },
5690     { "(bad)",          { XX } },
5691     { "(bad)",          { XX } },
5692     { "(bad)",          { XX } },
5693     { "(bad)",          { XX } },
5694     /* b8 */
5695     { "(bad)",          { XX } },
5696     { "(bad)",          { XX } },
5697     { "(bad)",          { XX } },
5698     { "(bad)",          { XX } },
5699     { "(bad)",          { XX } },
5700     { "(bad)",          { XX } },
5701     { "(bad)",          { XX } },
5702     { "(bad)",          { XX } },
5703     /* c0 */
5704     { "(bad)",          { XX } },
5705     { "(bad)",          { XX } },
5706     { "(bad)",          { XX } },
5707     { "(bad)",          { XX } },
5708     { "(bad)",          { XX } },
5709     { "(bad)",          { XX } },
5710     { "(bad)",          { XX } },
5711     { "(bad)",          { XX } },
5712     /* c8 */
5713     { "(bad)",          { XX } },
5714     { "(bad)",          { XX } },
5715     { "(bad)",          { XX } },
5716     { "(bad)",          { XX } },
5717     { "(bad)",          { XX } },
5718     { "(bad)",          { XX } },
5719     { "(bad)",          { XX } },
5720     { "(bad)",          { XX } },
5721     /* d0 */
5722     { "(bad)",          { XX } },
5723     { "(bad)",          { XX } },
5724     { "(bad)",          { XX } },
5725     { "(bad)",          { XX } },
5726     { "(bad)",          { XX } },
5727     { "(bad)",          { XX } },
5728     { "(bad)",          { XX } },
5729     { "(bad)",          { XX } },
5730     /* d8 */
5731     { "(bad)",          { XX } },
5732     { "(bad)",          { XX } },
5733     { "(bad)",          { XX } },
5734     { "(bad)",          { XX } },
5735     { "(bad)",          { XX } },
5736     { "(bad)",          { XX } },
5737     { "(bad)",          { XX } },
5738     { "(bad)",          { XX } },
5739     /* e0 */
5740     { "(bad)",          { XX } },
5741     { "(bad)",          { XX } },
5742     { "(bad)",          { XX } },
5743     { "(bad)",          { XX } },
5744     { "(bad)",          { XX } },
5745     { "(bad)",          { XX } },
5746     { "(bad)",          { XX } },
5747     { "(bad)",          { XX } },
5748     /* e8 */
5749     { "(bad)",          { XX } },
5750     { "(bad)",          { XX } },
5751     { "(bad)",          { XX } },
5752     { "(bad)",          { XX } },
5753     { "(bad)",          { XX } },
5754     { "(bad)",          { XX } },
5755     { "(bad)",          { XX } },
5756     { "(bad)",          { XX } },
5757     /* f0 */
5758     { "(bad)",          { XX } },
5759     { "(bad)",          { XX } },
5760     { "(bad)",          { XX } },
5761     { "(bad)",          { XX } },
5762     { "(bad)",          { XX } },
5763     { "(bad)",          { XX } },
5764     { "(bad)",          { XX } },
5765     { "(bad)",          { XX } },
5766     /* f8 */
5767     { "(bad)",          { XX } },
5768     { "(bad)",          { XX } },
5769     { "(bad)",          { XX } },
5770     { "(bad)",          { XX } },
5771     { "(bad)",          { XX } },
5772     { "(bad)",          { XX } },
5773     { "(bad)",          { XX } },
5774     { "(bad)",          { XX } },
5775   },
5776   /* THREE_BYTE_0F38 */
5777   {
5778     /* 00 */
5779     { "pshufb",         { MX, EM } },
5780     { "phaddw",         { MX, EM } },
5781     { "phaddd",         { MX, EM } },
5782     { "phaddsw",        { MX, EM } },
5783     { "pmaddubsw",      { MX, EM } },
5784     { "phsubw",         { MX, EM } },
5785     { "phsubd",         { MX, EM } },
5786     { "phsubsw",        { MX, EM } },
5787     /* 08 */
5788     { "psignb",         { MX, EM } },
5789     { "psignw",         { MX, EM } },
5790     { "psignd",         { MX, EM } },
5791     { "pmulhrsw",       { MX, EM } },
5792     { "(bad)",          { XX } },
5793     { "(bad)",          { XX } },
5794     { "(bad)",          { XX } },
5795     { "(bad)",          { XX } },
5796     /* 10 */
5797     { PREFIX_TABLE (PREFIX_0F3810) },
5798     { "(bad)",          { XX } },
5799     { "(bad)",          { XX } },
5800     { "(bad)",          { XX } },
5801     { PREFIX_TABLE (PREFIX_0F3814) },
5802     { PREFIX_TABLE (PREFIX_0F3815) },
5803     { "(bad)",          { XX } },
5804     { PREFIX_TABLE (PREFIX_0F3817) },
5805     /* 18 */
5806     { "(bad)",          { XX } },
5807     { "(bad)",          { XX } },
5808     { "(bad)",          { XX } },
5809     { "(bad)",          { XX } },
5810     { "pabsb",          { MX, EM } },
5811     { "pabsw",          { MX, EM } },
5812     { "pabsd",          { MX, EM } },
5813     { "(bad)",          { XX } },
5814     /* 20 */
5815     { PREFIX_TABLE (PREFIX_0F3820) },
5816     { PREFIX_TABLE (PREFIX_0F3821) },
5817     { PREFIX_TABLE (PREFIX_0F3822) },
5818     { PREFIX_TABLE (PREFIX_0F3823) },
5819     { PREFIX_TABLE (PREFIX_0F3824) },
5820     { PREFIX_TABLE (PREFIX_0F3825) },
5821     { "(bad)",          { XX } },
5822     { "(bad)",          { XX } },
5823     /* 28 */
5824     { PREFIX_TABLE (PREFIX_0F3828) },
5825     { PREFIX_TABLE (PREFIX_0F3829) },
5826     { PREFIX_TABLE (PREFIX_0F382A) },
5827     { PREFIX_TABLE (PREFIX_0F382B) },
5828     { "(bad)",          { XX } },
5829     { "(bad)",          { XX } },
5830     { "(bad)",          { XX } },
5831     { "(bad)",          { XX } },
5832     /* 30 */
5833     { PREFIX_TABLE (PREFIX_0F3830) },
5834     { PREFIX_TABLE (PREFIX_0F3831) },
5835     { PREFIX_TABLE (PREFIX_0F3832) },
5836     { PREFIX_TABLE (PREFIX_0F3833) },
5837     { PREFIX_TABLE (PREFIX_0F3834) },
5838     { PREFIX_TABLE (PREFIX_0F3835) },
5839     { "(bad)",          { XX } },
5840     { PREFIX_TABLE (PREFIX_0F3837) },
5841     /* 38 */
5842     { PREFIX_TABLE (PREFIX_0F3838) },
5843     { PREFIX_TABLE (PREFIX_0F3839) },
5844     { PREFIX_TABLE (PREFIX_0F383A) },
5845     { PREFIX_TABLE (PREFIX_0F383B) },
5846     { PREFIX_TABLE (PREFIX_0F383C) },
5847     { PREFIX_TABLE (PREFIX_0F383D) },
5848     { PREFIX_TABLE (PREFIX_0F383E) },
5849     { PREFIX_TABLE (PREFIX_0F383F) },
5850     /* 40 */
5851     { PREFIX_TABLE (PREFIX_0F3840) },
5852     { PREFIX_TABLE (PREFIX_0F3841) },
5853     { "(bad)",          { XX } },
5854     { "(bad)",          { XX } },
5855     { "(bad)",          { XX } },
5856     { "(bad)",          { XX } },
5857     { "(bad)",          { XX } },
5858     { "(bad)",          { XX } },
5859     /* 48 */
5860     { "(bad)",          { XX } },
5861     { "(bad)",          { XX } },
5862     { "(bad)",          { XX } },
5863     { "(bad)",          { XX } },
5864     { "(bad)",          { XX } },
5865     { "(bad)",          { XX } },
5866     { "(bad)",          { XX } },
5867     { "(bad)",          { XX } },
5868     /* 50 */
5869     { "(bad)",          { XX } },
5870     { "(bad)",          { XX } },
5871     { "(bad)",          { XX } },
5872     { "(bad)",          { XX } },
5873     { "(bad)",          { XX } },
5874     { "(bad)",          { XX } },
5875     { "(bad)",          { XX } },
5876     { "(bad)",          { XX } },
5877     /* 58 */
5878     { "(bad)",          { XX } },
5879     { "(bad)",          { XX } },
5880     { "(bad)",          { XX } },
5881     { "(bad)",          { XX } },
5882     { "(bad)",          { XX } },
5883     { "(bad)",          { XX } },
5884     { "(bad)",          { XX } },
5885     { "(bad)",          { XX } },
5886     /* 60 */
5887     { "(bad)",          { XX } },
5888     { "(bad)",          { XX } },
5889     { "(bad)",          { XX } },
5890     { "(bad)",          { XX } },
5891     { "(bad)",          { XX } },
5892     { "(bad)",          { XX } },
5893     { "(bad)",          { XX } },
5894     { "(bad)",          { XX } },
5895     /* 68 */
5896     { "(bad)",          { XX } },
5897     { "(bad)",          { XX } },
5898     { "(bad)",          { XX } },
5899     { "(bad)",          { XX } },
5900     { "(bad)",          { XX } },
5901     { "(bad)",          { XX } },
5902     { "(bad)",          { XX } },
5903     { "(bad)",          { XX } },
5904     /* 70 */
5905     { "(bad)",          { XX } },
5906     { "(bad)",          { XX } },
5907     { "(bad)",          { XX } },
5908     { "(bad)",          { XX } },
5909     { "(bad)",          { XX } },
5910     { "(bad)",          { XX } },
5911     { "(bad)",          { XX } },
5912     { "(bad)",          { XX } },
5913     /* 78 */
5914     { "(bad)",          { XX } },
5915     { "(bad)",          { XX } },
5916     { "(bad)",          { XX } },
5917     { "(bad)",          { XX } },
5918     { "(bad)",          { XX } },
5919     { "(bad)",          { XX } },
5920     { "(bad)",          { XX } },
5921     { "(bad)",          { XX } },
5922     /* 80 */
5923     { PREFIX_TABLE (PREFIX_0F3880) },
5924     { PREFIX_TABLE (PREFIX_0F3881) },
5925     { "(bad)",          { XX } },
5926     { "(bad)",          { XX } },
5927     { "(bad)",          { XX } },
5928     { "(bad)",          { XX } },
5929     { "(bad)",          { XX } },
5930     { "(bad)",          { XX } },
5931     /* 88 */
5932     { "(bad)",          { XX } },
5933     { "(bad)",          { XX } },
5934     { "(bad)",          { XX } },
5935     { "(bad)",          { XX } },
5936     { "(bad)",          { XX } },
5937     { "(bad)",          { XX } },
5938     { "(bad)",          { XX } },
5939     { "(bad)",          { XX } },
5940     /* 90 */
5941     { "(bad)",          { XX } },
5942     { "(bad)",          { XX } },
5943     { "(bad)",          { XX } },
5944     { "(bad)",          { XX } },
5945     { "(bad)",          { XX } },
5946     { "(bad)",          { XX } },
5947     { "(bad)",          { XX } },
5948     { "(bad)",          { XX } },
5949     /* 98 */
5950     { "(bad)",          { XX } },
5951     { "(bad)",          { XX } },
5952     { "(bad)",          { XX } },
5953     { "(bad)",          { XX } },
5954     { "(bad)",          { XX } },
5955     { "(bad)",          { XX } },
5956     { "(bad)",          { XX } },
5957     { "(bad)",          { XX } },
5958     /* a0 */
5959     { "(bad)",          { XX } },
5960     { "(bad)",          { XX } },
5961     { "(bad)",          { XX } },
5962     { "(bad)",          { XX } },
5963     { "(bad)",          { XX } },
5964     { "(bad)",          { XX } },
5965     { "(bad)",          { XX } },
5966     { "(bad)",          { XX } },
5967     /* a8 */
5968     { "(bad)",          { XX } },
5969     { "(bad)",          { XX } },
5970     { "(bad)",          { XX } },
5971     { "(bad)",          { XX } },
5972     { "(bad)",          { XX } },
5973     { "(bad)",          { XX } },
5974     { "(bad)",          { XX } },
5975     { "(bad)",          { XX } },
5976     /* b0 */
5977     { "(bad)",          { XX } },
5978     { "(bad)",          { XX } },
5979     { "(bad)",          { XX } },
5980     { "(bad)",          { XX } },
5981     { "(bad)",          { XX } },
5982     { "(bad)",          { XX } },
5983     { "(bad)",          { XX } },
5984     { "(bad)",          { XX } },
5985     /* b8 */
5986     { "(bad)",          { XX } },
5987     { "(bad)",          { XX } },
5988     { "(bad)",          { XX } },
5989     { "(bad)",          { XX } },
5990     { "(bad)",          { XX } },
5991     { "(bad)",          { XX } },
5992     { "(bad)",          { XX } },
5993     { "(bad)",          { XX } },
5994     /* c0 */
5995     { "(bad)",          { XX } },
5996     { "(bad)",          { XX } },
5997     { "(bad)",          { XX } },
5998     { "(bad)",          { XX } },
5999     { "(bad)",          { XX } },
6000     { "(bad)",          { XX } },
6001     { "(bad)",          { XX } },
6002     { "(bad)",          { XX } },
6003     /* c8 */
6004     { "(bad)",          { XX } },
6005     { "(bad)",          { XX } },
6006     { "(bad)",          { XX } },
6007     { "(bad)",          { XX } },
6008     { "(bad)",          { XX } },
6009     { "(bad)",          { XX } },
6010     { "(bad)",          { XX } },
6011     { "(bad)",          { XX } },
6012     /* d0 */
6013     { "(bad)",          { XX } },
6014     { "(bad)",          { XX } },
6015     { "(bad)",          { XX } },
6016     { "(bad)",          { XX } },
6017     { "(bad)",          { XX } },
6018     { "(bad)",          { XX } },
6019     { "(bad)",          { XX } },
6020     { "(bad)",          { XX } },
6021     /* d8 */
6022     { "(bad)",          { XX } },
6023     { "(bad)",          { XX } },
6024     { "(bad)",          { XX } },
6025     { PREFIX_TABLE (PREFIX_0F38DB) },
6026     { PREFIX_TABLE (PREFIX_0F38DC) },
6027     { PREFIX_TABLE (PREFIX_0F38DD) },
6028     { PREFIX_TABLE (PREFIX_0F38DE) },
6029     { PREFIX_TABLE (PREFIX_0F38DF) },
6030     /* e0 */
6031     { "(bad)",          { XX } },
6032     { "(bad)",          { XX } },
6033     { "(bad)",          { XX } },
6034     { "(bad)",          { XX } },
6035     { "(bad)",          { XX } },
6036     { "(bad)",          { XX } },
6037     { "(bad)",          { XX } },
6038     { "(bad)",          { XX } },
6039     /* e8 */
6040     { "(bad)",          { XX } },
6041     { "(bad)",          { XX } },
6042     { "(bad)",          { XX } },
6043     { "(bad)",          { XX } },
6044     { "(bad)",          { XX } },
6045     { "(bad)",          { XX } },
6046     { "(bad)",          { XX } },
6047     { "(bad)",          { XX } },
6048     /* f0 */
6049     { PREFIX_TABLE (PREFIX_0F38F0) },
6050     { PREFIX_TABLE (PREFIX_0F38F1) },
6051     { "(bad)",          { XX } },
6052     { "(bad)",          { XX } },
6053     { "(bad)",          { XX } },
6054     { "(bad)",          { XX } },
6055     { "(bad)",          { XX } },
6056     { "(bad)",          { XX } },
6057     /* f8 */
6058     { "(bad)",          { XX } },
6059     { "(bad)",          { XX } },
6060     { "(bad)",          { XX } },
6061     { "(bad)",          { XX } },
6062     { "(bad)",          { XX } },
6063     { "(bad)",          { XX } },
6064     { "(bad)",          { XX } },
6065     { "(bad)",          { XX } },
6066   },
6067   /* THREE_BYTE_0F3A */
6068   {
6069     /* 00 */
6070     { "(bad)",          { XX } },
6071     { "(bad)",          { XX } },
6072     { "(bad)",          { XX } },
6073     { "(bad)",          { XX } },
6074     { "(bad)",          { XX } },
6075     { "(bad)",          { XX } },
6076     { "(bad)",          { XX } },
6077     { "(bad)",          { XX } },
6078     /* 08 */
6079     { PREFIX_TABLE (PREFIX_0F3A08) },
6080     { PREFIX_TABLE (PREFIX_0F3A09) },
6081     { PREFIX_TABLE (PREFIX_0F3A0A) },
6082     { PREFIX_TABLE (PREFIX_0F3A0B) },
6083     { PREFIX_TABLE (PREFIX_0F3A0C) },
6084     { PREFIX_TABLE (PREFIX_0F3A0D) },
6085     { PREFIX_TABLE (PREFIX_0F3A0E) },
6086     { "palignr",        { MX, EM, Ib } },
6087     /* 10 */
6088     { "(bad)",          { XX } },
6089     { "(bad)",          { XX } },
6090     { "(bad)",          { XX } },
6091     { "(bad)",          { XX } },
6092     { PREFIX_TABLE (PREFIX_0F3A14) },
6093     { PREFIX_TABLE (PREFIX_0F3A15) },
6094     { PREFIX_TABLE (PREFIX_0F3A16) },
6095     { PREFIX_TABLE (PREFIX_0F3A17) },
6096     /* 18 */
6097     { "(bad)",          { XX } },
6098     { "(bad)",          { XX } },
6099     { "(bad)",          { XX } },
6100     { "(bad)",          { XX } },
6101     { "(bad)",          { XX } },
6102     { "(bad)",          { XX } },
6103     { "(bad)",          { XX } },
6104     { "(bad)",          { XX } },
6105     /* 20 */
6106     { PREFIX_TABLE (PREFIX_0F3A20) },
6107     { PREFIX_TABLE (PREFIX_0F3A21) },
6108     { PREFIX_TABLE (PREFIX_0F3A22) },
6109     { "(bad)",          { XX } },
6110     { "(bad)",          { XX } },
6111     { "(bad)",          { XX } },
6112     { "(bad)",          { XX } },
6113     { "(bad)",          { XX } },
6114     /* 28 */
6115     { "(bad)",          { XX } },
6116     { "(bad)",          { XX } },
6117     { "(bad)",          { XX } },
6118     { "(bad)",          { XX } },
6119     { "(bad)",          { XX } },
6120     { "(bad)",          { XX } },
6121     { "(bad)",          { XX } },
6122     { "(bad)",          { XX } },
6123     /* 30 */
6124     { "(bad)",          { XX } },
6125     { "(bad)",          { XX } },
6126     { "(bad)",          { XX } },
6127     { "(bad)",          { XX } },
6128     { "(bad)",          { XX } },
6129     { "(bad)",          { XX } },
6130     { "(bad)",          { XX } },
6131     { "(bad)",          { XX } },
6132     /* 38 */
6133     { "(bad)",          { XX } },
6134     { "(bad)",          { XX } },
6135     { "(bad)",          { XX } },
6136     { "(bad)",          { XX } },
6137     { "(bad)",          { XX } },
6138     { "(bad)",          { XX } },
6139     { "(bad)",          { XX } },
6140     { "(bad)",          { XX } },
6141     /* 40 */
6142     { PREFIX_TABLE (PREFIX_0F3A40) },
6143     { PREFIX_TABLE (PREFIX_0F3A41) },
6144     { PREFIX_TABLE (PREFIX_0F3A42) },
6145     { "(bad)",          { XX } },
6146     { PREFIX_TABLE (PREFIX_0F3A44) },
6147     { "(bad)",          { XX } },
6148     { "(bad)",          { XX } },
6149     { "(bad)",          { XX } },
6150     /* 48 */
6151     { "(bad)",          { XX } },
6152     { "(bad)",          { XX } },
6153     { "(bad)",          { XX } },
6154     { "(bad)",          { XX } },
6155     { "(bad)",          { XX } },
6156     { "(bad)",          { XX } },
6157     { "(bad)",          { XX } },
6158     { "(bad)",          { XX } },
6159     /* 50 */
6160     { "(bad)",          { XX } },
6161     { "(bad)",          { XX } },
6162     { "(bad)",          { XX } },
6163     { "(bad)",          { XX } },
6164     { "(bad)",          { XX } },
6165     { "(bad)",          { XX } },
6166     { "(bad)",          { XX } },
6167     { "(bad)",          { XX } },
6168     /* 58 */
6169     { "(bad)",          { XX } },
6170     { "(bad)",          { XX } },
6171     { "(bad)",          { XX } },
6172     { "(bad)",          { XX } },
6173     { "(bad)",          { XX } },
6174     { "(bad)",          { XX } },
6175     { "(bad)",          { XX } },
6176     { "(bad)",          { XX } },
6177     /* 60 */
6178     { PREFIX_TABLE (PREFIX_0F3A60) },
6179     { PREFIX_TABLE (PREFIX_0F3A61) },
6180     { PREFIX_TABLE (PREFIX_0F3A62) },
6181     { PREFIX_TABLE (PREFIX_0F3A63) },
6182     { "(bad)",          { XX } },
6183     { "(bad)",          { XX } },
6184     { "(bad)",          { XX } },
6185     { "(bad)",          { XX } },
6186     /* 68 */
6187     { "(bad)",          { XX } },
6188     { "(bad)",          { XX } },
6189     { "(bad)",          { XX } },
6190     { "(bad)",          { XX } },
6191     { "(bad)",          { XX } },
6192     { "(bad)",          { XX } },
6193     { "(bad)",          { XX } },
6194     { "(bad)",          { XX } },
6195     /* 70 */
6196     { "(bad)",          { XX } },
6197     { "(bad)",          { XX } },
6198     { "(bad)",          { XX } },
6199     { "(bad)",          { XX } },
6200     { "(bad)",          { XX } },
6201     { "(bad)",          { XX } },
6202     { "(bad)",          { XX } },
6203     { "(bad)",          { XX } },
6204     /* 78 */
6205     { "(bad)",          { XX } },
6206     { "(bad)",          { XX } },
6207     { "(bad)",          { XX } },
6208     { "(bad)",          { XX } },
6209     { "(bad)",          { XX } },
6210     { "(bad)",          { XX } },
6211     { "(bad)",          { XX } },
6212     { "(bad)",          { XX } },
6213     /* 80 */
6214     { "(bad)",          { XX } },
6215     { "(bad)",          { XX } },
6216     { "(bad)",          { XX } },
6217     { "(bad)",          { XX } },
6218     { "(bad)",          { XX } },
6219     { "(bad)",          { XX } },
6220     { "(bad)",          { XX } },
6221     { "(bad)",          { XX } },
6222     /* 88 */
6223     { "(bad)",          { XX } },
6224     { "(bad)",          { XX } },
6225     { "(bad)",          { XX } },
6226     { "(bad)",          { XX } },
6227     { "(bad)",          { XX } },
6228     { "(bad)",          { XX } },
6229     { "(bad)",          { XX } },
6230     { "(bad)",          { XX } },
6231     /* 90 */
6232     { "(bad)",          { XX } },
6233     { "(bad)",          { XX } },
6234     { "(bad)",          { XX } },
6235     { "(bad)",          { XX } },
6236     { "(bad)",          { XX } },
6237     { "(bad)",          { XX } },
6238     { "(bad)",          { XX } },
6239     { "(bad)",          { XX } },
6240     /* 98 */
6241     { "(bad)",          { XX } },
6242     { "(bad)",          { XX } },
6243     { "(bad)",          { XX } },
6244     { "(bad)",          { XX } },
6245     { "(bad)",          { XX } },
6246     { "(bad)",          { XX } },
6247     { "(bad)",          { XX } },
6248     { "(bad)",          { XX } },
6249     /* a0 */
6250     { "(bad)",          { XX } },
6251     { "(bad)",          { XX } },
6252     { "(bad)",          { XX } },
6253     { "(bad)",          { XX } },
6254     { "(bad)",          { XX } },
6255     { "(bad)",          { XX } },
6256     { "(bad)",          { XX } },
6257     { "(bad)",          { XX } },
6258     /* a8 */
6259     { "(bad)",          { XX } },
6260     { "(bad)",          { XX } },
6261     { "(bad)",          { XX } },
6262     { "(bad)",          { XX } },
6263     { "(bad)",          { XX } },
6264     { "(bad)",          { XX } },
6265     { "(bad)",          { XX } },
6266     { "(bad)",          { XX } },
6267     /* b0 */
6268     { "(bad)",          { XX } },
6269     { "(bad)",          { XX } },
6270     { "(bad)",          { XX } },
6271     { "(bad)",          { XX } },
6272     { "(bad)",          { XX } },
6273     { "(bad)",          { XX } },
6274     { "(bad)",          { XX } },
6275     { "(bad)",          { XX } },
6276     /* b8 */
6277     { "(bad)",          { XX } },
6278     { "(bad)",          { XX } },
6279     { "(bad)",          { XX } },
6280     { "(bad)",          { XX } },
6281     { "(bad)",          { XX } },
6282     { "(bad)",          { XX } },
6283     { "(bad)",          { XX } },
6284     { "(bad)",          { XX } },
6285     /* c0 */
6286     { "(bad)",          { XX } },
6287     { "(bad)",          { XX } },
6288     { "(bad)",          { XX } },
6289     { "(bad)",          { XX } },
6290     { "(bad)",          { XX } },
6291     { "(bad)",          { XX } },
6292     { "(bad)",          { XX } },
6293     { "(bad)",          { XX } },
6294     /* c8 */
6295     { "(bad)",          { XX } },
6296     { "(bad)",          { XX } },
6297     { "(bad)",          { XX } },
6298     { "(bad)",          { XX } },
6299     { "(bad)",          { XX } },
6300     { "(bad)",          { XX } },
6301     { "(bad)",          { XX } },
6302     { "(bad)",          { XX } },
6303     /* d0 */
6304     { "(bad)",          { XX } },
6305     { "(bad)",          { XX } },
6306     { "(bad)",          { XX } },
6307     { "(bad)",          { XX } },
6308     { "(bad)",          { XX } },
6309     { "(bad)",          { XX } },
6310     { "(bad)",          { XX } },
6311     { "(bad)",          { XX } },
6312     /* d8 */
6313     { "(bad)",          { XX } },
6314     { "(bad)",          { XX } },
6315     { "(bad)",          { XX } },
6316     { "(bad)",          { XX } },
6317     { "(bad)",          { XX } },
6318     { "(bad)",          { XX } },
6319     { "(bad)",          { XX } },
6320     { PREFIX_TABLE (PREFIX_0F3ADF) },
6321     /* e0 */
6322     { "(bad)",          { XX } },
6323     { "(bad)",          { XX } },
6324     { "(bad)",          { XX } },
6325     { "(bad)",          { XX } },
6326     { "(bad)",          { XX } },
6327     { "(bad)",          { XX } },
6328     { "(bad)",          { XX } },
6329     { "(bad)",          { XX } },
6330     /* e8 */
6331     { "(bad)",          { XX } },
6332     { "(bad)",          { XX } },
6333     { "(bad)",          { XX } },
6334     { "(bad)",          { XX } },
6335     { "(bad)",          { XX } },
6336     { "(bad)",          { XX } },
6337     { "(bad)",          { XX } },
6338     { "(bad)",          { XX } },
6339     /* f0 */
6340     { "(bad)",          { XX } },
6341     { "(bad)",          { XX } },
6342     { "(bad)",          { XX } },
6343     { "(bad)",          { XX } },
6344     { "(bad)",          { XX } },
6345     { "(bad)",          { XX } },
6346     { "(bad)",          { XX } },
6347     { "(bad)",          { XX } },
6348     /* f8 */
6349     { "(bad)",          { XX } },
6350     { "(bad)",          { XX } },
6351     { "(bad)",          { XX } },
6352     { "(bad)",          { XX } },
6353     { "(bad)",          { XX } },
6354     { "(bad)",          { XX } },
6355     { "(bad)",          { XX } },
6356     { "(bad)",          { XX } },
6357   },
6358   /* THREE_BYTE_0F7A */
6359   {
6360     /* 00 */
6361     { "(bad)",          { XX } },
6362     { "(bad)",          { XX } },
6363     { "(bad)",          { XX } },
6364     { "(bad)",          { XX } },
6365     { "(bad)",          { XX } },
6366     { "(bad)",          { XX } },
6367     { "(bad)",          { XX } },
6368     { "(bad)",          { XX } },
6369     /* 08 */
6370     { "(bad)",          { XX } },
6371     { "(bad)",          { XX } },
6372     { "(bad)",          { XX } },
6373     { "(bad)",          { XX } },
6374     { "(bad)",          { XX } },
6375     { "(bad)",          { XX } },
6376     { "(bad)",          { XX } },
6377     { "(bad)",          { XX } },
6378     /* 10 */
6379     { "frczps",         { XM, EXq } },
6380     { "frczpd",         { XM, EXq } },
6381     { "frczss",         { XM, EXq } },
6382     { "frczsd",         { XM, EXq } },
6383     { "(bad)",          { XX } },
6384     { "(bad)",          { XX } },
6385     { "(bad)",          { XX } },
6386     { "(bad)",          { XX } },
6387     /* 18 */
6388     { "(bad)",          { XX } },
6389     { "(bad)",          { XX } },
6390     { "(bad)",          { XX } },
6391     { "(bad)",          { XX } },
6392     { "(bad)",          { XX } },
6393     { "(bad)",          { XX } },
6394     { "(bad)",          { XX } },
6395     { "(bad)",          { XX } },
6396     /* 20 */
6397     { "ptest",          { XX } },
6398     { "(bad)",          { XX } },
6399     { "(bad)",          { XX } },
6400     { "(bad)",          { XX } },
6401     { "(bad)",          { XX } },
6402     { "(bad)",          { XX } },
6403     { "(bad)",          { XX } },
6404     { "(bad)",          { XX } },
6405     /* 28 */
6406     { "(bad)",          { XX } },
6407     { "(bad)",          { XX } },
6408     { "(bad)",          { XX } },
6409     { "(bad)",          { XX } },
6410     { "(bad)",          { XX } },
6411     { "(bad)",          { XX } },
6412     { "(bad)",          { XX } },
6413     { "(bad)",          { XX } },
6414     /* 30 */
6415     { "cvtph2ps",       { XM, EXd } },
6416     { "cvtps2ph",       { EXd, XM } },
6417     { "(bad)",          { XX } },
6418     { "(bad)",          { XX } },
6419     { "(bad)",          { XX } },
6420     { "(bad)",          { XX } },
6421     { "(bad)",          { XX } },
6422     { "(bad)",          { XX } },
6423     /* 38 */
6424     { "(bad)",          { XX } },
6425     { "(bad)",          { XX } },
6426     { "(bad)",          { XX } },
6427     { "(bad)",          { XX } },
6428     { "(bad)",          { XX } },
6429     { "(bad)",          { XX } },
6430     { "(bad)",          { XX } },
6431     { "(bad)",          { XX } },
6432     /* 40 */
6433     { "(bad)",          { XX } },
6434     { "phaddbw",        { XM, EXq } },
6435     { "phaddbd",        { XM, EXq } },
6436     { "phaddbq",        { XM, EXq } },
6437     { "(bad)",          { XX } },
6438     { "(bad)",          { XX } },
6439     { "phaddwd",        { XM, EXq } },
6440     { "phaddwq",        { XM, EXq } },
6441     /* 48 */
6442     { "(bad)",          { XX } },
6443     { "(bad)",          { XX } },
6444     { "(bad)",          { XX } },
6445     { "phadddq",        { XM, EXq } },
6446     { "(bad)",          { XX } },
6447     { "(bad)",          { XX } },
6448     { "(bad)",          { XX } },
6449     { "(bad)",          { XX } },
6450     /* 50 */
6451     { "(bad)",          { XX } },
6452     { "phaddubw",       { XM, EXq } },
6453     { "phaddubd",       { XM, EXq } },
6454     { "phaddubq",       { XM, EXq } },
6455     { "(bad)",          { XX } },
6456     { "(bad)",          { XX } },
6457     { "phadduwd",       { XM, EXq } },
6458     { "phadduwq",       { XM, EXq } },
6459     /* 58 */
6460     { "(bad)",          { XX } },
6461     { "(bad)",          { XX } },
6462     { "(bad)",          { XX } },
6463     { "phaddudq",       { XM, EXq } },
6464     { "(bad)",          { XX } },
6465     { "(bad)",          { XX } },
6466     { "(bad)",          { XX } },
6467     { "(bad)",          { XX } },
6468     /* 60 */
6469     { "(bad)",          { XX } },
6470     { "phsubbw",        { XM, EXq } },
6471     { "phsubbd",        { XM, EXq } },
6472     { "phsubbq",        { XM, EXq } },
6473     { "(bad)",          { XX } },
6474     { "(bad)",          { XX } },
6475     { "(bad)",          { XX } },
6476     { "(bad)",          { XX } },
6477     /* 68 */
6478     { "(bad)",          { XX } },
6479     { "(bad)",          { XX } },
6480     { "(bad)",          { XX } },
6481     { "(bad)",          { XX } },
6482     { "(bad)",          { XX } },
6483     { "(bad)",          { XX } },
6484     { "(bad)",          { XX } },
6485     { "(bad)",          { XX } },
6486     /* 70 */
6487     { "(bad)",          { XX } },
6488     { "(bad)",          { XX } },
6489     { "(bad)",          { XX } },
6490     { "(bad)",          { XX } },
6491     { "(bad)",          { XX } },
6492     { "(bad)",          { XX } },
6493     { "(bad)",          { XX } },
6494     { "(bad)",          { XX } },
6495     /* 78 */
6496     { "(bad)",          { XX } },
6497     { "(bad)",          { XX } },
6498     { "(bad)",          { XX } },
6499     { "(bad)",          { XX } },
6500     { "(bad)",          { XX } },
6501     { "(bad)",          { XX } },
6502     { "(bad)",          { XX } },
6503     { "(bad)",          { XX } },
6504     /* 80 */
6505     { "(bad)",          { XX } },
6506     { "(bad)",          { XX } },
6507     { "(bad)",          { XX } },
6508     { "(bad)",          { XX } },
6509     { "(bad)",          { XX } },
6510     { "(bad)",          { XX } },
6511     { "(bad)",          { XX } },
6512     { "(bad)",          { XX } },
6513     /* 88 */
6514     { "(bad)",          { XX } },
6515     { "(bad)",          { XX } },
6516     { "(bad)",          { XX } },
6517     { "(bad)",          { XX } },
6518     { "(bad)",          { XX } },
6519     { "(bad)",          { XX } },
6520     { "(bad)",          { XX } },
6521     { "(bad)",          { XX } },
6522     /* 90 */
6523     { "(bad)",          { XX } },
6524     { "(bad)",          { XX } },
6525     { "(bad)",          { XX } },
6526     { "(bad)",          { XX } },
6527     { "(bad)",          { XX } },
6528     { "(bad)",          { XX } },
6529     { "(bad)",          { XX } },
6530     { "(bad)",          { XX } },
6531     /* 98 */
6532     { "(bad)",          { XX } },
6533     { "(bad)",          { XX } },
6534     { "(bad)",          { XX } },
6535     { "(bad)",          { XX } },
6536     { "(bad)",          { XX } },
6537     { "(bad)",          { XX } },
6538     { "(bad)",          { XX } },
6539     { "(bad)",          { XX } },
6540     /* a0 */
6541     { "(bad)",          { XX } },
6542     { "(bad)",          { XX } },
6543     { "(bad)",          { XX } },
6544     { "(bad)",          { XX } },
6545     { "(bad)",          { XX } },
6546     { "(bad)",          { XX } },
6547     { "(bad)",          { XX } },
6548     { "(bad)",          { XX } },
6549     /* a8 */
6550     { "(bad)",          { XX } },
6551     { "(bad)",          { XX } },
6552     { "(bad)",          { XX } },
6553     { "(bad)",          { XX } },
6554     { "(bad)",          { XX } },
6555     { "(bad)",          { XX } },
6556     { "(bad)",          { XX } },
6557     { "(bad)",          { XX } },
6558     /* b0 */
6559     { "(bad)",          { XX } },
6560     { "(bad)",          { XX } },
6561     { "(bad)",          { XX } },
6562     { "(bad)",          { XX } },
6563     { "(bad)",          { XX } },
6564     { "(bad)",          { XX } },
6565     { "(bad)",          { XX } },
6566     { "(bad)",          { XX } },
6567     /* b8 */
6568     { "(bad)",          { XX } },
6569     { "(bad)",          { XX } },
6570     { "(bad)",          { XX } },
6571     { "(bad)",          { XX } },
6572     { "(bad)",          { XX } },
6573     { "(bad)",          { XX } },
6574     { "(bad)",          { XX } },
6575     { "(bad)",          { XX } },
6576     /* c0 */
6577     { "(bad)",          { XX } },
6578     { "(bad)",          { XX } },
6579     { "(bad)",          { XX } },
6580     { "(bad)",          { XX } },
6581     { "(bad)",          { XX } },
6582     { "(bad)",          { XX } },
6583     { "(bad)",          { XX } },
6584     { "(bad)",          { XX } },
6585     /* c8 */
6586     { "(bad)",          { XX } },
6587     { "(bad)",          { XX } },
6588     { "(bad)",          { XX } },
6589     { "(bad)",          { XX } },
6590     { "(bad)",          { XX } },
6591     { "(bad)",          { XX } },
6592     { "(bad)",          { XX } },
6593     { "(bad)",          { XX } },
6594     /* d0 */
6595     { "(bad)",          { XX } },
6596     { "(bad)",          { XX } },
6597     { "(bad)",          { XX } },
6598     { "(bad)",          { XX } },
6599     { "(bad)",          { XX } },
6600     { "(bad)",          { XX } },
6601     { "(bad)",          { XX } },
6602     { "(bad)",          { XX } },
6603     /* d8 */
6604     { "(bad)",          { XX } },
6605     { "(bad)",          { XX } },
6606     { "(bad)",          { XX } },
6607     { "(bad)",          { XX } },
6608     { "(bad)",          { XX } },
6609     { "(bad)",          { XX } },
6610     { "(bad)",          { XX } },
6611     { "(bad)",          { XX } },
6612     /* e0 */
6613     { "(bad)",          { XX } },
6614     { "(bad)",          { XX } },
6615     { "(bad)",          { XX } },
6616     { "(bad)",          { XX } },
6617     { "(bad)",          { XX } },
6618     { "(bad)",          { XX } },
6619     { "(bad)",          { XX } },
6620     { "(bad)",          { XX } },
6621     /* e8 */
6622     { "(bad)",          { XX } },
6623     { "(bad)",          { XX } },
6624     { "(bad)",          { XX } },
6625     { "(bad)",          { XX } },
6626     { "(bad)",          { XX } },
6627     { "(bad)",          { XX } },
6628     { "(bad)",          { XX } },
6629     { "(bad)",          { XX } },
6630     /* f0 */
6631     { "(bad)",          { XX } },
6632     { "(bad)",          { XX } },
6633     { "(bad)",          { XX } },
6634     { "(bad)",          { XX } },
6635     { "(bad)",          { XX } },
6636     { "(bad)",          { XX } },
6637     { "(bad)",          { XX } },
6638     { "(bad)",          { XX } },
6639     /* f8 */
6640     { "(bad)",          { XX } },
6641     { "(bad)",          { XX } },
6642     { "(bad)",          { XX } },
6643     { "(bad)",          { XX } },
6644     { "(bad)",          { XX } },
6645     { "(bad)",          { XX } },
6646     { "(bad)",          { XX } },
6647     { "(bad)",          { XX } },
6648   },
6649   /* THREE_BYTE_0F7B */
6650   {
6651     /* 00 */
6652     { "(bad)",          { XX } },
6653     { "(bad)",          { XX } },
6654     { "(bad)",          { XX } },
6655     { "(bad)",          { XX } },
6656     { "(bad)",          { XX } },
6657     { "(bad)",          { XX } },
6658     { "(bad)",          { XX } },
6659     { "(bad)",          { XX } },
6660     /* 08 */
6661     { "(bad)",          { XX } },
6662     { "(bad)",          { XX } },
6663     { "(bad)",          { XX } },
6664     { "(bad)",          { XX } },
6665     { "(bad)",          { XX } },
6666     { "(bad)",          { XX } },
6667     { "(bad)",          { XX } },
6668     { "(bad)",          { XX } },
6669     /* 10 */
6670     { "(bad)",          { XX } },
6671     { "(bad)",          { XX } },
6672     { "(bad)",          { XX } },
6673     { "(bad)",          { XX } },
6674     { "(bad)",          { XX } },
6675     { "(bad)",          { XX } },
6676     { "(bad)",          { XX } },
6677     { "(bad)",          { XX } },
6678     /* 18 */
6679     { "(bad)",          { XX } },
6680     { "(bad)",          { XX } },
6681     { "(bad)",          { XX } },
6682     { "(bad)",          { XX } },
6683     { "(bad)",          { XX } },
6684     { "(bad)",          { XX } },
6685     { "(bad)",          { XX } },
6686     { "(bad)",          { XX } },
6687     /* 20 */
6688     { "(bad)",          { XX } },
6689     { "(bad)",          { XX } },
6690     { "(bad)",          { XX } },
6691     { "(bad)",          { XX } },
6692     { "(bad)",          { XX } },
6693     { "(bad)",          { XX } },
6694     { "(bad)",          { XX } },
6695     { "(bad)",          { XX } },
6696     /* 28 */
6697     { "(bad)",          { XX } },
6698     { "(bad)",          { XX } },
6699     { "(bad)",          { XX } },
6700     { "(bad)",          { XX } },
6701     { "(bad)",          { XX } },
6702     { "(bad)",          { XX } },
6703     { "(bad)",          { XX } },
6704     { "(bad)",          { XX } },
6705     /* 30 */
6706     { "(bad)",          { XX } },
6707     { "(bad)",          { XX } },
6708     { "(bad)",          { XX } },
6709     { "(bad)",          { XX } },
6710     { "(bad)",          { XX } },
6711     { "(bad)",          { XX } },
6712     { "(bad)",          { XX } },
6713     { "(bad)",          { XX } },
6714     /* 38 */
6715     { "(bad)",          { XX } },
6716     { "(bad)",          { XX } },
6717     { "(bad)",          { XX } },
6718     { "(bad)",          { XX } },
6719     { "(bad)",          { XX } },
6720     { "(bad)",          { XX } },
6721     { "(bad)",          { XX } },
6722     { "(bad)",          { XX } },
6723     /* 40 */
6724     { "protb",          { XM, EXq, Ib } },
6725     { "protw",          { XM, EXq, Ib } },
6726     { "protd",          { XM, EXq, Ib } },
6727     { "protq",          { XM, EXq, Ib } },
6728     { "pshlb",          { XM, EXq, Ib } },
6729     { "pshlw",          { XM, EXq, Ib } },
6730     { "pshld",          { XM, EXq, Ib } },
6731     { "pshlq",          { XM, EXq, Ib } },
6732     /* 48 */
6733     { "pshab",          { XM, EXq, Ib } },
6734     { "pshaw",          { XM, EXq, Ib } },
6735     { "pshad",          { XM, EXq, Ib } },
6736     { "pshaq",          { XM, EXq, Ib } },
6737     { "(bad)",          { XX } },
6738     { "(bad)",          { XX } },
6739     { "(bad)",          { XX } },
6740     { "(bad)",          { XX } },
6741     /* 50 */
6742     { "(bad)",          { XX } },
6743     { "(bad)",          { XX } },
6744     { "(bad)",          { XX } },
6745     { "(bad)",          { XX } },
6746     { "(bad)",          { XX } },
6747     { "(bad)",          { XX } },
6748     { "(bad)",          { XX } },
6749     { "(bad)",          { XX } },
6750     /* 58 */
6751     { "(bad)",          { XX } },
6752     { "(bad)",          { XX } },
6753     { "(bad)",          { XX } },
6754     { "(bad)",          { XX } },
6755     { "(bad)",          { XX } },
6756     { "(bad)",          { XX } },
6757     { "(bad)",          { XX } },
6758     { "(bad)",          { XX } },
6759     /* 60 */
6760     { "(bad)",          { XX } },
6761     { "(bad)",          { XX } },
6762     { "(bad)",          { XX } },
6763     { "(bad)",          { XX } },
6764     { "(bad)",          { XX } },
6765     { "(bad)",          { XX } },
6766     { "(bad)",          { XX } },
6767     { "(bad)",          { XX } },
6768     /* 68 */
6769     { "(bad)",          { XX } },
6770     { "(bad)",          { XX } },
6771     { "(bad)",          { XX } },
6772     { "(bad)",          { XX } },
6773     { "(bad)",          { XX } },
6774     { "(bad)",          { XX } },
6775     { "(bad)",          { XX } },
6776     { "(bad)",          { XX } },
6777     /* 70 */
6778     { "(bad)",          { XX } },
6779     { "(bad)",          { XX } },
6780     { "(bad)",          { XX } },
6781     { "(bad)",          { XX } },
6782     { "(bad)",          { XX } },
6783     { "(bad)",          { XX } },
6784     { "(bad)",          { XX } },
6785     { "(bad)",          { XX } },
6786     /* 78 */
6787     { "(bad)",          { XX } },
6788     { "(bad)",          { XX } },
6789     { "(bad)",          { XX } },
6790     { "(bad)",          { XX } },
6791     { "(bad)",          { XX } },
6792     { "(bad)",          { XX } },
6793     { "(bad)",          { XX } },
6794     { "(bad)",          { XX } },
6795     /* 80 */
6796     { "(bad)",          { XX } },
6797     { "(bad)",          { XX } },
6798     { "(bad)",          { XX } },
6799     { "(bad)",          { XX } },
6800     { "(bad)",          { XX } },
6801     { "(bad)",          { XX } },
6802     { "(bad)",          { XX } },
6803     { "(bad)",          { XX } },
6804     /* 88 */
6805     { "(bad)",          { XX } },
6806     { "(bad)",          { XX } },
6807     { "(bad)",          { XX } },
6808     { "(bad)",          { XX } },
6809     { "(bad)",          { XX } },
6810     { "(bad)",          { XX } },
6811     { "(bad)",          { XX } },
6812     { "(bad)",          { XX } },
6813     /* 90 */
6814     { "(bad)",          { XX } },
6815     { "(bad)",          { XX } },
6816     { "(bad)",          { XX } },
6817     { "(bad)",          { XX } },
6818     { "(bad)",          { XX } },
6819     { "(bad)",          { XX } },
6820     { "(bad)",          { XX } },
6821     { "(bad)",          { XX } },
6822     /* 98 */
6823     { "(bad)",          { XX } },
6824     { "(bad)",          { XX } },
6825     { "(bad)",          { XX } },
6826     { "(bad)",          { XX } },
6827     { "(bad)",          { XX } },
6828     { "(bad)",          { XX } },
6829     { "(bad)",          { XX } },
6830     { "(bad)",          { XX } },
6831     /* a0 */
6832     { "(bad)",          { XX } },
6833     { "(bad)",          { XX } },
6834     { "(bad)",          { XX } },
6835     { "(bad)",          { XX } },
6836     { "(bad)",          { XX } },
6837     { "(bad)",          { XX } },
6838     { "(bad)",          { XX } },
6839     { "(bad)",          { XX } },
6840     /* a8 */
6841     { "(bad)",          { XX } },
6842     { "(bad)",          { XX } },
6843     { "(bad)",          { XX } },
6844     { "(bad)",          { XX } },
6845     { "(bad)",          { XX } },
6846     { "(bad)",          { XX } },
6847     { "(bad)",          { XX } },
6848     { "(bad)",          { XX } },
6849     /* b0 */
6850     { "(bad)",          { XX } },
6851     { "(bad)",          { XX } },
6852     { "(bad)",          { XX } },
6853     { "(bad)",          { XX } },
6854     { "(bad)",          { XX } },
6855     { "(bad)",          { XX } },
6856     { "(bad)",          { XX } },
6857     { "(bad)",          { XX } },
6858     /* b8 */
6859     { "(bad)",          { XX } },
6860     { "(bad)",          { XX } },
6861     { "(bad)",          { XX } },
6862     { "(bad)",          { XX } },
6863     { "(bad)",          { XX } },
6864     { "(bad)",          { XX } },
6865     { "(bad)",          { XX } },
6866     { "(bad)",          { XX } },
6867     /* c0 */
6868     { "(bad)",          { XX } },
6869     { "(bad)",          { XX } },
6870     { "(bad)",          { XX } },
6871     { "(bad)",          { XX } },
6872     { "(bad)",          { XX } },
6873     { "(bad)",          { XX } },
6874     { "(bad)",          { XX } },
6875     { "(bad)",          { XX } },
6876     /* c8 */
6877     { "(bad)",          { XX } },
6878     { "(bad)",          { XX } },
6879     { "(bad)",          { XX } },
6880     { "(bad)",          { XX } },
6881     { "(bad)",          { XX } },
6882     { "(bad)",          { XX } },
6883     { "(bad)",          { XX } },
6884     { "(bad)",          { XX } },
6885     /* d0 */
6886     { "(bad)",          { XX } },
6887     { "(bad)",          { XX } },
6888     { "(bad)",          { XX } },
6889     { "(bad)",          { XX } },
6890     { "(bad)",          { XX } },
6891     { "(bad)",          { XX } },
6892     { "(bad)",          { XX } },
6893     { "(bad)",          { XX } },
6894     /* d8 */
6895     { "(bad)",          { XX } },
6896     { "(bad)",          { XX } },
6897     { "(bad)",          { XX } },
6898     { "(bad)",          { XX } },
6899     { "(bad)",          { XX } },
6900     { "(bad)",          { XX } },
6901     { "(bad)",          { XX } },
6902     { "(bad)",          { XX } },
6903     /* e0 */
6904     { "(bad)",          { XX } },
6905     { "(bad)",          { XX } },
6906     { "(bad)",          { XX } },
6907     { "(bad)",          { XX } },
6908     { "(bad)",          { XX } },
6909     { "(bad)",          { XX } },
6910     { "(bad)",          { XX } },
6911     { "(bad)",          { XX } },
6912     /* e8 */
6913     { "(bad)",          { XX } },
6914     { "(bad)",          { XX } },
6915     { "(bad)",          { XX } },
6916     { "(bad)",          { XX } },
6917     { "(bad)",          { XX } },
6918     { "(bad)",          { XX } },
6919     { "(bad)",          { XX } },
6920     { "(bad)",          { XX } },
6921     /* f0 */
6922     { "(bad)",          { XX } },
6923     { "(bad)",          { XX } },
6924     { "(bad)",          { XX } },
6925     { "(bad)",          { XX } },
6926     { "(bad)",          { XX } },
6927     { "(bad)",          { XX } },
6928     { "(bad)",          { XX } },
6929     { "(bad)",          { XX } },
6930     /* f8 */
6931     { "(bad)",          { XX } },
6932     { "(bad)",          { XX } },
6933     { "(bad)",          { XX } },
6934     { "(bad)",          { XX } },
6935     { "(bad)",          { XX } },
6936     { "(bad)",          { XX } },
6937     { "(bad)",          { XX } },
6938     { "(bad)",          { XX } },
6939   },
6940 };
6941
6942 static const struct dis386 vex_table[][256] = {
6943   /* VEX_0F */
6944   {
6945     /* 00 */
6946     { "(bad)",          { XX } },
6947     { "(bad)",          { XX } },
6948     { "(bad)",          { XX } },
6949     { "(bad)",          { XX } },
6950     { "(bad)",          { XX } },
6951     { "(bad)",          { XX } },
6952     { "(bad)",          { XX } },
6953     { "(bad)",          { XX } },
6954     /* 08 */
6955     { "(bad)",          { XX } },
6956     { "(bad)",          { XX } },
6957     { "(bad)",          { XX } },
6958     { "(bad)",          { XX } },
6959     { "(bad)",          { XX } },
6960     { "(bad)",          { XX } },
6961     { "(bad)",          { XX } },
6962     { "(bad)",          { XX } },
6963     /* 10 */
6964     { PREFIX_TABLE (PREFIX_VEX_10) },
6965     { PREFIX_TABLE (PREFIX_VEX_11) },
6966     { PREFIX_TABLE (PREFIX_VEX_12) },
6967     { MOD_TABLE (MOD_VEX_13) },
6968     { "vunpcklpX",      { XM, Vex, EXx } },
6969     { "vunpckhpX",      { XM, Vex, EXx } },
6970     { PREFIX_TABLE (PREFIX_VEX_16) },
6971     { MOD_TABLE (MOD_VEX_17) },
6972     /* 18 */
6973     { "(bad)",          { XX } },
6974     { "(bad)",          { XX } },
6975     { "(bad)",          { XX } },
6976     { "(bad)",          { XX } },
6977     { "(bad)",          { XX } },
6978     { "(bad)",          { XX } },
6979     { "(bad)",          { XX } },
6980     { "(bad)",          { XX } },
6981     /* 20 */
6982     { "(bad)",          { XX } },
6983     { "(bad)",          { XX } },
6984     { "(bad)",          { XX } },
6985     { "(bad)",          { XX } },
6986     { "(bad)",          { XX } },
6987     { "(bad)",          { XX } },
6988     { "(bad)",          { XX } },
6989     { "(bad)",          { XX } },
6990     /* 28 */
6991     { "vmovapX",        { XM, EXx } },
6992     { "vmovapX",        { EXx, XM } },
6993     { PREFIX_TABLE (PREFIX_VEX_2A) },
6994     { MOD_TABLE (MOD_VEX_2B) },
6995     { PREFIX_TABLE (PREFIX_VEX_2C) },
6996     { PREFIX_TABLE (PREFIX_VEX_2D) },
6997     { PREFIX_TABLE (PREFIX_VEX_2E) },
6998     { PREFIX_TABLE (PREFIX_VEX_2F) },
6999     /* 30 */
7000     { "(bad)",          { XX } },
7001     { "(bad)",          { XX } },
7002     { "(bad)",          { XX } },
7003     { "(bad)",          { XX } },
7004     { "(bad)",          { XX } },
7005     { "(bad)",          { XX } },
7006     { "(bad)",          { XX } },
7007     { "(bad)",          { XX } },
7008     /* 38 */
7009     { "(bad)",          { XX } },
7010     { "(bad)",          { XX } },
7011     { "(bad)",          { XX } },
7012     { "(bad)",          { XX } },
7013     { "(bad)",          { XX } },
7014     { "(bad)",          { XX } },
7015     { "(bad)",          { XX } },
7016     { "(bad)",          { XX } },
7017     /* 40 */
7018     { "(bad)",          { XX } },
7019     { "(bad)",          { XX } },
7020     { "(bad)",          { XX } },
7021     { "(bad)",          { XX } },
7022     { "(bad)",          { XX } },
7023     { "(bad)",          { XX } },
7024     { "(bad)",          { XX } },
7025     { "(bad)",          { XX } },
7026     /* 48 */
7027     { "(bad)",          { XX } },
7028     { "(bad)",          { XX } },
7029     { "(bad)",          { XX } },
7030     { "(bad)",          { XX } },
7031     { "(bad)",          { XX } },
7032     { "(bad)",          { XX } },
7033     { "(bad)",          { XX } },
7034     { "(bad)",          { XX } },
7035     /* 50 */
7036     { MOD_TABLE (MOD_VEX_51) },
7037     { PREFIX_TABLE (PREFIX_VEX_51) },
7038     { PREFIX_TABLE (PREFIX_VEX_52) },
7039     { PREFIX_TABLE (PREFIX_VEX_53) },
7040     { "vandpX",         { XM, Vex, EXx } },
7041     { "vandnpX",        { XM, Vex, EXx } },
7042     { "vorpX",          { XM, Vex, EXx } },
7043     { "vxorpX",         { XM, Vex, EXx } },
7044     /* 58 */
7045     { PREFIX_TABLE (PREFIX_VEX_58) },
7046     { PREFIX_TABLE (PREFIX_VEX_59) },
7047     { PREFIX_TABLE (PREFIX_VEX_5A) },
7048     { PREFIX_TABLE (PREFIX_VEX_5B) },
7049     { PREFIX_TABLE (PREFIX_VEX_5C) },
7050     { PREFIX_TABLE (PREFIX_VEX_5D) },
7051     { PREFIX_TABLE (PREFIX_VEX_5E) },
7052     { PREFIX_TABLE (PREFIX_VEX_5F) },
7053     /* 60 */
7054     { PREFIX_TABLE (PREFIX_VEX_60) },
7055     { PREFIX_TABLE (PREFIX_VEX_61) },
7056     { PREFIX_TABLE (PREFIX_VEX_62) },
7057     { PREFIX_TABLE (PREFIX_VEX_63) },
7058     { PREFIX_TABLE (PREFIX_VEX_64) },
7059     { PREFIX_TABLE (PREFIX_VEX_65) },
7060     { PREFIX_TABLE (PREFIX_VEX_66) },
7061     { PREFIX_TABLE (PREFIX_VEX_67) },
7062     /* 68 */
7063     { PREFIX_TABLE (PREFIX_VEX_68) },
7064     { PREFIX_TABLE (PREFIX_VEX_69) },
7065     { PREFIX_TABLE (PREFIX_VEX_6A) },
7066     { PREFIX_TABLE (PREFIX_VEX_6B) },
7067     { PREFIX_TABLE (PREFIX_VEX_6C) },
7068     { PREFIX_TABLE (PREFIX_VEX_6D) },
7069     { PREFIX_TABLE (PREFIX_VEX_6E) },
7070     { PREFIX_TABLE (PREFIX_VEX_6F) },
7071     /* 70 */
7072     { PREFIX_TABLE (PREFIX_VEX_70) },
7073     { REG_TABLE (REG_VEX_71) },
7074     { REG_TABLE (REG_VEX_72) },
7075     { REG_TABLE (REG_VEX_73) },
7076     { PREFIX_TABLE (PREFIX_VEX_74) },
7077     { PREFIX_TABLE (PREFIX_VEX_75) },
7078     { PREFIX_TABLE (PREFIX_VEX_76) },
7079     { PREFIX_TABLE (PREFIX_VEX_77) },
7080     /* 78 */
7081     { "(bad)",          { XX } },
7082     { "(bad)",          { XX } },
7083     { "(bad)",          { XX } },
7084     { "(bad)",          { XX } },
7085     { PREFIX_TABLE (PREFIX_VEX_7C) },
7086     { PREFIX_TABLE (PREFIX_VEX_7D) },
7087     { PREFIX_TABLE (PREFIX_VEX_7E) },
7088     { PREFIX_TABLE (PREFIX_VEX_7F) },
7089     /* 80 */
7090     { "(bad)",          { XX } },
7091     { "(bad)",          { XX } },
7092     { "(bad)",          { XX } },
7093     { "(bad)",          { XX } },
7094     { "(bad)",          { XX } },
7095     { "(bad)",          { XX } },
7096     { "(bad)",          { XX } },
7097     { "(bad)",          { XX } },
7098     /* 88 */
7099     { "(bad)",          { XX } },
7100     { "(bad)",          { XX } },
7101     { "(bad)",          { XX } },
7102     { "(bad)",          { XX } },
7103     { "(bad)",          { XX } },
7104     { "(bad)",          { XX } },
7105     { "(bad)",          { XX } },
7106     { "(bad)",          { XX } },
7107     /* 90 */
7108     { "(bad)",          { XX } },
7109     { "(bad)",          { XX } },
7110     { "(bad)",          { XX } },
7111     { "(bad)",          { XX } },
7112     { "(bad)",          { XX } },
7113     { "(bad)",          { XX } },
7114     { "(bad)",          { XX } },
7115     { "(bad)",          { XX } },
7116     /* 98 */
7117     { "(bad)",          { XX } },
7118     { "(bad)",          { XX } },
7119     { "(bad)",          { XX } },
7120     { "(bad)",          { XX } },
7121     { "(bad)",          { XX } },
7122     { "(bad)",          { XX } },
7123     { "(bad)",          { XX } },
7124     { "(bad)",          { XX } },
7125     /* a0 */
7126     { "(bad)",          { XX } },
7127     { "(bad)",          { XX } },
7128     { "(bad)",          { XX } },
7129     { "(bad)",          { XX } },
7130     { "(bad)",          { XX } },
7131     { "(bad)",          { XX } },
7132     { "(bad)",          { XX } },
7133     { "(bad)",          { XX } },
7134     /* a8 */
7135     { "(bad)",          { XX } },
7136     { "(bad)",          { XX } },
7137     { "(bad)",          { XX } },
7138     { "(bad)",          { XX } },
7139     { "(bad)",          { XX } },
7140     { "(bad)",          { XX } },
7141     { REG_TABLE (REG_VEX_AE) },
7142     { "(bad)",          { XX } },
7143     /* b0 */
7144     { "(bad)",          { XX } },
7145     { "(bad)",          { XX } },
7146     { "(bad)",          { XX } },
7147     { "(bad)",          { XX } },
7148     { "(bad)",          { XX } },
7149     { "(bad)",          { XX } },
7150     { "(bad)",          { XX } },
7151     { "(bad)",          { XX } },
7152     /* b8 */
7153     { "(bad)",          { XX } },
7154     { "(bad)",          { XX } },
7155     { "(bad)",          { XX } },
7156     { "(bad)",          { XX } },
7157     { "(bad)",          { XX } },
7158     { "(bad)",          { XX } },
7159     { "(bad)",          { XX } },
7160     { "(bad)",          { XX } },
7161     /* c0 */
7162     { "(bad)",          { XX } },
7163     { "(bad)",          { XX } },
7164     { PREFIX_TABLE (PREFIX_VEX_C2) },
7165     { "(bad)",          { XX } },
7166     { PREFIX_TABLE (PREFIX_VEX_C4) },
7167     { PREFIX_TABLE (PREFIX_VEX_C5) },
7168     { "vshufpX",        { XM, Vex, EXx, Ib } },
7169     { "(bad)",          { XX } },
7170     /* c8 */
7171     { "(bad)",          { XX } },
7172     { "(bad)",          { XX } },
7173     { "(bad)",          { XX } },
7174     { "(bad)",          { XX } },
7175     { "(bad)",          { XX } },
7176     { "(bad)",          { XX } },
7177     { "(bad)",          { XX } },
7178     { "(bad)",          { XX } },
7179     /* d0 */
7180     { PREFIX_TABLE (PREFIX_VEX_D0) },
7181     { PREFIX_TABLE (PREFIX_VEX_D1) },
7182     { PREFIX_TABLE (PREFIX_VEX_D2) },
7183     { PREFIX_TABLE (PREFIX_VEX_D3) },
7184     { PREFIX_TABLE (PREFIX_VEX_D4) },
7185     { PREFIX_TABLE (PREFIX_VEX_D5) },
7186     { PREFIX_TABLE (PREFIX_VEX_D6) },
7187     { PREFIX_TABLE (PREFIX_VEX_D7) },
7188     /* d8 */
7189     { PREFIX_TABLE (PREFIX_VEX_D8) },
7190     { PREFIX_TABLE (PREFIX_VEX_D9) },
7191     { PREFIX_TABLE (PREFIX_VEX_DA) },
7192     { PREFIX_TABLE (PREFIX_VEX_DB) },
7193     { PREFIX_TABLE (PREFIX_VEX_DC) },
7194     { PREFIX_TABLE (PREFIX_VEX_DD) },
7195     { PREFIX_TABLE (PREFIX_VEX_DE) },
7196     { PREFIX_TABLE (PREFIX_VEX_DF) },
7197     /* e0 */
7198     { PREFIX_TABLE (PREFIX_VEX_E0) },
7199     { PREFIX_TABLE (PREFIX_VEX_E1) },
7200     { PREFIX_TABLE (PREFIX_VEX_E2) },
7201     { PREFIX_TABLE (PREFIX_VEX_E3) },
7202     { PREFIX_TABLE (PREFIX_VEX_E4) },
7203     { PREFIX_TABLE (PREFIX_VEX_E5) },
7204     { PREFIX_TABLE (PREFIX_VEX_E6) },
7205     { PREFIX_TABLE (PREFIX_VEX_E7) },
7206     /* e8 */
7207     { PREFIX_TABLE (PREFIX_VEX_E8) },
7208     { PREFIX_TABLE (PREFIX_VEX_E9) },
7209     { PREFIX_TABLE (PREFIX_VEX_EA) },
7210     { PREFIX_TABLE (PREFIX_VEX_EB) },
7211     { PREFIX_TABLE (PREFIX_VEX_EC) },
7212     { PREFIX_TABLE (PREFIX_VEX_ED) },
7213     { PREFIX_TABLE (PREFIX_VEX_EE) },
7214     { PREFIX_TABLE (PREFIX_VEX_EF) },
7215     /* f0 */
7216     { PREFIX_TABLE (PREFIX_VEX_F0) },
7217     { PREFIX_TABLE (PREFIX_VEX_F1) },
7218     { PREFIX_TABLE (PREFIX_VEX_F2) },
7219     { PREFIX_TABLE (PREFIX_VEX_F3) },
7220     { PREFIX_TABLE (PREFIX_VEX_F4) },
7221     { PREFIX_TABLE (PREFIX_VEX_F5) },
7222     { PREFIX_TABLE (PREFIX_VEX_F6) },
7223     { PREFIX_TABLE (PREFIX_VEX_F7) },
7224     /* f8 */
7225     { PREFIX_TABLE (PREFIX_VEX_F8) },
7226     { PREFIX_TABLE (PREFIX_VEX_F9) },
7227     { PREFIX_TABLE (PREFIX_VEX_FA) },
7228     { PREFIX_TABLE (PREFIX_VEX_FB) },
7229     { PREFIX_TABLE (PREFIX_VEX_FC) },
7230     { PREFIX_TABLE (PREFIX_VEX_FD) },
7231     { PREFIX_TABLE (PREFIX_VEX_FE) },
7232     { "(bad)",          { XX } },
7233   },
7234   /* VEX_0F38 */
7235   {
7236     /* 00 */
7237     { PREFIX_TABLE (PREFIX_VEX_3800) },
7238     { PREFIX_TABLE (PREFIX_VEX_3801) },
7239     { PREFIX_TABLE (PREFIX_VEX_3802) },
7240     { PREFIX_TABLE (PREFIX_VEX_3803) },
7241     { PREFIX_TABLE (PREFIX_VEX_3804) },
7242     { PREFIX_TABLE (PREFIX_VEX_3805) },
7243     { PREFIX_TABLE (PREFIX_VEX_3806) },
7244     { PREFIX_TABLE (PREFIX_VEX_3807) },
7245     /* 08 */
7246     { PREFIX_TABLE (PREFIX_VEX_3808) },
7247     { PREFIX_TABLE (PREFIX_VEX_3809) },
7248     { PREFIX_TABLE (PREFIX_VEX_380A) },
7249     { PREFIX_TABLE (PREFIX_VEX_380B) },
7250     { PREFIX_TABLE (PREFIX_VEX_380C) },
7251     { PREFIX_TABLE (PREFIX_VEX_380D) },
7252     { PREFIX_TABLE (PREFIX_VEX_380E) },
7253     { PREFIX_TABLE (PREFIX_VEX_380F) },
7254     /* 10 */
7255     { "(bad)",          { XX } },
7256     { "(bad)",          { XX } },
7257     { "(bad)",          { XX } },
7258     { "(bad)",          { XX } },
7259     { "(bad)",          { XX } },
7260     { "(bad)",          { XX } },
7261     { "(bad)",          { XX } },
7262     { PREFIX_TABLE (PREFIX_VEX_3817) },
7263     /* 18 */
7264     { PREFIX_TABLE (PREFIX_VEX_3818) },
7265     { PREFIX_TABLE (PREFIX_VEX_3819) },
7266     { PREFIX_TABLE (PREFIX_VEX_381A) },
7267     { "(bad)",          { XX } },
7268     { PREFIX_TABLE (PREFIX_VEX_381C) },
7269     { PREFIX_TABLE (PREFIX_VEX_381D) },
7270     { PREFIX_TABLE (PREFIX_VEX_381E) },
7271     { "(bad)",          { XX } },
7272     /* 20 */
7273     { PREFIX_TABLE (PREFIX_VEX_3820) },
7274     { PREFIX_TABLE (PREFIX_VEX_3821) },
7275     { PREFIX_TABLE (PREFIX_VEX_3822) },
7276     { PREFIX_TABLE (PREFIX_VEX_3823) },
7277     { PREFIX_TABLE (PREFIX_VEX_3824) },
7278     { PREFIX_TABLE (PREFIX_VEX_3825) },
7279     { "(bad)",          { XX } },
7280     { "(bad)",          { XX } },
7281     /* 28 */
7282     { PREFIX_TABLE (PREFIX_VEX_3828) },
7283     { PREFIX_TABLE (PREFIX_VEX_3829) },
7284     { PREFIX_TABLE (PREFIX_VEX_382A) },
7285     { PREFIX_TABLE (PREFIX_VEX_382B) },
7286     { PREFIX_TABLE (PREFIX_VEX_382C) },
7287     { PREFIX_TABLE (PREFIX_VEX_382D) },
7288     { PREFIX_TABLE (PREFIX_VEX_382E) },
7289     { PREFIX_TABLE (PREFIX_VEX_382F) },
7290     /* 30 */
7291     { PREFIX_TABLE (PREFIX_VEX_3830) },
7292     { PREFIX_TABLE (PREFIX_VEX_3831) },
7293     { PREFIX_TABLE (PREFIX_VEX_3832) },
7294     { PREFIX_TABLE (PREFIX_VEX_3833) },
7295     { PREFIX_TABLE (PREFIX_VEX_3834) },
7296     { PREFIX_TABLE (PREFIX_VEX_3835) },
7297     { "(bad)",          { XX } },
7298     { PREFIX_TABLE (PREFIX_VEX_3837) },
7299     /* 38 */
7300     { PREFIX_TABLE (PREFIX_VEX_3838) },
7301     { PREFIX_TABLE (PREFIX_VEX_3839) },
7302     { PREFIX_TABLE (PREFIX_VEX_383A) },
7303     { PREFIX_TABLE (PREFIX_VEX_383B) },
7304     { PREFIX_TABLE (PREFIX_VEX_383C) },
7305     { PREFIX_TABLE (PREFIX_VEX_383D) },
7306     { PREFIX_TABLE (PREFIX_VEX_383E) },
7307     { PREFIX_TABLE (PREFIX_VEX_383F) },
7308     /* 40 */
7309     { PREFIX_TABLE (PREFIX_VEX_3840) },
7310     { PREFIX_TABLE (PREFIX_VEX_3841) },
7311     { "(bad)",          { XX } },
7312     { "(bad)",          { XX } },
7313     { "(bad)",          { XX } },
7314     { "(bad)",          { XX } },
7315     { "(bad)",          { XX } },
7316     { "(bad)",          { XX } },
7317     /* 48 */
7318     { "(bad)",          { XX } },
7319     { "(bad)",          { XX } },
7320     { "(bad)",          { XX } },
7321     { "(bad)",          { XX } },
7322     { "(bad)",          { XX } },
7323     { "(bad)",          { XX } },
7324     { "(bad)",          { XX } },
7325     { "(bad)",          { XX } },
7326     /* 50 */
7327     { "(bad)",          { XX } },
7328     { "(bad)",          { XX } },
7329     { "(bad)",          { XX } },
7330     { "(bad)",          { XX } },
7331     { "(bad)",          { XX } },
7332     { "(bad)",          { XX } },
7333     { "(bad)",          { XX } },
7334     { "(bad)",          { XX } },
7335     /* 58 */
7336     { "(bad)",          { XX } },
7337     { "(bad)",          { XX } },
7338     { "(bad)",          { XX } },
7339     { "(bad)",          { XX } },
7340     { "(bad)",          { XX } },
7341     { "(bad)",          { XX } },
7342     { "(bad)",          { XX } },
7343     { "(bad)",          { XX } },
7344     /* 60 */
7345     { "(bad)",          { XX } },
7346     { "(bad)",          { XX } },
7347     { "(bad)",          { XX } },
7348     { "(bad)",          { XX } },
7349     { "(bad)",          { XX } },
7350     { "(bad)",          { XX } },
7351     { "(bad)",          { XX } },
7352     { "(bad)",          { XX } },
7353     /* 68 */
7354     { "(bad)",          { XX } },
7355     { "(bad)",          { XX } },
7356     { "(bad)",          { XX } },
7357     { "(bad)",          { XX } },
7358     { "(bad)",          { XX } },
7359     { "(bad)",          { XX } },
7360     { "(bad)",          { XX } },
7361     { "(bad)",          { XX } },
7362     /* 70 */
7363     { "(bad)",          { XX } },
7364     { "(bad)",          { XX } },
7365     { "(bad)",          { XX } },
7366     { "(bad)",          { XX } },
7367     { "(bad)",          { XX } },
7368     { "(bad)",          { XX } },
7369     { "(bad)",          { XX } },
7370     { "(bad)",          { XX } },
7371     /* 78 */
7372     { "(bad)",          { XX } },
7373     { "(bad)",          { XX } },
7374     { "(bad)",          { XX } },
7375     { "(bad)",          { XX } },
7376     { "(bad)",          { XX } },
7377     { "(bad)",          { XX } },
7378     { "(bad)",          { XX } },
7379     { "(bad)",          { XX } },
7380     /* 80 */
7381     { "(bad)",          { XX } },
7382     { "(bad)",          { XX } },
7383     { "(bad)",          { XX } },
7384     { "(bad)",          { XX } },
7385     { "(bad)",          { XX } },
7386     { "(bad)",          { XX } },
7387     { "(bad)",          { XX } },
7388     { "(bad)",          { XX } },
7389     /* 88 */
7390     { "(bad)",          { XX } },
7391     { "(bad)",          { XX } },
7392     { "(bad)",          { XX } },
7393     { "(bad)",          { XX } },
7394     { "(bad)",          { XX } },
7395     { "(bad)",          { XX } },
7396     { "(bad)",          { XX } },
7397     { "(bad)",          { XX } },
7398     /* 90 */
7399     { "(bad)",          { XX } },
7400     { "(bad)",          { XX } },
7401     { "(bad)",          { XX } },
7402     { "(bad)",          { XX } },
7403     { "(bad)",          { XX } },
7404     { "(bad)",          { XX } },
7405     { "(bad)",          { XX } },
7406     { "(bad)",          { XX } },
7407     /* 98 */
7408     { "(bad)",          { XX } },
7409     { "(bad)",          { XX } },
7410     { "(bad)",          { XX } },
7411     { "(bad)",          { XX } },
7412     { "(bad)",          { XX } },
7413     { "(bad)",          { XX } },
7414     { "(bad)",          { XX } },
7415     { "(bad)",          { XX } },
7416     /* a0 */
7417     { "(bad)",          { XX } },
7418     { "(bad)",          { XX } },
7419     { "(bad)",          { XX } },
7420     { "(bad)",          { XX } },
7421     { "(bad)",          { XX } },
7422     { "(bad)",          { XX } },
7423     { "(bad)",          { XX } },
7424     { "(bad)",          { XX } },
7425     /* a8 */
7426     { "(bad)",          { XX } },
7427     { "(bad)",          { XX } },
7428     { "(bad)",          { XX } },
7429     { "(bad)",          { XX } },
7430     { "(bad)",          { XX } },
7431     { "(bad)",          { XX } },
7432     { "(bad)",          { XX } },
7433     { "(bad)",          { XX } },
7434     /* b0 */
7435     { "(bad)",          { XX } },
7436     { "(bad)",          { XX } },
7437     { "(bad)",          { XX } },
7438     { "(bad)",          { XX } },
7439     { "(bad)",          { XX } },
7440     { "(bad)",          { XX } },
7441     { "(bad)",          { XX } },
7442     { "(bad)",          { XX } },
7443     /* b8 */
7444     { "(bad)",          { XX } },
7445     { "(bad)",          { XX } },
7446     { "(bad)",          { XX } },
7447     { "(bad)",          { XX } },
7448     { "(bad)",          { XX } },
7449     { "(bad)",          { XX } },
7450     { "(bad)",          { XX } },
7451     { "(bad)",          { XX } },
7452     /* c0 */
7453     { "(bad)",          { XX } },
7454     { "(bad)",          { XX } },
7455     { "(bad)",          { XX } },
7456     { "(bad)",          { XX } },
7457     { "(bad)",          { XX } },
7458     { "(bad)",          { XX } },
7459     { "(bad)",          { XX } },
7460     { "(bad)",          { XX } },
7461     /* c8 */
7462     { "(bad)",          { XX } },
7463     { "(bad)",          { XX } },
7464     { "(bad)",          { XX } },
7465     { "(bad)",          { XX } },
7466     { "(bad)",          { XX } },
7467     { "(bad)",          { XX } },
7468     { "(bad)",          { XX } },
7469     { "(bad)",          { XX } },
7470     /* d0 */
7471     { "(bad)",          { XX } },
7472     { "(bad)",          { XX } },
7473     { "(bad)",          { XX } },
7474     { "(bad)",          { XX } },
7475     { "(bad)",          { XX } },
7476     { "(bad)",          { XX } },
7477     { "(bad)",          { XX } },
7478     { "(bad)",          { XX } },
7479     /* d8 */
7480     { "(bad)",          { XX } },
7481     { "(bad)",          { XX } },
7482     { "(bad)",          { XX } },
7483     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7484     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7485     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7486     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7487     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7488     /* e0 */
7489     { "(bad)",          { XX } },
7490     { "(bad)",          { XX } },
7491     { "(bad)",          { XX } },
7492     { "(bad)",          { XX } },
7493     { "(bad)",          { XX } },
7494     { "(bad)",          { XX } },
7495     { "(bad)",          { XX } },
7496     { "(bad)",          { XX } },
7497     /* e8 */
7498     { "(bad)",          { XX } },
7499     { "(bad)",          { XX } },
7500     { "(bad)",          { XX } },
7501     { "(bad)",          { XX } },
7502     { "(bad)",          { XX } },
7503     { "(bad)",          { XX } },
7504     { "(bad)",          { XX } },
7505     { "(bad)",          { XX } },
7506     /* f0 */
7507     { "(bad)",          { XX } },
7508     { "(bad)",          { XX } },
7509     { "(bad)",          { XX } },
7510     { "(bad)",          { XX } },
7511     { "(bad)",          { XX } },
7512     { "(bad)",          { XX } },
7513     { "(bad)",          { XX } },
7514     { "(bad)",          { XX } },
7515     /* f8 */
7516     { "(bad)",          { XX } },
7517     { "(bad)",          { XX } },
7518     { "(bad)",          { XX } },
7519     { "(bad)",          { XX } },
7520     { "(bad)",          { XX } },
7521     { "(bad)",          { XX } },
7522     { "(bad)",          { XX } },
7523     { "(bad)",          { XX } },
7524   },
7525   /* VEX_0F3A */
7526   {
7527     /* 00 */
7528     { "(bad)",          { XX } },
7529     { "(bad)",          { XX } },
7530     { "(bad)",          { XX } },
7531     { "(bad)",          { XX } },
7532     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7533     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7534     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7535     { "(bad)",          { XX } },
7536     /* 08 */
7537     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7538     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7539     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7540     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7541     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7542     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7543     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7544     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7545     /* 10 */
7546     { "(bad)",          { XX } },
7547     { "(bad)",          { XX } },
7548     { "(bad)",          { XX } },
7549     { "(bad)",          { XX } },
7550     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7551     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7552     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7553     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7554     /* 18 */
7555     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7556     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7557     { "(bad)",          { XX } },
7558     { "(bad)",          { XX } },
7559     { "(bad)",          { XX } },
7560     { "(bad)",          { XX } },
7561     { "(bad)",          { XX } },
7562     { "(bad)",          { XX } },
7563     /* 20 */
7564     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7565     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7566     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7567     { "(bad)",          { XX } },
7568     { "(bad)",          { XX } },
7569     { "(bad)",          { XX } },
7570     { "(bad)",          { XX } },
7571     { "(bad)",          { XX } },
7572     /* 28 */
7573     { "(bad)",          { XX } },
7574     { "(bad)",          { XX } },
7575     { "(bad)",          { XX } },
7576     { "(bad)",          { XX } },
7577     { "(bad)",          { XX } },
7578     { "(bad)",          { XX } },
7579     { "(bad)",          { XX } },
7580     { "(bad)",          { XX } },
7581     /* 30 */
7582     { "(bad)",          { XX } },
7583     { "(bad)",          { XX } },
7584     { "(bad)",          { XX } },
7585     { "(bad)",          { XX } },
7586     { "(bad)",          { XX } },
7587     { "(bad)",          { XX } },
7588     { "(bad)",          { XX } },
7589     { "(bad)",          { XX } },
7590     /* 38 */
7591     { "(bad)",          { XX } },
7592     { "(bad)",          { XX } },
7593     { "(bad)",          { XX } },
7594     { "(bad)",          { XX } },
7595     { "(bad)",          { XX } },
7596     { "(bad)",          { XX } },
7597     { "(bad)",          { XX } },
7598     { "(bad)",          { XX } },
7599     /* 40 */
7600     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7601     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7602     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7603     { "(bad)",          { XX } },
7604     { "(bad)",          { XX } },
7605     { "(bad)",          { XX } },
7606     { "(bad)",          { XX } },
7607     { "(bad)",          { XX } },
7608     /* 48 */
7609     { PREFIX_TABLE (PREFIX_VEX_3A48) },
7610     { PREFIX_TABLE (PREFIX_VEX_3A49) },
7611     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7612     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7613     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7614     { "(bad)",          { XX } },
7615     { "(bad)",          { XX } },
7616     { "(bad)",          { XX } },
7617     /* 50 */
7618     { "(bad)",          { XX } },
7619     { "(bad)",          { XX } },
7620     { "(bad)",          { XX } },
7621     { "(bad)",          { XX } },
7622     { "(bad)",          { XX } },
7623     { "(bad)",          { XX } },
7624     { "(bad)",          { XX } },
7625     { "(bad)",          { XX } },
7626     /* 58 */
7627     { "(bad)",          { XX } },
7628     { "(bad)",          { XX } },
7629     { "(bad)",          { XX } },
7630     { "(bad)",          { XX } },
7631     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7632     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7633     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7634     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7635     /* 60 */
7636     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7637     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7638     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7639     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7640     { "(bad)",          { XX } },
7641     { "(bad)",          { XX } },
7642     { "(bad)",          { XX } },
7643     { "(bad)",          { XX } },
7644     /* 68 */
7645     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7646     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7647     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7648     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7649     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7650     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7651     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7652     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7653     /* 70 */
7654     { "(bad)",          { XX } },
7655     { "(bad)",          { XX } },
7656     { "(bad)",          { XX } },
7657     { "(bad)",          { XX } },
7658     { "(bad)",          { XX } },
7659     { "(bad)",          { XX } },
7660     { "(bad)",          { XX } },
7661     { "(bad)",          { XX } },
7662     /* 78 */
7663     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7664     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7665     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7666     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7667     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7668     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7669     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7670     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7671     /* 80 */
7672     { "(bad)",          { XX } },
7673     { "(bad)",          { XX } },
7674     { "(bad)",          { XX } },
7675     { "(bad)",          { XX } },
7676     { "(bad)",          { XX } },
7677     { "(bad)",          { XX } },
7678     { "(bad)",          { XX } },
7679     { "(bad)",          { XX } },
7680     /* 88 */
7681     { "(bad)",          { XX } },
7682     { "(bad)",          { XX } },
7683     { "(bad)",          { XX } },
7684     { "(bad)",          { XX } },
7685     { "(bad)",          { XX } },
7686     { "(bad)",          { XX } },
7687     { "(bad)",          { XX } },
7688     { "(bad)",          { XX } },
7689     /* 90 */
7690     { "(bad)",          { XX } },
7691     { "(bad)",          { XX } },
7692     { "(bad)",          { XX } },
7693     { "(bad)",          { XX } },
7694     { "(bad)",          { XX } },
7695     { "(bad)",          { XX } },
7696     { "(bad)",          { XX } },
7697     { "(bad)",          { XX } },
7698     /* 98 */
7699     { "(bad)",          { XX } },
7700     { "(bad)",          { XX } },
7701     { "(bad)",          { XX } },
7702     { "(bad)",          { XX } },
7703     { "(bad)",          { XX } },
7704     { "(bad)",          { XX } },
7705     { "(bad)",          { XX } },
7706     { "(bad)",          { XX } },
7707     /* a0 */
7708     { "(bad)",          { XX } },
7709     { "(bad)",          { XX } },
7710     { "(bad)",          { XX } },
7711     { "(bad)",          { XX } },
7712     { "(bad)",          { XX } },
7713     { "(bad)",          { XX } },
7714     { "(bad)",          { XX } },
7715     { "(bad)",          { XX } },
7716     /* a8 */
7717     { "(bad)",          { XX } },
7718     { "(bad)",          { XX } },
7719     { "(bad)",          { XX } },
7720     { "(bad)",          { XX } },
7721     { "(bad)",          { XX } },
7722     { "(bad)",          { XX } },
7723     { "(bad)",          { XX } },
7724     { "(bad)",          { XX } },
7725     /* b0 */
7726     { "(bad)",          { XX } },
7727     { "(bad)",          { XX } },
7728     { "(bad)",          { XX } },
7729     { "(bad)",          { XX } },
7730     { "(bad)",          { XX } },
7731     { "(bad)",          { XX } },
7732     { "(bad)",          { XX } },
7733     { "(bad)",          { XX } },
7734     /* b8 */
7735     { "(bad)",          { XX } },
7736     { "(bad)",          { XX } },
7737     { "(bad)",          { XX } },
7738     { "(bad)",          { XX } },
7739     { "(bad)",          { XX } },
7740     { "(bad)",          { XX } },
7741     { "(bad)",          { XX } },
7742     { "(bad)",          { XX } },
7743     /* c0 */
7744     { "(bad)",          { XX } },
7745     { "(bad)",          { XX } },
7746     { "(bad)",          { XX } },
7747     { "(bad)",          { XX } },
7748     { "(bad)",          { XX } },
7749     { "(bad)",          { XX } },
7750     { "(bad)",          { XX } },
7751     { "(bad)",          { XX } },
7752     /* c8 */
7753     { "(bad)",          { XX } },
7754     { "(bad)",          { XX } },
7755     { "(bad)",          { XX } },
7756     { "(bad)",          { XX } },
7757     { "(bad)",          { XX } },
7758     { "(bad)",          { XX } },
7759     { "(bad)",          { XX } },
7760     { "(bad)",          { XX } },
7761     /* d0 */
7762     { "(bad)",          { XX } },
7763     { "(bad)",          { XX } },
7764     { "(bad)",          { XX } },
7765     { "(bad)",          { XX } },
7766     { "(bad)",          { XX } },
7767     { "(bad)",          { XX } },
7768     { "(bad)",          { XX } },
7769     { "(bad)",          { XX } },
7770     /* d8 */
7771     { "(bad)",          { XX } },
7772     { "(bad)",          { XX } },
7773     { "(bad)",          { XX } },
7774     { "(bad)",          { XX } },
7775     { "(bad)",          { XX } },
7776     { "(bad)",          { XX } },
7777     { "(bad)",          { XX } },
7778     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
7779     /* e0 */
7780     { "(bad)",          { XX } },
7781     { "(bad)",          { XX } },
7782     { "(bad)",          { XX } },
7783     { "(bad)",          { XX } },
7784     { "(bad)",          { XX } },
7785     { "(bad)",          { XX } },
7786     { "(bad)",          { XX } },
7787     { "(bad)",          { XX } },
7788     /* e8 */
7789     { "(bad)",          { XX } },
7790     { "(bad)",          { XX } },
7791     { "(bad)",          { XX } },
7792     { "(bad)",          { XX } },
7793     { "(bad)",          { XX } },
7794     { "(bad)",          { XX } },
7795     { "(bad)",          { XX } },
7796     { "(bad)",          { XX } },
7797     /* f0 */
7798     { "(bad)",          { XX } },
7799     { "(bad)",          { XX } },
7800     { "(bad)",          { XX } },
7801     { "(bad)",          { XX } },
7802     { "(bad)",          { XX } },
7803     { "(bad)",          { XX } },
7804     { "(bad)",          { XX } },
7805     { "(bad)",          { XX } },
7806     /* f8 */
7807     { "(bad)",          { XX } },
7808     { "(bad)",          { XX } },
7809     { "(bad)",          { XX } },
7810     { "(bad)",          { XX } },
7811     { "(bad)",          { XX } },
7812     { "(bad)",          { XX } },
7813     { "(bad)",          { XX } },
7814     { "(bad)",          { XX } },
7815   },
7816 };
7817
7818 static const struct dis386 vex_len_table[][2] = {
7819   /* VEX_LEN_10_P_1 */
7820   {
7821     { "vmovss",         { XMVex, Vex128, EXd } },
7822     { "(bad)",          { XX } },
7823   },
7824
7825   /* VEX_LEN_10_P_3 */
7826   {
7827     { "vmovsd",         { XMVex, Vex128, EXq } },
7828     { "(bad)",          { XX } },
7829   },
7830
7831   /* VEX_LEN_11_P_1 */
7832   {
7833     { "vmovss",         { EXdVex, Vex128, XM } },
7834     { "(bad)",          { XX } },
7835   },
7836
7837   /* VEX_LEN_11_P_3 */
7838   {
7839     { "vmovsd",         { EXqVex, Vex128, XM } },
7840     { "(bad)",          { XX } },
7841   },
7842
7843   /* VEX_LEN_12_P_0_M_0 */
7844   {
7845     { "vmovlps",        { XM, Vex128, EXq } },
7846     { "(bad)",          { XX } },
7847   },
7848
7849   /* VEX_LEN_12_P_0_M_1 */
7850   {
7851     { "vmovhlps",       { XM, Vex128, EXq } },
7852     { "(bad)",          { XX } },
7853   },
7854
7855   /* VEX_LEN_12_P_2 */
7856   {
7857     { "vmovlpd",        { XM, Vex128, EXq } },
7858     { "(bad)",          { XX } },
7859   },
7860
7861   /* VEX_LEN_13_M_0 */
7862   {
7863     { "vmovlpX",        { EXq, XM } },
7864     { "(bad)",          { XX } },
7865   },
7866
7867   /* VEX_LEN_16_P_0_M_0 */
7868   {
7869     { "vmovhps",        { XM, Vex128, EXq } },
7870     { "(bad)",          { XX } },
7871   },
7872
7873   /* VEX_LEN_16_P_0_M_1 */
7874   {
7875     { "vmovlhps",       { XM, Vex128, EXq } },
7876     { "(bad)",          { XX } },
7877   },
7878
7879   /* VEX_LEN_16_P_2 */
7880   {
7881     { "vmovhpd",        { XM, Vex128, EXq } },
7882     { "(bad)",          { XX } },
7883   },
7884
7885   /* VEX_LEN_17_M_0 */
7886   {
7887     { "vmovhpX",        { EXq, XM } },
7888     { "(bad)",          { XX } },
7889   },
7890
7891   /* VEX_LEN_2A_P_1 */
7892   {
7893     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
7894     { "(bad)",          { XX } },
7895   },
7896
7897   /* VEX_LEN_2A_P_3 */
7898   {
7899     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
7900     { "(bad)",          { XX } },
7901   },
7902
7903   /* VEX_LEN_2B_M_0 */
7904   {
7905     { "vmovntpX",       { Mx, XM } },
7906     { "(bad)",          { XX } },
7907   },
7908
7909   /* VEX_LEN_2C_P_1 */
7910   {
7911     { "vcvttss2siY",    { Gv, EXd } },
7912     { "(bad)",          { XX } },
7913   },
7914
7915   /* VEX_LEN_2C_P_3 */
7916   {
7917     { "vcvttsd2siY",    { Gv, EXq } },
7918     { "(bad)",          { XX } },
7919   },
7920
7921   /* VEX_LEN_2D_P_1 */
7922   {
7923     { "vcvtss2siY",     { Gv, EXd } },
7924     { "(bad)",          { XX } },
7925   },
7926
7927   /* VEX_LEN_2D_P_3 */
7928   {
7929     { "vcvtsd2siY",     { Gv, EXq } },
7930     { "(bad)",          { XX } },
7931   },
7932
7933   /* VEX_LEN_2E_P_0 */
7934   {
7935     { "vucomiss",       { XM, EXd } },
7936     { "(bad)",          { XX } },
7937   },
7938
7939   /* VEX_LEN_2E_P_2 */
7940   {
7941     { "vucomisd",       { XM, EXq } },
7942     { "(bad)",          { XX } },
7943   },
7944
7945   /* VEX_LEN_2F_P_0 */
7946   {
7947     { "vcomiss",        { XM, EXd } },
7948     { "(bad)",          { XX } },
7949   },
7950
7951   /* VEX_LEN_2F_P_2 */
7952   {
7953     { "vcomisd",        { XM, EXq } },
7954     { "(bad)",          { XX } },
7955   },
7956
7957   /* VEX_LEN_51_P_1 */
7958   {
7959     { "vsqrtss",        { XM, Vex128, EXd } },
7960     { "(bad)",          { XX } },
7961   },
7962
7963   /* VEX_LEN_51_P_3 */
7964   {
7965     { "vsqrtsd",        { XM, Vex128, EXq } },
7966     { "(bad)",          { XX } },
7967   },
7968
7969   /* VEX_LEN_52_P_1 */
7970   {
7971     { "vrsqrtss",       { XM, Vex128, EXd } },
7972     { "(bad)",          { XX } },
7973   },
7974
7975   /* VEX_LEN_53_P_1 */
7976   {
7977     { "vrcpss",         { XM, Vex128, EXd } },
7978     { "(bad)",          { XX } },
7979   },
7980
7981   /* VEX_LEN_58_P_1 */
7982   {
7983     { "vaddss",         { XM, Vex128, EXd } },
7984     { "(bad)",          { XX } },
7985   },
7986
7987   /* VEX_LEN_58_P_3 */
7988   {
7989     { "vaddsd",         { XM, Vex128, EXq } },
7990     { "(bad)",          { XX } },
7991   },
7992
7993   /* VEX_LEN_59_P_1 */
7994   {
7995     { "vmulss",         { XM, Vex128, EXd } },
7996     { "(bad)",          { XX } },
7997   },
7998
7999   /* VEX_LEN_59_P_3 */
8000   {
8001     { "vmulsd",         { XM, Vex128, EXq } },
8002     { "(bad)",          { XX } },
8003   },
8004
8005   /* VEX_LEN_5A_P_1 */
8006   {
8007     { "vcvtss2sd",      { XM, Vex128, EXd } },
8008     { "(bad)",          { XX } },
8009   },
8010
8011   /* VEX_LEN_5A_P_3 */
8012   {
8013     { "vcvtsd2ss",      { XM, Vex128, EXq } },
8014     { "(bad)",          { XX } },
8015   },
8016
8017   /* VEX_LEN_5C_P_1 */
8018   {
8019     { "vsubss",         { XM, Vex128, EXd } },
8020     { "(bad)",          { XX } },
8021   },
8022
8023   /* VEX_LEN_5C_P_3 */
8024   {
8025     { "vsubsd",         { XM, Vex128, EXq } },
8026     { "(bad)",          { XX } },
8027   },
8028
8029   /* VEX_LEN_5D_P_1 */
8030   {
8031     { "vminss",         { XM, Vex128, EXd } },
8032     { "(bad)",          { XX } },
8033   },
8034
8035   /* VEX_LEN_5D_P_3 */
8036   {
8037     { "vminsd",         { XM, Vex128, EXq } },
8038     { "(bad)",          { XX } },
8039   },
8040
8041   /* VEX_LEN_5E_P_1 */
8042   {
8043     { "vdivss",         { XM, Vex128, EXd } },
8044     { "(bad)",          { XX } },
8045   },
8046
8047   /* VEX_LEN_5E_P_3 */
8048   {
8049     { "vdivsd",         { XM, Vex128, EXq } },
8050     { "(bad)",          { XX } },
8051   },
8052
8053   /* VEX_LEN_5F_P_1 */
8054   {
8055     { "vmaxss",         { XM, Vex128, EXd } },
8056     { "(bad)",          { XX } },
8057   },
8058
8059   /* VEX_LEN_5F_P_3 */
8060   {
8061     { "vmaxsd",         { XM, Vex128, EXq } },
8062     { "(bad)",          { XX } },
8063   },
8064
8065   /* VEX_LEN_60_P_2 */
8066   {
8067     { "vpunpcklbw",     { XM, Vex128, EXx } },
8068     { "(bad)",          { XX } },
8069   },
8070
8071   /* VEX_LEN_61_P_2 */
8072   {
8073     { "vpunpcklwd",     { XM, Vex128, EXx } },
8074     { "(bad)",          { XX } },
8075   },
8076
8077   /* VEX_LEN_62_P_2 */
8078   {
8079     { "vpunpckldq",     { XM, Vex128, EXx } },
8080     { "(bad)",          { XX } },
8081   },
8082
8083   /* VEX_LEN_63_P_2 */
8084   {
8085     { "vpacksswb",      { XM, Vex128, EXx } },
8086     { "(bad)",          { XX } },
8087   },
8088
8089   /* VEX_LEN_64_P_2 */
8090   {
8091     { "vpcmpgtb",       { XM, Vex128, EXx } },
8092     { "(bad)",          { XX } },
8093   },
8094
8095   /* VEX_LEN_65_P_2 */
8096   {
8097     { "vpcmpgtw",       { XM, Vex128, EXx } },
8098     { "(bad)",          { XX } },
8099   },
8100
8101   /* VEX_LEN_66_P_2 */
8102   {
8103     { "vpcmpgtd",       { XM, Vex128, EXx } },
8104     { "(bad)",          { XX } },
8105   },
8106
8107   /* VEX_LEN_67_P_2 */
8108   {
8109     { "vpackuswb",      { XM, Vex128, EXx } },
8110     { "(bad)",          { XX } },
8111   },
8112
8113   /* VEX_LEN_68_P_2 */
8114   {
8115     { "vpunpckhbw",     { XM, Vex128, EXx } },
8116     { "(bad)",          { XX } },
8117   },
8118
8119   /* VEX_LEN_69_P_2 */
8120   {
8121     { "vpunpckhwd",     { XM, Vex128, EXx } },
8122     { "(bad)",          { XX } },
8123   },
8124
8125   /* VEX_LEN_6A_P_2 */
8126   {
8127     { "vpunpckhdq",     { XM, Vex128, EXx } },
8128     { "(bad)",          { XX } },
8129   },
8130
8131   /* VEX_LEN_6B_P_2 */
8132   {
8133     { "vpackssdw",      { XM, Vex128, EXx } },
8134     { "(bad)",          { XX } },
8135   },
8136
8137   /* VEX_LEN_6C_P_2 */
8138   {
8139     { "vpunpcklqdq",    { XM, Vex128, EXx } },
8140     { "(bad)",          { XX } },
8141   },
8142
8143   /* VEX_LEN_6D_P_2 */
8144   {
8145     { "vpunpckhqdq",    { XM, Vex128, EXx } },
8146     { "(bad)",          { XX } },
8147   },
8148
8149   /* VEX_LEN_6E_P_2 */
8150   {
8151     { "vmovK",          { XM, Edq } },
8152     { "(bad)",          { XX } },
8153   },
8154
8155   /* VEX_LEN_70_P_1 */
8156   {
8157     { "vpshufhw",       { XM, EXx, Ib } },
8158     { "(bad)",          { XX } },
8159   },
8160
8161   /* VEX_LEN_70_P_2 */
8162   {
8163     { "vpshufd",        { XM, EXx, Ib } },
8164     { "(bad)",          { XX } },
8165   },
8166
8167   /* VEX_LEN_70_P_3 */
8168   {
8169     { "vpshuflw",       { XM, EXx, Ib } },
8170     { "(bad)",          { XX } },
8171   },
8172
8173   /* VEX_LEN_71_R_2_P_2 */
8174   {
8175     { "vpsrlw",         { Vex128, XS, Ib } },
8176     { "(bad)",          { XX } },
8177   },
8178
8179   /* VEX_LEN_71_R_4_P_2 */
8180   {
8181     { "vpsraw",         { Vex128, XS, Ib } },
8182     { "(bad)",          { XX } },
8183   },
8184
8185   /* VEX_LEN_71_R_6_P_2 */
8186   {
8187     { "vpsllw",         { Vex128, XS, Ib } },
8188     { "(bad)",          { XX } },
8189   },
8190
8191   /* VEX_LEN_72_R_2_P_2 */
8192   {
8193     { "vpsrld",         { Vex128, XS, Ib } },
8194     { "(bad)",          { XX } },
8195   },
8196
8197   /* VEX_LEN_72_R_4_P_2 */
8198   {
8199     { "vpsrad",         { Vex128, XS, Ib } },
8200     { "(bad)",          { XX } },
8201   },
8202
8203   /* VEX_LEN_72_R_6_P_2 */
8204   {
8205     { "vpslld",         { Vex128, XS, Ib } },
8206     { "(bad)",          { XX } },
8207   },
8208
8209   /* VEX_LEN_73_R_2_P_2 */
8210   {
8211     { "vpsrlq",         { Vex128, XS, Ib } },
8212     { "(bad)",          { XX } },
8213   },
8214
8215   /* VEX_LEN_73_R_3_P_2 */
8216   {
8217     { "vpsrldq",        { Vex128, XS, Ib } },
8218     { "(bad)",          { XX } },
8219   },
8220
8221   /* VEX_LEN_73_R_6_P_2 */
8222   {
8223     { "vpsllq",         { Vex128, XS, Ib } },
8224     { "(bad)",          { XX } },
8225   },
8226
8227   /* VEX_LEN_73_R_7_P_2 */
8228   {
8229     { "vpslldq",        { Vex128, XS, Ib } },
8230     { "(bad)",          { XX } },
8231   },
8232
8233   /* VEX_LEN_74_P_2 */
8234   {
8235     { "vpcmpeqb",       { XM, Vex128, EXx } },
8236     { "(bad)",          { XX } },
8237   },
8238
8239   /* VEX_LEN_75_P_2 */
8240   {
8241     { "vpcmpeqw",       { XM, Vex128, EXx } },
8242     { "(bad)",          { XX } },
8243   },
8244
8245   /* VEX_LEN_76_P_2 */
8246   {
8247     { "vpcmpeqd",       { XM, Vex128, EXx } },
8248     { "(bad)",          { XX } },
8249   },
8250
8251   /* VEX_LEN_7E_P_1 */
8252   {
8253     { "vmovq",          { XM, EXq } },
8254     { "(bad)",          { XX } },
8255   },
8256
8257   /* VEX_LEN_7E_P_2 */
8258   {
8259     { "vmovK",          { Edq, XM } },
8260     { "(bad)",          { XX } },
8261   },
8262
8263   /* VEX_LEN_AE_R_2_M0 */
8264   {
8265     { "vldmxcsr",       { Md } },
8266     { "(bad)",          { XX } },
8267   },
8268
8269   /* VEX_LEN_AE_R_3_M0 */
8270   {
8271     { "vstmxcsr",       { Md } },
8272     { "(bad)",          { XX } },
8273   },
8274
8275   /* VEX_LEN_C2_P_1 */
8276   {
8277     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
8278     { "(bad)",          { XX } },
8279   },
8280
8281   /* VEX_LEN_C2_P_3 */
8282   {
8283     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
8284     { "(bad)",          { XX } },
8285   },
8286
8287   /* VEX_LEN_C4_P_2 */
8288   {
8289     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
8290     { "(bad)",          { XX } },
8291   },
8292
8293   /* VEX_LEN_C5_P_2 */
8294   {
8295     { "vpextrw",        { Gdq, XS, Ib } },
8296     { "(bad)",          { XX } },
8297   },
8298
8299   /* VEX_LEN_D1_P_2 */
8300   {
8301     { "vpsrlw",         { XM, Vex128, EXx } },
8302     { "(bad)",          { XX } },
8303   },
8304
8305   /* VEX_LEN_D2_P_2 */
8306   {
8307     { "vpsrld",         { XM, Vex128, EXx } },
8308     { "(bad)",          { XX } },
8309   },
8310
8311   /* VEX_LEN_D3_P_2 */
8312   {
8313     { "vpsrlq",         { XM, Vex128, EXx } },
8314     { "(bad)",          { XX } },
8315   },
8316
8317   /* VEX_LEN_D4_P_2 */
8318   {
8319     { "vpaddq",         { XM, Vex128, EXx } },
8320     { "(bad)",          { XX } },
8321   },
8322
8323   /* VEX_LEN_D5_P_2 */
8324   {
8325     { "vpmullw",        { XM, Vex128, EXx } },
8326     { "(bad)",          { XX } },
8327   },
8328
8329   /* VEX_LEN_D6_P_2 */
8330   {
8331     { "vmovq",          { EXq, XM } },
8332     { "(bad)",          { XX } },
8333   },
8334
8335   /* VEX_LEN_D7_P_2_M_1 */
8336   {
8337     { "vpmovmskb",      { Gdq, XS } },
8338     { "(bad)",          { XX } },
8339   },
8340
8341   /* VEX_LEN_D8_P_2 */
8342   {
8343     { "vpsubusb",       { XM, Vex128, EXx } },
8344     { "(bad)",          { XX } },
8345   },
8346
8347   /* VEX_LEN_D9_P_2 */
8348   {
8349     { "vpsubusw",       { XM, Vex128, EXx } },
8350     { "(bad)",          { XX } },
8351   },
8352
8353   /* VEX_LEN_DA_P_2 */
8354   {
8355     { "vpminub",        { XM, Vex128, EXx } },
8356     { "(bad)",          { XX } },
8357   },
8358
8359   /* VEX_LEN_DB_P_2 */
8360   {
8361     { "vpand",          { XM, Vex128, EXx } },
8362     { "(bad)",          { XX } },
8363   },
8364
8365   /* VEX_LEN_DC_P_2 */
8366   {
8367     { "vpaddusb",       { XM, Vex128, EXx } },
8368     { "(bad)",          { XX } },
8369   },
8370
8371   /* VEX_LEN_DD_P_2 */
8372   {
8373     { "vpaddusw",       { XM, Vex128, EXx } },
8374     { "(bad)",          { XX } },
8375   },
8376
8377   /* VEX_LEN_DE_P_2 */
8378   {
8379     { "vpmaxub",        { XM, Vex128, EXx } },
8380     { "(bad)",          { XX } },
8381   },
8382
8383   /* VEX_LEN_DF_P_2 */
8384   {
8385     { "vpandn",         { XM, Vex128, EXx } },
8386     { "(bad)",          { XX } },
8387   },
8388
8389   /* VEX_LEN_E0_P_2 */
8390   {
8391     { "vpavgb",         { XM, Vex128, EXx } },
8392     { "(bad)",          { XX } },
8393   },
8394
8395   /* VEX_LEN_E1_P_2 */
8396   {
8397     { "vpsraw",         { XM, Vex128, EXx } },
8398     { "(bad)",          { XX } },
8399   },
8400
8401   /* VEX_LEN_E2_P_2 */
8402   {
8403     { "vpsrad",         { XM, Vex128, EXx } },
8404     { "(bad)",          { XX } },
8405   },
8406
8407   /* VEX_LEN_E3_P_2 */
8408   {
8409     { "vpavgw",         { XM, Vex128, EXx } },
8410     { "(bad)",          { XX } },
8411   },
8412
8413   /* VEX_LEN_E4_P_2 */
8414   {
8415     { "vpmulhuw",       { XM, Vex128, EXx } },
8416     { "(bad)",          { XX } },
8417   },
8418
8419   /* VEX_LEN_E5_P_2 */
8420   {
8421     { "vpmulhw",        { XM, Vex128, EXx } },
8422     { "(bad)",          { XX } },
8423   },
8424
8425   /* VEX_LEN_E7_P_2_M_0 */
8426   {
8427     { "vmovntdq",       { Mx, XM } },
8428     { "(bad)",          { XX } },
8429   },
8430
8431   /* VEX_LEN_E8_P_2 */
8432   {
8433     { "vpsubsb",        { XM, Vex128, EXx } },
8434     { "(bad)",          { XX } },
8435   },
8436
8437   /* VEX_LEN_E9_P_2 */
8438   {
8439     { "vpsubsw",        { XM, Vex128, EXx } },
8440     { "(bad)",          { XX } },
8441   },
8442
8443   /* VEX_LEN_EA_P_2 */
8444   {
8445     { "vpminsw",        { XM, Vex128, EXx } },
8446     { "(bad)",          { XX } },
8447   },
8448
8449   /* VEX_LEN_EB_P_2 */
8450   {
8451     { "vpor",           { XM, Vex128, EXx } },
8452     { "(bad)",          { XX } },
8453   },
8454
8455   /* VEX_LEN_EC_P_2 */
8456   {
8457     { "vpaddsb",        { XM, Vex128, EXx } },
8458     { "(bad)",          { XX } },
8459   },
8460
8461   /* VEX_LEN_ED_P_2 */
8462   {
8463     { "vpaddsw",        { XM, Vex128, EXx } },
8464     { "(bad)",          { XX } },
8465   },
8466
8467   /* VEX_LEN_EE_P_2 */
8468   {
8469     { "vpmaxsw",        { XM, Vex128, EXx } },
8470     { "(bad)",          { XX } },
8471   },
8472
8473   /* VEX_LEN_EF_P_2 */
8474   {
8475     { "vpxor",          { XM, Vex128, EXx } },
8476     { "(bad)",          { XX } },
8477   },
8478
8479   /* VEX_LEN_F1_P_2 */
8480   {
8481     { "vpsllw",         { XM, Vex128, EXx } },
8482     { "(bad)",          { XX } },
8483   },
8484
8485   /* VEX_LEN_F2_P_2 */
8486   {
8487     { "vpslld",         { XM, Vex128, EXx } },
8488     { "(bad)",          { XX } },
8489   },
8490
8491   /* VEX_LEN_F3_P_2 */
8492   {
8493     { "vpsllq",         { XM, Vex128, EXx } },
8494     { "(bad)",          { XX } },
8495   },
8496
8497   /* VEX_LEN_F4_P_2 */
8498   {
8499     { "vpmuludq",       { XM, Vex128, EXx } },
8500     { "(bad)",          { XX } },
8501   },
8502
8503   /* VEX_LEN_F5_P_2 */
8504   {
8505     { "vpmaddwd",       { XM, Vex128, EXx } },
8506     { "(bad)",          { XX } },
8507   },
8508
8509   /* VEX_LEN_F6_P_2 */
8510   {
8511     { "vpsadbw",        { XM, Vex128, EXx } },
8512     { "(bad)",          { XX } },
8513   },
8514
8515   /* VEX_LEN_F7_P_2 */
8516   {
8517     { "vmaskmovdqu",    { XM, XS } },
8518     { "(bad)",          { XX } },
8519   },
8520
8521   /* VEX_LEN_F8_P_2 */
8522   {
8523     { "vpsubb",         { XM, Vex128, EXx } },
8524     { "(bad)",          { XX } },
8525   },
8526
8527   /* VEX_LEN_F9_P_2 */
8528   {
8529     { "vpsubw",         { XM, Vex128, EXx } },
8530     { "(bad)",          { XX } },
8531   },
8532
8533   /* VEX_LEN_FA_P_2 */
8534   {
8535     { "vpsubd",         { XM, Vex128, EXx } },
8536     { "(bad)",          { XX } },
8537   },
8538
8539   /* VEX_LEN_FB_P_2 */
8540   {
8541     { "vpsubq",         { XM, Vex128, EXx } },
8542     { "(bad)",          { XX } },
8543   },
8544
8545   /* VEX_LEN_FC_P_2 */
8546   {
8547     { "vpaddb",         { XM, Vex128, EXx } },
8548     { "(bad)",          { XX } },
8549   },
8550
8551   /* VEX_LEN_FD_P_2 */
8552   {
8553     { "vpaddw",         { XM, Vex128, EXx } },
8554     { "(bad)",          { XX } },
8555   },
8556
8557   /* VEX_LEN_FE_P_2 */
8558   {
8559     { "vpaddd",         { XM, Vex128, EXx } },
8560     { "(bad)",          { XX } },
8561   },
8562
8563   /* VEX_LEN_3800_P_2 */
8564   {
8565     { "vpshufb",        { XM, Vex128, EXx } },
8566     { "(bad)",          { XX } },
8567   },
8568
8569   /* VEX_LEN_3801_P_2 */
8570   {
8571     { "vphaddw",        { XM, Vex128, EXx } },
8572     { "(bad)",          { XX } },
8573   },
8574
8575   /* VEX_LEN_3802_P_2 */
8576   {
8577     { "vphaddd",        { XM, Vex128, EXx } },
8578     { "(bad)",          { XX } },
8579   },
8580
8581   /* VEX_LEN_3803_P_2 */
8582   {
8583     { "vphaddsw",       { XM, Vex128, EXx } },
8584     { "(bad)",          { XX } },
8585   },
8586
8587   /* VEX_LEN_3804_P_2 */
8588   {
8589     { "vpmaddubsw",     { XM, Vex128, EXx } },
8590     { "(bad)",          { XX } },
8591   },
8592
8593   /* VEX_LEN_3805_P_2 */
8594   {
8595     { "vphsubw",        { XM, Vex128, EXx } },
8596     { "(bad)",          { XX } },
8597   },
8598
8599   /* VEX_LEN_3806_P_2 */
8600   {
8601     { "vphsubd",        { XM, Vex128, EXx } },
8602     { "(bad)",          { XX } },
8603   },
8604
8605   /* VEX_LEN_3807_P_2 */
8606   {
8607     { "vphsubsw",       { XM, Vex128, EXx } },
8608     { "(bad)",          { XX } },
8609   },
8610
8611   /* VEX_LEN_3808_P_2 */
8612   {
8613     { "vpsignb",        { XM, Vex128, EXx } },
8614     { "(bad)",          { XX } },
8615   },
8616
8617   /* VEX_LEN_3809_P_2 */
8618   {
8619     { "vpsignw",        { XM, Vex128, EXx } },
8620     { "(bad)",          { XX } },
8621   },
8622
8623   /* VEX_LEN_380A_P_2 */
8624   {
8625     { "vpsignd",        { XM, Vex128, EXx } },
8626     { "(bad)",          { XX } },
8627   },
8628
8629   /* VEX_LEN_380B_P_2 */
8630   {
8631     { "vpmulhrsw",      { XM, Vex128, EXx } },
8632     { "(bad)",          { XX } },
8633   },
8634
8635   /* VEX_LEN_3819_P_2_M_0 */
8636   {
8637     { "(bad)",          { XX } },
8638     { "vbroadcastsd",   { XM, Mq } },
8639   },
8640
8641   /* VEX_LEN_381A_P_2_M_0 */
8642   {
8643     { "(bad)",          { XX } },
8644     { "vbroadcastf128", { XM, Mxmm } },
8645   },
8646
8647   /* VEX_LEN_381C_P_2 */
8648   {
8649     { "vpabsb",         { XM, EXx } },
8650     { "(bad)",          { XX } },
8651   },
8652
8653   /* VEX_LEN_381D_P_2 */
8654   {
8655     { "vpabsw",         { XM, EXx } },
8656     { "(bad)",          { XX } },
8657   },
8658
8659   /* VEX_LEN_381E_P_2 */
8660   {
8661     { "vpabsd",         { XM, EXx } },
8662     { "(bad)",          { XX } },
8663   },
8664
8665   /* VEX_LEN_3820_P_2 */
8666   {
8667     { "vpmovsxbw",      { XM, EXq } },
8668     { "(bad)",          { XX } },
8669   },
8670
8671   /* VEX_LEN_3821_P_2 */
8672   {
8673     { "vpmovsxbd",      { XM, EXd } },
8674     { "(bad)",          { XX } },
8675   },
8676
8677   /* VEX_LEN_3822_P_2 */
8678   {
8679     { "vpmovsxbq",      { XM, EXw } },
8680     { "(bad)",          { XX } },
8681   },
8682
8683   /* VEX_LEN_3823_P_2 */
8684   {
8685     { "vpmovsxwd",      { XM, EXq } },
8686     { "(bad)",          { XX } },
8687   },
8688
8689   /* VEX_LEN_3824_P_2 */
8690   {
8691     { "vpmovsxwq",      { XM, EXd } },
8692     { "(bad)",          { XX } },
8693   },
8694
8695   /* VEX_LEN_3825_P_2 */
8696   {
8697     { "vpmovsxdq",      { XM, EXq } },
8698     { "(bad)",          { XX } },
8699   },
8700
8701   /* VEX_LEN_3828_P_2 */
8702   {
8703     { "vpmuldq",        { XM, Vex128, EXx } },
8704     { "(bad)",          { XX } },
8705   },
8706
8707   /* VEX_LEN_3829_P_2 */
8708   {
8709     { "vpcmpeqq",       { XM, Vex128, EXx } },
8710     { "(bad)",          { XX } },
8711   },
8712
8713   /* VEX_LEN_382A_P_2_M_0 */
8714   {
8715     { "vmovntdqa",      { XM, Mx } },
8716     { "(bad)",          { XX } },
8717   },
8718
8719   /* VEX_LEN_382B_P_2 */
8720   {
8721     { "vpackusdw",      { XM, Vex128, EXx } },
8722     { "(bad)",          { XX } },
8723   },
8724
8725   /* VEX_LEN_3830_P_2 */
8726   {
8727     { "vpmovzxbw",      { XM, EXq } },
8728     { "(bad)",          { XX } },
8729   },
8730
8731   /* VEX_LEN_3831_P_2 */
8732   {
8733     { "vpmovzxbd",      { XM, EXd } },
8734     { "(bad)",          { XX } },
8735   },
8736
8737   /* VEX_LEN_3832_P_2 */
8738   {
8739     { "vpmovzxbq",      { XM, EXw } },
8740     { "(bad)",          { XX } },
8741   },
8742
8743   /* VEX_LEN_3833_P_2 */
8744   {
8745     { "vpmovzxwd",      { XM, EXq } },
8746     { "(bad)",          { XX } },
8747   },
8748
8749   /* VEX_LEN_3834_P_2 */
8750   {
8751     { "vpmovzxwq",      { XM, EXd } },
8752     { "(bad)",          { XX } },
8753   },
8754
8755   /* VEX_LEN_3835_P_2 */
8756   {
8757     { "vpmovzxdq",      { XM, EXq } },
8758     { "(bad)",          { XX } },
8759   },
8760
8761   /* VEX_LEN_3837_P_2 */
8762   {
8763     { "vpcmpgtq",       { XM, Vex128, EXx } },
8764     { "(bad)",          { XX } },
8765   },
8766
8767   /* VEX_LEN_3838_P_2 */
8768   {
8769     { "vpminsb",        { XM, Vex128, EXx } },
8770     { "(bad)",          { XX } },
8771   },
8772
8773   /* VEX_LEN_3839_P_2 */
8774   {
8775     { "vpminsd",        { XM, Vex128, EXx } },
8776     { "(bad)",          { XX } },
8777   },
8778
8779   /* VEX_LEN_383A_P_2 */
8780   {
8781     { "vpminuw",        { XM, Vex128, EXx } },
8782     { "(bad)",          { XX } },
8783   },
8784
8785   /* VEX_LEN_383B_P_2 */
8786   {
8787     { "vpminud",        { XM, Vex128, EXx } },
8788     { "(bad)",          { XX } },
8789   },
8790
8791   /* VEX_LEN_383C_P_2 */
8792   {
8793     { "vpmaxsb",        { XM, Vex128, EXx } },
8794     { "(bad)",          { XX } },
8795   },
8796
8797   /* VEX_LEN_383D_P_2 */
8798   {
8799     { "vpmaxsd",        { XM, Vex128, EXx } },
8800     { "(bad)",          { XX } },
8801   },
8802
8803   /* VEX_LEN_383E_P_2 */
8804   {
8805     { "vpmaxuw",        { XM, Vex128, EXx } },
8806     { "(bad)",          { XX } },
8807   },
8808
8809   /* VEX_LEN_383F_P_2 */
8810   {
8811     { "vpmaxud",        { XM, Vex128, EXx } },
8812     { "(bad)",          { XX } },
8813   },
8814
8815   /* VEX_LEN_3840_P_2 */
8816   {
8817     { "vpmulld",        { XM, Vex128, EXx } },
8818     { "(bad)",          { XX } },
8819   },
8820
8821   /* VEX_LEN_3841_P_2 */
8822   {
8823     { "vphminposuw",    { XM, EXx } },
8824     { "(bad)",          { XX } },
8825   },
8826
8827   /* VEX_LEN_38DB_P_2 */
8828   {
8829     { "vaesimc",        { XM, EXx } },
8830     { "(bad)",          { XX } },
8831   },
8832
8833   /* VEX_LEN_38DC_P_2 */
8834   {
8835     { "vaesenc",        { XM, Vex128, EXx } },
8836     { "(bad)",          { XX } },
8837   },
8838
8839   /* VEX_LEN_38DD_P_2 */
8840   {
8841     { "vaesenclast",    { XM, Vex128, EXx } },
8842     { "(bad)",          { XX } },
8843   },
8844
8845   /* VEX_LEN_38DE_P_2 */
8846   {
8847     { "vaesdec",        { XM, Vex128, EXx } },
8848     { "(bad)",          { XX } },
8849   },
8850
8851   /* VEX_LEN_38DF_P_2 */
8852   {
8853     { "vaesdeclast",    { XM, Vex128, EXx } },
8854     { "(bad)",          { XX } },
8855   },
8856
8857   /* VEX_LEN_3A06_P_2 */
8858   {
8859     { "(bad)",          { XX } },
8860     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
8861   },
8862
8863   /* VEX_LEN_3A0A_P_2 */
8864   {
8865     { "vroundss",       { XM, Vex128, EXd, Ib } },
8866     { "(bad)",          { XX } },
8867   },
8868
8869   /* VEX_LEN_3A0B_P_2 */
8870   {
8871     { "vroundsd",       { XM, Vex128, EXq, Ib } },
8872     { "(bad)",          { XX } },
8873   },
8874
8875   /* VEX_LEN_3A0E_P_2 */
8876   {
8877     { "vpblendw",       { XM, Vex128, EXx, Ib } },
8878     { "(bad)",          { XX } },
8879   },
8880
8881   /* VEX_LEN_3A0F_P_2 */
8882   {
8883     { "vpalignr",       { XM, Vex128, EXx, Ib } },
8884     { "(bad)",          { XX } },
8885   },
8886
8887   /* VEX_LEN_3A14_P_2 */
8888   {
8889     { "vpextrb",        { Edqb, XM, Ib } },
8890     { "(bad)",          { XX } },
8891   },
8892
8893   /* VEX_LEN_3A15_P_2 */
8894   {
8895     { "vpextrw",        { Edqw, XM, Ib } },
8896     { "(bad)",          { XX } },
8897   },
8898
8899   /* VEX_LEN_3A16_P_2  */
8900   {
8901     { "vpextrK",        { Edq, XM, Ib } },
8902     { "(bad)",          { XX } },
8903   },
8904
8905   /* VEX_LEN_3A17_P_2 */
8906   {
8907     { "vextractps",     { Edqd, XM, Ib } },
8908     { "(bad)",          { XX } },
8909   },
8910
8911   /* VEX_LEN_3A18_P_2 */
8912   {
8913     { "(bad)",          { XX } },
8914     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
8915   },
8916
8917   /* VEX_LEN_3A19_P_2 */
8918   {
8919     { "(bad)",          { XX } },
8920     { "vextractf128",   { EXxmm, XM, Ib } },
8921   },
8922
8923   /* VEX_LEN_3A20_P_2 */
8924   {
8925     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
8926     { "(bad)",          { XX } },
8927   },
8928
8929   /* VEX_LEN_3A21_P_2 */
8930   {
8931     { "vinsertps",      { XM, Vex128, EXd, Ib } },
8932     { "(bad)",          { XX } },
8933   },
8934
8935   /* VEX_LEN_3A22_P_2 */
8936   {
8937     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8938     { "(bad)",          { XX } },
8939   },
8940
8941   /* VEX_LEN_3A41_P_2 */
8942   {
8943     { "vdppd",          { XM, Vex128, EXx, Ib } },
8944     { "(bad)",          { XX } },
8945   },
8946
8947   /* VEX_LEN_3A42_P_2 */
8948   {
8949     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
8950     { "(bad)",          { XX } },
8951   },
8952
8953   /* VEX_LEN_3A4C_P_2 */
8954   {
8955     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
8956     { "(bad)",          { XX } },
8957   },
8958
8959   /* VEX_LEN_3A60_P_2 */
8960   {
8961     { "vpcmpestrm",     { XM, EXx, Ib } },
8962     { "(bad)",          { XX } },
8963   },
8964
8965   /* VEX_LEN_3A61_P_2 */
8966   {
8967     { "vpcmpestri",     { XM, EXx, Ib } },
8968     { "(bad)",          { XX } },
8969   },
8970
8971   /* VEX_LEN_3A62_P_2 */
8972   {
8973     { "vpcmpistrm",     { XM, EXx, Ib } },
8974     { "(bad)",          { XX } },
8975   },
8976
8977   /* VEX_LEN_3A63_P_2 */
8978   {
8979     { "vpcmpistri",     { XM, EXx, Ib } },
8980     { "(bad)",          { XX } },
8981   },
8982
8983   /* VEX_LEN_3A6A_P_2 */
8984   {
8985     { "vfmaddss",       { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8986     { "(bad)",          { XX } },
8987   },
8988
8989   /* VEX_LEN_3A6B_P_2 */
8990   {
8991     { "vfmaddsd",       { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8992     { "(bad)",          { XX } },
8993   },
8994
8995   /* VEX_LEN_3A6E_P_2 */
8996   {
8997     { "vfmsubss",       { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8998     { "(bad)",          { XX } },
8999   },
9000
9001   /* VEX_LEN_3A6F_P_2 */
9002   {
9003     { "vfmsubsd",       { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
9004     { "(bad)",          { XX } },
9005   },
9006
9007   /* VEX_LEN_3A7A_P_2 */
9008   {
9009     { "vfnmaddss",      { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
9010     { "(bad)",          { XX } },
9011   },
9012
9013   /* VEX_LEN_3A7B_P_2 */
9014   {
9015     { "vfnmaddsd",      { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
9016     { "(bad)",          { XX } },
9017   },
9018
9019   /* VEX_LEN_3A7E_P_2 */
9020   {
9021     { "vfnmsubss",      { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
9022     { "(bad)",          { XX } },
9023   },
9024
9025   /* VEX_LEN_3A7F_P_2 */
9026   {
9027     { "vfnmsubsd",      { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
9028     { "(bad)",          { XX } },
9029   },
9030
9031   /* VEX_LEN_3ADF_P_2 */
9032   {
9033     { "vaeskeygenassist", { XM, EXx, Ib } },
9034     { "(bad)",          { XX } },
9035   },
9036 };
9037
9038 static const struct dis386 mod_table[][2] = {
9039   {
9040     /* MOD_8D */
9041     { "leaS",           { Gv, M } },
9042     { "(bad)",          { XX } },
9043   },
9044   {
9045     /* MOD_0F01_REG_0 */
9046     { X86_64_TABLE (X86_64_0F01_REG_0) },
9047     { RM_TABLE (RM_0F01_REG_0) },
9048   },
9049   {
9050     /* MOD_0F01_REG_1 */
9051     { X86_64_TABLE (X86_64_0F01_REG_1) },
9052     { RM_TABLE (RM_0F01_REG_1) },
9053   },
9054   {
9055     /* MOD_0F01_REG_2 */
9056     { X86_64_TABLE (X86_64_0F01_REG_2) },
9057     { RM_TABLE (RM_0F01_REG_2) },
9058   },
9059   {
9060     /* MOD_0F01_REG_3 */
9061     { X86_64_TABLE (X86_64_0F01_REG_3) },
9062     { RM_TABLE (RM_0F01_REG_3) },
9063   },
9064   {
9065     /* MOD_0F01_REG_7 */
9066     { "invlpg",         { Mb } },
9067     { RM_TABLE (RM_0F01_REG_7) },
9068   },
9069   {
9070     /* MOD_0F12_PREFIX_0 */
9071     { "movlps",         { XM, EXq } },
9072     { "movhlps",        { XM, EXq } },
9073   },
9074   {
9075     /* MOD_0F13 */
9076     { "movlpX",         { EXq, XM } },
9077     { "(bad)",          { XX } },
9078   },
9079   {
9080     /* MOD_0F16_PREFIX_0 */
9081     { "movhps",         { XM, EXq } },
9082     { "movlhps",        { XM, EXq } },
9083   },
9084   {
9085     /* MOD_0F17 */
9086     { "movhpX",         { EXq, XM } },
9087     { "(bad)",          { XX } },
9088   },
9089   {
9090     /* MOD_0F18_REG_0 */
9091     { "prefetchnta",    { Mb } },
9092     { "(bad)",          { XX } },
9093   },
9094   {
9095     /* MOD_0F18_REG_1 */
9096     { "prefetcht0",     { Mb } },
9097     { "(bad)",          { XX } },
9098   },
9099   {
9100     /* MOD_0F18_REG_2 */
9101     { "prefetcht1",     { Mb } },
9102     { "(bad)",          { XX } },
9103   },
9104   {
9105     /* MOD_0F18_REG_3 */
9106     { "prefetcht2",     { Mb } },
9107     { "(bad)",          { XX } },
9108   },
9109   {
9110     /* MOD_0F20 */
9111     { "(bad)",          { XX } },
9112     { "movZ",           { Rm, Cm } },
9113   },
9114   {
9115     /* MOD_0F21 */
9116     { "(bad)",          { XX } },
9117     { "movZ",           { Rm, Dm } },
9118   },
9119   {
9120     /* MOD_0F22 */
9121     { "(bad)",          { XX } },
9122     { "movZ",           { Cm, Rm } },
9123   },
9124   {
9125     /* MOD_0F23 */
9126     { "(bad)",          { XX } },
9127     { "movZ",           { Dm, Rm } },
9128   },
9129   {
9130     /* MOD_0F24 */
9131     { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
9132     { "movL",           { Rd, Td } },
9133   },
9134   {
9135     /* MOD_0F26 */
9136     { "(bad)",          { XX } },
9137     { "movL",           { Td, Rd } },
9138   },
9139   {
9140     /* MOD_0F2B_PREFIX_0 */
9141     {"movntps",         { Mx, XM } },
9142     { "(bad)",          { XX } },
9143   },
9144   {
9145     /* MOD_0F2B_PREFIX_1 */
9146     {"movntss",         { Md, XM } },
9147     { "(bad)",          { XX } },
9148   },
9149   {
9150     /* MOD_0F2B_PREFIX_2 */
9151     {"movntpd",         { Mx, XM } },
9152     { "(bad)",          { XX } },
9153   },
9154   {
9155     /* MOD_0F2B_PREFIX_3 */
9156     {"movntsd",         { Mq, XM } },
9157     { "(bad)",          { XX } },
9158   },
9159   {
9160     /* MOD_0F51 */
9161     { "(bad)",          { XX } },
9162     { "movmskpX",       { Gdq, XS } },
9163   },
9164   {
9165     /* MOD_0F71_REG_2 */
9166     { "(bad)",          { XX } },
9167     { "psrlw",          { MS, Ib } },
9168   },
9169   {
9170     /* MOD_0F71_REG_4 */
9171     { "(bad)",          { XX } },
9172     { "psraw",          { MS, Ib } },
9173   },
9174   {
9175     /* MOD_0F71_REG_6 */
9176     { "(bad)",          { XX } },
9177     { "psllw",          { MS, Ib } },
9178   },
9179   {
9180     /* MOD_0F72_REG_2 */
9181     { "(bad)",          { XX } },
9182     { "psrld",          { MS, Ib } },
9183   },
9184   {
9185     /* MOD_0F72_REG_4 */
9186     { "(bad)",          { XX } },
9187     { "psrad",          { MS, Ib } },
9188   },
9189   {
9190     /* MOD_0F72_REG_6 */
9191     { "(bad)",          { XX } },
9192     { "pslld",          { MS, Ib } },
9193   },
9194   {
9195     /* MOD_0F73_REG_2 */
9196     { "(bad)",          { XX } },
9197     { "psrlq",          { MS, Ib } },
9198   },
9199   {
9200     /* MOD_0F73_REG_3 */
9201     { "(bad)",          { XX } },
9202     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9203   },
9204   {
9205     /* MOD_0F73_REG_6 */
9206     { "(bad)",          { XX } },
9207     { "psllq",          { MS, Ib } },
9208   },
9209   {
9210     /* MOD_0F73_REG_7 */
9211     { "(bad)",          { XX } },
9212     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9213   },
9214   {
9215     /* MOD_0FAE_REG_0 */
9216     { "fxsave",         { M } },
9217     { "(bad)",          { XX } },
9218   },
9219   {
9220     /* MOD_0FAE_REG_1 */
9221     { "fxrstor",        { M } },
9222     { "(bad)",          { XX } },
9223   },
9224   {
9225     /* MOD_0FAE_REG_2 */
9226     { "ldmxcsr",        { Md } },
9227     { "(bad)",          { XX } },
9228   },
9229   {
9230     /* MOD_0FAE_REG_3 */
9231     { "stmxcsr",        { Md } },
9232     { "(bad)",          { XX } },
9233   },
9234   {
9235     /* MOD_0FAE_REG_4 */
9236     { "xsave",          { M } },
9237     { "(bad)",          { XX } },
9238   },
9239   {
9240     /* MOD_0FAE_REG_5 */
9241     { "xrstor",         { M } },
9242     { RM_TABLE (RM_0FAE_REG_5) },
9243   },
9244   {
9245     /* MOD_0FAE_REG_6 */
9246     { "xsaveopt",       { M } },
9247     { RM_TABLE (RM_0FAE_REG_6) },
9248   },
9249   {
9250     /* MOD_0FAE_REG_7 */
9251     { "clflush",        { Mb } },
9252     { RM_TABLE (RM_0FAE_REG_7) },
9253   },
9254   {
9255     /* MOD_0FB2 */
9256     { "lssS",           { Gv, Mp } },
9257     { "(bad)",          { XX } },
9258   },
9259   {
9260     /* MOD_0FB4 */
9261     { "lfsS",           { Gv, Mp } },
9262     { "(bad)",          { XX } },
9263   },
9264   {
9265     /* MOD_0FB5 */
9266     { "lgsS",           { Gv, Mp } },
9267     { "(bad)",          { XX } },
9268   },
9269   {
9270     /* MOD_0FC7_REG_6 */
9271     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9272     { "(bad)",          { XX } },
9273   },
9274   {
9275     /* MOD_0FC7_REG_7 */
9276     { "vmptrst",        { Mq } },
9277     { "(bad)",          { XX } },
9278   },
9279   {
9280     /* MOD_0FD7 */
9281     { "(bad)",          { XX } },
9282     { "pmovmskb",       { Gdq, MS } },
9283   },
9284   {
9285     /* MOD_0FE7_PREFIX_2 */
9286     { "movntdq",        { Mx, XM } },
9287     { "(bad)",          { XX } },
9288   },
9289   {
9290     /* MOD_0FF0_PREFIX_3 */
9291     { "lddqu",          { XM, M } },
9292     { "(bad)",          { XX } },
9293   },
9294   {
9295     /* MOD_0F382A_PREFIX_2 */
9296     { "movntdqa",       { XM, Mx } },
9297     { "(bad)",          { XX } },
9298   },
9299   {
9300     /* MOD_62_32BIT */
9301     { "bound{S|}",      { Gv, Ma } },
9302     { "(bad)",          { XX } },
9303   },
9304   {
9305     /* MOD_C4_32BIT */
9306     { "lesS",           { Gv, Mp } },
9307     { VEX_C4_TABLE (VEX_0F) },
9308   },
9309   {
9310     /* MOD_C5_32BIT */
9311     { "ldsS",           { Gv, Mp } },
9312     { VEX_C5_TABLE (VEX_0F) },
9313   },
9314   {
9315     /* MOD_VEX_12_PREFIX_0 */
9316     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9317     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9318   },
9319   {
9320     /* MOD_VEX_13 */
9321     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9322     { "(bad)",          { XX } },
9323   },
9324   {
9325     /* MOD_VEX_16_PREFIX_0 */
9326     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9327     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9328   },
9329   {
9330     /* MOD_VEX_17 */
9331     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9332     { "(bad)",          { XX } },
9333   },
9334   {
9335     /* MOD_VEX_2B */
9336     { VEX_LEN_TABLE (VEX_LEN_2B_M_0) },
9337     { "(bad)",          { XX } },
9338   },
9339   {
9340     /* MOD_VEX_51 */
9341     { "(bad)",          { XX } },
9342     { "vmovmskpX",      { Gdq, XS } },
9343   },
9344   {
9345     /* MOD_VEX_71_REG_2 */
9346     { "(bad)",          { XX } },
9347     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
9348   },
9349   {
9350     /* MOD_VEX_71_REG_4 */
9351     { "(bad)",          { XX } },
9352     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
9353   },
9354   {
9355     /* MOD_VEX_71_REG_6 */
9356     { "(bad)",          { XX } },
9357     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
9358   },
9359   {
9360     /* MOD_VEX_72_REG_2 */
9361     { "(bad)",          { XX } },
9362     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
9363   },
9364   {
9365     /* MOD_VEX_72_REG_4 */
9366     { "(bad)",          { XX } },
9367     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
9368   },
9369   {
9370     /* MOD_VEX_72_REG_6 */
9371     { "(bad)",          { XX } },
9372     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
9373   },
9374   {
9375     /* MOD_VEX_73_REG_2 */
9376     { "(bad)",          { XX } },
9377     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
9378   },
9379   {
9380     /* MOD_VEX_73_REG_3 */
9381     { "(bad)",          { XX } },
9382     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
9383   },
9384   {
9385     /* MOD_VEX_73_REG_6 */
9386     { "(bad)",          { XX } },
9387     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
9388   },
9389   {
9390     /* MOD_VEX_73_REG_7 */
9391     { "(bad)",          { XX } },
9392     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
9393   },
9394   {
9395     /* MOD_VEX_AE_REG_2 */
9396     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9397     { "(bad)",          { XX } },
9398   },
9399   {
9400     /* MOD_VEX_AE_REG_3 */
9401     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
9402     { "(bad)",          { XX } },
9403   },
9404   {
9405     /* MOD_VEX_D7_PREFIX_2 */
9406     { "(bad)",          { XX } },
9407     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
9408   },
9409   {
9410     /* MOD_VEX_E7_PREFIX_2 */
9411     { VEX_LEN_TABLE (VEX_LEN_E7_P_2_M_0) },
9412     { "(bad)",          { XX } },
9413   },
9414   {
9415     /* MOD_VEX_F0_PREFIX_3 */
9416     { "vlddqu",         { XM, M } },
9417     { "(bad)",          { XX } },
9418   },
9419   {
9420     /* MOD_VEX_3818_PREFIX_2 */
9421     { "vbroadcastss",   { XM, Md } },
9422     { "(bad)",          { XX } },
9423   },
9424   {
9425     /* MOD_VEX_3819_PREFIX_2 */
9426     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
9427     { "(bad)",          { XX } },
9428   },
9429   {
9430     /* MOD_VEX_381A_PREFIX_2 */
9431     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
9432     { "(bad)",          { XX } },
9433   },
9434   {
9435     /* MOD_VEX_382A_PREFIX_2 */
9436     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
9437     { "(bad)",          { XX } },
9438   },
9439   {
9440     /* MOD_VEX_382C_PREFIX_2 */
9441     { "vmaskmovps",     { XM, Vex, Mx } },
9442     { "(bad)",          { XX } },
9443   },
9444   {
9445     /* MOD_VEX_382D_PREFIX_2 */
9446     { "vmaskmovpd",     { XM, Vex, Mx } },
9447     { "(bad)",          { XX } },
9448   },
9449   {
9450     /* MOD_VEX_382E_PREFIX_2 */
9451     { "vmaskmovps",     { Mx, Vex, XM } },
9452     { "(bad)",          { XX } },
9453   },
9454   {
9455     /* MOD_VEX_382F_PREFIX_2 */
9456     { "vmaskmovpd",     { Mx, Vex, XM } },
9457     { "(bad)",          { XX } },
9458   },
9459 };
9460
9461 static const struct dis386 rm_table[][8] = {
9462   {
9463     /* RM_0F01_REG_0 */
9464     { "(bad)",          { XX } },
9465     { "vmcall",         { Skip_MODRM } },
9466     { "vmlaunch",       { Skip_MODRM } },
9467     { "vmresume",       { Skip_MODRM } },
9468     { "vmxoff",         { Skip_MODRM } },
9469     { "(bad)",          { XX } },
9470     { "(bad)",          { XX } },
9471     { "(bad)",          { XX } },
9472   },
9473   {
9474     /* RM_0F01_REG_1 */
9475     { "monitor",        { { OP_Monitor, 0 } } },
9476     { "mwait",          { { OP_Mwait, 0 } } },
9477     { "(bad)",          { XX } },
9478     { "(bad)",          { XX } },
9479     { "(bad)",          { XX } },
9480     { "(bad)",          { XX } },
9481     { "(bad)",          { XX } },
9482     { "(bad)",          { XX } },
9483   },
9484   {
9485     /* RM_0F01_REG_2 */
9486     { "xgetbv",         { Skip_MODRM } },
9487     { "xsetbv",         { Skip_MODRM } },
9488     { "(bad)",          { XX } },
9489     { "(bad)",          { XX } },
9490     { "(bad)",          { XX } },
9491     { "(bad)",          { XX } },
9492     { "(bad)",          { XX } },
9493     { "(bad)",          { XX } },
9494   },
9495   {
9496     /* RM_0F01_REG_3 */
9497     { "vmrun",          { Skip_MODRM } },
9498     { "vmmcall",        { Skip_MODRM } },
9499     { "vmload",         { Skip_MODRM } },
9500     { "vmsave",         { Skip_MODRM } },
9501     { "stgi",           { Skip_MODRM } },
9502     { "clgi",           { Skip_MODRM } },
9503     { "skinit",         { Skip_MODRM } },
9504     { "invlpga",        { Skip_MODRM } },
9505   },
9506   {
9507     /* RM_0F01_REG_7 */
9508     { "swapgs",         { Skip_MODRM } },
9509     { "rdtscp",         { Skip_MODRM } },
9510     { "(bad)",          { XX } },
9511     { "(bad)",          { XX } },
9512     { "(bad)",          { XX } },
9513     { "(bad)",          { XX } },
9514     { "(bad)",          { XX } },
9515     { "(bad)",          { XX } },
9516   },
9517   {
9518     /* RM_0FAE_REG_5 */
9519     { "lfence",         { Skip_MODRM } },
9520     { "(bad)",          { XX } },
9521     { "(bad)",          { XX } },
9522     { "(bad)",          { XX } },
9523     { "(bad)",          { XX } },
9524     { "(bad)",          { XX } },
9525     { "(bad)",          { XX } },
9526     { "(bad)",          { XX } },
9527   },
9528   {
9529     /* RM_0FAE_REG_6 */
9530     { "mfence",         { Skip_MODRM } },
9531     { "(bad)",          { XX } },
9532     { "(bad)",          { XX } },
9533     { "(bad)",          { XX } },
9534     { "(bad)",          { XX } },
9535     { "(bad)",          { XX } },
9536     { "(bad)",          { XX } },
9537     { "(bad)",          { XX } },
9538   },
9539   {
9540     /* RM_0FAE_REG_7 */
9541     { "sfence",         { Skip_MODRM } },
9542     { "(bad)",          { XX } },
9543     { "(bad)",          { XX } },
9544     { "(bad)",          { XX } },
9545     { "(bad)",          { XX } },
9546     { "(bad)",          { XX } },
9547     { "(bad)",          { XX } },
9548     { "(bad)",          { XX } },
9549   },
9550 };
9551
9552 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9553
9554 static void
9555 ckprefix (void)
9556 {
9557   int newrex;
9558   rex = 0;
9559   rex_original = 0;
9560   rex_ignored = 0;
9561   prefixes = 0;
9562   used_prefixes = 0;
9563   rex_used = 0;
9564   while (1)
9565     {
9566       FETCH_DATA (the_info, codep + 1);
9567       newrex = 0;
9568       switch (*codep)
9569         {
9570         /* REX prefixes family.  */
9571         case 0x40:
9572         case 0x41:
9573         case 0x42:
9574         case 0x43:
9575         case 0x44:
9576         case 0x45:
9577         case 0x46:
9578         case 0x47:
9579         case 0x48:
9580         case 0x49:
9581         case 0x4a:
9582         case 0x4b:
9583         case 0x4c:
9584         case 0x4d:
9585         case 0x4e:
9586         case 0x4f:
9587             if (address_mode == mode_64bit)
9588               newrex = *codep;
9589             else
9590               return;
9591           break;
9592         case 0xf3:
9593           prefixes |= PREFIX_REPZ;
9594           break;
9595         case 0xf2:
9596           prefixes |= PREFIX_REPNZ;
9597           break;
9598         case 0xf0:
9599           prefixes |= PREFIX_LOCK;
9600           break;
9601         case 0x2e:
9602           prefixes |= PREFIX_CS;
9603           break;
9604         case 0x36:
9605           prefixes |= PREFIX_SS;
9606           break;
9607         case 0x3e:
9608           prefixes |= PREFIX_DS;
9609           break;
9610         case 0x26:
9611           prefixes |= PREFIX_ES;
9612           break;
9613         case 0x64:
9614           prefixes |= PREFIX_FS;
9615           break;
9616         case 0x65:
9617           prefixes |= PREFIX_GS;
9618           break;
9619         case 0x66:
9620           prefixes |= PREFIX_DATA;
9621           break;
9622         case 0x67:
9623           prefixes |= PREFIX_ADDR;
9624           break;
9625         case FWAIT_OPCODE:
9626           /* fwait is really an instruction.  If there are prefixes
9627              before the fwait, they belong to the fwait, *not* to the
9628              following instruction.  */
9629           if (prefixes || rex)
9630             {
9631               prefixes |= PREFIX_FWAIT;
9632               codep++;
9633               return;
9634             }
9635           prefixes = PREFIX_FWAIT;
9636           break;
9637         default:
9638           return;
9639         }
9640       /* Rex is ignored when followed by another prefix.  */
9641       if (rex)
9642         {
9643           rex_used = rex;
9644           return;
9645         }
9646       rex = newrex;
9647       rex_original = rex;
9648       codep++;
9649     }
9650 }
9651
9652 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9653    prefix byte.  */
9654
9655 static const char *
9656 prefix_name (int pref, int sizeflag)
9657 {
9658   static const char *rexes [16] =
9659     {
9660       "rex",            /* 0x40 */
9661       "rex.B",          /* 0x41 */
9662       "rex.X",          /* 0x42 */
9663       "rex.XB",         /* 0x43 */
9664       "rex.R",          /* 0x44 */
9665       "rex.RB",         /* 0x45 */
9666       "rex.RX",         /* 0x46 */
9667       "rex.RXB",        /* 0x47 */
9668       "rex.W",          /* 0x48 */
9669       "rex.WB",         /* 0x49 */
9670       "rex.WX",         /* 0x4a */
9671       "rex.WXB",        /* 0x4b */
9672       "rex.WR",         /* 0x4c */
9673       "rex.WRB",        /* 0x4d */
9674       "rex.WRX",        /* 0x4e */
9675       "rex.WRXB",       /* 0x4f */
9676     };
9677
9678   switch (pref)
9679     {
9680     /* REX prefixes family.  */
9681     case 0x40:
9682     case 0x41:
9683     case 0x42:
9684     case 0x43:
9685     case 0x44:
9686     case 0x45:
9687     case 0x46:
9688     case 0x47:
9689     case 0x48:
9690     case 0x49:
9691     case 0x4a:
9692     case 0x4b:
9693     case 0x4c:
9694     case 0x4d:
9695     case 0x4e:
9696     case 0x4f:
9697       return rexes [pref - 0x40];
9698     case 0xf3:
9699       return "repz";
9700     case 0xf2:
9701       return "repnz";
9702     case 0xf0:
9703       return "lock";
9704     case 0x2e:
9705       return "cs";
9706     case 0x36:
9707       return "ss";
9708     case 0x3e:
9709       return "ds";
9710     case 0x26:
9711       return "es";
9712     case 0x64:
9713       return "fs";
9714     case 0x65:
9715       return "gs";
9716     case 0x66:
9717       return (sizeflag & DFLAG) ? "data16" : "data32";
9718     case 0x67:
9719       if (address_mode == mode_64bit)
9720         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9721       else
9722         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9723     case FWAIT_OPCODE:
9724       return "fwait";
9725     default:
9726       return NULL;
9727     }
9728 }
9729
9730 static char op_out[MAX_OPERANDS][100];
9731 static int op_ad, op_index[MAX_OPERANDS];
9732 static int two_source_ops;
9733 static bfd_vma op_address[MAX_OPERANDS];
9734 static bfd_vma op_riprel[MAX_OPERANDS];
9735 static bfd_vma start_pc;
9736
9737 /*
9738  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9739  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9740  *   section of the "Virtual 8086 Mode" chapter.)
9741  * 'pc' should be the address of this instruction, it will
9742  *   be used to print the target address if this is a relative jump or call
9743  * The function returns the length of this instruction in bytes.
9744  */
9745
9746 static char intel_syntax;
9747 static char intel_mnemonic = !SYSV386_COMPAT;
9748 static char open_char;
9749 static char close_char;
9750 static char separator_char;
9751 static char scale_char;
9752
9753 /* Here for backwards compatibility.  When gdb stops using
9754    print_insn_i386_att and print_insn_i386_intel these functions can
9755    disappear, and print_insn_i386 be merged into print_insn.  */
9756 int
9757 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9758 {
9759   intel_syntax = 0;
9760
9761   return print_insn (pc, info);
9762 }
9763
9764 int
9765 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9766 {
9767   intel_syntax = 1;
9768
9769   return print_insn (pc, info);
9770 }
9771
9772 int
9773 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9774 {
9775   intel_syntax = -1;
9776
9777   return print_insn (pc, info);
9778 }
9779
9780 void
9781 print_i386_disassembler_options (FILE *stream)
9782 {
9783   fprintf (stream, _("\n\
9784 The following i386/x86-64 specific disassembler options are supported for use\n\
9785 with the -M switch (multiple options should be separated by commas):\n"));
9786
9787   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9788   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9789   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9790   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9791   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9792   fprintf (stream, _("  att-mnemonic\n"
9793                      "              Display instruction in AT&T mnemonic\n"));
9794   fprintf (stream, _("  intel-mnemonic\n"
9795                      "              Display instruction in Intel mnemonic\n"));
9796   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9797   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9798   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9799   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9800   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9801   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9802 }
9803
9804 /* Get a pointer to struct dis386 with a valid name.  */
9805
9806 static const struct dis386 *
9807 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9808 {
9809   int index, vex_table_index;
9810
9811   if (dp->name != NULL)
9812     return dp;
9813
9814   switch (dp->op[0].bytemode)
9815     {
9816     case USE_REG_TABLE:
9817       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9818       break;
9819
9820     case USE_MOD_TABLE:
9821       index = modrm.mod == 0x3 ? 1 : 0;
9822       dp = &mod_table[dp->op[1].bytemode][index];
9823       break;
9824
9825     case USE_RM_TABLE:
9826       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9827       break;
9828
9829     case USE_PREFIX_TABLE:
9830       if (need_vex)
9831         {
9832           /* The prefix in VEX is implicit.  */
9833           switch (vex.prefix)
9834             {
9835             case 0:
9836               index = 0;
9837               break;
9838             case REPE_PREFIX_OPCODE:
9839               index = 1;
9840               break;
9841             case DATA_PREFIX_OPCODE:
9842               index = 2;
9843               break;
9844             case REPNE_PREFIX_OPCODE:
9845               index = 3;
9846               break;
9847             default:
9848               abort ();
9849               break;
9850             }
9851         }
9852       else
9853         {
9854           index = 0;
9855           used_prefixes |= (prefixes & PREFIX_REPZ);
9856           if (prefixes & PREFIX_REPZ)
9857             {
9858               index = 1;
9859               repz_prefix = NULL;
9860             }
9861           else
9862             {
9863               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9864                  PREFIX_DATA.  */
9865               used_prefixes |= (prefixes & PREFIX_REPNZ);
9866               if (prefixes & PREFIX_REPNZ)
9867                 {
9868                   index = 3;
9869                   repnz_prefix = NULL;
9870                 }
9871               else
9872                 {
9873                   used_prefixes |= (prefixes & PREFIX_DATA);
9874                   if (prefixes & PREFIX_DATA)
9875                     {
9876                       index = 2;
9877                       data_prefix = NULL;
9878                     }
9879                 }
9880             }
9881         }
9882       dp = &prefix_table[dp->op[1].bytemode][index];
9883       break;
9884
9885     case USE_X86_64_TABLE:
9886       index = address_mode == mode_64bit ? 1 : 0;
9887       dp = &x86_64_table[dp->op[1].bytemode][index];
9888       break;
9889
9890     case USE_3BYTE_TABLE:
9891       FETCH_DATA (info, codep + 2);
9892       index = *codep++;
9893       dp = &three_byte_table[dp->op[1].bytemode][index];
9894       modrm.mod = (*codep >> 6) & 3;
9895       modrm.reg = (*codep >> 3) & 7;
9896       modrm.rm = *codep & 7;
9897       break;
9898
9899     case USE_VEX_LEN_TABLE:
9900       if (!need_vex)
9901         abort ();
9902
9903       switch (vex.length)
9904         {
9905         case 128:
9906           index = 0;
9907           break;
9908         case 256:
9909           index = 1;
9910           break;
9911         default:
9912           abort ();
9913           break;
9914         }
9915
9916       dp = &vex_len_table[dp->op[1].bytemode][index];
9917       break;
9918
9919     case USE_VEX_C4_TABLE:
9920       FETCH_DATA (info, codep + 3);
9921       /* All bits in the REX prefix are ignored.  */
9922       rex_ignored = rex;
9923       rex = ~(*codep >> 5) & 0x7;
9924       switch ((*codep & 0x1f))
9925         {
9926         default:
9927           BadOp ();
9928         case 0x1:
9929           vex_table_index = 0;
9930           break;
9931         case 0x2:
9932           vex_table_index = 1;
9933           break;
9934         case 0x3:
9935           vex_table_index = 2;
9936           break;
9937         }
9938       codep++;
9939       vex.w = *codep & 0x80;
9940       if (vex.w && address_mode == mode_64bit)
9941         rex |= REX_W;
9942
9943       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9944       if (address_mode != mode_64bit
9945           && vex.register_specifier > 0x7)
9946         BadOp ();
9947
9948       vex.length = (*codep & 0x4) ? 256 : 128;
9949       switch ((*codep & 0x3))
9950         {
9951         case 0:
9952           vex.prefix = 0;
9953           break;
9954         case 1:
9955           vex.prefix = DATA_PREFIX_OPCODE;
9956           break;
9957         case 2:
9958           vex.prefix = REPE_PREFIX_OPCODE;
9959           break;
9960         case 3:
9961           vex.prefix = REPNE_PREFIX_OPCODE;
9962           break;
9963         }
9964       need_vex = 1;
9965       need_vex_reg = 1;
9966       codep++;
9967       index = *codep++;
9968       dp = &vex_table[vex_table_index][index];
9969       /* There is no MODRM byte for VEX [82|77].  */
9970       if (index != 0x77 && index != 0x82)
9971         {
9972           FETCH_DATA (info, codep + 1);
9973           modrm.mod = (*codep >> 6) & 3;
9974           modrm.reg = (*codep >> 3) & 7;
9975           modrm.rm = *codep & 7;
9976         }
9977       break;
9978
9979     case USE_VEX_C5_TABLE:
9980       FETCH_DATA (info, codep + 2);
9981       /* All bits in the REX prefix are ignored.  */
9982       rex_ignored = rex;
9983       rex = (*codep & 0x80) ? 0 : REX_R;
9984
9985       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9986       if (address_mode != mode_64bit
9987           && vex.register_specifier > 0x7)
9988         BadOp ();
9989
9990       vex.length = (*codep & 0x4) ? 256 : 128;
9991       switch ((*codep & 0x3))
9992         {
9993         case 0:
9994           vex.prefix = 0;
9995           break;
9996         case 1:
9997           vex.prefix = DATA_PREFIX_OPCODE;
9998           break;
9999         case 2:
10000           vex.prefix = REPE_PREFIX_OPCODE;
10001           break;
10002         case 3:
10003           vex.prefix = REPNE_PREFIX_OPCODE;
10004           break;
10005         }
10006       need_vex = 1;
10007       need_vex_reg = 1;
10008       codep++;
10009       index = *codep++;
10010       dp = &vex_table[dp->op[1].bytemode][index];
10011       /* There is no MODRM byte for VEX [82|77].  */
10012       if (index != 0x77 && index != 0x82)
10013         {
10014           FETCH_DATA (info, codep + 1);
10015           modrm.mod = (*codep >> 6) & 3;
10016           modrm.reg = (*codep >> 3) & 7;
10017           modrm.rm = *codep & 7;
10018         }
10019       break;
10020
10021     default:
10022       oappend (INTERNAL_DISASSEMBLER_ERROR);
10023       return NULL;
10024     }
10025
10026   if (dp->name != NULL)
10027     return dp;
10028   else
10029     return get_valid_dis386 (dp, info);
10030 }
10031
10032 static int
10033 print_insn (bfd_vma pc, disassemble_info *info)
10034 {
10035   const struct dis386 *dp;
10036   int i;
10037   char *op_txt[MAX_OPERANDS];
10038   int needcomma;
10039   int sizeflag;
10040   const char *p;
10041   struct dis_private priv;
10042   unsigned char op;
10043   char prefix_obuf[32];
10044   char *prefix_obufp;
10045
10046   if (info->mach == bfd_mach_x86_64_intel_syntax
10047       || info->mach == bfd_mach_x86_64)
10048     address_mode = mode_64bit;
10049   else
10050     address_mode = mode_32bit;
10051
10052   if (intel_syntax == (char) -1)
10053     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
10054                     || info->mach == bfd_mach_x86_64_intel_syntax);
10055
10056   if (info->mach == bfd_mach_i386_i386
10057       || info->mach == bfd_mach_x86_64
10058       || info->mach == bfd_mach_i386_i386_intel_syntax
10059       || info->mach == bfd_mach_x86_64_intel_syntax)
10060     priv.orig_sizeflag = AFLAG | DFLAG;
10061   else if (info->mach == bfd_mach_i386_i8086)
10062     priv.orig_sizeflag = 0;
10063   else
10064     abort ();
10065
10066   for (p = info->disassembler_options; p != NULL; )
10067     {
10068       if (CONST_STRNEQ (p, "x86-64"))
10069         {
10070           address_mode = mode_64bit;
10071           priv.orig_sizeflag = AFLAG | DFLAG;
10072         }
10073       else if (CONST_STRNEQ (p, "i386"))
10074         {
10075           address_mode = mode_32bit;
10076           priv.orig_sizeflag = AFLAG | DFLAG;
10077         }
10078       else if (CONST_STRNEQ (p, "i8086"))
10079         {
10080           address_mode = mode_16bit;
10081           priv.orig_sizeflag = 0;
10082         }
10083       else if (CONST_STRNEQ (p, "intel"))
10084         {
10085           intel_syntax = 1;
10086           if (CONST_STRNEQ (p + 5, "-mnemonic"))
10087             intel_mnemonic = 1;
10088         }
10089       else if (CONST_STRNEQ (p, "att"))
10090         {
10091           intel_syntax = 0;
10092           if (CONST_STRNEQ (p + 3, "-mnemonic"))
10093             intel_mnemonic = 0;
10094         }
10095       else if (CONST_STRNEQ (p, "addr"))
10096         {
10097           if (address_mode == mode_64bit)
10098             {
10099               if (p[4] == '3' && p[5] == '2')
10100                 priv.orig_sizeflag &= ~AFLAG;
10101               else if (p[4] == '6' && p[5] == '4')
10102                 priv.orig_sizeflag |= AFLAG;
10103             }
10104           else
10105             {
10106               if (p[4] == '1' && p[5] == '6')
10107                 priv.orig_sizeflag &= ~AFLAG;
10108               else if (p[4] == '3' && p[5] == '2')
10109                 priv.orig_sizeflag |= AFLAG;
10110             }
10111         }
10112       else if (CONST_STRNEQ (p, "data"))
10113         {
10114           if (p[4] == '1' && p[5] == '6')
10115             priv.orig_sizeflag &= ~DFLAG;
10116           else if (p[4] == '3' && p[5] == '2')
10117             priv.orig_sizeflag |= DFLAG;
10118         }
10119       else if (CONST_STRNEQ (p, "suffix"))
10120         priv.orig_sizeflag |= SUFFIX_ALWAYS;
10121
10122       p = strchr (p, ',');
10123       if (p != NULL)
10124         p++;
10125     }
10126
10127   if (intel_syntax)
10128     {
10129       names64 = intel_names64;
10130       names32 = intel_names32;
10131       names16 = intel_names16;
10132       names8 = intel_names8;
10133       names8rex = intel_names8rex;
10134       names_seg = intel_names_seg;
10135       index64 = intel_index64;
10136       index32 = intel_index32;
10137       index16 = intel_index16;
10138       open_char = '[';
10139       close_char = ']';
10140       separator_char = '+';
10141       scale_char = '*';
10142     }
10143   else
10144     {
10145       names64 = att_names64;
10146       names32 = att_names32;
10147       names16 = att_names16;
10148       names8 = att_names8;
10149       names8rex = att_names8rex;
10150       names_seg = att_names_seg;
10151       index64 = att_index64;
10152       index32 = att_index32;
10153       index16 = att_index16;
10154       open_char = '(';
10155       close_char =  ')';
10156       separator_char = ',';
10157       scale_char = ',';
10158     }
10159
10160   /* The output looks better if we put 7 bytes on a line, since that
10161      puts most long word instructions on a single line.  */
10162   info->bytes_per_line = 7;
10163
10164   info->private_data = &priv;
10165   priv.max_fetched = priv.the_buffer;
10166   priv.insn_start = pc;
10167
10168   obuf[0] = 0;
10169   for (i = 0; i < MAX_OPERANDS; ++i)
10170     {
10171       op_out[i][0] = 0;
10172       op_index[i] = -1;
10173     }
10174
10175   the_info = info;
10176   start_pc = pc;
10177   start_codep = priv.the_buffer;
10178   codep = priv.the_buffer;
10179
10180   if (setjmp (priv.bailout) != 0)
10181     {
10182       const char *name;
10183
10184       /* Getting here means we tried for data but didn't get it.  That
10185          means we have an incomplete instruction of some sort.  Just
10186          print the first byte as a prefix or a .byte pseudo-op.  */
10187       if (codep > priv.the_buffer)
10188         {
10189           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10190           if (name != NULL)
10191             (*info->fprintf_func) (info->stream, "%s", name);
10192           else
10193             {
10194               /* Just print the first byte as a .byte instruction.  */
10195               (*info->fprintf_func) (info->stream, ".byte 0x%x",
10196                                      (unsigned int) priv.the_buffer[0]);
10197             }
10198
10199           return 1;
10200         }
10201
10202       return -1;
10203     }
10204
10205   obufp = obuf;
10206   ckprefix ();
10207
10208   insn_codep = codep;
10209   sizeflag = priv.orig_sizeflag;
10210
10211   FETCH_DATA (info, codep + 1);
10212   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10213
10214   if (((prefixes & PREFIX_FWAIT)
10215        && ((*codep < 0xd8) || (*codep > 0xdf)))
10216       || (rex && rex_used))
10217     {
10218       const char *name;
10219
10220       /* fwait not followed by floating point instruction, or rex followed
10221          by other prefixes.  Print the first prefix.  */
10222       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10223       if (name == NULL)
10224         name = INTERNAL_DISASSEMBLER_ERROR;
10225       (*info->fprintf_func) (info->stream, "%s", name);
10226       return 1;
10227     }
10228
10229   op = 0;
10230   if (*codep == 0x0f)
10231     {
10232       unsigned char threebyte;
10233       FETCH_DATA (info, codep + 2);
10234       threebyte = *++codep;
10235       dp = &dis386_twobyte[threebyte];
10236       need_modrm = twobyte_has_modrm[*codep];
10237       codep++;
10238     }
10239   else
10240     {
10241       dp = &dis386[*codep];
10242       need_modrm = onebyte_has_modrm[*codep];
10243       codep++;
10244     }
10245
10246   if ((prefixes & PREFIX_REPZ))
10247     {
10248       repz_prefix = "repz ";
10249       used_prefixes |= PREFIX_REPZ;
10250     }
10251   else
10252     repz_prefix = NULL;
10253
10254   if ((prefixes & PREFIX_REPNZ))
10255     {
10256       repnz_prefix = "repnz ";
10257       used_prefixes |= PREFIX_REPNZ;
10258     }
10259   else
10260     repnz_prefix = NULL;
10261
10262   if ((prefixes & PREFIX_LOCK))
10263     {
10264       lock_prefix = "lock ";
10265       used_prefixes |= PREFIX_LOCK;
10266     }
10267   else
10268     lock_prefix = NULL;
10269
10270   addr_prefix = NULL;
10271   if (prefixes & PREFIX_ADDR)
10272     {
10273       sizeflag ^= AFLAG;
10274       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
10275         {
10276           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10277             addr_prefix = "addr32 ";
10278           else
10279             addr_prefix = "addr16 ";
10280           used_prefixes |= PREFIX_ADDR;
10281         }
10282     }
10283
10284   data_prefix = NULL;
10285   if ((prefixes & PREFIX_DATA))
10286     {
10287       sizeflag ^= DFLAG;
10288       if (dp->op[2].bytemode == cond_jump_mode
10289           && dp->op[0].bytemode == v_mode
10290           && !intel_syntax)
10291         {
10292           if (sizeflag & DFLAG)
10293             data_prefix = "data32 ";
10294           else
10295             data_prefix = "data16 ";
10296           used_prefixes |= PREFIX_DATA;
10297         }
10298     }
10299
10300   if (need_modrm)
10301     {
10302       FETCH_DATA (info, codep + 1);
10303       modrm.mod = (*codep >> 6) & 3;
10304       modrm.reg = (*codep >> 3) & 7;
10305       modrm.rm = *codep & 7;
10306     }
10307
10308   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10309     {
10310       dofloat (sizeflag);
10311     }
10312   else
10313     {
10314       need_vex = 0;
10315       need_vex_reg = 0;
10316       vex_w_done = 0;
10317       dp = get_valid_dis386 (dp, info);
10318       if (dp != NULL && putop (dp->name, sizeflag) == 0)
10319         {
10320           for (i = 0; i < MAX_OPERANDS; ++i)
10321             {
10322               obufp = op_out[i];
10323               op_ad = MAX_OPERANDS - 1 - i;
10324               if (dp->op[i].rtn)
10325                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10326             }
10327         }
10328     }
10329
10330   /* See if any prefixes were not used.  If so, print the first one
10331      separately.  If we don't do this, we'll wind up printing an
10332      instruction stream which does not precisely correspond to the
10333      bytes we are disassembling.  */
10334   if ((prefixes & ~used_prefixes) != 0)
10335     {
10336       const char *name;
10337
10338       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10339       if (name == NULL)
10340         name = INTERNAL_DISASSEMBLER_ERROR;
10341       (*info->fprintf_func) (info->stream, "%s", name);
10342       return 1;
10343     }
10344   if ((rex_original & ~rex_used) || rex_ignored)
10345     {
10346       const char *name;
10347       name = prefix_name (rex_original, priv.orig_sizeflag);
10348       if (name == NULL)
10349         name = INTERNAL_DISASSEMBLER_ERROR;
10350       (*info->fprintf_func) (info->stream, "%s ", name);
10351     }
10352
10353   prefix_obuf[0] = 0;
10354   prefix_obufp = prefix_obuf;
10355   if (lock_prefix)
10356     prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
10357   if (repz_prefix)
10358     prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
10359   if (repnz_prefix)
10360     prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
10361   if (addr_prefix)
10362     prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
10363   if (data_prefix)
10364     prefix_obufp = stpcpy (prefix_obufp, data_prefix);
10365
10366   if (prefix_obuf[0] != 0)
10367     (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
10368
10369   obufp = mnemonicendp;
10370   for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
10371     oappend (" ");
10372   oappend (" ");
10373   (*info->fprintf_func) (info->stream, "%s", obuf);
10374
10375   /* The enter and bound instructions are printed with operands in the same
10376      order as the intel book; everything else is printed in reverse order.  */
10377   if (intel_syntax || two_source_ops)
10378     {
10379       bfd_vma riprel;
10380
10381       for (i = 0; i < MAX_OPERANDS; ++i)
10382         op_txt[i] = op_out[i];
10383
10384       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10385         {
10386           op_ad = op_index[i];
10387           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10388           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10389           riprel = op_riprel[i];
10390           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10391           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10392         }
10393     }
10394   else
10395     {
10396       for (i = 0; i < MAX_OPERANDS; ++i)
10397         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10398     }
10399
10400   needcomma = 0;
10401   for (i = 0; i < MAX_OPERANDS; ++i)
10402     if (*op_txt[i])
10403       {
10404         if (needcomma)
10405           (*info->fprintf_func) (info->stream, ",");
10406         if (op_index[i] != -1 && !op_riprel[i])
10407           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10408         else
10409           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10410         needcomma = 1;
10411       }
10412
10413   for (i = 0; i < MAX_OPERANDS; i++)
10414     if (op_index[i] != -1 && op_riprel[i])
10415       {
10416         (*info->fprintf_func) (info->stream, "        # ");
10417         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10418                                                 + op_address[op_index[i]]), info);
10419         break;
10420       }
10421   return codep - priv.the_buffer;
10422 }
10423
10424 static const char *float_mem[] = {
10425   /* d8 */
10426   "fadd{s|}",
10427   "fmul{s|}",
10428   "fcom{s|}",
10429   "fcomp{s|}",
10430   "fsub{s|}",
10431   "fsubr{s|}",
10432   "fdiv{s|}",
10433   "fdivr{s|}",
10434   /* d9 */
10435   "fld{s|}",
10436   "(bad)",
10437   "fst{s|}",
10438   "fstp{s|}",
10439   "fldenvIC",
10440   "fldcw",
10441   "fNstenvIC",
10442   "fNstcw",
10443   /* da */
10444   "fiadd{l|}",
10445   "fimul{l|}",
10446   "ficom{l|}",
10447   "ficomp{l|}",
10448   "fisub{l|}",
10449   "fisubr{l|}",
10450   "fidiv{l|}",
10451   "fidivr{l|}",
10452   /* db */
10453   "fild{l|}",
10454   "fisttp{l|}",
10455   "fist{l|}",
10456   "fistp{l|}",
10457   "(bad)",
10458   "fld{t||t|}",
10459   "(bad)",
10460   "fstp{t||t|}",
10461   /* dc */
10462   "fadd{l|}",
10463   "fmul{l|}",
10464   "fcom{l|}",
10465   "fcomp{l|}",
10466   "fsub{l|}",
10467   "fsubr{l|}",
10468   "fdiv{l|}",
10469   "fdivr{l|}",
10470   /* dd */
10471   "fld{l|}",
10472   "fisttp{ll|}",
10473   "fst{l||}",
10474   "fstp{l|}",
10475   "frstorIC",
10476   "(bad)",
10477   "fNsaveIC",
10478   "fNstsw",
10479   /* de */
10480   "fiadd",
10481   "fimul",
10482   "ficom",
10483   "ficomp",
10484   "fisub",
10485   "fisubr",
10486   "fidiv",
10487   "fidivr",
10488   /* df */
10489   "fild",
10490   "fisttp",
10491   "fist",
10492   "fistp",
10493   "fbld",
10494   "fild{ll|}",
10495   "fbstp",
10496   "fistp{ll|}",
10497 };
10498
10499 static const unsigned char float_mem_mode[] = {
10500   /* d8 */
10501   d_mode,
10502   d_mode,
10503   d_mode,
10504   d_mode,
10505   d_mode,
10506   d_mode,
10507   d_mode,
10508   d_mode,
10509   /* d9 */
10510   d_mode,
10511   0,
10512   d_mode,
10513   d_mode,
10514   0,
10515   w_mode,
10516   0,
10517   w_mode,
10518   /* da */
10519   d_mode,
10520   d_mode,
10521   d_mode,
10522   d_mode,
10523   d_mode,
10524   d_mode,
10525   d_mode,
10526   d_mode,
10527   /* db */
10528   d_mode,
10529   d_mode,
10530   d_mode,
10531   d_mode,
10532   0,
10533   t_mode,
10534   0,
10535   t_mode,
10536   /* dc */
10537   q_mode,
10538   q_mode,
10539   q_mode,
10540   q_mode,
10541   q_mode,
10542   q_mode,
10543   q_mode,
10544   q_mode,
10545   /* dd */
10546   q_mode,
10547   q_mode,
10548   q_mode,
10549   q_mode,
10550   0,
10551   0,
10552   0,
10553   w_mode,
10554   /* de */
10555   w_mode,
10556   w_mode,
10557   w_mode,
10558   w_mode,
10559   w_mode,
10560   w_mode,
10561   w_mode,
10562   w_mode,
10563   /* df */
10564   w_mode,
10565   w_mode,
10566   w_mode,
10567   w_mode,
10568   t_mode,
10569   q_mode,
10570   t_mode,
10571   q_mode
10572 };
10573
10574 #define ST { OP_ST, 0 }
10575 #define STi { OP_STi, 0 }
10576
10577 #define FGRPd9_2 NULL, { { NULL, 0 } }
10578 #define FGRPd9_4 NULL, { { NULL, 1 } }
10579 #define FGRPd9_5 NULL, { { NULL, 2 } }
10580 #define FGRPd9_6 NULL, { { NULL, 3 } }
10581 #define FGRPd9_7 NULL, { { NULL, 4 } }
10582 #define FGRPda_5 NULL, { { NULL, 5 } }
10583 #define FGRPdb_4 NULL, { { NULL, 6 } }
10584 #define FGRPde_3 NULL, { { NULL, 7 } }
10585 #define FGRPdf_4 NULL, { { NULL, 8 } }
10586
10587 static const struct dis386 float_reg[][8] = {
10588   /* d8 */
10589   {
10590     { "fadd",   { ST, STi } },
10591     { "fmul",   { ST, STi } },
10592     { "fcom",   { STi } },
10593     { "fcomp",  { STi } },
10594     { "fsub",   { ST, STi } },
10595     { "fsubr",  { ST, STi } },
10596     { "fdiv",   { ST, STi } },
10597     { "fdivr",  { ST, STi } },
10598   },
10599   /* d9 */
10600   {
10601     { "fld",    { STi } },
10602     { "fxch",   { STi } },
10603     { FGRPd9_2 },
10604     { "(bad)",  { XX } },
10605     { FGRPd9_4 },
10606     { FGRPd9_5 },
10607     { FGRPd9_6 },
10608     { FGRPd9_7 },
10609   },
10610   /* da */
10611   {
10612     { "fcmovb", { ST, STi } },
10613     { "fcmove", { ST, STi } },
10614     { "fcmovbe",{ ST, STi } },
10615     { "fcmovu", { ST, STi } },
10616     { "(bad)",  { XX } },
10617     { FGRPda_5 },
10618     { "(bad)",  { XX } },
10619     { "(bad)",  { XX } },
10620   },
10621   /* db */
10622   {
10623     { "fcmovnb",{ ST, STi } },
10624     { "fcmovne",{ ST, STi } },
10625     { "fcmovnbe",{ ST, STi } },
10626     { "fcmovnu",{ ST, STi } },
10627     { FGRPdb_4 },
10628     { "fucomi", { ST, STi } },
10629     { "fcomi",  { ST, STi } },
10630     { "(bad)",  { XX } },
10631   },
10632   /* dc */
10633   {
10634     { "fadd",   { STi, ST } },
10635     { "fmul",   { STi, ST } },
10636     { "(bad)",  { XX } },
10637     { "(bad)",  { XX } },
10638     { "fsub!M", { STi, ST } },
10639     { "fsubM",  { STi, ST } },
10640     { "fdiv!M", { STi, ST } },
10641     { "fdivM",  { STi, ST } },
10642   },
10643   /* dd */
10644   {
10645     { "ffree",  { STi } },
10646     { "(bad)",  { XX } },
10647     { "fst",    { STi } },
10648     { "fstp",   { STi } },
10649     { "fucom",  { STi } },
10650     { "fucomp", { STi } },
10651     { "(bad)",  { XX } },
10652     { "(bad)",  { XX } },
10653   },
10654   /* de */
10655   {
10656     { "faddp",  { STi, ST } },
10657     { "fmulp",  { STi, ST } },
10658     { "(bad)",  { XX } },
10659     { FGRPde_3 },
10660     { "fsub!Mp", { STi, ST } },
10661     { "fsubMp", { STi, ST } },
10662     { "fdiv!Mp", { STi, ST } },
10663     { "fdivMp", { STi, ST } },
10664   },
10665   /* df */
10666   {
10667     { "ffreep", { STi } },
10668     { "(bad)",  { XX } },
10669     { "(bad)",  { XX } },
10670     { "(bad)",  { XX } },
10671     { FGRPdf_4 },
10672     { "fucomip", { ST, STi } },
10673     { "fcomip", { ST, STi } },
10674     { "(bad)",  { XX } },
10675   },
10676 };
10677
10678 static char *fgrps[][8] = {
10679   /* d9_2  0 */
10680   {
10681     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10682   },
10683
10684   /* d9_4  1 */
10685   {
10686     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10687   },
10688
10689   /* d9_5  2 */
10690   {
10691     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10692   },
10693
10694   /* d9_6  3 */
10695   {
10696     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10697   },
10698
10699   /* d9_7  4 */
10700   {
10701     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10702   },
10703
10704   /* da_5  5 */
10705   {
10706     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10707   },
10708
10709   /* db_4  6 */
10710   {
10711     "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
10712     "fNsetpm(287 only)","(bad)","(bad)","(bad)",
10713   },
10714
10715   /* de_3  7 */
10716   {
10717     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10718   },
10719
10720   /* df_4  8 */
10721   {
10722     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10723   },
10724 };
10725
10726 static void
10727 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10728                int sizeflag ATTRIBUTE_UNUSED)
10729 {
10730   /* Skip mod/rm byte.  */
10731   MODRM_CHECK;
10732   codep++;
10733 }
10734
10735 static void
10736 dofloat (int sizeflag)
10737 {
10738   const struct dis386 *dp;
10739   unsigned char floatop;
10740
10741   floatop = codep[-1];
10742
10743   if (modrm.mod != 3)
10744     {
10745       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10746
10747       putop (float_mem[fp_indx], sizeflag);
10748       obufp = op_out[0];
10749       op_ad = 2;
10750       OP_E (float_mem_mode[fp_indx], sizeflag);
10751       return;
10752     }
10753   /* Skip mod/rm byte.  */
10754   MODRM_CHECK;
10755   codep++;
10756
10757   dp = &float_reg[floatop - 0xd8][modrm.reg];
10758   if (dp->name == NULL)
10759     {
10760       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10761
10762       /* Instruction fnstsw is only one with strange arg.  */
10763       if (floatop == 0xdf && codep[-1] == 0xe0)
10764         strcpy (op_out[0], names16[0]);
10765     }
10766   else
10767     {
10768       putop (dp->name, sizeflag);
10769
10770       obufp = op_out[0];
10771       op_ad = 2;
10772       if (dp->op[0].rtn)
10773         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10774
10775       obufp = op_out[1];
10776       op_ad = 1;
10777       if (dp->op[1].rtn)
10778         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10779     }
10780 }
10781
10782 static void
10783 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10784 {
10785   oappend ("%st" + intel_syntax);
10786 }
10787
10788 static void
10789 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10790 {
10791   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10792   oappend (scratchbuf + intel_syntax);
10793 }
10794
10795 /* Capital letters in template are macros.  */
10796 static int
10797 putop (const char *template, int sizeflag)
10798 {
10799   const char *p;
10800   int alt = 0;
10801   int cond = 1;
10802   unsigned int l = 0, len = 1;
10803   char last[4];
10804
10805 #define SAVE_LAST(c)                    \
10806   if (l < len && l < sizeof (last))     \
10807     last[l++] = c;                      \
10808   else                                  \
10809     abort ();
10810
10811   for (p = template; *p; p++)
10812     {
10813       switch (*p)
10814         {
10815         default:
10816           *obufp++ = *p;
10817           break;
10818         case '%':
10819           len++;
10820           break;
10821         case '!':
10822           cond = 0;
10823           break;
10824         case '{':
10825           alt = 0;
10826           if (intel_syntax)
10827             {
10828               while (*++p != '|')
10829                 if (*p == '}' || *p == '\0')
10830                   abort ();
10831             }
10832           /* Fall through.  */
10833         case 'I':
10834           alt = 1;
10835           continue;
10836         case '|':
10837           while (*++p != '}')
10838             {
10839               if (*p == '\0')
10840                 abort ();
10841             }
10842           break;
10843         case '}':
10844           break;
10845         case 'A':
10846           if (intel_syntax)
10847             break;
10848           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10849             *obufp++ = 'b';
10850           break;
10851         case 'B':
10852           if (intel_syntax)
10853             break;
10854           if (sizeflag & SUFFIX_ALWAYS)
10855             *obufp++ = 'b';
10856           break;
10857         case 'C':
10858           if (intel_syntax && !alt)
10859             break;
10860           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10861             {
10862               if (sizeflag & DFLAG)
10863                 *obufp++ = intel_syntax ? 'd' : 'l';
10864               else
10865                 *obufp++ = intel_syntax ? 'w' : 's';
10866               used_prefixes |= (prefixes & PREFIX_DATA);
10867             }
10868           break;
10869         case 'D':
10870           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10871             break;
10872           USED_REX (REX_W);
10873           if (modrm.mod == 3)
10874             {
10875               if (rex & REX_W)
10876                 *obufp++ = 'q';
10877               else if (sizeflag & DFLAG)
10878                 *obufp++ = intel_syntax ? 'd' : 'l';
10879               else
10880                 *obufp++ = 'w';
10881               used_prefixes |= (prefixes & PREFIX_DATA);
10882             }
10883           else
10884             *obufp++ = 'w';
10885           break;
10886         case 'E':               /* For jcxz/jecxz */
10887           if (address_mode == mode_64bit)
10888             {
10889               if (sizeflag & AFLAG)
10890                 *obufp++ = 'r';
10891               else
10892                 *obufp++ = 'e';
10893             }
10894           else
10895             if (sizeflag & AFLAG)
10896               *obufp++ = 'e';
10897           used_prefixes |= (prefixes & PREFIX_ADDR);
10898           break;
10899         case 'F':
10900           if (intel_syntax)
10901             break;
10902           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10903             {
10904               if (sizeflag & AFLAG)
10905                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10906               else
10907                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10908               used_prefixes |= (prefixes & PREFIX_ADDR);
10909             }
10910           break;
10911         case 'G':
10912           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10913             break;
10914           if ((rex & REX_W) || (sizeflag & DFLAG))
10915             *obufp++ = 'l';
10916           else
10917             *obufp++ = 'w';
10918           if (!(rex & REX_W))
10919             used_prefixes |= (prefixes & PREFIX_DATA);
10920           break;
10921         case 'H':
10922           if (intel_syntax)
10923             break;
10924           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10925               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10926             {
10927               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10928               *obufp++ = ',';
10929               *obufp++ = 'p';
10930               if (prefixes & PREFIX_DS)
10931                 *obufp++ = 't';
10932               else
10933                 *obufp++ = 'n';
10934             }
10935           break;
10936         case 'J':
10937           if (intel_syntax)
10938             break;
10939           *obufp++ = 'l';
10940           break;
10941         case 'K':
10942           USED_REX (REX_W);
10943           if (rex & REX_W)
10944             *obufp++ = 'q';
10945           else
10946             *obufp++ = 'd';
10947           break;
10948         case 'Z':
10949           if (intel_syntax)
10950             break;
10951           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10952             {
10953               *obufp++ = 'q';
10954               break;
10955             }
10956           /* Fall through.  */
10957           goto case_L;
10958         case 'L':
10959           if (l != 0 || len != 1)
10960             {
10961               SAVE_LAST (*p);
10962               break;
10963             }
10964 case_L:
10965           if (intel_syntax)
10966             break;
10967           if (sizeflag & SUFFIX_ALWAYS)
10968             *obufp++ = 'l';
10969           break;
10970         case 'M':
10971           if (intel_mnemonic != cond)
10972             *obufp++ = 'r';
10973           break;
10974         case 'N':
10975           if ((prefixes & PREFIX_FWAIT) == 0)
10976             *obufp++ = 'n';
10977           else
10978             used_prefixes |= PREFIX_FWAIT;
10979           break;
10980         case 'O':
10981           USED_REX (REX_W);
10982           if (rex & REX_W)
10983             *obufp++ = 'o';
10984           else if (intel_syntax && (sizeflag & DFLAG))
10985             *obufp++ = 'q';
10986           else
10987             *obufp++ = 'd';
10988           if (!(rex & REX_W))
10989             used_prefixes |= (prefixes & PREFIX_DATA);
10990           break;
10991         case 'T':
10992           if (intel_syntax)
10993             break;
10994           if (address_mode == mode_64bit && (sizeflag & DFLAG))
10995             {
10996               *obufp++ = 'q';
10997               break;
10998             }
10999           /* Fall through.  */
11000         case 'P':
11001           if (intel_syntax)
11002             break;
11003           if ((prefixes & PREFIX_DATA)
11004               || (rex & REX_W)
11005               || (sizeflag & SUFFIX_ALWAYS))
11006             {
11007               USED_REX (REX_W);
11008               if (rex & REX_W)
11009                 *obufp++ = 'q';
11010               else
11011                 {
11012                    if (sizeflag & DFLAG)
11013                       *obufp++ = 'l';
11014                    else
11015                      *obufp++ = 'w';
11016                 }
11017               used_prefixes |= (prefixes & PREFIX_DATA);
11018             }
11019           break;
11020         case 'U':
11021           if (intel_syntax)
11022             break;
11023           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11024             {
11025               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11026                 *obufp++ = 'q';
11027               break;
11028             }
11029           /* Fall through.  */
11030           goto case_Q;
11031         case 'Q':
11032           if (l == 0 && len == 1)
11033             {
11034 case_Q:
11035               if (intel_syntax && !alt)
11036                 break;
11037               USED_REX (REX_W);
11038               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11039                 {
11040                   if (rex & REX_W)
11041                     *obufp++ = 'q';
11042                   else
11043                     {
11044                       if (sizeflag & DFLAG)
11045                         *obufp++ = intel_syntax ? 'd' : 'l';
11046                       else
11047                         *obufp++ = 'w';
11048                     }
11049                   used_prefixes |= (prefixes & PREFIX_DATA);
11050                 }
11051             }
11052           else
11053             {
11054               if (l != 1 || len != 2 || last[0] != 'L')
11055                 {
11056                   SAVE_LAST (*p);
11057                   break;
11058                 }
11059               if (intel_syntax
11060                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11061                 break;
11062               if ((rex & REX_W))
11063                 {
11064                   USED_REX (REX_W);
11065                   *obufp++ = 'q';
11066                 }
11067               else
11068                 *obufp++ = 'l';
11069             }
11070           break;
11071         case 'R':
11072           USED_REX (REX_W);
11073           if (rex & REX_W)
11074             *obufp++ = 'q';
11075           else if (sizeflag & DFLAG)
11076             {
11077               if (intel_syntax)
11078                   *obufp++ = 'd';
11079               else
11080                   *obufp++ = 'l';
11081             }
11082           else
11083             *obufp++ = 'w';
11084           if (intel_syntax && !p[1]
11085               && ((rex & REX_W) || (sizeflag & DFLAG)))
11086             *obufp++ = 'e';
11087           if (!(rex & REX_W))
11088             used_prefixes |= (prefixes & PREFIX_DATA);
11089           break;
11090         case 'V':
11091           if (intel_syntax)
11092             break;
11093           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11094             {
11095               if (sizeflag & SUFFIX_ALWAYS)
11096                 *obufp++ = 'q';
11097               break;
11098             }
11099           /* Fall through.  */
11100         case 'S':
11101           if (intel_syntax)
11102             break;
11103           if (sizeflag & SUFFIX_ALWAYS)
11104             {
11105               if (rex & REX_W)
11106                 *obufp++ = 'q';
11107               else
11108                 {
11109                   if (sizeflag & DFLAG)
11110                     *obufp++ = 'l';
11111                   else
11112                     *obufp++ = 'w';
11113                   used_prefixes |= (prefixes & PREFIX_DATA);
11114                 }
11115             }
11116           break;
11117         case 'X':
11118           if (l != 0 || len != 1)
11119             {
11120               SAVE_LAST (*p);
11121               break;
11122             }
11123           if (need_vex && vex.prefix)
11124             {
11125               if (vex.prefix == DATA_PREFIX_OPCODE)
11126                 *obufp++ = 'd';
11127               else
11128                 *obufp++ = 's';
11129             }
11130           else if (prefixes & PREFIX_DATA)
11131             *obufp++ = 'd';
11132           else
11133             *obufp++ = 's';
11134           used_prefixes |= (prefixes & PREFIX_DATA);
11135           break;
11136         case 'Y':
11137           if (l == 0 && len == 1)
11138             {
11139               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11140                 break;
11141               if (rex & REX_W)
11142                 {
11143                   USED_REX (REX_W);
11144                   *obufp++ = 'q';
11145                 }
11146               break;
11147             }
11148           else
11149             {
11150               if (l != 1 || len != 2 || last[0] != 'X')
11151                 {
11152                   SAVE_LAST (*p);
11153                   break;
11154                 }
11155               if (!need_vex)
11156                 abort ();
11157               if (intel_syntax
11158                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11159                 break;
11160               switch (vex.length)
11161                 {
11162                 case 128:
11163                   *obufp++ = 'x';
11164                   break;
11165                 case 256:
11166                   *obufp++ = 'y';
11167                   break;
11168                 default:
11169                   abort ();
11170                 }
11171             }
11172           break;
11173         case 'W':
11174           /* operand size flag for cwtl, cbtw */
11175           USED_REX (REX_W);
11176           if (rex & REX_W)
11177             {
11178               if (intel_syntax)
11179                 *obufp++ = 'd';
11180               else
11181                 *obufp++ = 'l';
11182             }
11183           else if (sizeflag & DFLAG)
11184             *obufp++ = 'w';
11185           else
11186             *obufp++ = 'b';
11187           if (!(rex & REX_W))
11188             used_prefixes |= (prefixes & PREFIX_DATA);
11189           break;
11190         }
11191       alt = 0;
11192     }
11193   *obufp = 0;
11194   mnemonicendp = obufp;
11195   return 0;
11196 }
11197
11198 static void
11199 oappend (const char *s)
11200 {
11201   obufp = stpcpy (obufp, s);
11202 }
11203
11204 static void
11205 append_seg (void)
11206 {
11207   if (prefixes & PREFIX_CS)
11208     {
11209       used_prefixes |= PREFIX_CS;
11210       oappend ("%cs:" + intel_syntax);
11211     }
11212   if (prefixes & PREFIX_DS)
11213     {
11214       used_prefixes |= PREFIX_DS;
11215       oappend ("%ds:" + intel_syntax);
11216     }
11217   if (prefixes & PREFIX_SS)
11218     {
11219       used_prefixes |= PREFIX_SS;
11220       oappend ("%ss:" + intel_syntax);
11221     }
11222   if (prefixes & PREFIX_ES)
11223     {
11224       used_prefixes |= PREFIX_ES;
11225       oappend ("%es:" + intel_syntax);
11226     }
11227   if (prefixes & PREFIX_FS)
11228     {
11229       used_prefixes |= PREFIX_FS;
11230       oappend ("%fs:" + intel_syntax);
11231     }
11232   if (prefixes & PREFIX_GS)
11233     {
11234       used_prefixes |= PREFIX_GS;
11235       oappend ("%gs:" + intel_syntax);
11236     }
11237 }
11238
11239 static void
11240 OP_indirE (int bytemode, int sizeflag)
11241 {
11242   if (!intel_syntax)
11243     oappend ("*");
11244   OP_E (bytemode, sizeflag);
11245 }
11246
11247 static void
11248 print_operand_value (char *buf, int hex, bfd_vma disp)
11249 {
11250   if (address_mode == mode_64bit)
11251     {
11252       if (hex)
11253         {
11254           char tmp[30];
11255           int i;
11256           buf[0] = '0';
11257           buf[1] = 'x';
11258           sprintf_vma (tmp, disp);
11259           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11260           strcpy (buf + 2, tmp + i);
11261         }
11262       else
11263         {
11264           bfd_signed_vma v = disp;
11265           char tmp[30];
11266           int i;
11267           if (v < 0)
11268             {
11269               *(buf++) = '-';
11270               v = -disp;
11271               /* Check for possible overflow on 0x8000000000000000.  */
11272               if (v < 0)
11273                 {
11274                   strcpy (buf, "9223372036854775808");
11275                   return;
11276                 }
11277             }
11278           if (!v)
11279             {
11280               strcpy (buf, "0");
11281               return;
11282             }
11283
11284           i = 0;
11285           tmp[29] = 0;
11286           while (v)
11287             {
11288               tmp[28 - i] = (v % 10) + '0';
11289               v /= 10;
11290               i++;
11291             }
11292           strcpy (buf, tmp + 29 - i);
11293         }
11294     }
11295   else
11296     {
11297       if (hex)
11298         sprintf (buf, "0x%x", (unsigned int) disp);
11299       else
11300         sprintf (buf, "%d", (int) disp);
11301     }
11302 }
11303
11304 /* Put DISP in BUF as signed hex number.  */
11305
11306 static void
11307 print_displacement (char *buf, bfd_vma disp)
11308 {
11309   bfd_signed_vma val = disp;
11310   char tmp[30];
11311   int i, j = 0;
11312
11313   if (val < 0)
11314     {
11315       buf[j++] = '-';
11316       val = -disp;
11317
11318       /* Check for possible overflow.  */
11319       if (val < 0)
11320         {
11321           switch (address_mode)
11322             {
11323             case mode_64bit:
11324               strcpy (buf + j, "0x8000000000000000");
11325               break;
11326             case mode_32bit:
11327               strcpy (buf + j, "0x80000000");
11328               break;
11329             case mode_16bit:
11330               strcpy (buf + j, "0x8000");
11331               break;
11332             }
11333           return;
11334         }
11335     }
11336
11337   buf[j++] = '0';
11338   buf[j++] = 'x';
11339
11340   sprintf_vma (tmp, (bfd_vma) val);
11341   for (i = 0; tmp[i] == '0'; i++)
11342     continue;
11343   if (tmp[i] == '\0')
11344     i--;
11345   strcpy (buf + j, tmp + i);
11346 }
11347
11348 static void
11349 intel_operand_size (int bytemode, int sizeflag)
11350 {
11351   switch (bytemode)
11352     {
11353     case b_mode:
11354     case dqb_mode:
11355       oappend ("BYTE PTR ");
11356       break;
11357     case w_mode:
11358     case dqw_mode:
11359       oappend ("WORD PTR ");
11360       break;
11361     case stack_v_mode:
11362       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11363         {
11364           oappend ("QWORD PTR ");
11365           used_prefixes |= (prefixes & PREFIX_DATA);
11366           break;
11367         }
11368       /* FALLTHRU */
11369     case v_mode:
11370     case dq_mode:
11371       USED_REX (REX_W);
11372       if (rex & REX_W)
11373         oappend ("QWORD PTR ");
11374       else if ((sizeflag & DFLAG) || bytemode == dq_mode)
11375         oappend ("DWORD PTR ");
11376       else
11377         oappend ("WORD PTR ");
11378       used_prefixes |= (prefixes & PREFIX_DATA);
11379       break;
11380     case z_mode:
11381       if ((rex & REX_W) || (sizeflag & DFLAG))
11382         *obufp++ = 'D';
11383       oappend ("WORD PTR ");
11384       if (!(rex & REX_W))
11385         used_prefixes |= (prefixes & PREFIX_DATA);
11386       break;
11387     case a_mode:
11388       if (sizeflag & DFLAG)
11389         oappend ("QWORD PTR ");
11390       else
11391         oappend ("DWORD PTR ");
11392       used_prefixes |= (prefixes & PREFIX_DATA);
11393       break;
11394     case d_mode:
11395     case dqd_mode:
11396       oappend ("DWORD PTR ");
11397       break;
11398     case q_mode:
11399       oappend ("QWORD PTR ");
11400       break;
11401     case m_mode:
11402       if (address_mode == mode_64bit)
11403         oappend ("QWORD PTR ");
11404       else
11405         oappend ("DWORD PTR ");
11406       break;
11407     case f_mode:
11408       if (sizeflag & DFLAG)
11409         oappend ("FWORD PTR ");
11410       else
11411         oappend ("DWORD PTR ");
11412       used_prefixes |= (prefixes & PREFIX_DATA);
11413       break;
11414     case t_mode:
11415       oappend ("TBYTE PTR ");
11416       break;
11417     case x_mode:
11418       if (need_vex)
11419         {
11420           switch (vex.length)
11421             {
11422             case 128:
11423               oappend ("XMMWORD PTR ");
11424               break;
11425             case 256:
11426               oappend ("YMMWORD PTR ");
11427               break;
11428             default:
11429               abort ();
11430             }
11431         }
11432       else
11433         oappend ("XMMWORD PTR ");
11434       break;
11435     case xmm_mode:
11436       oappend ("XMMWORD PTR ");
11437       break;
11438     case xmmq_mode:
11439       if (!need_vex)
11440         abort ();
11441
11442       switch (vex.length)
11443         {
11444         case 128:
11445           oappend ("QWORD PTR ");
11446           break;
11447         case 256:
11448           oappend ("XMMWORD PTR ");
11449           break;
11450         default:
11451           abort ();
11452         }
11453       break;
11454     case ymmq_mode:
11455       if (!need_vex)
11456         abort ();
11457
11458       switch (vex.length)
11459         {
11460         case 128:
11461           oappend ("QWORD PTR ");
11462           break;
11463         case 256:
11464           oappend ("YMMWORD PTR ");
11465           break;
11466         default:
11467           abort ();
11468         }
11469       break;
11470     case o_mode:
11471       oappend ("OWORD PTR ");
11472       break;
11473     default:
11474       break;
11475     }
11476 }
11477
11478 static void
11479 OP_E_register (int bytemode, int sizeflag)
11480 {
11481   int reg = modrm.rm;
11482   const char **names;
11483
11484   USED_REX (REX_B);
11485   if ((rex & REX_B))
11486     reg += 8;
11487
11488   switch (bytemode)
11489     {
11490     case b_mode:
11491       USED_REX (0);
11492       if (rex)
11493         names = names8rex;
11494       else
11495         names = names8;
11496       break;
11497     case w_mode:
11498       names = names16;
11499       break;
11500     case d_mode:
11501       names = names32;
11502       break;
11503     case q_mode:
11504       names = names64;
11505       break;
11506     case m_mode:
11507       names = address_mode == mode_64bit ? names64 : names32;
11508       break;
11509     case stack_v_mode:
11510       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11511         {
11512           names = names64;
11513           used_prefixes |= (prefixes & PREFIX_DATA);
11514           break;
11515         }
11516       bytemode = v_mode;
11517       /* FALLTHRU */
11518     case v_mode:
11519     case dq_mode:
11520     case dqb_mode:
11521     case dqd_mode:
11522     case dqw_mode:
11523       USED_REX (REX_W);
11524       if (rex & REX_W)
11525         names = names64;
11526       else if ((sizeflag & DFLAG) || bytemode != v_mode)
11527         names = names32;
11528       else
11529         names = names16;
11530       used_prefixes |= (prefixes & PREFIX_DATA);
11531       break;
11532     case 0:
11533       return;
11534     default:
11535       oappend (INTERNAL_DISASSEMBLER_ERROR);
11536       return;
11537     }
11538   oappend (names[reg]);
11539 }
11540
11541 static void
11542 OP_E_memory (int bytemode, int sizeflag, int has_drex)
11543 {
11544   bfd_vma disp = 0;
11545   int add = (rex & REX_B) ? 8 : 0;
11546   int riprel = 0;
11547
11548   USED_REX (REX_B);
11549   if (intel_syntax)
11550     intel_operand_size (bytemode, sizeflag);
11551   append_seg ();
11552
11553   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11554     {
11555       /* 32/64 bit address mode */
11556       int havedisp;
11557       int havesib;
11558       int havebase;
11559       int haveindex;
11560       int needindex;
11561       int base, rbase;
11562       int index = 0;
11563       int scale = 0;
11564
11565       havesib = 0;
11566       havebase = 1;
11567       haveindex = 0;
11568       base = modrm.rm;
11569
11570       if (base == 4)
11571         {
11572           havesib = 1;
11573           FETCH_DATA (the_info, codep + 1);
11574           index = (*codep >> 3) & 7;
11575           scale = (*codep >> 6) & 3;
11576           base = *codep & 7;
11577           USED_REX (REX_X);
11578           if (rex & REX_X)
11579             index += 8;
11580           haveindex = index != 4;
11581           codep++;
11582         }
11583       rbase = base + add;
11584
11585       /* If we have a DREX byte, skip it now
11586          (it has already been handled) */
11587       if (has_drex)
11588         {
11589           FETCH_DATA (the_info, codep + 1);
11590           codep++;
11591         }
11592
11593       switch (modrm.mod)
11594         {
11595         case 0:
11596           if (base == 5)
11597             {
11598               havebase = 0;
11599               if (address_mode == mode_64bit && !havesib)
11600                 riprel = 1;
11601               disp = get32s ();
11602             }
11603           break;
11604         case 1:
11605           FETCH_DATA (the_info, codep + 1);
11606           disp = *codep++;
11607           if ((disp & 0x80) != 0)
11608             disp -= 0x100;
11609           break;
11610         case 2:
11611           disp = get32s ();
11612           break;
11613         }
11614
11615       /* In 32bit mode, we need index register to tell [offset] from
11616          [eiz*1 + offset].  */
11617       needindex = (havesib
11618                    && !havebase
11619                    && !haveindex
11620                    && address_mode == mode_32bit);
11621       havedisp = (havebase
11622                   || needindex
11623                   || (havesib && (haveindex || scale != 0)));
11624
11625       if (!intel_syntax)
11626         if (modrm.mod != 0 || base == 5)
11627           {
11628             if (havedisp || riprel)
11629               print_displacement (scratchbuf, disp);
11630             else
11631               print_operand_value (scratchbuf, 1, disp);
11632             oappend (scratchbuf);
11633             if (riprel)
11634               {
11635                 set_op (disp, 1);
11636                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11637               }
11638           }
11639
11640       if (havebase || haveindex || riprel)
11641         used_prefixes |= PREFIX_ADDR;
11642
11643       if (havedisp || (intel_syntax && riprel))
11644         {
11645           *obufp++ = open_char;
11646           if (intel_syntax && riprel)
11647             {
11648               set_op (disp, 1);
11649               oappend (sizeflag & AFLAG ? "rip" : "eip");
11650             }
11651           *obufp = '\0';
11652           if (havebase)
11653             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11654                      ? names64[rbase] : names32[rbase]);
11655           if (havesib)
11656             {
11657               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11658                  print index to tell base + index from base.  */
11659               if (scale != 0
11660                   || needindex
11661                   || haveindex
11662                   || (havebase && base != ESP_REG_NUM))
11663                 {
11664                   if (!intel_syntax || havebase)
11665                     {
11666                       *obufp++ = separator_char;
11667                       *obufp = '\0';
11668                     }
11669                   if (haveindex)
11670                     oappend (address_mode == mode_64bit
11671                              && (sizeflag & AFLAG)
11672                              ? names64[index] : names32[index]);
11673                   else
11674                     oappend (address_mode == mode_64bit
11675                              && (sizeflag & AFLAG)
11676                              ? index64 : index32);
11677
11678                   *obufp++ = scale_char;
11679                   *obufp = '\0';
11680                   sprintf (scratchbuf, "%d", 1 << scale);
11681                   oappend (scratchbuf);
11682                 }
11683             }
11684           if (intel_syntax
11685               && (disp || modrm.mod != 0 || base == 5))
11686             {
11687               if (!havedisp || (bfd_signed_vma) disp >= 0)
11688                 {
11689                   *obufp++ = '+';
11690                   *obufp = '\0';
11691                 }
11692               else if (modrm.mod != 1)
11693                 {
11694                   *obufp++ = '-';
11695                   *obufp = '\0';
11696                   disp = - (bfd_signed_vma) disp;
11697                 }
11698
11699               if (havedisp)
11700                 print_displacement (scratchbuf, disp);
11701               else
11702                 print_operand_value (scratchbuf, 1, disp);
11703               oappend (scratchbuf);
11704             }
11705
11706           *obufp++ = close_char;
11707           *obufp = '\0';
11708         }
11709       else if (intel_syntax)
11710         {
11711           if (modrm.mod != 0 || base == 5)
11712             {
11713               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11714                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11715                 ;
11716               else
11717                 {
11718                   oappend (names_seg[ds_reg - es_reg]);
11719                   oappend (":");
11720                 }
11721               print_operand_value (scratchbuf, 1, disp);
11722               oappend (scratchbuf);
11723             }
11724         }
11725     }
11726   else
11727     { /* 16 bit address mode */
11728       switch (modrm.mod)
11729         {
11730         case 0:
11731           if (modrm.rm == 6)
11732             {
11733               disp = get16 ();
11734               if ((disp & 0x8000) != 0)
11735                 disp -= 0x10000;
11736             }
11737           break;
11738         case 1:
11739           FETCH_DATA (the_info, codep + 1);
11740           disp = *codep++;
11741           if ((disp & 0x80) != 0)
11742             disp -= 0x100;
11743           break;
11744         case 2:
11745           disp = get16 ();
11746           if ((disp & 0x8000) != 0)
11747             disp -= 0x10000;
11748           break;
11749         }
11750
11751       if (!intel_syntax)
11752         if (modrm.mod != 0 || modrm.rm == 6)
11753           {
11754             print_displacement (scratchbuf, disp);
11755             oappend (scratchbuf);
11756           }
11757
11758       if (modrm.mod != 0 || modrm.rm != 6)
11759         {
11760           *obufp++ = open_char;
11761           *obufp = '\0';
11762           oappend (index16[modrm.rm]);
11763           if (intel_syntax
11764               && (disp || modrm.mod != 0 || modrm.rm == 6))
11765             {
11766               if ((bfd_signed_vma) disp >= 0)
11767                 {
11768                   *obufp++ = '+';
11769                   *obufp = '\0';
11770                 }
11771               else if (modrm.mod != 1)
11772                 {
11773                   *obufp++ = '-';
11774                   *obufp = '\0';
11775                   disp = - (bfd_signed_vma) disp;
11776                 }
11777
11778               print_displacement (scratchbuf, disp);
11779               oappend (scratchbuf);
11780             }
11781
11782           *obufp++ = close_char;
11783           *obufp = '\0';
11784         }
11785       else if (intel_syntax)
11786         {
11787           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11788                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11789             ;
11790           else
11791             {
11792               oappend (names_seg[ds_reg - es_reg]);
11793               oappend (":");
11794             }
11795           print_operand_value (scratchbuf, 1, disp & 0xffff);
11796           oappend (scratchbuf);
11797         }
11798     }
11799 }
11800
11801 static void
11802 OP_E_extended (int bytemode, int sizeflag, int has_drex)
11803 {
11804   /* Skip mod/rm byte.  */
11805   MODRM_CHECK;
11806   codep++;
11807
11808   if (modrm.mod == 3)
11809     OP_E_register (bytemode, sizeflag);
11810   else
11811     OP_E_memory (bytemode, sizeflag, has_drex);
11812 }
11813
11814 static void
11815 OP_E (int bytemode, int sizeflag)
11816 {
11817   OP_E_extended (bytemode, sizeflag, 0);
11818 }
11819
11820
11821 static void
11822 OP_G (int bytemode, int sizeflag)
11823 {
11824   int add = 0;
11825   USED_REX (REX_R);
11826   if (rex & REX_R)
11827     add += 8;
11828   switch (bytemode)
11829     {
11830     case b_mode:
11831       USED_REX (0);
11832       if (rex)
11833         oappend (names8rex[modrm.reg + add]);
11834       else
11835         oappend (names8[modrm.reg + add]);
11836       break;
11837     case w_mode:
11838       oappend (names16[modrm.reg + add]);
11839       break;
11840     case d_mode:
11841       oappend (names32[modrm.reg + add]);
11842       break;
11843     case q_mode:
11844       oappend (names64[modrm.reg + add]);
11845       break;
11846     case v_mode:
11847     case dq_mode:
11848     case dqb_mode:
11849     case dqd_mode:
11850     case dqw_mode:
11851       USED_REX (REX_W);
11852       if (rex & REX_W)
11853         oappend (names64[modrm.reg + add]);
11854       else if ((sizeflag & DFLAG) || bytemode != v_mode)
11855         oappend (names32[modrm.reg + add]);
11856       else
11857         oappend (names16[modrm.reg + add]);
11858       used_prefixes |= (prefixes & PREFIX_DATA);
11859       break;
11860     case m_mode:
11861       if (address_mode == mode_64bit)
11862         oappend (names64[modrm.reg + add]);
11863       else
11864         oappend (names32[modrm.reg + add]);
11865       break;
11866     default:
11867       oappend (INTERNAL_DISASSEMBLER_ERROR);
11868       break;
11869     }
11870 }
11871
11872 static bfd_vma
11873 get64 (void)
11874 {
11875   bfd_vma x;
11876 #ifdef BFD64
11877   unsigned int a;
11878   unsigned int b;
11879
11880   FETCH_DATA (the_info, codep + 8);
11881   a = *codep++ & 0xff;
11882   a |= (*codep++ & 0xff) << 8;
11883   a |= (*codep++ & 0xff) << 16;
11884   a |= (*codep++ & 0xff) << 24;
11885   b = *codep++ & 0xff;
11886   b |= (*codep++ & 0xff) << 8;
11887   b |= (*codep++ & 0xff) << 16;
11888   b |= (*codep++ & 0xff) << 24;
11889   x = a + ((bfd_vma) b << 32);
11890 #else
11891   abort ();
11892   x = 0;
11893 #endif
11894   return x;
11895 }
11896
11897 static bfd_signed_vma
11898 get32 (void)
11899 {
11900   bfd_signed_vma x = 0;
11901
11902   FETCH_DATA (the_info, codep + 4);
11903   x = *codep++ & (bfd_signed_vma) 0xff;
11904   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11905   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11906   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11907   return x;
11908 }
11909
11910 static bfd_signed_vma
11911 get32s (void)
11912 {
11913   bfd_signed_vma x = 0;
11914
11915   FETCH_DATA (the_info, codep + 4);
11916   x = *codep++ & (bfd_signed_vma) 0xff;
11917   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11918   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11919   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11920
11921   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11922
11923   return x;
11924 }
11925
11926 static int
11927 get16 (void)
11928 {
11929   int x = 0;
11930
11931   FETCH_DATA (the_info, codep + 2);
11932   x = *codep++ & 0xff;
11933   x |= (*codep++ & 0xff) << 8;
11934   return x;
11935 }
11936
11937 static void
11938 set_op (bfd_vma op, int riprel)
11939 {
11940   op_index[op_ad] = op_ad;
11941   if (address_mode == mode_64bit)
11942     {
11943       op_address[op_ad] = op;
11944       op_riprel[op_ad] = riprel;
11945     }
11946   else
11947     {
11948       /* Mask to get a 32-bit address.  */
11949       op_address[op_ad] = op & 0xffffffff;
11950       op_riprel[op_ad] = riprel & 0xffffffff;
11951     }
11952 }
11953
11954 static void
11955 OP_REG (int code, int sizeflag)
11956 {
11957   const char *s;
11958   int add;
11959   USED_REX (REX_B);
11960   if (rex & REX_B)
11961     add = 8;
11962   else
11963     add = 0;
11964
11965   switch (code)
11966     {
11967     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11968     case sp_reg: case bp_reg: case si_reg: case di_reg:
11969       s = names16[code - ax_reg + add];
11970       break;
11971     case es_reg: case ss_reg: case cs_reg:
11972     case ds_reg: case fs_reg: case gs_reg:
11973       s = names_seg[code - es_reg + add];
11974       break;
11975     case al_reg: case ah_reg: case cl_reg: case ch_reg:
11976     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11977       USED_REX (0);
11978       if (rex)
11979         s = names8rex[code - al_reg + add];
11980       else
11981         s = names8[code - al_reg];
11982       break;
11983     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
11984     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
11985       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11986         {
11987           s = names64[code - rAX_reg + add];
11988           break;
11989         }
11990       code += eAX_reg - rAX_reg;
11991       /* Fall through.  */
11992     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11993     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11994       USED_REX (REX_W);
11995       if (rex & REX_W)
11996         s = names64[code - eAX_reg + add];
11997       else if (sizeflag & DFLAG)
11998         s = names32[code - eAX_reg + add];
11999       else
12000         s = names16[code - eAX_reg + add];
12001       used_prefixes |= (prefixes & PREFIX_DATA);
12002       break;
12003     default:
12004       s = INTERNAL_DISASSEMBLER_ERROR;
12005       break;
12006     }
12007   oappend (s);
12008 }
12009
12010 static void
12011 OP_IMREG (int code, int sizeflag)
12012 {
12013   const char *s;
12014
12015   switch (code)
12016     {
12017     case indir_dx_reg:
12018       if (intel_syntax)
12019         s = "dx";
12020       else
12021         s = "(%dx)";
12022       break;
12023     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12024     case sp_reg: case bp_reg: case si_reg: case di_reg:
12025       s = names16[code - ax_reg];
12026       break;
12027     case es_reg: case ss_reg: case cs_reg:
12028     case ds_reg: case fs_reg: case gs_reg:
12029       s = names_seg[code - es_reg];
12030       break;
12031     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12032     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12033       USED_REX (0);
12034       if (rex)
12035         s = names8rex[code - al_reg];
12036       else
12037         s = names8[code - al_reg];
12038       break;
12039     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12040     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12041       USED_REX (REX_W);
12042       if (rex & REX_W)
12043         s = names64[code - eAX_reg];
12044       else if (sizeflag & DFLAG)
12045         s = names32[code - eAX_reg];
12046       else
12047         s = names16[code - eAX_reg];
12048       used_prefixes |= (prefixes & PREFIX_DATA);
12049       break;
12050     case z_mode_ax_reg:
12051       if ((rex & REX_W) || (sizeflag & DFLAG))
12052         s = *names32;
12053       else
12054         s = *names16;
12055       if (!(rex & REX_W))
12056         used_prefixes |= (prefixes & PREFIX_DATA);
12057       break;
12058     default:
12059       s = INTERNAL_DISASSEMBLER_ERROR;
12060       break;
12061     }
12062   oappend (s);
12063 }
12064
12065 static void
12066 OP_I (int bytemode, int sizeflag)
12067 {
12068   bfd_signed_vma op;
12069   bfd_signed_vma mask = -1;
12070
12071   switch (bytemode)
12072     {
12073     case b_mode:
12074       FETCH_DATA (the_info, codep + 1);
12075       op = *codep++;
12076       mask = 0xff;
12077       break;
12078     case q_mode:
12079       if (address_mode == mode_64bit)
12080         {
12081           op = get32s ();
12082           break;
12083         }
12084       /* Fall through.  */
12085     case v_mode:
12086       USED_REX (REX_W);
12087       if (rex & REX_W)
12088         op = get32s ();
12089       else if (sizeflag & DFLAG)
12090         {
12091           op = get32 ();
12092           mask = 0xffffffff;
12093         }
12094       else
12095         {
12096           op = get16 ();
12097           mask = 0xfffff;
12098         }
12099       used_prefixes |= (prefixes & PREFIX_DATA);
12100       break;
12101     case w_mode:
12102       mask = 0xfffff;
12103       op = get16 ();
12104       break;
12105     case const_1_mode:
12106       if (intel_syntax)
12107         oappend ("1");
12108       return;
12109     default:
12110       oappend (INTERNAL_DISASSEMBLER_ERROR);
12111       return;
12112     }
12113
12114   op &= mask;
12115   scratchbuf[0] = '$';
12116   print_operand_value (scratchbuf + 1, 1, op);
12117   oappend (scratchbuf + intel_syntax);
12118   scratchbuf[0] = '\0';
12119 }
12120
12121 static void
12122 OP_I64 (int bytemode, int sizeflag)
12123 {
12124   bfd_signed_vma op;
12125   bfd_signed_vma mask = -1;
12126
12127   if (address_mode != mode_64bit)
12128     {
12129       OP_I (bytemode, sizeflag);
12130       return;
12131     }
12132
12133   switch (bytemode)
12134     {
12135     case b_mode:
12136       FETCH_DATA (the_info, codep + 1);
12137       op = *codep++;
12138       mask = 0xff;
12139       break;
12140     case v_mode:
12141       USED_REX (REX_W);
12142       if (rex & REX_W)
12143         op = get64 ();
12144       else if (sizeflag & DFLAG)
12145         {
12146           op = get32 ();
12147           mask = 0xffffffff;
12148         }
12149       else
12150         {
12151           op = get16 ();
12152           mask = 0xfffff;
12153         }
12154       used_prefixes |= (prefixes & PREFIX_DATA);
12155       break;
12156     case w_mode:
12157       mask = 0xfffff;
12158       op = get16 ();
12159       break;
12160     default:
12161       oappend (INTERNAL_DISASSEMBLER_ERROR);
12162       return;
12163     }
12164
12165   op &= mask;
12166   scratchbuf[0] = '$';
12167   print_operand_value (scratchbuf + 1, 1, op);
12168   oappend (scratchbuf + intel_syntax);
12169   scratchbuf[0] = '\0';
12170 }
12171
12172 static void
12173 OP_sI (int bytemode, int sizeflag)
12174 {
12175   bfd_signed_vma op;
12176   bfd_signed_vma mask = -1;
12177
12178   switch (bytemode)
12179     {
12180     case b_mode:
12181       FETCH_DATA (the_info, codep + 1);
12182       op = *codep++;
12183       if ((op & 0x80) != 0)
12184         op -= 0x100;
12185       mask = 0xffffffff;
12186       break;
12187     case v_mode:
12188       USED_REX (REX_W);
12189       if (rex & REX_W)
12190         op = get32s ();
12191       else if (sizeflag & DFLAG)
12192         {
12193           op = get32s ();
12194           mask = 0xffffffff;
12195         }
12196       else
12197         {
12198           mask = 0xffffffff;
12199           op = get16 ();
12200           if ((op & 0x8000) != 0)
12201             op -= 0x10000;
12202         }
12203       used_prefixes |= (prefixes & PREFIX_DATA);
12204       break;
12205     case w_mode:
12206       op = get16 ();
12207       mask = 0xffffffff;
12208       if ((op & 0x8000) != 0)
12209         op -= 0x10000;
12210       break;
12211     default:
12212       oappend (INTERNAL_DISASSEMBLER_ERROR);
12213       return;
12214     }
12215
12216   scratchbuf[0] = '$';
12217   print_operand_value (scratchbuf + 1, 1, op);
12218   oappend (scratchbuf + intel_syntax);
12219 }
12220
12221 static void
12222 OP_J (int bytemode, int sizeflag)
12223 {
12224   bfd_vma disp;
12225   bfd_vma mask = -1;
12226   bfd_vma segment = 0;
12227
12228   switch (bytemode)
12229     {
12230     case b_mode:
12231       FETCH_DATA (the_info, codep + 1);
12232       disp = *codep++;
12233       if ((disp & 0x80) != 0)
12234         disp -= 0x100;
12235       break;
12236     case v_mode:
12237       if ((sizeflag & DFLAG) || (rex & REX_W))
12238         disp = get32s ();
12239       else
12240         {
12241           disp = get16 ();
12242           if ((disp & 0x8000) != 0)
12243             disp -= 0x10000;
12244           /* In 16bit mode, address is wrapped around at 64k within
12245              the same segment.  Otherwise, a data16 prefix on a jump
12246              instruction means that the pc is masked to 16 bits after
12247              the displacement is added!  */
12248           mask = 0xffff;
12249           if ((prefixes & PREFIX_DATA) == 0)
12250             segment = ((start_pc + codep - start_codep)
12251                        & ~((bfd_vma) 0xffff));
12252         }
12253       used_prefixes |= (prefixes & PREFIX_DATA);
12254       break;
12255     default:
12256       oappend (INTERNAL_DISASSEMBLER_ERROR);
12257       return;
12258     }
12259   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
12260   set_op (disp, 0);
12261   print_operand_value (scratchbuf, 1, disp);
12262   oappend (scratchbuf);
12263 }
12264
12265 static void
12266 OP_SEG (int bytemode, int sizeflag)
12267 {
12268   if (bytemode == w_mode)
12269     oappend (names_seg[modrm.reg]);
12270   else
12271     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12272 }
12273
12274 static void
12275 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12276 {
12277   int seg, offset;
12278
12279   if (sizeflag & DFLAG)
12280     {
12281       offset = get32 ();
12282       seg = get16 ();
12283     }
12284   else
12285     {
12286       offset = get16 ();
12287       seg = get16 ();
12288     }
12289   used_prefixes |= (prefixes & PREFIX_DATA);
12290   if (intel_syntax)
12291     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12292   else
12293     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12294   oappend (scratchbuf);
12295 }
12296
12297 static void
12298 OP_OFF (int bytemode, int sizeflag)
12299 {
12300   bfd_vma off;
12301
12302   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12303     intel_operand_size (bytemode, sizeflag);
12304   append_seg ();
12305
12306   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12307     off = get32 ();
12308   else
12309     off = get16 ();
12310
12311   if (intel_syntax)
12312     {
12313       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12314                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12315         {
12316           oappend (names_seg[ds_reg - es_reg]);
12317           oappend (":");
12318         }
12319     }
12320   print_operand_value (scratchbuf, 1, off);
12321   oappend (scratchbuf);
12322 }
12323
12324 static void
12325 OP_OFF64 (int bytemode, int sizeflag)
12326 {
12327   bfd_vma off;
12328
12329   if (address_mode != mode_64bit
12330       || (prefixes & PREFIX_ADDR))
12331     {
12332       OP_OFF (bytemode, sizeflag);
12333       return;
12334     }
12335
12336   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12337     intel_operand_size (bytemode, sizeflag);
12338   append_seg ();
12339
12340   off = get64 ();
12341
12342   if (intel_syntax)
12343     {
12344       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12345                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12346         {
12347           oappend (names_seg[ds_reg - es_reg]);
12348           oappend (":");
12349         }
12350     }
12351   print_operand_value (scratchbuf, 1, off);
12352   oappend (scratchbuf);
12353 }
12354
12355 static void
12356 ptr_reg (int code, int sizeflag)
12357 {
12358   const char *s;
12359
12360   *obufp++ = open_char;
12361   used_prefixes |= (prefixes & PREFIX_ADDR);
12362   if (address_mode == mode_64bit)
12363     {
12364       if (!(sizeflag & AFLAG))
12365         s = names32[code - eAX_reg];
12366       else
12367         s = names64[code - eAX_reg];
12368     }
12369   else if (sizeflag & AFLAG)
12370     s = names32[code - eAX_reg];
12371   else
12372     s = names16[code - eAX_reg];
12373   oappend (s);
12374   *obufp++ = close_char;
12375   *obufp = 0;
12376 }
12377
12378 static void
12379 OP_ESreg (int code, int sizeflag)
12380 {
12381   if (intel_syntax)
12382     {
12383       switch (codep[-1])
12384         {
12385         case 0x6d:      /* insw/insl */
12386           intel_operand_size (z_mode, sizeflag);
12387           break;
12388         case 0xa5:      /* movsw/movsl/movsq */
12389         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12390         case 0xab:      /* stosw/stosl */
12391         case 0xaf:      /* scasw/scasl */
12392           intel_operand_size (v_mode, sizeflag);
12393           break;
12394         default:
12395           intel_operand_size (b_mode, sizeflag);
12396         }
12397     }
12398   oappend ("%es:" + intel_syntax);
12399   ptr_reg (code, sizeflag);
12400 }
12401
12402 static void
12403 OP_DSreg (int code, int sizeflag)
12404 {
12405   if (intel_syntax)
12406     {
12407       switch (codep[-1])
12408         {
12409         case 0x6f:      /* outsw/outsl */
12410           intel_operand_size (z_mode, sizeflag);
12411           break;
12412         case 0xa5:      /* movsw/movsl/movsq */
12413         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12414         case 0xad:      /* lodsw/lodsl/lodsq */
12415           intel_operand_size (v_mode, sizeflag);
12416           break;
12417         default:
12418           intel_operand_size (b_mode, sizeflag);
12419         }
12420     }
12421   if ((prefixes
12422        & (PREFIX_CS
12423           | PREFIX_DS
12424           | PREFIX_SS
12425           | PREFIX_ES
12426           | PREFIX_FS
12427           | PREFIX_GS)) == 0)
12428     prefixes |= PREFIX_DS;
12429   append_seg ();
12430   ptr_reg (code, sizeflag);
12431 }
12432
12433 static void
12434 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12435 {
12436   int add;
12437   if (rex & REX_R)
12438     {
12439       USED_REX (REX_R);
12440       add = 8;
12441     }
12442   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12443     {
12444       lock_prefix = NULL;
12445       used_prefixes |= PREFIX_LOCK;
12446       add = 8;
12447     }
12448   else
12449     add = 0;
12450   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12451   oappend (scratchbuf + intel_syntax);
12452 }
12453
12454 static void
12455 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12456 {
12457   int add;
12458   USED_REX (REX_R);
12459   if (rex & REX_R)
12460     add = 8;
12461   else
12462     add = 0;
12463   if (intel_syntax)
12464     sprintf (scratchbuf, "db%d", modrm.reg + add);
12465   else
12466     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12467   oappend (scratchbuf);
12468 }
12469
12470 static void
12471 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12472 {
12473   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12474   oappend (scratchbuf + intel_syntax);
12475 }
12476
12477 static void
12478 OP_R (int bytemode, int sizeflag)
12479 {
12480   if (modrm.mod == 3)
12481     OP_E (bytemode, sizeflag);
12482   else
12483     BadOp ();
12484 }
12485
12486 static void
12487 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12488 {
12489   used_prefixes |= (prefixes & PREFIX_DATA);
12490   if (prefixes & PREFIX_DATA)
12491     {
12492       int add;
12493       USED_REX (REX_R);
12494       if (rex & REX_R)
12495         add = 8;
12496       else
12497         add = 0;
12498       sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12499     }
12500   else
12501     sprintf (scratchbuf, "%%mm%d", modrm.reg);
12502   oappend (scratchbuf + intel_syntax);
12503 }
12504
12505 static void
12506 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12507 {
12508   int add;
12509   USED_REX (REX_R);
12510   if (rex & REX_R)
12511     add = 8;
12512   else
12513     add = 0;
12514   if (need_vex && bytemode != xmm_mode)
12515     {
12516       switch (vex.length)
12517         {
12518         case 128:
12519           sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12520           break;
12521         case 256:
12522           sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12523           break;
12524         default:
12525           abort ();
12526         }
12527     }
12528   else
12529     sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12530   oappend (scratchbuf + intel_syntax);
12531 }
12532
12533 static void
12534 OP_EM (int bytemode, int sizeflag)
12535 {
12536   if (modrm.mod != 3)
12537     {
12538       if (intel_syntax && bytemode == v_mode)
12539         {
12540           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12541           used_prefixes |= (prefixes & PREFIX_DATA);
12542         }
12543       OP_E (bytemode, sizeflag);
12544       return;
12545     }
12546
12547   /* Skip mod/rm byte.  */
12548   MODRM_CHECK;
12549   codep++;
12550   used_prefixes |= (prefixes & PREFIX_DATA);
12551   if (prefixes & PREFIX_DATA)
12552     {
12553       int add;
12554
12555       USED_REX (REX_B);
12556       if (rex & REX_B)
12557         add = 8;
12558       else
12559         add = 0;
12560       sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12561     }
12562   else
12563     sprintf (scratchbuf, "%%mm%d", modrm.rm);
12564   oappend (scratchbuf + intel_syntax);
12565 }
12566
12567 /* cvt* are the only instructions in sse2 which have
12568    both SSE and MMX operands and also have 0x66 prefix
12569    in their opcode. 0x66 was originally used to differentiate
12570    between SSE and MMX instruction(operands). So we have to handle the
12571    cvt* separately using OP_EMC and OP_MXC */
12572 static void
12573 OP_EMC (int bytemode, int sizeflag)
12574 {
12575   if (modrm.mod != 3)
12576     {
12577       if (intel_syntax && bytemode == v_mode)
12578         {
12579           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12580           used_prefixes |= (prefixes & PREFIX_DATA);
12581         }
12582       OP_E (bytemode, sizeflag);
12583       return;
12584     }
12585
12586   /* Skip mod/rm byte.  */
12587   MODRM_CHECK;
12588   codep++;
12589   used_prefixes |= (prefixes & PREFIX_DATA);
12590   sprintf (scratchbuf, "%%mm%d", modrm.rm);
12591   oappend (scratchbuf + intel_syntax);
12592 }
12593
12594 static void
12595 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12596 {
12597   used_prefixes |= (prefixes & PREFIX_DATA);
12598   sprintf (scratchbuf, "%%mm%d", modrm.reg);
12599   oappend (scratchbuf + intel_syntax);
12600 }
12601
12602 static void
12603 OP_EX (int bytemode, int sizeflag)
12604 {
12605   int add;
12606   if (modrm.mod != 3)
12607     {
12608       OP_E (bytemode, sizeflag);
12609       return;
12610     }
12611   USED_REX (REX_B);
12612   if (rex & REX_B)
12613     add = 8;
12614   else
12615     add = 0;
12616
12617   /* Skip mod/rm byte.  */
12618   MODRM_CHECK;
12619   codep++;
12620   if (need_vex
12621       && bytemode != xmm_mode
12622       && bytemode != xmmq_mode)
12623     {
12624       switch (vex.length)
12625         {
12626         case 128:
12627           sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12628           break;
12629         case 256:
12630           sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12631           break;
12632         default:
12633           abort ();
12634         }
12635     }
12636   else
12637     sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12638   oappend (scratchbuf + intel_syntax);
12639 }
12640
12641 static void
12642 OP_MS (int bytemode, int sizeflag)
12643 {
12644   if (modrm.mod == 3)
12645     OP_EM (bytemode, sizeflag);
12646   else
12647     BadOp ();
12648 }
12649
12650 static void
12651 OP_XS (int bytemode, int sizeflag)
12652 {
12653   if (modrm.mod == 3)
12654     OP_EX (bytemode, sizeflag);
12655   else
12656     BadOp ();
12657 }
12658
12659 static void
12660 OP_M (int bytemode, int sizeflag)
12661 {
12662   if (modrm.mod == 3)
12663     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12664     BadOp ();
12665   else
12666     OP_E (bytemode, sizeflag);
12667 }
12668
12669 static void
12670 OP_0f07 (int bytemode, int sizeflag)
12671 {
12672   if (modrm.mod != 3 || modrm.rm != 0)
12673     BadOp ();
12674   else
12675     OP_E (bytemode, sizeflag);
12676 }
12677
12678 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12679    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12680
12681 static void
12682 NOP_Fixup1 (int bytemode, int sizeflag)
12683 {
12684   if ((prefixes & PREFIX_DATA) != 0
12685       || (rex != 0
12686           && rex != 0x48
12687           && address_mode == mode_64bit))
12688     OP_REG (bytemode, sizeflag);
12689   else
12690     strcpy (obuf, "nop");
12691 }
12692
12693 static void
12694 NOP_Fixup2 (int bytemode, int sizeflag)
12695 {
12696   if ((prefixes & PREFIX_DATA) != 0
12697       || (rex != 0
12698           && rex != 0x48
12699           && address_mode == mode_64bit))
12700     OP_IMREG (bytemode, sizeflag);
12701 }
12702
12703 static const char *const Suffix3DNow[] = {
12704 /* 00 */        NULL,           NULL,           NULL,           NULL,
12705 /* 04 */        NULL,           NULL,           NULL,           NULL,
12706 /* 08 */        NULL,           NULL,           NULL,           NULL,
12707 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12708 /* 10 */        NULL,           NULL,           NULL,           NULL,
12709 /* 14 */        NULL,           NULL,           NULL,           NULL,
12710 /* 18 */        NULL,           NULL,           NULL,           NULL,
12711 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12712 /* 20 */        NULL,           NULL,           NULL,           NULL,
12713 /* 24 */        NULL,           NULL,           NULL,           NULL,
12714 /* 28 */        NULL,           NULL,           NULL,           NULL,
12715 /* 2C */        NULL,           NULL,           NULL,           NULL,
12716 /* 30 */        NULL,           NULL,           NULL,           NULL,
12717 /* 34 */        NULL,           NULL,           NULL,           NULL,
12718 /* 38 */        NULL,           NULL,           NULL,           NULL,
12719 /* 3C */        NULL,           NULL,           NULL,           NULL,
12720 /* 40 */        NULL,           NULL,           NULL,           NULL,
12721 /* 44 */        NULL,           NULL,           NULL,           NULL,
12722 /* 48 */        NULL,           NULL,           NULL,           NULL,
12723 /* 4C */        NULL,           NULL,           NULL,           NULL,
12724 /* 50 */        NULL,           NULL,           NULL,           NULL,
12725 /* 54 */        NULL,           NULL,           NULL,           NULL,
12726 /* 58 */        NULL,           NULL,           NULL,           NULL,
12727 /* 5C */        NULL,           NULL,           NULL,           NULL,
12728 /* 60 */        NULL,           NULL,           NULL,           NULL,
12729 /* 64 */        NULL,           NULL,           NULL,           NULL,
12730 /* 68 */        NULL,           NULL,           NULL,           NULL,
12731 /* 6C */        NULL,           NULL,           NULL,           NULL,
12732 /* 70 */        NULL,           NULL,           NULL,           NULL,
12733 /* 74 */        NULL,           NULL,           NULL,           NULL,
12734 /* 78 */        NULL,           NULL,           NULL,           NULL,
12735 /* 7C */        NULL,           NULL,           NULL,           NULL,
12736 /* 80 */        NULL,           NULL,           NULL,           NULL,
12737 /* 84 */        NULL,           NULL,           NULL,           NULL,
12738 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12739 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12740 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12741 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12742 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12743 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12744 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12745 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12746 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12747 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12748 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12749 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12750 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12751 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12752 /* C0 */        NULL,           NULL,           NULL,           NULL,
12753 /* C4 */        NULL,           NULL,           NULL,           NULL,
12754 /* C8 */        NULL,           NULL,           NULL,           NULL,
12755 /* CC */        NULL,           NULL,           NULL,           NULL,
12756 /* D0 */        NULL,           NULL,           NULL,           NULL,
12757 /* D4 */        NULL,           NULL,           NULL,           NULL,
12758 /* D8 */        NULL,           NULL,           NULL,           NULL,
12759 /* DC */        NULL,           NULL,           NULL,           NULL,
12760 /* E0 */        NULL,           NULL,           NULL,           NULL,
12761 /* E4 */        NULL,           NULL,           NULL,           NULL,
12762 /* E8 */        NULL,           NULL,           NULL,           NULL,
12763 /* EC */        NULL,           NULL,           NULL,           NULL,
12764 /* F0 */        NULL,           NULL,           NULL,           NULL,
12765 /* F4 */        NULL,           NULL,           NULL,           NULL,
12766 /* F8 */        NULL,           NULL,           NULL,           NULL,
12767 /* FC */        NULL,           NULL,           NULL,           NULL,
12768 };
12769
12770 static void
12771 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12772 {
12773   const char *mnemonic;
12774
12775   FETCH_DATA (the_info, codep + 1);
12776   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12777      place where an 8-bit immediate would normally go.  ie. the last
12778      byte of the instruction.  */
12779   obufp = mnemonicendp;
12780   mnemonic = Suffix3DNow[*codep++ & 0xff];
12781   if (mnemonic)
12782     oappend (mnemonic);
12783   else
12784     {
12785       /* Since a variable sized modrm/sib chunk is between the start
12786          of the opcode (0x0f0f) and the opcode suffix, we need to do
12787          all the modrm processing first, and don't know until now that
12788          we have a bad opcode.  This necessitates some cleaning up.  */
12789       op_out[0][0] = '\0';
12790       op_out[1][0] = '\0';
12791       BadOp ();
12792     }
12793   mnemonicendp = obufp;
12794 }
12795
12796 static struct op simd_cmp_op[] =
12797 {
12798   { STRING_COMMA_LEN ("eq") },
12799   { STRING_COMMA_LEN ("lt") },
12800   { STRING_COMMA_LEN ("le") },
12801   { STRING_COMMA_LEN ("unord") },
12802   { STRING_COMMA_LEN ("neq") },
12803   { STRING_COMMA_LEN ("nlt") },
12804   { STRING_COMMA_LEN ("nle") },
12805   { STRING_COMMA_LEN ("ord") }
12806 };
12807
12808 static void
12809 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12810 {
12811   unsigned int cmp_type;
12812
12813   FETCH_DATA (the_info, codep + 1);
12814   cmp_type = *codep++ & 0xff;
12815   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12816     {
12817       char suffix [3];
12818       char *p = mnemonicendp - 2;
12819       suffix[0] = p[0];
12820       suffix[1] = p[1];
12821       suffix[2] = '\0';
12822       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12823       mnemonicendp += simd_cmp_op[cmp_type].len;
12824     }
12825   else
12826     {
12827       /* We have a reserved extension byte.  Output it directly.  */
12828       scratchbuf[0] = '$';
12829       print_operand_value (scratchbuf + 1, 1, cmp_type);
12830       oappend (scratchbuf + intel_syntax);
12831       scratchbuf[0] = '\0';
12832     }
12833 }
12834
12835 static void
12836 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12837           int sizeflag ATTRIBUTE_UNUSED)
12838 {
12839   /* mwait %eax,%ecx  */
12840   if (!intel_syntax)
12841     {
12842       const char **names = (address_mode == mode_64bit
12843                             ? names64 : names32);
12844       strcpy (op_out[0], names[0]);
12845       strcpy (op_out[1], names[1]);
12846       two_source_ops = 1;
12847     }
12848   /* Skip mod/rm byte.  */
12849   MODRM_CHECK;
12850   codep++;
12851 }
12852
12853 static void
12854 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12855             int sizeflag ATTRIBUTE_UNUSED)
12856 {
12857   /* monitor %eax,%ecx,%edx"  */
12858   if (!intel_syntax)
12859     {
12860       const char **op1_names;
12861       const char **names = (address_mode == mode_64bit
12862                             ? names64 : names32);
12863
12864       if (!(prefixes & PREFIX_ADDR))
12865         op1_names = (address_mode == mode_16bit
12866                      ? names16 : names);
12867       else
12868         {
12869           /* Remove "addr16/addr32".  */
12870           addr_prefix = NULL;
12871           op1_names = (address_mode != mode_32bit
12872                        ? names32 : names16);
12873           used_prefixes |= PREFIX_ADDR;
12874         }
12875       strcpy (op_out[0], op1_names[0]);
12876       strcpy (op_out[1], names[1]);
12877       strcpy (op_out[2], names[2]);
12878       two_source_ops = 1;
12879     }
12880   /* Skip mod/rm byte.  */
12881   MODRM_CHECK;
12882   codep++;
12883 }
12884
12885 static void
12886 BadOp (void)
12887 {
12888   /* Throw away prefixes and 1st. opcode byte.  */
12889   codep = insn_codep + 1;
12890   oappend ("(bad)");
12891 }
12892
12893 static void
12894 REP_Fixup (int bytemode, int sizeflag)
12895 {
12896   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12897      lods and stos.  */
12898   if (prefixes & PREFIX_REPZ)
12899     repz_prefix = "rep ";
12900
12901   switch (bytemode)
12902     {
12903     case al_reg:
12904     case eAX_reg:
12905     case indir_dx_reg:
12906       OP_IMREG (bytemode, sizeflag);
12907       break;
12908     case eDI_reg:
12909       OP_ESreg (bytemode, sizeflag);
12910       break;
12911     case eSI_reg:
12912       OP_DSreg (bytemode, sizeflag);
12913       break;
12914     default:
12915       abort ();
12916       break;
12917     }
12918 }
12919
12920 static void
12921 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12922 {
12923   USED_REX (REX_W);
12924   if (rex & REX_W)
12925     {
12926       /* Change cmpxchg8b to cmpxchg16b.  */
12927       char *p = mnemonicendp - 2;
12928       mnemonicendp = stpcpy (p, "16b");
12929       bytemode = o_mode;
12930     }
12931   OP_M (bytemode, sizeflag);
12932 }
12933
12934 static void
12935 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
12936 {
12937   if (need_vex)
12938     {
12939       switch (vex.length)
12940         {
12941         case 128:
12942           sprintf (scratchbuf, "%%xmm%d", reg);
12943           break;
12944         case 256:
12945           sprintf (scratchbuf, "%%ymm%d", reg);
12946           break;
12947         default:
12948           abort ();
12949         }
12950     }
12951   else
12952     sprintf (scratchbuf, "%%xmm%d", reg);
12953   oappend (scratchbuf + intel_syntax);
12954 }
12955
12956 static void
12957 CRC32_Fixup (int bytemode, int sizeflag)
12958 {
12959   /* Add proper suffix to "crc32".  */
12960   char *p = mnemonicendp;
12961
12962   switch (bytemode)
12963     {
12964     case b_mode:
12965       if (intel_syntax)
12966         goto skip;
12967
12968       *p++ = 'b';
12969       break;
12970     case v_mode:
12971       if (intel_syntax)
12972         goto skip;
12973
12974       USED_REX (REX_W);
12975       if (rex & REX_W)
12976         *p++ = 'q';
12977       else if (sizeflag & DFLAG)
12978         *p++ = 'l';
12979       else
12980         *p++ = 'w';
12981       used_prefixes |= (prefixes & PREFIX_DATA);
12982       break;
12983     default:
12984       oappend (INTERNAL_DISASSEMBLER_ERROR);
12985       break;
12986     }
12987   mnemonicendp = p;
12988   *p = '\0';
12989
12990 skip:
12991   if (modrm.mod == 3)
12992     {
12993       int add;
12994
12995       /* Skip mod/rm byte.  */
12996       MODRM_CHECK;
12997       codep++;
12998
12999       USED_REX (REX_B);
13000       add = (rex & REX_B) ? 8 : 0;
13001       if (bytemode == b_mode)
13002         {
13003           USED_REX (0);
13004           if (rex)
13005             oappend (names8rex[modrm.rm + add]);
13006           else
13007             oappend (names8[modrm.rm + add]);
13008         }
13009       else
13010         {
13011           USED_REX (REX_W);
13012           if (rex & REX_W)
13013             oappend (names64[modrm.rm + add]);
13014           else if ((prefixes & PREFIX_DATA))
13015             oappend (names16[modrm.rm + add]);
13016           else
13017             oappend (names32[modrm.rm + add]);
13018         }
13019     }
13020   else
13021     OP_E (bytemode, sizeflag);
13022 }
13023
13024 /* Print a DREX argument as either a register or memory operation.  */
13025 static void
13026 print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
13027 {
13028   if (reg == DREX_REG_UNKNOWN)
13029     BadOp ();
13030
13031   else if (reg != DREX_REG_MEMORY)
13032     {
13033       sprintf (scratchbuf, "%%xmm%d", reg);
13034       oappend (scratchbuf + intel_syntax);
13035     }
13036
13037   else
13038     OP_E_extended (bytemode, sizeflag, 1);
13039 }
13040
13041 /* SSE5 instructions that have 4 arguments are encoded as:
13042    0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
13043
13044    The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
13045    the DREX field (0x8) to determine how the arguments are laid out.
13046    The destination register must be the same register as one of the
13047    inputs, and it is encoded in the DREX byte.  No REX prefix is used
13048    for these instructions, since the DREX field contains the 3 extension
13049    bits provided by the REX prefix.
13050
13051    The bytemode argument adds 2 extra bits for passing extra information:
13052         DREX_OC1        -- Set the OC1 bit to indicate dest == 1st arg
13053         DREX_NO_OC0     -- OC0 in DREX is invalid
13054         (but pretend it is set).  */
13055
13056 static void
13057 OP_DREX4 (int flag_bytemode, int sizeflag)
13058 {
13059   unsigned int drex_byte;
13060   unsigned int regs[4];
13061   unsigned int modrm_regmem;
13062   unsigned int modrm_reg;
13063   unsigned int drex_reg;
13064   int bytemode;
13065   int rex_save = rex;
13066   int rex_used_save = rex_used;
13067   int has_sib = 0;
13068   int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
13069   int oc0;
13070   int i;
13071
13072   bytemode = flag_bytemode & ~ DREX_MASK;
13073
13074   for (i = 0; i < 4; i++)
13075     regs[i] = DREX_REG_UNKNOWN;
13076
13077   /* Determine if we have a SIB byte in addition to MODRM before the
13078      DREX byte.  */
13079   if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13080       && (modrm.mod != 3)
13081       && (modrm.rm == 4))
13082     has_sib = 1;
13083
13084   /* Get the DREX byte.  */
13085   FETCH_DATA (the_info, codep + 2 + has_sib);
13086   drex_byte = codep[has_sib+1];
13087   drex_reg = DREX_XMM (drex_byte);
13088   modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13089
13090   /* Is OC0 legal?  If not, hardwire oc0 == 1.  */
13091   if (flag_bytemode & DREX_NO_OC0)
13092     {
13093       oc0 = 1;
13094       if (DREX_OC0 (drex_byte))
13095         BadOp ();
13096     }
13097   else
13098     oc0 = DREX_OC0 (drex_byte);
13099
13100   if (modrm.mod == 3)
13101     {
13102       /* regmem == register  */
13103       modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13104       rex = rex_used = 0;
13105       /* skip modrm/drex since we don't call OP_E_extended  */
13106       codep += 2;
13107     }
13108   else
13109     {
13110       /* regmem == memory, fill in appropriate REX bits  */
13111       modrm_regmem = DREX_REG_MEMORY;
13112       rex = drex_byte & (REX_B | REX_X | REX_R);
13113       if (rex)
13114         rex |= REX_OPCODE;
13115       rex_used = rex;
13116     }
13117
13118   /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13119      order.  */
13120   switch (oc0 + oc1)
13121     {
13122     default:
13123       BadOp ();
13124       return;
13125
13126     case 0:
13127       regs[0] = modrm_regmem;
13128       regs[1] = modrm_reg;
13129       regs[2] = drex_reg;
13130       regs[3] = drex_reg;
13131       break;
13132
13133     case 1:
13134       regs[0] = modrm_reg;
13135       regs[1] = modrm_regmem;
13136       regs[2] = drex_reg;
13137       regs[3] = drex_reg;
13138       break;
13139
13140     case 2:
13141       regs[0] = drex_reg;
13142       regs[1] = modrm_regmem;
13143       regs[2] = modrm_reg;
13144       regs[3] = drex_reg;
13145       break;
13146
13147     case 3:
13148       regs[0] = drex_reg;
13149       regs[1] = modrm_reg;
13150       regs[2] = modrm_regmem;
13151       regs[3] = drex_reg;
13152       break;
13153     }
13154
13155   /* Print out the arguments.  */
13156   for (i = 0; i < 4; i++)
13157     {
13158       int j = (intel_syntax) ? 3 - i : i;
13159       if (i > 0)
13160         {
13161           *obufp++ = ',';
13162           *obufp = '\0';
13163         }
13164
13165       print_drex_arg (regs[j], bytemode, sizeflag);
13166     }
13167
13168   rex = rex_save;
13169   rex_used = rex_used_save;
13170 }
13171
13172 /* SSE5 instructions that have 3 arguments, and are encoded as:
13173    0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>    (or)
13174    0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
13175
13176    The DREX field has 1 bit (0x8) to determine how the arguments are
13177    laid out. The destination register is encoded in the DREX byte.
13178    No REX prefix is used for these instructions, since the DREX field
13179    contains the 3 extension bits provided by the REX prefix.  */
13180
13181 static void
13182 OP_DREX3 (int flag_bytemode, int sizeflag)
13183 {
13184   unsigned int drex_byte;
13185   unsigned int regs[3];
13186   unsigned int modrm_regmem;
13187   unsigned int modrm_reg;
13188   unsigned int drex_reg;
13189   int bytemode;
13190   int rex_save = rex;
13191   int rex_used_save = rex_used;
13192   int has_sib = 0;
13193   int oc0;
13194   int i;
13195
13196   bytemode = flag_bytemode & ~ DREX_MASK;
13197
13198   for (i = 0; i < 3; i++)
13199     regs[i] = DREX_REG_UNKNOWN;
13200
13201   /* Determine if we have a SIB byte in addition to MODRM before the
13202      DREX byte.  */
13203   if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13204       && (modrm.mod != 3)
13205       && (modrm.rm == 4))
13206     has_sib = 1;
13207
13208   /* Get the DREX byte.  */
13209   FETCH_DATA (the_info, codep + 2 + has_sib);
13210   drex_byte = codep[has_sib+1];
13211   drex_reg = DREX_XMM (drex_byte);
13212   modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13213
13214   /* Is OC0 legal?  If not, hardwire oc0 == 0 */
13215   oc0 = DREX_OC0 (drex_byte);
13216   if ((flag_bytemode & DREX_NO_OC0) && oc0)
13217     BadOp ();
13218
13219   if (modrm.mod == 3)
13220     {
13221       /* regmem == register */
13222       modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13223       rex = rex_used = 0;
13224       /* skip modrm/drex since we don't call OP_E_extended.  */
13225       codep += 2;
13226     }
13227   else
13228     {
13229       /* regmem == memory, fill in appropriate REX bits.  */
13230       modrm_regmem = DREX_REG_MEMORY;
13231       rex = drex_byte & (REX_B | REX_X | REX_R);
13232       if (rex)
13233         rex |= REX_OPCODE;
13234       rex_used = rex;
13235     }
13236
13237   /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13238      order.  */
13239   switch (oc0)
13240     {
13241     default:
13242       BadOp ();
13243       return;
13244
13245     case 0:
13246       regs[0] = modrm_regmem;
13247       regs[1] = modrm_reg;
13248       regs[2] = drex_reg;
13249       break;
13250
13251     case 1:
13252       regs[0] = modrm_reg;
13253       regs[1] = modrm_regmem;
13254       regs[2] = drex_reg;
13255       break;
13256     }
13257
13258   /* Print out the arguments.  */
13259   for (i = 0; i < 3; i++)
13260     {
13261       int j = (intel_syntax) ? 2 - i : i;
13262       if (i > 0)
13263         {
13264           *obufp++ = ',';
13265           *obufp = '\0';
13266         }
13267
13268       print_drex_arg (regs[j], bytemode, sizeflag);
13269     }
13270
13271   rex = rex_save;
13272   rex_used = rex_used_save;
13273 }
13274
13275 /* Emit a floating point comparison for comp<xx> instructions.  */
13276
13277 static void
13278 OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
13279               int sizeflag ATTRIBUTE_UNUSED)
13280 {
13281   unsigned char byte;
13282
13283   static const char *const cmp_test[] = {
13284     "eq",
13285     "lt",
13286     "le",
13287     "unord",
13288     "ne",
13289     "nlt",
13290     "nle",
13291     "ord",
13292     "ueq",
13293     "ult",
13294     "ule",
13295     "false",
13296     "une",
13297     "unlt",
13298     "unle",
13299     "true"
13300   };
13301
13302   FETCH_DATA (the_info, codep + 1);
13303   byte = *codep & 0xff;
13304
13305   if (byte >= ARRAY_SIZE (cmp_test)
13306       || obuf[0] != 'c'
13307       || obuf[1] != 'o'
13308       || obuf[2] != 'm')
13309     {
13310       /* The instruction isn't one we know about, so just append the
13311          extension byte as a numeric value.  */
13312       OP_I (b_mode, 0);
13313     }
13314
13315   else
13316     {
13317       sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
13318       mnemonicendp = stpcpy (obuf, scratchbuf);
13319       codep++;
13320     }
13321 }
13322
13323 /* Emit an integer point comparison for pcom<xx> instructions,
13324    rewriting the instruction to have the test inside of it.  */
13325
13326 static void
13327 OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
13328               int sizeflag ATTRIBUTE_UNUSED)
13329 {
13330   unsigned char byte;
13331
13332   static const char *const cmp_test[] = {
13333     "lt",
13334     "le",
13335     "gt",
13336     "ge",
13337     "eq",
13338     "ne",
13339     "false",
13340     "true"
13341   };
13342
13343   FETCH_DATA (the_info, codep + 1);
13344   byte = *codep & 0xff;
13345
13346   if (byte >= ARRAY_SIZE (cmp_test)
13347       || obuf[0] != 'p'
13348       || obuf[1] != 'c'
13349       || obuf[2] != 'o'
13350       || obuf[3] != 'm')
13351     {
13352       /* The instruction isn't one we know about, so just print the
13353          comparison test byte as a numeric value.  */
13354       OP_I (b_mode, 0);
13355     }
13356
13357   else
13358     {
13359       sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
13360       mnemonicendp = stpcpy (obuf, scratchbuf);
13361       codep++;
13362     }
13363 }
13364
13365 /* Display the destination register operand for instructions with
13366    VEX. */
13367
13368 static void
13369 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13370 {
13371   if (!need_vex)
13372     abort ();
13373
13374   if (!need_vex_reg)
13375     return;
13376
13377   switch (vex.length)
13378     {
13379     case 128:
13380       switch (bytemode)
13381         {
13382         case vex_mode:
13383         case vex128_mode:
13384           break;
13385         default:
13386           abort ();
13387           return;
13388         }
13389
13390       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13391       break;
13392     case 256:
13393       switch (bytemode)
13394         {
13395         case vex_mode:
13396         case vex256_mode:
13397           break;
13398         default:
13399           abort ();
13400           return;
13401         }
13402
13403       sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13404       break;
13405     default:
13406       abort ();
13407       break;
13408     }
13409   oappend (scratchbuf + intel_syntax);
13410 }
13411
13412 /* Get the VEX immediate byte without moving codep.  */
13413
13414 static unsigned char
13415 get_vex_imm8 (int sizeflag)
13416 {
13417   int bytes_before_imm = 0;
13418
13419   /* Skip mod/rm byte.   */
13420   MODRM_CHECK;
13421   codep++;
13422
13423   if (modrm.mod != 3)
13424     {
13425       /* There are SIB/displacement bytes.  */
13426       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13427         {
13428           /* 32/64 bit address mode */
13429           int base = modrm.rm;
13430
13431           /* Check SIB byte.  */
13432           if (base == 4)
13433             {
13434               FETCH_DATA (the_info, codep + 1);
13435               base = *codep & 7;
13436               bytes_before_imm++;
13437             }
13438
13439           switch (modrm.mod)
13440             {
13441             case 0:
13442               /* When modrm.rm == 5 or modrm.rm == 4 and base in
13443                  SIB == 5, there is a 4 byte displacement.  */
13444               if (base != 5)
13445                 /* No displacement. */
13446                 break;
13447             case 2:
13448               /* 4 byte displacement.  */
13449               bytes_before_imm += 4;
13450               break;
13451             case 1:
13452               /* 1 byte displacement.  */
13453               bytes_before_imm++;
13454               break;
13455             }
13456         }
13457       else
13458         { /* 16 bit address mode */
13459           switch (modrm.mod)
13460             {
13461             case 0:
13462               /* When modrm.rm == 6, there is a 2 byte displacement.  */
13463               if (modrm.rm != 6)
13464                 /* No displacement. */
13465                 break;
13466             case 2:
13467               /* 2 byte displacement.  */
13468               bytes_before_imm += 2;
13469               break;
13470             case 1:
13471               /* 1 byte displacement.  */
13472               bytes_before_imm++;
13473               break;
13474             }
13475         }
13476     }
13477
13478   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
13479   return codep [bytes_before_imm];
13480 }
13481
13482 static void
13483 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
13484 {
13485   if (reg == -1 && modrm.mod != 3)
13486     {
13487       OP_E_memory (bytemode, sizeflag, 0);
13488       return;
13489     }
13490   else
13491     {
13492       if (reg == -1)
13493         {
13494           reg = modrm.rm;
13495           USED_REX (REX_B);
13496           if (rex & REX_B)
13497             reg += 8;
13498         }
13499       else if (reg > 7 && address_mode != mode_64bit)
13500         BadOp ();
13501     }
13502
13503   switch (vex.length)
13504     {
13505     case 128:
13506       sprintf (scratchbuf, "%%xmm%d", reg);
13507       break;
13508     case 256:
13509       sprintf (scratchbuf, "%%ymm%d", reg);
13510       break;
13511     default:
13512       abort ();
13513     }
13514   oappend (scratchbuf + intel_syntax);
13515 }
13516
13517 static void
13518 OP_EX_VexImmW (int bytemode, int sizeflag)
13519 {
13520   int reg = -1;
13521   static unsigned char vex_imm8;
13522
13523   if (!vex_w_done)
13524     {
13525       vex_imm8 = get_vex_imm8 (sizeflag);
13526       if (vex.w)
13527         reg = vex_imm8 >> 4;
13528       vex_w_done = 1;
13529     }
13530   else
13531     {
13532       if (!vex.w)
13533         reg = vex_imm8 >> 4;
13534     }
13535
13536   OP_EX_VexReg (bytemode, sizeflag, reg);
13537 }
13538
13539 static void
13540 OP_EX_VexW (int bytemode, int sizeflag)
13541 {
13542   int reg = -1;
13543
13544   if (!vex_w_done)
13545     {
13546       vex_w_done = 1;
13547       if (vex.w)
13548         reg = vex.register_specifier;
13549     }
13550   else
13551     {
13552       if (!vex.w)
13553         reg = vex.register_specifier;
13554     }
13555
13556   OP_EX_VexReg (bytemode, sizeflag, reg);
13557 }
13558
13559 static void
13560 OP_VEX_FMA (int bytemode, int sizeflag)
13561 {
13562   int reg = get_vex_imm8 (sizeflag) >> 4;
13563
13564   if (reg > 7 && address_mode != mode_64bit)
13565     BadOp ();
13566
13567   switch (vex.length)
13568     {
13569     case 128:
13570       switch (bytemode)
13571         {
13572         case vex_mode:
13573         case vex128_mode:
13574           break;
13575         default:
13576           abort ();
13577           return;
13578         }
13579
13580       sprintf (scratchbuf, "%%xmm%d", reg);
13581       break;
13582     case 256:
13583       switch (bytemode)
13584         {
13585         case vex_mode:
13586           break;
13587         default:
13588           abort ();
13589           return;
13590         }
13591
13592       sprintf (scratchbuf, "%%ymm%d", reg);
13593       break;
13594     default:
13595       abort ();
13596     }
13597   oappend (scratchbuf + intel_syntax);
13598 }
13599
13600 static void
13601 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
13602              int sizeflag ATTRIBUTE_UNUSED)
13603 {
13604   /* Skip the immediate byte and check for invalid bits.  */
13605   FETCH_DATA (the_info, codep + 1);
13606   if (*codep++ & 0xf)
13607     BadOp ();
13608 }
13609
13610 static void
13611 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13612 {
13613   int reg;
13614   FETCH_DATA (the_info, codep + 1);
13615   reg = *codep++;
13616
13617   if (bytemode != x_mode)
13618     abort ();
13619
13620   if (reg & 0xf)
13621       BadOp ();
13622
13623   reg >>= 4;
13624   if (reg > 7 && address_mode != mode_64bit)
13625     BadOp ();
13626
13627   switch (vex.length)
13628     {
13629     case 128:
13630       sprintf (scratchbuf, "%%xmm%d", reg);
13631       break;
13632     case 256:
13633       sprintf (scratchbuf, "%%ymm%d", reg);
13634       break;
13635     default:
13636       abort ();
13637     }
13638   oappend (scratchbuf + intel_syntax);
13639 }
13640
13641 static void
13642 OP_XMM_VexW (int bytemode, int sizeflag)
13643 {
13644   /* Turn off the REX.W bit since it is used for swapping operands
13645      now.  */
13646   rex &= ~REX_W;
13647   OP_XMM (bytemode, sizeflag);
13648 }
13649
13650 static void
13651 OP_EX_Vex (int bytemode, int sizeflag)
13652 {
13653   if (modrm.mod != 3)
13654     {
13655       if (vex.register_specifier != 0)
13656         BadOp ();
13657       need_vex_reg = 0;
13658     }
13659   OP_EX (bytemode, sizeflag);
13660 }
13661
13662 static void
13663 OP_XMM_Vex (int bytemode, int sizeflag)
13664 {
13665   if (modrm.mod != 3)
13666     {
13667       if (vex.register_specifier != 0)
13668         BadOp ();
13669       need_vex_reg = 0;
13670     }
13671   OP_XMM (bytemode, sizeflag);
13672 }
13673
13674 static void
13675 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13676 {
13677   switch (vex.length)
13678     {
13679     case 128:
13680       mnemonicendp = stpcpy (obuf, "vzeroupper");
13681       break;
13682     case 256:
13683       mnemonicendp = stpcpy (obuf, "vzeroall");
13684       break;
13685     default:
13686       abort ();
13687     }
13688 }
13689
13690 static struct op vex_cmp_op[] =
13691 {
13692   { STRING_COMMA_LEN ("eq") },
13693   { STRING_COMMA_LEN ("lt") },
13694   { STRING_COMMA_LEN ("le") },
13695   { STRING_COMMA_LEN ("unord") },
13696   { STRING_COMMA_LEN ("neq") },
13697   { STRING_COMMA_LEN ("nlt") },
13698   { STRING_COMMA_LEN ("nle") },
13699   { STRING_COMMA_LEN ("ord") },
13700   { STRING_COMMA_LEN ("eq_uq") },
13701   { STRING_COMMA_LEN ("nge") },
13702   { STRING_COMMA_LEN ("ngt") },
13703   { STRING_COMMA_LEN ("false") },
13704   { STRING_COMMA_LEN ("neq_oq") },
13705   { STRING_COMMA_LEN ("ge") },
13706   { STRING_COMMA_LEN ("gt") },
13707   { STRING_COMMA_LEN ("true") },
13708   { STRING_COMMA_LEN ("eq_os") },
13709   { STRING_COMMA_LEN ("lt_oq") },
13710   { STRING_COMMA_LEN ("le_oq") },
13711   { STRING_COMMA_LEN ("unord_s") },
13712   { STRING_COMMA_LEN ("neq_us") },
13713   { STRING_COMMA_LEN ("nlt_uq") },
13714   { STRING_COMMA_LEN ("nle_uq") },
13715   { STRING_COMMA_LEN ("ord_s") },
13716   { STRING_COMMA_LEN ("eq_us") },
13717   { STRING_COMMA_LEN ("nge_uq") },
13718   { STRING_COMMA_LEN ("ngt_uq") },
13719   { STRING_COMMA_LEN ("false_os") },
13720   { STRING_COMMA_LEN ("neq_os") },
13721   { STRING_COMMA_LEN ("ge_oq") },
13722   { STRING_COMMA_LEN ("gt_oq") },
13723   { STRING_COMMA_LEN ("true_us") },
13724 };
13725
13726 static void
13727 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13728 {
13729   unsigned int cmp_type;
13730
13731   FETCH_DATA (the_info, codep + 1);
13732   cmp_type = *codep++ & 0xff;
13733   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13734     {
13735       char suffix [3];
13736       char *p = mnemonicendp - 2;
13737       suffix[0] = p[0];
13738       suffix[1] = p[1];
13739       suffix[2] = '\0';
13740       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13741       mnemonicendp += vex_cmp_op[cmp_type].len;
13742     }
13743   else
13744     {
13745       /* We have a reserved extension byte.  Output it directly.  */
13746       scratchbuf[0] = '$';
13747       print_operand_value (scratchbuf + 1, 1, cmp_type);
13748       oappend (scratchbuf + intel_syntax);
13749       scratchbuf[0] = '\0';
13750     }
13751 }
13752
13753 static const struct op pclmul_op[] =
13754 {
13755   { STRING_COMMA_LEN ("lql") },
13756   { STRING_COMMA_LEN ("hql") },
13757   { STRING_COMMA_LEN ("lqh") },
13758   { STRING_COMMA_LEN ("hqh") }
13759 };
13760
13761 static void
13762 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13763               int sizeflag ATTRIBUTE_UNUSED)
13764 {
13765   unsigned int pclmul_type;
13766
13767   FETCH_DATA (the_info, codep + 1);
13768   pclmul_type = *codep++ & 0xff;
13769   switch (pclmul_type)
13770     {
13771     case 0x10:
13772       pclmul_type = 2;
13773       break;
13774     case 0x11:
13775       pclmul_type = 3;
13776       break;
13777     default:
13778       break;
13779     }
13780   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13781     {
13782       char suffix [4];
13783       char *p = mnemonicendp - 3;
13784       suffix[0] = p[0];
13785       suffix[1] = p[1];
13786       suffix[2] = p[2];
13787       suffix[3] = '\0';
13788       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13789       mnemonicendp += pclmul_op[pclmul_type].len;
13790     }
13791   else
13792     {
13793       /* We have a reserved extension byte.  Output it directly.  */
13794       scratchbuf[0] = '$';
13795       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13796       oappend (scratchbuf + intel_syntax);
13797       scratchbuf[0] = '\0';
13798     }
13799 }
13800
13801 static const struct op vpermil2_op[] =
13802 {
13803   { STRING_COMMA_LEN ("td") },
13804   { STRING_COMMA_LEN ("td") },
13805   { STRING_COMMA_LEN ("mo") },
13806   { STRING_COMMA_LEN ("mz") }
13807 };
13808
13809 static void
13810 VPERMIL2_Fixup (int bytemode ATTRIBUTE_UNUSED,
13811                 int sizeflag ATTRIBUTE_UNUSED)
13812 {
13813   unsigned int vpermil2_type;
13814
13815   FETCH_DATA (the_info, codep + 1);
13816   vpermil2_type = *codep++ & 0xf;
13817   if (vpermil2_type < ARRAY_SIZE (vpermil2_op))
13818     {
13819       char suffix [4];
13820       char *p = mnemonicendp - 3;
13821       suffix[0] = p[0];
13822       suffix[1] = p[1];
13823       suffix[2] = p[2];
13824       suffix[3] = '\0';
13825       sprintf (p, "%s%s", vpermil2_op[vpermil2_type].name, suffix);
13826       mnemonicendp += vpermil2_op[vpermil2_type].len;
13827     }
13828   else
13829     {
13830       /* We have a reserved extension byte.  Output it directly.  */
13831       scratchbuf[0] = '$';
13832       print_operand_value (scratchbuf + 1, 1, vpermil2_type);
13833       oappend (scratchbuf + intel_syntax);
13834       scratchbuf[0] = '\0';
13835     }
13836 }
13837
13838 static void
13839 MOVBE_Fixup (int bytemode, int sizeflag)
13840 {
13841   /* Add proper suffix to "movbe".  */
13842   char *p = mnemonicendp;
13843
13844   switch (bytemode)
13845     {
13846     case v_mode:
13847       if (intel_syntax)
13848         goto skip;
13849
13850       USED_REX (REX_W);
13851       if (sizeflag & SUFFIX_ALWAYS)
13852         {
13853           if (rex & REX_W)
13854             *p++ = 'q';
13855           else if (sizeflag & DFLAG)
13856             *p++ = 'l';
13857           else
13858             *p++ = 'w';
13859         }
13860       used_prefixes |= (prefixes & PREFIX_DATA);
13861       break;
13862     default:
13863       oappend (INTERNAL_DISASSEMBLER_ERROR);
13864       break;
13865     }
13866   mnemonicendp = p;
13867   *p = '\0';
13868
13869 skip:
13870   OP_M (bytemode, sizeflag);
13871 }