1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void OP_LWPCB_E (int, int);
120 static void OP_LWP_E (int, int);
121 static void OP_Vex_2src_1 (int, int);
122 static void OP_Vex_2src_2 (int, int);
124 static void MOVBE_Fixup (int, int);
126 static void OP_Mask (int, int);
129 /* Points to first byte not fetched. */
130 bfd_byte
*max_fetched
;
131 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
144 enum address_mode address_mode
;
146 /* Flags for the prefixes for the current instruction. See below. */
149 /* REX prefix the current instruction. See below. */
151 /* Bits of REX we've already used. */
153 /* REX bits in original REX prefix ignored. */
154 static int rex_ignored
;
155 /* Mark parts used in the REX prefix. When we are testing for
156 empty prefix (for 8bit register REX extension), just mask it
157 out. Otherwise test for REX bit is excuse for existence of REX
158 only in case value is nonzero. */
159 #define USED_REX(value) \
164 rex_used |= (value) | REX_OPCODE; \
167 rex_used |= REX_OPCODE; \
170 /* Flags for prefixes which we somehow handled when printing the
171 current instruction. */
172 static int used_prefixes
;
174 /* Flags stored in PREFIXES. */
175 #define PREFIX_REPZ 1
176 #define PREFIX_REPNZ 2
177 #define PREFIX_LOCK 4
179 #define PREFIX_SS 0x10
180 #define PREFIX_DS 0x20
181 #define PREFIX_ES 0x40
182 #define PREFIX_FS 0x80
183 #define PREFIX_GS 0x100
184 #define PREFIX_DATA 0x200
185 #define PREFIX_ADDR 0x400
186 #define PREFIX_FWAIT 0x800
188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
189 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
191 #define FETCH_DATA(info, addr) \
192 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
193 ? 1 : fetch_data ((info), (addr)))
196 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
199 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
200 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
202 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
203 status
= (*info
->read_memory_func
) (start
,
205 addr
- priv
->max_fetched
,
211 /* If we did manage to read at least one byte, then
212 print_insn_i386 will do something sensible. Otherwise, print
213 an error. We do that here because this is where we know
215 if (priv
->max_fetched
== priv
->the_buffer
)
216 (*info
->memory_error_func
) (status
, start
, info
);
217 longjmp (priv
->bailout
, 1);
220 priv
->max_fetched
= addr
;
224 #define XX { NULL, 0 }
225 #define Bad_Opcode NULL, { { NULL, 0 } }
227 #define Eb { OP_E, b_mode }
228 #define Ebnd { OP_E, bnd_mode }
229 #define EbS { OP_E, b_swap_mode }
230 #define Ev { OP_E, v_mode }
231 #define Ev_bnd { OP_E, v_bnd_mode }
232 #define EvS { OP_E, v_swap_mode }
233 #define Ed { OP_E, d_mode }
234 #define Edq { OP_E, dq_mode }
235 #define Edqw { OP_E, dqw_mode }
236 #define Edqb { OP_E, dqb_mode }
237 #define Edqd { OP_E, dqd_mode }
238 #define Eq { OP_E, q_mode }
239 #define indirEv { OP_indirE, stack_v_mode }
240 #define indirEp { OP_indirE, f_mode }
241 #define stackEv { OP_E, stack_v_mode }
242 #define Em { OP_E, m_mode }
243 #define Ew { OP_E, w_mode }
244 #define M { OP_M, 0 } /* lea, lgdt, etc. */
245 #define Ma { OP_M, a_mode }
246 #define Mb { OP_M, b_mode }
247 #define Md { OP_M, d_mode }
248 #define Mo { OP_M, o_mode }
249 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
250 #define Mq { OP_M, q_mode }
251 #define Mx { OP_M, x_mode }
252 #define Mxmm { OP_M, xmm_mode }
253 #define Gb { OP_G, b_mode }
254 #define Gbnd { OP_G, bnd_mode }
255 #define Gv { OP_G, v_mode }
256 #define Gd { OP_G, d_mode }
257 #define Gdq { OP_G, dq_mode }
258 #define Gm { OP_G, m_mode }
259 #define Gw { OP_G, w_mode }
260 #define Rd { OP_R, d_mode }
261 #define Rdq { OP_R, dq_mode }
262 #define Rm { OP_R, m_mode }
263 #define Ib { OP_I, b_mode }
264 #define sIb { OP_sI, b_mode } /* sign extened byte */
265 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
266 #define Iv { OP_I, v_mode }
267 #define sIv { OP_sI, v_mode }
268 #define Iq { OP_I, q_mode }
269 #define Iv64 { OP_I64, v_mode }
270 #define Iw { OP_I, w_mode }
271 #define I1 { OP_I, const_1_mode }
272 #define Jb { OP_J, b_mode }
273 #define Jv { OP_J, v_mode }
274 #define Cm { OP_C, m_mode }
275 #define Dm { OP_D, m_mode }
276 #define Td { OP_T, d_mode }
277 #define Skip_MODRM { OP_Skip_MODRM, 0 }
279 #define RMeAX { OP_REG, eAX_reg }
280 #define RMeBX { OP_REG, eBX_reg }
281 #define RMeCX { OP_REG, eCX_reg }
282 #define RMeDX { OP_REG, eDX_reg }
283 #define RMeSP { OP_REG, eSP_reg }
284 #define RMeBP { OP_REG, eBP_reg }
285 #define RMeSI { OP_REG, eSI_reg }
286 #define RMeDI { OP_REG, eDI_reg }
287 #define RMrAX { OP_REG, rAX_reg }
288 #define RMrBX { OP_REG, rBX_reg }
289 #define RMrCX { OP_REG, rCX_reg }
290 #define RMrDX { OP_REG, rDX_reg }
291 #define RMrSP { OP_REG, rSP_reg }
292 #define RMrBP { OP_REG, rBP_reg }
293 #define RMrSI { OP_REG, rSI_reg }
294 #define RMrDI { OP_REG, rDI_reg }
295 #define RMAL { OP_REG, al_reg }
296 #define RMCL { OP_REG, cl_reg }
297 #define RMDL { OP_REG, dl_reg }
298 #define RMBL { OP_REG, bl_reg }
299 #define RMAH { OP_REG, ah_reg }
300 #define RMCH { OP_REG, ch_reg }
301 #define RMDH { OP_REG, dh_reg }
302 #define RMBH { OP_REG, bh_reg }
303 #define RMAX { OP_REG, ax_reg }
304 #define RMDX { OP_REG, dx_reg }
306 #define eAX { OP_IMREG, eAX_reg }
307 #define eBX { OP_IMREG, eBX_reg }
308 #define eCX { OP_IMREG, eCX_reg }
309 #define eDX { OP_IMREG, eDX_reg }
310 #define eSP { OP_IMREG, eSP_reg }
311 #define eBP { OP_IMREG, eBP_reg }
312 #define eSI { OP_IMREG, eSI_reg }
313 #define eDI { OP_IMREG, eDI_reg }
314 #define AL { OP_IMREG, al_reg }
315 #define CL { OP_IMREG, cl_reg }
316 #define DL { OP_IMREG, dl_reg }
317 #define BL { OP_IMREG, bl_reg }
318 #define AH { OP_IMREG, ah_reg }
319 #define CH { OP_IMREG, ch_reg }
320 #define DH { OP_IMREG, dh_reg }
321 #define BH { OP_IMREG, bh_reg }
322 #define AX { OP_IMREG, ax_reg }
323 #define DX { OP_IMREG, dx_reg }
324 #define zAX { OP_IMREG, z_mode_ax_reg }
325 #define indirDX { OP_IMREG, indir_dx_reg }
327 #define Sw { OP_SEG, w_mode }
328 #define Sv { OP_SEG, v_mode }
329 #define Ap { OP_DIR, 0 }
330 #define Ob { OP_OFF64, b_mode }
331 #define Ov { OP_OFF64, v_mode }
332 #define Xb { OP_DSreg, eSI_reg }
333 #define Xv { OP_DSreg, eSI_reg }
334 #define Xz { OP_DSreg, eSI_reg }
335 #define Yb { OP_ESreg, eDI_reg }
336 #define Yv { OP_ESreg, eDI_reg }
337 #define DSBX { OP_DSreg, eBX_reg }
339 #define es { OP_REG, es_reg }
340 #define ss { OP_REG, ss_reg }
341 #define cs { OP_REG, cs_reg }
342 #define ds { OP_REG, ds_reg }
343 #define fs { OP_REG, fs_reg }
344 #define gs { OP_REG, gs_reg }
346 #define MX { OP_MMX, 0 }
347 #define XM { OP_XMM, 0 }
348 #define XMScalar { OP_XMM, scalar_mode }
349 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
350 #define XMM { OP_XMM, xmm_mode }
351 #define XMxmmq { OP_XMM, xmmq_mode }
352 #define EM { OP_EM, v_mode }
353 #define EMS { OP_EM, v_swap_mode }
354 #define EMd { OP_EM, d_mode }
355 #define EMx { OP_EM, x_mode }
356 #define EXw { OP_EX, w_mode }
357 #define EXd { OP_EX, d_mode }
358 #define EXdScalar { OP_EX, d_scalar_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
361 #define EXq { OP_EX, q_mode }
362 #define EXqScalar { OP_EX, q_scalar_mode }
363 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
364 #define EXqS { OP_EX, q_swap_mode }
365 #define EXx { OP_EX, x_mode }
366 #define EXxS { OP_EX, x_swap_mode }
367 #define EXxmm { OP_EX, xmm_mode }
368 #define EXymm { OP_EX, ymm_mode }
369 #define EXxmmq { OP_EX, xmmq_mode }
370 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
371 #define EXxmm_mb { OP_EX, xmm_mb_mode }
372 #define EXxmm_mw { OP_EX, xmm_mw_mode }
373 #define EXxmm_md { OP_EX, xmm_md_mode }
374 #define EXxmm_mq { OP_EX, xmm_mq_mode }
375 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
376 #define EXxmmdw { OP_EX, xmmdw_mode }
377 #define EXxmmqd { OP_EX, xmmqd_mode }
378 #define EXymmq { OP_EX, ymmq_mode }
379 #define EXVexWdq { OP_EX, vex_w_dq_mode }
380 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
381 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
382 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
383 #define MS { OP_MS, v_mode }
384 #define XS { OP_XS, v_mode }
385 #define EMCq { OP_EMC, q_mode }
386 #define MXC { OP_MXC, 0 }
387 #define OPSUF { OP_3DNowSuffix, 0 }
388 #define CMP { CMP_Fixup, 0 }
389 #define XMM0 { XMM_Fixup, 0 }
390 #define FXSAVE { FXSAVE_Fixup, 0 }
391 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
392 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
394 #define Vex { OP_VEX, vex_mode }
395 #define VexScalar { OP_VEX, vex_scalar_mode }
396 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
397 #define Vex128 { OP_VEX, vex128_mode }
398 #define Vex256 { OP_VEX, vex256_mode }
399 #define VexGdq { OP_VEX, dq_mode }
400 #define VexI4 { VEXI4_Fixup, 0}
401 #define EXdVex { OP_EX_Vex, d_mode }
402 #define EXdVexS { OP_EX_Vex, d_swap_mode }
403 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
404 #define EXqVex { OP_EX_Vex, q_mode }
405 #define EXqVexS { OP_EX_Vex, q_swap_mode }
406 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
407 #define EXVexW { OP_EX_VexW, x_mode }
408 #define EXdVexW { OP_EX_VexW, d_mode }
409 #define EXqVexW { OP_EX_VexW, q_mode }
410 #define EXVexImmW { OP_EX_VexImmW, x_mode }
411 #define XMVex { OP_XMM_Vex, 0 }
412 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
413 #define XMVexW { OP_XMM_VexW, 0 }
414 #define XMVexI4 { OP_REG_VexI4, x_mode }
415 #define PCLMUL { PCLMUL_Fixup, 0 }
416 #define VZERO { VZERO_Fixup, 0 }
417 #define VCMP { VCMP_Fixup, 0 }
418 #define VPCMP { VPCMP_Fixup, 0 }
420 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
421 #define EXxEVexS { OP_Rounding, evex_sae_mode }
423 #define XMask { OP_Mask, mask_mode }
424 #define MaskG { OP_G, mask_mode }
425 #define MaskE { OP_E, mask_mode }
426 #define MaskR { OP_R, mask_mode }
427 #define MaskVex { OP_VEX, mask_mode }
429 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
430 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
431 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
432 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
434 /* Used handle "rep" prefix for string instructions. */
435 #define Xbr { REP_Fixup, eSI_reg }
436 #define Xvr { REP_Fixup, eSI_reg }
437 #define Ybr { REP_Fixup, eDI_reg }
438 #define Yvr { REP_Fixup, eDI_reg }
439 #define Yzr { REP_Fixup, eDI_reg }
440 #define indirDXr { REP_Fixup, indir_dx_reg }
441 #define ALr { REP_Fixup, al_reg }
442 #define eAXr { REP_Fixup, eAX_reg }
444 /* Used handle HLE prefix for lockable instructions. */
445 #define Ebh1 { HLE_Fixup1, b_mode }
446 #define Evh1 { HLE_Fixup1, v_mode }
447 #define Ebh2 { HLE_Fixup2, b_mode }
448 #define Evh2 { HLE_Fixup2, v_mode }
449 #define Ebh3 { HLE_Fixup3, b_mode }
450 #define Evh3 { HLE_Fixup3, v_mode }
452 #define BND { BND_Fixup, 0 }
454 #define cond_jump_flag { NULL, cond_jump_mode }
455 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
457 /* bits in sizeflag */
458 #define SUFFIX_ALWAYS 4
466 /* byte operand with operand swapped */
468 /* byte operand, sign extend like 'T' suffix */
470 /* operand size depends on prefixes */
472 /* operand size depends on prefixes with operand swapped */
476 /* double word operand */
478 /* double word operand with operand swapped */
480 /* quad word operand */
482 /* quad word operand with operand swapped */
484 /* ten-byte operand */
486 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
487 broadcast enabled. */
489 /* Similar to x_mode, but with different EVEX mem shifts. */
491 /* Similar to x_mode, but with disabled broadcast. */
493 /* Similar to x_mode, but with operands swapped and disabled broadcast
496 /* 16-byte XMM operand */
498 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
499 memory operand (depending on vector length). Broadcast isn't
502 /* Same as xmmq_mode, but broadcast is allowed. */
503 evex_half_bcst_xmmq_mode
,
504 /* XMM register or byte memory operand */
506 /* XMM register or word memory operand */
508 /* XMM register or double word memory operand */
510 /* XMM register or quad word memory operand */
512 /* XMM register or double/quad word memory operand, depending on
515 /* 16-byte XMM, word, double word or quad word operand. */
517 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
519 /* 32-byte YMM operand */
521 /* quad word, ymmword or zmmword memory operand. */
523 /* 32-byte YMM or 16-byte word operand */
525 /* d_mode in 32bit, q_mode in 64bit mode. */
527 /* pair of v_mode operands */
532 /* operand size depends on REX prefixes. */
534 /* registers like dq_mode, memory like w_mode. */
537 /* 4- or 6-byte pointer operand */
540 /* v_mode for stack-related opcodes. */
542 /* non-quad operand size depends on prefixes */
544 /* 16-byte operand */
546 /* registers like dq_mode, memory like b_mode. */
548 /* registers like dq_mode, memory like d_mode. */
550 /* normal vex mode */
552 /* 128bit vex mode */
554 /* 256bit vex mode */
556 /* operand size depends on the VEX.W bit. */
559 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
560 vex_vsib_d_w_dq_mode
,
561 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
563 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
564 vex_vsib_q_w_dq_mode
,
565 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
568 /* scalar, ignore vector length. */
570 /* like d_mode, ignore vector length. */
572 /* like d_swap_mode, ignore vector length. */
574 /* like q_mode, ignore vector length. */
576 /* like q_swap_mode, ignore vector length. */
578 /* like vex_mode, ignore vector length. */
580 /* like vex_w_dq_mode, ignore vector length. */
581 vex_scalar_w_dq_mode
,
583 /* Static rounding. */
585 /* Supress all exceptions. */
588 /* Mask register operand. */
655 #define FLOAT NULL, { { NULL, FLOATCODE } }
657 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
658 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
659 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
660 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
661 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
662 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
663 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
664 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
665 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
666 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
667 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
668 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
669 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
788 MOD_VEX_0F12_PREFIX_0
,
790 MOD_VEX_0F16_PREFIX_0
,
806 MOD_VEX_0FD7_PREFIX_2
,
807 MOD_VEX_0FE7_PREFIX_2
,
808 MOD_VEX_0FF0_PREFIX_3
,
809 MOD_VEX_0F381A_PREFIX_2
,
810 MOD_VEX_0F382A_PREFIX_2
,
811 MOD_VEX_0F382C_PREFIX_2
,
812 MOD_VEX_0F382D_PREFIX_2
,
813 MOD_VEX_0F382E_PREFIX_2
,
814 MOD_VEX_0F382F_PREFIX_2
,
815 MOD_VEX_0F385A_PREFIX_2
,
816 MOD_VEX_0F388C_PREFIX_2
,
817 MOD_VEX_0F388E_PREFIX_2
,
819 MOD_EVEX_0F10_PREFIX_1
,
820 MOD_EVEX_0F10_PREFIX_3
,
821 MOD_EVEX_0F11_PREFIX_1
,
822 MOD_EVEX_0F11_PREFIX_3
,
823 MOD_EVEX_0F12_PREFIX_0
,
824 MOD_EVEX_0F16_PREFIX_0
,
825 MOD_EVEX_0F38C6_REG_1
,
826 MOD_EVEX_0F38C6_REG_2
,
827 MOD_EVEX_0F38C6_REG_5
,
828 MOD_EVEX_0F38C6_REG_6
,
829 MOD_EVEX_0F38C7_REG_1
,
830 MOD_EVEX_0F38C7_REG_2
,
831 MOD_EVEX_0F38C7_REG_5
,
832 MOD_EVEX_0F38C7_REG_6
1023 PREFIX_VEX_0F71_REG_2
,
1024 PREFIX_VEX_0F71_REG_4
,
1025 PREFIX_VEX_0F71_REG_6
,
1026 PREFIX_VEX_0F72_REG_2
,
1027 PREFIX_VEX_0F72_REG_4
,
1028 PREFIX_VEX_0F72_REG_6
,
1029 PREFIX_VEX_0F73_REG_2
,
1030 PREFIX_VEX_0F73_REG_3
,
1031 PREFIX_VEX_0F73_REG_6
,
1032 PREFIX_VEX_0F73_REG_7
,
1203 PREFIX_VEX_0F38F3_REG_1
,
1204 PREFIX_VEX_0F38F3_REG_2
,
1205 PREFIX_VEX_0F38F3_REG_3
,
1307 PREFIX_EVEX_0F72_REG_0
,
1308 PREFIX_EVEX_0F72_REG_1
,
1309 PREFIX_EVEX_0F72_REG_2
,
1310 PREFIX_EVEX_0F72_REG_4
,
1311 PREFIX_EVEX_0F72_REG_6
,
1312 PREFIX_EVEX_0F73_REG_2
,
1313 PREFIX_EVEX_0F73_REG_6
,
1442 PREFIX_EVEX_0F38C6_REG_1
,
1443 PREFIX_EVEX_0F38C6_REG_2
,
1444 PREFIX_EVEX_0F38C6_REG_5
,
1445 PREFIX_EVEX_0F38C6_REG_6
,
1446 PREFIX_EVEX_0F38C7_REG_1
,
1447 PREFIX_EVEX_0F38C7_REG_2
,
1448 PREFIX_EVEX_0F38C7_REG_5
,
1449 PREFIX_EVEX_0F38C7_REG_6
,
1521 THREE_BYTE_0F38
= 0,
1549 VEX_LEN_0F10_P_1
= 0,
1553 VEX_LEN_0F12_P_0_M_0
,
1554 VEX_LEN_0F12_P_0_M_1
,
1557 VEX_LEN_0F16_P_0_M_0
,
1558 VEX_LEN_0F16_P_0_M_1
,
1604 VEX_LEN_0FAE_R_2_M_0
,
1605 VEX_LEN_0FAE_R_3_M_0
,
1614 VEX_LEN_0F381A_P_2_M_0
,
1617 VEX_LEN_0F385A_P_2_M_0
,
1624 VEX_LEN_0F38F3_R_1_P_0
,
1625 VEX_LEN_0F38F3_R_2_P_0
,
1626 VEX_LEN_0F38F3_R_3_P_0
,
1670 VEX_LEN_0FXOP_08_CC
,
1671 VEX_LEN_0FXOP_08_CD
,
1672 VEX_LEN_0FXOP_08_CE
,
1673 VEX_LEN_0FXOP_08_CF
,
1674 VEX_LEN_0FXOP_08_EC
,
1675 VEX_LEN_0FXOP_08_ED
,
1676 VEX_LEN_0FXOP_08_EE
,
1677 VEX_LEN_0FXOP_08_EF
,
1678 VEX_LEN_0FXOP_09_80
,
1712 VEX_W_0F41_P_0_LEN_1
,
1713 VEX_W_0F42_P_0_LEN_1
,
1714 VEX_W_0F44_P_0_LEN_0
,
1715 VEX_W_0F45_P_0_LEN_1
,
1716 VEX_W_0F46_P_0_LEN_1
,
1717 VEX_W_0F47_P_0_LEN_1
,
1718 VEX_W_0F4B_P_2_LEN_1
,
1798 VEX_W_0F90_P_0_LEN_0
,
1799 VEX_W_0F91_P_0_LEN_0
,
1800 VEX_W_0F92_P_0_LEN_0
,
1801 VEX_W_0F93_P_0_LEN_0
,
1802 VEX_W_0F98_P_0_LEN_0
,
1881 VEX_W_0F381A_P_2_M_0
,
1893 VEX_W_0F382A_P_2_M_0
,
1895 VEX_W_0F382C_P_2_M_0
,
1896 VEX_W_0F382D_P_2_M_0
,
1897 VEX_W_0F382E_P_2_M_0
,
1898 VEX_W_0F382F_P_2_M_0
,
1920 VEX_W_0F385A_P_2_M_0
,
1948 VEX_W_0F3A30_P_2_LEN_0
,
1949 VEX_W_0F3A32_P_2_LEN_0
,
1969 EVEX_W_0F10_P_1_M_0
,
1970 EVEX_W_0F10_P_1_M_1
,
1972 EVEX_W_0F10_P_3_M_0
,
1973 EVEX_W_0F10_P_3_M_1
,
1975 EVEX_W_0F11_P_1_M_0
,
1976 EVEX_W_0F11_P_1_M_1
,
1978 EVEX_W_0F11_P_3_M_0
,
1979 EVEX_W_0F11_P_3_M_1
,
1980 EVEX_W_0F12_P_0_M_0
,
1981 EVEX_W_0F12_P_0_M_1
,
1991 EVEX_W_0F16_P_0_M_0
,
1992 EVEX_W_0F16_P_0_M_1
,
2053 EVEX_W_0F72_R_2_P_2
,
2054 EVEX_W_0F72_R_6_P_2
,
2055 EVEX_W_0F73_R_2_P_2
,
2056 EVEX_W_0F73_R_6_P_2
,
2129 EVEX_W_0F38C7_R_1_P_2
,
2130 EVEX_W_0F38C7_R_2_P_2
,
2131 EVEX_W_0F38C7_R_5_P_2
,
2132 EVEX_W_0F38C7_R_6_P_2
,
2156 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2167 /* Upper case letters in the instruction names here are macros.
2168 'A' => print 'b' if no register operands or suffix_always is true
2169 'B' => print 'b' if suffix_always is true
2170 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2172 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2173 suffix_always is true
2174 'E' => print 'e' if 32-bit form of jcxz
2175 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2176 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2177 'H' => print ",pt" or ",pn" branch hint
2178 'I' => honor following macro letter even in Intel mode (implemented only
2179 for some of the macro letters)
2181 'K' => print 'd' or 'q' if rex prefix is present.
2182 'L' => print 'l' if suffix_always is true
2183 'M' => print 'r' if intel_mnemonic is false.
2184 'N' => print 'n' if instruction has no wait "prefix"
2185 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2186 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2187 or suffix_always is true. print 'q' if rex prefix is present.
2188 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2190 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2191 'S' => print 'w', 'l' or 'q' if suffix_always is true
2192 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2193 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2194 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2195 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2196 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2197 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2198 suffix_always is true.
2199 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2200 '!' => change condition from true to false or from false to true.
2201 '%' => add 1 upper case letter to the macro.
2203 2 upper case letter macros:
2204 "XY" => print 'x' or 'y' if no register operands or suffix_always
2206 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2207 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2208 or suffix_always is true
2209 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2210 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2211 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2212 "LW" => print 'd', 'q' depending on the VEX.W bit
2214 Many of the above letters print nothing in Intel mode. See "putop"
2217 Braces '{' and '}', and vertical bars '|', indicate alternative
2218 mnemonic strings for AT&T and Intel. */
2220 static const struct dis386 dis386
[] = {
2222 { "addB", { Ebh1
, Gb
} },
2223 { "addS", { Evh1
, Gv
} },
2224 { "addB", { Gb
, EbS
} },
2225 { "addS", { Gv
, EvS
} },
2226 { "addB", { AL
, Ib
} },
2227 { "addS", { eAX
, Iv
} },
2228 { X86_64_TABLE (X86_64_06
) },
2229 { X86_64_TABLE (X86_64_07
) },
2231 { "orB", { Ebh1
, Gb
} },
2232 { "orS", { Evh1
, Gv
} },
2233 { "orB", { Gb
, EbS
} },
2234 { "orS", { Gv
, EvS
} },
2235 { "orB", { AL
, Ib
} },
2236 { "orS", { eAX
, Iv
} },
2237 { X86_64_TABLE (X86_64_0D
) },
2238 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2240 { "adcB", { Ebh1
, Gb
} },
2241 { "adcS", { Evh1
, Gv
} },
2242 { "adcB", { Gb
, EbS
} },
2243 { "adcS", { Gv
, EvS
} },
2244 { "adcB", { AL
, Ib
} },
2245 { "adcS", { eAX
, Iv
} },
2246 { X86_64_TABLE (X86_64_16
) },
2247 { X86_64_TABLE (X86_64_17
) },
2249 { "sbbB", { Ebh1
, Gb
} },
2250 { "sbbS", { Evh1
, Gv
} },
2251 { "sbbB", { Gb
, EbS
} },
2252 { "sbbS", { Gv
, EvS
} },
2253 { "sbbB", { AL
, Ib
} },
2254 { "sbbS", { eAX
, Iv
} },
2255 { X86_64_TABLE (X86_64_1E
) },
2256 { X86_64_TABLE (X86_64_1F
) },
2258 { "andB", { Ebh1
, Gb
} },
2259 { "andS", { Evh1
, Gv
} },
2260 { "andB", { Gb
, EbS
} },
2261 { "andS", { Gv
, EvS
} },
2262 { "andB", { AL
, Ib
} },
2263 { "andS", { eAX
, Iv
} },
2264 { Bad_Opcode
}, /* SEG ES prefix */
2265 { X86_64_TABLE (X86_64_27
) },
2267 { "subB", { Ebh1
, Gb
} },
2268 { "subS", { Evh1
, Gv
} },
2269 { "subB", { Gb
, EbS
} },
2270 { "subS", { Gv
, EvS
} },
2271 { "subB", { AL
, Ib
} },
2272 { "subS", { eAX
, Iv
} },
2273 { Bad_Opcode
}, /* SEG CS prefix */
2274 { X86_64_TABLE (X86_64_2F
) },
2276 { "xorB", { Ebh1
, Gb
} },
2277 { "xorS", { Evh1
, Gv
} },
2278 { "xorB", { Gb
, EbS
} },
2279 { "xorS", { Gv
, EvS
} },
2280 { "xorB", { AL
, Ib
} },
2281 { "xorS", { eAX
, Iv
} },
2282 { Bad_Opcode
}, /* SEG SS prefix */
2283 { X86_64_TABLE (X86_64_37
) },
2285 { "cmpB", { Eb
, Gb
} },
2286 { "cmpS", { Ev
, Gv
} },
2287 { "cmpB", { Gb
, EbS
} },
2288 { "cmpS", { Gv
, EvS
} },
2289 { "cmpB", { AL
, Ib
} },
2290 { "cmpS", { eAX
, Iv
} },
2291 { Bad_Opcode
}, /* SEG DS prefix */
2292 { X86_64_TABLE (X86_64_3F
) },
2294 { "inc{S|}", { RMeAX
} },
2295 { "inc{S|}", { RMeCX
} },
2296 { "inc{S|}", { RMeDX
} },
2297 { "inc{S|}", { RMeBX
} },
2298 { "inc{S|}", { RMeSP
} },
2299 { "inc{S|}", { RMeBP
} },
2300 { "inc{S|}", { RMeSI
} },
2301 { "inc{S|}", { RMeDI
} },
2303 { "dec{S|}", { RMeAX
} },
2304 { "dec{S|}", { RMeCX
} },
2305 { "dec{S|}", { RMeDX
} },
2306 { "dec{S|}", { RMeBX
} },
2307 { "dec{S|}", { RMeSP
} },
2308 { "dec{S|}", { RMeBP
} },
2309 { "dec{S|}", { RMeSI
} },
2310 { "dec{S|}", { RMeDI
} },
2312 { "pushV", { RMrAX
} },
2313 { "pushV", { RMrCX
} },
2314 { "pushV", { RMrDX
} },
2315 { "pushV", { RMrBX
} },
2316 { "pushV", { RMrSP
} },
2317 { "pushV", { RMrBP
} },
2318 { "pushV", { RMrSI
} },
2319 { "pushV", { RMrDI
} },
2321 { "popV", { RMrAX
} },
2322 { "popV", { RMrCX
} },
2323 { "popV", { RMrDX
} },
2324 { "popV", { RMrBX
} },
2325 { "popV", { RMrSP
} },
2326 { "popV", { RMrBP
} },
2327 { "popV", { RMrSI
} },
2328 { "popV", { RMrDI
} },
2330 { X86_64_TABLE (X86_64_60
) },
2331 { X86_64_TABLE (X86_64_61
) },
2332 { X86_64_TABLE (X86_64_62
) },
2333 { X86_64_TABLE (X86_64_63
) },
2334 { Bad_Opcode
}, /* seg fs */
2335 { Bad_Opcode
}, /* seg gs */
2336 { Bad_Opcode
}, /* op size prefix */
2337 { Bad_Opcode
}, /* adr size prefix */
2339 { "pushT", { sIv
} },
2340 { "imulS", { Gv
, Ev
, Iv
} },
2341 { "pushT", { sIbT
} },
2342 { "imulS", { Gv
, Ev
, sIb
} },
2343 { "ins{b|}", { Ybr
, indirDX
} },
2344 { X86_64_TABLE (X86_64_6D
) },
2345 { "outs{b|}", { indirDXr
, Xb
} },
2346 { X86_64_TABLE (X86_64_6F
) },
2348 { "joH", { Jb
, BND
, cond_jump_flag
} },
2349 { "jnoH", { Jb
, BND
, cond_jump_flag
} },
2350 { "jbH", { Jb
, BND
, cond_jump_flag
} },
2351 { "jaeH", { Jb
, BND
, cond_jump_flag
} },
2352 { "jeH", { Jb
, BND
, cond_jump_flag
} },
2353 { "jneH", { Jb
, BND
, cond_jump_flag
} },
2354 { "jbeH", { Jb
, BND
, cond_jump_flag
} },
2355 { "jaH", { Jb
, BND
, cond_jump_flag
} },
2357 { "jsH", { Jb
, BND
, cond_jump_flag
} },
2358 { "jnsH", { Jb
, BND
, cond_jump_flag
} },
2359 { "jpH", { Jb
, BND
, cond_jump_flag
} },
2360 { "jnpH", { Jb
, BND
, cond_jump_flag
} },
2361 { "jlH", { Jb
, BND
, cond_jump_flag
} },
2362 { "jgeH", { Jb
, BND
, cond_jump_flag
} },
2363 { "jleH", { Jb
, BND
, cond_jump_flag
} },
2364 { "jgH", { Jb
, BND
, cond_jump_flag
} },
2366 { REG_TABLE (REG_80
) },
2367 { REG_TABLE (REG_81
) },
2369 { REG_TABLE (REG_82
) },
2370 { "testB", { Eb
, Gb
} },
2371 { "testS", { Ev
, Gv
} },
2372 { "xchgB", { Ebh2
, Gb
} },
2373 { "xchgS", { Evh2
, Gv
} },
2375 { "movB", { Ebh3
, Gb
} },
2376 { "movS", { Evh3
, Gv
} },
2377 { "movB", { Gb
, EbS
} },
2378 { "movS", { Gv
, EvS
} },
2379 { "movD", { Sv
, Sw
} },
2380 { MOD_TABLE (MOD_8D
) },
2381 { "movD", { Sw
, Sv
} },
2382 { REG_TABLE (REG_8F
) },
2384 { PREFIX_TABLE (PREFIX_90
) },
2385 { "xchgS", { RMeCX
, eAX
} },
2386 { "xchgS", { RMeDX
, eAX
} },
2387 { "xchgS", { RMeBX
, eAX
} },
2388 { "xchgS", { RMeSP
, eAX
} },
2389 { "xchgS", { RMeBP
, eAX
} },
2390 { "xchgS", { RMeSI
, eAX
} },
2391 { "xchgS", { RMeDI
, eAX
} },
2393 { "cW{t|}R", { XX
} },
2394 { "cR{t|}O", { XX
} },
2395 { X86_64_TABLE (X86_64_9A
) },
2396 { Bad_Opcode
}, /* fwait */
2397 { "pushfT", { XX
} },
2398 { "popfT", { XX
} },
2402 { "mov%LB", { AL
, Ob
} },
2403 { "mov%LS", { eAX
, Ov
} },
2404 { "mov%LB", { Ob
, AL
} },
2405 { "mov%LS", { Ov
, eAX
} },
2406 { "movs{b|}", { Ybr
, Xb
} },
2407 { "movs{R|}", { Yvr
, Xv
} },
2408 { "cmps{b|}", { Xb
, Yb
} },
2409 { "cmps{R|}", { Xv
, Yv
} },
2411 { "testB", { AL
, Ib
} },
2412 { "testS", { eAX
, Iv
} },
2413 { "stosB", { Ybr
, AL
} },
2414 { "stosS", { Yvr
, eAX
} },
2415 { "lodsB", { ALr
, Xb
} },
2416 { "lodsS", { eAXr
, Xv
} },
2417 { "scasB", { AL
, Yb
} },
2418 { "scasS", { eAX
, Yv
} },
2420 { "movB", { RMAL
, Ib
} },
2421 { "movB", { RMCL
, Ib
} },
2422 { "movB", { RMDL
, Ib
} },
2423 { "movB", { RMBL
, Ib
} },
2424 { "movB", { RMAH
, Ib
} },
2425 { "movB", { RMCH
, Ib
} },
2426 { "movB", { RMDH
, Ib
} },
2427 { "movB", { RMBH
, Ib
} },
2429 { "mov%LV", { RMeAX
, Iv64
} },
2430 { "mov%LV", { RMeCX
, Iv64
} },
2431 { "mov%LV", { RMeDX
, Iv64
} },
2432 { "mov%LV", { RMeBX
, Iv64
} },
2433 { "mov%LV", { RMeSP
, Iv64
} },
2434 { "mov%LV", { RMeBP
, Iv64
} },
2435 { "mov%LV", { RMeSI
, Iv64
} },
2436 { "mov%LV", { RMeDI
, Iv64
} },
2438 { REG_TABLE (REG_C0
) },
2439 { REG_TABLE (REG_C1
) },
2440 { "retT", { Iw
, BND
} },
2441 { "retT", { BND
} },
2442 { X86_64_TABLE (X86_64_C4
) },
2443 { X86_64_TABLE (X86_64_C5
) },
2444 { REG_TABLE (REG_C6
) },
2445 { REG_TABLE (REG_C7
) },
2447 { "enterT", { Iw
, Ib
} },
2448 { "leaveT", { XX
} },
2449 { "Jret{|f}P", { Iw
} },
2450 { "Jret{|f}P", { XX
} },
2453 { X86_64_TABLE (X86_64_CE
) },
2454 { "iretP", { XX
} },
2456 { REG_TABLE (REG_D0
) },
2457 { REG_TABLE (REG_D1
) },
2458 { REG_TABLE (REG_D2
) },
2459 { REG_TABLE (REG_D3
) },
2460 { X86_64_TABLE (X86_64_D4
) },
2461 { X86_64_TABLE (X86_64_D5
) },
2463 { "xlat", { DSBX
} },
2474 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
} },
2475 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
} },
2476 { "loopFH", { Jb
, XX
, loop_jcxz_flag
} },
2477 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
} },
2478 { "inB", { AL
, Ib
} },
2479 { "inG", { zAX
, Ib
} },
2480 { "outB", { Ib
, AL
} },
2481 { "outG", { Ib
, zAX
} },
2483 { "callT", { Jv
, BND
} },
2484 { "jmpT", { Jv
, BND
} },
2485 { X86_64_TABLE (X86_64_EA
) },
2486 { "jmp", { Jb
, BND
} },
2487 { "inB", { AL
, indirDX
} },
2488 { "inG", { zAX
, indirDX
} },
2489 { "outB", { indirDX
, AL
} },
2490 { "outG", { indirDX
, zAX
} },
2492 { Bad_Opcode
}, /* lock prefix */
2493 { "icebp", { XX
} },
2494 { Bad_Opcode
}, /* repne */
2495 { Bad_Opcode
}, /* repz */
2498 { REG_TABLE (REG_F6
) },
2499 { REG_TABLE (REG_F7
) },
2507 { REG_TABLE (REG_FE
) },
2508 { REG_TABLE (REG_FF
) },
2511 static const struct dis386 dis386_twobyte
[] = {
2513 { REG_TABLE (REG_0F00
) },
2514 { REG_TABLE (REG_0F01
) },
2515 { "larS", { Gv
, Ew
} },
2516 { "lslS", { Gv
, Ew
} },
2518 { "syscall", { XX
} },
2520 { "sysretP", { XX
} },
2523 { "wbinvd", { XX
} },
2527 { REG_TABLE (REG_0F0D
) },
2528 { "femms", { XX
} },
2529 { "", { MX
, EM
, OPSUF
} }, /* See OP_3DNowSuffix. */
2531 { PREFIX_TABLE (PREFIX_0F10
) },
2532 { PREFIX_TABLE (PREFIX_0F11
) },
2533 { PREFIX_TABLE (PREFIX_0F12
) },
2534 { MOD_TABLE (MOD_0F13
) },
2535 { "unpcklpX", { XM
, EXx
} },
2536 { "unpckhpX", { XM
, EXx
} },
2537 { PREFIX_TABLE (PREFIX_0F16
) },
2538 { MOD_TABLE (MOD_0F17
) },
2540 { REG_TABLE (REG_0F18
) },
2542 { PREFIX_TABLE (PREFIX_0F1A
) },
2543 { PREFIX_TABLE (PREFIX_0F1B
) },
2549 { MOD_TABLE (MOD_0F20
) },
2550 { MOD_TABLE (MOD_0F21
) },
2551 { MOD_TABLE (MOD_0F22
) },
2552 { MOD_TABLE (MOD_0F23
) },
2553 { MOD_TABLE (MOD_0F24
) },
2555 { MOD_TABLE (MOD_0F26
) },
2558 { "movapX", { XM
, EXx
} },
2559 { "movapX", { EXxS
, XM
} },
2560 { PREFIX_TABLE (PREFIX_0F2A
) },
2561 { PREFIX_TABLE (PREFIX_0F2B
) },
2562 { PREFIX_TABLE (PREFIX_0F2C
) },
2563 { PREFIX_TABLE (PREFIX_0F2D
) },
2564 { PREFIX_TABLE (PREFIX_0F2E
) },
2565 { PREFIX_TABLE (PREFIX_0F2F
) },
2567 { "wrmsr", { XX
} },
2568 { "rdtsc", { XX
} },
2569 { "rdmsr", { XX
} },
2570 { "rdpmc", { XX
} },
2571 { "sysenter", { XX
} },
2572 { "sysexit", { XX
} },
2574 { "getsec", { XX
} },
2576 { THREE_BYTE_TABLE (THREE_BYTE_0F38
) },
2578 { THREE_BYTE_TABLE (THREE_BYTE_0F3A
) },
2585 { "cmovoS", { Gv
, Ev
} },
2586 { "cmovnoS", { Gv
, Ev
} },
2587 { "cmovbS", { Gv
, Ev
} },
2588 { "cmovaeS", { Gv
, Ev
} },
2589 { "cmoveS", { Gv
, Ev
} },
2590 { "cmovneS", { Gv
, Ev
} },
2591 { "cmovbeS", { Gv
, Ev
} },
2592 { "cmovaS", { Gv
, Ev
} },
2594 { "cmovsS", { Gv
, Ev
} },
2595 { "cmovnsS", { Gv
, Ev
} },
2596 { "cmovpS", { Gv
, Ev
} },
2597 { "cmovnpS", { Gv
, Ev
} },
2598 { "cmovlS", { Gv
, Ev
} },
2599 { "cmovgeS", { Gv
, Ev
} },
2600 { "cmovleS", { Gv
, Ev
} },
2601 { "cmovgS", { Gv
, Ev
} },
2603 { MOD_TABLE (MOD_0F51
) },
2604 { PREFIX_TABLE (PREFIX_0F51
) },
2605 { PREFIX_TABLE (PREFIX_0F52
) },
2606 { PREFIX_TABLE (PREFIX_0F53
) },
2607 { "andpX", { XM
, EXx
} },
2608 { "andnpX", { XM
, EXx
} },
2609 { "orpX", { XM
, EXx
} },
2610 { "xorpX", { XM
, EXx
} },
2612 { PREFIX_TABLE (PREFIX_0F58
) },
2613 { PREFIX_TABLE (PREFIX_0F59
) },
2614 { PREFIX_TABLE (PREFIX_0F5A
) },
2615 { PREFIX_TABLE (PREFIX_0F5B
) },
2616 { PREFIX_TABLE (PREFIX_0F5C
) },
2617 { PREFIX_TABLE (PREFIX_0F5D
) },
2618 { PREFIX_TABLE (PREFIX_0F5E
) },
2619 { PREFIX_TABLE (PREFIX_0F5F
) },
2621 { PREFIX_TABLE (PREFIX_0F60
) },
2622 { PREFIX_TABLE (PREFIX_0F61
) },
2623 { PREFIX_TABLE (PREFIX_0F62
) },
2624 { "packsswb", { MX
, EM
} },
2625 { "pcmpgtb", { MX
, EM
} },
2626 { "pcmpgtw", { MX
, EM
} },
2627 { "pcmpgtd", { MX
, EM
} },
2628 { "packuswb", { MX
, EM
} },
2630 { "punpckhbw", { MX
, EM
} },
2631 { "punpckhwd", { MX
, EM
} },
2632 { "punpckhdq", { MX
, EM
} },
2633 { "packssdw", { MX
, EM
} },
2634 { PREFIX_TABLE (PREFIX_0F6C
) },
2635 { PREFIX_TABLE (PREFIX_0F6D
) },
2636 { "movK", { MX
, Edq
} },
2637 { PREFIX_TABLE (PREFIX_0F6F
) },
2639 { PREFIX_TABLE (PREFIX_0F70
) },
2640 { REG_TABLE (REG_0F71
) },
2641 { REG_TABLE (REG_0F72
) },
2642 { REG_TABLE (REG_0F73
) },
2643 { "pcmpeqb", { MX
, EM
} },
2644 { "pcmpeqw", { MX
, EM
} },
2645 { "pcmpeqd", { MX
, EM
} },
2648 { PREFIX_TABLE (PREFIX_0F78
) },
2649 { PREFIX_TABLE (PREFIX_0F79
) },
2650 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2652 { PREFIX_TABLE (PREFIX_0F7C
) },
2653 { PREFIX_TABLE (PREFIX_0F7D
) },
2654 { PREFIX_TABLE (PREFIX_0F7E
) },
2655 { PREFIX_TABLE (PREFIX_0F7F
) },
2657 { "joH", { Jv
, BND
, cond_jump_flag
} },
2658 { "jnoH", { Jv
, BND
, cond_jump_flag
} },
2659 { "jbH", { Jv
, BND
, cond_jump_flag
} },
2660 { "jaeH", { Jv
, BND
, cond_jump_flag
} },
2661 { "jeH", { Jv
, BND
, cond_jump_flag
} },
2662 { "jneH", { Jv
, BND
, cond_jump_flag
} },
2663 { "jbeH", { Jv
, BND
, cond_jump_flag
} },
2664 { "jaH", { Jv
, BND
, cond_jump_flag
} },
2666 { "jsH", { Jv
, BND
, cond_jump_flag
} },
2667 { "jnsH", { Jv
, BND
, cond_jump_flag
} },
2668 { "jpH", { Jv
, BND
, cond_jump_flag
} },
2669 { "jnpH", { Jv
, BND
, cond_jump_flag
} },
2670 { "jlH", { Jv
, BND
, cond_jump_flag
} },
2671 { "jgeH", { Jv
, BND
, cond_jump_flag
} },
2672 { "jleH", { Jv
, BND
, cond_jump_flag
} },
2673 { "jgH", { Jv
, BND
, cond_jump_flag
} },
2676 { "setno", { Eb
} },
2678 { "setae", { Eb
} },
2680 { "setne", { Eb
} },
2681 { "setbe", { Eb
} },
2685 { "setns", { Eb
} },
2687 { "setnp", { Eb
} },
2689 { "setge", { Eb
} },
2690 { "setle", { Eb
} },
2693 { "pushT", { fs
} },
2695 { "cpuid", { XX
} },
2696 { "btS", { Ev
, Gv
} },
2697 { "shldS", { Ev
, Gv
, Ib
} },
2698 { "shldS", { Ev
, Gv
, CL
} },
2699 { REG_TABLE (REG_0FA6
) },
2700 { REG_TABLE (REG_0FA7
) },
2702 { "pushT", { gs
} },
2705 { "btsS", { Evh1
, Gv
} },
2706 { "shrdS", { Ev
, Gv
, Ib
} },
2707 { "shrdS", { Ev
, Gv
, CL
} },
2708 { REG_TABLE (REG_0FAE
) },
2709 { "imulS", { Gv
, Ev
} },
2711 { "cmpxchgB", { Ebh1
, Gb
} },
2712 { "cmpxchgS", { Evh1
, Gv
} },
2713 { MOD_TABLE (MOD_0FB2
) },
2714 { "btrS", { Evh1
, Gv
} },
2715 { MOD_TABLE (MOD_0FB4
) },
2716 { MOD_TABLE (MOD_0FB5
) },
2717 { "movz{bR|x}", { Gv
, Eb
} },
2718 { "movz{wR|x}", { Gv
, Ew
} }, /* yes, there really is movzww ! */
2720 { PREFIX_TABLE (PREFIX_0FB8
) },
2722 { REG_TABLE (REG_0FBA
) },
2723 { "btcS", { Evh1
, Gv
} },
2724 { PREFIX_TABLE (PREFIX_0FBC
) },
2725 { PREFIX_TABLE (PREFIX_0FBD
) },
2726 { "movs{bR|x}", { Gv
, Eb
} },
2727 { "movs{wR|x}", { Gv
, Ew
} }, /* yes, there really is movsww ! */
2729 { "xaddB", { Ebh1
, Gb
} },
2730 { "xaddS", { Evh1
, Gv
} },
2731 { PREFIX_TABLE (PREFIX_0FC2
) },
2732 { PREFIX_TABLE (PREFIX_0FC3
) },
2733 { "pinsrw", { MX
, Edqw
, Ib
} },
2734 { "pextrw", { Gdq
, MS
, Ib
} },
2735 { "shufpX", { XM
, EXx
, Ib
} },
2736 { REG_TABLE (REG_0FC7
) },
2738 { "bswap", { RMeAX
} },
2739 { "bswap", { RMeCX
} },
2740 { "bswap", { RMeDX
} },
2741 { "bswap", { RMeBX
} },
2742 { "bswap", { RMeSP
} },
2743 { "bswap", { RMeBP
} },
2744 { "bswap", { RMeSI
} },
2745 { "bswap", { RMeDI
} },
2747 { PREFIX_TABLE (PREFIX_0FD0
) },
2748 { "psrlw", { MX
, EM
} },
2749 { "psrld", { MX
, EM
} },
2750 { "psrlq", { MX
, EM
} },
2751 { "paddq", { MX
, EM
} },
2752 { "pmullw", { MX
, EM
} },
2753 { PREFIX_TABLE (PREFIX_0FD6
) },
2754 { MOD_TABLE (MOD_0FD7
) },
2756 { "psubusb", { MX
, EM
} },
2757 { "psubusw", { MX
, EM
} },
2758 { "pminub", { MX
, EM
} },
2759 { "pand", { MX
, EM
} },
2760 { "paddusb", { MX
, EM
} },
2761 { "paddusw", { MX
, EM
} },
2762 { "pmaxub", { MX
, EM
} },
2763 { "pandn", { MX
, EM
} },
2765 { "pavgb", { MX
, EM
} },
2766 { "psraw", { MX
, EM
} },
2767 { "psrad", { MX
, EM
} },
2768 { "pavgw", { MX
, EM
} },
2769 { "pmulhuw", { MX
, EM
} },
2770 { "pmulhw", { MX
, EM
} },
2771 { PREFIX_TABLE (PREFIX_0FE6
) },
2772 { PREFIX_TABLE (PREFIX_0FE7
) },
2774 { "psubsb", { MX
, EM
} },
2775 { "psubsw", { MX
, EM
} },
2776 { "pminsw", { MX
, EM
} },
2777 { "por", { MX
, EM
} },
2778 { "paddsb", { MX
, EM
} },
2779 { "paddsw", { MX
, EM
} },
2780 { "pmaxsw", { MX
, EM
} },
2781 { "pxor", { MX
, EM
} },
2783 { PREFIX_TABLE (PREFIX_0FF0
) },
2784 { "psllw", { MX
, EM
} },
2785 { "pslld", { MX
, EM
} },
2786 { "psllq", { MX
, EM
} },
2787 { "pmuludq", { MX
, EM
} },
2788 { "pmaddwd", { MX
, EM
} },
2789 { "psadbw", { MX
, EM
} },
2790 { PREFIX_TABLE (PREFIX_0FF7
) },
2792 { "psubb", { MX
, EM
} },
2793 { "psubw", { MX
, EM
} },
2794 { "psubd", { MX
, EM
} },
2795 { "psubq", { MX
, EM
} },
2796 { "paddb", { MX
, EM
} },
2797 { "paddw", { MX
, EM
} },
2798 { "paddd", { MX
, EM
} },
2802 static const unsigned char onebyte_has_modrm
[256] = {
2803 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2804 /* ------------------------------- */
2805 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2806 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2807 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2808 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2809 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2810 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2811 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2812 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2813 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2814 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2815 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2816 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2817 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2818 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2819 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2820 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2821 /* ------------------------------- */
2822 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2825 static const unsigned char twobyte_has_modrm
[256] = {
2826 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2827 /* ------------------------------- */
2828 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2829 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2830 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2831 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2832 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2833 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2834 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2835 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2836 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2837 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2838 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2839 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2840 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2841 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2842 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2843 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2844 /* ------------------------------- */
2845 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2848 static char obuf
[100];
2850 static char *mnemonicendp
;
2851 static char scratchbuf
[100];
2852 static unsigned char *start_codep
;
2853 static unsigned char *insn_codep
;
2854 static unsigned char *codep
;
2855 static int last_lock_prefix
;
2856 static int last_repz_prefix
;
2857 static int last_repnz_prefix
;
2858 static int last_data_prefix
;
2859 static int last_addr_prefix
;
2860 static int last_rex_prefix
;
2861 static int last_seg_prefix
;
2862 #define MAX_CODE_LENGTH 15
2863 /* We can up to 14 prefixes since the maximum instruction length is
2865 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2866 static disassemble_info
*the_info
;
2874 static unsigned char need_modrm
;
2884 int register_specifier
;
2891 int mask_register_specifier
;
2897 static unsigned char need_vex
;
2898 static unsigned char need_vex_reg
;
2899 static unsigned char vex_w_done
;
2907 /* If we are accessing mod/rm/reg without need_modrm set, then the
2908 values are stale. Hitting this abort likely indicates that you
2909 need to update onebyte_has_modrm or twobyte_has_modrm. */
2910 #define MODRM_CHECK if (!need_modrm) abort ()
2912 static const char **names64
;
2913 static const char **names32
;
2914 static const char **names16
;
2915 static const char **names8
;
2916 static const char **names8rex
;
2917 static const char **names_seg
;
2918 static const char *index64
;
2919 static const char *index32
;
2920 static const char **index16
;
2921 static const char **names_bnd
;
2923 static const char *intel_names64
[] = {
2924 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2925 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2927 static const char *intel_names32
[] = {
2928 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2929 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2931 static const char *intel_names16
[] = {
2932 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2933 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2935 static const char *intel_names8
[] = {
2936 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2938 static const char *intel_names8rex
[] = {
2939 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2940 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2942 static const char *intel_names_seg
[] = {
2943 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2945 static const char *intel_index64
= "riz";
2946 static const char *intel_index32
= "eiz";
2947 static const char *intel_index16
[] = {
2948 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2951 static const char *att_names64
[] = {
2952 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2953 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2955 static const char *att_names32
[] = {
2956 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2957 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2959 static const char *att_names16
[] = {
2960 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2961 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2963 static const char *att_names8
[] = {
2964 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2966 static const char *att_names8rex
[] = {
2967 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2968 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2970 static const char *att_names_seg
[] = {
2971 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2973 static const char *att_index64
= "%riz";
2974 static const char *att_index32
= "%eiz";
2975 static const char *att_index16
[] = {
2976 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2979 static const char **names_mm
;
2980 static const char *intel_names_mm
[] = {
2981 "mm0", "mm1", "mm2", "mm3",
2982 "mm4", "mm5", "mm6", "mm7"
2984 static const char *att_names_mm
[] = {
2985 "%mm0", "%mm1", "%mm2", "%mm3",
2986 "%mm4", "%mm5", "%mm6", "%mm7"
2989 static const char *intel_names_bnd
[] = {
2990 "bnd0", "bnd1", "bnd2", "bnd3"
2993 static const char *att_names_bnd
[] = {
2994 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2997 static const char **names_xmm
;
2998 static const char *intel_names_xmm
[] = {
2999 "xmm0", "xmm1", "xmm2", "xmm3",
3000 "xmm4", "xmm5", "xmm6", "xmm7",
3001 "xmm8", "xmm9", "xmm10", "xmm11",
3002 "xmm12", "xmm13", "xmm14", "xmm15",
3003 "xmm16", "xmm17", "xmm18", "xmm19",
3004 "xmm20", "xmm21", "xmm22", "xmm23",
3005 "xmm24", "xmm25", "xmm26", "xmm27",
3006 "xmm28", "xmm29", "xmm30", "xmm31"
3008 static const char *att_names_xmm
[] = {
3009 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3010 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3011 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3012 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3013 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3014 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3015 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3016 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3019 static const char **names_ymm
;
3020 static const char *intel_names_ymm
[] = {
3021 "ymm0", "ymm1", "ymm2", "ymm3",
3022 "ymm4", "ymm5", "ymm6", "ymm7",
3023 "ymm8", "ymm9", "ymm10", "ymm11",
3024 "ymm12", "ymm13", "ymm14", "ymm15",
3025 "ymm16", "ymm17", "ymm18", "ymm19",
3026 "ymm20", "ymm21", "ymm22", "ymm23",
3027 "ymm24", "ymm25", "ymm26", "ymm27",
3028 "ymm28", "ymm29", "ymm30", "ymm31"
3030 static const char *att_names_ymm
[] = {
3031 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3032 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3033 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3034 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3035 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3036 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3037 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3038 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3041 static const char **names_zmm
;
3042 static const char *intel_names_zmm
[] = {
3043 "zmm0", "zmm1", "zmm2", "zmm3",
3044 "zmm4", "zmm5", "zmm6", "zmm7",
3045 "zmm8", "zmm9", "zmm10", "zmm11",
3046 "zmm12", "zmm13", "zmm14", "zmm15",
3047 "zmm16", "zmm17", "zmm18", "zmm19",
3048 "zmm20", "zmm21", "zmm22", "zmm23",
3049 "zmm24", "zmm25", "zmm26", "zmm27",
3050 "zmm28", "zmm29", "zmm30", "zmm31"
3052 static const char *att_names_zmm
[] = {
3053 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3054 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3055 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3056 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3057 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3058 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3059 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3060 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3063 static const char **names_mask
;
3064 static const char *intel_names_mask
[] = {
3065 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3067 static const char *att_names_mask
[] = {
3068 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3071 static const char *names_rounding
[] =
3079 static const struct dis386 reg_table
[][8] = {
3082 { "addA", { Ebh1
, Ib
} },
3083 { "orA", { Ebh1
, Ib
} },
3084 { "adcA", { Ebh1
, Ib
} },
3085 { "sbbA", { Ebh1
, Ib
} },
3086 { "andA", { Ebh1
, Ib
} },
3087 { "subA", { Ebh1
, Ib
} },
3088 { "xorA", { Ebh1
, Ib
} },
3089 { "cmpA", { Eb
, Ib
} },
3093 { "addQ", { Evh1
, Iv
} },
3094 { "orQ", { Evh1
, Iv
} },
3095 { "adcQ", { Evh1
, Iv
} },
3096 { "sbbQ", { Evh1
, Iv
} },
3097 { "andQ", { Evh1
, Iv
} },
3098 { "subQ", { Evh1
, Iv
} },
3099 { "xorQ", { Evh1
, Iv
} },
3100 { "cmpQ", { Ev
, Iv
} },
3104 { "addQ", { Evh1
, sIb
} },
3105 { "orQ", { Evh1
, sIb
} },
3106 { "adcQ", { Evh1
, sIb
} },
3107 { "sbbQ", { Evh1
, sIb
} },
3108 { "andQ", { Evh1
, sIb
} },
3109 { "subQ", { Evh1
, sIb
} },
3110 { "xorQ", { Evh1
, sIb
} },
3111 { "cmpQ", { Ev
, sIb
} },
3115 { "popU", { stackEv
} },
3116 { XOP_8F_TABLE (XOP_09
) },
3120 { XOP_8F_TABLE (XOP_09
) },
3124 { "rolA", { Eb
, Ib
} },
3125 { "rorA", { Eb
, Ib
} },
3126 { "rclA", { Eb
, Ib
} },
3127 { "rcrA", { Eb
, Ib
} },
3128 { "shlA", { Eb
, Ib
} },
3129 { "shrA", { Eb
, Ib
} },
3131 { "sarA", { Eb
, Ib
} },
3135 { "rolQ", { Ev
, Ib
} },
3136 { "rorQ", { Ev
, Ib
} },
3137 { "rclQ", { Ev
, Ib
} },
3138 { "rcrQ", { Ev
, Ib
} },
3139 { "shlQ", { Ev
, Ib
} },
3140 { "shrQ", { Ev
, Ib
} },
3142 { "sarQ", { Ev
, Ib
} },
3146 { "movA", { Ebh3
, Ib
} },
3153 { MOD_TABLE (MOD_C6_REG_7
) },
3157 { "movQ", { Evh3
, Iv
} },
3164 { MOD_TABLE (MOD_C7_REG_7
) },
3168 { "rolA", { Eb
, I1
} },
3169 { "rorA", { Eb
, I1
} },
3170 { "rclA", { Eb
, I1
} },
3171 { "rcrA", { Eb
, I1
} },
3172 { "shlA", { Eb
, I1
} },
3173 { "shrA", { Eb
, I1
} },
3175 { "sarA", { Eb
, I1
} },
3179 { "rolQ", { Ev
, I1
} },
3180 { "rorQ", { Ev
, I1
} },
3181 { "rclQ", { Ev
, I1
} },
3182 { "rcrQ", { Ev
, I1
} },
3183 { "shlQ", { Ev
, I1
} },
3184 { "shrQ", { Ev
, I1
} },
3186 { "sarQ", { Ev
, I1
} },
3190 { "rolA", { Eb
, CL
} },
3191 { "rorA", { Eb
, CL
} },
3192 { "rclA", { Eb
, CL
} },
3193 { "rcrA", { Eb
, CL
} },
3194 { "shlA", { Eb
, CL
} },
3195 { "shrA", { Eb
, CL
} },
3197 { "sarA", { Eb
, CL
} },
3201 { "rolQ", { Ev
, CL
} },
3202 { "rorQ", { Ev
, CL
} },
3203 { "rclQ", { Ev
, CL
} },
3204 { "rcrQ", { Ev
, CL
} },
3205 { "shlQ", { Ev
, CL
} },
3206 { "shrQ", { Ev
, CL
} },
3208 { "sarQ", { Ev
, CL
} },
3212 { "testA", { Eb
, Ib
} },
3214 { "notA", { Ebh1
} },
3215 { "negA", { Ebh1
} },
3216 { "mulA", { Eb
} }, /* Don't print the implicit %al register, */
3217 { "imulA", { Eb
} }, /* to distinguish these opcodes from other */
3218 { "divA", { Eb
} }, /* mul/imul opcodes. Do the same for div */
3219 { "idivA", { Eb
} }, /* and idiv for consistency. */
3223 { "testQ", { Ev
, Iv
} },
3225 { "notQ", { Evh1
} },
3226 { "negQ", { Evh1
} },
3227 { "mulQ", { Ev
} }, /* Don't print the implicit register. */
3228 { "imulQ", { Ev
} },
3230 { "idivQ", { Ev
} },
3234 { "incA", { Ebh1
} },
3235 { "decA", { Ebh1
} },
3239 { "incQ", { Evh1
} },
3240 { "decQ", { Evh1
} },
3241 { "call{T|}", { indirEv
, BND
} },
3242 { MOD_TABLE (MOD_FF_REG_3
) },
3243 { "jmp{T|}", { indirEv
, BND
} },
3244 { MOD_TABLE (MOD_FF_REG_5
) },
3245 { "pushU", { stackEv
} },
3250 { "sldtD", { Sv
} },
3261 { MOD_TABLE (MOD_0F01_REG_0
) },
3262 { MOD_TABLE (MOD_0F01_REG_1
) },
3263 { MOD_TABLE (MOD_0F01_REG_2
) },
3264 { MOD_TABLE (MOD_0F01_REG_3
) },
3265 { "smswD", { Sv
} },
3268 { MOD_TABLE (MOD_0F01_REG_7
) },
3272 { "prefetch", { Mb
} },
3273 { "prefetchw", { Mb
} },
3274 { "prefetchwt1", { Mb
} },
3275 { "prefetch", { Mb
} },
3276 { "prefetch", { Mb
} },
3277 { "prefetch", { Mb
} },
3278 { "prefetch", { Mb
} },
3279 { "prefetch", { Mb
} },
3283 { MOD_TABLE (MOD_0F18_REG_0
) },
3284 { MOD_TABLE (MOD_0F18_REG_1
) },
3285 { MOD_TABLE (MOD_0F18_REG_2
) },
3286 { MOD_TABLE (MOD_0F18_REG_3
) },
3287 { MOD_TABLE (MOD_0F18_REG_4
) },
3288 { MOD_TABLE (MOD_0F18_REG_5
) },
3289 { MOD_TABLE (MOD_0F18_REG_6
) },
3290 { MOD_TABLE (MOD_0F18_REG_7
) },
3296 { MOD_TABLE (MOD_0F71_REG_2
) },
3298 { MOD_TABLE (MOD_0F71_REG_4
) },
3300 { MOD_TABLE (MOD_0F71_REG_6
) },
3306 { MOD_TABLE (MOD_0F72_REG_2
) },
3308 { MOD_TABLE (MOD_0F72_REG_4
) },
3310 { MOD_TABLE (MOD_0F72_REG_6
) },
3316 { MOD_TABLE (MOD_0F73_REG_2
) },
3317 { MOD_TABLE (MOD_0F73_REG_3
) },
3320 { MOD_TABLE (MOD_0F73_REG_6
) },
3321 { MOD_TABLE (MOD_0F73_REG_7
) },
3325 { "montmul", { { OP_0f07
, 0 } } },
3326 { "xsha1", { { OP_0f07
, 0 } } },
3327 { "xsha256", { { OP_0f07
, 0 } } },
3331 { "xstore-rng", { { OP_0f07
, 0 } } },
3332 { "xcrypt-ecb", { { OP_0f07
, 0 } } },
3333 { "xcrypt-cbc", { { OP_0f07
, 0 } } },
3334 { "xcrypt-ctr", { { OP_0f07
, 0 } } },
3335 { "xcrypt-cfb", { { OP_0f07
, 0 } } },
3336 { "xcrypt-ofb", { { OP_0f07
, 0 } } },
3340 { MOD_TABLE (MOD_0FAE_REG_0
) },
3341 { MOD_TABLE (MOD_0FAE_REG_1
) },
3342 { MOD_TABLE (MOD_0FAE_REG_2
) },
3343 { MOD_TABLE (MOD_0FAE_REG_3
) },
3344 { MOD_TABLE (MOD_0FAE_REG_4
) },
3345 { MOD_TABLE (MOD_0FAE_REG_5
) },
3346 { MOD_TABLE (MOD_0FAE_REG_6
) },
3347 { MOD_TABLE (MOD_0FAE_REG_7
) },
3355 { "btQ", { Ev
, Ib
} },
3356 { "btsQ", { Evh1
, Ib
} },
3357 { "btrQ", { Evh1
, Ib
} },
3358 { "btcQ", { Evh1
, Ib
} },
3363 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} } },
3365 { MOD_TABLE (MOD_0FC7_REG_3
) },
3366 { MOD_TABLE (MOD_0FC7_REG_4
) },
3367 { MOD_TABLE (MOD_0FC7_REG_5
) },
3368 { MOD_TABLE (MOD_0FC7_REG_6
) },
3369 { MOD_TABLE (MOD_0FC7_REG_7
) },
3375 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3377 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3379 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3385 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3387 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3389 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3395 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3396 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3399 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3400 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3406 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3407 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3409 /* REG_VEX_0F38F3 */
3412 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3413 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3414 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3418 { "llwpcb", { { OP_LWPCB_E
, 0 } } },
3419 { "slwpcb", { { OP_LWPCB_E
, 0 } } },
3423 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
3424 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
3426 /* REG_XOP_TBM_01 */
3429 { "blcfill", { { OP_LWP_E
, 0 }, Ev
} },
3430 { "blsfill", { { OP_LWP_E
, 0 }, Ev
} },
3431 { "blcs", { { OP_LWP_E
, 0 }, Ev
} },
3432 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
} },
3433 { "blcic", { { OP_LWP_E
, 0 }, Ev
} },
3434 { "blsic", { { OP_LWP_E
, 0 }, Ev
} },
3435 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
} },
3437 /* REG_XOP_TBM_02 */
3440 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
} },
3445 { "blci", { { OP_LWP_E
, 0 }, Ev
} },
3447 #define NEED_REG_TABLE
3448 #include "i386-dis-evex.h"
3449 #undef NEED_REG_TABLE
3452 static const struct dis386 prefix_table
[][4] = {
3455 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
3456 { "pause", { XX
} },
3457 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
3462 { "movups", { XM
, EXx
} },
3463 { "movss", { XM
, EXd
} },
3464 { "movupd", { XM
, EXx
} },
3465 { "movsd", { XM
, EXq
} },
3470 { "movups", { EXxS
, XM
} },
3471 { "movss", { EXdS
, XM
} },
3472 { "movupd", { EXxS
, XM
} },
3473 { "movsd", { EXqS
, XM
} },
3478 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3479 { "movsldup", { XM
, EXx
} },
3480 { "movlpd", { XM
, EXq
} },
3481 { "movddup", { XM
, EXq
} },
3486 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3487 { "movshdup", { XM
, EXx
} },
3488 { "movhpd", { XM
, EXq
} },
3493 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3494 { "bndcl", { Gbnd
, Ev_bnd
} },
3495 { "bndmov", { Gbnd
, Ebnd
} },
3496 { "bndcu", { Gbnd
, Ev_bnd
} },
3501 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3502 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3503 { "bndmov", { Ebnd
, Gbnd
} },
3504 { "bndcn", { Gbnd
, Ev_bnd
} },
3509 { "cvtpi2ps", { XM
, EMCq
} },
3510 { "cvtsi2ss%LQ", { XM
, Ev
} },
3511 { "cvtpi2pd", { XM
, EMCq
} },
3512 { "cvtsi2sd%LQ", { XM
, Ev
} },
3517 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3518 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3519 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3520 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3525 { "cvttps2pi", { MXC
, EXq
} },
3526 { "cvttss2siY", { Gv
, EXd
} },
3527 { "cvttpd2pi", { MXC
, EXx
} },
3528 { "cvttsd2siY", { Gv
, EXq
} },
3533 { "cvtps2pi", { MXC
, EXq
} },
3534 { "cvtss2siY", { Gv
, EXd
} },
3535 { "cvtpd2pi", { MXC
, EXx
} },
3536 { "cvtsd2siY", { Gv
, EXq
} },
3541 { "ucomiss",{ XM
, EXd
} },
3543 { "ucomisd",{ XM
, EXq
} },
3548 { "comiss", { XM
, EXd
} },
3550 { "comisd", { XM
, EXq
} },
3555 { "sqrtps", { XM
, EXx
} },
3556 { "sqrtss", { XM
, EXd
} },
3557 { "sqrtpd", { XM
, EXx
} },
3558 { "sqrtsd", { XM
, EXq
} },
3563 { "rsqrtps",{ XM
, EXx
} },
3564 { "rsqrtss",{ XM
, EXd
} },
3569 { "rcpps", { XM
, EXx
} },
3570 { "rcpss", { XM
, EXd
} },
3575 { "addps", { XM
, EXx
} },
3576 { "addss", { XM
, EXd
} },
3577 { "addpd", { XM
, EXx
} },
3578 { "addsd", { XM
, EXq
} },
3583 { "mulps", { XM
, EXx
} },
3584 { "mulss", { XM
, EXd
} },
3585 { "mulpd", { XM
, EXx
} },
3586 { "mulsd", { XM
, EXq
} },
3591 { "cvtps2pd", { XM
, EXq
} },
3592 { "cvtss2sd", { XM
, EXd
} },
3593 { "cvtpd2ps", { XM
, EXx
} },
3594 { "cvtsd2ss", { XM
, EXq
} },
3599 { "cvtdq2ps", { XM
, EXx
} },
3600 { "cvttps2dq", { XM
, EXx
} },
3601 { "cvtps2dq", { XM
, EXx
} },
3606 { "subps", { XM
, EXx
} },
3607 { "subss", { XM
, EXd
} },
3608 { "subpd", { XM
, EXx
} },
3609 { "subsd", { XM
, EXq
} },
3614 { "minps", { XM
, EXx
} },
3615 { "minss", { XM
, EXd
} },
3616 { "minpd", { XM
, EXx
} },
3617 { "minsd", { XM
, EXq
} },
3622 { "divps", { XM
, EXx
} },
3623 { "divss", { XM
, EXd
} },
3624 { "divpd", { XM
, EXx
} },
3625 { "divsd", { XM
, EXq
} },
3630 { "maxps", { XM
, EXx
} },
3631 { "maxss", { XM
, EXd
} },
3632 { "maxpd", { XM
, EXx
} },
3633 { "maxsd", { XM
, EXq
} },
3638 { "punpcklbw",{ MX
, EMd
} },
3640 { "punpcklbw",{ MX
, EMx
} },
3645 { "punpcklwd",{ MX
, EMd
} },
3647 { "punpcklwd",{ MX
, EMx
} },
3652 { "punpckldq",{ MX
, EMd
} },
3654 { "punpckldq",{ MX
, EMx
} },
3661 { "punpcklqdq", { XM
, EXx
} },
3668 { "punpckhqdq", { XM
, EXx
} },
3673 { "movq", { MX
, EM
} },
3674 { "movdqu", { XM
, EXx
} },
3675 { "movdqa", { XM
, EXx
} },
3680 { "pshufw", { MX
, EM
, Ib
} },
3681 { "pshufhw",{ XM
, EXx
, Ib
} },
3682 { "pshufd", { XM
, EXx
, Ib
} },
3683 { "pshuflw",{ XM
, EXx
, Ib
} },
3686 /* PREFIX_0F73_REG_3 */
3690 { "psrldq", { XS
, Ib
} },
3693 /* PREFIX_0F73_REG_7 */
3697 { "pslldq", { XS
, Ib
} },
3702 {"vmread", { Em
, Gm
} },
3704 {"extrq", { XS
, Ib
, Ib
} },
3705 {"insertq", { XM
, XS
, Ib
, Ib
} },
3710 {"vmwrite", { Gm
, Em
} },
3712 {"extrq", { XM
, XS
} },
3713 {"insertq", { XM
, XS
} },
3720 { "haddpd", { XM
, EXx
} },
3721 { "haddps", { XM
, EXx
} },
3728 { "hsubpd", { XM
, EXx
} },
3729 { "hsubps", { XM
, EXx
} },
3734 { "movK", { Edq
, MX
} },
3735 { "movq", { XM
, EXq
} },
3736 { "movK", { Edq
, XM
} },
3741 { "movq", { EMS
, MX
} },
3742 { "movdqu", { EXxS
, XM
} },
3743 { "movdqa", { EXxS
, XM
} },
3746 /* PREFIX_0FAE_REG_0 */
3749 { "rdfsbase", { Ev
} },
3752 /* PREFIX_0FAE_REG_1 */
3755 { "rdgsbase", { Ev
} },
3758 /* PREFIX_0FAE_REG_2 */
3761 { "wrfsbase", { Ev
} },
3764 /* PREFIX_0FAE_REG_3 */
3767 { "wrgsbase", { Ev
} },
3770 /* PREFIX_0FAE_REG_7 */
3772 { "clflush", { Mb
} },
3774 { "clflushopt", { Mb
} },
3780 { "popcntS", { Gv
, Ev
} },
3785 { "bsfS", { Gv
, Ev
} },
3786 { "tzcntS", { Gv
, Ev
} },
3787 { "bsfS", { Gv
, Ev
} },
3792 { "bsrS", { Gv
, Ev
} },
3793 { "lzcntS", { Gv
, Ev
} },
3794 { "bsrS", { Gv
, Ev
} },
3799 { "cmpps", { XM
, EXx
, CMP
} },
3800 { "cmpss", { XM
, EXd
, CMP
} },
3801 { "cmppd", { XM
, EXx
, CMP
} },
3802 { "cmpsd", { XM
, EXq
, CMP
} },
3807 { "movntiS", { Ma
, Gv
} },
3810 /* PREFIX_0FC7_REG_6 */
3812 { "vmptrld",{ Mq
} },
3813 { "vmxon", { Mq
} },
3814 { "vmclear",{ Mq
} },
3821 { "addsubpd", { XM
, EXx
} },
3822 { "addsubps", { XM
, EXx
} },
3828 { "movq2dq",{ XM
, MS
} },
3829 { "movq", { EXqS
, XM
} },
3830 { "movdq2q",{ MX
, XS
} },
3836 { "cvtdq2pd", { XM
, EXq
} },
3837 { "cvttpd2dq", { XM
, EXx
} },
3838 { "cvtpd2dq", { XM
, EXx
} },
3843 { "movntq", { Mq
, MX
} },
3845 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3853 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3858 { "maskmovq", { MX
, MS
} },
3860 { "maskmovdqu", { XM
, XS
} },
3867 { "pblendvb", { XM
, EXx
, XMM0
} },
3874 { "blendvps", { XM
, EXx
, XMM0
} },
3881 { "blendvpd", { XM
, EXx
, XMM0
} },
3888 { "ptest", { XM
, EXx
} },
3895 { "pmovsxbw", { XM
, EXq
} },
3902 { "pmovsxbd", { XM
, EXd
} },
3909 { "pmovsxbq", { XM
, EXw
} },
3916 { "pmovsxwd", { XM
, EXq
} },
3923 { "pmovsxwq", { XM
, EXd
} },
3930 { "pmovsxdq", { XM
, EXq
} },
3937 { "pmuldq", { XM
, EXx
} },
3944 { "pcmpeqq", { XM
, EXx
} },
3951 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
3958 { "packusdw", { XM
, EXx
} },
3965 { "pmovzxbw", { XM
, EXq
} },
3972 { "pmovzxbd", { XM
, EXd
} },
3979 { "pmovzxbq", { XM
, EXw
} },
3986 { "pmovzxwd", { XM
, EXq
} },
3993 { "pmovzxwq", { XM
, EXd
} },
4000 { "pmovzxdq", { XM
, EXq
} },
4007 { "pcmpgtq", { XM
, EXx
} },
4014 { "pminsb", { XM
, EXx
} },
4021 { "pminsd", { XM
, EXx
} },
4028 { "pminuw", { XM
, EXx
} },
4035 { "pminud", { XM
, EXx
} },
4042 { "pmaxsb", { XM
, EXx
} },
4049 { "pmaxsd", { XM
, EXx
} },
4056 { "pmaxuw", { XM
, EXx
} },
4063 { "pmaxud", { XM
, EXx
} },
4070 { "pmulld", { XM
, EXx
} },
4077 { "phminposuw", { XM
, EXx
} },
4084 { "invept", { Gm
, Mo
} },
4091 { "invvpid", { Gm
, Mo
} },
4098 { "invpcid", { Gm
, M
} },
4103 { "sha1nexte", { XM
, EXxmm
} },
4108 { "sha1msg1", { XM
, EXxmm
} },
4113 { "sha1msg2", { XM
, EXxmm
} },
4118 { "sha256rnds2", { XM
, EXxmm
, XMM0
} },
4123 { "sha256msg1", { XM
, EXxmm
} },
4128 { "sha256msg2", { XM
, EXxmm
} },
4135 { "aesimc", { XM
, EXx
} },
4142 { "aesenc", { XM
, EXx
} },
4149 { "aesenclast", { XM
, EXx
} },
4156 { "aesdec", { XM
, EXx
} },
4163 { "aesdeclast", { XM
, EXx
} },
4168 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
4170 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
4171 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} } },
4176 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
4178 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
4179 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} } },
4185 { "adoxS", { Gdq
, Edq
} },
4186 { "adcxS", { Gdq
, Edq
} },
4194 { "roundps", { XM
, EXx
, Ib
} },
4201 { "roundpd", { XM
, EXx
, Ib
} },
4208 { "roundss", { XM
, EXd
, Ib
} },
4215 { "roundsd", { XM
, EXq
, Ib
} },
4222 { "blendps", { XM
, EXx
, Ib
} },
4229 { "blendpd", { XM
, EXx
, Ib
} },
4236 { "pblendw", { XM
, EXx
, Ib
} },
4243 { "pextrb", { Edqb
, XM
, Ib
} },
4250 { "pextrw", { Edqw
, XM
, Ib
} },
4257 { "pextrK", { Edq
, XM
, Ib
} },
4264 { "extractps", { Edqd
, XM
, Ib
} },
4271 { "pinsrb", { XM
, Edqb
, Ib
} },
4278 { "insertps", { XM
, EXd
, Ib
} },
4285 { "pinsrK", { XM
, Edq
, Ib
} },
4292 { "dpps", { XM
, EXx
, Ib
} },
4299 { "dppd", { XM
, EXx
, Ib
} },
4306 { "mpsadbw", { XM
, EXx
, Ib
} },
4313 { "pclmulqdq", { XM
, EXx
, PCLMUL
} },
4320 { "pcmpestrm", { XM
, EXx
, Ib
} },
4327 { "pcmpestri", { XM
, EXx
, Ib
} },
4334 { "pcmpistrm", { XM
, EXx
, Ib
} },
4341 { "pcmpistri", { XM
, EXx
, Ib
} },
4346 { "sha1rnds4", { XM
, EXxmm
, Ib
} },
4353 { "aeskeygenassist", { XM
, EXx
, Ib
} },
4356 /* PREFIX_VEX_0F10 */
4358 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4359 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4360 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4361 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4364 /* PREFIX_VEX_0F11 */
4366 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4367 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4368 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4369 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4372 /* PREFIX_VEX_0F12 */
4374 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4375 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4376 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4377 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4380 /* PREFIX_VEX_0F16 */
4382 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4383 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4384 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4387 /* PREFIX_VEX_0F2A */
4390 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4392 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4395 /* PREFIX_VEX_0F2C */
4398 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4400 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4403 /* PREFIX_VEX_0F2D */
4406 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4408 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4411 /* PREFIX_VEX_0F2E */
4413 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4415 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4418 /* PREFIX_VEX_0F2F */
4420 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4422 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4425 /* PREFIX_VEX_0F41 */
4427 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4430 /* PREFIX_VEX_0F42 */
4432 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4435 /* PREFIX_VEX_0F44 */
4437 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4440 /* PREFIX_VEX_0F45 */
4442 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4445 /* PREFIX_VEX_0F46 */
4447 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4450 /* PREFIX_VEX_0F47 */
4452 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4455 /* PREFIX_VEX_0F4B */
4459 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4462 /* PREFIX_VEX_0F51 */
4464 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4465 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4466 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4467 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4470 /* PREFIX_VEX_0F52 */
4472 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4473 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4476 /* PREFIX_VEX_0F53 */
4478 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4479 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4482 /* PREFIX_VEX_0F58 */
4484 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4485 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4486 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4487 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4490 /* PREFIX_VEX_0F59 */
4492 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4493 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4494 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4495 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4498 /* PREFIX_VEX_0F5A */
4500 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4501 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4502 { "vcvtpd2ps%XY", { XMM
, EXx
} },
4503 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4506 /* PREFIX_VEX_0F5B */
4508 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4509 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4510 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4513 /* PREFIX_VEX_0F5C */
4515 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4516 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4517 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4518 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4521 /* PREFIX_VEX_0F5D */
4523 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4524 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4525 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4526 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4529 /* PREFIX_VEX_0F5E */
4531 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4532 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4533 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4534 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4537 /* PREFIX_VEX_0F5F */
4539 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4540 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4541 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4542 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4545 /* PREFIX_VEX_0F60 */
4549 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4552 /* PREFIX_VEX_0F61 */
4556 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4559 /* PREFIX_VEX_0F62 */
4563 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4566 /* PREFIX_VEX_0F63 */
4570 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4573 /* PREFIX_VEX_0F64 */
4577 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4580 /* PREFIX_VEX_0F65 */
4584 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4587 /* PREFIX_VEX_0F66 */
4591 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4594 /* PREFIX_VEX_0F67 */
4598 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4601 /* PREFIX_VEX_0F68 */
4605 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4608 /* PREFIX_VEX_0F69 */
4612 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4615 /* PREFIX_VEX_0F6A */
4619 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4622 /* PREFIX_VEX_0F6B */
4626 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4629 /* PREFIX_VEX_0F6C */
4633 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4636 /* PREFIX_VEX_0F6D */
4640 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
4643 /* PREFIX_VEX_0F6E */
4647 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4650 /* PREFIX_VEX_0F6F */
4653 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
4654 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
4657 /* PREFIX_VEX_0F70 */
4660 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
4661 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
4662 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
4665 /* PREFIX_VEX_0F71_REG_2 */
4669 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
4672 /* PREFIX_VEX_0F71_REG_4 */
4676 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
4679 /* PREFIX_VEX_0F71_REG_6 */
4683 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
4686 /* PREFIX_VEX_0F72_REG_2 */
4690 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
4693 /* PREFIX_VEX_0F72_REG_4 */
4697 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
4700 /* PREFIX_VEX_0F72_REG_6 */
4704 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
4707 /* PREFIX_VEX_0F73_REG_2 */
4711 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
4714 /* PREFIX_VEX_0F73_REG_3 */
4718 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
4721 /* PREFIX_VEX_0F73_REG_6 */
4725 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
4728 /* PREFIX_VEX_0F73_REG_7 */
4732 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
4735 /* PREFIX_VEX_0F74 */
4739 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
4742 /* PREFIX_VEX_0F75 */
4746 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
4749 /* PREFIX_VEX_0F76 */
4753 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
4756 /* PREFIX_VEX_0F77 */
4758 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
4761 /* PREFIX_VEX_0F7C */
4765 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
4766 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
4769 /* PREFIX_VEX_0F7D */
4773 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
4774 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
4777 /* PREFIX_VEX_0F7E */
4780 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
4781 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
4784 /* PREFIX_VEX_0F7F */
4787 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
4788 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
4791 /* PREFIX_VEX_0F90 */
4793 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
4796 /* PREFIX_VEX_0F91 */
4798 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
4801 /* PREFIX_VEX_0F92 */
4803 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
4806 /* PREFIX_VEX_0F93 */
4808 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
4811 /* PREFIX_VEX_0F98 */
4813 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
4816 /* PREFIX_VEX_0FC2 */
4818 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
4819 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
4820 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
4821 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
4824 /* PREFIX_VEX_0FC4 */
4828 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
4831 /* PREFIX_VEX_0FC5 */
4835 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
4838 /* PREFIX_VEX_0FD0 */
4842 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
4843 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
4846 /* PREFIX_VEX_0FD1 */
4850 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
4853 /* PREFIX_VEX_0FD2 */
4857 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
4860 /* PREFIX_VEX_0FD3 */
4864 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
4867 /* PREFIX_VEX_0FD4 */
4871 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
4874 /* PREFIX_VEX_0FD5 */
4878 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
4881 /* PREFIX_VEX_0FD6 */
4885 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
4888 /* PREFIX_VEX_0FD7 */
4892 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
4895 /* PREFIX_VEX_0FD8 */
4899 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
4902 /* PREFIX_VEX_0FD9 */
4906 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
4909 /* PREFIX_VEX_0FDA */
4913 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
4916 /* PREFIX_VEX_0FDB */
4920 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
4923 /* PREFIX_VEX_0FDC */
4927 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
4930 /* PREFIX_VEX_0FDD */
4934 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
4937 /* PREFIX_VEX_0FDE */
4941 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
4944 /* PREFIX_VEX_0FDF */
4948 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
4951 /* PREFIX_VEX_0FE0 */
4955 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
4958 /* PREFIX_VEX_0FE1 */
4962 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
4965 /* PREFIX_VEX_0FE2 */
4969 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
4972 /* PREFIX_VEX_0FE3 */
4976 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
4979 /* PREFIX_VEX_0FE4 */
4983 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
4986 /* PREFIX_VEX_0FE5 */
4990 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
4993 /* PREFIX_VEX_0FE6 */
4996 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
4997 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
4998 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5001 /* PREFIX_VEX_0FE7 */
5005 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5008 /* PREFIX_VEX_0FE8 */
5012 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5015 /* PREFIX_VEX_0FE9 */
5019 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5022 /* PREFIX_VEX_0FEA */
5026 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5029 /* PREFIX_VEX_0FEB */
5033 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5036 /* PREFIX_VEX_0FEC */
5040 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5043 /* PREFIX_VEX_0FED */
5047 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5050 /* PREFIX_VEX_0FEE */
5054 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5057 /* PREFIX_VEX_0FEF */
5061 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5064 /* PREFIX_VEX_0FF0 */
5069 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5072 /* PREFIX_VEX_0FF1 */
5076 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5079 /* PREFIX_VEX_0FF2 */
5083 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5086 /* PREFIX_VEX_0FF3 */
5090 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5093 /* PREFIX_VEX_0FF4 */
5097 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5100 /* PREFIX_VEX_0FF5 */
5104 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5107 /* PREFIX_VEX_0FF6 */
5111 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5114 /* PREFIX_VEX_0FF7 */
5118 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5121 /* PREFIX_VEX_0FF8 */
5125 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5128 /* PREFIX_VEX_0FF9 */
5132 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5135 /* PREFIX_VEX_0FFA */
5139 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5142 /* PREFIX_VEX_0FFB */
5146 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5149 /* PREFIX_VEX_0FFC */
5153 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5156 /* PREFIX_VEX_0FFD */
5160 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5163 /* PREFIX_VEX_0FFE */
5167 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5170 /* PREFIX_VEX_0F3800 */
5174 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5177 /* PREFIX_VEX_0F3801 */
5181 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5184 /* PREFIX_VEX_0F3802 */
5188 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5191 /* PREFIX_VEX_0F3803 */
5195 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5198 /* PREFIX_VEX_0F3804 */
5202 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5205 /* PREFIX_VEX_0F3805 */
5209 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5212 /* PREFIX_VEX_0F3806 */
5216 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5219 /* PREFIX_VEX_0F3807 */
5223 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5226 /* PREFIX_VEX_0F3808 */
5230 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5233 /* PREFIX_VEX_0F3809 */
5237 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5240 /* PREFIX_VEX_0F380A */
5244 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5247 /* PREFIX_VEX_0F380B */
5251 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5254 /* PREFIX_VEX_0F380C */
5258 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5261 /* PREFIX_VEX_0F380D */
5265 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5268 /* PREFIX_VEX_0F380E */
5272 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5275 /* PREFIX_VEX_0F380F */
5279 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5282 /* PREFIX_VEX_0F3813 */
5286 { "vcvtph2ps", { XM
, EXxmmq
} },
5289 /* PREFIX_VEX_0F3816 */
5293 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5296 /* PREFIX_VEX_0F3817 */
5300 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5303 /* PREFIX_VEX_0F3818 */
5307 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5310 /* PREFIX_VEX_0F3819 */
5314 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5317 /* PREFIX_VEX_0F381A */
5321 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5324 /* PREFIX_VEX_0F381C */
5328 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5331 /* PREFIX_VEX_0F381D */
5335 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5338 /* PREFIX_VEX_0F381E */
5342 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5345 /* PREFIX_VEX_0F3820 */
5349 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5352 /* PREFIX_VEX_0F3821 */
5356 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5359 /* PREFIX_VEX_0F3822 */
5363 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5366 /* PREFIX_VEX_0F3823 */
5370 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5373 /* PREFIX_VEX_0F3824 */
5377 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5380 /* PREFIX_VEX_0F3825 */
5384 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5387 /* PREFIX_VEX_0F3828 */
5391 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5394 /* PREFIX_VEX_0F3829 */
5398 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5401 /* PREFIX_VEX_0F382A */
5405 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5408 /* PREFIX_VEX_0F382B */
5412 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5415 /* PREFIX_VEX_0F382C */
5419 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5422 /* PREFIX_VEX_0F382D */
5426 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5429 /* PREFIX_VEX_0F382E */
5433 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5436 /* PREFIX_VEX_0F382F */
5440 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5443 /* PREFIX_VEX_0F3830 */
5447 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5450 /* PREFIX_VEX_0F3831 */
5454 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5457 /* PREFIX_VEX_0F3832 */
5461 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5464 /* PREFIX_VEX_0F3833 */
5468 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5471 /* PREFIX_VEX_0F3834 */
5475 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5478 /* PREFIX_VEX_0F3835 */
5482 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5485 /* PREFIX_VEX_0F3836 */
5489 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5492 /* PREFIX_VEX_0F3837 */
5496 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5499 /* PREFIX_VEX_0F3838 */
5503 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5506 /* PREFIX_VEX_0F3839 */
5510 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5513 /* PREFIX_VEX_0F383A */
5517 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5520 /* PREFIX_VEX_0F383B */
5524 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5527 /* PREFIX_VEX_0F383C */
5531 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5534 /* PREFIX_VEX_0F383D */
5538 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5541 /* PREFIX_VEX_0F383E */
5545 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5548 /* PREFIX_VEX_0F383F */
5552 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5555 /* PREFIX_VEX_0F3840 */
5559 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5562 /* PREFIX_VEX_0F3841 */
5566 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5569 /* PREFIX_VEX_0F3845 */
5573 { "vpsrlv%LW", { XM
, Vex
, EXx
} },
5576 /* PREFIX_VEX_0F3846 */
5580 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5583 /* PREFIX_VEX_0F3847 */
5587 { "vpsllv%LW", { XM
, Vex
, EXx
} },
5590 /* PREFIX_VEX_0F3858 */
5594 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5597 /* PREFIX_VEX_0F3859 */
5601 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5604 /* PREFIX_VEX_0F385A */
5608 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5611 /* PREFIX_VEX_0F3878 */
5615 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5618 /* PREFIX_VEX_0F3879 */
5622 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5625 /* PREFIX_VEX_0F388C */
5629 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5632 /* PREFIX_VEX_0F388E */
5636 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5639 /* PREFIX_VEX_0F3890 */
5643 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
} },
5646 /* PREFIX_VEX_0F3891 */
5650 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
} },
5653 /* PREFIX_VEX_0F3892 */
5657 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
} },
5660 /* PREFIX_VEX_0F3893 */
5664 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
} },
5667 /* PREFIX_VEX_0F3896 */
5671 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
} },
5674 /* PREFIX_VEX_0F3897 */
5678 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
} },
5681 /* PREFIX_VEX_0F3898 */
5685 { "vfmadd132p%XW", { XM
, Vex
, EXx
} },
5688 /* PREFIX_VEX_0F3899 */
5692 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5695 /* PREFIX_VEX_0F389A */
5699 { "vfmsub132p%XW", { XM
, Vex
, EXx
} },
5702 /* PREFIX_VEX_0F389B */
5706 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5709 /* PREFIX_VEX_0F389C */
5713 { "vfnmadd132p%XW", { XM
, Vex
, EXx
} },
5716 /* PREFIX_VEX_0F389D */
5720 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5723 /* PREFIX_VEX_0F389E */
5727 { "vfnmsub132p%XW", { XM
, Vex
, EXx
} },
5730 /* PREFIX_VEX_0F389F */
5734 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5737 /* PREFIX_VEX_0F38A6 */
5741 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
} },
5745 /* PREFIX_VEX_0F38A7 */
5749 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
} },
5752 /* PREFIX_VEX_0F38A8 */
5756 { "vfmadd213p%XW", { XM
, Vex
, EXx
} },
5759 /* PREFIX_VEX_0F38A9 */
5763 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5766 /* PREFIX_VEX_0F38AA */
5770 { "vfmsub213p%XW", { XM
, Vex
, EXx
} },
5773 /* PREFIX_VEX_0F38AB */
5777 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5780 /* PREFIX_VEX_0F38AC */
5784 { "vfnmadd213p%XW", { XM
, Vex
, EXx
} },
5787 /* PREFIX_VEX_0F38AD */
5791 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5794 /* PREFIX_VEX_0F38AE */
5798 { "vfnmsub213p%XW", { XM
, Vex
, EXx
} },
5801 /* PREFIX_VEX_0F38AF */
5805 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5808 /* PREFIX_VEX_0F38B6 */
5812 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
} },
5815 /* PREFIX_VEX_0F38B7 */
5819 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
} },
5822 /* PREFIX_VEX_0F38B8 */
5826 { "vfmadd231p%XW", { XM
, Vex
, EXx
} },
5829 /* PREFIX_VEX_0F38B9 */
5833 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5836 /* PREFIX_VEX_0F38BA */
5840 { "vfmsub231p%XW", { XM
, Vex
, EXx
} },
5843 /* PREFIX_VEX_0F38BB */
5847 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5850 /* PREFIX_VEX_0F38BC */
5854 { "vfnmadd231p%XW", { XM
, Vex
, EXx
} },
5857 /* PREFIX_VEX_0F38BD */
5861 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5864 /* PREFIX_VEX_0F38BE */
5868 { "vfnmsub231p%XW", { XM
, Vex
, EXx
} },
5871 /* PREFIX_VEX_0F38BF */
5875 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5878 /* PREFIX_VEX_0F38DB */
5882 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
5885 /* PREFIX_VEX_0F38DC */
5889 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
5892 /* PREFIX_VEX_0F38DD */
5896 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
5899 /* PREFIX_VEX_0F38DE */
5903 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
5906 /* PREFIX_VEX_0F38DF */
5910 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
5913 /* PREFIX_VEX_0F38F2 */
5915 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
5918 /* PREFIX_VEX_0F38F3_REG_1 */
5920 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
5923 /* PREFIX_VEX_0F38F3_REG_2 */
5925 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
5928 /* PREFIX_VEX_0F38F3_REG_3 */
5930 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
5933 /* PREFIX_VEX_0F38F5 */
5935 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
5936 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
5938 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
5941 /* PREFIX_VEX_0F38F6 */
5946 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
5949 /* PREFIX_VEX_0F38F7 */
5951 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
5952 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
5953 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
5954 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
5957 /* PREFIX_VEX_0F3A00 */
5961 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
5964 /* PREFIX_VEX_0F3A01 */
5968 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
5971 /* PREFIX_VEX_0F3A02 */
5975 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
5978 /* PREFIX_VEX_0F3A04 */
5982 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
5985 /* PREFIX_VEX_0F3A05 */
5989 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
5992 /* PREFIX_VEX_0F3A06 */
5996 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
5999 /* PREFIX_VEX_0F3A08 */
6003 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6006 /* PREFIX_VEX_0F3A09 */
6010 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6013 /* PREFIX_VEX_0F3A0A */
6017 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6020 /* PREFIX_VEX_0F3A0B */
6024 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6027 /* PREFIX_VEX_0F3A0C */
6031 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6034 /* PREFIX_VEX_0F3A0D */
6038 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6041 /* PREFIX_VEX_0F3A0E */
6045 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6048 /* PREFIX_VEX_0F3A0F */
6052 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6055 /* PREFIX_VEX_0F3A14 */
6059 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6062 /* PREFIX_VEX_0F3A15 */
6066 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6069 /* PREFIX_VEX_0F3A16 */
6073 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6076 /* PREFIX_VEX_0F3A17 */
6080 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6083 /* PREFIX_VEX_0F3A18 */
6087 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6090 /* PREFIX_VEX_0F3A19 */
6094 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6097 /* PREFIX_VEX_0F3A1D */
6101 { "vcvtps2ph", { EXxmmq
, XM
, Ib
} },
6104 /* PREFIX_VEX_0F3A20 */
6108 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6111 /* PREFIX_VEX_0F3A21 */
6115 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6118 /* PREFIX_VEX_0F3A22 */
6122 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6125 /* PREFIX_VEX_0F3A30 */
6129 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6132 /* PREFIX_VEX_0F3A32 */
6136 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6139 /* PREFIX_VEX_0F3A38 */
6143 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6146 /* PREFIX_VEX_0F3A39 */
6150 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6153 /* PREFIX_VEX_0F3A40 */
6157 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6160 /* PREFIX_VEX_0F3A41 */
6164 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6167 /* PREFIX_VEX_0F3A42 */
6171 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6174 /* PREFIX_VEX_0F3A44 */
6178 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6181 /* PREFIX_VEX_0F3A46 */
6185 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6188 /* PREFIX_VEX_0F3A48 */
6192 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6195 /* PREFIX_VEX_0F3A49 */
6199 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6202 /* PREFIX_VEX_0F3A4A */
6206 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6209 /* PREFIX_VEX_0F3A4B */
6213 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6216 /* PREFIX_VEX_0F3A4C */
6220 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6223 /* PREFIX_VEX_0F3A5C */
6227 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6230 /* PREFIX_VEX_0F3A5D */
6234 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6237 /* PREFIX_VEX_0F3A5E */
6241 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6244 /* PREFIX_VEX_0F3A5F */
6248 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6251 /* PREFIX_VEX_0F3A60 */
6255 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6259 /* PREFIX_VEX_0F3A61 */
6263 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6266 /* PREFIX_VEX_0F3A62 */
6270 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6273 /* PREFIX_VEX_0F3A63 */
6277 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6280 /* PREFIX_VEX_0F3A68 */
6284 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6287 /* PREFIX_VEX_0F3A69 */
6291 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6294 /* PREFIX_VEX_0F3A6A */
6298 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6301 /* PREFIX_VEX_0F3A6B */
6305 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6308 /* PREFIX_VEX_0F3A6C */
6312 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6315 /* PREFIX_VEX_0F3A6D */
6319 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6322 /* PREFIX_VEX_0F3A6E */
6326 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6329 /* PREFIX_VEX_0F3A6F */
6333 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6336 /* PREFIX_VEX_0F3A78 */
6340 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6343 /* PREFIX_VEX_0F3A79 */
6347 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6350 /* PREFIX_VEX_0F3A7A */
6354 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6357 /* PREFIX_VEX_0F3A7B */
6361 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6364 /* PREFIX_VEX_0F3A7C */
6368 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6372 /* PREFIX_VEX_0F3A7D */
6376 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6379 /* PREFIX_VEX_0F3A7E */
6383 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6386 /* PREFIX_VEX_0F3A7F */
6390 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6393 /* PREFIX_VEX_0F3ADF */
6397 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6400 /* PREFIX_VEX_0F3AF0 */
6405 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6408 #define NEED_PREFIX_TABLE
6409 #include "i386-dis-evex.h"
6410 #undef NEED_PREFIX_TABLE
6413 static const struct dis386 x86_64_table
[][2] = {
6416 { "pushP", { es
} },
6426 { "pushP", { cs
} },
6431 { "pushP", { ss
} },
6441 { "pushP", { ds
} },
6471 { "pushaP", { XX
} },
6476 { "popaP", { XX
} },
6481 { MOD_TABLE (MOD_62_32BIT
) },
6482 { EVEX_TABLE (EVEX_0F
) },
6487 { "arpl", { Ew
, Gw
} },
6488 { "movs{lq|xd}", { Gv
, Ed
} },
6493 { "ins{R|}", { Yzr
, indirDX
} },
6494 { "ins{G|}", { Yzr
, indirDX
} },
6499 { "outs{R|}", { indirDXr
, Xz
} },
6500 { "outs{G|}", { indirDXr
, Xz
} },
6505 { "Jcall{T|}", { Ap
} },
6510 { MOD_TABLE (MOD_C4_32BIT
) },
6511 { VEX_C4_TABLE (VEX_0F
) },
6516 { MOD_TABLE (MOD_C5_32BIT
) },
6517 { VEX_C5_TABLE (VEX_0F
) },
6537 { "Jjmp{T|}", { Ap
} },
6540 /* X86_64_0F01_REG_0 */
6542 { "sgdt{Q|IQ}", { M
} },
6546 /* X86_64_0F01_REG_1 */
6548 { "sidt{Q|IQ}", { M
} },
6552 /* X86_64_0F01_REG_2 */
6554 { "lgdt{Q|Q}", { M
} },
6558 /* X86_64_0F01_REG_3 */
6560 { "lidt{Q|Q}", { M
} },
6565 static const struct dis386 three_byte_table
[][256] = {
6567 /* THREE_BYTE_0F38 */
6570 { "pshufb", { MX
, EM
} },
6571 { "phaddw", { MX
, EM
} },
6572 { "phaddd", { MX
, EM
} },
6573 { "phaddsw", { MX
, EM
} },
6574 { "pmaddubsw", { MX
, EM
} },
6575 { "phsubw", { MX
, EM
} },
6576 { "phsubd", { MX
, EM
} },
6577 { "phsubsw", { MX
, EM
} },
6579 { "psignb", { MX
, EM
} },
6580 { "psignw", { MX
, EM
} },
6581 { "psignd", { MX
, EM
} },
6582 { "pmulhrsw", { MX
, EM
} },
6588 { PREFIX_TABLE (PREFIX_0F3810
) },
6592 { PREFIX_TABLE (PREFIX_0F3814
) },
6593 { PREFIX_TABLE (PREFIX_0F3815
) },
6595 { PREFIX_TABLE (PREFIX_0F3817
) },
6601 { "pabsb", { MX
, EM
} },
6602 { "pabsw", { MX
, EM
} },
6603 { "pabsd", { MX
, EM
} },
6606 { PREFIX_TABLE (PREFIX_0F3820
) },
6607 { PREFIX_TABLE (PREFIX_0F3821
) },
6608 { PREFIX_TABLE (PREFIX_0F3822
) },
6609 { PREFIX_TABLE (PREFIX_0F3823
) },
6610 { PREFIX_TABLE (PREFIX_0F3824
) },
6611 { PREFIX_TABLE (PREFIX_0F3825
) },
6615 { PREFIX_TABLE (PREFIX_0F3828
) },
6616 { PREFIX_TABLE (PREFIX_0F3829
) },
6617 { PREFIX_TABLE (PREFIX_0F382A
) },
6618 { PREFIX_TABLE (PREFIX_0F382B
) },
6624 { PREFIX_TABLE (PREFIX_0F3830
) },
6625 { PREFIX_TABLE (PREFIX_0F3831
) },
6626 { PREFIX_TABLE (PREFIX_0F3832
) },
6627 { PREFIX_TABLE (PREFIX_0F3833
) },
6628 { PREFIX_TABLE (PREFIX_0F3834
) },
6629 { PREFIX_TABLE (PREFIX_0F3835
) },
6631 { PREFIX_TABLE (PREFIX_0F3837
) },
6633 { PREFIX_TABLE (PREFIX_0F3838
) },
6634 { PREFIX_TABLE (PREFIX_0F3839
) },
6635 { PREFIX_TABLE (PREFIX_0F383A
) },
6636 { PREFIX_TABLE (PREFIX_0F383B
) },
6637 { PREFIX_TABLE (PREFIX_0F383C
) },
6638 { PREFIX_TABLE (PREFIX_0F383D
) },
6639 { PREFIX_TABLE (PREFIX_0F383E
) },
6640 { PREFIX_TABLE (PREFIX_0F383F
) },
6642 { PREFIX_TABLE (PREFIX_0F3840
) },
6643 { PREFIX_TABLE (PREFIX_0F3841
) },
6714 { PREFIX_TABLE (PREFIX_0F3880
) },
6715 { PREFIX_TABLE (PREFIX_0F3881
) },
6716 { PREFIX_TABLE (PREFIX_0F3882
) },
6795 { PREFIX_TABLE (PREFIX_0F38C8
) },
6796 { PREFIX_TABLE (PREFIX_0F38C9
) },
6797 { PREFIX_TABLE (PREFIX_0F38CA
) },
6798 { PREFIX_TABLE (PREFIX_0F38CB
) },
6799 { PREFIX_TABLE (PREFIX_0F38CC
) },
6800 { PREFIX_TABLE (PREFIX_0F38CD
) },
6816 { PREFIX_TABLE (PREFIX_0F38DB
) },
6817 { PREFIX_TABLE (PREFIX_0F38DC
) },
6818 { PREFIX_TABLE (PREFIX_0F38DD
) },
6819 { PREFIX_TABLE (PREFIX_0F38DE
) },
6820 { PREFIX_TABLE (PREFIX_0F38DF
) },
6840 { PREFIX_TABLE (PREFIX_0F38F0
) },
6841 { PREFIX_TABLE (PREFIX_0F38F1
) },
6846 { PREFIX_TABLE (PREFIX_0F38F6
) },
6858 /* THREE_BYTE_0F3A */
6870 { PREFIX_TABLE (PREFIX_0F3A08
) },
6871 { PREFIX_TABLE (PREFIX_0F3A09
) },
6872 { PREFIX_TABLE (PREFIX_0F3A0A
) },
6873 { PREFIX_TABLE (PREFIX_0F3A0B
) },
6874 { PREFIX_TABLE (PREFIX_0F3A0C
) },
6875 { PREFIX_TABLE (PREFIX_0F3A0D
) },
6876 { PREFIX_TABLE (PREFIX_0F3A0E
) },
6877 { "palignr", { MX
, EM
, Ib
} },
6883 { PREFIX_TABLE (PREFIX_0F3A14
) },
6884 { PREFIX_TABLE (PREFIX_0F3A15
) },
6885 { PREFIX_TABLE (PREFIX_0F3A16
) },
6886 { PREFIX_TABLE (PREFIX_0F3A17
) },
6897 { PREFIX_TABLE (PREFIX_0F3A20
) },
6898 { PREFIX_TABLE (PREFIX_0F3A21
) },
6899 { PREFIX_TABLE (PREFIX_0F3A22
) },
6933 { PREFIX_TABLE (PREFIX_0F3A40
) },
6934 { PREFIX_TABLE (PREFIX_0F3A41
) },
6935 { PREFIX_TABLE (PREFIX_0F3A42
) },
6937 { PREFIX_TABLE (PREFIX_0F3A44
) },
6969 { PREFIX_TABLE (PREFIX_0F3A60
) },
6970 { PREFIX_TABLE (PREFIX_0F3A61
) },
6971 { PREFIX_TABLE (PREFIX_0F3A62
) },
6972 { PREFIX_TABLE (PREFIX_0F3A63
) },
7090 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7111 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7150 /* THREE_BYTE_0F7A */
7189 { "ptest", { XX
} },
7226 { "phaddbw", { XM
, EXq
} },
7227 { "phaddbd", { XM
, EXq
} },
7228 { "phaddbq", { XM
, EXq
} },
7231 { "phaddwd", { XM
, EXq
} },
7232 { "phaddwq", { XM
, EXq
} },
7237 { "phadddq", { XM
, EXq
} },
7244 { "phaddubw", { XM
, EXq
} },
7245 { "phaddubd", { XM
, EXq
} },
7246 { "phaddubq", { XM
, EXq
} },
7249 { "phadduwd", { XM
, EXq
} },
7250 { "phadduwq", { XM
, EXq
} },
7255 { "phaddudq", { XM
, EXq
} },
7262 { "phsubbw", { XM
, EXq
} },
7263 { "phsubbd", { XM
, EXq
} },
7264 { "phsubbq", { XM
, EXq
} },
7443 static const struct dis386 xop_table
[][256] = {
7596 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7597 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7598 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7606 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7607 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7614 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7615 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7616 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7624 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7625 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7629 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7630 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7633 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7651 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7663 { "vprotb", { XM
, Vex_2src_1
, Ib
} },
7664 { "vprotw", { XM
, Vex_2src_1
, Ib
} },
7665 { "vprotd", { XM
, Vex_2src_1
, Ib
} },
7666 { "vprotq", { XM
, Vex_2src_1
, Ib
} },
7676 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7677 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7678 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7679 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7712 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7713 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7714 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7715 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7739 { REG_TABLE (REG_XOP_TBM_01
) },
7740 { REG_TABLE (REG_XOP_TBM_02
) },
7758 { REG_TABLE (REG_XOP_LWPCB
) },
7882 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7883 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7884 { "vfrczss", { XM
, EXd
} },
7885 { "vfrczsd", { XM
, EXq
} },
7900 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
} },
7901 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
} },
7902 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
} },
7903 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
} },
7904 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
} },
7905 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
} },
7906 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
} },
7907 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
} },
7909 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
} },
7910 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
} },
7911 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
} },
7912 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
} },
7955 { "vphaddbw", { XM
, EXxmm
} },
7956 { "vphaddbd", { XM
, EXxmm
} },
7957 { "vphaddbq", { XM
, EXxmm
} },
7960 { "vphaddwd", { XM
, EXxmm
} },
7961 { "vphaddwq", { XM
, EXxmm
} },
7966 { "vphadddq", { XM
, EXxmm
} },
7973 { "vphaddubw", { XM
, EXxmm
} },
7974 { "vphaddubd", { XM
, EXxmm
} },
7975 { "vphaddubq", { XM
, EXxmm
} },
7978 { "vphadduwd", { XM
, EXxmm
} },
7979 { "vphadduwq", { XM
, EXxmm
} },
7984 { "vphaddudq", { XM
, EXxmm
} },
7991 { "vphsubbw", { XM
, EXxmm
} },
7992 { "vphsubwd", { XM
, EXxmm
} },
7993 { "vphsubdq", { XM
, EXxmm
} },
8047 { "bextr", { Gv
, Ev
, Iq
} },
8049 { REG_TABLE (REG_XOP_LWP
) },
8319 static const struct dis386 vex_table
[][256] = {
8341 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8342 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8343 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8344 { MOD_TABLE (MOD_VEX_0F13
) },
8345 { VEX_W_TABLE (VEX_W_0F14
) },
8346 { VEX_W_TABLE (VEX_W_0F15
) },
8347 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8348 { MOD_TABLE (MOD_VEX_0F17
) },
8368 { VEX_W_TABLE (VEX_W_0F28
) },
8369 { VEX_W_TABLE (VEX_W_0F29
) },
8370 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8371 { MOD_TABLE (MOD_VEX_0F2B
) },
8372 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8373 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8374 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8375 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8396 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8397 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8399 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8400 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8401 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8402 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8407 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8413 { MOD_TABLE (MOD_VEX_0F50
) },
8414 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8415 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8416 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8417 { "vandpX", { XM
, Vex
, EXx
} },
8418 { "vandnpX", { XM
, Vex
, EXx
} },
8419 { "vorpX", { XM
, Vex
, EXx
} },
8420 { "vxorpX", { XM
, Vex
, EXx
} },
8422 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8423 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8424 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8425 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8426 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8427 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8428 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8429 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8431 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8432 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8433 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8434 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8435 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8436 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8437 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8438 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8440 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8441 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8442 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8443 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8444 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8445 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8446 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8447 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8449 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8450 { REG_TABLE (REG_VEX_0F71
) },
8451 { REG_TABLE (REG_VEX_0F72
) },
8452 { REG_TABLE (REG_VEX_0F73
) },
8453 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8454 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8455 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8456 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8462 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8463 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8464 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8465 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8485 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8486 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8487 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8488 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8494 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8518 { REG_TABLE (REG_VEX_0FAE
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8543 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8545 { "vshufpX", { XM
, Vex
, EXx
, Ib
} },
8557 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8560 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8564 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8566 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8575 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8580 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8581 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8582 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8584 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8585 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8586 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8587 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8588 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8589 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8590 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8591 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8593 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8594 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8595 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8596 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8597 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8598 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8599 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8600 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8602 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8603 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8604 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8605 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8606 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8607 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8608 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8614 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8615 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8616 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8617 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8618 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8619 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8620 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8621 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8623 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8624 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8625 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8626 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8627 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8628 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8629 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8630 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8635 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8638 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8639 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8641 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8645 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8646 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8647 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8650 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8651 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8652 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8654 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8663 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8863 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8887 { REG_TABLE (REG_VEX_0F38F3
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
8981 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9195 #define NEED_OPCODE_TABLE
9196 #include "i386-dis-evex.h"
9197 #undef NEED_OPCODE_TABLE
9198 static const struct dis386 vex_len_table
[][2] = {
9199 /* VEX_LEN_0F10_P_1 */
9201 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9202 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9205 /* VEX_LEN_0F10_P_3 */
9207 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9208 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9211 /* VEX_LEN_0F11_P_1 */
9213 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9214 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9217 /* VEX_LEN_0F11_P_3 */
9219 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9220 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9223 /* VEX_LEN_0F12_P_0_M_0 */
9225 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9228 /* VEX_LEN_0F12_P_0_M_1 */
9230 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9233 /* VEX_LEN_0F12_P_2 */
9235 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9238 /* VEX_LEN_0F13_M_0 */
9240 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9243 /* VEX_LEN_0F16_P_0_M_0 */
9245 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9248 /* VEX_LEN_0F16_P_0_M_1 */
9250 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9253 /* VEX_LEN_0F16_P_2 */
9255 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9258 /* VEX_LEN_0F17_M_0 */
9260 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9263 /* VEX_LEN_0F2A_P_1 */
9265 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
9266 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
9269 /* VEX_LEN_0F2A_P_3 */
9271 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
9272 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
9275 /* VEX_LEN_0F2C_P_1 */
9277 { "vcvttss2siY", { Gv
, EXdScalar
} },
9278 { "vcvttss2siY", { Gv
, EXdScalar
} },
9281 /* VEX_LEN_0F2C_P_3 */
9283 { "vcvttsd2siY", { Gv
, EXqScalar
} },
9284 { "vcvttsd2siY", { Gv
, EXqScalar
} },
9287 /* VEX_LEN_0F2D_P_1 */
9289 { "vcvtss2siY", { Gv
, EXdScalar
} },
9290 { "vcvtss2siY", { Gv
, EXdScalar
} },
9293 /* VEX_LEN_0F2D_P_3 */
9295 { "vcvtsd2siY", { Gv
, EXqScalar
} },
9296 { "vcvtsd2siY", { Gv
, EXqScalar
} },
9299 /* VEX_LEN_0F2E_P_0 */
9301 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9302 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9305 /* VEX_LEN_0F2E_P_2 */
9307 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9308 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9311 /* VEX_LEN_0F2F_P_0 */
9313 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9314 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9317 /* VEX_LEN_0F2F_P_2 */
9319 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9320 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9323 /* VEX_LEN_0F41_P_0 */
9326 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9328 /* VEX_LEN_0F42_P_0 */
9331 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9333 /* VEX_LEN_0F44_P_0 */
9335 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9337 /* VEX_LEN_0F45_P_0 */
9340 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9342 /* VEX_LEN_0F46_P_0 */
9345 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9347 /* VEX_LEN_0F47_P_0 */
9350 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9352 /* VEX_LEN_0F4B_P_2 */
9355 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9358 /* VEX_LEN_0F51_P_1 */
9360 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9361 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9364 /* VEX_LEN_0F51_P_3 */
9366 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9367 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9370 /* VEX_LEN_0F52_P_1 */
9372 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9373 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9376 /* VEX_LEN_0F53_P_1 */
9378 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9379 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9382 /* VEX_LEN_0F58_P_1 */
9384 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9385 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9388 /* VEX_LEN_0F58_P_3 */
9390 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9391 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9394 /* VEX_LEN_0F59_P_1 */
9396 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9397 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9400 /* VEX_LEN_0F59_P_3 */
9402 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9403 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9406 /* VEX_LEN_0F5A_P_1 */
9408 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9409 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9412 /* VEX_LEN_0F5A_P_3 */
9414 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9415 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9418 /* VEX_LEN_0F5C_P_1 */
9420 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9421 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9424 /* VEX_LEN_0F5C_P_3 */
9426 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9427 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9430 /* VEX_LEN_0F5D_P_1 */
9432 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9433 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9436 /* VEX_LEN_0F5D_P_3 */
9438 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9439 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9442 /* VEX_LEN_0F5E_P_1 */
9444 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9445 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9448 /* VEX_LEN_0F5E_P_3 */
9450 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9451 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9454 /* VEX_LEN_0F5F_P_1 */
9456 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9457 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9460 /* VEX_LEN_0F5F_P_3 */
9462 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9463 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9466 /* VEX_LEN_0F6E_P_2 */
9468 { "vmovK", { XMScalar
, Edq
} },
9469 { "vmovK", { XMScalar
, Edq
} },
9472 /* VEX_LEN_0F7E_P_1 */
9474 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9475 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9478 /* VEX_LEN_0F7E_P_2 */
9480 { "vmovK", { Edq
, XMScalar
} },
9481 { "vmovK", { Edq
, XMScalar
} },
9484 /* VEX_LEN_0F90_P_0 */
9486 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9489 /* VEX_LEN_0F91_P_0 */
9491 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9494 /* VEX_LEN_0F92_P_0 */
9496 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9499 /* VEX_LEN_0F93_P_0 */
9501 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9504 /* VEX_LEN_0F98_P_0 */
9506 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9509 /* VEX_LEN_0FAE_R_2_M_0 */
9511 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9514 /* VEX_LEN_0FAE_R_3_M_0 */
9516 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9519 /* VEX_LEN_0FC2_P_1 */
9521 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9522 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9525 /* VEX_LEN_0FC2_P_3 */
9527 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9528 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9531 /* VEX_LEN_0FC4_P_2 */
9533 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9536 /* VEX_LEN_0FC5_P_2 */
9538 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9541 /* VEX_LEN_0FD6_P_2 */
9543 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9544 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9547 /* VEX_LEN_0FF7_P_2 */
9549 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9552 /* VEX_LEN_0F3816_P_2 */
9555 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9558 /* VEX_LEN_0F3819_P_2 */
9561 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9564 /* VEX_LEN_0F381A_P_2_M_0 */
9567 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9570 /* VEX_LEN_0F3836_P_2 */
9573 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9576 /* VEX_LEN_0F3841_P_2 */
9578 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9581 /* VEX_LEN_0F385A_P_2_M_0 */
9584 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9587 /* VEX_LEN_0F38DB_P_2 */
9589 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9592 /* VEX_LEN_0F38DC_P_2 */
9594 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
9597 /* VEX_LEN_0F38DD_P_2 */
9599 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
9602 /* VEX_LEN_0F38DE_P_2 */
9604 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
9607 /* VEX_LEN_0F38DF_P_2 */
9609 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
9612 /* VEX_LEN_0F38F2_P_0 */
9614 { "andnS", { Gdq
, VexGdq
, Edq
} },
9617 /* VEX_LEN_0F38F3_R_1_P_0 */
9619 { "blsrS", { VexGdq
, Edq
} },
9622 /* VEX_LEN_0F38F3_R_2_P_0 */
9624 { "blsmskS", { VexGdq
, Edq
} },
9627 /* VEX_LEN_0F38F3_R_3_P_0 */
9629 { "blsiS", { VexGdq
, Edq
} },
9632 /* VEX_LEN_0F38F5_P_0 */
9634 { "bzhiS", { Gdq
, Edq
, VexGdq
} },
9637 /* VEX_LEN_0F38F5_P_1 */
9639 { "pextS", { Gdq
, VexGdq
, Edq
} },
9642 /* VEX_LEN_0F38F5_P_3 */
9644 { "pdepS", { Gdq
, VexGdq
, Edq
} },
9647 /* VEX_LEN_0F38F6_P_3 */
9649 { "mulxS", { Gdq
, VexGdq
, Edq
} },
9652 /* VEX_LEN_0F38F7_P_0 */
9654 { "bextrS", { Gdq
, Edq
, VexGdq
} },
9657 /* VEX_LEN_0F38F7_P_1 */
9659 { "sarxS", { Gdq
, Edq
, VexGdq
} },
9662 /* VEX_LEN_0F38F7_P_2 */
9664 { "shlxS", { Gdq
, Edq
, VexGdq
} },
9667 /* VEX_LEN_0F38F7_P_3 */
9669 { "shrxS", { Gdq
, Edq
, VexGdq
} },
9672 /* VEX_LEN_0F3A00_P_2 */
9675 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9678 /* VEX_LEN_0F3A01_P_2 */
9681 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9684 /* VEX_LEN_0F3A06_P_2 */
9687 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9690 /* VEX_LEN_0F3A0A_P_2 */
9692 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9693 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9696 /* VEX_LEN_0F3A0B_P_2 */
9698 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9699 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9702 /* VEX_LEN_0F3A14_P_2 */
9704 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
9707 /* VEX_LEN_0F3A15_P_2 */
9709 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
9712 /* VEX_LEN_0F3A16_P_2 */
9714 { "vpextrK", { Edq
, XM
, Ib
} },
9717 /* VEX_LEN_0F3A17_P_2 */
9719 { "vextractps", { Edqd
, XM
, Ib
} },
9722 /* VEX_LEN_0F3A18_P_2 */
9725 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9728 /* VEX_LEN_0F3A19_P_2 */
9731 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9734 /* VEX_LEN_0F3A20_P_2 */
9736 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
9739 /* VEX_LEN_0F3A21_P_2 */
9741 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
9744 /* VEX_LEN_0F3A22_P_2 */
9746 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
} },
9749 /* VEX_LEN_0F3A30_P_2 */
9751 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9754 /* VEX_LEN_0F3A32_P_2 */
9756 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9759 /* VEX_LEN_0F3A38_P_2 */
9762 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9765 /* VEX_LEN_0F3A39_P_2 */
9768 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9771 /* VEX_LEN_0F3A41_P_2 */
9773 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
9776 /* VEX_LEN_0F3A44_P_2 */
9778 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
9781 /* VEX_LEN_0F3A46_P_2 */
9784 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9787 /* VEX_LEN_0F3A60_P_2 */
9789 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
9792 /* VEX_LEN_0F3A61_P_2 */
9794 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
9797 /* VEX_LEN_0F3A62_P_2 */
9799 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
9802 /* VEX_LEN_0F3A63_P_2 */
9804 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
9807 /* VEX_LEN_0F3A6A_P_2 */
9809 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9812 /* VEX_LEN_0F3A6B_P_2 */
9814 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9817 /* VEX_LEN_0F3A6E_P_2 */
9819 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9822 /* VEX_LEN_0F3A6F_P_2 */
9824 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9827 /* VEX_LEN_0F3A7A_P_2 */
9829 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9832 /* VEX_LEN_0F3A7B_P_2 */
9834 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9837 /* VEX_LEN_0F3A7E_P_2 */
9839 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9842 /* VEX_LEN_0F3A7F_P_2 */
9844 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9847 /* VEX_LEN_0F3ADF_P_2 */
9849 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
9852 /* VEX_LEN_0F3AF0_P_3 */
9854 { "rorxS", { Gdq
, Edq
, Ib
} },
9857 /* VEX_LEN_0FXOP_08_CC */
9859 { "vpcomb", { XM
, Vex128
, EXx
, Ib
} },
9862 /* VEX_LEN_0FXOP_08_CD */
9864 { "vpcomw", { XM
, Vex128
, EXx
, Ib
} },
9867 /* VEX_LEN_0FXOP_08_CE */
9869 { "vpcomd", { XM
, Vex128
, EXx
, Ib
} },
9872 /* VEX_LEN_0FXOP_08_CF */
9874 { "vpcomq", { XM
, Vex128
, EXx
, Ib
} },
9877 /* VEX_LEN_0FXOP_08_EC */
9879 { "vpcomub", { XM
, Vex128
, EXx
, Ib
} },
9882 /* VEX_LEN_0FXOP_08_ED */
9884 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
} },
9887 /* VEX_LEN_0FXOP_08_EE */
9889 { "vpcomud", { XM
, Vex128
, EXx
, Ib
} },
9892 /* VEX_LEN_0FXOP_08_EF */
9894 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
} },
9897 /* VEX_LEN_0FXOP_09_80 */
9899 { "vfrczps", { XM
, EXxmm
} },
9900 { "vfrczps", { XM
, EXymmq
} },
9903 /* VEX_LEN_0FXOP_09_81 */
9905 { "vfrczpd", { XM
, EXxmm
} },
9906 { "vfrczpd", { XM
, EXymmq
} },
9910 static const struct dis386 vex_w_table
[][2] = {
9912 /* VEX_W_0F10_P_0 */
9913 { "vmovups", { XM
, EXx
} },
9916 /* VEX_W_0F10_P_1 */
9917 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
} },
9920 /* VEX_W_0F10_P_2 */
9921 { "vmovupd", { XM
, EXx
} },
9924 /* VEX_W_0F10_P_3 */
9925 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
} },
9928 /* VEX_W_0F11_P_0 */
9929 { "vmovups", { EXxS
, XM
} },
9932 /* VEX_W_0F11_P_1 */
9933 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
} },
9936 /* VEX_W_0F11_P_2 */
9937 { "vmovupd", { EXxS
, XM
} },
9940 /* VEX_W_0F11_P_3 */
9941 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
} },
9944 /* VEX_W_0F12_P_0_M_0 */
9945 { "vmovlps", { XM
, Vex128
, EXq
} },
9948 /* VEX_W_0F12_P_0_M_1 */
9949 { "vmovhlps", { XM
, Vex128
, EXq
} },
9952 /* VEX_W_0F12_P_1 */
9953 { "vmovsldup", { XM
, EXx
} },
9956 /* VEX_W_0F12_P_2 */
9957 { "vmovlpd", { XM
, Vex128
, EXq
} },
9960 /* VEX_W_0F12_P_3 */
9961 { "vmovddup", { XM
, EXymmq
} },
9964 /* VEX_W_0F13_M_0 */
9965 { "vmovlpX", { EXq
, XM
} },
9969 { "vunpcklpX", { XM
, Vex
, EXx
} },
9973 { "vunpckhpX", { XM
, Vex
, EXx
} },
9976 /* VEX_W_0F16_P_0_M_0 */
9977 { "vmovhps", { XM
, Vex128
, EXq
} },
9980 /* VEX_W_0F16_P_0_M_1 */
9981 { "vmovlhps", { XM
, Vex128
, EXq
} },
9984 /* VEX_W_0F16_P_1 */
9985 { "vmovshdup", { XM
, EXx
} },
9988 /* VEX_W_0F16_P_2 */
9989 { "vmovhpd", { XM
, Vex128
, EXq
} },
9992 /* VEX_W_0F17_M_0 */
9993 { "vmovhpX", { EXq
, XM
} },
9997 { "vmovapX", { XM
, EXx
} },
10001 { "vmovapX", { EXxS
, XM
} },
10004 /* VEX_W_0F2B_M_0 */
10005 { "vmovntpX", { Mx
, XM
} },
10008 /* VEX_W_0F2E_P_0 */
10009 { "vucomiss", { XMScalar
, EXdScalar
} },
10012 /* VEX_W_0F2E_P_2 */
10013 { "vucomisd", { XMScalar
, EXqScalar
} },
10016 /* VEX_W_0F2F_P_0 */
10017 { "vcomiss", { XMScalar
, EXdScalar
} },
10020 /* VEX_W_0F2F_P_2 */
10021 { "vcomisd", { XMScalar
, EXqScalar
} },
10024 /* VEX_W_0F41_P_0_LEN_1 */
10025 { "kandw", { MaskG
, MaskVex
, MaskR
} },
10028 /* VEX_W_0F42_P_0_LEN_1 */
10029 { "kandnw", { MaskG
, MaskVex
, MaskR
} },
10032 /* VEX_W_0F44_P_0_LEN_0 */
10033 { "knotw", { MaskG
, MaskR
} },
10036 /* VEX_W_0F45_P_0_LEN_1 */
10037 { "korw", { MaskG
, MaskVex
, MaskR
} },
10040 /* VEX_W_0F46_P_0_LEN_1 */
10041 { "kxnorw", { MaskG
, MaskVex
, MaskR
} },
10044 /* VEX_W_0F47_P_0_LEN_1 */
10045 { "kxorw", { MaskG
, MaskVex
, MaskR
} },
10048 /* VEX_W_0F4B_P_2_LEN_1 */
10049 { "kunpckbw", { MaskG
, MaskVex
, MaskR
} },
10052 /* VEX_W_0F50_M_0 */
10053 { "vmovmskpX", { Gdq
, XS
} },
10056 /* VEX_W_0F51_P_0 */
10057 { "vsqrtps", { XM
, EXx
} },
10060 /* VEX_W_0F51_P_1 */
10061 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
10064 /* VEX_W_0F51_P_2 */
10065 { "vsqrtpd", { XM
, EXx
} },
10068 /* VEX_W_0F51_P_3 */
10069 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
} },
10072 /* VEX_W_0F52_P_0 */
10073 { "vrsqrtps", { XM
, EXx
} },
10076 /* VEX_W_0F52_P_1 */
10077 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
10080 /* VEX_W_0F53_P_0 */
10081 { "vrcpps", { XM
, EXx
} },
10084 /* VEX_W_0F53_P_1 */
10085 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
} },
10088 /* VEX_W_0F58_P_0 */
10089 { "vaddps", { XM
, Vex
, EXx
} },
10092 /* VEX_W_0F58_P_1 */
10093 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
} },
10096 /* VEX_W_0F58_P_2 */
10097 { "vaddpd", { XM
, Vex
, EXx
} },
10100 /* VEX_W_0F58_P_3 */
10101 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
} },
10104 /* VEX_W_0F59_P_0 */
10105 { "vmulps", { XM
, Vex
, EXx
} },
10108 /* VEX_W_0F59_P_1 */
10109 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
} },
10112 /* VEX_W_0F59_P_2 */
10113 { "vmulpd", { XM
, Vex
, EXx
} },
10116 /* VEX_W_0F59_P_3 */
10117 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
} },
10120 /* VEX_W_0F5A_P_0 */
10121 { "vcvtps2pd", { XM
, EXxmmq
} },
10124 /* VEX_W_0F5A_P_1 */
10125 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
} },
10128 /* VEX_W_0F5A_P_3 */
10129 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
} },
10132 /* VEX_W_0F5B_P_0 */
10133 { "vcvtdq2ps", { XM
, EXx
} },
10136 /* VEX_W_0F5B_P_1 */
10137 { "vcvttps2dq", { XM
, EXx
} },
10140 /* VEX_W_0F5B_P_2 */
10141 { "vcvtps2dq", { XM
, EXx
} },
10144 /* VEX_W_0F5C_P_0 */
10145 { "vsubps", { XM
, Vex
, EXx
} },
10148 /* VEX_W_0F5C_P_1 */
10149 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
} },
10152 /* VEX_W_0F5C_P_2 */
10153 { "vsubpd", { XM
, Vex
, EXx
} },
10156 /* VEX_W_0F5C_P_3 */
10157 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
} },
10160 /* VEX_W_0F5D_P_0 */
10161 { "vminps", { XM
, Vex
, EXx
} },
10164 /* VEX_W_0F5D_P_1 */
10165 { "vminss", { XMScalar
, VexScalar
, EXdScalar
} },
10168 /* VEX_W_0F5D_P_2 */
10169 { "vminpd", { XM
, Vex
, EXx
} },
10172 /* VEX_W_0F5D_P_3 */
10173 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
} },
10176 /* VEX_W_0F5E_P_0 */
10177 { "vdivps", { XM
, Vex
, EXx
} },
10180 /* VEX_W_0F5E_P_1 */
10181 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
} },
10184 /* VEX_W_0F5E_P_2 */
10185 { "vdivpd", { XM
, Vex
, EXx
} },
10188 /* VEX_W_0F5E_P_3 */
10189 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
} },
10192 /* VEX_W_0F5F_P_0 */
10193 { "vmaxps", { XM
, Vex
, EXx
} },
10196 /* VEX_W_0F5F_P_1 */
10197 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
} },
10200 /* VEX_W_0F5F_P_2 */
10201 { "vmaxpd", { XM
, Vex
, EXx
} },
10204 /* VEX_W_0F5F_P_3 */
10205 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
} },
10208 /* VEX_W_0F60_P_2 */
10209 { "vpunpcklbw", { XM
, Vex
, EXx
} },
10212 /* VEX_W_0F61_P_2 */
10213 { "vpunpcklwd", { XM
, Vex
, EXx
} },
10216 /* VEX_W_0F62_P_2 */
10217 { "vpunpckldq", { XM
, Vex
, EXx
} },
10220 /* VEX_W_0F63_P_2 */
10221 { "vpacksswb", { XM
, Vex
, EXx
} },
10224 /* VEX_W_0F64_P_2 */
10225 { "vpcmpgtb", { XM
, Vex
, EXx
} },
10228 /* VEX_W_0F65_P_2 */
10229 { "vpcmpgtw", { XM
, Vex
, EXx
} },
10232 /* VEX_W_0F66_P_2 */
10233 { "vpcmpgtd", { XM
, Vex
, EXx
} },
10236 /* VEX_W_0F67_P_2 */
10237 { "vpackuswb", { XM
, Vex
, EXx
} },
10240 /* VEX_W_0F68_P_2 */
10241 { "vpunpckhbw", { XM
, Vex
, EXx
} },
10244 /* VEX_W_0F69_P_2 */
10245 { "vpunpckhwd", { XM
, Vex
, EXx
} },
10248 /* VEX_W_0F6A_P_2 */
10249 { "vpunpckhdq", { XM
, Vex
, EXx
} },
10252 /* VEX_W_0F6B_P_2 */
10253 { "vpackssdw", { XM
, Vex
, EXx
} },
10256 /* VEX_W_0F6C_P_2 */
10257 { "vpunpcklqdq", { XM
, Vex
, EXx
} },
10260 /* VEX_W_0F6D_P_2 */
10261 { "vpunpckhqdq", { XM
, Vex
, EXx
} },
10264 /* VEX_W_0F6F_P_1 */
10265 { "vmovdqu", { XM
, EXx
} },
10268 /* VEX_W_0F6F_P_2 */
10269 { "vmovdqa", { XM
, EXx
} },
10272 /* VEX_W_0F70_P_1 */
10273 { "vpshufhw", { XM
, EXx
, Ib
} },
10276 /* VEX_W_0F70_P_2 */
10277 { "vpshufd", { XM
, EXx
, Ib
} },
10280 /* VEX_W_0F70_P_3 */
10281 { "vpshuflw", { XM
, EXx
, Ib
} },
10284 /* VEX_W_0F71_R_2_P_2 */
10285 { "vpsrlw", { Vex
, XS
, Ib
} },
10288 /* VEX_W_0F71_R_4_P_2 */
10289 { "vpsraw", { Vex
, XS
, Ib
} },
10292 /* VEX_W_0F71_R_6_P_2 */
10293 { "vpsllw", { Vex
, XS
, Ib
} },
10296 /* VEX_W_0F72_R_2_P_2 */
10297 { "vpsrld", { Vex
, XS
, Ib
} },
10300 /* VEX_W_0F72_R_4_P_2 */
10301 { "vpsrad", { Vex
, XS
, Ib
} },
10304 /* VEX_W_0F72_R_6_P_2 */
10305 { "vpslld", { Vex
, XS
, Ib
} },
10308 /* VEX_W_0F73_R_2_P_2 */
10309 { "vpsrlq", { Vex
, XS
, Ib
} },
10312 /* VEX_W_0F73_R_3_P_2 */
10313 { "vpsrldq", { Vex
, XS
, Ib
} },
10316 /* VEX_W_0F73_R_6_P_2 */
10317 { "vpsllq", { Vex
, XS
, Ib
} },
10320 /* VEX_W_0F73_R_7_P_2 */
10321 { "vpslldq", { Vex
, XS
, Ib
} },
10324 /* VEX_W_0F74_P_2 */
10325 { "vpcmpeqb", { XM
, Vex
, EXx
} },
10328 /* VEX_W_0F75_P_2 */
10329 { "vpcmpeqw", { XM
, Vex
, EXx
} },
10332 /* VEX_W_0F76_P_2 */
10333 { "vpcmpeqd", { XM
, Vex
, EXx
} },
10336 /* VEX_W_0F77_P_0 */
10340 /* VEX_W_0F7C_P_2 */
10341 { "vhaddpd", { XM
, Vex
, EXx
} },
10344 /* VEX_W_0F7C_P_3 */
10345 { "vhaddps", { XM
, Vex
, EXx
} },
10348 /* VEX_W_0F7D_P_2 */
10349 { "vhsubpd", { XM
, Vex
, EXx
} },
10352 /* VEX_W_0F7D_P_3 */
10353 { "vhsubps", { XM
, Vex
, EXx
} },
10356 /* VEX_W_0F7E_P_1 */
10357 { "vmovq", { XMScalar
, EXqScalar
} },
10360 /* VEX_W_0F7F_P_1 */
10361 { "vmovdqu", { EXxS
, XM
} },
10364 /* VEX_W_0F7F_P_2 */
10365 { "vmovdqa", { EXxS
, XM
} },
10368 /* VEX_W_0F90_P_0_LEN_0 */
10369 { "kmovw", { MaskG
, MaskE
} },
10372 /* VEX_W_0F91_P_0_LEN_0 */
10373 { "kmovw", { Ew
, MaskG
} },
10376 /* VEX_W_0F92_P_0_LEN_0 */
10377 { "kmovw", { MaskG
, Rdq
} },
10380 /* VEX_W_0F93_P_0_LEN_0 */
10381 { "kmovw", { Gdq
, MaskR
} },
10384 /* VEX_W_0F98_P_0_LEN_0 */
10385 { "kortestw", { MaskG
, MaskR
} },
10388 /* VEX_W_0FAE_R_2_M_0 */
10389 { "vldmxcsr", { Md
} },
10392 /* VEX_W_0FAE_R_3_M_0 */
10393 { "vstmxcsr", { Md
} },
10396 /* VEX_W_0FC2_P_0 */
10397 { "vcmpps", { XM
, Vex
, EXx
, VCMP
} },
10400 /* VEX_W_0FC2_P_1 */
10401 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
} },
10404 /* VEX_W_0FC2_P_2 */
10405 { "vcmppd", { XM
, Vex
, EXx
, VCMP
} },
10408 /* VEX_W_0FC2_P_3 */
10409 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
} },
10412 /* VEX_W_0FC4_P_2 */
10413 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
} },
10416 /* VEX_W_0FC5_P_2 */
10417 { "vpextrw", { Gdq
, XS
, Ib
} },
10420 /* VEX_W_0FD0_P_2 */
10421 { "vaddsubpd", { XM
, Vex
, EXx
} },
10424 /* VEX_W_0FD0_P_3 */
10425 { "vaddsubps", { XM
, Vex
, EXx
} },
10428 /* VEX_W_0FD1_P_2 */
10429 { "vpsrlw", { XM
, Vex
, EXxmm
} },
10432 /* VEX_W_0FD2_P_2 */
10433 { "vpsrld", { XM
, Vex
, EXxmm
} },
10436 /* VEX_W_0FD3_P_2 */
10437 { "vpsrlq", { XM
, Vex
, EXxmm
} },
10440 /* VEX_W_0FD4_P_2 */
10441 { "vpaddq", { XM
, Vex
, EXx
} },
10444 /* VEX_W_0FD5_P_2 */
10445 { "vpmullw", { XM
, Vex
, EXx
} },
10448 /* VEX_W_0FD6_P_2 */
10449 { "vmovq", { EXqScalarS
, XMScalar
} },
10452 /* VEX_W_0FD7_P_2_M_1 */
10453 { "vpmovmskb", { Gdq
, XS
} },
10456 /* VEX_W_0FD8_P_2 */
10457 { "vpsubusb", { XM
, Vex
, EXx
} },
10460 /* VEX_W_0FD9_P_2 */
10461 { "vpsubusw", { XM
, Vex
, EXx
} },
10464 /* VEX_W_0FDA_P_2 */
10465 { "vpminub", { XM
, Vex
, EXx
} },
10468 /* VEX_W_0FDB_P_2 */
10469 { "vpand", { XM
, Vex
, EXx
} },
10472 /* VEX_W_0FDC_P_2 */
10473 { "vpaddusb", { XM
, Vex
, EXx
} },
10476 /* VEX_W_0FDD_P_2 */
10477 { "vpaddusw", { XM
, Vex
, EXx
} },
10480 /* VEX_W_0FDE_P_2 */
10481 { "vpmaxub", { XM
, Vex
, EXx
} },
10484 /* VEX_W_0FDF_P_2 */
10485 { "vpandn", { XM
, Vex
, EXx
} },
10488 /* VEX_W_0FE0_P_2 */
10489 { "vpavgb", { XM
, Vex
, EXx
} },
10492 /* VEX_W_0FE1_P_2 */
10493 { "vpsraw", { XM
, Vex
, EXxmm
} },
10496 /* VEX_W_0FE2_P_2 */
10497 { "vpsrad", { XM
, Vex
, EXxmm
} },
10500 /* VEX_W_0FE3_P_2 */
10501 { "vpavgw", { XM
, Vex
, EXx
} },
10504 /* VEX_W_0FE4_P_2 */
10505 { "vpmulhuw", { XM
, Vex
, EXx
} },
10508 /* VEX_W_0FE5_P_2 */
10509 { "vpmulhw", { XM
, Vex
, EXx
} },
10512 /* VEX_W_0FE6_P_1 */
10513 { "vcvtdq2pd", { XM
, EXxmmq
} },
10516 /* VEX_W_0FE6_P_2 */
10517 { "vcvttpd2dq%XY", { XMM
, EXx
} },
10520 /* VEX_W_0FE6_P_3 */
10521 { "vcvtpd2dq%XY", { XMM
, EXx
} },
10524 /* VEX_W_0FE7_P_2_M_0 */
10525 { "vmovntdq", { Mx
, XM
} },
10528 /* VEX_W_0FE8_P_2 */
10529 { "vpsubsb", { XM
, Vex
, EXx
} },
10532 /* VEX_W_0FE9_P_2 */
10533 { "vpsubsw", { XM
, Vex
, EXx
} },
10536 /* VEX_W_0FEA_P_2 */
10537 { "vpminsw", { XM
, Vex
, EXx
} },
10540 /* VEX_W_0FEB_P_2 */
10541 { "vpor", { XM
, Vex
, EXx
} },
10544 /* VEX_W_0FEC_P_2 */
10545 { "vpaddsb", { XM
, Vex
, EXx
} },
10548 /* VEX_W_0FED_P_2 */
10549 { "vpaddsw", { XM
, Vex
, EXx
} },
10552 /* VEX_W_0FEE_P_2 */
10553 { "vpmaxsw", { XM
, Vex
, EXx
} },
10556 /* VEX_W_0FEF_P_2 */
10557 { "vpxor", { XM
, Vex
, EXx
} },
10560 /* VEX_W_0FF0_P_3_M_0 */
10561 { "vlddqu", { XM
, M
} },
10564 /* VEX_W_0FF1_P_2 */
10565 { "vpsllw", { XM
, Vex
, EXxmm
} },
10568 /* VEX_W_0FF2_P_2 */
10569 { "vpslld", { XM
, Vex
, EXxmm
} },
10572 /* VEX_W_0FF3_P_2 */
10573 { "vpsllq", { XM
, Vex
, EXxmm
} },
10576 /* VEX_W_0FF4_P_2 */
10577 { "vpmuludq", { XM
, Vex
, EXx
} },
10580 /* VEX_W_0FF5_P_2 */
10581 { "vpmaddwd", { XM
, Vex
, EXx
} },
10584 /* VEX_W_0FF6_P_2 */
10585 { "vpsadbw", { XM
, Vex
, EXx
} },
10588 /* VEX_W_0FF7_P_2 */
10589 { "vmaskmovdqu", { XM
, XS
} },
10592 /* VEX_W_0FF8_P_2 */
10593 { "vpsubb", { XM
, Vex
, EXx
} },
10596 /* VEX_W_0FF9_P_2 */
10597 { "vpsubw", { XM
, Vex
, EXx
} },
10600 /* VEX_W_0FFA_P_2 */
10601 { "vpsubd", { XM
, Vex
, EXx
} },
10604 /* VEX_W_0FFB_P_2 */
10605 { "vpsubq", { XM
, Vex
, EXx
} },
10608 /* VEX_W_0FFC_P_2 */
10609 { "vpaddb", { XM
, Vex
, EXx
} },
10612 /* VEX_W_0FFD_P_2 */
10613 { "vpaddw", { XM
, Vex
, EXx
} },
10616 /* VEX_W_0FFE_P_2 */
10617 { "vpaddd", { XM
, Vex
, EXx
} },
10620 /* VEX_W_0F3800_P_2 */
10621 { "vpshufb", { XM
, Vex
, EXx
} },
10624 /* VEX_W_0F3801_P_2 */
10625 { "vphaddw", { XM
, Vex
, EXx
} },
10628 /* VEX_W_0F3802_P_2 */
10629 { "vphaddd", { XM
, Vex
, EXx
} },
10632 /* VEX_W_0F3803_P_2 */
10633 { "vphaddsw", { XM
, Vex
, EXx
} },
10636 /* VEX_W_0F3804_P_2 */
10637 { "vpmaddubsw", { XM
, Vex
, EXx
} },
10640 /* VEX_W_0F3805_P_2 */
10641 { "vphsubw", { XM
, Vex
, EXx
} },
10644 /* VEX_W_0F3806_P_2 */
10645 { "vphsubd", { XM
, Vex
, EXx
} },
10648 /* VEX_W_0F3807_P_2 */
10649 { "vphsubsw", { XM
, Vex
, EXx
} },
10652 /* VEX_W_0F3808_P_2 */
10653 { "vpsignb", { XM
, Vex
, EXx
} },
10656 /* VEX_W_0F3809_P_2 */
10657 { "vpsignw", { XM
, Vex
, EXx
} },
10660 /* VEX_W_0F380A_P_2 */
10661 { "vpsignd", { XM
, Vex
, EXx
} },
10664 /* VEX_W_0F380B_P_2 */
10665 { "vpmulhrsw", { XM
, Vex
, EXx
} },
10668 /* VEX_W_0F380C_P_2 */
10669 { "vpermilps", { XM
, Vex
, EXx
} },
10672 /* VEX_W_0F380D_P_2 */
10673 { "vpermilpd", { XM
, Vex
, EXx
} },
10676 /* VEX_W_0F380E_P_2 */
10677 { "vtestps", { XM
, EXx
} },
10680 /* VEX_W_0F380F_P_2 */
10681 { "vtestpd", { XM
, EXx
} },
10684 /* VEX_W_0F3816_P_2 */
10685 { "vpermps", { XM
, Vex
, EXx
} },
10688 /* VEX_W_0F3817_P_2 */
10689 { "vptest", { XM
, EXx
} },
10692 /* VEX_W_0F3818_P_2 */
10693 { "vbroadcastss", { XM
, EXxmm_md
} },
10696 /* VEX_W_0F3819_P_2 */
10697 { "vbroadcastsd", { XM
, EXxmm_mq
} },
10700 /* VEX_W_0F381A_P_2_M_0 */
10701 { "vbroadcastf128", { XM
, Mxmm
} },
10704 /* VEX_W_0F381C_P_2 */
10705 { "vpabsb", { XM
, EXx
} },
10708 /* VEX_W_0F381D_P_2 */
10709 { "vpabsw", { XM
, EXx
} },
10712 /* VEX_W_0F381E_P_2 */
10713 { "vpabsd", { XM
, EXx
} },
10716 /* VEX_W_0F3820_P_2 */
10717 { "vpmovsxbw", { XM
, EXxmmq
} },
10720 /* VEX_W_0F3821_P_2 */
10721 { "vpmovsxbd", { XM
, EXxmmqd
} },
10724 /* VEX_W_0F3822_P_2 */
10725 { "vpmovsxbq", { XM
, EXxmmdw
} },
10728 /* VEX_W_0F3823_P_2 */
10729 { "vpmovsxwd", { XM
, EXxmmq
} },
10732 /* VEX_W_0F3824_P_2 */
10733 { "vpmovsxwq", { XM
, EXxmmqd
} },
10736 /* VEX_W_0F3825_P_2 */
10737 { "vpmovsxdq", { XM
, EXxmmq
} },
10740 /* VEX_W_0F3828_P_2 */
10741 { "vpmuldq", { XM
, Vex
, EXx
} },
10744 /* VEX_W_0F3829_P_2 */
10745 { "vpcmpeqq", { XM
, Vex
, EXx
} },
10748 /* VEX_W_0F382A_P_2_M_0 */
10749 { "vmovntdqa", { XM
, Mx
} },
10752 /* VEX_W_0F382B_P_2 */
10753 { "vpackusdw", { XM
, Vex
, EXx
} },
10756 /* VEX_W_0F382C_P_2_M_0 */
10757 { "vmaskmovps", { XM
, Vex
, Mx
} },
10760 /* VEX_W_0F382D_P_2_M_0 */
10761 { "vmaskmovpd", { XM
, Vex
, Mx
} },
10764 /* VEX_W_0F382E_P_2_M_0 */
10765 { "vmaskmovps", { Mx
, Vex
, XM
} },
10768 /* VEX_W_0F382F_P_2_M_0 */
10769 { "vmaskmovpd", { Mx
, Vex
, XM
} },
10772 /* VEX_W_0F3830_P_2 */
10773 { "vpmovzxbw", { XM
, EXxmmq
} },
10776 /* VEX_W_0F3831_P_2 */
10777 { "vpmovzxbd", { XM
, EXxmmqd
} },
10780 /* VEX_W_0F3832_P_2 */
10781 { "vpmovzxbq", { XM
, EXxmmdw
} },
10784 /* VEX_W_0F3833_P_2 */
10785 { "vpmovzxwd", { XM
, EXxmmq
} },
10788 /* VEX_W_0F3834_P_2 */
10789 { "vpmovzxwq", { XM
, EXxmmqd
} },
10792 /* VEX_W_0F3835_P_2 */
10793 { "vpmovzxdq", { XM
, EXxmmq
} },
10796 /* VEX_W_0F3836_P_2 */
10797 { "vpermd", { XM
, Vex
, EXx
} },
10800 /* VEX_W_0F3837_P_2 */
10801 { "vpcmpgtq", { XM
, Vex
, EXx
} },
10804 /* VEX_W_0F3838_P_2 */
10805 { "vpminsb", { XM
, Vex
, EXx
} },
10808 /* VEX_W_0F3839_P_2 */
10809 { "vpminsd", { XM
, Vex
, EXx
} },
10812 /* VEX_W_0F383A_P_2 */
10813 { "vpminuw", { XM
, Vex
, EXx
} },
10816 /* VEX_W_0F383B_P_2 */
10817 { "vpminud", { XM
, Vex
, EXx
} },
10820 /* VEX_W_0F383C_P_2 */
10821 { "vpmaxsb", { XM
, Vex
, EXx
} },
10824 /* VEX_W_0F383D_P_2 */
10825 { "vpmaxsd", { XM
, Vex
, EXx
} },
10828 /* VEX_W_0F383E_P_2 */
10829 { "vpmaxuw", { XM
, Vex
, EXx
} },
10832 /* VEX_W_0F383F_P_2 */
10833 { "vpmaxud", { XM
, Vex
, EXx
} },
10836 /* VEX_W_0F3840_P_2 */
10837 { "vpmulld", { XM
, Vex
, EXx
} },
10840 /* VEX_W_0F3841_P_2 */
10841 { "vphminposuw", { XM
, EXx
} },
10844 /* VEX_W_0F3846_P_2 */
10845 { "vpsravd", { XM
, Vex
, EXx
} },
10848 /* VEX_W_0F3858_P_2 */
10849 { "vpbroadcastd", { XM
, EXxmm_md
} },
10852 /* VEX_W_0F3859_P_2 */
10853 { "vpbroadcastq", { XM
, EXxmm_mq
} },
10856 /* VEX_W_0F385A_P_2_M_0 */
10857 { "vbroadcasti128", { XM
, Mxmm
} },
10860 /* VEX_W_0F3878_P_2 */
10861 { "vpbroadcastb", { XM
, EXxmm_mb
} },
10864 /* VEX_W_0F3879_P_2 */
10865 { "vpbroadcastw", { XM
, EXxmm_mw
} },
10868 /* VEX_W_0F38DB_P_2 */
10869 { "vaesimc", { XM
, EXx
} },
10872 /* VEX_W_0F38DC_P_2 */
10873 { "vaesenc", { XM
, Vex128
, EXx
} },
10876 /* VEX_W_0F38DD_P_2 */
10877 { "vaesenclast", { XM
, Vex128
, EXx
} },
10880 /* VEX_W_0F38DE_P_2 */
10881 { "vaesdec", { XM
, Vex128
, EXx
} },
10884 /* VEX_W_0F38DF_P_2 */
10885 { "vaesdeclast", { XM
, Vex128
, EXx
} },
10888 /* VEX_W_0F3A00_P_2 */
10890 { "vpermq", { XM
, EXx
, Ib
} },
10893 /* VEX_W_0F3A01_P_2 */
10895 { "vpermpd", { XM
, EXx
, Ib
} },
10898 /* VEX_W_0F3A02_P_2 */
10899 { "vpblendd", { XM
, Vex
, EXx
, Ib
} },
10902 /* VEX_W_0F3A04_P_2 */
10903 { "vpermilps", { XM
, EXx
, Ib
} },
10906 /* VEX_W_0F3A05_P_2 */
10907 { "vpermilpd", { XM
, EXx
, Ib
} },
10910 /* VEX_W_0F3A06_P_2 */
10911 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
} },
10914 /* VEX_W_0F3A08_P_2 */
10915 { "vroundps", { XM
, EXx
, Ib
} },
10918 /* VEX_W_0F3A09_P_2 */
10919 { "vroundpd", { XM
, EXx
, Ib
} },
10922 /* VEX_W_0F3A0A_P_2 */
10923 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
} },
10926 /* VEX_W_0F3A0B_P_2 */
10927 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
} },
10930 /* VEX_W_0F3A0C_P_2 */
10931 { "vblendps", { XM
, Vex
, EXx
, Ib
} },
10934 /* VEX_W_0F3A0D_P_2 */
10935 { "vblendpd", { XM
, Vex
, EXx
, Ib
} },
10938 /* VEX_W_0F3A0E_P_2 */
10939 { "vpblendw", { XM
, Vex
, EXx
, Ib
} },
10942 /* VEX_W_0F3A0F_P_2 */
10943 { "vpalignr", { XM
, Vex
, EXx
, Ib
} },
10946 /* VEX_W_0F3A14_P_2 */
10947 { "vpextrb", { Edqb
, XM
, Ib
} },
10950 /* VEX_W_0F3A15_P_2 */
10951 { "vpextrw", { Edqw
, XM
, Ib
} },
10954 /* VEX_W_0F3A18_P_2 */
10955 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
} },
10958 /* VEX_W_0F3A19_P_2 */
10959 { "vextractf128", { EXxmm
, XM
, Ib
} },
10962 /* VEX_W_0F3A20_P_2 */
10963 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
} },
10966 /* VEX_W_0F3A21_P_2 */
10967 { "vinsertps", { XM
, Vex128
, EXd
, Ib
} },
10970 /* VEX_W_0F3A30_P_2 */
10972 { "kshiftrw", { MaskG
, MaskR
, Ib
} },
10975 /* VEX_W_0F3A32_P_2 */
10977 { "kshiftlw", { MaskG
, MaskR
, Ib
} },
10980 /* VEX_W_0F3A38_P_2 */
10981 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
} },
10984 /* VEX_W_0F3A39_P_2 */
10985 { "vextracti128", { EXxmm
, XM
, Ib
} },
10988 /* VEX_W_0F3A40_P_2 */
10989 { "vdpps", { XM
, Vex
, EXx
, Ib
} },
10992 /* VEX_W_0F3A41_P_2 */
10993 { "vdppd", { XM
, Vex128
, EXx
, Ib
} },
10996 /* VEX_W_0F3A42_P_2 */
10997 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
} },
11000 /* VEX_W_0F3A44_P_2 */
11001 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
} },
11004 /* VEX_W_0F3A46_P_2 */
11005 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
} },
11008 /* VEX_W_0F3A48_P_2 */
11009 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11010 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11013 /* VEX_W_0F3A49_P_2 */
11014 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11015 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11018 /* VEX_W_0F3A4A_P_2 */
11019 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
} },
11022 /* VEX_W_0F3A4B_P_2 */
11023 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
} },
11026 /* VEX_W_0F3A4C_P_2 */
11027 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
} },
11030 /* VEX_W_0F3A60_P_2 */
11031 { "vpcmpestrm", { XM
, EXx
, Ib
} },
11034 /* VEX_W_0F3A61_P_2 */
11035 { "vpcmpestri", { XM
, EXx
, Ib
} },
11038 /* VEX_W_0F3A62_P_2 */
11039 { "vpcmpistrm", { XM
, EXx
, Ib
} },
11042 /* VEX_W_0F3A63_P_2 */
11043 { "vpcmpistri", { XM
, EXx
, Ib
} },
11046 /* VEX_W_0F3ADF_P_2 */
11047 { "vaeskeygenassist", { XM
, EXx
, Ib
} },
11049 #define NEED_VEX_W_TABLE
11050 #include "i386-dis-evex.h"
11051 #undef NEED_VEX_W_TABLE
11054 static const struct dis386 mod_table
[][2] = {
11057 { "leaS", { Gv
, M
} },
11062 { RM_TABLE (RM_C6_REG_7
) },
11067 { RM_TABLE (RM_C7_REG_7
) },
11071 { "Jcall{T|}", { indirEp
} },
11075 { "Jjmp{T|}", { indirEp
} },
11078 /* MOD_0F01_REG_0 */
11079 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11080 { RM_TABLE (RM_0F01_REG_0
) },
11083 /* MOD_0F01_REG_1 */
11084 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11085 { RM_TABLE (RM_0F01_REG_1
) },
11088 /* MOD_0F01_REG_2 */
11089 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11090 { RM_TABLE (RM_0F01_REG_2
) },
11093 /* MOD_0F01_REG_3 */
11094 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11095 { RM_TABLE (RM_0F01_REG_3
) },
11098 /* MOD_0F01_REG_7 */
11099 { "invlpg", { Mb
} },
11100 { RM_TABLE (RM_0F01_REG_7
) },
11103 /* MOD_0F12_PREFIX_0 */
11104 { "movlps", { XM
, EXq
} },
11105 { "movhlps", { XM
, EXq
} },
11109 { "movlpX", { EXq
, XM
} },
11112 /* MOD_0F16_PREFIX_0 */
11113 { "movhps", { XM
, EXq
} },
11114 { "movlhps", { XM
, EXq
} },
11118 { "movhpX", { EXq
, XM
} },
11121 /* MOD_0F18_REG_0 */
11122 { "prefetchnta", { Mb
} },
11125 /* MOD_0F18_REG_1 */
11126 { "prefetcht0", { Mb
} },
11129 /* MOD_0F18_REG_2 */
11130 { "prefetcht1", { Mb
} },
11133 /* MOD_0F18_REG_3 */
11134 { "prefetcht2", { Mb
} },
11137 /* MOD_0F18_REG_4 */
11138 { "nop/reserved", { Mb
} },
11141 /* MOD_0F18_REG_5 */
11142 { "nop/reserved", { Mb
} },
11145 /* MOD_0F18_REG_6 */
11146 { "nop/reserved", { Mb
} },
11149 /* MOD_0F18_REG_7 */
11150 { "nop/reserved", { Mb
} },
11153 /* MOD_0F1A_PREFIX_0 */
11154 { "bndldx", { Gbnd
, Ev_bnd
} },
11155 { "nopQ", { Ev
} },
11158 /* MOD_0F1B_PREFIX_0 */
11159 { "bndstx", { Ev_bnd
, Gbnd
} },
11160 { "nopQ", { Ev
} },
11163 /* MOD_0F1B_PREFIX_1 */
11164 { "bndmk", { Gbnd
, Ev_bnd
} },
11165 { "nopQ", { Ev
} },
11170 { "movZ", { Rm
, Cm
} },
11175 { "movZ", { Rm
, Dm
} },
11180 { "movZ", { Cm
, Rm
} },
11185 { "movZ", { Dm
, Rm
} },
11190 { "movL", { Rd
, Td
} },
11195 { "movL", { Td
, Rd
} },
11198 /* MOD_0F2B_PREFIX_0 */
11199 {"movntps", { Mx
, XM
} },
11202 /* MOD_0F2B_PREFIX_1 */
11203 {"movntss", { Md
, XM
} },
11206 /* MOD_0F2B_PREFIX_2 */
11207 {"movntpd", { Mx
, XM
} },
11210 /* MOD_0F2B_PREFIX_3 */
11211 {"movntsd", { Mq
, XM
} },
11216 { "movmskpX", { Gdq
, XS
} },
11219 /* MOD_0F71_REG_2 */
11221 { "psrlw", { MS
, Ib
} },
11224 /* MOD_0F71_REG_4 */
11226 { "psraw", { MS
, Ib
} },
11229 /* MOD_0F71_REG_6 */
11231 { "psllw", { MS
, Ib
} },
11234 /* MOD_0F72_REG_2 */
11236 { "psrld", { MS
, Ib
} },
11239 /* MOD_0F72_REG_4 */
11241 { "psrad", { MS
, Ib
} },
11244 /* MOD_0F72_REG_6 */
11246 { "pslld", { MS
, Ib
} },
11249 /* MOD_0F73_REG_2 */
11251 { "psrlq", { MS
, Ib
} },
11254 /* MOD_0F73_REG_3 */
11256 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11259 /* MOD_0F73_REG_6 */
11261 { "psllq", { MS
, Ib
} },
11264 /* MOD_0F73_REG_7 */
11266 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11269 /* MOD_0FAE_REG_0 */
11270 { "fxsave", { FXSAVE
} },
11271 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11274 /* MOD_0FAE_REG_1 */
11275 { "fxrstor", { FXSAVE
} },
11276 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11279 /* MOD_0FAE_REG_2 */
11280 { "ldmxcsr", { Md
} },
11281 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11284 /* MOD_0FAE_REG_3 */
11285 { "stmxcsr", { Md
} },
11286 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11289 /* MOD_0FAE_REG_4 */
11290 { "xsave", { FXSAVE
} },
11293 /* MOD_0FAE_REG_5 */
11294 { "xrstor", { FXSAVE
} },
11295 { RM_TABLE (RM_0FAE_REG_5
) },
11298 /* MOD_0FAE_REG_6 */
11299 { "xsaveopt", { FXSAVE
} },
11300 { RM_TABLE (RM_0FAE_REG_6
) },
11303 /* MOD_0FAE_REG_7 */
11304 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11305 { RM_TABLE (RM_0FAE_REG_7
) },
11309 { "lssS", { Gv
, Mp
} },
11313 { "lfsS", { Gv
, Mp
} },
11317 { "lgsS", { Gv
, Mp
} },
11320 /* MOD_0FC7_REG_3 */
11321 { "xrstors", { FXSAVE
} },
11324 /* MOD_0FC7_REG_4 */
11325 { "xsavec", { FXSAVE
} },
11328 /* MOD_0FC7_REG_5 */
11329 { "xsaves", { FXSAVE
} },
11332 /* MOD_0FC7_REG_6 */
11333 { PREFIX_TABLE (PREFIX_0FC7_REG_6
) },
11334 { "rdrand", { Ev
} },
11337 /* MOD_0FC7_REG_7 */
11338 { "vmptrst", { Mq
} },
11339 { "rdseed", { Ev
} },
11344 { "pmovmskb", { Gdq
, MS
} },
11347 /* MOD_0FE7_PREFIX_2 */
11348 { "movntdq", { Mx
, XM
} },
11351 /* MOD_0FF0_PREFIX_3 */
11352 { "lddqu", { XM
, M
} },
11355 /* MOD_0F382A_PREFIX_2 */
11356 { "movntdqa", { XM
, Mx
} },
11360 { "bound{S|}", { Gv
, Ma
} },
11361 { EVEX_TABLE (EVEX_0F
) },
11365 { "lesS", { Gv
, Mp
} },
11366 { VEX_C4_TABLE (VEX_0F
) },
11370 { "ldsS", { Gv
, Mp
} },
11371 { VEX_C5_TABLE (VEX_0F
) },
11374 /* MOD_VEX_0F12_PREFIX_0 */
11375 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11376 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11380 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11383 /* MOD_VEX_0F16_PREFIX_0 */
11384 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11385 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11389 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11393 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11398 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
11401 /* MOD_VEX_0F71_REG_2 */
11403 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11406 /* MOD_VEX_0F71_REG_4 */
11408 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11411 /* MOD_VEX_0F71_REG_6 */
11413 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
11416 /* MOD_VEX_0F72_REG_2 */
11418 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
11421 /* MOD_VEX_0F72_REG_4 */
11423 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
11426 /* MOD_VEX_0F72_REG_6 */
11428 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
11431 /* MOD_VEX_0F73_REG_2 */
11433 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
11436 /* MOD_VEX_0F73_REG_3 */
11438 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
11441 /* MOD_VEX_0F73_REG_6 */
11443 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
11446 /* MOD_VEX_0F73_REG_7 */
11448 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
11451 /* MOD_VEX_0FAE_REG_2 */
11452 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
11455 /* MOD_VEX_0FAE_REG_3 */
11456 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
11459 /* MOD_VEX_0FD7_PREFIX_2 */
11461 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
11464 /* MOD_VEX_0FE7_PREFIX_2 */
11465 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
11468 /* MOD_VEX_0FF0_PREFIX_3 */
11469 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
11472 /* MOD_VEX_0F381A_PREFIX_2 */
11473 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
11476 /* MOD_VEX_0F382A_PREFIX_2 */
11477 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
11480 /* MOD_VEX_0F382C_PREFIX_2 */
11481 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
11484 /* MOD_VEX_0F382D_PREFIX_2 */
11485 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
11488 /* MOD_VEX_0F382E_PREFIX_2 */
11489 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
11492 /* MOD_VEX_0F382F_PREFIX_2 */
11493 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
11496 /* MOD_VEX_0F385A_PREFIX_2 */
11497 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
11500 /* MOD_VEX_0F388C_PREFIX_2 */
11501 { "vpmaskmov%LW", { XM
, Vex
, Mx
} },
11504 /* MOD_VEX_0F388E_PREFIX_2 */
11505 { "vpmaskmov%LW", { Mx
, Vex
, XM
} },
11507 #define NEED_MOD_TABLE
11508 #include "i386-dis-evex.h"
11509 #undef NEED_MOD_TABLE
11512 static const struct dis386 rm_table
[][8] = {
11515 { "xabort", { Skip_MODRM
, Ib
} },
11519 { "xbeginT", { Skip_MODRM
, Jv
} },
11522 /* RM_0F01_REG_0 */
11524 { "vmcall", { Skip_MODRM
} },
11525 { "vmlaunch", { Skip_MODRM
} },
11526 { "vmresume", { Skip_MODRM
} },
11527 { "vmxoff", { Skip_MODRM
} },
11530 /* RM_0F01_REG_1 */
11531 { "monitor", { { OP_Monitor
, 0 } } },
11532 { "mwait", { { OP_Mwait
, 0 } } },
11533 { "clac", { Skip_MODRM
} },
11534 { "stac", { Skip_MODRM
} },
11538 { "encls", { Skip_MODRM
} },
11541 /* RM_0F01_REG_2 */
11542 { "xgetbv", { Skip_MODRM
} },
11543 { "xsetbv", { Skip_MODRM
} },
11546 { "vmfunc", { Skip_MODRM
} },
11547 { "xend", { Skip_MODRM
} },
11548 { "xtest", { Skip_MODRM
} },
11549 { "enclu", { Skip_MODRM
} },
11552 /* RM_0F01_REG_3 */
11553 { "vmrun", { Skip_MODRM
} },
11554 { "vmmcall", { Skip_MODRM
} },
11555 { "vmload", { Skip_MODRM
} },
11556 { "vmsave", { Skip_MODRM
} },
11557 { "stgi", { Skip_MODRM
} },
11558 { "clgi", { Skip_MODRM
} },
11559 { "skinit", { Skip_MODRM
} },
11560 { "invlpga", { Skip_MODRM
} },
11563 /* RM_0F01_REG_7 */
11564 { "swapgs", { Skip_MODRM
} },
11565 { "rdtscp", { Skip_MODRM
} },
11568 /* RM_0FAE_REG_5 */
11569 { "lfence", { Skip_MODRM
} },
11572 /* RM_0FAE_REG_6 */
11573 { "mfence", { Skip_MODRM
} },
11576 /* RM_0FAE_REG_7 */
11577 { "sfence", { Skip_MODRM
} },
11581 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11583 /* We use the high bit to indicate different name for the same
11585 #define ADDR16_PREFIX (0x67 | 0x100)
11586 #define ADDR32_PREFIX (0x67 | 0x200)
11587 #define DATA16_PREFIX (0x66 | 0x100)
11588 #define DATA32_PREFIX (0x66 | 0x200)
11589 #define REP_PREFIX (0xf3 | 0x100)
11590 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11591 #define XRELEASE_PREFIX (0xf3 | 0x400)
11592 #define BND_PREFIX (0xf2 | 0x400)
11597 int newrex
, i
, length
;
11603 last_lock_prefix
= -1;
11604 last_repz_prefix
= -1;
11605 last_repnz_prefix
= -1;
11606 last_data_prefix
= -1;
11607 last_addr_prefix
= -1;
11608 last_rex_prefix
= -1;
11609 last_seg_prefix
= -1;
11610 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11611 all_prefixes
[i
] = 0;
11614 /* The maximum instruction length is 15bytes. */
11615 while (length
< MAX_CODE_LENGTH
- 1)
11617 FETCH_DATA (the_info
, codep
+ 1);
11621 /* REX prefixes family. */
11638 if (address_mode
== mode_64bit
)
11642 last_rex_prefix
= i
;
11645 prefixes
|= PREFIX_REPZ
;
11646 last_repz_prefix
= i
;
11649 prefixes
|= PREFIX_REPNZ
;
11650 last_repnz_prefix
= i
;
11653 prefixes
|= PREFIX_LOCK
;
11654 last_lock_prefix
= i
;
11657 prefixes
|= PREFIX_CS
;
11658 last_seg_prefix
= i
;
11661 prefixes
|= PREFIX_SS
;
11662 last_seg_prefix
= i
;
11665 prefixes
|= PREFIX_DS
;
11666 last_seg_prefix
= i
;
11669 prefixes
|= PREFIX_ES
;
11670 last_seg_prefix
= i
;
11673 prefixes
|= PREFIX_FS
;
11674 last_seg_prefix
= i
;
11677 prefixes
|= PREFIX_GS
;
11678 last_seg_prefix
= i
;
11681 prefixes
|= PREFIX_DATA
;
11682 last_data_prefix
= i
;
11685 prefixes
|= PREFIX_ADDR
;
11686 last_addr_prefix
= i
;
11689 /* fwait is really an instruction. If there are prefixes
11690 before the fwait, they belong to the fwait, *not* to the
11691 following instruction. */
11692 if (prefixes
|| rex
)
11694 prefixes
|= PREFIX_FWAIT
;
11696 /* This ensures that the previous REX prefixes are noticed
11697 as unused prefixes, as in the return case below. */
11701 prefixes
= PREFIX_FWAIT
;
11706 /* Rex is ignored when followed by another prefix. */
11712 if (*codep
!= FWAIT_OPCODE
)
11713 all_prefixes
[i
++] = *codep
;
11722 seg_prefix (int pref
)
11743 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11746 static const char *
11747 prefix_name (int pref
, int sizeflag
)
11749 static const char *rexes
[16] =
11752 "rex.B", /* 0x41 */
11753 "rex.X", /* 0x42 */
11754 "rex.XB", /* 0x43 */
11755 "rex.R", /* 0x44 */
11756 "rex.RB", /* 0x45 */
11757 "rex.RX", /* 0x46 */
11758 "rex.RXB", /* 0x47 */
11759 "rex.W", /* 0x48 */
11760 "rex.WB", /* 0x49 */
11761 "rex.WX", /* 0x4a */
11762 "rex.WXB", /* 0x4b */
11763 "rex.WR", /* 0x4c */
11764 "rex.WRB", /* 0x4d */
11765 "rex.WRX", /* 0x4e */
11766 "rex.WRXB", /* 0x4f */
11771 /* REX prefixes family. */
11788 return rexes
[pref
- 0x40];
11808 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11810 if (address_mode
== mode_64bit
)
11811 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11813 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11816 case ADDR16_PREFIX
:
11818 case ADDR32_PREFIX
:
11820 case DATA16_PREFIX
:
11822 case DATA32_PREFIX
:
11826 case XACQUIRE_PREFIX
:
11828 case XRELEASE_PREFIX
:
11837 static char op_out
[MAX_OPERANDS
][100];
11838 static int op_ad
, op_index
[MAX_OPERANDS
];
11839 static int two_source_ops
;
11840 static bfd_vma op_address
[MAX_OPERANDS
];
11841 static bfd_vma op_riprel
[MAX_OPERANDS
];
11842 static bfd_vma start_pc
;
11845 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11846 * (see topic "Redundant prefixes" in the "Differences from 8086"
11847 * section of the "Virtual 8086 Mode" chapter.)
11848 * 'pc' should be the address of this instruction, it will
11849 * be used to print the target address if this is a relative jump or call
11850 * The function returns the length of this instruction in bytes.
11853 static char intel_syntax
;
11854 static char intel_mnemonic
= !SYSV386_COMPAT
;
11855 static char open_char
;
11856 static char close_char
;
11857 static char separator_char
;
11858 static char scale_char
;
11860 /* Here for backwards compatibility. When gdb stops using
11861 print_insn_i386_att and print_insn_i386_intel these functions can
11862 disappear, and print_insn_i386 be merged into print_insn. */
11864 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11868 return print_insn (pc
, info
);
11872 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11876 return print_insn (pc
, info
);
11880 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11884 return print_insn (pc
, info
);
11888 print_i386_disassembler_options (FILE *stream
)
11890 fprintf (stream
, _("\n\
11891 The following i386/x86-64 specific disassembler options are supported for use\n\
11892 with the -M switch (multiple options should be separated by commas):\n"));
11894 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11895 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11896 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11897 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11898 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11899 fprintf (stream
, _(" att-mnemonic\n"
11900 " Display instruction in AT&T mnemonic\n"));
11901 fprintf (stream
, _(" intel-mnemonic\n"
11902 " Display instruction in Intel mnemonic\n"));
11903 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11904 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11905 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11906 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11907 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11908 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11912 static const struct dis386 bad_opcode
= { "(bad)", { XX
} };
11914 /* Get a pointer to struct dis386 with a valid name. */
11916 static const struct dis386
*
11917 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11919 int vindex
, vex_table_index
;
11921 if (dp
->name
!= NULL
)
11924 switch (dp
->op
[0].bytemode
)
11926 case USE_REG_TABLE
:
11927 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11930 case USE_MOD_TABLE
:
11931 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11932 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11936 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11939 case USE_PREFIX_TABLE
:
11942 /* The prefix in VEX is implicit. */
11943 switch (vex
.prefix
)
11948 case REPE_PREFIX_OPCODE
:
11951 case DATA_PREFIX_OPCODE
:
11954 case REPNE_PREFIX_OPCODE
:
11965 used_prefixes
|= (prefixes
& PREFIX_REPZ
);
11966 if (prefixes
& PREFIX_REPZ
)
11969 all_prefixes
[last_repz_prefix
] = 0;
11973 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11975 used_prefixes
|= (prefixes
& PREFIX_REPNZ
);
11976 if (prefixes
& PREFIX_REPNZ
)
11979 all_prefixes
[last_repnz_prefix
] = 0;
11983 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11984 if (prefixes
& PREFIX_DATA
)
11987 all_prefixes
[last_data_prefix
] = 0;
11992 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11995 case USE_X86_64_TABLE
:
11996 vindex
= address_mode
== mode_64bit
? 1 : 0;
11997 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12000 case USE_3BYTE_TABLE
:
12001 FETCH_DATA (info
, codep
+ 2);
12003 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12004 modrm
.mod
= (*codep
>> 6) & 3;
12005 modrm
.reg
= (*codep
>> 3) & 7;
12006 modrm
.rm
= *codep
& 7;
12009 case USE_VEX_LEN_TABLE
:
12013 switch (vex
.length
)
12026 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12029 case USE_XOP_8F_TABLE
:
12030 FETCH_DATA (info
, codep
+ 3);
12031 /* All bits in the REX prefix are ignored. */
12033 rex
= ~(*codep
>> 5) & 0x7;
12035 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12036 switch ((*codep
& 0x1f))
12042 vex_table_index
= XOP_08
;
12045 vex_table_index
= XOP_09
;
12048 vex_table_index
= XOP_0A
;
12052 vex
.w
= *codep
& 0x80;
12053 if (vex
.w
&& address_mode
== mode_64bit
)
12056 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12057 if (address_mode
!= mode_64bit
12058 && vex
.register_specifier
> 0x7)
12064 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12065 switch ((*codep
& 0x3))
12071 vex
.prefix
= DATA_PREFIX_OPCODE
;
12074 vex
.prefix
= REPE_PREFIX_OPCODE
;
12077 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12084 dp
= &xop_table
[vex_table_index
][vindex
];
12086 FETCH_DATA (info
, codep
+ 1);
12087 modrm
.mod
= (*codep
>> 6) & 3;
12088 modrm
.reg
= (*codep
>> 3) & 7;
12089 modrm
.rm
= *codep
& 7;
12092 case USE_VEX_C4_TABLE
:
12094 FETCH_DATA (info
, codep
+ 3);
12095 /* All bits in the REX prefix are ignored. */
12097 rex
= ~(*codep
>> 5) & 0x7;
12098 switch ((*codep
& 0x1f))
12104 vex_table_index
= VEX_0F
;
12107 vex_table_index
= VEX_0F38
;
12110 vex_table_index
= VEX_0F3A
;
12114 vex
.w
= *codep
& 0x80;
12115 if (vex
.w
&& address_mode
== mode_64bit
)
12118 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12119 if (address_mode
!= mode_64bit
12120 && vex
.register_specifier
> 0x7)
12126 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12127 switch ((*codep
& 0x3))
12133 vex
.prefix
= DATA_PREFIX_OPCODE
;
12136 vex
.prefix
= REPE_PREFIX_OPCODE
;
12139 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12146 dp
= &vex_table
[vex_table_index
][vindex
];
12147 /* There is no MODRM byte for VEX [82|77]. */
12148 if (vindex
!= 0x77 && vindex
!= 0x82)
12150 FETCH_DATA (info
, codep
+ 1);
12151 modrm
.mod
= (*codep
>> 6) & 3;
12152 modrm
.reg
= (*codep
>> 3) & 7;
12153 modrm
.rm
= *codep
& 7;
12157 case USE_VEX_C5_TABLE
:
12159 FETCH_DATA (info
, codep
+ 2);
12160 /* All bits in the REX prefix are ignored. */
12162 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12164 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12165 if (address_mode
!= mode_64bit
12166 && vex
.register_specifier
> 0x7)
12174 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12175 switch ((*codep
& 0x3))
12181 vex
.prefix
= DATA_PREFIX_OPCODE
;
12184 vex
.prefix
= REPE_PREFIX_OPCODE
;
12187 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12194 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12195 /* There is no MODRM byte for VEX [82|77]. */
12196 if (vindex
!= 0x77 && vindex
!= 0x82)
12198 FETCH_DATA (info
, codep
+ 1);
12199 modrm
.mod
= (*codep
>> 6) & 3;
12200 modrm
.reg
= (*codep
>> 3) & 7;
12201 modrm
.rm
= *codep
& 7;
12205 case USE_VEX_W_TABLE
:
12209 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12212 case USE_EVEX_TABLE
:
12213 two_source_ops
= 0;
12216 FETCH_DATA (info
, codep
+ 4);
12217 /* All bits in the REX prefix are ignored. */
12219 /* The first byte after 0x62. */
12220 rex
= ~(*codep
>> 5) & 0x7;
12221 vex
.r
= *codep
& 0x10;
12222 switch ((*codep
& 0xf))
12225 return &bad_opcode
;
12227 vex_table_index
= EVEX_0F
;
12230 vex_table_index
= EVEX_0F38
;
12233 vex_table_index
= EVEX_0F3A
;
12237 /* The second byte after 0x62. */
12239 vex
.w
= *codep
& 0x80;
12240 if (vex
.w
&& address_mode
== mode_64bit
)
12243 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12244 if (address_mode
!= mode_64bit
)
12246 /* In 16/32-bit mode silently ignore following bits. */
12250 vex
.register_specifier
&= 0x7;
12254 if (!(*codep
& 0x4))
12255 return &bad_opcode
;
12257 switch ((*codep
& 0x3))
12263 vex
.prefix
= DATA_PREFIX_OPCODE
;
12266 vex
.prefix
= REPE_PREFIX_OPCODE
;
12269 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12273 /* The third byte after 0x62. */
12276 /* Remember the static rounding bits. */
12277 vex
.ll
= (*codep
>> 5) & 3;
12278 vex
.b
= (*codep
& 0x10) != 0;
12280 vex
.v
= *codep
& 0x8;
12281 vex
.mask_register_specifier
= *codep
& 0x7;
12282 vex
.zeroing
= *codep
& 0x80;
12288 dp
= &evex_table
[vex_table_index
][vindex
];
12289 FETCH_DATA (info
, codep
+ 1);
12290 modrm
.mod
= (*codep
>> 6) & 3;
12291 modrm
.reg
= (*codep
>> 3) & 7;
12292 modrm
.rm
= *codep
& 7;
12294 /* Set vector length. */
12295 if (modrm
.mod
== 3 && vex
.b
)
12311 return &bad_opcode
;
12324 if (dp
->name
!= NULL
)
12327 return get_valid_dis386 (dp
, info
);
12331 get_sib (disassemble_info
*info
, int sizeflag
)
12333 /* If modrm.mod == 3, operand must be register. */
12335 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12339 FETCH_DATA (info
, codep
+ 2);
12340 sib
.index
= (codep
[1] >> 3) & 7;
12341 sib
.scale
= (codep
[1] >> 6) & 3;
12342 sib
.base
= codep
[1] & 7;
12347 print_insn (bfd_vma pc
, disassemble_info
*info
)
12349 const struct dis386
*dp
;
12351 char *op_txt
[MAX_OPERANDS
];
12355 struct dis_private priv
;
12357 int default_prefixes
;
12359 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12360 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
12361 address_mode
= mode_32bit
;
12362 else if (info
->mach
== bfd_mach_i386_i8086
)
12364 address_mode
= mode_16bit
;
12365 priv
.orig_sizeflag
= 0;
12368 address_mode
= mode_64bit
;
12370 if (intel_syntax
== (char) -1)
12371 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
12373 for (p
= info
->disassembler_options
; p
!= NULL
; )
12375 if (CONST_STRNEQ (p
, "x86-64"))
12377 address_mode
= mode_64bit
;
12378 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12380 else if (CONST_STRNEQ (p
, "i386"))
12382 address_mode
= mode_32bit
;
12383 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12385 else if (CONST_STRNEQ (p
, "i8086"))
12387 address_mode
= mode_16bit
;
12388 priv
.orig_sizeflag
= 0;
12390 else if (CONST_STRNEQ (p
, "intel"))
12393 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
12394 intel_mnemonic
= 1;
12396 else if (CONST_STRNEQ (p
, "att"))
12399 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
12400 intel_mnemonic
= 0;
12402 else if (CONST_STRNEQ (p
, "addr"))
12404 if (address_mode
== mode_64bit
)
12406 if (p
[4] == '3' && p
[5] == '2')
12407 priv
.orig_sizeflag
&= ~AFLAG
;
12408 else if (p
[4] == '6' && p
[5] == '4')
12409 priv
.orig_sizeflag
|= AFLAG
;
12413 if (p
[4] == '1' && p
[5] == '6')
12414 priv
.orig_sizeflag
&= ~AFLAG
;
12415 else if (p
[4] == '3' && p
[5] == '2')
12416 priv
.orig_sizeflag
|= AFLAG
;
12419 else if (CONST_STRNEQ (p
, "data"))
12421 if (p
[4] == '1' && p
[5] == '6')
12422 priv
.orig_sizeflag
&= ~DFLAG
;
12423 else if (p
[4] == '3' && p
[5] == '2')
12424 priv
.orig_sizeflag
|= DFLAG
;
12426 else if (CONST_STRNEQ (p
, "suffix"))
12427 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
12429 p
= strchr (p
, ',');
12436 names64
= intel_names64
;
12437 names32
= intel_names32
;
12438 names16
= intel_names16
;
12439 names8
= intel_names8
;
12440 names8rex
= intel_names8rex
;
12441 names_seg
= intel_names_seg
;
12442 names_mm
= intel_names_mm
;
12443 names_bnd
= intel_names_bnd
;
12444 names_xmm
= intel_names_xmm
;
12445 names_ymm
= intel_names_ymm
;
12446 names_zmm
= intel_names_zmm
;
12447 index64
= intel_index64
;
12448 index32
= intel_index32
;
12449 names_mask
= intel_names_mask
;
12450 index16
= intel_index16
;
12453 separator_char
= '+';
12458 names64
= att_names64
;
12459 names32
= att_names32
;
12460 names16
= att_names16
;
12461 names8
= att_names8
;
12462 names8rex
= att_names8rex
;
12463 names_seg
= att_names_seg
;
12464 names_mm
= att_names_mm
;
12465 names_bnd
= att_names_bnd
;
12466 names_xmm
= att_names_xmm
;
12467 names_ymm
= att_names_ymm
;
12468 names_zmm
= att_names_zmm
;
12469 index64
= att_index64
;
12470 index32
= att_index32
;
12471 names_mask
= att_names_mask
;
12472 index16
= att_index16
;
12475 separator_char
= ',';
12479 /* The output looks better if we put 7 bytes on a line, since that
12480 puts most long word instructions on a single line. Use 8 bytes
12482 if ((info
->mach
& bfd_mach_l1om
) != 0)
12483 info
->bytes_per_line
= 8;
12485 info
->bytes_per_line
= 7;
12487 info
->private_data
= &priv
;
12488 priv
.max_fetched
= priv
.the_buffer
;
12489 priv
.insn_start
= pc
;
12492 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12500 start_codep
= priv
.the_buffer
;
12501 codep
= priv
.the_buffer
;
12503 if (setjmp (priv
.bailout
) != 0)
12507 /* Getting here means we tried for data but didn't get it. That
12508 means we have an incomplete instruction of some sort. Just
12509 print the first byte as a prefix or a .byte pseudo-op. */
12510 if (codep
> priv
.the_buffer
)
12512 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12514 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12517 /* Just print the first byte as a .byte instruction. */
12518 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12519 (unsigned int) priv
.the_buffer
[0]);
12529 sizeflag
= priv
.orig_sizeflag
;
12531 if (!ckprefix () || rex_used
)
12533 /* Too many prefixes or unused REX prefixes. */
12535 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12537 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12539 prefix_name (all_prefixes
[i
], sizeflag
));
12543 insn_codep
= codep
;
12545 FETCH_DATA (info
, codep
+ 1);
12546 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12548 if (((prefixes
& PREFIX_FWAIT
)
12549 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12551 (*info
->fprintf_func
) (info
->stream
, "fwait");
12555 if (*codep
== 0x0f)
12557 unsigned char threebyte
;
12558 FETCH_DATA (info
, codep
+ 2);
12559 threebyte
= *++codep
;
12560 dp
= &dis386_twobyte
[threebyte
];
12561 need_modrm
= twobyte_has_modrm
[*codep
];
12566 dp
= &dis386
[*codep
];
12567 need_modrm
= onebyte_has_modrm
[*codep
];
12571 if ((prefixes
& PREFIX_REPZ
))
12572 used_prefixes
|= PREFIX_REPZ
;
12573 if ((prefixes
& PREFIX_REPNZ
))
12574 used_prefixes
|= PREFIX_REPNZ
;
12575 if ((prefixes
& PREFIX_LOCK
))
12576 used_prefixes
|= PREFIX_LOCK
;
12578 default_prefixes
= 0;
12579 if (prefixes
& PREFIX_ADDR
)
12582 if (dp
->op
[2].bytemode
!= loop_jcxz_mode
|| intel_syntax
)
12584 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12585 all_prefixes
[last_addr_prefix
] = ADDR32_PREFIX
;
12587 all_prefixes
[last_addr_prefix
] = ADDR16_PREFIX
;
12588 default_prefixes
|= PREFIX_ADDR
;
12592 if ((prefixes
& PREFIX_DATA
))
12595 if (dp
->op
[2].bytemode
== cond_jump_mode
12596 && dp
->op
[0].bytemode
== v_mode
12599 if (sizeflag
& DFLAG
)
12600 all_prefixes
[last_data_prefix
] = DATA32_PREFIX
;
12602 all_prefixes
[last_data_prefix
] = DATA16_PREFIX
;
12603 default_prefixes
|= PREFIX_DATA
;
12605 else if (rex
& REX_W
)
12607 /* REX_W will override PREFIX_DATA. */
12608 default_prefixes
|= PREFIX_DATA
;
12614 FETCH_DATA (info
, codep
+ 1);
12615 modrm
.mod
= (*codep
>> 6) & 3;
12616 modrm
.reg
= (*codep
>> 3) & 7;
12617 modrm
.rm
= *codep
& 7;
12625 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12627 get_sib (info
, sizeflag
);
12628 dofloat (sizeflag
);
12632 dp
= get_valid_dis386 (dp
, info
);
12633 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12635 get_sib (info
, sizeflag
);
12636 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12639 op_ad
= MAX_OPERANDS
- 1 - i
;
12641 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12642 /* For EVEX instruction after the last operand masking
12643 should be printed. */
12644 if (i
== 0 && vex
.evex
)
12646 /* Don't print {%k0}. */
12647 if (vex
.mask_register_specifier
)
12650 oappend (names_mask
[vex
.mask_register_specifier
]);
12660 /* See if any prefixes were not used. If so, print the first one
12661 separately. If we don't do this, we'll wind up printing an
12662 instruction stream which does not precisely correspond to the
12663 bytes we are disassembling. */
12664 if ((prefixes
& ~(used_prefixes
| default_prefixes
)) != 0)
12666 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12667 if (all_prefixes
[i
])
12670 name
= prefix_name (all_prefixes
[i
], priv
.orig_sizeflag
);
12672 name
= INTERNAL_DISASSEMBLER_ERROR
;
12673 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12678 /* Check if the REX prefix is used. */
12679 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12680 all_prefixes
[last_rex_prefix
] = 0;
12682 /* Check if the SEG prefix is used. */
12683 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12684 | PREFIX_FS
| PREFIX_GS
)) != 0
12686 & seg_prefix (all_prefixes
[last_seg_prefix
])) != 0)
12687 all_prefixes
[last_seg_prefix
] = 0;
12689 /* Check if the ADDR prefix is used. */
12690 if ((prefixes
& PREFIX_ADDR
) != 0
12691 && (used_prefixes
& PREFIX_ADDR
) != 0)
12692 all_prefixes
[last_addr_prefix
] = 0;
12694 /* Check if the DATA prefix is used. */
12695 if ((prefixes
& PREFIX_DATA
) != 0
12696 && (used_prefixes
& PREFIX_DATA
) != 0)
12697 all_prefixes
[last_data_prefix
] = 0;
12700 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12701 if (all_prefixes
[i
])
12704 name
= prefix_name (all_prefixes
[i
], sizeflag
);
12707 prefix_length
+= strlen (name
) + 1;
12708 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12711 /* Check maximum code length. */
12712 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12714 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12715 return MAX_CODE_LENGTH
;
12718 obufp
= mnemonicendp
;
12719 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12722 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12724 /* The enter and bound instructions are printed with operands in the same
12725 order as the intel book; everything else is printed in reverse order. */
12726 if (intel_syntax
|| two_source_ops
)
12730 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12731 op_txt
[i
] = op_out
[i
];
12733 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12735 op_ad
= op_index
[i
];
12736 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12737 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12738 riprel
= op_riprel
[i
];
12739 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12740 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12745 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12746 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12750 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12754 (*info
->fprintf_func
) (info
->stream
, ",");
12755 if (op_index
[i
] != -1 && !op_riprel
[i
])
12756 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
12758 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12762 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12763 if (op_index
[i
] != -1 && op_riprel
[i
])
12765 (*info
->fprintf_func
) (info
->stream
, " # ");
12766 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
12767 + op_address
[op_index
[i
]]), info
);
12770 return codep
- priv
.the_buffer
;
12773 static const char *float_mem
[] = {
12848 static const unsigned char float_mem_mode
[] = {
12923 #define ST { OP_ST, 0 }
12924 #define STi { OP_STi, 0 }
12926 #define FGRPd9_2 NULL, { { NULL, 0 } }
12927 #define FGRPd9_4 NULL, { { NULL, 1 } }
12928 #define FGRPd9_5 NULL, { { NULL, 2 } }
12929 #define FGRPd9_6 NULL, { { NULL, 3 } }
12930 #define FGRPd9_7 NULL, { { NULL, 4 } }
12931 #define FGRPda_5 NULL, { { NULL, 5 } }
12932 #define FGRPdb_4 NULL, { { NULL, 6 } }
12933 #define FGRPde_3 NULL, { { NULL, 7 } }
12934 #define FGRPdf_4 NULL, { { NULL, 8 } }
12936 static const struct dis386 float_reg
[][8] = {
12939 { "fadd", { ST
, STi
} },
12940 { "fmul", { ST
, STi
} },
12941 { "fcom", { STi
} },
12942 { "fcomp", { STi
} },
12943 { "fsub", { ST
, STi
} },
12944 { "fsubr", { ST
, STi
} },
12945 { "fdiv", { ST
, STi
} },
12946 { "fdivr", { ST
, STi
} },
12950 { "fld", { STi
} },
12951 { "fxch", { STi
} },
12961 { "fcmovb", { ST
, STi
} },
12962 { "fcmove", { ST
, STi
} },
12963 { "fcmovbe",{ ST
, STi
} },
12964 { "fcmovu", { ST
, STi
} },
12972 { "fcmovnb",{ ST
, STi
} },
12973 { "fcmovne",{ ST
, STi
} },
12974 { "fcmovnbe",{ ST
, STi
} },
12975 { "fcmovnu",{ ST
, STi
} },
12977 { "fucomi", { ST
, STi
} },
12978 { "fcomi", { ST
, STi
} },
12983 { "fadd", { STi
, ST
} },
12984 { "fmul", { STi
, ST
} },
12987 { "fsub!M", { STi
, ST
} },
12988 { "fsubM", { STi
, ST
} },
12989 { "fdiv!M", { STi
, ST
} },
12990 { "fdivM", { STi
, ST
} },
12994 { "ffree", { STi
} },
12996 { "fst", { STi
} },
12997 { "fstp", { STi
} },
12998 { "fucom", { STi
} },
12999 { "fucomp", { STi
} },
13005 { "faddp", { STi
, ST
} },
13006 { "fmulp", { STi
, ST
} },
13009 { "fsub!Mp", { STi
, ST
} },
13010 { "fsubMp", { STi
, ST
} },
13011 { "fdiv!Mp", { STi
, ST
} },
13012 { "fdivMp", { STi
, ST
} },
13016 { "ffreep", { STi
} },
13021 { "fucomip", { ST
, STi
} },
13022 { "fcomip", { ST
, STi
} },
13027 static char *fgrps
[][8] = {
13030 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13035 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13040 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13045 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13050 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13055 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13060 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13061 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13066 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13071 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13076 swap_operand (void)
13078 mnemonicendp
[0] = '.';
13079 mnemonicendp
[1] = 's';
13084 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13085 int sizeflag ATTRIBUTE_UNUSED
)
13087 /* Skip mod/rm byte. */
13093 dofloat (int sizeflag
)
13095 const struct dis386
*dp
;
13096 unsigned char floatop
;
13098 floatop
= codep
[-1];
13100 if (modrm
.mod
!= 3)
13102 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13104 putop (float_mem
[fp_indx
], sizeflag
);
13107 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13110 /* Skip mod/rm byte. */
13114 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13115 if (dp
->name
== NULL
)
13117 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13119 /* Instruction fnstsw is only one with strange arg. */
13120 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13121 strcpy (op_out
[0], names16
[0]);
13125 putop (dp
->name
, sizeflag
);
13130 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13135 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13139 /* Like oappend (below), but S is a string starting with '%'.
13140 In Intel syntax, the '%' is elided. */
13142 oappend_maybe_intel (const char *s
)
13144 oappend (s
+ intel_syntax
);
13148 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13150 oappend_maybe_intel ("%st");
13154 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13156 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13157 oappend_maybe_intel (scratchbuf
);
13160 /* Capital letters in template are macros. */
13162 putop (const char *in_template
, int sizeflag
)
13167 unsigned int l
= 0, len
= 1;
13170 #define SAVE_LAST(c) \
13171 if (l < len && l < sizeof (last)) \
13176 for (p
= in_template
; *p
; p
++)
13193 while (*++p
!= '|')
13194 if (*p
== '}' || *p
== '\0')
13197 /* Fall through. */
13202 while (*++p
!= '}')
13213 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13217 if (l
== 0 && len
== 1)
13222 if (sizeflag
& SUFFIX_ALWAYS
)
13235 if (address_mode
== mode_64bit
13236 && !(prefixes
& PREFIX_ADDR
))
13247 if (intel_syntax
&& !alt
)
13249 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13251 if (sizeflag
& DFLAG
)
13252 *obufp
++ = intel_syntax
? 'd' : 'l';
13254 *obufp
++ = intel_syntax
? 'w' : 's';
13255 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13259 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13262 if (modrm
.mod
== 3)
13268 if (sizeflag
& DFLAG
)
13269 *obufp
++ = intel_syntax
? 'd' : 'l';
13272 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13278 case 'E': /* For jcxz/jecxz */
13279 if (address_mode
== mode_64bit
)
13281 if (sizeflag
& AFLAG
)
13287 if (sizeflag
& AFLAG
)
13289 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13294 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
13296 if (sizeflag
& AFLAG
)
13297 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
13299 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
13300 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13304 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
13306 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13310 if (!(rex
& REX_W
))
13311 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13316 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
13317 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
13319 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
13322 if (prefixes
& PREFIX_DS
)
13343 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
13348 /* Fall through. */
13351 if (l
!= 0 || len
!= 1)
13359 if (sizeflag
& SUFFIX_ALWAYS
)
13363 if (intel_mnemonic
!= cond
)
13367 if ((prefixes
& PREFIX_FWAIT
) == 0)
13370 used_prefixes
|= PREFIX_FWAIT
;
13376 else if (intel_syntax
&& (sizeflag
& DFLAG
))
13380 if (!(rex
& REX_W
))
13381 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13385 && address_mode
== mode_64bit
13386 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13391 /* Fall through. */
13395 if ((rex
& REX_W
) == 0
13396 && (prefixes
& PREFIX_DATA
))
13398 if ((sizeflag
& DFLAG
) == 0)
13400 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13404 if ((prefixes
& PREFIX_DATA
)
13406 || (sizeflag
& SUFFIX_ALWAYS
))
13413 if (sizeflag
& DFLAG
)
13417 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13424 if (address_mode
== mode_64bit
13425 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13427 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13431 /* Fall through. */
13434 if (l
== 0 && len
== 1)
13437 if (intel_syntax
&& !alt
)
13440 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13446 if (sizeflag
& DFLAG
)
13447 *obufp
++ = intel_syntax
? 'd' : 'l';
13450 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13456 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13462 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13477 else if (sizeflag
& DFLAG
)
13486 if (intel_syntax
&& !p
[1]
13487 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13489 if (!(rex
& REX_W
))
13490 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13493 if (l
== 0 && len
== 1)
13497 if (address_mode
== mode_64bit
13498 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13500 if (sizeflag
& SUFFIX_ALWAYS
)
13522 /* Fall through. */
13525 if (l
== 0 && len
== 1)
13530 if (sizeflag
& SUFFIX_ALWAYS
)
13536 if (sizeflag
& DFLAG
)
13540 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13554 if (address_mode
== mode_64bit
13555 && !(prefixes
& PREFIX_ADDR
))
13566 if (l
!= 0 || len
!= 1)
13571 if (need_vex
&& vex
.prefix
)
13573 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13580 if (prefixes
& PREFIX_DATA
)
13584 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13588 if (l
== 0 && len
== 1)
13590 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13601 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13609 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13611 switch (vex
.length
)
13625 if (l
== 0 && len
== 1)
13627 /* operand size flag for cwtl, cbtw */
13636 else if (sizeflag
& DFLAG
)
13640 if (!(rex
& REX_W
))
13641 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13648 && last
[0] != 'L'))
13655 if (last
[0] == 'X')
13656 *obufp
++ = vex
.w
? 'd': 's';
13658 *obufp
++ = vex
.w
? 'q': 'd';
13665 mnemonicendp
= obufp
;
13670 oappend (const char *s
)
13672 obufp
= stpcpy (obufp
, s
);
13678 if (prefixes
& PREFIX_CS
)
13680 used_prefixes
|= PREFIX_CS
;
13681 oappend_maybe_intel ("%cs:");
13683 if (prefixes
& PREFIX_DS
)
13685 used_prefixes
|= PREFIX_DS
;
13686 oappend_maybe_intel ("%ds:");
13688 if (prefixes
& PREFIX_SS
)
13690 used_prefixes
|= PREFIX_SS
;
13691 oappend_maybe_intel ("%ss:");
13693 if (prefixes
& PREFIX_ES
)
13695 used_prefixes
|= PREFIX_ES
;
13696 oappend_maybe_intel ("%es:");
13698 if (prefixes
& PREFIX_FS
)
13700 used_prefixes
|= PREFIX_FS
;
13701 oappend_maybe_intel ("%fs:");
13703 if (prefixes
& PREFIX_GS
)
13705 used_prefixes
|= PREFIX_GS
;
13706 oappend_maybe_intel ("%gs:");
13711 OP_indirE (int bytemode
, int sizeflag
)
13715 OP_E (bytemode
, sizeflag
);
13719 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13721 if (address_mode
== mode_64bit
)
13729 sprintf_vma (tmp
, disp
);
13730 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13731 strcpy (buf
+ 2, tmp
+ i
);
13735 bfd_signed_vma v
= disp
;
13742 /* Check for possible overflow on 0x8000000000000000. */
13745 strcpy (buf
, "9223372036854775808");
13759 tmp
[28 - i
] = (v
% 10) + '0';
13763 strcpy (buf
, tmp
+ 29 - i
);
13769 sprintf (buf
, "0x%x", (unsigned int) disp
);
13771 sprintf (buf
, "%d", (int) disp
);
13775 /* Put DISP in BUF as signed hex number. */
13778 print_displacement (char *buf
, bfd_vma disp
)
13780 bfd_signed_vma val
= disp
;
13789 /* Check for possible overflow. */
13792 switch (address_mode
)
13795 strcpy (buf
+ j
, "0x8000000000000000");
13798 strcpy (buf
+ j
, "0x80000000");
13801 strcpy (buf
+ j
, "0x8000");
13811 sprintf_vma (tmp
, (bfd_vma
) val
);
13812 for (i
= 0; tmp
[i
] == '0'; i
++)
13814 if (tmp
[i
] == '\0')
13816 strcpy (buf
+ j
, tmp
+ i
);
13820 intel_operand_size (int bytemode
, int sizeflag
)
13824 && (bytemode
== x_mode
13825 || bytemode
== evex_half_bcst_xmmq_mode
))
13828 oappend ("QWORD PTR ");
13830 oappend ("DWORD PTR ");
13838 oappend ("BYTE PTR ");
13842 oappend ("WORD PTR ");
13845 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13847 oappend ("QWORD PTR ");
13856 oappend ("QWORD PTR ");
13859 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13860 oappend ("DWORD PTR ");
13862 oappend ("WORD PTR ");
13863 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13867 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13869 oappend ("WORD PTR ");
13870 if (!(rex
& REX_W
))
13871 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13874 if (sizeflag
& DFLAG
)
13875 oappend ("QWORD PTR ");
13877 oappend ("DWORD PTR ");
13878 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13881 case d_scalar_mode
:
13882 case d_scalar_swap_mode
:
13885 oappend ("DWORD PTR ");
13888 case q_scalar_mode
:
13889 case q_scalar_swap_mode
:
13891 oappend ("QWORD PTR ");
13894 if (address_mode
== mode_64bit
)
13895 oappend ("QWORD PTR ");
13897 oappend ("DWORD PTR ");
13900 if (sizeflag
& DFLAG
)
13901 oappend ("FWORD PTR ");
13903 oappend ("DWORD PTR ");
13904 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13907 oappend ("TBYTE PTR ");
13911 case evex_x_gscat_mode
:
13912 case evex_x_nobcst_mode
:
13915 switch (vex
.length
)
13918 oappend ("XMMWORD PTR ");
13921 oappend ("YMMWORD PTR ");
13924 oappend ("ZMMWORD PTR ");
13931 oappend ("XMMWORD PTR ");
13934 oappend ("XMMWORD PTR ");
13937 oappend ("YMMWORD PTR ");
13940 case evex_half_bcst_xmmq_mode
:
13944 switch (vex
.length
)
13947 oappend ("QWORD PTR ");
13950 oappend ("XMMWORD PTR ");
13953 oappend ("YMMWORD PTR ");
13963 switch (vex
.length
)
13968 oappend ("BYTE PTR ");
13978 switch (vex
.length
)
13983 oappend ("WORD PTR ");
13993 switch (vex
.length
)
13998 oappend ("DWORD PTR ");
14008 switch (vex
.length
)
14013 oappend ("QWORD PTR ");
14023 switch (vex
.length
)
14026 oappend ("WORD PTR ");
14029 oappend ("DWORD PTR ");
14032 oappend ("QWORD PTR ");
14042 switch (vex
.length
)
14045 oappend ("DWORD PTR ");
14048 oappend ("QWORD PTR ");
14051 oappend ("XMMWORD PTR ");
14061 switch (vex
.length
)
14064 oappend ("QWORD PTR ");
14067 oappend ("YMMWORD PTR ");
14070 oappend ("ZMMWORD PTR ");
14080 switch (vex
.length
)
14084 oappend ("XMMWORD PTR ");
14091 oappend ("OWORD PTR ");
14094 case vex_w_dq_mode
:
14095 case vex_scalar_w_dq_mode
:
14100 oappend ("QWORD PTR ");
14102 oappend ("DWORD PTR ");
14104 case vex_vsib_d_w_dq_mode
:
14105 case vex_vsib_q_w_dq_mode
:
14112 oappend ("QWORD PTR ");
14114 oappend ("DWORD PTR ");
14118 if (vex
.length
!= 512)
14120 oappend ("ZMMWORD PTR ");
14123 case vex_vsib_q_w_d_mode
:
14124 case vex_vsib_d_w_d_mode
:
14125 if (!need_vex
|| !vex
.evex
|| vex
.length
!= 512)
14128 oappend ("YMMWORD PTR ");
14134 /* Currently the only instructions, which allows either mask or
14135 memory operand, are AVX512's KMOVW instructions. They need
14136 Word-sized operand. */
14137 if (vex
.w
|| vex
.length
!= 128)
14139 oappend ("WORD PTR ");
14148 OP_E_register (int bytemode
, int sizeflag
)
14150 int reg
= modrm
.rm
;
14151 const char **names
;
14157 if ((sizeflag
& SUFFIX_ALWAYS
)
14158 && (bytemode
== b_swap_mode
|| bytemode
== v_swap_mode
))
14182 names
= address_mode
== mode_64bit
? names64
: names32
;
14188 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14206 if ((sizeflag
& DFLAG
)
14207 || (bytemode
!= v_mode
14208 && bytemode
!= v_swap_mode
))
14212 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14216 names
= names_mask
;
14221 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14224 oappend (names
[reg
]);
14228 OP_E_memory (int bytemode
, int sizeflag
)
14231 int add
= (rex
& REX_B
) ? 8 : 0;
14237 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14239 && bytemode
!= x_mode
14240 && bytemode
!= evex_half_bcst_xmmq_mode
)
14247 case vex_vsib_d_w_dq_mode
:
14248 case vex_vsib_d_w_d_mode
:
14249 case vex_vsib_q_w_dq_mode
:
14250 case vex_vsib_q_w_d_mode
:
14251 case evex_x_gscat_mode
:
14253 shift
= vex
.w
? 3 : 2;
14256 case evex_half_bcst_xmmq_mode
:
14259 shift
= vex
.w
? 3 : 2;
14262 /* Fall through if vex.b == 0. */
14267 case evex_x_nobcst_mode
:
14269 switch (vex
.length
)
14292 case q_scalar_mode
:
14294 case q_scalar_swap_mode
:
14300 case d_scalar_mode
:
14302 case d_scalar_swap_mode
:
14314 /* Make necessary corrections to shift for modes that need it.
14315 For these modes we currently have shift 4, 5 or 6 depending on
14316 vex.length (it corresponds to xmmword, ymmword or zmmword
14317 operand). We might want to make it 3, 4 or 5 (e.g. for
14318 xmmq_mode). In case of broadcast enabled the corrections
14319 aren't needed, as element size is always 32 or 64 bits. */
14320 if (bytemode
== xmmq_mode
14321 || (bytemode
== evex_half_bcst_xmmq_mode
14324 else if (bytemode
== xmmqd_mode
)
14326 else if (bytemode
== xmmdw_mode
)
14334 intel_operand_size (bytemode
, sizeflag
);
14337 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14339 /* 32/64 bit address mode */
14348 int addr32flag
= !((sizeflag
& AFLAG
)
14349 || bytemode
== v_bnd_mode
14350 || bytemode
== bnd_mode
);
14351 const char **indexes64
= names64
;
14352 const char **indexes32
= names32
;
14362 vindex
= sib
.index
;
14368 case vex_vsib_d_w_dq_mode
:
14369 case vex_vsib_d_w_d_mode
:
14370 case vex_vsib_q_w_dq_mode
:
14371 case vex_vsib_q_w_d_mode
:
14381 switch (vex
.length
)
14384 indexes64
= indexes32
= names_xmm
;
14388 || bytemode
== vex_vsib_q_w_dq_mode
14389 || bytemode
== vex_vsib_q_w_d_mode
)
14390 indexes64
= indexes32
= names_ymm
;
14392 indexes64
= indexes32
= names_xmm
;
14396 || bytemode
== vex_vsib_q_w_dq_mode
14397 || bytemode
== vex_vsib_q_w_d_mode
)
14398 indexes64
= indexes32
= names_zmm
;
14400 indexes64
= indexes32
= names_ymm
;
14407 haveindex
= vindex
!= 4;
14414 rbase
= base
+ add
;
14422 if (address_mode
== mode_64bit
&& !havesib
)
14428 FETCH_DATA (the_info
, codep
+ 1);
14430 if ((disp
& 0x80) != 0)
14432 if (vex
.evex
&& shift
> 0)
14440 /* In 32bit mode, we need index register to tell [offset] from
14441 [eiz*1 + offset]. */
14442 needindex
= (havesib
14445 && address_mode
== mode_32bit
);
14446 havedisp
= (havebase
14448 || (havesib
&& (haveindex
|| scale
!= 0)));
14451 if (modrm
.mod
!= 0 || base
== 5)
14453 if (havedisp
|| riprel
)
14454 print_displacement (scratchbuf
, disp
);
14456 print_operand_value (scratchbuf
, 1, disp
);
14457 oappend (scratchbuf
);
14461 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
14465 if ((havebase
|| haveindex
|| riprel
)
14466 && (bytemode
!= v_bnd_mode
)
14467 && (bytemode
!= bnd_mode
))
14468 used_prefixes
|= PREFIX_ADDR
;
14470 if (havedisp
|| (intel_syntax
&& riprel
))
14472 *obufp
++ = open_char
;
14473 if (intel_syntax
&& riprel
)
14476 oappend (sizeflag
& AFLAG
? "rip" : "eip");
14480 oappend (address_mode
== mode_64bit
&& !addr32flag
14481 ? names64
[rbase
] : names32
[rbase
]);
14484 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14485 print index to tell base + index from base. */
14489 || (havebase
&& base
!= ESP_REG_NUM
))
14491 if (!intel_syntax
|| havebase
)
14493 *obufp
++ = separator_char
;
14497 oappend (address_mode
== mode_64bit
&& !addr32flag
14498 ? indexes64
[vindex
] : indexes32
[vindex
]);
14500 oappend (address_mode
== mode_64bit
&& !addr32flag
14501 ? index64
: index32
);
14503 *obufp
++ = scale_char
;
14505 sprintf (scratchbuf
, "%d", 1 << scale
);
14506 oappend (scratchbuf
);
14510 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14512 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14517 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14521 disp
= - (bfd_signed_vma
) disp
;
14525 print_displacement (scratchbuf
, disp
);
14527 print_operand_value (scratchbuf
, 1, disp
);
14528 oappend (scratchbuf
);
14531 *obufp
++ = close_char
;
14534 else if (intel_syntax
)
14536 if (modrm
.mod
!= 0 || base
== 5)
14538 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
14539 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
14543 oappend (names_seg
[ds_reg
- es_reg
]);
14546 print_operand_value (scratchbuf
, 1, disp
);
14547 oappend (scratchbuf
);
14553 /* 16 bit address mode */
14554 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14561 if ((disp
& 0x8000) != 0)
14566 FETCH_DATA (the_info
, codep
+ 1);
14568 if ((disp
& 0x80) != 0)
14573 if ((disp
& 0x8000) != 0)
14579 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14581 print_displacement (scratchbuf
, disp
);
14582 oappend (scratchbuf
);
14585 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14587 *obufp
++ = open_char
;
14589 oappend (index16
[modrm
.rm
]);
14591 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14593 if ((bfd_signed_vma
) disp
>= 0)
14598 else if (modrm
.mod
!= 1)
14602 disp
= - (bfd_signed_vma
) disp
;
14605 print_displacement (scratchbuf
, disp
);
14606 oappend (scratchbuf
);
14609 *obufp
++ = close_char
;
14612 else if (intel_syntax
)
14614 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
14615 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
14619 oappend (names_seg
[ds_reg
- es_reg
]);
14622 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14623 oappend (scratchbuf
);
14626 if (vex
.evex
&& vex
.b
14627 && (bytemode
== x_mode
14628 || bytemode
== evex_half_bcst_xmmq_mode
))
14630 if (vex
.w
|| bytemode
== evex_half_bcst_xmmq_mode
)
14631 oappend ("{1to8}");
14633 oappend ("{1to16}");
14638 OP_E (int bytemode
, int sizeflag
)
14640 /* Skip mod/rm byte. */
14644 if (modrm
.mod
== 3)
14645 OP_E_register (bytemode
, sizeflag
);
14647 OP_E_memory (bytemode
, sizeflag
);
14651 OP_G (int bytemode
, int sizeflag
)
14662 oappend (names8rex
[modrm
.reg
+ add
]);
14664 oappend (names8
[modrm
.reg
+ add
]);
14667 oappend (names16
[modrm
.reg
+ add
]);
14670 oappend (names32
[modrm
.reg
+ add
]);
14673 oappend (names64
[modrm
.reg
+ add
]);
14676 oappend (names_bnd
[modrm
.reg
]);
14685 oappend (names64
[modrm
.reg
+ add
]);
14688 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
14689 oappend (names32
[modrm
.reg
+ add
]);
14691 oappend (names16
[modrm
.reg
+ add
]);
14692 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14696 if (address_mode
== mode_64bit
)
14697 oappend (names64
[modrm
.reg
+ add
]);
14699 oappend (names32
[modrm
.reg
+ add
]);
14702 oappend (names_mask
[modrm
.reg
+ add
]);
14705 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14718 FETCH_DATA (the_info
, codep
+ 8);
14719 a
= *codep
++ & 0xff;
14720 a
|= (*codep
++ & 0xff) << 8;
14721 a
|= (*codep
++ & 0xff) << 16;
14722 a
|= (*codep
++ & 0xff) << 24;
14723 b
= *codep
++ & 0xff;
14724 b
|= (*codep
++ & 0xff) << 8;
14725 b
|= (*codep
++ & 0xff) << 16;
14726 b
|= (*codep
++ & 0xff) << 24;
14727 x
= a
+ ((bfd_vma
) b
<< 32);
14735 static bfd_signed_vma
14738 bfd_signed_vma x
= 0;
14740 FETCH_DATA (the_info
, codep
+ 4);
14741 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14742 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14743 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14744 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14748 static bfd_signed_vma
14751 bfd_signed_vma x
= 0;
14753 FETCH_DATA (the_info
, codep
+ 4);
14754 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14755 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14756 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14757 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14759 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14769 FETCH_DATA (the_info
, codep
+ 2);
14770 x
= *codep
++ & 0xff;
14771 x
|= (*codep
++ & 0xff) << 8;
14776 set_op (bfd_vma op
, int riprel
)
14778 op_index
[op_ad
] = op_ad
;
14779 if (address_mode
== mode_64bit
)
14781 op_address
[op_ad
] = op
;
14782 op_riprel
[op_ad
] = riprel
;
14786 /* Mask to get a 32-bit address. */
14787 op_address
[op_ad
] = op
& 0xffffffff;
14788 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14793 OP_REG (int code
, int sizeflag
)
14800 case es_reg
: case ss_reg
: case cs_reg
:
14801 case ds_reg
: case fs_reg
: case gs_reg
:
14802 oappend (names_seg
[code
- es_reg
]);
14814 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14815 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14816 s
= names16
[code
- ax_reg
+ add
];
14818 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14819 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14822 s
= names8rex
[code
- al_reg
+ add
];
14824 s
= names8
[code
- al_reg
];
14826 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14827 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14828 if (address_mode
== mode_64bit
14829 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14831 s
= names64
[code
- rAX_reg
+ add
];
14834 code
+= eAX_reg
- rAX_reg
;
14835 /* Fall through. */
14836 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14837 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14840 s
= names64
[code
- eAX_reg
+ add
];
14843 if (sizeflag
& DFLAG
)
14844 s
= names32
[code
- eAX_reg
+ add
];
14846 s
= names16
[code
- eAX_reg
+ add
];
14847 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14851 s
= INTERNAL_DISASSEMBLER_ERROR
;
14858 OP_IMREG (int code
, int sizeflag
)
14870 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14871 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14872 s
= names16
[code
- ax_reg
];
14874 case es_reg
: case ss_reg
: case cs_reg
:
14875 case ds_reg
: case fs_reg
: case gs_reg
:
14876 s
= names_seg
[code
- es_reg
];
14878 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14879 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14882 s
= names8rex
[code
- al_reg
];
14884 s
= names8
[code
- al_reg
];
14886 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14887 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14890 s
= names64
[code
- eAX_reg
];
14893 if (sizeflag
& DFLAG
)
14894 s
= names32
[code
- eAX_reg
];
14896 s
= names16
[code
- eAX_reg
];
14897 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14900 case z_mode_ax_reg
:
14901 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14905 if (!(rex
& REX_W
))
14906 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14909 s
= INTERNAL_DISASSEMBLER_ERROR
;
14916 OP_I (int bytemode
, int sizeflag
)
14919 bfd_signed_vma mask
= -1;
14924 FETCH_DATA (the_info
, codep
+ 1);
14929 if (address_mode
== mode_64bit
)
14934 /* Fall through. */
14941 if (sizeflag
& DFLAG
)
14951 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14963 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14968 scratchbuf
[0] = '$';
14969 print_operand_value (scratchbuf
+ 1, 1, op
);
14970 oappend_maybe_intel (scratchbuf
);
14971 scratchbuf
[0] = '\0';
14975 OP_I64 (int bytemode
, int sizeflag
)
14978 bfd_signed_vma mask
= -1;
14980 if (address_mode
!= mode_64bit
)
14982 OP_I (bytemode
, sizeflag
);
14989 FETCH_DATA (the_info
, codep
+ 1);
14999 if (sizeflag
& DFLAG
)
15009 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15017 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15022 scratchbuf
[0] = '$';
15023 print_operand_value (scratchbuf
+ 1, 1, op
);
15024 oappend_maybe_intel (scratchbuf
);
15025 scratchbuf
[0] = '\0';
15029 OP_sI (int bytemode
, int sizeflag
)
15037 FETCH_DATA (the_info
, codep
+ 1);
15039 if ((op
& 0x80) != 0)
15041 if (bytemode
== b_T_mode
)
15043 if (address_mode
!= mode_64bit
15044 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15046 /* The operand-size prefix is overridden by a REX prefix. */
15047 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15055 if (!(rex
& REX_W
))
15057 if (sizeflag
& DFLAG
)
15065 /* The operand-size prefix is overridden by a REX prefix. */
15066 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15072 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15076 scratchbuf
[0] = '$';
15077 print_operand_value (scratchbuf
+ 1, 1, op
);
15078 oappend_maybe_intel (scratchbuf
);
15082 OP_J (int bytemode
, int sizeflag
)
15086 bfd_vma segment
= 0;
15091 FETCH_DATA (the_info
, codep
+ 1);
15093 if ((disp
& 0x80) != 0)
15098 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15103 if ((disp
& 0x8000) != 0)
15105 /* In 16bit mode, address is wrapped around at 64k within
15106 the same segment. Otherwise, a data16 prefix on a jump
15107 instruction means that the pc is masked to 16 bits after
15108 the displacement is added! */
15110 if ((prefixes
& PREFIX_DATA
) == 0)
15111 segment
= ((start_pc
+ codep
- start_codep
)
15112 & ~((bfd_vma
) 0xffff));
15114 if (!(rex
& REX_W
))
15115 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15118 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15121 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
15123 print_operand_value (scratchbuf
, 1, disp
);
15124 oappend (scratchbuf
);
15128 OP_SEG (int bytemode
, int sizeflag
)
15130 if (bytemode
== w_mode
)
15131 oappend (names_seg
[modrm
.reg
]);
15133 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
15137 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
15141 if (sizeflag
& DFLAG
)
15151 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15153 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15155 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15156 oappend (scratchbuf
);
15160 OP_OFF (int bytemode
, int sizeflag
)
15164 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15165 intel_operand_size (bytemode
, sizeflag
);
15168 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15175 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
15176 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
15178 oappend (names_seg
[ds_reg
- es_reg
]);
15182 print_operand_value (scratchbuf
, 1, off
);
15183 oappend (scratchbuf
);
15187 OP_OFF64 (int bytemode
, int sizeflag
)
15191 if (address_mode
!= mode_64bit
15192 || (prefixes
& PREFIX_ADDR
))
15194 OP_OFF (bytemode
, sizeflag
);
15198 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15199 intel_operand_size (bytemode
, sizeflag
);
15206 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
15207 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
15209 oappend (names_seg
[ds_reg
- es_reg
]);
15213 print_operand_value (scratchbuf
, 1, off
);
15214 oappend (scratchbuf
);
15218 ptr_reg (int code
, int sizeflag
)
15222 *obufp
++ = open_char
;
15223 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15224 if (address_mode
== mode_64bit
)
15226 if (!(sizeflag
& AFLAG
))
15227 s
= names32
[code
- eAX_reg
];
15229 s
= names64
[code
- eAX_reg
];
15231 else if (sizeflag
& AFLAG
)
15232 s
= names32
[code
- eAX_reg
];
15234 s
= names16
[code
- eAX_reg
];
15236 *obufp
++ = close_char
;
15241 OP_ESreg (int code
, int sizeflag
)
15247 case 0x6d: /* insw/insl */
15248 intel_operand_size (z_mode
, sizeflag
);
15250 case 0xa5: /* movsw/movsl/movsq */
15251 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15252 case 0xab: /* stosw/stosl */
15253 case 0xaf: /* scasw/scasl */
15254 intel_operand_size (v_mode
, sizeflag
);
15257 intel_operand_size (b_mode
, sizeflag
);
15260 oappend_maybe_intel ("%es:");
15261 ptr_reg (code
, sizeflag
);
15265 OP_DSreg (int code
, int sizeflag
)
15271 case 0x6f: /* outsw/outsl */
15272 intel_operand_size (z_mode
, sizeflag
);
15274 case 0xa5: /* movsw/movsl/movsq */
15275 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15276 case 0xad: /* lodsw/lodsl/lodsq */
15277 intel_operand_size (v_mode
, sizeflag
);
15280 intel_operand_size (b_mode
, sizeflag
);
15289 | PREFIX_GS
)) == 0)
15290 prefixes
|= PREFIX_DS
;
15292 ptr_reg (code
, sizeflag
);
15296 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15304 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15306 all_prefixes
[last_lock_prefix
] = 0;
15307 used_prefixes
|= PREFIX_LOCK
;
15312 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15313 oappend_maybe_intel (scratchbuf
);
15317 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15326 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15328 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15329 oappend (scratchbuf
);
15333 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15335 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15336 oappend_maybe_intel (scratchbuf
);
15340 OP_R (int bytemode
, int sizeflag
)
15342 if (modrm
.mod
== 3)
15343 OP_E (bytemode
, sizeflag
);
15349 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15351 int reg
= modrm
.reg
;
15352 const char **names
;
15354 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15355 if (prefixes
& PREFIX_DATA
)
15364 oappend (names
[reg
]);
15368 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15370 int reg
= modrm
.reg
;
15371 const char **names
;
15383 && bytemode
!= xmm_mode
15384 && bytemode
!= xmmq_mode
15385 && bytemode
!= evex_half_bcst_xmmq_mode
15386 && bytemode
!= ymm_mode
15387 && bytemode
!= scalar_mode
)
15389 switch (vex
.length
)
15396 || (bytemode
!= vex_vsib_q_w_dq_mode
15397 && bytemode
!= vex_vsib_q_w_d_mode
))
15409 else if (bytemode
== xmmq_mode
15410 || bytemode
== evex_half_bcst_xmmq_mode
)
15412 switch (vex
.length
)
15425 else if (bytemode
== ymm_mode
)
15429 oappend (names
[reg
]);
15433 OP_EM (int bytemode
, int sizeflag
)
15436 const char **names
;
15438 if (modrm
.mod
!= 3)
15441 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15443 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15444 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15446 OP_E (bytemode
, sizeflag
);
15450 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15453 /* Skip mod/rm byte. */
15456 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15458 if (prefixes
& PREFIX_DATA
)
15467 oappend (names
[reg
]);
15470 /* cvt* are the only instructions in sse2 which have
15471 both SSE and MMX operands and also have 0x66 prefix
15472 in their opcode. 0x66 was originally used to differentiate
15473 between SSE and MMX instruction(operands). So we have to handle the
15474 cvt* separately using OP_EMC and OP_MXC */
15476 OP_EMC (int bytemode
, int sizeflag
)
15478 if (modrm
.mod
!= 3)
15480 if (intel_syntax
&& bytemode
== v_mode
)
15482 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15483 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15485 OP_E (bytemode
, sizeflag
);
15489 /* Skip mod/rm byte. */
15492 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15493 oappend (names_mm
[modrm
.rm
]);
15497 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15499 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15500 oappend (names_mm
[modrm
.reg
]);
15504 OP_EX (int bytemode
, int sizeflag
)
15507 const char **names
;
15509 /* Skip mod/rm byte. */
15513 if (modrm
.mod
!= 3)
15515 OP_E_memory (bytemode
, sizeflag
);
15530 if ((sizeflag
& SUFFIX_ALWAYS
)
15531 && (bytemode
== x_swap_mode
15532 || bytemode
== d_swap_mode
15533 || bytemode
== d_scalar_swap_mode
15534 || bytemode
== q_swap_mode
15535 || bytemode
== q_scalar_swap_mode
))
15539 && bytemode
!= xmm_mode
15540 && bytemode
!= xmmdw_mode
15541 && bytemode
!= xmmqd_mode
15542 && bytemode
!= xmm_mb_mode
15543 && bytemode
!= xmm_mw_mode
15544 && bytemode
!= xmm_md_mode
15545 && bytemode
!= xmm_mq_mode
15546 && bytemode
!= xmm_mdq_mode
15547 && bytemode
!= xmmq_mode
15548 && bytemode
!= evex_half_bcst_xmmq_mode
15549 && bytemode
!= ymm_mode
15550 && bytemode
!= d_scalar_mode
15551 && bytemode
!= d_scalar_swap_mode
15552 && bytemode
!= q_scalar_mode
15553 && bytemode
!= q_scalar_swap_mode
15554 && bytemode
!= vex_scalar_w_dq_mode
)
15556 switch (vex
.length
)
15571 else if (bytemode
== xmmq_mode
15572 || bytemode
== evex_half_bcst_xmmq_mode
)
15574 switch (vex
.length
)
15587 else if (bytemode
== ymm_mode
)
15591 oappend (names
[reg
]);
15595 OP_MS (int bytemode
, int sizeflag
)
15597 if (modrm
.mod
== 3)
15598 OP_EM (bytemode
, sizeflag
);
15604 OP_XS (int bytemode
, int sizeflag
)
15606 if (modrm
.mod
== 3)
15607 OP_EX (bytemode
, sizeflag
);
15613 OP_M (int bytemode
, int sizeflag
)
15615 if (modrm
.mod
== 3)
15616 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15619 OP_E (bytemode
, sizeflag
);
15623 OP_0f07 (int bytemode
, int sizeflag
)
15625 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15628 OP_E (bytemode
, sizeflag
);
15631 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15632 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15635 NOP_Fixup1 (int bytemode
, int sizeflag
)
15637 if ((prefixes
& PREFIX_DATA
) != 0
15640 && address_mode
== mode_64bit
))
15641 OP_REG (bytemode
, sizeflag
);
15643 strcpy (obuf
, "nop");
15647 NOP_Fixup2 (int bytemode
, int sizeflag
)
15649 if ((prefixes
& PREFIX_DATA
) != 0
15652 && address_mode
== mode_64bit
))
15653 OP_IMREG (bytemode
, sizeflag
);
15656 static const char *const Suffix3DNow
[] = {
15657 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15658 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15659 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15660 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15661 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15662 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15663 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15664 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15665 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15666 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15667 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15668 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15669 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15670 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15671 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15672 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15673 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15674 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15675 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15676 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15677 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15678 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15679 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15680 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15681 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15682 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15683 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15684 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15685 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15686 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15687 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15688 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15689 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15690 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15691 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15692 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15693 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15694 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15695 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15696 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15697 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15698 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15699 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15700 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15701 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15702 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15703 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15704 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15705 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15706 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15707 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15708 /* CC */ NULL
, NULL
, NULL
, NULL
,
15709 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15710 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15711 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15712 /* DC */ NULL
, NULL
, NULL
, NULL
,
15713 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15714 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15715 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15716 /* EC */ NULL
, NULL
, NULL
, NULL
,
15717 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15718 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15719 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15720 /* FC */ NULL
, NULL
, NULL
, NULL
,
15724 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15726 const char *mnemonic
;
15728 FETCH_DATA (the_info
, codep
+ 1);
15729 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15730 place where an 8-bit immediate would normally go. ie. the last
15731 byte of the instruction. */
15732 obufp
= mnemonicendp
;
15733 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15735 oappend (mnemonic
);
15738 /* Since a variable sized modrm/sib chunk is between the start
15739 of the opcode (0x0f0f) and the opcode suffix, we need to do
15740 all the modrm processing first, and don't know until now that
15741 we have a bad opcode. This necessitates some cleaning up. */
15742 op_out
[0][0] = '\0';
15743 op_out
[1][0] = '\0';
15746 mnemonicendp
= obufp
;
15749 static struct op simd_cmp_op
[] =
15751 { STRING_COMMA_LEN ("eq") },
15752 { STRING_COMMA_LEN ("lt") },
15753 { STRING_COMMA_LEN ("le") },
15754 { STRING_COMMA_LEN ("unord") },
15755 { STRING_COMMA_LEN ("neq") },
15756 { STRING_COMMA_LEN ("nlt") },
15757 { STRING_COMMA_LEN ("nle") },
15758 { STRING_COMMA_LEN ("ord") }
15762 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15764 unsigned int cmp_type
;
15766 FETCH_DATA (the_info
, codep
+ 1);
15767 cmp_type
= *codep
++ & 0xff;
15768 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15771 char *p
= mnemonicendp
- 2;
15775 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15776 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15780 /* We have a reserved extension byte. Output it directly. */
15781 scratchbuf
[0] = '$';
15782 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15783 oappend_maybe_intel (scratchbuf
);
15784 scratchbuf
[0] = '\0';
15789 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
15790 int sizeflag ATTRIBUTE_UNUSED
)
15792 /* mwait %eax,%ecx */
15795 const char **names
= (address_mode
== mode_64bit
15796 ? names64
: names32
);
15797 strcpy (op_out
[0], names
[0]);
15798 strcpy (op_out
[1], names
[1]);
15799 two_source_ops
= 1;
15801 /* Skip mod/rm byte. */
15807 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15808 int sizeflag ATTRIBUTE_UNUSED
)
15810 /* monitor %eax,%ecx,%edx" */
15813 const char **op1_names
;
15814 const char **names
= (address_mode
== mode_64bit
15815 ? names64
: names32
);
15817 if (!(prefixes
& PREFIX_ADDR
))
15818 op1_names
= (address_mode
== mode_16bit
15819 ? names16
: names
);
15822 /* Remove "addr16/addr32". */
15823 all_prefixes
[last_addr_prefix
] = 0;
15824 op1_names
= (address_mode
!= mode_32bit
15825 ? names32
: names16
);
15826 used_prefixes
|= PREFIX_ADDR
;
15828 strcpy (op_out
[0], op1_names
[0]);
15829 strcpy (op_out
[1], names
[1]);
15830 strcpy (op_out
[2], names
[2]);
15831 two_source_ops
= 1;
15833 /* Skip mod/rm byte. */
15841 /* Throw away prefixes and 1st. opcode byte. */
15842 codep
= insn_codep
+ 1;
15847 REP_Fixup (int bytemode
, int sizeflag
)
15849 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15851 if (prefixes
& PREFIX_REPZ
)
15852 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15859 OP_IMREG (bytemode
, sizeflag
);
15862 OP_ESreg (bytemode
, sizeflag
);
15865 OP_DSreg (bytemode
, sizeflag
);
15873 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15877 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15879 if (prefixes
& PREFIX_REPNZ
)
15880 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15883 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15884 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15888 HLE_Fixup1 (int bytemode
, int sizeflag
)
15891 && (prefixes
& PREFIX_LOCK
) != 0)
15893 if (prefixes
& PREFIX_REPZ
)
15894 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15895 if (prefixes
& PREFIX_REPNZ
)
15896 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15899 OP_E (bytemode
, sizeflag
);
15902 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15903 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15907 HLE_Fixup2 (int bytemode
, int sizeflag
)
15909 if (modrm
.mod
!= 3)
15911 if (prefixes
& PREFIX_REPZ
)
15912 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15913 if (prefixes
& PREFIX_REPNZ
)
15914 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15917 OP_E (bytemode
, sizeflag
);
15920 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15921 "xrelease" for memory operand. No check for LOCK prefix. */
15924 HLE_Fixup3 (int bytemode
, int sizeflag
)
15927 && last_repz_prefix
> last_repnz_prefix
15928 && (prefixes
& PREFIX_REPZ
) != 0)
15929 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15931 OP_E (bytemode
, sizeflag
);
15935 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15940 /* Change cmpxchg8b to cmpxchg16b. */
15941 char *p
= mnemonicendp
- 2;
15942 mnemonicendp
= stpcpy (p
, "16b");
15945 else if ((prefixes
& PREFIX_LOCK
) != 0)
15947 if (prefixes
& PREFIX_REPZ
)
15948 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15949 if (prefixes
& PREFIX_REPNZ
)
15950 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15953 OP_M (bytemode
, sizeflag
);
15957 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15959 const char **names
;
15963 switch (vex
.length
)
15977 oappend (names
[reg
]);
15981 CRC32_Fixup (int bytemode
, int sizeflag
)
15983 /* Add proper suffix to "crc32". */
15984 char *p
= mnemonicendp
;
16003 if (sizeflag
& DFLAG
)
16007 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16011 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16018 if (modrm
.mod
== 3)
16022 /* Skip mod/rm byte. */
16027 add
= (rex
& REX_B
) ? 8 : 0;
16028 if (bytemode
== b_mode
)
16032 oappend (names8rex
[modrm
.rm
+ add
]);
16034 oappend (names8
[modrm
.rm
+ add
]);
16040 oappend (names64
[modrm
.rm
+ add
]);
16041 else if ((prefixes
& PREFIX_DATA
))
16042 oappend (names16
[modrm
.rm
+ add
]);
16044 oappend (names32
[modrm
.rm
+ add
]);
16048 OP_E (bytemode
, sizeflag
);
16052 FXSAVE_Fixup (int bytemode
, int sizeflag
)
16054 /* Add proper suffix to "fxsave" and "fxrstor". */
16058 char *p
= mnemonicendp
;
16064 OP_M (bytemode
, sizeflag
);
16067 /* Display the destination register operand for instructions with
16071 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16074 const char **names
;
16082 reg
= vex
.register_specifier
;
16089 if (bytemode
== vex_scalar_mode
)
16091 oappend (names_xmm
[reg
]);
16095 switch (vex
.length
)
16102 case vex_vsib_q_w_dq_mode
:
16103 case vex_vsib_q_w_d_mode
:
16113 names
= names_mask
;
16127 case vex_vsib_q_w_dq_mode
:
16128 case vex_vsib_q_w_d_mode
:
16129 names
= vex
.w
? names_ymm
: names_xmm
;
16132 names
= names_mask
;
16146 oappend (names
[reg
]);
16149 /* Get the VEX immediate byte without moving codep. */
16151 static unsigned char
16152 get_vex_imm8 (int sizeflag
, int opnum
)
16154 int bytes_before_imm
= 0;
16156 if (modrm
.mod
!= 3)
16158 /* There are SIB/displacement bytes. */
16159 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16161 /* 32/64 bit address mode */
16162 int base
= modrm
.rm
;
16164 /* Check SIB byte. */
16167 FETCH_DATA (the_info
, codep
+ 1);
16169 /* When decoding the third source, don't increase
16170 bytes_before_imm as this has already been incremented
16171 by one in OP_E_memory while decoding the second
16174 bytes_before_imm
++;
16177 /* Don't increase bytes_before_imm when decoding the third source,
16178 it has already been incremented by OP_E_memory while decoding
16179 the second source operand. */
16185 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16186 SIB == 5, there is a 4 byte displacement. */
16188 /* No displacement. */
16191 /* 4 byte displacement. */
16192 bytes_before_imm
+= 4;
16195 /* 1 byte displacement. */
16196 bytes_before_imm
++;
16203 /* 16 bit address mode */
16204 /* Don't increase bytes_before_imm when decoding the third source,
16205 it has already been incremented by OP_E_memory while decoding
16206 the second source operand. */
16212 /* When modrm.rm == 6, there is a 2 byte displacement. */
16214 /* No displacement. */
16217 /* 2 byte displacement. */
16218 bytes_before_imm
+= 2;
16221 /* 1 byte displacement: when decoding the third source,
16222 don't increase bytes_before_imm as this has already
16223 been incremented by one in OP_E_memory while decoding
16224 the second source operand. */
16226 bytes_before_imm
++;
16234 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16235 return codep
[bytes_before_imm
];
16239 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16241 const char **names
;
16243 if (reg
== -1 && modrm
.mod
!= 3)
16245 OP_E_memory (bytemode
, sizeflag
);
16257 else if (reg
> 7 && address_mode
!= mode_64bit
)
16261 switch (vex
.length
)
16272 oappend (names
[reg
]);
16276 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16279 static unsigned char vex_imm8
;
16281 if (vex_w_done
== 0)
16285 /* Skip mod/rm byte. */
16289 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16292 reg
= vex_imm8
>> 4;
16294 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16296 else if (vex_w_done
== 1)
16301 reg
= vex_imm8
>> 4;
16303 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16307 /* Output the imm8 directly. */
16308 scratchbuf
[0] = '$';
16309 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16310 oappend_maybe_intel (scratchbuf
);
16311 scratchbuf
[0] = '\0';
16317 OP_Vex_2src (int bytemode
, int sizeflag
)
16319 if (modrm
.mod
== 3)
16321 int reg
= modrm
.rm
;
16325 oappend (names_xmm
[reg
]);
16330 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16332 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16333 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16335 OP_E (bytemode
, sizeflag
);
16340 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16342 if (modrm
.mod
== 3)
16344 /* Skip mod/rm byte. */
16350 oappend (names_xmm
[vex
.register_specifier
]);
16352 OP_Vex_2src (bytemode
, sizeflag
);
16356 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16359 OP_Vex_2src (bytemode
, sizeflag
);
16361 oappend (names_xmm
[vex
.register_specifier
]);
16365 OP_EX_VexW (int bytemode
, int sizeflag
)
16373 /* Skip mod/rm byte. */
16378 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16383 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16386 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16390 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16391 int sizeflag ATTRIBUTE_UNUSED
)
16393 /* Skip the immediate byte and check for invalid bits. */
16394 FETCH_DATA (the_info
, codep
+ 1);
16395 if (*codep
++ & 0xf)
16400 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16403 const char **names
;
16405 FETCH_DATA (the_info
, codep
+ 1);
16408 if (bytemode
!= x_mode
)
16415 if (reg
> 7 && address_mode
!= mode_64bit
)
16418 switch (vex
.length
)
16429 oappend (names
[reg
]);
16433 OP_XMM_VexW (int bytemode
, int sizeflag
)
16435 /* Turn off the REX.W bit since it is used for swapping operands
16438 OP_XMM (bytemode
, sizeflag
);
16442 OP_EX_Vex (int bytemode
, int sizeflag
)
16444 if (modrm
.mod
!= 3)
16446 if (vex
.register_specifier
!= 0)
16450 OP_EX (bytemode
, sizeflag
);
16454 OP_XMM_Vex (int bytemode
, int sizeflag
)
16456 if (modrm
.mod
!= 3)
16458 if (vex
.register_specifier
!= 0)
16462 OP_XMM (bytemode
, sizeflag
);
16466 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16468 switch (vex
.length
)
16471 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
16474 mnemonicendp
= stpcpy (obuf
, "vzeroall");
16481 static struct op vex_cmp_op
[] =
16483 { STRING_COMMA_LEN ("eq") },
16484 { STRING_COMMA_LEN ("lt") },
16485 { STRING_COMMA_LEN ("le") },
16486 { STRING_COMMA_LEN ("unord") },
16487 { STRING_COMMA_LEN ("neq") },
16488 { STRING_COMMA_LEN ("nlt") },
16489 { STRING_COMMA_LEN ("nle") },
16490 { STRING_COMMA_LEN ("ord") },
16491 { STRING_COMMA_LEN ("eq_uq") },
16492 { STRING_COMMA_LEN ("nge") },
16493 { STRING_COMMA_LEN ("ngt") },
16494 { STRING_COMMA_LEN ("false") },
16495 { STRING_COMMA_LEN ("neq_oq") },
16496 { STRING_COMMA_LEN ("ge") },
16497 { STRING_COMMA_LEN ("gt") },
16498 { STRING_COMMA_LEN ("true") },
16499 { STRING_COMMA_LEN ("eq_os") },
16500 { STRING_COMMA_LEN ("lt_oq") },
16501 { STRING_COMMA_LEN ("le_oq") },
16502 { STRING_COMMA_LEN ("unord_s") },
16503 { STRING_COMMA_LEN ("neq_us") },
16504 { STRING_COMMA_LEN ("nlt_uq") },
16505 { STRING_COMMA_LEN ("nle_uq") },
16506 { STRING_COMMA_LEN ("ord_s") },
16507 { STRING_COMMA_LEN ("eq_us") },
16508 { STRING_COMMA_LEN ("nge_uq") },
16509 { STRING_COMMA_LEN ("ngt_uq") },
16510 { STRING_COMMA_LEN ("false_os") },
16511 { STRING_COMMA_LEN ("neq_os") },
16512 { STRING_COMMA_LEN ("ge_oq") },
16513 { STRING_COMMA_LEN ("gt_oq") },
16514 { STRING_COMMA_LEN ("true_us") },
16518 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16520 unsigned int cmp_type
;
16522 FETCH_DATA (the_info
, codep
+ 1);
16523 cmp_type
= *codep
++ & 0xff;
16524 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16527 char *p
= mnemonicendp
- 2;
16531 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16532 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16536 /* We have a reserved extension byte. Output it directly. */
16537 scratchbuf
[0] = '$';
16538 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16539 oappend_maybe_intel (scratchbuf
);
16540 scratchbuf
[0] = '\0';
16545 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16546 int sizeflag ATTRIBUTE_UNUSED
)
16548 unsigned int cmp_type
;
16553 FETCH_DATA (the_info
, codep
+ 1);
16554 cmp_type
= *codep
++ & 0xff;
16555 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16556 If it's the case, print suffix, otherwise - print the immediate. */
16557 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16562 char *p
= mnemonicendp
- 2;
16564 /* vpcmp* can have both one- and two-lettered suffix. */
16578 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16579 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16583 /* We have a reserved extension byte. Output it directly. */
16584 scratchbuf
[0] = '$';
16585 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16586 oappend_maybe_intel (scratchbuf
);
16587 scratchbuf
[0] = '\0';
16591 static const struct op pclmul_op
[] =
16593 { STRING_COMMA_LEN ("lql") },
16594 { STRING_COMMA_LEN ("hql") },
16595 { STRING_COMMA_LEN ("lqh") },
16596 { STRING_COMMA_LEN ("hqh") }
16600 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16601 int sizeflag ATTRIBUTE_UNUSED
)
16603 unsigned int pclmul_type
;
16605 FETCH_DATA (the_info
, codep
+ 1);
16606 pclmul_type
= *codep
++ & 0xff;
16607 switch (pclmul_type
)
16618 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16621 char *p
= mnemonicendp
- 3;
16626 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16627 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16631 /* We have a reserved extension byte. Output it directly. */
16632 scratchbuf
[0] = '$';
16633 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16634 oappend_maybe_intel (scratchbuf
);
16635 scratchbuf
[0] = '\0';
16640 MOVBE_Fixup (int bytemode
, int sizeflag
)
16642 /* Add proper suffix to "movbe". */
16643 char *p
= mnemonicendp
;
16652 if (sizeflag
& SUFFIX_ALWAYS
)
16658 if (sizeflag
& DFLAG
)
16662 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16667 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16674 OP_M (bytemode
, sizeflag
);
16678 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16681 const char **names
;
16683 /* Skip mod/rm byte. */
16697 oappend (names
[reg
]);
16701 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16703 const char **names
;
16710 oappend (names
[vex
.register_specifier
]);
16714 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16717 || bytemode
!= mask_mode
)
16721 if ((rex
& REX_R
) != 0 || !vex
.r
)
16727 oappend (names_mask
[modrm
.reg
]);
16731 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16734 || (bytemode
!= evex_rounding_mode
16735 && bytemode
!= evex_sae_mode
))
16737 if (modrm
.mod
== 3 && vex
.b
)
16740 case evex_rounding_mode
:
16741 oappend (names_rounding
[vex
.ll
]);
16743 case evex_sae_mode
: