opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 #define XX { NULL, 0 }
 225 #define Bad_Opcode NULL, { { NULL, 0 } }
 226
 227 #define Eb { OP_E, b_mode }
 228 #define Ebnd { OP_E, bnd_mode }
 229 #define EbS { OP_E, b_swap_mode }
 230 #define Ev { OP_E, v_mode }
 231 #define Ev_bnd { OP_E, v_bnd_mode }
 232 #define EvS { OP_E, v_swap_mode }
 233 #define Ed { OP_E, d_mode }
 234 #define Edq { OP_E, dq_mode }
 235 #define Edqw { OP_E, dqw_mode }
 236 #define Edqb { OP_E, dqb_mode }
 237 #define Edqd { OP_E, dqd_mode }
 238 #define Eq { OP_E, q_mode }
 239 #define indirEv { OP_indirE, stack_v_mode }
 240 #define indirEp { OP_indirE, f_mode }
 241 #define stackEv { OP_E, stack_v_mode }
 242 #define Em { OP_E, m_mode }
 243 #define Ew { OP_E, w_mode }
 244 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 245 #define Ma { OP_M, a_mode }
 246 #define Mb { OP_M, b_mode }
 247 #define Md { OP_M, d_mode }
 248 #define Mo { OP_M, o_mode }
 249 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 250 #define Mq { OP_M, q_mode }
 251 #define Mx { OP_M, x_mode }
 252 #define Mxmm { OP_M, xmm_mode }
 253 #define Gb { OP_G, b_mode }
 254 #define Gbnd { OP_G, bnd_mode }
 255 #define Gv { OP_G, v_mode }
 256 #define Gd { OP_G, d_mode }
 257 #define Gdq { OP_G, dq_mode }
 258 #define Gm { OP_G, m_mode }
 259 #define Gw { OP_G, w_mode }
 260 #define Rd { OP_R, d_mode }
 261 #define Rdq { OP_R, dq_mode }
 262 #define Rm { OP_R, m_mode }
 263 #define Ib { OP_I, b_mode }
 264 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 265 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 266 #define Iv { OP_I, v_mode }
 267 #define sIv { OP_sI, v_mode }
 268 #define Iq { OP_I, q_mode }
 269 #define Iv64 { OP_I64, v_mode }
 270 #define Iw { OP_I, w_mode }
 271 #define I1 { OP_I, const_1_mode }
 272 #define Jb { OP_J, b_mode }
 273 #define Jv { OP_J, v_mode }
 274 #define Cm { OP_C, m_mode }
 275 #define Dm { OP_D, m_mode }
 276 #define Td { OP_T, d_mode }
 277 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 278
 279 #define RMeAX { OP_REG, eAX_reg }
 280 #define RMeBX { OP_REG, eBX_reg }
 281 #define RMeCX { OP_REG, eCX_reg }
 282 #define RMeDX { OP_REG, eDX_reg }
 283 #define RMeSP { OP_REG, eSP_reg }
 284 #define RMeBP { OP_REG, eBP_reg }
 285 #define RMeSI { OP_REG, eSI_reg }
 286 #define RMeDI { OP_REG, eDI_reg }
 287 #define RMrAX { OP_REG, rAX_reg }
 288 #define RMrBX { OP_REG, rBX_reg }
 289 #define RMrCX { OP_REG, rCX_reg }
 290 #define RMrDX { OP_REG, rDX_reg }
 291 #define RMrSP { OP_REG, rSP_reg }
 292 #define RMrBP { OP_REG, rBP_reg }
 293 #define RMrSI { OP_REG, rSI_reg }
 294 #define RMrDI { OP_REG, rDI_reg }
 295 #define RMAL { OP_REG, al_reg }
 296 #define RMCL { OP_REG, cl_reg }
 297 #define RMDL { OP_REG, dl_reg }
 298 #define RMBL { OP_REG, bl_reg }
 299 #define RMAH { OP_REG, ah_reg }
 300 #define RMCH { OP_REG, ch_reg }
 301 #define RMDH { OP_REG, dh_reg }
 302 #define RMBH { OP_REG, bh_reg }
 303 #define RMAX { OP_REG, ax_reg }
 304 #define RMDX { OP_REG, dx_reg }
 305
 306 #define eAX { OP_IMREG, eAX_reg }
 307 #define eBX { OP_IMREG, eBX_reg }
 308 #define eCX { OP_IMREG, eCX_reg }
 309 #define eDX { OP_IMREG, eDX_reg }
 310 #define eSP { OP_IMREG, eSP_reg }
 311 #define eBP { OP_IMREG, eBP_reg }
 312 #define eSI { OP_IMREG, eSI_reg }
 313 #define eDI { OP_IMREG, eDI_reg }
 314 #define AL { OP_IMREG, al_reg }
 315 #define CL { OP_IMREG, cl_reg }
 316 #define DL { OP_IMREG, dl_reg }
 317 #define BL { OP_IMREG, bl_reg }
 318 #define AH { OP_IMREG, ah_reg }
 319 #define CH { OP_IMREG, ch_reg }
 320 #define DH { OP_IMREG, dh_reg }
 321 #define BH { OP_IMREG, bh_reg }
 322 #define AX { OP_IMREG, ax_reg }
 323 #define DX { OP_IMREG, dx_reg }
 324 #define zAX { OP_IMREG, z_mode_ax_reg }
 325 #define indirDX { OP_IMREG, indir_dx_reg }
 326
 327 #define Sw { OP_SEG, w_mode }
 328 #define Sv { OP_SEG, v_mode }
 329 #define Ap { OP_DIR, 0 }
 330 #define Ob { OP_OFF64, b_mode }
 331 #define Ov { OP_OFF64, v_mode }
 332 #define Xb { OP_DSreg, eSI_reg }
 333 #define Xv { OP_DSreg, eSI_reg }
 334 #define Xz { OP_DSreg, eSI_reg }
 335 #define Yb { OP_ESreg, eDI_reg }
 336 #define Yv { OP_ESreg, eDI_reg }
 337 #define DSBX { OP_DSreg, eBX_reg }
 338
 339 #define es { OP_REG, es_reg }
 340 #define ss { OP_REG, ss_reg }
 341 #define cs { OP_REG, cs_reg }
 342 #define ds { OP_REG, ds_reg }
 343 #define fs { OP_REG, fs_reg }
 344 #define gs { OP_REG, gs_reg }
 345
 346 #define MX { OP_MMX, 0 }
 347 #define XM { OP_XMM, 0 }
 348 #define XMScalar { OP_XMM, scalar_mode }
 349 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 350 #define XMM { OP_XMM, xmm_mode }
 351 #define XMxmmq { OP_XMM, xmmq_mode }
 352 #define EM { OP_EM, v_mode }
 353 #define EMS { OP_EM, v_swap_mode }
 354 #define EMd { OP_EM, d_mode }
 355 #define EMx { OP_EM, x_mode }
 356 #define EXw { OP_EX, w_mode }
 357 #define EXd { OP_EX, d_mode }
 358 #define EXdScalar { OP_EX, d_scalar_mode }
 359 #define EXdS { OP_EX, d_swap_mode }
 360 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 361 #define EXq { OP_EX, q_mode }
 362 #define EXqScalar { OP_EX, q_scalar_mode }
 363 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 364 #define EXqS { OP_EX, q_swap_mode }
 365 #define EXx { OP_EX, x_mode }
 366 #define EXxS { OP_EX, x_swap_mode }
 367 #define EXxmm { OP_EX, xmm_mode }
 368 #define EXymm { OP_EX, ymm_mode }
 369 #define EXxmmq { OP_EX, xmmq_mode }
 370 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 371 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 372 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 373 #define EXxmm_md { OP_EX, xmm_md_mode }
 374 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 375 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 376 #define EXxmmdw { OP_EX, xmmdw_mode }
 377 #define EXxmmqd { OP_EX, xmmqd_mode }
 378 #define EXymmq { OP_EX, ymmq_mode }
 379 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 380 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 381 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 382 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 383 #define MS { OP_MS, v_mode }
 384 #define XS { OP_XS, v_mode }
 385 #define EMCq { OP_EMC, q_mode }
 386 #define MXC { OP_MXC, 0 }
 387 #define OPSUF { OP_3DNowSuffix, 0 }
 388 #define CMP { CMP_Fixup, 0 }
 389 #define XMM0 { XMM_Fixup, 0 }
 390 #define FXSAVE { FXSAVE_Fixup, 0 }
 391 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 392 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 393
 394 #define Vex { OP_VEX, vex_mode }
 395 #define VexScalar { OP_VEX, vex_scalar_mode }
 396 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 397 #define Vex128 { OP_VEX, vex128_mode }
 398 #define Vex256 { OP_VEX, vex256_mode }
 399 #define VexGdq { OP_VEX, dq_mode }
 400 #define VexI4 { VEXI4_Fixup, 0}
 401 #define EXdVex { OP_EX_Vex, d_mode }
 402 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 403 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 404 #define EXqVex { OP_EX_Vex, q_mode }
 405 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 406 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 407 #define EXVexW { OP_EX_VexW, x_mode }
 408 #define EXdVexW { OP_EX_VexW, d_mode }
 409 #define EXqVexW { OP_EX_VexW, q_mode }
 410 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 411 #define XMVex { OP_XMM_Vex, 0 }
 412 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 413 #define XMVexW { OP_XMM_VexW, 0 }
 414 #define XMVexI4 { OP_REG_VexI4, x_mode }
 415 #define PCLMUL { PCLMUL_Fixup, 0 }
 416 #define VZERO { VZERO_Fixup, 0 }
 417 #define VCMP { VCMP_Fixup, 0 }
 418 #define VPCMP { VPCMP_Fixup, 0 }
 419
 420 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 421 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 422
 423 #define XMask { OP_Mask, mask_mode }
 424 #define MaskG { OP_G, mask_mode }
 425 #define MaskE { OP_E, mask_mode }
 426 #define MaskR { OP_R, mask_mode }
 427 #define MaskVex { OP_VEX, mask_mode }
 428
 429 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 430 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 431 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 432 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 433
 434 /* Used handle "rep" prefix for string instructions.  */
 435 #define Xbr { REP_Fixup, eSI_reg }
 436 #define Xvr { REP_Fixup, eSI_reg }
 437 #define Ybr { REP_Fixup, eDI_reg }
 438 #define Yvr { REP_Fixup, eDI_reg }
 439 #define Yzr { REP_Fixup, eDI_reg }
 440 #define indirDXr { REP_Fixup, indir_dx_reg }
 441 #define ALr { REP_Fixup, al_reg }
 442 #define eAXr { REP_Fixup, eAX_reg }
 443
 444 /* Used handle HLE prefix for lockable instructions.  */
 445 #define Ebh1 { HLE_Fixup1, b_mode }
 446 #define Evh1 { HLE_Fixup1, v_mode }
 447 #define Ebh2 { HLE_Fixup2, b_mode }
 448 #define Evh2 { HLE_Fixup2, v_mode }
 449 #define Ebh3 { HLE_Fixup3, b_mode }
 450 #define Evh3 { HLE_Fixup3, v_mode }
 451
 452 #define BND { BND_Fixup, 0 }
 453
 454 #define cond_jump_flag { NULL, cond_jump_mode }
 455 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 456
 457 /* bits in sizeflag */
 458 #define SUFFIX_ALWAYS 4
 459 #define AFLAG 2
 460 #define DFLAG 1
 461
 462 enum
 463 {
 464   /* byte operand */
 465   b_mode = 1,
 466   /* byte operand with operand swapped */
 467   b_swap_mode,
 468   /* byte operand, sign extend like 'T' suffix */
 469   b_T_mode,
 470   /* operand size depends on prefixes */
 471   v_mode,
 472   /* operand size depends on prefixes with operand swapped */
 473   v_swap_mode,
 474   /* word operand */
 475   w_mode,
 476   /* double word operand  */
 477   d_mode,
 478   /* double word operand with operand swapped */
 479   d_swap_mode,
 480   /* quad word operand */
 481   q_mode,
 482   /* quad word operand with operand swapped */
 483   q_swap_mode,
 484   /* ten-byte operand */
 485   t_mode,
 486   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 487      broadcast enabled.  */
 488   x_mode,
 489   /* Similar to x_mode, but with different EVEX mem shifts.  */
 490   evex_x_gscat_mode,
 491   /* Similar to x_mode, but with disabled broadcast.  */
 492   evex_x_nobcst_mode,
 493   /* Similar to x_mode, but with operands swapped and disabled broadcast
 494      in EVEX.  */
 495   x_swap_mode,
 496   /* 16-byte XMM operand */
 497   xmm_mode,
 498   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 499      memory operand (depending on vector length).  Broadcast isn't
 500      allowed.  */
 501   xmmq_mode,
 502   /* Same as xmmq_mode, but broadcast is allowed.  */
 503   evex_half_bcst_xmmq_mode,
 504   /* XMM register or byte memory operand */
 505   xmm_mb_mode,
 506   /* XMM register or word memory operand */
 507   xmm_mw_mode,
 508   /* XMM register or double word memory operand */
 509   xmm_md_mode,
 510   /* XMM register or quad word memory operand */
 511   xmm_mq_mode,
 512   /* XMM register or double/quad word memory operand, depending on
 513      VEX.W.  */
 514   xmm_mdq_mode,
 515   /* 16-byte XMM, word, double word or quad word operand.  */
 516   xmmdw_mode,
 517   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 518   xmmqd_mode,
 519   /* 32-byte YMM operand */
 520   ymm_mode,
 521   /* quad word, ymmword or zmmword memory operand.  */
 522   ymmq_mode,
 523   /* 32-byte YMM or 16-byte word operand */
 524   ymmxmm_mode,
 525   /* d_mode in 32bit, q_mode in 64bit mode.  */
 526   m_mode,
 527   /* pair of v_mode operands */
 528   a_mode,
 529   cond_jump_mode,
 530   loop_jcxz_mode,
 531   v_bnd_mode,
 532   /* operand size depends on REX prefixes.  */
 533   dq_mode,
 534   /* registers like dq_mode, memory like w_mode.  */
 535   dqw_mode,
 536   bnd_mode,
 537   /* 4- or 6-byte pointer operand */
 538   f_mode,
 539   const_1_mode,
 540   /* v_mode for stack-related opcodes.  */
 541   stack_v_mode,
 542   /* non-quad operand size depends on prefixes */
 543   z_mode,
 544   /* 16-byte operand */
 545   o_mode,
 546   /* registers like dq_mode, memory like b_mode.  */
 547   dqb_mode,
 548   /* registers like dq_mode, memory like d_mode.  */
 549   dqd_mode,
 550   /* normal vex mode */
 551   vex_mode,
 552   /* 128bit vex mode */
 553   vex128_mode,
 554   /* 256bit vex mode */
 555   vex256_mode,
 556   /* operand size depends on the VEX.W bit.  */
 557   vex_w_dq_mode,
 558
 559   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 560   vex_vsib_d_w_dq_mode,
 561   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 562   vex_vsib_d_w_d_mode,
 563   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 564   vex_vsib_q_w_dq_mode,
 565   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 566   vex_vsib_q_w_d_mode,
 567
 568   /* scalar, ignore vector length.  */
 569   scalar_mode,
 570   /* like d_mode, ignore vector length.  */
 571   d_scalar_mode,
 572   /* like d_swap_mode, ignore vector length.  */
 573   d_scalar_swap_mode,
 574   /* like q_mode, ignore vector length.  */
 575   q_scalar_mode,
 576   /* like q_swap_mode, ignore vector length.  */
 577   q_scalar_swap_mode,
 578   /* like vex_mode, ignore vector length.  */
 579   vex_scalar_mode,
 580   /* like vex_w_dq_mode, ignore vector length.  */
 581   vex_scalar_w_dq_mode,
 582
 583   /* Static rounding.  */
 584   evex_rounding_mode,
 585   /* Supress all exceptions.  */
 586   evex_sae_mode,
 587
 588   /* Mask register operand.  */
 589   mask_mode,
 590
 591   es_reg,
 592   cs_reg,
 593   ss_reg,
 594   ds_reg,
 595   fs_reg,
 596   gs_reg,
 597
 598   eAX_reg,
 599   eCX_reg,
 600   eDX_reg,
 601   eBX_reg,
 602   eSP_reg,
 603   eBP_reg,
 604   eSI_reg,
 605   eDI_reg,
 606
 607   al_reg,
 608   cl_reg,
 609   dl_reg,
 610   bl_reg,
 611   ah_reg,
 612   ch_reg,
 613   dh_reg,
 614   bh_reg,
 615
 616   ax_reg,
 617   cx_reg,
 618   dx_reg,
 619   bx_reg,
 620   sp_reg,
 621   bp_reg,
 622   si_reg,
 623   di_reg,
 624
 625   rAX_reg,
 626   rCX_reg,
 627   rDX_reg,
 628   rBX_reg,
 629   rSP_reg,
 630   rBP_reg,
 631   rSI_reg,
 632   rDI_reg,
 633
 634   z_mode_ax_reg,
 635   indir_dx_reg
 636 };
 637
 638 enum
 639 {
 640   FLOATCODE = 1,
 641   USE_REG_TABLE,
 642   USE_MOD_TABLE,
 643   USE_RM_TABLE,
 644   USE_PREFIX_TABLE,
 645   USE_X86_64_TABLE,
 646   USE_3BYTE_TABLE,
 647   USE_XOP_8F_TABLE,
 648   USE_VEX_C4_TABLE,
 649   USE_VEX_C5_TABLE,
 650   USE_VEX_LEN_TABLE,
 651   USE_VEX_W_TABLE,
 652   USE_EVEX_TABLE
 653 };
 654
 655 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 656
 657 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 658 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 659 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 660 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 661 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 662 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 663 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 664 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 665 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 666 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 667 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 668 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 669 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 670
 671 enum
 672 {
 673   REG_80 = 0,
 674   REG_81,
 675   REG_82,
 676   REG_8F,
 677   REG_C0,
 678   REG_C1,
 679   REG_C6,
 680   REG_C7,
 681   REG_D0,
 682   REG_D1,
 683   REG_D2,
 684   REG_D3,
 685   REG_F6,
 686   REG_F7,
 687   REG_FE,
 688   REG_FF,
 689   REG_0F00,
 690   REG_0F01,
 691   REG_0F0D,
 692   REG_0F18,
 693   REG_0F71,
 694   REG_0F72,
 695   REG_0F73,
 696   REG_0FA6,
 697   REG_0FA7,
 698   REG_0FAE,
 699   REG_0FBA,
 700   REG_0FC7,
 701   REG_VEX_0F71,
 702   REG_VEX_0F72,
 703   REG_VEX_0F73,
 704   REG_VEX_0FAE,
 705   REG_VEX_0F38F3,
 706   REG_XOP_LWPCB,
 707   REG_XOP_LWP,
 708   REG_XOP_TBM_01,
 709   REG_XOP_TBM_02,
 710
 711   REG_EVEX_0F72,
 712   REG_EVEX_0F73,
 713   REG_EVEX_0F38C6,
 714   REG_EVEX_0F38C7
 715 };
 716
 717 enum
 718 {
 719   MOD_8D = 0,
 720   MOD_C6_REG_7,
 721   MOD_C7_REG_7,
 722   MOD_FF_REG_3,
 723   MOD_FF_REG_5,
 724   MOD_0F01_REG_0,
 725   MOD_0F01_REG_1,
 726   MOD_0F01_REG_2,
 727   MOD_0F01_REG_3,
 728   MOD_0F01_REG_7,
 729   MOD_0F12_PREFIX_0,
 730   MOD_0F13,
 731   MOD_0F16_PREFIX_0,
 732   MOD_0F17,
 733   MOD_0F18_REG_0,
 734   MOD_0F18_REG_1,
 735   MOD_0F18_REG_2,
 736   MOD_0F18_REG_3,
 737   MOD_0F18_REG_4,
 738   MOD_0F18_REG_5,
 739   MOD_0F18_REG_6,
 740   MOD_0F18_REG_7,
 741   MOD_0F1A_PREFIX_0,
 742   MOD_0F1B_PREFIX_0,
 743   MOD_0F1B_PREFIX_1,
 744   MOD_0F20,
 745   MOD_0F21,
 746   MOD_0F22,
 747   MOD_0F23,
 748   MOD_0F24,
 749   MOD_0F26,
 750   MOD_0F2B_PREFIX_0,
 751   MOD_0F2B_PREFIX_1,
 752   MOD_0F2B_PREFIX_2,
 753   MOD_0F2B_PREFIX_3,
 754   MOD_0F51,
 755   MOD_0F71_REG_2,
 756   MOD_0F71_REG_4,
 757   MOD_0F71_REG_6,
 758   MOD_0F72_REG_2,
 759   MOD_0F72_REG_4,
 760   MOD_0F72_REG_6,
 761   MOD_0F73_REG_2,
 762   MOD_0F73_REG_3,
 763   MOD_0F73_REG_6,
 764   MOD_0F73_REG_7,
 765   MOD_0FAE_REG_0,
 766   MOD_0FAE_REG_1,
 767   MOD_0FAE_REG_2,
 768   MOD_0FAE_REG_3,
 769   MOD_0FAE_REG_4,
 770   MOD_0FAE_REG_5,
 771   MOD_0FAE_REG_6,
 772   MOD_0FAE_REG_7,
 773   MOD_0FB2,
 774   MOD_0FB4,
 775   MOD_0FB5,
 776   MOD_0FC7_REG_3,
 777   MOD_0FC7_REG_4,
 778   MOD_0FC7_REG_5,
 779   MOD_0FC7_REG_6,
 780   MOD_0FC7_REG_7,
 781   MOD_0FD7,
 782   MOD_0FE7_PREFIX_2,
 783   MOD_0FF0_PREFIX_3,
 784   MOD_0F382A_PREFIX_2,
 785   MOD_62_32BIT,
 786   MOD_C4_32BIT,
 787   MOD_C5_32BIT,
 788   MOD_VEX_0F12_PREFIX_0,
 789   MOD_VEX_0F13,
 790   MOD_VEX_0F16_PREFIX_0,
 791   MOD_VEX_0F17,
 792   MOD_VEX_0F2B,
 793   MOD_VEX_0F50,
 794   MOD_VEX_0F71_REG_2,
 795   MOD_VEX_0F71_REG_4,
 796   MOD_VEX_0F71_REG_6,
 797   MOD_VEX_0F72_REG_2,
 798   MOD_VEX_0F72_REG_4,
 799   MOD_VEX_0F72_REG_6,
 800   MOD_VEX_0F73_REG_2,
 801   MOD_VEX_0F73_REG_3,
 802   MOD_VEX_0F73_REG_6,
 803   MOD_VEX_0F73_REG_7,
 804   MOD_VEX_0FAE_REG_2,
 805   MOD_VEX_0FAE_REG_3,
 806   MOD_VEX_0FD7_PREFIX_2,
 807   MOD_VEX_0FE7_PREFIX_2,
 808   MOD_VEX_0FF0_PREFIX_3,
 809   MOD_VEX_0F381A_PREFIX_2,
 810   MOD_VEX_0F382A_PREFIX_2,
 811   MOD_VEX_0F382C_PREFIX_2,
 812   MOD_VEX_0F382D_PREFIX_2,
 813   MOD_VEX_0F382E_PREFIX_2,
 814   MOD_VEX_0F382F_PREFIX_2,
 815   MOD_VEX_0F385A_PREFIX_2,
 816   MOD_VEX_0F388C_PREFIX_2,
 817   MOD_VEX_0F388E_PREFIX_2,
 818
 819   MOD_EVEX_0F10_PREFIX_1,
 820   MOD_EVEX_0F10_PREFIX_3,
 821   MOD_EVEX_0F11_PREFIX_1,
 822   MOD_EVEX_0F11_PREFIX_3,
 823   MOD_EVEX_0F12_PREFIX_0,
 824   MOD_EVEX_0F16_PREFIX_0,
 825   MOD_EVEX_0F38C6_REG_1,
 826   MOD_EVEX_0F38C6_REG_2,
 827   MOD_EVEX_0F38C6_REG_5,
 828   MOD_EVEX_0F38C6_REG_6,
 829   MOD_EVEX_0F38C7_REG_1,
 830   MOD_EVEX_0F38C7_REG_2,
 831   MOD_EVEX_0F38C7_REG_5,
 832   MOD_EVEX_0F38C7_REG_6
 833 };
 834
 835 enum
 836 {
 837   RM_C6_REG_7 = 0,
 838   RM_C7_REG_7,
 839   RM_0F01_REG_0,
 840   RM_0F01_REG_1,
 841   RM_0F01_REG_2,
 842   RM_0F01_REG_3,
 843   RM_0F01_REG_7,
 844   RM_0FAE_REG_5,
 845   RM_0FAE_REG_6,
 846   RM_0FAE_REG_7
 847 };
 848
 849 enum
 850 {
 851   PREFIX_90 = 0,
 852   PREFIX_0F10,
 853   PREFIX_0F11,
 854   PREFIX_0F12,
 855   PREFIX_0F16,
 856   PREFIX_0F1A,
 857   PREFIX_0F1B,
 858   PREFIX_0F2A,
 859   PREFIX_0F2B,
 860   PREFIX_0F2C,
 861   PREFIX_0F2D,
 862   PREFIX_0F2E,
 863   PREFIX_0F2F,
 864   PREFIX_0F51,
 865   PREFIX_0F52,
 866   PREFIX_0F53,
 867   PREFIX_0F58,
 868   PREFIX_0F59,
 869   PREFIX_0F5A,
 870   PREFIX_0F5B,
 871   PREFIX_0F5C,
 872   PREFIX_0F5D,
 873   PREFIX_0F5E,
 874   PREFIX_0F5F,
 875   PREFIX_0F60,
 876   PREFIX_0F61,
 877   PREFIX_0F62,
 878   PREFIX_0F6C,
 879   PREFIX_0F6D,
 880   PREFIX_0F6F,
 881   PREFIX_0F70,
 882   PREFIX_0F73_REG_3,
 883   PREFIX_0F73_REG_7,
 884   PREFIX_0F78,
 885   PREFIX_0F79,
 886   PREFIX_0F7C,
 887   PREFIX_0F7D,
 888   PREFIX_0F7E,
 889   PREFIX_0F7F,
 890   PREFIX_0FAE_REG_0,
 891   PREFIX_0FAE_REG_1,
 892   PREFIX_0FAE_REG_2,
 893   PREFIX_0FAE_REG_3,
 894   PREFIX_0FAE_REG_7,
 895   PREFIX_0FB8,
 896   PREFIX_0FBC,
 897   PREFIX_0FBD,
 898   PREFIX_0FC2,
 899   PREFIX_0FC3,
 900   PREFIX_0FC7_REG_6,
 901   PREFIX_0FD0,
 902   PREFIX_0FD6,
 903   PREFIX_0FE6,
 904   PREFIX_0FE7,
 905   PREFIX_0FF0,
 906   PREFIX_0FF7,
 907   PREFIX_0F3810,
 908   PREFIX_0F3814,
 909   PREFIX_0F3815,
 910   PREFIX_0F3817,
 911   PREFIX_0F3820,
 912   PREFIX_0F3821,
 913   PREFIX_0F3822,
 914   PREFIX_0F3823,
 915   PREFIX_0F3824,
 916   PREFIX_0F3825,
 917   PREFIX_0F3828,
 918   PREFIX_0F3829,
 919   PREFIX_0F382A,
 920   PREFIX_0F382B,
 921   PREFIX_0F3830,
 922   PREFIX_0F3831,
 923   PREFIX_0F3832,
 924   PREFIX_0F3833,
 925   PREFIX_0F3834,
 926   PREFIX_0F3835,
 927   PREFIX_0F3837,
 928   PREFIX_0F3838,
 929   PREFIX_0F3839,
 930   PREFIX_0F383A,
 931   PREFIX_0F383B,
 932   PREFIX_0F383C,
 933   PREFIX_0F383D,
 934   PREFIX_0F383E,
 935   PREFIX_0F383F,
 936   PREFIX_0F3840,
 937   PREFIX_0F3841,
 938   PREFIX_0F3880,
 939   PREFIX_0F3881,
 940   PREFIX_0F3882,
 941   PREFIX_0F38C8,
 942   PREFIX_0F38C9,
 943   PREFIX_0F38CA,
 944   PREFIX_0F38CB,
 945   PREFIX_0F38CC,
 946   PREFIX_0F38CD,
 947   PREFIX_0F38DB,
 948   PREFIX_0F38DC,
 949   PREFIX_0F38DD,
 950   PREFIX_0F38DE,
 951   PREFIX_0F38DF,
 952   PREFIX_0F38F0,
 953   PREFIX_0F38F1,
 954   PREFIX_0F38F6,
 955   PREFIX_0F3A08,
 956   PREFIX_0F3A09,
 957   PREFIX_0F3A0A,
 958   PREFIX_0F3A0B,
 959   PREFIX_0F3A0C,
 960   PREFIX_0F3A0D,
 961   PREFIX_0F3A0E,
 962   PREFIX_0F3A14,
 963   PREFIX_0F3A15,
 964   PREFIX_0F3A16,
 965   PREFIX_0F3A17,
 966   PREFIX_0F3A20,
 967   PREFIX_0F3A21,
 968   PREFIX_0F3A22,
 969   PREFIX_0F3A40,
 970   PREFIX_0F3A41,
 971   PREFIX_0F3A42,
 972   PREFIX_0F3A44,
 973   PREFIX_0F3A60,
 974   PREFIX_0F3A61,
 975   PREFIX_0F3A62,
 976   PREFIX_0F3A63,
 977   PREFIX_0F3ACC,
 978   PREFIX_0F3ADF,
 979   PREFIX_VEX_0F10,
 980   PREFIX_VEX_0F11,
 981   PREFIX_VEX_0F12,
 982   PREFIX_VEX_0F16,
 983   PREFIX_VEX_0F2A,
 984   PREFIX_VEX_0F2C,
 985   PREFIX_VEX_0F2D,
 986   PREFIX_VEX_0F2E,
 987   PREFIX_VEX_0F2F,
 988   PREFIX_VEX_0F41,
 989   PREFIX_VEX_0F42,
 990   PREFIX_VEX_0F44,
 991   PREFIX_VEX_0F45,
 992   PREFIX_VEX_0F46,
 993   PREFIX_VEX_0F47,
 994   PREFIX_VEX_0F4B,
 995   PREFIX_VEX_0F51,
 996   PREFIX_VEX_0F52,
 997   PREFIX_VEX_0F53,
 998   PREFIX_VEX_0F58,
 999   PREFIX_VEX_0F59,
1000   PREFIX_VEX_0F5A,
1001   PREFIX_VEX_0F5B,
1002   PREFIX_VEX_0F5C,
1003   PREFIX_VEX_0F5D,
1004   PREFIX_VEX_0F5E,
1005   PREFIX_VEX_0F5F,
1006   PREFIX_VEX_0F60,
1007   PREFIX_VEX_0F61,
1008   PREFIX_VEX_0F62,
1009   PREFIX_VEX_0F63,
1010   PREFIX_VEX_0F64,
1011   PREFIX_VEX_0F65,
1012   PREFIX_VEX_0F66,
1013   PREFIX_VEX_0F67,
1014   PREFIX_VEX_0F68,
1015   PREFIX_VEX_0F69,
1016   PREFIX_VEX_0F6A,
1017   PREFIX_VEX_0F6B,
1018   PREFIX_VEX_0F6C,
1019   PREFIX_VEX_0F6D,
1020   PREFIX_VEX_0F6E,
1021   PREFIX_VEX_0F6F,
1022   PREFIX_VEX_0F70,
1023   PREFIX_VEX_0F71_REG_2,
1024   PREFIX_VEX_0F71_REG_4,
1025   PREFIX_VEX_0F71_REG_6,
1026   PREFIX_VEX_0F72_REG_2,
1027   PREFIX_VEX_0F72_REG_4,
1028   PREFIX_VEX_0F72_REG_6,
1029   PREFIX_VEX_0F73_REG_2,
1030   PREFIX_VEX_0F73_REG_3,
1031   PREFIX_VEX_0F73_REG_6,
1032   PREFIX_VEX_0F73_REG_7,
1033   PREFIX_VEX_0F74,
1034   PREFIX_VEX_0F75,
1035   PREFIX_VEX_0F76,
1036   PREFIX_VEX_0F77,
1037   PREFIX_VEX_0F7C,
1038   PREFIX_VEX_0F7D,
1039   PREFIX_VEX_0F7E,
1040   PREFIX_VEX_0F7F,
1041   PREFIX_VEX_0F90,
1042   PREFIX_VEX_0F91,
1043   PREFIX_VEX_0F92,
1044   PREFIX_VEX_0F93,
1045   PREFIX_VEX_0F98,
1046   PREFIX_VEX_0FC2,
1047   PREFIX_VEX_0FC4,
1048   PREFIX_VEX_0FC5,
1049   PREFIX_VEX_0FD0,
1050   PREFIX_VEX_0FD1,
1051   PREFIX_VEX_0FD2,
1052   PREFIX_VEX_0FD3,
1053   PREFIX_VEX_0FD4,
1054   PREFIX_VEX_0FD5,
1055   PREFIX_VEX_0FD6,
1056   PREFIX_VEX_0FD7,
1057   PREFIX_VEX_0FD8,
1058   PREFIX_VEX_0FD9,
1059   PREFIX_VEX_0FDA,
1060   PREFIX_VEX_0FDB,
1061   PREFIX_VEX_0FDC,
1062   PREFIX_VEX_0FDD,
1063   PREFIX_VEX_0FDE,
1064   PREFIX_VEX_0FDF,
1065   PREFIX_VEX_0FE0,
1066   PREFIX_VEX_0FE1,
1067   PREFIX_VEX_0FE2,
1068   PREFIX_VEX_0FE3,
1069   PREFIX_VEX_0FE4,
1070   PREFIX_VEX_0FE5,
1071   PREFIX_VEX_0FE6,
1072   PREFIX_VEX_0FE7,
1073   PREFIX_VEX_0FE8,
1074   PREFIX_VEX_0FE9,
1075   PREFIX_VEX_0FEA,
1076   PREFIX_VEX_0FEB,
1077   PREFIX_VEX_0FEC,
1078   PREFIX_VEX_0FED,
1079   PREFIX_VEX_0FEE,
1080   PREFIX_VEX_0FEF,
1081   PREFIX_VEX_0FF0,
1082   PREFIX_VEX_0FF1,
1083   PREFIX_VEX_0FF2,
1084   PREFIX_VEX_0FF3,
1085   PREFIX_VEX_0FF4,
1086   PREFIX_VEX_0FF5,
1087   PREFIX_VEX_0FF6,
1088   PREFIX_VEX_0FF7,
1089   PREFIX_VEX_0FF8,
1090   PREFIX_VEX_0FF9,
1091   PREFIX_VEX_0FFA,
1092   PREFIX_VEX_0FFB,
1093   PREFIX_VEX_0FFC,
1094   PREFIX_VEX_0FFD,
1095   PREFIX_VEX_0FFE,
1096   PREFIX_VEX_0F3800,
1097   PREFIX_VEX_0F3801,
1098   PREFIX_VEX_0F3802,
1099   PREFIX_VEX_0F3803,
1100   PREFIX_VEX_0F3804,
1101   PREFIX_VEX_0F3805,
1102   PREFIX_VEX_0F3806,
1103   PREFIX_VEX_0F3807,
1104   PREFIX_VEX_0F3808,
1105   PREFIX_VEX_0F3809,
1106   PREFIX_VEX_0F380A,
1107   PREFIX_VEX_0F380B,
1108   PREFIX_VEX_0F380C,
1109   PREFIX_VEX_0F380D,
1110   PREFIX_VEX_0F380E,
1111   PREFIX_VEX_0F380F,
1112   PREFIX_VEX_0F3813,
1113   PREFIX_VEX_0F3816,
1114   PREFIX_VEX_0F3817,
1115   PREFIX_VEX_0F3818,
1116   PREFIX_VEX_0F3819,
1117   PREFIX_VEX_0F381A,
1118   PREFIX_VEX_0F381C,
1119   PREFIX_VEX_0F381D,
1120   PREFIX_VEX_0F381E,
1121   PREFIX_VEX_0F3820,
1122   PREFIX_VEX_0F3821,
1123   PREFIX_VEX_0F3822,
1124   PREFIX_VEX_0F3823,
1125   PREFIX_VEX_0F3824,
1126   PREFIX_VEX_0F3825,
1127   PREFIX_VEX_0F3828,
1128   PREFIX_VEX_0F3829,
1129   PREFIX_VEX_0F382A,
1130   PREFIX_VEX_0F382B,
1131   PREFIX_VEX_0F382C,
1132   PREFIX_VEX_0F382D,
1133   PREFIX_VEX_0F382E,
1134   PREFIX_VEX_0F382F,
1135   PREFIX_VEX_0F3830,
1136   PREFIX_VEX_0F3831,
1137   PREFIX_VEX_0F3832,
1138   PREFIX_VEX_0F3833,
1139   PREFIX_VEX_0F3834,
1140   PREFIX_VEX_0F3835,
1141   PREFIX_VEX_0F3836,
1142   PREFIX_VEX_0F3837,
1143   PREFIX_VEX_0F3838,
1144   PREFIX_VEX_0F3839,
1145   PREFIX_VEX_0F383A,
1146   PREFIX_VEX_0F383B,
1147   PREFIX_VEX_0F383C,
1148   PREFIX_VEX_0F383D,
1149   PREFIX_VEX_0F383E,
1150   PREFIX_VEX_0F383F,
1151   PREFIX_VEX_0F3840,
1152   PREFIX_VEX_0F3841,
1153   PREFIX_VEX_0F3845,
1154   PREFIX_VEX_0F3846,
1155   PREFIX_VEX_0F3847,
1156   PREFIX_VEX_0F3858,
1157   PREFIX_VEX_0F3859,
1158   PREFIX_VEX_0F385A,
1159   PREFIX_VEX_0F3878,
1160   PREFIX_VEX_0F3879,
1161   PREFIX_VEX_0F388C,
1162   PREFIX_VEX_0F388E,
1163   PREFIX_VEX_0F3890,
1164   PREFIX_VEX_0F3891,
1165   PREFIX_VEX_0F3892,
1166   PREFIX_VEX_0F3893,
1167   PREFIX_VEX_0F3896,
1168   PREFIX_VEX_0F3897,
1169   PREFIX_VEX_0F3898,
1170   PREFIX_VEX_0F3899,
1171   PREFIX_VEX_0F389A,
1172   PREFIX_VEX_0F389B,
1173   PREFIX_VEX_0F389C,
1174   PREFIX_VEX_0F389D,
1175   PREFIX_VEX_0F389E,
1176   PREFIX_VEX_0F389F,
1177   PREFIX_VEX_0F38A6,
1178   PREFIX_VEX_0F38A7,
1179   PREFIX_VEX_0F38A8,
1180   PREFIX_VEX_0F38A9,
1181   PREFIX_VEX_0F38AA,
1182   PREFIX_VEX_0F38AB,
1183   PREFIX_VEX_0F38AC,
1184   PREFIX_VEX_0F38AD,
1185   PREFIX_VEX_0F38AE,
1186   PREFIX_VEX_0F38AF,
1187   PREFIX_VEX_0F38B6,
1188   PREFIX_VEX_0F38B7,
1189   PREFIX_VEX_0F38B8,
1190   PREFIX_VEX_0F38B9,
1191   PREFIX_VEX_0F38BA,
1192   PREFIX_VEX_0F38BB,
1193   PREFIX_VEX_0F38BC,
1194   PREFIX_VEX_0F38BD,
1195   PREFIX_VEX_0F38BE,
1196   PREFIX_VEX_0F38BF,
1197   PREFIX_VEX_0F38DB,
1198   PREFIX_VEX_0F38DC,
1199   PREFIX_VEX_0F38DD,
1200   PREFIX_VEX_0F38DE,
1201   PREFIX_VEX_0F38DF,
1202   PREFIX_VEX_0F38F2,
1203   PREFIX_VEX_0F38F3_REG_1,
1204   PREFIX_VEX_0F38F3_REG_2,
1205   PREFIX_VEX_0F38F3_REG_3,
1206   PREFIX_VEX_0F38F5,
1207   PREFIX_VEX_0F38F6,
1208   PREFIX_VEX_0F38F7,
1209   PREFIX_VEX_0F3A00,
1210   PREFIX_VEX_0F3A01,
1211   PREFIX_VEX_0F3A02,
1212   PREFIX_VEX_0F3A04,
1213   PREFIX_VEX_0F3A05,
1214   PREFIX_VEX_0F3A06,
1215   PREFIX_VEX_0F3A08,
1216   PREFIX_VEX_0F3A09,
1217   PREFIX_VEX_0F3A0A,
1218   PREFIX_VEX_0F3A0B,
1219   PREFIX_VEX_0F3A0C,
1220   PREFIX_VEX_0F3A0D,
1221   PREFIX_VEX_0F3A0E,
1222   PREFIX_VEX_0F3A0F,
1223   PREFIX_VEX_0F3A14,
1224   PREFIX_VEX_0F3A15,
1225   PREFIX_VEX_0F3A16,
1226   PREFIX_VEX_0F3A17,
1227   PREFIX_VEX_0F3A18,
1228   PREFIX_VEX_0F3A19,
1229   PREFIX_VEX_0F3A1D,
1230   PREFIX_VEX_0F3A20,
1231   PREFIX_VEX_0F3A21,
1232   PREFIX_VEX_0F3A22,
1233   PREFIX_VEX_0F3A30,
1234   PREFIX_VEX_0F3A32,
1235   PREFIX_VEX_0F3A38,
1236   PREFIX_VEX_0F3A39,
1237   PREFIX_VEX_0F3A40,
1238   PREFIX_VEX_0F3A41,
1239   PREFIX_VEX_0F3A42,
1240   PREFIX_VEX_0F3A44,
1241   PREFIX_VEX_0F3A46,
1242   PREFIX_VEX_0F3A48,
1243   PREFIX_VEX_0F3A49,
1244   PREFIX_VEX_0F3A4A,
1245   PREFIX_VEX_0F3A4B,
1246   PREFIX_VEX_0F3A4C,
1247   PREFIX_VEX_0F3A5C,
1248   PREFIX_VEX_0F3A5D,
1249   PREFIX_VEX_0F3A5E,
1250   PREFIX_VEX_0F3A5F,
1251   PREFIX_VEX_0F3A60,
1252   PREFIX_VEX_0F3A61,
1253   PREFIX_VEX_0F3A62,
1254   PREFIX_VEX_0F3A63,
1255   PREFIX_VEX_0F3A68,
1256   PREFIX_VEX_0F3A69,
1257   PREFIX_VEX_0F3A6A,
1258   PREFIX_VEX_0F3A6B,
1259   PREFIX_VEX_0F3A6C,
1260   PREFIX_VEX_0F3A6D,
1261   PREFIX_VEX_0F3A6E,
1262   PREFIX_VEX_0F3A6F,
1263   PREFIX_VEX_0F3A78,
1264   PREFIX_VEX_0F3A79,
1265   PREFIX_VEX_0F3A7A,
1266   PREFIX_VEX_0F3A7B,
1267   PREFIX_VEX_0F3A7C,
1268   PREFIX_VEX_0F3A7D,
1269   PREFIX_VEX_0F3A7E,
1270   PREFIX_VEX_0F3A7F,
1271   PREFIX_VEX_0F3ADF,
1272   PREFIX_VEX_0F3AF0,
1273
1274   PREFIX_EVEX_0F10,
1275   PREFIX_EVEX_0F11,
1276   PREFIX_EVEX_0F12,
1277   PREFIX_EVEX_0F13,
1278   PREFIX_EVEX_0F14,
1279   PREFIX_EVEX_0F15,
1280   PREFIX_EVEX_0F16,
1281   PREFIX_EVEX_0F17,
1282   PREFIX_EVEX_0F28,
1283   PREFIX_EVEX_0F29,
1284   PREFIX_EVEX_0F2A,
1285   PREFIX_EVEX_0F2B,
1286   PREFIX_EVEX_0F2C,
1287   PREFIX_EVEX_0F2D,
1288   PREFIX_EVEX_0F2E,
1289   PREFIX_EVEX_0F2F,
1290   PREFIX_EVEX_0F51,
1291   PREFIX_EVEX_0F58,
1292   PREFIX_EVEX_0F59,
1293   PREFIX_EVEX_0F5A,
1294   PREFIX_EVEX_0F5B,
1295   PREFIX_EVEX_0F5C,
1296   PREFIX_EVEX_0F5D,
1297   PREFIX_EVEX_0F5E,
1298   PREFIX_EVEX_0F5F,
1299   PREFIX_EVEX_0F62,
1300   PREFIX_EVEX_0F66,
1301   PREFIX_EVEX_0F6A,
1302   PREFIX_EVEX_0F6C,
1303   PREFIX_EVEX_0F6D,
1304   PREFIX_EVEX_0F6E,
1305   PREFIX_EVEX_0F6F,
1306   PREFIX_EVEX_0F70,
1307   PREFIX_EVEX_0F72_REG_0,
1308   PREFIX_EVEX_0F72_REG_1,
1309   PREFIX_EVEX_0F72_REG_2,
1310   PREFIX_EVEX_0F72_REG_4,
1311   PREFIX_EVEX_0F72_REG_6,
1312   PREFIX_EVEX_0F73_REG_2,
1313   PREFIX_EVEX_0F73_REG_6,
1314   PREFIX_EVEX_0F76,
1315   PREFIX_EVEX_0F78,
1316   PREFIX_EVEX_0F79,
1317   PREFIX_EVEX_0F7A,
1318   PREFIX_EVEX_0F7B,
1319   PREFIX_EVEX_0F7E,
1320   PREFIX_EVEX_0F7F,
1321   PREFIX_EVEX_0FC2,
1322   PREFIX_EVEX_0FC6,
1323   PREFIX_EVEX_0FD2,
1324   PREFIX_EVEX_0FD3,
1325   PREFIX_EVEX_0FD4,
1326   PREFIX_EVEX_0FD6,
1327   PREFIX_EVEX_0FDB,
1328   PREFIX_EVEX_0FDF,
1329   PREFIX_EVEX_0FE2,
1330   PREFIX_EVEX_0FE6,
1331   PREFIX_EVEX_0FE7,
1332   PREFIX_EVEX_0FEB,
1333   PREFIX_EVEX_0FEF,
1334   PREFIX_EVEX_0FF2,
1335   PREFIX_EVEX_0FF3,
1336   PREFIX_EVEX_0FF4,
1337   PREFIX_EVEX_0FFA,
1338   PREFIX_EVEX_0FFB,
1339   PREFIX_EVEX_0FFE,
1340   PREFIX_EVEX_0F380C,
1341   PREFIX_EVEX_0F380D,
1342   PREFIX_EVEX_0F3811,
1343   PREFIX_EVEX_0F3812,
1344   PREFIX_EVEX_0F3813,
1345   PREFIX_EVEX_0F3814,
1346   PREFIX_EVEX_0F3815,
1347   PREFIX_EVEX_0F3816,
1348   PREFIX_EVEX_0F3818,
1349   PREFIX_EVEX_0F3819,
1350   PREFIX_EVEX_0F381A,
1351   PREFIX_EVEX_0F381B,
1352   PREFIX_EVEX_0F381E,
1353   PREFIX_EVEX_0F381F,
1354   PREFIX_EVEX_0F3821,
1355   PREFIX_EVEX_0F3822,
1356   PREFIX_EVEX_0F3823,
1357   PREFIX_EVEX_0F3824,
1358   PREFIX_EVEX_0F3825,
1359   PREFIX_EVEX_0F3827,
1360   PREFIX_EVEX_0F3828,
1361   PREFIX_EVEX_0F3829,
1362   PREFIX_EVEX_0F382A,
1363   PREFIX_EVEX_0F382C,
1364   PREFIX_EVEX_0F382D,
1365   PREFIX_EVEX_0F3831,
1366   PREFIX_EVEX_0F3832,
1367   PREFIX_EVEX_0F3833,
1368   PREFIX_EVEX_0F3834,
1369   PREFIX_EVEX_0F3835,
1370   PREFIX_EVEX_0F3836,
1371   PREFIX_EVEX_0F3837,
1372   PREFIX_EVEX_0F3839,
1373   PREFIX_EVEX_0F383A,
1374   PREFIX_EVEX_0F383B,
1375   PREFIX_EVEX_0F383D,
1376   PREFIX_EVEX_0F383F,
1377   PREFIX_EVEX_0F3840,
1378   PREFIX_EVEX_0F3842,
1379   PREFIX_EVEX_0F3843,
1380   PREFIX_EVEX_0F3844,
1381   PREFIX_EVEX_0F3845,
1382   PREFIX_EVEX_0F3846,
1383   PREFIX_EVEX_0F3847,
1384   PREFIX_EVEX_0F384C,
1385   PREFIX_EVEX_0F384D,
1386   PREFIX_EVEX_0F384E,
1387   PREFIX_EVEX_0F384F,
1388   PREFIX_EVEX_0F3858,
1389   PREFIX_EVEX_0F3859,
1390   PREFIX_EVEX_0F385A,
1391   PREFIX_EVEX_0F385B,
1392   PREFIX_EVEX_0F3864,
1393   PREFIX_EVEX_0F3865,
1394   PREFIX_EVEX_0F3876,
1395   PREFIX_EVEX_0F3877,
1396   PREFIX_EVEX_0F387C,
1397   PREFIX_EVEX_0F387E,
1398   PREFIX_EVEX_0F387F,
1399   PREFIX_EVEX_0F3888,
1400   PREFIX_EVEX_0F3889,
1401   PREFIX_EVEX_0F388A,
1402   PREFIX_EVEX_0F388B,
1403   PREFIX_EVEX_0F3890,
1404   PREFIX_EVEX_0F3891,
1405   PREFIX_EVEX_0F3892,
1406   PREFIX_EVEX_0F3893,
1407   PREFIX_EVEX_0F3896,
1408   PREFIX_EVEX_0F3897,
1409   PREFIX_EVEX_0F3898,
1410   PREFIX_EVEX_0F3899,
1411   PREFIX_EVEX_0F389A,
1412   PREFIX_EVEX_0F389B,
1413   PREFIX_EVEX_0F389C,
1414   PREFIX_EVEX_0F389D,
1415   PREFIX_EVEX_0F389E,
1416   PREFIX_EVEX_0F389F,
1417   PREFIX_EVEX_0F38A0,
1418   PREFIX_EVEX_0F38A1,
1419   PREFIX_EVEX_0F38A2,
1420   PREFIX_EVEX_0F38A3,
1421   PREFIX_EVEX_0F38A6,
1422   PREFIX_EVEX_0F38A7,
1423   PREFIX_EVEX_0F38A8,
1424   PREFIX_EVEX_0F38A9,
1425   PREFIX_EVEX_0F38AA,
1426   PREFIX_EVEX_0F38AB,
1427   PREFIX_EVEX_0F38AC,
1428   PREFIX_EVEX_0F38AD,
1429   PREFIX_EVEX_0F38AE,
1430   PREFIX_EVEX_0F38AF,
1431   PREFIX_EVEX_0F38B6,
1432   PREFIX_EVEX_0F38B7,
1433   PREFIX_EVEX_0F38B8,
1434   PREFIX_EVEX_0F38B9,
1435   PREFIX_EVEX_0F38BA,
1436   PREFIX_EVEX_0F38BB,
1437   PREFIX_EVEX_0F38BC,
1438   PREFIX_EVEX_0F38BD,
1439   PREFIX_EVEX_0F38BE,
1440   PREFIX_EVEX_0F38BF,
1441   PREFIX_EVEX_0F38C4,
1442   PREFIX_EVEX_0F38C6_REG_1,
1443   PREFIX_EVEX_0F38C6_REG_2,
1444   PREFIX_EVEX_0F38C6_REG_5,
1445   PREFIX_EVEX_0F38C6_REG_6,
1446   PREFIX_EVEX_0F38C7_REG_1,
1447   PREFIX_EVEX_0F38C7_REG_2,
1448   PREFIX_EVEX_0F38C7_REG_5,
1449   PREFIX_EVEX_0F38C7_REG_6,
1450   PREFIX_EVEX_0F38C8,
1451   PREFIX_EVEX_0F38CA,
1452   PREFIX_EVEX_0F38CB,
1453   PREFIX_EVEX_0F38CC,
1454   PREFIX_EVEX_0F38CD,
1455
1456   PREFIX_EVEX_0F3A00,
1457   PREFIX_EVEX_0F3A01,
1458   PREFIX_EVEX_0F3A03,
1459   PREFIX_EVEX_0F3A04,
1460   PREFIX_EVEX_0F3A05,
1461   PREFIX_EVEX_0F3A08,
1462   PREFIX_EVEX_0F3A09,
1463   PREFIX_EVEX_0F3A0A,
1464   PREFIX_EVEX_0F3A0B,
1465   PREFIX_EVEX_0F3A17,
1466   PREFIX_EVEX_0F3A18,
1467   PREFIX_EVEX_0F3A19,
1468   PREFIX_EVEX_0F3A1A,
1469   PREFIX_EVEX_0F3A1B,
1470   PREFIX_EVEX_0F3A1D,
1471   PREFIX_EVEX_0F3A1E,
1472   PREFIX_EVEX_0F3A1F,
1473   PREFIX_EVEX_0F3A21,
1474   PREFIX_EVEX_0F3A23,
1475   PREFIX_EVEX_0F3A25,
1476   PREFIX_EVEX_0F3A26,
1477   PREFIX_EVEX_0F3A27,
1478   PREFIX_EVEX_0F3A38,
1479   PREFIX_EVEX_0F3A39,
1480   PREFIX_EVEX_0F3A3A,
1481   PREFIX_EVEX_0F3A3B,
1482   PREFIX_EVEX_0F3A43,
1483   PREFIX_EVEX_0F3A54,
1484   PREFIX_EVEX_0F3A55,
1485 };
1486
1487 enum
1488 {
1489   X86_64_06 = 0,
1490   X86_64_07,
1491   X86_64_0D,
1492   X86_64_16,
1493   X86_64_17,
1494   X86_64_1E,
1495   X86_64_1F,
1496   X86_64_27,
1497   X86_64_2F,
1498   X86_64_37,
1499   X86_64_3F,
1500   X86_64_60,
1501   X86_64_61,
1502   X86_64_62,
1503   X86_64_63,
1504   X86_64_6D,
1505   X86_64_6F,
1506   X86_64_9A,
1507   X86_64_C4,
1508   X86_64_C5,
1509   X86_64_CE,
1510   X86_64_D4,
1511   X86_64_D5,
1512   X86_64_EA,
1513   X86_64_0F01_REG_0,
1514   X86_64_0F01_REG_1,
1515   X86_64_0F01_REG_2,
1516   X86_64_0F01_REG_3
1517 };
1518
1519 enum
1520 {
1521   THREE_BYTE_0F38 = 0,
1522   THREE_BYTE_0F3A,
1523   THREE_BYTE_0F7A
1524 };
1525
1526 enum
1527 {
1528   XOP_08 = 0,
1529   XOP_09,
1530   XOP_0A
1531 };
1532
1533 enum
1534 {
1535   VEX_0F = 0,
1536   VEX_0F38,
1537   VEX_0F3A
1538 };
1539
1540 enum
1541 {
1542   EVEX_0F = 0,
1543   EVEX_0F38,
1544   EVEX_0F3A
1545 };
1546
1547 enum
1548 {
1549   VEX_LEN_0F10_P_1 = 0,
1550   VEX_LEN_0F10_P_3,
1551   VEX_LEN_0F11_P_1,
1552   VEX_LEN_0F11_P_3,
1553   VEX_LEN_0F12_P_0_M_0,
1554   VEX_LEN_0F12_P_0_M_1,
1555   VEX_LEN_0F12_P_2,
1556   VEX_LEN_0F13_M_0,
1557   VEX_LEN_0F16_P_0_M_0,
1558   VEX_LEN_0F16_P_0_M_1,
1559   VEX_LEN_0F16_P_2,
1560   VEX_LEN_0F17_M_0,
1561   VEX_LEN_0F2A_P_1,
1562   VEX_LEN_0F2A_P_3,
1563   VEX_LEN_0F2C_P_1,
1564   VEX_LEN_0F2C_P_3,
1565   VEX_LEN_0F2D_P_1,
1566   VEX_LEN_0F2D_P_3,
1567   VEX_LEN_0F2E_P_0,
1568   VEX_LEN_0F2E_P_2,
1569   VEX_LEN_0F2F_P_0,
1570   VEX_LEN_0F2F_P_2,
1571   VEX_LEN_0F41_P_0,
1572   VEX_LEN_0F42_P_0,
1573   VEX_LEN_0F44_P_0,
1574   VEX_LEN_0F45_P_0,
1575   VEX_LEN_0F46_P_0,
1576   VEX_LEN_0F47_P_0,
1577   VEX_LEN_0F4B_P_2,
1578   VEX_LEN_0F51_P_1,
1579   VEX_LEN_0F51_P_3,
1580   VEX_LEN_0F52_P_1,
1581   VEX_LEN_0F53_P_1,
1582   VEX_LEN_0F58_P_1,
1583   VEX_LEN_0F58_P_3,
1584   VEX_LEN_0F59_P_1,
1585   VEX_LEN_0F59_P_3,
1586   VEX_LEN_0F5A_P_1,
1587   VEX_LEN_0F5A_P_3,
1588   VEX_LEN_0F5C_P_1,
1589   VEX_LEN_0F5C_P_3,
1590   VEX_LEN_0F5D_P_1,
1591   VEX_LEN_0F5D_P_3,
1592   VEX_LEN_0F5E_P_1,
1593   VEX_LEN_0F5E_P_3,
1594   VEX_LEN_0F5F_P_1,
1595   VEX_LEN_0F5F_P_3,
1596   VEX_LEN_0F6E_P_2,
1597   VEX_LEN_0F7E_P_1,
1598   VEX_LEN_0F7E_P_2,
1599   VEX_LEN_0F90_P_0,
1600   VEX_LEN_0F91_P_0,
1601   VEX_LEN_0F92_P_0,
1602   VEX_LEN_0F93_P_0,
1603   VEX_LEN_0F98_P_0,
1604   VEX_LEN_0FAE_R_2_M_0,
1605   VEX_LEN_0FAE_R_3_M_0,
1606   VEX_LEN_0FC2_P_1,
1607   VEX_LEN_0FC2_P_3,
1608   VEX_LEN_0FC4_P_2,
1609   VEX_LEN_0FC5_P_2,
1610   VEX_LEN_0FD6_P_2,
1611   VEX_LEN_0FF7_P_2,
1612   VEX_LEN_0F3816_P_2,
1613   VEX_LEN_0F3819_P_2,
1614   VEX_LEN_0F381A_P_2_M_0,
1615   VEX_LEN_0F3836_P_2,
1616   VEX_LEN_0F3841_P_2,
1617   VEX_LEN_0F385A_P_2_M_0,
1618   VEX_LEN_0F38DB_P_2,
1619   VEX_LEN_0F38DC_P_2,
1620   VEX_LEN_0F38DD_P_2,
1621   VEX_LEN_0F38DE_P_2,
1622   VEX_LEN_0F38DF_P_2,
1623   VEX_LEN_0F38F2_P_0,
1624   VEX_LEN_0F38F3_R_1_P_0,
1625   VEX_LEN_0F38F3_R_2_P_0,
1626   VEX_LEN_0F38F3_R_3_P_0,
1627   VEX_LEN_0F38F5_P_0,
1628   VEX_LEN_0F38F5_P_1,
1629   VEX_LEN_0F38F5_P_3,
1630   VEX_LEN_0F38F6_P_3,
1631   VEX_LEN_0F38F7_P_0,
1632   VEX_LEN_0F38F7_P_1,
1633   VEX_LEN_0F38F7_P_2,
1634   VEX_LEN_0F38F7_P_3,
1635   VEX_LEN_0F3A00_P_2,
1636   VEX_LEN_0F3A01_P_2,
1637   VEX_LEN_0F3A06_P_2,
1638   VEX_LEN_0F3A0A_P_2,
1639   VEX_LEN_0F3A0B_P_2,
1640   VEX_LEN_0F3A14_P_2,
1641   VEX_LEN_0F3A15_P_2,
1642   VEX_LEN_0F3A16_P_2,
1643   VEX_LEN_0F3A17_P_2,
1644   VEX_LEN_0F3A18_P_2,
1645   VEX_LEN_0F3A19_P_2,
1646   VEX_LEN_0F3A20_P_2,
1647   VEX_LEN_0F3A21_P_2,
1648   VEX_LEN_0F3A22_P_2,
1649   VEX_LEN_0F3A30_P_2,
1650   VEX_LEN_0F3A32_P_2,
1651   VEX_LEN_0F3A38_P_2,
1652   VEX_LEN_0F3A39_P_2,
1653   VEX_LEN_0F3A41_P_2,
1654   VEX_LEN_0F3A44_P_2,
1655   VEX_LEN_0F3A46_P_2,
1656   VEX_LEN_0F3A60_P_2,
1657   VEX_LEN_0F3A61_P_2,
1658   VEX_LEN_0F3A62_P_2,
1659   VEX_LEN_0F3A63_P_2,
1660   VEX_LEN_0F3A6A_P_2,
1661   VEX_LEN_0F3A6B_P_2,
1662   VEX_LEN_0F3A6E_P_2,
1663   VEX_LEN_0F3A6F_P_2,
1664   VEX_LEN_0F3A7A_P_2,
1665   VEX_LEN_0F3A7B_P_2,
1666   VEX_LEN_0F3A7E_P_2,
1667   VEX_LEN_0F3A7F_P_2,
1668   VEX_LEN_0F3ADF_P_2,
1669   VEX_LEN_0F3AF0_P_3,
1670   VEX_LEN_0FXOP_08_CC,
1671   VEX_LEN_0FXOP_08_CD,
1672   VEX_LEN_0FXOP_08_CE,
1673   VEX_LEN_0FXOP_08_CF,
1674   VEX_LEN_0FXOP_08_EC,
1675   VEX_LEN_0FXOP_08_ED,
1676   VEX_LEN_0FXOP_08_EE,
1677   VEX_LEN_0FXOP_08_EF,
1678   VEX_LEN_0FXOP_09_80,
1679   VEX_LEN_0FXOP_09_81
1680 };
1681
1682 enum
1683 {
1684   VEX_W_0F10_P_0 = 0,
1685   VEX_W_0F10_P_1,
1686   VEX_W_0F10_P_2,
1687   VEX_W_0F10_P_3,
1688   VEX_W_0F11_P_0,
1689   VEX_W_0F11_P_1,
1690   VEX_W_0F11_P_2,
1691   VEX_W_0F11_P_3,
1692   VEX_W_0F12_P_0_M_0,
1693   VEX_W_0F12_P_0_M_1,
1694   VEX_W_0F12_P_1,
1695   VEX_W_0F12_P_2,
1696   VEX_W_0F12_P_3,
1697   VEX_W_0F13_M_0,
1698   VEX_W_0F14,
1699   VEX_W_0F15,
1700   VEX_W_0F16_P_0_M_0,
1701   VEX_W_0F16_P_0_M_1,
1702   VEX_W_0F16_P_1,
1703   VEX_W_0F16_P_2,
1704   VEX_W_0F17_M_0,
1705   VEX_W_0F28,
1706   VEX_W_0F29,
1707   VEX_W_0F2B_M_0,
1708   VEX_W_0F2E_P_0,
1709   VEX_W_0F2E_P_2,
1710   VEX_W_0F2F_P_0,
1711   VEX_W_0F2F_P_2,
1712   VEX_W_0F41_P_0_LEN_1,
1713   VEX_W_0F42_P_0_LEN_1,
1714   VEX_W_0F44_P_0_LEN_0,
1715   VEX_W_0F45_P_0_LEN_1,
1716   VEX_W_0F46_P_0_LEN_1,
1717   VEX_W_0F47_P_0_LEN_1,
1718   VEX_W_0F4B_P_2_LEN_1,
1719   VEX_W_0F50_M_0,
1720   VEX_W_0F51_P_0,
1721   VEX_W_0F51_P_1,
1722   VEX_W_0F51_P_2,
1723   VEX_W_0F51_P_3,
1724   VEX_W_0F52_P_0,
1725   VEX_W_0F52_P_1,
1726   VEX_W_0F53_P_0,
1727   VEX_W_0F53_P_1,
1728   VEX_W_0F58_P_0,
1729   VEX_W_0F58_P_1,
1730   VEX_W_0F58_P_2,
1731   VEX_W_0F58_P_3,
1732   VEX_W_0F59_P_0,
1733   VEX_W_0F59_P_1,
1734   VEX_W_0F59_P_2,
1735   VEX_W_0F59_P_3,
1736   VEX_W_0F5A_P_0,
1737   VEX_W_0F5A_P_1,
1738   VEX_W_0F5A_P_3,
1739   VEX_W_0F5B_P_0,
1740   VEX_W_0F5B_P_1,
1741   VEX_W_0F5B_P_2,
1742   VEX_W_0F5C_P_0,
1743   VEX_W_0F5C_P_1,
1744   VEX_W_0F5C_P_2,
1745   VEX_W_0F5C_P_3,
1746   VEX_W_0F5D_P_0,
1747   VEX_W_0F5D_P_1,
1748   VEX_W_0F5D_P_2,
1749   VEX_W_0F5D_P_3,
1750   VEX_W_0F5E_P_0,
1751   VEX_W_0F5E_P_1,
1752   VEX_W_0F5E_P_2,
1753   VEX_W_0F5E_P_3,
1754   VEX_W_0F5F_P_0,
1755   VEX_W_0F5F_P_1,
1756   VEX_W_0F5F_P_2,
1757   VEX_W_0F5F_P_3,
1758   VEX_W_0F60_P_2,
1759   VEX_W_0F61_P_2,
1760   VEX_W_0F62_P_2,
1761   VEX_W_0F63_P_2,
1762   VEX_W_0F64_P_2,
1763   VEX_W_0F65_P_2,
1764   VEX_W_0F66_P_2,
1765   VEX_W_0F67_P_2,
1766   VEX_W_0F68_P_2,
1767   VEX_W_0F69_P_2,
1768   VEX_W_0F6A_P_2,
1769   VEX_W_0F6B_P_2,
1770   VEX_W_0F6C_P_2,
1771   VEX_W_0F6D_P_2,
1772   VEX_W_0F6F_P_1,
1773   VEX_W_0F6F_P_2,
1774   VEX_W_0F70_P_1,
1775   VEX_W_0F70_P_2,
1776   VEX_W_0F70_P_3,
1777   VEX_W_0F71_R_2_P_2,
1778   VEX_W_0F71_R_4_P_2,
1779   VEX_W_0F71_R_6_P_2,
1780   VEX_W_0F72_R_2_P_2,
1781   VEX_W_0F72_R_4_P_2,
1782   VEX_W_0F72_R_6_P_2,
1783   VEX_W_0F73_R_2_P_2,
1784   VEX_W_0F73_R_3_P_2,
1785   VEX_W_0F73_R_6_P_2,
1786   VEX_W_0F73_R_7_P_2,
1787   VEX_W_0F74_P_2,
1788   VEX_W_0F75_P_2,
1789   VEX_W_0F76_P_2,
1790   VEX_W_0F77_P_0,
1791   VEX_W_0F7C_P_2,
1792   VEX_W_0F7C_P_3,
1793   VEX_W_0F7D_P_2,
1794   VEX_W_0F7D_P_3,
1795   VEX_W_0F7E_P_1,
1796   VEX_W_0F7F_P_1,
1797   VEX_W_0F7F_P_2,
1798   VEX_W_0F90_P_0_LEN_0,
1799   VEX_W_0F91_P_0_LEN_0,
1800   VEX_W_0F92_P_0_LEN_0,
1801   VEX_W_0F93_P_0_LEN_0,
1802   VEX_W_0F98_P_0_LEN_0,
1803   VEX_W_0FAE_R_2_M_0,
1804   VEX_W_0FAE_R_3_M_0,
1805   VEX_W_0FC2_P_0,
1806   VEX_W_0FC2_P_1,
1807   VEX_W_0FC2_P_2,
1808   VEX_W_0FC2_P_3,
1809   VEX_W_0FC4_P_2,
1810   VEX_W_0FC5_P_2,
1811   VEX_W_0FD0_P_2,
1812   VEX_W_0FD0_P_3,
1813   VEX_W_0FD1_P_2,
1814   VEX_W_0FD2_P_2,
1815   VEX_W_0FD3_P_2,
1816   VEX_W_0FD4_P_2,
1817   VEX_W_0FD5_P_2,
1818   VEX_W_0FD6_P_2,
1819   VEX_W_0FD7_P_2_M_1,
1820   VEX_W_0FD8_P_2,
1821   VEX_W_0FD9_P_2,
1822   VEX_W_0FDA_P_2,
1823   VEX_W_0FDB_P_2,
1824   VEX_W_0FDC_P_2,
1825   VEX_W_0FDD_P_2,
1826   VEX_W_0FDE_P_2,
1827   VEX_W_0FDF_P_2,
1828   VEX_W_0FE0_P_2,
1829   VEX_W_0FE1_P_2,
1830   VEX_W_0FE2_P_2,
1831   VEX_W_0FE3_P_2,
1832   VEX_W_0FE4_P_2,
1833   VEX_W_0FE5_P_2,
1834   VEX_W_0FE6_P_1,
1835   VEX_W_0FE6_P_2,
1836   VEX_W_0FE6_P_3,
1837   VEX_W_0FE7_P_2_M_0,
1838   VEX_W_0FE8_P_2,
1839   VEX_W_0FE9_P_2,
1840   VEX_W_0FEA_P_2,
1841   VEX_W_0FEB_P_2,
1842   VEX_W_0FEC_P_2,
1843   VEX_W_0FED_P_2,
1844   VEX_W_0FEE_P_2,
1845   VEX_W_0FEF_P_2,
1846   VEX_W_0FF0_P_3_M_0,
1847   VEX_W_0FF1_P_2,
1848   VEX_W_0FF2_P_2,
1849   VEX_W_0FF3_P_2,
1850   VEX_W_0FF4_P_2,
1851   VEX_W_0FF5_P_2,
1852   VEX_W_0FF6_P_2,
1853   VEX_W_0FF7_P_2,
1854   VEX_W_0FF8_P_2,
1855   VEX_W_0FF9_P_2,
1856   VEX_W_0FFA_P_2,
1857   VEX_W_0FFB_P_2,
1858   VEX_W_0FFC_P_2,
1859   VEX_W_0FFD_P_2,
1860   VEX_W_0FFE_P_2,
1861   VEX_W_0F3800_P_2,
1862   VEX_W_0F3801_P_2,
1863   VEX_W_0F3802_P_2,
1864   VEX_W_0F3803_P_2,
1865   VEX_W_0F3804_P_2,
1866   VEX_W_0F3805_P_2,
1867   VEX_W_0F3806_P_2,
1868   VEX_W_0F3807_P_2,
1869   VEX_W_0F3808_P_2,
1870   VEX_W_0F3809_P_2,
1871   VEX_W_0F380A_P_2,
1872   VEX_W_0F380B_P_2,
1873   VEX_W_0F380C_P_2,
1874   VEX_W_0F380D_P_2,
1875   VEX_W_0F380E_P_2,
1876   VEX_W_0F380F_P_2,
1877   VEX_W_0F3816_P_2,
1878   VEX_W_0F3817_P_2,
1879   VEX_W_0F3818_P_2,
1880   VEX_W_0F3819_P_2,
1881   VEX_W_0F381A_P_2_M_0,
1882   VEX_W_0F381C_P_2,
1883   VEX_W_0F381D_P_2,
1884   VEX_W_0F381E_P_2,
1885   VEX_W_0F3820_P_2,
1886   VEX_W_0F3821_P_2,
1887   VEX_W_0F3822_P_2,
1888   VEX_W_0F3823_P_2,
1889   VEX_W_0F3824_P_2,
1890   VEX_W_0F3825_P_2,
1891   VEX_W_0F3828_P_2,
1892   VEX_W_0F3829_P_2,
1893   VEX_W_0F382A_P_2_M_0,
1894   VEX_W_0F382B_P_2,
1895   VEX_W_0F382C_P_2_M_0,
1896   VEX_W_0F382D_P_2_M_0,
1897   VEX_W_0F382E_P_2_M_0,
1898   VEX_W_0F382F_P_2_M_0,
1899   VEX_W_0F3830_P_2,
1900   VEX_W_0F3831_P_2,
1901   VEX_W_0F3832_P_2,
1902   VEX_W_0F3833_P_2,
1903   VEX_W_0F3834_P_2,
1904   VEX_W_0F3835_P_2,
1905   VEX_W_0F3836_P_2,
1906   VEX_W_0F3837_P_2,
1907   VEX_W_0F3838_P_2,
1908   VEX_W_0F3839_P_2,
1909   VEX_W_0F383A_P_2,
1910   VEX_W_0F383B_P_2,
1911   VEX_W_0F383C_P_2,
1912   VEX_W_0F383D_P_2,
1913   VEX_W_0F383E_P_2,
1914   VEX_W_0F383F_P_2,
1915   VEX_W_0F3840_P_2,
1916   VEX_W_0F3841_P_2,
1917   VEX_W_0F3846_P_2,
1918   VEX_W_0F3858_P_2,
1919   VEX_W_0F3859_P_2,
1920   VEX_W_0F385A_P_2_M_0,
1921   VEX_W_0F3878_P_2,
1922   VEX_W_0F3879_P_2,
1923   VEX_W_0F38DB_P_2,
1924   VEX_W_0F38DC_P_2,
1925   VEX_W_0F38DD_P_2,
1926   VEX_W_0F38DE_P_2,
1927   VEX_W_0F38DF_P_2,
1928   VEX_W_0F3A00_P_2,
1929   VEX_W_0F3A01_P_2,
1930   VEX_W_0F3A02_P_2,
1931   VEX_W_0F3A04_P_2,
1932   VEX_W_0F3A05_P_2,
1933   VEX_W_0F3A06_P_2,
1934   VEX_W_0F3A08_P_2,
1935   VEX_W_0F3A09_P_2,
1936   VEX_W_0F3A0A_P_2,
1937   VEX_W_0F3A0B_P_2,
1938   VEX_W_0F3A0C_P_2,
1939   VEX_W_0F3A0D_P_2,
1940   VEX_W_0F3A0E_P_2,
1941   VEX_W_0F3A0F_P_2,
1942   VEX_W_0F3A14_P_2,
1943   VEX_W_0F3A15_P_2,
1944   VEX_W_0F3A18_P_2,
1945   VEX_W_0F3A19_P_2,
1946   VEX_W_0F3A20_P_2,
1947   VEX_W_0F3A21_P_2,
1948   VEX_W_0F3A30_P_2_LEN_0,
1949   VEX_W_0F3A32_P_2_LEN_0,
1950   VEX_W_0F3A38_P_2,
1951   VEX_W_0F3A39_P_2,
1952   VEX_W_0F3A40_P_2,
1953   VEX_W_0F3A41_P_2,
1954   VEX_W_0F3A42_P_2,
1955   VEX_W_0F3A44_P_2,
1956   VEX_W_0F3A46_P_2,
1957   VEX_W_0F3A48_P_2,
1958   VEX_W_0F3A49_P_2,
1959   VEX_W_0F3A4A_P_2,
1960   VEX_W_0F3A4B_P_2,
1961   VEX_W_0F3A4C_P_2,
1962   VEX_W_0F3A60_P_2,
1963   VEX_W_0F3A61_P_2,
1964   VEX_W_0F3A62_P_2,
1965   VEX_W_0F3A63_P_2,
1966   VEX_W_0F3ADF_P_2,
1967
1968   EVEX_W_0F10_P_0,
1969   EVEX_W_0F10_P_1_M_0,
1970   EVEX_W_0F10_P_1_M_1,
1971   EVEX_W_0F10_P_2,
1972   EVEX_W_0F10_P_3_M_0,
1973   EVEX_W_0F10_P_3_M_1,
1974   EVEX_W_0F11_P_0,
1975   EVEX_W_0F11_P_1_M_0,
1976   EVEX_W_0F11_P_1_M_1,
1977   EVEX_W_0F11_P_2,
1978   EVEX_W_0F11_P_3_M_0,
1979   EVEX_W_0F11_P_3_M_1,
1980   EVEX_W_0F12_P_0_M_0,
1981   EVEX_W_0F12_P_0_M_1,
1982   EVEX_W_0F12_P_1,
1983   EVEX_W_0F12_P_2,
1984   EVEX_W_0F12_P_3,
1985   EVEX_W_0F13_P_0,
1986   EVEX_W_0F13_P_2,
1987   EVEX_W_0F14_P_0,
1988   EVEX_W_0F14_P_2,
1989   EVEX_W_0F15_P_0,
1990   EVEX_W_0F15_P_2,
1991   EVEX_W_0F16_P_0_M_0,
1992   EVEX_W_0F16_P_0_M_1,
1993   EVEX_W_0F16_P_1,
1994   EVEX_W_0F16_P_2,
1995   EVEX_W_0F17_P_0,
1996   EVEX_W_0F17_P_2,
1997   EVEX_W_0F28_P_0,
1998   EVEX_W_0F28_P_2,
1999   EVEX_W_0F29_P_0,
2000   EVEX_W_0F29_P_2,
2001   EVEX_W_0F2A_P_1,
2002   EVEX_W_0F2A_P_3,
2003   EVEX_W_0F2B_P_0,
2004   EVEX_W_0F2B_P_2,
2005   EVEX_W_0F2E_P_0,
2006   EVEX_W_0F2E_P_2,
2007   EVEX_W_0F2F_P_0,
2008   EVEX_W_0F2F_P_2,
2009   EVEX_W_0F51_P_0,
2010   EVEX_W_0F51_P_1,
2011   EVEX_W_0F51_P_2,
2012   EVEX_W_0F51_P_3,
2013   EVEX_W_0F58_P_0,
2014   EVEX_W_0F58_P_1,
2015   EVEX_W_0F58_P_2,
2016   EVEX_W_0F58_P_3,
2017   EVEX_W_0F59_P_0,
2018   EVEX_W_0F59_P_1,
2019   EVEX_W_0F59_P_2,
2020   EVEX_W_0F59_P_3,
2021   EVEX_W_0F5A_P_0,
2022   EVEX_W_0F5A_P_1,
2023   EVEX_W_0F5A_P_2,
2024   EVEX_W_0F5A_P_3,
2025   EVEX_W_0F5B_P_0,
2026   EVEX_W_0F5B_P_1,
2027   EVEX_W_0F5B_P_2,
2028   EVEX_W_0F5C_P_0,
2029   EVEX_W_0F5C_P_1,
2030   EVEX_W_0F5C_P_2,
2031   EVEX_W_0F5C_P_3,
2032   EVEX_W_0F5D_P_0,
2033   EVEX_W_0F5D_P_1,
2034   EVEX_W_0F5D_P_2,
2035   EVEX_W_0F5D_P_3,
2036   EVEX_W_0F5E_P_0,
2037   EVEX_W_0F5E_P_1,
2038   EVEX_W_0F5E_P_2,
2039   EVEX_W_0F5E_P_3,
2040   EVEX_W_0F5F_P_0,
2041   EVEX_W_0F5F_P_1,
2042   EVEX_W_0F5F_P_2,
2043   EVEX_W_0F5F_P_3,
2044   EVEX_W_0F62_P_2,
2045   EVEX_W_0F66_P_2,
2046   EVEX_W_0F6A_P_2,
2047   EVEX_W_0F6C_P_2,
2048   EVEX_W_0F6D_P_2,
2049   EVEX_W_0F6E_P_2,
2050   EVEX_W_0F6F_P_1,
2051   EVEX_W_0F6F_P_2,
2052   EVEX_W_0F70_P_2,
2053   EVEX_W_0F72_R_2_P_2,
2054   EVEX_W_0F72_R_6_P_2,
2055   EVEX_W_0F73_R_2_P_2,
2056   EVEX_W_0F73_R_6_P_2,
2057   EVEX_W_0F76_P_2,
2058   EVEX_W_0F78_P_0,
2059   EVEX_W_0F79_P_0,
2060   EVEX_W_0F7A_P_1,
2061   EVEX_W_0F7A_P_3,
2062   EVEX_W_0F7B_P_1,
2063   EVEX_W_0F7B_P_3,
2064   EVEX_W_0F7E_P_1,
2065   EVEX_W_0F7E_P_2,
2066   EVEX_W_0F7F_P_1,
2067   EVEX_W_0F7F_P_2,
2068   EVEX_W_0FC2_P_0,
2069   EVEX_W_0FC2_P_1,
2070   EVEX_W_0FC2_P_2,
2071   EVEX_W_0FC2_P_3,
2072   EVEX_W_0FC6_P_0,
2073   EVEX_W_0FC6_P_2,
2074   EVEX_W_0FD2_P_2,
2075   EVEX_W_0FD3_P_2,
2076   EVEX_W_0FD4_P_2,
2077   EVEX_W_0FD6_P_2,
2078   EVEX_W_0FE6_P_1,
2079   EVEX_W_0FE6_P_2,
2080   EVEX_W_0FE6_P_3,
2081   EVEX_W_0FE7_P_2,
2082   EVEX_W_0FF2_P_2,
2083   EVEX_W_0FF3_P_2,
2084   EVEX_W_0FF4_P_2,
2085   EVEX_W_0FFA_P_2,
2086   EVEX_W_0FFB_P_2,
2087   EVEX_W_0FFE_P_2,
2088   EVEX_W_0F380C_P_2,
2089   EVEX_W_0F380D_P_2,
2090   EVEX_W_0F3811_P_1,
2091   EVEX_W_0F3812_P_1,
2092   EVEX_W_0F3813_P_1,
2093   EVEX_W_0F3813_P_2,
2094   EVEX_W_0F3814_P_1,
2095   EVEX_W_0F3815_P_1,
2096   EVEX_W_0F3818_P_2,
2097   EVEX_W_0F3819_P_2,
2098   EVEX_W_0F381A_P_2,
2099   EVEX_W_0F381B_P_2,
2100   EVEX_W_0F381E_P_2,
2101   EVEX_W_0F381F_P_2,
2102   EVEX_W_0F3821_P_1,
2103   EVEX_W_0F3822_P_1,
2104   EVEX_W_0F3823_P_1,
2105   EVEX_W_0F3824_P_1,
2106   EVEX_W_0F3825_P_1,
2107   EVEX_W_0F3825_P_2,
2108   EVEX_W_0F3828_P_2,
2109   EVEX_W_0F3829_P_2,
2110   EVEX_W_0F382A_P_1,
2111   EVEX_W_0F382A_P_2,
2112   EVEX_W_0F3831_P_1,
2113   EVEX_W_0F3832_P_1,
2114   EVEX_W_0F3833_P_1,
2115   EVEX_W_0F3834_P_1,
2116   EVEX_W_0F3835_P_1,
2117   EVEX_W_0F3835_P_2,
2118   EVEX_W_0F3837_P_2,
2119   EVEX_W_0F383A_P_1,
2120   EVEX_W_0F3840_P_2,
2121   EVEX_W_0F3858_P_2,
2122   EVEX_W_0F3859_P_2,
2123   EVEX_W_0F385A_P_2,
2124   EVEX_W_0F385B_P_2,
2125   EVEX_W_0F3891_P_2,
2126   EVEX_W_0F3893_P_2,
2127   EVEX_W_0F38A1_P_2,
2128   EVEX_W_0F38A3_P_2,
2129   EVEX_W_0F38C7_R_1_P_2,
2130   EVEX_W_0F38C7_R_2_P_2,
2131   EVEX_W_0F38C7_R_5_P_2,
2132   EVEX_W_0F38C7_R_6_P_2,
2133
2134   EVEX_W_0F3A00_P_2,
2135   EVEX_W_0F3A01_P_2,
2136   EVEX_W_0F3A04_P_2,
2137   EVEX_W_0F3A05_P_2,
2138   EVEX_W_0F3A08_P_2,
2139   EVEX_W_0F3A09_P_2,
2140   EVEX_W_0F3A0A_P_2,
2141   EVEX_W_0F3A0B_P_2,
2142   EVEX_W_0F3A18_P_2,
2143   EVEX_W_0F3A19_P_2,
2144   EVEX_W_0F3A1A_P_2,
2145   EVEX_W_0F3A1B_P_2,
2146   EVEX_W_0F3A1D_P_2,
2147   EVEX_W_0F3A21_P_2,
2148   EVEX_W_0F3A23_P_2,
2149   EVEX_W_0F3A38_P_2,
2150   EVEX_W_0F3A39_P_2,
2151   EVEX_W_0F3A3A_P_2,
2152   EVEX_W_0F3A3B_P_2,
2153   EVEX_W_0F3A43_P_2,
2154 };
2155
2156 typedef void (*op_rtn) (int bytemode, int sizeflag);
2157
2158 struct dis386 {
2159   const char *name;
2160   struct
2161     {
2162       op_rtn rtn;
2163       int bytemode;
2164     } op[MAX_OPERANDS];
2165 };
2166
2167 /* Upper case letters in the instruction names here are macros.
2168    'A' => print 'b' if no register operands or suffix_always is true
2169    'B' => print 'b' if suffix_always is true
2170    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2171           size prefix
2172    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2173           suffix_always is true
2174    'E' => print 'e' if 32-bit form of jcxz
2175    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2176    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2177    'H' => print ",pt" or ",pn" branch hint
2178    'I' => honor following macro letter even in Intel mode (implemented only
2179           for some of the macro letters)
2180    'J' => print 'l'
2181    'K' => print 'd' or 'q' if rex prefix is present.
2182    'L' => print 'l' if suffix_always is true
2183    'M' => print 'r' if intel_mnemonic is false.
2184    'N' => print 'n' if instruction has no wait "prefix"
2185    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2186    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2187           or suffix_always is true.  print 'q' if rex prefix is present.
2188    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2189           is true
2190    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2191    'S' => print 'w', 'l' or 'q' if suffix_always is true
2192    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2193    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2194    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2195    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2196    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2197    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2198           suffix_always is true.
2199    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2200    '!' => change condition from true to false or from false to true.
2201    '%' => add 1 upper case letter to the macro.
2202
2203    2 upper case letter macros:
2204    "XY" => print 'x' or 'y' if no register operands or suffix_always
2205            is true.
2206    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2207    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2208            or suffix_always is true
2209    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2210    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2211    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2212    "LW" => print 'd', 'q' depending on the VEX.W bit
2213
2214    Many of the above letters print nothing in Intel mode.  See "putop"
2215    for the details.
2216
2217    Braces '{' and '}', and vertical bars '|', indicate alternative
2218    mnemonic strings for AT&T and Intel.  */
2219
2220 static const struct dis386 dis386[] = {
2221   /* 00 */
2222   { "addB",             { Ebh1, Gb } },
2223   { "addS",             { Evh1, Gv } },
2224   { "addB",             { Gb, EbS } },
2225   { "addS",             { Gv, EvS } },
2226   { "addB",             { AL, Ib } },
2227   { "addS",             { eAX, Iv } },
2228   { X86_64_TABLE (X86_64_06) },
2229   { X86_64_TABLE (X86_64_07) },
2230   /* 08 */
2231   { "orB",              { Ebh1, Gb } },
2232   { "orS",              { Evh1, Gv } },
2233   { "orB",              { Gb, EbS } },
2234   { "orS",              { Gv, EvS } },
2235   { "orB",              { AL, Ib } },
2236   { "orS",              { eAX, Iv } },
2237   { X86_64_TABLE (X86_64_0D) },
2238   { Bad_Opcode },       /* 0x0f extended opcode escape */
2239   /* 10 */
2240   { "adcB",             { Ebh1, Gb } },
2241   { "adcS",             { Evh1, Gv } },
2242   { "adcB",             { Gb, EbS } },
2243   { "adcS",             { Gv, EvS } },
2244   { "adcB",             { AL, Ib } },
2245   { "adcS",             { eAX, Iv } },
2246   { X86_64_TABLE (X86_64_16) },
2247   { X86_64_TABLE (X86_64_17) },
2248   /* 18 */
2249   { "sbbB",             { Ebh1, Gb } },
2250   { "sbbS",             { Evh1, Gv } },
2251   { "sbbB",             { Gb, EbS } },
2252   { "sbbS",             { Gv, EvS } },
2253   { "sbbB",             { AL, Ib } },
2254   { "sbbS",             { eAX, Iv } },
2255   { X86_64_TABLE (X86_64_1E) },
2256   { X86_64_TABLE (X86_64_1F) },
2257   /* 20 */
2258   { "andB",             { Ebh1, Gb } },
2259   { "andS",             { Evh1, Gv } },
2260   { "andB",             { Gb, EbS } },
2261   { "andS",             { Gv, EvS } },
2262   { "andB",             { AL, Ib } },
2263   { "andS",             { eAX, Iv } },
2264   { Bad_Opcode },       /* SEG ES prefix */
2265   { X86_64_TABLE (X86_64_27) },
2266   /* 28 */
2267   { "subB",             { Ebh1, Gb } },
2268   { "subS",             { Evh1, Gv } },
2269   { "subB",             { Gb, EbS } },
2270   { "subS",             { Gv, EvS } },
2271   { "subB",             { AL, Ib } },
2272   { "subS",             { eAX, Iv } },
2273   { Bad_Opcode },       /* SEG CS prefix */
2274   { X86_64_TABLE (X86_64_2F) },
2275   /* 30 */
2276   { "xorB",             { Ebh1, Gb } },
2277   { "xorS",             { Evh1, Gv } },
2278   { "xorB",             { Gb, EbS } },
2279   { "xorS",             { Gv, EvS } },
2280   { "xorB",             { AL, Ib } },
2281   { "xorS",             { eAX, Iv } },
2282   { Bad_Opcode },       /* SEG SS prefix */
2283   { X86_64_TABLE (X86_64_37) },
2284   /* 38 */
2285   { "cmpB",             { Eb, Gb } },
2286   { "cmpS",             { Ev, Gv } },
2287   { "cmpB",             { Gb, EbS } },
2288   { "cmpS",             { Gv, EvS } },
2289   { "cmpB",             { AL, Ib } },
2290   { "cmpS",             { eAX, Iv } },
2291   { Bad_Opcode },       /* SEG DS prefix */
2292   { X86_64_TABLE (X86_64_3F) },
2293   /* 40 */
2294   { "inc{S|}",          { RMeAX } },
2295   { "inc{S|}",          { RMeCX } },
2296   { "inc{S|}",          { RMeDX } },
2297   { "inc{S|}",          { RMeBX } },
2298   { "inc{S|}",          { RMeSP } },
2299   { "inc{S|}",          { RMeBP } },
2300   { "inc{S|}",          { RMeSI } },
2301   { "inc{S|}",          { RMeDI } },
2302   /* 48 */
2303   { "dec{S|}",          { RMeAX } },
2304   { "dec{S|}",          { RMeCX } },
2305   { "dec{S|}",          { RMeDX } },
2306   { "dec{S|}",          { RMeBX } },
2307   { "dec{S|}",          { RMeSP } },
2308   { "dec{S|}",          { RMeBP } },
2309   { "dec{S|}",          { RMeSI } },
2310   { "dec{S|}",          { RMeDI } },
2311   /* 50 */
2312   { "pushV",            { RMrAX } },
2313   { "pushV",            { RMrCX } },
2314   { "pushV",            { RMrDX } },
2315   { "pushV",            { RMrBX } },
2316   { "pushV",            { RMrSP } },
2317   { "pushV",            { RMrBP } },
2318   { "pushV",            { RMrSI } },
2319   { "pushV",            { RMrDI } },
2320   /* 58 */
2321   { "popV",             { RMrAX } },
2322   { "popV",             { RMrCX } },
2323   { "popV",             { RMrDX } },
2324   { "popV",             { RMrBX } },
2325   { "popV",             { RMrSP } },
2326   { "popV",             { RMrBP } },
2327   { "popV",             { RMrSI } },
2328   { "popV",             { RMrDI } },
2329   /* 60 */
2330   { X86_64_TABLE (X86_64_60) },
2331   { X86_64_TABLE (X86_64_61) },
2332   { X86_64_TABLE (X86_64_62) },
2333   { X86_64_TABLE (X86_64_63) },
2334   { Bad_Opcode },       /* seg fs */
2335   { Bad_Opcode },       /* seg gs */
2336   { Bad_Opcode },       /* op size prefix */
2337   { Bad_Opcode },       /* adr size prefix */
2338   /* 68 */
2339   { "pushT",            { sIv } },
2340   { "imulS",            { Gv, Ev, Iv } },
2341   { "pushT",            { sIbT } },
2342   { "imulS",            { Gv, Ev, sIb } },
2343   { "ins{b|}",          { Ybr, indirDX } },
2344   { X86_64_TABLE (X86_64_6D) },
2345   { "outs{b|}",         { indirDXr, Xb } },
2346   { X86_64_TABLE (X86_64_6F) },
2347   /* 70 */
2348   { "joH",              { Jb, BND, cond_jump_flag } },
2349   { "jnoH",             { Jb, BND, cond_jump_flag } },
2350   { "jbH",              { Jb, BND, cond_jump_flag } },
2351   { "jaeH",             { Jb, BND, cond_jump_flag } },
2352   { "jeH",              { Jb, BND, cond_jump_flag } },
2353   { "jneH",             { Jb, BND, cond_jump_flag } },
2354   { "jbeH",             { Jb, BND, cond_jump_flag } },
2355   { "jaH",              { Jb, BND, cond_jump_flag } },
2356   /* 78 */
2357   { "jsH",              { Jb, BND, cond_jump_flag } },
2358   { "jnsH",             { Jb, BND, cond_jump_flag } },
2359   { "jpH",              { Jb, BND, cond_jump_flag } },
2360   { "jnpH",             { Jb, BND, cond_jump_flag } },
2361   { "jlH",              { Jb, BND, cond_jump_flag } },
2362   { "jgeH",             { Jb, BND, cond_jump_flag } },
2363   { "jleH",             { Jb, BND, cond_jump_flag } },
2364   { "jgH",              { Jb, BND, cond_jump_flag } },
2365   /* 80 */
2366   { REG_TABLE (REG_80) },
2367   { REG_TABLE (REG_81) },
2368   { Bad_Opcode },
2369   { REG_TABLE (REG_82) },
2370   { "testB",            { Eb, Gb } },
2371   { "testS",            { Ev, Gv } },
2372   { "xchgB",            { Ebh2, Gb } },
2373   { "xchgS",            { Evh2, Gv } },
2374   /* 88 */
2375   { "movB",             { Ebh3, Gb } },
2376   { "movS",             { Evh3, Gv } },
2377   { "movB",             { Gb, EbS } },
2378   { "movS",             { Gv, EvS } },
2379   { "movD",             { Sv, Sw } },
2380   { MOD_TABLE (MOD_8D) },
2381   { "movD",             { Sw, Sv } },
2382   { REG_TABLE (REG_8F) },
2383   /* 90 */
2384   { PREFIX_TABLE (PREFIX_90) },
2385   { "xchgS",            { RMeCX, eAX } },
2386   { "xchgS",            { RMeDX, eAX } },
2387   { "xchgS",            { RMeBX, eAX } },
2388   { "xchgS",            { RMeSP, eAX } },
2389   { "xchgS",            { RMeBP, eAX } },
2390   { "xchgS",            { RMeSI, eAX } },
2391   { "xchgS",            { RMeDI, eAX } },
2392   /* 98 */
2393   { "cW{t|}R",          { XX } },
2394   { "cR{t|}O",          { XX } },
2395   { X86_64_TABLE (X86_64_9A) },
2396   { Bad_Opcode },       /* fwait */
2397   { "pushfT",           { XX } },
2398   { "popfT",            { XX } },
2399   { "sahf",             { XX } },
2400   { "lahf",             { XX } },
2401   /* a0 */
2402   { "mov%LB",           { AL, Ob } },
2403   { "mov%LS",           { eAX, Ov } },
2404   { "mov%LB",           { Ob, AL } },
2405   { "mov%LS",           { Ov, eAX } },
2406   { "movs{b|}",         { Ybr, Xb } },
2407   { "movs{R|}",         { Yvr, Xv } },
2408   { "cmps{b|}",         { Xb, Yb } },
2409   { "cmps{R|}",         { Xv, Yv } },
2410   /* a8 */
2411   { "testB",            { AL, Ib } },
2412   { "testS",            { eAX, Iv } },
2413   { "stosB",            { Ybr, AL } },
2414   { "stosS",            { Yvr, eAX } },
2415   { "lodsB",            { ALr, Xb } },
2416   { "lodsS",            { eAXr, Xv } },
2417   { "scasB",            { AL, Yb } },
2418   { "scasS",            { eAX, Yv } },
2419   /* b0 */
2420   { "movB",             { RMAL, Ib } },
2421   { "movB",             { RMCL, Ib } },
2422   { "movB",             { RMDL, Ib } },
2423   { "movB",             { RMBL, Ib } },
2424   { "movB",             { RMAH, Ib } },
2425   { "movB",             { RMCH, Ib } },
2426   { "movB",             { RMDH, Ib } },
2427   { "movB",             { RMBH, Ib } },
2428   /* b8 */
2429   { "mov%LV",           { RMeAX, Iv64 } },
2430   { "mov%LV",           { RMeCX, Iv64 } },
2431   { "mov%LV",           { RMeDX, Iv64 } },
2432   { "mov%LV",           { RMeBX, Iv64 } },
2433   { "mov%LV",           { RMeSP, Iv64 } },
2434   { "mov%LV",           { RMeBP, Iv64 } },
2435   { "mov%LV",           { RMeSI, Iv64 } },
2436   { "mov%LV",           { RMeDI, Iv64 } },
2437   /* c0 */
2438   { REG_TABLE (REG_C0) },
2439   { REG_TABLE (REG_C1) },
2440   { "retT",             { Iw, BND } },
2441   { "retT",             { BND } },
2442   { X86_64_TABLE (X86_64_C4) },
2443   { X86_64_TABLE (X86_64_C5) },
2444   { REG_TABLE (REG_C6) },
2445   { REG_TABLE (REG_C7) },
2446   /* c8 */
2447   { "enterT",           { Iw, Ib } },
2448   { "leaveT",           { XX } },
2449   { "Jret{|f}P",        { Iw } },
2450   { "Jret{|f}P",        { XX } },
2451   { "int3",             { XX } },
2452   { "int",              { Ib } },
2453   { X86_64_TABLE (X86_64_CE) },
2454   { "iretP",            { XX } },
2455   /* d0 */
2456   { REG_TABLE (REG_D0) },
2457   { REG_TABLE (REG_D1) },
2458   { REG_TABLE (REG_D2) },
2459   { REG_TABLE (REG_D3) },
2460   { X86_64_TABLE (X86_64_D4) },
2461   { X86_64_TABLE (X86_64_D5) },
2462   { Bad_Opcode },
2463   { "xlat",             { DSBX } },
2464   /* d8 */
2465   { FLOAT },
2466   { FLOAT },
2467   { FLOAT },
2468   { FLOAT },
2469   { FLOAT },
2470   { FLOAT },
2471   { FLOAT },
2472   { FLOAT },
2473   /* e0 */
2474   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
2475   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
2476   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
2477   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
2478   { "inB",              { AL, Ib } },
2479   { "inG",              { zAX, Ib } },
2480   { "outB",             { Ib, AL } },
2481   { "outG",             { Ib, zAX } },
2482   /* e8 */
2483   { "callT",            { Jv, BND } },
2484   { "jmpT",             { Jv, BND } },
2485   { X86_64_TABLE (X86_64_EA) },
2486   { "jmp",              { Jb, BND } },
2487   { "inB",              { AL, indirDX } },
2488   { "inG",              { zAX, indirDX } },
2489   { "outB",             { indirDX, AL } },
2490   { "outG",             { indirDX, zAX } },
2491   /* f0 */
2492   { Bad_Opcode },       /* lock prefix */
2493   { "icebp",            { XX } },
2494   { Bad_Opcode },       /* repne */
2495   { Bad_Opcode },       /* repz */
2496   { "hlt",              { XX } },
2497   { "cmc",              { XX } },
2498   { REG_TABLE (REG_F6) },
2499   { REG_TABLE (REG_F7) },
2500   /* f8 */
2501   { "clc",              { XX } },
2502   { "stc",              { XX } },
2503   { "cli",              { XX } },
2504   { "sti",              { XX } },
2505   { "cld",              { XX } },
2506   { "std",              { XX } },
2507   { REG_TABLE (REG_FE) },
2508   { REG_TABLE (REG_FF) },
2509 };
2510
2511 static const struct dis386 dis386_twobyte[] = {
2512   /* 00 */
2513   { REG_TABLE (REG_0F00 ) },
2514   { REG_TABLE (REG_0F01 ) },
2515   { "larS",             { Gv, Ew } },
2516   { "lslS",             { Gv, Ew } },
2517   { Bad_Opcode },
2518   { "syscall",          { XX } },
2519   { "clts",             { XX } },
2520   { "sysretP",          { XX } },
2521   /* 08 */
2522   { "invd",             { XX } },
2523   { "wbinvd",           { XX } },
2524   { Bad_Opcode },
2525   { "ud2",              { XX } },
2526   { Bad_Opcode },
2527   { REG_TABLE (REG_0F0D) },
2528   { "femms",            { XX } },
2529   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2530   /* 10 */
2531   { PREFIX_TABLE (PREFIX_0F10) },
2532   { PREFIX_TABLE (PREFIX_0F11) },
2533   { PREFIX_TABLE (PREFIX_0F12) },
2534   { MOD_TABLE (MOD_0F13) },
2535   { "unpcklpX",         { XM, EXx } },
2536   { "unpckhpX",         { XM, EXx } },
2537   { PREFIX_TABLE (PREFIX_0F16) },
2538   { MOD_TABLE (MOD_0F17) },
2539   /* 18 */
2540   { REG_TABLE (REG_0F18) },
2541   { "nopQ",             { Ev } },
2542   { PREFIX_TABLE (PREFIX_0F1A) },
2543   { PREFIX_TABLE (PREFIX_0F1B) },
2544   { "nopQ",             { Ev } },
2545   { "nopQ",             { Ev } },
2546   { "nopQ",             { Ev } },
2547   { "nopQ",             { Ev } },
2548   /* 20 */
2549   { MOD_TABLE (MOD_0F20) },
2550   { MOD_TABLE (MOD_0F21) },
2551   { MOD_TABLE (MOD_0F22) },
2552   { MOD_TABLE (MOD_0F23) },
2553   { MOD_TABLE (MOD_0F24) },
2554   { Bad_Opcode },
2555   { MOD_TABLE (MOD_0F26) },
2556   { Bad_Opcode },
2557   /* 28 */
2558   { "movapX",           { XM, EXx } },
2559   { "movapX",           { EXxS, XM } },
2560   { PREFIX_TABLE (PREFIX_0F2A) },
2561   { PREFIX_TABLE (PREFIX_0F2B) },
2562   { PREFIX_TABLE (PREFIX_0F2C) },
2563   { PREFIX_TABLE (PREFIX_0F2D) },
2564   { PREFIX_TABLE (PREFIX_0F2E) },
2565   { PREFIX_TABLE (PREFIX_0F2F) },
2566   /* 30 */
2567   { "wrmsr",            { XX } },
2568   { "rdtsc",            { XX } },
2569   { "rdmsr",            { XX } },
2570   { "rdpmc",            { XX } },
2571   { "sysenter",         { XX } },
2572   { "sysexit",          { XX } },
2573   { Bad_Opcode },
2574   { "getsec",           { XX } },
2575   /* 38 */
2576   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2577   { Bad_Opcode },
2578   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2579   { Bad_Opcode },
2580   { Bad_Opcode },
2581   { Bad_Opcode },
2582   { Bad_Opcode },
2583   { Bad_Opcode },
2584   /* 40 */
2585   { "cmovoS",           { Gv, Ev } },
2586   { "cmovnoS",          { Gv, Ev } },
2587   { "cmovbS",           { Gv, Ev } },
2588   { "cmovaeS",          { Gv, Ev } },
2589   { "cmoveS",           { Gv, Ev } },
2590   { "cmovneS",          { Gv, Ev } },
2591   { "cmovbeS",          { Gv, Ev } },
2592   { "cmovaS",           { Gv, Ev } },
2593   /* 48 */
2594   { "cmovsS",           { Gv, Ev } },
2595   { "cmovnsS",          { Gv, Ev } },
2596   { "cmovpS",           { Gv, Ev } },
2597   { "cmovnpS",          { Gv, Ev } },
2598   { "cmovlS",           { Gv, Ev } },
2599   { "cmovgeS",          { Gv, Ev } },
2600   { "cmovleS",          { Gv, Ev } },
2601   { "cmovgS",           { Gv, Ev } },
2602   /* 50 */
2603   { MOD_TABLE (MOD_0F51) },
2604   { PREFIX_TABLE (PREFIX_0F51) },
2605   { PREFIX_TABLE (PREFIX_0F52) },
2606   { PREFIX_TABLE (PREFIX_0F53) },
2607   { "andpX",            { XM, EXx } },
2608   { "andnpX",           { XM, EXx } },
2609   { "orpX",             { XM, EXx } },
2610   { "xorpX",            { XM, EXx } },
2611   /* 58 */
2612   { PREFIX_TABLE (PREFIX_0F58) },
2613   { PREFIX_TABLE (PREFIX_0F59) },
2614   { PREFIX_TABLE (PREFIX_0F5A) },
2615   { PREFIX_TABLE (PREFIX_0F5B) },
2616   { PREFIX_TABLE (PREFIX_0F5C) },
2617   { PREFIX_TABLE (PREFIX_0F5D) },
2618   { PREFIX_TABLE (PREFIX_0F5E) },
2619   { PREFIX_TABLE (PREFIX_0F5F) },
2620   /* 60 */
2621   { PREFIX_TABLE (PREFIX_0F60) },
2622   { PREFIX_TABLE (PREFIX_0F61) },
2623   { PREFIX_TABLE (PREFIX_0F62) },
2624   { "packsswb",         { MX, EM } },
2625   { "pcmpgtb",          { MX, EM } },
2626   { "pcmpgtw",          { MX, EM } },
2627   { "pcmpgtd",          { MX, EM } },
2628   { "packuswb",         { MX, EM } },
2629   /* 68 */
2630   { "punpckhbw",        { MX, EM } },
2631   { "punpckhwd",        { MX, EM } },
2632   { "punpckhdq",        { MX, EM } },
2633   { "packssdw",         { MX, EM } },
2634   { PREFIX_TABLE (PREFIX_0F6C) },
2635   { PREFIX_TABLE (PREFIX_0F6D) },
2636   { "movK",             { MX, Edq } },
2637   { PREFIX_TABLE (PREFIX_0F6F) },
2638   /* 70 */
2639   { PREFIX_TABLE (PREFIX_0F70) },
2640   { REG_TABLE (REG_0F71) },
2641   { REG_TABLE (REG_0F72) },
2642   { REG_TABLE (REG_0F73) },
2643   { "pcmpeqb",          { MX, EM } },
2644   { "pcmpeqw",          { MX, EM } },
2645   { "pcmpeqd",          { MX, EM } },
2646   { "emms",             { XX } },
2647   /* 78 */
2648   { PREFIX_TABLE (PREFIX_0F78) },
2649   { PREFIX_TABLE (PREFIX_0F79) },
2650   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2651   { Bad_Opcode },
2652   { PREFIX_TABLE (PREFIX_0F7C) },
2653   { PREFIX_TABLE (PREFIX_0F7D) },
2654   { PREFIX_TABLE (PREFIX_0F7E) },
2655   { PREFIX_TABLE (PREFIX_0F7F) },
2656   /* 80 */
2657   { "joH",              { Jv, BND, cond_jump_flag } },
2658   { "jnoH",             { Jv, BND, cond_jump_flag } },
2659   { "jbH",              { Jv, BND, cond_jump_flag } },
2660   { "jaeH",             { Jv, BND, cond_jump_flag } },
2661   { "jeH",              { Jv, BND, cond_jump_flag } },
2662   { "jneH",             { Jv, BND, cond_jump_flag } },
2663   { "jbeH",             { Jv, BND, cond_jump_flag } },
2664   { "jaH",              { Jv, BND, cond_jump_flag } },
2665   /* 88 */
2666   { "jsH",              { Jv, BND, cond_jump_flag } },
2667   { "jnsH",             { Jv, BND, cond_jump_flag } },
2668   { "jpH",              { Jv, BND, cond_jump_flag } },
2669   { "jnpH",             { Jv, BND, cond_jump_flag } },
2670   { "jlH",              { Jv, BND, cond_jump_flag } },
2671   { "jgeH",             { Jv, BND, cond_jump_flag } },
2672   { "jleH",             { Jv, BND, cond_jump_flag } },
2673   { "jgH",              { Jv, BND, cond_jump_flag } },
2674   /* 90 */
2675   { "seto",             { Eb } },
2676   { "setno",            { Eb } },
2677   { "setb",             { Eb } },
2678   { "setae",            { Eb } },
2679   { "sete",             { Eb } },
2680   { "setne",            { Eb } },
2681   { "setbe",            { Eb } },
2682   { "seta",             { Eb } },
2683   /* 98 */
2684   { "sets",             { Eb } },
2685   { "setns",            { Eb } },
2686   { "setp",             { Eb } },
2687   { "setnp",            { Eb } },
2688   { "setl",             { Eb } },
2689   { "setge",            { Eb } },
2690   { "setle",            { Eb } },
2691   { "setg",             { Eb } },
2692   /* a0 */
2693   { "pushT",            { fs } },
2694   { "popT",             { fs } },
2695   { "cpuid",            { XX } },
2696   { "btS",              { Ev, Gv } },
2697   { "shldS",            { Ev, Gv, Ib } },
2698   { "shldS",            { Ev, Gv, CL } },
2699   { REG_TABLE (REG_0FA6) },
2700   { REG_TABLE (REG_0FA7) },
2701   /* a8 */
2702   { "pushT",            { gs } },
2703   { "popT",             { gs } },
2704   { "rsm",              { XX } },
2705   { "btsS",             { Evh1, Gv } },
2706   { "shrdS",            { Ev, Gv, Ib } },
2707   { "shrdS",            { Ev, Gv, CL } },
2708   { REG_TABLE (REG_0FAE) },
2709   { "imulS",            { Gv, Ev } },
2710   /* b0 */
2711   { "cmpxchgB",         { Ebh1, Gb } },
2712   { "cmpxchgS",         { Evh1, Gv } },
2713   { MOD_TABLE (MOD_0FB2) },
2714   { "btrS",             { Evh1, Gv } },
2715   { MOD_TABLE (MOD_0FB4) },
2716   { MOD_TABLE (MOD_0FB5) },
2717   { "movz{bR|x}",       { Gv, Eb } },
2718   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2719   /* b8 */
2720   { PREFIX_TABLE (PREFIX_0FB8) },
2721   { "ud1",              { XX } },
2722   { REG_TABLE (REG_0FBA) },
2723   { "btcS",             { Evh1, Gv } },
2724   { PREFIX_TABLE (PREFIX_0FBC) },
2725   { PREFIX_TABLE (PREFIX_0FBD) },
2726   { "movs{bR|x}",       { Gv, Eb } },
2727   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2728   /* c0 */
2729   { "xaddB",            { Ebh1, Gb } },
2730   { "xaddS",            { Evh1, Gv } },
2731   { PREFIX_TABLE (PREFIX_0FC2) },
2732   { PREFIX_TABLE (PREFIX_0FC3) },
2733   { "pinsrw",           { MX, Edqw, Ib } },
2734   { "pextrw",           { Gdq, MS, Ib } },
2735   { "shufpX",           { XM, EXx, Ib } },
2736   { REG_TABLE (REG_0FC7) },
2737   /* c8 */
2738   { "bswap",            { RMeAX } },
2739   { "bswap",            { RMeCX } },
2740   { "bswap",            { RMeDX } },
2741   { "bswap",            { RMeBX } },
2742   { "bswap",            { RMeSP } },
2743   { "bswap",            { RMeBP } },
2744   { "bswap",            { RMeSI } },
2745   { "bswap",            { RMeDI } },
2746   /* d0 */
2747   { PREFIX_TABLE (PREFIX_0FD0) },
2748   { "psrlw",            { MX, EM } },
2749   { "psrld",            { MX, EM } },
2750   { "psrlq",            { MX, EM } },
2751   { "paddq",            { MX, EM } },
2752   { "pmullw",           { MX, EM } },
2753   { PREFIX_TABLE (PREFIX_0FD6) },
2754   { MOD_TABLE (MOD_0FD7) },
2755   /* d8 */
2756   { "psubusb",          { MX, EM } },
2757   { "psubusw",          { MX, EM } },
2758   { "pminub",           { MX, EM } },
2759   { "pand",             { MX, EM } },
2760   { "paddusb",          { MX, EM } },
2761   { "paddusw",          { MX, EM } },
2762   { "pmaxub",           { MX, EM } },
2763   { "pandn",            { MX, EM } },
2764   /* e0 */
2765   { "pavgb",            { MX, EM } },
2766   { "psraw",            { MX, EM } },
2767   { "psrad",            { MX, EM } },
2768   { "pavgw",            { MX, EM } },
2769   { "pmulhuw",          { MX, EM } },
2770   { "pmulhw",           { MX, EM } },
2771   { PREFIX_TABLE (PREFIX_0FE6) },
2772   { PREFIX_TABLE (PREFIX_0FE7) },
2773   /* e8 */
2774   { "psubsb",           { MX, EM } },
2775   { "psubsw",           { MX, EM } },
2776   { "pminsw",           { MX, EM } },
2777   { "por",              { MX, EM } },
2778   { "paddsb",           { MX, EM } },
2779   { "paddsw",           { MX, EM } },
2780   { "pmaxsw",           { MX, EM } },
2781   { "pxor",             { MX, EM } },
2782   /* f0 */
2783   { PREFIX_TABLE (PREFIX_0FF0) },
2784   { "psllw",            { MX, EM } },
2785   { "pslld",            { MX, EM } },
2786   { "psllq",            { MX, EM } },
2787   { "pmuludq",          { MX, EM } },
2788   { "pmaddwd",          { MX, EM } },
2789   { "psadbw",           { MX, EM } },
2790   { PREFIX_TABLE (PREFIX_0FF7) },
2791   /* f8 */
2792   { "psubb",            { MX, EM } },
2793   { "psubw",            { MX, EM } },
2794   { "psubd",            { MX, EM } },
2795   { "psubq",            { MX, EM } },
2796   { "paddb",            { MX, EM } },
2797   { "paddw",            { MX, EM } },
2798   { "paddd",            { MX, EM } },
2799   { Bad_Opcode },
2800 };
2801
2802 static const unsigned char onebyte_has_modrm[256] = {
2803   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2804   /*       -------------------------------        */
2805   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2806   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2807   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2808   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2809   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2810   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2811   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2812   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2813   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2814   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2815   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2816   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2817   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2818   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2819   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2820   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2821   /*       -------------------------------        */
2822   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2823 };
2824
2825 static const unsigned char twobyte_has_modrm[256] = {
2826   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2827   /*       -------------------------------        */
2828   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2829   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2830   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2831   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2832   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2833   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2834   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2835   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2836   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2837   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2838   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2839   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2840   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2841   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2842   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2843   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2844   /*       -------------------------------        */
2845   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2846 };
2847
2848 static const unsigned char twobyte_has_mandatory_prefix[256] = {
2849   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2850   /*       -------------------------------        */
2851   /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
2852   /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
2853   /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
2854   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2855   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
2856   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2857   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2858   /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
2859   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2860   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
2861   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
2862   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
2863   /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
2864   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2865   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2866   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2867   /*       -------------------------------        */
2868   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2869 };
2870
2871 static char obuf[100];
2872 static char *obufp;
2873 static char *mnemonicendp;
2874 static char scratchbuf[100];
2875 static unsigned char *start_codep;
2876 static unsigned char *insn_codep;
2877 static unsigned char *codep;
2878 static unsigned char *end_codep;
2879 static int last_lock_prefix;
2880 static int last_repz_prefix;
2881 static int last_repnz_prefix;
2882 static int last_data_prefix;
2883 static int last_addr_prefix;
2884 static int last_rex_prefix;
2885 static int last_seg_prefix;
2886 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory.  */
2887 static int mandatory_prefix;
2888 /* The active segment register prefix.  */
2889 static int active_seg_prefix;
2890 #define MAX_CODE_LENGTH 15
2891 /* We can up to 14 prefixes since the maximum instruction length is
2892    15bytes.  */
2893 static int all_prefixes[MAX_CODE_LENGTH - 1];
2894 static disassemble_info *the_info;
2895 static struct
2896   {
2897     int mod;
2898     int reg;
2899     int rm;
2900   }
2901 modrm;
2902 static unsigned char need_modrm;
2903 static struct
2904   {
2905     int scale;
2906     int index;
2907     int base;
2908   }
2909 sib;
2910 static struct
2911   {
2912     int register_specifier;
2913     int length;
2914     int prefix;
2915     int w;
2916     int evex;
2917     int r;
2918     int v;
2919     int mask_register_specifier;
2920     int zeroing;
2921     int ll;
2922     int b;
2923   }
2924 vex;
2925 static unsigned char need_vex;
2926 static unsigned char need_vex_reg;
2927 static unsigned char vex_w_done;
2928
2929 struct op
2930   {
2931     const char *name;
2932     unsigned int len;
2933   };
2934
2935 /* If we are accessing mod/rm/reg without need_modrm set, then the
2936    values are stale.  Hitting this abort likely indicates that you
2937    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2938 #define MODRM_CHECK  if (!need_modrm) abort ()
2939
2940 static const char **names64;
2941 static const char **names32;
2942 static const char **names16;
2943 static const char **names8;
2944 static const char **names8rex;
2945 static const char **names_seg;
2946 static const char *index64;
2947 static const char *index32;
2948 static const char **index16;
2949 static const char **names_bnd;
2950
2951 static const char *intel_names64[] = {
2952   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2953   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2954 };
2955 static const char *intel_names32[] = {
2956   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2957   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2958 };
2959 static const char *intel_names16[] = {
2960   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2961   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2962 };
2963 static const char *intel_names8[] = {
2964   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2965 };
2966 static const char *intel_names8rex[] = {
2967   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2968   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2969 };
2970 static const char *intel_names_seg[] = {
2971   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2972 };
2973 static const char *intel_index64 = "riz";
2974 static const char *intel_index32 = "eiz";
2975 static const char *intel_index16[] = {
2976   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2977 };
2978
2979 static const char *att_names64[] = {
2980   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2981   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2982 };
2983 static const char *att_names32[] = {
2984   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2985   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2986 };
2987 static const char *att_names16[] = {
2988   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2989   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2990 };
2991 static const char *att_names8[] = {
2992   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2993 };
2994 static const char *att_names8rex[] = {
2995   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2996   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2997 };
2998 static const char *att_names_seg[] = {
2999   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3000 };
3001 static const char *att_index64 = "%riz";
3002 static const char *att_index32 = "%eiz";
3003 static const char *att_index16[] = {
3004   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3005 };
3006
3007 static const char **names_mm;
3008 static const char *intel_names_mm[] = {
3009   "mm0", "mm1", "mm2", "mm3",
3010   "mm4", "mm5", "mm6", "mm7"
3011 };
3012 static const char *att_names_mm[] = {
3013   "%mm0", "%mm1", "%mm2", "%mm3",
3014   "%mm4", "%mm5", "%mm6", "%mm7"
3015 };
3016
3017 static const char *intel_names_bnd[] = {
3018   "bnd0", "bnd1", "bnd2", "bnd3"
3019 };
3020
3021 static const char *att_names_bnd[] = {
3022   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3023 };
3024
3025 static const char **names_xmm;
3026 static const char *intel_names_xmm[] = {
3027   "xmm0", "xmm1", "xmm2", "xmm3",
3028   "xmm4", "xmm5", "xmm6", "xmm7",
3029   "xmm8", "xmm9", "xmm10", "xmm11",
3030   "xmm12", "xmm13", "xmm14", "xmm15",
3031   "xmm16", "xmm17", "xmm18", "xmm19",
3032   "xmm20", "xmm21", "xmm22", "xmm23",
3033   "xmm24", "xmm25", "xmm26", "xmm27",
3034   "xmm28", "xmm29", "xmm30", "xmm31"
3035 };
3036 static const char *att_names_xmm[] = {
3037   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3038   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3039   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3040   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3041   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3042   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3043   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3044   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3045 };
3046
3047 static const char **names_ymm;
3048 static const char *intel_names_ymm[] = {
3049   "ymm0", "ymm1", "ymm2", "ymm3",
3050   "ymm4", "ymm5", "ymm6", "ymm7",
3051   "ymm8", "ymm9", "ymm10", "ymm11",
3052   "ymm12", "ymm13", "ymm14", "ymm15",
3053   "ymm16", "ymm17", "ymm18", "ymm19",
3054   "ymm20", "ymm21", "ymm22", "ymm23",
3055   "ymm24", "ymm25", "ymm26", "ymm27",
3056   "ymm28", "ymm29", "ymm30", "ymm31"
3057 };
3058 static const char *att_names_ymm[] = {
3059   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3060   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3061   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3062   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3063   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3064   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3065   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3066   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3067 };
3068
3069 static const char **names_zmm;
3070 static const char *intel_names_zmm[] = {
3071   "zmm0", "zmm1", "zmm2", "zmm3",
3072   "zmm4", "zmm5", "zmm6", "zmm7",
3073   "zmm8", "zmm9", "zmm10", "zmm11",
3074   "zmm12", "zmm13", "zmm14", "zmm15",
3075   "zmm16", "zmm17", "zmm18", "zmm19",
3076   "zmm20", "zmm21", "zmm22", "zmm23",
3077   "zmm24", "zmm25", "zmm26", "zmm27",
3078   "zmm28", "zmm29", "zmm30", "zmm31"
3079 };
3080 static const char *att_names_zmm[] = {
3081   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3082   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3083   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3084   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3085   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3086   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3087   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3088   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3089 };
3090
3091 static const char **names_mask;
3092 static const char *intel_names_mask[] = {
3093   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3094 };
3095 static const char *att_names_mask[] = {
3096   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3097 };
3098
3099 static const char *names_rounding[] =
3100 {
3101   "{rn-sae}",
3102   "{rd-sae}",
3103   "{ru-sae}",
3104   "{rz-sae}"
3105 };
3106
3107 static const struct dis386 reg_table[][8] = {
3108   /* REG_80 */
3109   {
3110     { "addA",   { Ebh1, Ib } },
3111     { "orA",    { Ebh1, Ib } },
3112     { "adcA",   { Ebh1, Ib } },
3113     { "sbbA",   { Ebh1, Ib } },
3114     { "andA",   { Ebh1, Ib } },
3115     { "subA",   { Ebh1, Ib } },
3116     { "xorA",   { Ebh1, Ib } },
3117     { "cmpA",   { Eb, Ib } },
3118   },
3119   /* REG_81 */
3120   {
3121     { "addQ",   { Evh1, Iv } },
3122     { "orQ",    { Evh1, Iv } },
3123     { "adcQ",   { Evh1, Iv } },
3124     { "sbbQ",   { Evh1, Iv } },
3125     { "andQ",   { Evh1, Iv } },
3126     { "subQ",   { Evh1, Iv } },
3127     { "xorQ",   { Evh1, Iv } },
3128     { "cmpQ",   { Ev, Iv } },
3129   },
3130   /* REG_82 */
3131   {
3132     { "addQ",   { Evh1, sIb } },
3133     { "orQ",    { Evh1, sIb } },
3134     { "adcQ",   { Evh1, sIb } },
3135     { "sbbQ",   { Evh1, sIb } },
3136     { "andQ",   { Evh1, sIb } },
3137     { "subQ",   { Evh1, sIb } },
3138     { "xorQ",   { Evh1, sIb } },
3139     { "cmpQ",   { Ev, sIb } },
3140   },
3141   /* REG_8F */
3142   {
3143     { "popU",   { stackEv } },
3144     { XOP_8F_TABLE (XOP_09) },
3145     { Bad_Opcode },
3146     { Bad_Opcode },
3147     { Bad_Opcode },
3148     { XOP_8F_TABLE (XOP_09) },
3149   },
3150   /* REG_C0 */
3151   {
3152     { "rolA",   { Eb, Ib } },
3153     { "rorA",   { Eb, Ib } },
3154     { "rclA",   { Eb, Ib } },
3155     { "rcrA",   { Eb, Ib } },
3156     { "shlA",   { Eb, Ib } },
3157     { "shrA",   { Eb, Ib } },
3158     { Bad_Opcode },
3159     { "sarA",   { Eb, Ib } },
3160   },
3161   /* REG_C1 */
3162   {
3163     { "rolQ",   { Ev, Ib } },
3164     { "rorQ",   { Ev, Ib } },
3165     { "rclQ",   { Ev, Ib } },
3166     { "rcrQ",   { Ev, Ib } },
3167     { "shlQ",   { Ev, Ib } },
3168     { "shrQ",   { Ev, Ib } },
3169     { Bad_Opcode },
3170     { "sarQ",   { Ev, Ib } },
3171   },
3172   /* REG_C6 */
3173   {
3174     { "movA",   { Ebh3, Ib } },
3175     { Bad_Opcode },
3176     { Bad_Opcode },
3177     { Bad_Opcode },
3178     { Bad_Opcode },
3179     { Bad_Opcode },
3180     { Bad_Opcode },
3181     { MOD_TABLE (MOD_C6_REG_7) },
3182   },
3183   /* REG_C7 */
3184   {
3185     { "movQ",   { Evh3, Iv } },
3186     { Bad_Opcode },
3187     { Bad_Opcode },
3188     { Bad_Opcode },
3189     { Bad_Opcode },
3190     { Bad_Opcode },
3191     { Bad_Opcode },
3192     { MOD_TABLE (MOD_C7_REG_7) },
3193   },
3194   /* REG_D0 */
3195   {
3196     { "rolA",   { Eb, I1 } },
3197     { "rorA",   { Eb, I1 } },
3198     { "rclA",   { Eb, I1 } },
3199     { "rcrA",   { Eb, I1 } },
3200     { "shlA",   { Eb, I1 } },
3201     { "shrA",   { Eb, I1 } },
3202     { Bad_Opcode },
3203     { "sarA",   { Eb, I1 } },
3204   },
3205   /* REG_D1 */
3206   {
3207     { "rolQ",   { Ev, I1 } },
3208     { "rorQ",   { Ev, I1 } },
3209     { "rclQ",   { Ev, I1 } },
3210     { "rcrQ",   { Ev, I1 } },
3211     { "shlQ",   { Ev, I1 } },
3212     { "shrQ",   { Ev, I1 } },
3213     { Bad_Opcode },
3214     { "sarQ",   { Ev, I1 } },
3215   },
3216   /* REG_D2 */
3217   {
3218     { "rolA",   { Eb, CL } },
3219     { "rorA",   { Eb, CL } },
3220     { "rclA",   { Eb, CL } },
3221     { "rcrA",   { Eb, CL } },
3222     { "shlA",   { Eb, CL } },
3223     { "shrA",   { Eb, CL } },
3224     { Bad_Opcode },
3225     { "sarA",   { Eb, CL } },
3226   },
3227   /* REG_D3 */
3228   {
3229     { "rolQ",   { Ev, CL } },
3230     { "rorQ",   { Ev, CL } },
3231     { "rclQ",   { Ev, CL } },
3232     { "rcrQ",   { Ev, CL } },
3233     { "shlQ",   { Ev, CL } },
3234     { "shrQ",   { Ev, CL } },
3235     { Bad_Opcode },
3236     { "sarQ",   { Ev, CL } },
3237   },
3238   /* REG_F6 */
3239   {
3240     { "testA",  { Eb, Ib } },
3241     { Bad_Opcode },
3242     { "notA",   { Ebh1 } },
3243     { "negA",   { Ebh1 } },
3244     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
3245     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
3246     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
3247     { "idivA",  { Eb } },       /* and idiv for consistency.               */
3248   },
3249   /* REG_F7 */
3250   {
3251     { "testQ",  { Ev, Iv } },
3252     { Bad_Opcode },
3253     { "notQ",   { Evh1 } },
3254     { "negQ",   { Evh1 } },
3255     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
3256     { "imulQ",  { Ev } },
3257     { "divQ",   { Ev } },
3258     { "idivQ",  { Ev } },
3259   },
3260   /* REG_FE */
3261   {
3262     { "incA",   { Ebh1 } },
3263     { "decA",   { Ebh1 } },
3264   },
3265   /* REG_FF */
3266   {
3267     { "incQ",   { Evh1 } },
3268     { "decQ",   { Evh1 } },
3269     { "call{T|}", { indirEv, BND } },
3270     { MOD_TABLE (MOD_FF_REG_3) },
3271     { "jmp{T|}", { indirEv, BND } },
3272     { MOD_TABLE (MOD_FF_REG_5) },
3273     { "pushU",  { stackEv } },
3274     { Bad_Opcode },
3275   },
3276   /* REG_0F00 */
3277   {
3278     { "sldtD",  { Sv } },
3279     { "strD",   { Sv } },
3280     { "lldt",   { Ew } },
3281     { "ltr",    { Ew } },
3282     { "verr",   { Ew } },
3283     { "verw",   { Ew } },
3284     { Bad_Opcode },
3285     { Bad_Opcode },
3286   },
3287   /* REG_0F01 */
3288   {
3289     { MOD_TABLE (MOD_0F01_REG_0) },
3290     { MOD_TABLE (MOD_0F01_REG_1) },
3291     { MOD_TABLE (MOD_0F01_REG_2) },
3292     { MOD_TABLE (MOD_0F01_REG_3) },
3293     { "smswD",  { Sv } },
3294     { Bad_Opcode },
3295     { "lmsw",   { Ew } },
3296     { MOD_TABLE (MOD_0F01_REG_7) },
3297   },
3298   /* REG_0F0D */
3299   {
3300     { "prefetch",       { Mb } },
3301     { "prefetchw",      { Mb } },
3302     { "prefetchwt1",    { Mb } },
3303     { "prefetch",       { Mb } },
3304     { "prefetch",       { Mb } },
3305     { "prefetch",       { Mb } },
3306     { "prefetch",       { Mb } },
3307     { "prefetch",       { Mb } },
3308   },
3309   /* REG_0F18 */
3310   {
3311     { MOD_TABLE (MOD_0F18_REG_0) },
3312     { MOD_TABLE (MOD_0F18_REG_1) },
3313     { MOD_TABLE (MOD_0F18_REG_2) },
3314     { MOD_TABLE (MOD_0F18_REG_3) },
3315     { MOD_TABLE (MOD_0F18_REG_4) },
3316     { MOD_TABLE (MOD_0F18_REG_5) },
3317     { MOD_TABLE (MOD_0F18_REG_6) },
3318     { MOD_TABLE (MOD_0F18_REG_7) },
3319   },
3320   /* REG_0F71 */
3321   {
3322     { Bad_Opcode },
3323     { Bad_Opcode },
3324     { MOD_TABLE (MOD_0F71_REG_2) },
3325     { Bad_Opcode },
3326     { MOD_TABLE (MOD_0F71_REG_4) },
3327     { Bad_Opcode },
3328     { MOD_TABLE (MOD_0F71_REG_6) },
3329   },
3330   /* REG_0F72 */
3331   {
3332     { Bad_Opcode },
3333     { Bad_Opcode },
3334     { MOD_TABLE (MOD_0F72_REG_2) },
3335     { Bad_Opcode },
3336     { MOD_TABLE (MOD_0F72_REG_4) },
3337     { Bad_Opcode },
3338     { MOD_TABLE (MOD_0F72_REG_6) },
3339   },
3340   /* REG_0F73 */
3341   {
3342     { Bad_Opcode },
3343     { Bad_Opcode },
3344     { MOD_TABLE (MOD_0F73_REG_2) },
3345     { MOD_TABLE (MOD_0F73_REG_3) },
3346     { Bad_Opcode },
3347     { Bad_Opcode },
3348     { MOD_TABLE (MOD_0F73_REG_6) },
3349     { MOD_TABLE (MOD_0F73_REG_7) },
3350   },
3351   /* REG_0FA6 */
3352   {
3353     { "montmul",        { { OP_0f07, 0 } } },
3354     { "xsha1",          { { OP_0f07, 0 } } },
3355     { "xsha256",        { { OP_0f07, 0 } } },
3356   },
3357   /* REG_0FA7 */
3358   {
3359     { "xstore-rng",     { { OP_0f07, 0 } } },
3360     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
3361     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
3362     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
3363     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
3364     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
3365   },
3366   /* REG_0FAE */
3367   {
3368     { MOD_TABLE (MOD_0FAE_REG_0) },
3369     { MOD_TABLE (MOD_0FAE_REG_1) },
3370     { MOD_TABLE (MOD_0FAE_REG_2) },
3371     { MOD_TABLE (MOD_0FAE_REG_3) },
3372     { MOD_TABLE (MOD_0FAE_REG_4) },
3373     { MOD_TABLE (MOD_0FAE_REG_5) },
3374     { MOD_TABLE (MOD_0FAE_REG_6) },
3375     { MOD_TABLE (MOD_0FAE_REG_7) },
3376   },
3377   /* REG_0FBA */
3378   {
3379     { Bad_Opcode },
3380     { Bad_Opcode },
3381     { Bad_Opcode },
3382     { Bad_Opcode },
3383     { "btQ",    { Ev, Ib } },
3384     { "btsQ",   { Evh1, Ib } },
3385     { "btrQ",   { Evh1, Ib } },
3386     { "btcQ",   { Evh1, Ib } },
3387   },
3388   /* REG_0FC7 */
3389   {
3390     { Bad_Opcode },
3391     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3392     { Bad_Opcode },
3393     { MOD_TABLE (MOD_0FC7_REG_3) },
3394     { MOD_TABLE (MOD_0FC7_REG_4) },
3395     { MOD_TABLE (MOD_0FC7_REG_5) },
3396     { MOD_TABLE (MOD_0FC7_REG_6) },
3397     { MOD_TABLE (MOD_0FC7_REG_7) },
3398   },
3399   /* REG_VEX_0F71 */
3400   {
3401     { Bad_Opcode },
3402     { Bad_Opcode },
3403     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3404     { Bad_Opcode },
3405     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3406     { Bad_Opcode },
3407     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3408   },
3409   /* REG_VEX_0F72 */
3410   {
3411     { Bad_Opcode },
3412     { Bad_Opcode },
3413     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3414     { Bad_Opcode },
3415     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3416     { Bad_Opcode },
3417     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3418   },
3419   /* REG_VEX_0F73 */
3420   {
3421     { Bad_Opcode },
3422     { Bad_Opcode },
3423     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3424     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3425     { Bad_Opcode },
3426     { Bad_Opcode },
3427     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3428     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3429   },
3430   /* REG_VEX_0FAE */
3431   {
3432     { Bad_Opcode },
3433     { Bad_Opcode },
3434     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3435     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3436   },
3437   /* REG_VEX_0F38F3 */
3438   {
3439     { Bad_Opcode },
3440     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3441     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3442     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3443   },
3444   /* REG_XOP_LWPCB */
3445   {
3446     { "llwpcb", { { OP_LWPCB_E, 0 } } },
3447     { "slwpcb", { { OP_LWPCB_E, 0 } } },
3448   },
3449   /* REG_XOP_LWP */
3450   {
3451     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3452     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3453   },
3454   /* REG_XOP_TBM_01 */
3455   {
3456     { Bad_Opcode },
3457     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
3458     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
3459     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
3460     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
3461     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
3462     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
3463     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3464   },
3465   /* REG_XOP_TBM_02 */
3466   {
3467     { Bad_Opcode },
3468     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3469     { Bad_Opcode },
3470     { Bad_Opcode },
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473     { "blci",   { { OP_LWP_E, 0 }, Ev } },
3474   },
3475 #define NEED_REG_TABLE
3476 #include "i386-dis-evex.h"
3477 #undef NEED_REG_TABLE
3478 };
3479
3480 static const struct dis386 prefix_table[][4] = {
3481   /* PREFIX_90 */
3482   {
3483     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3484     { "pause", { XX } },
3485     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3486   },
3487
3488   /* PREFIX_0F10 */
3489   {
3490     { "movups", { XM, EXx } },
3491     { "movss",  { XM, EXd } },
3492     { "movupd", { XM, EXx } },
3493     { "movsd",  { XM, EXq } },
3494   },
3495
3496   /* PREFIX_0F11 */
3497   {
3498     { "movups", { EXxS, XM } },
3499     { "movss",  { EXdS, XM } },
3500     { "movupd", { EXxS, XM } },
3501     { "movsd",  { EXqS, XM } },
3502   },
3503
3504   /* PREFIX_0F12 */
3505   {
3506     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3507     { "movsldup", { XM, EXx } },
3508     { "movlpd", { XM, EXq } },
3509     { "movddup", { XM, EXq } },
3510   },
3511
3512   /* PREFIX_0F16 */
3513   {
3514     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3515     { "movshdup", { XM, EXx } },
3516     { "movhpd", { XM, EXq } },
3517   },
3518
3519   /* PREFIX_0F1A */
3520   {
3521     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3522     { "bndcl",  { Gbnd, Ev_bnd } },
3523     { "bndmov", { Gbnd, Ebnd } },
3524     { "bndcu",  { Gbnd, Ev_bnd } },
3525   },
3526
3527   /* PREFIX_0F1B */
3528   {
3529     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3530     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3531     { "bndmov", { Ebnd, Gbnd } },
3532     { "bndcn",  { Gbnd, Ev_bnd } },
3533   },
3534
3535   /* PREFIX_0F2A */
3536   {
3537     { "cvtpi2ps", { XM, EMCq } },
3538     { "cvtsi2ss%LQ", { XM, Ev } },
3539     { "cvtpi2pd", { XM, EMCq } },
3540     { "cvtsi2sd%LQ", { XM, Ev } },
3541   },
3542
3543   /* PREFIX_0F2B */
3544   {
3545     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3546     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3547     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3548     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3549   },
3550
3551   /* PREFIX_0F2C */
3552   {
3553     { "cvttps2pi", { MXC, EXq } },
3554     { "cvttss2siY", { Gv, EXd } },
3555     { "cvttpd2pi", { MXC, EXx } },
3556     { "cvttsd2siY", { Gv, EXq } },
3557   },
3558
3559   /* PREFIX_0F2D */
3560   {
3561     { "cvtps2pi", { MXC, EXq } },
3562     { "cvtss2siY", { Gv, EXd } },
3563     { "cvtpd2pi", { MXC, EXx } },
3564     { "cvtsd2siY", { Gv, EXq } },
3565   },
3566
3567   /* PREFIX_0F2E */
3568   {
3569     { "ucomiss",{ XM, EXd } },
3570     { Bad_Opcode },
3571     { "ucomisd",{ XM, EXq } },
3572   },
3573
3574   /* PREFIX_0F2F */
3575   {
3576     { "comiss", { XM, EXd } },
3577     { Bad_Opcode },
3578     { "comisd", { XM, EXq } },
3579   },
3580
3581   /* PREFIX_0F51 */
3582   {
3583     { "sqrtps", { XM, EXx } },
3584     { "sqrtss", { XM, EXd } },
3585     { "sqrtpd", { XM, EXx } },
3586     { "sqrtsd", { XM, EXq } },
3587   },
3588
3589   /* PREFIX_0F52 */
3590   {
3591     { "rsqrtps",{ XM, EXx } },
3592     { "rsqrtss",{ XM, EXd } },
3593   },
3594
3595   /* PREFIX_0F53 */
3596   {
3597     { "rcpps",  { XM, EXx } },
3598     { "rcpss",  { XM, EXd } },
3599   },
3600
3601   /* PREFIX_0F58 */
3602   {
3603     { "addps", { XM, EXx } },
3604     { "addss", { XM, EXd } },
3605     { "addpd", { XM, EXx } },
3606     { "addsd", { XM, EXq } },
3607   },
3608
3609   /* PREFIX_0F59 */
3610   {
3611     { "mulps",  { XM, EXx } },
3612     { "mulss",  { XM, EXd } },
3613     { "mulpd",  { XM, EXx } },
3614     { "mulsd",  { XM, EXq } },
3615   },
3616
3617   /* PREFIX_0F5A */
3618   {
3619     { "cvtps2pd", { XM, EXq } },
3620     { "cvtss2sd", { XM, EXd } },
3621     { "cvtpd2ps", { XM, EXx } },
3622     { "cvtsd2ss", { XM, EXq } },
3623   },
3624
3625   /* PREFIX_0F5B */
3626   {
3627     { "cvtdq2ps", { XM, EXx } },
3628     { "cvttps2dq", { XM, EXx } },
3629     { "cvtps2dq", { XM, EXx } },
3630   },
3631
3632   /* PREFIX_0F5C */
3633   {
3634     { "subps",  { XM, EXx } },
3635     { "subss",  { XM, EXd } },
3636     { "subpd",  { XM, EXx } },
3637     { "subsd",  { XM, EXq } },
3638   },
3639
3640   /* PREFIX_0F5D */
3641   {
3642     { "minps",  { XM, EXx } },
3643     { "minss",  { XM, EXd } },
3644     { "minpd",  { XM, EXx } },
3645     { "minsd",  { XM, EXq } },
3646   },
3647
3648   /* PREFIX_0F5E */
3649   {
3650     { "divps",  { XM, EXx } },
3651     { "divss",  { XM, EXd } },
3652     { "divpd",  { XM, EXx } },
3653     { "divsd",  { XM, EXq } },
3654   },
3655
3656   /* PREFIX_0F5F */
3657   {
3658     { "maxps",  { XM, EXx } },
3659     { "maxss",  { XM, EXd } },
3660     { "maxpd",  { XM, EXx } },
3661     { "maxsd",  { XM, EXq } },
3662   },
3663
3664   /* PREFIX_0F60 */
3665   {
3666     { "punpcklbw",{ MX, EMd } },
3667     { Bad_Opcode },
3668     { "punpcklbw",{ MX, EMx } },
3669   },
3670
3671   /* PREFIX_0F61 */
3672   {
3673     { "punpcklwd",{ MX, EMd } },
3674     { Bad_Opcode },
3675     { "punpcklwd",{ MX, EMx } },
3676   },
3677
3678   /* PREFIX_0F62 */
3679   {
3680     { "punpckldq",{ MX, EMd } },
3681     { Bad_Opcode },
3682     { "punpckldq",{ MX, EMx } },
3683   },
3684
3685   /* PREFIX_0F6C */
3686   {
3687     { Bad_Opcode },
3688     { Bad_Opcode },
3689     { "punpcklqdq", { XM, EXx } },
3690   },
3691
3692   /* PREFIX_0F6D */
3693   {
3694     { Bad_Opcode },
3695     { Bad_Opcode },
3696     { "punpckhqdq", { XM, EXx } },
3697   },
3698
3699   /* PREFIX_0F6F */
3700   {
3701     { "movq",   { MX, EM } },
3702     { "movdqu", { XM, EXx } },
3703     { "movdqa", { XM, EXx } },
3704   },
3705
3706   /* PREFIX_0F70 */
3707   {
3708     { "pshufw", { MX, EM, Ib } },
3709     { "pshufhw",{ XM, EXx, Ib } },
3710     { "pshufd", { XM, EXx, Ib } },
3711     { "pshuflw",{ XM, EXx, Ib } },
3712   },
3713
3714   /* PREFIX_0F73_REG_3 */
3715   {
3716     { Bad_Opcode },
3717     { Bad_Opcode },
3718     { "psrldq", { XS, Ib } },
3719   },
3720
3721   /* PREFIX_0F73_REG_7 */
3722   {
3723     { Bad_Opcode },
3724     { Bad_Opcode },
3725     { "pslldq", { XS, Ib } },
3726   },
3727
3728   /* PREFIX_0F78 */
3729   {
3730     {"vmread",  { Em, Gm } },
3731     { Bad_Opcode },
3732     {"extrq",   { XS, Ib, Ib } },
3733     {"insertq", { XM, XS, Ib, Ib } },
3734   },
3735
3736   /* PREFIX_0F79 */
3737   {
3738     {"vmwrite", { Gm, Em } },
3739     { Bad_Opcode },
3740     {"extrq",   { XM, XS } },
3741     {"insertq", { XM, XS } },
3742   },
3743
3744   /* PREFIX_0F7C */
3745   {
3746     { Bad_Opcode },
3747     { Bad_Opcode },
3748     { "haddpd", { XM, EXx } },
3749     { "haddps", { XM, EXx } },
3750   },
3751
3752   /* PREFIX_0F7D */
3753   {
3754     { Bad_Opcode },
3755     { Bad_Opcode },
3756     { "hsubpd", { XM, EXx } },
3757     { "hsubps", { XM, EXx } },
3758   },
3759
3760   /* PREFIX_0F7E */
3761   {
3762     { "movK",   { Edq, MX } },
3763     { "movq",   { XM, EXq } },
3764     { "movK",   { Edq, XM } },
3765   },
3766
3767   /* PREFIX_0F7F */
3768   {
3769     { "movq",   { EMS, MX } },
3770     { "movdqu", { EXxS, XM } },
3771     { "movdqa", { EXxS, XM } },
3772   },
3773
3774   /* PREFIX_0FAE_REG_0 */
3775   {
3776     { Bad_Opcode },
3777     { "rdfsbase", { Ev } },
3778   },
3779
3780   /* PREFIX_0FAE_REG_1 */
3781   {
3782     { Bad_Opcode },
3783     { "rdgsbase", { Ev } },
3784   },
3785
3786   /* PREFIX_0FAE_REG_2 */
3787   {
3788     { Bad_Opcode },
3789     { "wrfsbase", { Ev } },
3790   },
3791
3792   /* PREFIX_0FAE_REG_3 */
3793   {
3794     { Bad_Opcode },
3795     { "wrgsbase", { Ev } },
3796   },
3797
3798   /* PREFIX_0FAE_REG_7 */
3799   {
3800     { "clflush",        { Mb } },
3801     { Bad_Opcode },
3802     { "clflushopt",     { Mb } },
3803   },
3804
3805   /* PREFIX_0FB8 */
3806   {
3807     { Bad_Opcode },
3808     { "popcntS", { Gv, Ev } },
3809   },
3810
3811   /* PREFIX_0FBC */
3812   {
3813     { "bsfS",   { Gv, Ev } },
3814     { "tzcntS", { Gv, Ev } },
3815     { "bsfS",   { Gv, Ev } },
3816   },
3817
3818   /* PREFIX_0FBD */
3819   {
3820     { "bsrS",   { Gv, Ev } },
3821     { "lzcntS", { Gv, Ev } },
3822     { "bsrS",   { Gv, Ev } },
3823   },
3824
3825   /* PREFIX_0FC2 */
3826   {
3827     { "cmpps",  { XM, EXx, CMP } },
3828     { "cmpss",  { XM, EXd, CMP } },
3829     { "cmppd",  { XM, EXx, CMP } },
3830     { "cmpsd",  { XM, EXq, CMP } },
3831   },
3832
3833   /* PREFIX_0FC3 */
3834   {
3835     { "movntiS", { Ma, Gv } },
3836   },
3837
3838   /* PREFIX_0FC7_REG_6 */
3839   {
3840     { "vmptrld",{ Mq } },
3841     { "vmxon",  { Mq } },
3842     { "vmclear",{ Mq } },
3843   },
3844
3845   /* PREFIX_0FD0 */
3846   {
3847     { Bad_Opcode },
3848     { Bad_Opcode },
3849     { "addsubpd", { XM, EXx } },
3850     { "addsubps", { XM, EXx } },
3851   },
3852
3853   /* PREFIX_0FD6 */
3854   {
3855     { Bad_Opcode },
3856     { "movq2dq",{ XM, MS } },
3857     { "movq",   { EXqS, XM } },
3858     { "movdq2q",{ MX, XS } },
3859   },
3860
3861   /* PREFIX_0FE6 */
3862   {
3863     { Bad_Opcode },
3864     { "cvtdq2pd", { XM, EXq } },
3865     { "cvttpd2dq", { XM, EXx } },
3866     { "cvtpd2dq", { XM, EXx } },
3867   },
3868
3869   /* PREFIX_0FE7 */
3870   {
3871     { "movntq", { Mq, MX } },
3872     { Bad_Opcode },
3873     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3874   },
3875
3876   /* PREFIX_0FF0 */
3877   {
3878     { Bad_Opcode },
3879     { Bad_Opcode },
3880     { Bad_Opcode },
3881     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3882   },
3883
3884   /* PREFIX_0FF7 */
3885   {
3886     { "maskmovq", { MX, MS } },
3887     { Bad_Opcode },
3888     { "maskmovdqu", { XM, XS } },
3889   },
3890
3891   /* PREFIX_0F3810 */
3892   {
3893     { Bad_Opcode },
3894     { Bad_Opcode },
3895     { "pblendvb", { XM, EXx, XMM0 } },
3896   },
3897
3898   /* PREFIX_0F3814 */
3899   {
3900     { Bad_Opcode },
3901     { Bad_Opcode },
3902     { "blendvps", { XM, EXx, XMM0 } },
3903   },
3904
3905   /* PREFIX_0F3815 */
3906   {
3907     { Bad_Opcode },
3908     { Bad_Opcode },
3909     { "blendvpd", { XM, EXx, XMM0 } },
3910   },
3911
3912   /* PREFIX_0F3817 */
3913   {
3914     { Bad_Opcode },
3915     { Bad_Opcode },
3916     { "ptest",  { XM, EXx } },
3917   },
3918
3919   /* PREFIX_0F3820 */
3920   {
3921     { Bad_Opcode },
3922     { Bad_Opcode },
3923     { "pmovsxbw", { XM, EXq } },
3924   },
3925
3926   /* PREFIX_0F3821 */
3927   {
3928     { Bad_Opcode },
3929     { Bad_Opcode },
3930     { "pmovsxbd", { XM, EXd } },
3931   },
3932
3933   /* PREFIX_0F3822 */
3934   {
3935     { Bad_Opcode },
3936     { Bad_Opcode },
3937     { "pmovsxbq", { XM, EXw } },
3938   },
3939
3940   /* PREFIX_0F3823 */
3941   {
3942     { Bad_Opcode },
3943     { Bad_Opcode },
3944     { "pmovsxwd", { XM, EXq } },
3945   },
3946
3947   /* PREFIX_0F3824 */
3948   {
3949     { Bad_Opcode },
3950     { Bad_Opcode },
3951     { "pmovsxwq", { XM, EXd } },
3952   },
3953
3954   /* PREFIX_0F3825 */
3955   {
3956     { Bad_Opcode },
3957     { Bad_Opcode },
3958     { "pmovsxdq", { XM, EXq } },
3959   },
3960
3961   /* PREFIX_0F3828 */
3962   {
3963     { Bad_Opcode },
3964     { Bad_Opcode },
3965     { "pmuldq", { XM, EXx } },
3966   },
3967
3968   /* PREFIX_0F3829 */
3969   {
3970     { Bad_Opcode },
3971     { Bad_Opcode },
3972     { "pcmpeqq", { XM, EXx } },
3973   },
3974
3975   /* PREFIX_0F382A */
3976   {
3977     { Bad_Opcode },
3978     { Bad_Opcode },
3979     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3980   },
3981
3982   /* PREFIX_0F382B */
3983   {
3984     { Bad_Opcode },
3985     { Bad_Opcode },
3986     { "packusdw", { XM, EXx } },
3987   },
3988
3989   /* PREFIX_0F3830 */
3990   {
3991     { Bad_Opcode },
3992     { Bad_Opcode },
3993     { "pmovzxbw", { XM, EXq } },
3994   },
3995
3996   /* PREFIX_0F3831 */
3997   {
3998     { Bad_Opcode },
3999     { Bad_Opcode },
4000     { "pmovzxbd", { XM, EXd } },
4001   },
4002
4003   /* PREFIX_0F3832 */
4004   {
4005     { Bad_Opcode },
4006     { Bad_Opcode },
4007     { "pmovzxbq", { XM, EXw } },
4008   },
4009
4010   /* PREFIX_0F3833 */
4011   {
4012     { Bad_Opcode },
4013     { Bad_Opcode },
4014     { "pmovzxwd", { XM, EXq } },
4015   },
4016
4017   /* PREFIX_0F3834 */
4018   {
4019     { Bad_Opcode },
4020     { Bad_Opcode },
4021     { "pmovzxwq", { XM, EXd } },
4022   },
4023
4024   /* PREFIX_0F3835 */
4025   {
4026     { Bad_Opcode },
4027     { Bad_Opcode },
4028     { "pmovzxdq", { XM, EXq } },
4029   },
4030
4031   /* PREFIX_0F3837 */
4032   {
4033     { Bad_Opcode },
4034     { Bad_Opcode },
4035     { "pcmpgtq", { XM, EXx } },
4036   },
4037
4038   /* PREFIX_0F3838 */
4039   {
4040     { Bad_Opcode },
4041     { Bad_Opcode },
4042     { "pminsb", { XM, EXx } },
4043   },
4044
4045   /* PREFIX_0F3839 */
4046   {
4047     { Bad_Opcode },
4048     { Bad_Opcode },
4049     { "pminsd", { XM, EXx } },
4050   },
4051
4052   /* PREFIX_0F383A */
4053   {
4054     { Bad_Opcode },
4055     { Bad_Opcode },
4056     { "pminuw", { XM, EXx } },
4057   },
4058
4059   /* PREFIX_0F383B */
4060   {
4061     { Bad_Opcode },
4062     { Bad_Opcode },
4063     { "pminud", { XM, EXx } },
4064   },
4065
4066   /* PREFIX_0F383C */
4067   {
4068     { Bad_Opcode },
4069     { Bad_Opcode },
4070     { "pmaxsb", { XM, EXx } },
4071   },
4072
4073   /* PREFIX_0F383D */
4074   {
4075     { Bad_Opcode },
4076     { Bad_Opcode },
4077     { "pmaxsd", { XM, EXx } },
4078   },
4079
4080   /* PREFIX_0F383E */
4081   {
4082     { Bad_Opcode },
4083     { Bad_Opcode },
4084     { "pmaxuw", { XM, EXx } },
4085   },
4086
4087   /* PREFIX_0F383F */
4088   {
4089     { Bad_Opcode },
4090     { Bad_Opcode },
4091     { "pmaxud", { XM, EXx } },
4092   },
4093
4094   /* PREFIX_0F3840 */
4095   {
4096     { Bad_Opcode },
4097     { Bad_Opcode },
4098     { "pmulld", { XM, EXx } },
4099   },
4100
4101   /* PREFIX_0F3841 */
4102   {
4103     { Bad_Opcode },
4104     { Bad_Opcode },
4105     { "phminposuw", { XM, EXx } },
4106   },
4107
4108   /* PREFIX_0F3880 */
4109   {
4110     { Bad_Opcode },
4111     { Bad_Opcode },
4112     { "invept", { Gm, Mo } },
4113   },
4114
4115   /* PREFIX_0F3881 */
4116   {
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { "invvpid", { Gm, Mo } },
4120   },
4121
4122   /* PREFIX_0F3882 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { "invpcid", { Gm, M } },
4127   },
4128
4129   /* PREFIX_0F38C8 */
4130   {
4131     { "sha1nexte", { XM, EXxmm } },
4132   },
4133
4134   /* PREFIX_0F38C9 */
4135   {
4136     { "sha1msg1", { XM, EXxmm } },
4137   },
4138
4139   /* PREFIX_0F38CA */
4140   {
4141     { "sha1msg2", { XM, EXxmm } },
4142   },
4143
4144   /* PREFIX_0F38CB */
4145   {
4146     { "sha256rnds2", { XM, EXxmm, XMM0 } },
4147   },
4148
4149   /* PREFIX_0F38CC */
4150   {
4151     { "sha256msg1", { XM, EXxmm } },
4152   },
4153
4154   /* PREFIX_0F38CD */
4155   {
4156     { "sha256msg2", { XM, EXxmm } },
4157   },
4158
4159   /* PREFIX_0F38DB */
4160   {
4161     { Bad_Opcode },
4162     { Bad_Opcode },
4163     { "aesimc", { XM, EXx } },
4164   },
4165
4166   /* PREFIX_0F38DC */
4167   {
4168     { Bad_Opcode },
4169     { Bad_Opcode },
4170     { "aesenc", { XM, EXx } },
4171   },
4172
4173   /* PREFIX_0F38DD */
4174   {
4175     { Bad_Opcode },
4176     { Bad_Opcode },
4177     { "aesenclast", { XM, EXx } },
4178   },
4179
4180   /* PREFIX_0F38DE */
4181   {
4182     { Bad_Opcode },
4183     { Bad_Opcode },
4184     { "aesdec", { XM, EXx } },
4185   },
4186
4187   /* PREFIX_0F38DF */
4188   {
4189     { Bad_Opcode },
4190     { Bad_Opcode },
4191     { "aesdeclast", { XM, EXx } },
4192   },
4193
4194   /* PREFIX_0F38F0 */
4195   {
4196     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4197     { Bad_Opcode },
4198     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4199     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
4200   },
4201
4202   /* PREFIX_0F38F1 */
4203   {
4204     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4205     { Bad_Opcode },
4206     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4207     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
4208   },
4209
4210   /* PREFIX_0F38F6 */
4211   {
4212     { Bad_Opcode },
4213     { "adoxS",  { Gdq, Edq} },
4214     { "adcxS",  { Gdq, Edq} },
4215     { Bad_Opcode },
4216   },
4217
4218   /* PREFIX_0F3A08 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { "roundps", { XM, EXx, Ib } },
4223   },
4224
4225   /* PREFIX_0F3A09 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "roundpd", { XM, EXx, Ib } },
4230   },
4231
4232   /* PREFIX_0F3A0A */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "roundss", { XM, EXd, Ib } },
4237   },
4238
4239   /* PREFIX_0F3A0B */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { "roundsd", { XM, EXq, Ib } },
4244   },
4245
4246   /* PREFIX_0F3A0C */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { "blendps", { XM, EXx, Ib } },
4251   },
4252
4253   /* PREFIX_0F3A0D */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { "blendpd", { XM, EXx, Ib } },
4258   },
4259
4260   /* PREFIX_0F3A0E */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { "pblendw", { XM, EXx, Ib } },
4265   },
4266
4267   /* PREFIX_0F3A14 */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { "pextrb", { Edqb, XM, Ib } },
4272   },
4273
4274   /* PREFIX_0F3A15 */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { "pextrw", { Edqw, XM, Ib } },
4279   },
4280
4281   /* PREFIX_0F3A16 */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { "pextrK", { Edq, XM, Ib } },
4286   },
4287
4288   /* PREFIX_0F3A17 */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { "extractps", { Edqd, XM, Ib } },
4293   },
4294
4295   /* PREFIX_0F3A20 */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { "pinsrb", { XM, Edqb, Ib } },
4300   },
4301
4302   /* PREFIX_0F3A21 */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { "insertps", { XM, EXd, Ib } },
4307   },
4308
4309   /* PREFIX_0F3A22 */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "pinsrK", { XM, Edq, Ib } },
4314   },
4315
4316   /* PREFIX_0F3A40 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "dpps",   { XM, EXx, Ib } },
4321   },
4322
4323   /* PREFIX_0F3A41 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "dppd",   { XM, EXx, Ib } },
4328   },
4329
4330   /* PREFIX_0F3A42 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "mpsadbw", { XM, EXx, Ib } },
4335   },
4336
4337   /* PREFIX_0F3A44 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "pclmulqdq", { XM, EXx, PCLMUL } },
4342   },
4343
4344   /* PREFIX_0F3A60 */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { "pcmpestrm", { XM, EXx, Ib } },
4349   },
4350
4351   /* PREFIX_0F3A61 */
4352   {
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { "pcmpestri", { XM, EXx, Ib } },
4356   },
4357
4358   /* PREFIX_0F3A62 */
4359   {
4360     { Bad_Opcode },
4361     { Bad_Opcode },
4362     { "pcmpistrm", { XM, EXx, Ib } },
4363   },
4364
4365   /* PREFIX_0F3A63 */
4366   {
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { "pcmpistri", { XM, EXx, Ib } },
4370   },
4371
4372   /* PREFIX_0F3ACC */
4373   {
4374     { "sha1rnds4", { XM, EXxmm, Ib } },
4375   },
4376
4377   /* PREFIX_0F3ADF */
4378   {
4379     { Bad_Opcode },
4380     { Bad_Opcode },
4381     { "aeskeygenassist", { XM, EXx, Ib } },
4382   },
4383
4384   /* PREFIX_VEX_0F10 */
4385   {
4386     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4387     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4388     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4389     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4390   },
4391
4392   /* PREFIX_VEX_0F11 */
4393   {
4394     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4395     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4396     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4397     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4398   },
4399
4400   /* PREFIX_VEX_0F12 */
4401   {
4402     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4403     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4404     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4405     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4406   },
4407
4408   /* PREFIX_VEX_0F16 */
4409   {
4410     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4411     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4412     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4413   },
4414
4415   /* PREFIX_VEX_0F2A */
4416   {
4417     { Bad_Opcode },
4418     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4419     { Bad_Opcode },
4420     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4421   },
4422
4423   /* PREFIX_VEX_0F2C */
4424   {
4425     { Bad_Opcode },
4426     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4427     { Bad_Opcode },
4428     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4429   },
4430
4431   /* PREFIX_VEX_0F2D */
4432   {
4433     { Bad_Opcode },
4434     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4435     { Bad_Opcode },
4436     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4437   },
4438
4439   /* PREFIX_VEX_0F2E */
4440   {
4441     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4442     { Bad_Opcode },
4443     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4444   },
4445
4446   /* PREFIX_VEX_0F2F */
4447   {
4448     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4449     { Bad_Opcode },
4450     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4451   },
4452
4453   /* PREFIX_VEX_0F41 */
4454   {
4455     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4456   },
4457
4458   /* PREFIX_VEX_0F42 */
4459   {
4460     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4461   },
4462
4463   /* PREFIX_VEX_0F44 */
4464   {
4465     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4466   },
4467
4468   /* PREFIX_VEX_0F45 */
4469   {
4470     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4471   },
4472
4473   /* PREFIX_VEX_0F46 */
4474   {
4475     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4476   },
4477
4478   /* PREFIX_VEX_0F47 */
4479   {
4480     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4481   },
4482
4483   /* PREFIX_VEX_0F4B */
4484   {
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4488   },
4489
4490   /* PREFIX_VEX_0F51 */
4491   {
4492     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4493     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4494     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4495     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4496   },
4497
4498   /* PREFIX_VEX_0F52 */
4499   {
4500     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4501     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4502   },
4503
4504   /* PREFIX_VEX_0F53 */
4505   {
4506     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4507     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4508   },
4509
4510   /* PREFIX_VEX_0F58 */
4511   {
4512     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4513     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4514     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4515     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4516   },
4517
4518   /* PREFIX_VEX_0F59 */
4519   {
4520     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4521     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4522     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4523     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4524   },
4525
4526   /* PREFIX_VEX_0F5A */
4527   {
4528     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4529     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4530     { "vcvtpd2ps%XY", { XMM, EXx } },
4531     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4532   },
4533
4534   /* PREFIX_VEX_0F5B */
4535   {
4536     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4537     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4538     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4539   },
4540
4541   /* PREFIX_VEX_0F5C */
4542   {
4543     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4544     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4545     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4546     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4547   },
4548
4549   /* PREFIX_VEX_0F5D */
4550   {
4551     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4552     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4553     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4554     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4555   },
4556
4557   /* PREFIX_VEX_0F5E */
4558   {
4559     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4560     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4561     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4562     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4563   },
4564
4565   /* PREFIX_VEX_0F5F */
4566   {
4567     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4568     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4569     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4570     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4571   },
4572
4573   /* PREFIX_VEX_0F60 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4578   },
4579
4580   /* PREFIX_VEX_0F61 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4585   },
4586
4587   /* PREFIX_VEX_0F62 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4592   },
4593
4594   /* PREFIX_VEX_0F63 */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4599   },
4600
4601   /* PREFIX_VEX_0F64 */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4606   },
4607
4608   /* PREFIX_VEX_0F65 */
4609   {
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4613   },
4614
4615   /* PREFIX_VEX_0F66 */
4616   {
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4620   },
4621
4622   /* PREFIX_VEX_0F67 */
4623   {
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4627   },
4628
4629   /* PREFIX_VEX_0F68 */
4630   {
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4634   },
4635
4636   /* PREFIX_VEX_0F69 */
4637   {
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4641   },
4642
4643   /* PREFIX_VEX_0F6A */
4644   {
4645     { Bad_Opcode },
4646     { Bad_Opcode },
4647     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4648   },
4649
4650   /* PREFIX_VEX_0F6B */
4651   {
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4655   },
4656
4657   /* PREFIX_VEX_0F6C */
4658   {
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4662   },
4663
4664   /* PREFIX_VEX_0F6D */
4665   {
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4669   },
4670
4671   /* PREFIX_VEX_0F6E */
4672   {
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4676   },
4677
4678   /* PREFIX_VEX_0F6F */
4679   {
4680     { Bad_Opcode },
4681     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4682     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4683   },
4684
4685   /* PREFIX_VEX_0F70 */
4686   {
4687     { Bad_Opcode },
4688     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4689     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4690     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4691   },
4692
4693   /* PREFIX_VEX_0F71_REG_2 */
4694   {
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4698   },
4699
4700   /* PREFIX_VEX_0F71_REG_4 */
4701   {
4702     { Bad_Opcode },
4703     { Bad_Opcode },
4704     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4705   },
4706
4707   /* PREFIX_VEX_0F71_REG_6 */
4708   {
4709     { Bad_Opcode },
4710     { Bad_Opcode },
4711     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4712   },
4713
4714   /* PREFIX_VEX_0F72_REG_2 */
4715   {
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4719   },
4720
4721   /* PREFIX_VEX_0F72_REG_4 */
4722   {
4723     { Bad_Opcode },
4724     { Bad_Opcode },
4725     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4726   },
4727
4728   /* PREFIX_VEX_0F72_REG_6 */
4729   {
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4733   },
4734
4735   /* PREFIX_VEX_0F73_REG_2 */
4736   {
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4740   },
4741
4742   /* PREFIX_VEX_0F73_REG_3 */
4743   {
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4747   },
4748
4749   /* PREFIX_VEX_0F73_REG_6 */
4750   {
4751     { Bad_Opcode },
4752     { Bad_Opcode },
4753     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4754   },
4755
4756   /* PREFIX_VEX_0F73_REG_7 */
4757   {
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4761   },
4762
4763   /* PREFIX_VEX_0F74 */
4764   {
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4768   },
4769
4770   /* PREFIX_VEX_0F75 */
4771   {
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4775   },
4776
4777   /* PREFIX_VEX_0F76 */
4778   {
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4782   },
4783
4784   /* PREFIX_VEX_0F77 */
4785   {
4786     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4787   },
4788
4789   /* PREFIX_VEX_0F7C */
4790   {
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4794     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4795   },
4796
4797   /* PREFIX_VEX_0F7D */
4798   {
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4802     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4803   },
4804
4805   /* PREFIX_VEX_0F7E */
4806   {
4807     { Bad_Opcode },
4808     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4809     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4810   },
4811
4812   /* PREFIX_VEX_0F7F */
4813   {
4814     { Bad_Opcode },
4815     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4816     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4817   },
4818
4819   /* PREFIX_VEX_0F90 */
4820   {
4821     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4822   },
4823
4824   /* PREFIX_VEX_0F91 */
4825   {
4826     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4827   },
4828
4829   /* PREFIX_VEX_0F92 */
4830   {
4831     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4832   },
4833
4834   /* PREFIX_VEX_0F93 */
4835   {
4836     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4837   },
4838
4839   /* PREFIX_VEX_0F98 */
4840   {
4841     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4842   },
4843
4844   /* PREFIX_VEX_0FC2 */
4845   {
4846     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4847     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4848     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4849     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4850   },
4851
4852   /* PREFIX_VEX_0FC4 */
4853   {
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4857   },
4858
4859   /* PREFIX_VEX_0FC5 */
4860   {
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4864   },
4865
4866   /* PREFIX_VEX_0FD0 */
4867   {
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4871     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4872   },
4873
4874   /* PREFIX_VEX_0FD1 */
4875   {
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4879   },
4880
4881   /* PREFIX_VEX_0FD2 */
4882   {
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4886   },
4887
4888   /* PREFIX_VEX_0FD3 */
4889   {
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4893   },
4894
4895   /* PREFIX_VEX_0FD4 */
4896   {
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4900   },
4901
4902   /* PREFIX_VEX_0FD5 */
4903   {
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4907   },
4908
4909   /* PREFIX_VEX_0FD6 */
4910   {
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4914   },
4915
4916   /* PREFIX_VEX_0FD7 */
4917   {
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4921   },
4922
4923   /* PREFIX_VEX_0FD8 */
4924   {
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4928   },
4929
4930   /* PREFIX_VEX_0FD9 */
4931   {
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4935   },
4936
4937   /* PREFIX_VEX_0FDA */
4938   {
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4942   },
4943
4944   /* PREFIX_VEX_0FDB */
4945   {
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4949   },
4950
4951   /* PREFIX_VEX_0FDC */
4952   {
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4956   },
4957
4958   /* PREFIX_VEX_0FDD */
4959   {
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4963   },
4964
4965   /* PREFIX_VEX_0FDE */
4966   {
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4970   },
4971
4972   /* PREFIX_VEX_0FDF */
4973   {
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4977   },
4978
4979   /* PREFIX_VEX_0FE0 */
4980   {
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4984   },
4985
4986   /* PREFIX_VEX_0FE1 */
4987   {
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4991   },
4992
4993   /* PREFIX_VEX_0FE2 */
4994   {
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4998   },
4999
5000   /* PREFIX_VEX_0FE3 */
5001   {
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5005   },
5006
5007   /* PREFIX_VEX_0FE4 */
5008   {
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5012   },
5013
5014   /* PREFIX_VEX_0FE5 */
5015   {
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5019   },
5020
5021   /* PREFIX_VEX_0FE6 */
5022   {
5023     { Bad_Opcode },
5024     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5025     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5026     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5027   },
5028
5029   /* PREFIX_VEX_0FE7 */
5030   {
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5034   },
5035
5036   /* PREFIX_VEX_0FE8 */
5037   {
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5041   },
5042
5043   /* PREFIX_VEX_0FE9 */
5044   {
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5048   },
5049
5050   /* PREFIX_VEX_0FEA */
5051   {
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5055   },
5056
5057   /* PREFIX_VEX_0FEB */
5058   {
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5062   },
5063
5064   /* PREFIX_VEX_0FEC */
5065   {
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5069   },
5070
5071   /* PREFIX_VEX_0FED */
5072   {
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5076   },
5077
5078   /* PREFIX_VEX_0FEE */
5079   {
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5083   },
5084
5085   /* PREFIX_VEX_0FEF */
5086   {
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5090   },
5091
5092   /* PREFIX_VEX_0FF0 */
5093   {
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5098   },
5099
5100   /* PREFIX_VEX_0FF1 */
5101   {
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5105   },
5106
5107   /* PREFIX_VEX_0FF2 */
5108   {
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5112   },
5113
5114   /* PREFIX_VEX_0FF3 */
5115   {
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5119   },
5120
5121   /* PREFIX_VEX_0FF4 */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5126   },
5127
5128   /* PREFIX_VEX_0FF5 */
5129   {
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5133   },
5134
5135   /* PREFIX_VEX_0FF6 */
5136   {
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5140   },
5141
5142   /* PREFIX_VEX_0FF7 */
5143   {
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5147   },
5148
5149   /* PREFIX_VEX_0FF8 */
5150   {
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5154   },
5155
5156   /* PREFIX_VEX_0FF9 */
5157   {
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5161   },
5162
5163   /* PREFIX_VEX_0FFA */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5168   },
5169
5170   /* PREFIX_VEX_0FFB */
5171   {
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5175   },
5176
5177   /* PREFIX_VEX_0FFC */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5182   },
5183
5184   /* PREFIX_VEX_0FFD */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5189   },
5190
5191   /* PREFIX_VEX_0FFE */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5196   },
5197
5198   /* PREFIX_VEX_0F3800 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5203   },
5204
5205   /* PREFIX_VEX_0F3801 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5210   },
5211
5212   /* PREFIX_VEX_0F3802 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5217   },
5218
5219   /* PREFIX_VEX_0F3803 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5224   },
5225
5226   /* PREFIX_VEX_0F3804 */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5231   },
5232
5233   /* PREFIX_VEX_0F3805 */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5238   },
5239
5240   /* PREFIX_VEX_0F3806 */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5245   },
5246
5247   /* PREFIX_VEX_0F3807 */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5252   },
5253
5254   /* PREFIX_VEX_0F3808 */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5259   },
5260
5261   /* PREFIX_VEX_0F3809 */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5266   },
5267
5268   /* PREFIX_VEX_0F380A */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5273   },
5274
5275   /* PREFIX_VEX_0F380B */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5280   },
5281
5282   /* PREFIX_VEX_0F380C */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5287   },
5288
5289   /* PREFIX_VEX_0F380D */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5294   },
5295
5296   /* PREFIX_VEX_0F380E */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5301   },
5302
5303   /* PREFIX_VEX_0F380F */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5308   },
5309
5310   /* PREFIX_VEX_0F3813 */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { "vcvtph2ps", { XM, EXxmmq } },
5315   },
5316
5317   /* PREFIX_VEX_0F3816 */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5322   },
5323
5324   /* PREFIX_VEX_0F3817 */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5329   },
5330
5331   /* PREFIX_VEX_0F3818 */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5336   },
5337
5338   /* PREFIX_VEX_0F3819 */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5343   },
5344
5345   /* PREFIX_VEX_0F381A */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5350   },
5351
5352   /* PREFIX_VEX_0F381C */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5357   },
5358
5359   /* PREFIX_VEX_0F381D */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5364   },
5365
5366   /* PREFIX_VEX_0F381E */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5371   },
5372
5373   /* PREFIX_VEX_0F3820 */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5378   },
5379
5380   /* PREFIX_VEX_0F3821 */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5385   },
5386
5387   /* PREFIX_VEX_0F3822 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5392   },
5393
5394   /* PREFIX_VEX_0F3823 */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5399   },
5400
5401   /* PREFIX_VEX_0F3824 */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5406   },
5407
5408   /* PREFIX_VEX_0F3825 */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5413   },
5414
5415   /* PREFIX_VEX_0F3828 */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5420   },
5421
5422   /* PREFIX_VEX_0F3829 */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5427   },
5428
5429   /* PREFIX_VEX_0F382A */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5434   },
5435
5436   /* PREFIX_VEX_0F382B */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5441   },
5442
5443   /* PREFIX_VEX_0F382C */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5448   },
5449
5450   /* PREFIX_VEX_0F382D */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5455   },
5456
5457   /* PREFIX_VEX_0F382E */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5462   },
5463
5464   /* PREFIX_VEX_0F382F */
5465   {
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5469   },
5470
5471   /* PREFIX_VEX_0F3830 */
5472   {
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5476   },
5477
5478   /* PREFIX_VEX_0F3831 */
5479   {
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5483   },
5484
5485   /* PREFIX_VEX_0F3832 */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5490   },
5491
5492   /* PREFIX_VEX_0F3833 */
5493   {
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5497   },
5498
5499   /* PREFIX_VEX_0F3834 */
5500   {
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5504   },
5505
5506   /* PREFIX_VEX_0F3835 */
5507   {
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5511   },
5512
5513   /* PREFIX_VEX_0F3836 */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5518   },
5519
5520   /* PREFIX_VEX_0F3837 */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5525   },
5526
5527   /* PREFIX_VEX_0F3838 */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5532   },
5533
5534   /* PREFIX_VEX_0F3839 */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5539   },
5540
5541   /* PREFIX_VEX_0F383A */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5546   },
5547
5548   /* PREFIX_VEX_0F383B */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5553   },
5554
5555   /* PREFIX_VEX_0F383C */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5560   },
5561
5562   /* PREFIX_VEX_0F383D */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5567   },
5568
5569   /* PREFIX_VEX_0F383E */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5574   },
5575
5576   /* PREFIX_VEX_0F383F */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5581   },
5582
5583   /* PREFIX_VEX_0F3840 */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5588   },
5589
5590   /* PREFIX_VEX_0F3841 */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5595   },
5596
5597   /* PREFIX_VEX_0F3845 */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { "vpsrlv%LW", { XM, Vex, EXx } },
5602   },
5603
5604   /* PREFIX_VEX_0F3846 */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5609   },
5610
5611   /* PREFIX_VEX_0F3847 */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { "vpsllv%LW", { XM, Vex, EXx } },
5616   },
5617
5618   /* PREFIX_VEX_0F3858 */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5623   },
5624
5625   /* PREFIX_VEX_0F3859 */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5630   },
5631
5632   /* PREFIX_VEX_0F385A */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5637   },
5638
5639   /* PREFIX_VEX_0F3878 */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5644   },
5645
5646   /* PREFIX_VEX_0F3879 */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5651   },
5652
5653   /* PREFIX_VEX_0F388C */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5658   },
5659
5660   /* PREFIX_VEX_0F388E */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5665   },
5666
5667   /* PREFIX_VEX_0F3890 */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5672   },
5673
5674   /* PREFIX_VEX_0F3891 */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5679   },
5680
5681   /* PREFIX_VEX_0F3892 */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5686   },
5687
5688   /* PREFIX_VEX_0F3893 */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5693   },
5694
5695   /* PREFIX_VEX_0F3896 */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5700   },
5701
5702   /* PREFIX_VEX_0F3897 */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5707   },
5708
5709   /* PREFIX_VEX_0F3898 */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { "vfmadd132p%XW", { XM, Vex, EXx } },
5714   },
5715
5716   /* PREFIX_VEX_0F3899 */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5721   },
5722
5723   /* PREFIX_VEX_0F389A */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { "vfmsub132p%XW", { XM, Vex, EXx } },
5728   },
5729
5730   /* PREFIX_VEX_0F389B */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5735   },
5736
5737   /* PREFIX_VEX_0F389C */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5742   },
5743
5744   /* PREFIX_VEX_0F389D */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5749   },
5750
5751   /* PREFIX_VEX_0F389E */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5756   },
5757
5758   /* PREFIX_VEX_0F389F */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5763   },
5764
5765   /* PREFIX_VEX_0F38A6 */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5770     { Bad_Opcode },
5771   },
5772
5773   /* PREFIX_VEX_0F38A7 */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5778   },
5779
5780   /* PREFIX_VEX_0F38A8 */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { "vfmadd213p%XW", { XM, Vex, EXx } },
5785   },
5786
5787   /* PREFIX_VEX_0F38A9 */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5792   },
5793
5794   /* PREFIX_VEX_0F38AA */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { "vfmsub213p%XW", { XM, Vex, EXx } },
5799   },
5800
5801   /* PREFIX_VEX_0F38AB */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5806   },
5807
5808   /* PREFIX_VEX_0F38AC */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { "vfnmadd213p%XW", { XM, Vex, EXx } },
5813   },
5814
5815   /* PREFIX_VEX_0F38AD */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5820   },
5821
5822   /* PREFIX_VEX_0F38AE */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { "vfnmsub213p%XW", { XM, Vex, EXx } },
5827   },
5828
5829   /* PREFIX_VEX_0F38AF */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5834   },
5835
5836   /* PREFIX_VEX_0F38B6 */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5841   },
5842
5843   /* PREFIX_VEX_0F38B7 */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5848   },
5849
5850   /* PREFIX_VEX_0F38B8 */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { "vfmadd231p%XW", { XM, Vex, EXx } },
5855   },
5856
5857   /* PREFIX_VEX_0F38B9 */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5862   },
5863
5864   /* PREFIX_VEX_0F38BA */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { "vfmsub231p%XW", { XM, Vex, EXx } },
5869   },
5870
5871   /* PREFIX_VEX_0F38BB */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5876   },
5877
5878   /* PREFIX_VEX_0F38BC */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { "vfnmadd231p%XW", { XM, Vex, EXx } },
5883   },
5884
5885   /* PREFIX_VEX_0F38BD */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5890   },
5891
5892   /* PREFIX_VEX_0F38BE */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { "vfnmsub231p%XW", { XM, Vex, EXx } },
5897   },
5898
5899   /* PREFIX_VEX_0F38BF */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5904   },
5905
5906   /* PREFIX_VEX_0F38DB */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5911   },
5912
5913   /* PREFIX_VEX_0F38DC */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F38DD */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5925   },
5926
5927   /* PREFIX_VEX_0F38DE */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5932   },
5933
5934   /* PREFIX_VEX_0F38DF */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5939   },
5940
5941   /* PREFIX_VEX_0F38F2 */
5942   {
5943     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5944   },
5945
5946   /* PREFIX_VEX_0F38F3_REG_1 */
5947   {
5948     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5949   },
5950
5951   /* PREFIX_VEX_0F38F3_REG_2 */
5952   {
5953     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5954   },
5955
5956   /* PREFIX_VEX_0F38F3_REG_3 */
5957   {
5958     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5959   },
5960
5961   /* PREFIX_VEX_0F38F5 */
5962   {
5963     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5964     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5965     { Bad_Opcode },
5966     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5967   },
5968
5969   /* PREFIX_VEX_0F38F6 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5975   },
5976
5977   /* PREFIX_VEX_0F38F7 */
5978   {
5979     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5980     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5981     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5982     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5983   },
5984
5985   /* PREFIX_VEX_0F3A00 */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5990   },
5991
5992   /* PREFIX_VEX_0F3A01 */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5997   },
5998
5999   /* PREFIX_VEX_0F3A02 */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6004   },
6005
6006   /* PREFIX_VEX_0F3A04 */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6011   },
6012
6013   /* PREFIX_VEX_0F3A05 */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6018   },
6019
6020   /* PREFIX_VEX_0F3A06 */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6025   },
6026
6027   /* PREFIX_VEX_0F3A08 */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6032   },
6033
6034   /* PREFIX_VEX_0F3A09 */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6039   },
6040
6041   /* PREFIX_VEX_0F3A0A */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6046   },
6047
6048   /* PREFIX_VEX_0F3A0B */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6053   },
6054
6055   /* PREFIX_VEX_0F3A0C */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6060   },
6061
6062   /* PREFIX_VEX_0F3A0D */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6067   },
6068
6069   /* PREFIX_VEX_0F3A0E */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6074   },
6075
6076   /* PREFIX_VEX_0F3A0F */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6081   },
6082
6083   /* PREFIX_VEX_0F3A14 */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6088   },
6089
6090   /* PREFIX_VEX_0F3A15 */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6095   },
6096
6097   /* PREFIX_VEX_0F3A16 */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6102   },
6103
6104   /* PREFIX_VEX_0F3A17 */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6109   },
6110
6111   /* PREFIX_VEX_0F3A18 */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6116   },
6117
6118   /* PREFIX_VEX_0F3A19 */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6123   },
6124
6125   /* PREFIX_VEX_0F3A1D */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { "vcvtps2ph", { EXxmmq, XM, Ib } },
6130   },
6131
6132   /* PREFIX_VEX_0F3A20 */
6133   {
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6137   },
6138
6139   /* PREFIX_VEX_0F3A21 */
6140   {
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6144   },
6145
6146   /* PREFIX_VEX_0F3A22 */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6151   },
6152
6153   /* PREFIX_VEX_0F3A30 */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6158   },
6159
6160   /* PREFIX_VEX_0F3A32 */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6165   },
6166
6167   /* PREFIX_VEX_0F3A38 */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6172   },
6173
6174   /* PREFIX_VEX_0F3A39 */
6175   {
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6179   },
6180
6181   /* PREFIX_VEX_0F3A40 */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6186   },
6187
6188   /* PREFIX_VEX_0F3A41 */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6193   },
6194
6195   /* PREFIX_VEX_0F3A42 */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6200   },
6201
6202   /* PREFIX_VEX_0F3A44 */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6207   },
6208
6209   /* PREFIX_VEX_0F3A46 */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6214   },
6215
6216   /* PREFIX_VEX_0F3A48 */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6221   },
6222
6223   /* PREFIX_VEX_0F3A49 */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6228   },
6229
6230   /* PREFIX_VEX_0F3A4A */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6235   },
6236
6237   /* PREFIX_VEX_0F3A4B */
6238   {
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6242   },
6243
6244   /* PREFIX_VEX_0F3A4C */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6249   },
6250
6251   /* PREFIX_VEX_0F3A5C */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6256   },
6257
6258   /* PREFIX_VEX_0F3A5D */
6259   {
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6263   },
6264
6265   /* PREFIX_VEX_0F3A5E */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6270   },
6271
6272   /* PREFIX_VEX_0F3A5F */
6273   {
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6277   },
6278
6279   /* PREFIX_VEX_0F3A60 */
6280   {
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6284     { Bad_Opcode },
6285   },
6286
6287   /* PREFIX_VEX_0F3A61 */
6288   {
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6292   },
6293
6294   /* PREFIX_VEX_0F3A62 */
6295   {
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6299   },
6300
6301   /* PREFIX_VEX_0F3A63 */
6302   {
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6306   },
6307
6308   /* PREFIX_VEX_0F3A68 */
6309   {
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6313   },
6314
6315   /* PREFIX_VEX_0F3A69 */
6316   {
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6320   },
6321
6322   /* PREFIX_VEX_0F3A6A */
6323   {
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6327   },
6328
6329   /* PREFIX_VEX_0F3A6B */
6330   {
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6334   },
6335
6336   /* PREFIX_VEX_0F3A6C */
6337   {
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6341   },
6342
6343   /* PREFIX_VEX_0F3A6D */
6344   {
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6348   },
6349
6350   /* PREFIX_VEX_0F3A6E */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6355   },
6356
6357   /* PREFIX_VEX_0F3A6F */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6362   },
6363
6364   /* PREFIX_VEX_0F3A78 */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6369   },
6370
6371   /* PREFIX_VEX_0F3A79 */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6376   },
6377
6378   /* PREFIX_VEX_0F3A7A */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6383   },
6384
6385   /* PREFIX_VEX_0F3A7B */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6390   },
6391
6392   /* PREFIX_VEX_0F3A7C */
6393   {
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6397     { Bad_Opcode },
6398   },
6399
6400   /* PREFIX_VEX_0F3A7D */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6405   },
6406
6407   /* PREFIX_VEX_0F3A7E */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6412   },
6413
6414   /* PREFIX_VEX_0F3A7F */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6419   },
6420
6421   /* PREFIX_VEX_0F3ADF */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6426   },
6427
6428   /* PREFIX_VEX_0F3AF0 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6434   },
6435
6436 #define NEED_PREFIX_TABLE
6437 #include "i386-dis-evex.h"
6438 #undef NEED_PREFIX_TABLE
6439 };
6440
6441 static const struct dis386 x86_64_table[][2] = {
6442   /* X86_64_06 */
6443   {
6444     { "pushP", { es } },
6445   },
6446
6447   /* X86_64_07 */
6448   {
6449     { "popP", { es } },
6450   },
6451
6452   /* X86_64_0D */
6453   {
6454     { "pushP", { cs } },
6455   },
6456
6457   /* X86_64_16 */
6458   {
6459     { "pushP", { ss } },
6460   },
6461
6462   /* X86_64_17 */
6463   {
6464     { "popP", { ss } },
6465   },
6466
6467   /* X86_64_1E */
6468   {
6469     { "pushP", { ds } },
6470   },
6471
6472   /* X86_64_1F */
6473   {
6474     { "popP", { ds } },
6475   },
6476
6477   /* X86_64_27 */
6478   {
6479     { "daa", { XX } },
6480   },
6481
6482   /* X86_64_2F */
6483   {
6484     { "das", { XX } },
6485   },
6486
6487   /* X86_64_37 */
6488   {
6489     { "aaa", { XX } },
6490   },
6491
6492   /* X86_64_3F */
6493   {
6494     { "aas", { XX } },
6495   },
6496
6497   /* X86_64_60 */
6498   {
6499     { "pushaP", { XX } },
6500   },
6501
6502   /* X86_64_61 */
6503   {
6504     { "popaP", { XX } },
6505   },
6506
6507   /* X86_64_62 */
6508   {
6509     { MOD_TABLE (MOD_62_32BIT) },
6510     { EVEX_TABLE (EVEX_0F) },
6511   },
6512
6513   /* X86_64_63 */
6514   {
6515     { "arpl", { Ew, Gw } },
6516     { "movs{lq|xd}", { Gv, Ed } },
6517   },
6518
6519   /* X86_64_6D */
6520   {
6521     { "ins{R|}", { Yzr, indirDX } },
6522     { "ins{G|}", { Yzr, indirDX } },
6523   },
6524
6525   /* X86_64_6F */
6526   {
6527     { "outs{R|}", { indirDXr, Xz } },
6528     { "outs{G|}", { indirDXr, Xz } },
6529   },
6530
6531   /* X86_64_9A */
6532   {
6533     { "Jcall{T|}", { Ap } },
6534   },
6535
6536   /* X86_64_C4 */
6537   {
6538     { MOD_TABLE (MOD_C4_32BIT) },
6539     { VEX_C4_TABLE (VEX_0F) },
6540   },
6541
6542   /* X86_64_C5 */
6543   {
6544     { MOD_TABLE (MOD_C5_32BIT) },
6545     { VEX_C5_TABLE (VEX_0F) },
6546   },
6547
6548   /* X86_64_CE */
6549   {
6550     { "into", { XX } },
6551   },
6552
6553   /* X86_64_D4 */
6554   {
6555     { "aam", { Ib } },
6556   },
6557
6558   /* X86_64_D5 */
6559   {
6560     { "aad", { Ib } },
6561   },
6562
6563   /* X86_64_EA */
6564   {
6565     { "Jjmp{T|}", { Ap } },
6566   },
6567
6568   /* X86_64_0F01_REG_0 */
6569   {
6570     { "sgdt{Q|IQ}", { M } },
6571     { "sgdt", { M } },
6572   },
6573
6574   /* X86_64_0F01_REG_1 */
6575   {
6576     { "sidt{Q|IQ}", { M } },
6577     { "sidt", { M } },
6578   },
6579
6580   /* X86_64_0F01_REG_2 */
6581   {
6582     { "lgdt{Q|Q}", { M } },
6583     { "lgdt", { M } },
6584   },
6585
6586   /* X86_64_0F01_REG_3 */
6587   {
6588     { "lidt{Q|Q}", { M } },
6589     { "lidt", { M } },
6590   },
6591 };
6592
6593 static const struct dis386 three_byte_table[][256] = {
6594
6595   /* THREE_BYTE_0F38 */
6596   {
6597     /* 00 */
6598     { "pshufb",         { MX, EM } },
6599     { "phaddw",         { MX, EM } },
6600     { "phaddd",         { MX, EM } },
6601     { "phaddsw",        { MX, EM } },
6602     { "pmaddubsw",      { MX, EM } },
6603     { "phsubw",         { MX, EM } },
6604     { "phsubd",         { MX, EM } },
6605     { "phsubsw",        { MX, EM } },
6606     /* 08 */
6607     { "psignb",         { MX, EM } },
6608     { "psignw",         { MX, EM } },
6609     { "psignd",         { MX, EM } },
6610     { "pmulhrsw",       { MX, EM } },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     /* 10 */
6616     { PREFIX_TABLE (PREFIX_0F3810) },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { PREFIX_TABLE (PREFIX_0F3814) },
6621     { PREFIX_TABLE (PREFIX_0F3815) },
6622     { Bad_Opcode },
6623     { PREFIX_TABLE (PREFIX_0F3817) },
6624     /* 18 */
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { "pabsb",          { MX, EM } },
6630     { "pabsw",          { MX, EM } },
6631     { "pabsd",          { MX, EM } },
6632     { Bad_Opcode },
6633     /* 20 */
6634     { PREFIX_TABLE (PREFIX_0F3820) },
6635     { PREFIX_TABLE (PREFIX_0F3821) },
6636     { PREFIX_TABLE (PREFIX_0F3822) },
6637     { PREFIX_TABLE (PREFIX_0F3823) },
6638     { PREFIX_TABLE (PREFIX_0F3824) },
6639     { PREFIX_TABLE (PREFIX_0F3825) },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     /* 28 */
6643     { PREFIX_TABLE (PREFIX_0F3828) },
6644     { PREFIX_TABLE (PREFIX_0F3829) },
6645     { PREFIX_TABLE (PREFIX_0F382A) },
6646     { PREFIX_TABLE (PREFIX_0F382B) },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     /* 30 */
6652     { PREFIX_TABLE (PREFIX_0F3830) },
6653     { PREFIX_TABLE (PREFIX_0F3831) },
6654     { PREFIX_TABLE (PREFIX_0F3832) },
6655     { PREFIX_TABLE (PREFIX_0F3833) },
6656     { PREFIX_TABLE (PREFIX_0F3834) },
6657     { PREFIX_TABLE (PREFIX_0F3835) },
6658     { Bad_Opcode },
6659     { PREFIX_TABLE (PREFIX_0F3837) },
6660     /* 38 */
6661     { PREFIX_TABLE (PREFIX_0F3838) },
6662     { PREFIX_TABLE (PREFIX_0F3839) },
6663     { PREFIX_TABLE (PREFIX_0F383A) },
6664     { PREFIX_TABLE (PREFIX_0F383B) },
6665     { PREFIX_TABLE (PREFIX_0F383C) },
6666     { PREFIX_TABLE (PREFIX_0F383D) },
6667     { PREFIX_TABLE (PREFIX_0F383E) },
6668     { PREFIX_TABLE (PREFIX_0F383F) },
6669     /* 40 */
6670     { PREFIX_TABLE (PREFIX_0F3840) },
6671     { PREFIX_TABLE (PREFIX_0F3841) },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     /* 48 */
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     /* 50 */
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     /* 58 */
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     /* 60 */
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     /* 68 */
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     /* 70 */
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     /* 78 */
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     /* 80 */
6742     { PREFIX_TABLE (PREFIX_0F3880) },
6743     { PREFIX_TABLE (PREFIX_0F3881) },
6744     { PREFIX_TABLE (PREFIX_0F3882) },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     /* 88 */
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     /* 90 */
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     /* 98 */
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     /* a0 */
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     /* a8 */
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     /* b0 */
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     /* b8 */
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     /* c0 */
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     /* c8 */
6823     { PREFIX_TABLE (PREFIX_0F38C8) },
6824     { PREFIX_TABLE (PREFIX_0F38C9) },
6825     { PREFIX_TABLE (PREFIX_0F38CA) },
6826     { PREFIX_TABLE (PREFIX_0F38CB) },
6827     { PREFIX_TABLE (PREFIX_0F38CC) },
6828     { PREFIX_TABLE (PREFIX_0F38CD) },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     /* d0 */
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     /* d8 */
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { PREFIX_TABLE (PREFIX_0F38DB) },
6845     { PREFIX_TABLE (PREFIX_0F38DC) },
6846     { PREFIX_TABLE (PREFIX_0F38DD) },
6847     { PREFIX_TABLE (PREFIX_0F38DE) },
6848     { PREFIX_TABLE (PREFIX_0F38DF) },
6849     /* e0 */
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     /* e8 */
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     /* f0 */
6868     { PREFIX_TABLE (PREFIX_0F38F0) },
6869     { PREFIX_TABLE (PREFIX_0F38F1) },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { PREFIX_TABLE (PREFIX_0F38F6) },
6875     { Bad_Opcode },
6876     /* f8 */
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885   },
6886   /* THREE_BYTE_0F3A */
6887   {
6888     /* 00 */
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     /* 08 */
6898     { PREFIX_TABLE (PREFIX_0F3A08) },
6899     { PREFIX_TABLE (PREFIX_0F3A09) },
6900     { PREFIX_TABLE (PREFIX_0F3A0A) },
6901     { PREFIX_TABLE (PREFIX_0F3A0B) },
6902     { PREFIX_TABLE (PREFIX_0F3A0C) },
6903     { PREFIX_TABLE (PREFIX_0F3A0D) },
6904     { PREFIX_TABLE (PREFIX_0F3A0E) },
6905     { "palignr",        { MX, EM, Ib } },
6906     /* 10 */
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { PREFIX_TABLE (PREFIX_0F3A14) },
6912     { PREFIX_TABLE (PREFIX_0F3A15) },
6913     { PREFIX_TABLE (PREFIX_0F3A16) },
6914     { PREFIX_TABLE (PREFIX_0F3A17) },
6915     /* 18 */
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     /* 20 */
6925     { PREFIX_TABLE (PREFIX_0F3A20) },
6926     { PREFIX_TABLE (PREFIX_0F3A21) },
6927     { PREFIX_TABLE (PREFIX_0F3A22) },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     /* 28 */
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     /* 30 */
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     /* 38 */
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     /* 40 */
6961     { PREFIX_TABLE (PREFIX_0F3A40) },
6962     { PREFIX_TABLE (PREFIX_0F3A41) },
6963     { PREFIX_TABLE (PREFIX_0F3A42) },
6964     { Bad_Opcode },
6965     { PREFIX_TABLE (PREFIX_0F3A44) },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     /* 48 */
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     /* 50 */
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     /* 58 */
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     /* 60 */
6997     { PREFIX_TABLE (PREFIX_0F3A60) },
6998     { PREFIX_TABLE (PREFIX_0F3A61) },
6999     { PREFIX_TABLE (PREFIX_0F3A62) },
7000     { PREFIX_TABLE (PREFIX_0F3A63) },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     /* 68 */
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     /* 70 */
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     /* 78 */
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     /* 80 */
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     /* 88 */
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     /* 90 */
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     /* 98 */
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     /* a0 */
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     /* a8 */
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     /* b0 */
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     /* b8 */
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     /* c0 */
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     /* c8 */
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { PREFIX_TABLE (PREFIX_0F3ACC) },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     /* d0 */
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     /* d8 */
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { PREFIX_TABLE (PREFIX_0F3ADF) },
7140     /* e0 */
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     /* e8 */
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     /* f0 */
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     /* f8 */
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176   },
7177
7178   /* THREE_BYTE_0F7A */
7179   {
7180     /* 00 */
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     /* 08 */
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* 10 */
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     /* 18 */
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     /* 20 */
7217     { "ptest",          { XX } },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     /* 28 */
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     /* 30 */
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     /* 38 */
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     /* 40 */
7253     { Bad_Opcode },
7254     { "phaddbw",        { XM, EXq } },
7255     { "phaddbd",        { XM, EXq } },
7256     { "phaddbq",        { XM, EXq } },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { "phaddwd",        { XM, EXq } },
7260     { "phaddwq",        { XM, EXq } },
7261     /* 48 */
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { "phadddq",        { XM, EXq } },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     /* 50 */
7271     { Bad_Opcode },
7272     { "phaddubw",       { XM, EXq } },
7273     { "phaddubd",       { XM, EXq } },
7274     { "phaddubq",       { XM, EXq } },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { "phadduwd",       { XM, EXq } },
7278     { "phadduwq",       { XM, EXq } },
7279     /* 58 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { "phaddudq",       { XM, EXq } },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     /* 60 */
7289     { Bad_Opcode },
7290     { "phsubbw",        { XM, EXq } },
7291     { "phsubbd",        { XM, EXq } },
7292     { "phsubbq",        { XM, EXq } },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     /* 68 */
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     /* 70 */
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     /* 78 */
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     /* 80 */
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     /* 88 */
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     /* 90 */
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     /* 98 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     /* a0 */
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     /* a8 */
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     /* b0 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     /* b8 */
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     /* c0 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     /* c8 */
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     /* d0 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     /* d8 */
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     /* e0 */
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     /* e8 */
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     /* f0 */
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     /* f8 */
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468   },
7469 };
7470
7471 static const struct dis386 xop_table[][256] = {
7472   /* XOP_08 */
7473   {
7474     /* 00 */
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     /* 08 */
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     /* 10 */
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     /* 18 */
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     /* 20 */
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     /* 28 */
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     /* 30 */
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     /* 38 */
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     /* 40 */
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     /* 48 */
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     /* 50 */
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     /* 58 */
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     /* 60 */
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     /* 68 */
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     /* 70 */
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     /* 78 */
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     /* 80 */
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7625     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7626     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7627     /* 88 */
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7635     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7636     /* 90 */
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7643     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7644     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7645     /* 98 */
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7653     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7654     /* a0 */
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7658     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7662     { Bad_Opcode },
7663     /* a8 */
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     /* b0 */
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7680     { Bad_Opcode },
7681     /* b8 */
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     /* c0 */
7691     { "vprotb",         { XM, Vex_2src_1, Ib } },
7692     { "vprotw",         { XM, Vex_2src_1, Ib } },
7693     { "vprotd",         { XM, Vex_2src_1, Ib } },
7694     { "vprotq",         { XM, Vex_2src_1, Ib } },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     /* c8 */
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7705     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7706     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7707     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7708     /* d0 */
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     /* d8 */
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     /* e0 */
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     /* e8 */
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7741     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7742     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7743     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7744     /* f0 */
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     /* f8 */
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762   },
7763   /* XOP_09 */
7764   {
7765     /* 00 */
7766     { Bad_Opcode },
7767     { REG_TABLE (REG_XOP_TBM_01) },
7768     { REG_TABLE (REG_XOP_TBM_02) },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* 08 */
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     /* 10 */
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { REG_TABLE (REG_XOP_LWPCB) },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     /* 18 */
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* 20 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     /* 28 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* 30 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     /* 38 */
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* 40 */
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     /* 48 */
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     /* 50 */
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     /* 58 */
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     /* 60 */
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     /* 68 */
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     /* 70 */
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     /* 78 */
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     /* 80 */
7910     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7911     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7912     { "vfrczss",        { XM, EXd } },
7913     { "vfrczsd",        { XM, EXq } },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     /* 88 */
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     /* 90 */
7928     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
7929     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
7930     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
7931     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
7932     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
7933     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
7934     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
7935     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
7936     /* 98 */
7937     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
7938     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
7939     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
7940     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     /* a0 */
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     /* a8 */
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     /* b0 */
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     /* b8 */
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     /* c0 */
7982     { Bad_Opcode },
7983     { "vphaddbw",       { XM, EXxmm } },
7984     { "vphaddbd",       { XM, EXxmm } },
7985     { "vphaddbq",       { XM, EXxmm } },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { "vphaddwd",       { XM, EXxmm } },
7989     { "vphaddwq",       { XM, EXxmm } },
7990     /* c8 */
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { "vphadddq",       { XM, EXxmm } },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     /* d0 */
8000     { Bad_Opcode },
8001     { "vphaddubw",      { XM, EXxmm } },
8002     { "vphaddubd",      { XM, EXxmm } },
8003     { "vphaddubq",      { XM, EXxmm } },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { "vphadduwd",      { XM, EXxmm } },
8007     { "vphadduwq",      { XM, EXxmm } },
8008     /* d8 */
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { "vphaddudq",      { XM, EXxmm } },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     /* e0 */
8018     { Bad_Opcode },
8019     { "vphsubbw",       { XM, EXxmm } },
8020     { "vphsubwd",       { XM, EXxmm } },
8021     { "vphsubdq",       { XM, EXxmm } },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     /* e8 */
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     /* f0 */
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     /* f8 */
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053   },
8054   /* XOP_0A */
8055   {
8056     /* 00 */
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     /* 08 */
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     /* 10 */
8075     { "bextr",  { Gv, Ev, Iq } },
8076     { Bad_Opcode },
8077     { REG_TABLE (REG_XOP_LWP) },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     /* 18 */
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     /* 20 */
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     /* 28 */
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     /* 30 */
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     /* 38 */
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     /* 40 */
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     /* 48 */
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     /* 50 */
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     /* 58 */
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     /* 60 */
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     /* 68 */
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     /* 70 */
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     /* 78 */
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     /* 80 */
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     /* 88 */
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     /* 90 */
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     /* 98 */
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     /* a0 */
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     /* a8 */
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     /* b0 */
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     /* b8 */
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     /* c0 */
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     /* c8 */
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     /* d0 */
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     /* d8 */
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     /* e0 */
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     /* e8 */
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     /* f0 */
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     /* f8 */
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344   },
8345 };
8346
8347 static const struct dis386 vex_table[][256] = {
8348   /* VEX_0F */
8349   {
8350     /* 00 */
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     /* 08 */
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     /* 10 */
8369     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8370     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8371     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8372     { MOD_TABLE (MOD_VEX_0F13) },
8373     { VEX_W_TABLE (VEX_W_0F14) },
8374     { VEX_W_TABLE (VEX_W_0F15) },
8375     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8376     { MOD_TABLE (MOD_VEX_0F17) },
8377     /* 18 */
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     /* 20 */
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     /* 28 */
8396     { VEX_W_TABLE (VEX_W_0F28) },
8397     { VEX_W_TABLE (VEX_W_0F29) },
8398     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8399     { MOD_TABLE (MOD_VEX_0F2B) },
8400     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8401     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8402     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8403     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8404     /* 30 */
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     /* 38 */
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     /* 40 */
8423     { Bad_Opcode },
8424     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8425     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8426     { Bad_Opcode },
8427     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8428     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8429     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8431     /* 48 */
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     /* 50 */
8441     { MOD_TABLE (MOD_VEX_0F50) },
8442     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8443     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8444     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8445     { "vandpX",         { XM, Vex, EXx } },
8446     { "vandnpX",        { XM, Vex, EXx } },
8447     { "vorpX",          { XM, Vex, EXx } },
8448     { "vxorpX",         { XM, Vex, EXx } },
8449     /* 58 */
8450     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8451     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8452     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8453     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8454     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8456     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8457     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8458     /* 60 */
8459     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8460     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8461     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8462     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8463     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8464     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8465     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8466     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8467     /* 68 */
8468     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8469     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8470     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8471     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8472     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8473     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8474     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8475     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8476     /* 70 */
8477     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8478     { REG_TABLE (REG_VEX_0F71) },
8479     { REG_TABLE (REG_VEX_0F72) },
8480     { REG_TABLE (REG_VEX_0F73) },
8481     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8482     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8485     /* 78 */
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8491     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8492     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8493     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8494     /* 80 */
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     /* 88 */
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     /* 90 */
8513     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     /* 98 */
8522     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     /* a0 */
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     /* a8 */
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { REG_TABLE (REG_VEX_0FAE) },
8547     { Bad_Opcode },
8548     /* b0 */
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     /* b8 */
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     /* c0 */
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8570     { Bad_Opcode },
8571     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8572     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8573     { "vshufpX",        { XM, Vex, EXx, Ib } },
8574     { Bad_Opcode },
8575     /* c8 */
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     /* d0 */
8585     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8586     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8587     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8588     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8589     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8590     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8591     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8592     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8593     /* d8 */
8594     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8595     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8596     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8597     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8598     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8599     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8600     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8601     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8602     /* e0 */
8603     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8604     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8605     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8606     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8607     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8608     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8609     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8610     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8611     /* e8 */
8612     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8613     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8614     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8615     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8616     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8617     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8618     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8619     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8620     /* f0 */
8621     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8622     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8623     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8624     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8625     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8626     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8627     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8628     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8629     /* f8 */
8630     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8631     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8632     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8633     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8634     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8635     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8636     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8637     { Bad_Opcode },
8638   },
8639   /* VEX_0F38 */
8640   {
8641     /* 00 */
8642     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8646     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8650     /* 08 */
8651     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8652     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8654     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8659     /* 10 */
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8668     /* 18 */
8669     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8672     { Bad_Opcode },
8673     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8676     { Bad_Opcode },
8677     /* 20 */
8678     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8679     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8680     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8681     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8682     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     /* 28 */
8687     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8688     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8689     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8690     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8691     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8695     /* 30 */
8696     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8704     /* 38 */
8705     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8713     /* 40 */
8714     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8722     /* 48 */
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     /* 50 */
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     /* 58 */
8741     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     /* 60 */
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     /* 68 */
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     /* 70 */
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     /* 78 */
8777     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     /* 80 */
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     /* 88 */
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8800     { Bad_Opcode },
8801     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8802     { Bad_Opcode },
8803     /* 90 */
8804     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8812     /* 98 */
8813     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8814     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8817     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8818     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8821     /* a0 */
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8830     /* a8 */
8831     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8832     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8835     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8836     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8837     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8838     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8839     /* b0 */
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8848     /* b8 */
8849     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8850     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8851     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8852     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8853     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8854     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8855     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8856     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8857     /* c0 */
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     /* c8 */
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     /* d0 */
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     /* d8 */
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8893     /* e0 */
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     /* e8 */
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     /* f0 */
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8915     { REG_TABLE (REG_VEX_0F38F3) },
8916     { Bad_Opcode },
8917     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8920     /* f8 */
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929   },
8930   /* VEX_0F3A */
8931   {
8932     /* 00 */
8933     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8936     { Bad_Opcode },
8937     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8940     { Bad_Opcode },
8941     /* 08 */
8942     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8950     /* 10 */
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8959     /* 18 */
8960     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     /* 20 */
8969     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     /* 28 */
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     /* 30 */
8987     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8988     { Bad_Opcode },
8989     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     /* 38 */
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     /* 40 */
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9008     { Bad_Opcode },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9010     { Bad_Opcode },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9012     { Bad_Opcode },
9013     /* 48 */
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     /* 50 */
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     /* 58 */
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9040     /* 60 */
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     /* 68 */
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9058     /* 70 */
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     /* 78 */
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9076     /* 80 */
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     /* 88 */
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     /* 90 */
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     /* 98 */
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     /* a0 */
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     /* a8 */
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     /* b0 */
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     /* b8 */
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     /* c0 */
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     /* c8 */
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     /* d0 */
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     /* d8 */
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9184     /* e0 */
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     /* e8 */
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     /* f0 */
9203     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     /* f8 */
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220   },
9221 };
9222
9223 #define NEED_OPCODE_TABLE
9224 #include "i386-dis-evex.h"
9225 #undef NEED_OPCODE_TABLE
9226 static const struct dis386 vex_len_table[][2] = {
9227   /* VEX_LEN_0F10_P_1 */
9228   {
9229     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9230     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9231   },
9232
9233   /* VEX_LEN_0F10_P_3 */
9234   {
9235     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9236     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9237   },
9238
9239   /* VEX_LEN_0F11_P_1 */
9240   {
9241     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9242     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9243   },
9244
9245   /* VEX_LEN_0F11_P_3 */
9246   {
9247     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9248     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9249   },
9250
9251   /* VEX_LEN_0F12_P_0_M_0 */
9252   {
9253     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9254   },
9255
9256   /* VEX_LEN_0F12_P_0_M_1 */
9257   {
9258     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9259   },
9260
9261   /* VEX_LEN_0F12_P_2 */
9262   {
9263     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9264   },
9265
9266   /* VEX_LEN_0F13_M_0 */
9267   {
9268     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9269   },
9270
9271   /* VEX_LEN_0F16_P_0_M_0 */
9272   {
9273     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9274   },
9275
9276   /* VEX_LEN_0F16_P_0_M_1 */
9277   {
9278     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9279   },
9280
9281   /* VEX_LEN_0F16_P_2 */
9282   {
9283     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9284   },
9285
9286   /* VEX_LEN_0F17_M_0 */
9287   {
9288     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9289   },
9290
9291   /* VEX_LEN_0F2A_P_1 */
9292   {
9293     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9294     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9295   },
9296
9297   /* VEX_LEN_0F2A_P_3 */
9298   {
9299     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9300     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9301   },
9302
9303   /* VEX_LEN_0F2C_P_1 */
9304   {
9305     { "vcvttss2siY",    { Gv, EXdScalar } },
9306     { "vcvttss2siY",    { Gv, EXdScalar } },
9307   },
9308
9309   /* VEX_LEN_0F2C_P_3 */
9310   {
9311     { "vcvttsd2siY",    { Gv, EXqScalar } },
9312     { "vcvttsd2siY",    { Gv, EXqScalar } },
9313   },
9314
9315   /* VEX_LEN_0F2D_P_1 */
9316   {
9317     { "vcvtss2siY",     { Gv, EXdScalar } },
9318     { "vcvtss2siY",     { Gv, EXdScalar } },
9319   },
9320
9321   /* VEX_LEN_0F2D_P_3 */
9322   {
9323     { "vcvtsd2siY",     { Gv, EXqScalar } },
9324     { "vcvtsd2siY",     { Gv, EXqScalar } },
9325   },
9326
9327   /* VEX_LEN_0F2E_P_0 */
9328   {
9329     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9330     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9331   },
9332
9333   /* VEX_LEN_0F2E_P_2 */
9334   {
9335     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9336     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9337   },
9338
9339   /* VEX_LEN_0F2F_P_0 */
9340   {
9341     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9342     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9343   },
9344
9345   /* VEX_LEN_0F2F_P_2 */
9346   {
9347     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9348     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9349   },
9350
9351   /* VEX_LEN_0F41_P_0 */
9352   {
9353     { Bad_Opcode },
9354     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9355   },
9356   /* VEX_LEN_0F42_P_0 */
9357   {
9358     { Bad_Opcode },
9359     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9360   },
9361   /* VEX_LEN_0F44_P_0 */
9362   {
9363     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9364   },
9365   /* VEX_LEN_0F45_P_0 */
9366   {
9367     { Bad_Opcode },
9368     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9369   },
9370   /* VEX_LEN_0F46_P_0 */
9371   {
9372     { Bad_Opcode },
9373     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9374   },
9375   /* VEX_LEN_0F47_P_0 */
9376   {
9377     { Bad_Opcode },
9378     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9379   },
9380   /* VEX_LEN_0F4B_P_2 */
9381   {
9382     { Bad_Opcode },
9383     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9384   },
9385
9386   /* VEX_LEN_0F51_P_1 */
9387   {
9388     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9389     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9390   },
9391
9392   /* VEX_LEN_0F51_P_3 */
9393   {
9394     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9395     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9396   },
9397
9398   /* VEX_LEN_0F52_P_1 */
9399   {
9400     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9401     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9402   },
9403
9404   /* VEX_LEN_0F53_P_1 */
9405   {
9406     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9407     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9408   },
9409
9410   /* VEX_LEN_0F58_P_1 */
9411   {
9412     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9413     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9414   },
9415
9416   /* VEX_LEN_0F58_P_3 */
9417   {
9418     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9419     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9420   },
9421
9422   /* VEX_LEN_0F59_P_1 */
9423   {
9424     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9425     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9426   },
9427
9428   /* VEX_LEN_0F59_P_3 */
9429   {
9430     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9431     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9432   },
9433
9434   /* VEX_LEN_0F5A_P_1 */
9435   {
9436     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9437     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9438   },
9439
9440   /* VEX_LEN_0F5A_P_3 */
9441   {
9442     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9443     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9444   },
9445
9446   /* VEX_LEN_0F5C_P_1 */
9447   {
9448     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9449     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9450   },
9451
9452   /* VEX_LEN_0F5C_P_3 */
9453   {
9454     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9455     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9456   },
9457
9458   /* VEX_LEN_0F5D_P_1 */
9459   {
9460     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9461     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9462   },
9463
9464   /* VEX_LEN_0F5D_P_3 */
9465   {
9466     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9467     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9468   },
9469
9470   /* VEX_LEN_0F5E_P_1 */
9471   {
9472     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9473     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9474   },
9475
9476   /* VEX_LEN_0F5E_P_3 */
9477   {
9478     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9479     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9480   },
9481
9482   /* VEX_LEN_0F5F_P_1 */
9483   {
9484     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9485     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9486   },
9487
9488   /* VEX_LEN_0F5F_P_3 */
9489   {
9490     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9491     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9492   },
9493
9494   /* VEX_LEN_0F6E_P_2 */
9495   {
9496     { "vmovK",          { XMScalar, Edq } },
9497     { "vmovK",          { XMScalar, Edq } },
9498   },
9499
9500   /* VEX_LEN_0F7E_P_1 */
9501   {
9502     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9503     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9504   },
9505
9506   /* VEX_LEN_0F7E_P_2 */
9507   {
9508     { "vmovK",          { Edq, XMScalar } },
9509     { "vmovK",          { Edq, XMScalar } },
9510   },
9511
9512   /* VEX_LEN_0F90_P_0 */
9513   {
9514     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9515   },
9516
9517   /* VEX_LEN_0F91_P_0 */
9518   {
9519     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9520   },
9521
9522   /* VEX_LEN_0F92_P_0 */
9523   {
9524     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9525   },
9526
9527   /* VEX_LEN_0F93_P_0 */
9528   {
9529     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9530   },
9531
9532   /* VEX_LEN_0F98_P_0 */
9533   {
9534     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9535   },
9536
9537   /* VEX_LEN_0FAE_R_2_M_0 */
9538   {
9539     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9540   },
9541
9542   /* VEX_LEN_0FAE_R_3_M_0 */
9543   {
9544     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9545   },
9546
9547   /* VEX_LEN_0FC2_P_1 */
9548   {
9549     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9550     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9551   },
9552
9553   /* VEX_LEN_0FC2_P_3 */
9554   {
9555     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9556     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9557   },
9558
9559   /* VEX_LEN_0FC4_P_2 */
9560   {
9561     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9562   },
9563
9564   /* VEX_LEN_0FC5_P_2 */
9565   {
9566     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9567   },
9568
9569   /* VEX_LEN_0FD6_P_2 */
9570   {
9571     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9572     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9573   },
9574
9575   /* VEX_LEN_0FF7_P_2 */
9576   {
9577     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9578   },
9579
9580   /* VEX_LEN_0F3816_P_2 */
9581   {
9582     { Bad_Opcode },
9583     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9584   },
9585
9586   /* VEX_LEN_0F3819_P_2 */
9587   {
9588     { Bad_Opcode },
9589     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9590   },
9591
9592   /* VEX_LEN_0F381A_P_2_M_0 */
9593   {
9594     { Bad_Opcode },
9595     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9596   },
9597
9598   /* VEX_LEN_0F3836_P_2 */
9599   {
9600     { Bad_Opcode },
9601     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9602   },
9603
9604   /* VEX_LEN_0F3841_P_2 */
9605   {
9606     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9607   },
9608
9609   /* VEX_LEN_0F385A_P_2_M_0 */
9610   {
9611     { Bad_Opcode },
9612     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9613   },
9614
9615   /* VEX_LEN_0F38DB_P_2 */
9616   {
9617     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9618   },
9619
9620   /* VEX_LEN_0F38DC_P_2 */
9621   {
9622     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9623   },
9624
9625   /* VEX_LEN_0F38DD_P_2 */
9626   {
9627     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9628   },
9629
9630   /* VEX_LEN_0F38DE_P_2 */
9631   {
9632     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9633   },
9634
9635   /* VEX_LEN_0F38DF_P_2 */
9636   {
9637     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9638   },
9639
9640   /* VEX_LEN_0F38F2_P_0 */
9641   {
9642     { "andnS",          { Gdq, VexGdq, Edq } },
9643   },
9644
9645   /* VEX_LEN_0F38F3_R_1_P_0 */
9646   {
9647     { "blsrS",          { VexGdq, Edq } },
9648   },
9649
9650   /* VEX_LEN_0F38F3_R_2_P_0 */
9651   {
9652     { "blsmskS",        { VexGdq, Edq } },
9653   },
9654
9655   /* VEX_LEN_0F38F3_R_3_P_0 */
9656   {
9657     { "blsiS",          { VexGdq, Edq } },
9658   },
9659
9660   /* VEX_LEN_0F38F5_P_0 */
9661   {
9662     { "bzhiS",          { Gdq, Edq, VexGdq } },
9663   },
9664
9665   /* VEX_LEN_0F38F5_P_1 */
9666   {
9667     { "pextS",          { Gdq, VexGdq, Edq } },
9668   },
9669
9670   /* VEX_LEN_0F38F5_P_3 */
9671   {
9672     { "pdepS",          { Gdq, VexGdq, Edq } },
9673   },
9674
9675   /* VEX_LEN_0F38F6_P_3 */
9676   {
9677     { "mulxS",          { Gdq, VexGdq, Edq } },
9678   },
9679
9680   /* VEX_LEN_0F38F7_P_0 */
9681   {
9682     { "bextrS",         { Gdq, Edq, VexGdq } },
9683   },
9684
9685   /* VEX_LEN_0F38F7_P_1 */
9686   {
9687     { "sarxS",          { Gdq, Edq, VexGdq } },
9688   },
9689
9690   /* VEX_LEN_0F38F7_P_2 */
9691   {
9692     { "shlxS",          { Gdq, Edq, VexGdq } },
9693   },
9694
9695   /* VEX_LEN_0F38F7_P_3 */
9696   {
9697     { "shrxS",          { Gdq, Edq, VexGdq } },
9698   },
9699
9700   /* VEX_LEN_0F3A00_P_2 */
9701   {
9702     { Bad_Opcode },
9703     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9704   },
9705
9706   /* VEX_LEN_0F3A01_P_2 */
9707   {
9708     { Bad_Opcode },
9709     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9710   },
9711
9712   /* VEX_LEN_0F3A06_P_2 */
9713   {
9714     { Bad_Opcode },
9715     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9716   },
9717
9718   /* VEX_LEN_0F3A0A_P_2 */
9719   {
9720     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9721     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9722   },
9723
9724   /* VEX_LEN_0F3A0B_P_2 */
9725   {
9726     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9727     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9728   },
9729
9730   /* VEX_LEN_0F3A14_P_2 */
9731   {
9732     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9733   },
9734
9735   /* VEX_LEN_0F3A15_P_2 */
9736   {
9737     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9738   },
9739
9740   /* VEX_LEN_0F3A16_P_2  */
9741   {
9742     { "vpextrK",        { Edq, XM, Ib } },
9743   },
9744
9745   /* VEX_LEN_0F3A17_P_2 */
9746   {
9747     { "vextractps",     { Edqd, XM, Ib } },
9748   },
9749
9750   /* VEX_LEN_0F3A18_P_2 */
9751   {
9752     { Bad_Opcode },
9753     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9754   },
9755
9756   /* VEX_LEN_0F3A19_P_2 */
9757   {
9758     { Bad_Opcode },
9759     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9760   },
9761
9762   /* VEX_LEN_0F3A20_P_2 */
9763   {
9764     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9765   },
9766
9767   /* VEX_LEN_0F3A21_P_2 */
9768   {
9769     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9770   },
9771
9772   /* VEX_LEN_0F3A22_P_2 */
9773   {
9774     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9775   },
9776
9777   /* VEX_LEN_0F3A30_P_2 */
9778   {
9779     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9780   },
9781
9782   /* VEX_LEN_0F3A32_P_2 */
9783   {
9784     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9785   },
9786
9787   /* VEX_LEN_0F3A38_P_2 */
9788   {
9789     { Bad_Opcode },
9790     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9791   },
9792
9793   /* VEX_LEN_0F3A39_P_2 */
9794   {
9795     { Bad_Opcode },
9796     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9797   },
9798
9799   /* VEX_LEN_0F3A41_P_2 */
9800   {
9801     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9802   },
9803
9804   /* VEX_LEN_0F3A44_P_2 */
9805   {
9806     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9807   },
9808
9809   /* VEX_LEN_0F3A46_P_2 */
9810   {
9811     { Bad_Opcode },
9812     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9813   },
9814
9815   /* VEX_LEN_0F3A60_P_2 */
9816   {
9817     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9818   },
9819
9820   /* VEX_LEN_0F3A61_P_2 */
9821   {
9822     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9823   },
9824
9825   /* VEX_LEN_0F3A62_P_2 */
9826   {
9827     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9828   },
9829
9830   /* VEX_LEN_0F3A63_P_2 */
9831   {
9832     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9833   },
9834
9835   /* VEX_LEN_0F3A6A_P_2 */
9836   {
9837     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9838   },
9839
9840   /* VEX_LEN_0F3A6B_P_2 */
9841   {
9842     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9843   },
9844
9845   /* VEX_LEN_0F3A6E_P_2 */
9846   {
9847     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9848   },
9849
9850   /* VEX_LEN_0F3A6F_P_2 */
9851   {
9852     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9853   },
9854
9855   /* VEX_LEN_0F3A7A_P_2 */
9856   {
9857     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9858   },
9859
9860   /* VEX_LEN_0F3A7B_P_2 */
9861   {
9862     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9863   },
9864
9865   /* VEX_LEN_0F3A7E_P_2 */
9866   {
9867     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9868   },
9869
9870   /* VEX_LEN_0F3A7F_P_2 */
9871   {
9872     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9873   },
9874
9875   /* VEX_LEN_0F3ADF_P_2 */
9876   {
9877     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9878   },
9879
9880   /* VEX_LEN_0F3AF0_P_3 */
9881   {
9882     { "rorxS",          { Gdq, Edq, Ib } },
9883   },
9884
9885   /* VEX_LEN_0FXOP_08_CC */
9886   {
9887      { "vpcomb",        { XM, Vex128, EXx, Ib } },
9888   },
9889
9890   /* VEX_LEN_0FXOP_08_CD */
9891   {
9892      { "vpcomw",        { XM, Vex128, EXx, Ib } },
9893   },
9894
9895   /* VEX_LEN_0FXOP_08_CE */
9896   {
9897      { "vpcomd",        { XM, Vex128, EXx, Ib } },
9898   },
9899
9900   /* VEX_LEN_0FXOP_08_CF */
9901   {
9902      { "vpcomq",        { XM, Vex128, EXx, Ib } },
9903   },
9904
9905   /* VEX_LEN_0FXOP_08_EC */
9906   {
9907      { "vpcomub",       { XM, Vex128, EXx, Ib } },
9908   },
9909
9910   /* VEX_LEN_0FXOP_08_ED */
9911   {
9912      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
9913   },
9914
9915   /* VEX_LEN_0FXOP_08_EE */
9916   {
9917      { "vpcomud",       { XM, Vex128, EXx, Ib } },
9918   },
9919
9920   /* VEX_LEN_0FXOP_08_EF */
9921   {
9922      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
9923   },
9924
9925   /* VEX_LEN_0FXOP_09_80 */
9926   {
9927     { "vfrczps",        { XM, EXxmm } },
9928     { "vfrczps",        { XM, EXymmq } },
9929   },
9930
9931   /* VEX_LEN_0FXOP_09_81 */
9932   {
9933     { "vfrczpd",        { XM, EXxmm } },
9934     { "vfrczpd",        { XM, EXymmq } },
9935   },
9936 };
9937
9938 static const struct dis386 vex_w_table[][2] = {
9939   {
9940     /* VEX_W_0F10_P_0 */
9941     { "vmovups",        { XM, EXx } },
9942   },
9943   {
9944     /* VEX_W_0F10_P_1 */
9945     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9946   },
9947   {
9948     /* VEX_W_0F10_P_2 */
9949     { "vmovupd",        { XM, EXx } },
9950   },
9951   {
9952     /* VEX_W_0F10_P_3 */
9953     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9954   },
9955   {
9956     /* VEX_W_0F11_P_0 */
9957     { "vmovups",        { EXxS, XM } },
9958   },
9959   {
9960     /* VEX_W_0F11_P_1 */
9961     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9962   },
9963   {
9964     /* VEX_W_0F11_P_2 */
9965     { "vmovupd",        { EXxS, XM } },
9966   },
9967   {
9968     /* VEX_W_0F11_P_3 */
9969     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9970   },
9971   {
9972     /* VEX_W_0F12_P_0_M_0 */
9973     { "vmovlps",        { XM, Vex128, EXq } },
9974   },
9975   {
9976     /* VEX_W_0F12_P_0_M_1 */
9977     { "vmovhlps",       { XM, Vex128, EXq } },
9978   },
9979   {
9980     /* VEX_W_0F12_P_1 */
9981     { "vmovsldup",      { XM, EXx } },
9982   },
9983   {
9984     /* VEX_W_0F12_P_2 */
9985     { "vmovlpd",        { XM, Vex128, EXq } },
9986   },
9987   {
9988     /* VEX_W_0F12_P_3 */
9989     { "vmovddup",       { XM, EXymmq } },
9990   },
9991   {
9992     /* VEX_W_0F13_M_0 */
9993     { "vmovlpX",        { EXq, XM } },
9994   },
9995   {
9996     /* VEX_W_0F14 */
9997     { "vunpcklpX",      { XM, Vex, EXx } },
9998   },
9999   {
10000     /* VEX_W_0F15 */
10001     { "vunpckhpX",      { XM, Vex, EXx } },
10002   },
10003   {
10004     /* VEX_W_0F16_P_0_M_0 */
10005     { "vmovhps",        { XM, Vex128, EXq } },
10006   },
10007   {
10008     /* VEX_W_0F16_P_0_M_1 */
10009     { "vmovlhps",       { XM, Vex128, EXq } },
10010   },
10011   {
10012     /* VEX_W_0F16_P_1 */
10013     { "vmovshdup",      { XM, EXx } },
10014   },
10015   {
10016     /* VEX_W_0F16_P_2 */
10017     { "vmovhpd",        { XM, Vex128, EXq } },
10018   },
10019   {
10020     /* VEX_W_0F17_M_0 */
10021     { "vmovhpX",        { EXq, XM } },
10022   },
10023   {
10024     /* VEX_W_0F28 */
10025     { "vmovapX",        { XM, EXx } },
10026   },
10027   {
10028     /* VEX_W_0F29 */
10029     { "vmovapX",        { EXxS, XM } },
10030   },
10031   {
10032     /* VEX_W_0F2B_M_0 */
10033     { "vmovntpX",       { Mx, XM } },
10034   },
10035   {
10036     /* VEX_W_0F2E_P_0 */
10037     { "vucomiss",       { XMScalar, EXdScalar } },
10038   },
10039   {
10040     /* VEX_W_0F2E_P_2 */
10041     { "vucomisd",       { XMScalar, EXqScalar } },
10042   },
10043   {
10044     /* VEX_W_0F2F_P_0 */
10045     { "vcomiss",        { XMScalar, EXdScalar } },
10046   },
10047   {
10048     /* VEX_W_0F2F_P_2 */
10049     { "vcomisd",        { XMScalar, EXqScalar } },
10050   },
10051   {
10052     /* VEX_W_0F41_P_0_LEN_1 */
10053     { "kandw",          { MaskG, MaskVex, MaskR } },
10054   },
10055   {
10056     /* VEX_W_0F42_P_0_LEN_1 */
10057     { "kandnw",         { MaskG, MaskVex, MaskR } },
10058   },
10059   {
10060     /* VEX_W_0F44_P_0_LEN_0 */
10061     { "knotw",          { MaskG, MaskR } },
10062   },
10063   {
10064     /* VEX_W_0F45_P_0_LEN_1 */
10065     { "korw",           { MaskG, MaskVex, MaskR } },
10066   },
10067   {
10068     /* VEX_W_0F46_P_0_LEN_1 */
10069     { "kxnorw",         { MaskG, MaskVex, MaskR } },
10070   },
10071   {
10072     /* VEX_W_0F47_P_0_LEN_1 */
10073     { "kxorw",          { MaskG, MaskVex, MaskR } },
10074   },
10075   {
10076     /* VEX_W_0F4B_P_2_LEN_1 */
10077     { "kunpckbw",       { MaskG, MaskVex, MaskR } },
10078   },
10079   {
10080     /* VEX_W_0F50_M_0 */
10081     { "vmovmskpX",      { Gdq, XS } },
10082   },
10083   {
10084     /* VEX_W_0F51_P_0 */
10085     { "vsqrtps",        { XM, EXx } },
10086   },
10087   {
10088     /* VEX_W_0F51_P_1 */
10089     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
10090   },
10091   {
10092     /* VEX_W_0F51_P_2  */
10093     { "vsqrtpd",        { XM, EXx } },
10094   },
10095   {
10096     /* VEX_W_0F51_P_3 */
10097     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
10098   },
10099   {
10100     /* VEX_W_0F52_P_0 */
10101     { "vrsqrtps",       { XM, EXx } },
10102   },
10103   {
10104     /* VEX_W_0F52_P_1 */
10105     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
10106   },
10107   {
10108     /* VEX_W_0F53_P_0  */
10109     { "vrcpps",         { XM, EXx } },
10110   },
10111   {
10112     /* VEX_W_0F53_P_1  */
10113     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
10114   },
10115   {
10116     /* VEX_W_0F58_P_0  */
10117     { "vaddps",         { XM, Vex, EXx } },
10118   },
10119   {
10120     /* VEX_W_0F58_P_1  */
10121     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
10122   },
10123   {
10124     /* VEX_W_0F58_P_2  */
10125     { "vaddpd",         { XM, Vex, EXx } },
10126   },
10127   {
10128     /* VEX_W_0F58_P_3  */
10129     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
10130   },
10131   {
10132     /* VEX_W_0F59_P_0  */
10133     { "vmulps",         { XM, Vex, EXx } },
10134   },
10135   {
10136     /* VEX_W_0F59_P_1  */
10137     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
10138   },
10139   {
10140     /* VEX_W_0F59_P_2  */
10141     { "vmulpd",         { XM, Vex, EXx } },
10142   },
10143   {
10144     /* VEX_W_0F59_P_3  */
10145     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
10146   },
10147   {
10148     /* VEX_W_0F5A_P_0  */
10149     { "vcvtps2pd",      { XM, EXxmmq } },
10150   },
10151   {
10152     /* VEX_W_0F5A_P_1  */
10153     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
10154   },
10155   {
10156     /* VEX_W_0F5A_P_3  */
10157     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
10158   },
10159   {
10160     /* VEX_W_0F5B_P_0  */
10161     { "vcvtdq2ps",      { XM, EXx } },
10162   },
10163   {
10164     /* VEX_W_0F5B_P_1  */
10165     { "vcvttps2dq",     { XM, EXx } },
10166   },
10167   {
10168     /* VEX_W_0F5B_P_2  */
10169     { "vcvtps2dq",      { XM, EXx } },
10170   },
10171   {
10172     /* VEX_W_0F5C_P_0  */
10173     { "vsubps",         { XM, Vex, EXx } },
10174   },
10175   {
10176     /* VEX_W_0F5C_P_1  */
10177     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
10178   },
10179   {
10180     /* VEX_W_0F5C_P_2  */
10181     { "vsubpd",         { XM, Vex, EXx } },
10182   },
10183   {
10184     /* VEX_W_0F5C_P_3  */
10185     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
10186   },
10187   {
10188     /* VEX_W_0F5D_P_0  */
10189     { "vminps",         { XM, Vex, EXx } },
10190   },
10191   {
10192     /* VEX_W_0F5D_P_1  */
10193     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
10194   },
10195   {
10196     /* VEX_W_0F5D_P_2  */
10197     { "vminpd",         { XM, Vex, EXx } },
10198   },
10199   {
10200     /* VEX_W_0F5D_P_3  */
10201     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
10202   },
10203   {
10204     /* VEX_W_0F5E_P_0  */
10205     { "vdivps",         { XM, Vex, EXx } },
10206   },
10207   {
10208     /* VEX_W_0F5E_P_1  */
10209     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
10210   },
10211   {
10212     /* VEX_W_0F5E_P_2  */
10213     { "vdivpd",         { XM, Vex, EXx } },
10214   },
10215   {
10216     /* VEX_W_0F5E_P_3  */
10217     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
10218   },
10219   {
10220     /* VEX_W_0F5F_P_0  */
10221     { "vmaxps",         { XM, Vex, EXx } },
10222   },
10223   {
10224     /* VEX_W_0F5F_P_1  */
10225     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
10226   },
10227   {
10228     /* VEX_W_0F5F_P_2  */
10229     { "vmaxpd",         { XM, Vex, EXx } },
10230   },
10231   {
10232     /* VEX_W_0F5F_P_3  */
10233     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
10234   },
10235   {
10236     /* VEX_W_0F60_P_2  */
10237     { "vpunpcklbw",     { XM, Vex, EXx } },
10238   },
10239   {
10240     /* VEX_W_0F61_P_2  */
10241     { "vpunpcklwd",     { XM, Vex, EXx } },
10242   },
10243   {
10244     /* VEX_W_0F62_P_2  */
10245     { "vpunpckldq",     { XM, Vex, EXx } },
10246   },
10247   {
10248     /* VEX_W_0F63_P_2  */
10249     { "vpacksswb",      { XM, Vex, EXx } },
10250   },
10251   {
10252     /* VEX_W_0F64_P_2  */
10253     { "vpcmpgtb",       { XM, Vex, EXx } },
10254   },
10255   {
10256     /* VEX_W_0F65_P_2  */
10257     { "vpcmpgtw",       { XM, Vex, EXx } },
10258   },
10259   {
10260     /* VEX_W_0F66_P_2  */
10261     { "vpcmpgtd",       { XM, Vex, EXx } },
10262   },
10263   {
10264     /* VEX_W_0F67_P_2  */
10265     { "vpackuswb",      { XM, Vex, EXx } },
10266   },
10267   {
10268     /* VEX_W_0F68_P_2  */
10269     { "vpunpckhbw",     { XM, Vex, EXx } },
10270   },
10271   {
10272     /* VEX_W_0F69_P_2  */
10273     { "vpunpckhwd",     { XM, Vex, EXx } },
10274   },
10275   {
10276     /* VEX_W_0F6A_P_2  */
10277     { "vpunpckhdq",     { XM, Vex, EXx } },
10278   },
10279   {
10280     /* VEX_W_0F6B_P_2  */
10281     { "vpackssdw",      { XM, Vex, EXx } },
10282   },
10283   {
10284     /* VEX_W_0F6C_P_2  */
10285     { "vpunpcklqdq",    { XM, Vex, EXx } },
10286   },
10287   {
10288     /* VEX_W_0F6D_P_2  */
10289     { "vpunpckhqdq",    { XM, Vex, EXx } },
10290   },
10291   {
10292     /* VEX_W_0F6F_P_1  */
10293     { "vmovdqu",        { XM, EXx } },
10294   },
10295   {
10296     /* VEX_W_0F6F_P_2  */
10297     { "vmovdqa",        { XM, EXx } },
10298   },
10299   {
10300     /* VEX_W_0F70_P_1 */
10301     { "vpshufhw",       { XM, EXx, Ib } },
10302   },
10303   {
10304     /* VEX_W_0F70_P_2 */
10305     { "vpshufd",        { XM, EXx, Ib } },
10306   },
10307   {
10308     /* VEX_W_0F70_P_3 */
10309     { "vpshuflw",       { XM, EXx, Ib } },
10310   },
10311   {
10312     /* VEX_W_0F71_R_2_P_2  */
10313     { "vpsrlw",         { Vex, XS, Ib } },
10314   },
10315   {
10316     /* VEX_W_0F71_R_4_P_2  */
10317     { "vpsraw",         { Vex, XS, Ib } },
10318   },
10319   {
10320     /* VEX_W_0F71_R_6_P_2  */
10321     { "vpsllw",         { Vex, XS, Ib } },
10322   },
10323   {
10324     /* VEX_W_0F72_R_2_P_2  */
10325     { "vpsrld",         { Vex, XS, Ib } },
10326   },
10327   {
10328     /* VEX_W_0F72_R_4_P_2  */
10329     { "vpsrad",         { Vex, XS, Ib } },
10330   },
10331   {
10332     /* VEX_W_0F72_R_6_P_2  */
10333     { "vpslld",         { Vex, XS, Ib } },
10334   },
10335   {
10336     /* VEX_W_0F73_R_2_P_2  */
10337     { "vpsrlq",         { Vex, XS, Ib } },
10338   },
10339   {
10340     /* VEX_W_0F73_R_3_P_2  */
10341     { "vpsrldq",        { Vex, XS, Ib } },
10342   },
10343   {
10344     /* VEX_W_0F73_R_6_P_2  */
10345     { "vpsllq",         { Vex, XS, Ib } },
10346   },
10347   {
10348     /* VEX_W_0F73_R_7_P_2  */
10349     { "vpslldq",        { Vex, XS, Ib } },
10350   },
10351   {
10352     /* VEX_W_0F74_P_2 */
10353     { "vpcmpeqb",       { XM, Vex, EXx } },
10354   },
10355   {
10356     /* VEX_W_0F75_P_2 */
10357     { "vpcmpeqw",       { XM, Vex, EXx } },
10358   },
10359   {
10360     /* VEX_W_0F76_P_2 */
10361     { "vpcmpeqd",       { XM, Vex, EXx } },
10362   },
10363   {
10364     /* VEX_W_0F77_P_0 */
10365     { "",               { VZERO } },
10366   },
10367   {
10368     /* VEX_W_0F7C_P_2 */
10369     { "vhaddpd",        { XM, Vex, EXx } },
10370   },
10371   {
10372     /* VEX_W_0F7C_P_3 */
10373     { "vhaddps",        { XM, Vex, EXx } },
10374   },
10375   {
10376     /* VEX_W_0F7D_P_2 */
10377     { "vhsubpd",        { XM, Vex, EXx } },
10378   },
10379   {
10380     /* VEX_W_0F7D_P_3 */
10381     { "vhsubps",        { XM, Vex, EXx } },
10382   },
10383   {
10384     /* VEX_W_0F7E_P_1 */
10385     { "vmovq",          { XMScalar, EXqScalar } },
10386   },
10387   {
10388     /* VEX_W_0F7F_P_1 */
10389     { "vmovdqu",        { EXxS, XM } },
10390   },
10391   {
10392     /* VEX_W_0F7F_P_2 */
10393     { "vmovdqa",        { EXxS, XM } },
10394   },
10395   {
10396     /* VEX_W_0F90_P_0_LEN_0 */
10397     { "kmovw",          { MaskG, MaskE } },
10398   },
10399   {
10400     /* VEX_W_0F91_P_0_LEN_0 */
10401     { "kmovw",          { Ew, MaskG } },
10402   },
10403   {
10404     /* VEX_W_0F92_P_0_LEN_0 */
10405     { "kmovw",          { MaskG, Rdq } },
10406   },
10407   {
10408     /* VEX_W_0F93_P_0_LEN_0 */
10409     { "kmovw",          { Gdq, MaskR } },
10410   },
10411   {
10412     /* VEX_W_0F98_P_0_LEN_0 */
10413     { "kortestw",       { MaskG, MaskR } },
10414   },
10415   {
10416     /* VEX_W_0FAE_R_2_M_0 */
10417     { "vldmxcsr",       { Md } },
10418   },
10419   {
10420     /* VEX_W_0FAE_R_3_M_0 */
10421     { "vstmxcsr",       { Md } },
10422   },
10423   {
10424     /* VEX_W_0FC2_P_0 */
10425     { "vcmpps",         { XM, Vex, EXx, VCMP } },
10426   },
10427   {
10428     /* VEX_W_0FC2_P_1 */
10429     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
10430   },
10431   {
10432     /* VEX_W_0FC2_P_2 */
10433     { "vcmppd",         { XM, Vex, EXx, VCMP } },
10434   },
10435   {
10436     /* VEX_W_0FC2_P_3 */
10437     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
10438   },
10439   {
10440     /* VEX_W_0FC4_P_2 */
10441     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
10442   },
10443   {
10444     /* VEX_W_0FC5_P_2 */
10445     { "vpextrw",        { Gdq, XS, Ib } },
10446   },
10447   {
10448     /* VEX_W_0FD0_P_2 */
10449     { "vaddsubpd",      { XM, Vex, EXx } },
10450   },
10451   {
10452     /* VEX_W_0FD0_P_3 */
10453     { "vaddsubps",      { XM, Vex, EXx } },
10454   },
10455   {
10456     /* VEX_W_0FD1_P_2 */
10457     { "vpsrlw",         { XM, Vex, EXxmm } },
10458   },
10459   {
10460     /* VEX_W_0FD2_P_2 */
10461     { "vpsrld",         { XM, Vex, EXxmm } },
10462   },
10463   {
10464     /* VEX_W_0FD3_P_2 */
10465     { "vpsrlq",         { XM, Vex, EXxmm } },
10466   },
10467   {
10468     /* VEX_W_0FD4_P_2 */
10469     { "vpaddq",         { XM, Vex, EXx } },
10470   },
10471   {
10472     /* VEX_W_0FD5_P_2 */
10473     { "vpmullw",        { XM, Vex, EXx } },
10474   },
10475   {
10476     /* VEX_W_0FD6_P_2 */
10477     { "vmovq",          { EXqScalarS, XMScalar } },
10478   },
10479   {
10480     /* VEX_W_0FD7_P_2_M_1 */
10481     { "vpmovmskb",      { Gdq, XS } },
10482   },
10483   {
10484     /* VEX_W_0FD8_P_2 */
10485     { "vpsubusb",       { XM, Vex, EXx } },
10486   },
10487   {
10488     /* VEX_W_0FD9_P_2 */
10489     { "vpsubusw",       { XM, Vex, EXx } },
10490   },
10491   {
10492     /* VEX_W_0FDA_P_2 */
10493     { "vpminub",        { XM, Vex, EXx } },
10494   },
10495   {
10496     /* VEX_W_0FDB_P_2 */
10497     { "vpand",          { XM, Vex, EXx } },
10498   },
10499   {
10500     /* VEX_W_0FDC_P_2 */
10501     { "vpaddusb",       { XM, Vex, EXx } },
10502   },
10503   {
10504     /* VEX_W_0FDD_P_2 */
10505     { "vpaddusw",       { XM, Vex, EXx } },
10506   },
10507   {
10508     /* VEX_W_0FDE_P_2 */
10509     { "vpmaxub",        { XM, Vex, EXx } },
10510   },
10511   {
10512     /* VEX_W_0FDF_P_2 */
10513     { "vpandn",         { XM, Vex, EXx } },
10514   },
10515   {
10516     /* VEX_W_0FE0_P_2  */
10517     { "vpavgb",         { XM, Vex, EXx } },
10518   },
10519   {
10520     /* VEX_W_0FE1_P_2  */
10521     { "vpsraw",         { XM, Vex, EXxmm } },
10522   },
10523   {
10524     /* VEX_W_0FE2_P_2  */
10525     { "vpsrad",         { XM, Vex, EXxmm } },
10526   },
10527   {
10528     /* VEX_W_0FE3_P_2  */
10529     { "vpavgw",         { XM, Vex, EXx } },
10530   },
10531   {
10532     /* VEX_W_0FE4_P_2  */
10533     { "vpmulhuw",       { XM, Vex, EXx } },
10534   },
10535   {
10536     /* VEX_W_0FE5_P_2  */
10537     { "vpmulhw",        { XM, Vex, EXx } },
10538   },
10539   {
10540     /* VEX_W_0FE6_P_1  */
10541     { "vcvtdq2pd",      { XM, EXxmmq } },
10542   },
10543   {
10544     /* VEX_W_0FE6_P_2  */
10545     { "vcvttpd2dq%XY",  { XMM, EXx } },
10546   },
10547   {
10548     /* VEX_W_0FE6_P_3  */
10549     { "vcvtpd2dq%XY",   { XMM, EXx } },
10550   },
10551   {
10552     /* VEX_W_0FE7_P_2_M_0 */
10553     { "vmovntdq",       { Mx, XM } },
10554   },
10555   {
10556     /* VEX_W_0FE8_P_2  */
10557     { "vpsubsb",        { XM, Vex, EXx } },
10558   },
10559   {
10560     /* VEX_W_0FE9_P_2  */
10561     { "vpsubsw",        { XM, Vex, EXx } },
10562   },
10563   {
10564     /* VEX_W_0FEA_P_2  */
10565     { "vpminsw",        { XM, Vex, EXx } },
10566   },
10567   {
10568     /* VEX_W_0FEB_P_2  */
10569     { "vpor",           { XM, Vex, EXx } },
10570   },
10571   {
10572     /* VEX_W_0FEC_P_2  */
10573     { "vpaddsb",        { XM, Vex, EXx } },
10574   },
10575   {
10576     /* VEX_W_0FED_P_2  */
10577     { "vpaddsw",        { XM, Vex, EXx } },
10578   },
10579   {
10580     /* VEX_W_0FEE_P_2  */
10581     { "vpmaxsw",        { XM, Vex, EXx } },
10582   },
10583   {
10584     /* VEX_W_0FEF_P_2  */
10585     { "vpxor",          { XM, Vex, EXx } },
10586   },
10587   {
10588     /* VEX_W_0FF0_P_3_M_0 */
10589     { "vlddqu",         { XM, M } },
10590   },
10591   {
10592     /* VEX_W_0FF1_P_2 */
10593     { "vpsllw",         { XM, Vex, EXxmm } },
10594   },
10595   {
10596     /* VEX_W_0FF2_P_2 */
10597     { "vpslld",         { XM, Vex, EXxmm } },
10598   },
10599   {
10600     /* VEX_W_0FF3_P_2 */
10601     { "vpsllq",         { XM, Vex, EXxmm } },
10602   },
10603   {
10604     /* VEX_W_0FF4_P_2 */
10605     { "vpmuludq",       { XM, Vex, EXx } },
10606   },
10607   {
10608     /* VEX_W_0FF5_P_2 */
10609     { "vpmaddwd",       { XM, Vex, EXx } },
10610   },
10611   {
10612     /* VEX_W_0FF6_P_2 */
10613     { "vpsadbw",        { XM, Vex, EXx } },
10614   },
10615   {
10616     /* VEX_W_0FF7_P_2 */
10617     { "vmaskmovdqu",    { XM, XS } },
10618   },
10619   {
10620     /* VEX_W_0FF8_P_2 */
10621     { "vpsubb",         { XM, Vex, EXx } },
10622   },
10623   {
10624     /* VEX_W_0FF9_P_2 */
10625     { "vpsubw",         { XM, Vex, EXx } },
10626   },
10627   {
10628     /* VEX_W_0FFA_P_2 */
10629     { "vpsubd",         { XM, Vex, EXx } },
10630   },
10631   {
10632     /* VEX_W_0FFB_P_2 */
10633     { "vpsubq",         { XM, Vex, EXx } },
10634   },
10635   {
10636     /* VEX_W_0FFC_P_2 */
10637     { "vpaddb",         { XM, Vex, EXx } },
10638   },
10639   {
10640     /* VEX_W_0FFD_P_2 */
10641     { "vpaddw",         { XM, Vex, EXx } },
10642   },
10643   {
10644     /* VEX_W_0FFE_P_2 */
10645     { "vpaddd",         { XM, Vex, EXx } },
10646   },
10647   {
10648     /* VEX_W_0F3800_P_2  */
10649     { "vpshufb",        { XM, Vex, EXx } },
10650   },
10651   {
10652     /* VEX_W_0F3801_P_2  */
10653     { "vphaddw",        { XM, Vex, EXx } },
10654   },
10655   {
10656     /* VEX_W_0F3802_P_2  */
10657     { "vphaddd",        { XM, Vex, EXx } },
10658   },
10659   {
10660     /* VEX_W_0F3803_P_2  */
10661     { "vphaddsw",       { XM, Vex, EXx } },
10662   },
10663   {
10664     /* VEX_W_0F3804_P_2  */
10665     { "vpmaddubsw",     { XM, Vex, EXx } },
10666   },
10667   {
10668     /* VEX_W_0F3805_P_2  */
10669     { "vphsubw",        { XM, Vex, EXx } },
10670   },
10671   {
10672     /* VEX_W_0F3806_P_2  */
10673     { "vphsubd",        { XM, Vex, EXx } },
10674   },
10675   {
10676     /* VEX_W_0F3807_P_2  */
10677     { "vphsubsw",       { XM, Vex, EXx } },
10678   },
10679   {
10680     /* VEX_W_0F3808_P_2  */
10681     { "vpsignb",        { XM, Vex, EXx } },
10682   },
10683   {
10684     /* VEX_W_0F3809_P_2  */
10685     { "vpsignw",        { XM, Vex, EXx } },
10686   },
10687   {
10688     /* VEX_W_0F380A_P_2  */
10689     { "vpsignd",        { XM, Vex, EXx } },
10690   },
10691   {
10692     /* VEX_W_0F380B_P_2  */
10693     { "vpmulhrsw",      { XM, Vex, EXx } },
10694   },
10695   {
10696     /* VEX_W_0F380C_P_2  */
10697     { "vpermilps",      { XM, Vex, EXx } },
10698   },
10699   {
10700     /* VEX_W_0F380D_P_2  */
10701     { "vpermilpd",      { XM, Vex, EXx } },
10702   },
10703   {
10704     /* VEX_W_0F380E_P_2  */
10705     { "vtestps",        { XM, EXx } },
10706   },
10707   {
10708     /* VEX_W_0F380F_P_2  */
10709     { "vtestpd",        { XM, EXx } },
10710   },
10711   {
10712     /* VEX_W_0F3816_P_2  */
10713     { "vpermps",        { XM, Vex, EXx } },
10714   },
10715   {
10716     /* VEX_W_0F3817_P_2 */
10717     { "vptest",         { XM, EXx } },
10718   },
10719   {
10720     /* VEX_W_0F3818_P_2 */
10721     { "vbroadcastss",   { XM, EXxmm_md } },
10722   },
10723   {
10724     /* VEX_W_0F3819_P_2 */
10725     { "vbroadcastsd",   { XM, EXxmm_mq } },
10726   },
10727   {
10728     /* VEX_W_0F381A_P_2_M_0 */
10729     { "vbroadcastf128", { XM, Mxmm } },
10730   },
10731   {
10732     /* VEX_W_0F381C_P_2 */
10733     { "vpabsb",         { XM, EXx } },
10734   },
10735   {
10736     /* VEX_W_0F381D_P_2 */
10737     { "vpabsw",         { XM, EXx } },
10738   },
10739   {
10740     /* VEX_W_0F381E_P_2 */
10741     { "vpabsd",         { XM, EXx } },
10742   },
10743   {
10744     /* VEX_W_0F3820_P_2 */
10745     { "vpmovsxbw",      { XM, EXxmmq } },
10746   },
10747   {
10748     /* VEX_W_0F3821_P_2 */
10749     { "vpmovsxbd",      { XM, EXxmmqd } },
10750   },
10751   {
10752     /* VEX_W_0F3822_P_2 */
10753     { "vpmovsxbq",      { XM, EXxmmdw } },
10754   },
10755   {
10756     /* VEX_W_0F3823_P_2 */
10757     { "vpmovsxwd",      { XM, EXxmmq } },
10758   },
10759   {
10760     /* VEX_W_0F3824_P_2 */
10761     { "vpmovsxwq",      { XM, EXxmmqd } },
10762   },
10763   {
10764     /* VEX_W_0F3825_P_2 */
10765     { "vpmovsxdq",      { XM, EXxmmq } },
10766   },
10767   {
10768     /* VEX_W_0F3828_P_2 */
10769     { "vpmuldq",        { XM, Vex, EXx } },
10770   },
10771   {
10772     /* VEX_W_0F3829_P_2 */
10773     { "vpcmpeqq",       { XM, Vex, EXx } },
10774   },
10775   {
10776     /* VEX_W_0F382A_P_2_M_0 */
10777     { "vmovntdqa",      { XM, Mx } },
10778   },
10779   {
10780     /* VEX_W_0F382B_P_2 */
10781     { "vpackusdw",      { XM, Vex, EXx } },
10782   },
10783   {
10784     /* VEX_W_0F382C_P_2_M_0 */
10785     { "vmaskmovps",     { XM, Vex, Mx } },
10786   },
10787   {
10788     /* VEX_W_0F382D_P_2_M_0 */
10789     { "vmaskmovpd",     { XM, Vex, Mx } },
10790   },
10791   {
10792     /* VEX_W_0F382E_P_2_M_0 */
10793     { "vmaskmovps",     { Mx, Vex, XM } },
10794   },
10795   {
10796     /* VEX_W_0F382F_P_2_M_0 */
10797     { "vmaskmovpd",     { Mx, Vex, XM } },
10798   },
10799   {
10800     /* VEX_W_0F3830_P_2 */
10801     { "vpmovzxbw",      { XM, EXxmmq } },
10802   },
10803   {
10804     /* VEX_W_0F3831_P_2 */
10805     { "vpmovzxbd",      { XM, EXxmmqd } },
10806   },
10807   {
10808     /* VEX_W_0F3832_P_2 */
10809     { "vpmovzxbq",      { XM, EXxmmdw } },
10810   },
10811   {
10812     /* VEX_W_0F3833_P_2 */
10813     { "vpmovzxwd",      { XM, EXxmmq } },
10814   },
10815   {
10816     /* VEX_W_0F3834_P_2 */
10817     { "vpmovzxwq",      { XM, EXxmmqd } },
10818   },
10819   {
10820     /* VEX_W_0F3835_P_2 */
10821     { "vpmovzxdq",      { XM, EXxmmq } },
10822   },
10823   {
10824     /* VEX_W_0F3836_P_2  */
10825     { "vpermd",         { XM, Vex, EXx } },
10826   },
10827   {
10828     /* VEX_W_0F3837_P_2 */
10829     { "vpcmpgtq",       { XM, Vex, EXx } },
10830   },
10831   {
10832     /* VEX_W_0F3838_P_2 */
10833     { "vpminsb",        { XM, Vex, EXx } },
10834   },
10835   {
10836     /* VEX_W_0F3839_P_2 */
10837     { "vpminsd",        { XM, Vex, EXx } },
10838   },
10839   {
10840     /* VEX_W_0F383A_P_2 */
10841     { "vpminuw",        { XM, Vex, EXx } },
10842   },
10843   {
10844     /* VEX_W_0F383B_P_2 */
10845     { "vpminud",        { XM, Vex, EXx } },
10846   },
10847   {
10848     /* VEX_W_0F383C_P_2 */
10849     { "vpmaxsb",        { XM, Vex, EXx } },
10850   },
10851   {
10852     /* VEX_W_0F383D_P_2 */
10853     { "vpmaxsd",        { XM, Vex, EXx } },
10854   },
10855   {
10856     /* VEX_W_0F383E_P_2 */
10857     { "vpmaxuw",        { XM, Vex, EXx } },
10858   },
10859   {
10860     /* VEX_W_0F383F_P_2 */
10861     { "vpmaxud",        { XM, Vex, EXx } },
10862   },
10863   {
10864     /* VEX_W_0F3840_P_2 */
10865     { "vpmulld",        { XM, Vex, EXx } },
10866   },
10867   {
10868     /* VEX_W_0F3841_P_2 */
10869     { "vphminposuw",    { XM, EXx } },
10870   },
10871   {
10872     /* VEX_W_0F3846_P_2 */
10873     { "vpsravd",        { XM, Vex, EXx } },
10874   },
10875   {
10876     /* VEX_W_0F3858_P_2 */
10877     { "vpbroadcastd", { XM, EXxmm_md } },
10878   },
10879   {
10880     /* VEX_W_0F3859_P_2 */
10881     { "vpbroadcastq",   { XM, EXxmm_mq } },
10882   },
10883   {
10884     /* VEX_W_0F385A_P_2_M_0 */
10885     { "vbroadcasti128", { XM, Mxmm } },
10886   },
10887   {
10888     /* VEX_W_0F3878_P_2 */
10889     { "vpbroadcastb",   { XM, EXxmm_mb } },
10890   },
10891   {
10892     /* VEX_W_0F3879_P_2 */
10893     { "vpbroadcastw",   { XM, EXxmm_mw } },
10894   },
10895   {
10896     /* VEX_W_0F38DB_P_2 */
10897     { "vaesimc",        { XM, EXx } },
10898   },
10899   {
10900     /* VEX_W_0F38DC_P_2 */
10901     { "vaesenc",        { XM, Vex128, EXx } },
10902   },
10903   {
10904     /* VEX_W_0F38DD_P_2 */
10905     { "vaesenclast",    { XM, Vex128, EXx } },
10906   },
10907   {
10908     /* VEX_W_0F38DE_P_2 */
10909     { "vaesdec",        { XM, Vex128, EXx } },
10910   },
10911   {
10912     /* VEX_W_0F38DF_P_2 */
10913     { "vaesdeclast",    { XM, Vex128, EXx } },
10914   },
10915   {
10916     /* VEX_W_0F3A00_P_2 */
10917     { Bad_Opcode },
10918     { "vpermq",         { XM, EXx, Ib } },
10919   },
10920   {
10921     /* VEX_W_0F3A01_P_2 */
10922     { Bad_Opcode },
10923     { "vpermpd",        { XM, EXx, Ib } },
10924   },
10925   {
10926     /* VEX_W_0F3A02_P_2 */
10927     { "vpblendd",       { XM, Vex, EXx, Ib } },
10928   },
10929   {
10930     /* VEX_W_0F3A04_P_2 */
10931     { "vpermilps",      { XM, EXx, Ib } },
10932   },
10933   {
10934     /* VEX_W_0F3A05_P_2 */
10935     { "vpermilpd",      { XM, EXx, Ib } },
10936   },
10937   {
10938     /* VEX_W_0F3A06_P_2 */
10939     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10940   },
10941   {
10942     /* VEX_W_0F3A08_P_2 */
10943     { "vroundps",       { XM, EXx, Ib } },
10944   },
10945   {
10946     /* VEX_W_0F3A09_P_2 */
10947     { "vroundpd",       { XM, EXx, Ib } },
10948   },
10949   {
10950     /* VEX_W_0F3A0A_P_2 */
10951     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10952   },
10953   {
10954     /* VEX_W_0F3A0B_P_2 */
10955     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10956   },
10957   {
10958     /* VEX_W_0F3A0C_P_2 */
10959     { "vblendps",       { XM, Vex, EXx, Ib } },
10960   },
10961   {
10962     /* VEX_W_0F3A0D_P_2 */
10963     { "vblendpd",       { XM, Vex, EXx, Ib } },
10964   },
10965   {
10966     /* VEX_W_0F3A0E_P_2 */
10967     { "vpblendw",       { XM, Vex, EXx, Ib } },
10968   },
10969   {
10970     /* VEX_W_0F3A0F_P_2 */
10971     { "vpalignr",       { XM, Vex, EXx, Ib } },
10972   },
10973   {
10974     /* VEX_W_0F3A14_P_2 */
10975     { "vpextrb",        { Edqb, XM, Ib } },
10976   },
10977   {
10978     /* VEX_W_0F3A15_P_2 */
10979     { "vpextrw",        { Edqw, XM, Ib } },
10980   },
10981   {
10982     /* VEX_W_0F3A18_P_2 */
10983     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10984   },
10985   {
10986     /* VEX_W_0F3A19_P_2 */
10987     { "vextractf128",   { EXxmm, XM, Ib } },
10988   },
10989   {
10990     /* VEX_W_0F3A20_P_2 */
10991     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10992   },
10993   {
10994     /* VEX_W_0F3A21_P_2 */
10995     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10996   },
10997   {
10998     /* VEX_W_0F3A30_P_2 */
10999     { Bad_Opcode },
11000     { "kshiftrw",       { MaskG, MaskR, Ib } },
11001   },
11002   {
11003     /* VEX_W_0F3A32_P_2 */
11004     { Bad_Opcode },
11005     { "kshiftlw",       { MaskG, MaskR, Ib } },
11006   },
11007   {
11008     /* VEX_W_0F3A38_P_2 */
11009     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
11010   },
11011   {
11012     /* VEX_W_0F3A39_P_2 */
11013     { "vextracti128",   { EXxmm, XM, Ib } },
11014   },
11015   {
11016     /* VEX_W_0F3A40_P_2 */
11017     { "vdpps",          { XM, Vex, EXx, Ib } },
11018   },
11019   {
11020     /* VEX_W_0F3A41_P_2 */
11021     { "vdppd",          { XM, Vex128, EXx, Ib } },
11022   },
11023   {
11024     /* VEX_W_0F3A42_P_2 */
11025     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
11026   },
11027   {
11028     /* VEX_W_0F3A44_P_2 */
11029     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
11030   },
11031   {
11032     /* VEX_W_0F3A46_P_2 */
11033     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
11034   },
11035   {
11036     /* VEX_W_0F3A48_P_2 */
11037     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11038     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11039   },
11040   {
11041     /* VEX_W_0F3A49_P_2 */
11042     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11043     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11044   },
11045   {
11046     /* VEX_W_0F3A4A_P_2 */
11047     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
11048   },
11049   {
11050     /* VEX_W_0F3A4B_P_2 */
11051     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
11052   },
11053   {
11054     /* VEX_W_0F3A4C_P_2 */
11055     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
11056   },
11057   {
11058     /* VEX_W_0F3A60_P_2 */
11059     { "vpcmpestrm",     { XM, EXx, Ib } },
11060   },
11061   {
11062     /* VEX_W_0F3A61_P_2 */
11063     { "vpcmpestri",     { XM, EXx, Ib } },
11064   },
11065   {
11066     /* VEX_W_0F3A62_P_2 */
11067     { "vpcmpistrm",     { XM, EXx, Ib } },
11068   },
11069   {
11070     /* VEX_W_0F3A63_P_2 */
11071     { "vpcmpistri",     { XM, EXx, Ib } },
11072   },
11073   {
11074     /* VEX_W_0F3ADF_P_2 */
11075     { "vaeskeygenassist", { XM, EXx, Ib } },
11076   },
11077 #define NEED_VEX_W_TABLE
11078 #include "i386-dis-evex.h"
11079 #undef NEED_VEX_W_TABLE
11080 };
11081
11082 static const struct dis386 mod_table[][2] = {
11083   {
11084     /* MOD_8D */
11085     { "leaS",           { Gv, M } },
11086   },
11087   {
11088     /* MOD_C6_REG_7 */
11089     { Bad_Opcode },
11090     { RM_TABLE (RM_C6_REG_7) },
11091   },
11092   {
11093     /* MOD_C7_REG_7 */
11094     { Bad_Opcode },
11095     { RM_TABLE (RM_C7_REG_7) },
11096   },
11097   {
11098     /* MOD_FF_REG_3 */
11099     { "Jcall{T|}", { indirEp } },
11100   },
11101   {
11102     /* MOD_FF_REG_5 */
11103     { "Jjmp{T|}", { indirEp } },
11104   },
11105   {
11106     /* MOD_0F01_REG_0 */
11107     { X86_64_TABLE (X86_64_0F01_REG_0) },
11108     { RM_TABLE (RM_0F01_REG_0) },
11109   },
11110   {
11111     /* MOD_0F01_REG_1 */
11112     { X86_64_TABLE (X86_64_0F01_REG_1) },
11113     { RM_TABLE (RM_0F01_REG_1) },
11114   },
11115   {
11116     /* MOD_0F01_REG_2 */
11117     { X86_64_TABLE (X86_64_0F01_REG_2) },
11118     { RM_TABLE (RM_0F01_REG_2) },
11119   },
11120   {
11121     /* MOD_0F01_REG_3 */
11122     { X86_64_TABLE (X86_64_0F01_REG_3) },
11123     { RM_TABLE (RM_0F01_REG_3) },
11124   },
11125   {
11126     /* MOD_0F01_REG_7 */
11127     { "invlpg",         { Mb } },
11128     { RM_TABLE (RM_0F01_REG_7) },
11129   },
11130   {
11131     /* MOD_0F12_PREFIX_0 */
11132     { "movlps",         { XM, EXq } },
11133     { "movhlps",        { XM, EXq } },
11134   },
11135   {
11136     /* MOD_0F13 */
11137     { "movlpX",         { EXq, XM } },
11138   },
11139   {
11140     /* MOD_0F16_PREFIX_0 */
11141     { "movhps",         { XM, EXq } },
11142     { "movlhps",        { XM, EXq } },
11143   },
11144   {
11145     /* MOD_0F17 */
11146     { "movhpX",         { EXq, XM } },
11147   },
11148   {
11149     /* MOD_0F18_REG_0 */
11150     { "prefetchnta",    { Mb } },
11151   },
11152   {
11153     /* MOD_0F18_REG_1 */
11154     { "prefetcht0",     { Mb } },
11155   },
11156   {
11157     /* MOD_0F18_REG_2 */
11158     { "prefetcht1",     { Mb } },
11159   },
11160   {
11161     /* MOD_0F18_REG_3 */
11162     { "prefetcht2",     { Mb } },
11163   },
11164   {
11165     /* MOD_0F18_REG_4 */
11166     { "nop/reserved",   { Mb } },
11167   },
11168   {
11169     /* MOD_0F18_REG_5 */
11170     { "nop/reserved",   { Mb } },
11171   },
11172   {
11173     /* MOD_0F18_REG_6 */
11174     { "nop/reserved",   { Mb } },
11175   },
11176   {
11177     /* MOD_0F18_REG_7 */
11178     { "nop/reserved",   { Mb } },
11179   },
11180   {
11181     /* MOD_0F1A_PREFIX_0 */
11182     { "bndldx",         { Gbnd, Ev_bnd } },
11183     { "nopQ",           { Ev } },
11184   },
11185   {
11186     /* MOD_0F1B_PREFIX_0 */
11187     { "bndstx",         { Ev_bnd, Gbnd } },
11188     { "nopQ",           { Ev } },
11189   },
11190   {
11191     /* MOD_0F1B_PREFIX_1 */
11192     { "bndmk",          { Gbnd, Ev_bnd } },
11193     { "nopQ",           { Ev } },
11194   },
11195   {
11196     /* MOD_0F20 */
11197     { Bad_Opcode },
11198     { "movZ",           { Rm, Cm } },
11199   },
11200   {
11201     /* MOD_0F21 */
11202     { Bad_Opcode },
11203     { "movZ",           { Rm, Dm } },
11204   },
11205   {
11206     /* MOD_0F22 */
11207     { Bad_Opcode },
11208     { "movZ",           { Cm, Rm } },
11209   },
11210   {
11211     /* MOD_0F23 */
11212     { Bad_Opcode },
11213     { "movZ",           { Dm, Rm } },
11214   },
11215   {
11216     /* MOD_0F24 */
11217     { Bad_Opcode },
11218     { "movL",           { Rd, Td } },
11219   },
11220   {
11221     /* MOD_0F26 */
11222     { Bad_Opcode },
11223     { "movL",           { Td, Rd } },
11224   },
11225   {
11226     /* MOD_0F2B_PREFIX_0 */
11227     {"movntps",         { Mx, XM } },
11228   },
11229   {
11230     /* MOD_0F2B_PREFIX_1 */
11231     {"movntss",         { Md, XM } },
11232   },
11233   {
11234     /* MOD_0F2B_PREFIX_2 */
11235     {"movntpd",         { Mx, XM } },
11236   },
11237   {
11238     /* MOD_0F2B_PREFIX_3 */
11239     {"movntsd",         { Mq, XM } },
11240   },
11241   {
11242     /* MOD_0F51 */
11243     { Bad_Opcode },
11244     { "movmskpX",       { Gdq, XS } },
11245   },
11246   {
11247     /* MOD_0F71_REG_2 */
11248     { Bad_Opcode },
11249     { "psrlw",          { MS, Ib } },
11250   },
11251   {
11252     /* MOD_0F71_REG_4 */
11253     { Bad_Opcode },
11254     { "psraw",          { MS, Ib } },
11255   },
11256   {
11257     /* MOD_0F71_REG_6 */
11258     { Bad_Opcode },
11259     { "psllw",          { MS, Ib } },
11260   },
11261   {
11262     /* MOD_0F72_REG_2 */
11263     { Bad_Opcode },
11264     { "psrld",          { MS, Ib } },
11265   },
11266   {
11267     /* MOD_0F72_REG_4 */
11268     { Bad_Opcode },
11269     { "psrad",          { MS, Ib } },
11270   },
11271   {
11272     /* MOD_0F72_REG_6 */
11273     { Bad_Opcode },
11274     { "pslld",          { MS, Ib } },
11275   },
11276   {
11277     /* MOD_0F73_REG_2 */
11278     { Bad_Opcode },
11279     { "psrlq",          { MS, Ib } },
11280   },
11281   {
11282     /* MOD_0F73_REG_3 */
11283     { Bad_Opcode },
11284     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11285   },
11286   {
11287     /* MOD_0F73_REG_6 */
11288     { Bad_Opcode },
11289     { "psllq",          { MS, Ib } },
11290   },
11291   {
11292     /* MOD_0F73_REG_7 */
11293     { Bad_Opcode },
11294     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11295   },
11296   {
11297     /* MOD_0FAE_REG_0 */
11298     { "fxsave",         { FXSAVE } },
11299     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11300   },
11301   {
11302     /* MOD_0FAE_REG_1 */
11303     { "fxrstor",        { FXSAVE } },
11304     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11305   },
11306   {
11307     /* MOD_0FAE_REG_2 */
11308     { "ldmxcsr",        { Md } },
11309     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11310   },
11311   {
11312     /* MOD_0FAE_REG_3 */
11313     { "stmxcsr",        { Md } },
11314     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11315   },
11316   {
11317     /* MOD_0FAE_REG_4 */
11318     { "xsave",          { FXSAVE } },
11319   },
11320   {
11321     /* MOD_0FAE_REG_5 */
11322     { "xrstor",         { FXSAVE } },
11323     { RM_TABLE (RM_0FAE_REG_5) },
11324   },
11325   {
11326     /* MOD_0FAE_REG_6 */
11327     { "xsaveopt",       { FXSAVE } },
11328     { RM_TABLE (RM_0FAE_REG_6) },
11329   },
11330   {
11331     /* MOD_0FAE_REG_7 */
11332     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11333     { RM_TABLE (RM_0FAE_REG_7) },
11334   },
11335   {
11336     /* MOD_0FB2 */
11337     { "lssS",           { Gv, Mp } },
11338   },
11339   {
11340     /* MOD_0FB4 */
11341     { "lfsS",           { Gv, Mp } },
11342   },
11343   {
11344     /* MOD_0FB5 */
11345     { "lgsS",           { Gv, Mp } },
11346   },
11347   {
11348     /* MOD_0FC7_REG_3 */
11349     { "xrstors",                { FXSAVE } },
11350   },
11351   {
11352     /* MOD_0FC7_REG_4 */
11353     { "xsavec",         { FXSAVE } },
11354   },
11355   {
11356     /* MOD_0FC7_REG_5 */
11357     { "xsaves",         { FXSAVE } },
11358   },
11359   {
11360     /* MOD_0FC7_REG_6 */
11361     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11362     { "rdrand",         { Ev } },
11363   },
11364   {
11365     /* MOD_0FC7_REG_7 */
11366     { "vmptrst",        { Mq } },
11367     { "rdseed",         { Ev } },
11368   },
11369   {
11370     /* MOD_0FD7 */
11371     { Bad_Opcode },
11372     { "pmovmskb",       { Gdq, MS } },
11373   },
11374   {
11375     /* MOD_0FE7_PREFIX_2 */
11376     { "movntdq",        { Mx, XM } },
11377   },
11378   {
11379     /* MOD_0FF0_PREFIX_3 */
11380     { "lddqu",          { XM, M } },
11381   },
11382   {
11383     /* MOD_0F382A_PREFIX_2 */
11384     { "movntdqa",       { XM, Mx } },
11385   },
11386   {
11387     /* MOD_62_32BIT */
11388     { "bound{S|}",      { Gv, Ma } },
11389     { EVEX_TABLE (EVEX_0F) },
11390   },
11391   {
11392     /* MOD_C4_32BIT */
11393     { "lesS",           { Gv, Mp } },
11394     { VEX_C4_TABLE (VEX_0F) },
11395   },
11396   {
11397     /* MOD_C5_32BIT */
11398     { "ldsS",           { Gv, Mp } },
11399     { VEX_C5_TABLE (VEX_0F) },
11400   },
11401   {
11402     /* MOD_VEX_0F12_PREFIX_0 */
11403     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11404     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11405   },
11406   {
11407     /* MOD_VEX_0F13 */
11408     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11409   },
11410   {
11411     /* MOD_VEX_0F16_PREFIX_0 */
11412     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11413     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11414   },
11415   {
11416     /* MOD_VEX_0F17 */
11417     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11418   },
11419   {
11420     /* MOD_VEX_0F2B */
11421     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11422   },
11423   {
11424     /* MOD_VEX_0F50 */
11425     { Bad_Opcode },
11426     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11427   },
11428   {
11429     /* MOD_VEX_0F71_REG_2 */
11430     { Bad_Opcode },
11431     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11432   },
11433   {
11434     /* MOD_VEX_0F71_REG_4 */
11435     { Bad_Opcode },
11436     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11437   },
11438   {
11439     /* MOD_VEX_0F71_REG_6 */
11440     { Bad_Opcode },
11441     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11442   },
11443   {
11444     /* MOD_VEX_0F72_REG_2 */
11445     { Bad_Opcode },
11446     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11447   },
11448   {
11449     /* MOD_VEX_0F72_REG_4 */
11450     { Bad_Opcode },
11451     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11452   },
11453   {
11454     /* MOD_VEX_0F72_REG_6 */
11455     { Bad_Opcode },
11456     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11457   },
11458   {
11459     /* MOD_VEX_0F73_REG_2 */
11460     { Bad_Opcode },
11461     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11462   },
11463   {
11464     /* MOD_VEX_0F73_REG_3 */
11465     { Bad_Opcode },
11466     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11467   },
11468   {
11469     /* MOD_VEX_0F73_REG_6 */
11470     { Bad_Opcode },
11471     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11472   },
11473   {
11474     /* MOD_VEX_0F73_REG_7 */
11475     { Bad_Opcode },
11476     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11477   },
11478   {
11479     /* MOD_VEX_0FAE_REG_2 */
11480     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11481   },
11482   {
11483     /* MOD_VEX_0FAE_REG_3 */
11484     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11485   },
11486   {
11487     /* MOD_VEX_0FD7_PREFIX_2 */
11488     { Bad_Opcode },
11489     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11490   },
11491   {
11492     /* MOD_VEX_0FE7_PREFIX_2 */
11493     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11494   },
11495   {
11496     /* MOD_VEX_0FF0_PREFIX_3 */
11497     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11498   },
11499   {
11500     /* MOD_VEX_0F381A_PREFIX_2 */
11501     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11502   },
11503   {
11504     /* MOD_VEX_0F382A_PREFIX_2 */
11505     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11506   },
11507   {
11508     /* MOD_VEX_0F382C_PREFIX_2 */
11509     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11510   },
11511   {
11512     /* MOD_VEX_0F382D_PREFIX_2 */
11513     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11514   },
11515   {
11516     /* MOD_VEX_0F382E_PREFIX_2 */
11517     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11518   },
11519   {
11520     /* MOD_VEX_0F382F_PREFIX_2 */
11521     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11522   },
11523   {
11524     /* MOD_VEX_0F385A_PREFIX_2 */
11525     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11526   },
11527   {
11528     /* MOD_VEX_0F388C_PREFIX_2 */
11529     { "vpmaskmov%LW",   { XM, Vex, Mx } },
11530   },
11531   {
11532     /* MOD_VEX_0F388E_PREFIX_2 */
11533     { "vpmaskmov%LW",   { Mx, Vex, XM } },
11534   },
11535 #define NEED_MOD_TABLE
11536 #include "i386-dis-evex.h"
11537 #undef NEED_MOD_TABLE
11538 };
11539
11540 static const struct dis386 rm_table[][8] = {
11541   {
11542     /* RM_C6_REG_7 */
11543     { "xabort",         { Skip_MODRM, Ib } },
11544   },
11545   {
11546     /* RM_C7_REG_7 */
11547     { "xbeginT",        { Skip_MODRM, Jv } },
11548   },
11549   {
11550     /* RM_0F01_REG_0 */
11551     { Bad_Opcode },
11552     { "vmcall",         { Skip_MODRM } },
11553     { "vmlaunch",       { Skip_MODRM } },
11554     { "vmresume",       { Skip_MODRM } },
11555     { "vmxoff",         { Skip_MODRM } },
11556   },
11557   {
11558     /* RM_0F01_REG_1 */
11559     { "monitor",        { { OP_Monitor, 0 } } },
11560     { "mwait",          { { OP_Mwait, 0 } } },
11561     { "clac",           { Skip_MODRM } },
11562     { "stac",           { Skip_MODRM } },
11563     { Bad_Opcode },
11564     { Bad_Opcode },
11565     { Bad_Opcode },
11566     { "encls",          { Skip_MODRM } },
11567   },
11568   {
11569     /* RM_0F01_REG_2 */
11570     { "xgetbv",         { Skip_MODRM } },
11571     { "xsetbv",         { Skip_MODRM } },
11572     { Bad_Opcode },
11573     { Bad_Opcode },
11574     { "vmfunc",         { Skip_MODRM } },
11575     { "xend",           { Skip_MODRM } },
11576     { "xtest",          { Skip_MODRM } },
11577     { "enclu",          { Skip_MODRM } },
11578   },
11579   {
11580     /* RM_0F01_REG_3 */
11581     { "vmrun",          { Skip_MODRM } },
11582     { "vmmcall",        { Skip_MODRM } },
11583     { "vmload",         { Skip_MODRM } },
11584     { "vmsave",         { Skip_MODRM } },
11585     { "stgi",           { Skip_MODRM } },
11586     { "clgi",           { Skip_MODRM } },
11587     { "skinit",         { Skip_MODRM } },
11588     { "invlpga",        { Skip_MODRM } },
11589   },
11590   {
11591     /* RM_0F01_REG_7 */
11592     { "swapgs",         { Skip_MODRM } },
11593     { "rdtscp",         { Skip_MODRM } },
11594   },
11595   {
11596     /* RM_0FAE_REG_5 */
11597     { "lfence",         { Skip_MODRM } },
11598   },
11599   {
11600     /* RM_0FAE_REG_6 */
11601     { "mfence",         { Skip_MODRM } },
11602   },
11603   {
11604     /* RM_0FAE_REG_7 */
11605     { "sfence",         { Skip_MODRM } },
11606   },
11607 };
11608
11609 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11610
11611 /* We use the high bit to indicate different name for the same
11612    prefix.  */
11613 #define ADDR16_PREFIX   (0x67 | 0x100)
11614 #define ADDR32_PREFIX   (0x67 | 0x200)
11615 #define DATA16_PREFIX   (0x66 | 0x100)
11616 #define DATA32_PREFIX   (0x66 | 0x200)
11617 #define REP_PREFIX      (0xf3 | 0x100)
11618 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11619 #define XRELEASE_PREFIX (0xf3 | 0x400)
11620 #define BND_PREFIX      (0xf2 | 0x400)
11621
11622 static int
11623 ckprefix (void)
11624 {
11625   int newrex, i, length;
11626   rex = 0;
11627   rex_ignored = 0;
11628   prefixes = 0;
11629   used_prefixes = 0;
11630   rex_used = 0;
11631   last_lock_prefix = -1;
11632   last_repz_prefix = -1;
11633   last_repnz_prefix = -1;
11634   last_data_prefix = -1;
11635   last_addr_prefix = -1;
11636   last_rex_prefix = -1;
11637   last_seg_prefix = -1;
11638   active_seg_prefix = 0;
11639   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11640     all_prefixes[i] = 0;
11641   i = 0;
11642   length = 0;
11643   /* The maximum instruction length is 15bytes.  */
11644   while (length < MAX_CODE_LENGTH - 1)
11645     {
11646       FETCH_DATA (the_info, codep + 1);
11647       newrex = 0;
11648       switch (*codep)
11649         {
11650         /* REX prefixes family.  */
11651         case 0x40:
11652         case 0x41:
11653         case 0x42:
11654         case 0x43:
11655         case 0x44:
11656         case 0x45:
11657         case 0x46:
11658         case 0x47:
11659         case 0x48:
11660         case 0x49:
11661         case 0x4a:
11662         case 0x4b:
11663         case 0x4c:
11664         case 0x4d:
11665         case 0x4e:
11666         case 0x4f:
11667           if (address_mode == mode_64bit)
11668             newrex = *codep;
11669           else
11670             return 1;
11671           last_rex_prefix = i;
11672           break;
11673         case 0xf3:
11674           prefixes |= PREFIX_REPZ;
11675           last_repz_prefix = i;
11676           break;
11677         case 0xf2:
11678           prefixes |= PREFIX_REPNZ;
11679           last_repnz_prefix = i;
11680           break;
11681         case 0xf0:
11682           prefixes |= PREFIX_LOCK;
11683           last_lock_prefix = i;
11684           break;
11685         case 0x2e:
11686           prefixes |= PREFIX_CS;
11687           last_seg_prefix = i;
11688           active_seg_prefix = PREFIX_CS;
11689           break;
11690         case 0x36:
11691           prefixes |= PREFIX_SS;
11692           last_seg_prefix = i;
11693           active_seg_prefix = PREFIX_SS;
11694           break;
11695         case 0x3e:
11696           prefixes |= PREFIX_DS;
11697           last_seg_prefix = i;
11698           active_seg_prefix = PREFIX_DS;
11699           break;
11700         case 0x26:
11701           prefixes |= PREFIX_ES;
11702           last_seg_prefix = i;
11703           active_seg_prefix = PREFIX_ES;
11704           break;
11705         case 0x64:
11706           prefixes |= PREFIX_FS;
11707           last_seg_prefix = i;
11708           active_seg_prefix = PREFIX_FS;
11709           break;
11710         case 0x65:
11711           prefixes |= PREFIX_GS;
11712           last_seg_prefix = i;
11713           active_seg_prefix = PREFIX_GS;
11714           break;
11715         case 0x66:
11716           prefixes |= PREFIX_DATA;
11717           last_data_prefix = i;
11718           break;
11719         case 0x67:
11720           prefixes |= PREFIX_ADDR;
11721           last_addr_prefix = i;
11722           break;
11723         case FWAIT_OPCODE:
11724           /* fwait is really an instruction.  If there are prefixes
11725              before the fwait, they belong to the fwait, *not* to the
11726              following instruction.  */
11727           if (prefixes || rex)
11728             {
11729               prefixes |= PREFIX_FWAIT;
11730               codep++;
11731               /* This ensures that the previous REX prefixes are noticed
11732                  as unused prefixes, as in the return case below.  */
11733               rex_used = rex;
11734               return 1;
11735             }
11736           prefixes = PREFIX_FWAIT;
11737           break;
11738         default:
11739           return 1;
11740         }
11741       /* Rex is ignored when followed by another prefix.  */
11742       if (rex)
11743         {
11744           rex_used = rex;
11745           return 1;
11746         }
11747       if (*codep != FWAIT_OPCODE)
11748         all_prefixes[i++] = *codep;
11749       rex = newrex;
11750       codep++;
11751       length++;
11752     }
11753   return 0;
11754 }
11755
11756 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11757    prefix byte.  */
11758
11759 static const char *
11760 prefix_name (int pref, int sizeflag)
11761 {
11762   static const char *rexes [16] =
11763     {
11764       "rex",            /* 0x40 */
11765       "rex.B",          /* 0x41 */
11766       "rex.X",          /* 0x42 */
11767       "rex.XB",         /* 0x43 */
11768       "rex.R",          /* 0x44 */
11769       "rex.RB",         /* 0x45 */
11770       "rex.RX",         /* 0x46 */
11771       "rex.RXB",        /* 0x47 */
11772       "rex.W",          /* 0x48 */
11773       "rex.WB",         /* 0x49 */
11774       "rex.WX",         /* 0x4a */
11775       "rex.WXB",        /* 0x4b */
11776       "rex.WR",         /* 0x4c */
11777       "rex.WRB",        /* 0x4d */
11778       "rex.WRX",        /* 0x4e */
11779       "rex.WRXB",       /* 0x4f */
11780     };
11781
11782   switch (pref)
11783     {
11784     /* REX prefixes family.  */
11785     case 0x40:
11786     case 0x41:
11787     case 0x42:
11788     case 0x43:
11789     case 0x44:
11790     case 0x45:
11791     case 0x46:
11792     case 0x47:
11793     case 0x48:
11794     case 0x49:
11795     case 0x4a:
11796     case 0x4b:
11797     case 0x4c:
11798     case 0x4d:
11799     case 0x4e:
11800     case 0x4f:
11801       return rexes [pref - 0x40];
11802     case 0xf3:
11803       return "repz";
11804     case 0xf2:
11805       return "repnz";
11806     case 0xf0:
11807       return "lock";
11808     case 0x2e:
11809       return "cs";
11810     case 0x36:
11811       return "ss";
11812     case 0x3e:
11813       return "ds";
11814     case 0x26:
11815       return "es";
11816     case 0x64:
11817       return "fs";
11818     case 0x65:
11819       return "gs";
11820     case 0x66:
11821       return (sizeflag & DFLAG) ? "data16" : "data32";
11822     case 0x67:
11823       if (address_mode == mode_64bit)
11824         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11825       else
11826         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11827     case FWAIT_OPCODE:
11828       return "fwait";
11829     case ADDR16_PREFIX:
11830       return "addr16";
11831     case ADDR32_PREFIX:
11832       return "addr32";
11833     case DATA16_PREFIX:
11834       return "data16";
11835     case DATA32_PREFIX:
11836       return "data32";
11837     case REP_PREFIX:
11838       return "rep";
11839     case XACQUIRE_PREFIX:
11840       return "xacquire";
11841     case XRELEASE_PREFIX:
11842       return "xrelease";
11843     case BND_PREFIX:
11844       return "bnd";
11845     default:
11846       return NULL;
11847     }
11848 }
11849
11850 static char op_out[MAX_OPERANDS][100];
11851 static int op_ad, op_index[MAX_OPERANDS];
11852 static int two_source_ops;
11853 static bfd_vma op_address[MAX_OPERANDS];
11854 static bfd_vma op_riprel[MAX_OPERANDS];
11855 static bfd_vma start_pc;
11856
11857 /*
11858  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11859  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11860  *   section of the "Virtual 8086 Mode" chapter.)
11861  * 'pc' should be the address of this instruction, it will
11862  *   be used to print the target address if this is a relative jump or call
11863  * The function returns the length of this instruction in bytes.
11864  */
11865
11866 static char intel_syntax;
11867 static char intel_mnemonic = !SYSV386_COMPAT;
11868 static char open_char;
11869 static char close_char;
11870 static char separator_char;
11871 static char scale_char;
11872
11873 /* Here for backwards compatibility.  When gdb stops using
11874    print_insn_i386_att and print_insn_i386_intel these functions can
11875    disappear, and print_insn_i386 be merged into print_insn.  */
11876 int
11877 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11878 {
11879   intel_syntax = 0;
11880
11881   return print_insn (pc, info);
11882 }
11883
11884 int
11885 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11886 {
11887   intel_syntax = 1;
11888
11889   return print_insn (pc, info);
11890 }
11891
11892 int
11893 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11894 {
11895   intel_syntax = -1;
11896
11897   return print_insn (pc, info);
11898 }
11899
11900 void
11901 print_i386_disassembler_options (FILE *stream)
11902 {
11903   fprintf (stream, _("\n\
11904 The following i386/x86-64 specific disassembler options are supported for use\n\
11905 with the -M switch (multiple options should be separated by commas):\n"));
11906
11907   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11908   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11909   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11910   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11911   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11912   fprintf (stream, _("  att-mnemonic\n"
11913                      "              Display instruction in AT&T mnemonic\n"));
11914   fprintf (stream, _("  intel-mnemonic\n"
11915                      "              Display instruction in Intel mnemonic\n"));
11916   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11917   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11918   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11919   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11920   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11921   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11922 }
11923
11924 /* Bad opcode.  */
11925 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11926
11927 /* Get a pointer to struct dis386 with a valid name.  */
11928
11929 static const struct dis386 *
11930 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11931 {
11932   int vindex, vex_table_index;
11933
11934   if (dp->name != NULL)
11935     return dp;
11936
11937   switch (dp->op[0].bytemode)
11938     {
11939     case USE_REG_TABLE:
11940       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11941       break;
11942
11943     case USE_MOD_TABLE:
11944       vindex = modrm.mod == 0x3 ? 1 : 0;
11945       dp = &mod_table[dp->op[1].bytemode][vindex];
11946       break;
11947
11948     case USE_RM_TABLE:
11949       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11950       break;
11951
11952     case USE_PREFIX_TABLE:
11953       if (need_vex)
11954         {
11955           /* The prefix in VEX is implicit.  */
11956           switch (vex.prefix)
11957             {
11958             case 0:
11959               vindex = 0;
11960               break;
11961             case REPE_PREFIX_OPCODE:
11962               vindex = 1;
11963               break;
11964             case DATA_PREFIX_OPCODE:
11965               vindex = 2;
11966               break;
11967             case REPNE_PREFIX_OPCODE:
11968               vindex = 3;
11969               break;
11970             default:
11971               abort ();
11972               break;
11973             }
11974         }
11975       else
11976         {
11977           int last_prefix = -1;
11978           int prefix = 0;
11979           vindex = 0;
11980           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11981              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11982              last one wins.  */
11983           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11984             {
11985               if (last_repz_prefix > last_repnz_prefix)
11986                 {
11987                   vindex = 1;
11988                   prefix = PREFIX_REPZ;
11989                   last_prefix = last_repz_prefix;
11990                 }
11991               else
11992                 {
11993                   vindex = 3;
11994                   prefix = PREFIX_REPNZ;
11995                   last_prefix = last_repnz_prefix;
11996                 }
11997
11998               /* Ignore the invalid index if it isn't mandatory.  */
11999               if (!mandatory_prefix
12000                   && (prefix_table[dp->op[1].bytemode][vindex].name
12001                       == NULL)
12002                   && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
12003                       == 0))
12004                 vindex = 0;
12005             }
12006
12007           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12008             {
12009               vindex = 2;
12010               prefix = PREFIX_DATA;
12011               last_prefix = last_data_prefix;
12012             }
12013
12014           if (vindex != 0)
12015             {
12016               used_prefixes |= prefix;
12017               all_prefixes[last_prefix] = 0;
12018             }
12019         }
12020       dp = &prefix_table[dp->op[1].bytemode][vindex];
12021       break;
12022
12023     case USE_X86_64_TABLE:
12024       vindex = address_mode == mode_64bit ? 1 : 0;
12025       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12026       break;
12027
12028     case USE_3BYTE_TABLE:
12029       FETCH_DATA (info, codep + 2);
12030       vindex = *codep++;
12031       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12032       end_codep = codep;
12033       modrm.mod = (*codep >> 6) & 3;
12034       modrm.reg = (*codep >> 3) & 7;
12035       modrm.rm = *codep & 7;
12036       break;
12037
12038     case USE_VEX_LEN_TABLE:
12039       if (!need_vex)
12040         abort ();
12041
12042       switch (vex.length)
12043         {
12044         case 128:
12045           vindex = 0;
12046           break;
12047         case 256:
12048           vindex = 1;
12049           break;
12050         default:
12051           abort ();
12052           break;
12053         }
12054
12055       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12056       break;
12057
12058     case USE_XOP_8F_TABLE:
12059       FETCH_DATA (info, codep + 3);
12060       /* All bits in the REX prefix are ignored.  */
12061       rex_ignored = rex;
12062       rex = ~(*codep >> 5) & 0x7;
12063
12064       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12065       switch ((*codep & 0x1f))
12066         {
12067         default:
12068           dp = &bad_opcode;
12069           return dp;
12070         case 0x8:
12071           vex_table_index = XOP_08;
12072           break;
12073         case 0x9:
12074           vex_table_index = XOP_09;
12075           break;
12076         case 0xa:
12077           vex_table_index = XOP_0A;
12078           break;
12079         }
12080       codep++;
12081       vex.w = *codep & 0x80;
12082       if (vex.w && address_mode == mode_64bit)
12083         rex |= REX_W;
12084
12085       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12086       if (address_mode != mode_64bit
12087           && vex.register_specifier > 0x7)
12088         {
12089           dp = &bad_opcode;
12090           return dp;
12091         }
12092
12093       vex.length = (*codep & 0x4) ? 256 : 128;
12094       switch ((*codep & 0x3))
12095         {
12096         case 0:
12097           vex.prefix = 0;
12098           break;
12099         case 1:
12100           vex.prefix = DATA_PREFIX_OPCODE;
12101           break;
12102         case 2:
12103           vex.prefix = REPE_PREFIX_OPCODE;
12104           break;
12105         case 3:
12106           vex.prefix = REPNE_PREFIX_OPCODE;
12107           break;
12108         }
12109       need_vex = 1;
12110       need_vex_reg = 1;
12111       codep++;
12112       vindex = *codep++;
12113       dp = &xop_table[vex_table_index][vindex];
12114
12115       end_codep = codep;
12116       FETCH_DATA (info, codep + 1);
12117       modrm.mod = (*codep >> 6) & 3;
12118       modrm.reg = (*codep >> 3) & 7;
12119       modrm.rm = *codep & 7;
12120       break;
12121
12122     case USE_VEX_C4_TABLE:
12123       /* VEX prefix.  */
12124       FETCH_DATA (info, codep + 3);
12125       /* All bits in the REX prefix are ignored.  */
12126       rex_ignored = rex;
12127       rex = ~(*codep >> 5) & 0x7;
12128       switch ((*codep & 0x1f))
12129         {
12130         default:
12131           dp = &bad_opcode;
12132           return dp;
12133         case 0x1:
12134           vex_table_index = VEX_0F;
12135           break;
12136         case 0x2:
12137           vex_table_index = VEX_0F38;
12138           break;
12139         case 0x3:
12140           vex_table_index = VEX_0F3A;
12141           break;
12142         }
12143       codep++;
12144       vex.w = *codep & 0x80;
12145       if (vex.w && address_mode == mode_64bit)
12146         rex |= REX_W;
12147
12148       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12149       if (address_mode != mode_64bit
12150           && vex.register_specifier > 0x7)
12151         {
12152           dp = &bad_opcode;
12153           return dp;
12154         }
12155
12156       vex.length = (*codep & 0x4) ? 256 : 128;
12157       switch ((*codep & 0x3))
12158         {
12159         case 0:
12160           vex.prefix = 0;
12161           break;
12162         case 1:
12163           vex.prefix = DATA_PREFIX_OPCODE;
12164           break;
12165         case 2:
12166           vex.prefix = REPE_PREFIX_OPCODE;
12167           break;
12168         case 3:
12169           vex.prefix = REPNE_PREFIX_OPCODE;
12170           break;
12171         }
12172       need_vex = 1;
12173       need_vex_reg = 1;
12174       codep++;
12175       vindex = *codep++;
12176       dp = &vex_table[vex_table_index][vindex];
12177       end_codep = codep;
12178       /* There is no MODRM byte for VEX [82|77].  */
12179       if (vindex != 0x77 && vindex != 0x82)
12180         {
12181           FETCH_DATA (info, codep + 1);
12182           modrm.mod = (*codep >> 6) & 3;
12183           modrm.reg = (*codep >> 3) & 7;
12184           modrm.rm = *codep & 7;
12185         }
12186       break;
12187
12188     case USE_VEX_C5_TABLE:
12189       /* VEX prefix.  */
12190       FETCH_DATA (info, codep + 2);
12191       /* All bits in the REX prefix are ignored.  */
12192       rex_ignored = rex;
12193       rex = (*codep & 0x80) ? 0 : REX_R;
12194
12195       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12196       if (address_mode != mode_64bit
12197           && vex.register_specifier > 0x7)
12198         {
12199           dp = &bad_opcode;
12200           return dp;
12201         }
12202
12203       vex.w = 0;
12204
12205       vex.length = (*codep & 0x4) ? 256 : 128;
12206       switch ((*codep & 0x3))
12207         {
12208         case 0:
12209           vex.prefix = 0;
12210           break;
12211         case 1:
12212           vex.prefix = DATA_PREFIX_OPCODE;
12213           break;
12214         case 2:
12215           vex.prefix = REPE_PREFIX_OPCODE;
12216           break;
12217         case 3:
12218           vex.prefix = REPNE_PREFIX_OPCODE;
12219           break;
12220         }
12221       need_vex = 1;
12222       need_vex_reg = 1;
12223       codep++;
12224       vindex = *codep++;
12225       dp = &vex_table[dp->op[1].bytemode][vindex];
12226       end_codep = codep;
12227       /* There is no MODRM byte for VEX [82|77].  */
12228       if (vindex != 0x77 && vindex != 0x82)
12229         {
12230           FETCH_DATA (info, codep + 1);
12231           modrm.mod = (*codep >> 6) & 3;
12232           modrm.reg = (*codep >> 3) & 7;
12233           modrm.rm = *codep & 7;
12234         }
12235       break;
12236
12237     case USE_VEX_W_TABLE:
12238       if (!need_vex)
12239         abort ();
12240
12241       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12242       break;
12243
12244     case USE_EVEX_TABLE:
12245       two_source_ops = 0;
12246       /* EVEX prefix.  */
12247       vex.evex = 1;
12248       FETCH_DATA (info, codep + 4);
12249       /* All bits in the REX prefix are ignored.  */
12250       rex_ignored = rex;
12251       /* The first byte after 0x62.  */
12252       rex = ~(*codep >> 5) & 0x7;
12253       vex.r = *codep & 0x10;
12254       switch ((*codep & 0xf))
12255         {
12256         default:
12257           return &bad_opcode;
12258         case 0x1:
12259           vex_table_index = EVEX_0F;
12260           break;
12261         case 0x2:
12262           vex_table_index = EVEX_0F38;
12263           break;
12264         case 0x3:
12265           vex_table_index = EVEX_0F3A;
12266           break;
12267         }
12268
12269       /* The second byte after 0x62.  */
12270       codep++;
12271       vex.w = *codep & 0x80;
12272       if (vex.w && address_mode == mode_64bit)
12273         rex |= REX_W;
12274
12275       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12276       if (address_mode != mode_64bit)
12277         {
12278           /* In 16/32-bit mode silently ignore following bits.  */
12279           rex &= ~REX_B;
12280           vex.r = 1;
12281           vex.v = 1;
12282           vex.register_specifier &= 0x7;
12283         }
12284
12285       /* The U bit.  */
12286       if (!(*codep & 0x4))
12287         return &bad_opcode;
12288
12289       switch ((*codep & 0x3))
12290         {
12291         case 0:
12292           vex.prefix = 0;
12293           break;
12294         case 1:
12295           vex.prefix = DATA_PREFIX_OPCODE;
12296           break;
12297         case 2:
12298           vex.prefix = REPE_PREFIX_OPCODE;
12299           break;
12300         case 3:
12301           vex.prefix = REPNE_PREFIX_OPCODE;
12302           break;
12303         }
12304
12305       /* The third byte after 0x62.  */
12306       codep++;
12307
12308       /* Remember the static rounding bits.  */
12309       vex.ll = (*codep >> 5) & 3;
12310       vex.b = (*codep & 0x10) != 0;
12311
12312       vex.v = *codep & 0x8;
12313       vex.mask_register_specifier = *codep & 0x7;
12314       vex.zeroing = *codep & 0x80;
12315
12316       need_vex = 1;
12317       need_vex_reg = 1;
12318       codep++;
12319       vindex = *codep++;
12320       dp = &evex_table[vex_table_index][vindex];
12321       end_codep = codep;
12322       FETCH_DATA (info, codep + 1);
12323       modrm.mod = (*codep >> 6) & 3;
12324       modrm.reg = (*codep >> 3) & 7;
12325       modrm.rm = *codep & 7;
12326
12327       /* Set vector length.  */
12328       if (modrm.mod == 3 && vex.b)
12329         vex.length = 512;
12330       else
12331         {
12332           switch (vex.ll)
12333             {
12334             case 0x0:
12335               vex.length = 128;
12336               break;
12337             case 0x1:
12338               vex.length = 256;
12339               break;
12340             case 0x2:
12341               vex.length = 512;
12342               break;
12343             default:
12344               return &bad_opcode;
12345             }
12346         }
12347       break;
12348
12349     case 0:
12350       dp = &bad_opcode;
12351       break;
12352
12353     default:
12354       abort ();
12355     }
12356
12357   if (dp->name != NULL)
12358     return dp;
12359   else
12360     return get_valid_dis386 (dp, info);
12361 }
12362
12363 static void
12364 get_sib (disassemble_info *info, int sizeflag)
12365 {
12366   /* If modrm.mod == 3, operand must be register.  */
12367   if (need_modrm
12368       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12369       && modrm.mod != 3
12370       && modrm.rm == 4)
12371     {
12372       FETCH_DATA (info, codep + 2);
12373       sib.index = (codep [1] >> 3) & 7;
12374       sib.scale = (codep [1] >> 6) & 3;
12375       sib.base = codep [1] & 7;
12376     }
12377 }
12378
12379 static int
12380 print_insn (bfd_vma pc, disassemble_info *info)
12381 {
12382   const struct dis386 *dp;
12383   int i;
12384   char *op_txt[MAX_OPERANDS];
12385   int needcomma;
12386   int sizeflag;
12387   const char *p;
12388   struct dis_private priv;
12389   int prefix_length;
12390   int default_prefixes;
12391
12392   priv.orig_sizeflag = AFLAG | DFLAG;
12393   if ((info->mach & bfd_mach_i386_i386) != 0)
12394     address_mode = mode_32bit;
12395   else if (info->mach == bfd_mach_i386_i8086)
12396     {
12397       address_mode = mode_16bit;
12398       priv.orig_sizeflag = 0;
12399     }
12400   else
12401     address_mode = mode_64bit;
12402
12403   if (intel_syntax == (char) -1)
12404     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12405
12406   for (p = info->disassembler_options; p != NULL; )
12407     {
12408       if (CONST_STRNEQ (p, "x86-64"))
12409         {
12410           address_mode = mode_64bit;
12411           priv.orig_sizeflag = AFLAG | DFLAG;
12412         }
12413       else if (CONST_STRNEQ (p, "i386"))
12414         {
12415           address_mode = mode_32bit;
12416           priv.orig_sizeflag = AFLAG | DFLAG;
12417         }
12418       else if (CONST_STRNEQ (p, "i8086"))
12419         {
12420           address_mode = mode_16bit;
12421           priv.orig_sizeflag = 0;
12422         }
12423       else if (CONST_STRNEQ (p, "intel"))
12424         {
12425           intel_syntax = 1;
12426           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12427             intel_mnemonic = 1;
12428         }
12429       else if (CONST_STRNEQ (p, "att"))
12430         {
12431           intel_syntax = 0;
12432           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12433             intel_mnemonic = 0;
12434         }
12435       else if (CONST_STRNEQ (p, "addr"))
12436         {
12437           if (address_mode == mode_64bit)
12438             {
12439               if (p[4] == '3' && p[5] == '2')
12440                 priv.orig_sizeflag &= ~AFLAG;
12441               else if (p[4] == '6' && p[5] == '4')
12442                 priv.orig_sizeflag |= AFLAG;
12443             }
12444           else
12445             {
12446               if (p[4] == '1' && p[5] == '6')
12447                 priv.orig_sizeflag &= ~AFLAG;
12448               else if (p[4] == '3' && p[5] == '2')
12449                 priv.orig_sizeflag |= AFLAG;
12450             }
12451         }
12452       else if (CONST_STRNEQ (p, "data"))
12453         {
12454           if (p[4] == '1' && p[5] == '6')
12455             priv.orig_sizeflag &= ~DFLAG;
12456           else if (p[4] == '3' && p[5] == '2')
12457             priv.orig_sizeflag |= DFLAG;
12458         }
12459       else if (CONST_STRNEQ (p, "suffix"))
12460         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12461
12462       p = strchr (p, ',');
12463       if (p != NULL)
12464         p++;
12465     }
12466
12467   if (intel_syntax)
12468     {
12469       names64 = intel_names64;
12470       names32 = intel_names32;
12471       names16 = intel_names16;
12472       names8 = intel_names8;
12473       names8rex = intel_names8rex;
12474       names_seg = intel_names_seg;
12475       names_mm = intel_names_mm;
12476       names_bnd = intel_names_bnd;
12477       names_xmm = intel_names_xmm;
12478       names_ymm = intel_names_ymm;
12479       names_zmm = intel_names_zmm;
12480       index64 = intel_index64;
12481       index32 = intel_index32;
12482       names_mask = intel_names_mask;
12483       index16 = intel_index16;
12484       open_char = '[';
12485       close_char = ']';
12486       separator_char = '+';
12487       scale_char = '*';
12488     }
12489   else
12490     {
12491       names64 = att_names64;
12492       names32 = att_names32;
12493       names16 = att_names16;
12494       names8 = att_names8;
12495       names8rex = att_names8rex;
12496       names_seg = att_names_seg;
12497       names_mm = att_names_mm;
12498       names_bnd = att_names_bnd;
12499       names_xmm = att_names_xmm;
12500       names_ymm = att_names_ymm;
12501       names_zmm = att_names_zmm;
12502       index64 = att_index64;
12503       index32 = att_index32;
12504       names_mask = att_names_mask;
12505       index16 = att_index16;
12506       open_char = '(';
12507       close_char =  ')';
12508       separator_char = ',';
12509       scale_char = ',';
12510     }
12511
12512   /* The output looks better if we put 7 bytes on a line, since that
12513      puts most long word instructions on a single line.  Use 8 bytes
12514      for Intel L1OM.  */
12515   if ((info->mach & bfd_mach_l1om) != 0)
12516     info->bytes_per_line = 8;
12517   else
12518     info->bytes_per_line = 7;
12519
12520   info->private_data = &priv;
12521   priv.max_fetched = priv.the_buffer;
12522   priv.insn_start = pc;
12523
12524   obuf[0] = 0;
12525   for (i = 0; i < MAX_OPERANDS; ++i)
12526     {
12527       op_out[i][0] = 0;
12528       op_index[i] = -1;
12529     }
12530
12531   the_info = info;
12532   start_pc = pc;
12533   start_codep = priv.the_buffer;
12534   codep = priv.the_buffer;
12535
12536   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12537     {
12538       const char *name;
12539
12540       /* Getting here means we tried for data but didn't get it.  That
12541          means we have an incomplete instruction of some sort.  Just
12542          print the first byte as a prefix or a .byte pseudo-op.  */
12543       if (codep > priv.the_buffer)
12544         {
12545           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12546           if (name != NULL)
12547             (*info->fprintf_func) (info->stream, "%s", name);
12548           else
12549             {
12550               /* Just print the first byte as a .byte instruction.  */
12551               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12552                                      (unsigned int) priv.the_buffer[0]);
12553             }
12554
12555           return 1;
12556         }
12557
12558       return -1;
12559     }
12560
12561   obufp = obuf;
12562   sizeflag = priv.orig_sizeflag;
12563
12564   if (!ckprefix () || rex_used)
12565     {
12566       /* Too many prefixes or unused REX prefixes.  */
12567       for (i = 0;
12568            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12569            i++)
12570         (*info->fprintf_func) (info->stream, "%s%s",
12571                                i == 0 ? "" : " ",
12572                                prefix_name (all_prefixes[i], sizeflag));
12573       return i;
12574     }
12575
12576   insn_codep = codep;
12577
12578   FETCH_DATA (info, codep + 1);
12579   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12580
12581   if (((prefixes & PREFIX_FWAIT)
12582        && ((*codep < 0xd8) || (*codep > 0xdf))))
12583     {
12584       /* Handle prefixes before fwait.  */
12585       for (i = 0;
12586            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12587            i++)
12588         (*info->fprintf_func) (info->stream, "%s ",
12589                                prefix_name (all_prefixes[i], sizeflag));
12590       (*info->fprintf_func) (info->stream, "fwait");
12591       return i + 1;
12592     }
12593
12594   if (*codep == 0x0f)
12595     {
12596       unsigned char threebyte;
12597       FETCH_DATA (info, codep + 2);
12598       threebyte = *++codep;
12599       dp = &dis386_twobyte[threebyte];
12600       need_modrm = twobyte_has_modrm[*codep];
12601       mandatory_prefix = twobyte_has_mandatory_prefix[*codep];
12602       codep++;
12603     }
12604   else
12605     {
12606       dp = &dis386[*codep];
12607       need_modrm = onebyte_has_modrm[*codep];
12608       mandatory_prefix = 0;
12609       codep++;
12610     }
12611
12612   default_prefixes = 0;
12613   if (prefixes & PREFIX_ADDR)
12614     {
12615       sizeflag ^= AFLAG;
12616       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
12617         {
12618           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12619             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
12620           else
12621             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
12622           default_prefixes |= PREFIX_ADDR;
12623         }
12624     }
12625
12626   if ((prefixes & PREFIX_DATA))
12627     {
12628       sizeflag ^= DFLAG;
12629       if (dp->op[2].bytemode == cond_jump_mode
12630           && dp->op[0].bytemode == v_mode
12631           && !intel_syntax)
12632         {
12633           if (sizeflag & DFLAG)
12634             all_prefixes[last_data_prefix] = DATA32_PREFIX;
12635           else
12636             all_prefixes[last_data_prefix] = DATA16_PREFIX;
12637           default_prefixes |= PREFIX_DATA;
12638         }
12639       else if (rex & REX_W)
12640         {
12641           /* REX_W will override PREFIX_DATA.  */
12642           default_prefixes |= PREFIX_DATA;
12643         }
12644     }
12645
12646   end_codep = codep;
12647   if (need_modrm)
12648     {
12649       FETCH_DATA (info, codep + 1);
12650       modrm.mod = (*codep >> 6) & 3;
12651       modrm.reg = (*codep >> 3) & 7;
12652       modrm.rm = *codep & 7;
12653     }
12654
12655   need_vex = 0;
12656   need_vex_reg = 0;
12657   vex_w_done = 0;
12658   vex.evex = 0;
12659
12660   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12661     {
12662       get_sib (info, sizeflag);
12663       dofloat (sizeflag);
12664     }
12665   else
12666     {
12667       dp = get_valid_dis386 (dp, info);
12668       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12669         {
12670           get_sib (info, sizeflag);
12671           for (i = 0; i < MAX_OPERANDS; ++i)
12672             {
12673               obufp = op_out[i];
12674               op_ad = MAX_OPERANDS - 1 - i;
12675               if (dp->op[i].rtn)
12676                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12677               /* For EVEX instruction after the last operand masking
12678                  should be printed.  */
12679               if (i == 0 && vex.evex)
12680                 {
12681                   /* Don't print {%k0}.  */
12682                   if (vex.mask_register_specifier)
12683                     {
12684                       oappend ("{");
12685                       oappend (names_mask[vex.mask_register_specifier]);
12686                       oappend ("}");
12687                     }
12688                   if (vex.zeroing)
12689                     oappend ("{z}");
12690                 }
12691             }
12692         }
12693     }
12694
12695   /* Check if the REX prefix is used.  */
12696   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12697     all_prefixes[last_rex_prefix] = 0;
12698
12699   /* Check if the SEG prefix is used.  */
12700   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12701                    | PREFIX_FS | PREFIX_GS)) != 0
12702       && (used_prefixes & active_seg_prefix) != 0)
12703     all_prefixes[last_seg_prefix] = 0;
12704
12705   /* Check if the ADDR prefix is used.  */
12706   if ((prefixes & PREFIX_ADDR) != 0
12707       && (used_prefixes & PREFIX_ADDR) != 0)
12708     all_prefixes[last_addr_prefix] = 0;
12709
12710   /* Check if the DATA prefix is used.  Restore the DFLAG bit in
12711      sizeflag if the DATA prefix is unused.  */
12712   if ((prefixes & PREFIX_DATA) != 0)
12713     {
12714       if ((used_prefixes & PREFIX_DATA) != 0)
12715         all_prefixes[last_data_prefix] = 0;
12716       else if ((default_prefixes & PREFIX_DATA) == 0)
12717         sizeflag ^= DFLAG;
12718     }
12719
12720   prefix_length = 0;
12721   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12722     if (all_prefixes[i])
12723       {
12724         const char *name;
12725         name = prefix_name (all_prefixes[i], sizeflag);
12726         if (name == NULL)
12727           abort ();
12728         prefix_length += strlen (name) + 1;
12729         (*info->fprintf_func) (info->stream, "%s ", name);
12730       }
12731
12732   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12733      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12734      used by putop and MMX/SSE operand and may be overriden by the
12735      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12736      separately.  */
12737   if (mandatory_prefix
12738       && dp != &bad_opcode
12739       && (((prefixes
12740             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12741            && (used_prefixes
12742                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12743           || ((((prefixes
12744                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12745                 == PREFIX_DATA)
12746                && (used_prefixes & PREFIX_DATA) == 0))))
12747     {
12748       (*info->fprintf_func) (info->stream, "(bad)");
12749       return end_codep - priv.the_buffer;
12750     }
12751
12752   /* Check maximum code length.  */
12753   if ((codep - start_codep) > MAX_CODE_LENGTH)
12754     {
12755       (*info->fprintf_func) (info->stream, "(bad)");
12756       return MAX_CODE_LENGTH;
12757     }
12758
12759   obufp = mnemonicendp;
12760   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12761     oappend (" ");
12762   oappend (" ");
12763   (*info->fprintf_func) (info->stream, "%s", obuf);
12764
12765   /* The enter and bound instructions are printed with operands in the same
12766      order as the intel book; everything else is printed in reverse order.  */
12767   if (intel_syntax || two_source_ops)
12768     {
12769       bfd_vma riprel;
12770
12771       for (i = 0; i < MAX_OPERANDS; ++i)
12772         op_txt[i] = op_out[i];
12773
12774       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12775         {
12776           op_ad = op_index[i];
12777           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12778           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12779           riprel = op_riprel[i];
12780           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12781           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12782         }
12783     }
12784   else
12785     {
12786       for (i = 0; i < MAX_OPERANDS; ++i)
12787         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12788     }
12789
12790   needcomma = 0;
12791   for (i = 0; i < MAX_OPERANDS; ++i)
12792     if (*op_txt[i])
12793       {
12794         if (needcomma)
12795           (*info->fprintf_func) (info->stream, ",");
12796         if (op_index[i] != -1 && !op_riprel[i])
12797           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12798         else
12799           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12800         needcomma = 1;
12801       }
12802
12803   for (i = 0; i < MAX_OPERANDS; i++)
12804     if (op_index[i] != -1 && op_riprel[i])
12805       {
12806         (*info->fprintf_func) (info->stream, "        # ");
12807         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
12808                                                 + op_address[op_index[i]]), info);
12809         break;
12810       }
12811   return codep - priv.the_buffer;
12812 }
12813
12814 static const char *float_mem[] = {
12815   /* d8 */
12816   "fadd{s|}",
12817   "fmul{s|}",
12818   "fcom{s|}",
12819   "fcomp{s|}",
12820   "fsub{s|}",
12821   "fsubr{s|}",
12822   "fdiv{s|}",
12823   "fdivr{s|}",
12824   /* d9 */
12825   "fld{s|}",
12826   "(bad)",
12827   "fst{s|}",
12828   "fstp{s|}",
12829   "fldenvIC",
12830   "fldcw",
12831   "fNstenvIC",
12832   "fNstcw",
12833   /* da */
12834   "fiadd{l|}",
12835   "fimul{l|}",
12836   "ficom{l|}",
12837   "ficomp{l|}",
12838   "fisub{l|}",
12839   "fisubr{l|}",
12840   "fidiv{l|}",
12841   "fidivr{l|}",
12842   /* db */
12843   "fild{l|}",
12844   "fisttp{l|}",
12845   "fist{l|}",
12846   "fistp{l|}",
12847   "(bad)",
12848   "fld{t||t|}",
12849   "(bad)",
12850   "fstp{t||t|}",
12851   /* dc */
12852   "fadd{l|}",
12853   "fmul{l|}",
12854   "fcom{l|}",
12855   "fcomp{l|}",
12856   "fsub{l|}",
12857   "fsubr{l|}",
12858   "fdiv{l|}",
12859   "fdivr{l|}",
12860   /* dd */
12861   "fld{l|}",
12862   "fisttp{ll|}",
12863   "fst{l||}",
12864   "fstp{l|}",
12865   "frstorIC",
12866   "(bad)",
12867   "fNsaveIC",
12868   "fNstsw",
12869   /* de */
12870   "fiadd",
12871   "fimul",
12872   "ficom",
12873   "ficomp",
12874   "fisub",
12875   "fisubr",
12876   "fidiv",
12877   "fidivr",
12878   /* df */
12879   "fild",
12880   "fisttp",
12881   "fist",
12882   "fistp",
12883   "fbld",
12884   "fild{ll|}",
12885   "fbstp",
12886   "fistp{ll|}",
12887 };
12888
12889 static const unsigned char float_mem_mode[] = {
12890   /* d8 */
12891   d_mode,
12892   d_mode,
12893   d_mode,
12894   d_mode,
12895   d_mode,
12896   d_mode,
12897   d_mode,
12898   d_mode,
12899   /* d9 */
12900   d_mode,
12901   0,
12902   d_mode,
12903   d_mode,
12904   0,
12905   w_mode,
12906   0,
12907   w_mode,
12908   /* da */
12909   d_mode,
12910   d_mode,
12911   d_mode,
12912   d_mode,
12913   d_mode,
12914   d_mode,
12915   d_mode,
12916   d_mode,
12917   /* db */
12918   d_mode,
12919   d_mode,
12920   d_mode,
12921   d_mode,
12922   0,
12923   t_mode,
12924   0,
12925   t_mode,
12926   /* dc */
12927   q_mode,
12928   q_mode,
12929   q_mode,
12930   q_mode,
12931   q_mode,
12932   q_mode,
12933   q_mode,
12934   q_mode,
12935   /* dd */
12936   q_mode,
12937   q_mode,
12938   q_mode,
12939   q_mode,
12940   0,
12941   0,
12942   0,
12943   w_mode,
12944   /* de */
12945   w_mode,
12946   w_mode,
12947   w_mode,
12948   w_mode,
12949   w_mode,
12950   w_mode,
12951   w_mode,
12952   w_mode,
12953   /* df */
12954   w_mode,
12955   w_mode,
12956   w_mode,
12957   w_mode,
12958   t_mode,
12959   q_mode,
12960   t_mode,
12961   q_mode
12962 };
12963
12964 #define ST { OP_ST, 0 }
12965 #define STi { OP_STi, 0 }
12966
12967 #define FGRPd9_2 NULL, { { NULL, 0 } }
12968 #define FGRPd9_4 NULL, { { NULL, 1 } }
12969 #define FGRPd9_5 NULL, { { NULL, 2 } }
12970 #define FGRPd9_6 NULL, { { NULL, 3 } }
12971 #define FGRPd9_7 NULL, { { NULL, 4 } }
12972 #define FGRPda_5 NULL, { { NULL, 5 } }
12973 #define FGRPdb_4 NULL, { { NULL, 6 } }
12974 #define FGRPde_3 NULL, { { NULL, 7 } }
12975 #define FGRPdf_4 NULL, { { NULL, 8 } }
12976
12977 static const struct dis386 float_reg[][8] = {
12978   /* d8 */
12979   {
12980     { "fadd",   { ST, STi } },
12981     { "fmul",   { ST, STi } },
12982     { "fcom",   { STi } },
12983     { "fcomp",  { STi } },
12984     { "fsub",   { ST, STi } },
12985     { "fsubr",  { ST, STi } },
12986     { "fdiv",   { ST, STi } },
12987     { "fdivr",  { ST, STi } },
12988   },
12989   /* d9 */
12990   {
12991     { "fld",    { STi } },
12992     { "fxch",   { STi } },
12993     { FGRPd9_2 },
12994     { Bad_Opcode },
12995     { FGRPd9_4 },
12996     { FGRPd9_5 },
12997     { FGRPd9_6 },
12998     { FGRPd9_7 },
12999   },
13000   /* da */
13001   {
13002     { "fcmovb", { ST, STi } },
13003     { "fcmove", { ST, STi } },
13004     { "fcmovbe",{ ST, STi } },
13005     { "fcmovu", { ST, STi } },
13006     { Bad_Opcode },
13007     { FGRPda_5 },
13008     { Bad_Opcode },
13009     { Bad_Opcode },
13010   },
13011   /* db */
13012   {
13013     { "fcmovnb",{ ST, STi } },
13014     { "fcmovne",{ ST, STi } },
13015     { "fcmovnbe",{ ST, STi } },
13016     { "fcmovnu",{ ST, STi } },
13017     { FGRPdb_4 },
13018     { "fucomi", { ST, STi } },
13019     { "fcomi",  { ST, STi } },
13020     { Bad_Opcode },
13021   },
13022   /* dc */
13023   {
13024     { "fadd",   { STi, ST } },
13025     { "fmul",   { STi, ST } },
13026     { Bad_Opcode },
13027     { Bad_Opcode },
13028     { "fsub!M", { STi, ST } },
13029     { "fsubM",  { STi, ST } },
13030     { "fdiv!M", { STi, ST } },
13031     { "fdivM",  { STi, ST } },
13032   },
13033   /* dd */
13034   {
13035     { "ffree",  { STi } },
13036     { Bad_Opcode },
13037     { "fst",    { STi } },
13038     { "fstp",   { STi } },
13039     { "fucom",  { STi } },
13040     { "fucomp", { STi } },
13041     { Bad_Opcode },
13042     { Bad_Opcode },
13043   },
13044   /* de */
13045   {
13046     { "faddp",  { STi, ST } },
13047     { "fmulp",  { STi, ST } },
13048     { Bad_Opcode },
13049     { FGRPde_3 },
13050     { "fsub!Mp", { STi, ST } },
13051     { "fsubMp", { STi, ST } },
13052     { "fdiv!Mp", { STi, ST } },
13053     { "fdivMp", { STi, ST } },
13054   },
13055   /* df */
13056   {
13057     { "ffreep", { STi } },
13058     { Bad_Opcode },
13059     { Bad_Opcode },
13060     { Bad_Opcode },
13061     { FGRPdf_4 },
13062     { "fucomip", { ST, STi } },
13063     { "fcomip", { ST, STi } },
13064     { Bad_Opcode },
13065   },
13066 };
13067
13068 static char *fgrps[][8] = {
13069   /* d9_2  0 */
13070   {
13071     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13072   },
13073
13074   /* d9_4  1 */
13075   {
13076     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13077   },
13078
13079   /* d9_5  2 */
13080   {
13081     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13082   },
13083
13084   /* d9_6  3 */
13085   {
13086     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13087   },
13088
13089   /* d9_7  4 */
13090   {
13091     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13092   },
13093
13094   /* da_5  5 */
13095   {
13096     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13097   },
13098
13099   /* db_4  6 */
13100   {
13101     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13102     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13103   },
13104
13105   /* de_3  7 */
13106   {
13107     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13108   },
13109
13110   /* df_4  8 */
13111   {
13112     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13113   },
13114 };
13115
13116 static void
13117 swap_operand (void)
13118 {
13119   mnemonicendp[0] = '.';
13120   mnemonicendp[1] = 's';
13121   mnemonicendp += 2;
13122 }
13123
13124 static void
13125 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13126                int sizeflag ATTRIBUTE_UNUSED)
13127 {
13128   /* Skip mod/rm byte.  */
13129   MODRM_CHECK;
13130   codep++;
13131 }
13132
13133 static void
13134 dofloat (int sizeflag)
13135 {
13136   const struct dis386 *dp;
13137   unsigned char floatop;
13138
13139   floatop = codep[-1];
13140
13141   if (modrm.mod != 3)
13142     {
13143       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13144
13145       putop (float_mem[fp_indx], sizeflag);
13146       obufp = op_out[0];
13147       op_ad = 2;
13148       OP_E (float_mem_mode[fp_indx], sizeflag);
13149       return;
13150     }
13151   /* Skip mod/rm byte.  */
13152   MODRM_CHECK;
13153   codep++;
13154
13155   dp = &float_reg[floatop - 0xd8][modrm.reg];
13156   if (dp->name == NULL)
13157     {
13158       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13159
13160       /* Instruction fnstsw is only one with strange arg.  */
13161       if (floatop == 0xdf && codep[-1] == 0xe0)
13162         strcpy (op_out[0], names16[0]);
13163     }
13164   else
13165     {
13166       putop (dp->name, sizeflag);
13167
13168       obufp = op_out[0];
13169       op_ad = 2;
13170       if (dp->op[0].rtn)
13171         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13172
13173       obufp = op_out[1];
13174       op_ad = 1;
13175       if (dp->op[1].rtn)
13176         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13177     }
13178 }
13179
13180 /* Like oappend (below), but S is a string starting with '%'.
13181    In Intel syntax, the '%' is elided.  */
13182 static void
13183 oappend_maybe_intel (const char *s)
13184 {
13185   oappend (s + intel_syntax);
13186 }
13187
13188 static void
13189 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13190 {
13191   oappend_maybe_intel ("%st");
13192 }
13193
13194 static void
13195 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13196 {
13197   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13198   oappend_maybe_intel (scratchbuf);
13199 }
13200
13201 /* Capital letters in template are macros.  */
13202 static int
13203 putop (const char *in_template, int sizeflag)
13204 {
13205   const char *p;
13206   int alt = 0;
13207   int cond = 1;
13208   unsigned int l = 0, len = 1;
13209   char last[4];
13210
13211 #define SAVE_LAST(c)                    \
13212   if (l < len && l < sizeof (last))     \
13213     last[l++] = c;                      \
13214   else                                  \
13215     abort ();
13216
13217   for (p = in_template; *p; p++)
13218     {
13219       switch (*p)
13220         {
13221         default:
13222           *obufp++ = *p;
13223           break;
13224         case '%':
13225           len++;
13226           break;
13227         case '!':
13228           cond = 0;
13229           break;
13230         case '{':
13231           alt = 0;
13232           if (intel_syntax)
13233             {
13234               while (*++p != '|')
13235                 if (*p == '}' || *p == '\0')
13236                   abort ();
13237             }
13238           /* Fall through.  */
13239         case 'I':
13240           alt = 1;
13241           continue;
13242         case '|':
13243           while (*++p != '}')
13244             {
13245               if (*p == '\0')
13246                 abort ();
13247             }
13248           break;
13249         case '}':
13250           break;
13251         case 'A':
13252           if (intel_syntax)
13253             break;
13254           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13255             *obufp++ = 'b';
13256           break;
13257         case 'B':
13258           if (l == 0 && len == 1)
13259             {
13260 case_B:
13261               if (intel_syntax)
13262                 break;
13263               if (sizeflag & SUFFIX_ALWAYS)
13264                 *obufp++ = 'b';
13265             }
13266           else
13267             {
13268               if (l != 1
13269                   || len != 2
13270                   || last[0] != 'L')
13271                 {
13272                   SAVE_LAST (*p);
13273                   break;
13274                 }
13275
13276               if (address_mode == mode_64bit
13277                   && !(prefixes & PREFIX_ADDR))
13278                 {
13279                   *obufp++ = 'a';
13280                   *obufp++ = 'b';
13281                   *obufp++ = 's';
13282                 }
13283
13284               goto case_B;
13285             }
13286           break;
13287         case 'C':
13288           if (intel_syntax && !alt)
13289             break;
13290           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13291             {
13292               if (sizeflag & DFLAG)
13293                 *obufp++ = intel_syntax ? 'd' : 'l';
13294               else
13295                 *obufp++ = intel_syntax ? 'w' : 's';
13296               used_prefixes |= (prefixes & PREFIX_DATA);
13297             }
13298           break;
13299         case 'D':
13300           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13301             break;
13302           USED_REX (REX_W);
13303           if (modrm.mod == 3)
13304             {
13305               if (rex & REX_W)
13306                 *obufp++ = 'q';
13307               else
13308                 {
13309                   if (sizeflag & DFLAG)
13310                     *obufp++ = intel_syntax ? 'd' : 'l';
13311                   else
13312                     *obufp++ = 'w';
13313                   used_prefixes |= (prefixes & PREFIX_DATA);
13314                 }
13315             }
13316           else
13317             *obufp++ = 'w';
13318           break;
13319         case 'E':               /* For jcxz/jecxz */
13320           if (address_mode == mode_64bit)
13321             {
13322               if (sizeflag & AFLAG)
13323                 *obufp++ = 'r';
13324               else
13325                 *obufp++ = 'e';
13326             }
13327           else
13328             if (sizeflag & AFLAG)
13329               *obufp++ = 'e';
13330           used_prefixes |= (prefixes & PREFIX_ADDR);
13331           break;
13332         case 'F':
13333           if (intel_syntax)
13334             break;
13335           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13336             {
13337               if (sizeflag & AFLAG)
13338                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13339               else
13340                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13341               used_prefixes |= (prefixes & PREFIX_ADDR);
13342             }
13343           break;
13344         case 'G':
13345           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13346             break;
13347           if ((rex & REX_W) || (sizeflag & DFLAG))
13348             *obufp++ = 'l';
13349           else
13350             *obufp++ = 'w';
13351           if (!(rex & REX_W))
13352             used_prefixes |= (prefixes & PREFIX_DATA);
13353           break;
13354         case 'H':
13355           if (intel_syntax)
13356             break;
13357           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13358               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13359             {
13360               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13361               *obufp++ = ',';
13362               *obufp++ = 'p';
13363               if (prefixes & PREFIX_DS)
13364                 *obufp++ = 't';
13365               else
13366                 *obufp++ = 'n';
13367             }
13368           break;
13369         case 'J':
13370           if (intel_syntax)
13371             break;
13372           *obufp++ = 'l';
13373           break;
13374         case 'K':
13375           USED_REX (REX_W);
13376           if (rex & REX_W)
13377             *obufp++ = 'q';
13378           else
13379             *obufp++ = 'd';
13380           break;
13381         case 'Z':
13382           if (intel_syntax)
13383             break;
13384           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13385             {
13386               *obufp++ = 'q';
13387               break;
13388             }
13389           /* Fall through.  */
13390           goto case_L;
13391         case 'L':
13392           if (l != 0 || len != 1)
13393             {
13394               SAVE_LAST (*p);
13395               break;
13396             }
13397 case_L:
13398           if (intel_syntax)
13399             break;
13400           if (sizeflag & SUFFIX_ALWAYS)
13401             *obufp++ = 'l';
13402           break;
13403         case 'M':
13404           if (intel_mnemonic != cond)
13405             *obufp++ = 'r';
13406           break;
13407         case 'N':
13408           if ((prefixes & PREFIX_FWAIT) == 0)
13409             *obufp++ = 'n';
13410           else
13411             used_prefixes |= PREFIX_FWAIT;
13412           break;
13413         case 'O':
13414           USED_REX (REX_W);
13415           if (rex & REX_W)
13416             *obufp++ = 'o';
13417           else if (intel_syntax && (sizeflag & DFLAG))
13418             *obufp++ = 'q';
13419           else
13420             *obufp++ = 'd';
13421           if (!(rex & REX_W))
13422             used_prefixes |= (prefixes & PREFIX_DATA);
13423           break;
13424         case 'T':
13425           if (!intel_syntax
13426               && address_mode == mode_64bit
13427               && ((sizeflag & DFLAG) || (rex & REX_W)))
13428             {
13429               *obufp++ = 'q';
13430               break;
13431             }
13432           /* Fall through.  */
13433         case 'P':
13434           if (intel_syntax)
13435             {
13436               if ((rex & REX_W) == 0
13437                   && (prefixes & PREFIX_DATA))
13438                 {
13439                   if ((sizeflag & DFLAG) == 0)
13440                     *obufp++ = 'w';
13441                    used_prefixes |= (prefixes & PREFIX_DATA);
13442                 }
13443               break;
13444             }
13445           if ((prefixes & PREFIX_DATA)
13446               || (rex & REX_W)
13447               || (sizeflag & SUFFIX_ALWAYS))
13448             {
13449               USED_REX (REX_W);
13450               if (rex & REX_W)
13451                 *obufp++ = 'q';
13452               else
13453                 {
13454                    if (sizeflag & DFLAG)
13455                       *obufp++ = 'l';
13456                    else
13457                      *obufp++ = 'w';
13458                    used_prefixes |= (prefixes & PREFIX_DATA);
13459                 }
13460             }
13461           break;
13462         case 'U':
13463           if (intel_syntax)
13464             break;
13465           if (address_mode == mode_64bit
13466               && ((sizeflag & DFLAG) || (rex & REX_W)))
13467             {
13468               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13469                 *obufp++ = 'q';
13470               break;
13471             }
13472           /* Fall through.  */
13473           goto case_Q;
13474         case 'Q':
13475           if (l == 0 && len == 1)
13476             {
13477 case_Q:
13478               if (intel_syntax && !alt)
13479                 break;
13480               USED_REX (REX_W);
13481               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13482                 {
13483                   if (rex & REX_W)
13484                     *obufp++ = 'q';
13485                   else
13486                     {
13487                       if (sizeflag & DFLAG)
13488                         *obufp++ = intel_syntax ? 'd' : 'l';
13489                       else
13490                         *obufp++ = 'w';
13491                       used_prefixes |= (prefixes & PREFIX_DATA);
13492                     }
13493                 }
13494             }
13495           else
13496             {
13497               if (l != 1 || len != 2 || last[0] != 'L')
13498                 {
13499                   SAVE_LAST (*p);
13500                   break;
13501                 }
13502               if (intel_syntax
13503                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13504                 break;
13505               if ((rex & REX_W))
13506                 {
13507                   USED_REX (REX_W);
13508                   *obufp++ = 'q';
13509                 }
13510               else
13511                 *obufp++ = 'l';
13512             }
13513           break;
13514         case 'R':
13515           USED_REX (REX_W);
13516           if (rex & REX_W)
13517             *obufp++ = 'q';
13518           else if (sizeflag & DFLAG)
13519             {
13520               if (intel_syntax)
13521                   *obufp++ = 'd';
13522               else
13523                   *obufp++ = 'l';
13524             }
13525           else
13526             *obufp++ = 'w';
13527           if (intel_syntax && !p[1]
13528               && ((rex & REX_W) || (sizeflag & DFLAG)))
13529             *obufp++ = 'e';
13530           if (!(rex & REX_W))
13531             used_prefixes |= (prefixes & PREFIX_DATA);
13532           break;
13533         case 'V':
13534           if (l == 0 && len == 1)
13535             {
13536               if (intel_syntax)
13537                 break;
13538               if (address_mode == mode_64bit
13539                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13540                 {
13541                   if (sizeflag & SUFFIX_ALWAYS)
13542                     *obufp++ = 'q';
13543                   break;
13544                 }
13545             }
13546           else
13547             {
13548               if (l != 1
13549                   || len != 2
13550                   || last[0] != 'L')
13551                 {
13552                   SAVE_LAST (*p);
13553                   break;
13554                 }
13555
13556               if (rex & REX_W)
13557                 {
13558                   *obufp++ = 'a';
13559                   *obufp++ = 'b';
13560                   *obufp++ = 's';
13561                 }
13562             }
13563           /* Fall through.  */
13564           goto case_S;
13565         case 'S':
13566           if (l == 0 && len == 1)
13567             {
13568 case_S:
13569               if (intel_syntax)
13570                 break;
13571               if (sizeflag & SUFFIX_ALWAYS)
13572                 {
13573                   if (rex & REX_W)
13574                     *obufp++ = 'q';
13575                   else
13576                     {
13577                       if (sizeflag & DFLAG)
13578                         *obufp++ = 'l';
13579                       else
13580                         *obufp++ = 'w';
13581                       used_prefixes |= (prefixes & PREFIX_DATA);
13582                     }
13583                 }
13584             }
13585           else
13586             {
13587               if (l != 1
13588                   || len != 2
13589                   || last[0] != 'L')
13590                 {
13591                   SAVE_LAST (*p);
13592                   break;
13593                 }
13594
13595               if (address_mode == mode_64bit
13596                   && !(prefixes & PREFIX_ADDR))
13597                 {
13598                   *obufp++ = 'a';
13599                   *obufp++ = 'b';
13600                   *obufp++ = 's';
13601                 }
13602
13603               goto case_S;
13604             }
13605           break;
13606         case 'X':
13607           if (l != 0 || len != 1)
13608             {
13609               SAVE_LAST (*p);
13610               break;
13611             }
13612           if (need_vex && vex.prefix)
13613             {
13614               if (vex.prefix == DATA_PREFIX_OPCODE)
13615                 *obufp++ = 'd';
13616               else
13617                 *obufp++ = 's';
13618             }
13619           else
13620             {
13621               if (prefixes & PREFIX_DATA)
13622                 *obufp++ = 'd';
13623               else
13624                 *obufp++ = 's';
13625               used_prefixes |= (prefixes & PREFIX_DATA);
13626             }
13627           break;
13628         case 'Y':
13629           if (l == 0 && len == 1)
13630             {
13631               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13632                 break;
13633               if (rex & REX_W)
13634                 {
13635                   USED_REX (REX_W);
13636                   *obufp++ = 'q';
13637                 }
13638               break;
13639             }
13640           else
13641             {
13642               if (l != 1 || len != 2 || last[0] != 'X')
13643                 {
13644                   SAVE_LAST (*p);
13645                   break;
13646                 }
13647               if (!need_vex)
13648                 abort ();
13649               if (intel_syntax
13650                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13651                 break;
13652               switch (vex.length)
13653                 {
13654                 case 128:
13655                   *obufp++ = 'x';
13656                   break;
13657                 case 256:
13658                   *obufp++ = 'y';
13659                   break;
13660                 default:
13661                   abort ();
13662                 }
13663             }
13664           break;
13665         case 'W':
13666           if (l == 0 && len == 1)
13667             {
13668               /* operand size flag for cwtl, cbtw */
13669               USED_REX (REX_W);
13670               if (rex & REX_W)
13671                 {
13672                   if (intel_syntax)
13673                     *obufp++ = 'd';
13674                   else
13675                     *obufp++ = 'l';
13676                 }
13677               else if (sizeflag & DFLAG)
13678                 *obufp++ = 'w';
13679               else
13680                 *obufp++ = 'b';
13681               if (!(rex & REX_W))
13682                 used_prefixes |= (prefixes & PREFIX_DATA);
13683             }
13684           else
13685             {
13686               if (l != 1
13687                   || len != 2
13688                   || (last[0] != 'X'
13689                       && last[0] != 'L'))
13690                 {
13691                   SAVE_LAST (*p);
13692                   break;
13693                 }
13694               if (!need_vex)
13695                 abort ();
13696               if (last[0] == 'X')
13697                 *obufp++ = vex.w ? 'd': 's';
13698               else
13699                 *obufp++ = vex.w ? 'q': 'd';
13700             }
13701           break;
13702         }
13703       alt = 0;
13704     }
13705   *obufp = 0;
13706   mnemonicendp = obufp;
13707   return 0;
13708 }
13709
13710 static void
13711 oappend (const char *s)
13712 {
13713   obufp = stpcpy (obufp, s);
13714 }
13715
13716 static void
13717 append_seg (void)
13718 {
13719   /* Only print the active segment register.  */
13720   if (!active_seg_prefix)
13721     return;
13722
13723   used_prefixes |= active_seg_prefix;
13724   switch (active_seg_prefix)
13725     {
13726     case PREFIX_CS:
13727       oappend_maybe_intel ("%cs:");
13728       break;
13729     case PREFIX_DS:
13730       oappend_maybe_intel ("%ds:");
13731       break;
13732     case PREFIX_SS:
13733       oappend_maybe_intel ("%ss:");
13734       break;
13735     case PREFIX_ES:
13736       oappend_maybe_intel ("%es:");
13737       break;
13738     case PREFIX_FS:
13739       oappend_maybe_intel ("%fs:");
13740       break;
13741     case PREFIX_GS:
13742       oappend_maybe_intel ("%gs:");
13743       break;
13744     default:
13745       break;
13746     }
13747 }
13748
13749 static void
13750 OP_indirE (int bytemode, int sizeflag)
13751 {
13752   if (!intel_syntax)
13753     oappend ("*");
13754   OP_E (bytemode, sizeflag);
13755 }
13756
13757 static void
13758 print_operand_value (char *buf, int hex, bfd_vma disp)
13759 {
13760   if (address_mode == mode_64bit)
13761     {
13762       if (hex)
13763         {
13764           char tmp[30];
13765           int i;
13766           buf[0] = '0';
13767           buf[1] = 'x';
13768           sprintf_vma (tmp, disp);
13769           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13770           strcpy (buf + 2, tmp + i);
13771         }
13772       else
13773         {
13774           bfd_signed_vma v = disp;
13775           char tmp[30];
13776           int i;
13777           if (v < 0)
13778             {
13779               *(buf++) = '-';
13780               v = -disp;
13781               /* Check for possible overflow on 0x8000000000000000.  */
13782               if (v < 0)
13783                 {
13784                   strcpy (buf, "9223372036854775808");
13785                   return;
13786                 }
13787             }
13788           if (!v)
13789             {
13790               strcpy (buf, "0");
13791               return;
13792             }
13793
13794           i = 0;
13795           tmp[29] = 0;
13796           while (v)
13797             {
13798               tmp[28 - i] = (v % 10) + '0';
13799               v /= 10;
13800               i++;
13801             }
13802           strcpy (buf, tmp + 29 - i);
13803         }
13804     }
13805   else
13806     {
13807       if (hex)
13808         sprintf (buf, "0x%x", (unsigned int) disp);
13809       else
13810         sprintf (buf, "%d", (int) disp);
13811     }
13812 }
13813
13814 /* Put DISP in BUF as signed hex number.  */
13815
13816 static void
13817 print_displacement (char *buf, bfd_vma disp)
13818 {
13819   bfd_signed_vma val = disp;
13820   char tmp[30];
13821   int i, j = 0;
13822
13823   if (val < 0)
13824     {
13825       buf[j++] = '-';
13826       val = -disp;
13827
13828       /* Check for possible overflow.  */
13829       if (val < 0)
13830         {
13831           switch (address_mode)
13832             {
13833             case mode_64bit:
13834               strcpy (buf + j, "0x8000000000000000");
13835               break;
13836             case mode_32bit:
13837               strcpy (buf + j, "0x80000000");
13838               break;
13839             case mode_16bit:
13840               strcpy (buf + j, "0x8000");
13841               break;
13842             }
13843           return;
13844         }
13845     }
13846
13847   buf[j++] = '0';
13848   buf[j++] = 'x';
13849
13850   sprintf_vma (tmp, (bfd_vma) val);
13851   for (i = 0; tmp[i] == '0'; i++)
13852     continue;
13853   if (tmp[i] == '\0')
13854     i--;
13855   strcpy (buf + j, tmp + i);
13856 }
13857
13858 static void
13859 intel_operand_size (int bytemode, int sizeflag)
13860 {
13861   if (vex.evex
13862       && vex.b
13863       && (bytemode == x_mode
13864           || bytemode == evex_half_bcst_xmmq_mode))
13865     {
13866       if (vex.w)
13867         oappend ("QWORD PTR ");
13868       else
13869         oappend ("DWORD PTR ");
13870       return;
13871     }
13872   switch (bytemode)
13873     {
13874     case b_mode:
13875     case b_swap_mode:
13876     case dqb_mode:
13877       oappend ("BYTE PTR ");
13878       break;
13879     case w_mode:
13880     case dqw_mode:
13881       oappend ("WORD PTR ");
13882       break;
13883     case stack_v_mode:
13884       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13885         {
13886           oappend ("QWORD PTR ");
13887           break;
13888         }
13889       /* FALLTHRU */
13890     case v_mode:
13891     case v_swap_mode:
13892     case dq_mode:
13893       USED_REX (REX_W);
13894       if (rex & REX_W)
13895         oappend ("QWORD PTR ");
13896       else
13897         {
13898           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13899             oappend ("DWORD PTR ");
13900           else
13901             oappend ("WORD PTR ");
13902           used_prefixes |= (prefixes & PREFIX_DATA);
13903         }
13904       break;
13905     case z_mode:
13906       if ((rex & REX_W) || (sizeflag & DFLAG))
13907         *obufp++ = 'D';
13908       oappend ("WORD PTR ");
13909       if (!(rex & REX_W))
13910         used_prefixes |= (prefixes & PREFIX_DATA);
13911       break;
13912     case a_mode:
13913       if (sizeflag & DFLAG)
13914         oappend ("QWORD PTR ");
13915       else
13916         oappend ("DWORD PTR ");
13917       used_prefixes |= (prefixes & PREFIX_DATA);
13918       break;
13919     case d_mode:
13920     case d_scalar_mode:
13921     case d_scalar_swap_mode:
13922     case d_swap_mode:
13923     case dqd_mode:
13924       oappend ("DWORD PTR ");
13925       break;
13926     case q_mode:
13927     case q_scalar_mode:
13928     case q_scalar_swap_mode:
13929     case q_swap_mode:
13930       oappend ("QWORD PTR ");
13931       break;
13932     case m_mode:
13933       if (address_mode == mode_64bit)
13934         oappend ("QWORD PTR ");
13935       else
13936         oappend ("DWORD PTR ");
13937       break;
13938     case f_mode:
13939       if (sizeflag & DFLAG)
13940         oappend ("FWORD PTR ");
13941       else
13942         oappend ("DWORD PTR ");
13943       used_prefixes |= (prefixes & PREFIX_DATA);
13944       break;
13945     case t_mode:
13946       oappend ("TBYTE PTR ");
13947       break;
13948     case x_mode:
13949     case x_swap_mode:
13950     case evex_x_gscat_mode:
13951     case evex_x_nobcst_mode:
13952       if (need_vex)
13953         {
13954           switch (vex.length)
13955             {
13956             case 128:
13957               oappend ("XMMWORD PTR ");
13958               break;
13959             case 256:
13960               oappend ("YMMWORD PTR ");
13961               break;
13962             case 512:
13963               oappend ("ZMMWORD PTR ");
13964               break;
13965             default:
13966               abort ();
13967             }
13968         }
13969       else
13970         oappend ("XMMWORD PTR ");
13971       break;
13972     case xmm_mode:
13973       oappend ("XMMWORD PTR ");
13974       break;
13975     case ymm_mode:
13976       oappend ("YMMWORD PTR ");
13977       break;
13978     case xmmq_mode:
13979     case evex_half_bcst_xmmq_mode:
13980       if (!need_vex)
13981         abort ();
13982
13983       switch (vex.length)
13984         {
13985         case 128:
13986           oappend ("QWORD PTR ");
13987           break;
13988         case 256:
13989           oappend ("XMMWORD PTR ");
13990           break;
13991         case 512:
13992           oappend ("YMMWORD PTR ");
13993           break;
13994         default:
13995           abort ();
13996         }
13997       break;
13998     case xmm_mb_mode:
13999       if (!need_vex)
14000         abort ();
14001
14002       switch (vex.length)
14003         {
14004         case 128:
14005         case 256:
14006         case 512:
14007           oappend ("BYTE PTR ");
14008           break;
14009         default:
14010           abort ();
14011         }
14012       break;
14013     case xmm_mw_mode:
14014       if (!need_vex)
14015         abort ();
14016
14017       switch (vex.length)
14018         {
14019         case 128:
14020         case 256:
14021         case 512:
14022           oappend ("WORD PTR ");
14023           break;
14024         default:
14025           abort ();
14026         }
14027       break;
14028     case xmm_md_mode:
14029       if (!need_vex)
14030         abort ();
14031
14032       switch (vex.length)
14033         {
14034         case 128:
14035         case 256:
14036         case 512:
14037           oappend ("DWORD PTR ");
14038           break;
14039         default:
14040           abort ();
14041         }
14042       break;
14043     case xmm_mq_mode:
14044       if (!need_vex)
14045         abort ();
14046
14047       switch (vex.length)
14048         {
14049         case 128:
14050         case 256:
14051         case 512:
14052           oappend ("QWORD PTR ");
14053           break;
14054         default:
14055           abort ();
14056         }
14057       break;
14058     case xmmdw_mode:
14059       if (!need_vex)
14060         abort ();
14061
14062       switch (vex.length)
14063         {
14064         case 128:
14065           oappend ("WORD PTR ");
14066           break;
14067         case 256:
14068           oappend ("DWORD PTR ");
14069           break;
14070         case 512:
14071           oappend ("QWORD PTR ");
14072           break;
14073         default:
14074           abort ();
14075         }
14076       break;
14077     case xmmqd_mode:
14078       if (!need_vex)
14079         abort ();
14080
14081       switch (vex.length)
14082         {
14083         case 128:
14084           oappend ("DWORD PTR ");
14085           break;
14086         case 256:
14087           oappend ("QWORD PTR ");
14088           break;
14089         case 512:
14090           oappend ("XMMWORD PTR ");
14091           break;
14092         default:
14093           abort ();
14094         }
14095       break;
14096     case ymmq_mode:
14097       if (!need_vex)
14098         abort ();
14099
14100       switch (vex.length)
14101         {
14102         case 128:
14103           oappend ("QWORD PTR ");
14104           break;
14105         case 256:
14106           oappend ("YMMWORD PTR ");
14107           break;
14108         case 512:
14109           oappend ("ZMMWORD PTR ");
14110           break;
14111         default:
14112           abort ();
14113         }
14114       break;
14115     case ymmxmm_mode:
14116       if (!need_vex)
14117         abort ();
14118
14119       switch (vex.length)
14120         {
14121         case 128:
14122         case 256:
14123           oappend ("XMMWORD PTR ");
14124           break;
14125         default:
14126           abort ();
14127         }
14128       break;
14129     case o_mode:
14130       oappend ("OWORD PTR ");
14131       break;
14132     case xmm_mdq_mode:
14133     case vex_w_dq_mode:
14134     case vex_scalar_w_dq_mode:
14135       if (!need_vex)
14136         abort ();
14137
14138       if (vex.w)
14139         oappend ("QWORD PTR ");
14140       else
14141         oappend ("DWORD PTR ");
14142       break;
14143     case vex_vsib_d_w_dq_mode:
14144     case vex_vsib_q_w_dq_mode:
14145       if (!need_vex)
14146         abort ();
14147
14148       if (!vex.evex)
14149         {
14150           if (vex.w)
14151             oappend ("QWORD PTR ");
14152           else
14153             oappend ("DWORD PTR ");
14154         }
14155       else
14156         {
14157           if (vex.length != 512)
14158             abort ();
14159           oappend ("ZMMWORD PTR ");
14160         }
14161       break;
14162     case vex_vsib_q_w_d_mode:
14163     case vex_vsib_d_w_d_mode:
14164       if (!need_vex || !vex.evex || vex.length != 512)
14165         abort ();
14166
14167       oappend ("YMMWORD PTR ");
14168
14169       break;
14170     case mask_mode:
14171       if (!need_vex)
14172         abort ();
14173       /* Currently the only instructions, which allows either mask or
14174          memory operand, are AVX512's KMOVW instructions.  They need
14175          Word-sized operand.  */
14176       if (vex.w || vex.length != 128)
14177         abort ();
14178       oappend ("WORD PTR ");
14179       break;
14180     case v_bnd_mode:
14181     default:
14182       break;
14183     }
14184 }
14185
14186 static void
14187 OP_E_register (int bytemode, int sizeflag)
14188 {
14189   int reg = modrm.rm;
14190   const char **names;
14191
14192   USED_REX (REX_B);
14193   if ((rex & REX_B))
14194     reg += 8;
14195
14196   if ((sizeflag & SUFFIX_ALWAYS)
14197       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
14198     swap_operand ();
14199
14200   switch (bytemode)
14201     {
14202     case b_mode:
14203     case b_swap_mode:
14204       USED_REX (0);
14205       if (rex)
14206         names = names8rex;
14207       else
14208         names = names8;
14209       break;
14210     case w_mode:
14211       names = names16;
14212       break;
14213     case d_mode:
14214       names = names32;
14215       break;
14216     case q_mode:
14217       names = names64;
14218       break;
14219     case m_mode:
14220     case v_bnd_mode:
14221       names = address_mode == mode_64bit ? names64 : names32;
14222       break;
14223     case bnd_mode:
14224       names = names_bnd;
14225       break;
14226     case stack_v_mode:
14227       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14228         {
14229           names = names64;
14230           break;
14231         }
14232       bytemode = v_mode;
14233       /* FALLTHRU */
14234     case v_mode:
14235     case v_swap_mode:
14236     case dq_mode:
14237     case dqb_mode:
14238     case dqd_mode:
14239     case dqw_mode:
14240       USED_REX (REX_W);
14241       if (rex & REX_W)
14242         names = names64;
14243       else
14244         {
14245           if ((sizeflag & DFLAG)
14246               || (bytemode != v_mode
14247                   && bytemode != v_swap_mode))
14248             names = names32;
14249           else
14250             names = names16;
14251           used_prefixes |= (prefixes & PREFIX_DATA);
14252         }
14253       break;
14254     case mask_mode:
14255       names = names_mask;
14256       break;
14257     case 0:
14258       return;
14259     default:
14260       oappend (INTERNAL_DISASSEMBLER_ERROR);
14261       return;
14262     }
14263   oappend (names[reg]);
14264 }
14265
14266 static void
14267 OP_E_memory (int bytemode, int sizeflag)
14268 {
14269   bfd_vma disp = 0;
14270   int add = (rex & REX_B) ? 8 : 0;
14271   int riprel = 0;
14272   int shift;
14273
14274   if (vex.evex)
14275     {
14276       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14277       if (vex.b
14278           && bytemode != x_mode
14279           && bytemode != evex_half_bcst_xmmq_mode)
14280         {
14281           BadOp ();
14282           return;
14283         }
14284       switch (bytemode)
14285         {
14286         case vex_vsib_d_w_dq_mode:
14287         case vex_vsib_d_w_d_mode:
14288         case vex_vsib_q_w_dq_mode:
14289         case vex_vsib_q_w_d_mode:
14290         case evex_x_gscat_mode:
14291         case xmm_mdq_mode:
14292           shift = vex.w ? 3 : 2;
14293           break;
14294         case x_mode:
14295         case evex_half_bcst_xmmq_mode:
14296           if (vex.b)
14297             {
14298               shift = vex.w ? 3 : 2;
14299               break;
14300             }
14301           /* Fall through if vex.b == 0.  */
14302         case xmmqd_mode:
14303         case xmmdw_mode:
14304         case xmmq_mode:
14305         case ymmq_mode:
14306         case evex_x_nobcst_mode:
14307         case x_swap_mode:
14308           switch (vex.length)
14309             {
14310             case 128:
14311               shift = 4;
14312               break;
14313             case 256:
14314               shift = 5;
14315               break;
14316             case 512:
14317               shift = 6;
14318               break;
14319             default:
14320               abort ();
14321             }
14322           break;
14323         case ymm_mode:
14324           shift = 5;
14325           break;
14326         case xmm_mode:
14327           shift = 4;
14328           break;
14329         case xmm_mq_mode:
14330         case q_mode:
14331         case q_scalar_mode:
14332         case q_swap_mode:
14333         case q_scalar_swap_mode:
14334           shift = 3;
14335           break;
14336         case dqd_mode:
14337         case xmm_md_mode:
14338         case d_mode:
14339         case d_scalar_mode:
14340         case d_swap_mode:
14341         case d_scalar_swap_mode:
14342           shift = 2;
14343           break;
14344         case xmm_mw_mode:
14345           shift = 1;
14346           break;
14347         case xmm_mb_mode:
14348           shift = 0;
14349           break;
14350         default:
14351           abort ();
14352         }
14353       /* Make necessary corrections to shift for modes that need it.
14354          For these modes we currently have shift 4, 5 or 6 depending on
14355          vex.length (it corresponds to xmmword, ymmword or zmmword
14356          operand).  We might want to make it 3, 4 or 5 (e.g. for
14357          xmmq_mode).  In case of broadcast enabled the corrections
14358          aren't needed, as element size is always 32 or 64 bits.  */
14359       if (bytemode == xmmq_mode
14360           || (bytemode == evex_half_bcst_xmmq_mode
14361               && !vex.b))
14362         shift -= 1;
14363       else if (bytemode == xmmqd_mode)
14364         shift -= 2;
14365       else if (bytemode == xmmdw_mode)
14366         shift -= 3;
14367     }
14368   else
14369     shift = 0;
14370
14371   USED_REX (REX_B);
14372   if (intel_syntax)
14373     intel_operand_size (bytemode, sizeflag);
14374   append_seg ();
14375
14376   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14377     {
14378       /* 32/64 bit address mode */
14379       int havedisp;
14380       int havesib;
14381       int havebase;
14382       int haveindex;
14383       int needindex;
14384       int base, rbase;
14385       int vindex = 0;
14386       int scale = 0;
14387       int addr32flag = !((sizeflag & AFLAG)
14388                          || bytemode == v_bnd_mode
14389                          || bytemode == bnd_mode);
14390       const char **indexes64 = names64;
14391       const char **indexes32 = names32;
14392
14393       havesib = 0;
14394       havebase = 1;
14395       haveindex = 0;
14396       base = modrm.rm;
14397
14398       if (base == 4)
14399         {
14400           havesib = 1;
14401           vindex = sib.index;
14402           USED_REX (REX_X);
14403           if (rex & REX_X)
14404             vindex += 8;
14405           switch (bytemode)
14406             {
14407             case vex_vsib_d_w_dq_mode:
14408             case vex_vsib_d_w_d_mode:
14409             case vex_vsib_q_w_dq_mode:
14410             case vex_vsib_q_w_d_mode:
14411               if (!need_vex)
14412                 abort ();
14413               if (vex.evex)
14414                 {
14415                   if (!vex.v)
14416                     vindex += 16;
14417                 }
14418
14419               haveindex = 1;
14420               switch (vex.length)
14421                 {
14422                 case 128:
14423                   indexes64 = indexes32 = names_xmm;
14424                   break;
14425                 case 256:
14426                   if (!vex.w
14427                       || bytemode == vex_vsib_q_w_dq_mode
14428                       || bytemode == vex_vsib_q_w_d_mode)
14429                     indexes64 = indexes32 = names_ymm;
14430                   else
14431                     indexes64 = indexes32 = names_xmm;
14432                   break;
14433                 case 512:
14434                   if (!vex.w
14435                       || bytemode == vex_vsib_q_w_dq_mode
14436                       || bytemode == vex_vsib_q_w_d_mode)
14437                     indexes64 = indexes32 = names_zmm;
14438                   else
14439                     indexes64 = indexes32 = names_ymm;
14440                   break;
14441                 default:
14442                   abort ();
14443                 }
14444               break;
14445             default:
14446               haveindex = vindex != 4;
14447               break;
14448             }
14449           scale = sib.scale;
14450           base = sib.base;
14451           codep++;
14452         }
14453       rbase = base + add;
14454
14455       switch (modrm.mod)
14456         {
14457         case 0:
14458           if (base == 5)
14459             {
14460               havebase = 0;
14461               if (address_mode == mode_64bit && !havesib)
14462                 riprel = 1;
14463               disp = get32s ();
14464             }
14465           break;
14466         case 1:
14467           FETCH_DATA (the_info, codep + 1);
14468           disp = *codep++;
14469           if ((disp & 0x80) != 0)
14470             disp -= 0x100;
14471           if (vex.evex && shift > 0)
14472             disp <<= shift;
14473           break;
14474         case 2:
14475           disp = get32s ();
14476           break;
14477         }
14478
14479       /* In 32bit mode, we need index register to tell [offset] from
14480          [eiz*1 + offset].  */
14481       needindex = (havesib
14482                    && !havebase
14483                    && !haveindex
14484                    && address_mode == mode_32bit);
14485       havedisp = (havebase
14486                   || needindex
14487                   || (havesib && (haveindex || scale != 0)));
14488
14489       if (!intel_syntax)
14490         if (modrm.mod != 0 || base == 5)
14491           {
14492             if (havedisp || riprel)
14493               print_displacement (scratchbuf, disp);
14494             else
14495               print_operand_value (scratchbuf, 1, disp);
14496             oappend (scratchbuf);
14497             if (riprel)
14498               {
14499                 set_op (disp, 1);
14500                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14501               }
14502           }
14503
14504       if ((havebase || haveindex || riprel)
14505           && (bytemode != v_bnd_mode)
14506           && (bytemode != bnd_mode))
14507         used_prefixes |= PREFIX_ADDR;
14508
14509       if (havedisp || (intel_syntax && riprel))
14510         {
14511           *obufp++ = open_char;
14512           if (intel_syntax && riprel)
14513             {
14514               set_op (disp, 1);
14515               oappend (sizeflag & AFLAG ? "rip" : "eip");
14516             }
14517           *obufp = '\0';
14518           if (havebase)
14519             oappend (address_mode == mode_64bit && !addr32flag
14520                      ? names64[rbase] : names32[rbase]);
14521           if (havesib)
14522             {
14523               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14524                  print index to tell base + index from base.  */
14525               if (scale != 0
14526                   || needindex
14527                   || haveindex
14528                   || (havebase && base != ESP_REG_NUM))
14529                 {
14530                   if (!intel_syntax || havebase)
14531                     {
14532                       *obufp++ = separator_char;
14533                       *obufp = '\0';
14534                     }
14535                   if (haveindex)
14536                     oappend (address_mode == mode_64bit && !addr32flag
14537                              ? indexes64[vindex] : indexes32[vindex]);
14538                   else
14539                     oappend (address_mode == mode_64bit && !addr32flag
14540                              ? index64 : index32);
14541
14542                   *obufp++ = scale_char;
14543                   *obufp = '\0';
14544                   sprintf (scratchbuf, "%d", 1 << scale);
14545                   oappend (scratchbuf);
14546                 }
14547             }
14548           if (intel_syntax
14549               && (disp || modrm.mod != 0 || base == 5))
14550             {
14551               if (!havedisp || (bfd_signed_vma) disp >= 0)
14552                 {
14553                   *obufp++ = '+';
14554                   *obufp = '\0';
14555                 }
14556               else if (modrm.mod != 1 && disp != -disp)
14557                 {
14558                   *obufp++ = '-';
14559                   *obufp = '\0';
14560                   disp = - (bfd_signed_vma) disp;
14561                 }
14562
14563               if (havedisp)
14564                 print_displacement (scratchbuf, disp);
14565               else
14566                 print_operand_value (scratchbuf, 1, disp);
14567               oappend (scratchbuf);
14568             }
14569
14570           *obufp++ = close_char;
14571           *obufp = '\0';
14572         }
14573       else if (intel_syntax)
14574         {
14575           if (modrm.mod != 0 || base == 5)
14576             {
14577               if (!active_seg_prefix)
14578                 {
14579                   oappend (names_seg[ds_reg - es_reg]);
14580                   oappend (":");
14581                 }
14582               print_operand_value (scratchbuf, 1, disp);
14583               oappend (scratchbuf);
14584             }
14585         }
14586     }
14587   else
14588     {
14589       /* 16 bit address mode */
14590       used_prefixes |= prefixes & PREFIX_ADDR;
14591       switch (modrm.mod)
14592         {
14593         case 0:
14594           if (modrm.rm == 6)
14595             {
14596               disp = get16 ();
14597               if ((disp & 0x8000) != 0)
14598                 disp -= 0x10000;
14599             }
14600           break;
14601         case 1:
14602           FETCH_DATA (the_info, codep + 1);
14603           disp = *codep++;
14604           if ((disp & 0x80) != 0)
14605             disp -= 0x100;
14606           break;
14607         case 2:
14608           disp = get16 ();
14609           if ((disp & 0x8000) != 0)
14610             disp -= 0x10000;
14611           break;
14612         }
14613
14614       if (!intel_syntax)
14615         if (modrm.mod != 0 || modrm.rm == 6)
14616           {
14617             print_displacement (scratchbuf, disp);
14618             oappend (scratchbuf);
14619           }
14620
14621       if (modrm.mod != 0 || modrm.rm != 6)
14622         {
14623           *obufp++ = open_char;
14624           *obufp = '\0';
14625           oappend (index16[modrm.rm]);
14626           if (intel_syntax
14627               && (disp || modrm.mod != 0 || modrm.rm == 6))
14628             {
14629               if ((bfd_signed_vma) disp >= 0)
14630                 {
14631                   *obufp++ = '+';
14632                   *obufp = '\0';
14633                 }
14634               else if (modrm.mod != 1)
14635                 {
14636                   *obufp++ = '-';
14637                   *obufp = '\0';
14638                   disp = - (bfd_signed_vma) disp;
14639                 }
14640
14641               print_displacement (scratchbuf, disp);
14642               oappend (scratchbuf);
14643             }
14644
14645           *obufp++ = close_char;
14646           *obufp = '\0';
14647         }
14648       else if (intel_syntax)
14649         {
14650           if (!active_seg_prefix)
14651             {
14652               oappend (names_seg[ds_reg - es_reg]);
14653               oappend (":");
14654             }
14655           print_operand_value (scratchbuf, 1, disp & 0xffff);
14656           oappend (scratchbuf);
14657         }
14658     }
14659   if (vex.evex && vex.b
14660       && (bytemode == x_mode
14661           || bytemode == evex_half_bcst_xmmq_mode))
14662     {
14663       if (vex.w || bytemode == evex_half_bcst_xmmq_mode)
14664         oappend ("{1to8}");
14665       else
14666         oappend ("{1to16}");
14667     }
14668 }
14669
14670 static void
14671 OP_E (int bytemode, int sizeflag)
14672 {
14673   /* Skip mod/rm byte.  */
14674   MODRM_CHECK;
14675   codep++;
14676
14677   if (modrm.mod == 3)
14678     OP_E_register (bytemode, sizeflag);
14679   else
14680     OP_E_memory (bytemode, sizeflag);
14681 }
14682
14683 static void
14684 OP_G (int bytemode, int sizeflag)
14685 {
14686   int add = 0;
14687   USED_REX (REX_R);
14688   if (rex & REX_R)
14689     add += 8;
14690   switch (bytemode)
14691     {
14692     case b_mode:
14693       USED_REX (0);
14694       if (rex)
14695         oappend (names8rex[modrm.reg + add]);
14696       else
14697         oappend (names8[modrm.reg + add]);
14698       break;
14699     case w_mode:
14700       oappend (names16[modrm.reg + add]);
14701       break;
14702     case d_mode:
14703       oappend (names32[modrm.reg + add]);
14704       break;
14705     case q_mode:
14706       oappend (names64[modrm.reg + add]);
14707       break;
14708     case bnd_mode:
14709       oappend (names_bnd[modrm.reg]);
14710       break;
14711     case v_mode:
14712     case dq_mode:
14713     case dqb_mode:
14714     case dqd_mode:
14715     case dqw_mode:
14716       USED_REX (REX_W);
14717       if (rex & REX_W)
14718         oappend (names64[modrm.reg + add]);
14719       else
14720         {
14721           if ((sizeflag & DFLAG) || bytemode != v_mode)
14722             oappend (names32[modrm.reg + add]);
14723           else
14724             oappend (names16[modrm.reg + add]);
14725           used_prefixes |= (prefixes & PREFIX_DATA);
14726         }
14727       break;
14728     case m_mode:
14729       if (address_mode == mode_64bit)
14730         oappend (names64[modrm.reg + add]);
14731       else
14732         oappend (names32[modrm.reg + add]);
14733       break;
14734     case mask_mode:
14735       oappend (names_mask[modrm.reg + add]);
14736       break;
14737     default:
14738       oappend (INTERNAL_DISASSEMBLER_ERROR);
14739       break;
14740     }
14741 }
14742
14743 static bfd_vma
14744 get64 (void)
14745 {
14746   bfd_vma x;
14747 #ifdef BFD64
14748   unsigned int a;
14749   unsigned int b;
14750
14751   FETCH_DATA (the_info, codep + 8);
14752   a = *codep++ & 0xff;
14753   a |= (*codep++ & 0xff) << 8;
14754   a |= (*codep++ & 0xff) << 16;
14755   a |= (*codep++ & 0xff) << 24;
14756   b = *codep++ & 0xff;
14757   b |= (*codep++ & 0xff) << 8;
14758   b |= (*codep++ & 0xff) << 16;
14759   b |= (*codep++ & 0xff) << 24;
14760   x = a + ((bfd_vma) b << 32);
14761 #else
14762   abort ();
14763   x = 0;
14764 #endif
14765   return x;
14766 }
14767
14768 static bfd_signed_vma
14769 get32 (void)
14770 {
14771   bfd_signed_vma x = 0;
14772
14773   FETCH_DATA (the_info, codep + 4);
14774   x = *codep++ & (bfd_signed_vma) 0xff;
14775   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14776   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14777   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14778   return x;
14779 }
14780
14781 static bfd_signed_vma
14782 get32s (void)
14783 {
14784   bfd_signed_vma x = 0;
14785
14786   FETCH_DATA (the_info, codep + 4);
14787   x = *codep++ & (bfd_signed_vma) 0xff;
14788   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14789   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14790   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14791
14792   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14793
14794   return x;
14795 }
14796
14797 static int
14798 get16 (void)
14799 {
14800   int x = 0;
14801
14802   FETCH_DATA (the_info, codep + 2);
14803   x = *codep++ & 0xff;
14804   x |= (*codep++ & 0xff) << 8;
14805   return x;
14806 }
14807
14808 static void
14809 set_op (bfd_vma op, int riprel)
14810 {
14811   op_index[op_ad] = op_ad;
14812   if (address_mode == mode_64bit)
14813     {
14814       op_address[op_ad] = op;
14815       op_riprel[op_ad] = riprel;
14816     }
14817   else
14818     {
14819       /* Mask to get a 32-bit address.  */
14820       op_address[op_ad] = op & 0xffffffff;
14821       op_riprel[op_ad] = riprel & 0xffffffff;
14822     }
14823 }
14824
14825 static void
14826 OP_REG (int code, int sizeflag)
14827 {
14828   const char *s;
14829   int add;
14830
14831   switch (code)
14832     {
14833     case es_reg: case ss_reg: case cs_reg:
14834     case ds_reg: case fs_reg: case gs_reg:
14835       oappend (names_seg[code - es_reg]);
14836       return;
14837     }
14838
14839   USED_REX (REX_B);
14840   if (rex & REX_B)
14841     add = 8;
14842   else
14843     add = 0;
14844
14845   switch (code)
14846     {
14847     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14848     case sp_reg: case bp_reg: case si_reg: case di_reg:
14849       s = names16[code - ax_reg + add];
14850       break;
14851     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14852     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14853       USED_REX (0);
14854       if (rex)
14855         s = names8rex[code - al_reg + add];
14856       else
14857         s = names8[code - al_reg];
14858       break;
14859     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14860     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14861       if (address_mode == mode_64bit
14862           && ((sizeflag & DFLAG) || (rex & REX_W)))
14863         {
14864           s = names64[code - rAX_reg + add];
14865           break;
14866         }
14867       code += eAX_reg - rAX_reg;
14868       /* Fall through.  */
14869     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14870     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14871       USED_REX (REX_W);
14872       if (rex & REX_W)
14873         s = names64[code - eAX_reg + add];
14874       else
14875         {
14876           if (sizeflag & DFLAG)
14877             s = names32[code - eAX_reg + add];
14878           else
14879             s = names16[code - eAX_reg + add];
14880           used_prefixes |= (prefixes & PREFIX_DATA);
14881         }
14882       break;
14883     default:
14884       s = INTERNAL_DISASSEMBLER_ERROR;
14885       break;
14886     }
14887   oappend (s);
14888 }
14889
14890 static void
14891 OP_IMREG (int code, int sizeflag)
14892 {
14893   const char *s;
14894
14895   switch (code)
14896     {
14897     case indir_dx_reg:
14898       if (intel_syntax)
14899         s = "dx";
14900       else
14901         s = "(%dx)";
14902       break;
14903     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14904     case sp_reg: case bp_reg: case si_reg: case di_reg:
14905       s = names16[code - ax_reg];
14906       break;
14907     case es_reg: case ss_reg: case cs_reg:
14908     case ds_reg: case fs_reg: case gs_reg:
14909       s = names_seg[code - es_reg];
14910       break;
14911     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14912     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14913       USED_REX (0);
14914       if (rex)
14915         s = names8rex[code - al_reg];
14916       else
14917         s = names8[code - al_reg];
14918       break;
14919     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14920     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14921       USED_REX (REX_W);
14922       if (rex & REX_W)
14923         s = names64[code - eAX_reg];
14924       else
14925         {
14926           if (sizeflag & DFLAG)
14927             s = names32[code - eAX_reg];
14928           else
14929             s = names16[code - eAX_reg];
14930           used_prefixes |= (prefixes & PREFIX_DATA);
14931         }
14932       break;
14933     case z_mode_ax_reg:
14934       if ((rex & REX_W) || (sizeflag & DFLAG))
14935         s = *names32;
14936       else
14937         s = *names16;
14938       if (!(rex & REX_W))
14939         used_prefixes |= (prefixes & PREFIX_DATA);
14940       break;
14941     default:
14942       s = INTERNAL_DISASSEMBLER_ERROR;
14943       break;
14944     }
14945   oappend (s);
14946 }
14947
14948 static void
14949 OP_I (int bytemode, int sizeflag)
14950 {
14951   bfd_signed_vma op;
14952   bfd_signed_vma mask = -1;
14953
14954   switch (bytemode)
14955     {
14956     case b_mode:
14957       FETCH_DATA (the_info, codep + 1);
14958       op = *codep++;
14959       mask = 0xff;
14960       break;
14961     case q_mode:
14962       if (address_mode == mode_64bit)
14963         {
14964           op = get32s ();
14965           break;
14966         }
14967       /* Fall through.  */
14968     case v_mode:
14969       USED_REX (REX_W);
14970       if (rex & REX_W)
14971         op = get32s ();
14972       else
14973         {
14974           if (sizeflag & DFLAG)
14975             {
14976               op = get32 ();
14977               mask = 0xffffffff;
14978             }
14979           else
14980             {
14981               op = get16 ();
14982               mask = 0xfffff;
14983             }
14984           used_prefixes |= (prefixes & PREFIX_DATA);
14985         }
14986       break;
14987     case w_mode:
14988       mask = 0xfffff;
14989       op = get16 ();
14990       break;
14991     case const_1_mode:
14992       if (intel_syntax)
14993         oappend ("1");
14994       return;
14995     default:
14996       oappend (INTERNAL_DISASSEMBLER_ERROR);
14997       return;
14998     }
14999
15000   op &= mask;
15001   scratchbuf[0] = '$';
15002   print_operand_value (scratchbuf + 1, 1, op);
15003   oappend_maybe_intel (scratchbuf);
15004   scratchbuf[0] = '\0';
15005 }
15006
15007 static void
15008 OP_I64 (int bytemode, int sizeflag)
15009 {
15010   bfd_signed_vma op;
15011   bfd_signed_vma mask = -1;
15012
15013   if (address_mode != mode_64bit)
15014     {
15015       OP_I (bytemode, sizeflag);
15016       return;
15017     }
15018
15019   switch (bytemode)
15020     {
15021     case b_mode:
15022       FETCH_DATA (the_info, codep + 1);
15023       op = *codep++;
15024       mask = 0xff;
15025       break;
15026     case v_mode:
15027       USED_REX (REX_W);
15028       if (rex & REX_W)
15029         op = get64 ();
15030       else
15031         {
15032           if (sizeflag & DFLAG)
15033             {
15034               op = get32 ();
15035               mask = 0xffffffff;
15036             }
15037           else
15038             {
15039               op = get16 ();
15040               mask = 0xfffff;
15041             }
15042           used_prefixes |= (prefixes & PREFIX_DATA);
15043         }
15044       break;
15045     case w_mode:
15046       mask = 0xfffff;
15047       op = get16 ();
15048       break;
15049     default:
15050       oappend (INTERNAL_DISASSEMBLER_ERROR);
15051       return;
15052     }
15053
15054   op &= mask;
15055   scratchbuf[0] = '$';
15056   print_operand_value (scratchbuf + 1, 1, op);
15057   oappend_maybe_intel (scratchbuf);
15058   scratchbuf[0] = '\0';
15059 }
15060
15061 static void
15062 OP_sI (int bytemode, int sizeflag)
15063 {
15064   bfd_signed_vma op;
15065
15066   switch (bytemode)
15067     {
15068     case b_mode:
15069     case b_T_mode:
15070       FETCH_DATA (the_info, codep + 1);
15071       op = *codep++;
15072       if ((op & 0x80) != 0)
15073         op -= 0x100;
15074       if (bytemode == b_T_mode)
15075         {
15076           if (address_mode != mode_64bit
15077               || !((sizeflag & DFLAG) || (rex & REX_W)))
15078             {
15079               /* The operand-size prefix is overridden by a REX prefix.  */
15080               if ((sizeflag & DFLAG) || (rex & REX_W))
15081                 op &= 0xffffffff;
15082               else
15083                 op &= 0xffff;
15084           }
15085         }
15086       else
15087         {
15088           if (!(rex & REX_W))
15089             {
15090               if (sizeflag & DFLAG)
15091                 op &= 0xffffffff;
15092               else
15093                 op &= 0xffff;
15094             }
15095         }
15096       break;
15097     case v_mode:
15098       /* The operand-size prefix is overridden by a REX prefix.  */
15099       if ((sizeflag & DFLAG) || (rex & REX_W))
15100         op = get32s ();
15101       else
15102         op = get16 ();
15103       break;
15104     default:
15105       oappend (INTERNAL_DISASSEMBLER_ERROR);
15106       return;
15107     }
15108
15109   scratchbuf[0] = '$';
15110   print_operand_value (scratchbuf + 1, 1, op);
15111   oappend_maybe_intel (scratchbuf);
15112 }
15113
15114 static void
15115 OP_J (int bytemode, int sizeflag)
15116 {
15117   bfd_vma disp;
15118   bfd_vma mask = -1;
15119   bfd_vma segment = 0;
15120
15121   switch (bytemode)
15122     {
15123     case b_mode:
15124       FETCH_DATA (the_info, codep + 1);
15125       disp = *codep++;
15126       if ((disp & 0x80) != 0)
15127         disp -= 0x100;
15128       break;
15129     case v_mode:
15130       USED_REX (REX_W);
15131       if ((sizeflag & DFLAG) || (rex & REX_W))
15132         disp = get32s ();
15133       else
15134         {
15135           disp = get16 ();
15136           if ((disp & 0x8000) != 0)
15137             disp -= 0x10000;
15138           /* In 16bit mode, address is wrapped around at 64k within
15139              the same segment.  Otherwise, a data16 prefix on a jump
15140              instruction means that the pc is masked to 16 bits after
15141              the displacement is added!  */
15142           mask = 0xffff;
15143           if ((prefixes & PREFIX_DATA) == 0)
15144             segment = ((start_pc + codep - start_codep)
15145                        & ~((bfd_vma) 0xffff));
15146         }
15147       if (!(rex & REX_W))
15148         used_prefixes |= (prefixes & PREFIX_DATA);
15149       break;
15150     default:
15151       oappend (INTERNAL_DISASSEMBLER_ERROR);
15152       return;
15153     }
15154   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15155   set_op (disp, 0);
15156   print_operand_value (scratchbuf, 1, disp);
15157   oappend (scratchbuf);
15158 }
15159
15160 static void
15161 OP_SEG (int bytemode, int sizeflag)
15162 {
15163   if (bytemode == w_mode)
15164     oappend (names_seg[modrm.reg]);
15165   else
15166     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15167 }
15168
15169 static void
15170 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15171 {
15172   int seg, offset;
15173
15174   if (sizeflag & DFLAG)
15175     {
15176       offset = get32 ();
15177       seg = get16 ();
15178     }
15179   else
15180     {
15181       offset = get16 ();
15182       seg = get16 ();
15183     }
15184   used_prefixes |= (prefixes & PREFIX_DATA);
15185   if (intel_syntax)
15186     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15187   else
15188     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15189   oappend (scratchbuf);
15190 }
15191
15192 static void
15193 OP_OFF (int bytemode, int sizeflag)
15194 {
15195   bfd_vma off;
15196
15197   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15198     intel_operand_size (bytemode, sizeflag);
15199   append_seg ();
15200
15201   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15202     off = get32 ();
15203   else
15204     off = get16 ();
15205
15206   if (intel_syntax)
15207     {
15208       if (!active_seg_prefix)
15209         {
15210           oappend (names_seg[ds_reg - es_reg]);
15211           oappend (":");
15212         }
15213     }
15214   print_operand_value (scratchbuf, 1, off);
15215   oappend (scratchbuf);
15216 }
15217
15218 static void
15219 OP_OFF64 (int bytemode, int sizeflag)
15220 {
15221   bfd_vma off;
15222
15223   if (address_mode != mode_64bit
15224       || (prefixes & PREFIX_ADDR))
15225     {
15226       OP_OFF (bytemode, sizeflag);
15227       return;
15228     }
15229
15230   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15231     intel_operand_size (bytemode, sizeflag);
15232   append_seg ();
15233
15234   off = get64 ();
15235
15236   if (intel_syntax)
15237     {
15238       if (!active_seg_prefix)
15239         {
15240           oappend (names_seg[ds_reg - es_reg]);
15241           oappend (":");
15242         }
15243     }
15244   print_operand_value (scratchbuf, 1, off);
15245   oappend (scratchbuf);
15246 }
15247
15248 static void
15249 ptr_reg (int code, int sizeflag)
15250 {
15251   const char *s;
15252
15253   *obufp++ = open_char;
15254   used_prefixes |= (prefixes & PREFIX_ADDR);
15255   if (address_mode == mode_64bit)
15256     {
15257       if (!(sizeflag & AFLAG))
15258         s = names32[code - eAX_reg];
15259       else
15260         s = names64[code - eAX_reg];
15261     }
15262   else if (sizeflag & AFLAG)
15263     s = names32[code - eAX_reg];
15264   else
15265     s = names16[code - eAX_reg];
15266   oappend (s);
15267   *obufp++ = close_char;
15268   *obufp = 0;
15269 }
15270
15271 static void
15272 OP_ESreg (int code, int sizeflag)
15273 {
15274   if (intel_syntax)
15275     {
15276       switch (codep[-1])
15277         {
15278         case 0x6d:      /* insw/insl */
15279           intel_operand_size (z_mode, sizeflag);
15280           break;
15281         case 0xa5:      /* movsw/movsl/movsq */
15282         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15283         case 0xab:      /* stosw/stosl */
15284         case 0xaf:      /* scasw/scasl */
15285           intel_operand_size (v_mode, sizeflag);
15286           break;
15287         default:
15288           intel_operand_size (b_mode, sizeflag);
15289         }
15290     }
15291   oappend_maybe_intel ("%es:");
15292   ptr_reg (code, sizeflag);
15293 }
15294
15295 static void
15296 OP_DSreg (int code, int sizeflag)
15297 {
15298   if (intel_syntax)
15299     {
15300       switch (codep[-1])
15301         {
15302         case 0x6f:      /* outsw/outsl */
15303           intel_operand_size (z_mode, sizeflag);
15304           break;
15305         case 0xa5:      /* movsw/movsl/movsq */
15306         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15307         case 0xad:      /* lodsw/lodsl/lodsq */
15308           intel_operand_size (v_mode, sizeflag);
15309           break;
15310         default:
15311           intel_operand_size (b_mode, sizeflag);
15312         }
15313     }
15314   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15315      default segment register DS is printed.  */
15316   if (!active_seg_prefix)
15317     active_seg_prefix = PREFIX_DS;
15318   append_seg ();
15319   ptr_reg (code, sizeflag);
15320 }
15321
15322 static void
15323 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15324 {
15325   int add;
15326   if (rex & REX_R)
15327     {
15328       USED_REX (REX_R);
15329       add = 8;
15330     }
15331   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15332     {
15333       all_prefixes[last_lock_prefix] = 0;
15334       used_prefixes |= PREFIX_LOCK;
15335       add = 8;
15336     }
15337   else
15338     add = 0;
15339   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15340   oappend_maybe_intel (scratchbuf);
15341 }
15342
15343 static void
15344 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15345 {
15346   int add;
15347   USED_REX (REX_R);
15348   if (rex & REX_R)
15349     add = 8;
15350   else
15351     add = 0;
15352   if (intel_syntax)
15353     sprintf (scratchbuf, "db%d", modrm.reg + add);
15354   else
15355     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15356   oappend (scratchbuf);
15357 }
15358
15359 static void
15360 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15361 {
15362   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15363   oappend_maybe_intel (scratchbuf);
15364 }
15365
15366 static void
15367 OP_R (int bytemode, int sizeflag)
15368 {
15369   if (modrm.mod == 3)
15370     OP_E (bytemode, sizeflag);
15371   else
15372     BadOp ();
15373 }
15374
15375 static void
15376 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15377 {
15378   int reg = modrm.reg;
15379   const char **names;
15380
15381   used_prefixes |= (prefixes & PREFIX_DATA);
15382   if (prefixes & PREFIX_DATA)
15383     {
15384       names = names_xmm;
15385       USED_REX (REX_R);
15386       if (rex & REX_R)
15387         reg += 8;
15388     }
15389   else
15390     names = names_mm;
15391   oappend (names[reg]);
15392 }
15393
15394 static void
15395 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15396 {
15397   int reg = modrm.reg;
15398   const char **names;
15399
15400   USED_REX (REX_R);
15401   if (rex & REX_R)
15402     reg += 8;
15403   if (vex.evex)
15404     {
15405       if (!vex.r)
15406         reg += 16;
15407     }
15408
15409   if (need_vex
15410       && bytemode != xmm_mode
15411       && bytemode != xmmq_mode
15412       && bytemode != evex_half_bcst_xmmq_mode
15413       && bytemode != ymm_mode
15414       && bytemode != scalar_mode)
15415     {
15416       switch (vex.length)
15417         {
15418         case 128:
15419           names = names_xmm;
15420           break;
15421         case 256:
15422           if (vex.w
15423               || (bytemode != vex_vsib_q_w_dq_mode
15424                   && bytemode != vex_vsib_q_w_d_mode))
15425             names = names_ymm;
15426           else
15427             names = names_xmm;
15428           break;
15429         case 512:
15430           names = names_zmm;
15431           break;
15432         default:
15433           abort ();
15434         }
15435     }
15436   else if (bytemode == xmmq_mode
15437            || bytemode == evex_half_bcst_xmmq_mode)
15438     {
15439       switch (vex.length)
15440         {
15441         case 128:
15442         case 256:
15443           names = names_xmm;
15444           break;
15445         case 512:
15446           names = names_ymm;
15447           break;
15448         default:
15449           abort ();
15450         }
15451     }
15452   else if (bytemode == ymm_mode)
15453     names = names_ymm;
15454   else
15455     names = names_xmm;
15456   oappend (names[reg]);
15457 }
15458
15459 static void
15460 OP_EM (int bytemode, int sizeflag)
15461 {
15462   int reg;
15463   const char **names;
15464
15465   if (modrm.mod != 3)
15466     {
15467       if (intel_syntax
15468           && (bytemode == v_mode || bytemode == v_swap_mode))
15469         {
15470           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15471           used_prefixes |= (prefixes & PREFIX_DATA);
15472         }
15473       OP_E (bytemode, sizeflag);
15474       return;
15475     }
15476
15477   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15478     swap_operand ();
15479
15480   /* Skip mod/rm byte.  */
15481   MODRM_CHECK;
15482   codep++;
15483   used_prefixes |= (prefixes & PREFIX_DATA);
15484   reg = modrm.rm;
15485   if (prefixes & PREFIX_DATA)
15486     {
15487       names = names_xmm;
15488       USED_REX (REX_B);
15489       if (rex & REX_B)
15490         reg += 8;
15491     }
15492   else
15493     names = names_mm;
15494   oappend (names[reg]);
15495 }
15496
15497 /* cvt* are the only instructions in sse2 which have
15498    both SSE and MMX operands and also have 0x66 prefix
15499    in their opcode. 0x66 was originally used to differentiate
15500    between SSE and MMX instruction(operands). So we have to handle the
15501    cvt* separately using OP_EMC and OP_MXC */
15502 static void
15503 OP_EMC (int bytemode, int sizeflag)
15504 {
15505   if (modrm.mod != 3)
15506     {
15507       if (intel_syntax && bytemode == v_mode)
15508         {
15509           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15510           used_prefixes |= (prefixes & PREFIX_DATA);
15511         }
15512       OP_E (bytemode, sizeflag);
15513       return;
15514     }
15515
15516   /* Skip mod/rm byte.  */
15517   MODRM_CHECK;
15518   codep++;
15519   used_prefixes |= (prefixes & PREFIX_DATA);
15520   oappend (names_mm[modrm.rm]);
15521 }
15522
15523 static void
15524 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15525 {
15526   used_prefixes |= (prefixes & PREFIX_DATA);
15527   oappend (names_mm[modrm.reg]);
15528 }
15529
15530 static void
15531 OP_EX (int bytemode, int sizeflag)
15532 {
15533   int reg;
15534   const char **names;
15535
15536   /* Skip mod/rm byte.  */
15537   MODRM_CHECK;
15538   codep++;
15539
15540   if (modrm.mod != 3)
15541     {
15542       OP_E_memory (bytemode, sizeflag);
15543       return;
15544     }
15545
15546   reg = modrm.rm;
15547   USED_REX (REX_B);
15548   if (rex & REX_B)
15549     reg += 8;
15550   if (vex.evex)
15551     {
15552       USED_REX (REX_X);
15553       if ((rex & REX_X))
15554         reg += 16;
15555     }
15556
15557   if ((sizeflag & SUFFIX_ALWAYS)
15558       && (bytemode == x_swap_mode
15559           || bytemode == d_swap_mode
15560           || bytemode == d_scalar_swap_mode
15561           || bytemode == q_swap_mode
15562           || bytemode == q_scalar_swap_mode))
15563     swap_operand ();
15564
15565   if (need_vex
15566       && bytemode != xmm_mode
15567       && bytemode != xmmdw_mode
15568       && bytemode != xmmqd_mode
15569       && bytemode != xmm_mb_mode
15570       && bytemode != xmm_mw_mode
15571       && bytemode != xmm_md_mode
15572       && bytemode != xmm_mq_mode
15573       && bytemode != xmm_mdq_mode
15574       && bytemode != xmmq_mode
15575       && bytemode != evex_half_bcst_xmmq_mode
15576       && bytemode != ymm_mode
15577       && bytemode != d_scalar_mode
15578       && bytemode != d_scalar_swap_mode
15579       && bytemode != q_scalar_mode
15580       && bytemode != q_scalar_swap_mode
15581       && bytemode != vex_scalar_w_dq_mode)
15582     {
15583       switch (vex.length)
15584         {
15585         case 128:
15586           names = names_xmm;
15587           break;
15588         case 256:
15589           names = names_ymm;
15590           break;
15591         case 512:
15592           names = names_zmm;
15593           break;
15594         default:
15595           abort ();
15596         }
15597     }
15598   else if (bytemode == xmmq_mode
15599            || bytemode == evex_half_bcst_xmmq_mode)
15600     {
15601       switch (vex.length)
15602         {
15603         case 128:
15604         case 256:
15605           names = names_xmm;
15606           break;
15607         case 512:
15608           names = names_ymm;
15609           break;
15610         default:
15611           abort ();
15612         }
15613     }
15614   else if (bytemode == ymm_mode)
15615     names = names_ymm;
15616   else
15617     names = names_xmm;
15618   oappend (names[reg]);
15619 }
15620
15621 static void
15622 OP_MS (int bytemode, int sizeflag)
15623 {
15624   if (modrm.mod == 3)
15625     OP_EM (bytemode, sizeflag);
15626   else
15627     BadOp ();
15628 }
15629
15630 static void
15631 OP_XS (int bytemode, int sizeflag)
15632 {
15633   if (modrm.mod == 3)
15634     OP_EX (bytemode, sizeflag);
15635   else
15636     BadOp ();
15637 }
15638
15639 static void
15640 OP_M (int bytemode, int sizeflag)
15641 {
15642   if (modrm.mod == 3)
15643     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15644     BadOp ();
15645   else
15646     OP_E (bytemode, sizeflag);
15647 }
15648
15649 static void
15650 OP_0f07 (int bytemode, int sizeflag)
15651 {
15652   if (modrm.mod != 3 || modrm.rm != 0)
15653     BadOp ();
15654   else
15655     OP_E (bytemode, sizeflag);
15656 }
15657
15658 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15659    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15660
15661 static void
15662 NOP_Fixup1 (int bytemode, int sizeflag)
15663 {
15664   if ((prefixes & PREFIX_DATA) != 0
15665       || (rex != 0
15666           && rex != 0x48
15667           && address_mode == mode_64bit))
15668     OP_REG (bytemode, sizeflag);
15669   else
15670     strcpy (obuf, "nop");
15671 }
15672
15673 static void
15674 NOP_Fixup2 (int bytemode, int sizeflag)
15675 {
15676   if ((prefixes & PREFIX_DATA) != 0
15677       || (rex != 0
15678           && rex != 0x48
15679           && address_mode == mode_64bit))
15680     OP_IMREG (bytemode, sizeflag);
15681 }
15682
15683 static const char *const Suffix3DNow[] = {
15684 /* 00 */        NULL,           NULL,           NULL,           NULL,
15685 /* 04 */        NULL,           NULL,           NULL,           NULL,
15686 /* 08 */        NULL,           NULL,           NULL,           NULL,
15687 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15688 /* 10 */        NULL,           NULL,           NULL,           NULL,
15689 /* 14 */        NULL,           NULL,           NULL,           NULL,
15690 /* 18 */        NULL,           NULL,           NULL,           NULL,
15691 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15692 /* 20 */        NULL,           NULL,           NULL,           NULL,
15693 /* 24 */        NULL,           NULL,           NULL,           NULL,
15694 /* 28 */        NULL,           NULL,           NULL,           NULL,
15695 /* 2C */        NULL,           NULL,           NULL,           NULL,
15696 /* 30 */        NULL,           NULL,           NULL,           NULL,
15697 /* 34 */        NULL,           NULL,           NULL,           NULL,
15698 /* 38 */        NULL,           NULL,           NULL,           NULL,
15699 /* 3C */        NULL,           NULL,           NULL,           NULL,
15700 /* 40 */        NULL,           NULL,           NULL,           NULL,
15701 /* 44 */        NULL,           NULL,           NULL,           NULL,
15702 /* 48 */        NULL,           NULL,           NULL,           NULL,
15703 /* 4C */        NULL,           NULL,           NULL,           NULL,
15704 /* 50 */        NULL,           NULL,           NULL,           NULL,
15705 /* 54 */        NULL,           NULL,           NULL,           NULL,
15706 /* 58 */        NULL,           NULL,           NULL,           NULL,
15707 /* 5C */        NULL,           NULL,           NULL,           NULL,
15708 /* 60 */        NULL,           NULL,           NULL,           NULL,
15709 /* 64 */        NULL,           NULL,           NULL,           NULL,
15710 /* 68 */        NULL,           NULL,           NULL,           NULL,
15711 /* 6C */        NULL,           NULL,           NULL,           NULL,
15712 /* 70 */        NULL,           NULL,           NULL,           NULL,
15713 /* 74 */        NULL,           NULL,           NULL,           NULL,
15714 /* 78 */        NULL,           NULL,           NULL,           NULL,
15715 /* 7C */        NULL,           NULL,           NULL,           NULL,
15716 /* 80 */        NULL,           NULL,           NULL,           NULL,
15717 /* 84 */        NULL,           NULL,           NULL,           NULL,
15718 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15719 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15720 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15721 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15722 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15723 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15724 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15725 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15726 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15727 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15728 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15729 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15730 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15731 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15732 /* C0 */        NULL,           NULL,           NULL,           NULL,
15733 /* C4 */        NULL,           NULL,           NULL,           NULL,
15734 /* C8 */        NULL,           NULL,           NULL,           NULL,
15735 /* CC */        NULL,           NULL,           NULL,           NULL,
15736 /* D0 */        NULL,           NULL,           NULL,           NULL,
15737 /* D4 */        NULL,           NULL,           NULL,           NULL,
15738 /* D8 */        NULL,           NULL,           NULL,           NULL,
15739 /* DC */        NULL,           NULL,           NULL,           NULL,
15740 /* E0 */        NULL,           NULL,           NULL,           NULL,
15741 /* E4 */        NULL,           NULL,           NULL,           NULL,
15742 /* E8 */        NULL,           NULL,           NULL,           NULL,
15743 /* EC */        NULL,           NULL,           NULL,           NULL,
15744 /* F0 */        NULL,           NULL,           NULL,           NULL,
15745 /* F4 */        NULL,           NULL,           NULL,           NULL,
15746 /* F8 */        NULL,           NULL,           NULL,           NULL,
15747 /* FC */        NULL,           NULL,           NULL,           NULL,
15748 };
15749
15750 static void
15751 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15752 {
15753   const char *mnemonic;
15754
15755   FETCH_DATA (the_info, codep + 1);
15756   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15757      place where an 8-bit immediate would normally go.  ie. the last
15758      byte of the instruction.  */
15759   obufp = mnemonicendp;
15760   mnemonic = Suffix3DNow[*codep++ & 0xff];
15761   if (mnemonic)
15762     oappend (mnemonic);
15763   else
15764     {
15765       /* Since a variable sized modrm/sib chunk is between the start
15766          of the opcode (0x0f0f) and the opcode suffix, we need to do
15767          all the modrm processing first, and don't know until now that
15768          we have a bad opcode.  This necessitates some cleaning up.  */
15769       op_out[0][0] = '\0';
15770       op_out[1][0] = '\0';
15771       BadOp ();
15772     }
15773   mnemonicendp = obufp;
15774 }
15775
15776 static struct op simd_cmp_op[] =
15777 {
15778   { STRING_COMMA_LEN ("eq") },
15779   { STRING_COMMA_LEN ("lt") },
15780   { STRING_COMMA_LEN ("le") },
15781   { STRING_COMMA_LEN ("unord") },
15782   { STRING_COMMA_LEN ("neq") },
15783   { STRING_COMMA_LEN ("nlt") },
15784   { STRING_COMMA_LEN ("nle") },
15785   { STRING_COMMA_LEN ("ord") }
15786 };
15787
15788 static void
15789 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15790 {
15791   unsigned int cmp_type;
15792
15793   FETCH_DATA (the_info, codep + 1);
15794   cmp_type = *codep++ & 0xff;
15795   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15796     {
15797       char suffix [3];
15798       char *p = mnemonicendp - 2;
15799       suffix[0] = p[0];
15800       suffix[1] = p[1];
15801       suffix[2] = '\0';
15802       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15803       mnemonicendp += simd_cmp_op[cmp_type].len;
15804     }
15805   else
15806     {
15807       /* We have a reserved extension byte.  Output it directly.  */
15808       scratchbuf[0] = '$';
15809       print_operand_value (scratchbuf + 1, 1, cmp_type);
15810       oappend_maybe_intel (scratchbuf);
15811       scratchbuf[0] = '\0';
15812     }
15813 }
15814
15815 static void
15816 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15817           int sizeflag ATTRIBUTE_UNUSED)
15818 {
15819   /* mwait %eax,%ecx  */
15820   if (!intel_syntax)
15821     {
15822       const char **names = (address_mode == mode_64bit
15823                             ? names64 : names32);
15824       strcpy (op_out[0], names[0]);
15825       strcpy (op_out[1], names[1]);
15826       two_source_ops = 1;
15827     }
15828   /* Skip mod/rm byte.  */
15829   MODRM_CHECK;
15830   codep++;
15831 }
15832
15833 static void
15834 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15835             int sizeflag ATTRIBUTE_UNUSED)
15836 {
15837   /* monitor %eax,%ecx,%edx"  */
15838   if (!intel_syntax)
15839     {
15840       const char **op1_names;
15841       const char **names = (address_mode == mode_64bit
15842                             ? names64 : names32);
15843
15844       if (!(prefixes & PREFIX_ADDR))
15845         op1_names = (address_mode == mode_16bit
15846                      ? names16 : names);
15847       else
15848         {
15849           /* Remove "addr16/addr32".  */
15850           all_prefixes[last_addr_prefix] = 0;
15851           op1_names = (address_mode != mode_32bit
15852                        ? names32 : names16);
15853           used_prefixes |= PREFIX_ADDR;
15854         }
15855       strcpy (op_out[0], op1_names[0]);
15856       strcpy (op_out[1], names[1]);
15857       strcpy (op_out[2], names[2]);
15858       two_source_ops = 1;
15859     }
15860   /* Skip mod/rm byte.  */
15861   MODRM_CHECK;
15862   codep++;
15863 }
15864
15865 static void
15866 BadOp (void)
15867 {
15868   /* Throw away prefixes and 1st. opcode byte.  */
15869   codep = insn_codep + 1;
15870   oappend ("(bad)");
15871 }
15872
15873 static void
15874 REP_Fixup (int bytemode, int sizeflag)
15875 {
15876   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15877      lods and stos.  */
15878   if (prefixes & PREFIX_REPZ)
15879     all_prefixes[last_repz_prefix] = REP_PREFIX;
15880
15881   switch (bytemode)
15882     {
15883     case al_reg:
15884     case eAX_reg:
15885     case indir_dx_reg:
15886       OP_IMREG (bytemode, sizeflag);
15887       break;
15888     case eDI_reg:
15889       OP_ESreg (bytemode, sizeflag);
15890       break;
15891     case eSI_reg:
15892       OP_DSreg (bytemode, sizeflag);
15893       break;
15894     default:
15895       abort ();
15896       break;
15897     }
15898 }
15899
15900 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15901    "bnd".  */
15902
15903 static void
15904 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15905 {
15906   if (prefixes & PREFIX_REPNZ)
15907     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15908 }
15909
15910 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15911    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15912  */
15913
15914 static void
15915 HLE_Fixup1 (int bytemode, int sizeflag)
15916 {
15917   if (modrm.mod != 3
15918       && (prefixes & PREFIX_LOCK) != 0)
15919     {
15920       if (prefixes & PREFIX_REPZ)
15921         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15922       if (prefixes & PREFIX_REPNZ)
15923         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15924     }
15925
15926   OP_E (bytemode, sizeflag);
15927 }
15928
15929 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15930    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15931  */
15932
15933 static void
15934 HLE_Fixup2 (int bytemode, int sizeflag)
15935 {
15936   if (modrm.mod != 3)
15937     {
15938       if (prefixes & PREFIX_REPZ)
15939         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15940       if (prefixes & PREFIX_REPNZ)
15941         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15942     }
15943
15944   OP_E (bytemode, sizeflag);
15945 }
15946
15947 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15948    "xrelease" for memory operand.  No check for LOCK prefix.   */
15949
15950 static void
15951 HLE_Fixup3 (int bytemode, int sizeflag)
15952 {
15953   if (modrm.mod != 3
15954       && last_repz_prefix > last_repnz_prefix
15955       && (prefixes & PREFIX_REPZ) != 0)
15956     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15957
15958   OP_E (bytemode, sizeflag);
15959 }
15960
15961 static void
15962 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15963 {
15964   USED_REX (REX_W);
15965   if (rex & REX_W)
15966     {
15967       /* Change cmpxchg8b to cmpxchg16b.  */
15968       char *p = mnemonicendp - 2;
15969       mnemonicendp = stpcpy (p, "16b");
15970       bytemode = o_mode;
15971     }
15972   else if ((prefixes & PREFIX_LOCK) != 0)
15973     {
15974       if (prefixes & PREFIX_REPZ)
15975         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15976       if (prefixes & PREFIX_REPNZ)
15977         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15978     }
15979
15980   OP_M (bytemode, sizeflag);
15981 }
15982
15983 static void
15984 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15985 {
15986   const char **names;
15987
15988   if (need_vex)
15989     {
15990       switch (vex.length)
15991         {
15992         case 128:
15993           names = names_xmm;
15994           break;
15995         case 256:
15996           names = names_ymm;
15997           break;
15998         default:
15999           abort ();
16000         }
16001     }
16002   else
16003     names = names_xmm;
16004   oappend (names[reg]);
16005 }
16006
16007 static void
16008 CRC32_Fixup (int bytemode, int sizeflag)
16009 {
16010   /* Add proper suffix to "crc32".  */
16011   char *p = mnemonicendp;
16012
16013   switch (bytemode)
16014     {
16015     case b_mode:
16016       if (intel_syntax)
16017         goto skip;
16018
16019       *p++ = 'b';
16020       break;
16021     case v_mode:
16022       if (intel_syntax)
16023         goto skip;
16024
16025       USED_REX (REX_W);
16026       if (rex & REX_W)
16027         *p++ = 'q';
16028       else
16029         {
16030           if (sizeflag & DFLAG)
16031             *p++ = 'l';
16032           else
16033             *p++ = 'w';
16034           used_prefixes |= (prefixes & PREFIX_DATA);
16035         }
16036       break;
16037     default:
16038       oappend (INTERNAL_DISASSEMBLER_ERROR);
16039       break;
16040     }
16041   mnemonicendp = p;
16042   *p = '\0';
16043
16044 skip:
16045   if (modrm.mod == 3)
16046     {
16047       int add;
16048
16049       /* Skip mod/rm byte.  */
16050       MODRM_CHECK;
16051       codep++;
16052
16053       USED_REX (REX_B);
16054       add = (rex & REX_B) ? 8 : 0;
16055       if (bytemode == b_mode)
16056         {
16057           USED_REX (0);
16058           if (rex)
16059             oappend (names8rex[modrm.rm + add]);
16060           else
16061             oappend (names8[modrm.rm + add]);
16062         }
16063       else
16064         {
16065           USED_REX (REX_W);
16066           if (rex & REX_W)
16067             oappend (names64[modrm.rm + add]);
16068           else if ((prefixes & PREFIX_DATA))
16069             oappend (names16[modrm.rm + add]);
16070           else
16071             oappend (names32[modrm.rm + add]);
16072         }
16073     }
16074   else
16075     OP_E (bytemode, sizeflag);
16076 }
16077
16078 static void
16079 FXSAVE_Fixup (int bytemode, int sizeflag)
16080 {
16081   /* Add proper suffix to "fxsave" and "fxrstor".  */
16082   USED_REX (REX_W);
16083   if (rex & REX_W)
16084     {
16085       char *p = mnemonicendp;
16086       *p++ = '6';
16087       *p++ = '4';
16088       *p = '\0';
16089       mnemonicendp = p;
16090     }
16091   OP_M (bytemode, sizeflag);
16092 }
16093
16094 /* Display the destination register operand for instructions with
16095    VEX. */
16096
16097 static void
16098 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16099 {
16100   int reg;
16101   const char **names;
16102
16103   if (!need_vex)
16104     abort ();
16105
16106   if (!need_vex_reg)
16107     return;
16108
16109   reg = vex.register_specifier;
16110   if (vex.evex)
16111     {
16112       if (!vex.v)
16113         reg += 16;
16114     }
16115
16116   if (bytemode == vex_scalar_mode)
16117     {
16118       oappend (names_xmm[reg]);
16119       return;
16120     }
16121
16122   switch (vex.length)
16123     {
16124     case 128:
16125       switch (bytemode)
16126         {
16127         case vex_mode:
16128         case vex128_mode:
16129         case vex_vsib_q_w_dq_mode:
16130         case vex_vsib_q_w_d_mode:
16131           names = names_xmm;
16132           break;
16133         case dq_mode:
16134           if (vex.w)
16135             names = names64;
16136           else
16137             names = names32;
16138           break;
16139         case mask_mode:
16140           names = names_mask;
16141           break;
16142         default:
16143           abort ();
16144           return;
16145         }
16146       break;
16147     case 256:
16148       switch (bytemode)
16149         {
16150         case vex_mode:
16151         case vex256_mode:
16152           names = names_ymm;
16153           break;
16154         case vex_vsib_q_w_dq_mode:
16155         case vex_vsib_q_w_d_mode:
16156           names = vex.w ? names_ymm : names_xmm;
16157           break;
16158         case mask_mode:
16159           names = names_mask;
16160           break;
16161         default:
16162           abort ();
16163           return;
16164         }
16165       break;
16166     case 512:
16167       names = names_zmm;
16168       break;
16169     default:
16170       abort ();
16171       break;
16172     }
16173   oappend (names[reg]);
16174 }
16175
16176 /* Get the VEX immediate byte without moving codep.  */
16177
16178 static unsigned char
16179 get_vex_imm8 (int sizeflag, int opnum)
16180 {
16181   int bytes_before_imm = 0;
16182
16183   if (modrm.mod != 3)
16184     {
16185       /* There are SIB/displacement bytes.  */
16186       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16187         {
16188           /* 32/64 bit address mode */
16189           int base = modrm.rm;
16190
16191           /* Check SIB byte.  */
16192           if (base == 4)
16193             {
16194               FETCH_DATA (the_info, codep + 1);
16195               base = *codep & 7;
16196               /* When decoding the third source, don't increase
16197                  bytes_before_imm as this has already been incremented
16198                  by one in OP_E_memory while decoding the second
16199                  source operand.  */
16200               if (opnum == 0)
16201                 bytes_before_imm++;
16202             }
16203
16204           /* Don't increase bytes_before_imm when decoding the third source,
16205              it has already been incremented by OP_E_memory while decoding
16206              the second source operand.  */
16207           if (opnum == 0)
16208             {
16209               switch (modrm.mod)
16210                 {
16211                   case 0:
16212                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16213                        SIB == 5, there is a 4 byte displacement.  */
16214                     if (base != 5)
16215                       /* No displacement. */
16216                       break;
16217                   case 2:
16218                     /* 4 byte displacement.  */
16219                     bytes_before_imm += 4;
16220                     break;
16221                   case 1:
16222                     /* 1 byte displacement.  */
16223                     bytes_before_imm++;
16224                     break;
16225                 }
16226             }
16227         }
16228       else
16229         {
16230           /* 16 bit address mode */
16231           /* Don't increase bytes_before_imm when decoding the third source,
16232              it has already been incremented by OP_E_memory while decoding
16233              the second source operand.  */
16234           if (opnum == 0)
16235             {
16236               switch (modrm.mod)
16237                 {
16238                 case 0:
16239                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16240                   if (modrm.rm != 6)
16241                     /* No displacement. */
16242                     break;
16243                 case 2:
16244                   /* 2 byte displacement.  */
16245                   bytes_before_imm += 2;
16246                   break;
16247                 case 1:
16248                   /* 1 byte displacement: when decoding the third source,
16249                      don't increase bytes_before_imm as this has already
16250                      been incremented by one in OP_E_memory while decoding
16251                      the second source operand.  */
16252                   if (opnum == 0)
16253                     bytes_before_imm++;
16254
16255                   break;
16256                 }
16257             }
16258         }
16259     }
16260
16261   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16262   return codep [bytes_before_imm];
16263 }
16264
16265 static void
16266 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16267 {
16268   const char **names;
16269
16270   if (reg == -1 && modrm.mod != 3)
16271     {
16272       OP_E_memory (bytemode, sizeflag);
16273       return;
16274     }
16275   else
16276     {
16277       if (reg == -1)
16278         {
16279           reg = modrm.rm;
16280           USED_REX (REX_B);
16281           if (rex & REX_B)
16282             reg += 8;
16283         }
16284       else if (reg > 7 && address_mode != mode_64bit)
16285         BadOp ();
16286     }
16287
16288   switch (vex.length)
16289     {
16290     case 128:
16291       names = names_xmm;
16292       break;
16293     case 256:
16294       names = names_ymm;
16295       break;
16296     default:
16297       abort ();
16298     }
16299   oappend (names[reg]);
16300 }
16301
16302 static void
16303 OP_EX_VexImmW (int bytemode, int sizeflag)
16304 {
16305   int reg = -1;
16306   static unsigned char vex_imm8;
16307
16308   if (vex_w_done == 0)
16309     {
16310       vex_w_done = 1;
16311
16312       /* Skip mod/rm byte.  */
16313       MODRM_CHECK;
16314       codep++;
16315
16316       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16317
16318       if (vex.w)
16319           reg = vex_imm8 >> 4;
16320
16321       OP_EX_VexReg (bytemode, sizeflag, reg);
16322     }
16323   else if (vex_w_done == 1)
16324     {
16325       vex_w_done = 2;
16326
16327       if (!vex.w)
16328           reg = vex_imm8 >> 4;
16329
16330       OP_EX_VexReg (bytemode, sizeflag, reg);
16331     }
16332   else
16333     {
16334       /* Output the imm8 directly.  */
16335       scratchbuf[0] = '$';
16336       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16337       oappend_maybe_intel (scratchbuf);
16338       scratchbuf[0] = '\0';
16339       codep++;
16340     }
16341 }
16342
16343 static void
16344 OP_Vex_2src (int bytemode, int sizeflag)
16345 {
16346   if (modrm.mod == 3)
16347     {
16348       int reg = modrm.rm;
16349       USED_REX (REX_B);
16350       if (rex & REX_B)
16351         reg += 8;
16352       oappend (names_xmm[reg]);
16353     }
16354   else
16355     {
16356       if (intel_syntax
16357           && (bytemode == v_mode || bytemode == v_swap_mode))
16358         {
16359           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16360           used_prefixes |= (prefixes & PREFIX_DATA);
16361         }
16362       OP_E (bytemode, sizeflag);
16363     }
16364 }
16365
16366 static void
16367 OP_Vex_2src_1 (int bytemode, int sizeflag)
16368 {
16369   if (modrm.mod == 3)
16370     {
16371       /* Skip mod/rm byte.   */
16372       MODRM_CHECK;
16373       codep++;
16374     }
16375
16376   if (vex.w)
16377     oappend (names_xmm[vex.register_specifier]);
16378   else
16379     OP_Vex_2src (bytemode, sizeflag);
16380 }
16381
16382 static void
16383 OP_Vex_2src_2 (int bytemode, int sizeflag)
16384 {
16385   if (vex.w)
16386     OP_Vex_2src (bytemode, sizeflag);
16387   else
16388     oappend (names_xmm[vex.register_specifier]);
16389 }
16390
16391 static void
16392 OP_EX_VexW (int bytemode, int sizeflag)
16393 {
16394   int reg = -1;
16395
16396   if (!vex_w_done)
16397     {
16398       vex_w_done = 1;
16399
16400       /* Skip mod/rm byte.  */
16401       MODRM_CHECK;
16402       codep++;
16403
16404       if (vex.w)
16405         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16406     }
16407   else
16408     {
16409       if (!vex.w)
16410         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16411     }
16412
16413   OP_EX_VexReg (bytemode, sizeflag, reg);
16414 }
16415
16416 static void
16417 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16418              int sizeflag ATTRIBUTE_UNUSED)
16419 {
16420   /* Skip the immediate byte and check for invalid bits.  */
16421   FETCH_DATA (the_info, codep + 1);
16422   if (*codep++ & 0xf)
16423     BadOp ();
16424 }
16425
16426 static void
16427 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16428 {
16429   int reg;
16430   const char **names;
16431
16432   FETCH_DATA (the_info, codep + 1);
16433   reg = *codep++;
16434
16435   if (bytemode != x_mode)
16436     abort ();
16437
16438   if (reg & 0xf)
16439       BadOp ();
16440
16441   reg >>= 4;
16442   if (reg > 7 && address_mode != mode_64bit)
16443     BadOp ();
16444
16445   switch (vex.length)
16446     {
16447     case 128:
16448       names = names_xmm;
16449       break;
16450     case 256:
16451       names = names_ymm;
16452       break;
16453     default:
16454       abort ();
16455     }
16456   oappend (names[reg]);
16457 }
16458
16459 static void
16460 OP_XMM_VexW (int bytemode, int sizeflag)
16461 {
16462   /* Turn off the REX.W bit since it is used for swapping operands
16463      now.  */
16464   rex &= ~REX_W;
16465   OP_XMM (bytemode, sizeflag);
16466 }
16467
16468 static void
16469 OP_EX_Vex (int bytemode, int sizeflag)
16470 {
16471   if (modrm.mod != 3)
16472     {
16473       if (vex.register_specifier != 0)
16474         BadOp ();
16475       need_vex_reg = 0;
16476     }
16477   OP_EX (bytemode, sizeflag);
16478 }
16479
16480 static void
16481 OP_XMM_Vex (int bytemode, int sizeflag)
16482 {
16483   if (modrm.mod != 3)
16484     {
16485       if (vex.register_specifier != 0)
16486         BadOp ();
16487       need_vex_reg = 0;
16488     }
16489   OP_XMM (bytemode, sizeflag);
16490 }
16491
16492 static void
16493 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16494 {
16495   switch (vex.length)
16496     {
16497     case 128:
16498       mnemonicendp = stpcpy (obuf, "vzeroupper");
16499       break;
16500     case 256:
16501       mnemonicendp = stpcpy (obuf, "vzeroall");
16502       break;
16503     default:
16504       abort ();
16505     }
16506 }
16507
16508 static struct op vex_cmp_op[] =
16509 {
16510   { STRING_COMMA_LEN ("eq") },
16511   { STRING_COMMA_LEN ("lt") },
16512   { STRING_COMMA_LEN ("le") },
16513   { STRING_COMMA_LEN ("unord") },
16514   { STRING_COMMA_LEN ("neq") },
16515   { STRING_COMMA_LEN ("nlt") },
16516   { STRING_COMMA_LEN ("nle") },
16517   { STRING_COMMA_LEN ("ord") },
16518   { STRING_COMMA_LEN ("eq_uq") },
16519   { STRING_COMMA_LEN ("nge") },
16520   { STRING_COMMA_LEN ("ngt") },
16521   { STRING_COMMA_LEN ("false") },
16522   { STRING_COMMA_LEN ("neq_oq") },
16523   { STRING_COMMA_LEN ("ge") },
16524   { STRING_COMMA_LEN ("gt") },
16525   { STRING_COMMA_LEN ("true") },
16526   { STRING_COMMA_LEN ("eq_os") },
16527   { STRING_COMMA_LEN ("lt_oq") },
16528   { STRING_COMMA_LEN ("le_oq") },
16529   { STRING_COMMA_LEN ("unord_s") },
16530   { STRING_COMMA_LEN ("neq_us") },
16531   { STRING_COMMA_LEN ("nlt_uq") },
16532   { STRING_COMMA_LEN ("nle_uq") },
16533   { STRING_COMMA_LEN ("ord_s") },
16534   { STRING_COMMA_LEN ("eq_us") },
16535   { STRING_COMMA_LEN ("nge_uq") },
16536   { STRING_COMMA_LEN ("ngt_uq") },
16537   { STRING_COMMA_LEN ("false_os") },
16538   { STRING_COMMA_LEN ("neq_os") },
16539   { STRING_COMMA_LEN ("ge_oq") },
16540   { STRING_COMMA_LEN ("gt_oq") },
16541   { STRING_COMMA_LEN ("true_us") },
16542 };
16543
16544 static void
16545 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16546 {
16547   unsigned int cmp_type;
16548
16549   FETCH_DATA (the_info, codep + 1);
16550   cmp_type = *codep++ & 0xff;
16551   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16552     {
16553       char suffix [3];
16554       char *p = mnemonicendp - 2;
16555       suffix[0] = p[0];
16556       suffix[1] = p[1];
16557       suffix[2] = '\0';
16558       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16559       mnemonicendp += vex_cmp_op[cmp_type].len;
16560     }
16561   else
16562     {
16563       /* We have a reserved extension byte.  Output it directly.  */
16564       scratchbuf[0] = '$';
16565       print_operand_value (scratchbuf + 1, 1, cmp_type);
16566       oappend_maybe_intel (scratchbuf);
16567       scratchbuf[0] = '\0';
16568     }
16569 }
16570
16571 static void
16572 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16573              int sizeflag ATTRIBUTE_UNUSED)
16574 {
16575   unsigned int cmp_type;
16576
16577   if (!vex.evex)
16578     abort ();
16579
16580   FETCH_DATA (the_info, codep + 1);
16581   cmp_type = *codep++ & 0xff;
16582   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16583      If it's the case, print suffix, otherwise - print the immediate.  */
16584   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16585       && cmp_type != 3
16586       && cmp_type != 7)
16587     {
16588       char suffix [3];
16589       char *p = mnemonicendp - 2;
16590
16591       /* vpcmp* can have both one- and two-lettered suffix.  */
16592       if (p[0] == 'p')
16593         {
16594           p++;
16595           suffix[0] = p[0];
16596           suffix[1] = '\0';
16597         }
16598       else
16599         {
16600           suffix[0] = p[0];
16601           suffix[1] = p[1];
16602           suffix[2] = '\0';
16603         }
16604
16605       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16606       mnemonicendp += simd_cmp_op[cmp_type].len;
16607     }
16608   else
16609     {
16610       /* We have a reserved extension byte.  Output it directly.  */
16611       scratchbuf[0] = '$';
16612       print_operand_value (scratchbuf + 1, 1, cmp_type);
16613       oappend_maybe_intel (scratchbuf);
16614       scratchbuf[0] = '\0';
16615     }
16616 }
16617
16618 static const struct op pclmul_op[] =
16619 {
16620   { STRING_COMMA_LEN ("lql") },
16621   { STRING_COMMA_LEN ("hql") },
16622   { STRING_COMMA_LEN ("lqh") },
16623   { STRING_COMMA_LEN ("hqh") }
16624 };
16625
16626 static void
16627 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16628               int sizeflag ATTRIBUTE_UNUSED)
16629 {
16630   unsigned int pclmul_type;
16631
16632   FETCH_DATA (the_info, codep + 1);
16633   pclmul_type = *codep++ & 0xff;
16634   switch (pclmul_type)
16635     {
16636     case 0x10:
16637       pclmul_type = 2;
16638       break;
16639     case 0x11:
16640       pclmul_type = 3;
16641       break;
16642     default:
16643       break;
16644     }
16645   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16646     {
16647       char suffix [4];
16648       char *p = mnemonicendp - 3;
16649       suffix[0] = p[0];
16650       suffix[1] = p[1];
16651       suffix[2] = p[2];
16652       suffix[3] = '\0';
16653       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16654       mnemonicendp += pclmul_op[pclmul_type].len;
16655     }
16656   else
16657     {
16658       /* We have a reserved extension byte.  Output it directly.  */
16659       scratchbuf[0] = '$';
16660       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16661       oappend_maybe_intel (scratchbuf);
16662       scratchbuf[0] = '\0';
16663     }
16664 }
16665
16666 static void
16667 MOVBE_Fixup (int bytemode, int sizeflag)
16668 {
16669   /* Add proper suffix to "movbe".  */
16670   char *p = mnemonicendp;
16671
16672   switch (bytemode)
16673     {
16674     case v_mode:
16675       if (intel_syntax)
16676         goto skip;
16677
16678       USED_REX (REX_W);
16679       if (sizeflag & SUFFIX_ALWAYS)
16680         {
16681           if (rex & REX_W)
16682             *p++ = 'q';
16683           else
16684             {
16685               if (sizeflag & DFLAG)
16686                 *p++ = 'l';
16687               else
16688                 *p++ = 'w';
16689               used_prefixes |= (prefixes & PREFIX_DATA);
16690             }
16691         }
16692       break;
16693     default:
16694       oappend (INTERNAL_DISASSEMBLER_ERROR);
16695       break;
16696     }
16697   mnemonicendp = p;
16698   *p = '\0';
16699
16700 skip:
16701   OP_M (bytemode, sizeflag);
16702 }
16703
16704 static void
16705 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16706 {
16707   int reg;
16708   const char **names;
16709
16710   /* Skip mod/rm byte.  */
16711   MODRM_CHECK;
16712   codep++;
16713
16714   if (vex.w)
16715     names = names64;
16716   else
16717     names = names32;
16718
16719   reg = modrm.rm;
16720   USED_REX (REX_B);
16721   if (rex & REX_B)
16722     reg += 8;
16723
16724   oappend (names[reg]);
16725 }
16726
16727 static void
16728 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16729 {
16730   const char **names;
16731
16732   if (vex.w)
16733     names = names64;
16734   else
16735     names = names32;
16736
16737   oappend (names[vex.register_specifier]);
16738 }
16739
16740 static void
16741 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16742 {
16743   if (!vex.evex
16744       || bytemode != mask_mode)
16745     abort ();
16746
16747   USED_REX (REX_R);
16748   if ((rex & REX_R) != 0 || !vex.r)
16749     {
16750       BadOp ();
16751       return;
16752     }
16753
16754   oappend (names_mask [modrm.reg]);
16755 }
16756
16757 static void
16758 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16759 {
16760   if (!vex.evex
16761       || (bytemode != evex_rounding_mode
16762           && bytemode != evex_sae_mode))
16763     abort ();
16764   if (modrm.mod == 3 && vex.b)
16765     switch (bytemode)
16766       {
16767       case evex_rounding_mode:
16768         oappend (names_rounding[vex.ll]);
16769         break;
16770       case evex_sae_mode:
16771         oappend ("{sae}");
16772         break;
16773       default:
16774         break;
16775       }
16776 }