1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma
, disassemble_info
*);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma
);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma
);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma
get64 (void);
60 static bfd_signed_vma
get32 (void);
61 static bfd_signed_vma
get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma
, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_EX_VexImmW (int, int);
95 static void OP_XMM_Vex (int, int);
96 static void OP_XMM_VexW (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VEXI4_Fixup (int, int);
100 static void VZERO_Fixup (int, int);
101 static void VCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void HLE_Fixup1 (int, int);
112 static void HLE_Fixup2 (int, int);
113 static void HLE_Fixup3 (int, int);
114 static void CMPXCHG8B_Fixup (int, int);
115 static void XMM_Fixup (int, int);
116 static void CRC32_Fixup (int, int);
117 static void FXSAVE_Fixup (int, int);
118 static void OP_LWPCB_E (int, int);
119 static void OP_LWP_E (int, int);
120 static void OP_Vex_2src_1 (int, int);
121 static void OP_Vex_2src_2 (int, int);
123 static void MOVBE_Fixup (int, int);
126 /* Points to first byte not fetched. */
127 bfd_byte
*max_fetched
;
128 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
141 enum address_mode address_mode
;
143 /* Flags for the prefixes for the current instruction. See below. */
146 /* REX prefix the current instruction. See below. */
148 /* Bits of REX we've already used. */
150 /* REX bits in original REX prefix ignored. */
151 static int rex_ignored
;
152 /* Mark parts used in the REX prefix. When we are testing for
153 empty prefix (for 8bit register REX extension), just mask it
154 out. Otherwise test for REX bit is excuse for existence of REX
155 only in case value is nonzero. */
156 #define USED_REX(value) \
161 rex_used |= (value) | REX_OPCODE; \
164 rex_used |= REX_OPCODE; \
167 /* Flags for prefixes which we somehow handled when printing the
168 current instruction. */
169 static int used_prefixes
;
171 /* Flags stored in PREFIXES. */
172 #define PREFIX_REPZ 1
173 #define PREFIX_REPNZ 2
174 #define PREFIX_LOCK 4
176 #define PREFIX_SS 0x10
177 #define PREFIX_DS 0x20
178 #define PREFIX_ES 0x40
179 #define PREFIX_FS 0x80
180 #define PREFIX_GS 0x100
181 #define PREFIX_DATA 0x200
182 #define PREFIX_ADDR 0x400
183 #define PREFIX_FWAIT 0x800
185 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
186 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
188 #define FETCH_DATA(info, addr) \
189 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
190 ? 1 : fetch_data ((info), (addr)))
193 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
196 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
197 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
199 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
200 status
= (*info
->read_memory_func
) (start
,
202 addr
- priv
->max_fetched
,
208 /* If we did manage to read at least one byte, then
209 print_insn_i386 will do something sensible. Otherwise, print
210 an error. We do that here because this is where we know
212 if (priv
->max_fetched
== priv
->the_buffer
)
213 (*info
->memory_error_func
) (status
, start
, info
);
214 longjmp (priv
->bailout
, 1);
217 priv
->max_fetched
= addr
;
221 #define XX { NULL, 0 }
222 #define Bad_Opcode NULL, { { NULL, 0 } }
224 #define Eb { OP_E, b_mode }
225 #define EbS { OP_E, b_swap_mode }
226 #define Ev { OP_E, v_mode }
227 #define EvS { OP_E, v_swap_mode }
228 #define Ed { OP_E, d_mode }
229 #define Edq { OP_E, dq_mode }
230 #define Edqw { OP_E, dqw_mode }
231 #define Edqb { OP_E, dqb_mode }
232 #define Edqd { OP_E, dqd_mode }
233 #define Eq { OP_E, q_mode }
234 #define indirEv { OP_indirE, stack_v_mode }
235 #define indirEp { OP_indirE, f_mode }
236 #define stackEv { OP_E, stack_v_mode }
237 #define Em { OP_E, m_mode }
238 #define Ew { OP_E, w_mode }
239 #define M { OP_M, 0 } /* lea, lgdt, etc. */
240 #define Ma { OP_M, a_mode }
241 #define Mb { OP_M, b_mode }
242 #define Md { OP_M, d_mode }
243 #define Mo { OP_M, o_mode }
244 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
245 #define Mq { OP_M, q_mode }
246 #define Mx { OP_M, x_mode }
247 #define Mxmm { OP_M, xmm_mode }
248 #define Gb { OP_G, b_mode }
249 #define Gv { OP_G, v_mode }
250 #define Gd { OP_G, d_mode }
251 #define Gdq { OP_G, dq_mode }
252 #define Gm { OP_G, m_mode }
253 #define Gw { OP_G, w_mode }
254 #define Rd { OP_R, d_mode }
255 #define Rm { OP_R, m_mode }
256 #define Ib { OP_I, b_mode }
257 #define sIb { OP_sI, b_mode } /* sign extened byte */
258 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
259 #define Iv { OP_I, v_mode }
260 #define sIv { OP_sI, v_mode }
261 #define Iq { OP_I, q_mode }
262 #define Iv64 { OP_I64, v_mode }
263 #define Iw { OP_I, w_mode }
264 #define I1 { OP_I, const_1_mode }
265 #define Jb { OP_J, b_mode }
266 #define Jv { OP_J, v_mode }
267 #define Cm { OP_C, m_mode }
268 #define Dm { OP_D, m_mode }
269 #define Td { OP_T, d_mode }
270 #define Skip_MODRM { OP_Skip_MODRM, 0 }
272 #define RMeAX { OP_REG, eAX_reg }
273 #define RMeBX { OP_REG, eBX_reg }
274 #define RMeCX { OP_REG, eCX_reg }
275 #define RMeDX { OP_REG, eDX_reg }
276 #define RMeSP { OP_REG, eSP_reg }
277 #define RMeBP { OP_REG, eBP_reg }
278 #define RMeSI { OP_REG, eSI_reg }
279 #define RMeDI { OP_REG, eDI_reg }
280 #define RMrAX { OP_REG, rAX_reg }
281 #define RMrBX { OP_REG, rBX_reg }
282 #define RMrCX { OP_REG, rCX_reg }
283 #define RMrDX { OP_REG, rDX_reg }
284 #define RMrSP { OP_REG, rSP_reg }
285 #define RMrBP { OP_REG, rBP_reg }
286 #define RMrSI { OP_REG, rSI_reg }
287 #define RMrDI { OP_REG, rDI_reg }
288 #define RMAL { OP_REG, al_reg }
289 #define RMCL { OP_REG, cl_reg }
290 #define RMDL { OP_REG, dl_reg }
291 #define RMBL { OP_REG, bl_reg }
292 #define RMAH { OP_REG, ah_reg }
293 #define RMCH { OP_REG, ch_reg }
294 #define RMDH { OP_REG, dh_reg }
295 #define RMBH { OP_REG, bh_reg }
296 #define RMAX { OP_REG, ax_reg }
297 #define RMDX { OP_REG, dx_reg }
299 #define eAX { OP_IMREG, eAX_reg }
300 #define eBX { OP_IMREG, eBX_reg }
301 #define eCX { OP_IMREG, eCX_reg }
302 #define eDX { OP_IMREG, eDX_reg }
303 #define eSP { OP_IMREG, eSP_reg }
304 #define eBP { OP_IMREG, eBP_reg }
305 #define eSI { OP_IMREG, eSI_reg }
306 #define eDI { OP_IMREG, eDI_reg }
307 #define AL { OP_IMREG, al_reg }
308 #define CL { OP_IMREG, cl_reg }
309 #define DL { OP_IMREG, dl_reg }
310 #define BL { OP_IMREG, bl_reg }
311 #define AH { OP_IMREG, ah_reg }
312 #define CH { OP_IMREG, ch_reg }
313 #define DH { OP_IMREG, dh_reg }
314 #define BH { OP_IMREG, bh_reg }
315 #define AX { OP_IMREG, ax_reg }
316 #define DX { OP_IMREG, dx_reg }
317 #define zAX { OP_IMREG, z_mode_ax_reg }
318 #define indirDX { OP_IMREG, indir_dx_reg }
320 #define Sw { OP_SEG, w_mode }
321 #define Sv { OP_SEG, v_mode }
322 #define Ap { OP_DIR, 0 }
323 #define Ob { OP_OFF64, b_mode }
324 #define Ov { OP_OFF64, v_mode }
325 #define Xb { OP_DSreg, eSI_reg }
326 #define Xv { OP_DSreg, eSI_reg }
327 #define Xz { OP_DSreg, eSI_reg }
328 #define Yb { OP_ESreg, eDI_reg }
329 #define Yv { OP_ESreg, eDI_reg }
330 #define DSBX { OP_DSreg, eBX_reg }
332 #define es { OP_REG, es_reg }
333 #define ss { OP_REG, ss_reg }
334 #define cs { OP_REG, cs_reg }
335 #define ds { OP_REG, ds_reg }
336 #define fs { OP_REG, fs_reg }
337 #define gs { OP_REG, gs_reg }
339 #define MX { OP_MMX, 0 }
340 #define XM { OP_XMM, 0 }
341 #define XMScalar { OP_XMM, scalar_mode }
342 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
343 #define XMM { OP_XMM, xmm_mode }
344 #define EM { OP_EM, v_mode }
345 #define EMS { OP_EM, v_swap_mode }
346 #define EMd { OP_EM, d_mode }
347 #define EMx { OP_EM, x_mode }
348 #define EXw { OP_EX, w_mode }
349 #define EXd { OP_EX, d_mode }
350 #define EXdScalar { OP_EX, d_scalar_mode }
351 #define EXdS { OP_EX, d_swap_mode }
352 #define EXq { OP_EX, q_mode }
353 #define EXqScalar { OP_EX, q_scalar_mode }
354 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
355 #define EXqS { OP_EX, q_swap_mode }
356 #define EXx { OP_EX, x_mode }
357 #define EXxS { OP_EX, x_swap_mode }
358 #define EXxmm { OP_EX, xmm_mode }
359 #define EXxmmq { OP_EX, xmmq_mode }
360 #define EXxmm_mb { OP_EX, xmm_mb_mode }
361 #define EXxmm_mw { OP_EX, xmm_mw_mode }
362 #define EXxmm_md { OP_EX, xmm_md_mode }
363 #define EXxmm_mq { OP_EX, xmm_mq_mode }
364 #define EXxmmdw { OP_EX, xmmdw_mode }
365 #define EXxmmqd { OP_EX, xmmqd_mode }
366 #define EXymmq { OP_EX, ymmq_mode }
367 #define EXVexWdq { OP_EX, vex_w_dq_mode }
368 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
369 #define MS { OP_MS, v_mode }
370 #define XS { OP_XS, v_mode }
371 #define EMCq { OP_EMC, q_mode }
372 #define MXC { OP_MXC, 0 }
373 #define OPSUF { OP_3DNowSuffix, 0 }
374 #define CMP { CMP_Fixup, 0 }
375 #define XMM0 { XMM_Fixup, 0 }
376 #define FXSAVE { FXSAVE_Fixup, 0 }
377 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
378 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
380 #define Vex { OP_VEX, vex_mode }
381 #define VexScalar { OP_VEX, vex_scalar_mode }
382 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
383 #define Vex128 { OP_VEX, vex128_mode }
384 #define Vex256 { OP_VEX, vex256_mode }
385 #define VexGdq { OP_VEX, dq_mode }
386 #define VexI4 { VEXI4_Fixup, 0}
387 #define EXdVex { OP_EX_Vex, d_mode }
388 #define EXdVexS { OP_EX_Vex, d_swap_mode }
389 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
390 #define EXqVex { OP_EX_Vex, q_mode }
391 #define EXqVexS { OP_EX_Vex, q_swap_mode }
392 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
393 #define EXVexW { OP_EX_VexW, x_mode }
394 #define EXdVexW { OP_EX_VexW, d_mode }
395 #define EXqVexW { OP_EX_VexW, q_mode }
396 #define EXVexImmW { OP_EX_VexImmW, x_mode }
397 #define XMVex { OP_XMM_Vex, 0 }
398 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
399 #define XMVexW { OP_XMM_VexW, 0 }
400 #define XMVexI4 { OP_REG_VexI4, x_mode }
401 #define PCLMUL { PCLMUL_Fixup, 0 }
402 #define VZERO { VZERO_Fixup, 0 }
403 #define VCMP { VCMP_Fixup, 0 }
405 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
406 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
408 /* Used handle "rep" prefix for string instructions. */
409 #define Xbr { REP_Fixup, eSI_reg }
410 #define Xvr { REP_Fixup, eSI_reg }
411 #define Ybr { REP_Fixup, eDI_reg }
412 #define Yvr { REP_Fixup, eDI_reg }
413 #define Yzr { REP_Fixup, eDI_reg }
414 #define indirDXr { REP_Fixup, indir_dx_reg }
415 #define ALr { REP_Fixup, al_reg }
416 #define eAXr { REP_Fixup, eAX_reg }
418 /* Used handle HLE prefix for lockable instructions. */
419 #define Ebh1 { HLE_Fixup1, b_mode }
420 #define Evh1 { HLE_Fixup1, v_mode }
421 #define Ebh2 { HLE_Fixup2, b_mode }
422 #define Evh2 { HLE_Fixup2, v_mode }
423 #define Ebh3 { HLE_Fixup3, b_mode }
424 #define Evh3 { HLE_Fixup3, v_mode }
426 #define cond_jump_flag { NULL, cond_jump_mode }
427 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
429 /* bits in sizeflag */
430 #define SUFFIX_ALWAYS 4
438 /* byte operand with operand swapped */
440 /* byte operand, sign extend like 'T' suffix */
442 /* operand size depends on prefixes */
444 /* operand size depends on prefixes with operand swapped */
448 /* double word operand */
450 /* double word operand with operand swapped */
452 /* quad word operand */
454 /* quad word operand with operand swapped */
456 /* ten-byte operand */
458 /* 16-byte XMM or 32-byte YMM operand */
460 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
462 /* 16-byte XMM operand */
464 /* 16-byte XMM or quad word operand */
466 /* XMM register or byte memory operand */
468 /* XMM register or word memory operand */
470 /* XMM register or double word memory operand */
472 /* XMM register or quad word memory operand */
474 /* 16-byte XMM, word or double word operand */
476 /* 16-byte XMM, double word or quad word operand */
478 /* 32-byte YMM or quad word operand */
480 /* 32-byte YMM or 16-byte word operand */
482 /* d_mode in 32bit, q_mode in 64bit mode. */
484 /* pair of v_mode operands */
488 /* operand size depends on REX prefixes. */
490 /* registers like dq_mode, memory like w_mode. */
492 /* 4- or 6-byte pointer operand */
495 /* v_mode for stack-related opcodes. */
497 /* non-quad operand size depends on prefixes */
499 /* 16-byte operand */
501 /* registers like dq_mode, memory like b_mode. */
503 /* registers like dq_mode, memory like d_mode. */
505 /* normal vex mode */
507 /* 128bit vex mode */
509 /* 256bit vex mode */
511 /* operand size depends on the VEX.W bit. */
514 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
515 vex_vsib_d_w_dq_mode
,
516 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
517 vex_vsib_q_w_dq_mode
,
519 /* scalar, ignore vector length. */
521 /* like d_mode, ignore vector length. */
523 /* like d_swap_mode, ignore vector length. */
525 /* like q_mode, ignore vector length. */
527 /* like q_swap_mode, ignore vector length. */
529 /* like vex_mode, ignore vector length. */
531 /* like vex_w_dq_mode, ignore vector length. */
532 vex_scalar_w_dq_mode
,
597 #define FLOAT NULL, { { NULL, FLOATCODE } }
599 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
600 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
601 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
602 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
603 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
604 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
605 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
606 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
607 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
608 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
609 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
610 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
716 MOD_VEX_0F12_PREFIX_0
,
718 MOD_VEX_0F16_PREFIX_0
,
734 MOD_VEX_0FD7_PREFIX_2
,
735 MOD_VEX_0FE7_PREFIX_2
,
736 MOD_VEX_0FF0_PREFIX_3
,
737 MOD_VEX_0F381A_PREFIX_2
,
738 MOD_VEX_0F382A_PREFIX_2
,
739 MOD_VEX_0F382C_PREFIX_2
,
740 MOD_VEX_0F382D_PREFIX_2
,
741 MOD_VEX_0F382E_PREFIX_2
,
742 MOD_VEX_0F382F_PREFIX_2
,
743 MOD_VEX_0F385A_PREFIX_2
,
744 MOD_VEX_0F388C_PREFIX_2
,
745 MOD_VEX_0F388E_PREFIX_2
,
919 PREFIX_VEX_0F71_REG_2
,
920 PREFIX_VEX_0F71_REG_4
,
921 PREFIX_VEX_0F71_REG_6
,
922 PREFIX_VEX_0F72_REG_2
,
923 PREFIX_VEX_0F72_REG_4
,
924 PREFIX_VEX_0F72_REG_6
,
925 PREFIX_VEX_0F73_REG_2
,
926 PREFIX_VEX_0F73_REG_3
,
927 PREFIX_VEX_0F73_REG_6
,
928 PREFIX_VEX_0F73_REG_7
,
1094 PREFIX_VEX_0F38F3_REG_1
,
1095 PREFIX_VEX_0F38F3_REG_2
,
1096 PREFIX_VEX_0F38F3_REG_3
,
1198 THREE_BYTE_0F38
= 0,
1219 VEX_LEN_0F10_P_1
= 0,
1223 VEX_LEN_0F12_P_0_M_0
,
1224 VEX_LEN_0F12_P_0_M_1
,
1227 VEX_LEN_0F16_P_0_M_0
,
1228 VEX_LEN_0F16_P_0_M_1
,
1262 VEX_LEN_0FAE_R_2_M_0
,
1263 VEX_LEN_0FAE_R_3_M_0
,
1272 VEX_LEN_0F381A_P_2_M_0
,
1275 VEX_LEN_0F385A_P_2_M_0
,
1282 VEX_LEN_0F38F3_R_1_P_0
,
1283 VEX_LEN_0F38F3_R_2_P_0
,
1284 VEX_LEN_0F38F3_R_3_P_0
,
1326 VEX_LEN_0FXOP_08_CC
,
1327 VEX_LEN_0FXOP_08_CD
,
1328 VEX_LEN_0FXOP_08_CE
,
1329 VEX_LEN_0FXOP_08_CF
,
1330 VEX_LEN_0FXOP_08_EC
,
1331 VEX_LEN_0FXOP_08_ED
,
1332 VEX_LEN_0FXOP_08_EE
,
1333 VEX_LEN_0FXOP_08_EF
,
1334 VEX_LEN_0FXOP_09_80
,
1525 VEX_W_0F381A_P_2_M_0
,
1537 VEX_W_0F382A_P_2_M_0
,
1539 VEX_W_0F382C_P_2_M_0
,
1540 VEX_W_0F382D_P_2_M_0
,
1541 VEX_W_0F382E_P_2_M_0
,
1542 VEX_W_0F382F_P_2_M_0
,
1564 VEX_W_0F385A_P_2_M_0
,
1611 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1622 /* Upper case letters in the instruction names here are macros.
1623 'A' => print 'b' if no register operands or suffix_always is true
1624 'B' => print 'b' if suffix_always is true
1625 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1627 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1628 suffix_always is true
1629 'E' => print 'e' if 32-bit form of jcxz
1630 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1631 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1632 'H' => print ",pt" or ",pn" branch hint
1633 'I' => honor following macro letter even in Intel mode (implemented only
1634 for some of the macro letters)
1636 'K' => print 'd' or 'q' if rex prefix is present.
1637 'L' => print 'l' if suffix_always is true
1638 'M' => print 'r' if intel_mnemonic is false.
1639 'N' => print 'n' if instruction has no wait "prefix"
1640 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1641 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1642 or suffix_always is true. print 'q' if rex prefix is present.
1643 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1645 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1646 'S' => print 'w', 'l' or 'q' if suffix_always is true
1647 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1648 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1649 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1650 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1651 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1652 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1653 suffix_always is true.
1654 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1655 '!' => change condition from true to false or from false to true.
1656 '%' => add 1 upper case letter to the macro.
1658 2 upper case letter macros:
1659 "XY" => print 'x' or 'y' if no register operands or suffix_always
1661 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1662 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1663 or suffix_always is true
1664 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1665 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1666 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1667 "LW" => print 'd', 'q' depending on the VEX.W bit
1669 Many of the above letters print nothing in Intel mode. See "putop"
1672 Braces '{' and '}', and vertical bars '|', indicate alternative
1673 mnemonic strings for AT&T and Intel. */
1675 static const struct dis386 dis386
[] = {
1677 { "addB", { Ebh1
, Gb
} },
1678 { "addS", { Evh1
, Gv
} },
1679 { "addB", { Gb
, EbS
} },
1680 { "addS", { Gv
, EvS
} },
1681 { "addB", { AL
, Ib
} },
1682 { "addS", { eAX
, Iv
} },
1683 { X86_64_TABLE (X86_64_06
) },
1684 { X86_64_TABLE (X86_64_07
) },
1686 { "orB", { Ebh1
, Gb
} },
1687 { "orS", { Evh1
, Gv
} },
1688 { "orB", { Gb
, EbS
} },
1689 { "orS", { Gv
, EvS
} },
1690 { "orB", { AL
, Ib
} },
1691 { "orS", { eAX
, Iv
} },
1692 { X86_64_TABLE (X86_64_0D
) },
1693 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1695 { "adcB", { Ebh1
, Gb
} },
1696 { "adcS", { Evh1
, Gv
} },
1697 { "adcB", { Gb
, EbS
} },
1698 { "adcS", { Gv
, EvS
} },
1699 { "adcB", { AL
, Ib
} },
1700 { "adcS", { eAX
, Iv
} },
1701 { X86_64_TABLE (X86_64_16
) },
1702 { X86_64_TABLE (X86_64_17
) },
1704 { "sbbB", { Ebh1
, Gb
} },
1705 { "sbbS", { Evh1
, Gv
} },
1706 { "sbbB", { Gb
, EbS
} },
1707 { "sbbS", { Gv
, EvS
} },
1708 { "sbbB", { AL
, Ib
} },
1709 { "sbbS", { eAX
, Iv
} },
1710 { X86_64_TABLE (X86_64_1E
) },
1711 { X86_64_TABLE (X86_64_1F
) },
1713 { "andB", { Ebh1
, Gb
} },
1714 { "andS", { Evh1
, Gv
} },
1715 { "andB", { Gb
, EbS
} },
1716 { "andS", { Gv
, EvS
} },
1717 { "andB", { AL
, Ib
} },
1718 { "andS", { eAX
, Iv
} },
1719 { Bad_Opcode
}, /* SEG ES prefix */
1720 { X86_64_TABLE (X86_64_27
) },
1722 { "subB", { Ebh1
, Gb
} },
1723 { "subS", { Evh1
, Gv
} },
1724 { "subB", { Gb
, EbS
} },
1725 { "subS", { Gv
, EvS
} },
1726 { "subB", { AL
, Ib
} },
1727 { "subS", { eAX
, Iv
} },
1728 { Bad_Opcode
}, /* SEG CS prefix */
1729 { X86_64_TABLE (X86_64_2F
) },
1731 { "xorB", { Ebh1
, Gb
} },
1732 { "xorS", { Evh1
, Gv
} },
1733 { "xorB", { Gb
, EbS
} },
1734 { "xorS", { Gv
, EvS
} },
1735 { "xorB", { AL
, Ib
} },
1736 { "xorS", { eAX
, Iv
} },
1737 { Bad_Opcode
}, /* SEG SS prefix */
1738 { X86_64_TABLE (X86_64_37
) },
1740 { "cmpB", { Eb
, Gb
} },
1741 { "cmpS", { Ev
, Gv
} },
1742 { "cmpB", { Gb
, EbS
} },
1743 { "cmpS", { Gv
, EvS
} },
1744 { "cmpB", { AL
, Ib
} },
1745 { "cmpS", { eAX
, Iv
} },
1746 { Bad_Opcode
}, /* SEG DS prefix */
1747 { X86_64_TABLE (X86_64_3F
) },
1749 { "inc{S|}", { RMeAX
} },
1750 { "inc{S|}", { RMeCX
} },
1751 { "inc{S|}", { RMeDX
} },
1752 { "inc{S|}", { RMeBX
} },
1753 { "inc{S|}", { RMeSP
} },
1754 { "inc{S|}", { RMeBP
} },
1755 { "inc{S|}", { RMeSI
} },
1756 { "inc{S|}", { RMeDI
} },
1758 { "dec{S|}", { RMeAX
} },
1759 { "dec{S|}", { RMeCX
} },
1760 { "dec{S|}", { RMeDX
} },
1761 { "dec{S|}", { RMeBX
} },
1762 { "dec{S|}", { RMeSP
} },
1763 { "dec{S|}", { RMeBP
} },
1764 { "dec{S|}", { RMeSI
} },
1765 { "dec{S|}", { RMeDI
} },
1767 { "pushV", { RMrAX
} },
1768 { "pushV", { RMrCX
} },
1769 { "pushV", { RMrDX
} },
1770 { "pushV", { RMrBX
} },
1771 { "pushV", { RMrSP
} },
1772 { "pushV", { RMrBP
} },
1773 { "pushV", { RMrSI
} },
1774 { "pushV", { RMrDI
} },
1776 { "popV", { RMrAX
} },
1777 { "popV", { RMrCX
} },
1778 { "popV", { RMrDX
} },
1779 { "popV", { RMrBX
} },
1780 { "popV", { RMrSP
} },
1781 { "popV", { RMrBP
} },
1782 { "popV", { RMrSI
} },
1783 { "popV", { RMrDI
} },
1785 { X86_64_TABLE (X86_64_60
) },
1786 { X86_64_TABLE (X86_64_61
) },
1787 { X86_64_TABLE (X86_64_62
) },
1788 { X86_64_TABLE (X86_64_63
) },
1789 { Bad_Opcode
}, /* seg fs */
1790 { Bad_Opcode
}, /* seg gs */
1791 { Bad_Opcode
}, /* op size prefix */
1792 { Bad_Opcode
}, /* adr size prefix */
1794 { "pushT", { sIv
} },
1795 { "imulS", { Gv
, Ev
, Iv
} },
1796 { "pushT", { sIbT
} },
1797 { "imulS", { Gv
, Ev
, sIb
} },
1798 { "ins{b|}", { Ybr
, indirDX
} },
1799 { X86_64_TABLE (X86_64_6D
) },
1800 { "outs{b|}", { indirDXr
, Xb
} },
1801 { X86_64_TABLE (X86_64_6F
) },
1803 { "joH", { Jb
, XX
, cond_jump_flag
} },
1804 { "jnoH", { Jb
, XX
, cond_jump_flag
} },
1805 { "jbH", { Jb
, XX
, cond_jump_flag
} },
1806 { "jaeH", { Jb
, XX
, cond_jump_flag
} },
1807 { "jeH", { Jb
, XX
, cond_jump_flag
} },
1808 { "jneH", { Jb
, XX
, cond_jump_flag
} },
1809 { "jbeH", { Jb
, XX
, cond_jump_flag
} },
1810 { "jaH", { Jb
, XX
, cond_jump_flag
} },
1812 { "jsH", { Jb
, XX
, cond_jump_flag
} },
1813 { "jnsH", { Jb
, XX
, cond_jump_flag
} },
1814 { "jpH", { Jb
, XX
, cond_jump_flag
} },
1815 { "jnpH", { Jb
, XX
, cond_jump_flag
} },
1816 { "jlH", { Jb
, XX
, cond_jump_flag
} },
1817 { "jgeH", { Jb
, XX
, cond_jump_flag
} },
1818 { "jleH", { Jb
, XX
, cond_jump_flag
} },
1819 { "jgH", { Jb
, XX
, cond_jump_flag
} },
1821 { REG_TABLE (REG_80
) },
1822 { REG_TABLE (REG_81
) },
1824 { REG_TABLE (REG_82
) },
1825 { "testB", { Eb
, Gb
} },
1826 { "testS", { Ev
, Gv
} },
1827 { "xchgB", { Ebh2
, Gb
} },
1828 { "xchgS", { Evh2
, Gv
} },
1830 { "movB", { Ebh3
, Gb
} },
1831 { "movS", { Evh3
, Gv
} },
1832 { "movB", { Gb
, EbS
} },
1833 { "movS", { Gv
, EvS
} },
1834 { "movD", { Sv
, Sw
} },
1835 { MOD_TABLE (MOD_8D
) },
1836 { "movD", { Sw
, Sv
} },
1837 { REG_TABLE (REG_8F
) },
1839 { PREFIX_TABLE (PREFIX_90
) },
1840 { "xchgS", { RMeCX
, eAX
} },
1841 { "xchgS", { RMeDX
, eAX
} },
1842 { "xchgS", { RMeBX
, eAX
} },
1843 { "xchgS", { RMeSP
, eAX
} },
1844 { "xchgS", { RMeBP
, eAX
} },
1845 { "xchgS", { RMeSI
, eAX
} },
1846 { "xchgS", { RMeDI
, eAX
} },
1848 { "cW{t|}R", { XX
} },
1849 { "cR{t|}O", { XX
} },
1850 { X86_64_TABLE (X86_64_9A
) },
1851 { Bad_Opcode
}, /* fwait */
1852 { "pushfT", { XX
} },
1853 { "popfT", { XX
} },
1857 { "mov%LB", { AL
, Ob
} },
1858 { "mov%LS", { eAX
, Ov
} },
1859 { "mov%LB", { Ob
, AL
} },
1860 { "mov%LS", { Ov
, eAX
} },
1861 { "movs{b|}", { Ybr
, Xb
} },
1862 { "movs{R|}", { Yvr
, Xv
} },
1863 { "cmps{b|}", { Xb
, Yb
} },
1864 { "cmps{R|}", { Xv
, Yv
} },
1866 { "testB", { AL
, Ib
} },
1867 { "testS", { eAX
, Iv
} },
1868 { "stosB", { Ybr
, AL
} },
1869 { "stosS", { Yvr
, eAX
} },
1870 { "lodsB", { ALr
, Xb
} },
1871 { "lodsS", { eAXr
, Xv
} },
1872 { "scasB", { AL
, Yb
} },
1873 { "scasS", { eAX
, Yv
} },
1875 { "movB", { RMAL
, Ib
} },
1876 { "movB", { RMCL
, Ib
} },
1877 { "movB", { RMDL
, Ib
} },
1878 { "movB", { RMBL
, Ib
} },
1879 { "movB", { RMAH
, Ib
} },
1880 { "movB", { RMCH
, Ib
} },
1881 { "movB", { RMDH
, Ib
} },
1882 { "movB", { RMBH
, Ib
} },
1884 { "mov%LV", { RMeAX
, Iv64
} },
1885 { "mov%LV", { RMeCX
, Iv64
} },
1886 { "mov%LV", { RMeDX
, Iv64
} },
1887 { "mov%LV", { RMeBX
, Iv64
} },
1888 { "mov%LV", { RMeSP
, Iv64
} },
1889 { "mov%LV", { RMeBP
, Iv64
} },
1890 { "mov%LV", { RMeSI
, Iv64
} },
1891 { "mov%LV", { RMeDI
, Iv64
} },
1893 { REG_TABLE (REG_C0
) },
1894 { REG_TABLE (REG_C1
) },
1897 { X86_64_TABLE (X86_64_C4
) },
1898 { X86_64_TABLE (X86_64_C5
) },
1899 { REG_TABLE (REG_C6
) },
1900 { REG_TABLE (REG_C7
) },
1902 { "enterT", { Iw
, Ib
} },
1903 { "leaveT", { XX
} },
1904 { "Jret{|f}P", { Iw
} },
1905 { "Jret{|f}P", { XX
} },
1908 { X86_64_TABLE (X86_64_CE
) },
1909 { "iretP", { XX
} },
1911 { REG_TABLE (REG_D0
) },
1912 { REG_TABLE (REG_D1
) },
1913 { REG_TABLE (REG_D2
) },
1914 { REG_TABLE (REG_D3
) },
1915 { X86_64_TABLE (X86_64_D4
) },
1916 { X86_64_TABLE (X86_64_D5
) },
1918 { "xlat", { DSBX
} },
1929 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
} },
1930 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
} },
1931 { "loopFH", { Jb
, XX
, loop_jcxz_flag
} },
1932 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
} },
1933 { "inB", { AL
, Ib
} },
1934 { "inG", { zAX
, Ib
} },
1935 { "outB", { Ib
, AL
} },
1936 { "outG", { Ib
, zAX
} },
1938 { "callT", { Jv
} },
1940 { X86_64_TABLE (X86_64_EA
) },
1942 { "inB", { AL
, indirDX
} },
1943 { "inG", { zAX
, indirDX
} },
1944 { "outB", { indirDX
, AL
} },
1945 { "outG", { indirDX
, zAX
} },
1947 { Bad_Opcode
}, /* lock prefix */
1948 { "icebp", { XX
} },
1949 { Bad_Opcode
}, /* repne */
1950 { Bad_Opcode
}, /* repz */
1953 { REG_TABLE (REG_F6
) },
1954 { REG_TABLE (REG_F7
) },
1962 { REG_TABLE (REG_FE
) },
1963 { REG_TABLE (REG_FF
) },
1966 static const struct dis386 dis386_twobyte
[] = {
1968 { REG_TABLE (REG_0F00
) },
1969 { REG_TABLE (REG_0F01
) },
1970 { "larS", { Gv
, Ew
} },
1971 { "lslS", { Gv
, Ew
} },
1973 { "syscall", { XX
} },
1975 { "sysretP", { XX
} },
1978 { "wbinvd", { XX
} },
1982 { REG_TABLE (REG_0F0D
) },
1983 { "femms", { XX
} },
1984 { "", { MX
, EM
, OPSUF
} }, /* See OP_3DNowSuffix. */
1986 { PREFIX_TABLE (PREFIX_0F10
) },
1987 { PREFIX_TABLE (PREFIX_0F11
) },
1988 { PREFIX_TABLE (PREFIX_0F12
) },
1989 { MOD_TABLE (MOD_0F13
) },
1990 { "unpcklpX", { XM
, EXx
} },
1991 { "unpckhpX", { XM
, EXx
} },
1992 { PREFIX_TABLE (PREFIX_0F16
) },
1993 { MOD_TABLE (MOD_0F17
) },
1995 { REG_TABLE (REG_0F18
) },
2004 { MOD_TABLE (MOD_0F20
) },
2005 { MOD_TABLE (MOD_0F21
) },
2006 { MOD_TABLE (MOD_0F22
) },
2007 { MOD_TABLE (MOD_0F23
) },
2008 { MOD_TABLE (MOD_0F24
) },
2010 { MOD_TABLE (MOD_0F26
) },
2013 { "movapX", { XM
, EXx
} },
2014 { "movapX", { EXxS
, XM
} },
2015 { PREFIX_TABLE (PREFIX_0F2A
) },
2016 { PREFIX_TABLE (PREFIX_0F2B
) },
2017 { PREFIX_TABLE (PREFIX_0F2C
) },
2018 { PREFIX_TABLE (PREFIX_0F2D
) },
2019 { PREFIX_TABLE (PREFIX_0F2E
) },
2020 { PREFIX_TABLE (PREFIX_0F2F
) },
2022 { "wrmsr", { XX
} },
2023 { "rdtsc", { XX
} },
2024 { "rdmsr", { XX
} },
2025 { "rdpmc", { XX
} },
2026 { "sysenter", { XX
} },
2027 { "sysexit", { XX
} },
2029 { "getsec", { XX
} },
2031 { THREE_BYTE_TABLE (THREE_BYTE_0F38
) },
2033 { THREE_BYTE_TABLE (THREE_BYTE_0F3A
) },
2040 { "cmovoS", { Gv
, Ev
} },
2041 { "cmovnoS", { Gv
, Ev
} },
2042 { "cmovbS", { Gv
, Ev
} },
2043 { "cmovaeS", { Gv
, Ev
} },
2044 { "cmoveS", { Gv
, Ev
} },
2045 { "cmovneS", { Gv
, Ev
} },
2046 { "cmovbeS", { Gv
, Ev
} },
2047 { "cmovaS", { Gv
, Ev
} },
2049 { "cmovsS", { Gv
, Ev
} },
2050 { "cmovnsS", { Gv
, Ev
} },
2051 { "cmovpS", { Gv
, Ev
} },
2052 { "cmovnpS", { Gv
, Ev
} },
2053 { "cmovlS", { Gv
, Ev
} },
2054 { "cmovgeS", { Gv
, Ev
} },
2055 { "cmovleS", { Gv
, Ev
} },
2056 { "cmovgS", { Gv
, Ev
} },
2058 { MOD_TABLE (MOD_0F51
) },
2059 { PREFIX_TABLE (PREFIX_0F51
) },
2060 { PREFIX_TABLE (PREFIX_0F52
) },
2061 { PREFIX_TABLE (PREFIX_0F53
) },
2062 { "andpX", { XM
, EXx
} },
2063 { "andnpX", { XM
, EXx
} },
2064 { "orpX", { XM
, EXx
} },
2065 { "xorpX", { XM
, EXx
} },
2067 { PREFIX_TABLE (PREFIX_0F58
) },
2068 { PREFIX_TABLE (PREFIX_0F59
) },
2069 { PREFIX_TABLE (PREFIX_0F5A
) },
2070 { PREFIX_TABLE (PREFIX_0F5B
) },
2071 { PREFIX_TABLE (PREFIX_0F5C
) },
2072 { PREFIX_TABLE (PREFIX_0F5D
) },
2073 { PREFIX_TABLE (PREFIX_0F5E
) },
2074 { PREFIX_TABLE (PREFIX_0F5F
) },
2076 { PREFIX_TABLE (PREFIX_0F60
) },
2077 { PREFIX_TABLE (PREFIX_0F61
) },
2078 { PREFIX_TABLE (PREFIX_0F62
) },
2079 { "packsswb", { MX
, EM
} },
2080 { "pcmpgtb", { MX
, EM
} },
2081 { "pcmpgtw", { MX
, EM
} },
2082 { "pcmpgtd", { MX
, EM
} },
2083 { "packuswb", { MX
, EM
} },
2085 { "punpckhbw", { MX
, EM
} },
2086 { "punpckhwd", { MX
, EM
} },
2087 { "punpckhdq", { MX
, EM
} },
2088 { "packssdw", { MX
, EM
} },
2089 { PREFIX_TABLE (PREFIX_0F6C
) },
2090 { PREFIX_TABLE (PREFIX_0F6D
) },
2091 { "movK", { MX
, Edq
} },
2092 { PREFIX_TABLE (PREFIX_0F6F
) },
2094 { PREFIX_TABLE (PREFIX_0F70
) },
2095 { REG_TABLE (REG_0F71
) },
2096 { REG_TABLE (REG_0F72
) },
2097 { REG_TABLE (REG_0F73
) },
2098 { "pcmpeqb", { MX
, EM
} },
2099 { "pcmpeqw", { MX
, EM
} },
2100 { "pcmpeqd", { MX
, EM
} },
2103 { PREFIX_TABLE (PREFIX_0F78
) },
2104 { PREFIX_TABLE (PREFIX_0F79
) },
2105 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2107 { PREFIX_TABLE (PREFIX_0F7C
) },
2108 { PREFIX_TABLE (PREFIX_0F7D
) },
2109 { PREFIX_TABLE (PREFIX_0F7E
) },
2110 { PREFIX_TABLE (PREFIX_0F7F
) },
2112 { "joH", { Jv
, XX
, cond_jump_flag
} },
2113 { "jnoH", { Jv
, XX
, cond_jump_flag
} },
2114 { "jbH", { Jv
, XX
, cond_jump_flag
} },
2115 { "jaeH", { Jv
, XX
, cond_jump_flag
} },
2116 { "jeH", { Jv
, XX
, cond_jump_flag
} },
2117 { "jneH", { Jv
, XX
, cond_jump_flag
} },
2118 { "jbeH", { Jv
, XX
, cond_jump_flag
} },
2119 { "jaH", { Jv
, XX
, cond_jump_flag
} },
2121 { "jsH", { Jv
, XX
, cond_jump_flag
} },
2122 { "jnsH", { Jv
, XX
, cond_jump_flag
} },
2123 { "jpH", { Jv
, XX
, cond_jump_flag
} },
2124 { "jnpH", { Jv
, XX
, cond_jump_flag
} },
2125 { "jlH", { Jv
, XX
, cond_jump_flag
} },
2126 { "jgeH", { Jv
, XX
, cond_jump_flag
} },
2127 { "jleH", { Jv
, XX
, cond_jump_flag
} },
2128 { "jgH", { Jv
, XX
, cond_jump_flag
} },
2131 { "setno", { Eb
} },
2133 { "setae", { Eb
} },
2135 { "setne", { Eb
} },
2136 { "setbe", { Eb
} },
2140 { "setns", { Eb
} },
2142 { "setnp", { Eb
} },
2144 { "setge", { Eb
} },
2145 { "setle", { Eb
} },
2148 { "pushT", { fs
} },
2150 { "cpuid", { XX
} },
2151 { "btS", { Ev
, Gv
} },
2152 { "shldS", { Ev
, Gv
, Ib
} },
2153 { "shldS", { Ev
, Gv
, CL
} },
2154 { REG_TABLE (REG_0FA6
) },
2155 { REG_TABLE (REG_0FA7
) },
2157 { "pushT", { gs
} },
2160 { "btsS", { Evh1
, Gv
} },
2161 { "shrdS", { Ev
, Gv
, Ib
} },
2162 { "shrdS", { Ev
, Gv
, CL
} },
2163 { REG_TABLE (REG_0FAE
) },
2164 { "imulS", { Gv
, Ev
} },
2166 { "cmpxchgB", { Ebh1
, Gb
} },
2167 { "cmpxchgS", { Evh1
, Gv
} },
2168 { MOD_TABLE (MOD_0FB2
) },
2169 { "btrS", { Evh1
, Gv
} },
2170 { MOD_TABLE (MOD_0FB4
) },
2171 { MOD_TABLE (MOD_0FB5
) },
2172 { "movz{bR|x}", { Gv
, Eb
} },
2173 { "movz{wR|x}", { Gv
, Ew
} }, /* yes, there really is movzww ! */
2175 { PREFIX_TABLE (PREFIX_0FB8
) },
2177 { REG_TABLE (REG_0FBA
) },
2178 { "btcS", { Evh1
, Gv
} },
2179 { PREFIX_TABLE (PREFIX_0FBC
) },
2180 { PREFIX_TABLE (PREFIX_0FBD
) },
2181 { "movs{bR|x}", { Gv
, Eb
} },
2182 { "movs{wR|x}", { Gv
, Ew
} }, /* yes, there really is movsww ! */
2184 { "xaddB", { Ebh1
, Gb
} },
2185 { "xaddS", { Evh1
, Gv
} },
2186 { PREFIX_TABLE (PREFIX_0FC2
) },
2187 { PREFIX_TABLE (PREFIX_0FC3
) },
2188 { "pinsrw", { MX
, Edqw
, Ib
} },
2189 { "pextrw", { Gdq
, MS
, Ib
} },
2190 { "shufpX", { XM
, EXx
, Ib
} },
2191 { REG_TABLE (REG_0FC7
) },
2193 { "bswap", { RMeAX
} },
2194 { "bswap", { RMeCX
} },
2195 { "bswap", { RMeDX
} },
2196 { "bswap", { RMeBX
} },
2197 { "bswap", { RMeSP
} },
2198 { "bswap", { RMeBP
} },
2199 { "bswap", { RMeSI
} },
2200 { "bswap", { RMeDI
} },
2202 { PREFIX_TABLE (PREFIX_0FD0
) },
2203 { "psrlw", { MX
, EM
} },
2204 { "psrld", { MX
, EM
} },
2205 { "psrlq", { MX
, EM
} },
2206 { "paddq", { MX
, EM
} },
2207 { "pmullw", { MX
, EM
} },
2208 { PREFIX_TABLE (PREFIX_0FD6
) },
2209 { MOD_TABLE (MOD_0FD7
) },
2211 { "psubusb", { MX
, EM
} },
2212 { "psubusw", { MX
, EM
} },
2213 { "pminub", { MX
, EM
} },
2214 { "pand", { MX
, EM
} },
2215 { "paddusb", { MX
, EM
} },
2216 { "paddusw", { MX
, EM
} },
2217 { "pmaxub", { MX
, EM
} },
2218 { "pandn", { MX
, EM
} },
2220 { "pavgb", { MX
, EM
} },
2221 { "psraw", { MX
, EM
} },
2222 { "psrad", { MX
, EM
} },
2223 { "pavgw", { MX
, EM
} },
2224 { "pmulhuw", { MX
, EM
} },
2225 { "pmulhw", { MX
, EM
} },
2226 { PREFIX_TABLE (PREFIX_0FE6
) },
2227 { PREFIX_TABLE (PREFIX_0FE7
) },
2229 { "psubsb", { MX
, EM
} },
2230 { "psubsw", { MX
, EM
} },
2231 { "pminsw", { MX
, EM
} },
2232 { "por", { MX
, EM
} },
2233 { "paddsb", { MX
, EM
} },
2234 { "paddsw", { MX
, EM
} },
2235 { "pmaxsw", { MX
, EM
} },
2236 { "pxor", { MX
, EM
} },
2238 { PREFIX_TABLE (PREFIX_0FF0
) },
2239 { "psllw", { MX
, EM
} },
2240 { "pslld", { MX
, EM
} },
2241 { "psllq", { MX
, EM
} },
2242 { "pmuludq", { MX
, EM
} },
2243 { "pmaddwd", { MX
, EM
} },
2244 { "psadbw", { MX
, EM
} },
2245 { PREFIX_TABLE (PREFIX_0FF7
) },
2247 { "psubb", { MX
, EM
} },
2248 { "psubw", { MX
, EM
} },
2249 { "psubd", { MX
, EM
} },
2250 { "psubq", { MX
, EM
} },
2251 { "paddb", { MX
, EM
} },
2252 { "paddw", { MX
, EM
} },
2253 { "paddd", { MX
, EM
} },
2257 static const unsigned char onebyte_has_modrm
[256] = {
2258 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2259 /* ------------------------------- */
2260 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2261 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2262 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2263 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2264 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2265 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2266 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2267 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2268 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2269 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2270 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2271 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2272 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2273 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2274 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2275 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2276 /* ------------------------------- */
2277 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2280 static const unsigned char twobyte_has_modrm
[256] = {
2281 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2282 /* ------------------------------- */
2283 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2284 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2285 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2286 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2287 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2288 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2289 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2290 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2291 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2292 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2293 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2294 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2295 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2296 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2297 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2298 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2299 /* ------------------------------- */
2300 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2303 static char obuf
[100];
2305 static char *mnemonicendp
;
2306 static char scratchbuf
[100];
2307 static unsigned char *start_codep
;
2308 static unsigned char *insn_codep
;
2309 static unsigned char *codep
;
2310 static int last_lock_prefix
;
2311 static int last_repz_prefix
;
2312 static int last_repnz_prefix
;
2313 static int last_data_prefix
;
2314 static int last_addr_prefix
;
2315 static int last_rex_prefix
;
2316 static int last_seg_prefix
;
2317 #define MAX_CODE_LENGTH 15
2318 /* We can up to 14 prefixes since the maximum instruction length is
2320 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2321 static disassemble_info
*the_info
;
2329 static unsigned char need_modrm
;
2339 int register_specifier
;
2345 static unsigned char need_vex
;
2346 static unsigned char need_vex_reg
;
2347 static unsigned char vex_w_done
;
2355 /* If we are accessing mod/rm/reg without need_modrm set, then the
2356 values are stale. Hitting this abort likely indicates that you
2357 need to update onebyte_has_modrm or twobyte_has_modrm. */
2358 #define MODRM_CHECK if (!need_modrm) abort ()
2360 static const char **names64
;
2361 static const char **names32
;
2362 static const char **names16
;
2363 static const char **names8
;
2364 static const char **names8rex
;
2365 static const char **names_seg
;
2366 static const char *index64
;
2367 static const char *index32
;
2368 static const char **index16
;
2370 static const char *intel_names64
[] = {
2371 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2372 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2374 static const char *intel_names32
[] = {
2375 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2376 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2378 static const char *intel_names16
[] = {
2379 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2380 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2382 static const char *intel_names8
[] = {
2383 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2385 static const char *intel_names8rex
[] = {
2386 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2387 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2389 static const char *intel_names_seg
[] = {
2390 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2392 static const char *intel_index64
= "riz";
2393 static const char *intel_index32
= "eiz";
2394 static const char *intel_index16
[] = {
2395 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2398 static const char *att_names64
[] = {
2399 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2400 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2402 static const char *att_names32
[] = {
2403 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2404 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2406 static const char *att_names16
[] = {
2407 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2408 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2410 static const char *att_names8
[] = {
2411 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2413 static const char *att_names8rex
[] = {
2414 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2415 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2417 static const char *att_names_seg
[] = {
2418 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2420 static const char *att_index64
= "%riz";
2421 static const char *att_index32
= "%eiz";
2422 static const char *att_index16
[] = {
2423 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2426 static const char **names_mm
;
2427 static const char *intel_names_mm
[] = {
2428 "mm0", "mm1", "mm2", "mm3",
2429 "mm4", "mm5", "mm6", "mm7"
2431 static const char *att_names_mm
[] = {
2432 "%mm0", "%mm1", "%mm2", "%mm3",
2433 "%mm4", "%mm5", "%mm6", "%mm7"
2436 static const char **names_xmm
;
2437 static const char *intel_names_xmm
[] = {
2438 "xmm0", "xmm1", "xmm2", "xmm3",
2439 "xmm4", "xmm5", "xmm6", "xmm7",
2440 "xmm8", "xmm9", "xmm10", "xmm11",
2441 "xmm12", "xmm13", "xmm14", "xmm15"
2443 static const char *att_names_xmm
[] = {
2444 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2445 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2446 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2447 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2450 static const char **names_ymm
;
2451 static const char *intel_names_ymm
[] = {
2452 "ymm0", "ymm1", "ymm2", "ymm3",
2453 "ymm4", "ymm5", "ymm6", "ymm7",
2454 "ymm8", "ymm9", "ymm10", "ymm11",
2455 "ymm12", "ymm13", "ymm14", "ymm15"
2457 static const char *att_names_ymm
[] = {
2458 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2459 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2460 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2461 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2464 static const struct dis386 reg_table
[][8] = {
2467 { "addA", { Ebh1
, Ib
} },
2468 { "orA", { Ebh1
, Ib
} },
2469 { "adcA", { Ebh1
, Ib
} },
2470 { "sbbA", { Ebh1
, Ib
} },
2471 { "andA", { Ebh1
, Ib
} },
2472 { "subA", { Ebh1
, Ib
} },
2473 { "xorA", { Ebh1
, Ib
} },
2474 { "cmpA", { Eb
, Ib
} },
2478 { "addQ", { Evh1
, Iv
} },
2479 { "orQ", { Evh1
, Iv
} },
2480 { "adcQ", { Evh1
, Iv
} },
2481 { "sbbQ", { Evh1
, Iv
} },
2482 { "andQ", { Evh1
, Iv
} },
2483 { "subQ", { Evh1
, Iv
} },
2484 { "xorQ", { Evh1
, Iv
} },
2485 { "cmpQ", { Ev
, Iv
} },
2489 { "addQ", { Evh1
, sIb
} },
2490 { "orQ", { Evh1
, sIb
} },
2491 { "adcQ", { Evh1
, sIb
} },
2492 { "sbbQ", { Evh1
, sIb
} },
2493 { "andQ", { Evh1
, sIb
} },
2494 { "subQ", { Evh1
, sIb
} },
2495 { "xorQ", { Evh1
, sIb
} },
2496 { "cmpQ", { Ev
, sIb
} },
2500 { "popU", { stackEv
} },
2501 { XOP_8F_TABLE (XOP_09
) },
2505 { XOP_8F_TABLE (XOP_09
) },
2509 { "rolA", { Eb
, Ib
} },
2510 { "rorA", { Eb
, Ib
} },
2511 { "rclA", { Eb
, Ib
} },
2512 { "rcrA", { Eb
, Ib
} },
2513 { "shlA", { Eb
, Ib
} },
2514 { "shrA", { Eb
, Ib
} },
2516 { "sarA", { Eb
, Ib
} },
2520 { "rolQ", { Ev
, Ib
} },
2521 { "rorQ", { Ev
, Ib
} },
2522 { "rclQ", { Ev
, Ib
} },
2523 { "rcrQ", { Ev
, Ib
} },
2524 { "shlQ", { Ev
, Ib
} },
2525 { "shrQ", { Ev
, Ib
} },
2527 { "sarQ", { Ev
, Ib
} },
2531 { "movA", { Ebh3
, Ib
} },
2538 { MOD_TABLE (MOD_C6_REG_7
) },
2542 { "movQ", { Evh3
, Iv
} },
2549 { MOD_TABLE (MOD_C7_REG_7
) },
2553 { "rolA", { Eb
, I1
} },
2554 { "rorA", { Eb
, I1
} },
2555 { "rclA", { Eb
, I1
} },
2556 { "rcrA", { Eb
, I1
} },
2557 { "shlA", { Eb
, I1
} },
2558 { "shrA", { Eb
, I1
} },
2560 { "sarA", { Eb
, I1
} },
2564 { "rolQ", { Ev
, I1
} },
2565 { "rorQ", { Ev
, I1
} },
2566 { "rclQ", { Ev
, I1
} },
2567 { "rcrQ", { Ev
, I1
} },
2568 { "shlQ", { Ev
, I1
} },
2569 { "shrQ", { Ev
, I1
} },
2571 { "sarQ", { Ev
, I1
} },
2575 { "rolA", { Eb
, CL
} },
2576 { "rorA", { Eb
, CL
} },
2577 { "rclA", { Eb
, CL
} },
2578 { "rcrA", { Eb
, CL
} },
2579 { "shlA", { Eb
, CL
} },
2580 { "shrA", { Eb
, CL
} },
2582 { "sarA", { Eb
, CL
} },
2586 { "rolQ", { Ev
, CL
} },
2587 { "rorQ", { Ev
, CL
} },
2588 { "rclQ", { Ev
, CL
} },
2589 { "rcrQ", { Ev
, CL
} },
2590 { "shlQ", { Ev
, CL
} },
2591 { "shrQ", { Ev
, CL
} },
2593 { "sarQ", { Ev
, CL
} },
2597 { "testA", { Eb
, Ib
} },
2599 { "notA", { Ebh1
} },
2600 { "negA", { Ebh1
} },
2601 { "mulA", { Eb
} }, /* Don't print the implicit %al register, */
2602 { "imulA", { Eb
} }, /* to distinguish these opcodes from other */
2603 { "divA", { Eb
} }, /* mul/imul opcodes. Do the same for div */
2604 { "idivA", { Eb
} }, /* and idiv for consistency. */
2608 { "testQ", { Ev
, Iv
} },
2610 { "notQ", { Evh1
} },
2611 { "negQ", { Evh1
} },
2612 { "mulQ", { Ev
} }, /* Don't print the implicit register. */
2613 { "imulQ", { Ev
} },
2615 { "idivQ", { Ev
} },
2619 { "incA", { Ebh1
} },
2620 { "decA", { Ebh1
} },
2624 { "incQ", { Evh1
} },
2625 { "decQ", { Evh1
} },
2626 { "call{T|}", { indirEv
} },
2627 { "Jcall{T|}", { indirEp
} },
2628 { "jmp{T|}", { indirEv
} },
2629 { "Jjmp{T|}", { indirEp
} },
2630 { "pushU", { stackEv
} },
2635 { "sldtD", { Sv
} },
2646 { MOD_TABLE (MOD_0F01_REG_0
) },
2647 { MOD_TABLE (MOD_0F01_REG_1
) },
2648 { MOD_TABLE (MOD_0F01_REG_2
) },
2649 { MOD_TABLE (MOD_0F01_REG_3
) },
2650 { "smswD", { Sv
} },
2653 { MOD_TABLE (MOD_0F01_REG_7
) },
2657 { "prefetch", { Mb
} },
2658 { "prefetchw", { Mb
} },
2659 { "prefetch", { Mb
} },
2660 { "prefetch", { Mb
} },
2661 { "prefetch", { Mb
} },
2662 { "prefetch", { Mb
} },
2663 { "prefetch", { Mb
} },
2664 { "prefetch", { Mb
} },
2668 { MOD_TABLE (MOD_0F18_REG_0
) },
2669 { MOD_TABLE (MOD_0F18_REG_1
) },
2670 { MOD_TABLE (MOD_0F18_REG_2
) },
2671 { MOD_TABLE (MOD_0F18_REG_3
) },
2672 { MOD_TABLE (MOD_0F18_REG_4
) },
2673 { MOD_TABLE (MOD_0F18_REG_5
) },
2674 { MOD_TABLE (MOD_0F18_REG_6
) },
2675 { MOD_TABLE (MOD_0F18_REG_7
) },
2681 { MOD_TABLE (MOD_0F71_REG_2
) },
2683 { MOD_TABLE (MOD_0F71_REG_4
) },
2685 { MOD_TABLE (MOD_0F71_REG_6
) },
2691 { MOD_TABLE (MOD_0F72_REG_2
) },
2693 { MOD_TABLE (MOD_0F72_REG_4
) },
2695 { MOD_TABLE (MOD_0F72_REG_6
) },
2701 { MOD_TABLE (MOD_0F73_REG_2
) },
2702 { MOD_TABLE (MOD_0F73_REG_3
) },
2705 { MOD_TABLE (MOD_0F73_REG_6
) },
2706 { MOD_TABLE (MOD_0F73_REG_7
) },
2710 { "montmul", { { OP_0f07
, 0 } } },
2711 { "xsha1", { { OP_0f07
, 0 } } },
2712 { "xsha256", { { OP_0f07
, 0 } } },
2716 { "xstore-rng", { { OP_0f07
, 0 } } },
2717 { "xcrypt-ecb", { { OP_0f07
, 0 } } },
2718 { "xcrypt-cbc", { { OP_0f07
, 0 } } },
2719 { "xcrypt-ctr", { { OP_0f07
, 0 } } },
2720 { "xcrypt-cfb", { { OP_0f07
, 0 } } },
2721 { "xcrypt-ofb", { { OP_0f07
, 0 } } },
2725 { MOD_TABLE (MOD_0FAE_REG_0
) },
2726 { MOD_TABLE (MOD_0FAE_REG_1
) },
2727 { MOD_TABLE (MOD_0FAE_REG_2
) },
2728 { MOD_TABLE (MOD_0FAE_REG_3
) },
2729 { MOD_TABLE (MOD_0FAE_REG_4
) },
2730 { MOD_TABLE (MOD_0FAE_REG_5
) },
2731 { MOD_TABLE (MOD_0FAE_REG_6
) },
2732 { MOD_TABLE (MOD_0FAE_REG_7
) },
2740 { "btQ", { Ev
, Ib
} },
2741 { "btsQ", { Evh1
, Ib
} },
2742 { "btrQ", { Evh1
, Ib
} },
2743 { "btcQ", { Evh1
, Ib
} },
2748 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} } },
2753 { MOD_TABLE (MOD_0FC7_REG_6
) },
2754 { MOD_TABLE (MOD_0FC7_REG_7
) },
2760 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
2762 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
2764 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
2770 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
2772 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
2774 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
2780 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
2781 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
2784 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
2785 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
2791 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
2792 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
2794 /* REG_VEX_0F38F3 */
2797 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
2798 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
2799 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
2803 { "llwpcb", { { OP_LWPCB_E
, 0 } } },
2804 { "slwpcb", { { OP_LWPCB_E
, 0 } } },
2808 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
2809 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
2811 /* REG_XOP_TBM_01 */
2814 { "blcfill", { { OP_LWP_E
, 0 }, Ev
} },
2815 { "blsfill", { { OP_LWP_E
, 0 }, Ev
} },
2816 { "blcs", { { OP_LWP_E
, 0 }, Ev
} },
2817 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
} },
2818 { "blcic", { { OP_LWP_E
, 0 }, Ev
} },
2819 { "blsic", { { OP_LWP_E
, 0 }, Ev
} },
2820 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
} },
2822 /* REG_XOP_TBM_02 */
2825 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
} },
2830 { "blci", { { OP_LWP_E
, 0 }, Ev
} },
2834 static const struct dis386 prefix_table
[][4] = {
2837 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
2838 { "pause", { XX
} },
2839 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
2844 { "movups", { XM
, EXx
} },
2845 { "movss", { XM
, EXd
} },
2846 { "movupd", { XM
, EXx
} },
2847 { "movsd", { XM
, EXq
} },
2852 { "movups", { EXxS
, XM
} },
2853 { "movss", { EXdS
, XM
} },
2854 { "movupd", { EXxS
, XM
} },
2855 { "movsd", { EXqS
, XM
} },
2860 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
2861 { "movsldup", { XM
, EXx
} },
2862 { "movlpd", { XM
, EXq
} },
2863 { "movddup", { XM
, EXq
} },
2868 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
2869 { "movshdup", { XM
, EXx
} },
2870 { "movhpd", { XM
, EXq
} },
2875 { "cvtpi2ps", { XM
, EMCq
} },
2876 { "cvtsi2ss%LQ", { XM
, Ev
} },
2877 { "cvtpi2pd", { XM
, EMCq
} },
2878 { "cvtsi2sd%LQ", { XM
, Ev
} },
2883 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
2884 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
2885 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
2886 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
2891 { "cvttps2pi", { MXC
, EXq
} },
2892 { "cvttss2siY", { Gv
, EXd
} },
2893 { "cvttpd2pi", { MXC
, EXx
} },
2894 { "cvttsd2siY", { Gv
, EXq
} },
2899 { "cvtps2pi", { MXC
, EXq
} },
2900 { "cvtss2siY", { Gv
, EXd
} },
2901 { "cvtpd2pi", { MXC
, EXx
} },
2902 { "cvtsd2siY", { Gv
, EXq
} },
2907 { "ucomiss",{ XM
, EXd
} },
2909 { "ucomisd",{ XM
, EXq
} },
2914 { "comiss", { XM
, EXd
} },
2916 { "comisd", { XM
, EXq
} },
2921 { "sqrtps", { XM
, EXx
} },
2922 { "sqrtss", { XM
, EXd
} },
2923 { "sqrtpd", { XM
, EXx
} },
2924 { "sqrtsd", { XM
, EXq
} },
2929 { "rsqrtps",{ XM
, EXx
} },
2930 { "rsqrtss",{ XM
, EXd
} },
2935 { "rcpps", { XM
, EXx
} },
2936 { "rcpss", { XM
, EXd
} },
2941 { "addps", { XM
, EXx
} },
2942 { "addss", { XM
, EXd
} },
2943 { "addpd", { XM
, EXx
} },
2944 { "addsd", { XM
, EXq
} },
2949 { "mulps", { XM
, EXx
} },
2950 { "mulss", { XM
, EXd
} },
2951 { "mulpd", { XM
, EXx
} },
2952 { "mulsd", { XM
, EXq
} },
2957 { "cvtps2pd", { XM
, EXq
} },
2958 { "cvtss2sd", { XM
, EXd
} },
2959 { "cvtpd2ps", { XM
, EXx
} },
2960 { "cvtsd2ss", { XM
, EXq
} },
2965 { "cvtdq2ps", { XM
, EXx
} },
2966 { "cvttps2dq", { XM
, EXx
} },
2967 { "cvtps2dq", { XM
, EXx
} },
2972 { "subps", { XM
, EXx
} },
2973 { "subss", { XM
, EXd
} },
2974 { "subpd", { XM
, EXx
} },
2975 { "subsd", { XM
, EXq
} },
2980 { "minps", { XM
, EXx
} },
2981 { "minss", { XM
, EXd
} },
2982 { "minpd", { XM
, EXx
} },
2983 { "minsd", { XM
, EXq
} },
2988 { "divps", { XM
, EXx
} },
2989 { "divss", { XM
, EXd
} },
2990 { "divpd", { XM
, EXx
} },
2991 { "divsd", { XM
, EXq
} },
2996 { "maxps", { XM
, EXx
} },
2997 { "maxss", { XM
, EXd
} },
2998 { "maxpd", { XM
, EXx
} },
2999 { "maxsd", { XM
, EXq
} },
3004 { "punpcklbw",{ MX
, EMd
} },
3006 { "punpcklbw",{ MX
, EMx
} },
3011 { "punpcklwd",{ MX
, EMd
} },
3013 { "punpcklwd",{ MX
, EMx
} },
3018 { "punpckldq",{ MX
, EMd
} },
3020 { "punpckldq",{ MX
, EMx
} },
3027 { "punpcklqdq", { XM
, EXx
} },
3034 { "punpckhqdq", { XM
, EXx
} },
3039 { "movq", { MX
, EM
} },
3040 { "movdqu", { XM
, EXx
} },
3041 { "movdqa", { XM
, EXx
} },
3046 { "pshufw", { MX
, EM
, Ib
} },
3047 { "pshufhw",{ XM
, EXx
, Ib
} },
3048 { "pshufd", { XM
, EXx
, Ib
} },
3049 { "pshuflw",{ XM
, EXx
, Ib
} },
3052 /* PREFIX_0F73_REG_3 */
3056 { "psrldq", { XS
, Ib
} },
3059 /* PREFIX_0F73_REG_7 */
3063 { "pslldq", { XS
, Ib
} },
3068 {"vmread", { Em
, Gm
} },
3070 {"extrq", { XS
, Ib
, Ib
} },
3071 {"insertq", { XM
, XS
, Ib
, Ib
} },
3076 {"vmwrite", { Gm
, Em
} },
3078 {"extrq", { XM
, XS
} },
3079 {"insertq", { XM
, XS
} },
3086 { "haddpd", { XM
, EXx
} },
3087 { "haddps", { XM
, EXx
} },
3094 { "hsubpd", { XM
, EXx
} },
3095 { "hsubps", { XM
, EXx
} },
3100 { "movK", { Edq
, MX
} },
3101 { "movq", { XM
, EXq
} },
3102 { "movK", { Edq
, XM
} },
3107 { "movq", { EMS
, MX
} },
3108 { "movdqu", { EXxS
, XM
} },
3109 { "movdqa", { EXxS
, XM
} },
3112 /* PREFIX_0FAE_REG_0 */
3115 { "rdfsbase", { Ev
} },
3118 /* PREFIX_0FAE_REG_1 */
3121 { "rdgsbase", { Ev
} },
3124 /* PREFIX_0FAE_REG_2 */
3127 { "wrfsbase", { Ev
} },
3130 /* PREFIX_0FAE_REG_3 */
3133 { "wrgsbase", { Ev
} },
3139 { "popcntS", { Gv
, Ev
} },
3144 { "bsfS", { Gv
, Ev
} },
3145 { "tzcntS", { Gv
, Ev
} },
3146 { "bsfS", { Gv
, Ev
} },
3151 { "bsrS", { Gv
, Ev
} },
3152 { "lzcntS", { Gv
, Ev
} },
3153 { "bsrS", { Gv
, Ev
} },
3158 { "cmpps", { XM
, EXx
, CMP
} },
3159 { "cmpss", { XM
, EXd
, CMP
} },
3160 { "cmppd", { XM
, EXx
, CMP
} },
3161 { "cmpsd", { XM
, EXq
, CMP
} },
3166 { "movntiS", { Ma
, Gv
} },
3169 /* PREFIX_0FC7_REG_6 */
3171 { "vmptrld",{ Mq
} },
3172 { "vmxon", { Mq
} },
3173 { "vmclear",{ Mq
} },
3180 { "addsubpd", { XM
, EXx
} },
3181 { "addsubps", { XM
, EXx
} },
3187 { "movq2dq",{ XM
, MS
} },
3188 { "movq", { EXqS
, XM
} },
3189 { "movdq2q",{ MX
, XS
} },
3195 { "cvtdq2pd", { XM
, EXq
} },
3196 { "cvttpd2dq", { XM
, EXx
} },
3197 { "cvtpd2dq", { XM
, EXx
} },
3202 { "movntq", { Mq
, MX
} },
3204 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3212 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3217 { "maskmovq", { MX
, MS
} },
3219 { "maskmovdqu", { XM
, XS
} },
3226 { "pblendvb", { XM
, EXx
, XMM0
} },
3233 { "blendvps", { XM
, EXx
, XMM0
} },
3240 { "blendvpd", { XM
, EXx
, XMM0
} },
3247 { "ptest", { XM
, EXx
} },
3254 { "pmovsxbw", { XM
, EXq
} },
3261 { "pmovsxbd", { XM
, EXd
} },
3268 { "pmovsxbq", { XM
, EXw
} },
3275 { "pmovsxwd", { XM
, EXq
} },
3282 { "pmovsxwq", { XM
, EXd
} },
3289 { "pmovsxdq", { XM
, EXq
} },
3296 { "pmuldq", { XM
, EXx
} },
3303 { "pcmpeqq", { XM
, EXx
} },
3310 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
3317 { "packusdw", { XM
, EXx
} },
3324 { "pmovzxbw", { XM
, EXq
} },
3331 { "pmovzxbd", { XM
, EXd
} },
3338 { "pmovzxbq", { XM
, EXw
} },
3345 { "pmovzxwd", { XM
, EXq
} },
3352 { "pmovzxwq", { XM
, EXd
} },
3359 { "pmovzxdq", { XM
, EXq
} },
3366 { "pcmpgtq", { XM
, EXx
} },
3373 { "pminsb", { XM
, EXx
} },
3380 { "pminsd", { XM
, EXx
} },
3387 { "pminuw", { XM
, EXx
} },
3394 { "pminud", { XM
, EXx
} },
3401 { "pmaxsb", { XM
, EXx
} },
3408 { "pmaxsd", { XM
, EXx
} },
3415 { "pmaxuw", { XM
, EXx
} },
3422 { "pmaxud", { XM
, EXx
} },
3429 { "pmulld", { XM
, EXx
} },
3436 { "phminposuw", { XM
, EXx
} },
3443 { "invept", { Gm
, Mo
} },
3450 { "invvpid", { Gm
, Mo
} },
3457 { "invpcid", { Gm
, M
} },
3464 { "aesimc", { XM
, EXx
} },
3471 { "aesenc", { XM
, EXx
} },
3478 { "aesenclast", { XM
, EXx
} },
3485 { "aesdec", { XM
, EXx
} },
3492 { "aesdeclast", { XM
, EXx
} },
3497 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
3499 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
3500 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} } },
3505 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
3507 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
3508 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} } },
3514 { "adoxS", { Gdq
, Edq
} },
3515 { "adcxS", { Gdq
, Edq
} },
3523 { "roundps", { XM
, EXx
, Ib
} },
3530 { "roundpd", { XM
, EXx
, Ib
} },
3537 { "roundss", { XM
, EXd
, Ib
} },
3544 { "roundsd", { XM
, EXq
, Ib
} },
3551 { "blendps", { XM
, EXx
, Ib
} },
3558 { "blendpd", { XM
, EXx
, Ib
} },
3565 { "pblendw", { XM
, EXx
, Ib
} },
3572 { "pextrb", { Edqb
, XM
, Ib
} },
3579 { "pextrw", { Edqw
, XM
, Ib
} },
3586 { "pextrK", { Edq
, XM
, Ib
} },
3593 { "extractps", { Edqd
, XM
, Ib
} },
3600 { "pinsrb", { XM
, Edqb
, Ib
} },
3607 { "insertps", { XM
, EXd
, Ib
} },
3614 { "pinsrK", { XM
, Edq
, Ib
} },
3621 { "dpps", { XM
, EXx
, Ib
} },
3628 { "dppd", { XM
, EXx
, Ib
} },
3635 { "mpsadbw", { XM
, EXx
, Ib
} },
3642 { "pclmulqdq", { XM
, EXx
, PCLMUL
} },
3649 { "pcmpestrm", { XM
, EXx
, Ib
} },
3656 { "pcmpestri", { XM
, EXx
, Ib
} },
3663 { "pcmpistrm", { XM
, EXx
, Ib
} },
3670 { "pcmpistri", { XM
, EXx
, Ib
} },
3677 { "aeskeygenassist", { XM
, EXx
, Ib
} },
3680 /* PREFIX_VEX_0F10 */
3682 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
3683 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
3684 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
3685 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
3688 /* PREFIX_VEX_0F11 */
3690 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
3691 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
3692 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
3693 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
3696 /* PREFIX_VEX_0F12 */
3698 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
3699 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
3700 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
3701 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
3704 /* PREFIX_VEX_0F16 */
3706 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
3707 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
3708 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
3711 /* PREFIX_VEX_0F2A */
3714 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
3716 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
3719 /* PREFIX_VEX_0F2C */
3722 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
3724 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
3727 /* PREFIX_VEX_0F2D */
3730 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
3732 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
3735 /* PREFIX_VEX_0F2E */
3737 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
3739 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
3742 /* PREFIX_VEX_0F2F */
3744 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
3746 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
3749 /* PREFIX_VEX_0F51 */
3751 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
3752 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
3753 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
3754 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
3757 /* PREFIX_VEX_0F52 */
3759 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
3760 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
3763 /* PREFIX_VEX_0F53 */
3765 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
3766 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
3769 /* PREFIX_VEX_0F58 */
3771 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
3772 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
3773 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
3774 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
3777 /* PREFIX_VEX_0F59 */
3779 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
3780 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
3781 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
3782 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
3785 /* PREFIX_VEX_0F5A */
3787 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
3788 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
3789 { "vcvtpd2ps%XY", { XMM
, EXx
} },
3790 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
3793 /* PREFIX_VEX_0F5B */
3795 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
3796 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
3797 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
3800 /* PREFIX_VEX_0F5C */
3802 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
3803 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
3804 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
3805 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
3808 /* PREFIX_VEX_0F5D */
3810 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
3811 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
3812 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
3813 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
3816 /* PREFIX_VEX_0F5E */
3818 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
3819 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
3820 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
3821 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
3824 /* PREFIX_VEX_0F5F */
3826 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
3827 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
3828 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
3829 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
3832 /* PREFIX_VEX_0F60 */
3836 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
3839 /* PREFIX_VEX_0F61 */
3843 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
3846 /* PREFIX_VEX_0F62 */
3850 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
3853 /* PREFIX_VEX_0F63 */
3857 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
3860 /* PREFIX_VEX_0F64 */
3864 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
3867 /* PREFIX_VEX_0F65 */
3871 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
3874 /* PREFIX_VEX_0F66 */
3878 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
3881 /* PREFIX_VEX_0F67 */
3885 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
3888 /* PREFIX_VEX_0F68 */
3892 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
3895 /* PREFIX_VEX_0F69 */
3899 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
3902 /* PREFIX_VEX_0F6A */
3906 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
3909 /* PREFIX_VEX_0F6B */
3913 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
3916 /* PREFIX_VEX_0F6C */
3920 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
3923 /* PREFIX_VEX_0F6D */
3927 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
3930 /* PREFIX_VEX_0F6E */
3934 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
3937 /* PREFIX_VEX_0F6F */
3940 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
3941 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
3944 /* PREFIX_VEX_0F70 */
3947 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
3948 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
3949 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
3952 /* PREFIX_VEX_0F71_REG_2 */
3956 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
3959 /* PREFIX_VEX_0F71_REG_4 */
3963 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
3966 /* PREFIX_VEX_0F71_REG_6 */
3970 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
3973 /* PREFIX_VEX_0F72_REG_2 */
3977 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
3980 /* PREFIX_VEX_0F72_REG_4 */
3984 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
3987 /* PREFIX_VEX_0F72_REG_6 */
3991 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
3994 /* PREFIX_VEX_0F73_REG_2 */
3998 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
4001 /* PREFIX_VEX_0F73_REG_3 */
4005 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
4008 /* PREFIX_VEX_0F73_REG_6 */
4012 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
4015 /* PREFIX_VEX_0F73_REG_7 */
4019 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
4022 /* PREFIX_VEX_0F74 */
4026 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
4029 /* PREFIX_VEX_0F75 */
4033 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
4036 /* PREFIX_VEX_0F76 */
4040 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
4043 /* PREFIX_VEX_0F77 */
4045 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
4048 /* PREFIX_VEX_0F7C */
4052 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
4053 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
4056 /* PREFIX_VEX_0F7D */
4060 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
4061 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
4064 /* PREFIX_VEX_0F7E */
4067 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
4068 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
4071 /* PREFIX_VEX_0F7F */
4074 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
4075 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
4078 /* PREFIX_VEX_0FC2 */
4080 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
4081 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
4082 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
4083 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
4086 /* PREFIX_VEX_0FC4 */
4090 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
4093 /* PREFIX_VEX_0FC5 */
4097 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
4100 /* PREFIX_VEX_0FD0 */
4104 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
4105 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
4108 /* PREFIX_VEX_0FD1 */
4112 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
4115 /* PREFIX_VEX_0FD2 */
4119 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
4122 /* PREFIX_VEX_0FD3 */
4126 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
4129 /* PREFIX_VEX_0FD4 */
4133 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
4136 /* PREFIX_VEX_0FD5 */
4140 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
4143 /* PREFIX_VEX_0FD6 */
4147 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
4150 /* PREFIX_VEX_0FD7 */
4154 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
4157 /* PREFIX_VEX_0FD8 */
4161 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
4164 /* PREFIX_VEX_0FD9 */
4168 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
4171 /* PREFIX_VEX_0FDA */
4175 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
4178 /* PREFIX_VEX_0FDB */
4182 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
4185 /* PREFIX_VEX_0FDC */
4189 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
4192 /* PREFIX_VEX_0FDD */
4196 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
4199 /* PREFIX_VEX_0FDE */
4203 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
4206 /* PREFIX_VEX_0FDF */
4210 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
4213 /* PREFIX_VEX_0FE0 */
4217 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
4220 /* PREFIX_VEX_0FE1 */
4224 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
4227 /* PREFIX_VEX_0FE2 */
4231 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
4234 /* PREFIX_VEX_0FE3 */
4238 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
4241 /* PREFIX_VEX_0FE4 */
4245 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
4248 /* PREFIX_VEX_0FE5 */
4252 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
4255 /* PREFIX_VEX_0FE6 */
4258 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
4259 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
4260 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
4263 /* PREFIX_VEX_0FE7 */
4267 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
4270 /* PREFIX_VEX_0FE8 */
4274 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
4277 /* PREFIX_VEX_0FE9 */
4281 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
4284 /* PREFIX_VEX_0FEA */
4288 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
4291 /* PREFIX_VEX_0FEB */
4295 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
4298 /* PREFIX_VEX_0FEC */
4302 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
4305 /* PREFIX_VEX_0FED */
4309 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
4312 /* PREFIX_VEX_0FEE */
4316 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
4319 /* PREFIX_VEX_0FEF */
4323 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
4326 /* PREFIX_VEX_0FF0 */
4331 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
4334 /* PREFIX_VEX_0FF1 */
4338 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
4341 /* PREFIX_VEX_0FF2 */
4345 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
4348 /* PREFIX_VEX_0FF3 */
4352 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
4355 /* PREFIX_VEX_0FF4 */
4359 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
4362 /* PREFIX_VEX_0FF5 */
4366 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
4369 /* PREFIX_VEX_0FF6 */
4373 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
4376 /* PREFIX_VEX_0FF7 */
4380 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
4383 /* PREFIX_VEX_0FF8 */
4387 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
4390 /* PREFIX_VEX_0FF9 */
4394 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
4397 /* PREFIX_VEX_0FFA */
4401 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
4404 /* PREFIX_VEX_0FFB */
4408 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
4411 /* PREFIX_VEX_0FFC */
4415 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
4418 /* PREFIX_VEX_0FFD */
4422 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
4425 /* PREFIX_VEX_0FFE */
4429 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
4432 /* PREFIX_VEX_0F3800 */
4436 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
4439 /* PREFIX_VEX_0F3801 */
4443 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
4446 /* PREFIX_VEX_0F3802 */
4450 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
4453 /* PREFIX_VEX_0F3803 */
4457 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
4460 /* PREFIX_VEX_0F3804 */
4464 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
4467 /* PREFIX_VEX_0F3805 */
4471 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
4474 /* PREFIX_VEX_0F3806 */
4478 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
4481 /* PREFIX_VEX_0F3807 */
4485 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
4488 /* PREFIX_VEX_0F3808 */
4492 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
4495 /* PREFIX_VEX_0F3809 */
4499 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
4502 /* PREFIX_VEX_0F380A */
4506 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
4509 /* PREFIX_VEX_0F380B */
4513 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
4516 /* PREFIX_VEX_0F380C */
4520 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
4523 /* PREFIX_VEX_0F380D */
4527 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
4530 /* PREFIX_VEX_0F380E */
4534 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
4537 /* PREFIX_VEX_0F380F */
4541 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
4544 /* PREFIX_VEX_0F3813 */
4548 { "vcvtph2ps", { XM
, EXxmmq
} },
4551 /* PREFIX_VEX_0F3816 */
4555 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
4558 /* PREFIX_VEX_0F3817 */
4562 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
4565 /* PREFIX_VEX_0F3818 */
4569 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
4572 /* PREFIX_VEX_0F3819 */
4576 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
4579 /* PREFIX_VEX_0F381A */
4583 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
4586 /* PREFIX_VEX_0F381C */
4590 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
4593 /* PREFIX_VEX_0F381D */
4597 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
4600 /* PREFIX_VEX_0F381E */
4604 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
4607 /* PREFIX_VEX_0F3820 */
4611 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
4614 /* PREFIX_VEX_0F3821 */
4618 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
4621 /* PREFIX_VEX_0F3822 */
4625 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
4628 /* PREFIX_VEX_0F3823 */
4632 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
4635 /* PREFIX_VEX_0F3824 */
4639 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
4642 /* PREFIX_VEX_0F3825 */
4646 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
4649 /* PREFIX_VEX_0F3828 */
4653 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
4656 /* PREFIX_VEX_0F3829 */
4660 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
4663 /* PREFIX_VEX_0F382A */
4667 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
4670 /* PREFIX_VEX_0F382B */
4674 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
4677 /* PREFIX_VEX_0F382C */
4681 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
4684 /* PREFIX_VEX_0F382D */
4688 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
4691 /* PREFIX_VEX_0F382E */
4695 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
4698 /* PREFIX_VEX_0F382F */
4702 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
4705 /* PREFIX_VEX_0F3830 */
4709 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
4712 /* PREFIX_VEX_0F3831 */
4716 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
4719 /* PREFIX_VEX_0F3832 */
4723 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
4726 /* PREFIX_VEX_0F3833 */
4730 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
4733 /* PREFIX_VEX_0F3834 */
4737 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
4740 /* PREFIX_VEX_0F3835 */
4744 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
4747 /* PREFIX_VEX_0F3836 */
4751 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
4754 /* PREFIX_VEX_0F3837 */
4758 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
4761 /* PREFIX_VEX_0F3838 */
4765 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
4768 /* PREFIX_VEX_0F3839 */
4772 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
4775 /* PREFIX_VEX_0F383A */
4779 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
4782 /* PREFIX_VEX_0F383B */
4786 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
4789 /* PREFIX_VEX_0F383C */
4793 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
4796 /* PREFIX_VEX_0F383D */
4800 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
4803 /* PREFIX_VEX_0F383E */
4807 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
4810 /* PREFIX_VEX_0F383F */
4814 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
4817 /* PREFIX_VEX_0F3840 */
4821 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
4824 /* PREFIX_VEX_0F3841 */
4828 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
4831 /* PREFIX_VEX_0F3845 */
4835 { "vpsrlv%LW", { XM
, Vex
, EXx
} },
4838 /* PREFIX_VEX_0F3846 */
4842 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
4845 /* PREFIX_VEX_0F3847 */
4849 { "vpsllv%LW", { XM
, Vex
, EXx
} },
4852 /* PREFIX_VEX_0F3858 */
4856 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
4859 /* PREFIX_VEX_0F3859 */
4863 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
4866 /* PREFIX_VEX_0F385A */
4870 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
4873 /* PREFIX_VEX_0F3878 */
4877 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
4880 /* PREFIX_VEX_0F3879 */
4884 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
4887 /* PREFIX_VEX_0F388C */
4891 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
4894 /* PREFIX_VEX_0F388E */
4898 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
4901 /* PREFIX_VEX_0F3890 */
4905 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
} },
4908 /* PREFIX_VEX_0F3891 */
4912 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
} },
4915 /* PREFIX_VEX_0F3892 */
4919 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
} },
4922 /* PREFIX_VEX_0F3893 */
4926 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
} },
4929 /* PREFIX_VEX_0F3896 */
4933 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
} },
4936 /* PREFIX_VEX_0F3897 */
4940 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
} },
4943 /* PREFIX_VEX_0F3898 */
4947 { "vfmadd132p%XW", { XM
, Vex
, EXx
} },
4950 /* PREFIX_VEX_0F3899 */
4954 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4957 /* PREFIX_VEX_0F389A */
4961 { "vfmsub132p%XW", { XM
, Vex
, EXx
} },
4964 /* PREFIX_VEX_0F389B */
4968 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4971 /* PREFIX_VEX_0F389C */
4975 { "vfnmadd132p%XW", { XM
, Vex
, EXx
} },
4978 /* PREFIX_VEX_0F389D */
4982 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4985 /* PREFIX_VEX_0F389E */
4989 { "vfnmsub132p%XW", { XM
, Vex
, EXx
} },
4992 /* PREFIX_VEX_0F389F */
4996 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4999 /* PREFIX_VEX_0F38A6 */
5003 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
} },
5007 /* PREFIX_VEX_0F38A7 */
5011 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
} },
5014 /* PREFIX_VEX_0F38A8 */
5018 { "vfmadd213p%XW", { XM
, Vex
, EXx
} },
5021 /* PREFIX_VEX_0F38A9 */
5025 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5028 /* PREFIX_VEX_0F38AA */
5032 { "vfmsub213p%XW", { XM
, Vex
, EXx
} },
5035 /* PREFIX_VEX_0F38AB */
5039 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5042 /* PREFIX_VEX_0F38AC */
5046 { "vfnmadd213p%XW", { XM
, Vex
, EXx
} },
5049 /* PREFIX_VEX_0F38AD */
5053 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5056 /* PREFIX_VEX_0F38AE */
5060 { "vfnmsub213p%XW", { XM
, Vex
, EXx
} },
5063 /* PREFIX_VEX_0F38AF */
5067 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5070 /* PREFIX_VEX_0F38B6 */
5074 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
} },
5077 /* PREFIX_VEX_0F38B7 */
5081 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
} },
5084 /* PREFIX_VEX_0F38B8 */
5088 { "vfmadd231p%XW", { XM
, Vex
, EXx
} },
5091 /* PREFIX_VEX_0F38B9 */
5095 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5098 /* PREFIX_VEX_0F38BA */
5102 { "vfmsub231p%XW", { XM
, Vex
, EXx
} },
5105 /* PREFIX_VEX_0F38BB */
5109 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5112 /* PREFIX_VEX_0F38BC */
5116 { "vfnmadd231p%XW", { XM
, Vex
, EXx
} },
5119 /* PREFIX_VEX_0F38BD */
5123 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5126 /* PREFIX_VEX_0F38BE */
5130 { "vfnmsub231p%XW", { XM
, Vex
, EXx
} },
5133 /* PREFIX_VEX_0F38BF */
5137 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5140 /* PREFIX_VEX_0F38DB */
5144 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
5147 /* PREFIX_VEX_0F38DC */
5151 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
5154 /* PREFIX_VEX_0F38DD */
5158 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
5161 /* PREFIX_VEX_0F38DE */
5165 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
5168 /* PREFIX_VEX_0F38DF */
5172 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
5175 /* PREFIX_VEX_0F38F2 */
5177 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
5180 /* PREFIX_VEX_0F38F3_REG_1 */
5182 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
5185 /* PREFIX_VEX_0F38F3_REG_2 */
5187 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
5190 /* PREFIX_VEX_0F38F3_REG_3 */
5192 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
5195 /* PREFIX_VEX_0F38F5 */
5197 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
5198 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
5200 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
5203 /* PREFIX_VEX_0F38F6 */
5208 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
5211 /* PREFIX_VEX_0F38F7 */
5213 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
5214 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
5215 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
5216 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
5219 /* PREFIX_VEX_0F3A00 */
5223 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
5226 /* PREFIX_VEX_0F3A01 */
5230 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
5233 /* PREFIX_VEX_0F3A02 */
5237 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
5240 /* PREFIX_VEX_0F3A04 */
5244 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
5247 /* PREFIX_VEX_0F3A05 */
5251 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
5254 /* PREFIX_VEX_0F3A06 */
5258 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
5261 /* PREFIX_VEX_0F3A08 */
5265 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
5268 /* PREFIX_VEX_0F3A09 */
5272 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
5275 /* PREFIX_VEX_0F3A0A */
5279 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
5282 /* PREFIX_VEX_0F3A0B */
5286 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
5289 /* PREFIX_VEX_0F3A0C */
5293 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
5296 /* PREFIX_VEX_0F3A0D */
5300 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
5303 /* PREFIX_VEX_0F3A0E */
5307 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
5310 /* PREFIX_VEX_0F3A0F */
5314 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
5317 /* PREFIX_VEX_0F3A14 */
5321 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
5324 /* PREFIX_VEX_0F3A15 */
5328 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
5331 /* PREFIX_VEX_0F3A16 */
5335 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
5338 /* PREFIX_VEX_0F3A17 */
5342 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
5345 /* PREFIX_VEX_0F3A18 */
5349 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
5352 /* PREFIX_VEX_0F3A19 */
5356 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
5359 /* PREFIX_VEX_0F3A1D */
5363 { "vcvtps2ph", { EXxmmq
, XM
, Ib
} },
5366 /* PREFIX_VEX_0F3A20 */
5370 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
5373 /* PREFIX_VEX_0F3A21 */
5377 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
5380 /* PREFIX_VEX_0F3A22 */
5384 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
5387 /* PREFIX_VEX_0F3A38 */
5391 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
5394 /* PREFIX_VEX_0F3A39 */
5398 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
5401 /* PREFIX_VEX_0F3A40 */
5405 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
5408 /* PREFIX_VEX_0F3A41 */
5412 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
5415 /* PREFIX_VEX_0F3A42 */
5419 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
5422 /* PREFIX_VEX_0F3A44 */
5426 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
5429 /* PREFIX_VEX_0F3A46 */
5433 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
5436 /* PREFIX_VEX_0F3A48 */
5440 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
5443 /* PREFIX_VEX_0F3A49 */
5447 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
5450 /* PREFIX_VEX_0F3A4A */
5454 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
5457 /* PREFIX_VEX_0F3A4B */
5461 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
5464 /* PREFIX_VEX_0F3A4C */
5468 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
5471 /* PREFIX_VEX_0F3A5C */
5475 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5478 /* PREFIX_VEX_0F3A5D */
5482 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5485 /* PREFIX_VEX_0F3A5E */
5489 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5492 /* PREFIX_VEX_0F3A5F */
5496 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5499 /* PREFIX_VEX_0F3A60 */
5503 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
5507 /* PREFIX_VEX_0F3A61 */
5511 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
5514 /* PREFIX_VEX_0F3A62 */
5518 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
5521 /* PREFIX_VEX_0F3A63 */
5525 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
5528 /* PREFIX_VEX_0F3A68 */
5532 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5535 /* PREFIX_VEX_0F3A69 */
5539 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5542 /* PREFIX_VEX_0F3A6A */
5546 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
5549 /* PREFIX_VEX_0F3A6B */
5553 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
5556 /* PREFIX_VEX_0F3A6C */
5560 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5563 /* PREFIX_VEX_0F3A6D */
5567 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5570 /* PREFIX_VEX_0F3A6E */
5574 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
5577 /* PREFIX_VEX_0F3A6F */
5581 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
5584 /* PREFIX_VEX_0F3A78 */
5588 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5591 /* PREFIX_VEX_0F3A79 */
5595 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5598 /* PREFIX_VEX_0F3A7A */
5602 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
5605 /* PREFIX_VEX_0F3A7B */
5609 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
5612 /* PREFIX_VEX_0F3A7C */
5616 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5620 /* PREFIX_VEX_0F3A7D */
5624 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5627 /* PREFIX_VEX_0F3A7E */
5631 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
5634 /* PREFIX_VEX_0F3A7F */
5638 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
5641 /* PREFIX_VEX_0F3ADF */
5645 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
5648 /* PREFIX_VEX_0F3AF0 */
5653 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
5657 static const struct dis386 x86_64_table
[][2] = {
5660 { "pushP", { es
} },
5670 { "pushP", { cs
} },
5675 { "pushP", { ss
} },
5685 { "pushP", { ds
} },
5715 { "pushaP", { XX
} },
5720 { "popaP", { XX
} },
5725 { MOD_TABLE (MOD_62_32BIT
) },
5730 { "arpl", { Ew
, Gw
} },
5731 { "movs{lq|xd}", { Gv
, Ed
} },
5736 { "ins{R|}", { Yzr
, indirDX
} },
5737 { "ins{G|}", { Yzr
, indirDX
} },
5742 { "outs{R|}", { indirDXr
, Xz
} },
5743 { "outs{G|}", { indirDXr
, Xz
} },
5748 { "Jcall{T|}", { Ap
} },
5753 { MOD_TABLE (MOD_C4_32BIT
) },
5754 { VEX_C4_TABLE (VEX_0F
) },
5759 { MOD_TABLE (MOD_C5_32BIT
) },
5760 { VEX_C5_TABLE (VEX_0F
) },
5780 { "Jjmp{T|}", { Ap
} },
5783 /* X86_64_0F01_REG_0 */
5785 { "sgdt{Q|IQ}", { M
} },
5789 /* X86_64_0F01_REG_1 */
5791 { "sidt{Q|IQ}", { M
} },
5795 /* X86_64_0F01_REG_2 */
5797 { "lgdt{Q|Q}", { M
} },
5801 /* X86_64_0F01_REG_3 */
5803 { "lidt{Q|Q}", { M
} },
5808 static const struct dis386 three_byte_table
[][256] = {
5810 /* THREE_BYTE_0F38 */
5813 { "pshufb", { MX
, EM
} },
5814 { "phaddw", { MX
, EM
} },
5815 { "phaddd", { MX
, EM
} },
5816 { "phaddsw", { MX
, EM
} },
5817 { "pmaddubsw", { MX
, EM
} },
5818 { "phsubw", { MX
, EM
} },
5819 { "phsubd", { MX
, EM
} },
5820 { "phsubsw", { MX
, EM
} },
5822 { "psignb", { MX
, EM
} },
5823 { "psignw", { MX
, EM
} },
5824 { "psignd", { MX
, EM
} },
5825 { "pmulhrsw", { MX
, EM
} },
5831 { PREFIX_TABLE (PREFIX_0F3810
) },
5835 { PREFIX_TABLE (PREFIX_0F3814
) },
5836 { PREFIX_TABLE (PREFIX_0F3815
) },
5838 { PREFIX_TABLE (PREFIX_0F3817
) },
5844 { "pabsb", { MX
, EM
} },
5845 { "pabsw", { MX
, EM
} },
5846 { "pabsd", { MX
, EM
} },
5849 { PREFIX_TABLE (PREFIX_0F3820
) },
5850 { PREFIX_TABLE (PREFIX_0F3821
) },
5851 { PREFIX_TABLE (PREFIX_0F3822
) },
5852 { PREFIX_TABLE (PREFIX_0F3823
) },
5853 { PREFIX_TABLE (PREFIX_0F3824
) },
5854 { PREFIX_TABLE (PREFIX_0F3825
) },
5858 { PREFIX_TABLE (PREFIX_0F3828
) },
5859 { PREFIX_TABLE (PREFIX_0F3829
) },
5860 { PREFIX_TABLE (PREFIX_0F382A
) },
5861 { PREFIX_TABLE (PREFIX_0F382B
) },
5867 { PREFIX_TABLE (PREFIX_0F3830
) },
5868 { PREFIX_TABLE (PREFIX_0F3831
) },
5869 { PREFIX_TABLE (PREFIX_0F3832
) },
5870 { PREFIX_TABLE (PREFIX_0F3833
) },
5871 { PREFIX_TABLE (PREFIX_0F3834
) },
5872 { PREFIX_TABLE (PREFIX_0F3835
) },
5874 { PREFIX_TABLE (PREFIX_0F3837
) },
5876 { PREFIX_TABLE (PREFIX_0F3838
) },
5877 { PREFIX_TABLE (PREFIX_0F3839
) },
5878 { PREFIX_TABLE (PREFIX_0F383A
) },
5879 { PREFIX_TABLE (PREFIX_0F383B
) },
5880 { PREFIX_TABLE (PREFIX_0F383C
) },
5881 { PREFIX_TABLE (PREFIX_0F383D
) },
5882 { PREFIX_TABLE (PREFIX_0F383E
) },
5883 { PREFIX_TABLE (PREFIX_0F383F
) },
5885 { PREFIX_TABLE (PREFIX_0F3840
) },
5886 { PREFIX_TABLE (PREFIX_0F3841
) },
5957 { PREFIX_TABLE (PREFIX_0F3880
) },
5958 { PREFIX_TABLE (PREFIX_0F3881
) },
5959 { PREFIX_TABLE (PREFIX_0F3882
) },
6059 { PREFIX_TABLE (PREFIX_0F38DB
) },
6060 { PREFIX_TABLE (PREFIX_0F38DC
) },
6061 { PREFIX_TABLE (PREFIX_0F38DD
) },
6062 { PREFIX_TABLE (PREFIX_0F38DE
) },
6063 { PREFIX_TABLE (PREFIX_0F38DF
) },
6083 { PREFIX_TABLE (PREFIX_0F38F0
) },
6084 { PREFIX_TABLE (PREFIX_0F38F1
) },
6089 { PREFIX_TABLE (PREFIX_0F38F6
) },
6101 /* THREE_BYTE_0F3A */
6113 { PREFIX_TABLE (PREFIX_0F3A08
) },
6114 { PREFIX_TABLE (PREFIX_0F3A09
) },
6115 { PREFIX_TABLE (PREFIX_0F3A0A
) },
6116 { PREFIX_TABLE (PREFIX_0F3A0B
) },
6117 { PREFIX_TABLE (PREFIX_0F3A0C
) },
6118 { PREFIX_TABLE (PREFIX_0F3A0D
) },
6119 { PREFIX_TABLE (PREFIX_0F3A0E
) },
6120 { "palignr", { MX
, EM
, Ib
} },
6126 { PREFIX_TABLE (PREFIX_0F3A14
) },
6127 { PREFIX_TABLE (PREFIX_0F3A15
) },
6128 { PREFIX_TABLE (PREFIX_0F3A16
) },
6129 { PREFIX_TABLE (PREFIX_0F3A17
) },
6140 { PREFIX_TABLE (PREFIX_0F3A20
) },
6141 { PREFIX_TABLE (PREFIX_0F3A21
) },
6142 { PREFIX_TABLE (PREFIX_0F3A22
) },
6176 { PREFIX_TABLE (PREFIX_0F3A40
) },
6177 { PREFIX_TABLE (PREFIX_0F3A41
) },
6178 { PREFIX_TABLE (PREFIX_0F3A42
) },
6180 { PREFIX_TABLE (PREFIX_0F3A44
) },
6212 { PREFIX_TABLE (PREFIX_0F3A60
) },
6213 { PREFIX_TABLE (PREFIX_0F3A61
) },
6214 { PREFIX_TABLE (PREFIX_0F3A62
) },
6215 { PREFIX_TABLE (PREFIX_0F3A63
) },
6354 { PREFIX_TABLE (PREFIX_0F3ADF
) },
6393 /* THREE_BYTE_0F7A */
6432 { "ptest", { XX
} },
6469 { "phaddbw", { XM
, EXq
} },
6470 { "phaddbd", { XM
, EXq
} },
6471 { "phaddbq", { XM
, EXq
} },
6474 { "phaddwd", { XM
, EXq
} },
6475 { "phaddwq", { XM
, EXq
} },
6480 { "phadddq", { XM
, EXq
} },
6487 { "phaddubw", { XM
, EXq
} },
6488 { "phaddubd", { XM
, EXq
} },
6489 { "phaddubq", { XM
, EXq
} },
6492 { "phadduwd", { XM
, EXq
} },
6493 { "phadduwq", { XM
, EXq
} },
6498 { "phaddudq", { XM
, EXq
} },
6505 { "phsubbw", { XM
, EXq
} },
6506 { "phsubbd", { XM
, EXq
} },
6507 { "phsubbq", { XM
, EXq
} },
6686 static const struct dis386 xop_table
[][256] = {
6839 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6840 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6841 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6849 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6850 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6857 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6858 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6859 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6867 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6868 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6872 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6873 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6876 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6894 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6906 { "vprotb", { XM
, Vex_2src_1
, Ib
} },
6907 { "vprotw", { XM
, Vex_2src_1
, Ib
} },
6908 { "vprotd", { XM
, Vex_2src_1
, Ib
} },
6909 { "vprotq", { XM
, Vex_2src_1
, Ib
} },
6919 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
6920 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
6921 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
6922 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
6955 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
6956 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
6957 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
6958 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
6982 { REG_TABLE (REG_XOP_TBM_01
) },
6983 { REG_TABLE (REG_XOP_TBM_02
) },
7001 { REG_TABLE (REG_XOP_LWPCB
) },
7125 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7126 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7127 { "vfrczss", { XM
, EXd
} },
7128 { "vfrczsd", { XM
, EXq
} },
7143 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
} },
7144 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
} },
7145 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
} },
7146 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
} },
7147 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
} },
7148 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
} },
7149 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
} },
7150 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
} },
7152 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
} },
7153 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
} },
7154 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
} },
7155 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
} },
7198 { "vphaddbw", { XM
, EXxmm
} },
7199 { "vphaddbd", { XM
, EXxmm
} },
7200 { "vphaddbq", { XM
, EXxmm
} },
7203 { "vphaddwd", { XM
, EXxmm
} },
7204 { "vphaddwq", { XM
, EXxmm
} },
7209 { "vphadddq", { XM
, EXxmm
} },
7216 { "vphaddubw", { XM
, EXxmm
} },
7217 { "vphaddubd", { XM
, EXxmm
} },
7218 { "vphaddubq", { XM
, EXxmm
} },
7221 { "vphadduwd", { XM
, EXxmm
} },
7222 { "vphadduwq", { XM
, EXxmm
} },
7227 { "vphaddudq", { XM
, EXxmm
} },
7234 { "vphsubbw", { XM
, EXxmm
} },
7235 { "vphsubwd", { XM
, EXxmm
} },
7236 { "vphsubdq", { XM
, EXxmm
} },
7290 { "bextr", { Gv
, Ev
, Iq
} },
7292 { REG_TABLE (REG_XOP_LWP
) },
7562 static const struct dis386 vex_table
[][256] = {
7584 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
7585 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
7586 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
7587 { MOD_TABLE (MOD_VEX_0F13
) },
7588 { VEX_W_TABLE (VEX_W_0F14
) },
7589 { VEX_W_TABLE (VEX_W_0F15
) },
7590 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
7591 { MOD_TABLE (MOD_VEX_0F17
) },
7611 { VEX_W_TABLE (VEX_W_0F28
) },
7612 { VEX_W_TABLE (VEX_W_0F29
) },
7613 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
7614 { MOD_TABLE (MOD_VEX_0F2B
) },
7615 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
7616 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
7617 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
7618 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
7656 { MOD_TABLE (MOD_VEX_0F50
) },
7657 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
7658 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
7659 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
7660 { "vandpX", { XM
, Vex
, EXx
} },
7661 { "vandnpX", { XM
, Vex
, EXx
} },
7662 { "vorpX", { XM
, Vex
, EXx
} },
7663 { "vxorpX", { XM
, Vex
, EXx
} },
7665 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
7666 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
7667 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
7668 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
7669 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
7670 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
7671 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
7672 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
7674 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
7675 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
7676 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
7677 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
7678 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
7679 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
7680 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
7681 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
7683 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
7684 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
7685 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
7686 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
7687 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
7688 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
7689 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
7690 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
7692 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
7693 { REG_TABLE (REG_VEX_0F71
) },
7694 { REG_TABLE (REG_VEX_0F72
) },
7695 { REG_TABLE (REG_VEX_0F73
) },
7696 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
7697 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
7698 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
7699 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
7705 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
7706 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
7707 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
7708 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
7761 { REG_TABLE (REG_VEX_0FAE
) },
7784 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
7786 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
7787 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
7788 { "vshufpX", { XM
, Vex
, EXx
, Ib
} },
7800 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
7801 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
7802 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
7803 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
7804 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
7805 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
7806 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
7807 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
7809 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
7810 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
7811 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
7812 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
7813 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
7814 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
7815 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
7816 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
7818 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
7819 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
7820 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
7821 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
7822 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
7823 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
7824 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
7825 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
7827 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
7828 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
7829 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
7830 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
7831 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
7832 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
7833 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
7834 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
7836 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
7837 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
7838 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
7839 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
7840 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
7841 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
7842 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
7843 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
7845 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
7846 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
7847 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
7848 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
7849 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
7850 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
7851 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
7857 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
7858 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
7859 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
7860 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
7861 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
7862 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
7863 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
7864 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
7866 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
7867 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
7868 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
7869 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
7870 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
7871 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
7872 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
7873 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
7878 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
7881 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
7882 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
7884 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
7885 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
7886 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
7888 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
7889 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
7890 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
7893 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
7894 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
7895 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
7896 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
7897 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
7898 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
7902 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
7903 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
7904 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
7905 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
7906 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
7907 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
7908 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
7909 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
7911 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
7912 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
7913 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
7914 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
7915 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
7916 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
7917 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
7918 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
7920 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
7921 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
7922 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
7923 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
7924 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
7925 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
7926 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
7927 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
7929 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
7930 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
7934 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
7935 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
7936 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
7956 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
7957 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
7958 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
7992 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
7993 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8014 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8016 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8019 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8020 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8021 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8022 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8025 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8026 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8028 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8029 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8030 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8031 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8032 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8033 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8034 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8035 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8043 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8044 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8046 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8047 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8048 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8049 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8050 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8051 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8052 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8053 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8061 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8062 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8064 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8065 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8066 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8067 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8068 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8069 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8070 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8071 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8103 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8104 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8105 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8106 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8107 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8129 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8130 { REG_TABLE (REG_VEX_0F38F3
) },
8132 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8133 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8134 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8148 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8149 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8150 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
8152 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
8153 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
8154 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
8157 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
8158 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
8159 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
8160 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
8161 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
8162 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
8163 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
8164 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
8170 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
8171 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
8172 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
8173 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
8175 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
8176 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
8180 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
8184 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
8185 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
8186 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
8211 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
8212 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
8220 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
8221 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
8222 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
8224 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
8226 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
8229 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
8230 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
8231 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
8232 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
8233 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
8251 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
8252 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
8253 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
8254 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
8256 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
8257 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
8258 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
8259 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
8265 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
8266 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
8267 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
8268 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
8269 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
8270 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
8271 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
8272 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
8283 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
8284 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
8285 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
8286 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
8287 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
8288 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
8289 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
8290 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
8398 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
8418 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
8438 static const struct dis386 vex_len_table
[][2] = {
8439 /* VEX_LEN_0F10_P_1 */
8441 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
8442 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
8445 /* VEX_LEN_0F10_P_3 */
8447 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
8448 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
8451 /* VEX_LEN_0F11_P_1 */
8453 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
8454 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
8457 /* VEX_LEN_0F11_P_3 */
8459 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
8460 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
8463 /* VEX_LEN_0F12_P_0_M_0 */
8465 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
8468 /* VEX_LEN_0F12_P_0_M_1 */
8470 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
8473 /* VEX_LEN_0F12_P_2 */
8475 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
8478 /* VEX_LEN_0F13_M_0 */
8480 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
8483 /* VEX_LEN_0F16_P_0_M_0 */
8485 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
8488 /* VEX_LEN_0F16_P_0_M_1 */
8490 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
8493 /* VEX_LEN_0F16_P_2 */
8495 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
8498 /* VEX_LEN_0F17_M_0 */
8500 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
8503 /* VEX_LEN_0F2A_P_1 */
8505 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
8506 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
8509 /* VEX_LEN_0F2A_P_3 */
8511 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
8512 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
8515 /* VEX_LEN_0F2C_P_1 */
8517 { "vcvttss2siY", { Gv
, EXdScalar
} },
8518 { "vcvttss2siY", { Gv
, EXdScalar
} },
8521 /* VEX_LEN_0F2C_P_3 */
8523 { "vcvttsd2siY", { Gv
, EXqScalar
} },
8524 { "vcvttsd2siY", { Gv
, EXqScalar
} },
8527 /* VEX_LEN_0F2D_P_1 */
8529 { "vcvtss2siY", { Gv
, EXdScalar
} },
8530 { "vcvtss2siY", { Gv
, EXdScalar
} },
8533 /* VEX_LEN_0F2D_P_3 */
8535 { "vcvtsd2siY", { Gv
, EXqScalar
} },
8536 { "vcvtsd2siY", { Gv
, EXqScalar
} },
8539 /* VEX_LEN_0F2E_P_0 */
8541 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
8542 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
8545 /* VEX_LEN_0F2E_P_2 */
8547 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
8548 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
8551 /* VEX_LEN_0F2F_P_0 */
8553 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
8554 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
8557 /* VEX_LEN_0F2F_P_2 */
8559 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
8560 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
8563 /* VEX_LEN_0F51_P_1 */
8565 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
8566 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
8569 /* VEX_LEN_0F51_P_3 */
8571 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
8572 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
8575 /* VEX_LEN_0F52_P_1 */
8577 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
8578 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
8581 /* VEX_LEN_0F53_P_1 */
8583 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
8584 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
8587 /* VEX_LEN_0F58_P_1 */
8589 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
8590 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
8593 /* VEX_LEN_0F58_P_3 */
8595 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
8596 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
8599 /* VEX_LEN_0F59_P_1 */
8601 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
8602 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
8605 /* VEX_LEN_0F59_P_3 */
8607 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
8608 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
8611 /* VEX_LEN_0F5A_P_1 */
8613 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
8614 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
8617 /* VEX_LEN_0F5A_P_3 */
8619 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
8620 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
8623 /* VEX_LEN_0F5C_P_1 */
8625 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
8626 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
8629 /* VEX_LEN_0F5C_P_3 */
8631 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
8632 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
8635 /* VEX_LEN_0F5D_P_1 */
8637 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
8638 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
8641 /* VEX_LEN_0F5D_P_3 */
8643 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
8644 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
8647 /* VEX_LEN_0F5E_P_1 */
8649 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
8650 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
8653 /* VEX_LEN_0F5E_P_3 */
8655 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
8656 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
8659 /* VEX_LEN_0F5F_P_1 */
8661 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
8662 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
8665 /* VEX_LEN_0F5F_P_3 */
8667 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
8668 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
8671 /* VEX_LEN_0F6E_P_2 */
8673 { "vmovK", { XMScalar
, Edq
} },
8674 { "vmovK", { XMScalar
, Edq
} },
8677 /* VEX_LEN_0F7E_P_1 */
8679 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
8680 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
8683 /* VEX_LEN_0F7E_P_2 */
8685 { "vmovK", { Edq
, XMScalar
} },
8686 { "vmovK", { Edq
, XMScalar
} },
8689 /* VEX_LEN_0FAE_R_2_M_0 */
8691 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
8694 /* VEX_LEN_0FAE_R_3_M_0 */
8696 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
8699 /* VEX_LEN_0FC2_P_1 */
8701 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
8702 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
8705 /* VEX_LEN_0FC2_P_3 */
8707 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
8708 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
8711 /* VEX_LEN_0FC4_P_2 */
8713 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
8716 /* VEX_LEN_0FC5_P_2 */
8718 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
8721 /* VEX_LEN_0FD6_P_2 */
8723 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
8724 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
8727 /* VEX_LEN_0FF7_P_2 */
8729 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
8732 /* VEX_LEN_0F3816_P_2 */
8735 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
8738 /* VEX_LEN_0F3819_P_2 */
8741 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
8744 /* VEX_LEN_0F381A_P_2_M_0 */
8747 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
8750 /* VEX_LEN_0F3836_P_2 */
8753 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
8756 /* VEX_LEN_0F3841_P_2 */
8758 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
8761 /* VEX_LEN_0F385A_P_2_M_0 */
8764 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
8767 /* VEX_LEN_0F38DB_P_2 */
8769 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
8772 /* VEX_LEN_0F38DC_P_2 */
8774 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
8777 /* VEX_LEN_0F38DD_P_2 */
8779 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
8782 /* VEX_LEN_0F38DE_P_2 */
8784 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
8787 /* VEX_LEN_0F38DF_P_2 */
8789 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
8792 /* VEX_LEN_0F38F2_P_0 */
8794 { "andnS", { Gdq
, VexGdq
, Edq
} },
8797 /* VEX_LEN_0F38F3_R_1_P_0 */
8799 { "blsrS", { VexGdq
, Edq
} },
8802 /* VEX_LEN_0F38F3_R_2_P_0 */
8804 { "blsmskS", { VexGdq
, Edq
} },
8807 /* VEX_LEN_0F38F3_R_3_P_0 */
8809 { "blsiS", { VexGdq
, Edq
} },
8812 /* VEX_LEN_0F38F5_P_0 */
8814 { "bzhiS", { Gdq
, Edq
, VexGdq
} },
8817 /* VEX_LEN_0F38F5_P_1 */
8819 { "pextS", { Gdq
, VexGdq
, Edq
} },
8822 /* VEX_LEN_0F38F5_P_3 */
8824 { "pdepS", { Gdq
, VexGdq
, Edq
} },
8827 /* VEX_LEN_0F38F6_P_3 */
8829 { "mulxS", { Gdq
, VexGdq
, Edq
} },
8832 /* VEX_LEN_0F38F7_P_0 */
8834 { "bextrS", { Gdq
, Edq
, VexGdq
} },
8837 /* VEX_LEN_0F38F7_P_1 */
8839 { "sarxS", { Gdq
, Edq
, VexGdq
} },
8842 /* VEX_LEN_0F38F7_P_2 */
8844 { "shlxS", { Gdq
, Edq
, VexGdq
} },
8847 /* VEX_LEN_0F38F7_P_3 */
8849 { "shrxS", { Gdq
, Edq
, VexGdq
} },
8852 /* VEX_LEN_0F3A00_P_2 */
8855 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
8858 /* VEX_LEN_0F3A01_P_2 */
8861 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
8864 /* VEX_LEN_0F3A06_P_2 */
8867 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
8870 /* VEX_LEN_0F3A0A_P_2 */
8872 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
8873 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
8876 /* VEX_LEN_0F3A0B_P_2 */
8878 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
8879 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
8882 /* VEX_LEN_0F3A14_P_2 */
8884 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
8887 /* VEX_LEN_0F3A15_P_2 */
8889 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
8892 /* VEX_LEN_0F3A16_P_2 */
8894 { "vpextrK", { Edq
, XM
, Ib
} },
8897 /* VEX_LEN_0F3A17_P_2 */
8899 { "vextractps", { Edqd
, XM
, Ib
} },
8902 /* VEX_LEN_0F3A18_P_2 */
8905 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
8908 /* VEX_LEN_0F3A19_P_2 */
8911 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
8914 /* VEX_LEN_0F3A20_P_2 */
8916 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
8919 /* VEX_LEN_0F3A21_P_2 */
8921 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
8924 /* VEX_LEN_0F3A22_P_2 */
8926 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
} },
8929 /* VEX_LEN_0F3A38_P_2 */
8932 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
8935 /* VEX_LEN_0F3A39_P_2 */
8938 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
8941 /* VEX_LEN_0F3A41_P_2 */
8943 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
8946 /* VEX_LEN_0F3A44_P_2 */
8948 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
8951 /* VEX_LEN_0F3A46_P_2 */
8954 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
8957 /* VEX_LEN_0F3A60_P_2 */
8959 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
8962 /* VEX_LEN_0F3A61_P_2 */
8964 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
8967 /* VEX_LEN_0F3A62_P_2 */
8969 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
8972 /* VEX_LEN_0F3A63_P_2 */
8974 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
8977 /* VEX_LEN_0F3A6A_P_2 */
8979 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
8982 /* VEX_LEN_0F3A6B_P_2 */
8984 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
8987 /* VEX_LEN_0F3A6E_P_2 */
8989 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
8992 /* VEX_LEN_0F3A6F_P_2 */
8994 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
8997 /* VEX_LEN_0F3A7A_P_2 */
8999 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9002 /* VEX_LEN_0F3A7B_P_2 */
9004 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9007 /* VEX_LEN_0F3A7E_P_2 */
9009 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9012 /* VEX_LEN_0F3A7F_P_2 */
9014 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9017 /* VEX_LEN_0F3ADF_P_2 */
9019 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
9022 /* VEX_LEN_0F3AF0_P_3 */
9024 { "rorxS", { Gdq
, Edq
, Ib
} },
9027 /* VEX_LEN_0FXOP_08_CC */
9029 { "vpcomb", { XM
, Vex128
, EXx
, Ib
} },
9032 /* VEX_LEN_0FXOP_08_CD */
9034 { "vpcomw", { XM
, Vex128
, EXx
, Ib
} },
9037 /* VEX_LEN_0FXOP_08_CE */
9039 { "vpcomd", { XM
, Vex128
, EXx
, Ib
} },
9042 /* VEX_LEN_0FXOP_08_CF */
9044 { "vpcomq", { XM
, Vex128
, EXx
, Ib
} },
9047 /* VEX_LEN_0FXOP_08_EC */
9049 { "vpcomub", { XM
, Vex128
, EXx
, Ib
} },
9052 /* VEX_LEN_0FXOP_08_ED */
9054 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
} },
9057 /* VEX_LEN_0FXOP_08_EE */
9059 { "vpcomud", { XM
, Vex128
, EXx
, Ib
} },
9062 /* VEX_LEN_0FXOP_08_EF */
9064 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
} },
9067 /* VEX_LEN_0FXOP_09_80 */
9069 { "vfrczps", { XM
, EXxmm
} },
9070 { "vfrczps", { XM
, EXymmq
} },
9073 /* VEX_LEN_0FXOP_09_81 */
9075 { "vfrczpd", { XM
, EXxmm
} },
9076 { "vfrczpd", { XM
, EXymmq
} },
9080 static const struct dis386 vex_w_table
[][2] = {
9082 /* VEX_W_0F10_P_0 */
9083 { "vmovups", { XM
, EXx
} },
9086 /* VEX_W_0F10_P_1 */
9087 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
} },
9090 /* VEX_W_0F10_P_2 */
9091 { "vmovupd", { XM
, EXx
} },
9094 /* VEX_W_0F10_P_3 */
9095 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
} },
9098 /* VEX_W_0F11_P_0 */
9099 { "vmovups", { EXxS
, XM
} },
9102 /* VEX_W_0F11_P_1 */
9103 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
} },
9106 /* VEX_W_0F11_P_2 */
9107 { "vmovupd", { EXxS
, XM
} },
9110 /* VEX_W_0F11_P_3 */
9111 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
} },
9114 /* VEX_W_0F12_P_0_M_0 */
9115 { "vmovlps", { XM
, Vex128
, EXq
} },
9118 /* VEX_W_0F12_P_0_M_1 */
9119 { "vmovhlps", { XM
, Vex128
, EXq
} },
9122 /* VEX_W_0F12_P_1 */
9123 { "vmovsldup", { XM
, EXx
} },
9126 /* VEX_W_0F12_P_2 */
9127 { "vmovlpd", { XM
, Vex128
, EXq
} },
9130 /* VEX_W_0F12_P_3 */
9131 { "vmovddup", { XM
, EXymmq
} },
9134 /* VEX_W_0F13_M_0 */
9135 { "vmovlpX", { EXq
, XM
} },
9139 { "vunpcklpX", { XM
, Vex
, EXx
} },
9143 { "vunpckhpX", { XM
, Vex
, EXx
} },
9146 /* VEX_W_0F16_P_0_M_0 */
9147 { "vmovhps", { XM
, Vex128
, EXq
} },
9150 /* VEX_W_0F16_P_0_M_1 */
9151 { "vmovlhps", { XM
, Vex128
, EXq
} },
9154 /* VEX_W_0F16_P_1 */
9155 { "vmovshdup", { XM
, EXx
} },
9158 /* VEX_W_0F16_P_2 */
9159 { "vmovhpd", { XM
, Vex128
, EXq
} },
9162 /* VEX_W_0F17_M_0 */
9163 { "vmovhpX", { EXq
, XM
} },
9167 { "vmovapX", { XM
, EXx
} },
9171 { "vmovapX", { EXxS
, XM
} },
9174 /* VEX_W_0F2B_M_0 */
9175 { "vmovntpX", { Mx
, XM
} },
9178 /* VEX_W_0F2E_P_0 */
9179 { "vucomiss", { XMScalar
, EXdScalar
} },
9182 /* VEX_W_0F2E_P_2 */
9183 { "vucomisd", { XMScalar
, EXqScalar
} },
9186 /* VEX_W_0F2F_P_0 */
9187 { "vcomiss", { XMScalar
, EXdScalar
} },
9190 /* VEX_W_0F2F_P_2 */
9191 { "vcomisd", { XMScalar
, EXqScalar
} },
9194 /* VEX_W_0F50_M_0 */
9195 { "vmovmskpX", { Gdq
, XS
} },
9198 /* VEX_W_0F51_P_0 */
9199 { "vsqrtps", { XM
, EXx
} },
9202 /* VEX_W_0F51_P_1 */
9203 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
9206 /* VEX_W_0F51_P_2 */
9207 { "vsqrtpd", { XM
, EXx
} },
9210 /* VEX_W_0F51_P_3 */
9211 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
} },
9214 /* VEX_W_0F52_P_0 */
9215 { "vrsqrtps", { XM
, EXx
} },
9218 /* VEX_W_0F52_P_1 */
9219 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
9222 /* VEX_W_0F53_P_0 */
9223 { "vrcpps", { XM
, EXx
} },
9226 /* VEX_W_0F53_P_1 */
9227 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
} },
9230 /* VEX_W_0F58_P_0 */
9231 { "vaddps", { XM
, Vex
, EXx
} },
9234 /* VEX_W_0F58_P_1 */
9235 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
} },
9238 /* VEX_W_0F58_P_2 */
9239 { "vaddpd", { XM
, Vex
, EXx
} },
9242 /* VEX_W_0F58_P_3 */
9243 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
} },
9246 /* VEX_W_0F59_P_0 */
9247 { "vmulps", { XM
, Vex
, EXx
} },
9250 /* VEX_W_0F59_P_1 */
9251 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
} },
9254 /* VEX_W_0F59_P_2 */
9255 { "vmulpd", { XM
, Vex
, EXx
} },
9258 /* VEX_W_0F59_P_3 */
9259 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
} },
9262 /* VEX_W_0F5A_P_0 */
9263 { "vcvtps2pd", { XM
, EXxmmq
} },
9266 /* VEX_W_0F5A_P_1 */
9267 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
} },
9270 /* VEX_W_0F5A_P_3 */
9271 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
} },
9274 /* VEX_W_0F5B_P_0 */
9275 { "vcvtdq2ps", { XM
, EXx
} },
9278 /* VEX_W_0F5B_P_1 */
9279 { "vcvttps2dq", { XM
, EXx
} },
9282 /* VEX_W_0F5B_P_2 */
9283 { "vcvtps2dq", { XM
, EXx
} },
9286 /* VEX_W_0F5C_P_0 */
9287 { "vsubps", { XM
, Vex
, EXx
} },
9290 /* VEX_W_0F5C_P_1 */
9291 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
} },
9294 /* VEX_W_0F5C_P_2 */
9295 { "vsubpd", { XM
, Vex
, EXx
} },
9298 /* VEX_W_0F5C_P_3 */
9299 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
} },
9302 /* VEX_W_0F5D_P_0 */
9303 { "vminps", { XM
, Vex
, EXx
} },
9306 /* VEX_W_0F5D_P_1 */
9307 { "vminss", { XMScalar
, VexScalar
, EXdScalar
} },
9310 /* VEX_W_0F5D_P_2 */
9311 { "vminpd", { XM
, Vex
, EXx
} },
9314 /* VEX_W_0F5D_P_3 */
9315 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
} },
9318 /* VEX_W_0F5E_P_0 */
9319 { "vdivps", { XM
, Vex
, EXx
} },
9322 /* VEX_W_0F5E_P_1 */
9323 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
} },
9326 /* VEX_W_0F5E_P_2 */
9327 { "vdivpd", { XM
, Vex
, EXx
} },
9330 /* VEX_W_0F5E_P_3 */
9331 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
} },
9334 /* VEX_W_0F5F_P_0 */
9335 { "vmaxps", { XM
, Vex
, EXx
} },
9338 /* VEX_W_0F5F_P_1 */
9339 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
} },
9342 /* VEX_W_0F5F_P_2 */
9343 { "vmaxpd", { XM
, Vex
, EXx
} },
9346 /* VEX_W_0F5F_P_3 */
9347 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
} },
9350 /* VEX_W_0F60_P_2 */
9351 { "vpunpcklbw", { XM
, Vex
, EXx
} },
9354 /* VEX_W_0F61_P_2 */
9355 { "vpunpcklwd", { XM
, Vex
, EXx
} },
9358 /* VEX_W_0F62_P_2 */
9359 { "vpunpckldq", { XM
, Vex
, EXx
} },
9362 /* VEX_W_0F63_P_2 */
9363 { "vpacksswb", { XM
, Vex
, EXx
} },
9366 /* VEX_W_0F64_P_2 */
9367 { "vpcmpgtb", { XM
, Vex
, EXx
} },
9370 /* VEX_W_0F65_P_2 */
9371 { "vpcmpgtw", { XM
, Vex
, EXx
} },
9374 /* VEX_W_0F66_P_2 */
9375 { "vpcmpgtd", { XM
, Vex
, EXx
} },
9378 /* VEX_W_0F67_P_2 */
9379 { "vpackuswb", { XM
, Vex
, EXx
} },
9382 /* VEX_W_0F68_P_2 */
9383 { "vpunpckhbw", { XM
, Vex
, EXx
} },
9386 /* VEX_W_0F69_P_2 */
9387 { "vpunpckhwd", { XM
, Vex
, EXx
} },
9390 /* VEX_W_0F6A_P_2 */
9391 { "vpunpckhdq", { XM
, Vex
, EXx
} },
9394 /* VEX_W_0F6B_P_2 */
9395 { "vpackssdw", { XM
, Vex
, EXx
} },
9398 /* VEX_W_0F6C_P_2 */
9399 { "vpunpcklqdq", { XM
, Vex
, EXx
} },
9402 /* VEX_W_0F6D_P_2 */
9403 { "vpunpckhqdq", { XM
, Vex
, EXx
} },
9406 /* VEX_W_0F6F_P_1 */
9407 { "vmovdqu", { XM
, EXx
} },
9410 /* VEX_W_0F6F_P_2 */
9411 { "vmovdqa", { XM
, EXx
} },
9414 /* VEX_W_0F70_P_1 */
9415 { "vpshufhw", { XM
, EXx
, Ib
} },
9418 /* VEX_W_0F70_P_2 */
9419 { "vpshufd", { XM
, EXx
, Ib
} },
9422 /* VEX_W_0F70_P_3 */
9423 { "vpshuflw", { XM
, EXx
, Ib
} },
9426 /* VEX_W_0F71_R_2_P_2 */
9427 { "vpsrlw", { Vex
, XS
, Ib
} },
9430 /* VEX_W_0F71_R_4_P_2 */
9431 { "vpsraw", { Vex
, XS
, Ib
} },
9434 /* VEX_W_0F71_R_6_P_2 */
9435 { "vpsllw", { Vex
, XS
, Ib
} },
9438 /* VEX_W_0F72_R_2_P_2 */
9439 { "vpsrld", { Vex
, XS
, Ib
} },
9442 /* VEX_W_0F72_R_4_P_2 */
9443 { "vpsrad", { Vex
, XS
, Ib
} },
9446 /* VEX_W_0F72_R_6_P_2 */
9447 { "vpslld", { Vex
, XS
, Ib
} },
9450 /* VEX_W_0F73_R_2_P_2 */
9451 { "vpsrlq", { Vex
, XS
, Ib
} },
9454 /* VEX_W_0F73_R_3_P_2 */
9455 { "vpsrldq", { Vex
, XS
, Ib
} },
9458 /* VEX_W_0F73_R_6_P_2 */
9459 { "vpsllq", { Vex
, XS
, Ib
} },
9462 /* VEX_W_0F73_R_7_P_2 */
9463 { "vpslldq", { Vex
, XS
, Ib
} },
9466 /* VEX_W_0F74_P_2 */
9467 { "vpcmpeqb", { XM
, Vex
, EXx
} },
9470 /* VEX_W_0F75_P_2 */
9471 { "vpcmpeqw", { XM
, Vex
, EXx
} },
9474 /* VEX_W_0F76_P_2 */
9475 { "vpcmpeqd", { XM
, Vex
, EXx
} },
9478 /* VEX_W_0F77_P_0 */
9482 /* VEX_W_0F7C_P_2 */
9483 { "vhaddpd", { XM
, Vex
, EXx
} },
9486 /* VEX_W_0F7C_P_3 */
9487 { "vhaddps", { XM
, Vex
, EXx
} },
9490 /* VEX_W_0F7D_P_2 */
9491 { "vhsubpd", { XM
, Vex
, EXx
} },
9494 /* VEX_W_0F7D_P_3 */
9495 { "vhsubps", { XM
, Vex
, EXx
} },
9498 /* VEX_W_0F7E_P_1 */
9499 { "vmovq", { XMScalar
, EXqScalar
} },
9502 /* VEX_W_0F7F_P_1 */
9503 { "vmovdqu", { EXxS
, XM
} },
9506 /* VEX_W_0F7F_P_2 */
9507 { "vmovdqa", { EXxS
, XM
} },
9510 /* VEX_W_0FAE_R_2_M_0 */
9511 { "vldmxcsr", { Md
} },
9514 /* VEX_W_0FAE_R_3_M_0 */
9515 { "vstmxcsr", { Md
} },
9518 /* VEX_W_0FC2_P_0 */
9519 { "vcmpps", { XM
, Vex
, EXx
, VCMP
} },
9522 /* VEX_W_0FC2_P_1 */
9523 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
} },
9526 /* VEX_W_0FC2_P_2 */
9527 { "vcmppd", { XM
, Vex
, EXx
, VCMP
} },
9530 /* VEX_W_0FC2_P_3 */
9531 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
} },
9534 /* VEX_W_0FC4_P_2 */
9535 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
} },
9538 /* VEX_W_0FC5_P_2 */
9539 { "vpextrw", { Gdq
, XS
, Ib
} },
9542 /* VEX_W_0FD0_P_2 */
9543 { "vaddsubpd", { XM
, Vex
, EXx
} },
9546 /* VEX_W_0FD0_P_3 */
9547 { "vaddsubps", { XM
, Vex
, EXx
} },
9550 /* VEX_W_0FD1_P_2 */
9551 { "vpsrlw", { XM
, Vex
, EXxmm
} },
9554 /* VEX_W_0FD2_P_2 */
9555 { "vpsrld", { XM
, Vex
, EXxmm
} },
9558 /* VEX_W_0FD3_P_2 */
9559 { "vpsrlq", { XM
, Vex
, EXxmm
} },
9562 /* VEX_W_0FD4_P_2 */
9563 { "vpaddq", { XM
, Vex
, EXx
} },
9566 /* VEX_W_0FD5_P_2 */
9567 { "vpmullw", { XM
, Vex
, EXx
} },
9570 /* VEX_W_0FD6_P_2 */
9571 { "vmovq", { EXqScalarS
, XMScalar
} },
9574 /* VEX_W_0FD7_P_2_M_1 */
9575 { "vpmovmskb", { Gdq
, XS
} },
9578 /* VEX_W_0FD8_P_2 */
9579 { "vpsubusb", { XM
, Vex
, EXx
} },
9582 /* VEX_W_0FD9_P_2 */
9583 { "vpsubusw", { XM
, Vex
, EXx
} },
9586 /* VEX_W_0FDA_P_2 */
9587 { "vpminub", { XM
, Vex
, EXx
} },
9590 /* VEX_W_0FDB_P_2 */
9591 { "vpand", { XM
, Vex
, EXx
} },
9594 /* VEX_W_0FDC_P_2 */
9595 { "vpaddusb", { XM
, Vex
, EXx
} },
9598 /* VEX_W_0FDD_P_2 */
9599 { "vpaddusw", { XM
, Vex
, EXx
} },
9602 /* VEX_W_0FDE_P_2 */
9603 { "vpmaxub", { XM
, Vex
, EXx
} },
9606 /* VEX_W_0FDF_P_2 */
9607 { "vpandn", { XM
, Vex
, EXx
} },
9610 /* VEX_W_0FE0_P_2 */
9611 { "vpavgb", { XM
, Vex
, EXx
} },
9614 /* VEX_W_0FE1_P_2 */
9615 { "vpsraw", { XM
, Vex
, EXxmm
} },
9618 /* VEX_W_0FE2_P_2 */
9619 { "vpsrad", { XM
, Vex
, EXxmm
} },
9622 /* VEX_W_0FE3_P_2 */
9623 { "vpavgw", { XM
, Vex
, EXx
} },
9626 /* VEX_W_0FE4_P_2 */
9627 { "vpmulhuw", { XM
, Vex
, EXx
} },
9630 /* VEX_W_0FE5_P_2 */
9631 { "vpmulhw", { XM
, Vex
, EXx
} },
9634 /* VEX_W_0FE6_P_1 */
9635 { "vcvtdq2pd", { XM
, EXxmmq
} },
9638 /* VEX_W_0FE6_P_2 */
9639 { "vcvttpd2dq%XY", { XMM
, EXx
} },
9642 /* VEX_W_0FE6_P_3 */
9643 { "vcvtpd2dq%XY", { XMM
, EXx
} },
9646 /* VEX_W_0FE7_P_2_M_0 */
9647 { "vmovntdq", { Mx
, XM
} },
9650 /* VEX_W_0FE8_P_2 */
9651 { "vpsubsb", { XM
, Vex
, EXx
} },
9654 /* VEX_W_0FE9_P_2 */
9655 { "vpsubsw", { XM
, Vex
, EXx
} },
9658 /* VEX_W_0FEA_P_2 */
9659 { "vpminsw", { XM
, Vex
, EXx
} },
9662 /* VEX_W_0FEB_P_2 */
9663 { "vpor", { XM
, Vex
, EXx
} },
9666 /* VEX_W_0FEC_P_2 */
9667 { "vpaddsb", { XM
, Vex
, EXx
} },
9670 /* VEX_W_0FED_P_2 */
9671 { "vpaddsw", { XM
, Vex
, EXx
} },
9674 /* VEX_W_0FEE_P_2 */
9675 { "vpmaxsw", { XM
, Vex
, EXx
} },
9678 /* VEX_W_0FEF_P_2 */
9679 { "vpxor", { XM
, Vex
, EXx
} },
9682 /* VEX_W_0FF0_P_3_M_0 */
9683 { "vlddqu", { XM
, M
} },
9686 /* VEX_W_0FF1_P_2 */
9687 { "vpsllw", { XM
, Vex
, EXxmm
} },
9690 /* VEX_W_0FF2_P_2 */
9691 { "vpslld", { XM
, Vex
, EXxmm
} },
9694 /* VEX_W_0FF3_P_2 */
9695 { "vpsllq", { XM
, Vex
, EXxmm
} },
9698 /* VEX_W_0FF4_P_2 */
9699 { "vpmuludq", { XM
, Vex
, EXx
} },
9702 /* VEX_W_0FF5_P_2 */
9703 { "vpmaddwd", { XM
, Vex
, EXx
} },
9706 /* VEX_W_0FF6_P_2 */
9707 { "vpsadbw", { XM
, Vex
, EXx
} },
9710 /* VEX_W_0FF7_P_2 */
9711 { "vmaskmovdqu", { XM
, XS
} },
9714 /* VEX_W_0FF8_P_2 */
9715 { "vpsubb", { XM
, Vex
, EXx
} },
9718 /* VEX_W_0FF9_P_2 */
9719 { "vpsubw", { XM
, Vex
, EXx
} },
9722 /* VEX_W_0FFA_P_2 */
9723 { "vpsubd", { XM
, Vex
, EXx
} },
9726 /* VEX_W_0FFB_P_2 */
9727 { "vpsubq", { XM
, Vex
, EXx
} },
9730 /* VEX_W_0FFC_P_2 */
9731 { "vpaddb", { XM
, Vex
, EXx
} },
9734 /* VEX_W_0FFD_P_2 */
9735 { "vpaddw", { XM
, Vex
, EXx
} },
9738 /* VEX_W_0FFE_P_2 */
9739 { "vpaddd", { XM
, Vex
, EXx
} },
9742 /* VEX_W_0F3800_P_2 */
9743 { "vpshufb", { XM
, Vex
, EXx
} },
9746 /* VEX_W_0F3801_P_2 */
9747 { "vphaddw", { XM
, Vex
, EXx
} },
9750 /* VEX_W_0F3802_P_2 */
9751 { "vphaddd", { XM
, Vex
, EXx
} },
9754 /* VEX_W_0F3803_P_2 */
9755 { "vphaddsw", { XM
, Vex
, EXx
} },
9758 /* VEX_W_0F3804_P_2 */
9759 { "vpmaddubsw", { XM
, Vex
, EXx
} },
9762 /* VEX_W_0F3805_P_2 */
9763 { "vphsubw", { XM
, Vex
, EXx
} },
9766 /* VEX_W_0F3806_P_2 */
9767 { "vphsubd", { XM
, Vex
, EXx
} },
9770 /* VEX_W_0F3807_P_2 */
9771 { "vphsubsw", { XM
, Vex
, EXx
} },
9774 /* VEX_W_0F3808_P_2 */
9775 { "vpsignb", { XM
, Vex
, EXx
} },
9778 /* VEX_W_0F3809_P_2 */
9779 { "vpsignw", { XM
, Vex
, EXx
} },
9782 /* VEX_W_0F380A_P_2 */
9783 { "vpsignd", { XM
, Vex
, EXx
} },
9786 /* VEX_W_0F380B_P_2 */
9787 { "vpmulhrsw", { XM
, Vex
, EXx
} },
9790 /* VEX_W_0F380C_P_2 */
9791 { "vpermilps", { XM
, Vex
, EXx
} },
9794 /* VEX_W_0F380D_P_2 */
9795 { "vpermilpd", { XM
, Vex
, EXx
} },
9798 /* VEX_W_0F380E_P_2 */
9799 { "vtestps", { XM
, EXx
} },
9802 /* VEX_W_0F380F_P_2 */
9803 { "vtestpd", { XM
, EXx
} },
9806 /* VEX_W_0F3816_P_2 */
9807 { "vpermps", { XM
, Vex
, EXx
} },
9810 /* VEX_W_0F3817_P_2 */
9811 { "vptest", { XM
, EXx
} },
9814 /* VEX_W_0F3818_P_2 */
9815 { "vbroadcastss", { XM
, EXxmm_md
} },
9818 /* VEX_W_0F3819_P_2 */
9819 { "vbroadcastsd", { XM
, EXxmm_mq
} },
9822 /* VEX_W_0F381A_P_2_M_0 */
9823 { "vbroadcastf128", { XM
, Mxmm
} },
9826 /* VEX_W_0F381C_P_2 */
9827 { "vpabsb", { XM
, EXx
} },
9830 /* VEX_W_0F381D_P_2 */
9831 { "vpabsw", { XM
, EXx
} },
9834 /* VEX_W_0F381E_P_2 */
9835 { "vpabsd", { XM
, EXx
} },
9838 /* VEX_W_0F3820_P_2 */
9839 { "vpmovsxbw", { XM
, EXxmmq
} },
9842 /* VEX_W_0F3821_P_2 */
9843 { "vpmovsxbd", { XM
, EXxmmqd
} },
9846 /* VEX_W_0F3822_P_2 */
9847 { "vpmovsxbq", { XM
, EXxmmdw
} },
9850 /* VEX_W_0F3823_P_2 */
9851 { "vpmovsxwd", { XM
, EXxmmq
} },
9854 /* VEX_W_0F3824_P_2 */
9855 { "vpmovsxwq", { XM
, EXxmmqd
} },
9858 /* VEX_W_0F3825_P_2 */
9859 { "vpmovsxdq", { XM
, EXxmmq
} },
9862 /* VEX_W_0F3828_P_2 */
9863 { "vpmuldq", { XM
, Vex
, EXx
} },
9866 /* VEX_W_0F3829_P_2 */
9867 { "vpcmpeqq", { XM
, Vex
, EXx
} },
9870 /* VEX_W_0F382A_P_2_M_0 */
9871 { "vmovntdqa", { XM
, Mx
} },
9874 /* VEX_W_0F382B_P_2 */
9875 { "vpackusdw", { XM
, Vex
, EXx
} },
9878 /* VEX_W_0F382C_P_2_M_0 */
9879 { "vmaskmovps", { XM
, Vex
, Mx
} },
9882 /* VEX_W_0F382D_P_2_M_0 */
9883 { "vmaskmovpd", { XM
, Vex
, Mx
} },
9886 /* VEX_W_0F382E_P_2_M_0 */
9887 { "vmaskmovps", { Mx
, Vex
, XM
} },
9890 /* VEX_W_0F382F_P_2_M_0 */
9891 { "vmaskmovpd", { Mx
, Vex
, XM
} },
9894 /* VEX_W_0F3830_P_2 */
9895 { "vpmovzxbw", { XM
, EXxmmq
} },
9898 /* VEX_W_0F3831_P_2 */
9899 { "vpmovzxbd", { XM
, EXxmmqd
} },
9902 /* VEX_W_0F3832_P_2 */
9903 { "vpmovzxbq", { XM
, EXxmmdw
} },
9906 /* VEX_W_0F3833_P_2 */
9907 { "vpmovzxwd", { XM
, EXxmmq
} },
9910 /* VEX_W_0F3834_P_2 */
9911 { "vpmovzxwq", { XM
, EXxmmqd
} },
9914 /* VEX_W_0F3835_P_2 */
9915 { "vpmovzxdq", { XM
, EXxmmq
} },
9918 /* VEX_W_0F3836_P_2 */
9919 { "vpermd", { XM
, Vex
, EXx
} },
9922 /* VEX_W_0F3837_P_2 */
9923 { "vpcmpgtq", { XM
, Vex
, EXx
} },
9926 /* VEX_W_0F3838_P_2 */
9927 { "vpminsb", { XM
, Vex
, EXx
} },
9930 /* VEX_W_0F3839_P_2 */
9931 { "vpminsd", { XM
, Vex
, EXx
} },
9934 /* VEX_W_0F383A_P_2 */
9935 { "vpminuw", { XM
, Vex
, EXx
} },
9938 /* VEX_W_0F383B_P_2 */
9939 { "vpminud", { XM
, Vex
, EXx
} },
9942 /* VEX_W_0F383C_P_2 */
9943 { "vpmaxsb", { XM
, Vex
, EXx
} },
9946 /* VEX_W_0F383D_P_2 */
9947 { "vpmaxsd", { XM
, Vex
, EXx
} },
9950 /* VEX_W_0F383E_P_2 */
9951 { "vpmaxuw", { XM
, Vex
, EXx
} },
9954 /* VEX_W_0F383F_P_2 */
9955 { "vpmaxud", { XM
, Vex
, EXx
} },
9958 /* VEX_W_0F3840_P_2 */
9959 { "vpmulld", { XM
, Vex
, EXx
} },
9962 /* VEX_W_0F3841_P_2 */
9963 { "vphminposuw", { XM
, EXx
} },
9966 /* VEX_W_0F3846_P_2 */
9967 { "vpsravd", { XM
, Vex
, EXx
} },
9970 /* VEX_W_0F3858_P_2 */
9971 { "vpbroadcastd", { XM
, EXxmm_md
} },
9974 /* VEX_W_0F3859_P_2 */
9975 { "vpbroadcastq", { XM
, EXxmm_mq
} },
9978 /* VEX_W_0F385A_P_2_M_0 */
9979 { "vbroadcasti128", { XM
, Mxmm
} },
9982 /* VEX_W_0F3878_P_2 */
9983 { "vpbroadcastb", { XM
, EXxmm_mb
} },
9986 /* VEX_W_0F3879_P_2 */
9987 { "vpbroadcastw", { XM
, EXxmm_mw
} },
9990 /* VEX_W_0F38DB_P_2 */
9991 { "vaesimc", { XM
, EXx
} },
9994 /* VEX_W_0F38DC_P_2 */
9995 { "vaesenc", { XM
, Vex128
, EXx
} },
9998 /* VEX_W_0F38DD_P_2 */
9999 { "vaesenclast", { XM
, Vex128
, EXx
} },
10002 /* VEX_W_0F38DE_P_2 */
10003 { "vaesdec", { XM
, Vex128
, EXx
} },
10006 /* VEX_W_0F38DF_P_2 */
10007 { "vaesdeclast", { XM
, Vex128
, EXx
} },
10010 /* VEX_W_0F3A00_P_2 */
10012 { "vpermq", { XM
, EXx
, Ib
} },
10015 /* VEX_W_0F3A01_P_2 */
10017 { "vpermpd", { XM
, EXx
, Ib
} },
10020 /* VEX_W_0F3A02_P_2 */
10021 { "vpblendd", { XM
, Vex
, EXx
, Ib
} },
10024 /* VEX_W_0F3A04_P_2 */
10025 { "vpermilps", { XM
, EXx
, Ib
} },
10028 /* VEX_W_0F3A05_P_2 */
10029 { "vpermilpd", { XM
, EXx
, Ib
} },
10032 /* VEX_W_0F3A06_P_2 */
10033 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
} },
10036 /* VEX_W_0F3A08_P_2 */
10037 { "vroundps", { XM
, EXx
, Ib
} },
10040 /* VEX_W_0F3A09_P_2 */
10041 { "vroundpd", { XM
, EXx
, Ib
} },
10044 /* VEX_W_0F3A0A_P_2 */
10045 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
} },
10048 /* VEX_W_0F3A0B_P_2 */
10049 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
} },
10052 /* VEX_W_0F3A0C_P_2 */
10053 { "vblendps", { XM
, Vex
, EXx
, Ib
} },
10056 /* VEX_W_0F3A0D_P_2 */
10057 { "vblendpd", { XM
, Vex
, EXx
, Ib
} },
10060 /* VEX_W_0F3A0E_P_2 */
10061 { "vpblendw", { XM
, Vex
, EXx
, Ib
} },
10064 /* VEX_W_0F3A0F_P_2 */
10065 { "vpalignr", { XM
, Vex
, EXx
, Ib
} },
10068 /* VEX_W_0F3A14_P_2 */
10069 { "vpextrb", { Edqb
, XM
, Ib
} },
10072 /* VEX_W_0F3A15_P_2 */
10073 { "vpextrw", { Edqw
, XM
, Ib
} },
10076 /* VEX_W_0F3A18_P_2 */
10077 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
} },
10080 /* VEX_W_0F3A19_P_2 */
10081 { "vextractf128", { EXxmm
, XM
, Ib
} },
10084 /* VEX_W_0F3A20_P_2 */
10085 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
} },
10088 /* VEX_W_0F3A21_P_2 */
10089 { "vinsertps", { XM
, Vex128
, EXd
, Ib
} },
10092 /* VEX_W_0F3A38_P_2 */
10093 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
} },
10096 /* VEX_W_0F3A39_P_2 */
10097 { "vextracti128", { EXxmm
, XM
, Ib
} },
10100 /* VEX_W_0F3A40_P_2 */
10101 { "vdpps", { XM
, Vex
, EXx
, Ib
} },
10104 /* VEX_W_0F3A41_P_2 */
10105 { "vdppd", { XM
, Vex128
, EXx
, Ib
} },
10108 /* VEX_W_0F3A42_P_2 */
10109 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
} },
10112 /* VEX_W_0F3A44_P_2 */
10113 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
} },
10116 /* VEX_W_0F3A46_P_2 */
10117 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
} },
10120 /* VEX_W_0F3A48_P_2 */
10121 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10122 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10125 /* VEX_W_0F3A49_P_2 */
10126 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10127 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10130 /* VEX_W_0F3A4A_P_2 */
10131 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
} },
10134 /* VEX_W_0F3A4B_P_2 */
10135 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
} },
10138 /* VEX_W_0F3A4C_P_2 */
10139 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
} },
10142 /* VEX_W_0F3A60_P_2 */
10143 { "vpcmpestrm", { XM
, EXx
, Ib
} },
10146 /* VEX_W_0F3A61_P_2 */
10147 { "vpcmpestri", { XM
, EXx
, Ib
} },
10150 /* VEX_W_0F3A62_P_2 */
10151 { "vpcmpistrm", { XM
, EXx
, Ib
} },
10154 /* VEX_W_0F3A63_P_2 */
10155 { "vpcmpistri", { XM
, EXx
, Ib
} },
10158 /* VEX_W_0F3ADF_P_2 */
10159 { "vaeskeygenassist", { XM
, EXx
, Ib
} },
10163 static const struct dis386 mod_table
[][2] = {
10166 { "leaS", { Gv
, M
} },
10171 { RM_TABLE (RM_C6_REG_7
) },
10176 { RM_TABLE (RM_C7_REG_7
) },
10179 /* MOD_0F01_REG_0 */
10180 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10181 { RM_TABLE (RM_0F01_REG_0
) },
10184 /* MOD_0F01_REG_1 */
10185 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10186 { RM_TABLE (RM_0F01_REG_1
) },
10189 /* MOD_0F01_REG_2 */
10190 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10191 { RM_TABLE (RM_0F01_REG_2
) },
10194 /* MOD_0F01_REG_3 */
10195 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10196 { RM_TABLE (RM_0F01_REG_3
) },
10199 /* MOD_0F01_REG_7 */
10200 { "invlpg", { Mb
} },
10201 { RM_TABLE (RM_0F01_REG_7
) },
10204 /* MOD_0F12_PREFIX_0 */
10205 { "movlps", { XM
, EXq
} },
10206 { "movhlps", { XM
, EXq
} },
10210 { "movlpX", { EXq
, XM
} },
10213 /* MOD_0F16_PREFIX_0 */
10214 { "movhps", { XM
, EXq
} },
10215 { "movlhps", { XM
, EXq
} },
10219 { "movhpX", { EXq
, XM
} },
10222 /* MOD_0F18_REG_0 */
10223 { "prefetchnta", { Mb
} },
10226 /* MOD_0F18_REG_1 */
10227 { "prefetcht0", { Mb
} },
10230 /* MOD_0F18_REG_2 */
10231 { "prefetcht1", { Mb
} },
10234 /* MOD_0F18_REG_3 */
10235 { "prefetcht2", { Mb
} },
10238 /* MOD_0F18_REG_4 */
10239 { "nop/reserved", { Mb
} },
10242 /* MOD_0F18_REG_5 */
10243 { "nop/reserved", { Mb
} },
10246 /* MOD_0F18_REG_6 */
10247 { "nop/reserved", { Mb
} },
10250 /* MOD_0F18_REG_7 */
10251 { "nop/reserved", { Mb
} },
10256 { "movZ", { Rm
, Cm
} },
10261 { "movZ", { Rm
, Dm
} },
10266 { "movZ", { Cm
, Rm
} },
10271 { "movZ", { Dm
, Rm
} },
10276 { "movL", { Rd
, Td
} },
10281 { "movL", { Td
, Rd
} },
10284 /* MOD_0F2B_PREFIX_0 */
10285 {"movntps", { Mx
, XM
} },
10288 /* MOD_0F2B_PREFIX_1 */
10289 {"movntss", { Md
, XM
} },
10292 /* MOD_0F2B_PREFIX_2 */
10293 {"movntpd", { Mx
, XM
} },
10296 /* MOD_0F2B_PREFIX_3 */
10297 {"movntsd", { Mq
, XM
} },
10302 { "movmskpX", { Gdq
, XS
} },
10305 /* MOD_0F71_REG_2 */
10307 { "psrlw", { MS
, Ib
} },
10310 /* MOD_0F71_REG_4 */
10312 { "psraw", { MS
, Ib
} },
10315 /* MOD_0F71_REG_6 */
10317 { "psllw", { MS
, Ib
} },
10320 /* MOD_0F72_REG_2 */
10322 { "psrld", { MS
, Ib
} },
10325 /* MOD_0F72_REG_4 */
10327 { "psrad", { MS
, Ib
} },
10330 /* MOD_0F72_REG_6 */
10332 { "pslld", { MS
, Ib
} },
10335 /* MOD_0F73_REG_2 */
10337 { "psrlq", { MS
, Ib
} },
10340 /* MOD_0F73_REG_3 */
10342 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10345 /* MOD_0F73_REG_6 */
10347 { "psllq", { MS
, Ib
} },
10350 /* MOD_0F73_REG_7 */
10352 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10355 /* MOD_0FAE_REG_0 */
10356 { "fxsave", { FXSAVE
} },
10357 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
10360 /* MOD_0FAE_REG_1 */
10361 { "fxrstor", { FXSAVE
} },
10362 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
10365 /* MOD_0FAE_REG_2 */
10366 { "ldmxcsr", { Md
} },
10367 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
10370 /* MOD_0FAE_REG_3 */
10371 { "stmxcsr", { Md
} },
10372 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
10375 /* MOD_0FAE_REG_4 */
10376 { "xsave", { FXSAVE
} },
10379 /* MOD_0FAE_REG_5 */
10380 { "xrstor", { FXSAVE
} },
10381 { RM_TABLE (RM_0FAE_REG_5
) },
10384 /* MOD_0FAE_REG_6 */
10385 { "xsaveopt", { FXSAVE
} },
10386 { RM_TABLE (RM_0FAE_REG_6
) },
10389 /* MOD_0FAE_REG_7 */
10390 { "clflush", { Mb
} },
10391 { RM_TABLE (RM_0FAE_REG_7
) },
10395 { "lssS", { Gv
, Mp
} },
10399 { "lfsS", { Gv
, Mp
} },
10403 { "lgsS", { Gv
, Mp
} },
10406 /* MOD_0FC7_REG_6 */
10407 { PREFIX_TABLE (PREFIX_0FC7_REG_6
) },
10408 { "rdrand", { Ev
} },
10411 /* MOD_0FC7_REG_7 */
10412 { "vmptrst", { Mq
} },
10413 { "rdseed", { Ev
} },
10418 { "pmovmskb", { Gdq
, MS
} },
10421 /* MOD_0FE7_PREFIX_2 */
10422 { "movntdq", { Mx
, XM
} },
10425 /* MOD_0FF0_PREFIX_3 */
10426 { "lddqu", { XM
, M
} },
10429 /* MOD_0F382A_PREFIX_2 */
10430 { "movntdqa", { XM
, Mx
} },
10434 { "bound{S|}", { Gv
, Ma
} },
10438 { "lesS", { Gv
, Mp
} },
10439 { VEX_C4_TABLE (VEX_0F
) },
10443 { "ldsS", { Gv
, Mp
} },
10444 { VEX_C5_TABLE (VEX_0F
) },
10447 /* MOD_VEX_0F12_PREFIX_0 */
10448 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10449 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10453 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10456 /* MOD_VEX_0F16_PREFIX_0 */
10457 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10458 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10462 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10466 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
10471 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
10474 /* MOD_VEX_0F71_REG_2 */
10476 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10479 /* MOD_VEX_0F71_REG_4 */
10481 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10484 /* MOD_VEX_0F71_REG_6 */
10486 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10489 /* MOD_VEX_0F72_REG_2 */
10491 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10494 /* MOD_VEX_0F72_REG_4 */
10496 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10499 /* MOD_VEX_0F72_REG_6 */
10501 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10504 /* MOD_VEX_0F73_REG_2 */
10506 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10509 /* MOD_VEX_0F73_REG_3 */
10511 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10514 /* MOD_VEX_0F73_REG_6 */
10516 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10519 /* MOD_VEX_0F73_REG_7 */
10521 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10524 /* MOD_VEX_0FAE_REG_2 */
10525 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10528 /* MOD_VEX_0FAE_REG_3 */
10529 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10532 /* MOD_VEX_0FD7_PREFIX_2 */
10534 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
10537 /* MOD_VEX_0FE7_PREFIX_2 */
10538 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
10541 /* MOD_VEX_0FF0_PREFIX_3 */
10542 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
10545 /* MOD_VEX_0F381A_PREFIX_2 */
10546 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10549 /* MOD_VEX_0F382A_PREFIX_2 */
10550 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
10553 /* MOD_VEX_0F382C_PREFIX_2 */
10554 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10557 /* MOD_VEX_0F382D_PREFIX_2 */
10558 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10561 /* MOD_VEX_0F382E_PREFIX_2 */
10562 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10565 /* MOD_VEX_0F382F_PREFIX_2 */
10566 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10569 /* MOD_VEX_0F385A_PREFIX_2 */
10570 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10573 /* MOD_VEX_0F388C_PREFIX_2 */
10574 { "vpmaskmov%LW", { XM
, Vex
, Mx
} },
10577 /* MOD_VEX_0F388E_PREFIX_2 */
10578 { "vpmaskmov%LW", { Mx
, Vex
, XM
} },
10582 static const struct dis386 rm_table
[][8] = {
10585 { "xabort", { Skip_MODRM
, Ib
} },
10589 { "xbeginT", { Skip_MODRM
, Jv
} },
10592 /* RM_0F01_REG_0 */
10594 { "vmcall", { Skip_MODRM
} },
10595 { "vmlaunch", { Skip_MODRM
} },
10596 { "vmresume", { Skip_MODRM
} },
10597 { "vmxoff", { Skip_MODRM
} },
10600 /* RM_0F01_REG_1 */
10601 { "monitor", { { OP_Monitor
, 0 } } },
10602 { "mwait", { { OP_Mwait
, 0 } } },
10605 /* RM_0F01_REG_2 */
10606 { "xgetbv", { Skip_MODRM
} },
10607 { "xsetbv", { Skip_MODRM
} },
10610 { "vmfunc", { Skip_MODRM
} },
10611 { "xend", { Skip_MODRM
} },
10612 { "xtest", { Skip_MODRM
} },
10616 /* RM_0F01_REG_3 */
10617 { "vmrun", { Skip_MODRM
} },
10618 { "vmmcall", { Skip_MODRM
} },
10619 { "vmload", { Skip_MODRM
} },
10620 { "vmsave", { Skip_MODRM
} },
10621 { "stgi", { Skip_MODRM
} },
10622 { "clgi", { Skip_MODRM
} },
10623 { "skinit", { Skip_MODRM
} },
10624 { "invlpga", { Skip_MODRM
} },
10627 /* RM_0F01_REG_7 */
10628 { "swapgs", { Skip_MODRM
} },
10629 { "rdtscp", { Skip_MODRM
} },
10632 /* RM_0FAE_REG_5 */
10633 { "lfence", { Skip_MODRM
} },
10636 /* RM_0FAE_REG_6 */
10637 { "mfence", { Skip_MODRM
} },
10640 /* RM_0FAE_REG_7 */
10641 { "sfence", { Skip_MODRM
} },
10645 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10647 /* We use the high bit to indicate different name for the same
10649 #define ADDR16_PREFIX (0x67 | 0x100)
10650 #define ADDR32_PREFIX (0x67 | 0x200)
10651 #define DATA16_PREFIX (0x66 | 0x100)
10652 #define DATA32_PREFIX (0x66 | 0x200)
10653 #define REP_PREFIX (0xf3 | 0x100)
10654 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10655 #define XRELEASE_PREFIX (0xf3 | 0x400)
10660 int newrex
, i
, length
;
10666 last_lock_prefix
= -1;
10667 last_repz_prefix
= -1;
10668 last_repnz_prefix
= -1;
10669 last_data_prefix
= -1;
10670 last_addr_prefix
= -1;
10671 last_rex_prefix
= -1;
10672 last_seg_prefix
= -1;
10673 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
10674 all_prefixes
[i
] = 0;
10677 /* The maximum instruction length is 15bytes. */
10678 while (length
< MAX_CODE_LENGTH
- 1)
10680 FETCH_DATA (the_info
, codep
+ 1);
10684 /* REX prefixes family. */
10701 if (address_mode
== mode_64bit
)
10705 last_rex_prefix
= i
;
10708 prefixes
|= PREFIX_REPZ
;
10709 last_repz_prefix
= i
;
10712 prefixes
|= PREFIX_REPNZ
;
10713 last_repnz_prefix
= i
;
10716 prefixes
|= PREFIX_LOCK
;
10717 last_lock_prefix
= i
;
10720 prefixes
|= PREFIX_CS
;
10721 last_seg_prefix
= i
;
10724 prefixes
|= PREFIX_SS
;
10725 last_seg_prefix
= i
;
10728 prefixes
|= PREFIX_DS
;
10729 last_seg_prefix
= i
;
10732 prefixes
|= PREFIX_ES
;
10733 last_seg_prefix
= i
;
10736 prefixes
|= PREFIX_FS
;
10737 last_seg_prefix
= i
;
10740 prefixes
|= PREFIX_GS
;
10741 last_seg_prefix
= i
;
10744 prefixes
|= PREFIX_DATA
;
10745 last_data_prefix
= i
;
10748 prefixes
|= PREFIX_ADDR
;
10749 last_addr_prefix
= i
;
10752 /* fwait is really an instruction. If there are prefixes
10753 before the fwait, they belong to the fwait, *not* to the
10754 following instruction. */
10755 if (prefixes
|| rex
)
10757 prefixes
|= PREFIX_FWAIT
;
10761 prefixes
= PREFIX_FWAIT
;
10766 /* Rex is ignored when followed by another prefix. */
10772 if (*codep
!= FWAIT_OPCODE
)
10773 all_prefixes
[i
++] = *codep
;
10782 seg_prefix (int pref
)
10803 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10806 static const char *
10807 prefix_name (int pref
, int sizeflag
)
10809 static const char *rexes
[16] =
10812 "rex.B", /* 0x41 */
10813 "rex.X", /* 0x42 */
10814 "rex.XB", /* 0x43 */
10815 "rex.R", /* 0x44 */
10816 "rex.RB", /* 0x45 */
10817 "rex.RX", /* 0x46 */
10818 "rex.RXB", /* 0x47 */
10819 "rex.W", /* 0x48 */
10820 "rex.WB", /* 0x49 */
10821 "rex.WX", /* 0x4a */
10822 "rex.WXB", /* 0x4b */
10823 "rex.WR", /* 0x4c */
10824 "rex.WRB", /* 0x4d */
10825 "rex.WRX", /* 0x4e */
10826 "rex.WRXB", /* 0x4f */
10831 /* REX prefixes family. */
10848 return rexes
[pref
- 0x40];
10868 return (sizeflag
& DFLAG
) ? "data16" : "data32";
10870 if (address_mode
== mode_64bit
)
10871 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
10873 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
10876 case ADDR16_PREFIX
:
10878 case ADDR32_PREFIX
:
10880 case DATA16_PREFIX
:
10882 case DATA32_PREFIX
:
10886 case XACQUIRE_PREFIX
:
10888 case XRELEASE_PREFIX
:
10895 static char op_out
[MAX_OPERANDS
][100];
10896 static int op_ad
, op_index
[MAX_OPERANDS
];
10897 static int two_source_ops
;
10898 static bfd_vma op_address
[MAX_OPERANDS
];
10899 static bfd_vma op_riprel
[MAX_OPERANDS
];
10900 static bfd_vma start_pc
;
10903 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10904 * (see topic "Redundant prefixes" in the "Differences from 8086"
10905 * section of the "Virtual 8086 Mode" chapter.)
10906 * 'pc' should be the address of this instruction, it will
10907 * be used to print the target address if this is a relative jump or call
10908 * The function returns the length of this instruction in bytes.
10911 static char intel_syntax
;
10912 static char intel_mnemonic
= !SYSV386_COMPAT
;
10913 static char open_char
;
10914 static char close_char
;
10915 static char separator_char
;
10916 static char scale_char
;
10918 /* Here for backwards compatibility. When gdb stops using
10919 print_insn_i386_att and print_insn_i386_intel these functions can
10920 disappear, and print_insn_i386 be merged into print_insn. */
10922 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
10926 return print_insn (pc
, info
);
10930 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
10934 return print_insn (pc
, info
);
10938 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
10942 return print_insn (pc
, info
);
10946 print_i386_disassembler_options (FILE *stream
)
10948 fprintf (stream
, _("\n\
10949 The following i386/x86-64 specific disassembler options are supported for use\n\
10950 with the -M switch (multiple options should be separated by commas):\n"));
10952 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
10953 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
10954 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
10955 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
10956 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
10957 fprintf (stream
, _(" att-mnemonic\n"
10958 " Display instruction in AT&T mnemonic\n"));
10959 fprintf (stream
, _(" intel-mnemonic\n"
10960 " Display instruction in Intel mnemonic\n"));
10961 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
10962 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
10963 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
10964 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
10965 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
10966 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
10970 static const struct dis386 bad_opcode
= { "(bad)", { XX
} };
10972 /* Get a pointer to struct dis386 with a valid name. */
10974 static const struct dis386
*
10975 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
10977 int vindex
, vex_table_index
;
10979 if (dp
->name
!= NULL
)
10982 switch (dp
->op
[0].bytemode
)
10984 case USE_REG_TABLE
:
10985 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
10988 case USE_MOD_TABLE
:
10989 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
10990 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
10994 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
10997 case USE_PREFIX_TABLE
:
11000 /* The prefix in VEX is implicit. */
11001 switch (vex
.prefix
)
11006 case REPE_PREFIX_OPCODE
:
11009 case DATA_PREFIX_OPCODE
:
11012 case REPNE_PREFIX_OPCODE
:
11023 used_prefixes
|= (prefixes
& PREFIX_REPZ
);
11024 if (prefixes
& PREFIX_REPZ
)
11027 all_prefixes
[last_repz_prefix
] = 0;
11031 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11033 used_prefixes
|= (prefixes
& PREFIX_REPNZ
);
11034 if (prefixes
& PREFIX_REPNZ
)
11037 all_prefixes
[last_repnz_prefix
] = 0;
11041 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11042 if (prefixes
& PREFIX_DATA
)
11045 all_prefixes
[last_data_prefix
] = 0;
11050 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11053 case USE_X86_64_TABLE
:
11054 vindex
= address_mode
== mode_64bit
? 1 : 0;
11055 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11058 case USE_3BYTE_TABLE
:
11059 FETCH_DATA (info
, codep
+ 2);
11061 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11062 modrm
.mod
= (*codep
>> 6) & 3;
11063 modrm
.reg
= (*codep
>> 3) & 7;
11064 modrm
.rm
= *codep
& 7;
11067 case USE_VEX_LEN_TABLE
:
11071 switch (vex
.length
)
11084 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11087 case USE_XOP_8F_TABLE
:
11088 FETCH_DATA (info
, codep
+ 3);
11089 /* All bits in the REX prefix are ignored. */
11091 rex
= ~(*codep
>> 5) & 0x7;
11093 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11094 switch ((*codep
& 0x1f))
11100 vex_table_index
= XOP_08
;
11103 vex_table_index
= XOP_09
;
11106 vex_table_index
= XOP_0A
;
11110 vex
.w
= *codep
& 0x80;
11111 if (vex
.w
&& address_mode
== mode_64bit
)
11114 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11115 if (address_mode
!= mode_64bit
11116 && vex
.register_specifier
> 0x7)
11122 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11123 switch ((*codep
& 0x3))
11129 vex
.prefix
= DATA_PREFIX_OPCODE
;
11132 vex
.prefix
= REPE_PREFIX_OPCODE
;
11135 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11142 dp
= &xop_table
[vex_table_index
][vindex
];
11144 FETCH_DATA (info
, codep
+ 1);
11145 modrm
.mod
= (*codep
>> 6) & 3;
11146 modrm
.reg
= (*codep
>> 3) & 7;
11147 modrm
.rm
= *codep
& 7;
11150 case USE_VEX_C4_TABLE
:
11151 FETCH_DATA (info
, codep
+ 3);
11152 /* All bits in the REX prefix are ignored. */
11154 rex
= ~(*codep
>> 5) & 0x7;
11155 switch ((*codep
& 0x1f))
11161 vex_table_index
= VEX_0F
;
11164 vex_table_index
= VEX_0F38
;
11167 vex_table_index
= VEX_0F3A
;
11171 vex
.w
= *codep
& 0x80;
11172 if (vex
.w
&& address_mode
== mode_64bit
)
11175 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11176 if (address_mode
!= mode_64bit
11177 && vex
.register_specifier
> 0x7)
11183 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11184 switch ((*codep
& 0x3))
11190 vex
.prefix
= DATA_PREFIX_OPCODE
;
11193 vex
.prefix
= REPE_PREFIX_OPCODE
;
11196 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11203 dp
= &vex_table
[vex_table_index
][vindex
];
11204 /* There is no MODRM byte for VEX [82|77]. */
11205 if (vindex
!= 0x77 && vindex
!= 0x82)
11207 FETCH_DATA (info
, codep
+ 1);
11208 modrm
.mod
= (*codep
>> 6) & 3;
11209 modrm
.reg
= (*codep
>> 3) & 7;
11210 modrm
.rm
= *codep
& 7;
11214 case USE_VEX_C5_TABLE
:
11215 FETCH_DATA (info
, codep
+ 2);
11216 /* All bits in the REX prefix are ignored. */
11218 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11220 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11221 if (address_mode
!= mode_64bit
11222 && vex
.register_specifier
> 0x7)
11230 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11231 switch ((*codep
& 0x3))
11237 vex
.prefix
= DATA_PREFIX_OPCODE
;
11240 vex
.prefix
= REPE_PREFIX_OPCODE
;
11243 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11250 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11251 /* There is no MODRM byte for VEX [82|77]. */
11252 if (vindex
!= 0x77 && vindex
!= 0x82)
11254 FETCH_DATA (info
, codep
+ 1);
11255 modrm
.mod
= (*codep
>> 6) & 3;
11256 modrm
.reg
= (*codep
>> 3) & 7;
11257 modrm
.rm
= *codep
& 7;
11261 case USE_VEX_W_TABLE
:
11265 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11276 if (dp
->name
!= NULL
)
11279 return get_valid_dis386 (dp
, info
);
11283 get_sib (disassemble_info
*info
)
11285 /* If modrm.mod == 3, operand must be register. */
11287 && address_mode
!= mode_16bit
11291 FETCH_DATA (info
, codep
+ 2);
11292 sib
.index
= (codep
[1] >> 3) & 7;
11293 sib
.scale
= (codep
[1] >> 6) & 3;
11294 sib
.base
= codep
[1] & 7;
11299 print_insn (bfd_vma pc
, disassemble_info
*info
)
11301 const struct dis386
*dp
;
11303 char *op_txt
[MAX_OPERANDS
];
11307 struct dis_private priv
;
11309 int default_prefixes
;
11311 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11312 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11313 address_mode
= mode_32bit
;
11314 else if (info
->mach
== bfd_mach_i386_i8086
)
11316 address_mode
= mode_16bit
;
11317 priv
.orig_sizeflag
= 0;
11320 address_mode
= mode_64bit
;
11322 if (intel_syntax
== (char) -1)
11323 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11325 for (p
= info
->disassembler_options
; p
!= NULL
; )
11327 if (CONST_STRNEQ (p
, "x86-64"))
11329 address_mode
= mode_64bit
;
11330 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11332 else if (CONST_STRNEQ (p
, "i386"))
11334 address_mode
= mode_32bit
;
11335 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11337 else if (CONST_STRNEQ (p
, "i8086"))
11339 address_mode
= mode_16bit
;
11340 priv
.orig_sizeflag
= 0;
11342 else if (CONST_STRNEQ (p
, "intel"))
11345 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11346 intel_mnemonic
= 1;
11348 else if (CONST_STRNEQ (p
, "att"))
11351 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11352 intel_mnemonic
= 0;
11354 else if (CONST_STRNEQ (p
, "addr"))
11356 if (address_mode
== mode_64bit
)
11358 if (p
[4] == '3' && p
[5] == '2')
11359 priv
.orig_sizeflag
&= ~AFLAG
;
11360 else if (p
[4] == '6' && p
[5] == '4')
11361 priv
.orig_sizeflag
|= AFLAG
;
11365 if (p
[4] == '1' && p
[5] == '6')
11366 priv
.orig_sizeflag
&= ~AFLAG
;
11367 else if (p
[4] == '3' && p
[5] == '2')
11368 priv
.orig_sizeflag
|= AFLAG
;
11371 else if (CONST_STRNEQ (p
, "data"))
11373 if (p
[4] == '1' && p
[5] == '6')
11374 priv
.orig_sizeflag
&= ~DFLAG
;
11375 else if (p
[4] == '3' && p
[5] == '2')
11376 priv
.orig_sizeflag
|= DFLAG
;
11378 else if (CONST_STRNEQ (p
, "suffix"))
11379 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11381 p
= strchr (p
, ',');
11388 names64
= intel_names64
;
11389 names32
= intel_names32
;
11390 names16
= intel_names16
;
11391 names8
= intel_names8
;
11392 names8rex
= intel_names8rex
;
11393 names_seg
= intel_names_seg
;
11394 names_mm
= intel_names_mm
;
11395 names_xmm
= intel_names_xmm
;
11396 names_ymm
= intel_names_ymm
;
11397 index64
= intel_index64
;
11398 index32
= intel_index32
;
11399 index16
= intel_index16
;
11402 separator_char
= '+';
11407 names64
= att_names64
;
11408 names32
= att_names32
;
11409 names16
= att_names16
;
11410 names8
= att_names8
;
11411 names8rex
= att_names8rex
;
11412 names_seg
= att_names_seg
;
11413 names_mm
= att_names_mm
;
11414 names_xmm
= att_names_xmm
;
11415 names_ymm
= att_names_ymm
;
11416 index64
= att_index64
;
11417 index32
= att_index32
;
11418 index16
= att_index16
;
11421 separator_char
= ',';
11425 /* The output looks better if we put 7 bytes on a line, since that
11426 puts most long word instructions on a single line. Use 8 bytes
11428 if ((info
->mach
& bfd_mach_l1om
) != 0)
11429 info
->bytes_per_line
= 8;
11431 info
->bytes_per_line
= 7;
11433 info
->private_data
= &priv
;
11434 priv
.max_fetched
= priv
.the_buffer
;
11435 priv
.insn_start
= pc
;
11438 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11446 start_codep
= priv
.the_buffer
;
11447 codep
= priv
.the_buffer
;
11449 if (setjmp (priv
.bailout
) != 0)
11453 /* Getting here means we tried for data but didn't get it. That
11454 means we have an incomplete instruction of some sort. Just
11455 print the first byte as a prefix or a .byte pseudo-op. */
11456 if (codep
> priv
.the_buffer
)
11458 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
11460 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11463 /* Just print the first byte as a .byte instruction. */
11464 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
11465 (unsigned int) priv
.the_buffer
[0]);
11475 sizeflag
= priv
.orig_sizeflag
;
11477 if (!ckprefix () || rex_used
)
11479 /* Too many prefixes or unused REX prefixes. */
11481 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
11483 (*info
->fprintf_func
) (info
->stream
, "%s%s",
11485 prefix_name (all_prefixes
[i
], sizeflag
));
11489 insn_codep
= codep
;
11491 FETCH_DATA (info
, codep
+ 1);
11492 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
11494 if (((prefixes
& PREFIX_FWAIT
)
11495 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
11497 (*info
->fprintf_func
) (info
->stream
, "fwait");
11501 if (*codep
== 0x0f)
11503 unsigned char threebyte
;
11504 FETCH_DATA (info
, codep
+ 2);
11505 threebyte
= *++codep
;
11506 dp
= &dis386_twobyte
[threebyte
];
11507 need_modrm
= twobyte_has_modrm
[*codep
];
11512 dp
= &dis386
[*codep
];
11513 need_modrm
= onebyte_has_modrm
[*codep
];
11517 if ((prefixes
& PREFIX_REPZ
))
11518 used_prefixes
|= PREFIX_REPZ
;
11519 if ((prefixes
& PREFIX_REPNZ
))
11520 used_prefixes
|= PREFIX_REPNZ
;
11521 if ((prefixes
& PREFIX_LOCK
))
11522 used_prefixes
|= PREFIX_LOCK
;
11524 default_prefixes
= 0;
11525 if (prefixes
& PREFIX_ADDR
)
11528 if (dp
->op
[2].bytemode
!= loop_jcxz_mode
|| intel_syntax
)
11530 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11531 all_prefixes
[last_addr_prefix
] = ADDR32_PREFIX
;
11533 all_prefixes
[last_addr_prefix
] = ADDR16_PREFIX
;
11534 default_prefixes
|= PREFIX_ADDR
;
11538 if ((prefixes
& PREFIX_DATA
))
11541 if (dp
->op
[2].bytemode
== cond_jump_mode
11542 && dp
->op
[0].bytemode
== v_mode
11545 if (sizeflag
& DFLAG
)
11546 all_prefixes
[last_data_prefix
] = DATA32_PREFIX
;
11548 all_prefixes
[last_data_prefix
] = DATA16_PREFIX
;
11549 default_prefixes
|= PREFIX_DATA
;
11551 else if (rex
& REX_W
)
11553 /* REX_W will override PREFIX_DATA. */
11554 default_prefixes
|= PREFIX_DATA
;
11560 FETCH_DATA (info
, codep
+ 1);
11561 modrm
.mod
= (*codep
>> 6) & 3;
11562 modrm
.reg
= (*codep
>> 3) & 7;
11563 modrm
.rm
= *codep
& 7;
11570 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
11573 dofloat (sizeflag
);
11577 dp
= get_valid_dis386 (dp
, info
);
11578 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
11581 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11584 op_ad
= MAX_OPERANDS
- 1 - i
;
11586 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
11591 /* See if any prefixes were not used. If so, print the first one
11592 separately. If we don't do this, we'll wind up printing an
11593 instruction stream which does not precisely correspond to the
11594 bytes we are disassembling. */
11595 if ((prefixes
& ~(used_prefixes
| default_prefixes
)) != 0)
11597 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11598 if (all_prefixes
[i
])
11601 name
= prefix_name (all_prefixes
[i
], priv
.orig_sizeflag
);
11603 name
= INTERNAL_DISASSEMBLER_ERROR
;
11604 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11609 /* Check if the REX prefix is used. */
11610 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0)
11611 all_prefixes
[last_rex_prefix
] = 0;
11613 /* Check if the SEG prefix is used. */
11614 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
11615 | PREFIX_FS
| PREFIX_GS
)) != 0
11617 & seg_prefix (all_prefixes
[last_seg_prefix
])) != 0)
11618 all_prefixes
[last_seg_prefix
] = 0;
11620 /* Check if the ADDR prefix is used. */
11621 if ((prefixes
& PREFIX_ADDR
) != 0
11622 && (used_prefixes
& PREFIX_ADDR
) != 0)
11623 all_prefixes
[last_addr_prefix
] = 0;
11625 /* Check if the DATA prefix is used. */
11626 if ((prefixes
& PREFIX_DATA
) != 0
11627 && (used_prefixes
& PREFIX_DATA
) != 0)
11628 all_prefixes
[last_data_prefix
] = 0;
11631 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11632 if (all_prefixes
[i
])
11635 name
= prefix_name (all_prefixes
[i
], sizeflag
);
11638 prefix_length
+= strlen (name
) + 1;
11639 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
11642 /* Check maximum code length. */
11643 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
11645 (*info
->fprintf_func
) (info
->stream
, "(bad)");
11646 return MAX_CODE_LENGTH
;
11649 obufp
= mnemonicendp
;
11650 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
11653 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
11655 /* The enter and bound instructions are printed with operands in the same
11656 order as the intel book; everything else is printed in reverse order. */
11657 if (intel_syntax
|| two_source_ops
)
11661 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11662 op_txt
[i
] = op_out
[i
];
11664 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
11666 op_ad
= op_index
[i
];
11667 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
11668 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
11669 riprel
= op_riprel
[i
];
11670 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
11671 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
11676 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11677 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
11681 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11685 (*info
->fprintf_func
) (info
->stream
, ",");
11686 if (op_index
[i
] != -1 && !op_riprel
[i
])
11687 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
11689 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
11693 for (i
= 0; i
< MAX_OPERANDS
; i
++)
11694 if (op_index
[i
] != -1 && op_riprel
[i
])
11696 (*info
->fprintf_func
) (info
->stream
, " # ");
11697 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
11698 + op_address
[op_index
[i
]]), info
);
11701 return codep
- priv
.the_buffer
;
11704 static const char *float_mem
[] = {
11779 static const unsigned char float_mem_mode
[] = {
11854 #define ST { OP_ST, 0 }
11855 #define STi { OP_STi, 0 }
11857 #define FGRPd9_2 NULL, { { NULL, 0 } }
11858 #define FGRPd9_4 NULL, { { NULL, 1 } }
11859 #define FGRPd9_5 NULL, { { NULL, 2 } }
11860 #define FGRPd9_6 NULL, { { NULL, 3 } }
11861 #define FGRPd9_7 NULL, { { NULL, 4 } }
11862 #define FGRPda_5 NULL, { { NULL, 5 } }
11863 #define FGRPdb_4 NULL, { { NULL, 6 } }
11864 #define FGRPde_3 NULL, { { NULL, 7 } }
11865 #define FGRPdf_4 NULL, { { NULL, 8 } }
11867 static const struct dis386 float_reg
[][8] = {
11870 { "fadd", { ST
, STi
} },
11871 { "fmul", { ST
, STi
} },
11872 { "fcom", { STi
} },
11873 { "fcomp", { STi
} },
11874 { "fsub", { ST
, STi
} },
11875 { "fsubr", { ST
, STi
} },
11876 { "fdiv", { ST
, STi
} },
11877 { "fdivr", { ST
, STi
} },
11881 { "fld", { STi
} },
11882 { "fxch", { STi
} },
11892 { "fcmovb", { ST
, STi
} },
11893 { "fcmove", { ST
, STi
} },
11894 { "fcmovbe",{ ST
, STi
} },
11895 { "fcmovu", { ST
, STi
} },
11903 { "fcmovnb",{ ST
, STi
} },
11904 { "fcmovne",{ ST
, STi
} },
11905 { "fcmovnbe",{ ST
, STi
} },
11906 { "fcmovnu",{ ST
, STi
} },
11908 { "fucomi", { ST
, STi
} },
11909 { "fcomi", { ST
, STi
} },
11914 { "fadd", { STi
, ST
} },
11915 { "fmul", { STi
, ST
} },
11918 { "fsub!M", { STi
, ST
} },
11919 { "fsubM", { STi
, ST
} },
11920 { "fdiv!M", { STi
, ST
} },
11921 { "fdivM", { STi
, ST
} },
11925 { "ffree", { STi
} },
11927 { "fst", { STi
} },
11928 { "fstp", { STi
} },
11929 { "fucom", { STi
} },
11930 { "fucomp", { STi
} },
11936 { "faddp", { STi
, ST
} },
11937 { "fmulp", { STi
, ST
} },
11940 { "fsub!Mp", { STi
, ST
} },
11941 { "fsubMp", { STi
, ST
} },
11942 { "fdiv!Mp", { STi
, ST
} },
11943 { "fdivMp", { STi
, ST
} },
11947 { "ffreep", { STi
} },
11952 { "fucomip", { ST
, STi
} },
11953 { "fcomip", { ST
, STi
} },
11958 static char *fgrps
[][8] = {
11961 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11966 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11971 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11976 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11981 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11986 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11991 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11992 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11997 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12002 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12007 swap_operand (void)
12009 mnemonicendp
[0] = '.';
12010 mnemonicendp
[1] = 's';
12015 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12016 int sizeflag ATTRIBUTE_UNUSED
)
12018 /* Skip mod/rm byte. */
12024 dofloat (int sizeflag
)
12026 const struct dis386
*dp
;
12027 unsigned char floatop
;
12029 floatop
= codep
[-1];
12031 if (modrm
.mod
!= 3)
12033 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12035 putop (float_mem
[fp_indx
], sizeflag
);
12038 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12041 /* Skip mod/rm byte. */
12045 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12046 if (dp
->name
== NULL
)
12048 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12050 /* Instruction fnstsw is only one with strange arg. */
12051 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12052 strcpy (op_out
[0], names16
[0]);
12056 putop (dp
->name
, sizeflag
);
12061 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12066 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12071 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12073 oappend ("%st" + intel_syntax
);
12077 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12079 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12080 oappend (scratchbuf
+ intel_syntax
);
12083 /* Capital letters in template are macros. */
12085 putop (const char *in_template
, int sizeflag
)
12090 unsigned int l
= 0, len
= 1;
12093 #define SAVE_LAST(c) \
12094 if (l < len && l < sizeof (last)) \
12099 for (p
= in_template
; *p
; p
++)
12116 while (*++p
!= '|')
12117 if (*p
== '}' || *p
== '\0')
12120 /* Fall through. */
12125 while (*++p
!= '}')
12136 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12140 if (l
== 0 && len
== 1)
12145 if (sizeflag
& SUFFIX_ALWAYS
)
12158 if (address_mode
== mode_64bit
12159 && !(prefixes
& PREFIX_ADDR
))
12170 if (intel_syntax
&& !alt
)
12172 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12174 if (sizeflag
& DFLAG
)
12175 *obufp
++ = intel_syntax
? 'd' : 'l';
12177 *obufp
++ = intel_syntax
? 'w' : 's';
12178 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12182 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12185 if (modrm
.mod
== 3)
12191 if (sizeflag
& DFLAG
)
12192 *obufp
++ = intel_syntax
? 'd' : 'l';
12195 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12201 case 'E': /* For jcxz/jecxz */
12202 if (address_mode
== mode_64bit
)
12204 if (sizeflag
& AFLAG
)
12210 if (sizeflag
& AFLAG
)
12212 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12217 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12219 if (sizeflag
& AFLAG
)
12220 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12222 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12223 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12227 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12229 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12233 if (!(rex
& REX_W
))
12234 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12239 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12240 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12242 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12245 if (prefixes
& PREFIX_DS
)
12266 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12271 /* Fall through. */
12274 if (l
!= 0 || len
!= 1)
12282 if (sizeflag
& SUFFIX_ALWAYS
)
12286 if (intel_mnemonic
!= cond
)
12290 if ((prefixes
& PREFIX_FWAIT
) == 0)
12293 used_prefixes
|= PREFIX_FWAIT
;
12299 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12303 if (!(rex
& REX_W
))
12304 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12308 && address_mode
== mode_64bit
12309 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12314 /* Fall through. */
12318 if ((rex
& REX_W
) == 0
12319 && (prefixes
& PREFIX_DATA
))
12321 if ((sizeflag
& DFLAG
) == 0)
12323 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12327 if ((prefixes
& PREFIX_DATA
)
12329 || (sizeflag
& SUFFIX_ALWAYS
))
12336 if (sizeflag
& DFLAG
)
12340 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12347 if (address_mode
== mode_64bit
12348 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12350 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12354 /* Fall through. */
12357 if (l
== 0 && len
== 1)
12360 if (intel_syntax
&& !alt
)
12363 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12369 if (sizeflag
& DFLAG
)
12370 *obufp
++ = intel_syntax
? 'd' : 'l';
12373 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12379 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12385 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12400 else if (sizeflag
& DFLAG
)
12409 if (intel_syntax
&& !p
[1]
12410 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
12412 if (!(rex
& REX_W
))
12413 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12416 if (l
== 0 && len
== 1)
12420 if (address_mode
== mode_64bit
12421 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12423 if (sizeflag
& SUFFIX_ALWAYS
)
12445 /* Fall through. */
12448 if (l
== 0 && len
== 1)
12453 if (sizeflag
& SUFFIX_ALWAYS
)
12459 if (sizeflag
& DFLAG
)
12463 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12477 if (address_mode
== mode_64bit
12478 && !(prefixes
& PREFIX_ADDR
))
12489 if (l
!= 0 || len
!= 1)
12494 if (need_vex
&& vex
.prefix
)
12496 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
12503 if (prefixes
& PREFIX_DATA
)
12507 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12511 if (l
== 0 && len
== 1)
12513 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12524 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12532 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12534 switch (vex
.length
)
12548 if (l
== 0 && len
== 1)
12550 /* operand size flag for cwtl, cbtw */
12559 else if (sizeflag
& DFLAG
)
12563 if (!(rex
& REX_W
))
12564 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12571 && last
[0] != 'L'))
12578 if (last
[0] == 'X')
12579 *obufp
++ = vex
.w
? 'd': 's';
12581 *obufp
++ = vex
.w
? 'q': 'd';
12588 mnemonicendp
= obufp
;
12593 oappend (const char *s
)
12595 obufp
= stpcpy (obufp
, s
);
12601 if (prefixes
& PREFIX_CS
)
12603 used_prefixes
|= PREFIX_CS
;
12604 oappend ("%cs:" + intel_syntax
);
12606 if (prefixes
& PREFIX_DS
)
12608 used_prefixes
|= PREFIX_DS
;
12609 oappend ("%ds:" + intel_syntax
);
12611 if (prefixes
& PREFIX_SS
)
12613 used_prefixes
|= PREFIX_SS
;
12614 oappend ("%ss:" + intel_syntax
);
12616 if (prefixes
& PREFIX_ES
)
12618 used_prefixes
|= PREFIX_ES
;
12619 oappend ("%es:" + intel_syntax
);
12621 if (prefixes
& PREFIX_FS
)
12623 used_prefixes
|= PREFIX_FS
;
12624 oappend ("%fs:" + intel_syntax
);
12626 if (prefixes
& PREFIX_GS
)
12628 used_prefixes
|= PREFIX_GS
;
12629 oappend ("%gs:" + intel_syntax
);
12634 OP_indirE (int bytemode
, int sizeflag
)
12638 OP_E (bytemode
, sizeflag
);
12642 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
12644 if (address_mode
== mode_64bit
)
12652 sprintf_vma (tmp
, disp
);
12653 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
12654 strcpy (buf
+ 2, tmp
+ i
);
12658 bfd_signed_vma v
= disp
;
12665 /* Check for possible overflow on 0x8000000000000000. */
12668 strcpy (buf
, "9223372036854775808");
12682 tmp
[28 - i
] = (v
% 10) + '0';
12686 strcpy (buf
, tmp
+ 29 - i
);
12692 sprintf (buf
, "0x%x", (unsigned int) disp
);
12694 sprintf (buf
, "%d", (int) disp
);
12698 /* Put DISP in BUF as signed hex number. */
12701 print_displacement (char *buf
, bfd_vma disp
)
12703 bfd_signed_vma val
= disp
;
12712 /* Check for possible overflow. */
12715 switch (address_mode
)
12718 strcpy (buf
+ j
, "0x8000000000000000");
12721 strcpy (buf
+ j
, "0x80000000");
12724 strcpy (buf
+ j
, "0x8000");
12734 sprintf_vma (tmp
, (bfd_vma
) val
);
12735 for (i
= 0; tmp
[i
] == '0'; i
++)
12737 if (tmp
[i
] == '\0')
12739 strcpy (buf
+ j
, tmp
+ i
);
12743 intel_operand_size (int bytemode
, int sizeflag
)
12750 oappend ("BYTE PTR ");
12754 oappend ("WORD PTR ");
12757 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12759 oappend ("QWORD PTR ");
12768 oappend ("QWORD PTR ");
12771 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
12772 oappend ("DWORD PTR ");
12774 oappend ("WORD PTR ");
12775 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12779 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12781 oappend ("WORD PTR ");
12782 if (!(rex
& REX_W
))
12783 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12786 if (sizeflag
& DFLAG
)
12787 oappend ("QWORD PTR ");
12789 oappend ("DWORD PTR ");
12790 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12793 case d_scalar_mode
:
12794 case d_scalar_swap_mode
:
12797 oappend ("DWORD PTR ");
12800 case q_scalar_mode
:
12801 case q_scalar_swap_mode
:
12803 oappend ("QWORD PTR ");
12806 if (address_mode
== mode_64bit
)
12807 oappend ("QWORD PTR ");
12809 oappend ("DWORD PTR ");
12812 if (sizeflag
& DFLAG
)
12813 oappend ("FWORD PTR ");
12815 oappend ("DWORD PTR ");
12816 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12819 oappend ("TBYTE PTR ");
12825 switch (vex
.length
)
12828 oappend ("XMMWORD PTR ");
12831 oappend ("YMMWORD PTR ");
12838 oappend ("XMMWORD PTR ");
12841 oappend ("XMMWORD PTR ");
12847 switch (vex
.length
)
12850 oappend ("QWORD PTR ");
12853 oappend ("XMMWORD PTR ");
12863 switch (vex
.length
)
12867 oappend ("BYTE PTR ");
12877 switch (vex
.length
)
12881 oappend ("WORD PTR ");
12891 switch (vex
.length
)
12895 oappend ("DWORD PTR ");
12905 switch (vex
.length
)
12909 oappend ("QWORD PTR ");
12919 switch (vex
.length
)
12922 oappend ("WORD PTR ");
12925 oappend ("DWORD PTR ");
12935 switch (vex
.length
)
12938 oappend ("DWORD PTR ");
12941 oappend ("QWORD PTR ");
12951 switch (vex
.length
)
12954 oappend ("QWORD PTR ");
12957 oappend ("YMMWORD PTR ");
12967 switch (vex
.length
)
12971 oappend ("XMMWORD PTR ");
12978 oappend ("OWORD PTR ");
12980 case vex_w_dq_mode
:
12981 case vex_scalar_w_dq_mode
:
12982 case vex_vsib_d_w_dq_mode
:
12983 case vex_vsib_q_w_dq_mode
:
12988 oappend ("QWORD PTR ");
12990 oappend ("DWORD PTR ");
12998 OP_E_register (int bytemode
, int sizeflag
)
13000 int reg
= modrm
.rm
;
13001 const char **names
;
13007 if ((sizeflag
& SUFFIX_ALWAYS
)
13008 && (bytemode
== b_swap_mode
|| bytemode
== v_swap_mode
))
13031 names
= address_mode
== mode_64bit
? names64
: names32
;
13034 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13052 if ((sizeflag
& DFLAG
)
13053 || (bytemode
!= v_mode
13054 && bytemode
!= v_swap_mode
))
13058 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13064 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13067 oappend (names
[reg
]);
13071 OP_E_memory (int bytemode
, int sizeflag
)
13074 int add
= (rex
& REX_B
) ? 8 : 0;
13079 intel_operand_size (bytemode
, sizeflag
);
13082 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13084 /* 32/64 bit address mode */
13093 const char **indexes64
= names64
;
13094 const char **indexes32
= names32
;
13104 vindex
= sib
.index
;
13110 case vex_vsib_d_w_dq_mode
:
13111 case vex_vsib_q_w_dq_mode
:
13116 switch (vex
.length
)
13119 indexes64
= indexes32
= names_xmm
;
13122 if (!vex
.w
|| bytemode
== vex_vsib_q_w_dq_mode
)
13123 indexes64
= indexes32
= names_ymm
;
13125 indexes64
= indexes32
= names_xmm
;
13132 haveindex
= vindex
!= 4;
13139 rbase
= base
+ add
;
13147 if (address_mode
== mode_64bit
&& !havesib
)
13153 FETCH_DATA (the_info
, codep
+ 1);
13155 if ((disp
& 0x80) != 0)
13163 /* In 32bit mode, we need index register to tell [offset] from
13164 [eiz*1 + offset]. */
13165 needindex
= (havesib
13168 && address_mode
== mode_32bit
);
13169 havedisp
= (havebase
13171 || (havesib
&& (haveindex
|| scale
!= 0)));
13174 if (modrm
.mod
!= 0 || base
== 5)
13176 if (havedisp
|| riprel
)
13177 print_displacement (scratchbuf
, disp
);
13179 print_operand_value (scratchbuf
, 1, disp
);
13180 oappend (scratchbuf
);
13184 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
13188 if (havebase
|| haveindex
|| riprel
)
13189 used_prefixes
|= PREFIX_ADDR
;
13191 if (havedisp
|| (intel_syntax
&& riprel
))
13193 *obufp
++ = open_char
;
13194 if (intel_syntax
&& riprel
)
13197 oappend (sizeflag
& AFLAG
? "rip" : "eip");
13201 oappend (address_mode
== mode_64bit
&& (sizeflag
& AFLAG
)
13202 ? names64
[rbase
] : names32
[rbase
]);
13205 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
13206 print index to tell base + index from base. */
13210 || (havebase
&& base
!= ESP_REG_NUM
))
13212 if (!intel_syntax
|| havebase
)
13214 *obufp
++ = separator_char
;
13218 oappend (address_mode
== mode_64bit
13219 && (sizeflag
& AFLAG
)
13220 ? indexes64
[vindex
] : indexes32
[vindex
]);
13222 oappend (address_mode
== mode_64bit
13223 && (sizeflag
& AFLAG
)
13224 ? index64
: index32
);
13226 *obufp
++ = scale_char
;
13228 sprintf (scratchbuf
, "%d", 1 << scale
);
13229 oappend (scratchbuf
);
13233 && (disp
|| modrm
.mod
!= 0 || base
== 5))
13235 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
13240 else if (modrm
.mod
!= 1 && disp
!= -disp
)
13244 disp
= - (bfd_signed_vma
) disp
;
13248 print_displacement (scratchbuf
, disp
);
13250 print_operand_value (scratchbuf
, 1, disp
);
13251 oappend (scratchbuf
);
13254 *obufp
++ = close_char
;
13257 else if (intel_syntax
)
13259 if (modrm
.mod
!= 0 || base
== 5)
13261 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13262 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
13266 oappend (names_seg
[ds_reg
- es_reg
]);
13269 print_operand_value (scratchbuf
, 1, disp
);
13270 oappend (scratchbuf
);
13276 /* 16 bit address mode */
13277 used_prefixes
|= prefixes
& PREFIX_ADDR
;
13284 if ((disp
& 0x8000) != 0)
13289 FETCH_DATA (the_info
, codep
+ 1);
13291 if ((disp
& 0x80) != 0)
13296 if ((disp
& 0x8000) != 0)
13302 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
13304 print_displacement (scratchbuf
, disp
);
13305 oappend (scratchbuf
);
13308 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
13310 *obufp
++ = open_char
;
13312 oappend (index16
[modrm
.rm
]);
13314 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
13316 if ((bfd_signed_vma
) disp
>= 0)
13321 else if (modrm
.mod
!= 1)
13325 disp
= - (bfd_signed_vma
) disp
;
13328 print_displacement (scratchbuf
, disp
);
13329 oappend (scratchbuf
);
13332 *obufp
++ = close_char
;
13335 else if (intel_syntax
)
13337 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13338 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
13342 oappend (names_seg
[ds_reg
- es_reg
]);
13345 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
13346 oappend (scratchbuf
);
13352 OP_E (int bytemode
, int sizeflag
)
13354 /* Skip mod/rm byte. */
13358 if (modrm
.mod
== 3)
13359 OP_E_register (bytemode
, sizeflag
);
13361 OP_E_memory (bytemode
, sizeflag
);
13365 OP_G (int bytemode
, int sizeflag
)
13376 oappend (names8rex
[modrm
.reg
+ add
]);
13378 oappend (names8
[modrm
.reg
+ add
]);
13381 oappend (names16
[modrm
.reg
+ add
]);
13384 oappend (names32
[modrm
.reg
+ add
]);
13387 oappend (names64
[modrm
.reg
+ add
]);
13396 oappend (names64
[modrm
.reg
+ add
]);
13399 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
13400 oappend (names32
[modrm
.reg
+ add
]);
13402 oappend (names16
[modrm
.reg
+ add
]);
13403 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13407 if (address_mode
== mode_64bit
)
13408 oappend (names64
[modrm
.reg
+ add
]);
13410 oappend (names32
[modrm
.reg
+ add
]);
13413 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13426 FETCH_DATA (the_info
, codep
+ 8);
13427 a
= *codep
++ & 0xff;
13428 a
|= (*codep
++ & 0xff) << 8;
13429 a
|= (*codep
++ & 0xff) << 16;
13430 a
|= (*codep
++ & 0xff) << 24;
13431 b
= *codep
++ & 0xff;
13432 b
|= (*codep
++ & 0xff) << 8;
13433 b
|= (*codep
++ & 0xff) << 16;
13434 b
|= (*codep
++ & 0xff) << 24;
13435 x
= a
+ ((bfd_vma
) b
<< 32);
13443 static bfd_signed_vma
13446 bfd_signed_vma x
= 0;
13448 FETCH_DATA (the_info
, codep
+ 4);
13449 x
= *codep
++ & (bfd_signed_vma
) 0xff;
13450 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
13451 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
13452 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
13456 static bfd_signed_vma
13459 bfd_signed_vma x
= 0;
13461 FETCH_DATA (the_info
, codep
+ 4);
13462 x
= *codep
++ & (bfd_signed_vma
) 0xff;
13463 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
13464 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
13465 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
13467 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
13477 FETCH_DATA (the_info
, codep
+ 2);
13478 x
= *codep
++ & 0xff;
13479 x
|= (*codep
++ & 0xff) << 8;
13484 set_op (bfd_vma op
, int riprel
)
13486 op_index
[op_ad
] = op_ad
;
13487 if (address_mode
== mode_64bit
)
13489 op_address
[op_ad
] = op
;
13490 op_riprel
[op_ad
] = riprel
;
13494 /* Mask to get a 32-bit address. */
13495 op_address
[op_ad
] = op
& 0xffffffff;
13496 op_riprel
[op_ad
] = riprel
& 0xffffffff;
13501 OP_REG (int code
, int sizeflag
)
13508 case es_reg
: case ss_reg
: case cs_reg
:
13509 case ds_reg
: case fs_reg
: case gs_reg
:
13510 oappend (names_seg
[code
- es_reg
]);
13522 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
13523 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
13524 s
= names16
[code
- ax_reg
+ add
];
13526 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
13527 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
13530 s
= names8rex
[code
- al_reg
+ add
];
13532 s
= names8
[code
- al_reg
];
13534 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
13535 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
13536 if (address_mode
== mode_64bit
13537 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13539 s
= names64
[code
- rAX_reg
+ add
];
13542 code
+= eAX_reg
- rAX_reg
;
13543 /* Fall through. */
13544 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
13545 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
13548 s
= names64
[code
- eAX_reg
+ add
];
13551 if (sizeflag
& DFLAG
)
13552 s
= names32
[code
- eAX_reg
+ add
];
13554 s
= names16
[code
- eAX_reg
+ add
];
13555 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13559 s
= INTERNAL_DISASSEMBLER_ERROR
;
13566 OP_IMREG (int code
, int sizeflag
)
13578 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
13579 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
13580 s
= names16
[code
- ax_reg
];
13582 case es_reg
: case ss_reg
: case cs_reg
:
13583 case ds_reg
: case fs_reg
: case gs_reg
:
13584 s
= names_seg
[code
- es_reg
];
13586 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
13587 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
13590 s
= names8rex
[code
- al_reg
];
13592 s
= names8
[code
- al_reg
];
13594 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
13595 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
13598 s
= names64
[code
- eAX_reg
];
13601 if (sizeflag
& DFLAG
)
13602 s
= names32
[code
- eAX_reg
];
13604 s
= names16
[code
- eAX_reg
];
13605 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13608 case z_mode_ax_reg
:
13609 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13613 if (!(rex
& REX_W
))
13614 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13617 s
= INTERNAL_DISASSEMBLER_ERROR
;
13624 OP_I (int bytemode
, int sizeflag
)
13627 bfd_signed_vma mask
= -1;
13632 FETCH_DATA (the_info
, codep
+ 1);
13637 if (address_mode
== mode_64bit
)
13642 /* Fall through. */
13649 if (sizeflag
& DFLAG
)
13659 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13671 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13676 scratchbuf
[0] = '$';
13677 print_operand_value (scratchbuf
+ 1, 1, op
);
13678 oappend (scratchbuf
+ intel_syntax
);
13679 scratchbuf
[0] = '\0';
13683 OP_I64 (int bytemode
, int sizeflag
)
13686 bfd_signed_vma mask
= -1;
13688 if (address_mode
!= mode_64bit
)
13690 OP_I (bytemode
, sizeflag
);
13697 FETCH_DATA (the_info
, codep
+ 1);
13707 if (sizeflag
& DFLAG
)
13717 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13725 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13730 scratchbuf
[0] = '$';
13731 print_operand_value (scratchbuf
+ 1, 1, op
);
13732 oappend (scratchbuf
+ intel_syntax
);
13733 scratchbuf
[0] = '\0';
13737 OP_sI (int bytemode
, int sizeflag
)
13745 FETCH_DATA (the_info
, codep
+ 1);
13747 if ((op
& 0x80) != 0)
13749 if (bytemode
== b_T_mode
)
13751 if (address_mode
!= mode_64bit
13752 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13754 /* The operand-size prefix is overridden by a REX prefix. */
13755 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
13763 if (!(rex
& REX_W
))
13765 if (sizeflag
& DFLAG
)
13773 /* The operand-size prefix is overridden by a REX prefix. */
13774 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
13780 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13784 scratchbuf
[0] = '$';
13785 print_operand_value (scratchbuf
+ 1, 1, op
);
13786 oappend (scratchbuf
+ intel_syntax
);
13790 OP_J (int bytemode
, int sizeflag
)
13794 bfd_vma segment
= 0;
13799 FETCH_DATA (the_info
, codep
+ 1);
13801 if ((disp
& 0x80) != 0)
13806 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
13811 if ((disp
& 0x8000) != 0)
13813 /* In 16bit mode, address is wrapped around at 64k within
13814 the same segment. Otherwise, a data16 prefix on a jump
13815 instruction means that the pc is masked to 16 bits after
13816 the displacement is added! */
13818 if ((prefixes
& PREFIX_DATA
) == 0)
13819 segment
= ((start_pc
+ codep
- start_codep
)
13820 & ~((bfd_vma
) 0xffff));
13822 if (!(rex
& REX_W
))
13823 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13826 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13829 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
13831 print_operand_value (scratchbuf
, 1, disp
);
13832 oappend (scratchbuf
);
13836 OP_SEG (int bytemode
, int sizeflag
)
13838 if (bytemode
== w_mode
)
13839 oappend (names_seg
[modrm
.reg
]);
13841 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
13845 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
13849 if (sizeflag
& DFLAG
)
13859 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13861 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
13863 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
13864 oappend (scratchbuf
);
13868 OP_OFF (int bytemode
, int sizeflag
)
13872 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
13873 intel_operand_size (bytemode
, sizeflag
);
13876 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13883 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13884 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
13886 oappend (names_seg
[ds_reg
- es_reg
]);
13890 print_operand_value (scratchbuf
, 1, off
);
13891 oappend (scratchbuf
);
13895 OP_OFF64 (int bytemode
, int sizeflag
)
13899 if (address_mode
!= mode_64bit
13900 || (prefixes
& PREFIX_ADDR
))
13902 OP_OFF (bytemode
, sizeflag
);
13906 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
13907 intel_operand_size (bytemode
, sizeflag
);
13914 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13915 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
13917 oappend (names_seg
[ds_reg
- es_reg
]);
13921 print_operand_value (scratchbuf
, 1, off
);
13922 oappend (scratchbuf
);
13926 ptr_reg (int code
, int sizeflag
)
13930 *obufp
++ = open_char
;
13931 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13932 if (address_mode
== mode_64bit
)
13934 if (!(sizeflag
& AFLAG
))
13935 s
= names32
[code
- eAX_reg
];
13937 s
= names64
[code
- eAX_reg
];
13939 else if (sizeflag
& AFLAG
)
13940 s
= names32
[code
- eAX_reg
];
13942 s
= names16
[code
- eAX_reg
];
13944 *obufp
++ = close_char
;
13949 OP_ESreg (int code
, int sizeflag
)
13955 case 0x6d: /* insw/insl */
13956 intel_operand_size (z_mode
, sizeflag
);
13958 case 0xa5: /* movsw/movsl/movsq */
13959 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13960 case 0xab: /* stosw/stosl */
13961 case 0xaf: /* scasw/scasl */
13962 intel_operand_size (v_mode
, sizeflag
);
13965 intel_operand_size (b_mode
, sizeflag
);
13968 oappend ("%es:" + intel_syntax
);
13969 ptr_reg (code
, sizeflag
);
13973 OP_DSreg (int code
, int sizeflag
)
13979 case 0x6f: /* outsw/outsl */
13980 intel_operand_size (z_mode
, sizeflag
);
13982 case 0xa5: /* movsw/movsl/movsq */
13983 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13984 case 0xad: /* lodsw/lodsl/lodsq */
13985 intel_operand_size (v_mode
, sizeflag
);
13988 intel_operand_size (b_mode
, sizeflag
);
13997 | PREFIX_GS
)) == 0)
13998 prefixes
|= PREFIX_DS
;
14000 ptr_reg (code
, sizeflag
);
14004 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14012 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
14014 all_prefixes
[last_lock_prefix
] = 0;
14015 used_prefixes
|= PREFIX_LOCK
;
14020 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
14021 oappend (scratchbuf
+ intel_syntax
);
14025 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14034 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
14036 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
14037 oappend (scratchbuf
);
14041 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14043 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
14044 oappend (scratchbuf
+ intel_syntax
);
14048 OP_R (int bytemode
, int sizeflag
)
14050 if (modrm
.mod
== 3)
14051 OP_E (bytemode
, sizeflag
);
14057 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14059 int reg
= modrm
.reg
;
14060 const char **names
;
14062 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14063 if (prefixes
& PREFIX_DATA
)
14072 oappend (names
[reg
]);
14076 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14078 int reg
= modrm
.reg
;
14079 const char **names
;
14085 && bytemode
!= xmm_mode
14086 && bytemode
!= scalar_mode
)
14088 switch (vex
.length
)
14094 if (vex
.w
|| bytemode
!= vex_vsib_q_w_dq_mode
)
14105 oappend (names
[reg
]);
14109 OP_EM (int bytemode
, int sizeflag
)
14112 const char **names
;
14114 if (modrm
.mod
!= 3)
14117 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
14119 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
14120 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14122 OP_E (bytemode
, sizeflag
);
14126 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
14129 /* Skip mod/rm byte. */
14132 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14134 if (prefixes
& PREFIX_DATA
)
14143 oappend (names
[reg
]);
14146 /* cvt* are the only instructions in sse2 which have
14147 both SSE and MMX operands and also have 0x66 prefix
14148 in their opcode. 0x66 was originally used to differentiate
14149 between SSE and MMX instruction(operands). So we have to handle the
14150 cvt* separately using OP_EMC and OP_MXC */
14152 OP_EMC (int bytemode
, int sizeflag
)
14154 if (modrm
.mod
!= 3)
14156 if (intel_syntax
&& bytemode
== v_mode
)
14158 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
14159 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14161 OP_E (bytemode
, sizeflag
);
14165 /* Skip mod/rm byte. */
14168 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14169 oappend (names_mm
[modrm
.rm
]);
14173 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14175 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14176 oappend (names_mm
[modrm
.reg
]);
14180 OP_EX (int bytemode
, int sizeflag
)
14183 const char **names
;
14185 /* Skip mod/rm byte. */
14189 if (modrm
.mod
!= 3)
14191 OP_E_memory (bytemode
, sizeflag
);
14200 if ((sizeflag
& SUFFIX_ALWAYS
)
14201 && (bytemode
== x_swap_mode
14202 || bytemode
== d_swap_mode
14203 || bytemode
== d_scalar_swap_mode
14204 || bytemode
== q_swap_mode
14205 || bytemode
== q_scalar_swap_mode
))
14209 && bytemode
!= xmm_mode
14210 && bytemode
!= xmmdw_mode
14211 && bytemode
!= xmmqd_mode
14212 && bytemode
!= xmm_mb_mode
14213 && bytemode
!= xmm_mw_mode
14214 && bytemode
!= xmm_md_mode
14215 && bytemode
!= xmm_mq_mode
14216 && bytemode
!= xmmq_mode
14217 && bytemode
!= d_scalar_mode
14218 && bytemode
!= d_scalar_swap_mode
14219 && bytemode
!= q_scalar_mode
14220 && bytemode
!= q_scalar_swap_mode
14221 && bytemode
!= vex_scalar_w_dq_mode
)
14223 switch (vex
.length
)
14237 oappend (names
[reg
]);
14241 OP_MS (int bytemode
, int sizeflag
)
14243 if (modrm
.mod
== 3)
14244 OP_EM (bytemode
, sizeflag
);
14250 OP_XS (int bytemode
, int sizeflag
)
14252 if (modrm
.mod
== 3)
14253 OP_EX (bytemode
, sizeflag
);
14259 OP_M (int bytemode
, int sizeflag
)
14261 if (modrm
.mod
== 3)
14262 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14265 OP_E (bytemode
, sizeflag
);
14269 OP_0f07 (int bytemode
, int sizeflag
)
14271 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
14274 OP_E (bytemode
, sizeflag
);
14277 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14278 32bit mode and "xchg %rax,%rax" in 64bit mode. */
14281 NOP_Fixup1 (int bytemode
, int sizeflag
)
14283 if ((prefixes
& PREFIX_DATA
) != 0
14286 && address_mode
== mode_64bit
))
14287 OP_REG (bytemode
, sizeflag
);
14289 strcpy (obuf
, "nop");
14293 NOP_Fixup2 (int bytemode
, int sizeflag
)
14295 if ((prefixes
& PREFIX_DATA
) != 0
14298 && address_mode
== mode_64bit
))
14299 OP_IMREG (bytemode
, sizeflag
);
14302 static const char *const Suffix3DNow
[] = {
14303 /* 00 */ NULL
, NULL
, NULL
, NULL
,
14304 /* 04 */ NULL
, NULL
, NULL
, NULL
,
14305 /* 08 */ NULL
, NULL
, NULL
, NULL
,
14306 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
14307 /* 10 */ NULL
, NULL
, NULL
, NULL
,
14308 /* 14 */ NULL
, NULL
, NULL
, NULL
,
14309 /* 18 */ NULL
, NULL
, NULL
, NULL
,
14310 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
14311 /* 20 */ NULL
, NULL
, NULL
, NULL
,
14312 /* 24 */ NULL
, NULL
, NULL
, NULL
,
14313 /* 28 */ NULL
, NULL
, NULL
, NULL
,
14314 /* 2C */ NULL
, NULL
, NULL
, NULL
,
14315 /* 30 */ NULL
, NULL
, NULL
, NULL
,
14316 /* 34 */ NULL
, NULL
, NULL
, NULL
,
14317 /* 38 */ NULL
, NULL
, NULL
, NULL
,
14318 /* 3C */ NULL
, NULL
, NULL
, NULL
,
14319 /* 40 */ NULL
, NULL
, NULL
, NULL
,
14320 /* 44 */ NULL
, NULL
, NULL
, NULL
,
14321 /* 48 */ NULL
, NULL
, NULL
, NULL
,
14322 /* 4C */ NULL
, NULL
, NULL
, NULL
,
14323 /* 50 */ NULL
, NULL
, NULL
, NULL
,
14324 /* 54 */ NULL
, NULL
, NULL
, NULL
,
14325 /* 58 */ NULL
, NULL
, NULL
, NULL
,
14326 /* 5C */ NULL
, NULL
, NULL
, NULL
,
14327 /* 60 */ NULL
, NULL
, NULL
, NULL
,
14328 /* 64 */ NULL
, NULL
, NULL
, NULL
,
14329 /* 68 */ NULL
, NULL
, NULL
, NULL
,
14330 /* 6C */ NULL
, NULL
, NULL
, NULL
,
14331 /* 70 */ NULL
, NULL
, NULL
, NULL
,
14332 /* 74 */ NULL
, NULL
, NULL
, NULL
,
14333 /* 78 */ NULL
, NULL
, NULL
, NULL
,
14334 /* 7C */ NULL
, NULL
, NULL
, NULL
,
14335 /* 80 */ NULL
, NULL
, NULL
, NULL
,
14336 /* 84 */ NULL
, NULL
, NULL
, NULL
,
14337 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
14338 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
14339 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
14340 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
14341 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
14342 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
14343 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
14344 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
14345 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
14346 /* AC */ NULL
, NULL
, "pfacc", NULL
,
14347 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
14348 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
14349 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
14350 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
14351 /* C0 */ NULL
, NULL
, NULL
, NULL
,
14352 /* C4 */ NULL
, NULL
, NULL
, NULL
,
14353 /* C8 */ NULL
, NULL
, NULL
, NULL
,
14354 /* CC */ NULL
, NULL
, NULL
, NULL
,
14355 /* D0 */ NULL
, NULL
, NULL
, NULL
,
14356 /* D4 */ NULL
, NULL
, NULL
, NULL
,
14357 /* D8 */ NULL
, NULL
, NULL
, NULL
,
14358 /* DC */ NULL
, NULL
, NULL
, NULL
,
14359 /* E0 */ NULL
, NULL
, NULL
, NULL
,
14360 /* E4 */ NULL
, NULL
, NULL
, NULL
,
14361 /* E8 */ NULL
, NULL
, NULL
, NULL
,
14362 /* EC */ NULL
, NULL
, NULL
, NULL
,
14363 /* F0 */ NULL
, NULL
, NULL
, NULL
,
14364 /* F4 */ NULL
, NULL
, NULL
, NULL
,
14365 /* F8 */ NULL
, NULL
, NULL
, NULL
,
14366 /* FC */ NULL
, NULL
, NULL
, NULL
,
14370 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14372 const char *mnemonic
;
14374 FETCH_DATA (the_info
, codep
+ 1);
14375 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14376 place where an 8-bit immediate would normally go. ie. the last
14377 byte of the instruction. */
14378 obufp
= mnemonicendp
;
14379 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
14381 oappend (mnemonic
);
14384 /* Since a variable sized modrm/sib chunk is between the start
14385 of the opcode (0x0f0f) and the opcode suffix, we need to do
14386 all the modrm processing first, and don't know until now that
14387 we have a bad opcode. This necessitates some cleaning up. */
14388 op_out
[0][0] = '\0';
14389 op_out
[1][0] = '\0';
14392 mnemonicendp
= obufp
;
14395 static struct op simd_cmp_op
[] =
14397 { STRING_COMMA_LEN ("eq") },
14398 { STRING_COMMA_LEN ("lt") },
14399 { STRING_COMMA_LEN ("le") },
14400 { STRING_COMMA_LEN ("unord") },
14401 { STRING_COMMA_LEN ("neq") },
14402 { STRING_COMMA_LEN ("nlt") },
14403 { STRING_COMMA_LEN ("nle") },
14404 { STRING_COMMA_LEN ("ord") }
14408 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14410 unsigned int cmp_type
;
14412 FETCH_DATA (the_info
, codep
+ 1);
14413 cmp_type
= *codep
++ & 0xff;
14414 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
14417 char *p
= mnemonicendp
- 2;
14421 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
14422 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
14426 /* We have a reserved extension byte. Output it directly. */
14427 scratchbuf
[0] = '$';
14428 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
14429 oappend (scratchbuf
+ intel_syntax
);
14430 scratchbuf
[0] = '\0';
14435 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
14436 int sizeflag ATTRIBUTE_UNUSED
)
14438 /* mwait %eax,%ecx */
14441 const char **names
= (address_mode
== mode_64bit
14442 ? names64
: names32
);
14443 strcpy (op_out
[0], names
[0]);
14444 strcpy (op_out
[1], names
[1]);
14445 two_source_ops
= 1;
14447 /* Skip mod/rm byte. */
14453 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
14454 int sizeflag ATTRIBUTE_UNUSED
)
14456 /* monitor %eax,%ecx,%edx" */
14459 const char **op1_names
;
14460 const char **names
= (address_mode
== mode_64bit
14461 ? names64
: names32
);
14463 if (!(prefixes
& PREFIX_ADDR
))
14464 op1_names
= (address_mode
== mode_16bit
14465 ? names16
: names
);
14468 /* Remove "addr16/addr32". */
14469 all_prefixes
[last_addr_prefix
] = 0;
14470 op1_names
= (address_mode
!= mode_32bit
14471 ? names32
: names16
);
14472 used_prefixes
|= PREFIX_ADDR
;
14474 strcpy (op_out
[0], op1_names
[0]);
14475 strcpy (op_out
[1], names
[1]);
14476 strcpy (op_out
[2], names
[2]);
14477 two_source_ops
= 1;
14479 /* Skip mod/rm byte. */
14487 /* Throw away prefixes and 1st. opcode byte. */
14488 codep
= insn_codep
+ 1;
14493 REP_Fixup (int bytemode
, int sizeflag
)
14495 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14497 if (prefixes
& PREFIX_REPZ
)
14498 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
14505 OP_IMREG (bytemode
, sizeflag
);
14508 OP_ESreg (bytemode
, sizeflag
);
14511 OP_DSreg (bytemode
, sizeflag
);
14519 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
14520 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
14524 HLE_Fixup1 (int bytemode
, int sizeflag
)
14527 && (prefixes
& PREFIX_LOCK
) != 0)
14529 if (prefixes
& PREFIX_REPZ
)
14530 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
14531 if (prefixes
& PREFIX_REPNZ
)
14532 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
14535 OP_E (bytemode
, sizeflag
);
14538 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
14539 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
14543 HLE_Fixup2 (int bytemode
, int sizeflag
)
14545 if (modrm
.mod
!= 3)
14547 if (prefixes
& PREFIX_REPZ
)
14548 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
14549 if (prefixes
& PREFIX_REPNZ
)
14550 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
14553 OP_E (bytemode
, sizeflag
);
14556 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
14557 "xrelease" for memory operand. No check for LOCK prefix. */
14560 HLE_Fixup3 (int bytemode
, int sizeflag
)
14563 && last_repz_prefix
> last_repnz_prefix
14564 && (prefixes
& PREFIX_REPZ
) != 0)
14565 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
14567 OP_E (bytemode
, sizeflag
);
14571 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
14576 /* Change cmpxchg8b to cmpxchg16b. */
14577 char *p
= mnemonicendp
- 2;
14578 mnemonicendp
= stpcpy (p
, "16b");
14581 else if ((prefixes
& PREFIX_LOCK
) != 0)
14583 if (prefixes
& PREFIX_REPZ
)
14584 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
14585 if (prefixes
& PREFIX_REPNZ
)
14586 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
14589 OP_M (bytemode
, sizeflag
);
14593 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
14595 const char **names
;
14599 switch (vex
.length
)
14613 oappend (names
[reg
]);
14617 CRC32_Fixup (int bytemode
, int sizeflag
)
14619 /* Add proper suffix to "crc32". */
14620 char *p
= mnemonicendp
;
14639 if (sizeflag
& DFLAG
)
14643 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14647 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14654 if (modrm
.mod
== 3)
14658 /* Skip mod/rm byte. */
14663 add
= (rex
& REX_B
) ? 8 : 0;
14664 if (bytemode
== b_mode
)
14668 oappend (names8rex
[modrm
.rm
+ add
]);
14670 oappend (names8
[modrm
.rm
+ add
]);
14676 oappend (names64
[modrm
.rm
+ add
]);
14677 else if ((prefixes
& PREFIX_DATA
))
14678 oappend (names16
[modrm
.rm
+ add
]);
14680 oappend (names32
[modrm
.rm
+ add
]);
14684 OP_E (bytemode
, sizeflag
);
14688 FXSAVE_Fixup (int bytemode
, int sizeflag
)
14690 /* Add proper suffix to "fxsave" and "fxrstor". */
14694 char *p
= mnemonicendp
;
14700 OP_M (bytemode
, sizeflag
);
14703 /* Display the destination register operand for instructions with
14707 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14710 const char **names
;
14718 reg
= vex
.register_specifier
;
14719 if (bytemode
== vex_scalar_mode
)
14721 oappend (names_xmm
[reg
]);
14725 switch (vex
.length
)
14732 case vex_vsib_q_w_dq_mode
:
14753 case vex_vsib_q_w_dq_mode
:
14754 names
= vex
.w
? names_ymm
: names_xmm
;
14765 oappend (names
[reg
]);
14768 /* Get the VEX immediate byte without moving codep. */
14770 static unsigned char
14771 get_vex_imm8 (int sizeflag
, int opnum
)
14773 int bytes_before_imm
= 0;
14775 if (modrm
.mod
!= 3)
14777 /* There are SIB/displacement bytes. */
14778 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14780 /* 32/64 bit address mode */
14781 int base
= modrm
.rm
;
14783 /* Check SIB byte. */
14786 FETCH_DATA (the_info
, codep
+ 1);
14788 /* When decoding the third source, don't increase
14789 bytes_before_imm as this has already been incremented
14790 by one in OP_E_memory while decoding the second
14793 bytes_before_imm
++;
14796 /* Don't increase bytes_before_imm when decoding the third source,
14797 it has already been incremented by OP_E_memory while decoding
14798 the second source operand. */
14804 /* When modrm.rm == 5 or modrm.rm == 4 and base in
14805 SIB == 5, there is a 4 byte displacement. */
14807 /* No displacement. */
14810 /* 4 byte displacement. */
14811 bytes_before_imm
+= 4;
14814 /* 1 byte displacement. */
14815 bytes_before_imm
++;
14822 /* 16 bit address mode */
14823 /* Don't increase bytes_before_imm when decoding the third source,
14824 it has already been incremented by OP_E_memory while decoding
14825 the second source operand. */
14831 /* When modrm.rm == 6, there is a 2 byte displacement. */
14833 /* No displacement. */
14836 /* 2 byte displacement. */
14837 bytes_before_imm
+= 2;
14840 /* 1 byte displacement: when decoding the third source,
14841 don't increase bytes_before_imm as this has already
14842 been incremented by one in OP_E_memory while decoding
14843 the second source operand. */
14845 bytes_before_imm
++;
14853 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
14854 return codep
[bytes_before_imm
];
14858 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
14860 const char **names
;
14862 if (reg
== -1 && modrm
.mod
!= 3)
14864 OP_E_memory (bytemode
, sizeflag
);
14876 else if (reg
> 7 && address_mode
!= mode_64bit
)
14880 switch (vex
.length
)
14891 oappend (names
[reg
]);
14895 OP_EX_VexImmW (int bytemode
, int sizeflag
)
14898 static unsigned char vex_imm8
;
14900 if (vex_w_done
== 0)
14904 /* Skip mod/rm byte. */
14908 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
14911 reg
= vex_imm8
>> 4;
14913 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14915 else if (vex_w_done
== 1)
14920 reg
= vex_imm8
>> 4;
14922 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14926 /* Output the imm8 directly. */
14927 scratchbuf
[0] = '$';
14928 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
14929 oappend (scratchbuf
+ intel_syntax
);
14930 scratchbuf
[0] = '\0';
14936 OP_Vex_2src (int bytemode
, int sizeflag
)
14938 if (modrm
.mod
== 3)
14940 int reg
= modrm
.rm
;
14944 oappend (names_xmm
[reg
]);
14949 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
14951 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
14952 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14954 OP_E (bytemode
, sizeflag
);
14959 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
14961 if (modrm
.mod
== 3)
14963 /* Skip mod/rm byte. */
14969 oappend (names_xmm
[vex
.register_specifier
]);
14971 OP_Vex_2src (bytemode
, sizeflag
);
14975 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
14978 OP_Vex_2src (bytemode
, sizeflag
);
14980 oappend (names_xmm
[vex
.register_specifier
]);
14984 OP_EX_VexW (int bytemode
, int sizeflag
)
14992 /* Skip mod/rm byte. */
14997 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
15002 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
15005 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
15009 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15010 int sizeflag ATTRIBUTE_UNUSED
)
15012 /* Skip the immediate byte and check for invalid bits. */
15013 FETCH_DATA (the_info
, codep
+ 1);
15014 if (*codep
++ & 0xf)
15019 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15022 const char **names
;
15024 FETCH_DATA (the_info
, codep
+ 1);
15027 if (bytemode
!= x_mode
)
15034 if (reg
> 7 && address_mode
!= mode_64bit
)
15037 switch (vex
.length
)
15048 oappend (names
[reg
]);
15052 OP_XMM_VexW (int bytemode
, int sizeflag
)
15054 /* Turn off the REX.W bit since it is used for swapping operands
15057 OP_XMM (bytemode
, sizeflag
);
15061 OP_EX_Vex (int bytemode
, int sizeflag
)
15063 if (modrm
.mod
!= 3)
15065 if (vex
.register_specifier
!= 0)
15069 OP_EX (bytemode
, sizeflag
);
15073 OP_XMM_Vex (int bytemode
, int sizeflag
)
15075 if (modrm
.mod
!= 3)
15077 if (vex
.register_specifier
!= 0)
15081 OP_XMM (bytemode
, sizeflag
);
15085 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15087 switch (vex
.length
)
15090 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
15093 mnemonicendp
= stpcpy (obuf
, "vzeroall");
15100 static struct op vex_cmp_op
[] =
15102 { STRING_COMMA_LEN ("eq") },
15103 { STRING_COMMA_LEN ("lt") },
15104 { STRING_COMMA_LEN ("le") },
15105 { STRING_COMMA_LEN ("unord") },
15106 { STRING_COMMA_LEN ("neq") },
15107 { STRING_COMMA_LEN ("nlt") },
15108 { STRING_COMMA_LEN ("nle") },
15109 { STRING_COMMA_LEN ("ord") },
15110 { STRING_COMMA_LEN ("eq_uq") },
15111 { STRING_COMMA_LEN ("nge") },
15112 { STRING_COMMA_LEN ("ngt") },
15113 { STRING_COMMA_LEN ("false") },
15114 { STRING_COMMA_LEN ("neq_oq") },
15115 { STRING_COMMA_LEN ("ge") },
15116 { STRING_COMMA_LEN ("gt") },
15117 { STRING_COMMA_LEN ("true") },
15118 { STRING_COMMA_LEN ("eq_os") },
15119 { STRING_COMMA_LEN ("lt_oq") },
15120 { STRING_COMMA_LEN ("le_oq") },
15121 { STRING_COMMA_LEN ("unord_s") },
15122 { STRING_COMMA_LEN ("neq_us") },
15123 { STRING_COMMA_LEN ("nlt_uq") },
15124 { STRING_COMMA_LEN ("nle_uq") },
15125 { STRING_COMMA_LEN ("ord_s") },
15126 { STRING_COMMA_LEN ("eq_us") },
15127 { STRING_COMMA_LEN ("nge_uq") },
15128 { STRING_COMMA_LEN ("ngt_uq") },
15129 { STRING_COMMA_LEN ("false_os") },
15130 { STRING_COMMA_LEN ("neq_os") },
15131 { STRING_COMMA_LEN ("ge_oq") },
15132 { STRING_COMMA_LEN ("gt_oq") },
15133 { STRING_COMMA_LEN ("true_us") },
15137 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15139 unsigned int cmp_type
;
15141 FETCH_DATA (the_info
, codep
+ 1);
15142 cmp_type
= *codep
++ & 0xff;
15143 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
15146 char *p
= mnemonicendp
- 2;
15150 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
15151 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
15155 /* We have a reserved extension byte. Output it directly. */
15156 scratchbuf
[0] = '$';
15157 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15158 oappend (scratchbuf
+ intel_syntax
);
15159 scratchbuf
[0] = '\0';
15163 static const struct op pclmul_op
[] =
15165 { STRING_COMMA_LEN ("lql") },
15166 { STRING_COMMA_LEN ("hql") },
15167 { STRING_COMMA_LEN ("lqh") },
15168 { STRING_COMMA_LEN ("hqh") }
15172 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15173 int sizeflag ATTRIBUTE_UNUSED
)
15175 unsigned int pclmul_type
;
15177 FETCH_DATA (the_info
, codep
+ 1);
15178 pclmul_type
= *codep
++ & 0xff;
15179 switch (pclmul_type
)
15190 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
15193 char *p
= mnemonicendp
- 3;
15198 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
15199 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
15203 /* We have a reserved extension byte. Output it directly. */
15204 scratchbuf
[0] = '$';
15205 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
15206 oappend (scratchbuf
+ intel_syntax
);
15207 scratchbuf
[0] = '\0';
15212 MOVBE_Fixup (int bytemode
, int sizeflag
)
15214 /* Add proper suffix to "movbe". */
15215 char *p
= mnemonicendp
;
15224 if (sizeflag
& SUFFIX_ALWAYS
)
15230 if (sizeflag
& DFLAG
)
15234 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15239 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15246 OP_M (bytemode
, sizeflag
);
15250 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15253 const char **names
;
15255 /* Skip mod/rm byte. */
15269 oappend (names
[reg
]);
15273 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15275 const char **names
;
15282 oappend (names
[vex
.register_specifier
]);