1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte
*max_fetched
;
134 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
137 OPCODES_SIGJMP_BUF bailout
;
147 enum address_mode address_mode
;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored
;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes
;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
202 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
203 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
205 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
206 status
= (*info
->read_memory_func
) (start
,
208 addr
- priv
->max_fetched
,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv
->max_fetched
== priv
->the_buffer
)
219 (*info
->memory_error_func
) (status
, start
, info
);
220 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
223 priv
->max_fetched
= addr
;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Ev_bnd { OP_E, v_bnd_mode }
253 #define EvS { OP_E, v_swap_mode }
254 #define Ed { OP_E, d_mode }
255 #define Edq { OP_E, dq_mode }
256 #define Edqw { OP_E, dqw_mode }
257 #define Edqb { OP_E, dqb_mode }
258 #define Edb { OP_E, db_mode }
259 #define Edw { OP_E, dw_mode }
260 #define Edqd { OP_E, dqd_mode }
261 #define Eq { OP_E, q_mode }
262 #define indirEv { OP_indirE, indir_v_mode }
263 #define indirEp { OP_indirE, f_mode }
264 #define stackEv { OP_E, stack_v_mode }
265 #define Em { OP_E, m_mode }
266 #define Ew { OP_E, w_mode }
267 #define M { OP_M, 0 } /* lea, lgdt, etc. */
268 #define Ma { OP_M, a_mode }
269 #define Mb { OP_M, b_mode }
270 #define Md { OP_M, d_mode }
271 #define Mo { OP_M, o_mode }
272 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
273 #define Mq { OP_M, q_mode }
274 #define Mx { OP_M, x_mode }
275 #define Mxmm { OP_M, xmm_mode }
276 #define Gb { OP_G, b_mode }
277 #define Gbnd { OP_G, bnd_mode }
278 #define Gv { OP_G, v_mode }
279 #define Gd { OP_G, d_mode }
280 #define Gdq { OP_G, dq_mode }
281 #define Gm { OP_G, m_mode }
282 #define Gw { OP_G, w_mode }
283 #define Rd { OP_R, d_mode }
284 #define Rdq { OP_R, dq_mode }
285 #define Rm { OP_R, m_mode }
286 #define Ib { OP_I, b_mode }
287 #define sIb { OP_sI, b_mode } /* sign extened byte */
288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
289 #define Iv { OP_I, v_mode }
290 #define sIv { OP_sI, v_mode }
291 #define Iq { OP_I, q_mode }
292 #define Iv64 { OP_I64, v_mode }
293 #define Iw { OP_I, w_mode }
294 #define I1 { OP_I, const_1_mode }
295 #define Jb { OP_J, b_mode }
296 #define Jv { OP_J, v_mode }
297 #define Cm { OP_C, m_mode }
298 #define Dm { OP_D, m_mode }
299 #define Td { OP_T, d_mode }
300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
302 #define RMeAX { OP_REG, eAX_reg }
303 #define RMeBX { OP_REG, eBX_reg }
304 #define RMeCX { OP_REG, eCX_reg }
305 #define RMeDX { OP_REG, eDX_reg }
306 #define RMeSP { OP_REG, eSP_reg }
307 #define RMeBP { OP_REG, eBP_reg }
308 #define RMeSI { OP_REG, eSI_reg }
309 #define RMeDI { OP_REG, eDI_reg }
310 #define RMrAX { OP_REG, rAX_reg }
311 #define RMrBX { OP_REG, rBX_reg }
312 #define RMrCX { OP_REG, rCX_reg }
313 #define RMrDX { OP_REG, rDX_reg }
314 #define RMrSP { OP_REG, rSP_reg }
315 #define RMrBP { OP_REG, rBP_reg }
316 #define RMrSI { OP_REG, rSI_reg }
317 #define RMrDI { OP_REG, rDI_reg }
318 #define RMAL { OP_REG, al_reg }
319 #define RMCL { OP_REG, cl_reg }
320 #define RMDL { OP_REG, dl_reg }
321 #define RMBL { OP_REG, bl_reg }
322 #define RMAH { OP_REG, ah_reg }
323 #define RMCH { OP_REG, ch_reg }
324 #define RMDH { OP_REG, dh_reg }
325 #define RMBH { OP_REG, bh_reg }
326 #define RMAX { OP_REG, ax_reg }
327 #define RMDX { OP_REG, dx_reg }
329 #define eAX { OP_IMREG, eAX_reg }
330 #define eBX { OP_IMREG, eBX_reg }
331 #define eCX { OP_IMREG, eCX_reg }
332 #define eDX { OP_IMREG, eDX_reg }
333 #define eSP { OP_IMREG, eSP_reg }
334 #define eBP { OP_IMREG, eBP_reg }
335 #define eSI { OP_IMREG, eSI_reg }
336 #define eDI { OP_IMREG, eDI_reg }
337 #define AL { OP_IMREG, al_reg }
338 #define CL { OP_IMREG, cl_reg }
339 #define DL { OP_IMREG, dl_reg }
340 #define BL { OP_IMREG, bl_reg }
341 #define AH { OP_IMREG, ah_reg }
342 #define CH { OP_IMREG, ch_reg }
343 #define DH { OP_IMREG, dh_reg }
344 #define BH { OP_IMREG, bh_reg }
345 #define AX { OP_IMREG, ax_reg }
346 #define DX { OP_IMREG, dx_reg }
347 #define zAX { OP_IMREG, z_mode_ax_reg }
348 #define indirDX { OP_IMREG, indir_dx_reg }
350 #define Sw { OP_SEG, w_mode }
351 #define Sv { OP_SEG, v_mode }
352 #define Ap { OP_DIR, 0 }
353 #define Ob { OP_OFF64, b_mode }
354 #define Ov { OP_OFF64, v_mode }
355 #define Xb { OP_DSreg, eSI_reg }
356 #define Xv { OP_DSreg, eSI_reg }
357 #define Xz { OP_DSreg, eSI_reg }
358 #define Yb { OP_ESreg, eDI_reg }
359 #define Yv { OP_ESreg, eDI_reg }
360 #define DSBX { OP_DSreg, eBX_reg }
362 #define es { OP_REG, es_reg }
363 #define ss { OP_REG, ss_reg }
364 #define cs { OP_REG, cs_reg }
365 #define ds { OP_REG, ds_reg }
366 #define fs { OP_REG, fs_reg }
367 #define gs { OP_REG, gs_reg }
369 #define MX { OP_MMX, 0 }
370 #define XM { OP_XMM, 0 }
371 #define XMScalar { OP_XMM, scalar_mode }
372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
373 #define XMM { OP_XMM, xmm_mode }
374 #define XMxmmq { OP_XMM, xmmq_mode }
375 #define EM { OP_EM, v_mode }
376 #define EMS { OP_EM, v_swap_mode }
377 #define EMd { OP_EM, d_mode }
378 #define EMx { OP_EM, x_mode }
379 #define EXbScalar { OP_EX, b_scalar_mode }
380 #define EXw { OP_EX, w_mode }
381 #define EXwScalar { OP_EX, w_scalar_mode }
382 #define EXd { OP_EX, d_mode }
383 #define EXdScalar { OP_EX, d_scalar_mode }
384 #define EXdS { OP_EX, d_swap_mode }
385 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
386 #define EXq { OP_EX, q_mode }
387 #define EXqScalar { OP_EX, q_scalar_mode }
388 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
389 #define EXqS { OP_EX, q_swap_mode }
390 #define EXx { OP_EX, x_mode }
391 #define EXxS { OP_EX, x_swap_mode }
392 #define EXxmm { OP_EX, xmm_mode }
393 #define EXymm { OP_EX, ymm_mode }
394 #define EXxmmq { OP_EX, xmmq_mode }
395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
398 #define EXxmm_md { OP_EX, xmm_md_mode }
399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
400 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
401 #define EXxmmdw { OP_EX, xmmdw_mode }
402 #define EXxmmqd { OP_EX, xmmqd_mode }
403 #define EXymmq { OP_EX, ymmq_mode }
404 #define EXVexWdq { OP_EX, vex_w_dq_mode }
405 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
406 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
407 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
408 #define MS { OP_MS, v_mode }
409 #define XS { OP_XS, v_mode }
410 #define EMCq { OP_EMC, q_mode }
411 #define MXC { OP_MXC, 0 }
412 #define OPSUF { OP_3DNowSuffix, 0 }
413 #define CMP { CMP_Fixup, 0 }
414 #define XMM0 { XMM_Fixup, 0 }
415 #define FXSAVE { FXSAVE_Fixup, 0 }
416 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
417 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
419 #define Vex { OP_VEX, vex_mode }
420 #define VexScalar { OP_VEX, vex_scalar_mode }
421 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
422 #define Vex128 { OP_VEX, vex128_mode }
423 #define Vex256 { OP_VEX, vex256_mode }
424 #define VexGdq { OP_VEX, dq_mode }
425 #define VexI4 { VEXI4_Fixup, 0}
426 #define EXdVex { OP_EX_Vex, d_mode }
427 #define EXdVexS { OP_EX_Vex, d_swap_mode }
428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
429 #define EXqVex { OP_EX_Vex, q_mode }
430 #define EXqVexS { OP_EX_Vex, q_swap_mode }
431 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
432 #define EXVexW { OP_EX_VexW, x_mode }
433 #define EXdVexW { OP_EX_VexW, d_mode }
434 #define EXqVexW { OP_EX_VexW, q_mode }
435 #define EXVexImmW { OP_EX_VexImmW, x_mode }
436 #define XMVex { OP_XMM_Vex, 0 }
437 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
438 #define XMVexW { OP_XMM_VexW, 0 }
439 #define XMVexI4 { OP_REG_VexI4, x_mode }
440 #define PCLMUL { PCLMUL_Fixup, 0 }
441 #define VZERO { VZERO_Fixup, 0 }
442 #define VCMP { VCMP_Fixup, 0 }
443 #define VPCMP { VPCMP_Fixup, 0 }
445 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
446 #define EXxEVexS { OP_Rounding, evex_sae_mode }
448 #define XMask { OP_Mask, mask_mode }
449 #define MaskG { OP_G, mask_mode }
450 #define MaskE { OP_E, mask_mode }
451 #define MaskBDE { OP_E, mask_bd_mode }
452 #define MaskR { OP_R, mask_mode }
453 #define MaskVex { OP_VEX, mask_mode }
455 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
456 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
457 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
458 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
460 /* Used handle "rep" prefix for string instructions. */
461 #define Xbr { REP_Fixup, eSI_reg }
462 #define Xvr { REP_Fixup, eSI_reg }
463 #define Ybr { REP_Fixup, eDI_reg }
464 #define Yvr { REP_Fixup, eDI_reg }
465 #define Yzr { REP_Fixup, eDI_reg }
466 #define indirDXr { REP_Fixup, indir_dx_reg }
467 #define ALr { REP_Fixup, al_reg }
468 #define eAXr { REP_Fixup, eAX_reg }
470 /* Used handle HLE prefix for lockable instructions. */
471 #define Ebh1 { HLE_Fixup1, b_mode }
472 #define Evh1 { HLE_Fixup1, v_mode }
473 #define Ebh2 { HLE_Fixup2, b_mode }
474 #define Evh2 { HLE_Fixup2, v_mode }
475 #define Ebh3 { HLE_Fixup3, b_mode }
476 #define Evh3 { HLE_Fixup3, v_mode }
478 #define BND { BND_Fixup, 0 }
479 #define NOTRACK { NOTRACK_Fixup, 0 }
481 #define cond_jump_flag { NULL, cond_jump_mode }
482 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
484 /* bits in sizeflag */
485 #define SUFFIX_ALWAYS 4
493 /* byte operand with operand swapped */
495 /* byte operand, sign extend like 'T' suffix */
497 /* operand size depends on prefixes */
499 /* operand size depends on prefixes with operand swapped */
503 /* double word operand */
505 /* double word operand with operand swapped */
507 /* quad word operand */
509 /* quad word operand with operand swapped */
511 /* ten-byte operand */
513 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
514 broadcast enabled. */
516 /* Similar to x_mode, but with different EVEX mem shifts. */
518 /* Similar to x_mode, but with disabled broadcast. */
520 /* Similar to x_mode, but with operands swapped and disabled broadcast
523 /* 16-byte XMM operand */
525 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
526 memory operand (depending on vector length). Broadcast isn't
529 /* Same as xmmq_mode, but broadcast is allowed. */
530 evex_half_bcst_xmmq_mode
,
531 /* XMM register or byte memory operand */
533 /* XMM register or word memory operand */
535 /* XMM register or double word memory operand */
537 /* XMM register or quad word memory operand */
539 /* XMM register or double/quad word memory operand, depending on
542 /* 16-byte XMM, word, double word or quad word operand. */
544 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
546 /* 32-byte YMM operand */
548 /* quad word, ymmword or zmmword memory operand. */
550 /* 32-byte YMM or 16-byte word operand */
552 /* d_mode in 32bit, q_mode in 64bit mode. */
554 /* pair of v_mode operands */
559 /* operand size depends on REX prefixes. */
561 /* registers like dq_mode, memory like w_mode. */
564 /* 4- or 6-byte pointer operand */
567 /* v_mode for indirect branch opcodes. */
569 /* v_mode for stack-related opcodes. */
571 /* non-quad operand size depends on prefixes */
573 /* 16-byte operand */
575 /* registers like dq_mode, memory like b_mode. */
577 /* registers like d_mode, memory like b_mode. */
579 /* registers like d_mode, memory like w_mode. */
581 /* registers like dq_mode, memory like d_mode. */
583 /* normal vex mode */
585 /* 128bit vex mode */
587 /* 256bit vex mode */
589 /* operand size depends on the VEX.W bit. */
592 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
593 vex_vsib_d_w_dq_mode
,
594 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
596 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
597 vex_vsib_q_w_dq_mode
,
598 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
601 /* scalar, ignore vector length. */
603 /* like b_mode, ignore vector length. */
605 /* like w_mode, ignore vector length. */
607 /* like d_mode, ignore vector length. */
609 /* like d_swap_mode, ignore vector length. */
611 /* like q_mode, ignore vector length. */
613 /* like q_swap_mode, ignore vector length. */
615 /* like vex_mode, ignore vector length. */
617 /* like vex_w_dq_mode, ignore vector length. */
618 vex_scalar_w_dq_mode
,
620 /* Static rounding. */
622 /* Supress all exceptions. */
625 /* Mask register operand. */
627 /* Mask register operand. */
694 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
696 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
697 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
698 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
699 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
700 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
701 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
702 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
703 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
704 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
705 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
706 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
707 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
708 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
709 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
710 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
832 MOD_VEX_0F12_PREFIX_0
,
834 MOD_VEX_0F16_PREFIX_0
,
837 MOD_VEX_W_0_0F41_P_0_LEN_1
,
838 MOD_VEX_W_1_0F41_P_0_LEN_1
,
839 MOD_VEX_W_0_0F41_P_2_LEN_1
,
840 MOD_VEX_W_1_0F41_P_2_LEN_1
,
841 MOD_VEX_W_0_0F42_P_0_LEN_1
,
842 MOD_VEX_W_1_0F42_P_0_LEN_1
,
843 MOD_VEX_W_0_0F42_P_2_LEN_1
,
844 MOD_VEX_W_1_0F42_P_2_LEN_1
,
845 MOD_VEX_W_0_0F44_P_0_LEN_1
,
846 MOD_VEX_W_1_0F44_P_0_LEN_1
,
847 MOD_VEX_W_0_0F44_P_2_LEN_1
,
848 MOD_VEX_W_1_0F44_P_2_LEN_1
,
849 MOD_VEX_W_0_0F45_P_0_LEN_1
,
850 MOD_VEX_W_1_0F45_P_0_LEN_1
,
851 MOD_VEX_W_0_0F45_P_2_LEN_1
,
852 MOD_VEX_W_1_0F45_P_2_LEN_1
,
853 MOD_VEX_W_0_0F46_P_0_LEN_1
,
854 MOD_VEX_W_1_0F46_P_0_LEN_1
,
855 MOD_VEX_W_0_0F46_P_2_LEN_1
,
856 MOD_VEX_W_1_0F46_P_2_LEN_1
,
857 MOD_VEX_W_0_0F47_P_0_LEN_1
,
858 MOD_VEX_W_1_0F47_P_0_LEN_1
,
859 MOD_VEX_W_0_0F47_P_2_LEN_1
,
860 MOD_VEX_W_1_0F47_P_2_LEN_1
,
861 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
862 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
863 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
864 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
865 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
866 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
867 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
879 MOD_VEX_W_0_0F91_P_0_LEN_0
,
880 MOD_VEX_W_1_0F91_P_0_LEN_0
,
881 MOD_VEX_W_0_0F91_P_2_LEN_0
,
882 MOD_VEX_W_1_0F91_P_2_LEN_0
,
883 MOD_VEX_W_0_0F92_P_0_LEN_0
,
884 MOD_VEX_W_0_0F92_P_2_LEN_0
,
885 MOD_VEX_W_0_0F92_P_3_LEN_0
,
886 MOD_VEX_W_1_0F92_P_3_LEN_0
,
887 MOD_VEX_W_0_0F93_P_0_LEN_0
,
888 MOD_VEX_W_0_0F93_P_2_LEN_0
,
889 MOD_VEX_W_0_0F93_P_3_LEN_0
,
890 MOD_VEX_W_1_0F93_P_3_LEN_0
,
891 MOD_VEX_W_0_0F98_P_0_LEN_0
,
892 MOD_VEX_W_1_0F98_P_0_LEN_0
,
893 MOD_VEX_W_0_0F98_P_2_LEN_0
,
894 MOD_VEX_W_1_0F98_P_2_LEN_0
,
895 MOD_VEX_W_0_0F99_P_0_LEN_0
,
896 MOD_VEX_W_1_0F99_P_0_LEN_0
,
897 MOD_VEX_W_0_0F99_P_2_LEN_0
,
898 MOD_VEX_W_1_0F99_P_2_LEN_0
,
901 MOD_VEX_0FD7_PREFIX_2
,
902 MOD_VEX_0FE7_PREFIX_2
,
903 MOD_VEX_0FF0_PREFIX_3
,
904 MOD_VEX_0F381A_PREFIX_2
,
905 MOD_VEX_0F382A_PREFIX_2
,
906 MOD_VEX_0F382C_PREFIX_2
,
907 MOD_VEX_0F382D_PREFIX_2
,
908 MOD_VEX_0F382E_PREFIX_2
,
909 MOD_VEX_0F382F_PREFIX_2
,
910 MOD_VEX_0F385A_PREFIX_2
,
911 MOD_VEX_0F388C_PREFIX_2
,
912 MOD_VEX_0F388E_PREFIX_2
,
913 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
914 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
915 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
916 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
917 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
918 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
919 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
920 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
922 MOD_EVEX_0F10_PREFIX_1
,
923 MOD_EVEX_0F10_PREFIX_3
,
924 MOD_EVEX_0F11_PREFIX_1
,
925 MOD_EVEX_0F11_PREFIX_3
,
926 MOD_EVEX_0F12_PREFIX_0
,
927 MOD_EVEX_0F16_PREFIX_0
,
928 MOD_EVEX_0F38C6_REG_1
,
929 MOD_EVEX_0F38C6_REG_2
,
930 MOD_EVEX_0F38C6_REG_5
,
931 MOD_EVEX_0F38C6_REG_6
,
932 MOD_EVEX_0F38C7_REG_1
,
933 MOD_EVEX_0F38C7_REG_2
,
934 MOD_EVEX_0F38C7_REG_5
,
935 MOD_EVEX_0F38C7_REG_6
956 PREFIX_MOD_0_0F01_REG_5
,
957 PREFIX_MOD_3_0F01_REG_5_RM_0
,
958 PREFIX_MOD_3_0F01_REG_5_RM_2
,
1002 PREFIX_MOD_0_0FAE_REG_4
,
1003 PREFIX_MOD_3_0FAE_REG_4
,
1004 PREFIX_MOD_0_0FAE_REG_5
,
1005 PREFIX_MOD_3_0FAE_REG_5
,
1013 PREFIX_MOD_0_0FC7_REG_6
,
1014 PREFIX_MOD_3_0FC7_REG_6
,
1015 PREFIX_MOD_3_0FC7_REG_7
,
1143 PREFIX_VEX_0F71_REG_2
,
1144 PREFIX_VEX_0F71_REG_4
,
1145 PREFIX_VEX_0F71_REG_6
,
1146 PREFIX_VEX_0F72_REG_2
,
1147 PREFIX_VEX_0F72_REG_4
,
1148 PREFIX_VEX_0F72_REG_6
,
1149 PREFIX_VEX_0F73_REG_2
,
1150 PREFIX_VEX_0F73_REG_3
,
1151 PREFIX_VEX_0F73_REG_6
,
1152 PREFIX_VEX_0F73_REG_7
,
1325 PREFIX_VEX_0F38F3_REG_1
,
1326 PREFIX_VEX_0F38F3_REG_2
,
1327 PREFIX_VEX_0F38F3_REG_3
,
1446 PREFIX_EVEX_0F71_REG_2
,
1447 PREFIX_EVEX_0F71_REG_4
,
1448 PREFIX_EVEX_0F71_REG_6
,
1449 PREFIX_EVEX_0F72_REG_0
,
1450 PREFIX_EVEX_0F72_REG_1
,
1451 PREFIX_EVEX_0F72_REG_2
,
1452 PREFIX_EVEX_0F72_REG_4
,
1453 PREFIX_EVEX_0F72_REG_6
,
1454 PREFIX_EVEX_0F73_REG_2
,
1455 PREFIX_EVEX_0F73_REG_3
,
1456 PREFIX_EVEX_0F73_REG_6
,
1457 PREFIX_EVEX_0F73_REG_7
,
1653 PREFIX_EVEX_0F38C6_REG_1
,
1654 PREFIX_EVEX_0F38C6_REG_2
,
1655 PREFIX_EVEX_0F38C6_REG_5
,
1656 PREFIX_EVEX_0F38C6_REG_6
,
1657 PREFIX_EVEX_0F38C7_REG_1
,
1658 PREFIX_EVEX_0F38C7_REG_2
,
1659 PREFIX_EVEX_0F38C7_REG_5
,
1660 PREFIX_EVEX_0F38C7_REG_6
,
1762 THREE_BYTE_0F38
= 0,
1789 VEX_LEN_0F10_P_1
= 0,
1793 VEX_LEN_0F12_P_0_M_0
,
1794 VEX_LEN_0F12_P_0_M_1
,
1797 VEX_LEN_0F16_P_0_M_0
,
1798 VEX_LEN_0F16_P_0_M_1
,
1862 VEX_LEN_0FAE_R_2_M_0
,
1863 VEX_LEN_0FAE_R_3_M_0
,
1872 VEX_LEN_0F381A_P_2_M_0
,
1875 VEX_LEN_0F385A_P_2_M_0
,
1878 VEX_LEN_0F38F3_R_1_P_0
,
1879 VEX_LEN_0F38F3_R_2_P_0
,
1880 VEX_LEN_0F38F3_R_3_P_0
,
1925 VEX_LEN_0FXOP_08_CC
,
1926 VEX_LEN_0FXOP_08_CD
,
1927 VEX_LEN_0FXOP_08_CE
,
1928 VEX_LEN_0FXOP_08_CF
,
1929 VEX_LEN_0FXOP_08_EC
,
1930 VEX_LEN_0FXOP_08_ED
,
1931 VEX_LEN_0FXOP_08_EE
,
1932 VEX_LEN_0FXOP_08_EF
,
1933 VEX_LEN_0FXOP_09_80
,
1967 VEX_W_0F41_P_0_LEN_1
,
1968 VEX_W_0F41_P_2_LEN_1
,
1969 VEX_W_0F42_P_0_LEN_1
,
1970 VEX_W_0F42_P_2_LEN_1
,
1971 VEX_W_0F44_P_0_LEN_0
,
1972 VEX_W_0F44_P_2_LEN_0
,
1973 VEX_W_0F45_P_0_LEN_1
,
1974 VEX_W_0F45_P_2_LEN_1
,
1975 VEX_W_0F46_P_0_LEN_1
,
1976 VEX_W_0F46_P_2_LEN_1
,
1977 VEX_W_0F47_P_0_LEN_1
,
1978 VEX_W_0F47_P_2_LEN_1
,
1979 VEX_W_0F4A_P_0_LEN_1
,
1980 VEX_W_0F4A_P_2_LEN_1
,
1981 VEX_W_0F4B_P_0_LEN_1
,
1982 VEX_W_0F4B_P_2_LEN_1
,
2062 VEX_W_0F90_P_0_LEN_0
,
2063 VEX_W_0F90_P_2_LEN_0
,
2064 VEX_W_0F91_P_0_LEN_0
,
2065 VEX_W_0F91_P_2_LEN_0
,
2066 VEX_W_0F92_P_0_LEN_0
,
2067 VEX_W_0F92_P_2_LEN_0
,
2068 VEX_W_0F92_P_3_LEN_0
,
2069 VEX_W_0F93_P_0_LEN_0
,
2070 VEX_W_0F93_P_2_LEN_0
,
2071 VEX_W_0F93_P_3_LEN_0
,
2072 VEX_W_0F98_P_0_LEN_0
,
2073 VEX_W_0F98_P_2_LEN_0
,
2074 VEX_W_0F99_P_0_LEN_0
,
2075 VEX_W_0F99_P_2_LEN_0
,
2154 VEX_W_0F381A_P_2_M_0
,
2166 VEX_W_0F382A_P_2_M_0
,
2168 VEX_W_0F382C_P_2_M_0
,
2169 VEX_W_0F382D_P_2_M_0
,
2170 VEX_W_0F382E_P_2_M_0
,
2171 VEX_W_0F382F_P_2_M_0
,
2193 VEX_W_0F385A_P_2_M_0
,
2218 VEX_W_0F3A30_P_2_LEN_0
,
2219 VEX_W_0F3A31_P_2_LEN_0
,
2220 VEX_W_0F3A32_P_2_LEN_0
,
2221 VEX_W_0F3A33_P_2_LEN_0
,
2240 EVEX_W_0F10_P_1_M_0
,
2241 EVEX_W_0F10_P_1_M_1
,
2243 EVEX_W_0F10_P_3_M_0
,
2244 EVEX_W_0F10_P_3_M_1
,
2246 EVEX_W_0F11_P_1_M_0
,
2247 EVEX_W_0F11_P_1_M_1
,
2249 EVEX_W_0F11_P_3_M_0
,
2250 EVEX_W_0F11_P_3_M_1
,
2251 EVEX_W_0F12_P_0_M_0
,
2252 EVEX_W_0F12_P_0_M_1
,
2262 EVEX_W_0F16_P_0_M_0
,
2263 EVEX_W_0F16_P_0_M_1
,
2334 EVEX_W_0F72_R_2_P_2
,
2335 EVEX_W_0F72_R_6_P_2
,
2336 EVEX_W_0F73_R_2_P_2
,
2337 EVEX_W_0F73_R_6_P_2
,
2445 EVEX_W_0F38C7_R_1_P_2
,
2446 EVEX_W_0F38C7_R_2_P_2
,
2447 EVEX_W_0F38C7_R_5_P_2
,
2448 EVEX_W_0F38C7_R_6_P_2
,
2489 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2498 unsigned int prefix_requirement
;
2501 /* Upper case letters in the instruction names here are macros.
2502 'A' => print 'b' if no register operands or suffix_always is true
2503 'B' => print 'b' if suffix_always is true
2504 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2506 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2507 suffix_always is true
2508 'E' => print 'e' if 32-bit form of jcxz
2509 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2510 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2511 'H' => print ",pt" or ",pn" branch hint
2512 'I' => honor following macro letter even in Intel mode (implemented only
2513 for some of the macro letters)
2515 'K' => print 'd' or 'q' if rex prefix is present.
2516 'L' => print 'l' if suffix_always is true
2517 'M' => print 'r' if intel_mnemonic is false.
2518 'N' => print 'n' if instruction has no wait "prefix"
2519 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2520 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2521 or suffix_always is true. print 'q' if rex prefix is present.
2522 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2524 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2525 'S' => print 'w', 'l' or 'q' if suffix_always is true
2526 'T' => print 'q' in 64bit mode if instruction has no operand size
2527 prefix and behave as 'P' otherwise
2528 'U' => print 'q' in 64bit mode if instruction has no operand size
2529 prefix and behave as 'Q' otherwise
2530 'V' => print 'q' in 64bit mode if instruction has no operand size
2531 prefix and behave as 'S' otherwise
2532 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2533 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2534 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2535 suffix_always is true.
2536 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2537 '!' => change condition from true to false or from false to true.
2538 '%' => add 1 upper case letter to the macro.
2539 '^' => print 'w' or 'l' depending on operand size prefix or
2540 suffix_always is true (lcall/ljmp).
2541 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2542 on operand size prefix.
2543 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2544 has no operand size prefix for AMD64 ISA, behave as 'P'
2547 2 upper case letter macros:
2548 "XY" => print 'x' or 'y' if suffix_always is true or no register
2549 operands and no broadcast.
2550 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2551 register operands and no broadcast.
2552 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2553 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2554 or suffix_always is true
2555 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2556 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2557 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2558 "LW" => print 'd', 'q' depending on the VEX.W bit
2559 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2560 an operand size prefix, or suffix_always is true. print
2561 'q' if rex prefix is present.
2563 Many of the above letters print nothing in Intel mode. See "putop"
2566 Braces '{' and '}', and vertical bars '|', indicate alternative
2567 mnemonic strings for AT&T and Intel. */
2569 static const struct dis386 dis386
[] = {
2571 { "addB", { Ebh1
, Gb
}, 0 },
2572 { "addS", { Evh1
, Gv
}, 0 },
2573 { "addB", { Gb
, EbS
}, 0 },
2574 { "addS", { Gv
, EvS
}, 0 },
2575 { "addB", { AL
, Ib
}, 0 },
2576 { "addS", { eAX
, Iv
}, 0 },
2577 { X86_64_TABLE (X86_64_06
) },
2578 { X86_64_TABLE (X86_64_07
) },
2580 { "orB", { Ebh1
, Gb
}, 0 },
2581 { "orS", { Evh1
, Gv
}, 0 },
2582 { "orB", { Gb
, EbS
}, 0 },
2583 { "orS", { Gv
, EvS
}, 0 },
2584 { "orB", { AL
, Ib
}, 0 },
2585 { "orS", { eAX
, Iv
}, 0 },
2586 { X86_64_TABLE (X86_64_0D
) },
2587 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2589 { "adcB", { Ebh1
, Gb
}, 0 },
2590 { "adcS", { Evh1
, Gv
}, 0 },
2591 { "adcB", { Gb
, EbS
}, 0 },
2592 { "adcS", { Gv
, EvS
}, 0 },
2593 { "adcB", { AL
, Ib
}, 0 },
2594 { "adcS", { eAX
, Iv
}, 0 },
2595 { X86_64_TABLE (X86_64_16
) },
2596 { X86_64_TABLE (X86_64_17
) },
2598 { "sbbB", { Ebh1
, Gb
}, 0 },
2599 { "sbbS", { Evh1
, Gv
}, 0 },
2600 { "sbbB", { Gb
, EbS
}, 0 },
2601 { "sbbS", { Gv
, EvS
}, 0 },
2602 { "sbbB", { AL
, Ib
}, 0 },
2603 { "sbbS", { eAX
, Iv
}, 0 },
2604 { X86_64_TABLE (X86_64_1E
) },
2605 { X86_64_TABLE (X86_64_1F
) },
2607 { "andB", { Ebh1
, Gb
}, 0 },
2608 { "andS", { Evh1
, Gv
}, 0 },
2609 { "andB", { Gb
, EbS
}, 0 },
2610 { "andS", { Gv
, EvS
}, 0 },
2611 { "andB", { AL
, Ib
}, 0 },
2612 { "andS", { eAX
, Iv
}, 0 },
2613 { Bad_Opcode
}, /* SEG ES prefix */
2614 { X86_64_TABLE (X86_64_27
) },
2616 { "subB", { Ebh1
, Gb
}, 0 },
2617 { "subS", { Evh1
, Gv
}, 0 },
2618 { "subB", { Gb
, EbS
}, 0 },
2619 { "subS", { Gv
, EvS
}, 0 },
2620 { "subB", { AL
, Ib
}, 0 },
2621 { "subS", { eAX
, Iv
}, 0 },
2622 { Bad_Opcode
}, /* SEG CS prefix */
2623 { X86_64_TABLE (X86_64_2F
) },
2625 { "xorB", { Ebh1
, Gb
}, 0 },
2626 { "xorS", { Evh1
, Gv
}, 0 },
2627 { "xorB", { Gb
, EbS
}, 0 },
2628 { "xorS", { Gv
, EvS
}, 0 },
2629 { "xorB", { AL
, Ib
}, 0 },
2630 { "xorS", { eAX
, Iv
}, 0 },
2631 { Bad_Opcode
}, /* SEG SS prefix */
2632 { X86_64_TABLE (X86_64_37
) },
2634 { "cmpB", { Eb
, Gb
}, 0 },
2635 { "cmpS", { Ev
, Gv
}, 0 },
2636 { "cmpB", { Gb
, EbS
}, 0 },
2637 { "cmpS", { Gv
, EvS
}, 0 },
2638 { "cmpB", { AL
, Ib
}, 0 },
2639 { "cmpS", { eAX
, Iv
}, 0 },
2640 { Bad_Opcode
}, /* SEG DS prefix */
2641 { X86_64_TABLE (X86_64_3F
) },
2643 { "inc{S|}", { RMeAX
}, 0 },
2644 { "inc{S|}", { RMeCX
}, 0 },
2645 { "inc{S|}", { RMeDX
}, 0 },
2646 { "inc{S|}", { RMeBX
}, 0 },
2647 { "inc{S|}", { RMeSP
}, 0 },
2648 { "inc{S|}", { RMeBP
}, 0 },
2649 { "inc{S|}", { RMeSI
}, 0 },
2650 { "inc{S|}", { RMeDI
}, 0 },
2652 { "dec{S|}", { RMeAX
}, 0 },
2653 { "dec{S|}", { RMeCX
}, 0 },
2654 { "dec{S|}", { RMeDX
}, 0 },
2655 { "dec{S|}", { RMeBX
}, 0 },
2656 { "dec{S|}", { RMeSP
}, 0 },
2657 { "dec{S|}", { RMeBP
}, 0 },
2658 { "dec{S|}", { RMeSI
}, 0 },
2659 { "dec{S|}", { RMeDI
}, 0 },
2661 { "pushV", { RMrAX
}, 0 },
2662 { "pushV", { RMrCX
}, 0 },
2663 { "pushV", { RMrDX
}, 0 },
2664 { "pushV", { RMrBX
}, 0 },
2665 { "pushV", { RMrSP
}, 0 },
2666 { "pushV", { RMrBP
}, 0 },
2667 { "pushV", { RMrSI
}, 0 },
2668 { "pushV", { RMrDI
}, 0 },
2670 { "popV", { RMrAX
}, 0 },
2671 { "popV", { RMrCX
}, 0 },
2672 { "popV", { RMrDX
}, 0 },
2673 { "popV", { RMrBX
}, 0 },
2674 { "popV", { RMrSP
}, 0 },
2675 { "popV", { RMrBP
}, 0 },
2676 { "popV", { RMrSI
}, 0 },
2677 { "popV", { RMrDI
}, 0 },
2679 { X86_64_TABLE (X86_64_60
) },
2680 { X86_64_TABLE (X86_64_61
) },
2681 { X86_64_TABLE (X86_64_62
) },
2682 { X86_64_TABLE (X86_64_63
) },
2683 { Bad_Opcode
}, /* seg fs */
2684 { Bad_Opcode
}, /* seg gs */
2685 { Bad_Opcode
}, /* op size prefix */
2686 { Bad_Opcode
}, /* adr size prefix */
2688 { "pushT", { sIv
}, 0 },
2689 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2690 { "pushT", { sIbT
}, 0 },
2691 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2692 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2693 { X86_64_TABLE (X86_64_6D
) },
2694 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2695 { X86_64_TABLE (X86_64_6F
) },
2697 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2698 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2699 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2700 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2701 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2702 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2703 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2704 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2706 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2707 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2708 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2709 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2710 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2711 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2712 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2713 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2715 { REG_TABLE (REG_80
) },
2716 { REG_TABLE (REG_81
) },
2717 { X86_64_TABLE (X86_64_82
) },
2718 { REG_TABLE (REG_83
) },
2719 { "testB", { Eb
, Gb
}, 0 },
2720 { "testS", { Ev
, Gv
}, 0 },
2721 { "xchgB", { Ebh2
, Gb
}, 0 },
2722 { "xchgS", { Evh2
, Gv
}, 0 },
2724 { "movB", { Ebh3
, Gb
}, 0 },
2725 { "movS", { Evh3
, Gv
}, 0 },
2726 { "movB", { Gb
, EbS
}, 0 },
2727 { "movS", { Gv
, EvS
}, 0 },
2728 { "movD", { Sv
, Sw
}, 0 },
2729 { MOD_TABLE (MOD_8D
) },
2730 { "movD", { Sw
, Sv
}, 0 },
2731 { REG_TABLE (REG_8F
) },
2733 { PREFIX_TABLE (PREFIX_90
) },
2734 { "xchgS", { RMeCX
, eAX
}, 0 },
2735 { "xchgS", { RMeDX
, eAX
}, 0 },
2736 { "xchgS", { RMeBX
, eAX
}, 0 },
2737 { "xchgS", { RMeSP
, eAX
}, 0 },
2738 { "xchgS", { RMeBP
, eAX
}, 0 },
2739 { "xchgS", { RMeSI
, eAX
}, 0 },
2740 { "xchgS", { RMeDI
, eAX
}, 0 },
2742 { "cW{t|}R", { XX
}, 0 },
2743 { "cR{t|}O", { XX
}, 0 },
2744 { X86_64_TABLE (X86_64_9A
) },
2745 { Bad_Opcode
}, /* fwait */
2746 { "pushfT", { XX
}, 0 },
2747 { "popfT", { XX
}, 0 },
2748 { "sahf", { XX
}, 0 },
2749 { "lahf", { XX
}, 0 },
2751 { "mov%LB", { AL
, Ob
}, 0 },
2752 { "mov%LS", { eAX
, Ov
}, 0 },
2753 { "mov%LB", { Ob
, AL
}, 0 },
2754 { "mov%LS", { Ov
, eAX
}, 0 },
2755 { "movs{b|}", { Ybr
, Xb
}, 0 },
2756 { "movs{R|}", { Yvr
, Xv
}, 0 },
2757 { "cmps{b|}", { Xb
, Yb
}, 0 },
2758 { "cmps{R|}", { Xv
, Yv
}, 0 },
2760 { "testB", { AL
, Ib
}, 0 },
2761 { "testS", { eAX
, Iv
}, 0 },
2762 { "stosB", { Ybr
, AL
}, 0 },
2763 { "stosS", { Yvr
, eAX
}, 0 },
2764 { "lodsB", { ALr
, Xb
}, 0 },
2765 { "lodsS", { eAXr
, Xv
}, 0 },
2766 { "scasB", { AL
, Yb
}, 0 },
2767 { "scasS", { eAX
, Yv
}, 0 },
2769 { "movB", { RMAL
, Ib
}, 0 },
2770 { "movB", { RMCL
, Ib
}, 0 },
2771 { "movB", { RMDL
, Ib
}, 0 },
2772 { "movB", { RMBL
, Ib
}, 0 },
2773 { "movB", { RMAH
, Ib
}, 0 },
2774 { "movB", { RMCH
, Ib
}, 0 },
2775 { "movB", { RMDH
, Ib
}, 0 },
2776 { "movB", { RMBH
, Ib
}, 0 },
2778 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2779 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2780 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2781 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2782 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2783 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2784 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2785 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2787 { REG_TABLE (REG_C0
) },
2788 { REG_TABLE (REG_C1
) },
2789 { "retT", { Iw
, BND
}, 0 },
2790 { "retT", { BND
}, 0 },
2791 { X86_64_TABLE (X86_64_C4
) },
2792 { X86_64_TABLE (X86_64_C5
) },
2793 { REG_TABLE (REG_C6
) },
2794 { REG_TABLE (REG_C7
) },
2796 { "enterT", { Iw
, Ib
}, 0 },
2797 { "leaveT", { XX
}, 0 },
2798 { "Jret{|f}P", { Iw
}, 0 },
2799 { "Jret{|f}P", { XX
}, 0 },
2800 { "int3", { XX
}, 0 },
2801 { "int", { Ib
}, 0 },
2802 { X86_64_TABLE (X86_64_CE
) },
2803 { "iret%LP", { XX
}, 0 },
2805 { REG_TABLE (REG_D0
) },
2806 { REG_TABLE (REG_D1
) },
2807 { REG_TABLE (REG_D2
) },
2808 { REG_TABLE (REG_D3
) },
2809 { X86_64_TABLE (X86_64_D4
) },
2810 { X86_64_TABLE (X86_64_D5
) },
2812 { "xlat", { DSBX
}, 0 },
2823 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2824 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2825 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2826 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2827 { "inB", { AL
, Ib
}, 0 },
2828 { "inG", { zAX
, Ib
}, 0 },
2829 { "outB", { Ib
, AL
}, 0 },
2830 { "outG", { Ib
, zAX
}, 0 },
2832 { X86_64_TABLE (X86_64_E8
) },
2833 { X86_64_TABLE (X86_64_E9
) },
2834 { X86_64_TABLE (X86_64_EA
) },
2835 { "jmp", { Jb
, BND
}, 0 },
2836 { "inB", { AL
, indirDX
}, 0 },
2837 { "inG", { zAX
, indirDX
}, 0 },
2838 { "outB", { indirDX
, AL
}, 0 },
2839 { "outG", { indirDX
, zAX
}, 0 },
2841 { Bad_Opcode
}, /* lock prefix */
2842 { "icebp", { XX
}, 0 },
2843 { Bad_Opcode
}, /* repne */
2844 { Bad_Opcode
}, /* repz */
2845 { "hlt", { XX
}, 0 },
2846 { "cmc", { XX
}, 0 },
2847 { REG_TABLE (REG_F6
) },
2848 { REG_TABLE (REG_F7
) },
2850 { "clc", { XX
}, 0 },
2851 { "stc", { XX
}, 0 },
2852 { "cli", { XX
}, 0 },
2853 { "sti", { XX
}, 0 },
2854 { "cld", { XX
}, 0 },
2855 { "std", { XX
}, 0 },
2856 { REG_TABLE (REG_FE
) },
2857 { REG_TABLE (REG_FF
) },
2860 static const struct dis386 dis386_twobyte
[] = {
2862 { REG_TABLE (REG_0F00
) },
2863 { REG_TABLE (REG_0F01
) },
2864 { "larS", { Gv
, Ew
}, 0 },
2865 { "lslS", { Gv
, Ew
}, 0 },
2867 { "syscall", { XX
}, 0 },
2868 { "clts", { XX
}, 0 },
2869 { "sysret%LP", { XX
}, 0 },
2871 { "invd", { XX
}, 0 },
2872 { "wbinvd", { XX
}, 0 },
2874 { "ud2", { XX
}, 0 },
2876 { REG_TABLE (REG_0F0D
) },
2877 { "femms", { XX
}, 0 },
2878 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2880 { PREFIX_TABLE (PREFIX_0F10
) },
2881 { PREFIX_TABLE (PREFIX_0F11
) },
2882 { PREFIX_TABLE (PREFIX_0F12
) },
2883 { MOD_TABLE (MOD_0F13
) },
2884 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2885 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2886 { PREFIX_TABLE (PREFIX_0F16
) },
2887 { MOD_TABLE (MOD_0F17
) },
2889 { REG_TABLE (REG_0F18
) },
2890 { "nopQ", { Ev
}, 0 },
2891 { PREFIX_TABLE (PREFIX_0F1A
) },
2892 { PREFIX_TABLE (PREFIX_0F1B
) },
2893 { "nopQ", { Ev
}, 0 },
2894 { "nopQ", { Ev
}, 0 },
2895 { PREFIX_TABLE (PREFIX_0F1E
) },
2896 { "nopQ", { Ev
}, 0 },
2898 { "movZ", { Rm
, Cm
}, 0 },
2899 { "movZ", { Rm
, Dm
}, 0 },
2900 { "movZ", { Cm
, Rm
}, 0 },
2901 { "movZ", { Dm
, Rm
}, 0 },
2902 { MOD_TABLE (MOD_0F24
) },
2904 { MOD_TABLE (MOD_0F26
) },
2907 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2908 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2909 { PREFIX_TABLE (PREFIX_0F2A
) },
2910 { PREFIX_TABLE (PREFIX_0F2B
) },
2911 { PREFIX_TABLE (PREFIX_0F2C
) },
2912 { PREFIX_TABLE (PREFIX_0F2D
) },
2913 { PREFIX_TABLE (PREFIX_0F2E
) },
2914 { PREFIX_TABLE (PREFIX_0F2F
) },
2916 { "wrmsr", { XX
}, 0 },
2917 { "rdtsc", { XX
}, 0 },
2918 { "rdmsr", { XX
}, 0 },
2919 { "rdpmc", { XX
}, 0 },
2920 { "sysenter", { XX
}, 0 },
2921 { "sysexit", { XX
}, 0 },
2923 { "getsec", { XX
}, 0 },
2925 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2927 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2934 { "cmovoS", { Gv
, Ev
}, 0 },
2935 { "cmovnoS", { Gv
, Ev
}, 0 },
2936 { "cmovbS", { Gv
, Ev
}, 0 },
2937 { "cmovaeS", { Gv
, Ev
}, 0 },
2938 { "cmoveS", { Gv
, Ev
}, 0 },
2939 { "cmovneS", { Gv
, Ev
}, 0 },
2940 { "cmovbeS", { Gv
, Ev
}, 0 },
2941 { "cmovaS", { Gv
, Ev
}, 0 },
2943 { "cmovsS", { Gv
, Ev
}, 0 },
2944 { "cmovnsS", { Gv
, Ev
}, 0 },
2945 { "cmovpS", { Gv
, Ev
}, 0 },
2946 { "cmovnpS", { Gv
, Ev
}, 0 },
2947 { "cmovlS", { Gv
, Ev
}, 0 },
2948 { "cmovgeS", { Gv
, Ev
}, 0 },
2949 { "cmovleS", { Gv
, Ev
}, 0 },
2950 { "cmovgS", { Gv
, Ev
}, 0 },
2952 { MOD_TABLE (MOD_0F51
) },
2953 { PREFIX_TABLE (PREFIX_0F51
) },
2954 { PREFIX_TABLE (PREFIX_0F52
) },
2955 { PREFIX_TABLE (PREFIX_0F53
) },
2956 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2957 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2958 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2959 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2961 { PREFIX_TABLE (PREFIX_0F58
) },
2962 { PREFIX_TABLE (PREFIX_0F59
) },
2963 { PREFIX_TABLE (PREFIX_0F5A
) },
2964 { PREFIX_TABLE (PREFIX_0F5B
) },
2965 { PREFIX_TABLE (PREFIX_0F5C
) },
2966 { PREFIX_TABLE (PREFIX_0F5D
) },
2967 { PREFIX_TABLE (PREFIX_0F5E
) },
2968 { PREFIX_TABLE (PREFIX_0F5F
) },
2970 { PREFIX_TABLE (PREFIX_0F60
) },
2971 { PREFIX_TABLE (PREFIX_0F61
) },
2972 { PREFIX_TABLE (PREFIX_0F62
) },
2973 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2974 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2975 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2976 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2977 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2979 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2980 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2981 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2982 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2983 { PREFIX_TABLE (PREFIX_0F6C
) },
2984 { PREFIX_TABLE (PREFIX_0F6D
) },
2985 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2986 { PREFIX_TABLE (PREFIX_0F6F
) },
2988 { PREFIX_TABLE (PREFIX_0F70
) },
2989 { REG_TABLE (REG_0F71
) },
2990 { REG_TABLE (REG_0F72
) },
2991 { REG_TABLE (REG_0F73
) },
2992 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2993 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2994 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2995 { "emms", { XX
}, PREFIX_OPCODE
},
2997 { PREFIX_TABLE (PREFIX_0F78
) },
2998 { PREFIX_TABLE (PREFIX_0F79
) },
3001 { PREFIX_TABLE (PREFIX_0F7C
) },
3002 { PREFIX_TABLE (PREFIX_0F7D
) },
3003 { PREFIX_TABLE (PREFIX_0F7E
) },
3004 { PREFIX_TABLE (PREFIX_0F7F
) },
3006 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
3007 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
3008 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
3009 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3010 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3011 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
3012 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3013 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
3015 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
3016 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
3017 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
3018 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
3019 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
3020 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3021 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
3022 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
3024 { "seto", { Eb
}, 0 },
3025 { "setno", { Eb
}, 0 },
3026 { "setb", { Eb
}, 0 },
3027 { "setae", { Eb
}, 0 },
3028 { "sete", { Eb
}, 0 },
3029 { "setne", { Eb
}, 0 },
3030 { "setbe", { Eb
}, 0 },
3031 { "seta", { Eb
}, 0 },
3033 { "sets", { Eb
}, 0 },
3034 { "setns", { Eb
}, 0 },
3035 { "setp", { Eb
}, 0 },
3036 { "setnp", { Eb
}, 0 },
3037 { "setl", { Eb
}, 0 },
3038 { "setge", { Eb
}, 0 },
3039 { "setle", { Eb
}, 0 },
3040 { "setg", { Eb
}, 0 },
3042 { "pushT", { fs
}, 0 },
3043 { "popT", { fs
}, 0 },
3044 { "cpuid", { XX
}, 0 },
3045 { "btS", { Ev
, Gv
}, 0 },
3046 { "shldS", { Ev
, Gv
, Ib
}, 0 },
3047 { "shldS", { Ev
, Gv
, CL
}, 0 },
3048 { REG_TABLE (REG_0FA6
) },
3049 { REG_TABLE (REG_0FA7
) },
3051 { "pushT", { gs
}, 0 },
3052 { "popT", { gs
}, 0 },
3053 { "rsm", { XX
}, 0 },
3054 { "btsS", { Evh1
, Gv
}, 0 },
3055 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
3056 { "shrdS", { Ev
, Gv
, CL
}, 0 },
3057 { REG_TABLE (REG_0FAE
) },
3058 { "imulS", { Gv
, Ev
}, 0 },
3060 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
3061 { "cmpxchgS", { Evh1
, Gv
}, 0 },
3062 { MOD_TABLE (MOD_0FB2
) },
3063 { "btrS", { Evh1
, Gv
}, 0 },
3064 { MOD_TABLE (MOD_0FB4
) },
3065 { MOD_TABLE (MOD_0FB5
) },
3066 { "movz{bR|x}", { Gv
, Eb
}, 0 },
3067 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
3069 { PREFIX_TABLE (PREFIX_0FB8
) },
3070 { "ud1", { XX
}, 0 },
3071 { REG_TABLE (REG_0FBA
) },
3072 { "btcS", { Evh1
, Gv
}, 0 },
3073 { PREFIX_TABLE (PREFIX_0FBC
) },
3074 { PREFIX_TABLE (PREFIX_0FBD
) },
3075 { "movs{bR|x}", { Gv
, Eb
}, 0 },
3076 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
3078 { "xaddB", { Ebh1
, Gb
}, 0 },
3079 { "xaddS", { Evh1
, Gv
}, 0 },
3080 { PREFIX_TABLE (PREFIX_0FC2
) },
3081 { MOD_TABLE (MOD_0FC3
) },
3082 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
3083 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
3084 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3085 { REG_TABLE (REG_0FC7
) },
3087 { "bswap", { RMeAX
}, 0 },
3088 { "bswap", { RMeCX
}, 0 },
3089 { "bswap", { RMeDX
}, 0 },
3090 { "bswap", { RMeBX
}, 0 },
3091 { "bswap", { RMeSP
}, 0 },
3092 { "bswap", { RMeBP
}, 0 },
3093 { "bswap", { RMeSI
}, 0 },
3094 { "bswap", { RMeDI
}, 0 },
3096 { PREFIX_TABLE (PREFIX_0FD0
) },
3097 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
3098 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
3099 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
3100 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
3101 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
3102 { PREFIX_TABLE (PREFIX_0FD6
) },
3103 { MOD_TABLE (MOD_0FD7
) },
3105 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
3106 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
3107 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
3108 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
3109 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
3110 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
3111 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
3112 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
3114 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
3115 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
3116 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
3117 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
3118 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
3119 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
3120 { PREFIX_TABLE (PREFIX_0FE6
) },
3121 { PREFIX_TABLE (PREFIX_0FE7
) },
3123 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
3124 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
3125 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
3126 { "por", { MX
, EM
}, PREFIX_OPCODE
},
3127 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
3128 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
3129 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
3130 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
3132 { PREFIX_TABLE (PREFIX_0FF0
) },
3133 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
3134 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
3135 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
3136 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
3137 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
3138 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
3139 { PREFIX_TABLE (PREFIX_0FF7
) },
3141 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
3142 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
3143 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
3144 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
3145 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
3146 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
3147 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
3151 static const unsigned char onebyte_has_modrm
[256] = {
3152 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3153 /* ------------------------------- */
3154 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3155 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3156 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3157 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3158 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3159 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3160 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3161 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3162 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3163 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3164 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3165 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3166 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3167 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3168 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3169 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3170 /* ------------------------------- */
3171 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3174 static const unsigned char twobyte_has_modrm
[256] = {
3175 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3176 /* ------------------------------- */
3177 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3178 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3179 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3180 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3181 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3182 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3183 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3184 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3185 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3186 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3187 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3188 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3189 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3190 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3191 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3192 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3193 /* ------------------------------- */
3194 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3197 static char obuf
[100];
3199 static char *mnemonicendp
;
3200 static char scratchbuf
[100];
3201 static unsigned char *start_codep
;
3202 static unsigned char *insn_codep
;
3203 static unsigned char *codep
;
3204 static unsigned char *end_codep
;
3205 static int last_lock_prefix
;
3206 static int last_repz_prefix
;
3207 static int last_repnz_prefix
;
3208 static int last_data_prefix
;
3209 static int last_addr_prefix
;
3210 static int last_rex_prefix
;
3211 static int last_seg_prefix
;
3212 static int fwait_prefix
;
3213 /* The active segment register prefix. */
3214 static int active_seg_prefix
;
3215 #define MAX_CODE_LENGTH 15
3216 /* We can up to 14 prefixes since the maximum instruction length is
3218 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3219 static disassemble_info
*the_info
;
3227 static unsigned char need_modrm
;
3237 int register_specifier
;
3244 int mask_register_specifier
;
3250 static unsigned char need_vex
;
3251 static unsigned char need_vex_reg
;
3252 static unsigned char vex_w_done
;
3260 /* If we are accessing mod/rm/reg without need_modrm set, then the
3261 values are stale. Hitting this abort likely indicates that you
3262 need to update onebyte_has_modrm or twobyte_has_modrm. */
3263 #define MODRM_CHECK if (!need_modrm) abort ()
3265 static const char **names64
;
3266 static const char **names32
;
3267 static const char **names16
;
3268 static const char **names8
;
3269 static const char **names8rex
;
3270 static const char **names_seg
;
3271 static const char *index64
;
3272 static const char *index32
;
3273 static const char **index16
;
3274 static const char **names_bnd
;
3276 static const char *intel_names64
[] = {
3277 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3278 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3280 static const char *intel_names32
[] = {
3281 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3282 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3284 static const char *intel_names16
[] = {
3285 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3286 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3288 static const char *intel_names8
[] = {
3289 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3291 static const char *intel_names8rex
[] = {
3292 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3293 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3295 static const char *intel_names_seg
[] = {
3296 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3298 static const char *intel_index64
= "riz";
3299 static const char *intel_index32
= "eiz";
3300 static const char *intel_index16
[] = {
3301 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3304 static const char *att_names64
[] = {
3305 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3306 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3308 static const char *att_names32
[] = {
3309 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3310 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3312 static const char *att_names16
[] = {
3313 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3314 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3316 static const char *att_names8
[] = {
3317 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3319 static const char *att_names8rex
[] = {
3320 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3321 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3323 static const char *att_names_seg
[] = {
3324 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3326 static const char *att_index64
= "%riz";
3327 static const char *att_index32
= "%eiz";
3328 static const char *att_index16
[] = {
3329 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3332 static const char **names_mm
;
3333 static const char *intel_names_mm
[] = {
3334 "mm0", "mm1", "mm2", "mm3",
3335 "mm4", "mm5", "mm6", "mm7"
3337 static const char *att_names_mm
[] = {
3338 "%mm0", "%mm1", "%mm2", "%mm3",
3339 "%mm4", "%mm5", "%mm6", "%mm7"
3342 static const char *intel_names_bnd
[] = {
3343 "bnd0", "bnd1", "bnd2", "bnd3"
3346 static const char *att_names_bnd
[] = {
3347 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3350 static const char **names_xmm
;
3351 static const char *intel_names_xmm
[] = {
3352 "xmm0", "xmm1", "xmm2", "xmm3",
3353 "xmm4", "xmm5", "xmm6", "xmm7",
3354 "xmm8", "xmm9", "xmm10", "xmm11",
3355 "xmm12", "xmm13", "xmm14", "xmm15",
3356 "xmm16", "xmm17", "xmm18", "xmm19",
3357 "xmm20", "xmm21", "xmm22", "xmm23",
3358 "xmm24", "xmm25", "xmm26", "xmm27",
3359 "xmm28", "xmm29", "xmm30", "xmm31"
3361 static const char *att_names_xmm
[] = {
3362 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3363 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3364 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3365 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3366 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3367 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3368 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3369 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3372 static const char **names_ymm
;
3373 static const char *intel_names_ymm
[] = {
3374 "ymm0", "ymm1", "ymm2", "ymm3",
3375 "ymm4", "ymm5", "ymm6", "ymm7",
3376 "ymm8", "ymm9", "ymm10", "ymm11",
3377 "ymm12", "ymm13", "ymm14", "ymm15",
3378 "ymm16", "ymm17", "ymm18", "ymm19",
3379 "ymm20", "ymm21", "ymm22", "ymm23",
3380 "ymm24", "ymm25", "ymm26", "ymm27",
3381 "ymm28", "ymm29", "ymm30", "ymm31"
3383 static const char *att_names_ymm
[] = {
3384 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3385 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3386 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3387 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3388 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3389 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3390 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3391 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3394 static const char **names_zmm
;
3395 static const char *intel_names_zmm
[] = {
3396 "zmm0", "zmm1", "zmm2", "zmm3",
3397 "zmm4", "zmm5", "zmm6", "zmm7",
3398 "zmm8", "zmm9", "zmm10", "zmm11",
3399 "zmm12", "zmm13", "zmm14", "zmm15",
3400 "zmm16", "zmm17", "zmm18", "zmm19",
3401 "zmm20", "zmm21", "zmm22", "zmm23",
3402 "zmm24", "zmm25", "zmm26", "zmm27",
3403 "zmm28", "zmm29", "zmm30", "zmm31"
3405 static const char *att_names_zmm
[] = {
3406 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3407 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3408 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3409 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3410 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3411 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3412 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3413 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3416 static const char **names_mask
;
3417 static const char *intel_names_mask
[] = {
3418 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3420 static const char *att_names_mask
[] = {
3421 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3424 static const char *names_rounding
[] =
3432 static const struct dis386 reg_table
[][8] = {
3435 { "addA", { Ebh1
, Ib
}, 0 },
3436 { "orA", { Ebh1
, Ib
}, 0 },
3437 { "adcA", { Ebh1
, Ib
}, 0 },
3438 { "sbbA", { Ebh1
, Ib
}, 0 },
3439 { "andA", { Ebh1
, Ib
}, 0 },
3440 { "subA", { Ebh1
, Ib
}, 0 },
3441 { "xorA", { Ebh1
, Ib
}, 0 },
3442 { "cmpA", { Eb
, Ib
}, 0 },
3446 { "addQ", { Evh1
, Iv
}, 0 },
3447 { "orQ", { Evh1
, Iv
}, 0 },
3448 { "adcQ", { Evh1
, Iv
}, 0 },
3449 { "sbbQ", { Evh1
, Iv
}, 0 },
3450 { "andQ", { Evh1
, Iv
}, 0 },
3451 { "subQ", { Evh1
, Iv
}, 0 },
3452 { "xorQ", { Evh1
, Iv
}, 0 },
3453 { "cmpQ", { Ev
, Iv
}, 0 },
3457 { "addQ", { Evh1
, sIb
}, 0 },
3458 { "orQ", { Evh1
, sIb
}, 0 },
3459 { "adcQ", { Evh1
, sIb
}, 0 },
3460 { "sbbQ", { Evh1
, sIb
}, 0 },
3461 { "andQ", { Evh1
, sIb
}, 0 },
3462 { "subQ", { Evh1
, sIb
}, 0 },
3463 { "xorQ", { Evh1
, sIb
}, 0 },
3464 { "cmpQ", { Ev
, sIb
}, 0 },
3468 { "popU", { stackEv
}, 0 },
3469 { XOP_8F_TABLE (XOP_09
) },
3473 { XOP_8F_TABLE (XOP_09
) },
3477 { "rolA", { Eb
, Ib
}, 0 },
3478 { "rorA", { Eb
, Ib
}, 0 },
3479 { "rclA", { Eb
, Ib
}, 0 },
3480 { "rcrA", { Eb
, Ib
}, 0 },
3481 { "shlA", { Eb
, Ib
}, 0 },
3482 { "shrA", { Eb
, Ib
}, 0 },
3483 { "shlA", { Eb
, Ib
}, 0 },
3484 { "sarA", { Eb
, Ib
}, 0 },
3488 { "rolQ", { Ev
, Ib
}, 0 },
3489 { "rorQ", { Ev
, Ib
}, 0 },
3490 { "rclQ", { Ev
, Ib
}, 0 },
3491 { "rcrQ", { Ev
, Ib
}, 0 },
3492 { "shlQ", { Ev
, Ib
}, 0 },
3493 { "shrQ", { Ev
, Ib
}, 0 },
3494 { "shlQ", { Ev
, Ib
}, 0 },
3495 { "sarQ", { Ev
, Ib
}, 0 },
3499 { "movA", { Ebh3
, Ib
}, 0 },
3506 { MOD_TABLE (MOD_C6_REG_7
) },
3510 { "movQ", { Evh3
, Iv
}, 0 },
3517 { MOD_TABLE (MOD_C7_REG_7
) },
3521 { "rolA", { Eb
, I1
}, 0 },
3522 { "rorA", { Eb
, I1
}, 0 },
3523 { "rclA", { Eb
, I1
}, 0 },
3524 { "rcrA", { Eb
, I1
}, 0 },
3525 { "shlA", { Eb
, I1
}, 0 },
3526 { "shrA", { Eb
, I1
}, 0 },
3527 { "shlA", { Eb
, I1
}, 0 },
3528 { "sarA", { Eb
, I1
}, 0 },
3532 { "rolQ", { Ev
, I1
}, 0 },
3533 { "rorQ", { Ev
, I1
}, 0 },
3534 { "rclQ", { Ev
, I1
}, 0 },
3535 { "rcrQ", { Ev
, I1
}, 0 },
3536 { "shlQ", { Ev
, I1
}, 0 },
3537 { "shrQ", { Ev
, I1
}, 0 },
3538 { "shlQ", { Ev
, I1
}, 0 },
3539 { "sarQ", { Ev
, I1
}, 0 },
3543 { "rolA", { Eb
, CL
}, 0 },
3544 { "rorA", { Eb
, CL
}, 0 },
3545 { "rclA", { Eb
, CL
}, 0 },
3546 { "rcrA", { Eb
, CL
}, 0 },
3547 { "shlA", { Eb
, CL
}, 0 },
3548 { "shrA", { Eb
, CL
}, 0 },
3549 { "shlA", { Eb
, CL
}, 0 },
3550 { "sarA", { Eb
, CL
}, 0 },
3554 { "rolQ", { Ev
, CL
}, 0 },
3555 { "rorQ", { Ev
, CL
}, 0 },
3556 { "rclQ", { Ev
, CL
}, 0 },
3557 { "rcrQ", { Ev
, CL
}, 0 },
3558 { "shlQ", { Ev
, CL
}, 0 },
3559 { "shrQ", { Ev
, CL
}, 0 },
3560 { "shlQ", { Ev
, CL
}, 0 },
3561 { "sarQ", { Ev
, CL
}, 0 },
3565 { "testA", { Eb
, Ib
}, 0 },
3566 { "testA", { Eb
, Ib
}, 0 },
3567 { "notA", { Ebh1
}, 0 },
3568 { "negA", { Ebh1
}, 0 },
3569 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3570 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3571 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3572 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3576 { "testQ", { Ev
, Iv
}, 0 },
3577 { "testQ", { Ev
, Iv
}, 0 },
3578 { "notQ", { Evh1
}, 0 },
3579 { "negQ", { Evh1
}, 0 },
3580 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3581 { "imulQ", { Ev
}, 0 },
3582 { "divQ", { Ev
}, 0 },
3583 { "idivQ", { Ev
}, 0 },
3587 { "incA", { Ebh1
}, 0 },
3588 { "decA", { Ebh1
}, 0 },
3592 { "incQ", { Evh1
}, 0 },
3593 { "decQ", { Evh1
}, 0 },
3594 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3595 { MOD_TABLE (MOD_FF_REG_3
) },
3596 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3597 { MOD_TABLE (MOD_FF_REG_5
) },
3598 { "pushU", { stackEv
}, 0 },
3603 { "sldtD", { Sv
}, 0 },
3604 { "strD", { Sv
}, 0 },
3605 { "lldt", { Ew
}, 0 },
3606 { "ltr", { Ew
}, 0 },
3607 { "verr", { Ew
}, 0 },
3608 { "verw", { Ew
}, 0 },
3614 { MOD_TABLE (MOD_0F01_REG_0
) },
3615 { MOD_TABLE (MOD_0F01_REG_1
) },
3616 { MOD_TABLE (MOD_0F01_REG_2
) },
3617 { MOD_TABLE (MOD_0F01_REG_3
) },
3618 { "smswD", { Sv
}, 0 },
3619 { MOD_TABLE (MOD_0F01_REG_5
) },
3620 { "lmsw", { Ew
}, 0 },
3621 { MOD_TABLE (MOD_0F01_REG_7
) },
3625 { "prefetch", { Mb
}, 0 },
3626 { "prefetchw", { Mb
}, 0 },
3627 { "prefetchwt1", { Mb
}, 0 },
3628 { "prefetch", { Mb
}, 0 },
3629 { "prefetch", { Mb
}, 0 },
3630 { "prefetch", { Mb
}, 0 },
3631 { "prefetch", { Mb
}, 0 },
3632 { "prefetch", { Mb
}, 0 },
3636 { MOD_TABLE (MOD_0F18_REG_0
) },
3637 { MOD_TABLE (MOD_0F18_REG_1
) },
3638 { MOD_TABLE (MOD_0F18_REG_2
) },
3639 { MOD_TABLE (MOD_0F18_REG_3
) },
3640 { MOD_TABLE (MOD_0F18_REG_4
) },
3641 { MOD_TABLE (MOD_0F18_REG_5
) },
3642 { MOD_TABLE (MOD_0F18_REG_6
) },
3643 { MOD_TABLE (MOD_0F18_REG_7
) },
3645 /* REG_0F1E_MOD_3 */
3647 { "nopQ", { Ev
}, 0 },
3648 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3649 { "nopQ", { Ev
}, 0 },
3650 { "nopQ", { Ev
}, 0 },
3651 { "nopQ", { Ev
}, 0 },
3652 { "nopQ", { Ev
}, 0 },
3653 { "nopQ", { Ev
}, 0 },
3654 { RM_TABLE (RM_0F1E_MOD_3_REG_7
) },
3660 { MOD_TABLE (MOD_0F71_REG_2
) },
3662 { MOD_TABLE (MOD_0F71_REG_4
) },
3664 { MOD_TABLE (MOD_0F71_REG_6
) },
3670 { MOD_TABLE (MOD_0F72_REG_2
) },
3672 { MOD_TABLE (MOD_0F72_REG_4
) },
3674 { MOD_TABLE (MOD_0F72_REG_6
) },
3680 { MOD_TABLE (MOD_0F73_REG_2
) },
3681 { MOD_TABLE (MOD_0F73_REG_3
) },
3684 { MOD_TABLE (MOD_0F73_REG_6
) },
3685 { MOD_TABLE (MOD_0F73_REG_7
) },
3689 { "montmul", { { OP_0f07
, 0 } }, 0 },
3690 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3691 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3695 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3696 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3697 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3698 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3699 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3700 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3704 { MOD_TABLE (MOD_0FAE_REG_0
) },
3705 { MOD_TABLE (MOD_0FAE_REG_1
) },
3706 { MOD_TABLE (MOD_0FAE_REG_2
) },
3707 { MOD_TABLE (MOD_0FAE_REG_3
) },
3708 { MOD_TABLE (MOD_0FAE_REG_4
) },
3709 { MOD_TABLE (MOD_0FAE_REG_5
) },
3710 { MOD_TABLE (MOD_0FAE_REG_6
) },
3711 { MOD_TABLE (MOD_0FAE_REG_7
) },
3719 { "btQ", { Ev
, Ib
}, 0 },
3720 { "btsQ", { Evh1
, Ib
}, 0 },
3721 { "btrQ", { Evh1
, Ib
}, 0 },
3722 { "btcQ", { Evh1
, Ib
}, 0 },
3727 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3729 { MOD_TABLE (MOD_0FC7_REG_3
) },
3730 { MOD_TABLE (MOD_0FC7_REG_4
) },
3731 { MOD_TABLE (MOD_0FC7_REG_5
) },
3732 { MOD_TABLE (MOD_0FC7_REG_6
) },
3733 { MOD_TABLE (MOD_0FC7_REG_7
) },
3739 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3741 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3743 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3749 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3751 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3753 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3759 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3760 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3763 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3764 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3770 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3771 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3773 /* REG_VEX_0F38F3 */
3776 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3777 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3778 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3782 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3783 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3787 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3788 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3790 /* REG_XOP_TBM_01 */
3793 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3794 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3795 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3796 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3797 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3798 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3799 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3801 /* REG_XOP_TBM_02 */
3804 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3809 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3811 #define NEED_REG_TABLE
3812 #include "i386-dis-evex.h"
3813 #undef NEED_REG_TABLE
3816 static const struct dis386 prefix_table
[][4] = {
3819 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3820 { "pause", { XX
}, 0 },
3821 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3822 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3825 /* PREFIX_MOD_0_0F01_REG_5 */
3828 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3831 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3834 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3837 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3840 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3845 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3846 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3847 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3848 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3853 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3854 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3855 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3856 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3861 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3862 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3863 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3864 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3869 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3870 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3871 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3876 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3877 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3878 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3879 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3884 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3885 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3886 { "bndmov", { Ebnd
, Gbnd
}, 0 },
3887 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3892 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3893 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3894 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3895 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3900 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3901 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3902 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3903 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3908 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3909 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3910 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3911 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3916 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3917 { "cvttss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3918 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3919 { "cvttsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3924 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3925 { "cvtss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3926 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3927 { "cvtsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3932 { "ucomiss",{ XM
, EXd
}, 0 },
3934 { "ucomisd",{ XM
, EXq
}, 0 },
3939 { "comiss", { XM
, EXd
}, 0 },
3941 { "comisd", { XM
, EXq
}, 0 },
3946 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3947 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3948 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3949 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3954 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3955 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3960 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3961 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3966 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3967 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3968 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3969 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3974 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3975 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3976 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3977 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3982 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3983 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3984 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3985 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3990 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3991 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3992 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3997 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3998 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3999 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
4000 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
4005 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
4006 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
4007 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
4008 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
4013 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
4014 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
4015 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
4016 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
4021 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
4022 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
4023 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
4024 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
4029 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
4031 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
4036 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
4038 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
4043 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
4045 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
4052 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
4059 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
4064 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
4065 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
4066 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
4071 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4072 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4073 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4074 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4077 /* PREFIX_0F73_REG_3 */
4081 { "psrldq", { XS
, Ib
}, 0 },
4084 /* PREFIX_0F73_REG_7 */
4088 { "pslldq", { XS
, Ib
}, 0 },
4093 {"vmread", { Em
, Gm
}, 0 },
4095 {"extrq", { XS
, Ib
, Ib
}, 0 },
4096 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
4101 {"vmwrite", { Gm
, Em
}, 0 },
4103 {"extrq", { XM
, XS
}, 0 },
4104 {"insertq", { XM
, XS
}, 0 },
4111 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
4112 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
4119 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
4120 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
4125 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
4126 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
4127 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
4132 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
4133 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
4134 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
4137 /* PREFIX_0FAE_REG_0 */
4140 { "rdfsbase", { Ev
}, 0 },
4143 /* PREFIX_0FAE_REG_1 */
4146 { "rdgsbase", { Ev
}, 0 },
4149 /* PREFIX_0FAE_REG_2 */
4152 { "wrfsbase", { Ev
}, 0 },
4155 /* PREFIX_0FAE_REG_3 */
4158 { "wrgsbase", { Ev
}, 0 },
4161 /* PREFIX_MOD_0_0FAE_REG_4 */
4163 { "xsave", { FXSAVE
}, 0 },
4164 { "ptwrite%LQ", { Edq
}, 0 },
4167 /* PREFIX_MOD_3_0FAE_REG_4 */
4170 { "ptwrite%LQ", { Edq
}, 0 },
4173 /* PREFIX_MOD_0_0FAE_REG_5 */
4175 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4178 /* PREFIX_MOD_3_0FAE_REG_5 */
4180 { "lfence", { Skip_MODRM
}, 0 },
4181 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4184 /* PREFIX_0FAE_REG_6 */
4186 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4187 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4188 { "clwb", { Mb
}, PREFIX_OPCODE
},
4191 /* PREFIX_0FAE_REG_7 */
4193 { "clflush", { Mb
}, 0 },
4195 { "clflushopt", { Mb
}, 0 },
4201 { "popcntS", { Gv
, Ev
}, 0 },
4206 { "bsfS", { Gv
, Ev
}, 0 },
4207 { "tzcntS", { Gv
, Ev
}, 0 },
4208 { "bsfS", { Gv
, Ev
}, 0 },
4213 { "bsrS", { Gv
, Ev
}, 0 },
4214 { "lzcntS", { Gv
, Ev
}, 0 },
4215 { "bsrS", { Gv
, Ev
}, 0 },
4220 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4221 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4222 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4223 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4226 /* PREFIX_MOD_0_0FC3 */
4228 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4231 /* PREFIX_MOD_0_0FC7_REG_6 */
4233 { "vmptrld",{ Mq
}, 0 },
4234 { "vmxon", { Mq
}, 0 },
4235 { "vmclear",{ Mq
}, 0 },
4238 /* PREFIX_MOD_3_0FC7_REG_6 */
4240 { "rdrand", { Ev
}, 0 },
4242 { "rdrand", { Ev
}, 0 }
4245 /* PREFIX_MOD_3_0FC7_REG_7 */
4247 { "rdseed", { Ev
}, 0 },
4248 { "rdpid", { Em
}, 0 },
4249 { "rdseed", { Ev
}, 0 },
4256 { "addsubpd", { XM
, EXx
}, 0 },
4257 { "addsubps", { XM
, EXx
}, 0 },
4263 { "movq2dq",{ XM
, MS
}, 0 },
4264 { "movq", { EXqS
, XM
}, 0 },
4265 { "movdq2q",{ MX
, XS
}, 0 },
4271 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4272 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4273 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4278 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4280 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4288 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4293 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4295 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4302 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4309 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4316 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4323 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4330 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4337 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4344 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4351 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4358 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4365 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4372 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4379 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4386 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4393 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4400 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4407 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4414 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4421 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4428 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4435 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4442 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4449 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4456 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4463 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4470 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4477 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4484 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4491 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4498 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4505 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4512 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4519 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4526 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4533 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4538 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4543 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4548 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4553 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4558 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4563 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4570 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4577 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4584 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4591 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4598 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4605 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4610 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4612 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4613 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4618 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4620 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4621 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4628 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4633 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4634 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4635 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4643 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4650 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4657 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4664 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4671 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4678 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4685 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4692 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4699 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4706 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4713 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4720 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4727 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4734 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4741 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4748 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4755 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4762 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4769 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4776 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4783 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4790 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4795 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4802 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4809 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4816 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4819 /* PREFIX_VEX_0F10 */
4821 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4822 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4823 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4824 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4827 /* PREFIX_VEX_0F11 */
4829 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4830 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4831 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4832 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4835 /* PREFIX_VEX_0F12 */
4837 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4838 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4839 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4840 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4843 /* PREFIX_VEX_0F16 */
4845 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4846 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4847 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4850 /* PREFIX_VEX_0F2A */
4853 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4855 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4858 /* PREFIX_VEX_0F2C */
4861 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4863 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4866 /* PREFIX_VEX_0F2D */
4869 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4871 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4874 /* PREFIX_VEX_0F2E */
4876 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4878 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4881 /* PREFIX_VEX_0F2F */
4883 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4885 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4888 /* PREFIX_VEX_0F41 */
4890 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4892 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4895 /* PREFIX_VEX_0F42 */
4897 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4899 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4902 /* PREFIX_VEX_0F44 */
4904 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4906 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4909 /* PREFIX_VEX_0F45 */
4911 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4913 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4916 /* PREFIX_VEX_0F46 */
4918 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4920 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4923 /* PREFIX_VEX_0F47 */
4925 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4927 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4930 /* PREFIX_VEX_0F4A */
4932 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4934 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4937 /* PREFIX_VEX_0F4B */
4939 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4941 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4944 /* PREFIX_VEX_0F51 */
4946 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4947 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4948 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4949 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4952 /* PREFIX_VEX_0F52 */
4954 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4955 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4958 /* PREFIX_VEX_0F53 */
4960 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4961 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4964 /* PREFIX_VEX_0F58 */
4966 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4967 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4968 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4969 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4972 /* PREFIX_VEX_0F59 */
4974 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4975 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4976 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4977 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4980 /* PREFIX_VEX_0F5A */
4982 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4983 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4984 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
4985 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4988 /* PREFIX_VEX_0F5B */
4990 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4991 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4992 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4995 /* PREFIX_VEX_0F5C */
4997 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4998 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4999 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
5000 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
5003 /* PREFIX_VEX_0F5D */
5005 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
5006 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
5007 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
5008 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
5011 /* PREFIX_VEX_0F5E */
5013 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
5014 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
5015 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
5016 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
5019 /* PREFIX_VEX_0F5F */
5021 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
5022 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
5023 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
5024 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
5027 /* PREFIX_VEX_0F60 */
5031 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
5034 /* PREFIX_VEX_0F61 */
5038 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
5041 /* PREFIX_VEX_0F62 */
5045 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
5048 /* PREFIX_VEX_0F63 */
5052 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
5055 /* PREFIX_VEX_0F64 */
5059 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
5062 /* PREFIX_VEX_0F65 */
5066 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
5069 /* PREFIX_VEX_0F66 */
5073 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
5076 /* PREFIX_VEX_0F67 */
5080 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
5083 /* PREFIX_VEX_0F68 */
5087 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
5090 /* PREFIX_VEX_0F69 */
5094 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
5097 /* PREFIX_VEX_0F6A */
5101 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
5104 /* PREFIX_VEX_0F6B */
5108 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
5111 /* PREFIX_VEX_0F6C */
5115 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
5118 /* PREFIX_VEX_0F6D */
5122 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
5125 /* PREFIX_VEX_0F6E */
5129 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
5132 /* PREFIX_VEX_0F6F */
5135 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
5136 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
5139 /* PREFIX_VEX_0F70 */
5142 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
5143 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
5144 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
5147 /* PREFIX_VEX_0F71_REG_2 */
5151 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
5154 /* PREFIX_VEX_0F71_REG_4 */
5158 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
5161 /* PREFIX_VEX_0F71_REG_6 */
5165 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
5168 /* PREFIX_VEX_0F72_REG_2 */
5172 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
5175 /* PREFIX_VEX_0F72_REG_4 */
5179 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
5182 /* PREFIX_VEX_0F72_REG_6 */
5186 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
5189 /* PREFIX_VEX_0F73_REG_2 */
5193 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
5196 /* PREFIX_VEX_0F73_REG_3 */
5200 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
5203 /* PREFIX_VEX_0F73_REG_6 */
5207 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
5210 /* PREFIX_VEX_0F73_REG_7 */
5214 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
5217 /* PREFIX_VEX_0F74 */
5221 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
5224 /* PREFIX_VEX_0F75 */
5228 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5231 /* PREFIX_VEX_0F76 */
5235 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5238 /* PREFIX_VEX_0F77 */
5240 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5243 /* PREFIX_VEX_0F7C */
5247 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5248 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5251 /* PREFIX_VEX_0F7D */
5255 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5256 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5259 /* PREFIX_VEX_0F7E */
5262 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5263 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5266 /* PREFIX_VEX_0F7F */
5269 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5270 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5273 /* PREFIX_VEX_0F90 */
5275 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5277 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5280 /* PREFIX_VEX_0F91 */
5282 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5284 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5287 /* PREFIX_VEX_0F92 */
5289 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5291 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5292 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5295 /* PREFIX_VEX_0F93 */
5297 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5299 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5300 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5303 /* PREFIX_VEX_0F98 */
5305 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5307 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5310 /* PREFIX_VEX_0F99 */
5312 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5314 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5317 /* PREFIX_VEX_0FC2 */
5319 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5320 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5321 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5322 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5325 /* PREFIX_VEX_0FC4 */
5329 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5332 /* PREFIX_VEX_0FC5 */
5336 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5339 /* PREFIX_VEX_0FD0 */
5343 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5344 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5347 /* PREFIX_VEX_0FD1 */
5351 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5354 /* PREFIX_VEX_0FD2 */
5358 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5361 /* PREFIX_VEX_0FD3 */
5365 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5368 /* PREFIX_VEX_0FD4 */
5372 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5375 /* PREFIX_VEX_0FD5 */
5379 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5382 /* PREFIX_VEX_0FD6 */
5386 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5389 /* PREFIX_VEX_0FD7 */
5393 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5396 /* PREFIX_VEX_0FD8 */
5400 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5403 /* PREFIX_VEX_0FD9 */
5407 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5410 /* PREFIX_VEX_0FDA */
5414 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5417 /* PREFIX_VEX_0FDB */
5421 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5424 /* PREFIX_VEX_0FDC */
5428 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5431 /* PREFIX_VEX_0FDD */
5435 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5438 /* PREFIX_VEX_0FDE */
5442 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5445 /* PREFIX_VEX_0FDF */
5449 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5452 /* PREFIX_VEX_0FE0 */
5456 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5459 /* PREFIX_VEX_0FE1 */
5463 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5466 /* PREFIX_VEX_0FE2 */
5470 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5473 /* PREFIX_VEX_0FE3 */
5477 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5480 /* PREFIX_VEX_0FE4 */
5484 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5487 /* PREFIX_VEX_0FE5 */
5491 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5494 /* PREFIX_VEX_0FE6 */
5497 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5498 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5499 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5502 /* PREFIX_VEX_0FE7 */
5506 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5509 /* PREFIX_VEX_0FE8 */
5513 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5516 /* PREFIX_VEX_0FE9 */
5520 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5523 /* PREFIX_VEX_0FEA */
5527 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5530 /* PREFIX_VEX_0FEB */
5534 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5537 /* PREFIX_VEX_0FEC */
5541 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5544 /* PREFIX_VEX_0FED */
5548 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5551 /* PREFIX_VEX_0FEE */
5555 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5558 /* PREFIX_VEX_0FEF */
5562 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5565 /* PREFIX_VEX_0FF0 */
5570 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5573 /* PREFIX_VEX_0FF1 */
5577 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5580 /* PREFIX_VEX_0FF2 */
5584 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5587 /* PREFIX_VEX_0FF3 */
5591 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5594 /* PREFIX_VEX_0FF4 */
5598 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5601 /* PREFIX_VEX_0FF5 */
5605 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5608 /* PREFIX_VEX_0FF6 */
5612 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5615 /* PREFIX_VEX_0FF7 */
5619 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5622 /* PREFIX_VEX_0FF8 */
5626 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5629 /* PREFIX_VEX_0FF9 */
5633 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5636 /* PREFIX_VEX_0FFA */
5640 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5643 /* PREFIX_VEX_0FFB */
5647 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5650 /* PREFIX_VEX_0FFC */
5654 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5657 /* PREFIX_VEX_0FFD */
5661 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5664 /* PREFIX_VEX_0FFE */
5668 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5671 /* PREFIX_VEX_0F3800 */
5675 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5678 /* PREFIX_VEX_0F3801 */
5682 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5685 /* PREFIX_VEX_0F3802 */
5689 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5692 /* PREFIX_VEX_0F3803 */
5696 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5699 /* PREFIX_VEX_0F3804 */
5703 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5706 /* PREFIX_VEX_0F3805 */
5710 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5713 /* PREFIX_VEX_0F3806 */
5717 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5720 /* PREFIX_VEX_0F3807 */
5724 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5727 /* PREFIX_VEX_0F3808 */
5731 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5734 /* PREFIX_VEX_0F3809 */
5738 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5741 /* PREFIX_VEX_0F380A */
5745 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5748 /* PREFIX_VEX_0F380B */
5752 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5755 /* PREFIX_VEX_0F380C */
5759 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5762 /* PREFIX_VEX_0F380D */
5766 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5769 /* PREFIX_VEX_0F380E */
5773 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5776 /* PREFIX_VEX_0F380F */
5780 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5783 /* PREFIX_VEX_0F3813 */
5787 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5790 /* PREFIX_VEX_0F3816 */
5794 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5797 /* PREFIX_VEX_0F3817 */
5801 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5804 /* PREFIX_VEX_0F3818 */
5808 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5811 /* PREFIX_VEX_0F3819 */
5815 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5818 /* PREFIX_VEX_0F381A */
5822 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5825 /* PREFIX_VEX_0F381C */
5829 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5832 /* PREFIX_VEX_0F381D */
5836 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5839 /* PREFIX_VEX_0F381E */
5843 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5846 /* PREFIX_VEX_0F3820 */
5850 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5853 /* PREFIX_VEX_0F3821 */
5857 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5860 /* PREFIX_VEX_0F3822 */
5864 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5867 /* PREFIX_VEX_0F3823 */
5871 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5874 /* PREFIX_VEX_0F3824 */
5878 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5881 /* PREFIX_VEX_0F3825 */
5885 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5888 /* PREFIX_VEX_0F3828 */
5892 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5895 /* PREFIX_VEX_0F3829 */
5899 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5902 /* PREFIX_VEX_0F382A */
5906 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5909 /* PREFIX_VEX_0F382B */
5913 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5916 /* PREFIX_VEX_0F382C */
5920 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5923 /* PREFIX_VEX_0F382D */
5927 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5930 /* PREFIX_VEX_0F382E */
5934 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5937 /* PREFIX_VEX_0F382F */
5941 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5944 /* PREFIX_VEX_0F3830 */
5948 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5951 /* PREFIX_VEX_0F3831 */
5955 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5958 /* PREFIX_VEX_0F3832 */
5962 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5965 /* PREFIX_VEX_0F3833 */
5969 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5972 /* PREFIX_VEX_0F3834 */
5976 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5979 /* PREFIX_VEX_0F3835 */
5983 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5986 /* PREFIX_VEX_0F3836 */
5990 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5993 /* PREFIX_VEX_0F3837 */
5997 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
6000 /* PREFIX_VEX_0F3838 */
6004 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
6007 /* PREFIX_VEX_0F3839 */
6011 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
6014 /* PREFIX_VEX_0F383A */
6018 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
6021 /* PREFIX_VEX_0F383B */
6025 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
6028 /* PREFIX_VEX_0F383C */
6032 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
6035 /* PREFIX_VEX_0F383D */
6039 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
6042 /* PREFIX_VEX_0F383E */
6046 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
6049 /* PREFIX_VEX_0F383F */
6053 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
6056 /* PREFIX_VEX_0F3840 */
6060 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
6063 /* PREFIX_VEX_0F3841 */
6067 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
6070 /* PREFIX_VEX_0F3845 */
6074 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
6077 /* PREFIX_VEX_0F3846 */
6081 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
6084 /* PREFIX_VEX_0F3847 */
6088 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
6091 /* PREFIX_VEX_0F3858 */
6095 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
6098 /* PREFIX_VEX_0F3859 */
6102 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
6105 /* PREFIX_VEX_0F385A */
6109 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
6112 /* PREFIX_VEX_0F3878 */
6116 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
6119 /* PREFIX_VEX_0F3879 */
6123 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
6126 /* PREFIX_VEX_0F388C */
6130 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
6133 /* PREFIX_VEX_0F388E */
6137 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
6140 /* PREFIX_VEX_0F3890 */
6144 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6147 /* PREFIX_VEX_0F3891 */
6151 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6154 /* PREFIX_VEX_0F3892 */
6158 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6161 /* PREFIX_VEX_0F3893 */
6165 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6168 /* PREFIX_VEX_0F3896 */
6172 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6175 /* PREFIX_VEX_0F3897 */
6179 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6182 /* PREFIX_VEX_0F3898 */
6186 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6189 /* PREFIX_VEX_0F3899 */
6193 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6196 /* PREFIX_VEX_0F389A */
6200 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6203 /* PREFIX_VEX_0F389B */
6207 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6210 /* PREFIX_VEX_0F389C */
6214 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6217 /* PREFIX_VEX_0F389D */
6221 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6224 /* PREFIX_VEX_0F389E */
6228 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6231 /* PREFIX_VEX_0F389F */
6235 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6238 /* PREFIX_VEX_0F38A6 */
6242 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6246 /* PREFIX_VEX_0F38A7 */
6250 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6253 /* PREFIX_VEX_0F38A8 */
6257 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6260 /* PREFIX_VEX_0F38A9 */
6264 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6267 /* PREFIX_VEX_0F38AA */
6271 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6274 /* PREFIX_VEX_0F38AB */
6278 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6281 /* PREFIX_VEX_0F38AC */
6285 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6288 /* PREFIX_VEX_0F38AD */
6292 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6295 /* PREFIX_VEX_0F38AE */
6299 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6302 /* PREFIX_VEX_0F38AF */
6306 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6309 /* PREFIX_VEX_0F38B6 */
6313 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6316 /* PREFIX_VEX_0F38B7 */
6320 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6323 /* PREFIX_VEX_0F38B8 */
6327 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6330 /* PREFIX_VEX_0F38B9 */
6334 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6337 /* PREFIX_VEX_0F38BA */
6341 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6344 /* PREFIX_VEX_0F38BB */
6348 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6351 /* PREFIX_VEX_0F38BC */
6355 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6358 /* PREFIX_VEX_0F38BD */
6362 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6365 /* PREFIX_VEX_0F38BE */
6369 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6372 /* PREFIX_VEX_0F38BF */
6376 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6379 /* PREFIX_VEX_0F38CF */
6383 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6386 /* PREFIX_VEX_0F38DB */
6390 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6393 /* PREFIX_VEX_0F38DC */
6397 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6400 /* PREFIX_VEX_0F38DD */
6404 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6407 /* PREFIX_VEX_0F38DE */
6411 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6414 /* PREFIX_VEX_0F38DF */
6418 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6421 /* PREFIX_VEX_0F38F2 */
6423 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6426 /* PREFIX_VEX_0F38F3_REG_1 */
6428 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6431 /* PREFIX_VEX_0F38F3_REG_2 */
6433 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6436 /* PREFIX_VEX_0F38F3_REG_3 */
6438 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6441 /* PREFIX_VEX_0F38F5 */
6443 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6444 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6446 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6449 /* PREFIX_VEX_0F38F6 */
6454 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6457 /* PREFIX_VEX_0F38F7 */
6459 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6460 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6461 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6462 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6465 /* PREFIX_VEX_0F3A00 */
6469 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6472 /* PREFIX_VEX_0F3A01 */
6476 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6479 /* PREFIX_VEX_0F3A02 */
6483 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6486 /* PREFIX_VEX_0F3A04 */
6490 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6493 /* PREFIX_VEX_0F3A05 */
6497 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6500 /* PREFIX_VEX_0F3A06 */
6504 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6507 /* PREFIX_VEX_0F3A08 */
6511 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6514 /* PREFIX_VEX_0F3A09 */
6518 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6521 /* PREFIX_VEX_0F3A0A */
6525 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6528 /* PREFIX_VEX_0F3A0B */
6532 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6535 /* PREFIX_VEX_0F3A0C */
6539 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6542 /* PREFIX_VEX_0F3A0D */
6546 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6549 /* PREFIX_VEX_0F3A0E */
6553 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6556 /* PREFIX_VEX_0F3A0F */
6560 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6563 /* PREFIX_VEX_0F3A14 */
6567 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6570 /* PREFIX_VEX_0F3A15 */
6574 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6577 /* PREFIX_VEX_0F3A16 */
6581 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6584 /* PREFIX_VEX_0F3A17 */
6588 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6591 /* PREFIX_VEX_0F3A18 */
6595 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6598 /* PREFIX_VEX_0F3A19 */
6602 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6605 /* PREFIX_VEX_0F3A1D */
6609 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6612 /* PREFIX_VEX_0F3A20 */
6616 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6619 /* PREFIX_VEX_0F3A21 */
6623 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6626 /* PREFIX_VEX_0F3A22 */
6630 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6633 /* PREFIX_VEX_0F3A30 */
6637 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6640 /* PREFIX_VEX_0F3A31 */
6644 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6647 /* PREFIX_VEX_0F3A32 */
6651 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6654 /* PREFIX_VEX_0F3A33 */
6658 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6661 /* PREFIX_VEX_0F3A38 */
6665 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6668 /* PREFIX_VEX_0F3A39 */
6672 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6675 /* PREFIX_VEX_0F3A40 */
6679 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6682 /* PREFIX_VEX_0F3A41 */
6686 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6689 /* PREFIX_VEX_0F3A42 */
6693 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6696 /* PREFIX_VEX_0F3A44 */
6700 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6703 /* PREFIX_VEX_0F3A46 */
6707 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6710 /* PREFIX_VEX_0F3A48 */
6714 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6717 /* PREFIX_VEX_0F3A49 */
6721 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6724 /* PREFIX_VEX_0F3A4A */
6728 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6731 /* PREFIX_VEX_0F3A4B */
6735 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6738 /* PREFIX_VEX_0F3A4C */
6742 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6745 /* PREFIX_VEX_0F3A5C */
6749 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6752 /* PREFIX_VEX_0F3A5D */
6756 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6759 /* PREFIX_VEX_0F3A5E */
6763 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6766 /* PREFIX_VEX_0F3A5F */
6770 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6773 /* PREFIX_VEX_0F3A60 */
6777 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6781 /* PREFIX_VEX_0F3A61 */
6785 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6788 /* PREFIX_VEX_0F3A62 */
6792 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6795 /* PREFIX_VEX_0F3A63 */
6799 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6802 /* PREFIX_VEX_0F3A68 */
6806 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6809 /* PREFIX_VEX_0F3A69 */
6813 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6816 /* PREFIX_VEX_0F3A6A */
6820 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6823 /* PREFIX_VEX_0F3A6B */
6827 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6830 /* PREFIX_VEX_0F3A6C */
6834 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6837 /* PREFIX_VEX_0F3A6D */
6841 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6844 /* PREFIX_VEX_0F3A6E */
6848 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6851 /* PREFIX_VEX_0F3A6F */
6855 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6858 /* PREFIX_VEX_0F3A78 */
6862 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6865 /* PREFIX_VEX_0F3A79 */
6869 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6872 /* PREFIX_VEX_0F3A7A */
6876 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6879 /* PREFIX_VEX_0F3A7B */
6883 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6886 /* PREFIX_VEX_0F3A7C */
6890 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6894 /* PREFIX_VEX_0F3A7D */
6898 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6901 /* PREFIX_VEX_0F3A7E */
6905 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6908 /* PREFIX_VEX_0F3A7F */
6912 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6915 /* PREFIX_VEX_0F3ACE */
6919 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6922 /* PREFIX_VEX_0F3ACF */
6926 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6929 /* PREFIX_VEX_0F3ADF */
6933 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6936 /* PREFIX_VEX_0F3AF0 */
6941 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6944 #define NEED_PREFIX_TABLE
6945 #include "i386-dis-evex.h"
6946 #undef NEED_PREFIX_TABLE
6949 static const struct dis386 x86_64_table
[][2] = {
6952 { "pushP", { es
}, 0 },
6957 { "popP", { es
}, 0 },
6962 { "pushP", { cs
}, 0 },
6967 { "pushP", { ss
}, 0 },
6972 { "popP", { ss
}, 0 },
6977 { "pushP", { ds
}, 0 },
6982 { "popP", { ds
}, 0 },
6987 { "daa", { XX
}, 0 },
6992 { "das", { XX
}, 0 },
6997 { "aaa", { XX
}, 0 },
7002 { "aas", { XX
}, 0 },
7007 { "pushaP", { XX
}, 0 },
7012 { "popaP", { XX
}, 0 },
7017 { MOD_TABLE (MOD_62_32BIT
) },
7018 { EVEX_TABLE (EVEX_0F
) },
7023 { "arpl", { Ew
, Gw
}, 0 },
7024 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
7029 { "ins{R|}", { Yzr
, indirDX
}, 0 },
7030 { "ins{G|}", { Yzr
, indirDX
}, 0 },
7035 { "outs{R|}", { indirDXr
, Xz
}, 0 },
7036 { "outs{G|}", { indirDXr
, Xz
}, 0 },
7041 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
7042 { REG_TABLE (REG_80
) },
7047 { "Jcall{T|}", { Ap
}, 0 },
7052 { MOD_TABLE (MOD_C4_32BIT
) },
7053 { VEX_C4_TABLE (VEX_0F
) },
7058 { MOD_TABLE (MOD_C5_32BIT
) },
7059 { VEX_C5_TABLE (VEX_0F
) },
7064 { "into", { XX
}, 0 },
7069 { "aam", { Ib
}, 0 },
7074 { "aad", { Ib
}, 0 },
7079 { "callP", { Jv
, BND
}, 0 },
7080 { "call@", { Jv
, BND
}, 0 }
7085 { "jmpP", { Jv
, BND
}, 0 },
7086 { "jmp@", { Jv
, BND
}, 0 }
7091 { "Jjmp{T|}", { Ap
}, 0 },
7094 /* X86_64_0F01_REG_0 */
7096 { "sgdt{Q|IQ}", { M
}, 0 },
7097 { "sgdt", { M
}, 0 },
7100 /* X86_64_0F01_REG_1 */
7102 { "sidt{Q|IQ}", { M
}, 0 },
7103 { "sidt", { M
}, 0 },
7106 /* X86_64_0F01_REG_2 */
7108 { "lgdt{Q|Q}", { M
}, 0 },
7109 { "lgdt", { M
}, 0 },
7112 /* X86_64_0F01_REG_3 */
7114 { "lidt{Q|Q}", { M
}, 0 },
7115 { "lidt", { M
}, 0 },
7119 static const struct dis386 three_byte_table
[][256] = {
7121 /* THREE_BYTE_0F38 */
7124 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
7125 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
7126 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
7127 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
7128 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
7129 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
7130 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
7131 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
7133 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
7134 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
7135 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
7136 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
7142 { PREFIX_TABLE (PREFIX_0F3810
) },
7146 { PREFIX_TABLE (PREFIX_0F3814
) },
7147 { PREFIX_TABLE (PREFIX_0F3815
) },
7149 { PREFIX_TABLE (PREFIX_0F3817
) },
7155 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7156 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7157 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7160 { PREFIX_TABLE (PREFIX_0F3820
) },
7161 { PREFIX_TABLE (PREFIX_0F3821
) },
7162 { PREFIX_TABLE (PREFIX_0F3822
) },
7163 { PREFIX_TABLE (PREFIX_0F3823
) },
7164 { PREFIX_TABLE (PREFIX_0F3824
) },
7165 { PREFIX_TABLE (PREFIX_0F3825
) },
7169 { PREFIX_TABLE (PREFIX_0F3828
) },
7170 { PREFIX_TABLE (PREFIX_0F3829
) },
7171 { PREFIX_TABLE (PREFIX_0F382A
) },
7172 { PREFIX_TABLE (PREFIX_0F382B
) },
7178 { PREFIX_TABLE (PREFIX_0F3830
) },
7179 { PREFIX_TABLE (PREFIX_0F3831
) },
7180 { PREFIX_TABLE (PREFIX_0F3832
) },
7181 { PREFIX_TABLE (PREFIX_0F3833
) },
7182 { PREFIX_TABLE (PREFIX_0F3834
) },
7183 { PREFIX_TABLE (PREFIX_0F3835
) },
7185 { PREFIX_TABLE (PREFIX_0F3837
) },
7187 { PREFIX_TABLE (PREFIX_0F3838
) },
7188 { PREFIX_TABLE (PREFIX_0F3839
) },
7189 { PREFIX_TABLE (PREFIX_0F383A
) },
7190 { PREFIX_TABLE (PREFIX_0F383B
) },
7191 { PREFIX_TABLE (PREFIX_0F383C
) },
7192 { PREFIX_TABLE (PREFIX_0F383D
) },
7193 { PREFIX_TABLE (PREFIX_0F383E
) },
7194 { PREFIX_TABLE (PREFIX_0F383F
) },
7196 { PREFIX_TABLE (PREFIX_0F3840
) },
7197 { PREFIX_TABLE (PREFIX_0F3841
) },
7268 { PREFIX_TABLE (PREFIX_0F3880
) },
7269 { PREFIX_TABLE (PREFIX_0F3881
) },
7270 { PREFIX_TABLE (PREFIX_0F3882
) },
7349 { PREFIX_TABLE (PREFIX_0F38C8
) },
7350 { PREFIX_TABLE (PREFIX_0F38C9
) },
7351 { PREFIX_TABLE (PREFIX_0F38CA
) },
7352 { PREFIX_TABLE (PREFIX_0F38CB
) },
7353 { PREFIX_TABLE (PREFIX_0F38CC
) },
7354 { PREFIX_TABLE (PREFIX_0F38CD
) },
7356 { PREFIX_TABLE (PREFIX_0F38CF
) },
7370 { PREFIX_TABLE (PREFIX_0F38DB
) },
7371 { PREFIX_TABLE (PREFIX_0F38DC
) },
7372 { PREFIX_TABLE (PREFIX_0F38DD
) },
7373 { PREFIX_TABLE (PREFIX_0F38DE
) },
7374 { PREFIX_TABLE (PREFIX_0F38DF
) },
7394 { PREFIX_TABLE (PREFIX_0F38F0
) },
7395 { PREFIX_TABLE (PREFIX_0F38F1
) },
7399 { PREFIX_TABLE (PREFIX_0F38F5
) },
7400 { PREFIX_TABLE (PREFIX_0F38F6
) },
7412 /* THREE_BYTE_0F3A */
7424 { PREFIX_TABLE (PREFIX_0F3A08
) },
7425 { PREFIX_TABLE (PREFIX_0F3A09
) },
7426 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7427 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7428 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7429 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7430 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7431 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7437 { PREFIX_TABLE (PREFIX_0F3A14
) },
7438 { PREFIX_TABLE (PREFIX_0F3A15
) },
7439 { PREFIX_TABLE (PREFIX_0F3A16
) },
7440 { PREFIX_TABLE (PREFIX_0F3A17
) },
7451 { PREFIX_TABLE (PREFIX_0F3A20
) },
7452 { PREFIX_TABLE (PREFIX_0F3A21
) },
7453 { PREFIX_TABLE (PREFIX_0F3A22
) },
7487 { PREFIX_TABLE (PREFIX_0F3A40
) },
7488 { PREFIX_TABLE (PREFIX_0F3A41
) },
7489 { PREFIX_TABLE (PREFIX_0F3A42
) },
7491 { PREFIX_TABLE (PREFIX_0F3A44
) },
7523 { PREFIX_TABLE (PREFIX_0F3A60
) },
7524 { PREFIX_TABLE (PREFIX_0F3A61
) },
7525 { PREFIX_TABLE (PREFIX_0F3A62
) },
7526 { PREFIX_TABLE (PREFIX_0F3A63
) },
7644 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7646 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7647 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7665 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7705 static const struct dis386 xop_table
[][256] = {
7858 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7859 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7860 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7868 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7869 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7876 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7877 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7878 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7886 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7887 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7891 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7892 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7895 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7913 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7925 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7926 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7927 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7928 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7938 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7939 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7940 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7941 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7974 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7975 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7976 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7977 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8001 { REG_TABLE (REG_XOP_TBM_01
) },
8002 { REG_TABLE (REG_XOP_TBM_02
) },
8020 { REG_TABLE (REG_XOP_LWPCB
) },
8144 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8145 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8146 { "vfrczss", { XM
, EXd
}, 0 },
8147 { "vfrczsd", { XM
, EXq
}, 0 },
8162 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8163 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8164 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8165 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8166 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8167 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8168 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8169 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8171 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8172 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8173 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8174 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8217 { "vphaddbw", { XM
, EXxmm
}, 0 },
8218 { "vphaddbd", { XM
, EXxmm
}, 0 },
8219 { "vphaddbq", { XM
, EXxmm
}, 0 },
8222 { "vphaddwd", { XM
, EXxmm
}, 0 },
8223 { "vphaddwq", { XM
, EXxmm
}, 0 },
8228 { "vphadddq", { XM
, EXxmm
}, 0 },
8235 { "vphaddubw", { XM
, EXxmm
}, 0 },
8236 { "vphaddubd", { XM
, EXxmm
}, 0 },
8237 { "vphaddubq", { XM
, EXxmm
}, 0 },
8240 { "vphadduwd", { XM
, EXxmm
}, 0 },
8241 { "vphadduwq", { XM
, EXxmm
}, 0 },
8246 { "vphaddudq", { XM
, EXxmm
}, 0 },
8253 { "vphsubbw", { XM
, EXxmm
}, 0 },
8254 { "vphsubwd", { XM
, EXxmm
}, 0 },
8255 { "vphsubdq", { XM
, EXxmm
}, 0 },
8309 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8311 { REG_TABLE (REG_XOP_LWP
) },
8581 static const struct dis386 vex_table
[][256] = {
8603 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8605 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8606 { MOD_TABLE (MOD_VEX_0F13
) },
8607 { VEX_W_TABLE (VEX_W_0F14
) },
8608 { VEX_W_TABLE (VEX_W_0F15
) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8610 { MOD_TABLE (MOD_VEX_0F17
) },
8630 { VEX_W_TABLE (VEX_W_0F28
) },
8631 { VEX_W_TABLE (VEX_W_0F29
) },
8632 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8633 { MOD_TABLE (MOD_VEX_0F2B
) },
8634 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8635 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8636 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8637 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8663 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8675 { MOD_TABLE (MOD_VEX_0F50
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8679 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8680 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8681 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8682 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8684 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8712 { REG_TABLE (REG_VEX_0F71
) },
8713 { REG_TABLE (REG_VEX_0F72
) },
8714 { REG_TABLE (REG_VEX_0F73
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8780 { REG_TABLE (REG_VEX_0FAE
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8807 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8819 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8822 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8823 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8832 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8833 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8834 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8835 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8837 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8838 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8840 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8841 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8842 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8843 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8844 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8849 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8851 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8852 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8855 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8856 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8876 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8877 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8878 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8879 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8880 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8881 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9149 { REG_TABLE (REG_VEX_0F38F3
) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9167 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9168 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9169 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9171 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9172 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9179 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9180 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9181 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9182 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9199 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9221 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9222 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9223 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9224 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9230 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9231 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9239 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9240 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9241 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9243 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9245 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9248 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9249 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9250 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9251 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9252 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9270 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9271 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9272 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9273 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9275 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9276 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9277 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9278 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9284 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9286 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9288 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9289 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9290 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9291 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9302 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9303 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9304 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9305 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9306 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9307 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9308 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9309 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9398 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9399 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9417 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9437 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9457 #define NEED_OPCODE_TABLE
9458 #include "i386-dis-evex.h"
9459 #undef NEED_OPCODE_TABLE
9460 static const struct dis386 vex_len_table
[][2] = {
9461 /* VEX_LEN_0F10_P_1 */
9463 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9464 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9467 /* VEX_LEN_0F10_P_3 */
9469 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9470 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9473 /* VEX_LEN_0F11_P_1 */
9475 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9476 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9479 /* VEX_LEN_0F11_P_3 */
9481 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9482 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9485 /* VEX_LEN_0F12_P_0_M_0 */
9487 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9490 /* VEX_LEN_0F12_P_0_M_1 */
9492 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9495 /* VEX_LEN_0F12_P_2 */
9497 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9500 /* VEX_LEN_0F13_M_0 */
9502 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9505 /* VEX_LEN_0F16_P_0_M_0 */
9507 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9510 /* VEX_LEN_0F16_P_0_M_1 */
9512 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9515 /* VEX_LEN_0F16_P_2 */
9517 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9520 /* VEX_LEN_0F17_M_0 */
9522 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9525 /* VEX_LEN_0F2A_P_1 */
9527 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9528 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9531 /* VEX_LEN_0F2A_P_3 */
9533 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9534 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9537 /* VEX_LEN_0F2C_P_1 */
9539 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9540 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9543 /* VEX_LEN_0F2C_P_3 */
9545 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9546 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9549 /* VEX_LEN_0F2D_P_1 */
9551 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9552 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9555 /* VEX_LEN_0F2D_P_3 */
9557 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9558 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9561 /* VEX_LEN_0F2E_P_0 */
9563 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9564 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9567 /* VEX_LEN_0F2E_P_2 */
9569 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9570 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9573 /* VEX_LEN_0F2F_P_0 */
9575 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9576 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9579 /* VEX_LEN_0F2F_P_2 */
9581 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9582 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9585 /* VEX_LEN_0F41_P_0 */
9588 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9590 /* VEX_LEN_0F41_P_2 */
9593 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9595 /* VEX_LEN_0F42_P_0 */
9598 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9600 /* VEX_LEN_0F42_P_2 */
9603 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9605 /* VEX_LEN_0F44_P_0 */
9607 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9609 /* VEX_LEN_0F44_P_2 */
9611 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9613 /* VEX_LEN_0F45_P_0 */
9616 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9618 /* VEX_LEN_0F45_P_2 */
9621 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9623 /* VEX_LEN_0F46_P_0 */
9626 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9628 /* VEX_LEN_0F46_P_2 */
9631 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9633 /* VEX_LEN_0F47_P_0 */
9636 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9638 /* VEX_LEN_0F47_P_2 */
9641 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9643 /* VEX_LEN_0F4A_P_0 */
9646 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9648 /* VEX_LEN_0F4A_P_2 */
9651 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9653 /* VEX_LEN_0F4B_P_0 */
9656 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9658 /* VEX_LEN_0F4B_P_2 */
9661 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9664 /* VEX_LEN_0F51_P_1 */
9666 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9667 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9670 /* VEX_LEN_0F51_P_3 */
9672 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9673 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9676 /* VEX_LEN_0F52_P_1 */
9678 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9679 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9682 /* VEX_LEN_0F53_P_1 */
9684 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9685 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9688 /* VEX_LEN_0F58_P_1 */
9690 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9691 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9694 /* VEX_LEN_0F58_P_3 */
9696 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9697 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9700 /* VEX_LEN_0F59_P_1 */
9702 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9703 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9706 /* VEX_LEN_0F59_P_3 */
9708 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9709 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9712 /* VEX_LEN_0F5A_P_1 */
9714 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9715 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9718 /* VEX_LEN_0F5A_P_3 */
9720 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9721 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9724 /* VEX_LEN_0F5C_P_1 */
9726 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9727 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9730 /* VEX_LEN_0F5C_P_3 */
9732 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9733 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9736 /* VEX_LEN_0F5D_P_1 */
9738 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9739 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9742 /* VEX_LEN_0F5D_P_3 */
9744 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9745 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9748 /* VEX_LEN_0F5E_P_1 */
9750 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9751 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9754 /* VEX_LEN_0F5E_P_3 */
9756 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9757 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9760 /* VEX_LEN_0F5F_P_1 */
9762 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9763 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9766 /* VEX_LEN_0F5F_P_3 */
9768 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9769 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9772 /* VEX_LEN_0F6E_P_2 */
9774 { "vmovK", { XMScalar
, Edq
}, 0 },
9775 { "vmovK", { XMScalar
, Edq
}, 0 },
9778 /* VEX_LEN_0F7E_P_1 */
9780 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9781 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9784 /* VEX_LEN_0F7E_P_2 */
9786 { "vmovK", { Edq
, XMScalar
}, 0 },
9787 { "vmovK", { Edq
, XMScalar
}, 0 },
9790 /* VEX_LEN_0F90_P_0 */
9792 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9795 /* VEX_LEN_0F90_P_2 */
9797 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9800 /* VEX_LEN_0F91_P_0 */
9802 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9805 /* VEX_LEN_0F91_P_2 */
9807 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9810 /* VEX_LEN_0F92_P_0 */
9812 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9815 /* VEX_LEN_0F92_P_2 */
9817 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9820 /* VEX_LEN_0F92_P_3 */
9822 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9825 /* VEX_LEN_0F93_P_0 */
9827 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9830 /* VEX_LEN_0F93_P_2 */
9832 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9835 /* VEX_LEN_0F93_P_3 */
9837 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9840 /* VEX_LEN_0F98_P_0 */
9842 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9845 /* VEX_LEN_0F98_P_2 */
9847 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9850 /* VEX_LEN_0F99_P_0 */
9852 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9855 /* VEX_LEN_0F99_P_2 */
9857 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9860 /* VEX_LEN_0FAE_R_2_M_0 */
9862 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9865 /* VEX_LEN_0FAE_R_3_M_0 */
9867 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9870 /* VEX_LEN_0FC2_P_1 */
9872 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9873 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9876 /* VEX_LEN_0FC2_P_3 */
9878 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9879 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9882 /* VEX_LEN_0FC4_P_2 */
9884 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9887 /* VEX_LEN_0FC5_P_2 */
9889 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9892 /* VEX_LEN_0FD6_P_2 */
9894 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9895 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9898 /* VEX_LEN_0FF7_P_2 */
9900 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9903 /* VEX_LEN_0F3816_P_2 */
9906 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9909 /* VEX_LEN_0F3819_P_2 */
9912 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9915 /* VEX_LEN_0F381A_P_2_M_0 */
9918 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9921 /* VEX_LEN_0F3836_P_2 */
9924 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9927 /* VEX_LEN_0F3841_P_2 */
9929 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9932 /* VEX_LEN_0F385A_P_2_M_0 */
9935 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9938 /* VEX_LEN_0F38DB_P_2 */
9940 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9943 /* VEX_LEN_0F38F2_P_0 */
9945 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9948 /* VEX_LEN_0F38F3_R_1_P_0 */
9950 { "blsrS", { VexGdq
, Edq
}, 0 },
9953 /* VEX_LEN_0F38F3_R_2_P_0 */
9955 { "blsmskS", { VexGdq
, Edq
}, 0 },
9958 /* VEX_LEN_0F38F3_R_3_P_0 */
9960 { "blsiS", { VexGdq
, Edq
}, 0 },
9963 /* VEX_LEN_0F38F5_P_0 */
9965 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9968 /* VEX_LEN_0F38F5_P_1 */
9970 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9973 /* VEX_LEN_0F38F5_P_3 */
9975 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9978 /* VEX_LEN_0F38F6_P_3 */
9980 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9983 /* VEX_LEN_0F38F7_P_0 */
9985 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9988 /* VEX_LEN_0F38F7_P_1 */
9990 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9993 /* VEX_LEN_0F38F7_P_2 */
9995 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9998 /* VEX_LEN_0F38F7_P_3 */
10000 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
10003 /* VEX_LEN_0F3A00_P_2 */
10006 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10009 /* VEX_LEN_0F3A01_P_2 */
10012 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10015 /* VEX_LEN_0F3A06_P_2 */
10018 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10021 /* VEX_LEN_0F3A0A_P_2 */
10023 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10024 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10027 /* VEX_LEN_0F3A0B_P_2 */
10029 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10030 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10033 /* VEX_LEN_0F3A14_P_2 */
10035 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10038 /* VEX_LEN_0F3A15_P_2 */
10040 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10043 /* VEX_LEN_0F3A16_P_2 */
10045 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
10048 /* VEX_LEN_0F3A17_P_2 */
10050 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
10053 /* VEX_LEN_0F3A18_P_2 */
10056 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10059 /* VEX_LEN_0F3A19_P_2 */
10062 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10065 /* VEX_LEN_0F3A20_P_2 */
10067 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10070 /* VEX_LEN_0F3A21_P_2 */
10072 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10075 /* VEX_LEN_0F3A22_P_2 */
10077 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
10080 /* VEX_LEN_0F3A30_P_2 */
10082 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10085 /* VEX_LEN_0F3A31_P_2 */
10087 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10090 /* VEX_LEN_0F3A32_P_2 */
10092 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10095 /* VEX_LEN_0F3A33_P_2 */
10097 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10100 /* VEX_LEN_0F3A38_P_2 */
10103 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10106 /* VEX_LEN_0F3A39_P_2 */
10109 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10112 /* VEX_LEN_0F3A41_P_2 */
10114 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10117 /* VEX_LEN_0F3A46_P_2 */
10120 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10123 /* VEX_LEN_0F3A60_P_2 */
10125 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
10128 /* VEX_LEN_0F3A61_P_2 */
10130 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
10133 /* VEX_LEN_0F3A62_P_2 */
10135 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10138 /* VEX_LEN_0F3A63_P_2 */
10140 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10143 /* VEX_LEN_0F3A6A_P_2 */
10145 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10148 /* VEX_LEN_0F3A6B_P_2 */
10150 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10153 /* VEX_LEN_0F3A6E_P_2 */
10155 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10158 /* VEX_LEN_0F3A6F_P_2 */
10160 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10163 /* VEX_LEN_0F3A7A_P_2 */
10165 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10168 /* VEX_LEN_0F3A7B_P_2 */
10170 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10173 /* VEX_LEN_0F3A7E_P_2 */
10175 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10178 /* VEX_LEN_0F3A7F_P_2 */
10180 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10183 /* VEX_LEN_0F3ADF_P_2 */
10185 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10188 /* VEX_LEN_0F3AF0_P_3 */
10190 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10193 /* VEX_LEN_0FXOP_08_CC */
10195 { "vpcomb", { XM
, Vex128
, EXx
, Ib
}, 0 },
10198 /* VEX_LEN_0FXOP_08_CD */
10200 { "vpcomw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10203 /* VEX_LEN_0FXOP_08_CE */
10205 { "vpcomd", { XM
, Vex128
, EXx
, Ib
}, 0 },
10208 /* VEX_LEN_0FXOP_08_CF */
10210 { "vpcomq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10213 /* VEX_LEN_0FXOP_08_EC */
10215 { "vpcomub", { XM
, Vex128
, EXx
, Ib
}, 0 },
10218 /* VEX_LEN_0FXOP_08_ED */
10220 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10223 /* VEX_LEN_0FXOP_08_EE */
10225 { "vpcomud", { XM
, Vex128
, EXx
, Ib
}, 0 },
10228 /* VEX_LEN_0FXOP_08_EF */
10230 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10233 /* VEX_LEN_0FXOP_09_80 */
10235 { "vfrczps", { XM
, EXxmm
}, 0 },
10236 { "vfrczps", { XM
, EXymmq
}, 0 },
10239 /* VEX_LEN_0FXOP_09_81 */
10241 { "vfrczpd", { XM
, EXxmm
}, 0 },
10242 { "vfrczpd", { XM
, EXymmq
}, 0 },
10246 static const struct dis386 vex_w_table
[][2] = {
10248 /* VEX_W_0F10_P_0 */
10249 { "vmovups", { XM
, EXx
}, 0 },
10252 /* VEX_W_0F10_P_1 */
10253 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10256 /* VEX_W_0F10_P_2 */
10257 { "vmovupd", { XM
, EXx
}, 0 },
10260 /* VEX_W_0F10_P_3 */
10261 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10264 /* VEX_W_0F11_P_0 */
10265 { "vmovups", { EXxS
, XM
}, 0 },
10268 /* VEX_W_0F11_P_1 */
10269 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10272 /* VEX_W_0F11_P_2 */
10273 { "vmovupd", { EXxS
, XM
}, 0 },
10276 /* VEX_W_0F11_P_3 */
10277 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10280 /* VEX_W_0F12_P_0_M_0 */
10281 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10284 /* VEX_W_0F12_P_0_M_1 */
10285 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10288 /* VEX_W_0F12_P_1 */
10289 { "vmovsldup", { XM
, EXx
}, 0 },
10292 /* VEX_W_0F12_P_2 */
10293 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10296 /* VEX_W_0F12_P_3 */
10297 { "vmovddup", { XM
, EXymmq
}, 0 },
10300 /* VEX_W_0F13_M_0 */
10301 { "vmovlpX", { EXq
, XM
}, 0 },
10305 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10309 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10312 /* VEX_W_0F16_P_0_M_0 */
10313 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10316 /* VEX_W_0F16_P_0_M_1 */
10317 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10320 /* VEX_W_0F16_P_1 */
10321 { "vmovshdup", { XM
, EXx
}, 0 },
10324 /* VEX_W_0F16_P_2 */
10325 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10328 /* VEX_W_0F17_M_0 */
10329 { "vmovhpX", { EXq
, XM
}, 0 },
10333 { "vmovapX", { XM
, EXx
}, 0 },
10337 { "vmovapX", { EXxS
, XM
}, 0 },
10340 /* VEX_W_0F2B_M_0 */
10341 { "vmovntpX", { Mx
, XM
}, 0 },
10344 /* VEX_W_0F2E_P_0 */
10345 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10348 /* VEX_W_0F2E_P_2 */
10349 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10352 /* VEX_W_0F2F_P_0 */
10353 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10356 /* VEX_W_0F2F_P_2 */
10357 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10360 /* VEX_W_0F41_P_0_LEN_1 */
10361 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10362 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10365 /* VEX_W_0F41_P_2_LEN_1 */
10366 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10367 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10370 /* VEX_W_0F42_P_0_LEN_1 */
10371 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10372 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10375 /* VEX_W_0F42_P_2_LEN_1 */
10376 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10377 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10380 /* VEX_W_0F44_P_0_LEN_0 */
10381 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10382 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10385 /* VEX_W_0F44_P_2_LEN_0 */
10386 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10387 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10390 /* VEX_W_0F45_P_0_LEN_1 */
10391 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10392 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10395 /* VEX_W_0F45_P_2_LEN_1 */
10396 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10397 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10400 /* VEX_W_0F46_P_0_LEN_1 */
10401 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10402 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10405 /* VEX_W_0F46_P_2_LEN_1 */
10406 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10407 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10410 /* VEX_W_0F47_P_0_LEN_1 */
10411 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10412 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10415 /* VEX_W_0F47_P_2_LEN_1 */
10416 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10417 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10420 /* VEX_W_0F4A_P_0_LEN_1 */
10421 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10422 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10425 /* VEX_W_0F4A_P_2_LEN_1 */
10426 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10427 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10430 /* VEX_W_0F4B_P_0_LEN_1 */
10431 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10432 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10435 /* VEX_W_0F4B_P_2_LEN_1 */
10436 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10439 /* VEX_W_0F50_M_0 */
10440 { "vmovmskpX", { Gdq
, XS
}, 0 },
10443 /* VEX_W_0F51_P_0 */
10444 { "vsqrtps", { XM
, EXx
}, 0 },
10447 /* VEX_W_0F51_P_1 */
10448 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10451 /* VEX_W_0F51_P_2 */
10452 { "vsqrtpd", { XM
, EXx
}, 0 },
10455 /* VEX_W_0F51_P_3 */
10456 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10459 /* VEX_W_0F52_P_0 */
10460 { "vrsqrtps", { XM
, EXx
}, 0 },
10463 /* VEX_W_0F52_P_1 */
10464 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10467 /* VEX_W_0F53_P_0 */
10468 { "vrcpps", { XM
, EXx
}, 0 },
10471 /* VEX_W_0F53_P_1 */
10472 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10475 /* VEX_W_0F58_P_0 */
10476 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10479 /* VEX_W_0F58_P_1 */
10480 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10483 /* VEX_W_0F58_P_2 */
10484 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10487 /* VEX_W_0F58_P_3 */
10488 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10491 /* VEX_W_0F59_P_0 */
10492 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10495 /* VEX_W_0F59_P_1 */
10496 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10499 /* VEX_W_0F59_P_2 */
10500 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10503 /* VEX_W_0F59_P_3 */
10504 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10507 /* VEX_W_0F5A_P_0 */
10508 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10511 /* VEX_W_0F5A_P_1 */
10512 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10515 /* VEX_W_0F5A_P_3 */
10516 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10519 /* VEX_W_0F5B_P_0 */
10520 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10523 /* VEX_W_0F5B_P_1 */
10524 { "vcvttps2dq", { XM
, EXx
}, 0 },
10527 /* VEX_W_0F5B_P_2 */
10528 { "vcvtps2dq", { XM
, EXx
}, 0 },
10531 /* VEX_W_0F5C_P_0 */
10532 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10535 /* VEX_W_0F5C_P_1 */
10536 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10539 /* VEX_W_0F5C_P_2 */
10540 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10543 /* VEX_W_0F5C_P_3 */
10544 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10547 /* VEX_W_0F5D_P_0 */
10548 { "vminps", { XM
, Vex
, EXx
}, 0 },
10551 /* VEX_W_0F5D_P_1 */
10552 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10555 /* VEX_W_0F5D_P_2 */
10556 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10559 /* VEX_W_0F5D_P_3 */
10560 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10563 /* VEX_W_0F5E_P_0 */
10564 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10567 /* VEX_W_0F5E_P_1 */
10568 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10571 /* VEX_W_0F5E_P_2 */
10572 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10575 /* VEX_W_0F5E_P_3 */
10576 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10579 /* VEX_W_0F5F_P_0 */
10580 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10583 /* VEX_W_0F5F_P_1 */
10584 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10587 /* VEX_W_0F5F_P_2 */
10588 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10591 /* VEX_W_0F5F_P_3 */
10592 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10595 /* VEX_W_0F60_P_2 */
10596 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10599 /* VEX_W_0F61_P_2 */
10600 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10603 /* VEX_W_0F62_P_2 */
10604 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10607 /* VEX_W_0F63_P_2 */
10608 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10611 /* VEX_W_0F64_P_2 */
10612 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10615 /* VEX_W_0F65_P_2 */
10616 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10619 /* VEX_W_0F66_P_2 */
10620 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10623 /* VEX_W_0F67_P_2 */
10624 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10627 /* VEX_W_0F68_P_2 */
10628 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10631 /* VEX_W_0F69_P_2 */
10632 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10635 /* VEX_W_0F6A_P_2 */
10636 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10639 /* VEX_W_0F6B_P_2 */
10640 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10643 /* VEX_W_0F6C_P_2 */
10644 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10647 /* VEX_W_0F6D_P_2 */
10648 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10651 /* VEX_W_0F6F_P_1 */
10652 { "vmovdqu", { XM
, EXx
}, 0 },
10655 /* VEX_W_0F6F_P_2 */
10656 { "vmovdqa", { XM
, EXx
}, 0 },
10659 /* VEX_W_0F70_P_1 */
10660 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10663 /* VEX_W_0F70_P_2 */
10664 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10667 /* VEX_W_0F70_P_3 */
10668 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10671 /* VEX_W_0F71_R_2_P_2 */
10672 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10675 /* VEX_W_0F71_R_4_P_2 */
10676 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10679 /* VEX_W_0F71_R_6_P_2 */
10680 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10683 /* VEX_W_0F72_R_2_P_2 */
10684 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10687 /* VEX_W_0F72_R_4_P_2 */
10688 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10691 /* VEX_W_0F72_R_6_P_2 */
10692 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10695 /* VEX_W_0F73_R_2_P_2 */
10696 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10699 /* VEX_W_0F73_R_3_P_2 */
10700 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10703 /* VEX_W_0F73_R_6_P_2 */
10704 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10707 /* VEX_W_0F73_R_7_P_2 */
10708 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10711 /* VEX_W_0F74_P_2 */
10712 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10715 /* VEX_W_0F75_P_2 */
10716 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10719 /* VEX_W_0F76_P_2 */
10720 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10723 /* VEX_W_0F77_P_0 */
10724 { "", { VZERO
}, 0 },
10727 /* VEX_W_0F7C_P_2 */
10728 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10731 /* VEX_W_0F7C_P_3 */
10732 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10735 /* VEX_W_0F7D_P_2 */
10736 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10739 /* VEX_W_0F7D_P_3 */
10740 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10743 /* VEX_W_0F7E_P_1 */
10744 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10747 /* VEX_W_0F7F_P_1 */
10748 { "vmovdqu", { EXxS
, XM
}, 0 },
10751 /* VEX_W_0F7F_P_2 */
10752 { "vmovdqa", { EXxS
, XM
}, 0 },
10755 /* VEX_W_0F90_P_0_LEN_0 */
10756 { "kmovw", { MaskG
, MaskE
}, 0 },
10757 { "kmovq", { MaskG
, MaskE
}, 0 },
10760 /* VEX_W_0F90_P_2_LEN_0 */
10761 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10762 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10765 /* VEX_W_0F91_P_0_LEN_0 */
10766 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10767 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10770 /* VEX_W_0F91_P_2_LEN_0 */
10771 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10772 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10775 /* VEX_W_0F92_P_0_LEN_0 */
10776 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10779 /* VEX_W_0F92_P_2_LEN_0 */
10780 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10783 /* VEX_W_0F92_P_3_LEN_0 */
10784 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0
) },
10785 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0
) },
10788 /* VEX_W_0F93_P_0_LEN_0 */
10789 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10792 /* VEX_W_0F93_P_2_LEN_0 */
10793 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10796 /* VEX_W_0F93_P_3_LEN_0 */
10797 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0
) },
10798 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0
) },
10801 /* VEX_W_0F98_P_0_LEN_0 */
10802 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10803 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10806 /* VEX_W_0F98_P_2_LEN_0 */
10807 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10808 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10811 /* VEX_W_0F99_P_0_LEN_0 */
10812 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10813 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10816 /* VEX_W_0F99_P_2_LEN_0 */
10817 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10818 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10821 /* VEX_W_0FAE_R_2_M_0 */
10822 { "vldmxcsr", { Md
}, 0 },
10825 /* VEX_W_0FAE_R_3_M_0 */
10826 { "vstmxcsr", { Md
}, 0 },
10829 /* VEX_W_0FC2_P_0 */
10830 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
10833 /* VEX_W_0FC2_P_1 */
10834 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
10837 /* VEX_W_0FC2_P_2 */
10838 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
10841 /* VEX_W_0FC2_P_3 */
10842 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
10845 /* VEX_W_0FC4_P_2 */
10846 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
10849 /* VEX_W_0FC5_P_2 */
10850 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
10853 /* VEX_W_0FD0_P_2 */
10854 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
10857 /* VEX_W_0FD0_P_3 */
10858 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
10861 /* VEX_W_0FD1_P_2 */
10862 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
10865 /* VEX_W_0FD2_P_2 */
10866 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
10869 /* VEX_W_0FD3_P_2 */
10870 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
10873 /* VEX_W_0FD4_P_2 */
10874 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
10877 /* VEX_W_0FD5_P_2 */
10878 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
10881 /* VEX_W_0FD6_P_2 */
10882 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
10885 /* VEX_W_0FD7_P_2_M_1 */
10886 { "vpmovmskb", { Gdq
, XS
}, 0 },
10889 /* VEX_W_0FD8_P_2 */
10890 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
10893 /* VEX_W_0FD9_P_2 */
10894 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
10897 /* VEX_W_0FDA_P_2 */
10898 { "vpminub", { XM
, Vex
, EXx
}, 0 },
10901 /* VEX_W_0FDB_P_2 */
10902 { "vpand", { XM
, Vex
, EXx
}, 0 },
10905 /* VEX_W_0FDC_P_2 */
10906 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
10909 /* VEX_W_0FDD_P_2 */
10910 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
10913 /* VEX_W_0FDE_P_2 */
10914 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
10917 /* VEX_W_0FDF_P_2 */
10918 { "vpandn", { XM
, Vex
, EXx
}, 0 },
10921 /* VEX_W_0FE0_P_2 */
10922 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
10925 /* VEX_W_0FE1_P_2 */
10926 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
10929 /* VEX_W_0FE2_P_2 */
10930 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
10933 /* VEX_W_0FE3_P_2 */
10934 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
10937 /* VEX_W_0FE4_P_2 */
10938 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
10941 /* VEX_W_0FE5_P_2 */
10942 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
10945 /* VEX_W_0FE6_P_1 */
10946 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
10949 /* VEX_W_0FE6_P_2 */
10950 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
10953 /* VEX_W_0FE6_P_3 */
10954 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
10957 /* VEX_W_0FE7_P_2_M_0 */
10958 { "vmovntdq", { Mx
, XM
}, 0 },
10961 /* VEX_W_0FE8_P_2 */
10962 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
10965 /* VEX_W_0FE9_P_2 */
10966 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
10969 /* VEX_W_0FEA_P_2 */
10970 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
10973 /* VEX_W_0FEB_P_2 */
10974 { "vpor", { XM
, Vex
, EXx
}, 0 },
10977 /* VEX_W_0FEC_P_2 */
10978 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
10981 /* VEX_W_0FED_P_2 */
10982 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
10985 /* VEX_W_0FEE_P_2 */
10986 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
10989 /* VEX_W_0FEF_P_2 */
10990 { "vpxor", { XM
, Vex
, EXx
}, 0 },
10993 /* VEX_W_0FF0_P_3_M_0 */
10994 { "vlddqu", { XM
, M
}, 0 },
10997 /* VEX_W_0FF1_P_2 */
10998 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
11001 /* VEX_W_0FF2_P_2 */
11002 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
11005 /* VEX_W_0FF3_P_2 */
11006 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
11009 /* VEX_W_0FF4_P_2 */
11010 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
11013 /* VEX_W_0FF5_P_2 */
11014 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
11017 /* VEX_W_0FF6_P_2 */
11018 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
11021 /* VEX_W_0FF7_P_2 */
11022 { "vmaskmovdqu", { XM
, XS
}, 0 },
11025 /* VEX_W_0FF8_P_2 */
11026 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
11029 /* VEX_W_0FF9_P_2 */
11030 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
11033 /* VEX_W_0FFA_P_2 */
11034 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
11037 /* VEX_W_0FFB_P_2 */
11038 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
11041 /* VEX_W_0FFC_P_2 */
11042 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
11045 /* VEX_W_0FFD_P_2 */
11046 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
11049 /* VEX_W_0FFE_P_2 */
11050 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
11053 /* VEX_W_0F3800_P_2 */
11054 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
11057 /* VEX_W_0F3801_P_2 */
11058 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
11061 /* VEX_W_0F3802_P_2 */
11062 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
11065 /* VEX_W_0F3803_P_2 */
11066 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
11069 /* VEX_W_0F3804_P_2 */
11070 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
11073 /* VEX_W_0F3805_P_2 */
11074 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
11077 /* VEX_W_0F3806_P_2 */
11078 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
11081 /* VEX_W_0F3807_P_2 */
11082 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
11085 /* VEX_W_0F3808_P_2 */
11086 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
11089 /* VEX_W_0F3809_P_2 */
11090 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
11093 /* VEX_W_0F380A_P_2 */
11094 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
11097 /* VEX_W_0F380B_P_2 */
11098 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
11101 /* VEX_W_0F380C_P_2 */
11102 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
11105 /* VEX_W_0F380D_P_2 */
11106 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
11109 /* VEX_W_0F380E_P_2 */
11110 { "vtestps", { XM
, EXx
}, 0 },
11113 /* VEX_W_0F380F_P_2 */
11114 { "vtestpd", { XM
, EXx
}, 0 },
11117 /* VEX_W_0F3816_P_2 */
11118 { "vpermps", { XM
, Vex
, EXx
}, 0 },
11121 /* VEX_W_0F3817_P_2 */
11122 { "vptest", { XM
, EXx
}, 0 },
11125 /* VEX_W_0F3818_P_2 */
11126 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11129 /* VEX_W_0F3819_P_2 */
11130 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11133 /* VEX_W_0F381A_P_2_M_0 */
11134 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11137 /* VEX_W_0F381C_P_2 */
11138 { "vpabsb", { XM
, EXx
}, 0 },
11141 /* VEX_W_0F381D_P_2 */
11142 { "vpabsw", { XM
, EXx
}, 0 },
11145 /* VEX_W_0F381E_P_2 */
11146 { "vpabsd", { XM
, EXx
}, 0 },
11149 /* VEX_W_0F3820_P_2 */
11150 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11153 /* VEX_W_0F3821_P_2 */
11154 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11157 /* VEX_W_0F3822_P_2 */
11158 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11161 /* VEX_W_0F3823_P_2 */
11162 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11165 /* VEX_W_0F3824_P_2 */
11166 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11169 /* VEX_W_0F3825_P_2 */
11170 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11173 /* VEX_W_0F3828_P_2 */
11174 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11177 /* VEX_W_0F3829_P_2 */
11178 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11181 /* VEX_W_0F382A_P_2_M_0 */
11182 { "vmovntdqa", { XM
, Mx
}, 0 },
11185 /* VEX_W_0F382B_P_2 */
11186 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11189 /* VEX_W_0F382C_P_2_M_0 */
11190 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11193 /* VEX_W_0F382D_P_2_M_0 */
11194 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11197 /* VEX_W_0F382E_P_2_M_0 */
11198 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11201 /* VEX_W_0F382F_P_2_M_0 */
11202 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11205 /* VEX_W_0F3830_P_2 */
11206 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11209 /* VEX_W_0F3831_P_2 */
11210 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11213 /* VEX_W_0F3832_P_2 */
11214 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11217 /* VEX_W_0F3833_P_2 */
11218 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11221 /* VEX_W_0F3834_P_2 */
11222 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11225 /* VEX_W_0F3835_P_2 */
11226 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11229 /* VEX_W_0F3836_P_2 */
11230 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11233 /* VEX_W_0F3837_P_2 */
11234 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11237 /* VEX_W_0F3838_P_2 */
11238 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11241 /* VEX_W_0F3839_P_2 */
11242 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11245 /* VEX_W_0F383A_P_2 */
11246 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11249 /* VEX_W_0F383B_P_2 */
11250 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11253 /* VEX_W_0F383C_P_2 */
11254 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11257 /* VEX_W_0F383D_P_2 */
11258 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11261 /* VEX_W_0F383E_P_2 */
11262 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11265 /* VEX_W_0F383F_P_2 */
11266 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11269 /* VEX_W_0F3840_P_2 */
11270 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11273 /* VEX_W_0F3841_P_2 */
11274 { "vphminposuw", { XM
, EXx
}, 0 },
11277 /* VEX_W_0F3846_P_2 */
11278 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11281 /* VEX_W_0F3858_P_2 */
11282 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11285 /* VEX_W_0F3859_P_2 */
11286 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11289 /* VEX_W_0F385A_P_2_M_0 */
11290 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11293 /* VEX_W_0F3878_P_2 */
11294 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11297 /* VEX_W_0F3879_P_2 */
11298 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11301 /* VEX_W_0F38CF_P_2 */
11302 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
11305 /* VEX_W_0F38DB_P_2 */
11306 { "vaesimc", { XM
, EXx
}, 0 },
11309 /* VEX_W_0F3A00_P_2 */
11311 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11314 /* VEX_W_0F3A01_P_2 */
11316 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11319 /* VEX_W_0F3A02_P_2 */
11320 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11323 /* VEX_W_0F3A04_P_2 */
11324 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11327 /* VEX_W_0F3A05_P_2 */
11328 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11331 /* VEX_W_0F3A06_P_2 */
11332 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11335 /* VEX_W_0F3A08_P_2 */
11336 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11339 /* VEX_W_0F3A09_P_2 */
11340 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11343 /* VEX_W_0F3A0A_P_2 */
11344 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11347 /* VEX_W_0F3A0B_P_2 */
11348 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11351 /* VEX_W_0F3A0C_P_2 */
11352 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11355 /* VEX_W_0F3A0D_P_2 */
11356 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11359 /* VEX_W_0F3A0E_P_2 */
11360 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11363 /* VEX_W_0F3A0F_P_2 */
11364 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11367 /* VEX_W_0F3A14_P_2 */
11368 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11371 /* VEX_W_0F3A15_P_2 */
11372 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11375 /* VEX_W_0F3A18_P_2 */
11376 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11379 /* VEX_W_0F3A19_P_2 */
11380 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11383 /* VEX_W_0F3A20_P_2 */
11384 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11387 /* VEX_W_0F3A21_P_2 */
11388 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11391 /* VEX_W_0F3A30_P_2_LEN_0 */
11392 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
11393 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
11396 /* VEX_W_0F3A31_P_2_LEN_0 */
11397 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
11398 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
11401 /* VEX_W_0F3A32_P_2_LEN_0 */
11402 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
11403 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
11406 /* VEX_W_0F3A33_P_2_LEN_0 */
11407 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
11408 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
11411 /* VEX_W_0F3A38_P_2 */
11412 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11415 /* VEX_W_0F3A39_P_2 */
11416 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11419 /* VEX_W_0F3A40_P_2 */
11420 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11423 /* VEX_W_0F3A41_P_2 */
11424 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11427 /* VEX_W_0F3A42_P_2 */
11428 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11431 /* VEX_W_0F3A46_P_2 */
11432 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11435 /* VEX_W_0F3A48_P_2 */
11436 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11437 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11440 /* VEX_W_0F3A49_P_2 */
11441 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11442 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11445 /* VEX_W_0F3A4A_P_2 */
11446 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11449 /* VEX_W_0F3A4B_P_2 */
11450 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11453 /* VEX_W_0F3A4C_P_2 */
11454 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11457 /* VEX_W_0F3A62_P_2 */
11458 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11461 /* VEX_W_0F3A63_P_2 */
11462 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11465 /* VEX_W_0F3ACE_P_2 */
11467 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
11470 /* VEX_W_0F3ACF_P_2 */
11472 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
11475 /* VEX_W_0F3ADF_P_2 */
11476 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11478 #define NEED_VEX_W_TABLE
11479 #include "i386-dis-evex.h"
11480 #undef NEED_VEX_W_TABLE
11483 static const struct dis386 mod_table
[][2] = {
11486 { "leaS", { Gv
, M
}, 0 },
11491 { RM_TABLE (RM_C6_REG_7
) },
11496 { RM_TABLE (RM_C7_REG_7
) },
11500 { "Jcall^", { indirEp
}, 0 },
11504 { "Jjmp^", { indirEp
}, 0 },
11507 /* MOD_0F01_REG_0 */
11508 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11509 { RM_TABLE (RM_0F01_REG_0
) },
11512 /* MOD_0F01_REG_1 */
11513 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11514 { RM_TABLE (RM_0F01_REG_1
) },
11517 /* MOD_0F01_REG_2 */
11518 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11519 { RM_TABLE (RM_0F01_REG_2
) },
11522 /* MOD_0F01_REG_3 */
11523 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11524 { RM_TABLE (RM_0F01_REG_3
) },
11527 /* MOD_0F01_REG_5 */
11528 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5
) },
11529 { RM_TABLE (RM_0F01_REG_5
) },
11532 /* MOD_0F01_REG_7 */
11533 { "invlpg", { Mb
}, 0 },
11534 { RM_TABLE (RM_0F01_REG_7
) },
11537 /* MOD_0F12_PREFIX_0 */
11538 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
11539 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
11543 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
11546 /* MOD_0F16_PREFIX_0 */
11547 { "movhps", { XM
, EXq
}, 0 },
11548 { "movlhps", { XM
, EXq
}, 0 },
11552 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
11555 /* MOD_0F18_REG_0 */
11556 { "prefetchnta", { Mb
}, 0 },
11559 /* MOD_0F18_REG_1 */
11560 { "prefetcht0", { Mb
}, 0 },
11563 /* MOD_0F18_REG_2 */
11564 { "prefetcht1", { Mb
}, 0 },
11567 /* MOD_0F18_REG_3 */
11568 { "prefetcht2", { Mb
}, 0 },
11571 /* MOD_0F18_REG_4 */
11572 { "nop/reserved", { Mb
}, 0 },
11575 /* MOD_0F18_REG_5 */
11576 { "nop/reserved", { Mb
}, 0 },
11579 /* MOD_0F18_REG_6 */
11580 { "nop/reserved", { Mb
}, 0 },
11583 /* MOD_0F18_REG_7 */
11584 { "nop/reserved", { Mb
}, 0 },
11587 /* MOD_0F1A_PREFIX_0 */
11588 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11589 { "nopQ", { Ev
}, 0 },
11592 /* MOD_0F1B_PREFIX_0 */
11593 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11594 { "nopQ", { Ev
}, 0 },
11597 /* MOD_0F1B_PREFIX_1 */
11598 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11599 { "nopQ", { Ev
}, 0 },
11602 /* MOD_0F1E_PREFIX_1 */
11603 { "nopQ", { Ev
}, 0 },
11604 { REG_TABLE (REG_0F1E_MOD_3
) },
11609 { "movL", { Rd
, Td
}, 0 },
11614 { "movL", { Td
, Rd
}, 0 },
11617 /* MOD_0F2B_PREFIX_0 */
11618 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
11621 /* MOD_0F2B_PREFIX_1 */
11622 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
11625 /* MOD_0F2B_PREFIX_2 */
11626 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
11629 /* MOD_0F2B_PREFIX_3 */
11630 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
11635 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11638 /* MOD_0F71_REG_2 */
11640 { "psrlw", { MS
, Ib
}, 0 },
11643 /* MOD_0F71_REG_4 */
11645 { "psraw", { MS
, Ib
}, 0 },
11648 /* MOD_0F71_REG_6 */
11650 { "psllw", { MS
, Ib
}, 0 },
11653 /* MOD_0F72_REG_2 */
11655 { "psrld", { MS
, Ib
}, 0 },
11658 /* MOD_0F72_REG_4 */
11660 { "psrad", { MS
, Ib
}, 0 },
11663 /* MOD_0F72_REG_6 */
11665 { "pslld", { MS
, Ib
}, 0 },
11668 /* MOD_0F73_REG_2 */
11670 { "psrlq", { MS
, Ib
}, 0 },
11673 /* MOD_0F73_REG_3 */
11675 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11678 /* MOD_0F73_REG_6 */
11680 { "psllq", { MS
, Ib
}, 0 },
11683 /* MOD_0F73_REG_7 */
11685 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11688 /* MOD_0FAE_REG_0 */
11689 { "fxsave", { FXSAVE
}, 0 },
11690 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11693 /* MOD_0FAE_REG_1 */
11694 { "fxrstor", { FXSAVE
}, 0 },
11695 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11698 /* MOD_0FAE_REG_2 */
11699 { "ldmxcsr", { Md
}, 0 },
11700 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11703 /* MOD_0FAE_REG_3 */
11704 { "stmxcsr", { Md
}, 0 },
11705 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11708 /* MOD_0FAE_REG_4 */
11709 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
11710 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
11713 /* MOD_0FAE_REG_5 */
11714 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5
) },
11715 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5
) },
11718 /* MOD_0FAE_REG_6 */
11719 { PREFIX_TABLE (PREFIX_0FAE_REG_6
) },
11720 { RM_TABLE (RM_0FAE_REG_6
) },
11723 /* MOD_0FAE_REG_7 */
11724 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11725 { RM_TABLE (RM_0FAE_REG_7
) },
11729 { "lssS", { Gv
, Mp
}, 0 },
11733 { "lfsS", { Gv
, Mp
}, 0 },
11737 { "lgsS", { Gv
, Mp
}, 0 },
11741 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
11744 /* MOD_0FC7_REG_3 */
11745 { "xrstors", { FXSAVE
}, 0 },
11748 /* MOD_0FC7_REG_4 */
11749 { "xsavec", { FXSAVE
}, 0 },
11752 /* MOD_0FC7_REG_5 */
11753 { "xsaves", { FXSAVE
}, 0 },
11756 /* MOD_0FC7_REG_6 */
11757 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
11758 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
11761 /* MOD_0FC7_REG_7 */
11762 { "vmptrst", { Mq
}, 0 },
11763 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
11768 { "pmovmskb", { Gdq
, MS
}, 0 },
11771 /* MOD_0FE7_PREFIX_2 */
11772 { "movntdq", { Mx
, XM
}, 0 },
11775 /* MOD_0FF0_PREFIX_3 */
11776 { "lddqu", { XM
, M
}, 0 },
11779 /* MOD_0F382A_PREFIX_2 */
11780 { "movntdqa", { XM
, Mx
}, 0 },
11783 /* MOD_0F38F5_PREFIX_2 */
11784 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
11787 /* MOD_0F38F6_PREFIX_0 */
11788 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
11792 { "bound{S|}", { Gv
, Ma
}, 0 },
11793 { EVEX_TABLE (EVEX_0F
) },
11797 { "lesS", { Gv
, Mp
}, 0 },
11798 { VEX_C4_TABLE (VEX_0F
) },
11802 { "ldsS", { Gv
, Mp
}, 0 },
11803 { VEX_C5_TABLE (VEX_0F
) },
11806 /* MOD_VEX_0F12_PREFIX_0 */
11807 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11808 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11812 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11815 /* MOD_VEX_0F16_PREFIX_0 */
11816 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11817 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11821 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11825 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11828 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11830 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
11833 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11835 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
11838 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11840 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
11843 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11845 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
11848 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11850 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
11853 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11855 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
11858 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11860 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
11863 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11865 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
11868 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11870 { "knotw", { MaskG
, MaskR
}, 0 },
11873 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11875 { "knotq", { MaskG
, MaskR
}, 0 },
11878 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11880 { "knotb", { MaskG
, MaskR
}, 0 },
11883 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11885 { "knotd", { MaskG
, MaskR
}, 0 },
11888 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11890 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
11893 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11895 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
11898 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11900 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
11903 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11905 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
11908 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11910 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11913 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11915 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11918 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11920 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11923 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11925 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
11928 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11930 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11933 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11935 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11938 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11940 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11943 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11945 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
11948 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11950 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
11953 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11955 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
11958 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11960 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
11963 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11965 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
11968 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11970 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
11973 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11975 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
11978 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11980 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
11985 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
11988 /* MOD_VEX_0F71_REG_2 */
11990 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11993 /* MOD_VEX_0F71_REG_4 */
11995 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11998 /* MOD_VEX_0F71_REG_6 */
12000 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
12003 /* MOD_VEX_0F72_REG_2 */
12005 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
12008 /* MOD_VEX_0F72_REG_4 */
12010 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
12013 /* MOD_VEX_0F72_REG_6 */
12015 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
12018 /* MOD_VEX_0F73_REG_2 */
12020 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
12023 /* MOD_VEX_0F73_REG_3 */
12025 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
12028 /* MOD_VEX_0F73_REG_6 */
12030 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
12033 /* MOD_VEX_0F73_REG_7 */
12035 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
12038 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12039 { "kmovw", { Ew
, MaskG
}, 0 },
12043 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12044 { "kmovq", { Eq
, MaskG
}, 0 },
12048 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12049 { "kmovb", { Eb
, MaskG
}, 0 },
12053 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12054 { "kmovd", { Ed
, MaskG
}, 0 },
12058 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12060 { "kmovw", { MaskG
, Rdq
}, 0 },
12063 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12065 { "kmovb", { MaskG
, Rdq
}, 0 },
12068 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12070 { "kmovd", { MaskG
, Rdq
}, 0 },
12073 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12075 { "kmovq", { MaskG
, Rdq
}, 0 },
12078 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12080 { "kmovw", { Gdq
, MaskR
}, 0 },
12083 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12085 { "kmovb", { Gdq
, MaskR
}, 0 },
12088 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12090 { "kmovd", { Gdq
, MaskR
}, 0 },
12093 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12095 { "kmovq", { Gdq
, MaskR
}, 0 },
12098 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12100 { "kortestw", { MaskG
, MaskR
}, 0 },
12103 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12105 { "kortestq", { MaskG
, MaskR
}, 0 },
12108 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12110 { "kortestb", { MaskG
, MaskR
}, 0 },
12113 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12115 { "kortestd", { MaskG
, MaskR
}, 0 },
12118 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12120 { "ktestw", { MaskG
, MaskR
}, 0 },
12123 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12125 { "ktestq", { MaskG
, MaskR
}, 0 },
12128 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12130 { "ktestb", { MaskG
, MaskR
}, 0 },
12133 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12135 { "ktestd", { MaskG
, MaskR
}, 0 },
12138 /* MOD_VEX_0FAE_REG_2 */
12139 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
12142 /* MOD_VEX_0FAE_REG_3 */
12143 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
12146 /* MOD_VEX_0FD7_PREFIX_2 */
12148 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
12151 /* MOD_VEX_0FE7_PREFIX_2 */
12152 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
12155 /* MOD_VEX_0FF0_PREFIX_3 */
12156 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
12159 /* MOD_VEX_0F381A_PREFIX_2 */
12160 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
12163 /* MOD_VEX_0F382A_PREFIX_2 */
12164 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
12167 /* MOD_VEX_0F382C_PREFIX_2 */
12168 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
12171 /* MOD_VEX_0F382D_PREFIX_2 */
12172 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
12175 /* MOD_VEX_0F382E_PREFIX_2 */
12176 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
12179 /* MOD_VEX_0F382F_PREFIX_2 */
12180 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
12183 /* MOD_VEX_0F385A_PREFIX_2 */
12184 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
12187 /* MOD_VEX_0F388C_PREFIX_2 */
12188 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
12191 /* MOD_VEX_0F388E_PREFIX_2 */
12192 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
12195 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12197 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
12200 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12202 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
12205 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12207 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
12210 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12212 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
12215 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12217 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
12220 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12222 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
12225 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12227 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
12230 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12232 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
12234 #define NEED_MOD_TABLE
12235 #include "i386-dis-evex.h"
12236 #undef NEED_MOD_TABLE
12239 static const struct dis386 rm_table
[][8] = {
12242 { "xabort", { Skip_MODRM
, Ib
}, 0 },
12246 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
12249 /* RM_0F01_REG_0 */
12251 { "vmcall", { Skip_MODRM
}, 0 },
12252 { "vmlaunch", { Skip_MODRM
}, 0 },
12253 { "vmresume", { Skip_MODRM
}, 0 },
12254 { "vmxoff", { Skip_MODRM
}, 0 },
12257 /* RM_0F01_REG_1 */
12258 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12259 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12260 { "clac", { Skip_MODRM
}, 0 },
12261 { "stac", { Skip_MODRM
}, 0 },
12265 { "encls", { Skip_MODRM
}, 0 },
12268 /* RM_0F01_REG_2 */
12269 { "xgetbv", { Skip_MODRM
}, 0 },
12270 { "xsetbv", { Skip_MODRM
}, 0 },
12273 { "vmfunc", { Skip_MODRM
}, 0 },
12274 { "xend", { Skip_MODRM
}, 0 },
12275 { "xtest", { Skip_MODRM
}, 0 },
12276 { "enclu", { Skip_MODRM
}, 0 },
12279 /* RM_0F01_REG_3 */
12280 { "vmrun", { Skip_MODRM
}, 0 },
12281 { "vmmcall", { Skip_MODRM
}, 0 },
12282 { "vmload", { Skip_MODRM
}, 0 },
12283 { "vmsave", { Skip_MODRM
}, 0 },
12284 { "stgi", { Skip_MODRM
}, 0 },
12285 { "clgi", { Skip_MODRM
}, 0 },
12286 { "skinit", { Skip_MODRM
}, 0 },
12287 { "invlpga", { Skip_MODRM
}, 0 },
12290 /* RM_0F01_REG_5 */
12291 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0
) },
12293 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2
) },
12297 { "rdpkru", { Skip_MODRM
}, 0 },
12298 { "wrpkru", { Skip_MODRM
}, 0 },
12301 /* RM_0F01_REG_7 */
12302 { "swapgs", { Skip_MODRM
}, 0 },
12303 { "rdtscp", { Skip_MODRM
}, 0 },
12304 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
12305 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
12306 { "clzero", { Skip_MODRM
}, 0 },
12309 /* RM_0F1E_MOD_3_REG_7 */
12310 { "nopQ", { Ev
}, 0 },
12311 { "nopQ", { Ev
}, 0 },
12312 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
12313 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
12314 { "nopQ", { Ev
}, 0 },
12315 { "nopQ", { Ev
}, 0 },
12316 { "nopQ", { Ev
}, 0 },
12317 { "nopQ", { Ev
}, 0 },
12320 /* RM_0FAE_REG_6 */
12321 { "mfence", { Skip_MODRM
}, 0 },
12324 /* RM_0FAE_REG_7 */
12325 { "sfence", { Skip_MODRM
}, 0 },
12330 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12332 /* We use the high bit to indicate different name for the same
12334 #define REP_PREFIX (0xf3 | 0x100)
12335 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12336 #define XRELEASE_PREFIX (0xf3 | 0x400)
12337 #define BND_PREFIX (0xf2 | 0x400)
12338 #define NOTRACK_PREFIX (0x3e | 0x100)
12343 int newrex
, i
, length
;
12349 last_lock_prefix
= -1;
12350 last_repz_prefix
= -1;
12351 last_repnz_prefix
= -1;
12352 last_data_prefix
= -1;
12353 last_addr_prefix
= -1;
12354 last_rex_prefix
= -1;
12355 last_seg_prefix
= -1;
12357 active_seg_prefix
= 0;
12358 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12359 all_prefixes
[i
] = 0;
12362 /* The maximum instruction length is 15bytes. */
12363 while (length
< MAX_CODE_LENGTH
- 1)
12365 FETCH_DATA (the_info
, codep
+ 1);
12369 /* REX prefixes family. */
12386 if (address_mode
== mode_64bit
)
12390 last_rex_prefix
= i
;
12393 prefixes
|= PREFIX_REPZ
;
12394 last_repz_prefix
= i
;
12397 prefixes
|= PREFIX_REPNZ
;
12398 last_repnz_prefix
= i
;
12401 prefixes
|= PREFIX_LOCK
;
12402 last_lock_prefix
= i
;
12405 prefixes
|= PREFIX_CS
;
12406 last_seg_prefix
= i
;
12407 active_seg_prefix
= PREFIX_CS
;
12410 prefixes
|= PREFIX_SS
;
12411 last_seg_prefix
= i
;
12412 active_seg_prefix
= PREFIX_SS
;
12415 prefixes
|= PREFIX_DS
;
12416 last_seg_prefix
= i
;
12417 active_seg_prefix
= PREFIX_DS
;
12420 prefixes
|= PREFIX_ES
;
12421 last_seg_prefix
= i
;
12422 active_seg_prefix
= PREFIX_ES
;
12425 prefixes
|= PREFIX_FS
;
12426 last_seg_prefix
= i
;
12427 active_seg_prefix
= PREFIX_FS
;
12430 prefixes
|= PREFIX_GS
;
12431 last_seg_prefix
= i
;
12432 active_seg_prefix
= PREFIX_GS
;
12435 prefixes
|= PREFIX_DATA
;
12436 last_data_prefix
= i
;
12439 prefixes
|= PREFIX_ADDR
;
12440 last_addr_prefix
= i
;
12443 /* fwait is really an instruction. If there are prefixes
12444 before the fwait, they belong to the fwait, *not* to the
12445 following instruction. */
12447 if (prefixes
|| rex
)
12449 prefixes
|= PREFIX_FWAIT
;
12451 /* This ensures that the previous REX prefixes are noticed
12452 as unused prefixes, as in the return case below. */
12456 prefixes
= PREFIX_FWAIT
;
12461 /* Rex is ignored when followed by another prefix. */
12467 if (*codep
!= FWAIT_OPCODE
)
12468 all_prefixes
[i
++] = *codep
;
12476 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12479 static const char *
12480 prefix_name (int pref
, int sizeflag
)
12482 static const char *rexes
[16] =
12485 "rex.B", /* 0x41 */
12486 "rex.X", /* 0x42 */
12487 "rex.XB", /* 0x43 */
12488 "rex.R", /* 0x44 */
12489 "rex.RB", /* 0x45 */
12490 "rex.RX", /* 0x46 */
12491 "rex.RXB", /* 0x47 */
12492 "rex.W", /* 0x48 */
12493 "rex.WB", /* 0x49 */
12494 "rex.WX", /* 0x4a */
12495 "rex.WXB", /* 0x4b */
12496 "rex.WR", /* 0x4c */
12497 "rex.WRB", /* 0x4d */
12498 "rex.WRX", /* 0x4e */
12499 "rex.WRXB", /* 0x4f */
12504 /* REX prefixes family. */
12521 return rexes
[pref
- 0x40];
12541 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12543 if (address_mode
== mode_64bit
)
12544 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12546 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12551 case XACQUIRE_PREFIX
:
12553 case XRELEASE_PREFIX
:
12557 case NOTRACK_PREFIX
:
12564 static char op_out
[MAX_OPERANDS
][100];
12565 static int op_ad
, op_index
[MAX_OPERANDS
];
12566 static int two_source_ops
;
12567 static bfd_vma op_address
[MAX_OPERANDS
];
12568 static bfd_vma op_riprel
[MAX_OPERANDS
];
12569 static bfd_vma start_pc
;
12572 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12573 * (see topic "Redundant prefixes" in the "Differences from 8086"
12574 * section of the "Virtual 8086 Mode" chapter.)
12575 * 'pc' should be the address of this instruction, it will
12576 * be used to print the target address if this is a relative jump or call
12577 * The function returns the length of this instruction in bytes.
12580 static char intel_syntax
;
12581 static char intel_mnemonic
= !SYSV386_COMPAT
;
12582 static char open_char
;
12583 static char close_char
;
12584 static char separator_char
;
12585 static char scale_char
;
12593 static enum x86_64_isa isa64
;
12595 /* Here for backwards compatibility. When gdb stops using
12596 print_insn_i386_att and print_insn_i386_intel these functions can
12597 disappear, and print_insn_i386 be merged into print_insn. */
12599 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12603 return print_insn (pc
, info
);
12607 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12611 return print_insn (pc
, info
);
12615 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12619 return print_insn (pc
, info
);
12623 print_i386_disassembler_options (FILE *stream
)
12625 fprintf (stream
, _("\n\
12626 The following i386/x86-64 specific disassembler options are supported for use\n\
12627 with the -M switch (multiple options should be separated by commas):\n"));
12629 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12630 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12631 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12632 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12633 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12634 fprintf (stream
, _(" att-mnemonic\n"
12635 " Display instruction in AT&T mnemonic\n"));
12636 fprintf (stream
, _(" intel-mnemonic\n"
12637 " Display instruction in Intel mnemonic\n"));
12638 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12639 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12640 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12641 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12642 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12643 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12644 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
12645 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
12649 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12651 /* Get a pointer to struct dis386 with a valid name. */
12653 static const struct dis386
*
12654 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12656 int vindex
, vex_table_index
;
12658 if (dp
->name
!= NULL
)
12661 switch (dp
->op
[0].bytemode
)
12663 case USE_REG_TABLE
:
12664 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12667 case USE_MOD_TABLE
:
12668 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12669 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12673 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12676 case USE_PREFIX_TABLE
:
12679 /* The prefix in VEX is implicit. */
12680 switch (vex
.prefix
)
12685 case REPE_PREFIX_OPCODE
:
12688 case DATA_PREFIX_OPCODE
:
12691 case REPNE_PREFIX_OPCODE
:
12701 int last_prefix
= -1;
12704 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12705 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12707 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12709 if (last_repz_prefix
> last_repnz_prefix
)
12712 prefix
= PREFIX_REPZ
;
12713 last_prefix
= last_repz_prefix
;
12718 prefix
= PREFIX_REPNZ
;
12719 last_prefix
= last_repnz_prefix
;
12722 /* Check if prefix should be ignored. */
12723 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12724 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12729 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12732 prefix
= PREFIX_DATA
;
12733 last_prefix
= last_data_prefix
;
12738 used_prefixes
|= prefix
;
12739 all_prefixes
[last_prefix
] = 0;
12742 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12745 case USE_X86_64_TABLE
:
12746 vindex
= address_mode
== mode_64bit
? 1 : 0;
12747 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12750 case USE_3BYTE_TABLE
:
12751 FETCH_DATA (info
, codep
+ 2);
12753 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12755 modrm
.mod
= (*codep
>> 6) & 3;
12756 modrm
.reg
= (*codep
>> 3) & 7;
12757 modrm
.rm
= *codep
& 7;
12760 case USE_VEX_LEN_TABLE
:
12764 switch (vex
.length
)
12777 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12780 case USE_XOP_8F_TABLE
:
12781 FETCH_DATA (info
, codep
+ 3);
12782 /* All bits in the REX prefix are ignored. */
12784 rex
= ~(*codep
>> 5) & 0x7;
12786 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12787 switch ((*codep
& 0x1f))
12793 vex_table_index
= XOP_08
;
12796 vex_table_index
= XOP_09
;
12799 vex_table_index
= XOP_0A
;
12803 vex
.w
= *codep
& 0x80;
12804 if (vex
.w
&& address_mode
== mode_64bit
)
12807 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12808 if (address_mode
!= mode_64bit
)
12810 /* In 16/32-bit mode REX_B is silently ignored. */
12812 if (vex
.register_specifier
> 0x7)
12819 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12820 switch ((*codep
& 0x3))
12826 vex
.prefix
= DATA_PREFIX_OPCODE
;
12829 vex
.prefix
= REPE_PREFIX_OPCODE
;
12832 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12839 dp
= &xop_table
[vex_table_index
][vindex
];
12842 FETCH_DATA (info
, codep
+ 1);
12843 modrm
.mod
= (*codep
>> 6) & 3;
12844 modrm
.reg
= (*codep
>> 3) & 7;
12845 modrm
.rm
= *codep
& 7;
12848 case USE_VEX_C4_TABLE
:
12850 FETCH_DATA (info
, codep
+ 3);
12851 /* All bits in the REX prefix are ignored. */
12853 rex
= ~(*codep
>> 5) & 0x7;
12854 switch ((*codep
& 0x1f))
12860 vex_table_index
= VEX_0F
;
12863 vex_table_index
= VEX_0F38
;
12866 vex_table_index
= VEX_0F3A
;
12870 vex
.w
= *codep
& 0x80;
12871 if (address_mode
== mode_64bit
)
12875 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12879 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12880 is ignored, other REX bits are 0 and the highest bit in
12881 VEX.vvvv is also ignored. */
12883 vex
.register_specifier
= (~(*codep
>> 3)) & 0x7;
12885 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12886 switch ((*codep
& 0x3))
12892 vex
.prefix
= DATA_PREFIX_OPCODE
;
12895 vex
.prefix
= REPE_PREFIX_OPCODE
;
12898 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12905 dp
= &vex_table
[vex_table_index
][vindex
];
12907 /* There is no MODRM byte for VEX0F 77. */
12908 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
12910 FETCH_DATA (info
, codep
+ 1);
12911 modrm
.mod
= (*codep
>> 6) & 3;
12912 modrm
.reg
= (*codep
>> 3) & 7;
12913 modrm
.rm
= *codep
& 7;
12917 case USE_VEX_C5_TABLE
:
12919 FETCH_DATA (info
, codep
+ 2);
12920 /* All bits in the REX prefix are ignored. */
12922 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12924 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12926 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12928 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12929 switch ((*codep
& 0x3))
12935 vex
.prefix
= DATA_PREFIX_OPCODE
;
12938 vex
.prefix
= REPE_PREFIX_OPCODE
;
12941 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12948 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12950 /* There is no MODRM byte for VEX 77. */
12951 if (vindex
!= 0x77)
12953 FETCH_DATA (info
, codep
+ 1);
12954 modrm
.mod
= (*codep
>> 6) & 3;
12955 modrm
.reg
= (*codep
>> 3) & 7;
12956 modrm
.rm
= *codep
& 7;
12960 case USE_VEX_W_TABLE
:
12964 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12967 case USE_EVEX_TABLE
:
12968 two_source_ops
= 0;
12971 FETCH_DATA (info
, codep
+ 4);
12972 /* All bits in the REX prefix are ignored. */
12974 /* The first byte after 0x62. */
12975 rex
= ~(*codep
>> 5) & 0x7;
12976 vex
.r
= *codep
& 0x10;
12977 switch ((*codep
& 0xf))
12980 return &bad_opcode
;
12982 vex_table_index
= EVEX_0F
;
12985 vex_table_index
= EVEX_0F38
;
12988 vex_table_index
= EVEX_0F3A
;
12992 /* The second byte after 0x62. */
12994 vex
.w
= *codep
& 0x80;
12995 if (vex
.w
&& address_mode
== mode_64bit
)
12998 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12999 if (address_mode
!= mode_64bit
)
13001 /* In 16/32-bit mode silently ignore following bits. */
13005 vex
.register_specifier
&= 0x7;
13009 if (!(*codep
& 0x4))
13010 return &bad_opcode
;
13012 switch ((*codep
& 0x3))
13018 vex
.prefix
= DATA_PREFIX_OPCODE
;
13021 vex
.prefix
= REPE_PREFIX_OPCODE
;
13024 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13028 /* The third byte after 0x62. */
13031 /* Remember the static rounding bits. */
13032 vex
.ll
= (*codep
>> 5) & 3;
13033 vex
.b
= (*codep
& 0x10) != 0;
13035 vex
.v
= *codep
& 0x8;
13036 vex
.mask_register_specifier
= *codep
& 0x7;
13037 vex
.zeroing
= *codep
& 0x80;
13043 dp
= &evex_table
[vex_table_index
][vindex
];
13045 FETCH_DATA (info
, codep
+ 1);
13046 modrm
.mod
= (*codep
>> 6) & 3;
13047 modrm
.reg
= (*codep
>> 3) & 7;
13048 modrm
.rm
= *codep
& 7;
13050 /* Set vector length. */
13051 if (modrm
.mod
== 3 && vex
.b
)
13067 return &bad_opcode
;
13080 if (dp
->name
!= NULL
)
13083 return get_valid_dis386 (dp
, info
);
13087 get_sib (disassemble_info
*info
, int sizeflag
)
13089 /* If modrm.mod == 3, operand must be register. */
13091 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13095 FETCH_DATA (info
, codep
+ 2);
13096 sib
.index
= (codep
[1] >> 3) & 7;
13097 sib
.scale
= (codep
[1] >> 6) & 3;
13098 sib
.base
= codep
[1] & 7;
13103 print_insn (bfd_vma pc
, disassemble_info
*info
)
13105 const struct dis386
*dp
;
13107 char *op_txt
[MAX_OPERANDS
];
13109 int sizeflag
, orig_sizeflag
;
13111 struct dis_private priv
;
13114 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13115 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
13116 address_mode
= mode_32bit
;
13117 else if (info
->mach
== bfd_mach_i386_i8086
)
13119 address_mode
= mode_16bit
;
13120 priv
.orig_sizeflag
= 0;
13123 address_mode
= mode_64bit
;
13125 if (intel_syntax
== (char) -1)
13126 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
13128 for (p
= info
->disassembler_options
; p
!= NULL
; )
13130 if (CONST_STRNEQ (p
, "amd64"))
13132 else if (CONST_STRNEQ (p
, "intel64"))
13134 else if (CONST_STRNEQ (p
, "x86-64"))
13136 address_mode
= mode_64bit
;
13137 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13139 else if (CONST_STRNEQ (p
, "i386"))
13141 address_mode
= mode_32bit
;
13142 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13144 else if (CONST_STRNEQ (p
, "i8086"))
13146 address_mode
= mode_16bit
;
13147 priv
.orig_sizeflag
= 0;
13149 else if (CONST_STRNEQ (p
, "intel"))
13152 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
13153 intel_mnemonic
= 1;
13155 else if (CONST_STRNEQ (p
, "att"))
13158 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
13159 intel_mnemonic
= 0;
13161 else if (CONST_STRNEQ (p
, "addr"))
13163 if (address_mode
== mode_64bit
)
13165 if (p
[4] == '3' && p
[5] == '2')
13166 priv
.orig_sizeflag
&= ~AFLAG
;
13167 else if (p
[4] == '6' && p
[5] == '4')
13168 priv
.orig_sizeflag
|= AFLAG
;
13172 if (p
[4] == '1' && p
[5] == '6')
13173 priv
.orig_sizeflag
&= ~AFLAG
;
13174 else if (p
[4] == '3' && p
[5] == '2')
13175 priv
.orig_sizeflag
|= AFLAG
;
13178 else if (CONST_STRNEQ (p
, "data"))
13180 if (p
[4] == '1' && p
[5] == '6')
13181 priv
.orig_sizeflag
&= ~DFLAG
;
13182 else if (p
[4] == '3' && p
[5] == '2')
13183 priv
.orig_sizeflag
|= DFLAG
;
13185 else if (CONST_STRNEQ (p
, "suffix"))
13186 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
13188 p
= strchr (p
, ',');
13193 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
13195 (*info
->fprintf_func
) (info
->stream
,
13196 _("64-bit address is disabled"));
13202 names64
= intel_names64
;
13203 names32
= intel_names32
;
13204 names16
= intel_names16
;
13205 names8
= intel_names8
;
13206 names8rex
= intel_names8rex
;
13207 names_seg
= intel_names_seg
;
13208 names_mm
= intel_names_mm
;
13209 names_bnd
= intel_names_bnd
;
13210 names_xmm
= intel_names_xmm
;
13211 names_ymm
= intel_names_ymm
;
13212 names_zmm
= intel_names_zmm
;
13213 index64
= intel_index64
;
13214 index32
= intel_index32
;
13215 names_mask
= intel_names_mask
;
13216 index16
= intel_index16
;
13219 separator_char
= '+';
13224 names64
= att_names64
;
13225 names32
= att_names32
;
13226 names16
= att_names16
;
13227 names8
= att_names8
;
13228 names8rex
= att_names8rex
;
13229 names_seg
= att_names_seg
;
13230 names_mm
= att_names_mm
;
13231 names_bnd
= att_names_bnd
;
13232 names_xmm
= att_names_xmm
;
13233 names_ymm
= att_names_ymm
;
13234 names_zmm
= att_names_zmm
;
13235 index64
= att_index64
;
13236 index32
= att_index32
;
13237 names_mask
= att_names_mask
;
13238 index16
= att_index16
;
13241 separator_char
= ',';
13245 /* The output looks better if we put 7 bytes on a line, since that
13246 puts most long word instructions on a single line. Use 8 bytes
13248 if ((info
->mach
& bfd_mach_l1om
) != 0)
13249 info
->bytes_per_line
= 8;
13251 info
->bytes_per_line
= 7;
13253 info
->private_data
= &priv
;
13254 priv
.max_fetched
= priv
.the_buffer
;
13255 priv
.insn_start
= pc
;
13258 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13266 start_codep
= priv
.the_buffer
;
13267 codep
= priv
.the_buffer
;
13269 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
13273 /* Getting here means we tried for data but didn't get it. That
13274 means we have an incomplete instruction of some sort. Just
13275 print the first byte as a prefix or a .byte pseudo-op. */
13276 if (codep
> priv
.the_buffer
)
13278 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
13280 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
13283 /* Just print the first byte as a .byte instruction. */
13284 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
13285 (unsigned int) priv
.the_buffer
[0]);
13295 sizeflag
= priv
.orig_sizeflag
;
13297 if (!ckprefix () || rex_used
)
13299 /* Too many prefixes or unused REX prefixes. */
13301 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13303 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13305 prefix_name (all_prefixes
[i
], sizeflag
));
13309 insn_codep
= codep
;
13311 FETCH_DATA (info
, codep
+ 1);
13312 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13314 if (((prefixes
& PREFIX_FWAIT
)
13315 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13317 /* Handle prefixes before fwait. */
13318 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13320 (*info
->fprintf_func
) (info
->stream
, "%s ",
13321 prefix_name (all_prefixes
[i
], sizeflag
));
13322 (*info
->fprintf_func
) (info
->stream
, "fwait");
13326 if (*codep
== 0x0f)
13328 unsigned char threebyte
;
13331 FETCH_DATA (info
, codep
+ 1);
13332 threebyte
= *codep
;
13333 dp
= &dis386_twobyte
[threebyte
];
13334 need_modrm
= twobyte_has_modrm
[*codep
];
13339 dp
= &dis386
[*codep
];
13340 need_modrm
= onebyte_has_modrm
[*codep
];
13344 /* Save sizeflag for printing the extra prefixes later before updating
13345 it for mnemonic and operand processing. The prefix names depend
13346 only on the address mode. */
13347 orig_sizeflag
= sizeflag
;
13348 if (prefixes
& PREFIX_ADDR
)
13350 if ((prefixes
& PREFIX_DATA
))
13356 FETCH_DATA (info
, codep
+ 1);
13357 modrm
.mod
= (*codep
>> 6) & 3;
13358 modrm
.reg
= (*codep
>> 3) & 7;
13359 modrm
.rm
= *codep
& 7;
13367 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13369 get_sib (info
, sizeflag
);
13370 dofloat (sizeflag
);
13374 dp
= get_valid_dis386 (dp
, info
);
13375 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13377 get_sib (info
, sizeflag
);
13378 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13381 op_ad
= MAX_OPERANDS
- 1 - i
;
13383 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13384 /* For EVEX instruction after the last operand masking
13385 should be printed. */
13386 if (i
== 0 && vex
.evex
)
13388 /* Don't print {%k0}. */
13389 if (vex
.mask_register_specifier
)
13392 oappend (names_mask
[vex
.mask_register_specifier
]);
13402 /* Check if the REX prefix is used. */
13403 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13404 all_prefixes
[last_rex_prefix
] = 0;
13406 /* Check if the SEG prefix is used. */
13407 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13408 | PREFIX_FS
| PREFIX_GS
)) != 0
13409 && (used_prefixes
& active_seg_prefix
) != 0)
13410 all_prefixes
[last_seg_prefix
] = 0;
13412 /* Check if the ADDR prefix is used. */
13413 if ((prefixes
& PREFIX_ADDR
) != 0
13414 && (used_prefixes
& PREFIX_ADDR
) != 0)
13415 all_prefixes
[last_addr_prefix
] = 0;
13417 /* Check if the DATA prefix is used. */
13418 if ((prefixes
& PREFIX_DATA
) != 0
13419 && (used_prefixes
& PREFIX_DATA
) != 0)
13420 all_prefixes
[last_data_prefix
] = 0;
13422 /* Print the extra prefixes. */
13424 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13425 if (all_prefixes
[i
])
13428 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13431 prefix_length
+= strlen (name
) + 1;
13432 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13435 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13436 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13437 used by putop and MMX/SSE operand and may be overriden by the
13438 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13440 if (dp
->prefix_requirement
== PREFIX_OPCODE
13441 && dp
!= &bad_opcode
13443 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13445 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13447 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13449 && (used_prefixes
& PREFIX_DATA
) == 0))))
13451 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13452 return end_codep
- priv
.the_buffer
;
13455 /* Check maximum code length. */
13456 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13458 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13459 return MAX_CODE_LENGTH
;
13462 obufp
= mnemonicendp
;
13463 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13466 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13468 /* The enter and bound instructions are printed with operands in the same
13469 order as the intel book; everything else is printed in reverse order. */
13470 if (intel_syntax
|| two_source_ops
)
13474 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13475 op_txt
[i
] = op_out
[i
];
13477 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
13478 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
13480 op_txt
[2] = op_out
[3];
13481 op_txt
[3] = op_out
[2];
13484 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13486 op_ad
= op_index
[i
];
13487 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13488 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13489 riprel
= op_riprel
[i
];
13490 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13491 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13496 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13497 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13501 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13505 (*info
->fprintf_func
) (info
->stream
, ",");
13506 if (op_index
[i
] != -1 && !op_riprel
[i
])
13507 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13509 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13513 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13514 if (op_index
[i
] != -1 && op_riprel
[i
])
13516 (*info
->fprintf_func
) (info
->stream
, " # ");
13517 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
13518 + op_address
[op_index
[i
]]), info
);
13521 return codep
- priv
.the_buffer
;
13524 static const char *float_mem
[] = {
13599 static const unsigned char float_mem_mode
[] = {
13674 #define ST { OP_ST, 0 }
13675 #define STi { OP_STi, 0 }
13677 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13678 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13679 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13680 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13681 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13682 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13683 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13684 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13685 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13687 static const struct dis386 float_reg
[][8] = {
13690 { "fadd", { ST
, STi
}, 0 },
13691 { "fmul", { ST
, STi
}, 0 },
13692 { "fcom", { STi
}, 0 },
13693 { "fcomp", { STi
}, 0 },
13694 { "fsub", { ST
, STi
}, 0 },
13695 { "fsubr", { ST
, STi
}, 0 },
13696 { "fdiv", { ST
, STi
}, 0 },
13697 { "fdivr", { ST
, STi
}, 0 },
13701 { "fld", { STi
}, 0 },
13702 { "fxch", { STi
}, 0 },
13712 { "fcmovb", { ST
, STi
}, 0 },
13713 { "fcmove", { ST
, STi
}, 0 },
13714 { "fcmovbe",{ ST
, STi
}, 0 },
13715 { "fcmovu", { ST
, STi
}, 0 },
13723 { "fcmovnb",{ ST
, STi
}, 0 },
13724 { "fcmovne",{ ST
, STi
}, 0 },
13725 { "fcmovnbe",{ ST
, STi
}, 0 },
13726 { "fcmovnu",{ ST
, STi
}, 0 },
13728 { "fucomi", { ST
, STi
}, 0 },
13729 { "fcomi", { ST
, STi
}, 0 },
13734 { "fadd", { STi
, ST
}, 0 },
13735 { "fmul", { STi
, ST
}, 0 },
13738 { "fsub!M", { STi
, ST
}, 0 },
13739 { "fsubM", { STi
, ST
}, 0 },
13740 { "fdiv!M", { STi
, ST
}, 0 },
13741 { "fdivM", { STi
, ST
}, 0 },
13745 { "ffree", { STi
}, 0 },
13747 { "fst", { STi
}, 0 },
13748 { "fstp", { STi
}, 0 },
13749 { "fucom", { STi
}, 0 },
13750 { "fucomp", { STi
}, 0 },
13756 { "faddp", { STi
, ST
}, 0 },
13757 { "fmulp", { STi
, ST
}, 0 },
13760 { "fsub!Mp", { STi
, ST
}, 0 },
13761 { "fsubMp", { STi
, ST
}, 0 },
13762 { "fdiv!Mp", { STi
, ST
}, 0 },
13763 { "fdivMp", { STi
, ST
}, 0 },
13767 { "ffreep", { STi
}, 0 },
13772 { "fucomip", { ST
, STi
}, 0 },
13773 { "fcomip", { ST
, STi
}, 0 },
13778 static char *fgrps
[][8] = {
13781 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13786 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13791 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13796 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13801 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13806 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13811 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13816 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13817 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13822 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13827 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13832 swap_operand (void)
13834 mnemonicendp
[0] = '.';
13835 mnemonicendp
[1] = 's';
13840 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13841 int sizeflag ATTRIBUTE_UNUSED
)
13843 /* Skip mod/rm byte. */
13849 dofloat (int sizeflag
)
13851 const struct dis386
*dp
;
13852 unsigned char floatop
;
13854 floatop
= codep
[-1];
13856 if (modrm
.mod
!= 3)
13858 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13860 putop (float_mem
[fp_indx
], sizeflag
);
13863 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13866 /* Skip mod/rm byte. */
13870 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13871 if (dp
->name
== NULL
)
13873 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13875 /* Instruction fnstsw is only one with strange arg. */
13876 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13877 strcpy (op_out
[0], names16
[0]);
13881 putop (dp
->name
, sizeflag
);
13886 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13891 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13895 /* Like oappend (below), but S is a string starting with '%'.
13896 In Intel syntax, the '%' is elided. */
13898 oappend_maybe_intel (const char *s
)
13900 oappend (s
+ intel_syntax
);
13904 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13906 oappend_maybe_intel ("%st");
13910 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13912 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13913 oappend_maybe_intel (scratchbuf
);
13916 /* Capital letters in template are macros. */
13918 putop (const char *in_template
, int sizeflag
)
13923 unsigned int l
= 0, len
= 1;
13926 #define SAVE_LAST(c) \
13927 if (l < len && l < sizeof (last)) \
13932 for (p
= in_template
; *p
; p
++)
13948 while (*++p
!= '|')
13949 if (*p
== '}' || *p
== '\0')
13952 /* Fall through. */
13957 while (*++p
!= '}')
13968 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13972 if (l
== 0 && len
== 1)
13977 if (sizeflag
& SUFFIX_ALWAYS
)
13990 if (address_mode
== mode_64bit
13991 && !(prefixes
& PREFIX_ADDR
))
14002 if (intel_syntax
&& !alt
)
14004 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14006 if (sizeflag
& DFLAG
)
14007 *obufp
++ = intel_syntax
? 'd' : 'l';
14009 *obufp
++ = intel_syntax
? 'w' : 's';
14010 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14014 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14017 if (modrm
.mod
== 3)
14023 if (sizeflag
& DFLAG
)
14024 *obufp
++ = intel_syntax
? 'd' : 'l';
14027 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14033 case 'E': /* For jcxz/jecxz */
14034 if (address_mode
== mode_64bit
)
14036 if (sizeflag
& AFLAG
)
14042 if (sizeflag
& AFLAG
)
14044 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14049 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
14051 if (sizeflag
& AFLAG
)
14052 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
14054 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
14055 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14059 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
14061 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14065 if (!(rex
& REX_W
))
14066 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14071 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
14072 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
14074 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
14077 if (prefixes
& PREFIX_DS
)
14096 if (l
!= 0 || len
!= 1)
14098 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14103 if (!need_vex
|| !vex
.evex
)
14106 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14108 switch (vex
.length
)
14126 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
14131 /* Fall through. */
14134 if (l
!= 0 || len
!= 1)
14142 if (sizeflag
& SUFFIX_ALWAYS
)
14146 if (intel_mnemonic
!= cond
)
14150 if ((prefixes
& PREFIX_FWAIT
) == 0)
14153 used_prefixes
|= PREFIX_FWAIT
;
14159 else if (intel_syntax
&& (sizeflag
& DFLAG
))
14163 if (!(rex
& REX_W
))
14164 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14168 && address_mode
== mode_64bit
14169 && isa64
== intel64
)
14174 /* Fall through. */
14177 && address_mode
== mode_64bit
14178 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14183 /* Fall through. */
14186 if (l
== 0 && len
== 1)
14191 if ((rex
& REX_W
) == 0
14192 && (prefixes
& PREFIX_DATA
))
14194 if ((sizeflag
& DFLAG
) == 0)
14196 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14200 if ((prefixes
& PREFIX_DATA
)
14202 || (sizeflag
& SUFFIX_ALWAYS
))
14209 if (sizeflag
& DFLAG
)
14213 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14219 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14225 if ((prefixes
& PREFIX_DATA
)
14227 || (sizeflag
& SUFFIX_ALWAYS
))
14234 if (sizeflag
& DFLAG
)
14235 *obufp
++ = intel_syntax
? 'd' : 'l';
14238 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14246 if (address_mode
== mode_64bit
14247 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14249 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14253 /* Fall through. */
14256 if (l
== 0 && len
== 1)
14259 if (intel_syntax
&& !alt
)
14262 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14268 if (sizeflag
& DFLAG
)
14269 *obufp
++ = intel_syntax
? 'd' : 'l';
14272 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14278 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14284 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14299 else if (sizeflag
& DFLAG
)
14308 if (intel_syntax
&& !p
[1]
14309 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
14311 if (!(rex
& REX_W
))
14312 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14315 if (l
== 0 && len
== 1)
14319 if (address_mode
== mode_64bit
14320 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14322 if (sizeflag
& SUFFIX_ALWAYS
)
14344 /* Fall through. */
14347 if (l
== 0 && len
== 1)
14352 if (sizeflag
& SUFFIX_ALWAYS
)
14358 if (sizeflag
& DFLAG
)
14362 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14376 if (address_mode
== mode_64bit
14377 && !(prefixes
& PREFIX_ADDR
))
14388 if (l
!= 0 || len
!= 1)
14393 if (need_vex
&& vex
.prefix
)
14395 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14402 if (prefixes
& PREFIX_DATA
)
14406 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14410 if (l
== 0 && len
== 1)
14412 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14423 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14431 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14433 switch (vex
.length
)
14449 if (l
== 0 && len
== 1)
14451 /* operand size flag for cwtl, cbtw */
14460 else if (sizeflag
& DFLAG
)
14464 if (!(rex
& REX_W
))
14465 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14472 && last
[0] != 'L'))
14479 if (last
[0] == 'X')
14480 *obufp
++ = vex
.w
? 'd': 's';
14482 *obufp
++ = vex
.w
? 'q': 'd';
14488 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14490 if (sizeflag
& DFLAG
)
14494 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14500 if (address_mode
== mode_64bit
14501 && (isa64
== intel64
14502 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
14504 else if ((prefixes
& PREFIX_DATA
))
14506 if (!(sizeflag
& DFLAG
))
14508 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14515 mnemonicendp
= obufp
;
14520 oappend (const char *s
)
14522 obufp
= stpcpy (obufp
, s
);
14528 /* Only print the active segment register. */
14529 if (!active_seg_prefix
)
14532 used_prefixes
|= active_seg_prefix
;
14533 switch (active_seg_prefix
)
14536 oappend_maybe_intel ("%cs:");
14539 oappend_maybe_intel ("%ds:");
14542 oappend_maybe_intel ("%ss:");
14545 oappend_maybe_intel ("%es:");
14548 oappend_maybe_intel ("%fs:");
14551 oappend_maybe_intel ("%gs:");
14559 OP_indirE (int bytemode
, int sizeflag
)
14563 OP_E (bytemode
, sizeflag
);
14567 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14569 if (address_mode
== mode_64bit
)
14577 sprintf_vma (tmp
, disp
);
14578 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14579 strcpy (buf
+ 2, tmp
+ i
);
14583 bfd_signed_vma v
= disp
;
14590 /* Check for possible overflow on 0x8000000000000000. */
14593 strcpy (buf
, "9223372036854775808");
14607 tmp
[28 - i
] = (v
% 10) + '0';
14611 strcpy (buf
, tmp
+ 29 - i
);
14617 sprintf (buf
, "0x%x", (unsigned int) disp
);
14619 sprintf (buf
, "%d", (int) disp
);
14623 /* Put DISP in BUF as signed hex number. */
14626 print_displacement (char *buf
, bfd_vma disp
)
14628 bfd_signed_vma val
= disp
;
14637 /* Check for possible overflow. */
14640 switch (address_mode
)
14643 strcpy (buf
+ j
, "0x8000000000000000");
14646 strcpy (buf
+ j
, "0x80000000");
14649 strcpy (buf
+ j
, "0x8000");
14659 sprintf_vma (tmp
, (bfd_vma
) val
);
14660 for (i
= 0; tmp
[i
] == '0'; i
++)
14662 if (tmp
[i
] == '\0')
14664 strcpy (buf
+ j
, tmp
+ i
);
14668 intel_operand_size (int bytemode
, int sizeflag
)
14672 && (bytemode
== x_mode
14673 || bytemode
== evex_half_bcst_xmmq_mode
))
14676 oappend ("QWORD PTR ");
14678 oappend ("DWORD PTR ");
14687 oappend ("BYTE PTR ");
14692 oappend ("WORD PTR ");
14695 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14697 oappend ("QWORD PTR ");
14700 /* Fall through. */
14702 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14704 oappend ("QWORD PTR ");
14707 /* Fall through. */
14713 oappend ("QWORD PTR ");
14716 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14717 oappend ("DWORD PTR ");
14719 oappend ("WORD PTR ");
14720 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14724 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14726 oappend ("WORD PTR ");
14727 if (!(rex
& REX_W
))
14728 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14731 if (sizeflag
& DFLAG
)
14732 oappend ("QWORD PTR ");
14734 oappend ("DWORD PTR ");
14735 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14738 case d_scalar_mode
:
14739 case d_scalar_swap_mode
:
14742 oappend ("DWORD PTR ");
14745 case q_scalar_mode
:
14746 case q_scalar_swap_mode
:
14748 oappend ("QWORD PTR ");
14751 if (address_mode
== mode_64bit
)
14752 oappend ("QWORD PTR ");
14754 oappend ("DWORD PTR ");
14757 if (sizeflag
& DFLAG
)
14758 oappend ("FWORD PTR ");
14760 oappend ("DWORD PTR ");
14761 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14764 oappend ("TBYTE PTR ");
14768 case evex_x_gscat_mode
:
14769 case evex_x_nobcst_mode
:
14770 case b_scalar_mode
:
14771 case w_scalar_mode
:
14774 switch (vex
.length
)
14777 oappend ("XMMWORD PTR ");
14780 oappend ("YMMWORD PTR ");
14783 oappend ("ZMMWORD PTR ");
14790 oappend ("XMMWORD PTR ");
14793 oappend ("XMMWORD PTR ");
14796 oappend ("YMMWORD PTR ");
14799 case evex_half_bcst_xmmq_mode
:
14803 switch (vex
.length
)
14806 oappend ("QWORD PTR ");
14809 oappend ("XMMWORD PTR ");
14812 oappend ("YMMWORD PTR ");
14822 switch (vex
.length
)
14827 oappend ("BYTE PTR ");
14837 switch (vex
.length
)
14842 oappend ("WORD PTR ");
14852 switch (vex
.length
)
14857 oappend ("DWORD PTR ");
14867 switch (vex
.length
)
14872 oappend ("QWORD PTR ");
14882 switch (vex
.length
)
14885 oappend ("WORD PTR ");
14888 oappend ("DWORD PTR ");
14891 oappend ("QWORD PTR ");
14901 switch (vex
.length
)
14904 oappend ("DWORD PTR ");
14907 oappend ("QWORD PTR ");
14910 oappend ("XMMWORD PTR ");
14920 switch (vex
.length
)
14923 oappend ("QWORD PTR ");
14926 oappend ("YMMWORD PTR ");
14929 oappend ("ZMMWORD PTR ");
14939 switch (vex
.length
)
14943 oappend ("XMMWORD PTR ");
14950 oappend ("OWORD PTR ");
14953 case vex_w_dq_mode
:
14954 case vex_scalar_w_dq_mode
:
14959 oappend ("QWORD PTR ");
14961 oappend ("DWORD PTR ");
14963 case vex_vsib_d_w_dq_mode
:
14964 case vex_vsib_q_w_dq_mode
:
14971 oappend ("QWORD PTR ");
14973 oappend ("DWORD PTR ");
14977 switch (vex
.length
)
14980 oappend ("XMMWORD PTR ");
14983 oappend ("YMMWORD PTR ");
14986 oappend ("ZMMWORD PTR ");
14993 case vex_vsib_q_w_d_mode
:
14994 case vex_vsib_d_w_d_mode
:
14995 if (!need_vex
|| !vex
.evex
)
14998 switch (vex
.length
)
15001 oappend ("QWORD PTR ");
15004 oappend ("XMMWORD PTR ");
15007 oappend ("YMMWORD PTR ");
15015 if (!need_vex
|| vex
.length
!= 128)
15018 oappend ("DWORD PTR ");
15020 oappend ("BYTE PTR ");
15026 oappend ("QWORD PTR ");
15028 oappend ("WORD PTR ");
15037 OP_E_register (int bytemode
, int sizeflag
)
15039 int reg
= modrm
.rm
;
15040 const char **names
;
15046 if ((sizeflag
& SUFFIX_ALWAYS
)
15047 && (bytemode
== b_swap_mode
15048 || bytemode
== v_swap_mode
))
15074 names
= address_mode
== mode_64bit
? names64
: names32
;
15085 if (address_mode
== mode_64bit
&& isa64
== intel64
)
15090 /* Fall through. */
15092 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15098 /* Fall through. */
15110 if ((sizeflag
& DFLAG
)
15111 || (bytemode
!= v_mode
15112 && bytemode
!= v_swap_mode
))
15116 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15126 names
= names_mask
;
15131 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15134 oappend (names
[reg
]);
15138 OP_E_memory (int bytemode
, int sizeflag
)
15141 int add
= (rex
& REX_B
) ? 8 : 0;
15147 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15149 && bytemode
!= x_mode
15150 && bytemode
!= xmmq_mode
15151 && bytemode
!= evex_half_bcst_xmmq_mode
)
15166 case vex_vsib_d_w_dq_mode
:
15167 case vex_vsib_d_w_d_mode
:
15168 case vex_vsib_q_w_dq_mode
:
15169 case vex_vsib_q_w_d_mode
:
15170 case evex_x_gscat_mode
:
15172 shift
= vex
.w
? 3 : 2;
15175 case evex_half_bcst_xmmq_mode
:
15179 shift
= vex
.w
? 3 : 2;
15182 /* Fall through. */
15186 case evex_x_nobcst_mode
:
15188 switch (vex
.length
)
15211 case q_scalar_mode
:
15213 case q_scalar_swap_mode
:
15219 case d_scalar_mode
:
15221 case d_scalar_swap_mode
:
15224 case w_scalar_mode
:
15228 case b_scalar_mode
:
15235 /* Make necessary corrections to shift for modes that need it.
15236 For these modes we currently have shift 4, 5 or 6 depending on
15237 vex.length (it corresponds to xmmword, ymmword or zmmword
15238 operand). We might want to make it 3, 4 or 5 (e.g. for
15239 xmmq_mode). In case of broadcast enabled the corrections
15240 aren't needed, as element size is always 32 or 64 bits. */
15242 && (bytemode
== xmmq_mode
15243 || bytemode
== evex_half_bcst_xmmq_mode
))
15245 else if (bytemode
== xmmqd_mode
)
15247 else if (bytemode
== xmmdw_mode
)
15249 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
15257 intel_operand_size (bytemode
, sizeflag
);
15260 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15262 /* 32/64 bit address mode */
15271 int addr32flag
= !((sizeflag
& AFLAG
)
15272 || bytemode
== v_bnd_mode
15273 || bytemode
== bnd_mode
);
15274 const char **indexes64
= names64
;
15275 const char **indexes32
= names32
;
15285 vindex
= sib
.index
;
15291 case vex_vsib_d_w_dq_mode
:
15292 case vex_vsib_d_w_d_mode
:
15293 case vex_vsib_q_w_dq_mode
:
15294 case vex_vsib_q_w_d_mode
:
15304 switch (vex
.length
)
15307 indexes64
= indexes32
= names_xmm
;
15311 || bytemode
== vex_vsib_q_w_dq_mode
15312 || bytemode
== vex_vsib_q_w_d_mode
)
15313 indexes64
= indexes32
= names_ymm
;
15315 indexes64
= indexes32
= names_xmm
;
15319 || bytemode
== vex_vsib_q_w_dq_mode
15320 || bytemode
== vex_vsib_q_w_d_mode
)
15321 indexes64
= indexes32
= names_zmm
;
15323 indexes64
= indexes32
= names_ymm
;
15330 haveindex
= vindex
!= 4;
15337 rbase
= base
+ add
;
15345 if (address_mode
== mode_64bit
&& !havesib
)
15351 FETCH_DATA (the_info
, codep
+ 1);
15353 if ((disp
& 0x80) != 0)
15355 if (vex
.evex
&& shift
> 0)
15363 /* In 32bit mode, we need index register to tell [offset] from
15364 [eiz*1 + offset]. */
15365 needindex
= (havesib
15368 && address_mode
== mode_32bit
);
15369 havedisp
= (havebase
15371 || (havesib
&& (haveindex
|| scale
!= 0)));
15374 if (modrm
.mod
!= 0 || base
== 5)
15376 if (havedisp
|| riprel
)
15377 print_displacement (scratchbuf
, disp
);
15379 print_operand_value (scratchbuf
, 1, disp
);
15380 oappend (scratchbuf
);
15384 oappend (!addr32flag
? "(%rip)" : "(%eip)");
15388 if ((havebase
|| haveindex
|| riprel
)
15389 && (bytemode
!= v_bnd_mode
)
15390 && (bytemode
!= bnd_mode
))
15391 used_prefixes
|= PREFIX_ADDR
;
15393 if (havedisp
|| (intel_syntax
&& riprel
))
15395 *obufp
++ = open_char
;
15396 if (intel_syntax
&& riprel
)
15399 oappend (!addr32flag
? "rip" : "eip");
15403 oappend (address_mode
== mode_64bit
&& !addr32flag
15404 ? names64
[rbase
] : names32
[rbase
]);
15407 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15408 print index to tell base + index from base. */
15412 || (havebase
&& base
!= ESP_REG_NUM
))
15414 if (!intel_syntax
|| havebase
)
15416 *obufp
++ = separator_char
;
15420 oappend (address_mode
== mode_64bit
&& !addr32flag
15421 ? indexes64
[vindex
] : indexes32
[vindex
]);
15423 oappend (address_mode
== mode_64bit
&& !addr32flag
15424 ? index64
: index32
);
15426 *obufp
++ = scale_char
;
15428 sprintf (scratchbuf
, "%d", 1 << scale
);
15429 oappend (scratchbuf
);
15433 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15435 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15440 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15444 disp
= - (bfd_signed_vma
) disp
;
15448 print_displacement (scratchbuf
, disp
);
15450 print_operand_value (scratchbuf
, 1, disp
);
15451 oappend (scratchbuf
);
15454 *obufp
++ = close_char
;
15457 else if (intel_syntax
)
15459 if (modrm
.mod
!= 0 || base
== 5)
15461 if (!active_seg_prefix
)
15463 oappend (names_seg
[ds_reg
- es_reg
]);
15466 print_operand_value (scratchbuf
, 1, disp
);
15467 oappend (scratchbuf
);
15473 /* 16 bit address mode */
15474 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15481 if ((disp
& 0x8000) != 0)
15486 FETCH_DATA (the_info
, codep
+ 1);
15488 if ((disp
& 0x80) != 0)
15493 if ((disp
& 0x8000) != 0)
15499 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15501 print_displacement (scratchbuf
, disp
);
15502 oappend (scratchbuf
);
15505 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15507 *obufp
++ = open_char
;
15509 oappend (index16
[modrm
.rm
]);
15511 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15513 if ((bfd_signed_vma
) disp
>= 0)
15518 else if (modrm
.mod
!= 1)
15522 disp
= - (bfd_signed_vma
) disp
;
15525 print_displacement (scratchbuf
, disp
);
15526 oappend (scratchbuf
);
15529 *obufp
++ = close_char
;
15532 else if (intel_syntax
)
15534 if (!active_seg_prefix
)
15536 oappend (names_seg
[ds_reg
- es_reg
]);
15539 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15540 oappend (scratchbuf
);
15543 if (vex
.evex
&& vex
.b
15544 && (bytemode
== x_mode
15545 || bytemode
== xmmq_mode
15546 || bytemode
== evex_half_bcst_xmmq_mode
))
15549 || bytemode
== xmmq_mode
15550 || bytemode
== evex_half_bcst_xmmq_mode
)
15552 switch (vex
.length
)
15555 oappend ("{1to2}");
15558 oappend ("{1to4}");
15561 oappend ("{1to8}");
15569 switch (vex
.length
)
15572 oappend ("{1to4}");
15575 oappend ("{1to8}");
15578 oappend ("{1to16}");
15588 OP_E (int bytemode
, int sizeflag
)
15590 /* Skip mod/rm byte. */
15594 if (modrm
.mod
== 3)
15595 OP_E_register (bytemode
, sizeflag
);
15597 OP_E_memory (bytemode
, sizeflag
);
15601 OP_G (int bytemode
, int sizeflag
)
15612 oappend (names8rex
[modrm
.reg
+ add
]);
15614 oappend (names8
[modrm
.reg
+ add
]);
15617 oappend (names16
[modrm
.reg
+ add
]);
15622 oappend (names32
[modrm
.reg
+ add
]);
15625 oappend (names64
[modrm
.reg
+ add
]);
15628 if (modrm
.reg
> 0x3)
15633 oappend (names_bnd
[modrm
.reg
]);
15642 oappend (names64
[modrm
.reg
+ add
]);
15645 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15646 oappend (names32
[modrm
.reg
+ add
]);
15648 oappend (names16
[modrm
.reg
+ add
]);
15649 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15653 if (address_mode
== mode_64bit
)
15654 oappend (names64
[modrm
.reg
+ add
]);
15656 oappend (names32
[modrm
.reg
+ add
]);
15660 if ((modrm
.reg
+ add
) > 0x7)
15665 oappend (names_mask
[modrm
.reg
+ add
]);
15668 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15681 FETCH_DATA (the_info
, codep
+ 8);
15682 a
= *codep
++ & 0xff;
15683 a
|= (*codep
++ & 0xff) << 8;
15684 a
|= (*codep
++ & 0xff) << 16;
15685 a
|= (*codep
++ & 0xffu
) << 24;
15686 b
= *codep
++ & 0xff;
15687 b
|= (*codep
++ & 0xff) << 8;
15688 b
|= (*codep
++ & 0xff) << 16;
15689 b
|= (*codep
++ & 0xffu
) << 24;
15690 x
= a
+ ((bfd_vma
) b
<< 32);
15698 static bfd_signed_vma
15701 bfd_signed_vma x
= 0;
15703 FETCH_DATA (the_info
, codep
+ 4);
15704 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15705 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15706 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15707 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15711 static bfd_signed_vma
15714 bfd_signed_vma x
= 0;
15716 FETCH_DATA (the_info
, codep
+ 4);
15717 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15718 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15719 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15720 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15722 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15732 FETCH_DATA (the_info
, codep
+ 2);
15733 x
= *codep
++ & 0xff;
15734 x
|= (*codep
++ & 0xff) << 8;
15739 set_op (bfd_vma op
, int riprel
)
15741 op_index
[op_ad
] = op_ad
;
15742 if (address_mode
== mode_64bit
)
15744 op_address
[op_ad
] = op
;
15745 op_riprel
[op_ad
] = riprel
;
15749 /* Mask to get a 32-bit address. */
15750 op_address
[op_ad
] = op
& 0xffffffff;
15751 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15756 OP_REG (int code
, int sizeflag
)
15763 case es_reg
: case ss_reg
: case cs_reg
:
15764 case ds_reg
: case fs_reg
: case gs_reg
:
15765 oappend (names_seg
[code
- es_reg
]);
15777 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15778 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15779 s
= names16
[code
- ax_reg
+ add
];
15781 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15782 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15785 s
= names8rex
[code
- al_reg
+ add
];
15787 s
= names8
[code
- al_reg
];
15789 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15790 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15791 if (address_mode
== mode_64bit
15792 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15794 s
= names64
[code
- rAX_reg
+ add
];
15797 code
+= eAX_reg
- rAX_reg
;
15798 /* Fall through. */
15799 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15800 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15803 s
= names64
[code
- eAX_reg
+ add
];
15806 if (sizeflag
& DFLAG
)
15807 s
= names32
[code
- eAX_reg
+ add
];
15809 s
= names16
[code
- eAX_reg
+ add
];
15810 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15814 s
= INTERNAL_DISASSEMBLER_ERROR
;
15821 OP_IMREG (int code
, int sizeflag
)
15833 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15834 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15835 s
= names16
[code
- ax_reg
];
15837 case es_reg
: case ss_reg
: case cs_reg
:
15838 case ds_reg
: case fs_reg
: case gs_reg
:
15839 s
= names_seg
[code
- es_reg
];
15841 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15842 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15845 s
= names8rex
[code
- al_reg
];
15847 s
= names8
[code
- al_reg
];
15849 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15850 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15853 s
= names64
[code
- eAX_reg
];
15856 if (sizeflag
& DFLAG
)
15857 s
= names32
[code
- eAX_reg
];
15859 s
= names16
[code
- eAX_reg
];
15860 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15863 case z_mode_ax_reg
:
15864 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15868 if (!(rex
& REX_W
))
15869 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15872 s
= INTERNAL_DISASSEMBLER_ERROR
;
15879 OP_I (int bytemode
, int sizeflag
)
15882 bfd_signed_vma mask
= -1;
15887 FETCH_DATA (the_info
, codep
+ 1);
15892 if (address_mode
== mode_64bit
)
15897 /* Fall through. */
15904 if (sizeflag
& DFLAG
)
15914 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15926 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15931 scratchbuf
[0] = '$';
15932 print_operand_value (scratchbuf
+ 1, 1, op
);
15933 oappend_maybe_intel (scratchbuf
);
15934 scratchbuf
[0] = '\0';
15938 OP_I64 (int bytemode
, int sizeflag
)
15941 bfd_signed_vma mask
= -1;
15943 if (address_mode
!= mode_64bit
)
15945 OP_I (bytemode
, sizeflag
);
15952 FETCH_DATA (the_info
, codep
+ 1);
15962 if (sizeflag
& DFLAG
)
15972 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15980 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15985 scratchbuf
[0] = '$';
15986 print_operand_value (scratchbuf
+ 1, 1, op
);
15987 oappend_maybe_intel (scratchbuf
);
15988 scratchbuf
[0] = '\0';
15992 OP_sI (int bytemode
, int sizeflag
)
16000 FETCH_DATA (the_info
, codep
+ 1);
16002 if ((op
& 0x80) != 0)
16004 if (bytemode
== b_T_mode
)
16006 if (address_mode
!= mode_64bit
16007 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
16009 /* The operand-size prefix is overridden by a REX prefix. */
16010 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16018 if (!(rex
& REX_W
))
16020 if (sizeflag
& DFLAG
)
16028 /* The operand-size prefix is overridden by a REX prefix. */
16029 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16035 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16039 scratchbuf
[0] = '$';
16040 print_operand_value (scratchbuf
+ 1, 1, op
);
16041 oappend_maybe_intel (scratchbuf
);
16045 OP_J (int bytemode
, int sizeflag
)
16049 bfd_vma segment
= 0;
16054 FETCH_DATA (the_info
, codep
+ 1);
16056 if ((disp
& 0x80) != 0)
16060 if (isa64
== amd64
)
16062 if ((sizeflag
& DFLAG
)
16063 || (address_mode
== mode_64bit
16064 && (isa64
!= amd64
|| (rex
& REX_W
))))
16069 if ((disp
& 0x8000) != 0)
16071 /* In 16bit mode, address is wrapped around at 64k within
16072 the same segment. Otherwise, a data16 prefix on a jump
16073 instruction means that the pc is masked to 16 bits after
16074 the displacement is added! */
16076 if ((prefixes
& PREFIX_DATA
) == 0)
16077 segment
= ((start_pc
+ (codep
- start_codep
))
16078 & ~((bfd_vma
) 0xffff));
16080 if (address_mode
!= mode_64bit
16081 || (isa64
== amd64
&& !(rex
& REX_W
)))
16082 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16085 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16088 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
16090 print_operand_value (scratchbuf
, 1, disp
);
16091 oappend (scratchbuf
);
16095 OP_SEG (int bytemode
, int sizeflag
)
16097 if (bytemode
== w_mode
)
16098 oappend (names_seg
[modrm
.reg
]);
16100 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
16104 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
16108 if (sizeflag
& DFLAG
)
16118 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16120 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
16122 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
16123 oappend (scratchbuf
);
16127 OP_OFF (int bytemode
, int sizeflag
)
16131 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16132 intel_operand_size (bytemode
, sizeflag
);
16135 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16142 if (!active_seg_prefix
)
16144 oappend (names_seg
[ds_reg
- es_reg
]);
16148 print_operand_value (scratchbuf
, 1, off
);
16149 oappend (scratchbuf
);
16153 OP_OFF64 (int bytemode
, int sizeflag
)
16157 if (address_mode
!= mode_64bit
16158 || (prefixes
& PREFIX_ADDR
))
16160 OP_OFF (bytemode
, sizeflag
);
16164 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16165 intel_operand_size (bytemode
, sizeflag
);
16172 if (!active_seg_prefix
)
16174 oappend (names_seg
[ds_reg
- es_reg
]);
16178 print_operand_value (scratchbuf
, 1, off
);
16179 oappend (scratchbuf
);
16183 ptr_reg (int code
, int sizeflag
)
16187 *obufp
++ = open_char
;
16188 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
16189 if (address_mode
== mode_64bit
)
16191 if (!(sizeflag
& AFLAG
))
16192 s
= names32
[code
- eAX_reg
];
16194 s
= names64
[code
- eAX_reg
];
16196 else if (sizeflag
& AFLAG
)
16197 s
= names32
[code
- eAX_reg
];
16199 s
= names16
[code
- eAX_reg
];
16201 *obufp
++ = close_char
;
16206 OP_ESreg (int code
, int sizeflag
)
16212 case 0x6d: /* insw/insl */
16213 intel_operand_size (z_mode
, sizeflag
);
16215 case 0xa5: /* movsw/movsl/movsq */
16216 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16217 case 0xab: /* stosw/stosl */
16218 case 0xaf: /* scasw/scasl */
16219 intel_operand_size (v_mode
, sizeflag
);
16222 intel_operand_size (b_mode
, sizeflag
);
16225 oappend_maybe_intel ("%es:");
16226 ptr_reg (code
, sizeflag
);
16230 OP_DSreg (int code
, int sizeflag
)
16236 case 0x6f: /* outsw/outsl */
16237 intel_operand_size (z_mode
, sizeflag
);
16239 case 0xa5: /* movsw/movsl/movsq */
16240 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16241 case 0xad: /* lodsw/lodsl/lodsq */
16242 intel_operand_size (v_mode
, sizeflag
);
16245 intel_operand_size (b_mode
, sizeflag
);
16248 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16249 default segment register DS is printed. */
16250 if (!active_seg_prefix
)
16251 active_seg_prefix
= PREFIX_DS
;
16253 ptr_reg (code
, sizeflag
);
16257 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16265 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
16267 all_prefixes
[last_lock_prefix
] = 0;
16268 used_prefixes
|= PREFIX_LOCK
;
16273 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
16274 oappend_maybe_intel (scratchbuf
);
16278 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16287 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
16289 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
16290 oappend (scratchbuf
);
16294 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16296 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
16297 oappend_maybe_intel (scratchbuf
);
16301 OP_R (int bytemode
, int sizeflag
)
16303 /* Skip mod/rm byte. */
16306 OP_E_register (bytemode
, sizeflag
);
16310 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16312 int reg
= modrm
.reg
;
16313 const char **names
;
16315 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16316 if (prefixes
& PREFIX_DATA
)
16325 oappend (names
[reg
]);
16329 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16331 int reg
= modrm
.reg
;
16332 const char **names
;
16344 && bytemode
!= xmm_mode
16345 && bytemode
!= xmmq_mode
16346 && bytemode
!= evex_half_bcst_xmmq_mode
16347 && bytemode
!= ymm_mode
16348 && bytemode
!= scalar_mode
)
16350 switch (vex
.length
)
16357 || (bytemode
!= vex_vsib_q_w_dq_mode
16358 && bytemode
!= vex_vsib_q_w_d_mode
))
16370 else if (bytemode
== xmmq_mode
16371 || bytemode
== evex_half_bcst_xmmq_mode
)
16373 switch (vex
.length
)
16386 else if (bytemode
== ymm_mode
)
16390 oappend (names
[reg
]);
16394 OP_EM (int bytemode
, int sizeflag
)
16397 const char **names
;
16399 if (modrm
.mod
!= 3)
16402 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16404 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16405 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16407 OP_E (bytemode
, sizeflag
);
16411 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16414 /* Skip mod/rm byte. */
16417 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16419 if (prefixes
& PREFIX_DATA
)
16428 oappend (names
[reg
]);
16431 /* cvt* are the only instructions in sse2 which have
16432 both SSE and MMX operands and also have 0x66 prefix
16433 in their opcode. 0x66 was originally used to differentiate
16434 between SSE and MMX instruction(operands). So we have to handle the
16435 cvt* separately using OP_EMC and OP_MXC */
16437 OP_EMC (int bytemode
, int sizeflag
)
16439 if (modrm
.mod
!= 3)
16441 if (intel_syntax
&& bytemode
== v_mode
)
16443 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16444 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16446 OP_E (bytemode
, sizeflag
);
16450 /* Skip mod/rm byte. */
16453 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16454 oappend (names_mm
[modrm
.rm
]);
16458 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16460 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16461 oappend (names_mm
[modrm
.reg
]);
16465 OP_EX (int bytemode
, int sizeflag
)
16468 const char **names
;
16470 /* Skip mod/rm byte. */
16474 if (modrm
.mod
!= 3)
16476 OP_E_memory (bytemode
, sizeflag
);
16491 if ((sizeflag
& SUFFIX_ALWAYS
)
16492 && (bytemode
== x_swap_mode
16493 || bytemode
== d_swap_mode
16494 || bytemode
== d_scalar_swap_mode
16495 || bytemode
== q_swap_mode
16496 || bytemode
== q_scalar_swap_mode
))
16500 && bytemode
!= xmm_mode
16501 && bytemode
!= xmmdw_mode
16502 && bytemode
!= xmmqd_mode
16503 && bytemode
!= xmm_mb_mode
16504 && bytemode
!= xmm_mw_mode
16505 && bytemode
!= xmm_md_mode
16506 && bytemode
!= xmm_mq_mode
16507 && bytemode
!= xmm_mdq_mode
16508 && bytemode
!= xmmq_mode
16509 && bytemode
!= evex_half_bcst_xmmq_mode
16510 && bytemode
!= ymm_mode
16511 && bytemode
!= d_scalar_mode
16512 && bytemode
!= d_scalar_swap_mode
16513 && bytemode
!= q_scalar_mode
16514 && bytemode
!= q_scalar_swap_mode
16515 && bytemode
!= vex_scalar_w_dq_mode
)
16517 switch (vex
.length
)
16532 else if (bytemode
== xmmq_mode
16533 || bytemode
== evex_half_bcst_xmmq_mode
)
16535 switch (vex
.length
)
16548 else if (bytemode
== ymm_mode
)
16552 oappend (names
[reg
]);
16556 OP_MS (int bytemode
, int sizeflag
)
16558 if (modrm
.mod
== 3)
16559 OP_EM (bytemode
, sizeflag
);
16565 OP_XS (int bytemode
, int sizeflag
)
16567 if (modrm
.mod
== 3)
16568 OP_EX (bytemode
, sizeflag
);
16574 OP_M (int bytemode
, int sizeflag
)
16576 if (modrm
.mod
== 3)
16577 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16580 OP_E (bytemode
, sizeflag
);
16584 OP_0f07 (int bytemode
, int sizeflag
)
16586 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16589 OP_E (bytemode
, sizeflag
);
16592 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16593 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16596 NOP_Fixup1 (int bytemode
, int sizeflag
)
16598 if ((prefixes
& PREFIX_DATA
) != 0
16601 && address_mode
== mode_64bit
))
16602 OP_REG (bytemode
, sizeflag
);
16604 strcpy (obuf
, "nop");
16608 NOP_Fixup2 (int bytemode
, int sizeflag
)
16610 if ((prefixes
& PREFIX_DATA
) != 0
16613 && address_mode
== mode_64bit
))
16614 OP_IMREG (bytemode
, sizeflag
);
16617 static const char *const Suffix3DNow
[] = {
16618 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16619 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16620 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16621 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16622 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16623 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16624 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16625 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16626 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16627 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16628 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16629 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16630 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16631 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16632 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16633 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16634 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16635 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16636 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16637 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16638 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16639 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16640 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16641 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16642 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16643 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16644 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16645 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16646 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16647 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16648 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16649 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16650 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16651 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16652 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16653 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16654 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16655 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16656 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16657 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16658 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16659 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16660 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16661 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16662 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16663 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16664 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16665 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16666 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16667 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16668 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16669 /* CC */ NULL
, NULL
, NULL
, NULL
,
16670 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16671 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16672 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16673 /* DC */ NULL
, NULL
, NULL
, NULL
,
16674 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16675 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16676 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16677 /* EC */ NULL
, NULL
, NULL
, NULL
,
16678 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16679 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16680 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16681 /* FC */ NULL
, NULL
, NULL
, NULL
,
16685 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16687 const char *mnemonic
;
16689 FETCH_DATA (the_info
, codep
+ 1);
16690 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16691 place where an 8-bit immediate would normally go. ie. the last
16692 byte of the instruction. */
16693 obufp
= mnemonicendp
;
16694 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16696 oappend (mnemonic
);
16699 /* Since a variable sized modrm/sib chunk is between the start
16700 of the opcode (0x0f0f) and the opcode suffix, we need to do
16701 all the modrm processing first, and don't know until now that
16702 we have a bad opcode. This necessitates some cleaning up. */
16703 op_out
[0][0] = '\0';
16704 op_out
[1][0] = '\0';
16707 mnemonicendp
= obufp
;
16710 static struct op simd_cmp_op
[] =
16712 { STRING_COMMA_LEN ("eq") },
16713 { STRING_COMMA_LEN ("lt") },
16714 { STRING_COMMA_LEN ("le") },
16715 { STRING_COMMA_LEN ("unord") },
16716 { STRING_COMMA_LEN ("neq") },
16717 { STRING_COMMA_LEN ("nlt") },
16718 { STRING_COMMA_LEN ("nle") },
16719 { STRING_COMMA_LEN ("ord") }
16723 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16725 unsigned int cmp_type
;
16727 FETCH_DATA (the_info
, codep
+ 1);
16728 cmp_type
= *codep
++ & 0xff;
16729 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16732 char *p
= mnemonicendp
- 2;
16736 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16737 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16741 /* We have a reserved extension byte. Output it directly. */
16742 scratchbuf
[0] = '$';
16743 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16744 oappend_maybe_intel (scratchbuf
);
16745 scratchbuf
[0] = '\0';
16750 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
16751 int sizeflag ATTRIBUTE_UNUSED
)
16753 /* mwaitx %eax,%ecx,%ebx */
16756 const char **names
= (address_mode
== mode_64bit
16757 ? names64
: names32
);
16758 strcpy (op_out
[0], names
[0]);
16759 strcpy (op_out
[1], names
[1]);
16760 strcpy (op_out
[2], names
[3]);
16761 two_source_ops
= 1;
16763 /* Skip mod/rm byte. */
16769 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16770 int sizeflag ATTRIBUTE_UNUSED
)
16772 /* mwait %eax,%ecx */
16775 const char **names
= (address_mode
== mode_64bit
16776 ? names64
: names32
);
16777 strcpy (op_out
[0], names
[0]);
16778 strcpy (op_out
[1], names
[1]);
16779 two_source_ops
= 1;
16781 /* Skip mod/rm byte. */
16787 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16788 int sizeflag ATTRIBUTE_UNUSED
)
16790 /* monitor %eax,%ecx,%edx" */
16793 const char **op1_names
;
16794 const char **names
= (address_mode
== mode_64bit
16795 ? names64
: names32
);
16797 if (!(prefixes
& PREFIX_ADDR
))
16798 op1_names
= (address_mode
== mode_16bit
16799 ? names16
: names
);
16802 /* Remove "addr16/addr32". */
16803 all_prefixes
[last_addr_prefix
] = 0;
16804 op1_names
= (address_mode
!= mode_32bit
16805 ? names32
: names16
);
16806 used_prefixes
|= PREFIX_ADDR
;
16808 strcpy (op_out
[0], op1_names
[0]);
16809 strcpy (op_out
[1], names
[1]);
16810 strcpy (op_out
[2], names
[2]);
16811 two_source_ops
= 1;
16813 /* Skip mod/rm byte. */
16821 /* Throw away prefixes and 1st. opcode byte. */
16822 codep
= insn_codep
+ 1;
16827 REP_Fixup (int bytemode
, int sizeflag
)
16829 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16831 if (prefixes
& PREFIX_REPZ
)
16832 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16839 OP_IMREG (bytemode
, sizeflag
);
16842 OP_ESreg (bytemode
, sizeflag
);
16845 OP_DSreg (bytemode
, sizeflag
);
16853 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16857 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16859 if (prefixes
& PREFIX_REPNZ
)
16860 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16863 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16867 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16868 int sizeflag ATTRIBUTE_UNUSED
)
16870 if (active_seg_prefix
== PREFIX_DS
16871 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
16873 /* NOTRACK prefix is only valid on indirect branch instructions.
16874 NB: DATA prefix is unsupported for Intel64. */
16875 active_seg_prefix
= 0;
16876 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
16880 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16881 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16885 HLE_Fixup1 (int bytemode
, int sizeflag
)
16888 && (prefixes
& PREFIX_LOCK
) != 0)
16890 if (prefixes
& PREFIX_REPZ
)
16891 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16892 if (prefixes
& PREFIX_REPNZ
)
16893 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16896 OP_E (bytemode
, sizeflag
);
16899 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16900 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16904 HLE_Fixup2 (int bytemode
, int sizeflag
)
16906 if (modrm
.mod
!= 3)
16908 if (prefixes
& PREFIX_REPZ
)
16909 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16910 if (prefixes
& PREFIX_REPNZ
)
16911 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16914 OP_E (bytemode
, sizeflag
);
16917 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16918 "xrelease" for memory operand. No check for LOCK prefix. */
16921 HLE_Fixup3 (int bytemode
, int sizeflag
)
16924 && last_repz_prefix
> last_repnz_prefix
16925 && (prefixes
& PREFIX_REPZ
) != 0)
16926 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16928 OP_E (bytemode
, sizeflag
);
16932 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16937 /* Change cmpxchg8b to cmpxchg16b. */
16938 char *p
= mnemonicendp
- 2;
16939 mnemonicendp
= stpcpy (p
, "16b");
16942 else if ((prefixes
& PREFIX_LOCK
) != 0)
16944 if (prefixes
& PREFIX_REPZ
)
16945 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16946 if (prefixes
& PREFIX_REPNZ
)
16947 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16950 OP_M (bytemode
, sizeflag
);
16954 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
16956 const char **names
;
16960 switch (vex
.length
)
16974 oappend (names
[reg
]);
16978 CRC32_Fixup (int bytemode
, int sizeflag
)
16980 /* Add proper suffix to "crc32". */
16981 char *p
= mnemonicendp
;
17000 if (sizeflag
& DFLAG
)
17004 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17008 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17015 if (modrm
.mod
== 3)
17019 /* Skip mod/rm byte. */
17024 add
= (rex
& REX_B
) ? 8 : 0;
17025 if (bytemode
== b_mode
)
17029 oappend (names8rex
[modrm
.rm
+ add
]);
17031 oappend (names8
[modrm
.rm
+ add
]);
17037 oappend (names64
[modrm
.rm
+ add
]);
17038 else if ((prefixes
& PREFIX_DATA
))
17039 oappend (names16
[modrm
.rm
+ add
]);
17041 oappend (names32
[modrm
.rm
+ add
]);
17045 OP_E (bytemode
, sizeflag
);
17049 FXSAVE_Fixup (int bytemode
, int sizeflag
)
17051 /* Add proper suffix to "fxsave" and "fxrstor". */
17055 char *p
= mnemonicendp
;
17061 OP_M (bytemode
, sizeflag
);
17065 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
17067 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17070 char *p
= mnemonicendp
;
17075 else if (sizeflag
& SUFFIX_ALWAYS
)
17082 OP_EX (bytemode
, sizeflag
);
17085 /* Display the destination register operand for instructions with
17089 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17092 const char **names
;
17100 reg
= vex
.register_specifier
;
17107 if (bytemode
== vex_scalar_mode
)
17109 oappend (names_xmm
[reg
]);
17113 switch (vex
.length
)
17120 case vex_vsib_q_w_dq_mode
:
17121 case vex_vsib_q_w_d_mode
:
17137 names
= names_mask
;
17151 case vex_vsib_q_w_dq_mode
:
17152 case vex_vsib_q_w_d_mode
:
17153 names
= vex
.w
? names_ymm
: names_xmm
;
17162 names
= names_mask
;
17165 /* See PR binutils/20893 for a reproducer. */
17177 oappend (names
[reg
]);
17180 /* Get the VEX immediate byte without moving codep. */
17182 static unsigned char
17183 get_vex_imm8 (int sizeflag
, int opnum
)
17185 int bytes_before_imm
= 0;
17187 if (modrm
.mod
!= 3)
17189 /* There are SIB/displacement bytes. */
17190 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
17192 /* 32/64 bit address mode */
17193 int base
= modrm
.rm
;
17195 /* Check SIB byte. */
17198 FETCH_DATA (the_info
, codep
+ 1);
17200 /* When decoding the third source, don't increase
17201 bytes_before_imm as this has already been incremented
17202 by one in OP_E_memory while decoding the second
17205 bytes_before_imm
++;
17208 /* Don't increase bytes_before_imm when decoding the third source,
17209 it has already been incremented by OP_E_memory while decoding
17210 the second source operand. */
17216 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17217 SIB == 5, there is a 4 byte displacement. */
17219 /* No displacement. */
17221 /* Fall through. */
17223 /* 4 byte displacement. */
17224 bytes_before_imm
+= 4;
17227 /* 1 byte displacement. */
17228 bytes_before_imm
++;
17235 /* 16 bit address mode */
17236 /* Don't increase bytes_before_imm when decoding the third source,
17237 it has already been incremented by OP_E_memory while decoding
17238 the second source operand. */
17244 /* When modrm.rm == 6, there is a 2 byte displacement. */
17246 /* No displacement. */
17248 /* Fall through. */
17250 /* 2 byte displacement. */
17251 bytes_before_imm
+= 2;
17254 /* 1 byte displacement: when decoding the third source,
17255 don't increase bytes_before_imm as this has already
17256 been incremented by one in OP_E_memory while decoding
17257 the second source operand. */
17259 bytes_before_imm
++;
17267 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
17268 return codep
[bytes_before_imm
];
17272 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
17274 const char **names
;
17276 if (reg
== -1 && modrm
.mod
!= 3)
17278 OP_E_memory (bytemode
, sizeflag
);
17290 else if (reg
> 7 && address_mode
!= mode_64bit
)
17294 switch (vex
.length
)
17305 oappend (names
[reg
]);
17309 OP_EX_VexImmW (int bytemode
, int sizeflag
)
17312 static unsigned char vex_imm8
;
17314 if (vex_w_done
== 0)
17318 /* Skip mod/rm byte. */
17322 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
17325 reg
= vex_imm8
>> 4;
17327 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17329 else if (vex_w_done
== 1)
17334 reg
= vex_imm8
>> 4;
17336 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17340 /* Output the imm8 directly. */
17341 scratchbuf
[0] = '$';
17342 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
17343 oappend_maybe_intel (scratchbuf
);
17344 scratchbuf
[0] = '\0';
17350 OP_Vex_2src (int bytemode
, int sizeflag
)
17352 if (modrm
.mod
== 3)
17354 int reg
= modrm
.rm
;
17358 oappend (names_xmm
[reg
]);
17363 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
17365 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
17366 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17368 OP_E (bytemode
, sizeflag
);
17373 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
17375 if (modrm
.mod
== 3)
17377 /* Skip mod/rm byte. */
17383 oappend (names_xmm
[vex
.register_specifier
]);
17385 OP_Vex_2src (bytemode
, sizeflag
);
17389 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
17392 OP_Vex_2src (bytemode
, sizeflag
);
17394 oappend (names_xmm
[vex
.register_specifier
]);
17398 OP_EX_VexW (int bytemode
, int sizeflag
)
17406 /* Skip mod/rm byte. */
17411 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
17416 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
17419 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17423 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17424 int sizeflag ATTRIBUTE_UNUSED
)
17426 /* Skip the immediate byte and check for invalid bits. */
17427 FETCH_DATA (the_info
, codep
+ 1);
17428 if (*codep
++ & 0xf)
17433 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17436 const char **names
;
17438 FETCH_DATA (the_info
, codep
+ 1);
17441 if (bytemode
!= x_mode
)
17448 if (reg
> 7 && address_mode
!= mode_64bit
)
17451 switch (vex
.length
)
17462 oappend (names
[reg
]);
17466 OP_XMM_VexW (int bytemode
, int sizeflag
)
17468 /* Turn off the REX.W bit since it is used for swapping operands
17471 OP_XMM (bytemode
, sizeflag
);
17475 OP_EX_Vex (int bytemode
, int sizeflag
)
17477 if (modrm
.mod
!= 3)
17479 if (vex
.register_specifier
!= 0)
17483 OP_EX (bytemode
, sizeflag
);
17487 OP_XMM_Vex (int bytemode
, int sizeflag
)
17489 if (modrm
.mod
!= 3)
17491 if (vex
.register_specifier
!= 0)
17495 OP_XMM (bytemode
, sizeflag
);
17499 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17501 switch (vex
.length
)
17504 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17507 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17514 static struct op vex_cmp_op
[] =
17516 { STRING_COMMA_LEN ("eq") },
17517 { STRING_COMMA_LEN ("lt") },
17518 { STRING_COMMA_LEN ("le") },
17519 { STRING_COMMA_LEN ("unord") },
17520 { STRING_COMMA_LEN ("neq") },
17521 { STRING_COMMA_LEN ("nlt") },
17522 { STRING_COMMA_LEN ("nle") },
17523 { STRING_COMMA_LEN ("ord") },
17524 { STRING_COMMA_LEN ("eq_uq") },
17525 { STRING_COMMA_LEN ("nge") },
17526 { STRING_COMMA_LEN ("ngt") },
17527 { STRING_COMMA_LEN ("false") },
17528 { STRING_COMMA_LEN ("neq_oq") },
17529 { STRING_COMMA_LEN ("ge") },
17530 { STRING_COMMA_LEN ("gt") },
17531 { STRING_COMMA_LEN ("true") },
17532 { STRING_COMMA_LEN ("eq_os") },
17533 { STRING_COMMA_LEN ("lt_oq") },
17534 { STRING_COMMA_LEN ("le_oq") },
17535 { STRING_COMMA_LEN ("unord_s") },
17536 { STRING_COMMA_LEN ("neq_us") },
17537 { STRING_COMMA_LEN ("nlt_uq") },
17538 { STRING_COMMA_LEN ("nle_uq") },
17539 { STRING_COMMA_LEN ("ord_s") },
17540 { STRING_COMMA_LEN ("eq_us") },
17541 { STRING_COMMA_LEN ("nge_uq") },
17542 { STRING_COMMA_LEN ("ngt_uq") },
17543 { STRING_COMMA_LEN ("false_os") },
17544 { STRING_COMMA_LEN ("neq_os") },
17545 { STRING_COMMA_LEN ("ge_oq") },
17546 { STRING_COMMA_LEN ("gt_oq") },
17547 { STRING_COMMA_LEN ("true_us") },
17551 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17553 unsigned int cmp_type
;
17555 FETCH_DATA (the_info
, codep
+ 1);
17556 cmp_type
= *codep
++ & 0xff;
17557 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17560 char *p
= mnemonicendp
- 2;
17564 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17565 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17569 /* We have a reserved extension byte. Output it directly. */
17570 scratchbuf
[0] = '$';
17571 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17572 oappend_maybe_intel (scratchbuf
);
17573 scratchbuf
[0] = '\0';
17578 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17579 int sizeflag ATTRIBUTE_UNUSED
)
17581 unsigned int cmp_type
;
17586 FETCH_DATA (the_info
, codep
+ 1);
17587 cmp_type
= *codep
++ & 0xff;
17588 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17589 If it's the case, print suffix, otherwise - print the immediate. */
17590 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17595 char *p
= mnemonicendp
- 2;
17597 /* vpcmp* can have both one- and two-lettered suffix. */
17611 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17612 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17616 /* We have a reserved extension byte. Output it directly. */
17617 scratchbuf
[0] = '$';
17618 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17619 oappend_maybe_intel (scratchbuf
);
17620 scratchbuf
[0] = '\0';
17624 static const struct op pclmul_op
[] =
17626 { STRING_COMMA_LEN ("lql") },
17627 { STRING_COMMA_LEN ("hql") },
17628 { STRING_COMMA_LEN ("lqh") },
17629 { STRING_COMMA_LEN ("hqh") }
17633 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17634 int sizeflag ATTRIBUTE_UNUSED
)
17636 unsigned int pclmul_type
;
17638 FETCH_DATA (the_info
, codep
+ 1);
17639 pclmul_type
= *codep
++ & 0xff;
17640 switch (pclmul_type
)
17651 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17654 char *p
= mnemonicendp
- 3;
17659 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17660 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17664 /* We have a reserved extension byte. Output it directly. */
17665 scratchbuf
[0] = '$';
17666 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17667 oappend_maybe_intel (scratchbuf
);
17668 scratchbuf
[0] = '\0';
17673 MOVBE_Fixup (int bytemode
, int sizeflag
)
17675 /* Add proper suffix to "movbe". */
17676 char *p
= mnemonicendp
;
17685 if (sizeflag
& SUFFIX_ALWAYS
)
17691 if (sizeflag
& DFLAG
)
17695 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17700 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17707 OP_M (bytemode
, sizeflag
);
17711 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17714 const char **names
;
17716 /* Skip mod/rm byte. */
17730 oappend (names
[reg
]);
17734 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17736 const char **names
;
17743 oappend (names
[vex
.register_specifier
]);
17747 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17750 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17754 if ((rex
& REX_R
) != 0 || !vex
.r
)
17760 oappend (names_mask
[modrm
.reg
]);
17764 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17767 || (bytemode
!= evex_rounding_mode
17768 && bytemode
!= evex_sae_mode
))
17770 if (modrm
.mod
== 3 && vex
.b
)
17773 case evex_rounding_mode
:
17774 oappend (names_rounding
[vex
.ll
]);
17776 case evex_sae_mode
: