1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void NOP_Fixup1 (int, int);
105 static void NOP_Fixup2 (int, int);
106 static void OP_3DNowSuffix (int, int);
107 static void CMP_Fixup (int, int);
108 static void BadOp (void);
109 static void REP_Fixup (int, int);
110 static void SEP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
127 static void MOVSXD_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte
*max_fetched
;
134 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
137 OPCODES_SIGJMP_BUF bailout
;
147 enum address_mode address_mode
;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored
;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes
;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
202 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
203 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
205 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
206 status
= (*info
->read_memory_func
) (start
,
208 addr
- priv
->max_fetched
,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv
->max_fetched
== priv
->the_buffer
)
219 (*info
->memory_error_func
) (status
, start
, info
);
220 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
223 priv
->max_fetched
= addr
;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define EbndS { OP_E, bnd_swap_mode }
252 #define Ev { OP_E, v_mode }
253 #define Eva { OP_E, va_mode }
254 #define Ev_bnd { OP_E, v_bnd_mode }
255 #define EvS { OP_E, v_swap_mode }
256 #define Ed { OP_E, d_mode }
257 #define Edq { OP_E, dq_mode }
258 #define Edqw { OP_E, dqw_mode }
259 #define Edqb { OP_E, dqb_mode }
260 #define Edb { OP_E, db_mode }
261 #define Edw { OP_E, dw_mode }
262 #define Edqd { OP_E, dqd_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mv_bnd { OP_M, v_bndmk_mode }
277 #define Mx { OP_M, x_mode }
278 #define Mxmm { OP_M, xmm_mode }
279 #define Gb { OP_G, b_mode }
280 #define Gbnd { OP_G, bnd_mode }
281 #define Gv { OP_G, v_mode }
282 #define Gd { OP_G, d_mode }
283 #define Gdq { OP_G, dq_mode }
284 #define Gm { OP_G, m_mode }
285 #define Gva { OP_G, va_mode }
286 #define Gw { OP_G, w_mode }
287 #define Rd { OP_R, d_mode }
288 #define Rdq { OP_R, dq_mode }
289 #define Rm { OP_R, m_mode }
290 #define Ib { OP_I, b_mode }
291 #define sIb { OP_sI, b_mode } /* sign extened byte */
292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
293 #define Iv { OP_I, v_mode }
294 #define sIv { OP_sI, v_mode }
295 #define Iv64 { OP_I64, v_mode }
296 #define Id { OP_I, d_mode }
297 #define Iw { OP_I, w_mode }
298 #define I1 { OP_I, const_1_mode }
299 #define Jb { OP_J, b_mode }
300 #define Jv { OP_J, v_mode }
301 #define Jdqw { OP_J, dqw_mode }
302 #define Cm { OP_C, m_mode }
303 #define Dm { OP_D, m_mode }
304 #define Td { OP_T, d_mode }
305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
307 #define RMeAX { OP_REG, eAX_reg }
308 #define RMeBX { OP_REG, eBX_reg }
309 #define RMeCX { OP_REG, eCX_reg }
310 #define RMeDX { OP_REG, eDX_reg }
311 #define RMeSP { OP_REG, eSP_reg }
312 #define RMeBP { OP_REG, eBP_reg }
313 #define RMeSI { OP_REG, eSI_reg }
314 #define RMeDI { OP_REG, eDI_reg }
315 #define RMrAX { OP_REG, rAX_reg }
316 #define RMrBX { OP_REG, rBX_reg }
317 #define RMrCX { OP_REG, rCX_reg }
318 #define RMrDX { OP_REG, rDX_reg }
319 #define RMrSP { OP_REG, rSP_reg }
320 #define RMrBP { OP_REG, rBP_reg }
321 #define RMrSI { OP_REG, rSI_reg }
322 #define RMrDI { OP_REG, rDI_reg }
323 #define RMAL { OP_REG, al_reg }
324 #define RMCL { OP_REG, cl_reg }
325 #define RMDL { OP_REG, dl_reg }
326 #define RMBL { OP_REG, bl_reg }
327 #define RMAH { OP_REG, ah_reg }
328 #define RMCH { OP_REG, ch_reg }
329 #define RMDH { OP_REG, dh_reg }
330 #define RMBH { OP_REG, bh_reg }
331 #define RMAX { OP_REG, ax_reg }
332 #define RMDX { OP_REG, dx_reg }
334 #define eAX { OP_IMREG, eAX_reg }
335 #define eBX { OP_IMREG, eBX_reg }
336 #define eCX { OP_IMREG, eCX_reg }
337 #define eDX { OP_IMREG, eDX_reg }
338 #define eSP { OP_IMREG, eSP_reg }
339 #define eBP { OP_IMREG, eBP_reg }
340 #define eSI { OP_IMREG, eSI_reg }
341 #define eDI { OP_IMREG, eDI_reg }
342 #define AL { OP_IMREG, al_reg }
343 #define CL { OP_IMREG, cl_reg }
344 #define DL { OP_IMREG, dl_reg }
345 #define BL { OP_IMREG, bl_reg }
346 #define AH { OP_IMREG, ah_reg }
347 #define CH { OP_IMREG, ch_reg }
348 #define DH { OP_IMREG, dh_reg }
349 #define BH { OP_IMREG, bh_reg }
350 #define AX { OP_IMREG, ax_reg }
351 #define DX { OP_IMREG, dx_reg }
352 #define zAX { OP_IMREG, z_mode_ax_reg }
353 #define indirDX { OP_IMREG, indir_dx_reg }
355 #define Sw { OP_SEG, w_mode }
356 #define Sv { OP_SEG, v_mode }
357 #define Ap { OP_DIR, 0 }
358 #define Ob { OP_OFF64, b_mode }
359 #define Ov { OP_OFF64, v_mode }
360 #define Xb { OP_DSreg, eSI_reg }
361 #define Xv { OP_DSreg, eSI_reg }
362 #define Xz { OP_DSreg, eSI_reg }
363 #define Yb { OP_ESreg, eDI_reg }
364 #define Yv { OP_ESreg, eDI_reg }
365 #define DSBX { OP_DSreg, eBX_reg }
367 #define es { OP_REG, es_reg }
368 #define ss { OP_REG, ss_reg }
369 #define cs { OP_REG, cs_reg }
370 #define ds { OP_REG, ds_reg }
371 #define fs { OP_REG, fs_reg }
372 #define gs { OP_REG, gs_reg }
374 #define MX { OP_MMX, 0 }
375 #define XM { OP_XMM, 0 }
376 #define XMScalar { OP_XMM, scalar_mode }
377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
378 #define XMM { OP_XMM, xmm_mode }
379 #define XMxmmq { OP_XMM, xmmq_mode }
380 #define EM { OP_EM, v_mode }
381 #define EMS { OP_EM, v_swap_mode }
382 #define EMd { OP_EM, d_mode }
383 #define EMx { OP_EM, x_mode }
384 #define EXbScalar { OP_EX, b_scalar_mode }
385 #define EXw { OP_EX, w_mode }
386 #define EXwScalar { OP_EX, w_scalar_mode }
387 #define EXd { OP_EX, d_mode }
388 #define EXdScalar { OP_EX, d_scalar_mode }
389 #define EXdS { OP_EX, d_swap_mode }
390 #define EXq { OP_EX, q_mode }
391 #define EXqScalar { OP_EX, q_scalar_mode }
392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
393 #define EXqS { OP_EX, q_swap_mode }
394 #define EXx { OP_EX, x_mode }
395 #define EXxS { OP_EX, x_swap_mode }
396 #define EXxmm { OP_EX, xmm_mode }
397 #define EXymm { OP_EX, ymm_mode }
398 #define EXxmmq { OP_EX, xmmq_mode }
399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
402 #define EXxmm_md { OP_EX, xmm_md_mode }
403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
404 #define EXxmmdw { OP_EX, xmmdw_mode }
405 #define EXxmmqd { OP_EX, xmmqd_mode }
406 #define EXymmq { OP_EX, ymmq_mode }
407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
410 #define MS { OP_MS, v_mode }
411 #define XS { OP_XS, v_mode }
412 #define EMCq { OP_EMC, q_mode }
413 #define MXC { OP_MXC, 0 }
414 #define OPSUF { OP_3DNowSuffix, 0 }
415 #define SEP { SEP_Fixup, 0 }
416 #define CMP { CMP_Fixup, 0 }
417 #define XMM0 { XMM_Fixup, 0 }
418 #define FXSAVE { FXSAVE_Fixup, 0 }
419 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
420 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
422 #define Vex { OP_VEX, vex_mode }
423 #define VexScalar { OP_VEX, vex_scalar_mode }
424 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
425 #define Vex128 { OP_VEX, vex128_mode }
426 #define Vex256 { OP_VEX, vex256_mode }
427 #define VexGdq { OP_VEX, dq_mode }
428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
430 #define EXVexW { OP_EX_VexW, x_mode }
431 #define EXdVexW { OP_EX_VexW, d_mode }
432 #define EXqVexW { OP_EX_VexW, q_mode }
433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
435 #define XMVexW { OP_XMM_VexW, 0 }
436 #define XMVexI4 { OP_REG_VexI4, x_mode }
437 #define PCLMUL { PCLMUL_Fixup, 0 }
438 #define VCMP { VCMP_Fixup, 0 }
439 #define VPCMP { VPCMP_Fixup, 0 }
440 #define VPCOM { VPCOM_Fixup, 0 }
442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
443 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
446 #define XMask { OP_Mask, mask_mode }
447 #define MaskG { OP_G, mask_mode }
448 #define MaskE { OP_E, mask_mode }
449 #define MaskBDE { OP_E, mask_bd_mode }
450 #define MaskR { OP_R, mask_mode }
451 #define MaskVex { OP_VEX, mask_mode }
453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
458 /* Used handle "rep" prefix for string instructions. */
459 #define Xbr { REP_Fixup, eSI_reg }
460 #define Xvr { REP_Fixup, eSI_reg }
461 #define Ybr { REP_Fixup, eDI_reg }
462 #define Yvr { REP_Fixup, eDI_reg }
463 #define Yzr { REP_Fixup, eDI_reg }
464 #define indirDXr { REP_Fixup, indir_dx_reg }
465 #define ALr { REP_Fixup, al_reg }
466 #define eAXr { REP_Fixup, eAX_reg }
468 /* Used handle HLE prefix for lockable instructions. */
469 #define Ebh1 { HLE_Fixup1, b_mode }
470 #define Evh1 { HLE_Fixup1, v_mode }
471 #define Ebh2 { HLE_Fixup2, b_mode }
472 #define Evh2 { HLE_Fixup2, v_mode }
473 #define Ebh3 { HLE_Fixup3, b_mode }
474 #define Evh3 { HLE_Fixup3, v_mode }
476 #define BND { BND_Fixup, 0 }
477 #define NOTRACK { NOTRACK_Fixup, 0 }
479 #define cond_jump_flag { NULL, cond_jump_mode }
480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
482 /* bits in sizeflag */
483 #define SUFFIX_ALWAYS 4
491 /* byte operand with operand swapped */
493 /* byte operand, sign extend like 'T' suffix */
495 /* operand size depends on prefixes */
497 /* operand size depends on prefixes with operand swapped */
499 /* operand size depends on address prefix */
503 /* double word operand */
505 /* double word operand with operand swapped */
507 /* quad word operand */
509 /* quad word operand with operand swapped */
511 /* ten-byte operand */
513 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
514 broadcast enabled. */
516 /* Similar to x_mode, but with different EVEX mem shifts. */
518 /* Similar to x_mode, but with disabled broadcast. */
520 /* Similar to x_mode, but with operands swapped and disabled broadcast
523 /* 16-byte XMM operand */
525 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
526 memory operand (depending on vector length). Broadcast isn't
529 /* Same as xmmq_mode, but broadcast is allowed. */
530 evex_half_bcst_xmmq_mode
,
531 /* XMM register or byte memory operand */
533 /* XMM register or word memory operand */
535 /* XMM register or double word memory operand */
537 /* XMM register or quad word memory operand */
539 /* 16-byte XMM, word, double word or quad word operand. */
541 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
543 /* 32-byte YMM operand */
545 /* quad word, ymmword or zmmword memory operand. */
547 /* 32-byte YMM or 16-byte word operand */
549 /* d_mode in 32bit, q_mode in 64bit mode. */
551 /* pair of v_mode operands */
557 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
559 /* operand size depends on REX prefixes. */
561 /* registers like dq_mode, memory like w_mode, displacements like
562 v_mode without considering Intel64 ISA. */
566 /* bounds operand with operand swapped */
568 /* 4- or 6-byte pointer operand */
571 /* v_mode for indirect branch opcodes. */
573 /* v_mode for stack-related opcodes. */
575 /* non-quad operand size depends on prefixes */
577 /* 16-byte operand */
579 /* registers like dq_mode, memory like b_mode. */
581 /* registers like d_mode, memory like b_mode. */
583 /* registers like d_mode, memory like w_mode. */
585 /* registers like dq_mode, memory like d_mode. */
587 /* normal vex mode */
589 /* 128bit vex mode */
591 /* 256bit vex mode */
594 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
595 vex_vsib_d_w_dq_mode
,
596 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
598 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
599 vex_vsib_q_w_dq_mode
,
600 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
603 /* scalar, ignore vector length. */
605 /* like b_mode, ignore vector length. */
607 /* like w_mode, ignore vector length. */
609 /* like d_mode, ignore vector length. */
611 /* like d_swap_mode, ignore vector length. */
613 /* like q_mode, ignore vector length. */
615 /* like q_swap_mode, ignore vector length. */
617 /* like vex_mode, ignore vector length. */
619 /* Operand size depends on the VEX.W bit, ignore vector length. */
620 vex_scalar_w_dq_mode
,
622 /* Static rounding. */
624 /* Static rounding, 64-bit mode only. */
625 evex_rounding_64_mode
,
626 /* Supress all exceptions. */
629 /* Mask register operand. */
631 /* Mask register operand. */
699 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
701 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
702 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
703 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
704 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
705 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
706 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
707 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
708 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
709 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
710 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
711 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
712 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
713 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
714 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
715 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
716 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
844 MOD_VEX_0F12_PREFIX_0
,
846 MOD_VEX_0F16_PREFIX_0
,
849 MOD_VEX_W_0_0F41_P_0_LEN_1
,
850 MOD_VEX_W_1_0F41_P_0_LEN_1
,
851 MOD_VEX_W_0_0F41_P_2_LEN_1
,
852 MOD_VEX_W_1_0F41_P_2_LEN_1
,
853 MOD_VEX_W_0_0F42_P_0_LEN_1
,
854 MOD_VEX_W_1_0F42_P_0_LEN_1
,
855 MOD_VEX_W_0_0F42_P_2_LEN_1
,
856 MOD_VEX_W_1_0F42_P_2_LEN_1
,
857 MOD_VEX_W_0_0F44_P_0_LEN_1
,
858 MOD_VEX_W_1_0F44_P_0_LEN_1
,
859 MOD_VEX_W_0_0F44_P_2_LEN_1
,
860 MOD_VEX_W_1_0F44_P_2_LEN_1
,
861 MOD_VEX_W_0_0F45_P_0_LEN_1
,
862 MOD_VEX_W_1_0F45_P_0_LEN_1
,
863 MOD_VEX_W_0_0F45_P_2_LEN_1
,
864 MOD_VEX_W_1_0F45_P_2_LEN_1
,
865 MOD_VEX_W_0_0F46_P_0_LEN_1
,
866 MOD_VEX_W_1_0F46_P_0_LEN_1
,
867 MOD_VEX_W_0_0F46_P_2_LEN_1
,
868 MOD_VEX_W_1_0F46_P_2_LEN_1
,
869 MOD_VEX_W_0_0F47_P_0_LEN_1
,
870 MOD_VEX_W_1_0F47_P_0_LEN_1
,
871 MOD_VEX_W_0_0F47_P_2_LEN_1
,
872 MOD_VEX_W_1_0F47_P_2_LEN_1
,
873 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
874 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
875 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
876 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
877 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
878 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
879 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
891 MOD_VEX_W_0_0F91_P_0_LEN_0
,
892 MOD_VEX_W_1_0F91_P_0_LEN_0
,
893 MOD_VEX_W_0_0F91_P_2_LEN_0
,
894 MOD_VEX_W_1_0F91_P_2_LEN_0
,
895 MOD_VEX_W_0_0F92_P_0_LEN_0
,
896 MOD_VEX_W_0_0F92_P_2_LEN_0
,
897 MOD_VEX_0F92_P_3_LEN_0
,
898 MOD_VEX_W_0_0F93_P_0_LEN_0
,
899 MOD_VEX_W_0_0F93_P_2_LEN_0
,
900 MOD_VEX_0F93_P_3_LEN_0
,
901 MOD_VEX_W_0_0F98_P_0_LEN_0
,
902 MOD_VEX_W_1_0F98_P_0_LEN_0
,
903 MOD_VEX_W_0_0F98_P_2_LEN_0
,
904 MOD_VEX_W_1_0F98_P_2_LEN_0
,
905 MOD_VEX_W_0_0F99_P_0_LEN_0
,
906 MOD_VEX_W_1_0F99_P_0_LEN_0
,
907 MOD_VEX_W_0_0F99_P_2_LEN_0
,
908 MOD_VEX_W_1_0F99_P_2_LEN_0
,
911 MOD_VEX_0FD7_PREFIX_2
,
912 MOD_VEX_0FE7_PREFIX_2
,
913 MOD_VEX_0FF0_PREFIX_3
,
914 MOD_VEX_0F381A_PREFIX_2
,
915 MOD_VEX_0F382A_PREFIX_2
,
916 MOD_VEX_0F382C_PREFIX_2
,
917 MOD_VEX_0F382D_PREFIX_2
,
918 MOD_VEX_0F382E_PREFIX_2
,
919 MOD_VEX_0F382F_PREFIX_2
,
920 MOD_VEX_0F385A_PREFIX_2
,
921 MOD_VEX_0F388C_PREFIX_2
,
922 MOD_VEX_0F388E_PREFIX_2
,
923 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
924 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
925 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
926 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
927 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
928 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
929 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
930 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
932 MOD_EVEX_0F12_PREFIX_0
,
933 MOD_EVEX_0F16_PREFIX_0
,
934 MOD_EVEX_0F38C6_REG_1
,
935 MOD_EVEX_0F38C6_REG_2
,
936 MOD_EVEX_0F38C6_REG_5
,
937 MOD_EVEX_0F38C6_REG_6
,
938 MOD_EVEX_0F38C7_REG_1
,
939 MOD_EVEX_0F38C7_REG_2
,
940 MOD_EVEX_0F38C7_REG_5
,
941 MOD_EVEX_0F38C7_REG_6
954 RM_0F1E_P_1_MOD_3_REG_7
,
955 RM_0FAE_REG_6_MOD_3_P_0
,
962 PREFIX_0F01_REG_3_RM_1
,
963 PREFIX_0F01_REG_5_MOD_0
,
964 PREFIX_0F01_REG_5_MOD_3_RM_0
,
965 PREFIX_0F01_REG_5_MOD_3_RM_1
,
966 PREFIX_0F01_REG_5_MOD_3_RM_2
,
967 PREFIX_0F01_REG_7_MOD_3_RM_2
,
968 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1010 PREFIX_0FAE_REG_0_MOD_3
,
1011 PREFIX_0FAE_REG_1_MOD_3
,
1012 PREFIX_0FAE_REG_2_MOD_3
,
1013 PREFIX_0FAE_REG_3_MOD_3
,
1014 PREFIX_0FAE_REG_4_MOD_0
,
1015 PREFIX_0FAE_REG_4_MOD_3
,
1016 PREFIX_0FAE_REG_5_MOD_0
,
1017 PREFIX_0FAE_REG_5_MOD_3
,
1018 PREFIX_0FAE_REG_6_MOD_0
,
1019 PREFIX_0FAE_REG_6_MOD_3
,
1020 PREFIX_0FAE_REG_7_MOD_0
,
1026 PREFIX_0FC7_REG_6_MOD_0
,
1027 PREFIX_0FC7_REG_6_MOD_3
,
1028 PREFIX_0FC7_REG_7_MOD_3
,
1158 PREFIX_VEX_0F71_REG_2
,
1159 PREFIX_VEX_0F71_REG_4
,
1160 PREFIX_VEX_0F71_REG_6
,
1161 PREFIX_VEX_0F72_REG_2
,
1162 PREFIX_VEX_0F72_REG_4
,
1163 PREFIX_VEX_0F72_REG_6
,
1164 PREFIX_VEX_0F73_REG_2
,
1165 PREFIX_VEX_0F73_REG_3
,
1166 PREFIX_VEX_0F73_REG_6
,
1167 PREFIX_VEX_0F73_REG_7
,
1340 PREFIX_VEX_0F38F3_REG_1
,
1341 PREFIX_VEX_0F38F3_REG_2
,
1342 PREFIX_VEX_0F38F3_REG_3
,
1461 PREFIX_EVEX_0F71_REG_2
,
1462 PREFIX_EVEX_0F71_REG_4
,
1463 PREFIX_EVEX_0F71_REG_6
,
1464 PREFIX_EVEX_0F72_REG_0
,
1465 PREFIX_EVEX_0F72_REG_1
,
1466 PREFIX_EVEX_0F72_REG_2
,
1467 PREFIX_EVEX_0F72_REG_4
,
1468 PREFIX_EVEX_0F72_REG_6
,
1469 PREFIX_EVEX_0F73_REG_2
,
1470 PREFIX_EVEX_0F73_REG_3
,
1471 PREFIX_EVEX_0F73_REG_6
,
1472 PREFIX_EVEX_0F73_REG_7
,
1669 PREFIX_EVEX_0F38C6_REG_1
,
1670 PREFIX_EVEX_0F38C6_REG_2
,
1671 PREFIX_EVEX_0F38C6_REG_5
,
1672 PREFIX_EVEX_0F38C6_REG_6
,
1673 PREFIX_EVEX_0F38C7_REG_1
,
1674 PREFIX_EVEX_0F38C7_REG_2
,
1675 PREFIX_EVEX_0F38C7_REG_5
,
1676 PREFIX_EVEX_0F38C7_REG_6
,
1780 THREE_BYTE_0F38
= 0,
1807 VEX_LEN_0F12_P_0_M_0
= 0,
1808 VEX_LEN_0F12_P_0_M_1
,
1811 VEX_LEN_0F16_P_0_M_0
,
1812 VEX_LEN_0F16_P_0_M_1
,
1849 VEX_LEN_0FAE_R_2_M_0
,
1850 VEX_LEN_0FAE_R_3_M_0
,
1857 VEX_LEN_0F381A_P_2_M_0
,
1860 VEX_LEN_0F385A_P_2_M_0
,
1863 VEX_LEN_0F38F3_R_1_P_0
,
1864 VEX_LEN_0F38F3_R_2_P_0
,
1865 VEX_LEN_0F38F3_R_3_P_0
,
1908 VEX_LEN_0FXOP_08_CC
,
1909 VEX_LEN_0FXOP_08_CD
,
1910 VEX_LEN_0FXOP_08_CE
,
1911 VEX_LEN_0FXOP_08_CF
,
1912 VEX_LEN_0FXOP_08_EC
,
1913 VEX_LEN_0FXOP_08_ED
,
1914 VEX_LEN_0FXOP_08_EE
,
1915 VEX_LEN_0FXOP_08_EF
,
1916 VEX_LEN_0FXOP_09_80
,
1922 EVEX_LEN_0F6E_P_2
= 0,
1926 EVEX_LEN_0F3819_P_2_W_0
,
1927 EVEX_LEN_0F3819_P_2_W_1
,
1928 EVEX_LEN_0F381A_P_2_W_0
,
1929 EVEX_LEN_0F381A_P_2_W_1
,
1930 EVEX_LEN_0F381B_P_2_W_0
,
1931 EVEX_LEN_0F381B_P_2_W_1
,
1932 EVEX_LEN_0F385A_P_2_W_0
,
1933 EVEX_LEN_0F385A_P_2_W_1
,
1934 EVEX_LEN_0F385B_P_2_W_0
,
1935 EVEX_LEN_0F385B_P_2_W_1
,
1936 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1937 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1938 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1939 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1940 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1941 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1942 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1943 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1944 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1945 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1946 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1947 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1948 EVEX_LEN_0F3A18_P_2_W_0
,
1949 EVEX_LEN_0F3A18_P_2_W_1
,
1950 EVEX_LEN_0F3A19_P_2_W_0
,
1951 EVEX_LEN_0F3A19_P_2_W_1
,
1952 EVEX_LEN_0F3A1A_P_2_W_0
,
1953 EVEX_LEN_0F3A1A_P_2_W_1
,
1954 EVEX_LEN_0F3A1B_P_2_W_0
,
1955 EVEX_LEN_0F3A1B_P_2_W_1
,
1956 EVEX_LEN_0F3A23_P_2_W_0
,
1957 EVEX_LEN_0F3A23_P_2_W_1
,
1958 EVEX_LEN_0F3A38_P_2_W_0
,
1959 EVEX_LEN_0F3A38_P_2_W_1
,
1960 EVEX_LEN_0F3A39_P_2_W_0
,
1961 EVEX_LEN_0F3A39_P_2_W_1
,
1962 EVEX_LEN_0F3A3A_P_2_W_0
,
1963 EVEX_LEN_0F3A3A_P_2_W_1
,
1964 EVEX_LEN_0F3A3B_P_2_W_0
,
1965 EVEX_LEN_0F3A3B_P_2_W_1
,
1966 EVEX_LEN_0F3A43_P_2_W_0
,
1967 EVEX_LEN_0F3A43_P_2_W_1
1972 VEX_W_0F41_P_0_LEN_1
= 0,
1973 VEX_W_0F41_P_2_LEN_1
,
1974 VEX_W_0F42_P_0_LEN_1
,
1975 VEX_W_0F42_P_2_LEN_1
,
1976 VEX_W_0F44_P_0_LEN_0
,
1977 VEX_W_0F44_P_2_LEN_0
,
1978 VEX_W_0F45_P_0_LEN_1
,
1979 VEX_W_0F45_P_2_LEN_1
,
1980 VEX_W_0F46_P_0_LEN_1
,
1981 VEX_W_0F46_P_2_LEN_1
,
1982 VEX_W_0F47_P_0_LEN_1
,
1983 VEX_W_0F47_P_2_LEN_1
,
1984 VEX_W_0F4A_P_0_LEN_1
,
1985 VEX_W_0F4A_P_2_LEN_1
,
1986 VEX_W_0F4B_P_0_LEN_1
,
1987 VEX_W_0F4B_P_2_LEN_1
,
1988 VEX_W_0F90_P_0_LEN_0
,
1989 VEX_W_0F90_P_2_LEN_0
,
1990 VEX_W_0F91_P_0_LEN_0
,
1991 VEX_W_0F91_P_2_LEN_0
,
1992 VEX_W_0F92_P_0_LEN_0
,
1993 VEX_W_0F92_P_2_LEN_0
,
1994 VEX_W_0F93_P_0_LEN_0
,
1995 VEX_W_0F93_P_2_LEN_0
,
1996 VEX_W_0F98_P_0_LEN_0
,
1997 VEX_W_0F98_P_2_LEN_0
,
1998 VEX_W_0F99_P_0_LEN_0
,
1999 VEX_W_0F99_P_2_LEN_0
,
2007 VEX_W_0F381A_P_2_M_0
,
2008 VEX_W_0F382C_P_2_M_0
,
2009 VEX_W_0F382D_P_2_M_0
,
2010 VEX_W_0F382E_P_2_M_0
,
2011 VEX_W_0F382F_P_2_M_0
,
2016 VEX_W_0F385A_P_2_M_0
,
2028 VEX_W_0F3A30_P_2_LEN_0
,
2029 VEX_W_0F3A31_P_2_LEN_0
,
2030 VEX_W_0F3A32_P_2_LEN_0
,
2031 VEX_W_0F3A33_P_2_LEN_0
,
2051 EVEX_W_0F12_P_0_M_0
,
2052 EVEX_W_0F12_P_0_M_1
,
2062 EVEX_W_0F16_P_0_M_0
,
2063 EVEX_W_0F16_P_0_M_1
,
2132 EVEX_W_0F72_R_2_P_2
,
2133 EVEX_W_0F72_R_6_P_2
,
2134 EVEX_W_0F73_R_2_P_2
,
2135 EVEX_W_0F73_R_6_P_2
,
2245 EVEX_W_0F38C7_R_1_P_2
,
2246 EVEX_W_0F38C7_R_2_P_2
,
2247 EVEX_W_0F38C7_R_5_P_2
,
2248 EVEX_W_0F38C7_R_6_P_2
,
2287 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2296 unsigned int prefix_requirement
;
2299 /* Upper case letters in the instruction names here are macros.
2300 'A' => print 'b' if no register operands or suffix_always is true
2301 'B' => print 'b' if suffix_always is true
2302 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2304 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2305 suffix_always is true
2306 'E' => print 'e' if 32-bit form of jcxz
2307 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2308 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2309 'H' => print ",pt" or ",pn" branch hint
2310 'I' => honor following macro letter even in Intel mode (implemented only
2311 for some of the macro letters)
2313 'K' => print 'd' or 'q' if rex prefix is present.
2314 'L' => print 'l' if suffix_always is true
2315 'M' => print 'r' if intel_mnemonic is false.
2316 'N' => print 'n' if instruction has no wait "prefix"
2317 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2318 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2319 or suffix_always is true. print 'q' if rex prefix is present.
2320 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2322 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2323 'S' => print 'w', 'l' or 'q' if suffix_always is true
2324 'T' => print 'q' in 64bit mode if instruction has no operand size
2325 prefix and behave as 'P' otherwise
2326 'U' => print 'q' in 64bit mode if instruction has no operand size
2327 prefix and behave as 'Q' otherwise
2328 'V' => print 'q' in 64bit mode if instruction has no operand size
2329 prefix and behave as 'S' otherwise
2330 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2331 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2333 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2334 '!' => change condition from true to false or from false to true.
2335 '%' => add 1 upper case letter to the macro.
2336 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2337 prefix or suffix_always is true (lcall/ljmp).
2338 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2339 on operand size prefix.
2340 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2341 has no operand size prefix for AMD64 ISA, behave as 'P'
2344 2 upper case letter macros:
2345 "XY" => print 'x' or 'y' if suffix_always is true or no register
2346 operands and no broadcast.
2347 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2348 register operands and no broadcast.
2349 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2350 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2351 or suffix_always is true
2352 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2353 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2354 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2355 "LW" => print 'd', 'q' depending on the VEX.W bit
2356 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2357 an operand size prefix, or suffix_always is true. print
2358 'q' if rex prefix is present.
2360 Many of the above letters print nothing in Intel mode. See "putop"
2363 Braces '{' and '}', and vertical bars '|', indicate alternative
2364 mnemonic strings for AT&T and Intel. */
2366 static const struct dis386 dis386
[] = {
2368 { "addB", { Ebh1
, Gb
}, 0 },
2369 { "addS", { Evh1
, Gv
}, 0 },
2370 { "addB", { Gb
, EbS
}, 0 },
2371 { "addS", { Gv
, EvS
}, 0 },
2372 { "addB", { AL
, Ib
}, 0 },
2373 { "addS", { eAX
, Iv
}, 0 },
2374 { X86_64_TABLE (X86_64_06
) },
2375 { X86_64_TABLE (X86_64_07
) },
2377 { "orB", { Ebh1
, Gb
}, 0 },
2378 { "orS", { Evh1
, Gv
}, 0 },
2379 { "orB", { Gb
, EbS
}, 0 },
2380 { "orS", { Gv
, EvS
}, 0 },
2381 { "orB", { AL
, Ib
}, 0 },
2382 { "orS", { eAX
, Iv
}, 0 },
2383 { X86_64_TABLE (X86_64_0E
) },
2384 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2386 { "adcB", { Ebh1
, Gb
}, 0 },
2387 { "adcS", { Evh1
, Gv
}, 0 },
2388 { "adcB", { Gb
, EbS
}, 0 },
2389 { "adcS", { Gv
, EvS
}, 0 },
2390 { "adcB", { AL
, Ib
}, 0 },
2391 { "adcS", { eAX
, Iv
}, 0 },
2392 { X86_64_TABLE (X86_64_16
) },
2393 { X86_64_TABLE (X86_64_17
) },
2395 { "sbbB", { Ebh1
, Gb
}, 0 },
2396 { "sbbS", { Evh1
, Gv
}, 0 },
2397 { "sbbB", { Gb
, EbS
}, 0 },
2398 { "sbbS", { Gv
, EvS
}, 0 },
2399 { "sbbB", { AL
, Ib
}, 0 },
2400 { "sbbS", { eAX
, Iv
}, 0 },
2401 { X86_64_TABLE (X86_64_1E
) },
2402 { X86_64_TABLE (X86_64_1F
) },
2404 { "andB", { Ebh1
, Gb
}, 0 },
2405 { "andS", { Evh1
, Gv
}, 0 },
2406 { "andB", { Gb
, EbS
}, 0 },
2407 { "andS", { Gv
, EvS
}, 0 },
2408 { "andB", { AL
, Ib
}, 0 },
2409 { "andS", { eAX
, Iv
}, 0 },
2410 { Bad_Opcode
}, /* SEG ES prefix */
2411 { X86_64_TABLE (X86_64_27
) },
2413 { "subB", { Ebh1
, Gb
}, 0 },
2414 { "subS", { Evh1
, Gv
}, 0 },
2415 { "subB", { Gb
, EbS
}, 0 },
2416 { "subS", { Gv
, EvS
}, 0 },
2417 { "subB", { AL
, Ib
}, 0 },
2418 { "subS", { eAX
, Iv
}, 0 },
2419 { Bad_Opcode
}, /* SEG CS prefix */
2420 { X86_64_TABLE (X86_64_2F
) },
2422 { "xorB", { Ebh1
, Gb
}, 0 },
2423 { "xorS", { Evh1
, Gv
}, 0 },
2424 { "xorB", { Gb
, EbS
}, 0 },
2425 { "xorS", { Gv
, EvS
}, 0 },
2426 { "xorB", { AL
, Ib
}, 0 },
2427 { "xorS", { eAX
, Iv
}, 0 },
2428 { Bad_Opcode
}, /* SEG SS prefix */
2429 { X86_64_TABLE (X86_64_37
) },
2431 { "cmpB", { Eb
, Gb
}, 0 },
2432 { "cmpS", { Ev
, Gv
}, 0 },
2433 { "cmpB", { Gb
, EbS
}, 0 },
2434 { "cmpS", { Gv
, EvS
}, 0 },
2435 { "cmpB", { AL
, Ib
}, 0 },
2436 { "cmpS", { eAX
, Iv
}, 0 },
2437 { Bad_Opcode
}, /* SEG DS prefix */
2438 { X86_64_TABLE (X86_64_3F
) },
2440 { "inc{S|}", { RMeAX
}, 0 },
2441 { "inc{S|}", { RMeCX
}, 0 },
2442 { "inc{S|}", { RMeDX
}, 0 },
2443 { "inc{S|}", { RMeBX
}, 0 },
2444 { "inc{S|}", { RMeSP
}, 0 },
2445 { "inc{S|}", { RMeBP
}, 0 },
2446 { "inc{S|}", { RMeSI
}, 0 },
2447 { "inc{S|}", { RMeDI
}, 0 },
2449 { "dec{S|}", { RMeAX
}, 0 },
2450 { "dec{S|}", { RMeCX
}, 0 },
2451 { "dec{S|}", { RMeDX
}, 0 },
2452 { "dec{S|}", { RMeBX
}, 0 },
2453 { "dec{S|}", { RMeSP
}, 0 },
2454 { "dec{S|}", { RMeBP
}, 0 },
2455 { "dec{S|}", { RMeSI
}, 0 },
2456 { "dec{S|}", { RMeDI
}, 0 },
2458 { "pushV", { RMrAX
}, 0 },
2459 { "pushV", { RMrCX
}, 0 },
2460 { "pushV", { RMrDX
}, 0 },
2461 { "pushV", { RMrBX
}, 0 },
2462 { "pushV", { RMrSP
}, 0 },
2463 { "pushV", { RMrBP
}, 0 },
2464 { "pushV", { RMrSI
}, 0 },
2465 { "pushV", { RMrDI
}, 0 },
2467 { "popV", { RMrAX
}, 0 },
2468 { "popV", { RMrCX
}, 0 },
2469 { "popV", { RMrDX
}, 0 },
2470 { "popV", { RMrBX
}, 0 },
2471 { "popV", { RMrSP
}, 0 },
2472 { "popV", { RMrBP
}, 0 },
2473 { "popV", { RMrSI
}, 0 },
2474 { "popV", { RMrDI
}, 0 },
2476 { X86_64_TABLE (X86_64_60
) },
2477 { X86_64_TABLE (X86_64_61
) },
2478 { X86_64_TABLE (X86_64_62
) },
2479 { X86_64_TABLE (X86_64_63
) },
2480 { Bad_Opcode
}, /* seg fs */
2481 { Bad_Opcode
}, /* seg gs */
2482 { Bad_Opcode
}, /* op size prefix */
2483 { Bad_Opcode
}, /* adr size prefix */
2485 { "pushT", { sIv
}, 0 },
2486 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2487 { "pushT", { sIbT
}, 0 },
2488 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2489 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2490 { X86_64_TABLE (X86_64_6D
) },
2491 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2492 { X86_64_TABLE (X86_64_6F
) },
2494 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2495 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2496 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2497 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2498 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2499 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2500 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2501 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2503 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2504 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2505 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2506 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2507 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2508 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2509 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2510 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2512 { REG_TABLE (REG_80
) },
2513 { REG_TABLE (REG_81
) },
2514 { X86_64_TABLE (X86_64_82
) },
2515 { REG_TABLE (REG_83
) },
2516 { "testB", { Eb
, Gb
}, 0 },
2517 { "testS", { Ev
, Gv
}, 0 },
2518 { "xchgB", { Ebh2
, Gb
}, 0 },
2519 { "xchgS", { Evh2
, Gv
}, 0 },
2521 { "movB", { Ebh3
, Gb
}, 0 },
2522 { "movS", { Evh3
, Gv
}, 0 },
2523 { "movB", { Gb
, EbS
}, 0 },
2524 { "movS", { Gv
, EvS
}, 0 },
2525 { "movD", { Sv
, Sw
}, 0 },
2526 { MOD_TABLE (MOD_8D
) },
2527 { "movD", { Sw
, Sv
}, 0 },
2528 { REG_TABLE (REG_8F
) },
2530 { PREFIX_TABLE (PREFIX_90
) },
2531 { "xchgS", { RMeCX
, eAX
}, 0 },
2532 { "xchgS", { RMeDX
, eAX
}, 0 },
2533 { "xchgS", { RMeBX
, eAX
}, 0 },
2534 { "xchgS", { RMeSP
, eAX
}, 0 },
2535 { "xchgS", { RMeBP
, eAX
}, 0 },
2536 { "xchgS", { RMeSI
, eAX
}, 0 },
2537 { "xchgS", { RMeDI
, eAX
}, 0 },
2539 { "cW{t|}R", { XX
}, 0 },
2540 { "cR{t|}O", { XX
}, 0 },
2541 { X86_64_TABLE (X86_64_9A
) },
2542 { Bad_Opcode
}, /* fwait */
2543 { "pushfT", { XX
}, 0 },
2544 { "popfT", { XX
}, 0 },
2545 { "sahf", { XX
}, 0 },
2546 { "lahf", { XX
}, 0 },
2548 { "mov%LB", { AL
, Ob
}, 0 },
2549 { "mov%LS", { eAX
, Ov
}, 0 },
2550 { "mov%LB", { Ob
, AL
}, 0 },
2551 { "mov%LS", { Ov
, eAX
}, 0 },
2552 { "movs{b|}", { Ybr
, Xb
}, 0 },
2553 { "movs{R|}", { Yvr
, Xv
}, 0 },
2554 { "cmps{b|}", { Xb
, Yb
}, 0 },
2555 { "cmps{R|}", { Xv
, Yv
}, 0 },
2557 { "testB", { AL
, Ib
}, 0 },
2558 { "testS", { eAX
, Iv
}, 0 },
2559 { "stosB", { Ybr
, AL
}, 0 },
2560 { "stosS", { Yvr
, eAX
}, 0 },
2561 { "lodsB", { ALr
, Xb
}, 0 },
2562 { "lodsS", { eAXr
, Xv
}, 0 },
2563 { "scasB", { AL
, Yb
}, 0 },
2564 { "scasS", { eAX
, Yv
}, 0 },
2566 { "movB", { RMAL
, Ib
}, 0 },
2567 { "movB", { RMCL
, Ib
}, 0 },
2568 { "movB", { RMDL
, Ib
}, 0 },
2569 { "movB", { RMBL
, Ib
}, 0 },
2570 { "movB", { RMAH
, Ib
}, 0 },
2571 { "movB", { RMCH
, Ib
}, 0 },
2572 { "movB", { RMDH
, Ib
}, 0 },
2573 { "movB", { RMBH
, Ib
}, 0 },
2575 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2576 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2577 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2578 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2579 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2580 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2581 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2582 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2584 { REG_TABLE (REG_C0
) },
2585 { REG_TABLE (REG_C1
) },
2586 { X86_64_TABLE (X86_64_C2
) },
2587 { X86_64_TABLE (X86_64_C3
) },
2588 { X86_64_TABLE (X86_64_C4
) },
2589 { X86_64_TABLE (X86_64_C5
) },
2590 { REG_TABLE (REG_C6
) },
2591 { REG_TABLE (REG_C7
) },
2593 { "enterT", { Iw
, Ib
}, 0 },
2594 { "leaveT", { XX
}, 0 },
2595 { "Jret{|f}P", { Iw
}, 0 },
2596 { "Jret{|f}P", { XX
}, 0 },
2597 { "int3", { XX
}, 0 },
2598 { "int", { Ib
}, 0 },
2599 { X86_64_TABLE (X86_64_CE
) },
2600 { "iret%LP", { XX
}, 0 },
2602 { REG_TABLE (REG_D0
) },
2603 { REG_TABLE (REG_D1
) },
2604 { REG_TABLE (REG_D2
) },
2605 { REG_TABLE (REG_D3
) },
2606 { X86_64_TABLE (X86_64_D4
) },
2607 { X86_64_TABLE (X86_64_D5
) },
2609 { "xlat", { DSBX
}, 0 },
2620 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2621 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2622 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2623 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2624 { "inB", { AL
, Ib
}, 0 },
2625 { "inG", { zAX
, Ib
}, 0 },
2626 { "outB", { Ib
, AL
}, 0 },
2627 { "outG", { Ib
, zAX
}, 0 },
2629 { X86_64_TABLE (X86_64_E8
) },
2630 { X86_64_TABLE (X86_64_E9
) },
2631 { X86_64_TABLE (X86_64_EA
) },
2632 { "jmp", { Jb
, BND
}, 0 },
2633 { "inB", { AL
, indirDX
}, 0 },
2634 { "inG", { zAX
, indirDX
}, 0 },
2635 { "outB", { indirDX
, AL
}, 0 },
2636 { "outG", { indirDX
, zAX
}, 0 },
2638 { Bad_Opcode
}, /* lock prefix */
2639 { "icebp", { XX
}, 0 },
2640 { Bad_Opcode
}, /* repne */
2641 { Bad_Opcode
}, /* repz */
2642 { "hlt", { XX
}, 0 },
2643 { "cmc", { XX
}, 0 },
2644 { REG_TABLE (REG_F6
) },
2645 { REG_TABLE (REG_F7
) },
2647 { "clc", { XX
}, 0 },
2648 { "stc", { XX
}, 0 },
2649 { "cli", { XX
}, 0 },
2650 { "sti", { XX
}, 0 },
2651 { "cld", { XX
}, 0 },
2652 { "std", { XX
}, 0 },
2653 { REG_TABLE (REG_FE
) },
2654 { REG_TABLE (REG_FF
) },
2657 static const struct dis386 dis386_twobyte
[] = {
2659 { REG_TABLE (REG_0F00
) },
2660 { REG_TABLE (REG_0F01
) },
2661 { "larS", { Gv
, Ew
}, 0 },
2662 { "lslS", { Gv
, Ew
}, 0 },
2664 { "syscall", { XX
}, 0 },
2665 { "clts", { XX
}, 0 },
2666 { "sysret%LP", { XX
}, 0 },
2668 { "invd", { XX
}, 0 },
2669 { PREFIX_TABLE (PREFIX_0F09
) },
2671 { "ud2", { XX
}, 0 },
2673 { REG_TABLE (REG_0F0D
) },
2674 { "femms", { XX
}, 0 },
2675 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2677 { PREFIX_TABLE (PREFIX_0F10
) },
2678 { PREFIX_TABLE (PREFIX_0F11
) },
2679 { PREFIX_TABLE (PREFIX_0F12
) },
2680 { MOD_TABLE (MOD_0F13
) },
2681 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2682 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2683 { PREFIX_TABLE (PREFIX_0F16
) },
2684 { MOD_TABLE (MOD_0F17
) },
2686 { REG_TABLE (REG_0F18
) },
2687 { "nopQ", { Ev
}, 0 },
2688 { PREFIX_TABLE (PREFIX_0F1A
) },
2689 { PREFIX_TABLE (PREFIX_0F1B
) },
2690 { PREFIX_TABLE (PREFIX_0F1C
) },
2691 { "nopQ", { Ev
}, 0 },
2692 { PREFIX_TABLE (PREFIX_0F1E
) },
2693 { "nopQ", { Ev
}, 0 },
2695 { "movZ", { Rm
, Cm
}, 0 },
2696 { "movZ", { Rm
, Dm
}, 0 },
2697 { "movZ", { Cm
, Rm
}, 0 },
2698 { "movZ", { Dm
, Rm
}, 0 },
2699 { MOD_TABLE (MOD_0F24
) },
2701 { MOD_TABLE (MOD_0F26
) },
2704 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2705 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2706 { PREFIX_TABLE (PREFIX_0F2A
) },
2707 { PREFIX_TABLE (PREFIX_0F2B
) },
2708 { PREFIX_TABLE (PREFIX_0F2C
) },
2709 { PREFIX_TABLE (PREFIX_0F2D
) },
2710 { PREFIX_TABLE (PREFIX_0F2E
) },
2711 { PREFIX_TABLE (PREFIX_0F2F
) },
2713 { "wrmsr", { XX
}, 0 },
2714 { "rdtsc", { XX
}, 0 },
2715 { "rdmsr", { XX
}, 0 },
2716 { "rdpmc", { XX
}, 0 },
2717 { "sysenter", { SEP
}, 0 },
2718 { "sysexit", { SEP
}, 0 },
2720 { "getsec", { XX
}, 0 },
2722 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2724 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2731 { "cmovoS", { Gv
, Ev
}, 0 },
2732 { "cmovnoS", { Gv
, Ev
}, 0 },
2733 { "cmovbS", { Gv
, Ev
}, 0 },
2734 { "cmovaeS", { Gv
, Ev
}, 0 },
2735 { "cmoveS", { Gv
, Ev
}, 0 },
2736 { "cmovneS", { Gv
, Ev
}, 0 },
2737 { "cmovbeS", { Gv
, Ev
}, 0 },
2738 { "cmovaS", { Gv
, Ev
}, 0 },
2740 { "cmovsS", { Gv
, Ev
}, 0 },
2741 { "cmovnsS", { Gv
, Ev
}, 0 },
2742 { "cmovpS", { Gv
, Ev
}, 0 },
2743 { "cmovnpS", { Gv
, Ev
}, 0 },
2744 { "cmovlS", { Gv
, Ev
}, 0 },
2745 { "cmovgeS", { Gv
, Ev
}, 0 },
2746 { "cmovleS", { Gv
, Ev
}, 0 },
2747 { "cmovgS", { Gv
, Ev
}, 0 },
2749 { MOD_TABLE (MOD_0F51
) },
2750 { PREFIX_TABLE (PREFIX_0F51
) },
2751 { PREFIX_TABLE (PREFIX_0F52
) },
2752 { PREFIX_TABLE (PREFIX_0F53
) },
2753 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2754 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2755 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2756 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2758 { PREFIX_TABLE (PREFIX_0F58
) },
2759 { PREFIX_TABLE (PREFIX_0F59
) },
2760 { PREFIX_TABLE (PREFIX_0F5A
) },
2761 { PREFIX_TABLE (PREFIX_0F5B
) },
2762 { PREFIX_TABLE (PREFIX_0F5C
) },
2763 { PREFIX_TABLE (PREFIX_0F5D
) },
2764 { PREFIX_TABLE (PREFIX_0F5E
) },
2765 { PREFIX_TABLE (PREFIX_0F5F
) },
2767 { PREFIX_TABLE (PREFIX_0F60
) },
2768 { PREFIX_TABLE (PREFIX_0F61
) },
2769 { PREFIX_TABLE (PREFIX_0F62
) },
2770 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2771 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2772 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2773 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2774 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2776 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2777 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2778 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2779 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2780 { PREFIX_TABLE (PREFIX_0F6C
) },
2781 { PREFIX_TABLE (PREFIX_0F6D
) },
2782 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2783 { PREFIX_TABLE (PREFIX_0F6F
) },
2785 { PREFIX_TABLE (PREFIX_0F70
) },
2786 { REG_TABLE (REG_0F71
) },
2787 { REG_TABLE (REG_0F72
) },
2788 { REG_TABLE (REG_0F73
) },
2789 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2790 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2791 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2792 { "emms", { XX
}, PREFIX_OPCODE
},
2794 { PREFIX_TABLE (PREFIX_0F78
) },
2795 { PREFIX_TABLE (PREFIX_0F79
) },
2798 { PREFIX_TABLE (PREFIX_0F7C
) },
2799 { PREFIX_TABLE (PREFIX_0F7D
) },
2800 { PREFIX_TABLE (PREFIX_0F7E
) },
2801 { PREFIX_TABLE (PREFIX_0F7F
) },
2803 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2804 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2805 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2806 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2807 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2808 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2809 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2810 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2812 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2813 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2814 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2815 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2816 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2817 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2818 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2819 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2821 { "seto", { Eb
}, 0 },
2822 { "setno", { Eb
}, 0 },
2823 { "setb", { Eb
}, 0 },
2824 { "setae", { Eb
}, 0 },
2825 { "sete", { Eb
}, 0 },
2826 { "setne", { Eb
}, 0 },
2827 { "setbe", { Eb
}, 0 },
2828 { "seta", { Eb
}, 0 },
2830 { "sets", { Eb
}, 0 },
2831 { "setns", { Eb
}, 0 },
2832 { "setp", { Eb
}, 0 },
2833 { "setnp", { Eb
}, 0 },
2834 { "setl", { Eb
}, 0 },
2835 { "setge", { Eb
}, 0 },
2836 { "setle", { Eb
}, 0 },
2837 { "setg", { Eb
}, 0 },
2839 { "pushT", { fs
}, 0 },
2840 { "popT", { fs
}, 0 },
2841 { "cpuid", { XX
}, 0 },
2842 { "btS", { Ev
, Gv
}, 0 },
2843 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2844 { "shldS", { Ev
, Gv
, CL
}, 0 },
2845 { REG_TABLE (REG_0FA6
) },
2846 { REG_TABLE (REG_0FA7
) },
2848 { "pushT", { gs
}, 0 },
2849 { "popT", { gs
}, 0 },
2850 { "rsm", { XX
}, 0 },
2851 { "btsS", { Evh1
, Gv
}, 0 },
2852 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2853 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2854 { REG_TABLE (REG_0FAE
) },
2855 { "imulS", { Gv
, Ev
}, 0 },
2857 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2858 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2859 { MOD_TABLE (MOD_0FB2
) },
2860 { "btrS", { Evh1
, Gv
}, 0 },
2861 { MOD_TABLE (MOD_0FB4
) },
2862 { MOD_TABLE (MOD_0FB5
) },
2863 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2864 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2866 { PREFIX_TABLE (PREFIX_0FB8
) },
2867 { "ud1S", { Gv
, Ev
}, 0 },
2868 { REG_TABLE (REG_0FBA
) },
2869 { "btcS", { Evh1
, Gv
}, 0 },
2870 { PREFIX_TABLE (PREFIX_0FBC
) },
2871 { PREFIX_TABLE (PREFIX_0FBD
) },
2872 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2873 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2875 { "xaddB", { Ebh1
, Gb
}, 0 },
2876 { "xaddS", { Evh1
, Gv
}, 0 },
2877 { PREFIX_TABLE (PREFIX_0FC2
) },
2878 { MOD_TABLE (MOD_0FC3
) },
2879 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2880 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2881 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2882 { REG_TABLE (REG_0FC7
) },
2884 { "bswap", { RMeAX
}, 0 },
2885 { "bswap", { RMeCX
}, 0 },
2886 { "bswap", { RMeDX
}, 0 },
2887 { "bswap", { RMeBX
}, 0 },
2888 { "bswap", { RMeSP
}, 0 },
2889 { "bswap", { RMeBP
}, 0 },
2890 { "bswap", { RMeSI
}, 0 },
2891 { "bswap", { RMeDI
}, 0 },
2893 { PREFIX_TABLE (PREFIX_0FD0
) },
2894 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2895 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2896 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2897 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2898 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2899 { PREFIX_TABLE (PREFIX_0FD6
) },
2900 { MOD_TABLE (MOD_0FD7
) },
2902 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2903 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2904 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2905 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2906 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2907 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2908 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2909 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2911 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2913 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2915 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2916 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2917 { PREFIX_TABLE (PREFIX_0FE6
) },
2918 { PREFIX_TABLE (PREFIX_0FE7
) },
2920 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2923 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2924 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2925 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2926 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2927 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2929 { PREFIX_TABLE (PREFIX_0FF0
) },
2930 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2931 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2932 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2933 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2934 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2935 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2936 { PREFIX_TABLE (PREFIX_0FF7
) },
2938 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2939 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2940 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2941 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2942 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2943 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2944 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2945 { "ud0S", { Gv
, Ev
}, 0 },
2948 static const unsigned char onebyte_has_modrm
[256] = {
2949 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2950 /* ------------------------------- */
2951 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2952 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2953 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2954 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2955 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2956 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2957 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2958 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2959 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2960 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2961 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2962 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2963 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2964 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2965 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2966 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2967 /* ------------------------------- */
2968 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2971 static const unsigned char twobyte_has_modrm
[256] = {
2972 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2973 /* ------------------------------- */
2974 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2975 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2976 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2977 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2978 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2979 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2980 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2981 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2982 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2983 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2984 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2985 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2986 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2987 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2988 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2989 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2990 /* ------------------------------- */
2991 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2994 static char obuf
[100];
2996 static char *mnemonicendp
;
2997 static char scratchbuf
[100];
2998 static unsigned char *start_codep
;
2999 static unsigned char *insn_codep
;
3000 static unsigned char *codep
;
3001 static unsigned char *end_codep
;
3002 static int last_lock_prefix
;
3003 static int last_repz_prefix
;
3004 static int last_repnz_prefix
;
3005 static int last_data_prefix
;
3006 static int last_addr_prefix
;
3007 static int last_rex_prefix
;
3008 static int last_seg_prefix
;
3009 static int fwait_prefix
;
3010 /* The active segment register prefix. */
3011 static int active_seg_prefix
;
3012 #define MAX_CODE_LENGTH 15
3013 /* We can up to 14 prefixes since the maximum instruction length is
3015 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3016 static disassemble_info
*the_info
;
3024 static unsigned char need_modrm
;
3034 int register_specifier
;
3041 int mask_register_specifier
;
3047 static unsigned char need_vex
;
3048 static unsigned char need_vex_reg
;
3049 static unsigned char vex_w_done
;
3057 /* If we are accessing mod/rm/reg without need_modrm set, then the
3058 values are stale. Hitting this abort likely indicates that you
3059 need to update onebyte_has_modrm or twobyte_has_modrm. */
3060 #define MODRM_CHECK if (!need_modrm) abort ()
3062 static const char **names64
;
3063 static const char **names32
;
3064 static const char **names16
;
3065 static const char **names8
;
3066 static const char **names8rex
;
3067 static const char **names_seg
;
3068 static const char *index64
;
3069 static const char *index32
;
3070 static const char **index16
;
3071 static const char **names_bnd
;
3073 static const char *intel_names64
[] = {
3074 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3075 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3077 static const char *intel_names32
[] = {
3078 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3079 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3081 static const char *intel_names16
[] = {
3082 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3083 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3085 static const char *intel_names8
[] = {
3086 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3088 static const char *intel_names8rex
[] = {
3089 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3090 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3092 static const char *intel_names_seg
[] = {
3093 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3095 static const char *intel_index64
= "riz";
3096 static const char *intel_index32
= "eiz";
3097 static const char *intel_index16
[] = {
3098 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3101 static const char *att_names64
[] = {
3102 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3103 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3105 static const char *att_names32
[] = {
3106 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3107 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3109 static const char *att_names16
[] = {
3110 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3111 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3113 static const char *att_names8
[] = {
3114 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3116 static const char *att_names8rex
[] = {
3117 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3118 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3120 static const char *att_names_seg
[] = {
3121 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3123 static const char *att_index64
= "%riz";
3124 static const char *att_index32
= "%eiz";
3125 static const char *att_index16
[] = {
3126 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3129 static const char **names_mm
;
3130 static const char *intel_names_mm
[] = {
3131 "mm0", "mm1", "mm2", "mm3",
3132 "mm4", "mm5", "mm6", "mm7"
3134 static const char *att_names_mm
[] = {
3135 "%mm0", "%mm1", "%mm2", "%mm3",
3136 "%mm4", "%mm5", "%mm6", "%mm7"
3139 static const char *intel_names_bnd
[] = {
3140 "bnd0", "bnd1", "bnd2", "bnd3"
3143 static const char *att_names_bnd
[] = {
3144 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3147 static const char **names_xmm
;
3148 static const char *intel_names_xmm
[] = {
3149 "xmm0", "xmm1", "xmm2", "xmm3",
3150 "xmm4", "xmm5", "xmm6", "xmm7",
3151 "xmm8", "xmm9", "xmm10", "xmm11",
3152 "xmm12", "xmm13", "xmm14", "xmm15",
3153 "xmm16", "xmm17", "xmm18", "xmm19",
3154 "xmm20", "xmm21", "xmm22", "xmm23",
3155 "xmm24", "xmm25", "xmm26", "xmm27",
3156 "xmm28", "xmm29", "xmm30", "xmm31"
3158 static const char *att_names_xmm
[] = {
3159 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3160 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3161 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3162 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3163 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3164 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3165 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3166 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3169 static const char **names_ymm
;
3170 static const char *intel_names_ymm
[] = {
3171 "ymm0", "ymm1", "ymm2", "ymm3",
3172 "ymm4", "ymm5", "ymm6", "ymm7",
3173 "ymm8", "ymm9", "ymm10", "ymm11",
3174 "ymm12", "ymm13", "ymm14", "ymm15",
3175 "ymm16", "ymm17", "ymm18", "ymm19",
3176 "ymm20", "ymm21", "ymm22", "ymm23",
3177 "ymm24", "ymm25", "ymm26", "ymm27",
3178 "ymm28", "ymm29", "ymm30", "ymm31"
3180 static const char *att_names_ymm
[] = {
3181 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3182 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3183 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3184 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3185 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3186 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3187 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3188 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3191 static const char **names_zmm
;
3192 static const char *intel_names_zmm
[] = {
3193 "zmm0", "zmm1", "zmm2", "zmm3",
3194 "zmm4", "zmm5", "zmm6", "zmm7",
3195 "zmm8", "zmm9", "zmm10", "zmm11",
3196 "zmm12", "zmm13", "zmm14", "zmm15",
3197 "zmm16", "zmm17", "zmm18", "zmm19",
3198 "zmm20", "zmm21", "zmm22", "zmm23",
3199 "zmm24", "zmm25", "zmm26", "zmm27",
3200 "zmm28", "zmm29", "zmm30", "zmm31"
3202 static const char *att_names_zmm
[] = {
3203 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3204 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3205 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3206 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3207 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3208 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3209 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3210 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3213 static const char **names_mask
;
3214 static const char *intel_names_mask
[] = {
3215 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3217 static const char *att_names_mask
[] = {
3218 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3221 static const char *names_rounding
[] =
3229 static const struct dis386 reg_table
[][8] = {
3232 { "addA", { Ebh1
, Ib
}, 0 },
3233 { "orA", { Ebh1
, Ib
}, 0 },
3234 { "adcA", { Ebh1
, Ib
}, 0 },
3235 { "sbbA", { Ebh1
, Ib
}, 0 },
3236 { "andA", { Ebh1
, Ib
}, 0 },
3237 { "subA", { Ebh1
, Ib
}, 0 },
3238 { "xorA", { Ebh1
, Ib
}, 0 },
3239 { "cmpA", { Eb
, Ib
}, 0 },
3243 { "addQ", { Evh1
, Iv
}, 0 },
3244 { "orQ", { Evh1
, Iv
}, 0 },
3245 { "adcQ", { Evh1
, Iv
}, 0 },
3246 { "sbbQ", { Evh1
, Iv
}, 0 },
3247 { "andQ", { Evh1
, Iv
}, 0 },
3248 { "subQ", { Evh1
, Iv
}, 0 },
3249 { "xorQ", { Evh1
, Iv
}, 0 },
3250 { "cmpQ", { Ev
, Iv
}, 0 },
3254 { "addQ", { Evh1
, sIb
}, 0 },
3255 { "orQ", { Evh1
, sIb
}, 0 },
3256 { "adcQ", { Evh1
, sIb
}, 0 },
3257 { "sbbQ", { Evh1
, sIb
}, 0 },
3258 { "andQ", { Evh1
, sIb
}, 0 },
3259 { "subQ", { Evh1
, sIb
}, 0 },
3260 { "xorQ", { Evh1
, sIb
}, 0 },
3261 { "cmpQ", { Ev
, sIb
}, 0 },
3265 { "popU", { stackEv
}, 0 },
3266 { XOP_8F_TABLE (XOP_09
) },
3270 { XOP_8F_TABLE (XOP_09
) },
3274 { "rolA", { Eb
, Ib
}, 0 },
3275 { "rorA", { Eb
, Ib
}, 0 },
3276 { "rclA", { Eb
, Ib
}, 0 },
3277 { "rcrA", { Eb
, Ib
}, 0 },
3278 { "shlA", { Eb
, Ib
}, 0 },
3279 { "shrA", { Eb
, Ib
}, 0 },
3280 { "shlA", { Eb
, Ib
}, 0 },
3281 { "sarA", { Eb
, Ib
}, 0 },
3285 { "rolQ", { Ev
, Ib
}, 0 },
3286 { "rorQ", { Ev
, Ib
}, 0 },
3287 { "rclQ", { Ev
, Ib
}, 0 },
3288 { "rcrQ", { Ev
, Ib
}, 0 },
3289 { "shlQ", { Ev
, Ib
}, 0 },
3290 { "shrQ", { Ev
, Ib
}, 0 },
3291 { "shlQ", { Ev
, Ib
}, 0 },
3292 { "sarQ", { Ev
, Ib
}, 0 },
3296 { "movA", { Ebh3
, Ib
}, 0 },
3303 { MOD_TABLE (MOD_C6_REG_7
) },
3307 { "movQ", { Evh3
, Iv
}, 0 },
3314 { MOD_TABLE (MOD_C7_REG_7
) },
3318 { "rolA", { Eb
, I1
}, 0 },
3319 { "rorA", { Eb
, I1
}, 0 },
3320 { "rclA", { Eb
, I1
}, 0 },
3321 { "rcrA", { Eb
, I1
}, 0 },
3322 { "shlA", { Eb
, I1
}, 0 },
3323 { "shrA", { Eb
, I1
}, 0 },
3324 { "shlA", { Eb
, I1
}, 0 },
3325 { "sarA", { Eb
, I1
}, 0 },
3329 { "rolQ", { Ev
, I1
}, 0 },
3330 { "rorQ", { Ev
, I1
}, 0 },
3331 { "rclQ", { Ev
, I1
}, 0 },
3332 { "rcrQ", { Ev
, I1
}, 0 },
3333 { "shlQ", { Ev
, I1
}, 0 },
3334 { "shrQ", { Ev
, I1
}, 0 },
3335 { "shlQ", { Ev
, I1
}, 0 },
3336 { "sarQ", { Ev
, I1
}, 0 },
3340 { "rolA", { Eb
, CL
}, 0 },
3341 { "rorA", { Eb
, CL
}, 0 },
3342 { "rclA", { Eb
, CL
}, 0 },
3343 { "rcrA", { Eb
, CL
}, 0 },
3344 { "shlA", { Eb
, CL
}, 0 },
3345 { "shrA", { Eb
, CL
}, 0 },
3346 { "shlA", { Eb
, CL
}, 0 },
3347 { "sarA", { Eb
, CL
}, 0 },
3351 { "rolQ", { Ev
, CL
}, 0 },
3352 { "rorQ", { Ev
, CL
}, 0 },
3353 { "rclQ", { Ev
, CL
}, 0 },
3354 { "rcrQ", { Ev
, CL
}, 0 },
3355 { "shlQ", { Ev
, CL
}, 0 },
3356 { "shrQ", { Ev
, CL
}, 0 },
3357 { "shlQ", { Ev
, CL
}, 0 },
3358 { "sarQ", { Ev
, CL
}, 0 },
3362 { "testA", { Eb
, Ib
}, 0 },
3363 { "testA", { Eb
, Ib
}, 0 },
3364 { "notA", { Ebh1
}, 0 },
3365 { "negA", { Ebh1
}, 0 },
3366 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3367 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3368 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3369 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3373 { "testQ", { Ev
, Iv
}, 0 },
3374 { "testQ", { Ev
, Iv
}, 0 },
3375 { "notQ", { Evh1
}, 0 },
3376 { "negQ", { Evh1
}, 0 },
3377 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3378 { "imulQ", { Ev
}, 0 },
3379 { "divQ", { Ev
}, 0 },
3380 { "idivQ", { Ev
}, 0 },
3384 { "incA", { Ebh1
}, 0 },
3385 { "decA", { Ebh1
}, 0 },
3389 { "incQ", { Evh1
}, 0 },
3390 { "decQ", { Evh1
}, 0 },
3391 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3392 { MOD_TABLE (MOD_FF_REG_3
) },
3393 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3394 { MOD_TABLE (MOD_FF_REG_5
) },
3395 { "pushU", { stackEv
}, 0 },
3400 { "sldtD", { Sv
}, 0 },
3401 { "strD", { Sv
}, 0 },
3402 { "lldt", { Ew
}, 0 },
3403 { "ltr", { Ew
}, 0 },
3404 { "verr", { Ew
}, 0 },
3405 { "verw", { Ew
}, 0 },
3411 { MOD_TABLE (MOD_0F01_REG_0
) },
3412 { MOD_TABLE (MOD_0F01_REG_1
) },
3413 { MOD_TABLE (MOD_0F01_REG_2
) },
3414 { MOD_TABLE (MOD_0F01_REG_3
) },
3415 { "smswD", { Sv
}, 0 },
3416 { MOD_TABLE (MOD_0F01_REG_5
) },
3417 { "lmsw", { Ew
}, 0 },
3418 { MOD_TABLE (MOD_0F01_REG_7
) },
3422 { "prefetch", { Mb
}, 0 },
3423 { "prefetchw", { Mb
}, 0 },
3424 { "prefetchwt1", { Mb
}, 0 },
3425 { "prefetch", { Mb
}, 0 },
3426 { "prefetch", { Mb
}, 0 },
3427 { "prefetch", { Mb
}, 0 },
3428 { "prefetch", { Mb
}, 0 },
3429 { "prefetch", { Mb
}, 0 },
3433 { MOD_TABLE (MOD_0F18_REG_0
) },
3434 { MOD_TABLE (MOD_0F18_REG_1
) },
3435 { MOD_TABLE (MOD_0F18_REG_2
) },
3436 { MOD_TABLE (MOD_0F18_REG_3
) },
3437 { MOD_TABLE (MOD_0F18_REG_4
) },
3438 { MOD_TABLE (MOD_0F18_REG_5
) },
3439 { MOD_TABLE (MOD_0F18_REG_6
) },
3440 { MOD_TABLE (MOD_0F18_REG_7
) },
3442 /* REG_0F1C_P_0_MOD_0 */
3444 { "cldemote", { Mb
}, 0 },
3445 { "nopQ", { Ev
}, 0 },
3446 { "nopQ", { Ev
}, 0 },
3447 { "nopQ", { Ev
}, 0 },
3448 { "nopQ", { Ev
}, 0 },
3449 { "nopQ", { Ev
}, 0 },
3450 { "nopQ", { Ev
}, 0 },
3451 { "nopQ", { Ev
}, 0 },
3453 /* REG_0F1E_P_1_MOD_3 */
3455 { "nopQ", { Ev
}, 0 },
3456 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3457 { "nopQ", { Ev
}, 0 },
3458 { "nopQ", { Ev
}, 0 },
3459 { "nopQ", { Ev
}, 0 },
3460 { "nopQ", { Ev
}, 0 },
3461 { "nopQ", { Ev
}, 0 },
3462 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3468 { MOD_TABLE (MOD_0F71_REG_2
) },
3470 { MOD_TABLE (MOD_0F71_REG_4
) },
3472 { MOD_TABLE (MOD_0F71_REG_6
) },
3478 { MOD_TABLE (MOD_0F72_REG_2
) },
3480 { MOD_TABLE (MOD_0F72_REG_4
) },
3482 { MOD_TABLE (MOD_0F72_REG_6
) },
3488 { MOD_TABLE (MOD_0F73_REG_2
) },
3489 { MOD_TABLE (MOD_0F73_REG_3
) },
3492 { MOD_TABLE (MOD_0F73_REG_6
) },
3493 { MOD_TABLE (MOD_0F73_REG_7
) },
3497 { "montmul", { { OP_0f07
, 0 } }, 0 },
3498 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3499 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3503 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3504 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3505 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3506 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3507 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3508 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3512 { MOD_TABLE (MOD_0FAE_REG_0
) },
3513 { MOD_TABLE (MOD_0FAE_REG_1
) },
3514 { MOD_TABLE (MOD_0FAE_REG_2
) },
3515 { MOD_TABLE (MOD_0FAE_REG_3
) },
3516 { MOD_TABLE (MOD_0FAE_REG_4
) },
3517 { MOD_TABLE (MOD_0FAE_REG_5
) },
3518 { MOD_TABLE (MOD_0FAE_REG_6
) },
3519 { MOD_TABLE (MOD_0FAE_REG_7
) },
3527 { "btQ", { Ev
, Ib
}, 0 },
3528 { "btsQ", { Evh1
, Ib
}, 0 },
3529 { "btrQ", { Evh1
, Ib
}, 0 },
3530 { "btcQ", { Evh1
, Ib
}, 0 },
3535 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3537 { MOD_TABLE (MOD_0FC7_REG_3
) },
3538 { MOD_TABLE (MOD_0FC7_REG_4
) },
3539 { MOD_TABLE (MOD_0FC7_REG_5
) },
3540 { MOD_TABLE (MOD_0FC7_REG_6
) },
3541 { MOD_TABLE (MOD_0FC7_REG_7
) },
3547 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3549 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3551 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3557 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3559 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3561 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3567 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3568 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3571 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3572 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3578 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3579 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3581 /* REG_VEX_0F38F3 */
3584 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3585 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3586 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3590 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3591 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3595 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3596 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3598 /* REG_XOP_TBM_01 */
3601 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3602 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3603 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3604 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3605 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3606 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3607 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3609 /* REG_XOP_TBM_02 */
3612 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3617 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3620 #include "i386-dis-evex-reg.h"
3623 static const struct dis386 prefix_table
[][4] = {
3626 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3627 { "pause", { XX
}, 0 },
3628 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3629 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3632 /* PREFIX_0F01_REG_3_MOD_1 */
3634 { "vmmcall", { Skip_MODRM
}, 0 },
3635 { "vmgexit", { Skip_MODRM
}, 0 },
3637 { "vmgexit", { Skip_MODRM
}, 0 },
3640 /* PREFIX_0F01_REG_5_MOD_0 */
3643 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3646 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3648 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3649 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3651 { "xsuspldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3654 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3659 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3662 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3665 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3668 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3670 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3671 { "mcommit", { Skip_MODRM
}, 0 },
3674 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3676 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3681 { "wbinvd", { XX
}, 0 },
3682 { "wbnoinvd", { XX
}, 0 },
3687 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3688 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3689 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3690 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3695 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3696 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3697 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3698 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3703 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3704 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3705 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3706 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3711 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3712 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3713 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3718 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3719 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3720 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3721 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3726 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3727 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3728 { "bndmov", { EbndS
, Gbnd
}, 0 },
3729 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3734 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3735 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3736 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3737 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3742 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3743 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3744 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3745 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3750 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3751 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3752 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3753 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3758 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3759 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3760 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3761 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3766 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3767 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3768 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3769 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3774 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3775 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3776 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3777 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3782 { "ucomiss",{ XM
, EXd
}, 0 },
3784 { "ucomisd",{ XM
, EXq
}, 0 },
3789 { "comiss", { XM
, EXd
}, 0 },
3791 { "comisd", { XM
, EXq
}, 0 },
3796 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3797 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3798 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3799 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3804 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3805 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3810 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3811 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3816 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3817 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3818 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3819 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3824 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3825 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3826 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3827 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3832 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3833 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3834 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3835 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3840 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3841 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3842 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3847 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3848 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3849 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3850 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3855 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3856 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3857 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3858 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3863 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3864 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3865 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3866 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3871 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3872 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3873 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3874 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3879 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3881 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3886 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3888 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3893 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3895 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3902 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3909 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3914 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3915 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3916 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3921 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3922 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3923 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3924 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3927 /* PREFIX_0F73_REG_3 */
3931 { "psrldq", { XS
, Ib
}, 0 },
3934 /* PREFIX_0F73_REG_7 */
3938 { "pslldq", { XS
, Ib
}, 0 },
3943 {"vmread", { Em
, Gm
}, 0 },
3945 {"extrq", { XS
, Ib
, Ib
}, 0 },
3946 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3951 {"vmwrite", { Gm
, Em
}, 0 },
3953 {"extrq", { XM
, XS
}, 0 },
3954 {"insertq", { XM
, XS
}, 0 },
3961 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3962 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3969 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3970 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3975 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3976 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3977 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3982 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3983 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3984 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3987 /* PREFIX_0FAE_REG_0_MOD_3 */
3990 { "rdfsbase", { Ev
}, 0 },
3993 /* PREFIX_0FAE_REG_1_MOD_3 */
3996 { "rdgsbase", { Ev
}, 0 },
3999 /* PREFIX_0FAE_REG_2_MOD_3 */
4002 { "wrfsbase", { Ev
}, 0 },
4005 /* PREFIX_0FAE_REG_3_MOD_3 */
4008 { "wrgsbase", { Ev
}, 0 },
4011 /* PREFIX_0FAE_REG_4_MOD_0 */
4013 { "xsave", { FXSAVE
}, 0 },
4014 { "ptwrite%LQ", { Edq
}, 0 },
4017 /* PREFIX_0FAE_REG_4_MOD_3 */
4020 { "ptwrite%LQ", { Edq
}, 0 },
4023 /* PREFIX_0FAE_REG_5_MOD_0 */
4025 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4028 /* PREFIX_0FAE_REG_5_MOD_3 */
4030 { "lfence", { Skip_MODRM
}, 0 },
4031 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4034 /* PREFIX_0FAE_REG_6_MOD_0 */
4036 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4037 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4038 { "clwb", { Mb
}, PREFIX_OPCODE
},
4041 /* PREFIX_0FAE_REG_6_MOD_3 */
4043 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
4044 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4045 { "tpause", { Edq
}, PREFIX_OPCODE
},
4046 { "umwait", { Edq
}, PREFIX_OPCODE
},
4049 /* PREFIX_0FAE_REG_7_MOD_0 */
4051 { "clflush", { Mb
}, 0 },
4053 { "clflushopt", { Mb
}, 0 },
4059 { "popcntS", { Gv
, Ev
}, 0 },
4064 { "bsfS", { Gv
, Ev
}, 0 },
4065 { "tzcntS", { Gv
, Ev
}, 0 },
4066 { "bsfS", { Gv
, Ev
}, 0 },
4071 { "bsrS", { Gv
, Ev
}, 0 },
4072 { "lzcntS", { Gv
, Ev
}, 0 },
4073 { "bsrS", { Gv
, Ev
}, 0 },
4078 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4079 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4080 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4081 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4084 /* PREFIX_0FC3_MOD_0 */
4086 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4089 /* PREFIX_0FC7_REG_6_MOD_0 */
4091 { "vmptrld",{ Mq
}, 0 },
4092 { "vmxon", { Mq
}, 0 },
4093 { "vmclear",{ Mq
}, 0 },
4096 /* PREFIX_0FC7_REG_6_MOD_3 */
4098 { "rdrand", { Ev
}, 0 },
4100 { "rdrand", { Ev
}, 0 }
4103 /* PREFIX_0FC7_REG_7_MOD_3 */
4105 { "rdseed", { Ev
}, 0 },
4106 { "rdpid", { Em
}, 0 },
4107 { "rdseed", { Ev
}, 0 },
4114 { "addsubpd", { XM
, EXx
}, 0 },
4115 { "addsubps", { XM
, EXx
}, 0 },
4121 { "movq2dq",{ XM
, MS
}, 0 },
4122 { "movq", { EXqS
, XM
}, 0 },
4123 { "movdq2q",{ MX
, XS
}, 0 },
4129 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4130 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4131 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4136 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4138 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4146 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4151 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4153 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4160 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4167 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4174 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4181 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4188 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4195 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4202 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4209 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4216 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4223 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4230 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4237 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4244 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4251 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4258 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4265 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4272 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4279 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4286 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4293 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4300 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4307 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4314 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4321 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4328 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4335 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4342 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4349 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4356 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4363 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4370 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4377 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4384 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4391 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4396 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4401 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4406 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4411 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4416 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4421 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4428 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4435 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4442 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4449 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4456 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4463 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4468 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4470 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4471 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4476 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4478 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4479 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4486 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4491 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4492 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4493 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4500 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4501 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4502 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4507 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4514 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4521 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4528 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4535 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4542 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4549 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4556 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4563 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4570 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4577 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4584 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4591 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4598 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4605 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4612 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4619 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4626 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4633 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4640 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4647 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4654 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4661 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4666 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4673 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4680 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4687 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4690 /* PREFIX_VEX_0F10 */
4692 { "vmovups", { XM
, EXx
}, 0 },
4693 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4694 { "vmovupd", { XM
, EXx
}, 0 },
4695 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4698 /* PREFIX_VEX_0F11 */
4700 { "vmovups", { EXxS
, XM
}, 0 },
4701 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4702 { "vmovupd", { EXxS
, XM
}, 0 },
4703 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4706 /* PREFIX_VEX_0F12 */
4708 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4709 { "vmovsldup", { XM
, EXx
}, 0 },
4710 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4711 { "vmovddup", { XM
, EXymmq
}, 0 },
4714 /* PREFIX_VEX_0F16 */
4716 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4717 { "vmovshdup", { XM
, EXx
}, 0 },
4718 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4721 /* PREFIX_VEX_0F2A */
4724 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4726 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4729 /* PREFIX_VEX_0F2C */
4732 { "vcvttss2si", { Gdq
, EXdScalar
}, 0 },
4734 { "vcvttsd2si", { Gdq
, EXqScalar
}, 0 },
4737 /* PREFIX_VEX_0F2D */
4740 { "vcvtss2si", { Gdq
, EXdScalar
}, 0 },
4742 { "vcvtsd2si", { Gdq
, EXqScalar
}, 0 },
4745 /* PREFIX_VEX_0F2E */
4747 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4749 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4752 /* PREFIX_VEX_0F2F */
4754 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4756 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4759 /* PREFIX_VEX_0F41 */
4761 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4763 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4766 /* PREFIX_VEX_0F42 */
4768 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4770 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4773 /* PREFIX_VEX_0F44 */
4775 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4777 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4780 /* PREFIX_VEX_0F45 */
4782 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4784 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4787 /* PREFIX_VEX_0F46 */
4789 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4791 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4794 /* PREFIX_VEX_0F47 */
4796 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4798 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4801 /* PREFIX_VEX_0F4A */
4803 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4805 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4808 /* PREFIX_VEX_0F4B */
4810 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4812 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4815 /* PREFIX_VEX_0F51 */
4817 { "vsqrtps", { XM
, EXx
}, 0 },
4818 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4819 { "vsqrtpd", { XM
, EXx
}, 0 },
4820 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4823 /* PREFIX_VEX_0F52 */
4825 { "vrsqrtps", { XM
, EXx
}, 0 },
4826 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4829 /* PREFIX_VEX_0F53 */
4831 { "vrcpps", { XM
, EXx
}, 0 },
4832 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4835 /* PREFIX_VEX_0F58 */
4837 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4838 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4839 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4840 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4843 /* PREFIX_VEX_0F59 */
4845 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4846 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4847 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4848 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4851 /* PREFIX_VEX_0F5A */
4853 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4854 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4855 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4856 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4859 /* PREFIX_VEX_0F5B */
4861 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4862 { "vcvttps2dq", { XM
, EXx
}, 0 },
4863 { "vcvtps2dq", { XM
, EXx
}, 0 },
4866 /* PREFIX_VEX_0F5C */
4868 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4869 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4870 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4871 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4874 /* PREFIX_VEX_0F5D */
4876 { "vminps", { XM
, Vex
, EXx
}, 0 },
4877 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4878 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4879 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4882 /* PREFIX_VEX_0F5E */
4884 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4885 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4886 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4887 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4890 /* PREFIX_VEX_0F5F */
4892 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4893 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4894 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4895 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4898 /* PREFIX_VEX_0F60 */
4902 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4905 /* PREFIX_VEX_0F61 */
4909 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4912 /* PREFIX_VEX_0F62 */
4916 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4919 /* PREFIX_VEX_0F63 */
4923 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4926 /* PREFIX_VEX_0F64 */
4930 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4933 /* PREFIX_VEX_0F65 */
4937 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4940 /* PREFIX_VEX_0F66 */
4944 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4947 /* PREFIX_VEX_0F67 */
4951 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4954 /* PREFIX_VEX_0F68 */
4958 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4961 /* PREFIX_VEX_0F69 */
4965 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4968 /* PREFIX_VEX_0F6A */
4972 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4975 /* PREFIX_VEX_0F6B */
4979 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4982 /* PREFIX_VEX_0F6C */
4986 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4989 /* PREFIX_VEX_0F6D */
4993 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4996 /* PREFIX_VEX_0F6E */
5000 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
5003 /* PREFIX_VEX_0F6F */
5006 { "vmovdqu", { XM
, EXx
}, 0 },
5007 { "vmovdqa", { XM
, EXx
}, 0 },
5010 /* PREFIX_VEX_0F70 */
5013 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
5014 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
5015 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
5018 /* PREFIX_VEX_0F71_REG_2 */
5022 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
5025 /* PREFIX_VEX_0F71_REG_4 */
5029 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
5032 /* PREFIX_VEX_0F71_REG_6 */
5036 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
5039 /* PREFIX_VEX_0F72_REG_2 */
5043 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
5046 /* PREFIX_VEX_0F72_REG_4 */
5050 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5053 /* PREFIX_VEX_0F72_REG_6 */
5057 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5060 /* PREFIX_VEX_0F73_REG_2 */
5064 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5067 /* PREFIX_VEX_0F73_REG_3 */
5071 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5074 /* PREFIX_VEX_0F73_REG_6 */
5078 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5081 /* PREFIX_VEX_0F73_REG_7 */
5085 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5088 /* PREFIX_VEX_0F74 */
5092 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5095 /* PREFIX_VEX_0F75 */
5099 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5102 /* PREFIX_VEX_0F76 */
5106 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5109 /* PREFIX_VEX_0F77 */
5111 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5114 /* PREFIX_VEX_0F7C */
5118 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5119 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5122 /* PREFIX_VEX_0F7D */
5126 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5127 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5130 /* PREFIX_VEX_0F7E */
5133 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5134 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5137 /* PREFIX_VEX_0F7F */
5140 { "vmovdqu", { EXxS
, XM
}, 0 },
5141 { "vmovdqa", { EXxS
, XM
}, 0 },
5144 /* PREFIX_VEX_0F90 */
5146 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5148 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5151 /* PREFIX_VEX_0F91 */
5153 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5155 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5158 /* PREFIX_VEX_0F92 */
5160 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5162 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5163 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5166 /* PREFIX_VEX_0F93 */
5168 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5170 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5171 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5174 /* PREFIX_VEX_0F98 */
5176 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5178 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5181 /* PREFIX_VEX_0F99 */
5183 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5185 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5188 /* PREFIX_VEX_0FC2 */
5190 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5191 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5192 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5193 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5196 /* PREFIX_VEX_0FC4 */
5200 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5203 /* PREFIX_VEX_0FC5 */
5207 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5210 /* PREFIX_VEX_0FD0 */
5214 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5215 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5218 /* PREFIX_VEX_0FD1 */
5222 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5225 /* PREFIX_VEX_0FD2 */
5229 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5232 /* PREFIX_VEX_0FD3 */
5236 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5239 /* PREFIX_VEX_0FD4 */
5243 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5246 /* PREFIX_VEX_0FD5 */
5250 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5253 /* PREFIX_VEX_0FD6 */
5257 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5260 /* PREFIX_VEX_0FD7 */
5264 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5267 /* PREFIX_VEX_0FD8 */
5271 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5274 /* PREFIX_VEX_0FD9 */
5278 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5281 /* PREFIX_VEX_0FDA */
5285 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5288 /* PREFIX_VEX_0FDB */
5292 { "vpand", { XM
, Vex
, EXx
}, 0 },
5295 /* PREFIX_VEX_0FDC */
5299 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5302 /* PREFIX_VEX_0FDD */
5306 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5309 /* PREFIX_VEX_0FDE */
5313 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5316 /* PREFIX_VEX_0FDF */
5320 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5323 /* PREFIX_VEX_0FE0 */
5327 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5330 /* PREFIX_VEX_0FE1 */
5334 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5337 /* PREFIX_VEX_0FE2 */
5341 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5344 /* PREFIX_VEX_0FE3 */
5348 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5351 /* PREFIX_VEX_0FE4 */
5355 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5358 /* PREFIX_VEX_0FE5 */
5362 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5365 /* PREFIX_VEX_0FE6 */
5368 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5369 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5370 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5373 /* PREFIX_VEX_0FE7 */
5377 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5380 /* PREFIX_VEX_0FE8 */
5384 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5387 /* PREFIX_VEX_0FE9 */
5391 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5394 /* PREFIX_VEX_0FEA */
5398 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5401 /* PREFIX_VEX_0FEB */
5405 { "vpor", { XM
, Vex
, EXx
}, 0 },
5408 /* PREFIX_VEX_0FEC */
5412 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5415 /* PREFIX_VEX_0FED */
5419 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5422 /* PREFIX_VEX_0FEE */
5426 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5429 /* PREFIX_VEX_0FEF */
5433 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5436 /* PREFIX_VEX_0FF0 */
5441 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5444 /* PREFIX_VEX_0FF1 */
5448 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5451 /* PREFIX_VEX_0FF2 */
5455 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5458 /* PREFIX_VEX_0FF3 */
5462 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5465 /* PREFIX_VEX_0FF4 */
5469 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5472 /* PREFIX_VEX_0FF5 */
5476 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5479 /* PREFIX_VEX_0FF6 */
5483 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5486 /* PREFIX_VEX_0FF7 */
5490 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5493 /* PREFIX_VEX_0FF8 */
5497 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5500 /* PREFIX_VEX_0FF9 */
5504 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5507 /* PREFIX_VEX_0FFA */
5511 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5514 /* PREFIX_VEX_0FFB */
5518 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5521 /* PREFIX_VEX_0FFC */
5525 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5528 /* PREFIX_VEX_0FFD */
5532 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5535 /* PREFIX_VEX_0FFE */
5539 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5542 /* PREFIX_VEX_0F3800 */
5546 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5549 /* PREFIX_VEX_0F3801 */
5553 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5556 /* PREFIX_VEX_0F3802 */
5560 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5563 /* PREFIX_VEX_0F3803 */
5567 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5570 /* PREFIX_VEX_0F3804 */
5574 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5577 /* PREFIX_VEX_0F3805 */
5581 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5584 /* PREFIX_VEX_0F3806 */
5588 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5591 /* PREFIX_VEX_0F3807 */
5595 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5598 /* PREFIX_VEX_0F3808 */
5602 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5605 /* PREFIX_VEX_0F3809 */
5609 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5612 /* PREFIX_VEX_0F380A */
5616 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5619 /* PREFIX_VEX_0F380B */
5623 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5626 /* PREFIX_VEX_0F380C */
5630 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5633 /* PREFIX_VEX_0F380D */
5637 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5640 /* PREFIX_VEX_0F380E */
5644 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5647 /* PREFIX_VEX_0F380F */
5651 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5654 /* PREFIX_VEX_0F3813 */
5658 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5661 /* PREFIX_VEX_0F3816 */
5665 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5668 /* PREFIX_VEX_0F3817 */
5672 { "vptest", { XM
, EXx
}, 0 },
5675 /* PREFIX_VEX_0F3818 */
5679 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5682 /* PREFIX_VEX_0F3819 */
5686 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5689 /* PREFIX_VEX_0F381A */
5693 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5696 /* PREFIX_VEX_0F381C */
5700 { "vpabsb", { XM
, EXx
}, 0 },
5703 /* PREFIX_VEX_0F381D */
5707 { "vpabsw", { XM
, EXx
}, 0 },
5710 /* PREFIX_VEX_0F381E */
5714 { "vpabsd", { XM
, EXx
}, 0 },
5717 /* PREFIX_VEX_0F3820 */
5721 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5724 /* PREFIX_VEX_0F3821 */
5728 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5731 /* PREFIX_VEX_0F3822 */
5735 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5738 /* PREFIX_VEX_0F3823 */
5742 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5745 /* PREFIX_VEX_0F3824 */
5749 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5752 /* PREFIX_VEX_0F3825 */
5756 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5759 /* PREFIX_VEX_0F3828 */
5763 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5766 /* PREFIX_VEX_0F3829 */
5770 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5773 /* PREFIX_VEX_0F382A */
5777 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5780 /* PREFIX_VEX_0F382B */
5784 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5787 /* PREFIX_VEX_0F382C */
5791 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5794 /* PREFIX_VEX_0F382D */
5798 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5801 /* PREFIX_VEX_0F382E */
5805 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5808 /* PREFIX_VEX_0F382F */
5812 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5815 /* PREFIX_VEX_0F3830 */
5819 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5822 /* PREFIX_VEX_0F3831 */
5826 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5829 /* PREFIX_VEX_0F3832 */
5833 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5836 /* PREFIX_VEX_0F3833 */
5840 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5843 /* PREFIX_VEX_0F3834 */
5847 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5850 /* PREFIX_VEX_0F3835 */
5854 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5857 /* PREFIX_VEX_0F3836 */
5861 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5864 /* PREFIX_VEX_0F3837 */
5868 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5871 /* PREFIX_VEX_0F3838 */
5875 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5878 /* PREFIX_VEX_0F3839 */
5882 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5885 /* PREFIX_VEX_0F383A */
5889 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5892 /* PREFIX_VEX_0F383B */
5896 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5899 /* PREFIX_VEX_0F383C */
5903 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5906 /* PREFIX_VEX_0F383D */
5910 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5913 /* PREFIX_VEX_0F383E */
5917 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5920 /* PREFIX_VEX_0F383F */
5924 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5927 /* PREFIX_VEX_0F3840 */
5931 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5934 /* PREFIX_VEX_0F3841 */
5938 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5941 /* PREFIX_VEX_0F3845 */
5945 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5948 /* PREFIX_VEX_0F3846 */
5952 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5955 /* PREFIX_VEX_0F3847 */
5959 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5962 /* PREFIX_VEX_0F3858 */
5966 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5969 /* PREFIX_VEX_0F3859 */
5973 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5976 /* PREFIX_VEX_0F385A */
5980 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5983 /* PREFIX_VEX_0F3878 */
5987 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5990 /* PREFIX_VEX_0F3879 */
5994 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5997 /* PREFIX_VEX_0F388C */
6001 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
6004 /* PREFIX_VEX_0F388E */
6008 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
6011 /* PREFIX_VEX_0F3890 */
6015 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6018 /* PREFIX_VEX_0F3891 */
6022 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6025 /* PREFIX_VEX_0F3892 */
6029 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6032 /* PREFIX_VEX_0F3893 */
6036 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6039 /* PREFIX_VEX_0F3896 */
6043 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6046 /* PREFIX_VEX_0F3897 */
6050 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6053 /* PREFIX_VEX_0F3898 */
6057 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6060 /* PREFIX_VEX_0F3899 */
6064 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6067 /* PREFIX_VEX_0F389A */
6071 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6074 /* PREFIX_VEX_0F389B */
6078 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6081 /* PREFIX_VEX_0F389C */
6085 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6088 /* PREFIX_VEX_0F389D */
6092 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6095 /* PREFIX_VEX_0F389E */
6099 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6102 /* PREFIX_VEX_0F389F */
6106 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6109 /* PREFIX_VEX_0F38A6 */
6113 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6117 /* PREFIX_VEX_0F38A7 */
6121 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6124 /* PREFIX_VEX_0F38A8 */
6128 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6131 /* PREFIX_VEX_0F38A9 */
6135 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6138 /* PREFIX_VEX_0F38AA */
6142 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6145 /* PREFIX_VEX_0F38AB */
6149 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6152 /* PREFIX_VEX_0F38AC */
6156 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6159 /* PREFIX_VEX_0F38AD */
6163 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6166 /* PREFIX_VEX_0F38AE */
6170 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6173 /* PREFIX_VEX_0F38AF */
6177 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6180 /* PREFIX_VEX_0F38B6 */
6184 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6187 /* PREFIX_VEX_0F38B7 */
6191 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6194 /* PREFIX_VEX_0F38B8 */
6198 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6201 /* PREFIX_VEX_0F38B9 */
6205 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6208 /* PREFIX_VEX_0F38BA */
6212 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6215 /* PREFIX_VEX_0F38BB */
6219 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6222 /* PREFIX_VEX_0F38BC */
6226 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6229 /* PREFIX_VEX_0F38BD */
6233 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6236 /* PREFIX_VEX_0F38BE */
6240 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6243 /* PREFIX_VEX_0F38BF */
6247 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6250 /* PREFIX_VEX_0F38CF */
6254 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6257 /* PREFIX_VEX_0F38DB */
6261 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6264 /* PREFIX_VEX_0F38DC */
6268 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6271 /* PREFIX_VEX_0F38DD */
6275 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6278 /* PREFIX_VEX_0F38DE */
6282 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6285 /* PREFIX_VEX_0F38DF */
6289 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6292 /* PREFIX_VEX_0F38F2 */
6294 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6297 /* PREFIX_VEX_0F38F3_REG_1 */
6299 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6302 /* PREFIX_VEX_0F38F3_REG_2 */
6304 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6307 /* PREFIX_VEX_0F38F3_REG_3 */
6309 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6312 /* PREFIX_VEX_0F38F5 */
6314 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6315 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6317 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6320 /* PREFIX_VEX_0F38F6 */
6325 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6328 /* PREFIX_VEX_0F38F7 */
6330 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6331 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6332 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6333 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6336 /* PREFIX_VEX_0F3A00 */
6340 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6343 /* PREFIX_VEX_0F3A01 */
6347 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6350 /* PREFIX_VEX_0F3A02 */
6354 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6357 /* PREFIX_VEX_0F3A04 */
6361 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6364 /* PREFIX_VEX_0F3A05 */
6368 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6371 /* PREFIX_VEX_0F3A06 */
6375 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6378 /* PREFIX_VEX_0F3A08 */
6382 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6385 /* PREFIX_VEX_0F3A09 */
6389 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6392 /* PREFIX_VEX_0F3A0A */
6396 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6399 /* PREFIX_VEX_0F3A0B */
6403 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6406 /* PREFIX_VEX_0F3A0C */
6410 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6413 /* PREFIX_VEX_0F3A0D */
6417 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6420 /* PREFIX_VEX_0F3A0E */
6424 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6427 /* PREFIX_VEX_0F3A0F */
6431 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6434 /* PREFIX_VEX_0F3A14 */
6438 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6441 /* PREFIX_VEX_0F3A15 */
6445 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6448 /* PREFIX_VEX_0F3A16 */
6452 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6455 /* PREFIX_VEX_0F3A17 */
6459 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6462 /* PREFIX_VEX_0F3A18 */
6466 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6469 /* PREFIX_VEX_0F3A19 */
6473 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6476 /* PREFIX_VEX_0F3A1D */
6480 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6483 /* PREFIX_VEX_0F3A20 */
6487 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6490 /* PREFIX_VEX_0F3A21 */
6494 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6497 /* PREFIX_VEX_0F3A22 */
6501 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6504 /* PREFIX_VEX_0F3A30 */
6508 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6511 /* PREFIX_VEX_0F3A31 */
6515 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6518 /* PREFIX_VEX_0F3A32 */
6522 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6525 /* PREFIX_VEX_0F3A33 */
6529 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6532 /* PREFIX_VEX_0F3A38 */
6536 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6539 /* PREFIX_VEX_0F3A39 */
6543 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6546 /* PREFIX_VEX_0F3A40 */
6550 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6553 /* PREFIX_VEX_0F3A41 */
6557 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6560 /* PREFIX_VEX_0F3A42 */
6564 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6567 /* PREFIX_VEX_0F3A44 */
6571 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6574 /* PREFIX_VEX_0F3A46 */
6578 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6581 /* PREFIX_VEX_0F3A48 */
6585 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6588 /* PREFIX_VEX_0F3A49 */
6592 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6595 /* PREFIX_VEX_0F3A4A */
6599 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6602 /* PREFIX_VEX_0F3A4B */
6606 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6609 /* PREFIX_VEX_0F3A4C */
6613 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6616 /* PREFIX_VEX_0F3A5C */
6620 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6623 /* PREFIX_VEX_0F3A5D */
6627 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6630 /* PREFIX_VEX_0F3A5E */
6634 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6637 /* PREFIX_VEX_0F3A5F */
6641 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6644 /* PREFIX_VEX_0F3A60 */
6648 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6652 /* PREFIX_VEX_0F3A61 */
6656 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6659 /* PREFIX_VEX_0F3A62 */
6663 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6666 /* PREFIX_VEX_0F3A63 */
6670 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6673 /* PREFIX_VEX_0F3A68 */
6677 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6680 /* PREFIX_VEX_0F3A69 */
6684 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6687 /* PREFIX_VEX_0F3A6A */
6691 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6694 /* PREFIX_VEX_0F3A6B */
6698 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6701 /* PREFIX_VEX_0F3A6C */
6705 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6708 /* PREFIX_VEX_0F3A6D */
6712 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6715 /* PREFIX_VEX_0F3A6E */
6719 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6722 /* PREFIX_VEX_0F3A6F */
6726 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6729 /* PREFIX_VEX_0F3A78 */
6733 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6736 /* PREFIX_VEX_0F3A79 */
6740 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6743 /* PREFIX_VEX_0F3A7A */
6747 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6750 /* PREFIX_VEX_0F3A7B */
6754 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6757 /* PREFIX_VEX_0F3A7C */
6761 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6765 /* PREFIX_VEX_0F3A7D */
6769 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6772 /* PREFIX_VEX_0F3A7E */
6776 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6779 /* PREFIX_VEX_0F3A7F */
6783 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6786 /* PREFIX_VEX_0F3ACE */
6790 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6793 /* PREFIX_VEX_0F3ACF */
6797 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6800 /* PREFIX_VEX_0F3ADF */
6804 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6807 /* PREFIX_VEX_0F3AF0 */
6812 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6815 #include "i386-dis-evex-prefix.h"
6818 static const struct dis386 x86_64_table
[][2] = {
6821 { "pushP", { es
}, 0 },
6826 { "popP", { es
}, 0 },
6831 { "pushP", { cs
}, 0 },
6836 { "pushP", { ss
}, 0 },
6841 { "popP", { ss
}, 0 },
6846 { "pushP", { ds
}, 0 },
6851 { "popP", { ds
}, 0 },
6856 { "daa", { XX
}, 0 },
6861 { "das", { XX
}, 0 },
6866 { "aaa", { XX
}, 0 },
6871 { "aas", { XX
}, 0 },
6876 { "pushaP", { XX
}, 0 },
6881 { "popaP", { XX
}, 0 },
6886 { MOD_TABLE (MOD_62_32BIT
) },
6887 { EVEX_TABLE (EVEX_0F
) },
6892 { "arpl", { Ew
, Gw
}, 0 },
6893 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
6898 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6899 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6904 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6905 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6910 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6911 { REG_TABLE (REG_80
) },
6916 { "Jcall{T|}", { Ap
}, 0 },
6921 { "retP", { Iw
, BND
}, 0 },
6922 { "ret@", { Iw
, BND
}, 0 },
6927 { "retP", { BND
}, 0 },
6928 { "ret@", { BND
}, 0 },
6933 { MOD_TABLE (MOD_C4_32BIT
) },
6934 { VEX_C4_TABLE (VEX_0F
) },
6939 { MOD_TABLE (MOD_C5_32BIT
) },
6940 { VEX_C5_TABLE (VEX_0F
) },
6945 { "into", { XX
}, 0 },
6950 { "aam", { Ib
}, 0 },
6955 { "aad", { Ib
}, 0 },
6960 { "callP", { Jv
, BND
}, 0 },
6961 { "call@", { Jv
, BND
}, 0 }
6966 { "jmpP", { Jv
, BND
}, 0 },
6967 { "jmp@", { Jv
, BND
}, 0 }
6972 { "Jjmp{T|}", { Ap
}, 0 },
6975 /* X86_64_0F01_REG_0 */
6977 { "sgdt{Q|IQ}", { M
}, 0 },
6978 { "sgdt", { M
}, 0 },
6981 /* X86_64_0F01_REG_1 */
6983 { "sidt{Q|IQ}", { M
}, 0 },
6984 { "sidt", { M
}, 0 },
6987 /* X86_64_0F01_REG_2 */
6989 { "lgdt{Q|Q}", { M
}, 0 },
6990 { "lgdt", { M
}, 0 },
6993 /* X86_64_0F01_REG_3 */
6995 { "lidt{Q|Q}", { M
}, 0 },
6996 { "lidt", { M
}, 0 },
7000 static const struct dis386 three_byte_table
[][256] = {
7002 /* THREE_BYTE_0F38 */
7005 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
7006 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
7007 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
7008 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
7009 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
7010 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
7011 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
7012 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
7014 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
7015 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
7016 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
7017 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
7023 { PREFIX_TABLE (PREFIX_0F3810
) },
7027 { PREFIX_TABLE (PREFIX_0F3814
) },
7028 { PREFIX_TABLE (PREFIX_0F3815
) },
7030 { PREFIX_TABLE (PREFIX_0F3817
) },
7036 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7037 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7038 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7041 { PREFIX_TABLE (PREFIX_0F3820
) },
7042 { PREFIX_TABLE (PREFIX_0F3821
) },
7043 { PREFIX_TABLE (PREFIX_0F3822
) },
7044 { PREFIX_TABLE (PREFIX_0F3823
) },
7045 { PREFIX_TABLE (PREFIX_0F3824
) },
7046 { PREFIX_TABLE (PREFIX_0F3825
) },
7050 { PREFIX_TABLE (PREFIX_0F3828
) },
7051 { PREFIX_TABLE (PREFIX_0F3829
) },
7052 { PREFIX_TABLE (PREFIX_0F382A
) },
7053 { PREFIX_TABLE (PREFIX_0F382B
) },
7059 { PREFIX_TABLE (PREFIX_0F3830
) },
7060 { PREFIX_TABLE (PREFIX_0F3831
) },
7061 { PREFIX_TABLE (PREFIX_0F3832
) },
7062 { PREFIX_TABLE (PREFIX_0F3833
) },
7063 { PREFIX_TABLE (PREFIX_0F3834
) },
7064 { PREFIX_TABLE (PREFIX_0F3835
) },
7066 { PREFIX_TABLE (PREFIX_0F3837
) },
7068 { PREFIX_TABLE (PREFIX_0F3838
) },
7069 { PREFIX_TABLE (PREFIX_0F3839
) },
7070 { PREFIX_TABLE (PREFIX_0F383A
) },
7071 { PREFIX_TABLE (PREFIX_0F383B
) },
7072 { PREFIX_TABLE (PREFIX_0F383C
) },
7073 { PREFIX_TABLE (PREFIX_0F383D
) },
7074 { PREFIX_TABLE (PREFIX_0F383E
) },
7075 { PREFIX_TABLE (PREFIX_0F383F
) },
7077 { PREFIX_TABLE (PREFIX_0F3840
) },
7078 { PREFIX_TABLE (PREFIX_0F3841
) },
7149 { PREFIX_TABLE (PREFIX_0F3880
) },
7150 { PREFIX_TABLE (PREFIX_0F3881
) },
7151 { PREFIX_TABLE (PREFIX_0F3882
) },
7230 { PREFIX_TABLE (PREFIX_0F38C8
) },
7231 { PREFIX_TABLE (PREFIX_0F38C9
) },
7232 { PREFIX_TABLE (PREFIX_0F38CA
) },
7233 { PREFIX_TABLE (PREFIX_0F38CB
) },
7234 { PREFIX_TABLE (PREFIX_0F38CC
) },
7235 { PREFIX_TABLE (PREFIX_0F38CD
) },
7237 { PREFIX_TABLE (PREFIX_0F38CF
) },
7251 { PREFIX_TABLE (PREFIX_0F38DB
) },
7252 { PREFIX_TABLE (PREFIX_0F38DC
) },
7253 { PREFIX_TABLE (PREFIX_0F38DD
) },
7254 { PREFIX_TABLE (PREFIX_0F38DE
) },
7255 { PREFIX_TABLE (PREFIX_0F38DF
) },
7275 { PREFIX_TABLE (PREFIX_0F38F0
) },
7276 { PREFIX_TABLE (PREFIX_0F38F1
) },
7280 { PREFIX_TABLE (PREFIX_0F38F5
) },
7281 { PREFIX_TABLE (PREFIX_0F38F6
) },
7284 { PREFIX_TABLE (PREFIX_0F38F8
) },
7285 { PREFIX_TABLE (PREFIX_0F38F9
) },
7293 /* THREE_BYTE_0F3A */
7305 { PREFIX_TABLE (PREFIX_0F3A08
) },
7306 { PREFIX_TABLE (PREFIX_0F3A09
) },
7307 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7308 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7309 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7310 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7311 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7312 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7318 { PREFIX_TABLE (PREFIX_0F3A14
) },
7319 { PREFIX_TABLE (PREFIX_0F3A15
) },
7320 { PREFIX_TABLE (PREFIX_0F3A16
) },
7321 { PREFIX_TABLE (PREFIX_0F3A17
) },
7332 { PREFIX_TABLE (PREFIX_0F3A20
) },
7333 { PREFIX_TABLE (PREFIX_0F3A21
) },
7334 { PREFIX_TABLE (PREFIX_0F3A22
) },
7368 { PREFIX_TABLE (PREFIX_0F3A40
) },
7369 { PREFIX_TABLE (PREFIX_0F3A41
) },
7370 { PREFIX_TABLE (PREFIX_0F3A42
) },
7372 { PREFIX_TABLE (PREFIX_0F3A44
) },
7404 { PREFIX_TABLE (PREFIX_0F3A60
) },
7405 { PREFIX_TABLE (PREFIX_0F3A61
) },
7406 { PREFIX_TABLE (PREFIX_0F3A62
) },
7407 { PREFIX_TABLE (PREFIX_0F3A63
) },
7525 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7527 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7528 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7546 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7586 static const struct dis386 xop_table
[][256] = {
7739 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7740 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7741 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7749 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7750 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7757 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7758 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7759 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7767 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7768 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7772 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7773 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7776 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7794 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7806 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7807 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7808 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7809 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7819 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7820 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7821 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7822 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7855 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7856 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7857 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7858 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7882 { REG_TABLE (REG_XOP_TBM_01
) },
7883 { REG_TABLE (REG_XOP_TBM_02
) },
7901 { REG_TABLE (REG_XOP_LWPCB
) },
8025 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8026 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8027 { "vfrczss", { XM
, EXd
}, 0 },
8028 { "vfrczsd", { XM
, EXq
}, 0 },
8043 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8044 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8045 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8046 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8047 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8048 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8049 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8050 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8052 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8053 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8054 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8055 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8098 { "vphaddbw", { XM
, EXxmm
}, 0 },
8099 { "vphaddbd", { XM
, EXxmm
}, 0 },
8100 { "vphaddbq", { XM
, EXxmm
}, 0 },
8103 { "vphaddwd", { XM
, EXxmm
}, 0 },
8104 { "vphaddwq", { XM
, EXxmm
}, 0 },
8109 { "vphadddq", { XM
, EXxmm
}, 0 },
8116 { "vphaddubw", { XM
, EXxmm
}, 0 },
8117 { "vphaddubd", { XM
, EXxmm
}, 0 },
8118 { "vphaddubq", { XM
, EXxmm
}, 0 },
8121 { "vphadduwd", { XM
, EXxmm
}, 0 },
8122 { "vphadduwq", { XM
, EXxmm
}, 0 },
8127 { "vphaddudq", { XM
, EXxmm
}, 0 },
8134 { "vphsubbw", { XM
, EXxmm
}, 0 },
8135 { "vphsubwd", { XM
, EXxmm
}, 0 },
8136 { "vphsubdq", { XM
, EXxmm
}, 0 },
8190 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8192 { REG_TABLE (REG_XOP_LWP
) },
8462 static const struct dis386 vex_table
[][256] = {
8484 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8485 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8486 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8487 { MOD_TABLE (MOD_VEX_0F13
) },
8488 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8489 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8490 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8491 { MOD_TABLE (MOD_VEX_0F17
) },
8511 { "vmovapX", { XM
, EXx
}, 0 },
8512 { "vmovapX", { EXxS
, XM
}, 0 },
8513 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8514 { MOD_TABLE (MOD_VEX_0F2B
) },
8515 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8517 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8542 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8550 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8556 { MOD_TABLE (MOD_VEX_0F50
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8560 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8561 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8562 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8563 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8565 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8566 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8575 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8580 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8581 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8583 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8584 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8585 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8586 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8587 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8588 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8589 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8590 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8592 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8593 { REG_TABLE (REG_VEX_0F71
) },
8594 { REG_TABLE (REG_VEX_0F72
) },
8595 { REG_TABLE (REG_VEX_0F73
) },
8596 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8598 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8605 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8606 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8607 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8608 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8628 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8629 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8630 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8631 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8637 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8638 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8661 { REG_TABLE (REG_VEX_0FAE
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8688 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8700 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8814 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8816 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8834 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8835 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8836 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8856 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9030 { REG_TABLE (REG_VEX_0F38F3
) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9165 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9166 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9167 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9168 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9169 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9170 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9171 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9172 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9185 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9279 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9280 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9298 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9318 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9338 #include "i386-dis-evex.h"
9340 static const struct dis386 vex_len_table
[][2] = {
9341 /* VEX_LEN_0F12_P_0_M_0 */
9343 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9346 /* VEX_LEN_0F12_P_0_M_1 */
9348 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9351 /* VEX_LEN_0F12_P_2 */
9353 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9356 /* VEX_LEN_0F13_M_0 */
9358 { "vmovlpX", { EXq
, XM
}, 0 },
9361 /* VEX_LEN_0F16_P_0_M_0 */
9363 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9366 /* VEX_LEN_0F16_P_0_M_1 */
9368 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9371 /* VEX_LEN_0F16_P_2 */
9373 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9376 /* VEX_LEN_0F17_M_0 */
9378 { "vmovhpX", { EXq
, XM
}, 0 },
9381 /* VEX_LEN_0F41_P_0 */
9384 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9386 /* VEX_LEN_0F41_P_2 */
9389 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9391 /* VEX_LEN_0F42_P_0 */
9394 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9396 /* VEX_LEN_0F42_P_2 */
9399 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9401 /* VEX_LEN_0F44_P_0 */
9403 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9405 /* VEX_LEN_0F44_P_2 */
9407 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9409 /* VEX_LEN_0F45_P_0 */
9412 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9414 /* VEX_LEN_0F45_P_2 */
9417 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9419 /* VEX_LEN_0F46_P_0 */
9422 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9424 /* VEX_LEN_0F46_P_2 */
9427 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9429 /* VEX_LEN_0F47_P_0 */
9432 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9434 /* VEX_LEN_0F47_P_2 */
9437 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9439 /* VEX_LEN_0F4A_P_0 */
9442 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9444 /* VEX_LEN_0F4A_P_2 */
9447 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9449 /* VEX_LEN_0F4B_P_0 */
9452 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9454 /* VEX_LEN_0F4B_P_2 */
9457 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9460 /* VEX_LEN_0F6E_P_2 */
9462 { "vmovK", { XMScalar
, Edq
}, 0 },
9465 /* VEX_LEN_0F77_P_1 */
9467 { "vzeroupper", { XX
}, 0 },
9468 { "vzeroall", { XX
}, 0 },
9471 /* VEX_LEN_0F7E_P_1 */
9473 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9476 /* VEX_LEN_0F7E_P_2 */
9478 { "vmovK", { Edq
, XMScalar
}, 0 },
9481 /* VEX_LEN_0F90_P_0 */
9483 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9486 /* VEX_LEN_0F90_P_2 */
9488 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9491 /* VEX_LEN_0F91_P_0 */
9493 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9496 /* VEX_LEN_0F91_P_2 */
9498 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9501 /* VEX_LEN_0F92_P_0 */
9503 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9506 /* VEX_LEN_0F92_P_2 */
9508 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9511 /* VEX_LEN_0F92_P_3 */
9513 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9516 /* VEX_LEN_0F93_P_0 */
9518 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9521 /* VEX_LEN_0F93_P_2 */
9523 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9526 /* VEX_LEN_0F93_P_3 */
9528 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9531 /* VEX_LEN_0F98_P_0 */
9533 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9536 /* VEX_LEN_0F98_P_2 */
9538 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9541 /* VEX_LEN_0F99_P_0 */
9543 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9546 /* VEX_LEN_0F99_P_2 */
9548 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9551 /* VEX_LEN_0FAE_R_2_M_0 */
9553 { "vldmxcsr", { Md
}, 0 },
9556 /* VEX_LEN_0FAE_R_3_M_0 */
9558 { "vstmxcsr", { Md
}, 0 },
9561 /* VEX_LEN_0FC4_P_2 */
9563 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9566 /* VEX_LEN_0FC5_P_2 */
9568 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9571 /* VEX_LEN_0FD6_P_2 */
9573 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9576 /* VEX_LEN_0FF7_P_2 */
9578 { "vmaskmovdqu", { XM
, XS
}, 0 },
9581 /* VEX_LEN_0F3816_P_2 */
9584 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9587 /* VEX_LEN_0F3819_P_2 */
9590 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9593 /* VEX_LEN_0F381A_P_2_M_0 */
9596 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9599 /* VEX_LEN_0F3836_P_2 */
9602 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9605 /* VEX_LEN_0F3841_P_2 */
9607 { "vphminposuw", { XM
, EXx
}, 0 },
9610 /* VEX_LEN_0F385A_P_2_M_0 */
9613 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9616 /* VEX_LEN_0F38DB_P_2 */
9618 { "vaesimc", { XM
, EXx
}, 0 },
9621 /* VEX_LEN_0F38F2_P_0 */
9623 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9626 /* VEX_LEN_0F38F3_R_1_P_0 */
9628 { "blsrS", { VexGdq
, Edq
}, 0 },
9631 /* VEX_LEN_0F38F3_R_2_P_0 */
9633 { "blsmskS", { VexGdq
, Edq
}, 0 },
9636 /* VEX_LEN_0F38F3_R_3_P_0 */
9638 { "blsiS", { VexGdq
, Edq
}, 0 },
9641 /* VEX_LEN_0F38F5_P_0 */
9643 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9646 /* VEX_LEN_0F38F5_P_1 */
9648 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9651 /* VEX_LEN_0F38F5_P_3 */
9653 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9656 /* VEX_LEN_0F38F6_P_3 */
9658 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9661 /* VEX_LEN_0F38F7_P_0 */
9663 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9666 /* VEX_LEN_0F38F7_P_1 */
9668 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9671 /* VEX_LEN_0F38F7_P_2 */
9673 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9676 /* VEX_LEN_0F38F7_P_3 */
9678 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9681 /* VEX_LEN_0F3A00_P_2 */
9684 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9687 /* VEX_LEN_0F3A01_P_2 */
9690 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9693 /* VEX_LEN_0F3A06_P_2 */
9696 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9699 /* VEX_LEN_0F3A14_P_2 */
9701 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9704 /* VEX_LEN_0F3A15_P_2 */
9706 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9709 /* VEX_LEN_0F3A16_P_2 */
9711 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9714 /* VEX_LEN_0F3A17_P_2 */
9716 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9719 /* VEX_LEN_0F3A18_P_2 */
9722 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9725 /* VEX_LEN_0F3A19_P_2 */
9728 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9731 /* VEX_LEN_0F3A20_P_2 */
9733 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9736 /* VEX_LEN_0F3A21_P_2 */
9738 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9741 /* VEX_LEN_0F3A22_P_2 */
9743 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9746 /* VEX_LEN_0F3A30_P_2 */
9748 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9751 /* VEX_LEN_0F3A31_P_2 */
9753 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9756 /* VEX_LEN_0F3A32_P_2 */
9758 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9761 /* VEX_LEN_0F3A33_P_2 */
9763 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9766 /* VEX_LEN_0F3A38_P_2 */
9769 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9772 /* VEX_LEN_0F3A39_P_2 */
9775 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9778 /* VEX_LEN_0F3A41_P_2 */
9780 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9783 /* VEX_LEN_0F3A46_P_2 */
9786 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9789 /* VEX_LEN_0F3A60_P_2 */
9791 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9794 /* VEX_LEN_0F3A61_P_2 */
9796 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9799 /* VEX_LEN_0F3A62_P_2 */
9801 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9804 /* VEX_LEN_0F3A63_P_2 */
9806 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9809 /* VEX_LEN_0F3A6A_P_2 */
9811 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9814 /* VEX_LEN_0F3A6B_P_2 */
9816 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9819 /* VEX_LEN_0F3A6E_P_2 */
9821 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9824 /* VEX_LEN_0F3A6F_P_2 */
9826 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9829 /* VEX_LEN_0F3A7A_P_2 */
9831 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9834 /* VEX_LEN_0F3A7B_P_2 */
9836 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9839 /* VEX_LEN_0F3A7E_P_2 */
9841 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9844 /* VEX_LEN_0F3A7F_P_2 */
9846 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9849 /* VEX_LEN_0F3ADF_P_2 */
9851 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9854 /* VEX_LEN_0F3AF0_P_3 */
9856 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9859 /* VEX_LEN_0FXOP_08_CC */
9861 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9864 /* VEX_LEN_0FXOP_08_CD */
9866 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9869 /* VEX_LEN_0FXOP_08_CE */
9871 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9874 /* VEX_LEN_0FXOP_08_CF */
9876 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9879 /* VEX_LEN_0FXOP_08_EC */
9881 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9884 /* VEX_LEN_0FXOP_08_ED */
9886 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9889 /* VEX_LEN_0FXOP_08_EE */
9891 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9894 /* VEX_LEN_0FXOP_08_EF */
9896 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9899 /* VEX_LEN_0FXOP_09_80 */
9901 { "vfrczps", { XM
, EXxmm
}, 0 },
9902 { "vfrczps", { XM
, EXymmq
}, 0 },
9905 /* VEX_LEN_0FXOP_09_81 */
9907 { "vfrczpd", { XM
, EXxmm
}, 0 },
9908 { "vfrczpd", { XM
, EXymmq
}, 0 },
9912 #include "i386-dis-evex-len.h"
9914 static const struct dis386 vex_w_table
[][2] = {
9916 /* VEX_W_0F41_P_0_LEN_1 */
9917 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9918 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9921 /* VEX_W_0F41_P_2_LEN_1 */
9922 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9923 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9926 /* VEX_W_0F42_P_0_LEN_1 */
9927 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9928 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9931 /* VEX_W_0F42_P_2_LEN_1 */
9932 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9933 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9936 /* VEX_W_0F44_P_0_LEN_0 */
9937 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9938 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9941 /* VEX_W_0F44_P_2_LEN_0 */
9942 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9943 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9946 /* VEX_W_0F45_P_0_LEN_1 */
9947 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9948 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9951 /* VEX_W_0F45_P_2_LEN_1 */
9952 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9953 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9956 /* VEX_W_0F46_P_0_LEN_1 */
9957 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9958 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9961 /* VEX_W_0F46_P_2_LEN_1 */
9962 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9963 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9966 /* VEX_W_0F47_P_0_LEN_1 */
9967 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9968 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9971 /* VEX_W_0F47_P_2_LEN_1 */
9972 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9973 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9976 /* VEX_W_0F4A_P_0_LEN_1 */
9977 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9978 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9981 /* VEX_W_0F4A_P_2_LEN_1 */
9982 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9983 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9986 /* VEX_W_0F4B_P_0_LEN_1 */
9987 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9988 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9991 /* VEX_W_0F4B_P_2_LEN_1 */
9992 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9995 /* VEX_W_0F90_P_0_LEN_0 */
9996 { "kmovw", { MaskG
, MaskE
}, 0 },
9997 { "kmovq", { MaskG
, MaskE
}, 0 },
10000 /* VEX_W_0F90_P_2_LEN_0 */
10001 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10002 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10005 /* VEX_W_0F91_P_0_LEN_0 */
10006 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10007 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10010 /* VEX_W_0F91_P_2_LEN_0 */
10011 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10012 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10015 /* VEX_W_0F92_P_0_LEN_0 */
10016 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10019 /* VEX_W_0F92_P_2_LEN_0 */
10020 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10023 /* VEX_W_0F93_P_0_LEN_0 */
10024 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10027 /* VEX_W_0F93_P_2_LEN_0 */
10028 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10031 /* VEX_W_0F98_P_0_LEN_0 */
10032 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10033 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10036 /* VEX_W_0F98_P_2_LEN_0 */
10037 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10038 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10041 /* VEX_W_0F99_P_0_LEN_0 */
10042 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10043 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10046 /* VEX_W_0F99_P_2_LEN_0 */
10047 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10048 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10051 /* VEX_W_0F380C_P_2 */
10052 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10055 /* VEX_W_0F380D_P_2 */
10056 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10059 /* VEX_W_0F380E_P_2 */
10060 { "vtestps", { XM
, EXx
}, 0 },
10063 /* VEX_W_0F380F_P_2 */
10064 { "vtestpd", { XM
, EXx
}, 0 },
10067 /* VEX_W_0F3816_P_2 */
10068 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10071 /* VEX_W_0F3818_P_2 */
10072 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10075 /* VEX_W_0F3819_P_2 */
10076 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10079 /* VEX_W_0F381A_P_2_M_0 */
10080 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10083 /* VEX_W_0F382C_P_2_M_0 */
10084 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10087 /* VEX_W_0F382D_P_2_M_0 */
10088 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10091 /* VEX_W_0F382E_P_2_M_0 */
10092 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10095 /* VEX_W_0F382F_P_2_M_0 */
10096 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10099 /* VEX_W_0F3836_P_2 */
10100 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10103 /* VEX_W_0F3846_P_2 */
10104 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10107 /* VEX_W_0F3858_P_2 */
10108 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10111 /* VEX_W_0F3859_P_2 */
10112 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10115 /* VEX_W_0F385A_P_2_M_0 */
10116 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10119 /* VEX_W_0F3878_P_2 */
10120 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10123 /* VEX_W_0F3879_P_2 */
10124 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10127 /* VEX_W_0F38CF_P_2 */
10128 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10131 /* VEX_W_0F3A00_P_2 */
10133 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10136 /* VEX_W_0F3A01_P_2 */
10138 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10141 /* VEX_W_0F3A02_P_2 */
10142 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10145 /* VEX_W_0F3A04_P_2 */
10146 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10149 /* VEX_W_0F3A05_P_2 */
10150 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10153 /* VEX_W_0F3A06_P_2 */
10154 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10157 /* VEX_W_0F3A18_P_2 */
10158 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10161 /* VEX_W_0F3A19_P_2 */
10162 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10165 /* VEX_W_0F3A30_P_2_LEN_0 */
10166 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10167 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10170 /* VEX_W_0F3A31_P_2_LEN_0 */
10171 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10172 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10175 /* VEX_W_0F3A32_P_2_LEN_0 */
10176 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10177 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10180 /* VEX_W_0F3A33_P_2_LEN_0 */
10181 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10182 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10185 /* VEX_W_0F3A38_P_2 */
10186 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10189 /* VEX_W_0F3A39_P_2 */
10190 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10193 /* VEX_W_0F3A46_P_2 */
10194 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10197 /* VEX_W_0F3A48_P_2 */
10198 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10199 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10202 /* VEX_W_0F3A49_P_2 */
10203 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10204 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10207 /* VEX_W_0F3A4A_P_2 */
10208 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10211 /* VEX_W_0F3A4B_P_2 */
10212 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10215 /* VEX_W_0F3A4C_P_2 */
10216 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10219 /* VEX_W_0F3ACE_P_2 */
10221 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10224 /* VEX_W_0F3ACF_P_2 */
10226 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10229 #include "i386-dis-evex-w.h"
10232 static const struct dis386 mod_table
[][2] = {
10235 { "leaS", { Gv
, M
}, 0 },
10240 { RM_TABLE (RM_C6_REG_7
) },
10245 { RM_TABLE (RM_C7_REG_7
) },
10249 { "Jcall^", { indirEp
}, 0 },
10253 { "Jjmp^", { indirEp
}, 0 },
10256 /* MOD_0F01_REG_0 */
10257 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10258 { RM_TABLE (RM_0F01_REG_0
) },
10261 /* MOD_0F01_REG_1 */
10262 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10263 { RM_TABLE (RM_0F01_REG_1
) },
10266 /* MOD_0F01_REG_2 */
10267 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10268 { RM_TABLE (RM_0F01_REG_2
) },
10271 /* MOD_0F01_REG_3 */
10272 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10273 { RM_TABLE (RM_0F01_REG_3
) },
10276 /* MOD_0F01_REG_5 */
10277 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10278 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10281 /* MOD_0F01_REG_7 */
10282 { "invlpg", { Mb
}, 0 },
10283 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10286 /* MOD_0F12_PREFIX_0 */
10287 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10288 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10292 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10295 /* MOD_0F16_PREFIX_0 */
10296 { "movhps", { XM
, EXq
}, 0 },
10297 { "movlhps", { XM
, EXq
}, 0 },
10301 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10304 /* MOD_0F18_REG_0 */
10305 { "prefetchnta", { Mb
}, 0 },
10308 /* MOD_0F18_REG_1 */
10309 { "prefetcht0", { Mb
}, 0 },
10312 /* MOD_0F18_REG_2 */
10313 { "prefetcht1", { Mb
}, 0 },
10316 /* MOD_0F18_REG_3 */
10317 { "prefetcht2", { Mb
}, 0 },
10320 /* MOD_0F18_REG_4 */
10321 { "nop/reserved", { Mb
}, 0 },
10324 /* MOD_0F18_REG_5 */
10325 { "nop/reserved", { Mb
}, 0 },
10328 /* MOD_0F18_REG_6 */
10329 { "nop/reserved", { Mb
}, 0 },
10332 /* MOD_0F18_REG_7 */
10333 { "nop/reserved", { Mb
}, 0 },
10336 /* MOD_0F1A_PREFIX_0 */
10337 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10338 { "nopQ", { Ev
}, 0 },
10341 /* MOD_0F1B_PREFIX_0 */
10342 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10343 { "nopQ", { Ev
}, 0 },
10346 /* MOD_0F1B_PREFIX_1 */
10347 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10348 { "nopQ", { Ev
}, 0 },
10351 /* MOD_0F1C_PREFIX_0 */
10352 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10353 { "nopQ", { Ev
}, 0 },
10356 /* MOD_0F1E_PREFIX_1 */
10357 { "nopQ", { Ev
}, 0 },
10358 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10363 { "movL", { Rd
, Td
}, 0 },
10368 { "movL", { Td
, Rd
}, 0 },
10371 /* MOD_0F2B_PREFIX_0 */
10372 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10375 /* MOD_0F2B_PREFIX_1 */
10376 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10379 /* MOD_0F2B_PREFIX_2 */
10380 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10383 /* MOD_0F2B_PREFIX_3 */
10384 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10389 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10392 /* MOD_0F71_REG_2 */
10394 { "psrlw", { MS
, Ib
}, 0 },
10397 /* MOD_0F71_REG_4 */
10399 { "psraw", { MS
, Ib
}, 0 },
10402 /* MOD_0F71_REG_6 */
10404 { "psllw", { MS
, Ib
}, 0 },
10407 /* MOD_0F72_REG_2 */
10409 { "psrld", { MS
, Ib
}, 0 },
10412 /* MOD_0F72_REG_4 */
10414 { "psrad", { MS
, Ib
}, 0 },
10417 /* MOD_0F72_REG_6 */
10419 { "pslld", { MS
, Ib
}, 0 },
10422 /* MOD_0F73_REG_2 */
10424 { "psrlq", { MS
, Ib
}, 0 },
10427 /* MOD_0F73_REG_3 */
10429 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10432 /* MOD_0F73_REG_6 */
10434 { "psllq", { MS
, Ib
}, 0 },
10437 /* MOD_0F73_REG_7 */
10439 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10442 /* MOD_0FAE_REG_0 */
10443 { "fxsave", { FXSAVE
}, 0 },
10444 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10447 /* MOD_0FAE_REG_1 */
10448 { "fxrstor", { FXSAVE
}, 0 },
10449 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10452 /* MOD_0FAE_REG_2 */
10453 { "ldmxcsr", { Md
}, 0 },
10454 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10457 /* MOD_0FAE_REG_3 */
10458 { "stmxcsr", { Md
}, 0 },
10459 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10462 /* MOD_0FAE_REG_4 */
10463 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10464 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10467 /* MOD_0FAE_REG_5 */
10468 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10469 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10472 /* MOD_0FAE_REG_6 */
10473 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10474 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10477 /* MOD_0FAE_REG_7 */
10478 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10479 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10483 { "lssS", { Gv
, Mp
}, 0 },
10487 { "lfsS", { Gv
, Mp
}, 0 },
10491 { "lgsS", { Gv
, Mp
}, 0 },
10495 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10498 /* MOD_0FC7_REG_3 */
10499 { "xrstors", { FXSAVE
}, 0 },
10502 /* MOD_0FC7_REG_4 */
10503 { "xsavec", { FXSAVE
}, 0 },
10506 /* MOD_0FC7_REG_5 */
10507 { "xsaves", { FXSAVE
}, 0 },
10510 /* MOD_0FC7_REG_6 */
10511 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10512 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10515 /* MOD_0FC7_REG_7 */
10516 { "vmptrst", { Mq
}, 0 },
10517 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10522 { "pmovmskb", { Gdq
, MS
}, 0 },
10525 /* MOD_0FE7_PREFIX_2 */
10526 { "movntdq", { Mx
, XM
}, 0 },
10529 /* MOD_0FF0_PREFIX_3 */
10530 { "lddqu", { XM
, M
}, 0 },
10533 /* MOD_0F382A_PREFIX_2 */
10534 { "movntdqa", { XM
, Mx
}, 0 },
10537 /* MOD_0F38F5_PREFIX_2 */
10538 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10541 /* MOD_0F38F6_PREFIX_0 */
10542 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10545 /* MOD_0F38F8_PREFIX_1 */
10546 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10549 /* MOD_0F38F8_PREFIX_2 */
10550 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10553 /* MOD_0F38F8_PREFIX_3 */
10554 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10557 /* MOD_0F38F9_PREFIX_0 */
10558 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
10562 { "bound{S|}", { Gv
, Ma
}, 0 },
10563 { EVEX_TABLE (EVEX_0F
) },
10567 { "lesS", { Gv
, Mp
}, 0 },
10568 { VEX_C4_TABLE (VEX_0F
) },
10572 { "ldsS", { Gv
, Mp
}, 0 },
10573 { VEX_C5_TABLE (VEX_0F
) },
10576 /* MOD_VEX_0F12_PREFIX_0 */
10577 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10578 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10582 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10585 /* MOD_VEX_0F16_PREFIX_0 */
10586 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10587 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10591 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10595 { "vmovntpX", { Mx
, XM
}, 0 },
10598 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10600 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10603 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10605 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10608 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10610 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10613 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10615 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10618 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10620 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10623 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10625 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10628 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10630 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10633 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10635 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10638 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10640 { "knotw", { MaskG
, MaskR
}, 0 },
10643 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10645 { "knotq", { MaskG
, MaskR
}, 0 },
10648 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10650 { "knotb", { MaskG
, MaskR
}, 0 },
10653 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10655 { "knotd", { MaskG
, MaskR
}, 0 },
10658 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10660 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10663 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10665 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10668 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10670 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10673 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10675 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10678 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10680 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10683 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10685 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10688 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10690 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10693 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10695 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10698 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10700 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10703 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10705 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10708 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10710 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10713 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10715 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10718 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10720 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10723 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10725 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10728 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10730 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10733 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10735 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10738 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10740 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10743 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10745 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10748 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10750 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10755 { "vmovmskpX", { Gdq
, XS
}, 0 },
10758 /* MOD_VEX_0F71_REG_2 */
10760 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10763 /* MOD_VEX_0F71_REG_4 */
10765 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10768 /* MOD_VEX_0F71_REG_6 */
10770 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10773 /* MOD_VEX_0F72_REG_2 */
10775 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10778 /* MOD_VEX_0F72_REG_4 */
10780 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10783 /* MOD_VEX_0F72_REG_6 */
10785 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10788 /* MOD_VEX_0F73_REG_2 */
10790 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10793 /* MOD_VEX_0F73_REG_3 */
10795 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10798 /* MOD_VEX_0F73_REG_6 */
10800 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10803 /* MOD_VEX_0F73_REG_7 */
10805 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10808 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10809 { "kmovw", { Ew
, MaskG
}, 0 },
10813 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10814 { "kmovq", { Eq
, MaskG
}, 0 },
10818 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10819 { "kmovb", { Eb
, MaskG
}, 0 },
10823 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10824 { "kmovd", { Ed
, MaskG
}, 0 },
10828 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10830 { "kmovw", { MaskG
, Rdq
}, 0 },
10833 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10835 { "kmovb", { MaskG
, Rdq
}, 0 },
10838 /* MOD_VEX_0F92_P_3_LEN_0 */
10840 { "kmovK", { MaskG
, Rdq
}, 0 },
10843 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10845 { "kmovw", { Gdq
, MaskR
}, 0 },
10848 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10850 { "kmovb", { Gdq
, MaskR
}, 0 },
10853 /* MOD_VEX_0F93_P_3_LEN_0 */
10855 { "kmovK", { Gdq
, MaskR
}, 0 },
10858 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10860 { "kortestw", { MaskG
, MaskR
}, 0 },
10863 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10865 { "kortestq", { MaskG
, MaskR
}, 0 },
10868 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10870 { "kortestb", { MaskG
, MaskR
}, 0 },
10873 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10875 { "kortestd", { MaskG
, MaskR
}, 0 },
10878 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10880 { "ktestw", { MaskG
, MaskR
}, 0 },
10883 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10885 { "ktestq", { MaskG
, MaskR
}, 0 },
10888 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10890 { "ktestb", { MaskG
, MaskR
}, 0 },
10893 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10895 { "ktestd", { MaskG
, MaskR
}, 0 },
10898 /* MOD_VEX_0FAE_REG_2 */
10899 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10902 /* MOD_VEX_0FAE_REG_3 */
10903 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10906 /* MOD_VEX_0FD7_PREFIX_2 */
10908 { "vpmovmskb", { Gdq
, XS
}, 0 },
10911 /* MOD_VEX_0FE7_PREFIX_2 */
10912 { "vmovntdq", { Mx
, XM
}, 0 },
10915 /* MOD_VEX_0FF0_PREFIX_3 */
10916 { "vlddqu", { XM
, M
}, 0 },
10919 /* MOD_VEX_0F381A_PREFIX_2 */
10920 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10923 /* MOD_VEX_0F382A_PREFIX_2 */
10924 { "vmovntdqa", { XM
, Mx
}, 0 },
10927 /* MOD_VEX_0F382C_PREFIX_2 */
10928 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10931 /* MOD_VEX_0F382D_PREFIX_2 */
10932 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10935 /* MOD_VEX_0F382E_PREFIX_2 */
10936 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10939 /* MOD_VEX_0F382F_PREFIX_2 */
10940 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10943 /* MOD_VEX_0F385A_PREFIX_2 */
10944 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10947 /* MOD_VEX_0F388C_PREFIX_2 */
10948 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10951 /* MOD_VEX_0F388E_PREFIX_2 */
10952 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10955 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10957 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10960 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10962 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10965 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10967 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10970 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10972 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10975 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10977 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10980 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10982 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10985 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10987 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10990 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10992 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10995 #include "i386-dis-evex-mod.h"
10998 static const struct dis386 rm_table
[][8] = {
11001 { "xabort", { Skip_MODRM
, Ib
}, 0 },
11005 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
11008 /* RM_0F01_REG_0 */
11009 { "enclv", { Skip_MODRM
}, 0 },
11010 { "vmcall", { Skip_MODRM
}, 0 },
11011 { "vmlaunch", { Skip_MODRM
}, 0 },
11012 { "vmresume", { Skip_MODRM
}, 0 },
11013 { "vmxoff", { Skip_MODRM
}, 0 },
11014 { "pconfig", { Skip_MODRM
}, 0 },
11017 /* RM_0F01_REG_1 */
11018 { "monitor", { { OP_Monitor
, 0 } }, 0 },
11019 { "mwait", { { OP_Mwait
, 0 } }, 0 },
11020 { "clac", { Skip_MODRM
}, 0 },
11021 { "stac", { Skip_MODRM
}, 0 },
11025 { "encls", { Skip_MODRM
}, 0 },
11028 /* RM_0F01_REG_2 */
11029 { "xgetbv", { Skip_MODRM
}, 0 },
11030 { "xsetbv", { Skip_MODRM
}, 0 },
11033 { "vmfunc", { Skip_MODRM
}, 0 },
11034 { "xend", { Skip_MODRM
}, 0 },
11035 { "xtest", { Skip_MODRM
}, 0 },
11036 { "enclu", { Skip_MODRM
}, 0 },
11039 /* RM_0F01_REG_3 */
11040 { "vmrun", { Skip_MODRM
}, 0 },
11041 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
11042 { "vmload", { Skip_MODRM
}, 0 },
11043 { "vmsave", { Skip_MODRM
}, 0 },
11044 { "stgi", { Skip_MODRM
}, 0 },
11045 { "clgi", { Skip_MODRM
}, 0 },
11046 { "skinit", { Skip_MODRM
}, 0 },
11047 { "invlpga", { Skip_MODRM
}, 0 },
11050 /* RM_0F01_REG_5_MOD_3 */
11051 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
11052 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
11053 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
11057 { "rdpkru", { Skip_MODRM
}, 0 },
11058 { "wrpkru", { Skip_MODRM
}, 0 },
11061 /* RM_0F01_REG_7_MOD_3 */
11062 { "swapgs", { Skip_MODRM
}, 0 },
11063 { "rdtscp", { Skip_MODRM
}, 0 },
11064 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
11065 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
11066 { "clzero", { Skip_MODRM
}, 0 },
11067 { "rdpru", { Skip_MODRM
}, 0 },
11070 /* RM_0F1E_P_1_MOD_3_REG_7 */
11071 { "nopQ", { Ev
}, 0 },
11072 { "nopQ", { Ev
}, 0 },
11073 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11074 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11075 { "nopQ", { Ev
}, 0 },
11076 { "nopQ", { Ev
}, 0 },
11077 { "nopQ", { Ev
}, 0 },
11078 { "nopQ", { Ev
}, 0 },
11081 /* RM_0FAE_REG_6_MOD_3 */
11082 { "mfence", { Skip_MODRM
}, 0 },
11085 /* RM_0FAE_REG_7_MOD_3 */
11086 { "sfence", { Skip_MODRM
}, 0 },
11091 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11093 /* We use the high bit to indicate different name for the same
11095 #define REP_PREFIX (0xf3 | 0x100)
11096 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11097 #define XRELEASE_PREFIX (0xf3 | 0x400)
11098 #define BND_PREFIX (0xf2 | 0x400)
11099 #define NOTRACK_PREFIX (0x3e | 0x100)
11101 /* Remember if the current op is a jump instruction. */
11102 static bfd_boolean op_is_jump
= FALSE
;
11107 int newrex
, i
, length
;
11113 last_lock_prefix
= -1;
11114 last_repz_prefix
= -1;
11115 last_repnz_prefix
= -1;
11116 last_data_prefix
= -1;
11117 last_addr_prefix
= -1;
11118 last_rex_prefix
= -1;
11119 last_seg_prefix
= -1;
11121 active_seg_prefix
= 0;
11122 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11123 all_prefixes
[i
] = 0;
11126 /* The maximum instruction length is 15bytes. */
11127 while (length
< MAX_CODE_LENGTH
- 1)
11129 FETCH_DATA (the_info
, codep
+ 1);
11133 /* REX prefixes family. */
11150 if (address_mode
== mode_64bit
)
11154 last_rex_prefix
= i
;
11157 prefixes
|= PREFIX_REPZ
;
11158 last_repz_prefix
= i
;
11161 prefixes
|= PREFIX_REPNZ
;
11162 last_repnz_prefix
= i
;
11165 prefixes
|= PREFIX_LOCK
;
11166 last_lock_prefix
= i
;
11169 prefixes
|= PREFIX_CS
;
11170 last_seg_prefix
= i
;
11171 active_seg_prefix
= PREFIX_CS
;
11174 prefixes
|= PREFIX_SS
;
11175 last_seg_prefix
= i
;
11176 active_seg_prefix
= PREFIX_SS
;
11179 prefixes
|= PREFIX_DS
;
11180 last_seg_prefix
= i
;
11181 active_seg_prefix
= PREFIX_DS
;
11184 prefixes
|= PREFIX_ES
;
11185 last_seg_prefix
= i
;
11186 active_seg_prefix
= PREFIX_ES
;
11189 prefixes
|= PREFIX_FS
;
11190 last_seg_prefix
= i
;
11191 active_seg_prefix
= PREFIX_FS
;
11194 prefixes
|= PREFIX_GS
;
11195 last_seg_prefix
= i
;
11196 active_seg_prefix
= PREFIX_GS
;
11199 prefixes
|= PREFIX_DATA
;
11200 last_data_prefix
= i
;
11203 prefixes
|= PREFIX_ADDR
;
11204 last_addr_prefix
= i
;
11207 /* fwait is really an instruction. If there are prefixes
11208 before the fwait, they belong to the fwait, *not* to the
11209 following instruction. */
11211 if (prefixes
|| rex
)
11213 prefixes
|= PREFIX_FWAIT
;
11215 /* This ensures that the previous REX prefixes are noticed
11216 as unused prefixes, as in the return case below. */
11220 prefixes
= PREFIX_FWAIT
;
11225 /* Rex is ignored when followed by another prefix. */
11231 if (*codep
!= FWAIT_OPCODE
)
11232 all_prefixes
[i
++] = *codep
;
11240 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11243 static const char *
11244 prefix_name (int pref
, int sizeflag
)
11246 static const char *rexes
[16] =
11249 "rex.B", /* 0x41 */
11250 "rex.X", /* 0x42 */
11251 "rex.XB", /* 0x43 */
11252 "rex.R", /* 0x44 */
11253 "rex.RB", /* 0x45 */
11254 "rex.RX", /* 0x46 */
11255 "rex.RXB", /* 0x47 */
11256 "rex.W", /* 0x48 */
11257 "rex.WB", /* 0x49 */
11258 "rex.WX", /* 0x4a */
11259 "rex.WXB", /* 0x4b */
11260 "rex.WR", /* 0x4c */
11261 "rex.WRB", /* 0x4d */
11262 "rex.WRX", /* 0x4e */
11263 "rex.WRXB", /* 0x4f */
11268 /* REX prefixes family. */
11285 return rexes
[pref
- 0x40];
11305 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11307 if (address_mode
== mode_64bit
)
11308 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11310 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11315 case XACQUIRE_PREFIX
:
11317 case XRELEASE_PREFIX
:
11321 case NOTRACK_PREFIX
:
11328 static char op_out
[MAX_OPERANDS
][100];
11329 static int op_ad
, op_index
[MAX_OPERANDS
];
11330 static int two_source_ops
;
11331 static bfd_vma op_address
[MAX_OPERANDS
];
11332 static bfd_vma op_riprel
[MAX_OPERANDS
];
11333 static bfd_vma start_pc
;
11336 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11337 * (see topic "Redundant prefixes" in the "Differences from 8086"
11338 * section of the "Virtual 8086 Mode" chapter.)
11339 * 'pc' should be the address of this instruction, it will
11340 * be used to print the target address if this is a relative jump or call
11341 * The function returns the length of this instruction in bytes.
11344 static char intel_syntax
;
11345 static char intel_mnemonic
= !SYSV386_COMPAT
;
11346 static char open_char
;
11347 static char close_char
;
11348 static char separator_char
;
11349 static char scale_char
;
11357 static enum x86_64_isa isa64
;
11359 /* Here for backwards compatibility. When gdb stops using
11360 print_insn_i386_att and print_insn_i386_intel these functions can
11361 disappear, and print_insn_i386 be merged into print_insn. */
11363 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11367 return print_insn (pc
, info
);
11371 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11375 return print_insn (pc
, info
);
11379 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11383 return print_insn (pc
, info
);
11387 print_i386_disassembler_options (FILE *stream
)
11389 fprintf (stream
, _("\n\
11390 The following i386/x86-64 specific disassembler options are supported for use\n\
11391 with the -M switch (multiple options should be separated by commas):\n"));
11393 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11394 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11395 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11396 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11397 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11398 fprintf (stream
, _(" att-mnemonic\n"
11399 " Display instruction in AT&T mnemonic\n"));
11400 fprintf (stream
, _(" intel-mnemonic\n"
11401 " Display instruction in Intel mnemonic\n"));
11402 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11403 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11404 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11405 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11406 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11407 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11408 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11409 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11413 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11415 /* Get a pointer to struct dis386 with a valid name. */
11417 static const struct dis386
*
11418 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11420 int vindex
, vex_table_index
;
11422 if (dp
->name
!= NULL
)
11425 switch (dp
->op
[0].bytemode
)
11427 case USE_REG_TABLE
:
11428 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11431 case USE_MOD_TABLE
:
11432 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11433 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11437 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11440 case USE_PREFIX_TABLE
:
11443 /* The prefix in VEX is implicit. */
11444 switch (vex
.prefix
)
11449 case REPE_PREFIX_OPCODE
:
11452 case DATA_PREFIX_OPCODE
:
11455 case REPNE_PREFIX_OPCODE
:
11465 int last_prefix
= -1;
11468 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11469 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11471 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11473 if (last_repz_prefix
> last_repnz_prefix
)
11476 prefix
= PREFIX_REPZ
;
11477 last_prefix
= last_repz_prefix
;
11482 prefix
= PREFIX_REPNZ
;
11483 last_prefix
= last_repnz_prefix
;
11486 /* Check if prefix should be ignored. */
11487 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11488 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11493 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11496 prefix
= PREFIX_DATA
;
11497 last_prefix
= last_data_prefix
;
11502 used_prefixes
|= prefix
;
11503 all_prefixes
[last_prefix
] = 0;
11506 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11509 case USE_X86_64_TABLE
:
11510 vindex
= address_mode
== mode_64bit
? 1 : 0;
11511 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11514 case USE_3BYTE_TABLE
:
11515 FETCH_DATA (info
, codep
+ 2);
11517 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11519 modrm
.mod
= (*codep
>> 6) & 3;
11520 modrm
.reg
= (*codep
>> 3) & 7;
11521 modrm
.rm
= *codep
& 7;
11524 case USE_VEX_LEN_TABLE
:
11528 switch (vex
.length
)
11541 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11544 case USE_EVEX_LEN_TABLE
:
11548 switch (vex
.length
)
11564 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11567 case USE_XOP_8F_TABLE
:
11568 FETCH_DATA (info
, codep
+ 3);
11569 /* All bits in the REX prefix are ignored. */
11571 rex
= ~(*codep
>> 5) & 0x7;
11573 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11574 switch ((*codep
& 0x1f))
11580 vex_table_index
= XOP_08
;
11583 vex_table_index
= XOP_09
;
11586 vex_table_index
= XOP_0A
;
11590 vex
.w
= *codep
& 0x80;
11591 if (vex
.w
&& address_mode
== mode_64bit
)
11594 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11595 if (address_mode
!= mode_64bit
)
11597 /* In 16/32-bit mode REX_B is silently ignored. */
11601 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11602 switch ((*codep
& 0x3))
11607 vex
.prefix
= DATA_PREFIX_OPCODE
;
11610 vex
.prefix
= REPE_PREFIX_OPCODE
;
11613 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11620 dp
= &xop_table
[vex_table_index
][vindex
];
11623 FETCH_DATA (info
, codep
+ 1);
11624 modrm
.mod
= (*codep
>> 6) & 3;
11625 modrm
.reg
= (*codep
>> 3) & 7;
11626 modrm
.rm
= *codep
& 7;
11629 case USE_VEX_C4_TABLE
:
11631 FETCH_DATA (info
, codep
+ 3);
11632 /* All bits in the REX prefix are ignored. */
11634 rex
= ~(*codep
>> 5) & 0x7;
11635 switch ((*codep
& 0x1f))
11641 vex_table_index
= VEX_0F
;
11644 vex_table_index
= VEX_0F38
;
11647 vex_table_index
= VEX_0F3A
;
11651 vex
.w
= *codep
& 0x80;
11652 if (address_mode
== mode_64bit
)
11659 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11660 is ignored, other REX bits are 0 and the highest bit in
11661 VEX.vvvv is also ignored (but we mustn't clear it here). */
11664 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11665 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11666 switch ((*codep
& 0x3))
11671 vex
.prefix
= DATA_PREFIX_OPCODE
;
11674 vex
.prefix
= REPE_PREFIX_OPCODE
;
11677 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11684 dp
= &vex_table
[vex_table_index
][vindex
];
11686 /* There is no MODRM byte for VEX0F 77. */
11687 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11689 FETCH_DATA (info
, codep
+ 1);
11690 modrm
.mod
= (*codep
>> 6) & 3;
11691 modrm
.reg
= (*codep
>> 3) & 7;
11692 modrm
.rm
= *codep
& 7;
11696 case USE_VEX_C5_TABLE
:
11698 FETCH_DATA (info
, codep
+ 2);
11699 /* All bits in the REX prefix are ignored. */
11701 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11703 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11705 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11706 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11707 switch ((*codep
& 0x3))
11712 vex
.prefix
= DATA_PREFIX_OPCODE
;
11715 vex
.prefix
= REPE_PREFIX_OPCODE
;
11718 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11725 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11727 /* There is no MODRM byte for VEX 77. */
11728 if (vindex
!= 0x77)
11730 FETCH_DATA (info
, codep
+ 1);
11731 modrm
.mod
= (*codep
>> 6) & 3;
11732 modrm
.reg
= (*codep
>> 3) & 7;
11733 modrm
.rm
= *codep
& 7;
11737 case USE_VEX_W_TABLE
:
11741 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11744 case USE_EVEX_TABLE
:
11745 two_source_ops
= 0;
11748 FETCH_DATA (info
, codep
+ 4);
11749 /* All bits in the REX prefix are ignored. */
11751 /* The first byte after 0x62. */
11752 rex
= ~(*codep
>> 5) & 0x7;
11753 vex
.r
= *codep
& 0x10;
11754 switch ((*codep
& 0xf))
11757 return &bad_opcode
;
11759 vex_table_index
= EVEX_0F
;
11762 vex_table_index
= EVEX_0F38
;
11765 vex_table_index
= EVEX_0F3A
;
11769 /* The second byte after 0x62. */
11771 vex
.w
= *codep
& 0x80;
11772 if (vex
.w
&& address_mode
== mode_64bit
)
11775 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11778 if (!(*codep
& 0x4))
11779 return &bad_opcode
;
11781 switch ((*codep
& 0x3))
11786 vex
.prefix
= DATA_PREFIX_OPCODE
;
11789 vex
.prefix
= REPE_PREFIX_OPCODE
;
11792 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11796 /* The third byte after 0x62. */
11799 /* Remember the static rounding bits. */
11800 vex
.ll
= (*codep
>> 5) & 3;
11801 vex
.b
= (*codep
& 0x10) != 0;
11803 vex
.v
= *codep
& 0x8;
11804 vex
.mask_register_specifier
= *codep
& 0x7;
11805 vex
.zeroing
= *codep
& 0x80;
11807 if (address_mode
!= mode_64bit
)
11809 /* In 16/32-bit mode silently ignore following bits. */
11819 dp
= &evex_table
[vex_table_index
][vindex
];
11821 FETCH_DATA (info
, codep
+ 1);
11822 modrm
.mod
= (*codep
>> 6) & 3;
11823 modrm
.reg
= (*codep
>> 3) & 7;
11824 modrm
.rm
= *codep
& 7;
11826 /* Set vector length. */
11827 if (modrm
.mod
== 3 && vex
.b
)
11843 return &bad_opcode
;
11856 if (dp
->name
!= NULL
)
11859 return get_valid_dis386 (dp
, info
);
11863 get_sib (disassemble_info
*info
, int sizeflag
)
11865 /* If modrm.mod == 3, operand must be register. */
11867 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11871 FETCH_DATA (info
, codep
+ 2);
11872 sib
.index
= (codep
[1] >> 3) & 7;
11873 sib
.scale
= (codep
[1] >> 6) & 3;
11874 sib
.base
= codep
[1] & 7;
11879 print_insn (bfd_vma pc
, disassemble_info
*info
)
11881 const struct dis386
*dp
;
11883 char *op_txt
[MAX_OPERANDS
];
11885 int sizeflag
, orig_sizeflag
;
11887 struct dis_private priv
;
11890 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11891 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11892 address_mode
= mode_32bit
;
11893 else if (info
->mach
== bfd_mach_i386_i8086
)
11895 address_mode
= mode_16bit
;
11896 priv
.orig_sizeflag
= 0;
11899 address_mode
= mode_64bit
;
11901 if (intel_syntax
== (char) -1)
11902 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11904 for (p
= info
->disassembler_options
; p
!= NULL
; )
11906 if (CONST_STRNEQ (p
, "amd64"))
11908 else if (CONST_STRNEQ (p
, "intel64"))
11910 else if (CONST_STRNEQ (p
, "x86-64"))
11912 address_mode
= mode_64bit
;
11913 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11915 else if (CONST_STRNEQ (p
, "i386"))
11917 address_mode
= mode_32bit
;
11918 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11920 else if (CONST_STRNEQ (p
, "i8086"))
11922 address_mode
= mode_16bit
;
11923 priv
.orig_sizeflag
= 0;
11925 else if (CONST_STRNEQ (p
, "intel"))
11928 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11929 intel_mnemonic
= 1;
11931 else if (CONST_STRNEQ (p
, "att"))
11934 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11935 intel_mnemonic
= 0;
11937 else if (CONST_STRNEQ (p
, "addr"))
11939 if (address_mode
== mode_64bit
)
11941 if (p
[4] == '3' && p
[5] == '2')
11942 priv
.orig_sizeflag
&= ~AFLAG
;
11943 else if (p
[4] == '6' && p
[5] == '4')
11944 priv
.orig_sizeflag
|= AFLAG
;
11948 if (p
[4] == '1' && p
[5] == '6')
11949 priv
.orig_sizeflag
&= ~AFLAG
;
11950 else if (p
[4] == '3' && p
[5] == '2')
11951 priv
.orig_sizeflag
|= AFLAG
;
11954 else if (CONST_STRNEQ (p
, "data"))
11956 if (p
[4] == '1' && p
[5] == '6')
11957 priv
.orig_sizeflag
&= ~DFLAG
;
11958 else if (p
[4] == '3' && p
[5] == '2')
11959 priv
.orig_sizeflag
|= DFLAG
;
11961 else if (CONST_STRNEQ (p
, "suffix"))
11962 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11964 p
= strchr (p
, ',');
11969 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11971 (*info
->fprintf_func
) (info
->stream
,
11972 _("64-bit address is disabled"));
11978 names64
= intel_names64
;
11979 names32
= intel_names32
;
11980 names16
= intel_names16
;
11981 names8
= intel_names8
;
11982 names8rex
= intel_names8rex
;
11983 names_seg
= intel_names_seg
;
11984 names_mm
= intel_names_mm
;
11985 names_bnd
= intel_names_bnd
;
11986 names_xmm
= intel_names_xmm
;
11987 names_ymm
= intel_names_ymm
;
11988 names_zmm
= intel_names_zmm
;
11989 index64
= intel_index64
;
11990 index32
= intel_index32
;
11991 names_mask
= intel_names_mask
;
11992 index16
= intel_index16
;
11995 separator_char
= '+';
12000 names64
= att_names64
;
12001 names32
= att_names32
;
12002 names16
= att_names16
;
12003 names8
= att_names8
;
12004 names8rex
= att_names8rex
;
12005 names_seg
= att_names_seg
;
12006 names_mm
= att_names_mm
;
12007 names_bnd
= att_names_bnd
;
12008 names_xmm
= att_names_xmm
;
12009 names_ymm
= att_names_ymm
;
12010 names_zmm
= att_names_zmm
;
12011 index64
= att_index64
;
12012 index32
= att_index32
;
12013 names_mask
= att_names_mask
;
12014 index16
= att_index16
;
12017 separator_char
= ',';
12021 /* The output looks better if we put 7 bytes on a line, since that
12022 puts most long word instructions on a single line. Use 8 bytes
12024 if ((info
->mach
& bfd_mach_l1om
) != 0)
12025 info
->bytes_per_line
= 8;
12027 info
->bytes_per_line
= 7;
12029 info
->private_data
= &priv
;
12030 priv
.max_fetched
= priv
.the_buffer
;
12031 priv
.insn_start
= pc
;
12034 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12042 start_codep
= priv
.the_buffer
;
12043 codep
= priv
.the_buffer
;
12045 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12049 /* Getting here means we tried for data but didn't get it. That
12050 means we have an incomplete instruction of some sort. Just
12051 print the first byte as a prefix or a .byte pseudo-op. */
12052 if (codep
> priv
.the_buffer
)
12054 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12056 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12059 /* Just print the first byte as a .byte instruction. */
12060 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12061 (unsigned int) priv
.the_buffer
[0]);
12071 sizeflag
= priv
.orig_sizeflag
;
12073 if (!ckprefix () || rex_used
)
12075 /* Too many prefixes or unused REX prefixes. */
12077 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12079 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12081 prefix_name (all_prefixes
[i
], sizeflag
));
12085 insn_codep
= codep
;
12087 FETCH_DATA (info
, codep
+ 1);
12088 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12090 if (((prefixes
& PREFIX_FWAIT
)
12091 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12093 /* Handle prefixes before fwait. */
12094 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12096 (*info
->fprintf_func
) (info
->stream
, "%s ",
12097 prefix_name (all_prefixes
[i
], sizeflag
));
12098 (*info
->fprintf_func
) (info
->stream
, "fwait");
12102 if (*codep
== 0x0f)
12104 unsigned char threebyte
;
12107 FETCH_DATA (info
, codep
+ 1);
12108 threebyte
= *codep
;
12109 dp
= &dis386_twobyte
[threebyte
];
12110 need_modrm
= twobyte_has_modrm
[*codep
];
12115 dp
= &dis386
[*codep
];
12116 need_modrm
= onebyte_has_modrm
[*codep
];
12120 /* Save sizeflag for printing the extra prefixes later before updating
12121 it for mnemonic and operand processing. The prefix names depend
12122 only on the address mode. */
12123 orig_sizeflag
= sizeflag
;
12124 if (prefixes
& PREFIX_ADDR
)
12126 if ((prefixes
& PREFIX_DATA
))
12132 FETCH_DATA (info
, codep
+ 1);
12133 modrm
.mod
= (*codep
>> 6) & 3;
12134 modrm
.reg
= (*codep
>> 3) & 7;
12135 modrm
.rm
= *codep
& 7;
12141 memset (&vex
, 0, sizeof (vex
));
12143 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12145 get_sib (info
, sizeflag
);
12146 dofloat (sizeflag
);
12150 dp
= get_valid_dis386 (dp
, info
);
12151 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12153 get_sib (info
, sizeflag
);
12154 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12157 op_ad
= MAX_OPERANDS
- 1 - i
;
12159 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12160 /* For EVEX instruction after the last operand masking
12161 should be printed. */
12162 if (i
== 0 && vex
.evex
)
12164 /* Don't print {%k0}. */
12165 if (vex
.mask_register_specifier
)
12168 oappend (names_mask
[vex
.mask_register_specifier
]);
12178 /* Clear instruction information. */
12181 the_info
->insn_info_valid
= 0;
12182 the_info
->branch_delay_insns
= 0;
12183 the_info
->data_size
= 0;
12184 the_info
->insn_type
= dis_noninsn
;
12185 the_info
->target
= 0;
12186 the_info
->target2
= 0;
12189 /* Reset jump operation indicator. */
12190 op_is_jump
= FALSE
;
12193 int jump_detection
= 0;
12195 /* Extract flags. */
12196 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12198 if ((dp
->op
[i
].rtn
== OP_J
)
12199 || (dp
->op
[i
].rtn
== OP_indirE
))
12200 jump_detection
|= 1;
12201 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12202 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12203 jump_detection
|= 2;
12204 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12205 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12206 jump_detection
|= 4;
12209 /* Determine if this is a jump or branch. */
12210 if ((jump_detection
& 0x3) == 0x3)
12213 if (jump_detection
& 0x4)
12214 the_info
->insn_type
= dis_condbranch
;
12216 the_info
->insn_type
=
12217 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12218 ? dis_jsr
: dis_branch
;
12222 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12223 are all 0s in inverted form. */
12224 if (need_vex
&& vex
.register_specifier
!= 0)
12226 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12227 return end_codep
- priv
.the_buffer
;
12230 /* Check if the REX prefix is used. */
12231 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12232 all_prefixes
[last_rex_prefix
] = 0;
12234 /* Check if the SEG prefix is used. */
12235 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12236 | PREFIX_FS
| PREFIX_GS
)) != 0
12237 && (used_prefixes
& active_seg_prefix
) != 0)
12238 all_prefixes
[last_seg_prefix
] = 0;
12240 /* Check if the ADDR prefix is used. */
12241 if ((prefixes
& PREFIX_ADDR
) != 0
12242 && (used_prefixes
& PREFIX_ADDR
) != 0)
12243 all_prefixes
[last_addr_prefix
] = 0;
12245 /* Check if the DATA prefix is used. */
12246 if ((prefixes
& PREFIX_DATA
) != 0
12247 && (used_prefixes
& PREFIX_DATA
) != 0)
12248 all_prefixes
[last_data_prefix
] = 0;
12250 /* Print the extra prefixes. */
12252 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12253 if (all_prefixes
[i
])
12256 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12259 prefix_length
+= strlen (name
) + 1;
12260 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12263 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12264 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12265 used by putop and MMX/SSE operand and may be overriden by the
12266 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12268 if (dp
->prefix_requirement
== PREFIX_OPCODE
12269 && dp
!= &bad_opcode
12271 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12273 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12275 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12277 && (used_prefixes
& PREFIX_DATA
) == 0))))
12279 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12280 return end_codep
- priv
.the_buffer
;
12283 /* Check maximum code length. */
12284 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12286 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12287 return MAX_CODE_LENGTH
;
12290 obufp
= mnemonicendp
;
12291 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12294 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12296 /* The enter and bound instructions are printed with operands in the same
12297 order as the intel book; everything else is printed in reverse order. */
12298 if (intel_syntax
|| two_source_ops
)
12302 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12303 op_txt
[i
] = op_out
[i
];
12305 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12306 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12308 op_txt
[2] = op_out
[3];
12309 op_txt
[3] = op_out
[2];
12312 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12314 op_ad
= op_index
[i
];
12315 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12316 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12317 riprel
= op_riprel
[i
];
12318 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12319 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12324 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12325 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12329 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12333 (*info
->fprintf_func
) (info
->stream
, ",");
12334 if (op_index
[i
] != -1 && !op_riprel
[i
])
12336 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12338 if (the_info
&& op_is_jump
)
12340 the_info
->insn_info_valid
= 1;
12341 the_info
->branch_delay_insns
= 0;
12342 the_info
->data_size
= 0;
12343 the_info
->target
= target
;
12344 the_info
->target2
= 0;
12346 (*info
->print_address_func
) (target
, info
);
12349 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12353 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12354 if (op_index
[i
] != -1 && op_riprel
[i
])
12356 (*info
->fprintf_func
) (info
->stream
, " # ");
12357 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12358 + op_address
[op_index
[i
]]), info
);
12361 return codep
- priv
.the_buffer
;
12364 static const char *float_mem
[] = {
12439 static const unsigned char float_mem_mode
[] = {
12514 #define ST { OP_ST, 0 }
12515 #define STi { OP_STi, 0 }
12517 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12518 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12519 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12520 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12521 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12522 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12523 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12524 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12525 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12527 static const struct dis386 float_reg
[][8] = {
12530 { "fadd", { ST
, STi
}, 0 },
12531 { "fmul", { ST
, STi
}, 0 },
12532 { "fcom", { STi
}, 0 },
12533 { "fcomp", { STi
}, 0 },
12534 { "fsub", { ST
, STi
}, 0 },
12535 { "fsubr", { ST
, STi
}, 0 },
12536 { "fdiv", { ST
, STi
}, 0 },
12537 { "fdivr", { ST
, STi
}, 0 },
12541 { "fld", { STi
}, 0 },
12542 { "fxch", { STi
}, 0 },
12552 { "fcmovb", { ST
, STi
}, 0 },
12553 { "fcmove", { ST
, STi
}, 0 },
12554 { "fcmovbe",{ ST
, STi
}, 0 },
12555 { "fcmovu", { ST
, STi
}, 0 },
12563 { "fcmovnb",{ ST
, STi
}, 0 },
12564 { "fcmovne",{ ST
, STi
}, 0 },
12565 { "fcmovnbe",{ ST
, STi
}, 0 },
12566 { "fcmovnu",{ ST
, STi
}, 0 },
12568 { "fucomi", { ST
, STi
}, 0 },
12569 { "fcomi", { ST
, STi
}, 0 },
12574 { "fadd", { STi
, ST
}, 0 },
12575 { "fmul", { STi
, ST
}, 0 },
12578 { "fsub{!M|r}", { STi
, ST
}, 0 },
12579 { "fsub{M|}", { STi
, ST
}, 0 },
12580 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12581 { "fdiv{M|}", { STi
, ST
}, 0 },
12585 { "ffree", { STi
}, 0 },
12587 { "fst", { STi
}, 0 },
12588 { "fstp", { STi
}, 0 },
12589 { "fucom", { STi
}, 0 },
12590 { "fucomp", { STi
}, 0 },
12596 { "faddp", { STi
, ST
}, 0 },
12597 { "fmulp", { STi
, ST
}, 0 },
12600 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12601 { "fsub{M|}p", { STi
, ST
}, 0 },
12602 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12603 { "fdiv{M|}p", { STi
, ST
}, 0 },
12607 { "ffreep", { STi
}, 0 },
12612 { "fucomip", { ST
, STi
}, 0 },
12613 { "fcomip", { ST
, STi
}, 0 },
12618 static char *fgrps
[][8] = {
12621 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12626 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12631 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12636 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12641 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12646 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12651 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12656 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12657 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12662 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12667 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12672 swap_operand (void)
12674 mnemonicendp
[0] = '.';
12675 mnemonicendp
[1] = 's';
12680 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12681 int sizeflag ATTRIBUTE_UNUSED
)
12683 /* Skip mod/rm byte. */
12689 dofloat (int sizeflag
)
12691 const struct dis386
*dp
;
12692 unsigned char floatop
;
12694 floatop
= codep
[-1];
12696 if (modrm
.mod
!= 3)
12698 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12700 putop (float_mem
[fp_indx
], sizeflag
);
12703 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12706 /* Skip mod/rm byte. */
12710 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12711 if (dp
->name
== NULL
)
12713 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12715 /* Instruction fnstsw is only one with strange arg. */
12716 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12717 strcpy (op_out
[0], names16
[0]);
12721 putop (dp
->name
, sizeflag
);
12726 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12731 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12735 /* Like oappend (below), but S is a string starting with '%'.
12736 In Intel syntax, the '%' is elided. */
12738 oappend_maybe_intel (const char *s
)
12740 oappend (s
+ intel_syntax
);
12744 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12746 oappend_maybe_intel ("%st");
12750 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12752 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12753 oappend_maybe_intel (scratchbuf
);
12756 /* Capital letters in template are macros. */
12758 putop (const char *in_template
, int sizeflag
)
12763 unsigned int l
= 0, len
= 1;
12766 #define SAVE_LAST(c) \
12767 if (l < len && l < sizeof (last)) \
12772 for (p
= in_template
; *p
; p
++)
12788 while (*++p
!= '|')
12789 if (*p
== '}' || *p
== '\0')
12792 /* Fall through. */
12797 while (*++p
!= '}')
12808 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12812 if (l
== 0 && len
== 1)
12817 if (sizeflag
& SUFFIX_ALWAYS
)
12830 if (address_mode
== mode_64bit
12831 && !(prefixes
& PREFIX_ADDR
))
12842 if (intel_syntax
&& !alt
)
12844 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12846 if (sizeflag
& DFLAG
)
12847 *obufp
++ = intel_syntax
? 'd' : 'l';
12849 *obufp
++ = intel_syntax
? 'w' : 's';
12850 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12854 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12857 if (modrm
.mod
== 3)
12863 if (sizeflag
& DFLAG
)
12864 *obufp
++ = intel_syntax
? 'd' : 'l';
12867 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12873 case 'E': /* For jcxz/jecxz */
12874 if (address_mode
== mode_64bit
)
12876 if (sizeflag
& AFLAG
)
12882 if (sizeflag
& AFLAG
)
12884 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12889 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12891 if (sizeflag
& AFLAG
)
12892 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12894 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12895 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12899 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12901 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12905 if (!(rex
& REX_W
))
12906 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12911 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12912 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12914 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12917 if (prefixes
& PREFIX_DS
)
12936 if (l
!= 0 || len
!= 1)
12938 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12943 if (!need_vex
|| !vex
.evex
)
12946 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12948 switch (vex
.length
)
12966 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12971 /* Fall through. */
12974 if (l
!= 0 || len
!= 1)
12982 if (sizeflag
& SUFFIX_ALWAYS
)
12986 if (intel_mnemonic
!= cond
)
12990 if ((prefixes
& PREFIX_FWAIT
) == 0)
12993 used_prefixes
|= PREFIX_FWAIT
;
12999 else if (intel_syntax
&& (sizeflag
& DFLAG
))
13003 if (!(rex
& REX_W
))
13004 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13008 && address_mode
== mode_64bit
13009 && isa64
== intel64
)
13014 /* Fall through. */
13017 && address_mode
== mode_64bit
13018 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13023 /* Fall through. */
13026 if (l
== 0 && len
== 1)
13031 if ((rex
& REX_W
) == 0
13032 && (prefixes
& PREFIX_DATA
))
13034 if ((sizeflag
& DFLAG
) == 0)
13036 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13040 if ((prefixes
& PREFIX_DATA
)
13042 || (sizeflag
& SUFFIX_ALWAYS
))
13049 if (sizeflag
& DFLAG
)
13053 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13059 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13065 if ((prefixes
& PREFIX_DATA
)
13067 || (sizeflag
& SUFFIX_ALWAYS
))
13074 if (sizeflag
& DFLAG
)
13075 *obufp
++ = intel_syntax
? 'd' : 'l';
13078 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13086 if (address_mode
== mode_64bit
13087 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13089 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13093 /* Fall through. */
13096 if (l
== 0 && len
== 1)
13099 if (intel_syntax
&& !alt
)
13102 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13108 if (sizeflag
& DFLAG
)
13109 *obufp
++ = intel_syntax
? 'd' : 'l';
13112 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13118 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13124 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13139 else if (sizeflag
& DFLAG
)
13148 if (intel_syntax
&& !p
[1]
13149 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13151 if (!(rex
& REX_W
))
13152 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13155 if (l
== 0 && len
== 1)
13159 if (address_mode
== mode_64bit
13160 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13162 if (sizeflag
& SUFFIX_ALWAYS
)
13184 /* Fall through. */
13187 if (l
== 0 && len
== 1)
13192 if (sizeflag
& SUFFIX_ALWAYS
)
13198 if (sizeflag
& DFLAG
)
13202 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13216 if (address_mode
== mode_64bit
13217 && !(prefixes
& PREFIX_ADDR
))
13228 if (l
!= 0 || len
!= 1)
13233 if (need_vex
&& vex
.prefix
)
13235 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13242 if (prefixes
& PREFIX_DATA
)
13246 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13250 if (l
== 0 && len
== 1)
13254 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13262 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13264 switch (vex
.length
)
13280 if (l
== 0 && len
== 1)
13282 /* operand size flag for cwtl, cbtw */
13291 else if (sizeflag
& DFLAG
)
13295 if (!(rex
& REX_W
))
13296 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13303 && last
[0] != 'L'))
13310 if (last
[0] == 'X')
13311 *obufp
++ = vex
.w
? 'd': 's';
13313 *obufp
++ = vex
.w
? 'q': 'd';
13319 if (isa64
== intel64
&& (rex
& REX_W
))
13325 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13327 if (sizeflag
& DFLAG
)
13331 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13337 if (address_mode
== mode_64bit
13338 && (isa64
== intel64
13339 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13341 else if ((prefixes
& PREFIX_DATA
))
13343 if (!(sizeflag
& DFLAG
))
13345 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13352 mnemonicendp
= obufp
;
13357 oappend (const char *s
)
13359 obufp
= stpcpy (obufp
, s
);
13365 /* Only print the active segment register. */
13366 if (!active_seg_prefix
)
13369 used_prefixes
|= active_seg_prefix
;
13370 switch (active_seg_prefix
)
13373 oappend_maybe_intel ("%cs:");
13376 oappend_maybe_intel ("%ds:");
13379 oappend_maybe_intel ("%ss:");
13382 oappend_maybe_intel ("%es:");
13385 oappend_maybe_intel ("%fs:");
13388 oappend_maybe_intel ("%gs:");
13396 OP_indirE (int bytemode
, int sizeflag
)
13400 OP_E (bytemode
, sizeflag
);
13404 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13406 if (address_mode
== mode_64bit
)
13414 sprintf_vma (tmp
, disp
);
13415 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13416 strcpy (buf
+ 2, tmp
+ i
);
13420 bfd_signed_vma v
= disp
;
13427 /* Check for possible overflow on 0x8000000000000000. */
13430 strcpy (buf
, "9223372036854775808");
13444 tmp
[28 - i
] = (v
% 10) + '0';
13448 strcpy (buf
, tmp
+ 29 - i
);
13454 sprintf (buf
, "0x%x", (unsigned int) disp
);
13456 sprintf (buf
, "%d", (int) disp
);
13460 /* Put DISP in BUF as signed hex number. */
13463 print_displacement (char *buf
, bfd_vma disp
)
13465 bfd_signed_vma val
= disp
;
13474 /* Check for possible overflow. */
13477 switch (address_mode
)
13480 strcpy (buf
+ j
, "0x8000000000000000");
13483 strcpy (buf
+ j
, "0x80000000");
13486 strcpy (buf
+ j
, "0x8000");
13496 sprintf_vma (tmp
, (bfd_vma
) val
);
13497 for (i
= 0; tmp
[i
] == '0'; i
++)
13499 if (tmp
[i
] == '\0')
13501 strcpy (buf
+ j
, tmp
+ i
);
13505 intel_operand_size (int bytemode
, int sizeflag
)
13509 && (bytemode
== x_mode
13510 || bytemode
== evex_half_bcst_xmmq_mode
))
13513 oappend ("QWORD PTR ");
13515 oappend ("DWORD PTR ");
13524 oappend ("BYTE PTR ");
13529 oappend ("WORD PTR ");
13532 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13534 oappend ("QWORD PTR ");
13537 /* Fall through. */
13539 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13541 oappend ("QWORD PTR ");
13544 /* Fall through. */
13550 oappend ("QWORD PTR ");
13553 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13554 oappend ("DWORD PTR ");
13556 oappend ("WORD PTR ");
13557 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13561 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13563 oappend ("WORD PTR ");
13564 if (!(rex
& REX_W
))
13565 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13568 if (sizeflag
& DFLAG
)
13569 oappend ("QWORD PTR ");
13571 oappend ("DWORD PTR ");
13572 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13575 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13576 oappend ("WORD PTR ");
13578 oappend ("DWORD PTR ");
13579 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13582 case d_scalar_mode
:
13583 case d_scalar_swap_mode
:
13586 oappend ("DWORD PTR ");
13589 case q_scalar_mode
:
13590 case q_scalar_swap_mode
:
13592 oappend ("QWORD PTR ");
13595 if (address_mode
== mode_64bit
)
13596 oappend ("QWORD PTR ");
13598 oappend ("DWORD PTR ");
13601 if (sizeflag
& DFLAG
)
13602 oappend ("FWORD PTR ");
13604 oappend ("DWORD PTR ");
13605 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13608 oappend ("TBYTE PTR ");
13612 case evex_x_gscat_mode
:
13613 case evex_x_nobcst_mode
:
13614 case b_scalar_mode
:
13615 case w_scalar_mode
:
13618 switch (vex
.length
)
13621 oappend ("XMMWORD PTR ");
13624 oappend ("YMMWORD PTR ");
13627 oappend ("ZMMWORD PTR ");
13634 oappend ("XMMWORD PTR ");
13637 oappend ("XMMWORD PTR ");
13640 oappend ("YMMWORD PTR ");
13643 case evex_half_bcst_xmmq_mode
:
13647 switch (vex
.length
)
13650 oappend ("QWORD PTR ");
13653 oappend ("XMMWORD PTR ");
13656 oappend ("YMMWORD PTR ");
13666 switch (vex
.length
)
13671 oappend ("BYTE PTR ");
13681 switch (vex
.length
)
13686 oappend ("WORD PTR ");
13696 switch (vex
.length
)
13701 oappend ("DWORD PTR ");
13711 switch (vex
.length
)
13716 oappend ("QWORD PTR ");
13726 switch (vex
.length
)
13729 oappend ("WORD PTR ");
13732 oappend ("DWORD PTR ");
13735 oappend ("QWORD PTR ");
13745 switch (vex
.length
)
13748 oappend ("DWORD PTR ");
13751 oappend ("QWORD PTR ");
13754 oappend ("XMMWORD PTR ");
13764 switch (vex
.length
)
13767 oappend ("QWORD PTR ");
13770 oappend ("YMMWORD PTR ");
13773 oappend ("ZMMWORD PTR ");
13783 switch (vex
.length
)
13787 oappend ("XMMWORD PTR ");
13794 oappend ("OWORD PTR ");
13796 case vex_scalar_w_dq_mode
:
13801 oappend ("QWORD PTR ");
13803 oappend ("DWORD PTR ");
13805 case vex_vsib_d_w_dq_mode
:
13806 case vex_vsib_q_w_dq_mode
:
13813 oappend ("QWORD PTR ");
13815 oappend ("DWORD PTR ");
13819 switch (vex
.length
)
13822 oappend ("XMMWORD PTR ");
13825 oappend ("YMMWORD PTR ");
13828 oappend ("ZMMWORD PTR ");
13835 case vex_vsib_q_w_d_mode
:
13836 case vex_vsib_d_w_d_mode
:
13837 if (!need_vex
|| !vex
.evex
)
13840 switch (vex
.length
)
13843 oappend ("QWORD PTR ");
13846 oappend ("XMMWORD PTR ");
13849 oappend ("YMMWORD PTR ");
13857 if (!need_vex
|| vex
.length
!= 128)
13860 oappend ("DWORD PTR ");
13862 oappend ("BYTE PTR ");
13868 oappend ("QWORD PTR ");
13870 oappend ("WORD PTR ");
13880 OP_E_register (int bytemode
, int sizeflag
)
13882 int reg
= modrm
.rm
;
13883 const char **names
;
13889 if ((sizeflag
& SUFFIX_ALWAYS
)
13890 && (bytemode
== b_swap_mode
13891 || bytemode
== bnd_swap_mode
13892 || bytemode
== v_swap_mode
))
13918 names
= address_mode
== mode_64bit
? names64
: names32
;
13921 case bnd_swap_mode
:
13930 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13935 /* Fall through. */
13937 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13943 /* Fall through. */
13955 if ((sizeflag
& DFLAG
)
13956 || (bytemode
!= v_mode
13957 && bytemode
!= v_swap_mode
))
13961 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13965 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13969 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13972 names
= (address_mode
== mode_64bit
13973 ? names64
: names32
);
13974 if (!(prefixes
& PREFIX_ADDR
))
13975 names
= (address_mode
== mode_16bit
13976 ? names16
: names
);
13979 /* Remove "addr16/addr32". */
13980 all_prefixes
[last_addr_prefix
] = 0;
13981 names
= (address_mode
!= mode_32bit
13982 ? names32
: names16
);
13983 used_prefixes
|= PREFIX_ADDR
;
13993 names
= names_mask
;
13998 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14001 oappend (names
[reg
]);
14005 OP_E_memory (int bytemode
, int sizeflag
)
14008 int add
= (rex
& REX_B
) ? 8 : 0;
14014 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14016 && bytemode
!= x_mode
14017 && bytemode
!= xmmq_mode
14018 && bytemode
!= evex_half_bcst_xmmq_mode
)
14034 if (address_mode
!= mode_64bit
)
14040 case vex_scalar_w_dq_mode
:
14041 case vex_vsib_d_w_dq_mode
:
14042 case vex_vsib_d_w_d_mode
:
14043 case vex_vsib_q_w_dq_mode
:
14044 case vex_vsib_q_w_d_mode
:
14045 case evex_x_gscat_mode
:
14046 shift
= vex
.w
? 3 : 2;
14049 case evex_half_bcst_xmmq_mode
:
14053 shift
= vex
.w
? 3 : 2;
14056 /* Fall through. */
14060 case evex_x_nobcst_mode
:
14062 switch (vex
.length
)
14085 case q_scalar_mode
:
14087 case q_scalar_swap_mode
:
14093 case d_scalar_mode
:
14095 case d_scalar_swap_mode
:
14098 case w_scalar_mode
:
14102 case b_scalar_mode
:
14109 /* Make necessary corrections to shift for modes that need it.
14110 For these modes we currently have shift 4, 5 or 6 depending on
14111 vex.length (it corresponds to xmmword, ymmword or zmmword
14112 operand). We might want to make it 3, 4 or 5 (e.g. for
14113 xmmq_mode). In case of broadcast enabled the corrections
14114 aren't needed, as element size is always 32 or 64 bits. */
14116 && (bytemode
== xmmq_mode
14117 || bytemode
== evex_half_bcst_xmmq_mode
))
14119 else if (bytemode
== xmmqd_mode
)
14121 else if (bytemode
== xmmdw_mode
)
14123 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14131 intel_operand_size (bytemode
, sizeflag
);
14134 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14136 /* 32/64 bit address mode */
14146 int addr32flag
= !((sizeflag
& AFLAG
)
14147 || bytemode
== v_bnd_mode
14148 || bytemode
== v_bndmk_mode
14149 || bytemode
== bnd_mode
14150 || bytemode
== bnd_swap_mode
);
14151 const char **indexes64
= names64
;
14152 const char **indexes32
= names32
;
14162 vindex
= sib
.index
;
14168 case vex_vsib_d_w_dq_mode
:
14169 case vex_vsib_d_w_d_mode
:
14170 case vex_vsib_q_w_dq_mode
:
14171 case vex_vsib_q_w_d_mode
:
14181 switch (vex
.length
)
14184 indexes64
= indexes32
= names_xmm
;
14188 || bytemode
== vex_vsib_q_w_dq_mode
14189 || bytemode
== vex_vsib_q_w_d_mode
)
14190 indexes64
= indexes32
= names_ymm
;
14192 indexes64
= indexes32
= names_xmm
;
14196 || bytemode
== vex_vsib_q_w_dq_mode
14197 || bytemode
== vex_vsib_q_w_d_mode
)
14198 indexes64
= indexes32
= names_zmm
;
14200 indexes64
= indexes32
= names_ymm
;
14207 haveindex
= vindex
!= 4;
14214 rbase
= base
+ add
;
14222 if (address_mode
== mode_64bit
&& !havesib
)
14225 if (riprel
&& bytemode
== v_bndmk_mode
)
14233 FETCH_DATA (the_info
, codep
+ 1);
14235 if ((disp
& 0x80) != 0)
14237 if (vex
.evex
&& shift
> 0)
14250 && address_mode
!= mode_16bit
)
14252 if (address_mode
== mode_64bit
)
14254 /* Display eiz instead of addr32. */
14255 needindex
= addr32flag
;
14260 /* In 32-bit mode, we need index register to tell [offset]
14261 from [eiz*1 + offset]. */
14266 havedisp
= (havebase
14268 || (havesib
&& (haveindex
|| scale
!= 0)));
14271 if (modrm
.mod
!= 0 || base
== 5)
14273 if (havedisp
|| riprel
)
14274 print_displacement (scratchbuf
, disp
);
14276 print_operand_value (scratchbuf
, 1, disp
);
14277 oappend (scratchbuf
);
14281 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14285 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14286 && (address_mode
!= mode_64bit
14287 || ((bytemode
!= v_bnd_mode
)
14288 && (bytemode
!= v_bndmk_mode
)
14289 && (bytemode
!= bnd_mode
)
14290 && (bytemode
!= bnd_swap_mode
))))
14291 used_prefixes
|= PREFIX_ADDR
;
14293 if (havedisp
|| (intel_syntax
&& riprel
))
14295 *obufp
++ = open_char
;
14296 if (intel_syntax
&& riprel
)
14299 oappend (!addr32flag
? "rip" : "eip");
14303 oappend (address_mode
== mode_64bit
&& !addr32flag
14304 ? names64
[rbase
] : names32
[rbase
]);
14307 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14308 print index to tell base + index from base. */
14312 || (havebase
&& base
!= ESP_REG_NUM
))
14314 if (!intel_syntax
|| havebase
)
14316 *obufp
++ = separator_char
;
14320 oappend (address_mode
== mode_64bit
&& !addr32flag
14321 ? indexes64
[vindex
] : indexes32
[vindex
]);
14323 oappend (address_mode
== mode_64bit
&& !addr32flag
14324 ? index64
: index32
);
14326 *obufp
++ = scale_char
;
14328 sprintf (scratchbuf
, "%d", 1 << scale
);
14329 oappend (scratchbuf
);
14333 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14335 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14340 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14344 disp
= - (bfd_signed_vma
) disp
;
14348 print_displacement (scratchbuf
, disp
);
14350 print_operand_value (scratchbuf
, 1, disp
);
14351 oappend (scratchbuf
);
14354 *obufp
++ = close_char
;
14357 else if (intel_syntax
)
14359 if (modrm
.mod
!= 0 || base
== 5)
14361 if (!active_seg_prefix
)
14363 oappend (names_seg
[ds_reg
- es_reg
]);
14366 print_operand_value (scratchbuf
, 1, disp
);
14367 oappend (scratchbuf
);
14371 else if (bytemode
== v_bnd_mode
14372 || bytemode
== v_bndmk_mode
14373 || bytemode
== bnd_mode
14374 || bytemode
== bnd_swap_mode
)
14381 /* 16 bit address mode */
14382 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14389 if ((disp
& 0x8000) != 0)
14394 FETCH_DATA (the_info
, codep
+ 1);
14396 if ((disp
& 0x80) != 0)
14398 if (vex
.evex
&& shift
> 0)
14403 if ((disp
& 0x8000) != 0)
14409 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14411 print_displacement (scratchbuf
, disp
);
14412 oappend (scratchbuf
);
14415 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14417 *obufp
++ = open_char
;
14419 oappend (index16
[modrm
.rm
]);
14421 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14423 if ((bfd_signed_vma
) disp
>= 0)
14428 else if (modrm
.mod
!= 1)
14432 disp
= - (bfd_signed_vma
) disp
;
14435 print_displacement (scratchbuf
, disp
);
14436 oappend (scratchbuf
);
14439 *obufp
++ = close_char
;
14442 else if (intel_syntax
)
14444 if (!active_seg_prefix
)
14446 oappend (names_seg
[ds_reg
- es_reg
]);
14449 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14450 oappend (scratchbuf
);
14453 if (vex
.evex
&& vex
.b
14454 && (bytemode
== x_mode
14455 || bytemode
== xmmq_mode
14456 || bytemode
== evex_half_bcst_xmmq_mode
))
14459 || bytemode
== xmmq_mode
14460 || bytemode
== evex_half_bcst_xmmq_mode
)
14462 switch (vex
.length
)
14465 oappend ("{1to2}");
14468 oappend ("{1to4}");
14471 oappend ("{1to8}");
14479 switch (vex
.length
)
14482 oappend ("{1to4}");
14485 oappend ("{1to8}");
14488 oappend ("{1to16}");
14498 OP_E (int bytemode
, int sizeflag
)
14500 /* Skip mod/rm byte. */
14504 if (modrm
.mod
== 3)
14505 OP_E_register (bytemode
, sizeflag
);
14507 OP_E_memory (bytemode
, sizeflag
);
14511 OP_G (int bytemode
, int sizeflag
)
14514 const char **names
;
14523 oappend (names8rex
[modrm
.reg
+ add
]);
14525 oappend (names8
[modrm
.reg
+ add
]);
14528 oappend (names16
[modrm
.reg
+ add
]);
14533 oappend (names32
[modrm
.reg
+ add
]);
14536 oappend (names64
[modrm
.reg
+ add
]);
14539 if (modrm
.reg
> 0x3)
14544 oappend (names_bnd
[modrm
.reg
]);
14554 oappend (names64
[modrm
.reg
+ add
]);
14557 if ((sizeflag
& DFLAG
)
14558 || (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
))
14559 oappend (names32
[modrm
.reg
+ add
]);
14561 oappend (names16
[modrm
.reg
+ add
]);
14562 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14566 names
= (address_mode
== mode_64bit
14567 ? names64
: names32
);
14568 if (!(prefixes
& PREFIX_ADDR
))
14570 if (address_mode
== mode_16bit
)
14575 /* Remove "addr16/addr32". */
14576 all_prefixes
[last_addr_prefix
] = 0;
14577 names
= (address_mode
!= mode_32bit
14578 ? names32
: names16
);
14579 used_prefixes
|= PREFIX_ADDR
;
14581 oappend (names
[modrm
.reg
+ add
]);
14584 if (address_mode
== mode_64bit
)
14585 oappend (names64
[modrm
.reg
+ add
]);
14587 oappend (names32
[modrm
.reg
+ add
]);
14591 if ((modrm
.reg
+ add
) > 0x7)
14596 oappend (names_mask
[modrm
.reg
+ add
]);
14599 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14612 FETCH_DATA (the_info
, codep
+ 8);
14613 a
= *codep
++ & 0xff;
14614 a
|= (*codep
++ & 0xff) << 8;
14615 a
|= (*codep
++ & 0xff) << 16;
14616 a
|= (*codep
++ & 0xffu
) << 24;
14617 b
= *codep
++ & 0xff;
14618 b
|= (*codep
++ & 0xff) << 8;
14619 b
|= (*codep
++ & 0xff) << 16;
14620 b
|= (*codep
++ & 0xffu
) << 24;
14621 x
= a
+ ((bfd_vma
) b
<< 32);
14629 static bfd_signed_vma
14632 bfd_signed_vma x
= 0;
14634 FETCH_DATA (the_info
, codep
+ 4);
14635 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14636 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14637 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14638 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14642 static bfd_signed_vma
14645 bfd_signed_vma x
= 0;
14647 FETCH_DATA (the_info
, codep
+ 4);
14648 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14649 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14650 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14651 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14653 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14663 FETCH_DATA (the_info
, codep
+ 2);
14664 x
= *codep
++ & 0xff;
14665 x
|= (*codep
++ & 0xff) << 8;
14670 set_op (bfd_vma op
, int riprel
)
14672 op_index
[op_ad
] = op_ad
;
14673 if (address_mode
== mode_64bit
)
14675 op_address
[op_ad
] = op
;
14676 op_riprel
[op_ad
] = riprel
;
14680 /* Mask to get a 32-bit address. */
14681 op_address
[op_ad
] = op
& 0xffffffff;
14682 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14687 OP_REG (int code
, int sizeflag
)
14694 case es_reg
: case ss_reg
: case cs_reg
:
14695 case ds_reg
: case fs_reg
: case gs_reg
:
14696 oappend (names_seg
[code
- es_reg
]);
14708 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14709 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14710 s
= names16
[code
- ax_reg
+ add
];
14712 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14713 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14716 s
= names8rex
[code
- al_reg
+ add
];
14718 s
= names8
[code
- al_reg
];
14720 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14721 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14722 if (address_mode
== mode_64bit
14723 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14725 s
= names64
[code
- rAX_reg
+ add
];
14728 code
+= eAX_reg
- rAX_reg
;
14729 /* Fall through. */
14730 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14731 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14734 s
= names64
[code
- eAX_reg
+ add
];
14737 if (sizeflag
& DFLAG
)
14738 s
= names32
[code
- eAX_reg
+ add
];
14740 s
= names16
[code
- eAX_reg
+ add
];
14741 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14745 s
= INTERNAL_DISASSEMBLER_ERROR
;
14752 OP_IMREG (int code
, int sizeflag
)
14764 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14765 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14766 s
= names16
[code
- ax_reg
];
14768 case es_reg
: case ss_reg
: case cs_reg
:
14769 case ds_reg
: case fs_reg
: case gs_reg
:
14770 s
= names_seg
[code
- es_reg
];
14772 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14773 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14776 s
= names8rex
[code
- al_reg
];
14778 s
= names8
[code
- al_reg
];
14780 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14781 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14784 s
= names64
[code
- eAX_reg
];
14787 if (sizeflag
& DFLAG
)
14788 s
= names32
[code
- eAX_reg
];
14790 s
= names16
[code
- eAX_reg
];
14791 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14794 case z_mode_ax_reg
:
14795 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14799 if (!(rex
& REX_W
))
14800 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14803 s
= INTERNAL_DISASSEMBLER_ERROR
;
14810 OP_I (int bytemode
, int sizeflag
)
14813 bfd_signed_vma mask
= -1;
14818 FETCH_DATA (the_info
, codep
+ 1);
14828 if (sizeflag
& DFLAG
)
14838 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14854 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14859 scratchbuf
[0] = '$';
14860 print_operand_value (scratchbuf
+ 1, 1, op
);
14861 oappend_maybe_intel (scratchbuf
);
14862 scratchbuf
[0] = '\0';
14866 OP_I64 (int bytemode
, int sizeflag
)
14868 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14870 OP_I (bytemode
, sizeflag
);
14876 scratchbuf
[0] = '$';
14877 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14878 oappend_maybe_intel (scratchbuf
);
14879 scratchbuf
[0] = '\0';
14883 OP_sI (int bytemode
, int sizeflag
)
14891 FETCH_DATA (the_info
, codep
+ 1);
14893 if ((op
& 0x80) != 0)
14895 if (bytemode
== b_T_mode
)
14897 if (address_mode
!= mode_64bit
14898 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14900 /* The operand-size prefix is overridden by a REX prefix. */
14901 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14909 if (!(rex
& REX_W
))
14911 if (sizeflag
& DFLAG
)
14919 /* The operand-size prefix is overridden by a REX prefix. */
14920 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14926 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14930 scratchbuf
[0] = '$';
14931 print_operand_value (scratchbuf
+ 1, 1, op
);
14932 oappend_maybe_intel (scratchbuf
);
14936 OP_J (int bytemode
, int sizeflag
)
14940 bfd_vma segment
= 0;
14945 FETCH_DATA (the_info
, codep
+ 1);
14947 if ((disp
& 0x80) != 0)
14951 if (isa64
!= intel64
)
14954 if ((sizeflag
& DFLAG
)
14955 || (address_mode
== mode_64bit
14956 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
14957 || (rex
& REX_W
))))
14962 if ((disp
& 0x8000) != 0)
14964 /* In 16bit mode, address is wrapped around at 64k within
14965 the same segment. Otherwise, a data16 prefix on a jump
14966 instruction means that the pc is masked to 16 bits after
14967 the displacement is added! */
14969 if ((prefixes
& PREFIX_DATA
) == 0)
14970 segment
= ((start_pc
+ (codep
- start_codep
))
14971 & ~((bfd_vma
) 0xffff));
14973 if (address_mode
!= mode_64bit
14974 || (isa64
!= intel64
&& !(rex
& REX_W
)))
14975 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14978 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14981 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14983 print_operand_value (scratchbuf
, 1, disp
);
14984 oappend (scratchbuf
);
14988 OP_SEG (int bytemode
, int sizeflag
)
14990 if (bytemode
== w_mode
)
14991 oappend (names_seg
[modrm
.reg
]);
14993 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14997 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
15001 if (sizeflag
& DFLAG
)
15011 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15013 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15015 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15016 oappend (scratchbuf
);
15020 OP_OFF (int bytemode
, int sizeflag
)
15024 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15025 intel_operand_size (bytemode
, sizeflag
);
15028 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15035 if (!active_seg_prefix
)
15037 oappend (names_seg
[ds_reg
- es_reg
]);
15041 print_operand_value (scratchbuf
, 1, off
);
15042 oappend (scratchbuf
);
15046 OP_OFF64 (int bytemode
, int sizeflag
)
15050 if (address_mode
!= mode_64bit
15051 || (prefixes
& PREFIX_ADDR
))
15053 OP_OFF (bytemode
, sizeflag
);
15057 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15058 intel_operand_size (bytemode
, sizeflag
);
15065 if (!active_seg_prefix
)
15067 oappend (names_seg
[ds_reg
- es_reg
]);
15071 print_operand_value (scratchbuf
, 1, off
);
15072 oappend (scratchbuf
);
15076 ptr_reg (int code
, int sizeflag
)
15080 *obufp
++ = open_char
;
15081 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15082 if (address_mode
== mode_64bit
)
15084 if (!(sizeflag
& AFLAG
))
15085 s
= names32
[code
- eAX_reg
];
15087 s
= names64
[code
- eAX_reg
];
15089 else if (sizeflag
& AFLAG
)
15090 s
= names32
[code
- eAX_reg
];
15092 s
= names16
[code
- eAX_reg
];
15094 *obufp
++ = close_char
;
15099 OP_ESreg (int code
, int sizeflag
)
15105 case 0x6d: /* insw/insl */
15106 intel_operand_size (z_mode
, sizeflag
);
15108 case 0xa5: /* movsw/movsl/movsq */
15109 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15110 case 0xab: /* stosw/stosl */
15111 case 0xaf: /* scasw/scasl */
15112 intel_operand_size (v_mode
, sizeflag
);
15115 intel_operand_size (b_mode
, sizeflag
);
15118 oappend_maybe_intel ("%es:");
15119 ptr_reg (code
, sizeflag
);
15123 OP_DSreg (int code
, int sizeflag
)
15129 case 0x6f: /* outsw/outsl */
15130 intel_operand_size (z_mode
, sizeflag
);
15132 case 0xa5: /* movsw/movsl/movsq */
15133 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15134 case 0xad: /* lodsw/lodsl/lodsq */
15135 intel_operand_size (v_mode
, sizeflag
);
15138 intel_operand_size (b_mode
, sizeflag
);
15141 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15142 default segment register DS is printed. */
15143 if (!active_seg_prefix
)
15144 active_seg_prefix
= PREFIX_DS
;
15146 ptr_reg (code
, sizeflag
);
15150 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15158 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15160 all_prefixes
[last_lock_prefix
] = 0;
15161 used_prefixes
|= PREFIX_LOCK
;
15166 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15167 oappend_maybe_intel (scratchbuf
);
15171 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15180 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15182 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15183 oappend (scratchbuf
);
15187 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15189 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15190 oappend_maybe_intel (scratchbuf
);
15194 OP_R (int bytemode
, int sizeflag
)
15196 /* Skip mod/rm byte. */
15199 OP_E_register (bytemode
, sizeflag
);
15203 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15205 int reg
= modrm
.reg
;
15206 const char **names
;
15208 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15209 if (prefixes
& PREFIX_DATA
)
15218 oappend (names
[reg
]);
15222 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15224 int reg
= modrm
.reg
;
15225 const char **names
;
15237 && bytemode
!= xmm_mode
15238 && bytemode
!= xmmq_mode
15239 && bytemode
!= evex_half_bcst_xmmq_mode
15240 && bytemode
!= ymm_mode
15241 && bytemode
!= scalar_mode
)
15243 switch (vex
.length
)
15250 || (bytemode
!= vex_vsib_q_w_dq_mode
15251 && bytemode
!= vex_vsib_q_w_d_mode
))
15263 else if (bytemode
== xmmq_mode
15264 || bytemode
== evex_half_bcst_xmmq_mode
)
15266 switch (vex
.length
)
15279 else if (bytemode
== ymm_mode
)
15283 oappend (names
[reg
]);
15287 OP_EM (int bytemode
, int sizeflag
)
15290 const char **names
;
15292 if (modrm
.mod
!= 3)
15295 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15297 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15298 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15300 OP_E (bytemode
, sizeflag
);
15304 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15307 /* Skip mod/rm byte. */
15310 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15312 if (prefixes
& PREFIX_DATA
)
15321 oappend (names
[reg
]);
15324 /* cvt* are the only instructions in sse2 which have
15325 both SSE and MMX operands and also have 0x66 prefix
15326 in their opcode. 0x66 was originally used to differentiate
15327 between SSE and MMX instruction(operands). So we have to handle the
15328 cvt* separately using OP_EMC and OP_MXC */
15330 OP_EMC (int bytemode
, int sizeflag
)
15332 if (modrm
.mod
!= 3)
15334 if (intel_syntax
&& bytemode
== v_mode
)
15336 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15337 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15339 OP_E (bytemode
, sizeflag
);
15343 /* Skip mod/rm byte. */
15346 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15347 oappend (names_mm
[modrm
.rm
]);
15351 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15353 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15354 oappend (names_mm
[modrm
.reg
]);
15358 OP_EX (int bytemode
, int sizeflag
)
15361 const char **names
;
15363 /* Skip mod/rm byte. */
15367 if (modrm
.mod
!= 3)
15369 OP_E_memory (bytemode
, sizeflag
);
15384 if ((sizeflag
& SUFFIX_ALWAYS
)
15385 && (bytemode
== x_swap_mode
15386 || bytemode
== d_swap_mode
15387 || bytemode
== d_scalar_swap_mode
15388 || bytemode
== q_swap_mode
15389 || bytemode
== q_scalar_swap_mode
))
15393 && bytemode
!= xmm_mode
15394 && bytemode
!= xmmdw_mode
15395 && bytemode
!= xmmqd_mode
15396 && bytemode
!= xmm_mb_mode
15397 && bytemode
!= xmm_mw_mode
15398 && bytemode
!= xmm_md_mode
15399 && bytemode
!= xmm_mq_mode
15400 && bytemode
!= xmmq_mode
15401 && bytemode
!= evex_half_bcst_xmmq_mode
15402 && bytemode
!= ymm_mode
15403 && bytemode
!= d_scalar_mode
15404 && bytemode
!= d_scalar_swap_mode
15405 && bytemode
!= q_scalar_mode
15406 && bytemode
!= q_scalar_swap_mode
15407 && bytemode
!= vex_scalar_w_dq_mode
)
15409 switch (vex
.length
)
15424 else if (bytemode
== xmmq_mode
15425 || bytemode
== evex_half_bcst_xmmq_mode
)
15427 switch (vex
.length
)
15440 else if (bytemode
== ymm_mode
)
15444 oappend (names
[reg
]);
15448 OP_MS (int bytemode
, int sizeflag
)
15450 if (modrm
.mod
== 3)
15451 OP_EM (bytemode
, sizeflag
);
15457 OP_XS (int bytemode
, int sizeflag
)
15459 if (modrm
.mod
== 3)
15460 OP_EX (bytemode
, sizeflag
);
15466 OP_M (int bytemode
, int sizeflag
)
15468 if (modrm
.mod
== 3)
15469 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15472 OP_E (bytemode
, sizeflag
);
15476 OP_0f07 (int bytemode
, int sizeflag
)
15478 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15481 OP_E (bytemode
, sizeflag
);
15484 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15485 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15488 NOP_Fixup1 (int bytemode
, int sizeflag
)
15490 if ((prefixes
& PREFIX_DATA
) != 0
15493 && address_mode
== mode_64bit
))
15494 OP_REG (bytemode
, sizeflag
);
15496 strcpy (obuf
, "nop");
15500 NOP_Fixup2 (int bytemode
, int sizeflag
)
15502 if ((prefixes
& PREFIX_DATA
) != 0
15505 && address_mode
== mode_64bit
))
15506 OP_IMREG (bytemode
, sizeflag
);
15509 static const char *const Suffix3DNow
[] = {
15510 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15511 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15512 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15513 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15514 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15515 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15516 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15517 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15518 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15519 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15520 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15521 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15522 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15523 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15524 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15525 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15526 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15527 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15528 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15529 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15530 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15531 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15532 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15533 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15534 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15535 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15536 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15537 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15538 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15539 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15540 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15541 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15542 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15543 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15544 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15545 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15546 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15547 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15548 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15549 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15550 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15551 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15552 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15553 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15554 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15555 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15556 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15557 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15558 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15559 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15560 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15561 /* CC */ NULL
, NULL
, NULL
, NULL
,
15562 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15563 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15564 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15565 /* DC */ NULL
, NULL
, NULL
, NULL
,
15566 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15567 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15568 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15569 /* EC */ NULL
, NULL
, NULL
, NULL
,
15570 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15571 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15572 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15573 /* FC */ NULL
, NULL
, NULL
, NULL
,
15577 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15579 const char *mnemonic
;
15581 FETCH_DATA (the_info
, codep
+ 1);
15582 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15583 place where an 8-bit immediate would normally go. ie. the last
15584 byte of the instruction. */
15585 obufp
= mnemonicendp
;
15586 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15588 oappend (mnemonic
);
15591 /* Since a variable sized modrm/sib chunk is between the start
15592 of the opcode (0x0f0f) and the opcode suffix, we need to do
15593 all the modrm processing first, and don't know until now that
15594 we have a bad opcode. This necessitates some cleaning up. */
15595 op_out
[0][0] = '\0';
15596 op_out
[1][0] = '\0';
15599 mnemonicendp
= obufp
;
15602 static struct op simd_cmp_op
[] =
15604 { STRING_COMMA_LEN ("eq") },
15605 { STRING_COMMA_LEN ("lt") },
15606 { STRING_COMMA_LEN ("le") },
15607 { STRING_COMMA_LEN ("unord") },
15608 { STRING_COMMA_LEN ("neq") },
15609 { STRING_COMMA_LEN ("nlt") },
15610 { STRING_COMMA_LEN ("nle") },
15611 { STRING_COMMA_LEN ("ord") }
15615 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15617 unsigned int cmp_type
;
15619 FETCH_DATA (the_info
, codep
+ 1);
15620 cmp_type
= *codep
++ & 0xff;
15621 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15624 char *p
= mnemonicendp
- 2;
15628 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15629 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15633 /* We have a reserved extension byte. Output it directly. */
15634 scratchbuf
[0] = '$';
15635 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15636 oappend_maybe_intel (scratchbuf
);
15637 scratchbuf
[0] = '\0';
15642 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15644 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
15647 strcpy (op_out
[0], names32
[0]);
15648 strcpy (op_out
[1], names32
[1]);
15649 if (bytemode
== eBX_reg
)
15650 strcpy (op_out
[2], names32
[3]);
15651 two_source_ops
= 1;
15653 /* Skip mod/rm byte. */
15659 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15660 int sizeflag ATTRIBUTE_UNUSED
)
15662 /* monitor %{e,r,}ax,%ecx,%edx" */
15665 const char **names
= (address_mode
== mode_64bit
15666 ? names64
: names32
);
15668 if (prefixes
& PREFIX_ADDR
)
15670 /* Remove "addr16/addr32". */
15671 all_prefixes
[last_addr_prefix
] = 0;
15672 names
= (address_mode
!= mode_32bit
15673 ? names32
: names16
);
15674 used_prefixes
|= PREFIX_ADDR
;
15676 else if (address_mode
== mode_16bit
)
15678 strcpy (op_out
[0], names
[0]);
15679 strcpy (op_out
[1], names32
[1]);
15680 strcpy (op_out
[2], names32
[2]);
15681 two_source_ops
= 1;
15683 /* Skip mod/rm byte. */
15691 /* Throw away prefixes and 1st. opcode byte. */
15692 codep
= insn_codep
+ 1;
15697 REP_Fixup (int bytemode
, int sizeflag
)
15699 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15701 if (prefixes
& PREFIX_REPZ
)
15702 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15709 OP_IMREG (bytemode
, sizeflag
);
15712 OP_ESreg (bytemode
, sizeflag
);
15715 OP_DSreg (bytemode
, sizeflag
);
15724 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15726 if ( isa64
!= amd64
)
15731 mnemonicendp
= obufp
;
15735 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15739 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15741 if (prefixes
& PREFIX_REPNZ
)
15742 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15745 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15749 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15750 int sizeflag ATTRIBUTE_UNUSED
)
15752 if (active_seg_prefix
== PREFIX_DS
15753 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15755 /* NOTRACK prefix is only valid on indirect branch instructions.
15756 NB: DATA prefix is unsupported for Intel64. */
15757 active_seg_prefix
= 0;
15758 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15762 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15763 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15767 HLE_Fixup1 (int bytemode
, int sizeflag
)
15770 && (prefixes
& PREFIX_LOCK
) != 0)
15772 if (prefixes
& PREFIX_REPZ
)
15773 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15774 if (prefixes
& PREFIX_REPNZ
)
15775 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15778 OP_E (bytemode
, sizeflag
);
15781 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15782 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15786 HLE_Fixup2 (int bytemode
, int sizeflag
)
15788 if (modrm
.mod
!= 3)
15790 if (prefixes
& PREFIX_REPZ
)
15791 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15792 if (prefixes
& PREFIX_REPNZ
)
15793 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15796 OP_E (bytemode
, sizeflag
);
15799 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15800 "xrelease" for memory operand. No check for LOCK prefix. */
15803 HLE_Fixup3 (int bytemode
, int sizeflag
)
15806 && last_repz_prefix
> last_repnz_prefix
15807 && (prefixes
& PREFIX_REPZ
) != 0)
15808 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15810 OP_E (bytemode
, sizeflag
);
15814 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15819 /* Change cmpxchg8b to cmpxchg16b. */
15820 char *p
= mnemonicendp
- 2;
15821 mnemonicendp
= stpcpy (p
, "16b");
15824 else if ((prefixes
& PREFIX_LOCK
) != 0)
15826 if (prefixes
& PREFIX_REPZ
)
15827 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15828 if (prefixes
& PREFIX_REPNZ
)
15829 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15832 OP_M (bytemode
, sizeflag
);
15836 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15838 const char **names
;
15842 switch (vex
.length
)
15856 oappend (names
[reg
]);
15860 CRC32_Fixup (int bytemode
, int sizeflag
)
15862 /* Add proper suffix to "crc32". */
15863 char *p
= mnemonicendp
;
15882 if (sizeflag
& DFLAG
)
15886 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15890 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15897 if (modrm
.mod
== 3)
15901 /* Skip mod/rm byte. */
15906 add
= (rex
& REX_B
) ? 8 : 0;
15907 if (bytemode
== b_mode
)
15911 oappend (names8rex
[modrm
.rm
+ add
]);
15913 oappend (names8
[modrm
.rm
+ add
]);
15919 oappend (names64
[modrm
.rm
+ add
]);
15920 else if ((prefixes
& PREFIX_DATA
))
15921 oappend (names16
[modrm
.rm
+ add
]);
15923 oappend (names32
[modrm
.rm
+ add
]);
15927 OP_E (bytemode
, sizeflag
);
15931 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15933 /* Add proper suffix to "fxsave" and "fxrstor". */
15937 char *p
= mnemonicendp
;
15943 OP_M (bytemode
, sizeflag
);
15947 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15949 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15952 char *p
= mnemonicendp
;
15957 else if (sizeflag
& SUFFIX_ALWAYS
)
15964 OP_EX (bytemode
, sizeflag
);
15967 /* Display the destination register operand for instructions with
15971 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15974 const char **names
;
15982 reg
= vex
.register_specifier
;
15983 vex
.register_specifier
= 0;
15984 if (address_mode
!= mode_64bit
)
15986 else if (vex
.evex
&& !vex
.v
)
15989 if (bytemode
== vex_scalar_mode
)
15991 oappend (names_xmm
[reg
]);
15995 switch (vex
.length
)
16002 case vex_vsib_q_w_dq_mode
:
16003 case vex_vsib_q_w_d_mode
:
16019 names
= names_mask
;
16033 case vex_vsib_q_w_dq_mode
:
16034 case vex_vsib_q_w_d_mode
:
16035 names
= vex
.w
? names_ymm
: names_xmm
;
16044 names
= names_mask
;
16047 /* See PR binutils/20893 for a reproducer. */
16059 oappend (names
[reg
]);
16062 /* Get the VEX immediate byte without moving codep. */
16064 static unsigned char
16065 get_vex_imm8 (int sizeflag
, int opnum
)
16067 int bytes_before_imm
= 0;
16069 if (modrm
.mod
!= 3)
16071 /* There are SIB/displacement bytes. */
16072 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16074 /* 32/64 bit address mode */
16075 int base
= modrm
.rm
;
16077 /* Check SIB byte. */
16080 FETCH_DATA (the_info
, codep
+ 1);
16082 /* When decoding the third source, don't increase
16083 bytes_before_imm as this has already been incremented
16084 by one in OP_E_memory while decoding the second
16087 bytes_before_imm
++;
16090 /* Don't increase bytes_before_imm when decoding the third source,
16091 it has already been incremented by OP_E_memory while decoding
16092 the second source operand. */
16098 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16099 SIB == 5, there is a 4 byte displacement. */
16101 /* No displacement. */
16103 /* Fall through. */
16105 /* 4 byte displacement. */
16106 bytes_before_imm
+= 4;
16109 /* 1 byte displacement. */
16110 bytes_before_imm
++;
16117 /* 16 bit address mode */
16118 /* Don't increase bytes_before_imm when decoding the third source,
16119 it has already been incremented by OP_E_memory while decoding
16120 the second source operand. */
16126 /* When modrm.rm == 6, there is a 2 byte displacement. */
16128 /* No displacement. */
16130 /* Fall through. */
16132 /* 2 byte displacement. */
16133 bytes_before_imm
+= 2;
16136 /* 1 byte displacement: when decoding the third source,
16137 don't increase bytes_before_imm as this has already
16138 been incremented by one in OP_E_memory while decoding
16139 the second source operand. */
16141 bytes_before_imm
++;
16149 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16150 return codep
[bytes_before_imm
];
16154 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16156 const char **names
;
16158 if (reg
== -1 && modrm
.mod
!= 3)
16160 OP_E_memory (bytemode
, sizeflag
);
16172 if (address_mode
!= mode_64bit
)
16176 switch (vex
.length
)
16187 oappend (names
[reg
]);
16191 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16194 static unsigned char vex_imm8
;
16196 if (vex_w_done
== 0)
16200 /* Skip mod/rm byte. */
16204 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16207 reg
= vex_imm8
>> 4;
16209 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16211 else if (vex_w_done
== 1)
16216 reg
= vex_imm8
>> 4;
16218 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16222 /* Output the imm8 directly. */
16223 scratchbuf
[0] = '$';
16224 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16225 oappend_maybe_intel (scratchbuf
);
16226 scratchbuf
[0] = '\0';
16232 OP_Vex_2src (int bytemode
, int sizeflag
)
16234 if (modrm
.mod
== 3)
16236 int reg
= modrm
.rm
;
16240 oappend (names_xmm
[reg
]);
16245 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16247 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16248 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16250 OP_E (bytemode
, sizeflag
);
16255 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16257 if (modrm
.mod
== 3)
16259 /* Skip mod/rm byte. */
16266 unsigned int reg
= vex
.register_specifier
;
16267 vex
.register_specifier
= 0;
16269 if (address_mode
!= mode_64bit
)
16271 oappend (names_xmm
[reg
]);
16274 OP_Vex_2src (bytemode
, sizeflag
);
16278 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16281 OP_Vex_2src (bytemode
, sizeflag
);
16284 unsigned int reg
= vex
.register_specifier
;
16285 vex
.register_specifier
= 0;
16287 if (address_mode
!= mode_64bit
)
16289 oappend (names_xmm
[reg
]);
16294 OP_EX_VexW (int bytemode
, int sizeflag
)
16300 /* Skip mod/rm byte. */
16305 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16310 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16313 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16321 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16324 const char **names
;
16326 FETCH_DATA (the_info
, codep
+ 1);
16329 if (bytemode
!= x_mode
)
16333 if (address_mode
!= mode_64bit
)
16336 switch (vex
.length
)
16347 oappend (names
[reg
]);
16351 OP_XMM_VexW (int bytemode
, int sizeflag
)
16353 /* Turn off the REX.W bit since it is used for swapping operands
16356 OP_XMM (bytemode
, sizeflag
);
16360 OP_EX_Vex (int bytemode
, int sizeflag
)
16362 if (modrm
.mod
!= 3)
16364 OP_EX (bytemode
, sizeflag
);
16368 OP_XMM_Vex (int bytemode
, int sizeflag
)
16370 if (modrm
.mod
!= 3)
16372 OP_XMM (bytemode
, sizeflag
);
16375 static struct op vex_cmp_op
[] =
16377 { STRING_COMMA_LEN ("eq") },
16378 { STRING_COMMA_LEN ("lt") },
16379 { STRING_COMMA_LEN ("le") },
16380 { STRING_COMMA_LEN ("unord") },
16381 { STRING_COMMA_LEN ("neq") },
16382 { STRING_COMMA_LEN ("nlt") },
16383 { STRING_COMMA_LEN ("nle") },
16384 { STRING_COMMA_LEN ("ord") },
16385 { STRING_COMMA_LEN ("eq_uq") },
16386 { STRING_COMMA_LEN ("nge") },
16387 { STRING_COMMA_LEN ("ngt") },
16388 { STRING_COMMA_LEN ("false") },
16389 { STRING_COMMA_LEN ("neq_oq") },
16390 { STRING_COMMA_LEN ("ge") },
16391 { STRING_COMMA_LEN ("gt") },
16392 { STRING_COMMA_LEN ("true") },
16393 { STRING_COMMA_LEN ("eq_os") },
16394 { STRING_COMMA_LEN ("lt_oq") },
16395 { STRING_COMMA_LEN ("le_oq") },
16396 { STRING_COMMA_LEN ("unord_s") },
16397 { STRING_COMMA_LEN ("neq_us") },
16398 { STRING_COMMA_LEN ("nlt_uq") },
16399 { STRING_COMMA_LEN ("nle_uq") },
16400 { STRING_COMMA_LEN ("ord_s") },
16401 { STRING_COMMA_LEN ("eq_us") },
16402 { STRING_COMMA_LEN ("nge_uq") },
16403 { STRING_COMMA_LEN ("ngt_uq") },
16404 { STRING_COMMA_LEN ("false_os") },
16405 { STRING_COMMA_LEN ("neq_os") },
16406 { STRING_COMMA_LEN ("ge_oq") },
16407 { STRING_COMMA_LEN ("gt_oq") },
16408 { STRING_COMMA_LEN ("true_us") },
16412 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16414 unsigned int cmp_type
;
16416 FETCH_DATA (the_info
, codep
+ 1);
16417 cmp_type
= *codep
++ & 0xff;
16418 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16421 char *p
= mnemonicendp
- 2;
16425 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16426 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16430 /* We have a reserved extension byte. Output it directly. */
16431 scratchbuf
[0] = '$';
16432 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16433 oappend_maybe_intel (scratchbuf
);
16434 scratchbuf
[0] = '\0';
16439 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16440 int sizeflag ATTRIBUTE_UNUSED
)
16442 unsigned int cmp_type
;
16447 FETCH_DATA (the_info
, codep
+ 1);
16448 cmp_type
= *codep
++ & 0xff;
16449 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16450 If it's the case, print suffix, otherwise - print the immediate. */
16451 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16456 char *p
= mnemonicendp
- 2;
16458 /* vpcmp* can have both one- and two-lettered suffix. */
16472 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16473 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16477 /* We have a reserved extension byte. Output it directly. */
16478 scratchbuf
[0] = '$';
16479 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16480 oappend_maybe_intel (scratchbuf
);
16481 scratchbuf
[0] = '\0';
16485 static const struct op xop_cmp_op
[] =
16487 { STRING_COMMA_LEN ("lt") },
16488 { STRING_COMMA_LEN ("le") },
16489 { STRING_COMMA_LEN ("gt") },
16490 { STRING_COMMA_LEN ("ge") },
16491 { STRING_COMMA_LEN ("eq") },
16492 { STRING_COMMA_LEN ("neq") },
16493 { STRING_COMMA_LEN ("false") },
16494 { STRING_COMMA_LEN ("true") }
16498 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16499 int sizeflag ATTRIBUTE_UNUSED
)
16501 unsigned int cmp_type
;
16503 FETCH_DATA (the_info
, codep
+ 1);
16504 cmp_type
= *codep
++ & 0xff;
16505 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16508 char *p
= mnemonicendp
- 2;
16510 /* vpcom* can have both one- and two-lettered suffix. */
16524 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16525 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16529 /* We have a reserved extension byte. Output it directly. */
16530 scratchbuf
[0] = '$';
16531 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16532 oappend_maybe_intel (scratchbuf
);
16533 scratchbuf
[0] = '\0';
16537 static const struct op pclmul_op
[] =
16539 { STRING_COMMA_LEN ("lql") },
16540 { STRING_COMMA_LEN ("hql") },
16541 { STRING_COMMA_LEN ("lqh") },
16542 { STRING_COMMA_LEN ("hqh") }
16546 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16547 int sizeflag ATTRIBUTE_UNUSED
)
16549 unsigned int pclmul_type
;
16551 FETCH_DATA (the_info
, codep
+ 1);
16552 pclmul_type
= *codep
++ & 0xff;
16553 switch (pclmul_type
)
16564 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16567 char *p
= mnemonicendp
- 3;
16572 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16573 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16577 /* We have a reserved extension byte. Output it directly. */
16578 scratchbuf
[0] = '$';
16579 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16580 oappend_maybe_intel (scratchbuf
);
16581 scratchbuf
[0] = '\0';
16586 MOVBE_Fixup (int bytemode
, int sizeflag
)
16588 /* Add proper suffix to "movbe". */
16589 char *p
= mnemonicendp
;
16598 if (sizeflag
& SUFFIX_ALWAYS
)
16604 if (sizeflag
& DFLAG
)
16608 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16613 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16620 OP_M (bytemode
, sizeflag
);
16624 MOVSXD_Fixup (int bytemode
, int sizeflag
)
16626 /* Add proper suffix to "movsxd". */
16627 char *p
= mnemonicendp
;
16652 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16659 OP_E (bytemode
, sizeflag
);
16663 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16666 const char **names
;
16668 /* Skip mod/rm byte. */
16682 oappend (names
[reg
]);
16686 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16688 const char **names
;
16689 unsigned int reg
= vex
.register_specifier
;
16690 vex
.register_specifier
= 0;
16697 if (address_mode
!= mode_64bit
)
16699 oappend (names
[reg
]);
16703 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16706 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16710 if ((rex
& REX_R
) != 0 || !vex
.r
)
16716 oappend (names_mask
[modrm
.reg
]);
16720 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16723 || (bytemode
!= evex_rounding_mode
16724 && bytemode
!= evex_rounding_64_mode
16725 && bytemode
!= evex_sae_mode
))
16727 if (modrm
.mod
== 3 && vex
.b
)
16730 case evex_rounding_64_mode
:
16731 if (address_mode
!= mode_64bit
)
16736 /* Fall through. */
16737 case evex_rounding_mode
:
16738 oappend (names_rounding
[vex
.ll
]);
16740 case evex_sae_mode
: