opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int fetch_data (struct disassemble_info *, bfd_byte *);
  46 static void ckprefix (void);
  47 static const char *prefix_name (int, int);
  48 static int print_insn (bfd_vma, disassemble_info *);
  49 static void dofloat (int);
  50 static void OP_ST (int, int);
  51 static void OP_STi (int, int);
  52 static int putop (const char *, int);
  53 static void oappend (const char *);
  54 static void append_seg (void);
  55 static void OP_indirE (int, int);
  56 static void print_operand_value (char *, int, bfd_vma);
  57 static void OP_E_register (int, int);
  58 static void OP_E_memory (int, int);
  59 static void OP_E_extended (int, int);
  60 static void print_displacement (char *, bfd_vma);
  61 static void OP_E (int, int);
  62 static void OP_G (int, int);
  63 static bfd_vma get64 (void);
  64 static bfd_signed_vma get32 (void);
  65 static bfd_signed_vma get32s (void);
  66 static int get16 (void);
  67 static void set_op (bfd_vma, int);
  68 static void OP_Skip_MODRM (int, int);
  69 static void OP_REG (int, int);
  70 static void OP_IMREG (int, int);
  71 static void OP_I (int, int);
  72 static void OP_I64 (int, int);
  73 static void OP_sI (int, int);
  74 static void OP_J (int, int);
  75 static void OP_SEG (int, int);
  76 static void OP_DIR (int, int);
  77 static void OP_OFF (int, int);
  78 static void OP_OFF64 (int, int);
  79 static void ptr_reg (int, int);
  80 static void OP_ESreg (int, int);
  81 static void OP_DSreg (int, int);
  82 static void OP_C (int, int);
  83 static void OP_D (int, int);
  84 static void OP_T (int, int);
  85 static void OP_R (int, int);
  86 static void OP_MMX (int, int);
  87 static void OP_XMM (int, int);
  88 static void OP_EM (int, int);
  89 static void OP_EX (int, int);
  90 static void OP_EMC (int,int);
  91 static void OP_MXC (int,int);
  92 static void OP_MS (int, int);
  93 static void OP_XS (int, int);
  94 static void OP_M (int, int);
  95 static void OP_VEX (int, int);
  96 static void OP_EX_Vex (int, int);
  97 static void OP_EX_VexW (int, int);
  98 static void OP_XMM_Vex (int, int);
  99 static void OP_XMM_VexW (int, int);
 100 static void OP_REG_VexI4 (int, int);
 101 static void PCLMUL_Fixup (int, int);
 102 static void VEXI4_Fixup (int, int);
 103 static void VZERO_Fixup (int, int);
 104 static void VCMP_Fixup (int, int);
 105 static void OP_0f07 (int, int);
 106 static void OP_Monitor (int, int);
 107 static void OP_Mwait (int, int);
 108 static void NOP_Fixup1 (int, int);
 109 static void NOP_Fixup2 (int, int);
 110 static void OP_3DNowSuffix (int, int);
 111 static void CMP_Fixup (int, int);
 112 static void BadOp (void);
 113 static void REP_Fixup (int, int);
 114 static void CMPXCHG8B_Fixup (int, int);
 115 static void XMM_Fixup (int, int);
 116 static void CRC32_Fixup (int, int);
 117
 118 static void MOVBE_Fixup (int, int);
 119
 120 struct dis_private {
 121   /* Points to first byte not fetched.  */
 122   bfd_byte *max_fetched;
 123   bfd_byte the_buffer[MAX_MNEM_SIZE];
 124   bfd_vma insn_start;
 125   int orig_sizeflag;
 126   jmp_buf bailout;
 127 };
 128
 129 enum address_mode
 130 {
 131   mode_16bit,
 132   mode_32bit,
 133   mode_64bit
 134 };
 135
 136 enum address_mode address_mode;
 137
 138 /* Flags for the prefixes for the current instruction.  See below.  */
 139 static int prefixes;
 140
 141 /* REX prefix the current instruction.  See below.  */
 142 static int rex;
 143 /* Bits of REX we've already used.  */
 144 static int rex_used;
 145 /* Original REX prefix.  */
 146 static int rex_original;
 147 /* REX bits in original REX prefix ignored.  It may not be the same
 148    as rex_original since some bits may not be ignored.  */
 149 static int rex_ignored;
 150 /* Mark parts used in the REX prefix.  When we are testing for
 151    empty prefix (for 8bit register REX extension), just mask it
 152    out.  Otherwise test for REX bit is excuse for existence of REX
 153    only in case value is nonzero.  */
 154 #define USED_REX(value)                                 \
 155   {                                                     \
 156     if (value)                                          \
 157       {                                                 \
 158         if ((rex & value))                              \
 159           rex_used |= (value) | REX_OPCODE;             \
 160       }                                                 \
 161     else                                                \
 162       rex_used |= REX_OPCODE;                           \
 163   }
 164
 165 /* Flags for prefixes which we somehow handled when printing the
 166    current instruction.  */
 167 static int used_prefixes;
 168
 169 /* Flags stored in PREFIXES.  */
 170 #define PREFIX_REPZ 1
 171 #define PREFIX_REPNZ 2
 172 #define PREFIX_LOCK 4
 173 #define PREFIX_CS 8
 174 #define PREFIX_SS 0x10
 175 #define PREFIX_DS 0x20
 176 #define PREFIX_ES 0x40
 177 #define PREFIX_FS 0x80
 178 #define PREFIX_GS 0x100
 179 #define PREFIX_DATA 0x200
 180 #define PREFIX_ADDR 0x400
 181 #define PREFIX_FWAIT 0x800
 182
 183 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 184    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 185    on error.  */
 186 #define FETCH_DATA(info, addr) \
 187   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 188    ? 1 : fetch_data ((info), (addr)))
 189
 190 static int
 191 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 192 {
 193   int status;
 194   struct dis_private *priv = (struct dis_private *) info->private_data;
 195   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 196
 197   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 198     status = (*info->read_memory_func) (start,
 199                                         priv->max_fetched,
 200                                         addr - priv->max_fetched,
 201                                         info);
 202   else
 203     status = -1;
 204   if (status != 0)
 205     {
 206       /* If we did manage to read at least one byte, then
 207          print_insn_i386 will do something sensible.  Otherwise, print
 208          an error.  We do that here because this is where we know
 209          STATUS.  */
 210       if (priv->max_fetched == priv->the_buffer)
 211         (*info->memory_error_func) (status, start, info);
 212       longjmp (priv->bailout, 1);
 213     }
 214   else
 215     priv->max_fetched = addr;
 216   return 1;
 217 }
 218
 219 #define XX { NULL, 0 }
 220
 221 #define Eb { OP_E, b_mode }
 222 #define EbS { OP_E, b_swap_mode }
 223 #define Ev { OP_E, v_mode }
 224 #define EvS { OP_E, v_swap_mode }
 225 #define Ed { OP_E, d_mode }
 226 #define Edq { OP_E, dq_mode }
 227 #define Edqw { OP_E, dqw_mode }
 228 #define Edqb { OP_E, dqb_mode }
 229 #define Edqd { OP_E, dqd_mode }
 230 #define Eq { OP_E, q_mode }
 231 #define indirEv { OP_indirE, stack_v_mode }
 232 #define indirEp { OP_indirE, f_mode }
 233 #define stackEv { OP_E, stack_v_mode }
 234 #define Em { OP_E, m_mode }
 235 #define Ew { OP_E, w_mode }
 236 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 237 #define Ma { OP_M, a_mode }
 238 #define Mb { OP_M, b_mode }
 239 #define Md { OP_M, d_mode }
 240 #define Mo { OP_M, o_mode }
 241 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 242 #define Mq { OP_M, q_mode }
 243 #define Mx { OP_M, x_mode }
 244 #define Mxmm { OP_M, xmm_mode }
 245 #define Gb { OP_G, b_mode }
 246 #define Gv { OP_G, v_mode }
 247 #define Gd { OP_G, d_mode }
 248 #define Gdq { OP_G, dq_mode }
 249 #define Gm { OP_G, m_mode }
 250 #define Gw { OP_G, w_mode }
 251 #define Rd { OP_R, d_mode }
 252 #define Rm { OP_R, m_mode }
 253 #define Ib { OP_I, b_mode }
 254 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 255 #define Iv { OP_I, v_mode }
 256 #define Iq { OP_I, q_mode }
 257 #define Iv64 { OP_I64, v_mode }
 258 #define Iw { OP_I, w_mode }
 259 #define I1 { OP_I, const_1_mode }
 260 #define Jb { OP_J, b_mode }
 261 #define Jv { OP_J, v_mode }
 262 #define Cm { OP_C, m_mode }
 263 #define Dm { OP_D, m_mode }
 264 #define Td { OP_T, d_mode }
 265 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 266
 267 #define RMeAX { OP_REG, eAX_reg }
 268 #define RMeBX { OP_REG, eBX_reg }
 269 #define RMeCX { OP_REG, eCX_reg }
 270 #define RMeDX { OP_REG, eDX_reg }
 271 #define RMeSP { OP_REG, eSP_reg }
 272 #define RMeBP { OP_REG, eBP_reg }
 273 #define RMeSI { OP_REG, eSI_reg }
 274 #define RMeDI { OP_REG, eDI_reg }
 275 #define RMrAX { OP_REG, rAX_reg }
 276 #define RMrBX { OP_REG, rBX_reg }
 277 #define RMrCX { OP_REG, rCX_reg }
 278 #define RMrDX { OP_REG, rDX_reg }
 279 #define RMrSP { OP_REG, rSP_reg }
 280 #define RMrBP { OP_REG, rBP_reg }
 281 #define RMrSI { OP_REG, rSI_reg }
 282 #define RMrDI { OP_REG, rDI_reg }
 283 #define RMAL { OP_REG, al_reg }
 284 #define RMAL { OP_REG, al_reg }
 285 #define RMCL { OP_REG, cl_reg }
 286 #define RMDL { OP_REG, dl_reg }
 287 #define RMBL { OP_REG, bl_reg }
 288 #define RMAH { OP_REG, ah_reg }
 289 #define RMCH { OP_REG, ch_reg }
 290 #define RMDH { OP_REG, dh_reg }
 291 #define RMBH { OP_REG, bh_reg }
 292 #define RMAX { OP_REG, ax_reg }
 293 #define RMDX { OP_REG, dx_reg }
 294
 295 #define eAX { OP_IMREG, eAX_reg }
 296 #define eBX { OP_IMREG, eBX_reg }
 297 #define eCX { OP_IMREG, eCX_reg }
 298 #define eDX { OP_IMREG, eDX_reg }
 299 #define eSP { OP_IMREG, eSP_reg }
 300 #define eBP { OP_IMREG, eBP_reg }
 301 #define eSI { OP_IMREG, eSI_reg }
 302 #define eDI { OP_IMREG, eDI_reg }
 303 #define AL { OP_IMREG, al_reg }
 304 #define CL { OP_IMREG, cl_reg }
 305 #define DL { OP_IMREG, dl_reg }
 306 #define BL { OP_IMREG, bl_reg }
 307 #define AH { OP_IMREG, ah_reg }
 308 #define CH { OP_IMREG, ch_reg }
 309 #define DH { OP_IMREG, dh_reg }
 310 #define BH { OP_IMREG, bh_reg }
 311 #define AX { OP_IMREG, ax_reg }
 312 #define DX { OP_IMREG, dx_reg }
 313 #define zAX { OP_IMREG, z_mode_ax_reg }
 314 #define indirDX { OP_IMREG, indir_dx_reg }
 315
 316 #define Sw { OP_SEG, w_mode }
 317 #define Sv { OP_SEG, v_mode }
 318 #define Ap { OP_DIR, 0 }
 319 #define Ob { OP_OFF64, b_mode }
 320 #define Ov { OP_OFF64, v_mode }
 321 #define Xb { OP_DSreg, eSI_reg }
 322 #define Xv { OP_DSreg, eSI_reg }
 323 #define Xz { OP_DSreg, eSI_reg }
 324 #define Yb { OP_ESreg, eDI_reg }
 325 #define Yv { OP_ESreg, eDI_reg }
 326 #define DSBX { OP_DSreg, eBX_reg }
 327
 328 #define es { OP_REG, es_reg }
 329 #define ss { OP_REG, ss_reg }
 330 #define cs { OP_REG, cs_reg }
 331 #define ds { OP_REG, ds_reg }
 332 #define fs { OP_REG, fs_reg }
 333 #define gs { OP_REG, gs_reg }
 334
 335 #define MX { OP_MMX, 0 }
 336 #define XM { OP_XMM, 0 }
 337 #define XMM { OP_XMM, xmm_mode }
 338 #define EM { OP_EM, v_mode }
 339 #define EMS { OP_EM, v_swap_mode }
 340 #define EMd { OP_EM, d_mode }
 341 #define EMx { OP_EM, x_mode }
 342 #define EXw { OP_EX, w_mode }
 343 #define EXd { OP_EX, d_mode }
 344 #define EXdS { OP_EX, d_swap_mode }
 345 #define EXq { OP_EX, q_mode }
 346 #define EXqS { OP_EX, q_swap_mode }
 347 #define EXx { OP_EX, x_mode }
 348 #define EXxS { OP_EX, x_swap_mode }
 349 #define EXxmm { OP_EX, xmm_mode }
 350 #define EXxmmq { OP_EX, xmmq_mode }
 351 #define EXymmq { OP_EX, ymmq_mode }
 352 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 353 #define MS { OP_MS, v_mode }
 354 #define XS { OP_XS, v_mode }
 355 #define EMCq { OP_EMC, q_mode }
 356 #define MXC { OP_MXC, 0 }
 357 #define OPSUF { OP_3DNowSuffix, 0 }
 358 #define CMP { CMP_Fixup, 0 }
 359 #define XMM0 { XMM_Fixup, 0 }
 360
 361 #define Vex { OP_VEX, vex_mode }
 362 #define Vex128 { OP_VEX, vex128_mode }
 363 #define Vex256 { OP_VEX, vex256_mode }
 364 #define VexI4 { VEXI4_Fixup, 0}
 365 #define EXdVex { OP_EX_Vex, d_mode }
 366 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 367 #define EXqVex { OP_EX_Vex, q_mode }
 368 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 369 #define EXVexW { OP_EX_VexW, x_mode }
 370 #define EXdVexW { OP_EX_VexW, d_mode }
 371 #define EXqVexW { OP_EX_VexW, q_mode }
 372 #define XMVex { OP_XMM_Vex, 0 }
 373 #define XMVexW { OP_XMM_VexW, 0 }
 374 #define XMVexI4 { OP_REG_VexI4, x_mode }
 375 #define PCLMUL { PCLMUL_Fixup, 0 }
 376 #define VZERO { VZERO_Fixup, 0 }
 377 #define VCMP { VCMP_Fixup, 0 }
 378
 379 /* Used handle "rep" prefix for string instructions.  */
 380 #define Xbr { REP_Fixup, eSI_reg }
 381 #define Xvr { REP_Fixup, eSI_reg }
 382 #define Ybr { REP_Fixup, eDI_reg }
 383 #define Yvr { REP_Fixup, eDI_reg }
 384 #define Yzr { REP_Fixup, eDI_reg }
 385 #define indirDXr { REP_Fixup, indir_dx_reg }
 386 #define ALr { REP_Fixup, al_reg }
 387 #define eAXr { REP_Fixup, eAX_reg }
 388
 389 #define cond_jump_flag { NULL, cond_jump_mode }
 390 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 391
 392 /* bits in sizeflag */
 393 #define SUFFIX_ALWAYS 4
 394 #define AFLAG 2
 395 #define DFLAG 1
 396
 397 enum
 398 {
 399   /* byte operand */
 400   b_mode = 1,
 401   /* byte operand with operand swapped */
 402   b_swap_mode,
 403   /* operand size depends on prefixes */
 404   v_mode,
 405   /* operand size depends on prefixes with operand swapped */
 406   v_swap_mode,
 407   /* word operand */
 408   w_mode,
 409   /* double word operand  */
 410   d_mode,
 411   /* double word operand with operand swapped */
 412   d_swap_mode,
 413   /* quad word operand */
 414   q_mode,
 415   /* quad word operand with operand swapped */
 416   q_swap_mode,
 417   /* ten-byte operand */
 418   t_mode,
 419   /* 16-byte XMM or 32-byte YMM operand */
 420   x_mode,
 421   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 422   x_swap_mode,
 423   /* 16-byte XMM operand */
 424   xmm_mode,
 425   /* 16-byte XMM or quad word operand */
 426   xmmq_mode,
 427   /* 32-byte YMM or quad word operand */
 428   ymmq_mode,
 429   /* d_mode in 32bit, q_mode in 64bit mode.  */
 430   m_mode,
 431   /* pair of v_mode operands */
 432   a_mode,
 433   cond_jump_mode,
 434   loop_jcxz_mode,
 435   /* operand size depends on REX prefixes.  */
 436   dq_mode,
 437   /* registers like dq_mode, memory like w_mode.  */
 438   dqw_mode,
 439   /* 4- or 6-byte pointer operand */
 440   f_mode,
 441   const_1_mode,
 442   /* v_mode for stack-related opcodes.  */
 443   stack_v_mode,
 444   /* non-quad operand size depends on prefixes */
 445   z_mode,
 446   /* 16-byte operand */
 447   o_mode,
 448   /* registers like dq_mode, memory like b_mode.  */
 449   dqb_mode,
 450   /* registers like dq_mode, memory like d_mode.  */
 451   dqd_mode,
 452   /* normal vex mode */
 453   vex_mode,
 454   /* 128bit vex mode */
 455   vex128_mode,
 456   /* 256bit vex mode */
 457   vex256_mode,
 458   /* operand size depends on the VEX.W bit.  */
 459   vex_w_dq_mode,
 460
 461   es_reg,
 462   cs_reg,
 463   ss_reg,
 464   ds_reg,
 465   fs_reg,
 466   gs_reg,
 467
 468   eAX_reg,
 469   eCX_reg,
 470   eDX_reg,
 471   eBX_reg,
 472   eSP_reg,
 473   eBP_reg,
 474   eSI_reg,
 475   eDI_reg,
 476
 477   al_reg,
 478   cl_reg,
 479   dl_reg,
 480   bl_reg,
 481   ah_reg,
 482   ch_reg,
 483   dh_reg,
 484   bh_reg,
 485
 486   ax_reg,
 487   cx_reg,
 488   dx_reg,
 489   bx_reg,
 490   sp_reg,
 491   bp_reg,
 492   si_reg,
 493   di_reg,
 494
 495   rAX_reg,
 496   rCX_reg,
 497   rDX_reg,
 498   rBX_reg,
 499   rSP_reg,
 500   rBP_reg,
 501   rSI_reg,
 502   rDI_reg,
 503
 504   z_mode_ax_reg,
 505   indir_dx_reg
 506 };
 507
 508 enum
 509 {
 510   FLOATCODE = 1,
 511   USE_REG_TABLE,
 512   USE_MOD_TABLE,
 513   USE_RM_TABLE,
 514   USE_PREFIX_TABLE,
 515   USE_X86_64_TABLE,
 516   USE_3BYTE_TABLE,
 517   USE_VEX_C4_TABLE,
 518   USE_VEX_C5_TABLE,
 519   USE_VEX_LEN_TABLE
 520 };
 521
 522 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 523
 524 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 525 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 526 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 527 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 528 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 529 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 530 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 531 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 532 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 533 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 534
 535 enum
 536 {
 537   REG_80 = 0,
 538   REG_81,
 539   REG_82,
 540   REG_8F,
 541   REG_C0,
 542   REG_C1,
 543   REG_C6,
 544   REG_C7,
 545   REG_D0,
 546   REG_D1,
 547   REG_D2,
 548   REG_D3,
 549   REG_F6,
 550   REG_F7,
 551   REG_FE,
 552   REG_FF,
 553   REG_0F00,
 554   REG_0F01,
 555   REG_0F0D,
 556   REG_0F18,
 557   REG_0F71,
 558   REG_0F72,
 559   REG_0F73,
 560   REG_0FA6,
 561   REG_0FA7,
 562   REG_0FAE,
 563   REG_0FBA,
 564   REG_0FC7,
 565   REG_VEX_71,
 566   REG_VEX_72,
 567   REG_VEX_73,
 568   REG_VEX_AE
 569 };
 570
 571 enum
 572 {
 573   MOD_8D = 0,
 574   MOD_0F01_REG_0,
 575   MOD_0F01_REG_1,
 576   MOD_0F01_REG_2,
 577   MOD_0F01_REG_3,
 578   MOD_0F01_REG_7,
 579   MOD_0F12_PREFIX_0,
 580   MOD_0F13,
 581   MOD_0F16_PREFIX_0,
 582   MOD_0F17,
 583   MOD_0F18_REG_0,
 584   MOD_0F18_REG_1,
 585   MOD_0F18_REG_2,
 586   MOD_0F18_REG_3,
 587   MOD_0F20,
 588   MOD_0F21,
 589   MOD_0F22,
 590   MOD_0F23,
 591   MOD_0F24,
 592   MOD_0F26,
 593   MOD_0F2B_PREFIX_0,
 594   MOD_0F2B_PREFIX_1,
 595   MOD_0F2B_PREFIX_2,
 596   MOD_0F2B_PREFIX_3,
 597   MOD_0F51,
 598   MOD_0F71_REG_2,
 599   MOD_0F71_REG_4,
 600   MOD_0F71_REG_6,
 601   MOD_0F72_REG_2,
 602   MOD_0F72_REG_4,
 603   MOD_0F72_REG_6,
 604   MOD_0F73_REG_2,
 605   MOD_0F73_REG_3,
 606   MOD_0F73_REG_6,
 607   MOD_0F73_REG_7,
 608   MOD_0FAE_REG_0,
 609   MOD_0FAE_REG_1,
 610   MOD_0FAE_REG_2,
 611   MOD_0FAE_REG_3,
 612   MOD_0FAE_REG_4,
 613   MOD_0FAE_REG_5,
 614   MOD_0FAE_REG_6,
 615   MOD_0FAE_REG_7,
 616   MOD_0FB2,
 617   MOD_0FB4,
 618   MOD_0FB5,
 619   MOD_0FC7_REG_6,
 620   MOD_0FC7_REG_7,
 621   MOD_0FD7,
 622   MOD_0FE7_PREFIX_2,
 623   MOD_0FF0_PREFIX_3,
 624   MOD_0F382A_PREFIX_2,
 625   MOD_62_32BIT,
 626   MOD_C4_32BIT,
 627   MOD_C5_32BIT,
 628   MOD_VEX_12_PREFIX_0,
 629   MOD_VEX_13,
 630   MOD_VEX_16_PREFIX_0,
 631   MOD_VEX_17,
 632   MOD_VEX_2B,
 633   MOD_VEX_51,
 634   MOD_VEX_71_REG_2,
 635   MOD_VEX_71_REG_4,
 636   MOD_VEX_71_REG_6,
 637   MOD_VEX_72_REG_2,
 638   MOD_VEX_72_REG_4,
 639   MOD_VEX_72_REG_6,
 640   MOD_VEX_73_REG_2,
 641   MOD_VEX_73_REG_3,
 642   MOD_VEX_73_REG_6,
 643   MOD_VEX_73_REG_7,
 644   MOD_VEX_AE_REG_2,
 645   MOD_VEX_AE_REG_3,
 646   MOD_VEX_D7_PREFIX_2,
 647   MOD_VEX_E7_PREFIX_2,
 648   MOD_VEX_F0_PREFIX_3,
 649   MOD_VEX_3818_PREFIX_2,
 650   MOD_VEX_3819_PREFIX_2,
 651   MOD_VEX_381A_PREFIX_2,
 652   MOD_VEX_382A_PREFIX_2,
 653   MOD_VEX_382C_PREFIX_2,
 654   MOD_VEX_382D_PREFIX_2,
 655   MOD_VEX_382E_PREFIX_2,
 656   MOD_VEX_382F_PREFIX_2
 657 };
 658
 659 enum
 660 {
 661   RM_0F01_REG_0 = 0,
 662   RM_0F01_REG_1,
 663   RM_0F01_REG_2,
 664   RM_0F01_REG_3,
 665   RM_0F01_REG_7,
 666   RM_0FAE_REG_5,
 667   RM_0FAE_REG_6,
 668   RM_0FAE_REG_7
 669 };
 670
 671 enum
 672 {
 673   PREFIX_90 = 0,
 674   PREFIX_0F10,
 675   PREFIX_0F11,
 676   PREFIX_0F12,
 677   PREFIX_0F16,
 678   PREFIX_0F2A,
 679   PREFIX_0F2B,
 680   PREFIX_0F2C,
 681   PREFIX_0F2D,
 682   PREFIX_0F2E,
 683   PREFIX_0F2F,
 684   PREFIX_0F51,
 685   PREFIX_0F52,
 686   PREFIX_0F53,
 687   PREFIX_0F58,
 688   PREFIX_0F59,
 689   PREFIX_0F5A,
 690   PREFIX_0F5B,
 691   PREFIX_0F5C,
 692   PREFIX_0F5D,
 693   PREFIX_0F5E,
 694   PREFIX_0F5F,
 695   PREFIX_0F60,
 696   PREFIX_0F61,
 697   PREFIX_0F62,
 698   PREFIX_0F6C,
 699   PREFIX_0F6D,
 700   PREFIX_0F6F,
 701   PREFIX_0F70,
 702   PREFIX_0F73_REG_3,
 703   PREFIX_0F73_REG_7,
 704   PREFIX_0F78,
 705   PREFIX_0F79,
 706   PREFIX_0F7C,
 707   PREFIX_0F7D,
 708   PREFIX_0F7E,
 709   PREFIX_0F7F,
 710   PREFIX_0FB8,
 711   PREFIX_0FBD,
 712   PREFIX_0FC2,
 713   PREFIX_0FC3,
 714   PREFIX_0FC7_REG_6,
 715   PREFIX_0FD0,
 716   PREFIX_0FD6,
 717   PREFIX_0FE6,
 718   PREFIX_0FE7,
 719   PREFIX_0FF0,
 720   PREFIX_0FF7,
 721   PREFIX_0F3810,
 722   PREFIX_0F3814,
 723   PREFIX_0F3815,
 724   PREFIX_0F3817,
 725   PREFIX_0F3820,
 726   PREFIX_0F3821,
 727   PREFIX_0F3822,
 728   PREFIX_0F3823,
 729   PREFIX_0F3824,
 730   PREFIX_0F3825,
 731   PREFIX_0F3828,
 732   PREFIX_0F3829,
 733   PREFIX_0F382A,
 734   PREFIX_0F382B,
 735   PREFIX_0F3830,
 736   PREFIX_0F3831,
 737   PREFIX_0F3832,
 738   PREFIX_0F3833,
 739   PREFIX_0F3834,
 740   PREFIX_0F3835,
 741   PREFIX_0F3837,
 742   PREFIX_0F3838,
 743   PREFIX_0F3839,
 744   PREFIX_0F383A,
 745   PREFIX_0F383B,
 746   PREFIX_0F383C,
 747   PREFIX_0F383D,
 748   PREFIX_0F383E,
 749   PREFIX_0F383F,
 750   PREFIX_0F3840,
 751   PREFIX_0F3841,
 752   PREFIX_0F3880,
 753   PREFIX_0F3881,
 754   PREFIX_0F38DB,
 755   PREFIX_0F38DC,
 756   PREFIX_0F38DD,
 757   PREFIX_0F38DE,
 758   PREFIX_0F38DF,
 759   PREFIX_0F38F0,
 760   PREFIX_0F38F1,
 761   PREFIX_0F3A08,
 762   PREFIX_0F3A09,
 763   PREFIX_0F3A0A,
 764   PREFIX_0F3A0B,
 765   PREFIX_0F3A0C,
 766   PREFIX_0F3A0D,
 767   PREFIX_0F3A0E,
 768   PREFIX_0F3A14,
 769   PREFIX_0F3A15,
 770   PREFIX_0F3A16,
 771   PREFIX_0F3A17,
 772   PREFIX_0F3A20,
 773   PREFIX_0F3A21,
 774   PREFIX_0F3A22,
 775   PREFIX_0F3A40,
 776   PREFIX_0F3A41,
 777   PREFIX_0F3A42,
 778   PREFIX_0F3A44,
 779   PREFIX_0F3A60,
 780   PREFIX_0F3A61,
 781   PREFIX_0F3A62,
 782   PREFIX_0F3A63,
 783   PREFIX_0F3ADF,
 784   PREFIX_VEX_10,
 785   PREFIX_VEX_11,
 786   PREFIX_VEX_12,
 787   PREFIX_VEX_16,
 788   PREFIX_VEX_2A,
 789   PREFIX_VEX_2C,
 790   PREFIX_VEX_2D,
 791   PREFIX_VEX_2E,
 792   PREFIX_VEX_2F,
 793   PREFIX_VEX_51,
 794   PREFIX_VEX_52,
 795   PREFIX_VEX_53,
 796   PREFIX_VEX_58,
 797   PREFIX_VEX_59,
 798   PREFIX_VEX_5A,
 799   PREFIX_VEX_5B,
 800   PREFIX_VEX_5C,
 801   PREFIX_VEX_5D,
 802   PREFIX_VEX_5E,
 803   PREFIX_VEX_5F,
 804   PREFIX_VEX_60,
 805   PREFIX_VEX_61,
 806   PREFIX_VEX_62,
 807   PREFIX_VEX_63,
 808   PREFIX_VEX_64,
 809   PREFIX_VEX_65,
 810   PREFIX_VEX_66,
 811   PREFIX_VEX_67,
 812   PREFIX_VEX_68,
 813   PREFIX_VEX_69,
 814   PREFIX_VEX_6A,
 815   PREFIX_VEX_6B,
 816   PREFIX_VEX_6C,
 817   PREFIX_VEX_6D,
 818   PREFIX_VEX_6E,
 819   PREFIX_VEX_6F,
 820   PREFIX_VEX_70,
 821   PREFIX_VEX_71_REG_2,
 822   PREFIX_VEX_71_REG_4,
 823   PREFIX_VEX_71_REG_6,
 824   PREFIX_VEX_72_REG_2,
 825   PREFIX_VEX_72_REG_4,
 826   PREFIX_VEX_72_REG_6,
 827   PREFIX_VEX_73_REG_2,
 828   PREFIX_VEX_73_REG_3,
 829   PREFIX_VEX_73_REG_6,
 830   PREFIX_VEX_73_REG_7,
 831   PREFIX_VEX_74,
 832   PREFIX_VEX_75,
 833   PREFIX_VEX_76,
 834   PREFIX_VEX_77,
 835   PREFIX_VEX_7C,
 836   PREFIX_VEX_7D,
 837   PREFIX_VEX_7E,
 838   PREFIX_VEX_7F,
 839   PREFIX_VEX_C2,
 840   PREFIX_VEX_C4,
 841   PREFIX_VEX_C5,
 842   PREFIX_VEX_D0,
 843   PREFIX_VEX_D1,
 844   PREFIX_VEX_D2,
 845   PREFIX_VEX_D3,
 846   PREFIX_VEX_D4,
 847   PREFIX_VEX_D5,
 848   PREFIX_VEX_D6,
 849   PREFIX_VEX_D7,
 850   PREFIX_VEX_D8,
 851   PREFIX_VEX_D9,
 852   PREFIX_VEX_DA,
 853   PREFIX_VEX_DB,
 854   PREFIX_VEX_DC,
 855   PREFIX_VEX_DD,
 856   PREFIX_VEX_DE,
 857   PREFIX_VEX_DF,
 858   PREFIX_VEX_E0,
 859   PREFIX_VEX_E1,
 860   PREFIX_VEX_E2,
 861   PREFIX_VEX_E3,
 862   PREFIX_VEX_E4,
 863   PREFIX_VEX_E5,
 864   PREFIX_VEX_E6,
 865   PREFIX_VEX_E7,
 866   PREFIX_VEX_E8,
 867   PREFIX_VEX_E9,
 868   PREFIX_VEX_EA,
 869   PREFIX_VEX_EB,
 870   PREFIX_VEX_EC,
 871   PREFIX_VEX_ED,
 872   PREFIX_VEX_EE,
 873   PREFIX_VEX_EF,
 874   PREFIX_VEX_F0,
 875   PREFIX_VEX_F1,
 876   PREFIX_VEX_F2,
 877   PREFIX_VEX_F3,
 878   PREFIX_VEX_F4,
 879   PREFIX_VEX_F5,
 880   PREFIX_VEX_F6,
 881   PREFIX_VEX_F7,
 882   PREFIX_VEX_F8,
 883   PREFIX_VEX_F9,
 884   PREFIX_VEX_FA,
 885   PREFIX_VEX_FB,
 886   PREFIX_VEX_FC,
 887   PREFIX_VEX_FD,
 888   PREFIX_VEX_FE,
 889   PREFIX_VEX_3800,
 890   PREFIX_VEX_3801,
 891   PREFIX_VEX_3802,
 892   PREFIX_VEX_3803,
 893   PREFIX_VEX_3804,
 894   PREFIX_VEX_3805,
 895   PREFIX_VEX_3806,
 896   PREFIX_VEX_3807,
 897   PREFIX_VEX_3808,
 898   PREFIX_VEX_3809,
 899   PREFIX_VEX_380A,
 900   PREFIX_VEX_380B,
 901   PREFIX_VEX_380C,
 902   PREFIX_VEX_380D,
 903   PREFIX_VEX_380E,
 904   PREFIX_VEX_380F,
 905   PREFIX_VEX_3817,
 906   PREFIX_VEX_3818,
 907   PREFIX_VEX_3819,
 908   PREFIX_VEX_381A,
 909   PREFIX_VEX_381C,
 910   PREFIX_VEX_381D,
 911   PREFIX_VEX_381E,
 912   PREFIX_VEX_3820,
 913   PREFIX_VEX_3821,
 914   PREFIX_VEX_3822,
 915   PREFIX_VEX_3823,
 916   PREFIX_VEX_3824,
 917   PREFIX_VEX_3825,
 918   PREFIX_VEX_3828,
 919   PREFIX_VEX_3829,
 920   PREFIX_VEX_382A,
 921   PREFIX_VEX_382B,
 922   PREFIX_VEX_382C,
 923   PREFIX_VEX_382D,
 924   PREFIX_VEX_382E,
 925   PREFIX_VEX_382F,
 926   PREFIX_VEX_3830,
 927   PREFIX_VEX_3831,
 928   PREFIX_VEX_3832,
 929   PREFIX_VEX_3833,
 930   PREFIX_VEX_3834,
 931   PREFIX_VEX_3835,
 932   PREFIX_VEX_3837,
 933   PREFIX_VEX_3838,
 934   PREFIX_VEX_3839,
 935   PREFIX_VEX_383A,
 936   PREFIX_VEX_383B,
 937   PREFIX_VEX_383C,
 938   PREFIX_VEX_383D,
 939   PREFIX_VEX_383E,
 940   PREFIX_VEX_383F,
 941   PREFIX_VEX_3840,
 942   PREFIX_VEX_3841,
 943   PREFIX_VEX_3896,
 944   PREFIX_VEX_3897,
 945   PREFIX_VEX_3898,
 946   PREFIX_VEX_3899,
 947   PREFIX_VEX_389A,
 948   PREFIX_VEX_389B,
 949   PREFIX_VEX_389C,
 950   PREFIX_VEX_389D,
 951   PREFIX_VEX_389E,
 952   PREFIX_VEX_389F,
 953   PREFIX_VEX_38A6,
 954   PREFIX_VEX_38A7,
 955   PREFIX_VEX_38A8,
 956   PREFIX_VEX_38A9,
 957   PREFIX_VEX_38AA,
 958   PREFIX_VEX_38AB,
 959   PREFIX_VEX_38AC,
 960   PREFIX_VEX_38AD,
 961   PREFIX_VEX_38AE,
 962   PREFIX_VEX_38AF,
 963   PREFIX_VEX_38B6,
 964   PREFIX_VEX_38B7,
 965   PREFIX_VEX_38B8,
 966   PREFIX_VEX_38B9,
 967   PREFIX_VEX_38BA,
 968   PREFIX_VEX_38BB,
 969   PREFIX_VEX_38BC,
 970   PREFIX_VEX_38BD,
 971   PREFIX_VEX_38BE,
 972   PREFIX_VEX_38BF,
 973   PREFIX_VEX_38DB,
 974   PREFIX_VEX_38DC,
 975   PREFIX_VEX_38DD,
 976   PREFIX_VEX_38DE,
 977   PREFIX_VEX_38DF,
 978   PREFIX_VEX_3A04,
 979   PREFIX_VEX_3A05,
 980   PREFIX_VEX_3A06,
 981   PREFIX_VEX_3A08,
 982   PREFIX_VEX_3A09,
 983   PREFIX_VEX_3A0A,
 984   PREFIX_VEX_3A0B,
 985   PREFIX_VEX_3A0C,
 986   PREFIX_VEX_3A0D,
 987   PREFIX_VEX_3A0E,
 988   PREFIX_VEX_3A0F,
 989   PREFIX_VEX_3A14,
 990   PREFIX_VEX_3A15,
 991   PREFIX_VEX_3A16,
 992   PREFIX_VEX_3A17,
 993   PREFIX_VEX_3A18,
 994   PREFIX_VEX_3A19,
 995   PREFIX_VEX_3A20,
 996   PREFIX_VEX_3A21,
 997   PREFIX_VEX_3A22,
 998   PREFIX_VEX_3A40,
 999   PREFIX_VEX_3A41,
1000   PREFIX_VEX_3A42,
1001   PREFIX_VEX_3A44,
1002   PREFIX_VEX_3A4A,
1003   PREFIX_VEX_3A4B,
1004   PREFIX_VEX_3A4C,
1005   PREFIX_VEX_3A5C,
1006   PREFIX_VEX_3A5D,
1007   PREFIX_VEX_3A5E,
1008   PREFIX_VEX_3A5F,
1009   PREFIX_VEX_3A60,
1010   PREFIX_VEX_3A61,
1011   PREFIX_VEX_3A62,
1012   PREFIX_VEX_3A63,
1013   PREFIX_VEX_3A68,
1014   PREFIX_VEX_3A69,
1015   PREFIX_VEX_3A6A,
1016   PREFIX_VEX_3A6B,
1017   PREFIX_VEX_3A6C,
1018   PREFIX_VEX_3A6D,
1019   PREFIX_VEX_3A6E,
1020   PREFIX_VEX_3A6F,
1021   PREFIX_VEX_3A78,
1022   PREFIX_VEX_3A79,
1023   PREFIX_VEX_3A7A,
1024   PREFIX_VEX_3A7B,
1025   PREFIX_VEX_3A7C,
1026   PREFIX_VEX_3A7D,
1027   PREFIX_VEX_3A7E,
1028   PREFIX_VEX_3A7F,
1029   PREFIX_VEX_3ADF
1030 };
1031
1032 enum
1033 {
1034   X86_64_06 = 0,
1035   X86_64_07,
1036   X86_64_0D,
1037   X86_64_16,
1038   X86_64_17,
1039   X86_64_1E,
1040   X86_64_1F,
1041   X86_64_27,
1042   X86_64_2F,
1043   X86_64_37,
1044   X86_64_3F,
1045   X86_64_60,
1046   X86_64_61,
1047   X86_64_62,
1048   X86_64_63,
1049   X86_64_6D,
1050   X86_64_6F,
1051   X86_64_9A,
1052   X86_64_C4,
1053   X86_64_C5,
1054   X86_64_CE,
1055   X86_64_D4,
1056   X86_64_D5,
1057   X86_64_EA,
1058   X86_64_0F01_REG_0,
1059   X86_64_0F01_REG_1,
1060   X86_64_0F01_REG_2,
1061   X86_64_0F01_REG_3
1062 };
1063
1064 enum
1065 {
1066   THREE_BYTE_0F38 = 0,
1067   THREE_BYTE_0F3A,
1068   THREE_BYTE_0F7A
1069 };
1070
1071 enum
1072 {
1073   VEX_0F = 0,
1074   VEX_0F38,
1075   VEX_0F3A
1076 };
1077
1078 enum
1079 {
1080   VEX_LEN_10_P_1 = 0,
1081   VEX_LEN_10_P_3,
1082   VEX_LEN_11_P_1,
1083   VEX_LEN_11_P_3,
1084   VEX_LEN_12_P_0_M_0,
1085   VEX_LEN_12_P_0_M_1,
1086   VEX_LEN_12_P_2,
1087   VEX_LEN_13_M_0,
1088   VEX_LEN_16_P_0_M_0,
1089   VEX_LEN_16_P_0_M_1,
1090   VEX_LEN_16_P_2,
1091   VEX_LEN_17_M_0,
1092   VEX_LEN_2A_P_1,
1093   VEX_LEN_2A_P_3,
1094   VEX_LEN_2C_P_1,
1095   VEX_LEN_2C_P_3,
1096   VEX_LEN_2D_P_1,
1097   VEX_LEN_2D_P_3,
1098   VEX_LEN_2E_P_0,
1099   VEX_LEN_2E_P_2,
1100   VEX_LEN_2F_P_0,
1101   VEX_LEN_2F_P_2,
1102   VEX_LEN_51_P_1,
1103   VEX_LEN_51_P_3,
1104   VEX_LEN_52_P_1,
1105   VEX_LEN_53_P_1,
1106   VEX_LEN_58_P_1,
1107   VEX_LEN_58_P_3,
1108   VEX_LEN_59_P_1,
1109   VEX_LEN_59_P_3,
1110   VEX_LEN_5A_P_1,
1111   VEX_LEN_5A_P_3,
1112   VEX_LEN_5C_P_1,
1113   VEX_LEN_5C_P_3,
1114   VEX_LEN_5D_P_1,
1115   VEX_LEN_5D_P_3,
1116   VEX_LEN_5E_P_1,
1117   VEX_LEN_5E_P_3,
1118   VEX_LEN_5F_P_1,
1119   VEX_LEN_5F_P_3,
1120   VEX_LEN_60_P_2,
1121   VEX_LEN_61_P_2,
1122   VEX_LEN_62_P_2,
1123   VEX_LEN_63_P_2,
1124   VEX_LEN_64_P_2,
1125   VEX_LEN_65_P_2,
1126   VEX_LEN_66_P_2,
1127   VEX_LEN_67_P_2,
1128   VEX_LEN_68_P_2,
1129   VEX_LEN_69_P_2,
1130   VEX_LEN_6A_P_2,
1131   VEX_LEN_6B_P_2,
1132   VEX_LEN_6C_P_2,
1133   VEX_LEN_6D_P_2,
1134   VEX_LEN_6E_P_2,
1135   VEX_LEN_70_P_1,
1136   VEX_LEN_70_P_2,
1137   VEX_LEN_70_P_3,
1138   VEX_LEN_71_R_2_P_2,
1139   VEX_LEN_71_R_4_P_2,
1140   VEX_LEN_71_R_6_P_2,
1141   VEX_LEN_72_R_2_P_2,
1142   VEX_LEN_72_R_4_P_2,
1143   VEX_LEN_72_R_6_P_2,
1144   VEX_LEN_73_R_2_P_2,
1145   VEX_LEN_73_R_3_P_2,
1146   VEX_LEN_73_R_6_P_2,
1147   VEX_LEN_73_R_7_P_2,
1148   VEX_LEN_74_P_2,
1149   VEX_LEN_75_P_2,
1150   VEX_LEN_76_P_2,
1151   VEX_LEN_7E_P_1,
1152   VEX_LEN_7E_P_2,
1153   VEX_LEN_AE_R_2_M_0,
1154   VEX_LEN_AE_R_3_M_0,
1155   VEX_LEN_C2_P_1,
1156   VEX_LEN_C2_P_3,
1157   VEX_LEN_C4_P_2,
1158   VEX_LEN_C5_P_2,
1159   VEX_LEN_D1_P_2,
1160   VEX_LEN_D2_P_2,
1161   VEX_LEN_D3_P_2,
1162   VEX_LEN_D4_P_2,
1163   VEX_LEN_D5_P_2,
1164   VEX_LEN_D6_P_2,
1165   VEX_LEN_D7_P_2_M_1,
1166   VEX_LEN_D8_P_2,
1167   VEX_LEN_D9_P_2,
1168   VEX_LEN_DA_P_2,
1169   VEX_LEN_DB_P_2,
1170   VEX_LEN_DC_P_2,
1171   VEX_LEN_DD_P_2,
1172   VEX_LEN_DE_P_2,
1173   VEX_LEN_DF_P_2,
1174   VEX_LEN_E0_P_2,
1175   VEX_LEN_E1_P_2,
1176   VEX_LEN_E2_P_2,
1177   VEX_LEN_E3_P_2,
1178   VEX_LEN_E4_P_2,
1179   VEX_LEN_E5_P_2,
1180   VEX_LEN_E8_P_2,
1181   VEX_LEN_E9_P_2,
1182   VEX_LEN_EA_P_2,
1183   VEX_LEN_EB_P_2,
1184   VEX_LEN_EC_P_2,
1185   VEX_LEN_ED_P_2,
1186   VEX_LEN_EE_P_2,
1187   VEX_LEN_EF_P_2,
1188   VEX_LEN_F1_P_2,
1189   VEX_LEN_F2_P_2,
1190   VEX_LEN_F3_P_2,
1191   VEX_LEN_F4_P_2,
1192   VEX_LEN_F5_P_2,
1193   VEX_LEN_F6_P_2,
1194   VEX_LEN_F7_P_2,
1195   VEX_LEN_F8_P_2,
1196   VEX_LEN_F9_P_2,
1197   VEX_LEN_FA_P_2,
1198   VEX_LEN_FB_P_2,
1199   VEX_LEN_FC_P_2,
1200   VEX_LEN_FD_P_2,
1201   VEX_LEN_FE_P_2,
1202   VEX_LEN_3800_P_2,
1203   VEX_LEN_3801_P_2,
1204   VEX_LEN_3802_P_2,
1205   VEX_LEN_3803_P_2,
1206   VEX_LEN_3804_P_2,
1207   VEX_LEN_3805_P_2,
1208   VEX_LEN_3806_P_2,
1209   VEX_LEN_3807_P_2,
1210   VEX_LEN_3808_P_2,
1211   VEX_LEN_3809_P_2,
1212   VEX_LEN_380A_P_2,
1213   VEX_LEN_380B_P_2,
1214   VEX_LEN_3819_P_2_M_0,
1215   VEX_LEN_381A_P_2_M_0,
1216   VEX_LEN_381C_P_2,
1217   VEX_LEN_381D_P_2,
1218   VEX_LEN_381E_P_2,
1219   VEX_LEN_3820_P_2,
1220   VEX_LEN_3821_P_2,
1221   VEX_LEN_3822_P_2,
1222   VEX_LEN_3823_P_2,
1223   VEX_LEN_3824_P_2,
1224   VEX_LEN_3825_P_2,
1225   VEX_LEN_3828_P_2,
1226   VEX_LEN_3829_P_2,
1227   VEX_LEN_382A_P_2_M_0,
1228   VEX_LEN_382B_P_2,
1229   VEX_LEN_3830_P_2,
1230   VEX_LEN_3831_P_2,
1231   VEX_LEN_3832_P_2,
1232   VEX_LEN_3833_P_2,
1233   VEX_LEN_3834_P_2,
1234   VEX_LEN_3835_P_2,
1235   VEX_LEN_3837_P_2,
1236   VEX_LEN_3838_P_2,
1237   VEX_LEN_3839_P_2,
1238   VEX_LEN_383A_P_2,
1239   VEX_LEN_383B_P_2,
1240   VEX_LEN_383C_P_2,
1241   VEX_LEN_383D_P_2,
1242   VEX_LEN_383E_P_2,
1243   VEX_LEN_383F_P_2,
1244   VEX_LEN_3840_P_2,
1245   VEX_LEN_3841_P_2,
1246   VEX_LEN_38DB_P_2,
1247   VEX_LEN_38DC_P_2,
1248   VEX_LEN_38DD_P_2,
1249   VEX_LEN_38DE_P_2,
1250   VEX_LEN_38DF_P_2,
1251   VEX_LEN_3A06_P_2,
1252   VEX_LEN_3A0A_P_2,
1253   VEX_LEN_3A0B_P_2,
1254   VEX_LEN_3A0E_P_2,
1255   VEX_LEN_3A0F_P_2,
1256   VEX_LEN_3A14_P_2,
1257   VEX_LEN_3A15_P_2,
1258   VEX_LEN_3A16_P_2,
1259   VEX_LEN_3A17_P_2,
1260   VEX_LEN_3A18_P_2,
1261   VEX_LEN_3A19_P_2,
1262   VEX_LEN_3A20_P_2,
1263   VEX_LEN_3A21_P_2,
1264   VEX_LEN_3A22_P_2,
1265   VEX_LEN_3A41_P_2,
1266   VEX_LEN_3A42_P_2,
1267   VEX_LEN_3A44_P_2,
1268   VEX_LEN_3A4C_P_2,
1269   VEX_LEN_3A60_P_2,
1270   VEX_LEN_3A61_P_2,
1271   VEX_LEN_3A62_P_2,
1272   VEX_LEN_3A63_P_2,
1273   VEX_LEN_3A6A_P_2,
1274   VEX_LEN_3A6B_P_2,
1275   VEX_LEN_3A6E_P_2,
1276   VEX_LEN_3A6F_P_2,
1277   VEX_LEN_3A7A_P_2,
1278   VEX_LEN_3A7B_P_2,
1279   VEX_LEN_3A7E_P_2,
1280   VEX_LEN_3A7F_P_2,
1281   VEX_LEN_3ADF_P_2
1282 };
1283
1284 typedef void (*op_rtn) (int bytemode, int sizeflag);
1285
1286 struct dis386 {
1287   const char *name;
1288   struct
1289     {
1290       op_rtn rtn;
1291       int bytemode;
1292     } op[MAX_OPERANDS];
1293 };
1294
1295 /* Upper case letters in the instruction names here are macros.
1296    'A' => print 'b' if no register operands or suffix_always is true
1297    'B' => print 'b' if suffix_always is true
1298    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1299           size prefix
1300    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1301           suffix_always is true
1302    'E' => print 'e' if 32-bit form of jcxz
1303    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1304    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1305    'H' => print ",pt" or ",pn" branch hint
1306    'I' => honor following macro letter even in Intel mode (implemented only
1307           for some of the macro letters)
1308    'J' => print 'l'
1309    'K' => print 'd' or 'q' if rex prefix is present.
1310    'L' => print 'l' if suffix_always is true
1311    'M' => print 'r' if intel_mnemonic is false.
1312    'N' => print 'n' if instruction has no wait "prefix"
1313    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1314    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1315           or suffix_always is true.  print 'q' if rex prefix is present.
1316    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1317           is true
1318    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1319    'S' => print 'w', 'l' or 'q' if suffix_always is true
1320    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1321    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1322    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1323    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1324    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1325    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1326           suffix_always is true.
1327    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1328    '!' => change condition from true to false or from false to true.
1329    '%' => add 1 upper case letter to the macro.
1330
1331    2 upper case letter macros:
1332    "XY" => print 'x' or 'y' if no register operands or suffix_always
1333            is true.
1334    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1335    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1336            or suffix_always is true
1337    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1338    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1339    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1340
1341    Many of the above letters print nothing in Intel mode.  See "putop"
1342    for the details.
1343
1344    Braces '{' and '}', and vertical bars '|', indicate alternative
1345    mnemonic strings for AT&T and Intel.  */
1346
1347 static const struct dis386 dis386[] = {
1348   /* 00 */
1349   { "addB",             { Eb, Gb } },
1350   { "addS",             { Ev, Gv } },
1351   { "addB",             { Gb, EbS } },
1352   { "addS",             { Gv, EvS } },
1353   { "addB",             { AL, Ib } },
1354   { "addS",             { eAX, Iv } },
1355   { X86_64_TABLE (X86_64_06) },
1356   { X86_64_TABLE (X86_64_07) },
1357   /* 08 */
1358   { "orB",              { Eb, Gb } },
1359   { "orS",              { Ev, Gv } },
1360   { "orB",              { Gb, EbS } },
1361   { "orS",              { Gv, EvS } },
1362   { "orB",              { AL, Ib } },
1363   { "orS",              { eAX, Iv } },
1364   { X86_64_TABLE (X86_64_0D) },
1365   { "(bad)",            { XX } },       /* 0x0f extended opcode escape */
1366   /* 10 */
1367   { "adcB",             { Eb, Gb } },
1368   { "adcS",             { Ev, Gv } },
1369   { "adcB",             { Gb, EbS } },
1370   { "adcS",             { Gv, EvS } },
1371   { "adcB",             { AL, Ib } },
1372   { "adcS",             { eAX, Iv } },
1373   { X86_64_TABLE (X86_64_16) },
1374   { X86_64_TABLE (X86_64_17) },
1375   /* 18 */
1376   { "sbbB",             { Eb, Gb } },
1377   { "sbbS",             { Ev, Gv } },
1378   { "sbbB",             { Gb, EbS } },
1379   { "sbbS",             { Gv, EvS } },
1380   { "sbbB",             { AL, Ib } },
1381   { "sbbS",             { eAX, Iv } },
1382   { X86_64_TABLE (X86_64_1E) },
1383   { X86_64_TABLE (X86_64_1F) },
1384   /* 20 */
1385   { "andB",             { Eb, Gb } },
1386   { "andS",             { Ev, Gv } },
1387   { "andB",             { Gb, EbS } },
1388   { "andS",             { Gv, EvS } },
1389   { "andB",             { AL, Ib } },
1390   { "andS",             { eAX, Iv } },
1391   { "(bad)",            { XX } },       /* SEG ES prefix */
1392   { X86_64_TABLE (X86_64_27) },
1393   /* 28 */
1394   { "subB",             { Eb, Gb } },
1395   { "subS",             { Ev, Gv } },
1396   { "subB",             { Gb, EbS } },
1397   { "subS",             { Gv, EvS } },
1398   { "subB",             { AL, Ib } },
1399   { "subS",             { eAX, Iv } },
1400   { "(bad)",            { XX } },       /* SEG CS prefix */
1401   { X86_64_TABLE (X86_64_2F) },
1402   /* 30 */
1403   { "xorB",             { Eb, Gb } },
1404   { "xorS",             { Ev, Gv } },
1405   { "xorB",             { Gb, EbS } },
1406   { "xorS",             { Gv, EvS } },
1407   { "xorB",             { AL, Ib } },
1408   { "xorS",             { eAX, Iv } },
1409   { "(bad)",            { XX } },       /* SEG SS prefix */
1410   { X86_64_TABLE (X86_64_37) },
1411   /* 38 */
1412   { "cmpB",             { Eb, Gb } },
1413   { "cmpS",             { Ev, Gv } },
1414   { "cmpB",             { Gb, EbS } },
1415   { "cmpS",             { Gv, EvS } },
1416   { "cmpB",             { AL, Ib } },
1417   { "cmpS",             { eAX, Iv } },
1418   { "(bad)",            { XX } },       /* SEG DS prefix */
1419   { X86_64_TABLE (X86_64_3F) },
1420   /* 40 */
1421   { "inc{S|}",          { RMeAX } },
1422   { "inc{S|}",          { RMeCX } },
1423   { "inc{S|}",          { RMeDX } },
1424   { "inc{S|}",          { RMeBX } },
1425   { "inc{S|}",          { RMeSP } },
1426   { "inc{S|}",          { RMeBP } },
1427   { "inc{S|}",          { RMeSI } },
1428   { "inc{S|}",          { RMeDI } },
1429   /* 48 */
1430   { "dec{S|}",          { RMeAX } },
1431   { "dec{S|}",          { RMeCX } },
1432   { "dec{S|}",          { RMeDX } },
1433   { "dec{S|}",          { RMeBX } },
1434   { "dec{S|}",          { RMeSP } },
1435   { "dec{S|}",          { RMeBP } },
1436   { "dec{S|}",          { RMeSI } },
1437   { "dec{S|}",          { RMeDI } },
1438   /* 50 */
1439   { "pushV",            { RMrAX } },
1440   { "pushV",            { RMrCX } },
1441   { "pushV",            { RMrDX } },
1442   { "pushV",            { RMrBX } },
1443   { "pushV",            { RMrSP } },
1444   { "pushV",            { RMrBP } },
1445   { "pushV",            { RMrSI } },
1446   { "pushV",            { RMrDI } },
1447   /* 58 */
1448   { "popV",             { RMrAX } },
1449   { "popV",             { RMrCX } },
1450   { "popV",             { RMrDX } },
1451   { "popV",             { RMrBX } },
1452   { "popV",             { RMrSP } },
1453   { "popV",             { RMrBP } },
1454   { "popV",             { RMrSI } },
1455   { "popV",             { RMrDI } },
1456   /* 60 */
1457   { X86_64_TABLE (X86_64_60) },
1458   { X86_64_TABLE (X86_64_61) },
1459   { X86_64_TABLE (X86_64_62) },
1460   { X86_64_TABLE (X86_64_63) },
1461   { "(bad)",            { XX } },       /* seg fs */
1462   { "(bad)",            { XX } },       /* seg gs */
1463   { "(bad)",            { XX } },       /* op size prefix */
1464   { "(bad)",            { XX } },       /* adr size prefix */
1465   /* 68 */
1466   { "pushT",            { Iq } },
1467   { "imulS",            { Gv, Ev, Iv } },
1468   { "pushT",            { sIb } },
1469   { "imulS",            { Gv, Ev, sIb } },
1470   { "ins{b|}",          { Ybr, indirDX } },
1471   { X86_64_TABLE (X86_64_6D) },
1472   { "outs{b|}",         { indirDXr, Xb } },
1473   { X86_64_TABLE (X86_64_6F) },
1474   /* 70 */
1475   { "joH",              { Jb, XX, cond_jump_flag } },
1476   { "jnoH",             { Jb, XX, cond_jump_flag } },
1477   { "jbH",              { Jb, XX, cond_jump_flag } },
1478   { "jaeH",             { Jb, XX, cond_jump_flag } },
1479   { "jeH",              { Jb, XX, cond_jump_flag } },
1480   { "jneH",             { Jb, XX, cond_jump_flag } },
1481   { "jbeH",             { Jb, XX, cond_jump_flag } },
1482   { "jaH",              { Jb, XX, cond_jump_flag } },
1483   /* 78 */
1484   { "jsH",              { Jb, XX, cond_jump_flag } },
1485   { "jnsH",             { Jb, XX, cond_jump_flag } },
1486   { "jpH",              { Jb, XX, cond_jump_flag } },
1487   { "jnpH",             { Jb, XX, cond_jump_flag } },
1488   { "jlH",              { Jb, XX, cond_jump_flag } },
1489   { "jgeH",             { Jb, XX, cond_jump_flag } },
1490   { "jleH",             { Jb, XX, cond_jump_flag } },
1491   { "jgH",              { Jb, XX, cond_jump_flag } },
1492   /* 80 */
1493   { REG_TABLE (REG_80) },
1494   { REG_TABLE (REG_81) },
1495   { "(bad)",            { XX } },
1496   { REG_TABLE (REG_82) },
1497   { "testB",            { Eb, Gb } },
1498   { "testS",            { Ev, Gv } },
1499   { "xchgB",            { Eb, Gb } },
1500   { "xchgS",            { Ev, Gv } },
1501   /* 88 */
1502   { "movB",             { Eb, Gb } },
1503   { "movS",             { Ev, Gv } },
1504   { "movB",             { Gb, EbS } },
1505   { "movS",             { Gv, EvS } },
1506   { "movD",             { Sv, Sw } },
1507   { MOD_TABLE (MOD_8D) },
1508   { "movD",             { Sw, Sv } },
1509   { REG_TABLE (REG_8F) },
1510   /* 90 */
1511   { PREFIX_TABLE (PREFIX_90) },
1512   { "xchgS",            { RMeCX, eAX } },
1513   { "xchgS",            { RMeDX, eAX } },
1514   { "xchgS",            { RMeBX, eAX } },
1515   { "xchgS",            { RMeSP, eAX } },
1516   { "xchgS",            { RMeBP, eAX } },
1517   { "xchgS",            { RMeSI, eAX } },
1518   { "xchgS",            { RMeDI, eAX } },
1519   /* 98 */
1520   { "cW{t|}R",          { XX } },
1521   { "cR{t|}O",          { XX } },
1522   { X86_64_TABLE (X86_64_9A) },
1523   { "(bad)",            { XX } },       /* fwait */
1524   { "pushfT",           { XX } },
1525   { "popfT",            { XX } },
1526   { "sahf",             { XX } },
1527   { "lahf",             { XX } },
1528   /* a0 */
1529   { "mov%LB",           { AL, Ob } },
1530   { "mov%LS",           { eAX, Ov } },
1531   { "mov%LB",           { Ob, AL } },
1532   { "mov%LS",           { Ov, eAX } },
1533   { "movs{b|}",         { Ybr, Xb } },
1534   { "movs{R|}",         { Yvr, Xv } },
1535   { "cmps{b|}",         { Xb, Yb } },
1536   { "cmps{R|}",         { Xv, Yv } },
1537   /* a8 */
1538   { "testB",            { AL, Ib } },
1539   { "testS",            { eAX, Iv } },
1540   { "stosB",            { Ybr, AL } },
1541   { "stosS",            { Yvr, eAX } },
1542   { "lodsB",            { ALr, Xb } },
1543   { "lodsS",            { eAXr, Xv } },
1544   { "scasB",            { AL, Yb } },
1545   { "scasS",            { eAX, Yv } },
1546   /* b0 */
1547   { "movB",             { RMAL, Ib } },
1548   { "movB",             { RMCL, Ib } },
1549   { "movB",             { RMDL, Ib } },
1550   { "movB",             { RMBL, Ib } },
1551   { "movB",             { RMAH, Ib } },
1552   { "movB",             { RMCH, Ib } },
1553   { "movB",             { RMDH, Ib } },
1554   { "movB",             { RMBH, Ib } },
1555   /* b8 */
1556   { "mov%LV",           { RMeAX, Iv64 } },
1557   { "mov%LV",           { RMeCX, Iv64 } },
1558   { "mov%LV",           { RMeDX, Iv64 } },
1559   { "mov%LV",           { RMeBX, Iv64 } },
1560   { "mov%LV",           { RMeSP, Iv64 } },
1561   { "mov%LV",           { RMeBP, Iv64 } },
1562   { "mov%LV",           { RMeSI, Iv64 } },
1563   { "mov%LV",           { RMeDI, Iv64 } },
1564   /* c0 */
1565   { REG_TABLE (REG_C0) },
1566   { REG_TABLE (REG_C1) },
1567   { "retT",             { Iw } },
1568   { "retT",             { XX } },
1569   { X86_64_TABLE (X86_64_C4) },
1570   { X86_64_TABLE (X86_64_C5) },
1571   { REG_TABLE (REG_C6) },
1572   { REG_TABLE (REG_C7) },
1573   /* c8 */
1574   { "enterT",           { Iw, Ib } },
1575   { "leaveT",           { XX } },
1576   { "Jret{|f}P",        { Iw } },
1577   { "Jret{|f}P",        { XX } },
1578   { "int3",             { XX } },
1579   { "int",              { Ib } },
1580   { X86_64_TABLE (X86_64_CE) },
1581   { "iretP",            { XX } },
1582   /* d0 */
1583   { REG_TABLE (REG_D0) },
1584   { REG_TABLE (REG_D1) },
1585   { REG_TABLE (REG_D2) },
1586   { REG_TABLE (REG_D3) },
1587   { X86_64_TABLE (X86_64_D4) },
1588   { X86_64_TABLE (X86_64_D5) },
1589   { "(bad)",            { XX } },
1590   { "xlat",             { DSBX } },
1591   /* d8 */
1592   { FLOAT },
1593   { FLOAT },
1594   { FLOAT },
1595   { FLOAT },
1596   { FLOAT },
1597   { FLOAT },
1598   { FLOAT },
1599   { FLOAT },
1600   /* e0 */
1601   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1602   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1603   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1604   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1605   { "inB",              { AL, Ib } },
1606   { "inG",              { zAX, Ib } },
1607   { "outB",             { Ib, AL } },
1608   { "outG",             { Ib, zAX } },
1609   /* e8 */
1610   { "callT",            { Jv } },
1611   { "jmpT",             { Jv } },
1612   { X86_64_TABLE (X86_64_EA) },
1613   { "jmp",              { Jb } },
1614   { "inB",              { AL, indirDX } },
1615   { "inG",              { zAX, indirDX } },
1616   { "outB",             { indirDX, AL } },
1617   { "outG",             { indirDX, zAX } },
1618   /* f0 */
1619   { "(bad)",            { XX } },       /* lock prefix */
1620   { "icebp",            { XX } },
1621   { "(bad)",            { XX } },       /* repne */
1622   { "(bad)",            { XX } },       /* repz */
1623   { "hlt",              { XX } },
1624   { "cmc",              { XX } },
1625   { REG_TABLE (REG_F6) },
1626   { REG_TABLE (REG_F7) },
1627   /* f8 */
1628   { "clc",              { XX } },
1629   { "stc",              { XX } },
1630   { "cli",              { XX } },
1631   { "sti",              { XX } },
1632   { "cld",              { XX } },
1633   { "std",              { XX } },
1634   { REG_TABLE (REG_FE) },
1635   { REG_TABLE (REG_FF) },
1636 };
1637
1638 static const struct dis386 dis386_twobyte[] = {
1639   /* 00 */
1640   { REG_TABLE (REG_0F00 ) },
1641   { REG_TABLE (REG_0F01 ) },
1642   { "larS",             { Gv, Ew } },
1643   { "lslS",             { Gv, Ew } },
1644   { "(bad)",            { XX } },
1645   { "syscall",          { XX } },
1646   { "clts",             { XX } },
1647   { "sysretP",          { XX } },
1648   /* 08 */
1649   { "invd",             { XX } },
1650   { "wbinvd",           { XX } },
1651   { "(bad)",            { XX } },
1652   { "ud2a",             { XX } },
1653   { "(bad)",            { XX } },
1654   { REG_TABLE (REG_0F0D) },
1655   { "femms",            { XX } },
1656   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1657   /* 10 */
1658   { PREFIX_TABLE (PREFIX_0F10) },
1659   { PREFIX_TABLE (PREFIX_0F11) },
1660   { PREFIX_TABLE (PREFIX_0F12) },
1661   { MOD_TABLE (MOD_0F13) },
1662   { "unpcklpX",         { XM, EXx } },
1663   { "unpckhpX",         { XM, EXx } },
1664   { PREFIX_TABLE (PREFIX_0F16) },
1665   { MOD_TABLE (MOD_0F17) },
1666   /* 18 */
1667   { REG_TABLE (REG_0F18) },
1668   { "nopQ",             { Ev } },
1669   { "nopQ",             { Ev } },
1670   { "nopQ",             { Ev } },
1671   { "nopQ",             { Ev } },
1672   { "nopQ",             { Ev } },
1673   { "nopQ",             { Ev } },
1674   { "nopQ",             { Ev } },
1675   /* 20 */
1676   { MOD_TABLE (MOD_0F20) },
1677   { MOD_TABLE (MOD_0F21) },
1678   { MOD_TABLE (MOD_0F22) },
1679   { MOD_TABLE (MOD_0F23) },
1680   { MOD_TABLE (MOD_0F24) },
1681   { "(bad)",            { XX } },
1682   { MOD_TABLE (MOD_0F26) },
1683   { "(bad)",            { XX } },
1684   /* 28 */
1685   { "movapX",           { XM, EXx } },
1686   { "movapX",           { EXxS, XM } },
1687   { PREFIX_TABLE (PREFIX_0F2A) },
1688   { PREFIX_TABLE (PREFIX_0F2B) },
1689   { PREFIX_TABLE (PREFIX_0F2C) },
1690   { PREFIX_TABLE (PREFIX_0F2D) },
1691   { PREFIX_TABLE (PREFIX_0F2E) },
1692   { PREFIX_TABLE (PREFIX_0F2F) },
1693   /* 30 */
1694   { "wrmsr",            { XX } },
1695   { "rdtsc",            { XX } },
1696   { "rdmsr",            { XX } },
1697   { "rdpmc",            { XX } },
1698   { "sysenter",         { XX } },
1699   { "sysexit",          { XX } },
1700   { "(bad)",            { XX } },
1701   { "getsec",           { XX } },
1702   /* 38 */
1703   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1704   { "(bad)",            { XX } },
1705   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1706   { "(bad)",            { XX } },
1707   { "(bad)",            { XX } },
1708   { "(bad)",            { XX } },
1709   { "(bad)",            { XX } },
1710   { "(bad)",            { XX } },
1711   /* 40 */
1712   { "cmovoS",           { Gv, Ev } },
1713   { "cmovnoS",          { Gv, Ev } },
1714   { "cmovbS",           { Gv, Ev } },
1715   { "cmovaeS",          { Gv, Ev } },
1716   { "cmoveS",           { Gv, Ev } },
1717   { "cmovneS",          { Gv, Ev } },
1718   { "cmovbeS",          { Gv, Ev } },
1719   { "cmovaS",           { Gv, Ev } },
1720   /* 48 */
1721   { "cmovsS",           { Gv, Ev } },
1722   { "cmovnsS",          { Gv, Ev } },
1723   { "cmovpS",           { Gv, Ev } },
1724   { "cmovnpS",          { Gv, Ev } },
1725   { "cmovlS",           { Gv, Ev } },
1726   { "cmovgeS",          { Gv, Ev } },
1727   { "cmovleS",          { Gv, Ev } },
1728   { "cmovgS",           { Gv, Ev } },
1729   /* 50 */
1730   { MOD_TABLE (MOD_0F51) },
1731   { PREFIX_TABLE (PREFIX_0F51) },
1732   { PREFIX_TABLE (PREFIX_0F52) },
1733   { PREFIX_TABLE (PREFIX_0F53) },
1734   { "andpX",            { XM, EXx } },
1735   { "andnpX",           { XM, EXx } },
1736   { "orpX",             { XM, EXx } },
1737   { "xorpX",            { XM, EXx } },
1738   /* 58 */
1739   { PREFIX_TABLE (PREFIX_0F58) },
1740   { PREFIX_TABLE (PREFIX_0F59) },
1741   { PREFIX_TABLE (PREFIX_0F5A) },
1742   { PREFIX_TABLE (PREFIX_0F5B) },
1743   { PREFIX_TABLE (PREFIX_0F5C) },
1744   { PREFIX_TABLE (PREFIX_0F5D) },
1745   { PREFIX_TABLE (PREFIX_0F5E) },
1746   { PREFIX_TABLE (PREFIX_0F5F) },
1747   /* 60 */
1748   { PREFIX_TABLE (PREFIX_0F60) },
1749   { PREFIX_TABLE (PREFIX_0F61) },
1750   { PREFIX_TABLE (PREFIX_0F62) },
1751   { "packsswb",         { MX, EM } },
1752   { "pcmpgtb",          { MX, EM } },
1753   { "pcmpgtw",          { MX, EM } },
1754   { "pcmpgtd",          { MX, EM } },
1755   { "packuswb",         { MX, EM } },
1756   /* 68 */
1757   { "punpckhbw",        { MX, EM } },
1758   { "punpckhwd",        { MX, EM } },
1759   { "punpckhdq",        { MX, EM } },
1760   { "packssdw",         { MX, EM } },
1761   { PREFIX_TABLE (PREFIX_0F6C) },
1762   { PREFIX_TABLE (PREFIX_0F6D) },
1763   { "movK",             { MX, Edq } },
1764   { PREFIX_TABLE (PREFIX_0F6F) },
1765   /* 70 */
1766   { PREFIX_TABLE (PREFIX_0F70) },
1767   { REG_TABLE (REG_0F71) },
1768   { REG_TABLE (REG_0F72) },
1769   { REG_TABLE (REG_0F73) },
1770   { "pcmpeqb",          { MX, EM } },
1771   { "pcmpeqw",          { MX, EM } },
1772   { "pcmpeqd",          { MX, EM } },
1773   { "emms",             { XX } },
1774   /* 78 */
1775   { PREFIX_TABLE (PREFIX_0F78) },
1776   { PREFIX_TABLE (PREFIX_0F79) },
1777   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1778   { "(bad)",            { XX } },
1779   { PREFIX_TABLE (PREFIX_0F7C) },
1780   { PREFIX_TABLE (PREFIX_0F7D) },
1781   { PREFIX_TABLE (PREFIX_0F7E) },
1782   { PREFIX_TABLE (PREFIX_0F7F) },
1783   /* 80 */
1784   { "joH",              { Jv, XX, cond_jump_flag } },
1785   { "jnoH",             { Jv, XX, cond_jump_flag } },
1786   { "jbH",              { Jv, XX, cond_jump_flag } },
1787   { "jaeH",             { Jv, XX, cond_jump_flag } },
1788   { "jeH",              { Jv, XX, cond_jump_flag } },
1789   { "jneH",             { Jv, XX, cond_jump_flag } },
1790   { "jbeH",             { Jv, XX, cond_jump_flag } },
1791   { "jaH",              { Jv, XX, cond_jump_flag } },
1792   /* 88 */
1793   { "jsH",              { Jv, XX, cond_jump_flag } },
1794   { "jnsH",             { Jv, XX, cond_jump_flag } },
1795   { "jpH",              { Jv, XX, cond_jump_flag } },
1796   { "jnpH",             { Jv, XX, cond_jump_flag } },
1797   { "jlH",              { Jv, XX, cond_jump_flag } },
1798   { "jgeH",             { Jv, XX, cond_jump_flag } },
1799   { "jleH",             { Jv, XX, cond_jump_flag } },
1800   { "jgH",              { Jv, XX, cond_jump_flag } },
1801   /* 90 */
1802   { "seto",             { Eb } },
1803   { "setno",            { Eb } },
1804   { "setb",             { Eb } },
1805   { "setae",            { Eb } },
1806   { "sete",             { Eb } },
1807   { "setne",            { Eb } },
1808   { "setbe",            { Eb } },
1809   { "seta",             { Eb } },
1810   /* 98 */
1811   { "sets",             { Eb } },
1812   { "setns",            { Eb } },
1813   { "setp",             { Eb } },
1814   { "setnp",            { Eb } },
1815   { "setl",             { Eb } },
1816   { "setge",            { Eb } },
1817   { "setle",            { Eb } },
1818   { "setg",             { Eb } },
1819   /* a0 */
1820   { "pushT",            { fs } },
1821   { "popT",             { fs } },
1822   { "cpuid",            { XX } },
1823   { "btS",              { Ev, Gv } },
1824   { "shldS",            { Ev, Gv, Ib } },
1825   { "shldS",            { Ev, Gv, CL } },
1826   { REG_TABLE (REG_0FA6) },
1827   { REG_TABLE (REG_0FA7) },
1828   /* a8 */
1829   { "pushT",            { gs } },
1830   { "popT",             { gs } },
1831   { "rsm",              { XX } },
1832   { "btsS",             { Ev, Gv } },
1833   { "shrdS",            { Ev, Gv, Ib } },
1834   { "shrdS",            { Ev, Gv, CL } },
1835   { REG_TABLE (REG_0FAE) },
1836   { "imulS",            { Gv, Ev } },
1837   /* b0 */
1838   { "cmpxchgB",         { Eb, Gb } },
1839   { "cmpxchgS",         { Ev, Gv } },
1840   { MOD_TABLE (MOD_0FB2) },
1841   { "btrS",             { Ev, Gv } },
1842   { MOD_TABLE (MOD_0FB4) },
1843   { MOD_TABLE (MOD_0FB5) },
1844   { "movz{bR|x}",       { Gv, Eb } },
1845   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
1846   /* b8 */
1847   { PREFIX_TABLE (PREFIX_0FB8) },
1848   { "ud2b",             { XX } },
1849   { REG_TABLE (REG_0FBA) },
1850   { "btcS",             { Ev, Gv } },
1851   { "bsfS",             { Gv, Ev } },
1852   { PREFIX_TABLE (PREFIX_0FBD) },
1853   { "movs{bR|x}",       { Gv, Eb } },
1854   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
1855   /* c0 */
1856   { "xaddB",            { Eb, Gb } },
1857   { "xaddS",            { Ev, Gv } },
1858   { PREFIX_TABLE (PREFIX_0FC2) },
1859   { PREFIX_TABLE (PREFIX_0FC3) },
1860   { "pinsrw",           { MX, Edqw, Ib } },
1861   { "pextrw",           { Gdq, MS, Ib } },
1862   { "shufpX",           { XM, EXx, Ib } },
1863   { REG_TABLE (REG_0FC7) },
1864   /* c8 */
1865   { "bswap",            { RMeAX } },
1866   { "bswap",            { RMeCX } },
1867   { "bswap",            { RMeDX } },
1868   { "bswap",            { RMeBX } },
1869   { "bswap",            { RMeSP } },
1870   { "bswap",            { RMeBP } },
1871   { "bswap",            { RMeSI } },
1872   { "bswap",            { RMeDI } },
1873   /* d0 */
1874   { PREFIX_TABLE (PREFIX_0FD0) },
1875   { "psrlw",            { MX, EM } },
1876   { "psrld",            { MX, EM } },
1877   { "psrlq",            { MX, EM } },
1878   { "paddq",            { MX, EM } },
1879   { "pmullw",           { MX, EM } },
1880   { PREFIX_TABLE (PREFIX_0FD6) },
1881   { MOD_TABLE (MOD_0FD7) },
1882   /* d8 */
1883   { "psubusb",          { MX, EM } },
1884   { "psubusw",          { MX, EM } },
1885   { "pminub",           { MX, EM } },
1886   { "pand",             { MX, EM } },
1887   { "paddusb",          { MX, EM } },
1888   { "paddusw",          { MX, EM } },
1889   { "pmaxub",           { MX, EM } },
1890   { "pandn",            { MX, EM } },
1891   /* e0 */
1892   { "pavgb",            { MX, EM } },
1893   { "psraw",            { MX, EM } },
1894   { "psrad",            { MX, EM } },
1895   { "pavgw",            { MX, EM } },
1896   { "pmulhuw",          { MX, EM } },
1897   { "pmulhw",           { MX, EM } },
1898   { PREFIX_TABLE (PREFIX_0FE6) },
1899   { PREFIX_TABLE (PREFIX_0FE7) },
1900   /* e8 */
1901   { "psubsb",           { MX, EM } },
1902   { "psubsw",           { MX, EM } },
1903   { "pminsw",           { MX, EM } },
1904   { "por",              { MX, EM } },
1905   { "paddsb",           { MX, EM } },
1906   { "paddsw",           { MX, EM } },
1907   { "pmaxsw",           { MX, EM } },
1908   { "pxor",             { MX, EM } },
1909   /* f0 */
1910   { PREFIX_TABLE (PREFIX_0FF0) },
1911   { "psllw",            { MX, EM } },
1912   { "pslld",            { MX, EM } },
1913   { "psllq",            { MX, EM } },
1914   { "pmuludq",          { MX, EM } },
1915   { "pmaddwd",          { MX, EM } },
1916   { "psadbw",           { MX, EM } },
1917   { PREFIX_TABLE (PREFIX_0FF7) },
1918   /* f8 */
1919   { "psubb",            { MX, EM } },
1920   { "psubw",            { MX, EM } },
1921   { "psubd",            { MX, EM } },
1922   { "psubq",            { MX, EM } },
1923   { "paddb",            { MX, EM } },
1924   { "paddw",            { MX, EM } },
1925   { "paddd",            { MX, EM } },
1926   { "(bad)",            { XX } },
1927 };
1928
1929 static const unsigned char onebyte_has_modrm[256] = {
1930   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1931   /*       -------------------------------        */
1932   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1933   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1934   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1935   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1936   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1937   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1938   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1939   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1940   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1941   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1942   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1943   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1944   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1945   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1946   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1947   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
1948   /*       -------------------------------        */
1949   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1950 };
1951
1952 static const unsigned char twobyte_has_modrm[256] = {
1953   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1954   /*       -------------------------------        */
1955   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1956   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1957   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1958   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1959   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1960   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1961   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1962   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1963   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1964   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1965   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1966   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1967   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1968   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1969   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1970   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
1971   /*       -------------------------------        */
1972   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1973 };
1974
1975 static char obuf[100];
1976 static char *obufp;
1977 static char *mnemonicendp;
1978 static char scratchbuf[100];
1979 static unsigned char *start_codep;
1980 static unsigned char *insn_codep;
1981 static unsigned char *codep;
1982 static const char *lock_prefix;
1983 static const char *data_prefix;
1984 static const char *addr_prefix;
1985 static const char *repz_prefix;
1986 static const char *repnz_prefix;
1987 static disassemble_info *the_info;
1988 static struct
1989   {
1990     int mod;
1991     int reg;
1992     int rm;
1993   }
1994 modrm;
1995 static unsigned char need_modrm;
1996 static struct
1997   {
1998     int register_specifier;
1999     int length;
2000     int prefix;
2001     int w;
2002   }
2003 vex;
2004 static unsigned char need_vex;
2005 static unsigned char need_vex_reg;
2006 static unsigned char vex_w_done;
2007
2008 struct op
2009   {
2010     const char *name;
2011     unsigned int len;
2012   };
2013
2014 /* If we are accessing mod/rm/reg without need_modrm set, then the
2015    values are stale.  Hitting this abort likely indicates that you
2016    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2017 #define MODRM_CHECK  if (!need_modrm) abort ()
2018
2019 static const char **names64;
2020 static const char **names32;
2021 static const char **names16;
2022 static const char **names8;
2023 static const char **names8rex;
2024 static const char **names_seg;
2025 static const char *index64;
2026 static const char *index32;
2027 static const char **index16;
2028
2029 static const char *intel_names64[] = {
2030   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2031   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2032 };
2033 static const char *intel_names32[] = {
2034   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2035   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2036 };
2037 static const char *intel_names16[] = {
2038   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2039   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2040 };
2041 static const char *intel_names8[] = {
2042   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2043 };
2044 static const char *intel_names8rex[] = {
2045   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2046   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2047 };
2048 static const char *intel_names_seg[] = {
2049   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2050 };
2051 static const char *intel_index64 = "riz";
2052 static const char *intel_index32 = "eiz";
2053 static const char *intel_index16[] = {
2054   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2055 };
2056
2057 static const char *att_names64[] = {
2058   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2059   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2060 };
2061 static const char *att_names32[] = {
2062   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2063   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2064 };
2065 static const char *att_names16[] = {
2066   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2067   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2068 };
2069 static const char *att_names8[] = {
2070   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2071 };
2072 static const char *att_names8rex[] = {
2073   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2074   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2075 };
2076 static const char *att_names_seg[] = {
2077   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2078 };
2079 static const char *att_index64 = "%riz";
2080 static const char *att_index32 = "%eiz";
2081 static const char *att_index16[] = {
2082   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2083 };
2084
2085 static const struct dis386 reg_table[][8] = {
2086   /* REG_80 */
2087   {
2088     { "addA",   { Eb, Ib } },
2089     { "orA",    { Eb, Ib } },
2090     { "adcA",   { Eb, Ib } },
2091     { "sbbA",   { Eb, Ib } },
2092     { "andA",   { Eb, Ib } },
2093     { "subA",   { Eb, Ib } },
2094     { "xorA",   { Eb, Ib } },
2095     { "cmpA",   { Eb, Ib } },
2096   },
2097   /* REG_81 */
2098   {
2099     { "addQ",   { Ev, Iv } },
2100     { "orQ",    { Ev, Iv } },
2101     { "adcQ",   { Ev, Iv } },
2102     { "sbbQ",   { Ev, Iv } },
2103     { "andQ",   { Ev, Iv } },
2104     { "subQ",   { Ev, Iv } },
2105     { "xorQ",   { Ev, Iv } },
2106     { "cmpQ",   { Ev, Iv } },
2107   },
2108   /* REG_82 */
2109   {
2110     { "addQ",   { Ev, sIb } },
2111     { "orQ",    { Ev, sIb } },
2112     { "adcQ",   { Ev, sIb } },
2113     { "sbbQ",   { Ev, sIb } },
2114     { "andQ",   { Ev, sIb } },
2115     { "subQ",   { Ev, sIb } },
2116     { "xorQ",   { Ev, sIb } },
2117     { "cmpQ",   { Ev, sIb } },
2118   },
2119   /* REG_8F */
2120   {
2121     { "popU",   { stackEv } },
2122     { "(bad)",  { XX } },
2123     { "(bad)",  { XX } },
2124     { "(bad)",  { XX } },
2125     { "(bad)",  { XX } },
2126     { "(bad)",  { XX } },
2127     { "(bad)",  { XX } },
2128     { "(bad)",  { XX } },
2129   },
2130   /* REG_C0 */
2131   {
2132     { "rolA",   { Eb, Ib } },
2133     { "rorA",   { Eb, Ib } },
2134     { "rclA",   { Eb, Ib } },
2135     { "rcrA",   { Eb, Ib } },
2136     { "shlA",   { Eb, Ib } },
2137     { "shrA",   { Eb, Ib } },
2138     { "(bad)",  { XX } },
2139     { "sarA",   { Eb, Ib } },
2140   },
2141   /* REG_C1 */
2142   {
2143     { "rolQ",   { Ev, Ib } },
2144     { "rorQ",   { Ev, Ib } },
2145     { "rclQ",   { Ev, Ib } },
2146     { "rcrQ",   { Ev, Ib } },
2147     { "shlQ",   { Ev, Ib } },
2148     { "shrQ",   { Ev, Ib } },
2149     { "(bad)",  { XX } },
2150     { "sarQ",   { Ev, Ib } },
2151   },
2152   /* REG_C6 */
2153   {
2154     { "movA",   { Eb, Ib } },
2155     { "(bad)",  { XX } },
2156     { "(bad)",  { XX } },
2157     { "(bad)",  { XX } },
2158     { "(bad)",  { XX } },
2159     { "(bad)",  { XX } },
2160     { "(bad)",  { XX } },
2161     { "(bad)",  { XX } },
2162   },
2163   /* REG_C7 */
2164   {
2165     { "movQ",   { Ev, Iv } },
2166     { "(bad)",  { XX } },
2167     { "(bad)",  { XX } },
2168     { "(bad)",  { XX } },
2169     { "(bad)",  { XX } },
2170     { "(bad)",  { XX } },
2171     { "(bad)",  { XX } },
2172     { "(bad)",  { XX } },
2173   },
2174   /* REG_D0 */
2175   {
2176     { "rolA",   { Eb, I1 } },
2177     { "rorA",   { Eb, I1 } },
2178     { "rclA",   { Eb, I1 } },
2179     { "rcrA",   { Eb, I1 } },
2180     { "shlA",   { Eb, I1 } },
2181     { "shrA",   { Eb, I1 } },
2182     { "(bad)",  { XX } },
2183     { "sarA",   { Eb, I1 } },
2184   },
2185   /* REG_D1 */
2186   {
2187     { "rolQ",   { Ev, I1 } },
2188     { "rorQ",   { Ev, I1 } },
2189     { "rclQ",   { Ev, I1 } },
2190     { "rcrQ",   { Ev, I1 } },
2191     { "shlQ",   { Ev, I1 } },
2192     { "shrQ",   { Ev, I1 } },
2193     { "(bad)",  { XX } },
2194     { "sarQ",   { Ev, I1 } },
2195   },
2196   /* REG_D2 */
2197   {
2198     { "rolA",   { Eb, CL } },
2199     { "rorA",   { Eb, CL } },
2200     { "rclA",   { Eb, CL } },
2201     { "rcrA",   { Eb, CL } },
2202     { "shlA",   { Eb, CL } },
2203     { "shrA",   { Eb, CL } },
2204     { "(bad)",  { XX } },
2205     { "sarA",   { Eb, CL } },
2206   },
2207   /* REG_D3 */
2208   {
2209     { "rolQ",   { Ev, CL } },
2210     { "rorQ",   { Ev, CL } },
2211     { "rclQ",   { Ev, CL } },
2212     { "rcrQ",   { Ev, CL } },
2213     { "shlQ",   { Ev, CL } },
2214     { "shrQ",   { Ev, CL } },
2215     { "(bad)",  { XX } },
2216     { "sarQ",   { Ev, CL } },
2217   },
2218   /* REG_F6 */
2219   {
2220     { "testA",  { Eb, Ib } },
2221     { "(bad)",  { XX } },
2222     { "notA",   { Eb } },
2223     { "negA",   { Eb } },
2224     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2225     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2226     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2227     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2228   },
2229   /* REG_F7 */
2230   {
2231     { "testQ",  { Ev, Iv } },
2232     { "(bad)",  { XX } },
2233     { "notQ",   { Ev } },
2234     { "negQ",   { Ev } },
2235     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2236     { "imulQ",  { Ev } },
2237     { "divQ",   { Ev } },
2238     { "idivQ",  { Ev } },
2239   },
2240   /* REG_FE */
2241   {
2242     { "incA",   { Eb } },
2243     { "decA",   { Eb } },
2244     { "(bad)",  { XX } },
2245     { "(bad)",  { XX } },
2246     { "(bad)",  { XX } },
2247     { "(bad)",  { XX } },
2248     { "(bad)",  { XX } },
2249     { "(bad)",  { XX } },
2250   },
2251   /* REG_FF */
2252   {
2253     { "incQ",   { Ev } },
2254     { "decQ",   { Ev } },
2255     { "callT",  { indirEv } },
2256     { "JcallT", { indirEp } },
2257     { "jmpT",   { indirEv } },
2258     { "JjmpT",  { indirEp } },
2259     { "pushU",  { stackEv } },
2260     { "(bad)",  { XX } },
2261   },
2262   /* REG_0F00 */
2263   {
2264     { "sldtD",  { Sv } },
2265     { "strD",   { Sv } },
2266     { "lldt",   { Ew } },
2267     { "ltr",    { Ew } },
2268     { "verr",   { Ew } },
2269     { "verw",   { Ew } },
2270     { "(bad)",  { XX } },
2271     { "(bad)",  { XX } },
2272   },
2273   /* REG_0F01 */
2274   {
2275     { MOD_TABLE (MOD_0F01_REG_0) },
2276     { MOD_TABLE (MOD_0F01_REG_1) },
2277     { MOD_TABLE (MOD_0F01_REG_2) },
2278     { MOD_TABLE (MOD_0F01_REG_3) },
2279     { "smswD",  { Sv } },
2280     { "(bad)",  { XX } },
2281     { "lmsw",   { Ew } },
2282     { MOD_TABLE (MOD_0F01_REG_7) },
2283   },
2284   /* REG_0F0D */
2285   {
2286     { "prefetch",       { Eb } },
2287     { "prefetchw",      { Eb } },
2288     { "(bad)",          { XX } },
2289     { "(bad)",          { XX } },
2290     { "(bad)",          { XX } },
2291     { "(bad)",          { XX } },
2292     { "(bad)",          { XX } },
2293     { "(bad)",          { XX } },
2294   },
2295   /* REG_0F18 */
2296   {
2297     { MOD_TABLE (MOD_0F18_REG_0) },
2298     { MOD_TABLE (MOD_0F18_REG_1) },
2299     { MOD_TABLE (MOD_0F18_REG_2) },
2300     { MOD_TABLE (MOD_0F18_REG_3) },
2301     { "(bad)",  { XX } },
2302     { "(bad)",  { XX } },
2303     { "(bad)",  { XX } },
2304     { "(bad)",  { XX } },
2305   },
2306   /* REG_0F71 */
2307   {
2308     { "(bad)",  { XX } },
2309     { "(bad)",  { XX } },
2310     { MOD_TABLE (MOD_0F71_REG_2) },
2311     { "(bad)",  { XX } },
2312     { MOD_TABLE (MOD_0F71_REG_4) },
2313     { "(bad)",  { XX } },
2314     { MOD_TABLE (MOD_0F71_REG_6) },
2315     { "(bad)",  { XX } },
2316   },
2317   /* REG_0F72 */
2318   {
2319     { "(bad)",  { XX } },
2320     { "(bad)",  { XX } },
2321     { MOD_TABLE (MOD_0F72_REG_2) },
2322     { "(bad)",  { XX } },
2323     { MOD_TABLE (MOD_0F72_REG_4) },
2324     { "(bad)",  { XX } },
2325     { MOD_TABLE (MOD_0F72_REG_6) },
2326     { "(bad)",  { XX } },
2327   },
2328   /* REG_0F73 */
2329   {
2330     { "(bad)",  { XX } },
2331     { "(bad)",  { XX } },
2332     { MOD_TABLE (MOD_0F73_REG_2) },
2333     { MOD_TABLE (MOD_0F73_REG_3) },
2334     { "(bad)",  { XX } },
2335     { "(bad)",  { XX } },
2336     { MOD_TABLE (MOD_0F73_REG_6) },
2337     { MOD_TABLE (MOD_0F73_REG_7) },
2338   },
2339   /* REG_0FA6 */
2340   {
2341     { "montmul",        { { OP_0f07, 0 } } },
2342     { "xsha1",          { { OP_0f07, 0 } } },
2343     { "xsha256",        { { OP_0f07, 0 } } },
2344     { "(bad)",          { { OP_0f07, 0 } } },
2345     { "(bad)",          { { OP_0f07, 0 } } },
2346     { "(bad)",          { { OP_0f07, 0 } } },
2347     { "(bad)",          { { OP_0f07, 0 } } },
2348     { "(bad)",          { { OP_0f07, 0 } } },
2349   },
2350   /* REG_0FA7 */
2351   {
2352     { "xstore-rng",     { { OP_0f07, 0 } } },
2353     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2354     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2355     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2356     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2357     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2358     { "(bad)",          { { OP_0f07, 0 } } },
2359     { "(bad)",          { { OP_0f07, 0 } } },
2360   },
2361   /* REG_0FAE */
2362   {
2363     { MOD_TABLE (MOD_0FAE_REG_0) },
2364     { MOD_TABLE (MOD_0FAE_REG_1) },
2365     { MOD_TABLE (MOD_0FAE_REG_2) },
2366     { MOD_TABLE (MOD_0FAE_REG_3) },
2367     { MOD_TABLE (MOD_0FAE_REG_4) },
2368     { MOD_TABLE (MOD_0FAE_REG_5) },
2369     { MOD_TABLE (MOD_0FAE_REG_6) },
2370     { MOD_TABLE (MOD_0FAE_REG_7) },
2371   },
2372   /* REG_0FBA */
2373   {
2374     { "(bad)",  { XX } },
2375     { "(bad)",  { XX } },
2376     { "(bad)",  { XX } },
2377     { "(bad)",  { XX } },
2378     { "btQ",    { Ev, Ib } },
2379     { "btsQ",   { Ev, Ib } },
2380     { "btrQ",   { Ev, Ib } },
2381     { "btcQ",   { Ev, Ib } },
2382   },
2383   /* REG_0FC7 */
2384   {
2385     { "(bad)",  { XX } },
2386     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2387     { "(bad)",  { XX } },
2388     { "(bad)",  { XX } },
2389     { "(bad)",  { XX } },
2390     { "(bad)",  { XX } },
2391     { MOD_TABLE (MOD_0FC7_REG_6) },
2392     { MOD_TABLE (MOD_0FC7_REG_7) },
2393   },
2394   /* REG_VEX_71 */
2395   {
2396     { "(bad)",  { XX } },
2397     { "(bad)",  { XX } },
2398     { MOD_TABLE (MOD_VEX_71_REG_2) },
2399     { "(bad)",  { XX } },
2400     { MOD_TABLE (MOD_VEX_71_REG_4) },
2401     { "(bad)",  { XX } },
2402     { MOD_TABLE (MOD_VEX_71_REG_6) },
2403     { "(bad)",  { XX } },
2404   },
2405   /* REG_VEX_72 */
2406   {
2407     { "(bad)",  { XX } },
2408     { "(bad)",  { XX } },
2409     { MOD_TABLE (MOD_VEX_72_REG_2) },
2410     { "(bad)",  { XX } },
2411     { MOD_TABLE (MOD_VEX_72_REG_4) },
2412     { "(bad)",  { XX } },
2413     { MOD_TABLE (MOD_VEX_72_REG_6) },
2414     { "(bad)",  { XX } },
2415   },
2416   /* REG_VEX_73 */
2417   {
2418     { "(bad)",  { XX } },
2419     { "(bad)",  { XX } },
2420     { MOD_TABLE (MOD_VEX_73_REG_2) },
2421     { MOD_TABLE (MOD_VEX_73_REG_3) },
2422     { "(bad)",  { XX } },
2423     { "(bad)",  { XX } },
2424     { MOD_TABLE (MOD_VEX_73_REG_6) },
2425     { MOD_TABLE (MOD_VEX_73_REG_7) },
2426   },
2427   /* REG_VEX_AE */
2428   {
2429     { "(bad)",  { XX } },
2430     { "(bad)",  { XX } },
2431     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2432     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2433     { "(bad)",  { XX } },
2434     { "(bad)",  { XX } },
2435     { "(bad)",  { XX } },
2436     { "(bad)",  { XX } },
2437   },
2438 };
2439
2440 static const struct dis386 prefix_table[][4] = {
2441   /* PREFIX_90 */
2442   {
2443     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2444     { "pause", { XX } },
2445     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2446     { "(bad)", { XX } },
2447   },
2448
2449   /* PREFIX_0F10 */
2450   {
2451     { "movups", { XM, EXx } },
2452     { "movss",  { XM, EXd } },
2453     { "movupd", { XM, EXx } },
2454     { "movsd",  { XM, EXq } },
2455   },
2456
2457   /* PREFIX_0F11 */
2458   {
2459     { "movups", { EXxS, XM } },
2460     { "movss",  { EXdS, XM } },
2461     { "movupd", { EXxS, XM } },
2462     { "movsd",  { EXqS, XM } },
2463   },
2464
2465   /* PREFIX_0F12 */
2466   {
2467     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2468     { "movsldup", { XM, EXx } },
2469     { "movlpd", { XM, EXq } },
2470     { "movddup", { XM, EXq } },
2471   },
2472
2473   /* PREFIX_0F16 */
2474   {
2475     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2476     { "movshdup", { XM, EXx } },
2477     { "movhpd", { XM, EXq } },
2478     { "(bad)",  { XX } },
2479   },
2480
2481   /* PREFIX_0F2A */
2482   {
2483     { "cvtpi2ps", { XM, EMCq } },
2484     { "cvtsi2ss%LQ", { XM, Ev } },
2485     { "cvtpi2pd", { XM, EMCq } },
2486     { "cvtsi2sd%LQ", { XM, Ev } },
2487   },
2488
2489   /* PREFIX_0F2B */
2490   {
2491     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2492     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2493     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2494     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2495   },
2496
2497   /* PREFIX_0F2C */
2498   {
2499     { "cvttps2pi", { MXC, EXq } },
2500     { "cvttss2siY", { Gv, EXd } },
2501     { "cvttpd2pi", { MXC, EXx } },
2502     { "cvttsd2siY", { Gv, EXq } },
2503   },
2504
2505   /* PREFIX_0F2D */
2506   {
2507     { "cvtps2pi", { MXC, EXq } },
2508     { "cvtss2siY", { Gv, EXd } },
2509     { "cvtpd2pi", { MXC, EXx } },
2510     { "cvtsd2siY", { Gv, EXq } },
2511   },
2512
2513   /* PREFIX_0F2E */
2514   {
2515     { "ucomiss",{ XM, EXd } },
2516     { "(bad)",  { XX } },
2517     { "ucomisd",{ XM, EXq } },
2518     { "(bad)",  { XX } },
2519   },
2520
2521   /* PREFIX_0F2F */
2522   {
2523     { "comiss", { XM, EXd } },
2524     { "(bad)",  { XX } },
2525     { "comisd", { XM, EXq } },
2526     { "(bad)",  { XX } },
2527   },
2528
2529   /* PREFIX_0F51 */
2530   {
2531     { "sqrtps", { XM, EXx } },
2532     { "sqrtss", { XM, EXd } },
2533     { "sqrtpd", { XM, EXx } },
2534     { "sqrtsd", { XM, EXq } },
2535   },
2536
2537   /* PREFIX_0F52 */
2538   {
2539     { "rsqrtps",{ XM, EXx } },
2540     { "rsqrtss",{ XM, EXd } },
2541     { "(bad)",  { XX } },
2542     { "(bad)",  { XX } },
2543   },
2544
2545   /* PREFIX_0F53 */
2546   {
2547     { "rcpps",  { XM, EXx } },
2548     { "rcpss",  { XM, EXd } },
2549     { "(bad)",  { XX } },
2550     { "(bad)",  { XX } },
2551   },
2552
2553   /* PREFIX_0F58 */
2554   {
2555     { "addps", { XM, EXx } },
2556     { "addss", { XM, EXd } },
2557     { "addpd", { XM, EXx } },
2558     { "addsd", { XM, EXq } },
2559   },
2560
2561   /* PREFIX_0F59 */
2562   {
2563     { "mulps",  { XM, EXx } },
2564     { "mulss",  { XM, EXd } },
2565     { "mulpd",  { XM, EXx } },
2566     { "mulsd",  { XM, EXq } },
2567   },
2568
2569   /* PREFIX_0F5A */
2570   {
2571     { "cvtps2pd", { XM, EXq } },
2572     { "cvtss2sd", { XM, EXd } },
2573     { "cvtpd2ps", { XM, EXx } },
2574     { "cvtsd2ss", { XM, EXq } },
2575   },
2576
2577   /* PREFIX_0F5B */
2578   {
2579     { "cvtdq2ps", { XM, EXx } },
2580     { "cvttps2dq", { XM, EXx } },
2581     { "cvtps2dq", { XM, EXx } },
2582     { "(bad)",  { XX } },
2583   },
2584
2585   /* PREFIX_0F5C */
2586   {
2587     { "subps",  { XM, EXx } },
2588     { "subss",  { XM, EXd } },
2589     { "subpd",  { XM, EXx } },
2590     { "subsd",  { XM, EXq } },
2591   },
2592
2593   /* PREFIX_0F5D */
2594   {
2595     { "minps",  { XM, EXx } },
2596     { "minss",  { XM, EXd } },
2597     { "minpd",  { XM, EXx } },
2598     { "minsd",  { XM, EXq } },
2599   },
2600
2601   /* PREFIX_0F5E */
2602   {
2603     { "divps",  { XM, EXx } },
2604     { "divss",  { XM, EXd } },
2605     { "divpd",  { XM, EXx } },
2606     { "divsd",  { XM, EXq } },
2607   },
2608
2609   /* PREFIX_0F5F */
2610   {
2611     { "maxps",  { XM, EXx } },
2612     { "maxss",  { XM, EXd } },
2613     { "maxpd",  { XM, EXx } },
2614     { "maxsd",  { XM, EXq } },
2615   },
2616
2617   /* PREFIX_0F60 */
2618   {
2619     { "punpcklbw",{ MX, EMd } },
2620     { "(bad)",  { XX } },
2621     { "punpcklbw",{ MX, EMx } },
2622     { "(bad)",  { XX } },
2623   },
2624
2625   /* PREFIX_0F61 */
2626   {
2627     { "punpcklwd",{ MX, EMd } },
2628     { "(bad)",  { XX } },
2629     { "punpcklwd",{ MX, EMx } },
2630     { "(bad)",  { XX } },
2631   },
2632
2633   /* PREFIX_0F62 */
2634   {
2635     { "punpckldq",{ MX, EMd } },
2636     { "(bad)",  { XX } },
2637     { "punpckldq",{ MX, EMx } },
2638     { "(bad)",  { XX } },
2639   },
2640
2641   /* PREFIX_0F6C */
2642   {
2643     { "(bad)",  { XX } },
2644     { "(bad)",  { XX } },
2645     { "punpcklqdq", { XM, EXx } },
2646     { "(bad)",  { XX } },
2647   },
2648
2649   /* PREFIX_0F6D */
2650   {
2651     { "(bad)",  { XX } },
2652     { "(bad)",  { XX } },
2653     { "punpckhqdq", { XM, EXx } },
2654     { "(bad)",  { XX } },
2655   },
2656
2657   /* PREFIX_0F6F */
2658   {
2659     { "movq",   { MX, EM } },
2660     { "movdqu", { XM, EXx } },
2661     { "movdqa", { XM, EXx } },
2662     { "(bad)",  { XX } },
2663   },
2664
2665   /* PREFIX_0F70 */
2666   {
2667     { "pshufw", { MX, EM, Ib } },
2668     { "pshufhw",{ XM, EXx, Ib } },
2669     { "pshufd", { XM, EXx, Ib } },
2670     { "pshuflw",{ XM, EXx, Ib } },
2671   },
2672
2673   /* PREFIX_0F73_REG_3 */
2674   {
2675     { "(bad)",  { XX } },
2676     { "(bad)",  { XX } },
2677     { "psrldq", { XS, Ib } },
2678     { "(bad)",  { XX } },
2679   },
2680
2681   /* PREFIX_0F73_REG_7 */
2682   {
2683     { "(bad)",  { XX } },
2684     { "(bad)",  { XX } },
2685     { "pslldq", { XS, Ib } },
2686     { "(bad)",  { XX } },
2687   },
2688
2689   /* PREFIX_0F78 */
2690   {
2691     {"vmread",  { Em, Gm } },
2692     {"(bad)",   { XX } },
2693     {"extrq",   { XS, Ib, Ib } },
2694     {"insertq", { XM, XS, Ib, Ib } },
2695   },
2696
2697   /* PREFIX_0F79 */
2698   {
2699     {"vmwrite", { Gm, Em } },
2700     {"(bad)",   { XX } },
2701     {"extrq",   { XM, XS } },
2702     {"insertq", { XM, XS } },
2703   },
2704
2705   /* PREFIX_0F7C */
2706   {
2707     { "(bad)",  { XX } },
2708     { "(bad)",  { XX } },
2709     { "haddpd", { XM, EXx } },
2710     { "haddps", { XM, EXx } },
2711   },
2712
2713   /* PREFIX_0F7D */
2714   {
2715     { "(bad)",  { XX } },
2716     { "(bad)",  { XX } },
2717     { "hsubpd", { XM, EXx } },
2718     { "hsubps", { XM, EXx } },
2719   },
2720
2721   /* PREFIX_0F7E */
2722   {
2723     { "movK",   { Edq, MX } },
2724     { "movq",   { XM, EXq } },
2725     { "movK",   { Edq, XM } },
2726     { "(bad)",  { XX } },
2727   },
2728
2729   /* PREFIX_0F7F */
2730   {
2731     { "movq",   { EMS, MX } },
2732     { "movdqu", { EXxS, XM } },
2733     { "movdqa", { EXxS, XM } },
2734     { "(bad)",  { XX } },
2735   },
2736
2737   /* PREFIX_0FB8 */
2738   {
2739     { "(bad)", { XX } },
2740     { "popcntS", { Gv, Ev } },
2741     { "(bad)", { XX } },
2742     { "(bad)", { XX } },
2743   },
2744
2745   /* PREFIX_0FBD */
2746   {
2747     { "bsrS",   { Gv, Ev } },
2748     { "lzcntS", { Gv, Ev } },
2749     { "bsrS",   { Gv, Ev } },
2750     { "(bad)",  { XX } },
2751   },
2752
2753   /* PREFIX_0FC2 */
2754   {
2755     { "cmpps",  { XM, EXx, CMP } },
2756     { "cmpss",  { XM, EXd, CMP } },
2757     { "cmppd",  { XM, EXx, CMP } },
2758     { "cmpsd",  { XM, EXq, CMP } },
2759   },
2760
2761   /* PREFIX_0FC3 */
2762   {
2763     { "movntiS", { Ma, Gv } },
2764     { "(bad)",  { XX } },
2765     { "(bad)",  { XX } },
2766     { "(bad)",  { XX } },
2767   },
2768
2769   /* PREFIX_0FC7_REG_6 */
2770   {
2771     { "vmptrld",{ Mq } },
2772     { "vmxon",  { Mq } },
2773     { "vmclear",{ Mq } },
2774     { "(bad)",  { XX } },
2775   },
2776
2777   /* PREFIX_0FD0 */
2778   {
2779     { "(bad)",  { XX } },
2780     { "(bad)",  { XX } },
2781     { "addsubpd", { XM, EXx } },
2782     { "addsubps", { XM, EXx } },
2783   },
2784
2785   /* PREFIX_0FD6 */
2786   {
2787     { "(bad)",  { XX } },
2788     { "movq2dq",{ XM, MS } },
2789     { "movq",   { EXqS, XM } },
2790     { "movdq2q",{ MX, XS } },
2791   },
2792
2793   /* PREFIX_0FE6 */
2794   {
2795     { "(bad)",  { XX } },
2796     { "cvtdq2pd", { XM, EXq } },
2797     { "cvttpd2dq", { XM, EXx } },
2798     { "cvtpd2dq", { XM, EXx } },
2799   },
2800
2801   /* PREFIX_0FE7 */
2802   {
2803     { "movntq", { Mq, MX } },
2804     { "(bad)",  { XX } },
2805     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2806     { "(bad)",  { XX } },
2807   },
2808
2809   /* PREFIX_0FF0 */
2810   {
2811     { "(bad)",  { XX } },
2812     { "(bad)",  { XX } },
2813     { "(bad)",  { XX } },
2814     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2815   },
2816
2817   /* PREFIX_0FF7 */
2818   {
2819     { "maskmovq", { MX, MS } },
2820     { "(bad)",  { XX } },
2821     { "maskmovdqu", { XM, XS } },
2822     { "(bad)",  { XX } },
2823   },
2824
2825   /* PREFIX_0F3810 */
2826   {
2827     { "(bad)",  { XX } },
2828     { "(bad)",  { XX } },
2829     { "pblendvb", { XM, EXx, XMM0 } },
2830     { "(bad)",  { XX } },
2831   },
2832
2833   /* PREFIX_0F3814 */
2834   {
2835     { "(bad)",  { XX } },
2836     { "(bad)",  { XX } },
2837     { "blendvps", { XM, EXx, XMM0 } },
2838     { "(bad)",  { XX } },
2839   },
2840
2841   /* PREFIX_0F3815 */
2842   {
2843     { "(bad)",  { XX } },
2844     { "(bad)",  { XX } },
2845     { "blendvpd", { XM, EXx, XMM0 } },
2846     { "(bad)",  { XX } },
2847   },
2848
2849   /* PREFIX_0F3817 */
2850   {
2851     { "(bad)",  { XX } },
2852     { "(bad)",  { XX } },
2853     { "ptest",  { XM, EXx } },
2854     { "(bad)",  { XX } },
2855   },
2856
2857   /* PREFIX_0F3820 */
2858   {
2859     { "(bad)",  { XX } },
2860     { "(bad)",  { XX } },
2861     { "pmovsxbw", { XM, EXq } },
2862     { "(bad)",  { XX } },
2863   },
2864
2865   /* PREFIX_0F3821 */
2866   {
2867     { "(bad)",  { XX } },
2868     { "(bad)",  { XX } },
2869     { "pmovsxbd", { XM, EXd } },
2870     { "(bad)",  { XX } },
2871   },
2872
2873   /* PREFIX_0F3822 */
2874   {
2875     { "(bad)",  { XX } },
2876     { "(bad)",  { XX } },
2877     { "pmovsxbq", { XM, EXw } },
2878     { "(bad)",  { XX } },
2879   },
2880
2881   /* PREFIX_0F3823 */
2882   {
2883     { "(bad)",  { XX } },
2884     { "(bad)",  { XX } },
2885     { "pmovsxwd", { XM, EXq } },
2886     { "(bad)",  { XX } },
2887   },
2888
2889   /* PREFIX_0F3824 */
2890   {
2891     { "(bad)",  { XX } },
2892     { "(bad)",  { XX } },
2893     { "pmovsxwq", { XM, EXd } },
2894     { "(bad)",  { XX } },
2895   },
2896
2897   /* PREFIX_0F3825 */
2898   {
2899     { "(bad)",  { XX } },
2900     { "(bad)",  { XX } },
2901     { "pmovsxdq", { XM, EXq } },
2902     { "(bad)",  { XX } },
2903   },
2904
2905   /* PREFIX_0F3828 */
2906   {
2907     { "(bad)",  { XX } },
2908     { "(bad)",  { XX } },
2909     { "pmuldq", { XM, EXx } },
2910     { "(bad)",  { XX } },
2911   },
2912
2913   /* PREFIX_0F3829 */
2914   {
2915     { "(bad)",  { XX } },
2916     { "(bad)",  { XX } },
2917     { "pcmpeqq", { XM, EXx } },
2918     { "(bad)",  { XX } },
2919   },
2920
2921   /* PREFIX_0F382A */
2922   {
2923     { "(bad)",  { XX } },
2924     { "(bad)",  { XX } },
2925     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2926     { "(bad)",  { XX } },
2927   },
2928
2929   /* PREFIX_0F382B */
2930   {
2931     { "(bad)",  { XX } },
2932     { "(bad)",  { XX } },
2933     { "packusdw", { XM, EXx } },
2934     { "(bad)",  { XX } },
2935   },
2936
2937   /* PREFIX_0F3830 */
2938   {
2939     { "(bad)",  { XX } },
2940     { "(bad)",  { XX } },
2941     { "pmovzxbw", { XM, EXq } },
2942     { "(bad)",  { XX } },
2943   },
2944
2945   /* PREFIX_0F3831 */
2946   {
2947     { "(bad)",  { XX } },
2948     { "(bad)",  { XX } },
2949     { "pmovzxbd", { XM, EXd } },
2950     { "(bad)",  { XX } },
2951   },
2952
2953   /* PREFIX_0F3832 */
2954   {
2955     { "(bad)",  { XX } },
2956     { "(bad)",  { XX } },
2957     { "pmovzxbq", { XM, EXw } },
2958     { "(bad)",  { XX } },
2959   },
2960
2961   /* PREFIX_0F3833 */
2962   {
2963     { "(bad)",  { XX } },
2964     { "(bad)",  { XX } },
2965     { "pmovzxwd", { XM, EXq } },
2966     { "(bad)",  { XX } },
2967   },
2968
2969   /* PREFIX_0F3834 */
2970   {
2971     { "(bad)",  { XX } },
2972     { "(bad)",  { XX } },
2973     { "pmovzxwq", { XM, EXd } },
2974     { "(bad)",  { XX } },
2975   },
2976
2977   /* PREFIX_0F3835 */
2978   {
2979     { "(bad)",  { XX } },
2980     { "(bad)",  { XX } },
2981     { "pmovzxdq", { XM, EXq } },
2982     { "(bad)",  { XX } },
2983   },
2984
2985   /* PREFIX_0F3837 */
2986   {
2987     { "(bad)",  { XX } },
2988     { "(bad)",  { XX } },
2989     { "pcmpgtq", { XM, EXx } },
2990     { "(bad)",  { XX } },
2991   },
2992
2993   /* PREFIX_0F3838 */
2994   {
2995     { "(bad)",  { XX } },
2996     { "(bad)",  { XX } },
2997     { "pminsb", { XM, EXx } },
2998     { "(bad)",  { XX } },
2999   },
3000
3001   /* PREFIX_0F3839 */
3002   {
3003     { "(bad)",  { XX } },
3004     { "(bad)",  { XX } },
3005     { "pminsd", { XM, EXx } },
3006     { "(bad)",  { XX } },
3007   },
3008
3009   /* PREFIX_0F383A */
3010   {
3011     { "(bad)",  { XX } },
3012     { "(bad)",  { XX } },
3013     { "pminuw", { XM, EXx } },
3014     { "(bad)",  { XX } },
3015   },
3016
3017   /* PREFIX_0F383B */
3018   {
3019     { "(bad)",  { XX } },
3020     { "(bad)",  { XX } },
3021     { "pminud", { XM, EXx } },
3022     { "(bad)",  { XX } },
3023   },
3024
3025   /* PREFIX_0F383C */
3026   {
3027     { "(bad)",  { XX } },
3028     { "(bad)",  { XX } },
3029     { "pmaxsb", { XM, EXx } },
3030     { "(bad)",  { XX } },
3031   },
3032
3033   /* PREFIX_0F383D */
3034   {
3035     { "(bad)",  { XX } },
3036     { "(bad)",  { XX } },
3037     { "pmaxsd", { XM, EXx } },
3038     { "(bad)",  { XX } },
3039   },
3040
3041   /* PREFIX_0F383E */
3042   {
3043     { "(bad)",  { XX } },
3044     { "(bad)",  { XX } },
3045     { "pmaxuw", { XM, EXx } },
3046     { "(bad)",  { XX } },
3047   },
3048
3049   /* PREFIX_0F383F */
3050   {
3051     { "(bad)",  { XX } },
3052     { "(bad)",  { XX } },
3053     { "pmaxud", { XM, EXx } },
3054     { "(bad)",  { XX } },
3055   },
3056
3057   /* PREFIX_0F3840 */
3058   {
3059     { "(bad)",  { XX } },
3060     { "(bad)",  { XX } },
3061     { "pmulld", { XM, EXx } },
3062     { "(bad)",  { XX } },
3063   },
3064
3065   /* PREFIX_0F3841 */
3066   {
3067     { "(bad)",  { XX } },
3068     { "(bad)",  { XX } },
3069     { "phminposuw", { XM, EXx } },
3070     { "(bad)",  { XX } },
3071   },
3072
3073   /* PREFIX_0F3880 */
3074   {
3075     { "(bad)",  { XX } },
3076     { "(bad)",  { XX } },
3077     { "invept", { Gm, Mo } },
3078     { "(bad)",  { XX } },
3079   },
3080
3081   /* PREFIX_0F3881 */
3082   {
3083     { "(bad)",  { XX } },
3084     { "(bad)",  { XX } },
3085     { "invvpid", { Gm, Mo } },
3086     { "(bad)",  { XX } },
3087   },
3088
3089   /* PREFIX_0F38DB */
3090   {
3091     { "(bad)",  { XX } },
3092     { "(bad)",  { XX } },
3093     { "aesimc", { XM, EXx } },
3094     { "(bad)",  { XX } },
3095   },
3096
3097   /* PREFIX_0F38DC */
3098   {
3099     { "(bad)",  { XX } },
3100     { "(bad)",  { XX } },
3101     { "aesenc", { XM, EXx } },
3102     { "(bad)",  { XX } },
3103   },
3104
3105   /* PREFIX_0F38DD */
3106   {
3107     { "(bad)",  { XX } },
3108     { "(bad)",  { XX } },
3109     { "aesenclast", { XM, EXx } },
3110     { "(bad)",  { XX } },
3111   },
3112
3113   /* PREFIX_0F38DE */
3114   {
3115     { "(bad)",  { XX } },
3116     { "(bad)",  { XX } },
3117     { "aesdec", { XM, EXx } },
3118     { "(bad)",  { XX } },
3119   },
3120
3121   /* PREFIX_0F38DF */
3122   {
3123     { "(bad)",  { XX } },
3124     { "(bad)",  { XX } },
3125     { "aesdeclast", { XM, EXx } },
3126     { "(bad)",  { XX } },
3127   },
3128
3129   /* PREFIX_0F38F0 */
3130   {
3131     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3132     { "(bad)",  { XX } },
3133     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3134     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3135   },
3136
3137   /* PREFIX_0F38F1 */
3138   {
3139     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3140     { "(bad)",  { XX } },
3141     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3142     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3143   },
3144
3145   /* PREFIX_0F3A08 */
3146   {
3147     { "(bad)",  { XX } },
3148     { "(bad)",  { XX } },
3149     { "roundps", { XM, EXx, Ib } },
3150     { "(bad)",  { XX } },
3151   },
3152
3153   /* PREFIX_0F3A09 */
3154   {
3155     { "(bad)",  { XX } },
3156     { "(bad)",  { XX } },
3157     { "roundpd", { XM, EXx, Ib } },
3158     { "(bad)",  { XX } },
3159   },
3160
3161   /* PREFIX_0F3A0A */
3162   {
3163     { "(bad)",  { XX } },
3164     { "(bad)",  { XX } },
3165     { "roundss", { XM, EXd, Ib } },
3166     { "(bad)",  { XX } },
3167   },
3168
3169   /* PREFIX_0F3A0B */
3170   {
3171     { "(bad)",  { XX } },
3172     { "(bad)",  { XX } },
3173     { "roundsd", { XM, EXq, Ib } },
3174     { "(bad)",  { XX } },
3175   },
3176
3177   /* PREFIX_0F3A0C */
3178   {
3179     { "(bad)",  { XX } },
3180     { "(bad)",  { XX } },
3181     { "blendps", { XM, EXx, Ib } },
3182     { "(bad)",  { XX } },
3183   },
3184
3185   /* PREFIX_0F3A0D */
3186   {
3187     { "(bad)",  { XX } },
3188     { "(bad)",  { XX } },
3189     { "blendpd", { XM, EXx, Ib } },
3190     { "(bad)",  { XX } },
3191   },
3192
3193   /* PREFIX_0F3A0E */
3194   {
3195     { "(bad)",  { XX } },
3196     { "(bad)",  { XX } },
3197     { "pblendw", { XM, EXx, Ib } },
3198     { "(bad)",  { XX } },
3199   },
3200
3201   /* PREFIX_0F3A14 */
3202   {
3203     { "(bad)",  { XX } },
3204     { "(bad)",  { XX } },
3205     { "pextrb", { Edqb, XM, Ib } },
3206     { "(bad)",  { XX } },
3207   },
3208
3209   /* PREFIX_0F3A15 */
3210   {
3211     { "(bad)",  { XX } },
3212     { "(bad)",  { XX } },
3213     { "pextrw", { Edqw, XM, Ib } },
3214     { "(bad)",  { XX } },
3215   },
3216
3217   /* PREFIX_0F3A16 */
3218   {
3219     { "(bad)",  { XX } },
3220     { "(bad)",  { XX } },
3221     { "pextrK", { Edq, XM, Ib } },
3222     { "(bad)",  { XX } },
3223   },
3224
3225   /* PREFIX_0F3A17 */
3226   {
3227     { "(bad)",  { XX } },
3228     { "(bad)",  { XX } },
3229     { "extractps", { Edqd, XM, Ib } },
3230     { "(bad)",  { XX } },
3231   },
3232
3233   /* PREFIX_0F3A20 */
3234   {
3235     { "(bad)",  { XX } },
3236     { "(bad)",  { XX } },
3237     { "pinsrb", { XM, Edqb, Ib } },
3238     { "(bad)",  { XX } },
3239   },
3240
3241   /* PREFIX_0F3A21 */
3242   {
3243     { "(bad)",  { XX } },
3244     { "(bad)",  { XX } },
3245     { "insertps", { XM, EXd, Ib } },
3246     { "(bad)",  { XX } },
3247   },
3248
3249   /* PREFIX_0F3A22 */
3250   {
3251     { "(bad)",  { XX } },
3252     { "(bad)",  { XX } },
3253     { "pinsrK", { XM, Edq, Ib } },
3254     { "(bad)",  { XX } },
3255   },
3256
3257   /* PREFIX_0F3A40 */
3258   {
3259     { "(bad)",  { XX } },
3260     { "(bad)",  { XX } },
3261     { "dpps",   { XM, EXx, Ib } },
3262     { "(bad)",  { XX } },
3263   },
3264
3265   /* PREFIX_0F3A41 */
3266   {
3267     { "(bad)",  { XX } },
3268     { "(bad)",  { XX } },
3269     { "dppd",   { XM, EXx, Ib } },
3270     { "(bad)",  { XX } },
3271   },
3272
3273   /* PREFIX_0F3A42 */
3274   {
3275     { "(bad)",  { XX } },
3276     { "(bad)",  { XX } },
3277     { "mpsadbw", { XM, EXx, Ib } },
3278     { "(bad)",  { XX } },
3279   },
3280
3281   /* PREFIX_0F3A44 */
3282   {
3283     { "(bad)",  { XX } },
3284     { "(bad)",  { XX } },
3285     { "pclmulqdq", { XM, EXx, PCLMUL } },
3286     { "(bad)",  { XX } },
3287   },
3288
3289   /* PREFIX_0F3A60 */
3290   {
3291     { "(bad)",  { XX } },
3292     { "(bad)",  { XX } },
3293     { "pcmpestrm", { XM, EXx, Ib } },
3294     { "(bad)",  { XX } },
3295   },
3296
3297   /* PREFIX_0F3A61 */
3298   {
3299     { "(bad)",  { XX } },
3300     { "(bad)",  { XX } },
3301     { "pcmpestri", { XM, EXx, Ib } },
3302     { "(bad)",  { XX } },
3303   },
3304
3305   /* PREFIX_0F3A62 */
3306   {
3307     { "(bad)",  { XX } },
3308     { "(bad)",  { XX } },
3309     { "pcmpistrm", { XM, EXx, Ib } },
3310     { "(bad)",  { XX } },
3311   },
3312
3313   /* PREFIX_0F3A63 */
3314   {
3315     { "(bad)",  { XX } },
3316     { "(bad)",  { XX } },
3317     { "pcmpistri", { XM, EXx, Ib } },
3318     { "(bad)",  { XX } },
3319   },
3320
3321   /* PREFIX_0F3ADF */
3322   {
3323     { "(bad)",  { XX } },
3324     { "(bad)",  { XX } },
3325     { "aeskeygenassist", { XM, EXx, Ib } },
3326     { "(bad)",  { XX } },
3327   },
3328
3329   /* PREFIX_VEX_10 */
3330   {
3331     { "vmovups", { XM, EXx } },
3332     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3333     { "vmovupd", { XM, EXx } },
3334     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3335   },
3336
3337   /* PREFIX_VEX_11 */
3338   {
3339     { "vmovups", { EXxS, XM } },
3340     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3341     { "vmovupd", { EXxS, XM } },
3342     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3343   },
3344
3345   /* PREFIX_VEX_12 */
3346   {
3347     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3348     { "vmovsldup", { XM, EXx } },
3349     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3350     { "vmovddup", { XM, EXymmq } },
3351   },
3352
3353   /* PREFIX_VEX_16 */
3354   {
3355     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3356     { "vmovshdup", { XM, EXx } },
3357     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3358     { "(bad)",  { XX } },
3359   },
3360
3361   /* PREFIX_VEX_2A */
3362   {
3363     { "(bad)",  { XX } },
3364     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3365     { "(bad)",  { XX } },
3366     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3367   },
3368
3369   /* PREFIX_VEX_2C */
3370   {
3371     { "(bad)",  { XX } },
3372     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3373     { "(bad)",  { XX } },
3374     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3375   },
3376
3377   /* PREFIX_VEX_2D */
3378   {
3379     { "(bad)",  { XX } },
3380     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3381     { "(bad)",  { XX } },
3382     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3383   },
3384
3385   /* PREFIX_VEX_2E */
3386   {
3387     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3388     { "(bad)",  { XX } },
3389     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3390     { "(bad)",  { XX } },
3391   },
3392
3393   /* PREFIX_VEX_2F */
3394   {
3395     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3396     { "(bad)",  { XX } },
3397     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3398     { "(bad)",  { XX } },
3399   },
3400
3401   /* PREFIX_VEX_51 */
3402   {
3403     { "vsqrtps", { XM, EXx } },
3404     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3405     { "vsqrtpd", { XM, EXx } },
3406     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3407   },
3408
3409   /* PREFIX_VEX_52 */
3410   {
3411     { "vrsqrtps", { XM, EXx } },
3412     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3413     { "(bad)",  { XX } },
3414     { "(bad)",  { XX } },
3415   },
3416
3417   /* PREFIX_VEX_53 */
3418   {
3419     { "vrcpps", { XM, EXx } },
3420     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3421     { "(bad)",  { XX } },
3422     { "(bad)",  { XX } },
3423   },
3424
3425   /* PREFIX_VEX_58 */
3426   {
3427     { "vaddps", { XM, Vex, EXx } },
3428     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3429     { "vaddpd", { XM, Vex, EXx } },
3430     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3431   },
3432
3433   /* PREFIX_VEX_59 */
3434   {
3435     { "vmulps", { XM, Vex, EXx } },
3436     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3437     { "vmulpd", { XM, Vex, EXx } },
3438     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3439   },
3440
3441   /* PREFIX_VEX_5A */
3442   {
3443     { "vcvtps2pd", { XM, EXxmmq } },
3444     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3445     { "vcvtpd2ps%XY", { XMM, EXx } },
3446     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3447   },
3448
3449   /* PREFIX_VEX_5B */
3450   {
3451     { "vcvtdq2ps", { XM, EXx } },
3452     { "vcvttps2dq", { XM, EXx } },
3453     { "vcvtps2dq", { XM, EXx } },
3454     { "(bad)",  { XX } },
3455   },
3456
3457   /* PREFIX_VEX_5C */
3458   {
3459     { "vsubps", { XM, Vex, EXx } },
3460     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3461     { "vsubpd", { XM, Vex, EXx } },
3462     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3463   },
3464
3465   /* PREFIX_VEX_5D */
3466   {
3467     { "vminps", { XM, Vex, EXx } },
3468     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3469     { "vminpd", { XM, Vex, EXx } },
3470     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3471   },
3472
3473   /* PREFIX_VEX_5E */
3474   {
3475     { "vdivps", { XM, Vex, EXx } },
3476     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3477     { "vdivpd", { XM, Vex, EXx } },
3478     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3479   },
3480
3481   /* PREFIX_VEX_5F */
3482   {
3483     { "vmaxps", { XM, Vex, EXx } },
3484     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3485     { "vmaxpd", { XM, Vex, EXx } },
3486     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3487   },
3488
3489   /* PREFIX_VEX_60 */
3490   {
3491     { "(bad)",  { XX } },
3492     { "(bad)",  { XX } },
3493     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3494     { "(bad)",  { XX } },
3495   },
3496
3497   /* PREFIX_VEX_61 */
3498   {
3499     { "(bad)",  { XX } },
3500     { "(bad)",  { XX } },
3501     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3502     { "(bad)",  { XX } },
3503   },
3504
3505   /* PREFIX_VEX_62 */
3506   {
3507     { "(bad)",  { XX } },
3508     { "(bad)",  { XX } },
3509     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3510     { "(bad)",  { XX } },
3511   },
3512
3513   /* PREFIX_VEX_63 */
3514   {
3515     { "(bad)",  { XX } },
3516     { "(bad)",  { XX } },
3517     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3518     { "(bad)",  { XX } },
3519   },
3520
3521   /* PREFIX_VEX_64 */
3522   {
3523     { "(bad)",  { XX } },
3524     { "(bad)",  { XX } },
3525     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3526     { "(bad)",  { XX } },
3527   },
3528
3529   /* PREFIX_VEX_65 */
3530   {
3531     { "(bad)",  { XX } },
3532     { "(bad)",  { XX } },
3533     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3534     { "(bad)",  { XX } },
3535   },
3536
3537   /* PREFIX_VEX_66 */
3538   {
3539     { "(bad)",  { XX } },
3540     { "(bad)",  { XX } },
3541     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3542     { "(bad)",  { XX } },
3543   },
3544
3545   /* PREFIX_VEX_67 */
3546   {
3547     { "(bad)",  { XX } },
3548     { "(bad)",  { XX } },
3549     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3550     { "(bad)",  { XX } },
3551   },
3552
3553   /* PREFIX_VEX_68 */
3554   {
3555     { "(bad)",  { XX } },
3556     { "(bad)",  { XX } },
3557     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3558     { "(bad)",  { XX } },
3559   },
3560
3561   /* PREFIX_VEX_69 */
3562   {
3563     { "(bad)",  { XX } },
3564     { "(bad)",  { XX } },
3565     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3566     { "(bad)",  { XX } },
3567   },
3568
3569   /* PREFIX_VEX_6A */
3570   {
3571     { "(bad)",  { XX } },
3572     { "(bad)",  { XX } },
3573     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3574     { "(bad)",  { XX } },
3575   },
3576
3577   /* PREFIX_VEX_6B */
3578   {
3579     { "(bad)",  { XX } },
3580     { "(bad)",  { XX } },
3581     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3582     { "(bad)",  { XX } },
3583   },
3584
3585   /* PREFIX_VEX_6C */
3586   {
3587     { "(bad)",  { XX } },
3588     { "(bad)",  { XX } },
3589     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3590     { "(bad)",  { XX } },
3591   },
3592
3593   /* PREFIX_VEX_6D */
3594   {
3595     { "(bad)",  { XX } },
3596     { "(bad)",  { XX } },
3597     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3598     { "(bad)",  { XX } },
3599   },
3600
3601   /* PREFIX_VEX_6E */
3602   {
3603     { "(bad)",  { XX } },
3604     { "(bad)",  { XX } },
3605     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3606     { "(bad)",  { XX } },
3607   },
3608
3609   /* PREFIX_VEX_6F */
3610   {
3611     { "(bad)",  { XX } },
3612     { "vmovdqu", { XM, EXx } },
3613     { "vmovdqa", { XM, EXx } },
3614     { "(bad)",  { XX } },
3615   },
3616
3617   /* PREFIX_VEX_70 */
3618   {
3619     { "(bad)",  { XX } },
3620     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3621     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3622     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3623   },
3624
3625   /* PREFIX_VEX_71_REG_2 */
3626   {
3627     { "(bad)",  { XX } },
3628     { "(bad)",  { XX } },
3629     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3630     { "(bad)",  { XX } },
3631   },
3632
3633   /* PREFIX_VEX_71_REG_4 */
3634   {
3635     { "(bad)",  { XX } },
3636     { "(bad)",  { XX } },
3637     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3638     { "(bad)",  { XX } },
3639   },
3640
3641   /* PREFIX_VEX_71_REG_6 */
3642   {
3643     { "(bad)",  { XX } },
3644     { "(bad)",  { XX } },
3645     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3646     { "(bad)",  { XX } },
3647   },
3648
3649   /* PREFIX_VEX_72_REG_2 */
3650   {
3651     { "(bad)",  { XX } },
3652     { "(bad)",  { XX } },
3653     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3654     { "(bad)",  { XX } },
3655   },
3656
3657   /* PREFIX_VEX_72_REG_4 */
3658   {
3659     { "(bad)",  { XX } },
3660     { "(bad)",  { XX } },
3661     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3662     { "(bad)",  { XX } },
3663   },
3664
3665   /* PREFIX_VEX_72_REG_6 */
3666   {
3667     { "(bad)",  { XX } },
3668     { "(bad)",  { XX } },
3669     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3670     { "(bad)",  { XX } },
3671   },
3672
3673   /* PREFIX_VEX_73_REG_2 */
3674   {
3675     { "(bad)",  { XX } },
3676     { "(bad)",  { XX } },
3677     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3678     { "(bad)",  { XX } },
3679   },
3680
3681   /* PREFIX_VEX_73_REG_3 */
3682   {
3683     { "(bad)",  { XX } },
3684     { "(bad)",  { XX } },
3685     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3686     { "(bad)",  { XX } },
3687   },
3688
3689   /* PREFIX_VEX_73_REG_6 */
3690   {
3691     { "(bad)",  { XX } },
3692     { "(bad)",  { XX } },
3693     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3694     { "(bad)",  { XX } },
3695   },
3696
3697   /* PREFIX_VEX_73_REG_7 */
3698   {
3699     { "(bad)",  { XX } },
3700     { "(bad)",  { XX } },
3701     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3702     { "(bad)",  { XX } },
3703   },
3704
3705   /* PREFIX_VEX_74 */
3706   {
3707     { "(bad)",  { XX } },
3708     { "(bad)",  { XX } },
3709     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3710     { "(bad)",  { XX } },
3711   },
3712
3713   /* PREFIX_VEX_75 */
3714   {
3715     { "(bad)",  { XX } },
3716     { "(bad)",  { XX } },
3717     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3718     { "(bad)",  { XX } },
3719   },
3720
3721   /* PREFIX_VEX_76 */
3722   {
3723     { "(bad)",  { XX } },
3724     { "(bad)",  { XX } },
3725     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3726     { "(bad)",  { XX } },
3727   },
3728
3729   /* PREFIX_VEX_77 */
3730   {
3731     { "",       { VZERO } },
3732     { "(bad)",  { XX } },
3733     { "(bad)",  { XX } },
3734     { "(bad)",  { XX } },
3735   },
3736
3737   /* PREFIX_VEX_7C */
3738   {
3739     { "(bad)",  { XX } },
3740     { "(bad)",  { XX } },
3741     { "vhaddpd", { XM, Vex, EXx } },
3742     { "vhaddps", { XM, Vex, EXx } },
3743   },
3744
3745   /* PREFIX_VEX_7D */
3746   {
3747     { "(bad)",  { XX } },
3748     { "(bad)",  { XX } },
3749     { "vhsubpd", { XM, Vex, EXx } },
3750     { "vhsubps", { XM, Vex, EXx } },
3751   },
3752
3753   /* PREFIX_VEX_7E */
3754   {
3755     { "(bad)",  { XX } },
3756     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3757     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3758     { "(bad)",  { XX } },
3759   },
3760
3761   /* PREFIX_VEX_7F */
3762   {
3763     { "(bad)",  { XX } },
3764     { "vmovdqu", { EXxS, XM } },
3765     { "vmovdqa", { EXxS, XM } },
3766     { "(bad)",  { XX } },
3767   },
3768
3769   /* PREFIX_VEX_C2 */
3770   {
3771     { "vcmpps", { XM, Vex, EXx, VCMP } },
3772     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3773     { "vcmppd", { XM, Vex, EXx, VCMP } },
3774     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3775   },
3776
3777   /* PREFIX_VEX_C4 */
3778   {
3779     { "(bad)",  { XX } },
3780     { "(bad)",  { XX } },
3781     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3782     { "(bad)",  { XX } },
3783   },
3784
3785   /* PREFIX_VEX_C5 */
3786   {
3787     { "(bad)",  { XX } },
3788     { "(bad)",  { XX } },
3789     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3790     { "(bad)",  { XX } },
3791   },
3792
3793   /* PREFIX_VEX_D0 */
3794   {
3795     { "(bad)",  { XX } },
3796     { "(bad)",  { XX } },
3797     { "vaddsubpd", { XM, Vex, EXx } },
3798     { "vaddsubps", { XM, Vex, EXx } },
3799   },
3800
3801   /* PREFIX_VEX_D1 */
3802   {
3803     { "(bad)",  { XX } },
3804     { "(bad)",  { XX } },
3805     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3806     { "(bad)",  { XX } },
3807   },
3808
3809   /* PREFIX_VEX_D2 */
3810   {
3811     { "(bad)",  { XX } },
3812     { "(bad)",  { XX } },
3813     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3814     { "(bad)",  { XX } },
3815   },
3816
3817   /* PREFIX_VEX_D3 */
3818   {
3819     { "(bad)",  { XX } },
3820     { "(bad)",  { XX } },
3821     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3822     { "(bad)",  { XX } },
3823   },
3824
3825   /* PREFIX_VEX_D4 */
3826   {
3827     { "(bad)",  { XX } },
3828     { "(bad)",  { XX } },
3829     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3830     { "(bad)",  { XX } },
3831   },
3832
3833   /* PREFIX_VEX_D5 */
3834   {
3835     { "(bad)",  { XX } },
3836     { "(bad)",  { XX } },
3837     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3838     { "(bad)",  { XX } },
3839   },
3840
3841   /* PREFIX_VEX_D6 */
3842   {
3843     { "(bad)",  { XX } },
3844     { "(bad)",  { XX } },
3845     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3846     { "(bad)",  { XX } },
3847   },
3848
3849   /* PREFIX_VEX_D7 */
3850   {
3851     { "(bad)",  { XX } },
3852     { "(bad)",  { XX } },
3853     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3854     { "(bad)",  { XX } },
3855   },
3856
3857   /* PREFIX_VEX_D8 */
3858   {
3859     { "(bad)",  { XX } },
3860     { "(bad)",  { XX } },
3861     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3862     { "(bad)",  { XX } },
3863   },
3864
3865   /* PREFIX_VEX_D9 */
3866   {
3867     { "(bad)",  { XX } },
3868     { "(bad)",  { XX } },
3869     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3870     { "(bad)",  { XX } },
3871   },
3872
3873   /* PREFIX_VEX_DA */
3874   {
3875     { "(bad)",  { XX } },
3876     { "(bad)",  { XX } },
3877     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3878     { "(bad)",  { XX } },
3879   },
3880
3881   /* PREFIX_VEX_DB */
3882   {
3883     { "(bad)",  { XX } },
3884     { "(bad)",  { XX } },
3885     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3886     { "(bad)",  { XX } },
3887   },
3888
3889   /* PREFIX_VEX_DC */
3890   {
3891     { "(bad)",  { XX } },
3892     { "(bad)",  { XX } },
3893     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3894     { "(bad)",  { XX } },
3895   },
3896
3897   /* PREFIX_VEX_DD */
3898   {
3899     { "(bad)",  { XX } },
3900     { "(bad)",  { XX } },
3901     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3902     { "(bad)",  { XX } },
3903   },
3904
3905   /* PREFIX_VEX_DE */
3906   {
3907     { "(bad)",  { XX } },
3908     { "(bad)",  { XX } },
3909     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3910     { "(bad)",  { XX } },
3911   },
3912
3913   /* PREFIX_VEX_DF */
3914   {
3915     { "(bad)",  { XX } },
3916     { "(bad)",  { XX } },
3917     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3918     { "(bad)",  { XX } },
3919   },
3920
3921   /* PREFIX_VEX_E0 */
3922   {
3923     { "(bad)",  { XX } },
3924     { "(bad)",  { XX } },
3925     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3926     { "(bad)",  { XX } },
3927   },
3928
3929   /* PREFIX_VEX_E1 */
3930   {
3931     { "(bad)",  { XX } },
3932     { "(bad)",  { XX } },
3933     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3934     { "(bad)",  { XX } },
3935   },
3936
3937   /* PREFIX_VEX_E2 */
3938   {
3939     { "(bad)",  { XX } },
3940     { "(bad)",  { XX } },
3941     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3942     { "(bad)",  { XX } },
3943   },
3944
3945   /* PREFIX_VEX_E3 */
3946   {
3947     { "(bad)",  { XX } },
3948     { "(bad)",  { XX } },
3949     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3950     { "(bad)",  { XX } },
3951   },
3952
3953   /* PREFIX_VEX_E4 */
3954   {
3955     { "(bad)",  { XX } },
3956     { "(bad)",  { XX } },
3957     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3958     { "(bad)",  { XX } },
3959   },
3960
3961   /* PREFIX_VEX_E5 */
3962   {
3963     { "(bad)",  { XX } },
3964     { "(bad)",  { XX } },
3965     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3966     { "(bad)",  { XX } },
3967   },
3968
3969   /* PREFIX_VEX_E6 */
3970   {
3971     { "(bad)",  { XX } },
3972     { "vcvtdq2pd", { XM, EXxmmq } },
3973     { "vcvttpd2dq%XY", { XMM, EXx } },
3974     { "vcvtpd2dq%XY", { XMM, EXx } },
3975   },
3976
3977   /* PREFIX_VEX_E7 */
3978   {
3979     { "(bad)",  { XX } },
3980     { "(bad)",  { XX } },
3981     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3982     { "(bad)",  { XX } },
3983   },
3984
3985   /* PREFIX_VEX_E8 */
3986   {
3987     { "(bad)",  { XX } },
3988     { "(bad)",  { XX } },
3989     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3990     { "(bad)",  { XX } },
3991   },
3992
3993   /* PREFIX_VEX_E9 */
3994   {
3995     { "(bad)",  { XX } },
3996     { "(bad)",  { XX } },
3997     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3998     { "(bad)",  { XX } },
3999   },
4000
4001   /* PREFIX_VEX_EA */
4002   {
4003     { "(bad)",  { XX } },
4004     { "(bad)",  { XX } },
4005     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4006     { "(bad)",  { XX } },
4007   },
4008
4009   /* PREFIX_VEX_EB */
4010   {
4011     { "(bad)",  { XX } },
4012     { "(bad)",  { XX } },
4013     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4014     { "(bad)",  { XX } },
4015   },
4016
4017   /* PREFIX_VEX_EC */
4018   {
4019     { "(bad)",  { XX } },
4020     { "(bad)",  { XX } },
4021     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4022     { "(bad)",  { XX } },
4023   },
4024
4025   /* PREFIX_VEX_ED */
4026   {
4027     { "(bad)",  { XX } },
4028     { "(bad)",  { XX } },
4029     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4030     { "(bad)",  { XX } },
4031   },
4032
4033   /* PREFIX_VEX_EE */
4034   {
4035     { "(bad)",  { XX } },
4036     { "(bad)",  { XX } },
4037     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4038     { "(bad)",  { XX } },
4039   },
4040
4041   /* PREFIX_VEX_EF */
4042   {
4043     { "(bad)",  { XX } },
4044     { "(bad)",  { XX } },
4045     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4046     { "(bad)",  { XX } },
4047   },
4048
4049   /* PREFIX_VEX_F0 */
4050   {
4051     { "(bad)",  { XX } },
4052     { "(bad)",  { XX } },
4053     { "(bad)",  { XX } },
4054     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4055   },
4056
4057   /* PREFIX_VEX_F1 */
4058   {
4059     { "(bad)",  { XX } },
4060     { "(bad)",  { XX } },
4061     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4062     { "(bad)",  { XX } },
4063   },
4064
4065   /* PREFIX_VEX_F2 */
4066   {
4067     { "(bad)",  { XX } },
4068     { "(bad)",  { XX } },
4069     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4070     { "(bad)",  { XX } },
4071   },
4072
4073   /* PREFIX_VEX_F3 */
4074   {
4075     { "(bad)",  { XX } },
4076     { "(bad)",  { XX } },
4077     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4078     { "(bad)",  { XX } },
4079   },
4080
4081   /* PREFIX_VEX_F4 */
4082   {
4083     { "(bad)",  { XX } },
4084     { "(bad)",  { XX } },
4085     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4086     { "(bad)",  { XX } },
4087   },
4088
4089   /* PREFIX_VEX_F5 */
4090   {
4091     { "(bad)",  { XX } },
4092     { "(bad)",  { XX } },
4093     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4094     { "(bad)",  { XX } },
4095   },
4096
4097   /* PREFIX_VEX_F6 */
4098   {
4099     { "(bad)",  { XX } },
4100     { "(bad)",  { XX } },
4101     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4102     { "(bad)",  { XX } },
4103   },
4104
4105   /* PREFIX_VEX_F7 */
4106   {
4107     { "(bad)",  { XX } },
4108     { "(bad)",  { XX } },
4109     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4110     { "(bad)",  { XX } },
4111   },
4112
4113   /* PREFIX_VEX_F8 */
4114   {
4115     { "(bad)",  { XX } },
4116     { "(bad)",  { XX } },
4117     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4118     { "(bad)",  { XX } },
4119   },
4120
4121   /* PREFIX_VEX_F9 */
4122   {
4123     { "(bad)",  { XX } },
4124     { "(bad)",  { XX } },
4125     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4126     { "(bad)",  { XX } },
4127   },
4128
4129   /* PREFIX_VEX_FA */
4130   {
4131     { "(bad)",  { XX } },
4132     { "(bad)",  { XX } },
4133     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4134     { "(bad)",  { XX } },
4135   },
4136
4137   /* PREFIX_VEX_FB */
4138   {
4139     { "(bad)",  { XX } },
4140     { "(bad)",  { XX } },
4141     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4142     { "(bad)",  { XX } },
4143   },
4144
4145   /* PREFIX_VEX_FC */
4146   {
4147     { "(bad)",  { XX } },
4148     { "(bad)",  { XX } },
4149     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4150     { "(bad)",  { XX } },
4151   },
4152
4153   /* PREFIX_VEX_FD */
4154   {
4155     { "(bad)",  { XX } },
4156     { "(bad)",  { XX } },
4157     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4158     { "(bad)",  { XX } },
4159   },
4160
4161   /* PREFIX_VEX_FE */
4162   {
4163     { "(bad)",  { XX } },
4164     { "(bad)",  { XX } },
4165     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4166     { "(bad)",  { XX } },
4167   },
4168
4169   /* PREFIX_VEX_3800 */
4170   {
4171     { "(bad)",  { XX } },
4172     { "(bad)",  { XX } },
4173     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4174     { "(bad)",  { XX } },
4175   },
4176
4177   /* PREFIX_VEX_3801 */
4178   {
4179     { "(bad)",  { XX } },
4180     { "(bad)",  { XX } },
4181     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4182     { "(bad)",  { XX } },
4183   },
4184
4185   /* PREFIX_VEX_3802 */
4186   {
4187     { "(bad)",  { XX } },
4188     { "(bad)",  { XX } },
4189     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4190     { "(bad)",  { XX } },
4191   },
4192
4193   /* PREFIX_VEX_3803 */
4194   {
4195     { "(bad)",  { XX } },
4196     { "(bad)",  { XX } },
4197     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4198     { "(bad)",  { XX } },
4199   },
4200
4201   /* PREFIX_VEX_3804 */
4202   {
4203     { "(bad)",  { XX } },
4204     { "(bad)",  { XX } },
4205     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4206     { "(bad)",  { XX } },
4207   },
4208
4209   /* PREFIX_VEX_3805 */
4210   {
4211     { "(bad)",  { XX } },
4212     { "(bad)",  { XX } },
4213     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4214     { "(bad)",  { XX } },
4215   },
4216
4217   /* PREFIX_VEX_3806 */
4218   {
4219     { "(bad)",  { XX } },
4220     { "(bad)",  { XX } },
4221     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4222     { "(bad)",  { XX } },
4223   },
4224
4225   /* PREFIX_VEX_3807 */
4226   {
4227     { "(bad)",  { XX } },
4228     { "(bad)",  { XX } },
4229     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4230     { "(bad)",  { XX } },
4231   },
4232
4233   /* PREFIX_VEX_3808 */
4234   {
4235     { "(bad)",  { XX } },
4236     { "(bad)",  { XX } },
4237     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4238     { "(bad)",  { XX } },
4239   },
4240
4241   /* PREFIX_VEX_3809 */
4242   {
4243     { "(bad)",  { XX } },
4244     { "(bad)",  { XX } },
4245     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4246     { "(bad)",  { XX } },
4247   },
4248
4249   /* PREFIX_VEX_380A */
4250   {
4251     { "(bad)",  { XX } },
4252     { "(bad)",  { XX } },
4253     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4254     { "(bad)",  { XX } },
4255   },
4256
4257   /* PREFIX_VEX_380B */
4258   {
4259     { "(bad)",  { XX } },
4260     { "(bad)",  { XX } },
4261     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4262     { "(bad)",  { XX } },
4263   },
4264
4265   /* PREFIX_VEX_380C */
4266   {
4267     { "(bad)",  { XX } },
4268     { "(bad)",  { XX } },
4269     { "vpermilps", { XM, Vex, EXx } },
4270     { "(bad)",  { XX } },
4271   },
4272
4273   /* PREFIX_VEX_380D */
4274   {
4275     { "(bad)",  { XX } },
4276     { "(bad)",  { XX } },
4277     { "vpermilpd", { XM, Vex, EXx } },
4278     { "(bad)",  { XX } },
4279   },
4280
4281   /* PREFIX_VEX_380E */
4282   {
4283     { "(bad)",  { XX } },
4284     { "(bad)",  { XX } },
4285     { "vtestps", { XM, EXx } },
4286     { "(bad)",  { XX } },
4287   },
4288
4289   /* PREFIX_VEX_380F */
4290   {
4291     { "(bad)",  { XX } },
4292     { "(bad)",  { XX } },
4293     { "vtestpd", { XM, EXx } },
4294     { "(bad)",  { XX } },
4295   },
4296
4297   /* PREFIX_VEX_3817 */
4298   {
4299     { "(bad)",  { XX } },
4300     { "(bad)",  { XX } },
4301     { "vptest", { XM, EXx } },
4302     { "(bad)",  { XX } },
4303   },
4304
4305   /* PREFIX_VEX_3818 */
4306   {
4307     { "(bad)",  { XX } },
4308     { "(bad)",  { XX } },
4309     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4310     { "(bad)",  { XX } },
4311   },
4312
4313   /* PREFIX_VEX_3819 */
4314   {
4315     { "(bad)",  { XX } },
4316     { "(bad)",  { XX } },
4317     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4318     { "(bad)",  { XX } },
4319   },
4320
4321   /* PREFIX_VEX_381A */
4322   {
4323     { "(bad)",  { XX } },
4324     { "(bad)",  { XX } },
4325     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4326     { "(bad)",  { XX } },
4327   },
4328
4329   /* PREFIX_VEX_381C */
4330   {
4331     { "(bad)",  { XX } },
4332     { "(bad)",  { XX } },
4333     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4334     { "(bad)",  { XX } },
4335   },
4336
4337   /* PREFIX_VEX_381D */
4338   {
4339     { "(bad)",  { XX } },
4340     { "(bad)",  { XX } },
4341     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4342     { "(bad)",  { XX } },
4343   },
4344
4345   /* PREFIX_VEX_381E */
4346   {
4347     { "(bad)",  { XX } },
4348     { "(bad)",  { XX } },
4349     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4350     { "(bad)",  { XX } },
4351   },
4352
4353   /* PREFIX_VEX_3820 */
4354   {
4355     { "(bad)",  { XX } },
4356     { "(bad)",  { XX } },
4357     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4358     { "(bad)",  { XX } },
4359   },
4360
4361   /* PREFIX_VEX_3821 */
4362   {
4363     { "(bad)",  { XX } },
4364     { "(bad)",  { XX } },
4365     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4366     { "(bad)",  { XX } },
4367   },
4368
4369   /* PREFIX_VEX_3822 */
4370   {
4371     { "(bad)",  { XX } },
4372     { "(bad)",  { XX } },
4373     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4374     { "(bad)",  { XX } },
4375   },
4376
4377   /* PREFIX_VEX_3823 */
4378   {
4379     { "(bad)",  { XX } },
4380     { "(bad)",  { XX } },
4381     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4382     { "(bad)",  { XX } },
4383   },
4384
4385   /* PREFIX_VEX_3824 */
4386   {
4387     { "(bad)",  { XX } },
4388     { "(bad)",  { XX } },
4389     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4390     { "(bad)",  { XX } },
4391   },
4392
4393   /* PREFIX_VEX_3825 */
4394   {
4395     { "(bad)",  { XX } },
4396     { "(bad)",  { XX } },
4397     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4398     { "(bad)",  { XX } },
4399   },
4400
4401   /* PREFIX_VEX_3828 */
4402   {
4403     { "(bad)",  { XX } },
4404     { "(bad)",  { XX } },
4405     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4406     { "(bad)",  { XX } },
4407   },
4408
4409   /* PREFIX_VEX_3829 */
4410   {
4411     { "(bad)",  { XX } },
4412     { "(bad)",  { XX } },
4413     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4414     { "(bad)",  { XX } },
4415   },
4416
4417   /* PREFIX_VEX_382A */
4418   {
4419     { "(bad)",  { XX } },
4420     { "(bad)",  { XX } },
4421     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4422     { "(bad)",  { XX } },
4423   },
4424
4425   /* PREFIX_VEX_382B */
4426   {
4427     { "(bad)",  { XX } },
4428     { "(bad)",  { XX } },
4429     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4430     { "(bad)",  { XX } },
4431   },
4432
4433   /* PREFIX_VEX_382C */
4434   {
4435     { "(bad)",  { XX } },
4436     { "(bad)",  { XX } },
4437      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4438     { "(bad)",  { XX } },
4439   },
4440
4441   /* PREFIX_VEX_382D */
4442   {
4443     { "(bad)",  { XX } },
4444     { "(bad)",  { XX } },
4445      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4446     { "(bad)",  { XX } },
4447   },
4448
4449   /* PREFIX_VEX_382E */
4450   {
4451     { "(bad)",  { XX } },
4452     { "(bad)",  { XX } },
4453      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4454     { "(bad)",  { XX } },
4455   },
4456
4457   /* PREFIX_VEX_382F */
4458   {
4459     { "(bad)",  { XX } },
4460     { "(bad)",  { XX } },
4461      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4462     { "(bad)",  { XX } },
4463   },
4464
4465   /* PREFIX_VEX_3830 */
4466   {
4467     { "(bad)",  { XX } },
4468     { "(bad)",  { XX } },
4469     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4470     { "(bad)",  { XX } },
4471   },
4472
4473   /* PREFIX_VEX_3831 */
4474   {
4475     { "(bad)",  { XX } },
4476     { "(bad)",  { XX } },
4477     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4478     { "(bad)",  { XX } },
4479   },
4480
4481   /* PREFIX_VEX_3832 */
4482   {
4483     { "(bad)",  { XX } },
4484     { "(bad)",  { XX } },
4485     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4486     { "(bad)",  { XX } },
4487   },
4488
4489   /* PREFIX_VEX_3833 */
4490   {
4491     { "(bad)",  { XX } },
4492     { "(bad)",  { XX } },
4493     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4494     { "(bad)",  { XX } },
4495   },
4496
4497   /* PREFIX_VEX_3834 */
4498   {
4499     { "(bad)",  { XX } },
4500     { "(bad)",  { XX } },
4501     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4502     { "(bad)",  { XX } },
4503   },
4504
4505   /* PREFIX_VEX_3835 */
4506   {
4507     { "(bad)",  { XX } },
4508     { "(bad)",  { XX } },
4509     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4510     { "(bad)",  { XX } },
4511   },
4512
4513   /* PREFIX_VEX_3837 */
4514   {
4515     { "(bad)",  { XX } },
4516     { "(bad)",  { XX } },
4517     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4518     { "(bad)",  { XX } },
4519   },
4520
4521   /* PREFIX_VEX_3838 */
4522   {
4523     { "(bad)",  { XX } },
4524     { "(bad)",  { XX } },
4525     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4526     { "(bad)",  { XX } },
4527   },
4528
4529   /* PREFIX_VEX_3839 */
4530   {
4531     { "(bad)",  { XX } },
4532     { "(bad)",  { XX } },
4533     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4534     { "(bad)",  { XX } },
4535   },
4536
4537   /* PREFIX_VEX_383A */
4538   {
4539     { "(bad)",  { XX } },
4540     { "(bad)",  { XX } },
4541     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4542     { "(bad)",  { XX } },
4543   },
4544
4545   /* PREFIX_VEX_383B */
4546   {
4547     { "(bad)",  { XX } },
4548     { "(bad)",  { XX } },
4549     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4550     { "(bad)",  { XX } },
4551   },
4552
4553   /* PREFIX_VEX_383C */
4554   {
4555     { "(bad)",  { XX } },
4556     { "(bad)",  { XX } },
4557     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4558     { "(bad)",  { XX } },
4559   },
4560
4561   /* PREFIX_VEX_383D */
4562   {
4563     { "(bad)",  { XX } },
4564     { "(bad)",  { XX } },
4565     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4566     { "(bad)",  { XX } },
4567   },
4568
4569   /* PREFIX_VEX_383E */
4570   {
4571     { "(bad)",  { XX } },
4572     { "(bad)",  { XX } },
4573     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4574     { "(bad)",  { XX } },
4575   },
4576
4577   /* PREFIX_VEX_383F */
4578   {
4579     { "(bad)",  { XX } },
4580     { "(bad)",  { XX } },
4581     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4582     { "(bad)",  { XX } },
4583   },
4584
4585   /* PREFIX_VEX_3840 */
4586   {
4587     { "(bad)",  { XX } },
4588     { "(bad)",  { XX } },
4589     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4590     { "(bad)",  { XX } },
4591   },
4592
4593   /* PREFIX_VEX_3841 */
4594   {
4595     { "(bad)",  { XX } },
4596     { "(bad)",  { XX } },
4597     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4598     { "(bad)",  { XX } },
4599   },
4600
4601   /* PREFIX_VEX_3896 */
4602   {
4603     { "(bad)",  { XX } },
4604     { "(bad)",  { XX } },
4605     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4606     { "(bad)",  { XX } },
4607   },
4608
4609   /* PREFIX_VEX_3897 */
4610   {
4611     { "(bad)",  { XX } },
4612     { "(bad)",  { XX } },
4613     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4614     { "(bad)",  { XX } },
4615   },
4616
4617   /* PREFIX_VEX_3898 */
4618   {
4619     { "(bad)",  { XX } },
4620     { "(bad)",  { XX } },
4621     { "vfmadd132p%XW", { XM, Vex, EXx } },
4622     { "(bad)",  { XX } },
4623   },
4624
4625   /* PREFIX_VEX_3899 */
4626   {
4627     { "(bad)",  { XX } },
4628     { "(bad)",  { XX } },
4629     { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4630     { "(bad)",  { XX } },
4631   },
4632
4633   /* PREFIX_VEX_389A */
4634   {
4635     { "(bad)",  { XX } },
4636     { "(bad)",  { XX } },
4637     { "vfmsub132p%XW", { XM, Vex, EXx } },
4638     { "(bad)",  { XX } },
4639   },
4640
4641   /* PREFIX_VEX_389B */
4642   {
4643     { "(bad)",  { XX } },
4644     { "(bad)",  { XX } },
4645     { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4646     { "(bad)",  { XX } },
4647   },
4648
4649   /* PREFIX_VEX_389C */
4650   {
4651     { "(bad)",  { XX } },
4652     { "(bad)",  { XX } },
4653     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4654     { "(bad)",  { XX } },
4655   },
4656
4657   /* PREFIX_VEX_389D */
4658   {
4659     { "(bad)",  { XX } },
4660     { "(bad)",  { XX } },
4661     { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4662     { "(bad)",  { XX } },
4663   },
4664
4665   /* PREFIX_VEX_389E */
4666   {
4667     { "(bad)",  { XX } },
4668     { "(bad)",  { XX } },
4669     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4670     { "(bad)",  { XX } },
4671   },
4672
4673   /* PREFIX_VEX_389F */
4674   {
4675     { "(bad)",  { XX } },
4676     { "(bad)",  { XX } },
4677     { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4678     { "(bad)",  { XX } },
4679   },
4680
4681   /* PREFIX_VEX_38A6 */
4682   {
4683     { "(bad)",  { XX } },
4684     { "(bad)",  { XX } },
4685     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4686     { "(bad)",  { XX } },
4687   },
4688
4689   /* PREFIX_VEX_38A7 */
4690   {
4691     { "(bad)",  { XX } },
4692     { "(bad)",  { XX } },
4693     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4694     { "(bad)",  { XX } },
4695   },
4696
4697   /* PREFIX_VEX_38A8 */
4698   {
4699     { "(bad)",  { XX } },
4700     { "(bad)",  { XX } },
4701     { "vfmadd213p%XW", { XM, Vex, EXx } },
4702     { "(bad)",  { XX } },
4703   },
4704
4705   /* PREFIX_VEX_38A9 */
4706   {
4707     { "(bad)",  { XX } },
4708     { "(bad)",  { XX } },
4709     { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4710     { "(bad)",  { XX } },
4711   },
4712
4713   /* PREFIX_VEX_38AA */
4714   {
4715     { "(bad)",  { XX } },
4716     { "(bad)",  { XX } },
4717     { "vfmsub213p%XW", { XM, Vex, EXx } },
4718     { "(bad)",  { XX } },
4719   },
4720
4721   /* PREFIX_VEX_38AB */
4722   {
4723     { "(bad)",  { XX } },
4724     { "(bad)",  { XX } },
4725     { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4726     { "(bad)",  { XX } },
4727   },
4728
4729   /* PREFIX_VEX_38AC */
4730   {
4731     { "(bad)",  { XX } },
4732     { "(bad)",  { XX } },
4733     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4734     { "(bad)",  { XX } },
4735   },
4736
4737   /* PREFIX_VEX_38AD */
4738   {
4739     { "(bad)",  { XX } },
4740     { "(bad)",  { XX } },
4741     { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4742     { "(bad)",  { XX } },
4743   },
4744
4745   /* PREFIX_VEX_38AE */
4746   {
4747     { "(bad)",  { XX } },
4748     { "(bad)",  { XX } },
4749     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4750     { "(bad)",  { XX } },
4751   },
4752
4753   /* PREFIX_VEX_38AF */
4754   {
4755     { "(bad)",  { XX } },
4756     { "(bad)",  { XX } },
4757     { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4758     { "(bad)",  { XX } },
4759   },
4760
4761   /* PREFIX_VEX_38B6 */
4762   {
4763     { "(bad)",  { XX } },
4764     { "(bad)",  { XX } },
4765     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4766     { "(bad)",  { XX } },
4767   },
4768
4769   /* PREFIX_VEX_38B7 */
4770   {
4771     { "(bad)",  { XX } },
4772     { "(bad)",  { XX } },
4773     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4774     { "(bad)",  { XX } },
4775   },
4776
4777   /* PREFIX_VEX_38B8 */
4778   {
4779     { "(bad)",  { XX } },
4780     { "(bad)",  { XX } },
4781     { "vfmadd231p%XW", { XM, Vex, EXx } },
4782     { "(bad)",  { XX } },
4783   },
4784
4785   /* PREFIX_VEX_38B9 */
4786   {
4787     { "(bad)",  { XX } },
4788     { "(bad)",  { XX } },
4789     { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4790     { "(bad)",  { XX } },
4791   },
4792
4793   /* PREFIX_VEX_38BA */
4794   {
4795     { "(bad)",  { XX } },
4796     { "(bad)",  { XX } },
4797     { "vfmsub231p%XW", { XM, Vex, EXx } },
4798     { "(bad)",  { XX } },
4799   },
4800
4801   /* PREFIX_VEX_38BB */
4802   {
4803     { "(bad)",  { XX } },
4804     { "(bad)",  { XX } },
4805     { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4806     { "(bad)",  { XX } },
4807   },
4808
4809   /* PREFIX_VEX_38BC */
4810   {
4811     { "(bad)",  { XX } },
4812     { "(bad)",  { XX } },
4813     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4814     { "(bad)",  { XX } },
4815   },
4816
4817   /* PREFIX_VEX_38BD */
4818   {
4819     { "(bad)",  { XX } },
4820     { "(bad)",  { XX } },
4821     { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4822     { "(bad)",  { XX } },
4823   },
4824
4825   /* PREFIX_VEX_38BE */
4826   {
4827     { "(bad)",  { XX } },
4828     { "(bad)",  { XX } },
4829     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4830     { "(bad)",  { XX } },
4831   },
4832
4833   /* PREFIX_VEX_38BF */
4834   {
4835     { "(bad)",  { XX } },
4836     { "(bad)",  { XX } },
4837     { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4838     { "(bad)",  { XX } },
4839   },
4840
4841   /* PREFIX_VEX_38DB */
4842   {
4843     { "(bad)",  { XX } },
4844     { "(bad)",  { XX } },
4845     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4846     { "(bad)",  { XX } },
4847   },
4848
4849   /* PREFIX_VEX_38DC */
4850   {
4851     { "(bad)",  { XX } },
4852     { "(bad)",  { XX } },
4853     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4854     { "(bad)",  { XX } },
4855   },
4856
4857   /* PREFIX_VEX_38DD */
4858   {
4859     { "(bad)",  { XX } },
4860     { "(bad)",  { XX } },
4861     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4862     { "(bad)",  { XX } },
4863   },
4864
4865   /* PREFIX_VEX_38DE */
4866   {
4867     { "(bad)",  { XX } },
4868     { "(bad)",  { XX } },
4869     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4870     { "(bad)",  { XX } },
4871   },
4872
4873   /* PREFIX_VEX_38DF */
4874   {
4875     { "(bad)",  { XX } },
4876     { "(bad)",  { XX } },
4877     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4878     { "(bad)",  { XX } },
4879   },
4880
4881   /* PREFIX_VEX_3A04 */
4882   {
4883     { "(bad)",  { XX } },
4884     { "(bad)",  { XX } },
4885     { "vpermilps", { XM, EXx, Ib } },
4886     { "(bad)",  { XX } },
4887   },
4888
4889   /* PREFIX_VEX_3A05 */
4890   {
4891     { "(bad)",  { XX } },
4892     { "(bad)",  { XX } },
4893     { "vpermilpd", { XM, EXx, Ib } },
4894     { "(bad)",  { XX } },
4895   },
4896
4897   /* PREFIX_VEX_3A06 */
4898   {
4899     { "(bad)",  { XX } },
4900     { "(bad)",  { XX } },
4901     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4902     { "(bad)",  { XX } },
4903   },
4904
4905   /* PREFIX_VEX_3A08 */
4906   {
4907     { "(bad)",  { XX } },
4908     { "(bad)",  { XX } },
4909     { "vroundps", { XM, EXx, Ib } },
4910     { "(bad)",  { XX } },
4911   },
4912
4913   /* PREFIX_VEX_3A09 */
4914   {
4915     { "(bad)",  { XX } },
4916     { "(bad)",  { XX } },
4917     { "vroundpd", { XM, EXx, Ib } },
4918     { "(bad)",  { XX } },
4919   },
4920
4921   /* PREFIX_VEX_3A0A */
4922   {
4923     { "(bad)",  { XX } },
4924     { "(bad)",  { XX } },
4925     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4926     { "(bad)",  { XX } },
4927   },
4928
4929   /* PREFIX_VEX_3A0B */
4930   {
4931     { "(bad)",  { XX } },
4932     { "(bad)",  { XX } },
4933     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4934     { "(bad)",  { XX } },
4935   },
4936
4937   /* PREFIX_VEX_3A0C */
4938   {
4939     { "(bad)",  { XX } },
4940     { "(bad)",  { XX } },
4941     { "vblendps", { XM, Vex, EXx, Ib } },
4942     { "(bad)",  { XX } },
4943   },
4944
4945   /* PREFIX_VEX_3A0D */
4946   {
4947     { "(bad)",  { XX } },
4948     { "(bad)",  { XX } },
4949     { "vblendpd", { XM, Vex, EXx, Ib } },
4950     { "(bad)",  { XX } },
4951   },
4952
4953   /* PREFIX_VEX_3A0E */
4954   {
4955     { "(bad)",  { XX } },
4956     { "(bad)",  { XX } },
4957     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4958     { "(bad)",  { XX } },
4959   },
4960
4961   /* PREFIX_VEX_3A0F */
4962   {
4963     { "(bad)",  { XX } },
4964     { "(bad)",  { XX } },
4965     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4966     { "(bad)",  { XX } },
4967   },
4968
4969   /* PREFIX_VEX_3A14 */
4970   {
4971     { "(bad)",  { XX } },
4972     { "(bad)",  { XX } },
4973     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4974     { "(bad)",  { XX } },
4975   },
4976
4977   /* PREFIX_VEX_3A15 */
4978   {
4979     { "(bad)",  { XX } },
4980     { "(bad)",  { XX } },
4981     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4982     { "(bad)",  { XX } },
4983   },
4984
4985   /* PREFIX_VEX_3A16 */
4986   {
4987     { "(bad)",  { XX } },
4988     { "(bad)",  { XX } },
4989     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4990     { "(bad)",  { XX } },
4991   },
4992
4993   /* PREFIX_VEX_3A17 */
4994   {
4995     { "(bad)",  { XX } },
4996     { "(bad)",  { XX } },
4997     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
4998     { "(bad)",  { XX } },
4999   },
5000
5001   /* PREFIX_VEX_3A18 */
5002   {
5003     { "(bad)",  { XX } },
5004     { "(bad)",  { XX } },
5005     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5006     { "(bad)",  { XX } },
5007   },
5008
5009   /* PREFIX_VEX_3A19 */
5010   {
5011     { "(bad)",  { XX } },
5012     { "(bad)",  { XX } },
5013     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5014     { "(bad)",  { XX } },
5015   },
5016
5017   /* PREFIX_VEX_3A20 */
5018   {
5019     { "(bad)",  { XX } },
5020     { "(bad)",  { XX } },
5021     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5022     { "(bad)",  { XX } },
5023   },
5024
5025   /* PREFIX_VEX_3A21 */
5026   {
5027     { "(bad)",  { XX } },
5028     { "(bad)",  { XX } },
5029     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5030     { "(bad)",  { XX } },
5031   },
5032
5033   /* PREFIX_VEX_3A22 */
5034   {
5035     { "(bad)",  { XX } },
5036     { "(bad)",  { XX } },
5037     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5038     { "(bad)",  { XX } },
5039   },
5040
5041   /* PREFIX_VEX_3A40 */
5042   {
5043     { "(bad)",  { XX } },
5044     { "(bad)",  { XX } },
5045     { "vdpps",  { XM, Vex, EXx, Ib } },
5046     { "(bad)",  { XX } },
5047   },
5048
5049   /* PREFIX_VEX_3A41 */
5050   {
5051     { "(bad)",  { XX } },
5052     { "(bad)",  { XX } },
5053     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5054     { "(bad)",  { XX } },
5055   },
5056
5057   /* PREFIX_VEX_3A42 */
5058   {
5059     { "(bad)",  { XX } },
5060     { "(bad)",  { XX } },
5061     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5062     { "(bad)",  { XX } },
5063   },
5064
5065   /* PREFIX_VEX_3A44 */
5066   {
5067     { "(bad)",  { XX } },
5068     { "(bad)",  { XX } },
5069     { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5070     { "(bad)",  { XX } },
5071   },
5072
5073   /* PREFIX_VEX_3A4A */
5074   {
5075     { "(bad)",  { XX } },
5076     { "(bad)",  { XX } },
5077     { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
5078     { "(bad)",  { XX } },
5079   },
5080
5081   /* PREFIX_VEX_3A4B */
5082   {
5083     { "(bad)",  { XX } },
5084     { "(bad)",  { XX } },
5085     { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
5086     { "(bad)",  { XX } },
5087   },
5088
5089   /* PREFIX_VEX_3A4C */
5090   {
5091     { "(bad)",  { XX } },
5092     { "(bad)",  { XX } },
5093     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5094     { "(bad)",  { XX } },
5095   },
5096
5097   /* PREFIX_VEX_3A5C */
5098   {
5099     { "(bad)",  { XX } },
5100     { "(bad)",  { XX } },
5101     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5102     { "(bad)",  { XX } },
5103   },
5104
5105   /* PREFIX_VEX_3A5D */
5106   {
5107     { "(bad)",  { XX } },
5108     { "(bad)",  { XX } },
5109     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5110     { "(bad)",  { XX } },
5111   },
5112
5113   /* PREFIX_VEX_3A5E */
5114   {
5115     { "(bad)",  { XX } },
5116     { "(bad)",  { XX } },
5117     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5118     { "(bad)",  { XX } },
5119   },
5120
5121   /* PREFIX_VEX_3A5F */
5122   {
5123     { "(bad)",  { XX } },
5124     { "(bad)",  { XX } },
5125     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5126     { "(bad)",  { XX } },
5127   },
5128
5129   /* PREFIX_VEX_3A60 */
5130   {
5131     { "(bad)",  { XX } },
5132     { "(bad)",  { XX } },
5133     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5134     { "(bad)",  { XX } },
5135   },
5136
5137   /* PREFIX_VEX_3A61 */
5138   {
5139     { "(bad)",  { XX } },
5140     { "(bad)",  { XX } },
5141     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5142     { "(bad)",  { XX } },
5143   },
5144
5145   /* PREFIX_VEX_3A62 */
5146   {
5147     { "(bad)",  { XX } },
5148     { "(bad)",  { XX } },
5149     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5150     { "(bad)",  { XX } },
5151   },
5152
5153   /* PREFIX_VEX_3A63 */
5154   {
5155     { "(bad)",  { XX } },
5156     { "(bad)",  { XX } },
5157     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5158     { "(bad)",  { XX } },
5159   },
5160
5161   /* PREFIX_VEX_3A68 */
5162   {
5163     { "(bad)",  { XX } },
5164     { "(bad)",  { XX } },
5165     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5166     { "(bad)",  { XX } },
5167   },
5168
5169   /* PREFIX_VEX_3A69 */
5170   {
5171     { "(bad)",  { XX } },
5172     { "(bad)",  { XX } },
5173     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5174     { "(bad)",  { XX } },
5175   },
5176
5177   /* PREFIX_VEX_3A6A */
5178   {
5179     { "(bad)",  { XX } },
5180     { "(bad)",  { XX } },
5181     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5182     { "(bad)",  { XX } },
5183   },
5184
5185   /* PREFIX_VEX_3A6B */
5186   {
5187     { "(bad)",  { XX } },
5188     { "(bad)",  { XX } },
5189     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5190     { "(bad)",  { XX } },
5191   },
5192
5193   /* PREFIX_VEX_3A6C */
5194   {
5195     { "(bad)",  { XX } },
5196     { "(bad)",  { XX } },
5197     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5198     { "(bad)",  { XX } },
5199   },
5200
5201   /* PREFIX_VEX_3A6D */
5202   {
5203     { "(bad)",  { XX } },
5204     { "(bad)",  { XX } },
5205     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5206     { "(bad)",  { XX } },
5207   },
5208
5209   /* PREFIX_VEX_3A6E */
5210   {
5211     { "(bad)",  { XX } },
5212     { "(bad)",  { XX } },
5213     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5214     { "(bad)",  { XX } },
5215   },
5216
5217   /* PREFIX_VEX_3A6F */
5218   {
5219     { "(bad)",  { XX } },
5220     { "(bad)",  { XX } },
5221     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5222     { "(bad)",  { XX } },
5223   },
5224
5225   /* PREFIX_VEX_3A78 */
5226   {
5227     { "(bad)",  { XX } },
5228     { "(bad)",  { XX } },
5229     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5230     { "(bad)",  { XX } },
5231   },
5232
5233   /* PREFIX_VEX_3A79 */
5234   {
5235     { "(bad)",  { XX } },
5236     { "(bad)",  { XX } },
5237     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5238     { "(bad)",  { XX } },
5239   },
5240
5241   /* PREFIX_VEX_3A7A */
5242   {
5243     { "(bad)",  { XX } },
5244     { "(bad)",  { XX } },
5245     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5246     { "(bad)",  { XX } },
5247   },
5248
5249   /* PREFIX_VEX_3A7B */
5250   {
5251     { "(bad)",  { XX } },
5252     { "(bad)",  { XX } },
5253     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5254     { "(bad)",  { XX } },
5255   },
5256
5257   /* PREFIX_VEX_3A7C */
5258   {
5259     { "(bad)",  { XX } },
5260     { "(bad)",  { XX } },
5261     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5262     { "(bad)",  { XX } },
5263   },
5264
5265   /* PREFIX_VEX_3A7D */
5266   {
5267     { "(bad)",  { XX } },
5268     { "(bad)",  { XX } },
5269     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5270     { "(bad)",  { XX } },
5271   },
5272
5273   /* PREFIX_VEX_3A7E */
5274   {
5275     { "(bad)",  { XX } },
5276     { "(bad)",  { XX } },
5277     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5278     { "(bad)",  { XX } },
5279   },
5280
5281   /* PREFIX_VEX_3A7F */
5282   {
5283     { "(bad)",  { XX } },
5284     { "(bad)",  { XX } },
5285     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5286     { "(bad)",  { XX } },
5287   },
5288
5289   /* PREFIX_VEX_3ADF */
5290   {
5291     { "(bad)",  { XX } },
5292     { "(bad)",  { XX } },
5293     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5294     { "(bad)",  { XX } },
5295   },
5296 };
5297
5298 static const struct dis386 x86_64_table[][2] = {
5299   /* X86_64_06 */
5300   {
5301     { "push{T|}", { es } },
5302     { "(bad)", { XX } },
5303   },
5304
5305   /* X86_64_07 */
5306   {
5307     { "pop{T|}", { es } },
5308     { "(bad)", { XX } },
5309   },
5310
5311   /* X86_64_0D */
5312   {
5313     { "push{T|}", { cs } },
5314     { "(bad)", { XX } },
5315   },
5316
5317   /* X86_64_16 */
5318   {
5319     { "push{T|}", { ss } },
5320     { "(bad)", { XX } },
5321   },
5322
5323   /* X86_64_17 */
5324   {
5325     { "pop{T|}", { ss } },
5326     { "(bad)", { XX } },
5327   },
5328
5329   /* X86_64_1E */
5330   {
5331     { "push{T|}", { ds } },
5332     { "(bad)", { XX } },
5333   },
5334
5335   /* X86_64_1F */
5336   {
5337     { "pop{T|}", { ds } },
5338     { "(bad)", { XX } },
5339   },
5340
5341   /* X86_64_27 */
5342   {
5343     { "daa", { XX } },
5344     { "(bad)", { XX } },
5345   },
5346
5347   /* X86_64_2F */
5348   {
5349     { "das", { XX } },
5350     { "(bad)", { XX } },
5351   },
5352
5353   /* X86_64_37 */
5354   {
5355     { "aaa", { XX } },
5356     { "(bad)", { XX } },
5357   },
5358
5359   /* X86_64_3F */
5360   {
5361     { "aas", { XX } },
5362     { "(bad)", { XX } },
5363   },
5364
5365   /* X86_64_60 */
5366   {
5367     { "pusha{P|}", { XX } },
5368     { "(bad)", { XX } },
5369   },
5370
5371   /* X86_64_61 */
5372   {
5373     { "popa{P|}", { XX } },
5374     { "(bad)", { XX } },
5375   },
5376
5377   /* X86_64_62 */
5378   {
5379     { MOD_TABLE (MOD_62_32BIT) },
5380     { "(bad)", { XX } },
5381   },
5382
5383   /* X86_64_63 */
5384   {
5385     { "arpl", { Ew, Gw } },
5386     { "movs{lq|xd}", { Gv, Ed } },
5387   },
5388
5389   /* X86_64_6D */
5390   {
5391     { "ins{R|}", { Yzr, indirDX } },
5392     { "ins{G|}", { Yzr, indirDX } },
5393   },
5394
5395   /* X86_64_6F */
5396   {
5397     { "outs{R|}", { indirDXr, Xz } },
5398     { "outs{G|}", { indirDXr, Xz } },
5399   },
5400
5401   /* X86_64_9A */
5402   {
5403     { "Jcall{T|}", { Ap } },
5404     { "(bad)", { XX } },
5405   },
5406
5407   /* X86_64_C4 */
5408   {
5409     { MOD_TABLE (MOD_C4_32BIT) },
5410     { VEX_C4_TABLE (VEX_0F) },
5411   },
5412
5413   /* X86_64_C5 */
5414   {
5415     { MOD_TABLE (MOD_C5_32BIT) },
5416     { VEX_C5_TABLE (VEX_0F) },
5417   },
5418
5419   /* X86_64_CE */
5420   {
5421     { "into", { XX } },
5422     { "(bad)", { XX } },
5423   },
5424
5425   /* X86_64_D4 */
5426   {
5427     { "aam", { sIb } },
5428     { "(bad)", { XX } },
5429   },
5430
5431   /* X86_64_D5 */
5432   {
5433     { "aad", { sIb } },
5434     { "(bad)", { XX } },
5435   },
5436
5437   /* X86_64_EA */
5438   {
5439     { "Jjmp{T|}", { Ap } },
5440     { "(bad)", { XX } },
5441   },
5442
5443   /* X86_64_0F01_REG_0 */
5444   {
5445     { "sgdt{Q|IQ}", { M } },
5446     { "sgdt", { M } },
5447   },
5448
5449   /* X86_64_0F01_REG_1 */
5450   {
5451     { "sidt{Q|IQ}", { M } },
5452     { "sidt", { M } },
5453   },
5454
5455   /* X86_64_0F01_REG_2 */
5456   {
5457     { "lgdt{Q|Q}", { M } },
5458     { "lgdt", { M } },
5459   },
5460
5461   /* X86_64_0F01_REG_3 */
5462   {
5463     { "lidt{Q|Q}", { M } },
5464     { "lidt", { M } },
5465   },
5466 };
5467
5468 static const struct dis386 three_byte_table[][256] = {
5469
5470   /* THREE_BYTE_0F38 */
5471   {
5472     /* 00 */
5473     { "pshufb",         { MX, EM } },
5474     { "phaddw",         { MX, EM } },
5475     { "phaddd",         { MX, EM } },
5476     { "phaddsw",        { MX, EM } },
5477     { "pmaddubsw",      { MX, EM } },
5478     { "phsubw",         { MX, EM } },
5479     { "phsubd",         { MX, EM } },
5480     { "phsubsw",        { MX, EM } },
5481     /* 08 */
5482     { "psignb",         { MX, EM } },
5483     { "psignw",         { MX, EM } },
5484     { "psignd",         { MX, EM } },
5485     { "pmulhrsw",       { MX, EM } },
5486     { "(bad)",          { XX } },
5487     { "(bad)",          { XX } },
5488     { "(bad)",          { XX } },
5489     { "(bad)",          { XX } },
5490     /* 10 */
5491     { PREFIX_TABLE (PREFIX_0F3810) },
5492     { "(bad)",          { XX } },
5493     { "(bad)",          { XX } },
5494     { "(bad)",          { XX } },
5495     { PREFIX_TABLE (PREFIX_0F3814) },
5496     { PREFIX_TABLE (PREFIX_0F3815) },
5497     { "(bad)",          { XX } },
5498     { PREFIX_TABLE (PREFIX_0F3817) },
5499     /* 18 */
5500     { "(bad)",          { XX } },
5501     { "(bad)",          { XX } },
5502     { "(bad)",          { XX } },
5503     { "(bad)",          { XX } },
5504     { "pabsb",          { MX, EM } },
5505     { "pabsw",          { MX, EM } },
5506     { "pabsd",          { MX, EM } },
5507     { "(bad)",          { XX } },
5508     /* 20 */
5509     { PREFIX_TABLE (PREFIX_0F3820) },
5510     { PREFIX_TABLE (PREFIX_0F3821) },
5511     { PREFIX_TABLE (PREFIX_0F3822) },
5512     { PREFIX_TABLE (PREFIX_0F3823) },
5513     { PREFIX_TABLE (PREFIX_0F3824) },
5514     { PREFIX_TABLE (PREFIX_0F3825) },
5515     { "(bad)",          { XX } },
5516     { "(bad)",          { XX } },
5517     /* 28 */
5518     { PREFIX_TABLE (PREFIX_0F3828) },
5519     { PREFIX_TABLE (PREFIX_0F3829) },
5520     { PREFIX_TABLE (PREFIX_0F382A) },
5521     { PREFIX_TABLE (PREFIX_0F382B) },
5522     { "(bad)",          { XX } },
5523     { "(bad)",          { XX } },
5524     { "(bad)",          { XX } },
5525     { "(bad)",          { XX } },
5526     /* 30 */
5527     { PREFIX_TABLE (PREFIX_0F3830) },
5528     { PREFIX_TABLE (PREFIX_0F3831) },
5529     { PREFIX_TABLE (PREFIX_0F3832) },
5530     { PREFIX_TABLE (PREFIX_0F3833) },
5531     { PREFIX_TABLE (PREFIX_0F3834) },
5532     { PREFIX_TABLE (PREFIX_0F3835) },
5533     { "(bad)",          { XX } },
5534     { PREFIX_TABLE (PREFIX_0F3837) },
5535     /* 38 */
5536     { PREFIX_TABLE (PREFIX_0F3838) },
5537     { PREFIX_TABLE (PREFIX_0F3839) },
5538     { PREFIX_TABLE (PREFIX_0F383A) },
5539     { PREFIX_TABLE (PREFIX_0F383B) },
5540     { PREFIX_TABLE (PREFIX_0F383C) },
5541     { PREFIX_TABLE (PREFIX_0F383D) },
5542     { PREFIX_TABLE (PREFIX_0F383E) },
5543     { PREFIX_TABLE (PREFIX_0F383F) },
5544     /* 40 */
5545     { PREFIX_TABLE (PREFIX_0F3840) },
5546     { PREFIX_TABLE (PREFIX_0F3841) },
5547     { "(bad)",          { XX } },
5548     { "(bad)",          { XX } },
5549     { "(bad)",          { XX } },
5550     { "(bad)",          { XX } },
5551     { "(bad)",          { XX } },
5552     { "(bad)",          { XX } },
5553     /* 48 */
5554     { "(bad)",          { XX } },
5555     { "(bad)",          { XX } },
5556     { "(bad)",          { XX } },
5557     { "(bad)",          { XX } },
5558     { "(bad)",          { XX } },
5559     { "(bad)",          { XX } },
5560     { "(bad)",          { XX } },
5561     { "(bad)",          { XX } },
5562     /* 50 */
5563     { "(bad)",          { XX } },
5564     { "(bad)",          { XX } },
5565     { "(bad)",          { XX } },
5566     { "(bad)",          { XX } },
5567     { "(bad)",          { XX } },
5568     { "(bad)",          { XX } },
5569     { "(bad)",          { XX } },
5570     { "(bad)",          { XX } },
5571     /* 58 */
5572     { "(bad)",          { XX } },
5573     { "(bad)",          { XX } },
5574     { "(bad)",          { XX } },
5575     { "(bad)",          { XX } },
5576     { "(bad)",          { XX } },
5577     { "(bad)",          { XX } },
5578     { "(bad)",          { XX } },
5579     { "(bad)",          { XX } },
5580     /* 60 */
5581     { "(bad)",          { XX } },
5582     { "(bad)",          { XX } },
5583     { "(bad)",          { XX } },
5584     { "(bad)",          { XX } },
5585     { "(bad)",          { XX } },
5586     { "(bad)",          { XX } },
5587     { "(bad)",          { XX } },
5588     { "(bad)",          { XX } },
5589     /* 68 */
5590     { "(bad)",          { XX } },
5591     { "(bad)",          { XX } },
5592     { "(bad)",          { XX } },
5593     { "(bad)",          { XX } },
5594     { "(bad)",          { XX } },
5595     { "(bad)",          { XX } },
5596     { "(bad)",          { XX } },
5597     { "(bad)",          { XX } },
5598     /* 70 */
5599     { "(bad)",          { XX } },
5600     { "(bad)",          { XX } },
5601     { "(bad)",          { XX } },
5602     { "(bad)",          { XX } },
5603     { "(bad)",          { XX } },
5604     { "(bad)",          { XX } },
5605     { "(bad)",          { XX } },
5606     { "(bad)",          { XX } },
5607     /* 78 */
5608     { "(bad)",          { XX } },
5609     { "(bad)",          { XX } },
5610     { "(bad)",          { XX } },
5611     { "(bad)",          { XX } },
5612     { "(bad)",          { XX } },
5613     { "(bad)",          { XX } },
5614     { "(bad)",          { XX } },
5615     { "(bad)",          { XX } },
5616     /* 80 */
5617     { PREFIX_TABLE (PREFIX_0F3880) },
5618     { PREFIX_TABLE (PREFIX_0F3881) },
5619     { "(bad)",          { XX } },
5620     { "(bad)",          { XX } },
5621     { "(bad)",          { XX } },
5622     { "(bad)",          { XX } },
5623     { "(bad)",          { XX } },
5624     { "(bad)",          { XX } },
5625     /* 88 */
5626     { "(bad)",          { XX } },
5627     { "(bad)",          { XX } },
5628     { "(bad)",          { XX } },
5629     { "(bad)",          { XX } },
5630     { "(bad)",          { XX } },
5631     { "(bad)",          { XX } },
5632     { "(bad)",          { XX } },
5633     { "(bad)",          { XX } },
5634     /* 90 */
5635     { "(bad)",          { XX } },
5636     { "(bad)",          { XX } },
5637     { "(bad)",          { XX } },
5638     { "(bad)",          { XX } },
5639     { "(bad)",          { XX } },
5640     { "(bad)",          { XX } },
5641     { "(bad)",          { XX } },
5642     { "(bad)",          { XX } },
5643     /* 98 */
5644     { "(bad)",          { XX } },
5645     { "(bad)",          { XX } },
5646     { "(bad)",          { XX } },
5647     { "(bad)",          { XX } },
5648     { "(bad)",          { XX } },
5649     { "(bad)",          { XX } },
5650     { "(bad)",          { XX } },
5651     { "(bad)",          { XX } },
5652     /* a0 */
5653     { "(bad)",          { XX } },
5654     { "(bad)",          { XX } },
5655     { "(bad)",          { XX } },
5656     { "(bad)",          { XX } },
5657     { "(bad)",          { XX } },
5658     { "(bad)",          { XX } },
5659     { "(bad)",          { XX } },
5660     { "(bad)",          { XX } },
5661     /* a8 */
5662     { "(bad)",          { XX } },
5663     { "(bad)",          { XX } },
5664     { "(bad)",          { XX } },
5665     { "(bad)",          { XX } },
5666     { "(bad)",          { XX } },
5667     { "(bad)",          { XX } },
5668     { "(bad)",          { XX } },
5669     { "(bad)",          { XX } },
5670     /* b0 */
5671     { "(bad)",          { XX } },
5672     { "(bad)",          { XX } },
5673     { "(bad)",          { XX } },
5674     { "(bad)",          { XX } },
5675     { "(bad)",          { XX } },
5676     { "(bad)",          { XX } },
5677     { "(bad)",          { XX } },
5678     { "(bad)",          { XX } },
5679     /* b8 */
5680     { "(bad)",          { XX } },
5681     { "(bad)",          { XX } },
5682     { "(bad)",          { XX } },
5683     { "(bad)",          { XX } },
5684     { "(bad)",          { XX } },
5685     { "(bad)",          { XX } },
5686     { "(bad)",          { XX } },
5687     { "(bad)",          { XX } },
5688     /* c0 */
5689     { "(bad)",          { XX } },
5690     { "(bad)",          { XX } },
5691     { "(bad)",          { XX } },
5692     { "(bad)",          { XX } },
5693     { "(bad)",          { XX } },
5694     { "(bad)",          { XX } },
5695     { "(bad)",          { XX } },
5696     { "(bad)",          { XX } },
5697     /* c8 */
5698     { "(bad)",          { XX } },
5699     { "(bad)",          { XX } },
5700     { "(bad)",          { XX } },
5701     { "(bad)",          { XX } },
5702     { "(bad)",          { XX } },
5703     { "(bad)",          { XX } },
5704     { "(bad)",          { XX } },
5705     { "(bad)",          { XX } },
5706     /* d0 */
5707     { "(bad)",          { XX } },
5708     { "(bad)",          { XX } },
5709     { "(bad)",          { XX } },
5710     { "(bad)",          { XX } },
5711     { "(bad)",          { XX } },
5712     { "(bad)",          { XX } },
5713     { "(bad)",          { XX } },
5714     { "(bad)",          { XX } },
5715     /* d8 */
5716     { "(bad)",          { XX } },
5717     { "(bad)",          { XX } },
5718     { "(bad)",          { XX } },
5719     { PREFIX_TABLE (PREFIX_0F38DB) },
5720     { PREFIX_TABLE (PREFIX_0F38DC) },
5721     { PREFIX_TABLE (PREFIX_0F38DD) },
5722     { PREFIX_TABLE (PREFIX_0F38DE) },
5723     { PREFIX_TABLE (PREFIX_0F38DF) },
5724     /* e0 */
5725     { "(bad)",          { XX } },
5726     { "(bad)",          { XX } },
5727     { "(bad)",          { XX } },
5728     { "(bad)",          { XX } },
5729     { "(bad)",          { XX } },
5730     { "(bad)",          { XX } },
5731     { "(bad)",          { XX } },
5732     { "(bad)",          { XX } },
5733     /* e8 */
5734     { "(bad)",          { XX } },
5735     { "(bad)",          { XX } },
5736     { "(bad)",          { XX } },
5737     { "(bad)",          { XX } },
5738     { "(bad)",          { XX } },
5739     { "(bad)",          { XX } },
5740     { "(bad)",          { XX } },
5741     { "(bad)",          { XX } },
5742     /* f0 */
5743     { PREFIX_TABLE (PREFIX_0F38F0) },
5744     { PREFIX_TABLE (PREFIX_0F38F1) },
5745     { "(bad)",          { XX } },
5746     { "(bad)",          { XX } },
5747     { "(bad)",          { XX } },
5748     { "(bad)",          { XX } },
5749     { "(bad)",          { XX } },
5750     { "(bad)",          { XX } },
5751     /* f8 */
5752     { "(bad)",          { XX } },
5753     { "(bad)",          { XX } },
5754     { "(bad)",          { XX } },
5755     { "(bad)",          { XX } },
5756     { "(bad)",          { XX } },
5757     { "(bad)",          { XX } },
5758     { "(bad)",          { XX } },
5759     { "(bad)",          { XX } },
5760   },
5761   /* THREE_BYTE_0F3A */
5762   {
5763     /* 00 */
5764     { "(bad)",          { XX } },
5765     { "(bad)",          { XX } },
5766     { "(bad)",          { XX } },
5767     { "(bad)",          { XX } },
5768     { "(bad)",          { XX } },
5769     { "(bad)",          { XX } },
5770     { "(bad)",          { XX } },
5771     { "(bad)",          { XX } },
5772     /* 08 */
5773     { PREFIX_TABLE (PREFIX_0F3A08) },
5774     { PREFIX_TABLE (PREFIX_0F3A09) },
5775     { PREFIX_TABLE (PREFIX_0F3A0A) },
5776     { PREFIX_TABLE (PREFIX_0F3A0B) },
5777     { PREFIX_TABLE (PREFIX_0F3A0C) },
5778     { PREFIX_TABLE (PREFIX_0F3A0D) },
5779     { PREFIX_TABLE (PREFIX_0F3A0E) },
5780     { "palignr",        { MX, EM, Ib } },
5781     /* 10 */
5782     { "(bad)",          { XX } },
5783     { "(bad)",          { XX } },
5784     { "(bad)",          { XX } },
5785     { "(bad)",          { XX } },
5786     { PREFIX_TABLE (PREFIX_0F3A14) },
5787     { PREFIX_TABLE (PREFIX_0F3A15) },
5788     { PREFIX_TABLE (PREFIX_0F3A16) },
5789     { PREFIX_TABLE (PREFIX_0F3A17) },
5790     /* 18 */
5791     { "(bad)",          { XX } },
5792     { "(bad)",          { XX } },
5793     { "(bad)",          { XX } },
5794     { "(bad)",          { XX } },
5795     { "(bad)",          { XX } },
5796     { "(bad)",          { XX } },
5797     { "(bad)",          { XX } },
5798     { "(bad)",          { XX } },
5799     /* 20 */
5800     { PREFIX_TABLE (PREFIX_0F3A20) },
5801     { PREFIX_TABLE (PREFIX_0F3A21) },
5802     { PREFIX_TABLE (PREFIX_0F3A22) },
5803     { "(bad)",          { XX } },
5804     { "(bad)",          { XX } },
5805     { "(bad)",          { XX } },
5806     { "(bad)",          { XX } },
5807     { "(bad)",          { XX } },
5808     /* 28 */
5809     { "(bad)",          { XX } },
5810     { "(bad)",          { XX } },
5811     { "(bad)",          { XX } },
5812     { "(bad)",          { XX } },
5813     { "(bad)",          { XX } },
5814     { "(bad)",          { XX } },
5815     { "(bad)",          { XX } },
5816     { "(bad)",          { XX } },
5817     /* 30 */
5818     { "(bad)",          { XX } },
5819     { "(bad)",          { XX } },
5820     { "(bad)",          { XX } },
5821     { "(bad)",          { XX } },
5822     { "(bad)",          { XX } },
5823     { "(bad)",          { XX } },
5824     { "(bad)",          { XX } },
5825     { "(bad)",          { XX } },
5826     /* 38 */
5827     { "(bad)",          { XX } },
5828     { "(bad)",          { XX } },
5829     { "(bad)",          { XX } },
5830     { "(bad)",          { XX } },
5831     { "(bad)",          { XX } },
5832     { "(bad)",          { XX } },
5833     { "(bad)",          { XX } },
5834     { "(bad)",          { XX } },
5835     /* 40 */
5836     { PREFIX_TABLE (PREFIX_0F3A40) },
5837     { PREFIX_TABLE (PREFIX_0F3A41) },
5838     { PREFIX_TABLE (PREFIX_0F3A42) },
5839     { "(bad)",          { XX } },
5840     { PREFIX_TABLE (PREFIX_0F3A44) },
5841     { "(bad)",          { XX } },
5842     { "(bad)",          { XX } },
5843     { "(bad)",          { XX } },
5844     /* 48 */
5845     { "(bad)",          { XX } },
5846     { "(bad)",          { XX } },
5847     { "(bad)",          { XX } },
5848     { "(bad)",          { XX } },
5849     { "(bad)",          { XX } },
5850     { "(bad)",          { XX } },
5851     { "(bad)",          { XX } },
5852     { "(bad)",          { XX } },
5853     /* 50 */
5854     { "(bad)",          { XX } },
5855     { "(bad)",          { XX } },
5856     { "(bad)",          { XX } },
5857     { "(bad)",          { XX } },
5858     { "(bad)",          { XX } },
5859     { "(bad)",          { XX } },
5860     { "(bad)",          { XX } },
5861     { "(bad)",          { XX } },
5862     /* 58 */
5863     { "(bad)",          { XX } },
5864     { "(bad)",          { XX } },
5865     { "(bad)",          { XX } },
5866     { "(bad)",          { XX } },
5867     { "(bad)",          { XX } },
5868     { "(bad)",          { XX } },
5869     { "(bad)",          { XX } },
5870     { "(bad)",          { XX } },
5871     /* 60 */
5872     { PREFIX_TABLE (PREFIX_0F3A60) },
5873     { PREFIX_TABLE (PREFIX_0F3A61) },
5874     { PREFIX_TABLE (PREFIX_0F3A62) },
5875     { PREFIX_TABLE (PREFIX_0F3A63) },
5876     { "(bad)",          { XX } },
5877     { "(bad)",          { XX } },
5878     { "(bad)",          { XX } },
5879     { "(bad)",          { XX } },
5880     /* 68 */
5881     { "(bad)",          { XX } },
5882     { "(bad)",          { XX } },
5883     { "(bad)",          { XX } },
5884     { "(bad)",          { XX } },
5885     { "(bad)",          { XX } },
5886     { "(bad)",          { XX } },
5887     { "(bad)",          { XX } },
5888     { "(bad)",          { XX } },
5889     /* 70 */
5890     { "(bad)",          { XX } },
5891     { "(bad)",          { XX } },
5892     { "(bad)",          { XX } },
5893     { "(bad)",          { XX } },
5894     { "(bad)",          { XX } },
5895     { "(bad)",          { XX } },
5896     { "(bad)",          { XX } },
5897     { "(bad)",          { XX } },
5898     /* 78 */
5899     { "(bad)",          { XX } },
5900     { "(bad)",          { XX } },
5901     { "(bad)",          { XX } },
5902     { "(bad)",          { XX } },
5903     { "(bad)",          { XX } },
5904     { "(bad)",          { XX } },
5905     { "(bad)",          { XX } },
5906     { "(bad)",          { XX } },
5907     /* 80 */
5908     { "(bad)",          { XX } },
5909     { "(bad)",          { XX } },
5910     { "(bad)",          { XX } },
5911     { "(bad)",          { XX } },
5912     { "(bad)",          { XX } },
5913     { "(bad)",          { XX } },
5914     { "(bad)",          { XX } },
5915     { "(bad)",          { XX } },
5916     /* 88 */
5917     { "(bad)",          { XX } },
5918     { "(bad)",          { XX } },
5919     { "(bad)",          { XX } },
5920     { "(bad)",          { XX } },
5921     { "(bad)",          { XX } },
5922     { "(bad)",          { XX } },
5923     { "(bad)",          { XX } },
5924     { "(bad)",          { XX } },
5925     /* 90 */
5926     { "(bad)",          { XX } },
5927     { "(bad)",          { XX } },
5928     { "(bad)",          { XX } },
5929     { "(bad)",          { XX } },
5930     { "(bad)",          { XX } },
5931     { "(bad)",          { XX } },
5932     { "(bad)",          { XX } },
5933     { "(bad)",          { XX } },
5934     /* 98 */
5935     { "(bad)",          { XX } },
5936     { "(bad)",          { XX } },
5937     { "(bad)",          { XX } },
5938     { "(bad)",          { XX } },
5939     { "(bad)",          { XX } },
5940     { "(bad)",          { XX } },
5941     { "(bad)",          { XX } },
5942     { "(bad)",          { XX } },
5943     /* a0 */
5944     { "(bad)",          { XX } },
5945     { "(bad)",          { XX } },
5946     { "(bad)",          { XX } },
5947     { "(bad)",          { XX } },
5948     { "(bad)",          { XX } },
5949     { "(bad)",          { XX } },
5950     { "(bad)",          { XX } },
5951     { "(bad)",          { XX } },
5952     /* a8 */
5953     { "(bad)",          { XX } },
5954     { "(bad)",          { XX } },
5955     { "(bad)",          { XX } },
5956     { "(bad)",          { XX } },
5957     { "(bad)",          { XX } },
5958     { "(bad)",          { XX } },
5959     { "(bad)",          { XX } },
5960     { "(bad)",          { XX } },
5961     /* b0 */
5962     { "(bad)",          { XX } },
5963     { "(bad)",          { XX } },
5964     { "(bad)",          { XX } },
5965     { "(bad)",          { XX } },
5966     { "(bad)",          { XX } },
5967     { "(bad)",          { XX } },
5968     { "(bad)",          { XX } },
5969     { "(bad)",          { XX } },
5970     /* b8 */
5971     { "(bad)",          { XX } },
5972     { "(bad)",          { XX } },
5973     { "(bad)",          { XX } },
5974     { "(bad)",          { XX } },
5975     { "(bad)",          { XX } },
5976     { "(bad)",          { XX } },
5977     { "(bad)",          { XX } },
5978     { "(bad)",          { XX } },
5979     /* c0 */
5980     { "(bad)",          { XX } },
5981     { "(bad)",          { XX } },
5982     { "(bad)",          { XX } },
5983     { "(bad)",          { XX } },
5984     { "(bad)",          { XX } },
5985     { "(bad)",          { XX } },
5986     { "(bad)",          { XX } },
5987     { "(bad)",          { XX } },
5988     /* c8 */
5989     { "(bad)",          { XX } },
5990     { "(bad)",          { XX } },
5991     { "(bad)",          { XX } },
5992     { "(bad)",          { XX } },
5993     { "(bad)",          { XX } },
5994     { "(bad)",          { XX } },
5995     { "(bad)",          { XX } },
5996     { "(bad)",          { XX } },
5997     /* d0 */
5998     { "(bad)",          { XX } },
5999     { "(bad)",          { XX } },
6000     { "(bad)",          { XX } },
6001     { "(bad)",          { XX } },
6002     { "(bad)",          { XX } },
6003     { "(bad)",          { XX } },
6004     { "(bad)",          { XX } },
6005     { "(bad)",          { XX } },
6006     /* d8 */
6007     { "(bad)",          { XX } },
6008     { "(bad)",          { XX } },
6009     { "(bad)",          { XX } },
6010     { "(bad)",          { XX } },
6011     { "(bad)",          { XX } },
6012     { "(bad)",          { XX } },
6013     { "(bad)",          { XX } },
6014     { PREFIX_TABLE (PREFIX_0F3ADF) },
6015     /* e0 */
6016     { "(bad)",          { XX } },
6017     { "(bad)",          { XX } },
6018     { "(bad)",          { XX } },
6019     { "(bad)",          { XX } },
6020     { "(bad)",          { XX } },
6021     { "(bad)",          { XX } },
6022     { "(bad)",          { XX } },
6023     { "(bad)",          { XX } },
6024     /* e8 */
6025     { "(bad)",          { XX } },
6026     { "(bad)",          { XX } },
6027     { "(bad)",          { XX } },
6028     { "(bad)",          { XX } },
6029     { "(bad)",          { XX } },
6030     { "(bad)",          { XX } },
6031     { "(bad)",          { XX } },
6032     { "(bad)",          { XX } },
6033     /* f0 */
6034     { "(bad)",          { XX } },
6035     { "(bad)",          { XX } },
6036     { "(bad)",          { XX } },
6037     { "(bad)",          { XX } },
6038     { "(bad)",          { XX } },
6039     { "(bad)",          { XX } },
6040     { "(bad)",          { XX } },
6041     { "(bad)",          { XX } },
6042     /* f8 */
6043     { "(bad)",          { XX } },
6044     { "(bad)",          { XX } },
6045     { "(bad)",          { XX } },
6046     { "(bad)",          { XX } },
6047     { "(bad)",          { XX } },
6048     { "(bad)",          { XX } },
6049     { "(bad)",          { XX } },
6050     { "(bad)",          { XX } },
6051   },
6052
6053   /* THREE_BYTE_0F7A */
6054   {
6055     /* 00 */
6056     { "(bad)",          { XX } },
6057     { "(bad)",          { XX } },
6058     { "(bad)",          { XX } },
6059     { "(bad)",          { XX } },
6060     { "(bad)",          { XX } },
6061     { "(bad)",          { XX } },
6062     { "(bad)",          { XX } },
6063     { "(bad)",          { XX } },
6064     /* 08 */
6065     { "(bad)",          { XX } },
6066     { "(bad)",          { XX } },
6067     { "(bad)",          { XX } },
6068     { "(bad)",          { XX } },
6069     { "(bad)",          { XX } },
6070     { "(bad)",          { XX } },
6071     { "(bad)",          { XX } },
6072     { "(bad)",          { XX } },
6073     /* 10 */
6074     { "(bad)",          { XX } },
6075     { "(bad)",          { XX } },
6076     { "(bad)",          { XX } },
6077     { "(bad)",          { XX } },
6078     { "(bad)",          { XX } },
6079     { "(bad)",          { XX } },
6080     { "(bad)",          { XX } },
6081     { "(bad)",          { XX } },
6082     /* 18 */
6083     { "(bad)",          { XX } },
6084     { "(bad)",          { XX } },
6085     { "(bad)",          { XX } },
6086     { "(bad)",          { XX } },
6087     { "(bad)",          { XX } },
6088     { "(bad)",          { XX } },
6089     { "(bad)",          { XX } },
6090     { "(bad)",          { XX } },
6091     /* 20 */
6092     { "ptest",          { XX } },
6093     { "(bad)",          { XX } },
6094     { "(bad)",          { XX } },
6095     { "(bad)",          { XX } },
6096     { "(bad)",          { XX } },
6097     { "(bad)",          { XX } },
6098     { "(bad)",          { XX } },
6099     { "(bad)",          { XX } },
6100     /* 28 */
6101     { "(bad)",          { XX } },
6102     { "(bad)",          { XX } },
6103     { "(bad)",          { XX } },
6104     { "(bad)",          { XX } },
6105     { "(bad)",          { XX } },
6106     { "(bad)",          { XX } },
6107     { "(bad)",          { XX } },
6108     { "(bad)",          { XX } },
6109     /* 30 */
6110     { "(bad)",          { XX } },
6111     { "(bad)",          { XX } },
6112     { "(bad)",          { XX } },
6113     { "(bad)",          { XX } },
6114     { "(bad)",          { XX } },
6115     { "(bad)",          { XX } },
6116     { "(bad)",          { XX } },
6117     { "(bad)",          { XX } },
6118     /* 38 */
6119     { "(bad)",          { XX } },
6120     { "(bad)",          { XX } },
6121     { "(bad)",          { XX } },
6122     { "(bad)",          { XX } },
6123     { "(bad)",          { XX } },
6124     { "(bad)",          { XX } },
6125     { "(bad)",          { XX } },
6126     { "(bad)",          { XX } },
6127     /* 40 */
6128     { "(bad)",          { XX } },
6129     { "phaddbw",        { XM, EXq } },
6130     { "phaddbd",        { XM, EXq } },
6131     { "phaddbq",        { XM, EXq } },
6132     { "(bad)",          { XX } },
6133     { "(bad)",          { XX } },
6134     { "phaddwd",        { XM, EXq } },
6135     { "phaddwq",        { XM, EXq } },
6136     /* 48 */
6137     { "(bad)",          { XX } },
6138     { "(bad)",          { XX } },
6139     { "(bad)",          { XX } },
6140     { "phadddq",        { XM, EXq } },
6141     { "(bad)",          { XX } },
6142     { "(bad)",          { XX } },
6143     { "(bad)",          { XX } },
6144     { "(bad)",          { XX } },
6145     /* 50 */
6146     { "(bad)",          { XX } },
6147     { "phaddubw",       { XM, EXq } },
6148     { "phaddubd",       { XM, EXq } },
6149     { "phaddubq",       { XM, EXq } },
6150     { "(bad)",          { XX } },
6151     { "(bad)",          { XX } },
6152     { "phadduwd",       { XM, EXq } },
6153     { "phadduwq",       { XM, EXq } },
6154     /* 58 */
6155     { "(bad)",          { XX } },
6156     { "(bad)",          { XX } },
6157     { "(bad)",          { XX } },
6158     { "phaddudq",       { XM, EXq } },
6159     { "(bad)",          { XX } },
6160     { "(bad)",          { XX } },
6161     { "(bad)",          { XX } },
6162     { "(bad)",          { XX } },
6163     /* 60 */
6164     { "(bad)",          { XX } },
6165     { "phsubbw",        { XM, EXq } },
6166     { "phsubbd",        { XM, EXq } },
6167     { "phsubbq",        { XM, EXq } },
6168     { "(bad)",          { XX } },
6169     { "(bad)",          { XX } },
6170     { "(bad)",          { XX } },
6171     { "(bad)",          { XX } },
6172     /* 68 */
6173     { "(bad)",          { XX } },
6174     { "(bad)",          { XX } },
6175     { "(bad)",          { XX } },
6176     { "(bad)",          { XX } },
6177     { "(bad)",          { XX } },
6178     { "(bad)",          { XX } },
6179     { "(bad)",          { XX } },
6180     { "(bad)",          { XX } },
6181     /* 70 */
6182     { "(bad)",          { XX } },
6183     { "(bad)",          { XX } },
6184     { "(bad)",          { XX } },
6185     { "(bad)",          { XX } },
6186     { "(bad)",          { XX } },
6187     { "(bad)",          { XX } },
6188     { "(bad)",          { XX } },
6189     { "(bad)",          { XX } },
6190     /* 78 */
6191     { "(bad)",          { XX } },
6192     { "(bad)",          { XX } },
6193     { "(bad)",          { XX } },
6194     { "(bad)",          { XX } },
6195     { "(bad)",          { XX } },
6196     { "(bad)",          { XX } },
6197     { "(bad)",          { XX } },
6198     { "(bad)",          { XX } },
6199     /* 80 */
6200     { "(bad)",          { XX } },
6201     { "(bad)",          { XX } },
6202     { "(bad)",          { XX } },
6203     { "(bad)",          { XX } },
6204     { "(bad)",          { XX } },
6205     { "(bad)",          { XX } },
6206     { "(bad)",          { XX } },
6207     { "(bad)",          { XX } },
6208     /* 88 */
6209     { "(bad)",          { XX } },
6210     { "(bad)",          { XX } },
6211     { "(bad)",          { XX } },
6212     { "(bad)",          { XX } },
6213     { "(bad)",          { XX } },
6214     { "(bad)",          { XX } },
6215     { "(bad)",          { XX } },
6216     { "(bad)",          { XX } },
6217     /* 90 */
6218     { "(bad)",          { XX } },
6219     { "(bad)",          { XX } },
6220     { "(bad)",          { XX } },
6221     { "(bad)",          { XX } },
6222     { "(bad)",          { XX } },
6223     { "(bad)",          { XX } },
6224     { "(bad)",          { XX } },
6225     { "(bad)",          { XX } },
6226     /* 98 */
6227     { "(bad)",          { XX } },
6228     { "(bad)",          { XX } },
6229     { "(bad)",          { XX } },
6230     { "(bad)",          { XX } },
6231     { "(bad)",          { XX } },
6232     { "(bad)",          { XX } },
6233     { "(bad)",          { XX } },
6234     { "(bad)",          { XX } },
6235     /* a0 */
6236     { "(bad)",          { XX } },
6237     { "(bad)",          { XX } },
6238     { "(bad)",          { XX } },
6239     { "(bad)",          { XX } },
6240     { "(bad)",          { XX } },
6241     { "(bad)",          { XX } },
6242     { "(bad)",          { XX } },
6243     { "(bad)",          { XX } },
6244     /* a8 */
6245     { "(bad)",          { XX } },
6246     { "(bad)",          { XX } },
6247     { "(bad)",          { XX } },
6248     { "(bad)",          { XX } },
6249     { "(bad)",          { XX } },
6250     { "(bad)",          { XX } },
6251     { "(bad)",          { XX } },
6252     { "(bad)",          { XX } },
6253     /* b0 */
6254     { "(bad)",          { XX } },
6255     { "(bad)",          { XX } },
6256     { "(bad)",          { XX } },
6257     { "(bad)",          { XX } },
6258     { "(bad)",          { XX } },
6259     { "(bad)",          { XX } },
6260     { "(bad)",          { XX } },
6261     { "(bad)",          { XX } },
6262     /* b8 */
6263     { "(bad)",          { XX } },
6264     { "(bad)",          { XX } },
6265     { "(bad)",          { XX } },
6266     { "(bad)",          { XX } },
6267     { "(bad)",          { XX } },
6268     { "(bad)",          { XX } },
6269     { "(bad)",          { XX } },
6270     { "(bad)",          { XX } },
6271     /* c0 */
6272     { "(bad)",          { XX } },
6273     { "(bad)",          { XX } },
6274     { "(bad)",          { XX } },
6275     { "(bad)",          { XX } },
6276     { "(bad)",          { XX } },
6277     { "(bad)",          { XX } },
6278     { "(bad)",          { XX } },
6279     { "(bad)",          { XX } },
6280     /* c8 */
6281     { "(bad)",          { XX } },
6282     { "(bad)",          { XX } },
6283     { "(bad)",          { XX } },
6284     { "(bad)",          { XX } },
6285     { "(bad)",          { XX } },
6286     { "(bad)",          { XX } },
6287     { "(bad)",          { XX } },
6288     { "(bad)",          { XX } },
6289     /* d0 */
6290     { "(bad)",          { XX } },
6291     { "(bad)",          { XX } },
6292     { "(bad)",          { XX } },
6293     { "(bad)",          { XX } },
6294     { "(bad)",          { XX } },
6295     { "(bad)",          { XX } },
6296     { "(bad)",          { XX } },
6297     { "(bad)",          { XX } },
6298     /* d8 */
6299     { "(bad)",          { XX } },
6300     { "(bad)",          { XX } },
6301     { "(bad)",          { XX } },
6302     { "(bad)",          { XX } },
6303     { "(bad)",          { XX } },
6304     { "(bad)",          { XX } },
6305     { "(bad)",          { XX } },
6306     { "(bad)",          { XX } },
6307     /* e0 */
6308     { "(bad)",          { XX } },
6309     { "(bad)",          { XX } },
6310     { "(bad)",          { XX } },
6311     { "(bad)",          { XX } },
6312     { "(bad)",          { XX } },
6313     { "(bad)",          { XX } },
6314     { "(bad)",          { XX } },
6315     { "(bad)",          { XX } },
6316     /* e8 */
6317     { "(bad)",          { XX } },
6318     { "(bad)",          { XX } },
6319     { "(bad)",          { XX } },
6320     { "(bad)",          { XX } },
6321     { "(bad)",          { XX } },
6322     { "(bad)",          { XX } },
6323     { "(bad)",          { XX } },
6324     { "(bad)",          { XX } },
6325     /* f0 */
6326     { "(bad)",          { XX } },
6327     { "(bad)",          { XX } },
6328     { "(bad)",          { XX } },
6329     { "(bad)",          { XX } },
6330     { "(bad)",          { XX } },
6331     { "(bad)",          { XX } },
6332     { "(bad)",          { XX } },
6333     { "(bad)",          { XX } },
6334     /* f8 */
6335     { "(bad)",          { XX } },
6336     { "(bad)",          { XX } },
6337     { "(bad)",          { XX } },
6338     { "(bad)",          { XX } },
6339     { "(bad)",          { XX } },
6340     { "(bad)",          { XX } },
6341     { "(bad)",          { XX } },
6342     { "(bad)",          { XX } },
6343   },
6344 };
6345
6346
6347 static const struct dis386 vex_table[][256] = {
6348   /* VEX_0F */
6349   {
6350     /* 00 */
6351     { "(bad)",          { XX } },
6352     { "(bad)",          { XX } },
6353     { "(bad)",          { XX } },
6354     { "(bad)",          { XX } },
6355     { "(bad)",          { XX } },
6356     { "(bad)",          { XX } },
6357     { "(bad)",          { XX } },
6358     { "(bad)",          { XX } },
6359     /* 08 */
6360     { "(bad)",          { XX } },
6361     { "(bad)",          { XX } },
6362     { "(bad)",          { XX } },
6363     { "(bad)",          { XX } },
6364     { "(bad)",          { XX } },
6365     { "(bad)",          { XX } },
6366     { "(bad)",          { XX } },
6367     { "(bad)",          { XX } },
6368     /* 10 */
6369     { PREFIX_TABLE (PREFIX_VEX_10) },
6370     { PREFIX_TABLE (PREFIX_VEX_11) },
6371     { PREFIX_TABLE (PREFIX_VEX_12) },
6372     { MOD_TABLE (MOD_VEX_13) },
6373     { "vunpcklpX",      { XM, Vex, EXx } },
6374     { "vunpckhpX",      { XM, Vex, EXx } },
6375     { PREFIX_TABLE (PREFIX_VEX_16) },
6376     { MOD_TABLE (MOD_VEX_17) },
6377     /* 18 */
6378     { "(bad)",          { XX } },
6379     { "(bad)",          { XX } },
6380     { "(bad)",          { XX } },
6381     { "(bad)",          { XX } },
6382     { "(bad)",          { XX } },
6383     { "(bad)",          { XX } },
6384     { "(bad)",          { XX } },
6385     { "(bad)",          { XX } },
6386     /* 20 */
6387     { "(bad)",          { XX } },
6388     { "(bad)",          { XX } },
6389     { "(bad)",          { XX } },
6390     { "(bad)",          { XX } },
6391     { "(bad)",          { XX } },
6392     { "(bad)",          { XX } },
6393     { "(bad)",          { XX } },
6394     { "(bad)",          { XX } },
6395     /* 28 */
6396     { "vmovapX",        { XM, EXx } },
6397     { "vmovapX",        { EXxS, XM } },
6398     { PREFIX_TABLE (PREFIX_VEX_2A) },
6399     { MOD_TABLE (MOD_VEX_2B) },
6400     { PREFIX_TABLE (PREFIX_VEX_2C) },
6401     { PREFIX_TABLE (PREFIX_VEX_2D) },
6402     { PREFIX_TABLE (PREFIX_VEX_2E) },
6403     { PREFIX_TABLE (PREFIX_VEX_2F) },
6404     /* 30 */
6405     { "(bad)",          { XX } },
6406     { "(bad)",          { XX } },
6407     { "(bad)",          { XX } },
6408     { "(bad)",          { XX } },
6409     { "(bad)",          { XX } },
6410     { "(bad)",          { XX } },
6411     { "(bad)",          { XX } },
6412     { "(bad)",          { XX } },
6413     /* 38 */
6414     { "(bad)",          { XX } },
6415     { "(bad)",          { XX } },
6416     { "(bad)",          { XX } },
6417     { "(bad)",          { XX } },
6418     { "(bad)",          { XX } },
6419     { "(bad)",          { XX } },
6420     { "(bad)",          { XX } },
6421     { "(bad)",          { XX } },
6422     /* 40 */
6423     { "(bad)",          { XX } },
6424     { "(bad)",          { XX } },
6425     { "(bad)",          { XX } },
6426     { "(bad)",          { XX } },
6427     { "(bad)",          { XX } },
6428     { "(bad)",          { XX } },
6429     { "(bad)",          { XX } },
6430     { "(bad)",          { XX } },
6431     /* 48 */
6432     { "(bad)",          { XX } },
6433     { "(bad)",          { XX } },
6434     { "(bad)",          { XX } },
6435     { "(bad)",          { XX } },
6436     { "(bad)",          { XX } },
6437     { "(bad)",          { XX } },
6438     { "(bad)",          { XX } },
6439     { "(bad)",          { XX } },
6440     /* 50 */
6441     { MOD_TABLE (MOD_VEX_51) },
6442     { PREFIX_TABLE (PREFIX_VEX_51) },
6443     { PREFIX_TABLE (PREFIX_VEX_52) },
6444     { PREFIX_TABLE (PREFIX_VEX_53) },
6445     { "vandpX",         { XM, Vex, EXx } },
6446     { "vandnpX",        { XM, Vex, EXx } },
6447     { "vorpX",          { XM, Vex, EXx } },
6448     { "vxorpX",         { XM, Vex, EXx } },
6449     /* 58 */
6450     { PREFIX_TABLE (PREFIX_VEX_58) },
6451     { PREFIX_TABLE (PREFIX_VEX_59) },
6452     { PREFIX_TABLE (PREFIX_VEX_5A) },
6453     { PREFIX_TABLE (PREFIX_VEX_5B) },
6454     { PREFIX_TABLE (PREFIX_VEX_5C) },
6455     { PREFIX_TABLE (PREFIX_VEX_5D) },
6456     { PREFIX_TABLE (PREFIX_VEX_5E) },
6457     { PREFIX_TABLE (PREFIX_VEX_5F) },
6458     /* 60 */
6459     { PREFIX_TABLE (PREFIX_VEX_60) },
6460     { PREFIX_TABLE (PREFIX_VEX_61) },
6461     { PREFIX_TABLE (PREFIX_VEX_62) },
6462     { PREFIX_TABLE (PREFIX_VEX_63) },
6463     { PREFIX_TABLE (PREFIX_VEX_64) },
6464     { PREFIX_TABLE (PREFIX_VEX_65) },
6465     { PREFIX_TABLE (PREFIX_VEX_66) },
6466     { PREFIX_TABLE (PREFIX_VEX_67) },
6467     /* 68 */
6468     { PREFIX_TABLE (PREFIX_VEX_68) },
6469     { PREFIX_TABLE (PREFIX_VEX_69) },
6470     { PREFIX_TABLE (PREFIX_VEX_6A) },
6471     { PREFIX_TABLE (PREFIX_VEX_6B) },
6472     { PREFIX_TABLE (PREFIX_VEX_6C) },
6473     { PREFIX_TABLE (PREFIX_VEX_6D) },
6474     { PREFIX_TABLE (PREFIX_VEX_6E) },
6475     { PREFIX_TABLE (PREFIX_VEX_6F) },
6476     /* 70 */
6477     { PREFIX_TABLE (PREFIX_VEX_70) },
6478     { REG_TABLE (REG_VEX_71) },
6479     { REG_TABLE (REG_VEX_72) },
6480     { REG_TABLE (REG_VEX_73) },
6481     { PREFIX_TABLE (PREFIX_VEX_74) },
6482     { PREFIX_TABLE (PREFIX_VEX_75) },
6483     { PREFIX_TABLE (PREFIX_VEX_76) },
6484     { PREFIX_TABLE (PREFIX_VEX_77) },
6485     /* 78 */
6486     { "(bad)",          { XX } },
6487     { "(bad)",          { XX } },
6488     { "(bad)",          { XX } },
6489     { "(bad)",          { XX } },
6490     { PREFIX_TABLE (PREFIX_VEX_7C) },
6491     { PREFIX_TABLE (PREFIX_VEX_7D) },
6492     { PREFIX_TABLE (PREFIX_VEX_7E) },
6493     { PREFIX_TABLE (PREFIX_VEX_7F) },
6494     /* 80 */
6495     { "(bad)",          { XX } },
6496     { "(bad)",          { XX } },
6497     { "(bad)",          { XX } },
6498     { "(bad)",          { XX } },
6499     { "(bad)",          { XX } },
6500     { "(bad)",          { XX } },
6501     { "(bad)",          { XX } },
6502     { "(bad)",          { XX } },
6503     /* 88 */
6504     { "(bad)",          { XX } },
6505     { "(bad)",          { XX } },
6506     { "(bad)",          { XX } },
6507     { "(bad)",          { XX } },
6508     { "(bad)",          { XX } },
6509     { "(bad)",          { XX } },
6510     { "(bad)",          { XX } },
6511     { "(bad)",          { XX } },
6512     /* 90 */
6513     { "(bad)",          { XX } },
6514     { "(bad)",          { XX } },
6515     { "(bad)",          { XX } },
6516     { "(bad)",          { XX } },
6517     { "(bad)",          { XX } },
6518     { "(bad)",          { XX } },
6519     { "(bad)",          { XX } },
6520     { "(bad)",          { XX } },
6521     /* 98 */
6522     { "(bad)",          { XX } },
6523     { "(bad)",          { XX } },
6524     { "(bad)",          { XX } },
6525     { "(bad)",          { XX } },
6526     { "(bad)",          { XX } },
6527     { "(bad)",          { XX } },
6528     { "(bad)",          { XX } },
6529     { "(bad)",          { XX } },
6530     /* a0 */
6531     { "(bad)",          { XX } },
6532     { "(bad)",          { XX } },
6533     { "(bad)",          { XX } },
6534     { "(bad)",          { XX } },
6535     { "(bad)",          { XX } },
6536     { "(bad)",          { XX } },
6537     { "(bad)",          { XX } },
6538     { "(bad)",          { XX } },
6539     /* a8 */
6540     { "(bad)",          { XX } },
6541     { "(bad)",          { XX } },
6542     { "(bad)",          { XX } },
6543     { "(bad)",          { XX } },
6544     { "(bad)",          { XX } },
6545     { "(bad)",          { XX } },
6546     { REG_TABLE (REG_VEX_AE) },
6547     { "(bad)",          { XX } },
6548     /* b0 */
6549     { "(bad)",          { XX } },
6550     { "(bad)",          { XX } },
6551     { "(bad)",          { XX } },
6552     { "(bad)",          { XX } },
6553     { "(bad)",          { XX } },
6554     { "(bad)",          { XX } },
6555     { "(bad)",          { XX } },
6556     { "(bad)",          { XX } },
6557     /* b8 */
6558     { "(bad)",          { XX } },
6559     { "(bad)",          { XX } },
6560     { "(bad)",          { XX } },
6561     { "(bad)",          { XX } },
6562     { "(bad)",          { XX } },
6563     { "(bad)",          { XX } },
6564     { "(bad)",          { XX } },
6565     { "(bad)",          { XX } },
6566     /* c0 */
6567     { "(bad)",          { XX } },
6568     { "(bad)",          { XX } },
6569     { PREFIX_TABLE (PREFIX_VEX_C2) },
6570     { "(bad)",          { XX } },
6571     { PREFIX_TABLE (PREFIX_VEX_C4) },
6572     { PREFIX_TABLE (PREFIX_VEX_C5) },
6573     { "vshufpX",        { XM, Vex, EXx, Ib } },
6574     { "(bad)",          { XX } },
6575     /* c8 */
6576     { "(bad)",          { XX } },
6577     { "(bad)",          { XX } },
6578     { "(bad)",          { XX } },
6579     { "(bad)",          { XX } },
6580     { "(bad)",          { XX } },
6581     { "(bad)",          { XX } },
6582     { "(bad)",          { XX } },
6583     { "(bad)",          { XX } },
6584     /* d0 */
6585     { PREFIX_TABLE (PREFIX_VEX_D0) },
6586     { PREFIX_TABLE (PREFIX_VEX_D1) },
6587     { PREFIX_TABLE (PREFIX_VEX_D2) },
6588     { PREFIX_TABLE (PREFIX_VEX_D3) },
6589     { PREFIX_TABLE (PREFIX_VEX_D4) },
6590     { PREFIX_TABLE (PREFIX_VEX_D5) },
6591     { PREFIX_TABLE (PREFIX_VEX_D6) },
6592     { PREFIX_TABLE (PREFIX_VEX_D7) },
6593     /* d8 */
6594     { PREFIX_TABLE (PREFIX_VEX_D8) },
6595     { PREFIX_TABLE (PREFIX_VEX_D9) },
6596     { PREFIX_TABLE (PREFIX_VEX_DA) },
6597     { PREFIX_TABLE (PREFIX_VEX_DB) },
6598     { PREFIX_TABLE (PREFIX_VEX_DC) },
6599     { PREFIX_TABLE (PREFIX_VEX_DD) },
6600     { PREFIX_TABLE (PREFIX_VEX_DE) },
6601     { PREFIX_TABLE (PREFIX_VEX_DF) },
6602     /* e0 */
6603     { PREFIX_TABLE (PREFIX_VEX_E0) },
6604     { PREFIX_TABLE (PREFIX_VEX_E1) },
6605     { PREFIX_TABLE (PREFIX_VEX_E2) },
6606     { PREFIX_TABLE (PREFIX_VEX_E3) },
6607     { PREFIX_TABLE (PREFIX_VEX_E4) },
6608     { PREFIX_TABLE (PREFIX_VEX_E5) },
6609     { PREFIX_TABLE (PREFIX_VEX_E6) },
6610     { PREFIX_TABLE (PREFIX_VEX_E7) },
6611     /* e8 */
6612     { PREFIX_TABLE (PREFIX_VEX_E8) },
6613     { PREFIX_TABLE (PREFIX_VEX_E9) },
6614     { PREFIX_TABLE (PREFIX_VEX_EA) },
6615     { PREFIX_TABLE (PREFIX_VEX_EB) },
6616     { PREFIX_TABLE (PREFIX_VEX_EC) },
6617     { PREFIX_TABLE (PREFIX_VEX_ED) },
6618     { PREFIX_TABLE (PREFIX_VEX_EE) },
6619     { PREFIX_TABLE (PREFIX_VEX_EF) },
6620     /* f0 */
6621     { PREFIX_TABLE (PREFIX_VEX_F0) },
6622     { PREFIX_TABLE (PREFIX_VEX_F1) },
6623     { PREFIX_TABLE (PREFIX_VEX_F2) },
6624     { PREFIX_TABLE (PREFIX_VEX_F3) },
6625     { PREFIX_TABLE (PREFIX_VEX_F4) },
6626     { PREFIX_TABLE (PREFIX_VEX_F5) },
6627     { PREFIX_TABLE (PREFIX_VEX_F6) },
6628     { PREFIX_TABLE (PREFIX_VEX_F7) },
6629     /* f8 */
6630     { PREFIX_TABLE (PREFIX_VEX_F8) },
6631     { PREFIX_TABLE (PREFIX_VEX_F9) },
6632     { PREFIX_TABLE (PREFIX_VEX_FA) },
6633     { PREFIX_TABLE (PREFIX_VEX_FB) },
6634     { PREFIX_TABLE (PREFIX_VEX_FC) },
6635     { PREFIX_TABLE (PREFIX_VEX_FD) },
6636     { PREFIX_TABLE (PREFIX_VEX_FE) },
6637     { "(bad)",          { XX } },
6638   },
6639   /* VEX_0F38 */
6640   {
6641     /* 00 */
6642     { PREFIX_TABLE (PREFIX_VEX_3800) },
6643     { PREFIX_TABLE (PREFIX_VEX_3801) },
6644     { PREFIX_TABLE (PREFIX_VEX_3802) },
6645     { PREFIX_TABLE (PREFIX_VEX_3803) },
6646     { PREFIX_TABLE (PREFIX_VEX_3804) },
6647     { PREFIX_TABLE (PREFIX_VEX_3805) },
6648     { PREFIX_TABLE (PREFIX_VEX_3806) },
6649     { PREFIX_TABLE (PREFIX_VEX_3807) },
6650     /* 08 */
6651     { PREFIX_TABLE (PREFIX_VEX_3808) },
6652     { PREFIX_TABLE (PREFIX_VEX_3809) },
6653     { PREFIX_TABLE (PREFIX_VEX_380A) },
6654     { PREFIX_TABLE (PREFIX_VEX_380B) },
6655     { PREFIX_TABLE (PREFIX_VEX_380C) },
6656     { PREFIX_TABLE (PREFIX_VEX_380D) },
6657     { PREFIX_TABLE (PREFIX_VEX_380E) },
6658     { PREFIX_TABLE (PREFIX_VEX_380F) },
6659     /* 10 */
6660     { "(bad)",          { XX } },
6661     { "(bad)",          { XX } },
6662     { "(bad)",          { XX } },
6663     { "(bad)",          { XX } },
6664     { "(bad)",          { XX } },
6665     { "(bad)",          { XX } },
6666     { "(bad)",          { XX } },
6667     { PREFIX_TABLE (PREFIX_VEX_3817) },
6668     /* 18 */
6669     { PREFIX_TABLE (PREFIX_VEX_3818) },
6670     { PREFIX_TABLE (PREFIX_VEX_3819) },
6671     { PREFIX_TABLE (PREFIX_VEX_381A) },
6672     { "(bad)",          { XX } },
6673     { PREFIX_TABLE (PREFIX_VEX_381C) },
6674     { PREFIX_TABLE (PREFIX_VEX_381D) },
6675     { PREFIX_TABLE (PREFIX_VEX_381E) },
6676     { "(bad)",          { XX } },
6677     /* 20 */
6678     { PREFIX_TABLE (PREFIX_VEX_3820) },
6679     { PREFIX_TABLE (PREFIX_VEX_3821) },
6680     { PREFIX_TABLE (PREFIX_VEX_3822) },
6681     { PREFIX_TABLE (PREFIX_VEX_3823) },
6682     { PREFIX_TABLE (PREFIX_VEX_3824) },
6683     { PREFIX_TABLE (PREFIX_VEX_3825) },
6684     { "(bad)",          { XX } },
6685     { "(bad)",          { XX } },
6686     /* 28 */
6687     { PREFIX_TABLE (PREFIX_VEX_3828) },
6688     { PREFIX_TABLE (PREFIX_VEX_3829) },
6689     { PREFIX_TABLE (PREFIX_VEX_382A) },
6690     { PREFIX_TABLE (PREFIX_VEX_382B) },
6691     { PREFIX_TABLE (PREFIX_VEX_382C) },
6692     { PREFIX_TABLE (PREFIX_VEX_382D) },
6693     { PREFIX_TABLE (PREFIX_VEX_382E) },
6694     { PREFIX_TABLE (PREFIX_VEX_382F) },
6695     /* 30 */
6696     { PREFIX_TABLE (PREFIX_VEX_3830) },
6697     { PREFIX_TABLE (PREFIX_VEX_3831) },
6698     { PREFIX_TABLE (PREFIX_VEX_3832) },
6699     { PREFIX_TABLE (PREFIX_VEX_3833) },
6700     { PREFIX_TABLE (PREFIX_VEX_3834) },
6701     { PREFIX_TABLE (PREFIX_VEX_3835) },
6702     { "(bad)",          { XX } },
6703     { PREFIX_TABLE (PREFIX_VEX_3837) },
6704     /* 38 */
6705     { PREFIX_TABLE (PREFIX_VEX_3838) },
6706     { PREFIX_TABLE (PREFIX_VEX_3839) },
6707     { PREFIX_TABLE (PREFIX_VEX_383A) },
6708     { PREFIX_TABLE (PREFIX_VEX_383B) },
6709     { PREFIX_TABLE (PREFIX_VEX_383C) },
6710     { PREFIX_TABLE (PREFIX_VEX_383D) },
6711     { PREFIX_TABLE (PREFIX_VEX_383E) },
6712     { PREFIX_TABLE (PREFIX_VEX_383F) },
6713     /* 40 */
6714     { PREFIX_TABLE (PREFIX_VEX_3840) },
6715     { PREFIX_TABLE (PREFIX_VEX_3841) },
6716     { "(bad)",          { XX } },
6717     { "(bad)",          { XX } },
6718     { "(bad)",          { XX } },
6719     { "(bad)",          { XX } },
6720     { "(bad)",          { XX } },
6721     { "(bad)",          { XX } },
6722     /* 48 */
6723     { "(bad)",          { XX } },
6724     { "(bad)",          { XX } },
6725     { "(bad)",          { XX } },
6726     { "(bad)",          { XX } },
6727     { "(bad)",          { XX } },
6728     { "(bad)",          { XX } },
6729     { "(bad)",          { XX } },
6730     { "(bad)",          { XX } },
6731     /* 50 */
6732     { "(bad)",          { XX } },
6733     { "(bad)",          { XX } },
6734     { "(bad)",          { XX } },
6735     { "(bad)",          { XX } },
6736     { "(bad)",          { XX } },
6737     { "(bad)",          { XX } },
6738     { "(bad)",          { XX } },
6739     { "(bad)",          { XX } },
6740     /* 58 */
6741     { "(bad)",          { XX } },
6742     { "(bad)",          { XX } },
6743     { "(bad)",          { XX } },
6744     { "(bad)",          { XX } },
6745     { "(bad)",          { XX } },
6746     { "(bad)",          { XX } },
6747     { "(bad)",          { XX } },
6748     { "(bad)",          { XX } },
6749     /* 60 */
6750     { "(bad)",          { XX } },
6751     { "(bad)",          { XX } },
6752     { "(bad)",          { XX } },
6753     { "(bad)",          { XX } },
6754     { "(bad)",          { XX } },
6755     { "(bad)",          { XX } },
6756     { "(bad)",          { XX } },
6757     { "(bad)",          { XX } },
6758     /* 68 */
6759     { "(bad)",          { XX } },
6760     { "(bad)",          { XX } },
6761     { "(bad)",          { XX } },
6762     { "(bad)",          { XX } },
6763     { "(bad)",          { XX } },
6764     { "(bad)",          { XX } },
6765     { "(bad)",          { XX } },
6766     { "(bad)",          { XX } },
6767     /* 70 */
6768     { "(bad)",          { XX } },
6769     { "(bad)",          { XX } },
6770     { "(bad)",          { XX } },
6771     { "(bad)",          { XX } },
6772     { "(bad)",          { XX } },
6773     { "(bad)",          { XX } },
6774     { "(bad)",          { XX } },
6775     { "(bad)",          { XX } },
6776     /* 78 */
6777     { "(bad)",          { XX } },
6778     { "(bad)",          { XX } },
6779     { "(bad)",          { XX } },
6780     { "(bad)",          { XX } },
6781     { "(bad)",          { XX } },
6782     { "(bad)",          { XX } },
6783     { "(bad)",          { XX } },
6784     { "(bad)",          { XX } },
6785     /* 80 */
6786     { "(bad)",          { XX } },
6787     { "(bad)",          { XX } },
6788     { "(bad)",          { XX } },
6789     { "(bad)",          { XX } },
6790     { "(bad)",          { XX } },
6791     { "(bad)",          { XX } },
6792     { "(bad)",          { XX } },
6793     { "(bad)",          { XX } },
6794     /* 88 */
6795     { "(bad)",          { XX } },
6796     { "(bad)",          { XX } },
6797     { "(bad)",          { XX } },
6798     { "(bad)",          { XX } },
6799     { "(bad)",          { XX } },
6800     { "(bad)",          { XX } },
6801     { "(bad)",          { XX } },
6802     { "(bad)",          { XX } },
6803     /* 90 */
6804     { "(bad)",          { XX } },
6805     { "(bad)",          { XX } },
6806     { "(bad)",          { XX } },
6807     { "(bad)",          { XX } },
6808     { "(bad)",          { XX } },
6809     { "(bad)",          { XX } },
6810     { PREFIX_TABLE (PREFIX_VEX_3896) },
6811     { PREFIX_TABLE (PREFIX_VEX_3897) },
6812     /* 98 */
6813     { PREFIX_TABLE (PREFIX_VEX_3898) },
6814     { PREFIX_TABLE (PREFIX_VEX_3899) },
6815     { PREFIX_TABLE (PREFIX_VEX_389A) },
6816     { PREFIX_TABLE (PREFIX_VEX_389B) },
6817     { PREFIX_TABLE (PREFIX_VEX_389C) },
6818     { PREFIX_TABLE (PREFIX_VEX_389D) },
6819     { PREFIX_TABLE (PREFIX_VEX_389E) },
6820     { PREFIX_TABLE (PREFIX_VEX_389F) },
6821     /* a0 */
6822     { "(bad)",          { XX } },
6823     { "(bad)",          { XX } },
6824     { "(bad)",          { XX } },
6825     { "(bad)",          { XX } },
6826     { "(bad)",          { XX } },
6827     { "(bad)",          { XX } },
6828     { PREFIX_TABLE (PREFIX_VEX_38A6) },
6829     { PREFIX_TABLE (PREFIX_VEX_38A7) },
6830     /* a8 */
6831     { PREFIX_TABLE (PREFIX_VEX_38A8) },
6832     { PREFIX_TABLE (PREFIX_VEX_38A9) },
6833     { PREFIX_TABLE (PREFIX_VEX_38AA) },
6834     { PREFIX_TABLE (PREFIX_VEX_38AB) },
6835     { PREFIX_TABLE (PREFIX_VEX_38AC) },
6836     { PREFIX_TABLE (PREFIX_VEX_38AD) },
6837     { PREFIX_TABLE (PREFIX_VEX_38AE) },
6838     { PREFIX_TABLE (PREFIX_VEX_38AF) },
6839     /* b0 */
6840     { "(bad)",          { XX } },
6841     { "(bad)",          { XX } },
6842     { "(bad)",          { XX } },
6843     { "(bad)",          { XX } },
6844     { "(bad)",          { XX } },
6845     { "(bad)",          { XX } },
6846     { PREFIX_TABLE (PREFIX_VEX_38B6) },
6847     { PREFIX_TABLE (PREFIX_VEX_38B7) },
6848     /* b8 */
6849     { PREFIX_TABLE (PREFIX_VEX_38B8) },
6850     { PREFIX_TABLE (PREFIX_VEX_38B9) },
6851     { PREFIX_TABLE (PREFIX_VEX_38BA) },
6852     { PREFIX_TABLE (PREFIX_VEX_38BB) },
6853     { PREFIX_TABLE (PREFIX_VEX_38BC) },
6854     { PREFIX_TABLE (PREFIX_VEX_38BD) },
6855     { PREFIX_TABLE (PREFIX_VEX_38BE) },
6856     { PREFIX_TABLE (PREFIX_VEX_38BF) },
6857     /* c0 */
6858     { "(bad)",          { XX } },
6859     { "(bad)",          { XX } },
6860     { "(bad)",          { XX } },
6861     { "(bad)",          { XX } },
6862     { "(bad)",          { XX } },
6863     { "(bad)",          { XX } },
6864     { "(bad)",          { XX } },
6865     { "(bad)",          { XX } },
6866     /* c8 */
6867     { "(bad)",          { XX } },
6868     { "(bad)",          { XX } },
6869     { "(bad)",          { XX } },
6870     { "(bad)",          { XX } },
6871     { "(bad)",          { XX } },
6872     { "(bad)",          { XX } },
6873     { "(bad)",          { XX } },
6874     { "(bad)",          { XX } },
6875     /* d0 */
6876     { "(bad)",          { XX } },
6877     { "(bad)",          { XX } },
6878     { "(bad)",          { XX } },
6879     { "(bad)",          { XX } },
6880     { "(bad)",          { XX } },
6881     { "(bad)",          { XX } },
6882     { "(bad)",          { XX } },
6883     { "(bad)",          { XX } },
6884     /* d8 */
6885     { "(bad)",          { XX } },
6886     { "(bad)",          { XX } },
6887     { "(bad)",          { XX } },
6888     { PREFIX_TABLE (PREFIX_VEX_38DB) },
6889     { PREFIX_TABLE (PREFIX_VEX_38DC) },
6890     { PREFIX_TABLE (PREFIX_VEX_38DD) },
6891     { PREFIX_TABLE (PREFIX_VEX_38DE) },
6892     { PREFIX_TABLE (PREFIX_VEX_38DF) },
6893     /* e0 */
6894     { "(bad)",          { XX } },
6895     { "(bad)",          { XX } },
6896     { "(bad)",          { XX } },
6897     { "(bad)",          { XX } },
6898     { "(bad)",          { XX } },
6899     { "(bad)",          { XX } },
6900     { "(bad)",          { XX } },
6901     { "(bad)",          { XX } },
6902     /* e8 */
6903     { "(bad)",          { XX } },
6904     { "(bad)",          { XX } },
6905     { "(bad)",          { XX } },
6906     { "(bad)",          { XX } },
6907     { "(bad)",          { XX } },
6908     { "(bad)",          { XX } },
6909     { "(bad)",          { XX } },
6910     { "(bad)",          { XX } },
6911     /* f0 */
6912     { "(bad)",          { XX } },
6913     { "(bad)",          { XX } },
6914     { "(bad)",          { XX } },
6915     { "(bad)",          { XX } },
6916     { "(bad)",          { XX } },
6917     { "(bad)",          { XX } },
6918     { "(bad)",          { XX } },
6919     { "(bad)",          { XX } },
6920     /* f8 */
6921     { "(bad)",          { XX } },
6922     { "(bad)",          { XX } },
6923     { "(bad)",          { XX } },
6924     { "(bad)",          { XX } },
6925     { "(bad)",          { XX } },
6926     { "(bad)",          { XX } },
6927     { "(bad)",          { XX } },
6928     { "(bad)",          { XX } },
6929   },
6930   /* VEX_0F3A */
6931   {
6932     /* 00 */
6933     { "(bad)",          { XX } },
6934     { "(bad)",          { XX } },
6935     { "(bad)",          { XX } },
6936     { "(bad)",          { XX } },
6937     { PREFIX_TABLE (PREFIX_VEX_3A04) },
6938     { PREFIX_TABLE (PREFIX_VEX_3A05) },
6939     { PREFIX_TABLE (PREFIX_VEX_3A06) },
6940     { "(bad)",          { XX } },
6941     /* 08 */
6942     { PREFIX_TABLE (PREFIX_VEX_3A08) },
6943     { PREFIX_TABLE (PREFIX_VEX_3A09) },
6944     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
6945     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
6946     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
6947     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
6948     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
6949     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
6950     /* 10 */
6951     { "(bad)",          { XX } },
6952     { "(bad)",          { XX } },
6953     { "(bad)",          { XX } },
6954     { "(bad)",          { XX } },
6955     { PREFIX_TABLE (PREFIX_VEX_3A14) },
6956     { PREFIX_TABLE (PREFIX_VEX_3A15) },
6957     { PREFIX_TABLE (PREFIX_VEX_3A16) },
6958     { PREFIX_TABLE (PREFIX_VEX_3A17) },
6959     /* 18 */
6960     { PREFIX_TABLE (PREFIX_VEX_3A18) },
6961     { PREFIX_TABLE (PREFIX_VEX_3A19) },
6962     { "(bad)",          { XX } },
6963     { "(bad)",          { XX } },
6964     { "(bad)",          { XX } },
6965     { "(bad)",          { XX } },
6966     { "(bad)",          { XX } },
6967     { "(bad)",          { XX } },
6968     /* 20 */
6969     { PREFIX_TABLE (PREFIX_VEX_3A20) },
6970     { PREFIX_TABLE (PREFIX_VEX_3A21) },
6971     { PREFIX_TABLE (PREFIX_VEX_3A22) },
6972     { "(bad)",          { XX } },
6973     { "(bad)",          { XX } },
6974     { "(bad)",          { XX } },
6975     { "(bad)",          { XX } },
6976     { "(bad)",          { XX } },
6977     /* 28 */
6978     { "(bad)",          { XX } },
6979     { "(bad)",          { XX } },
6980     { "(bad)",          { XX } },
6981     { "(bad)",          { XX } },
6982     { "(bad)",          { XX } },
6983     { "(bad)",          { XX } },
6984     { "(bad)",          { XX } },
6985     { "(bad)",          { XX } },
6986     /* 30 */
6987     { "(bad)",          { XX } },
6988     { "(bad)",          { XX } },
6989     { "(bad)",          { XX } },
6990     { "(bad)",          { XX } },
6991     { "(bad)",          { XX } },
6992     { "(bad)",          { XX } },
6993     { "(bad)",          { XX } },
6994     { "(bad)",          { XX } },
6995     /* 38 */
6996     { "(bad)",          { XX } },
6997     { "(bad)",          { XX } },
6998     { "(bad)",          { XX } },
6999     { "(bad)",          { XX } },
7000     { "(bad)",          { XX } },
7001     { "(bad)",          { XX } },
7002     { "(bad)",          { XX } },
7003     { "(bad)",          { XX } },
7004     /* 40 */
7005     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7006     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7007     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7008     { "(bad)",          { XX } },
7009     { PREFIX_TABLE (PREFIX_VEX_3A44) },
7010     { "(bad)",          { XX } },
7011     { "(bad)",          { XX } },
7012     { "(bad)",          { XX } },
7013     /* 48 */
7014     { "(bad)",          { XX } },
7015     { "(bad)",          { XX } },
7016     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7017     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7018     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7019     { "(bad)",          { XX } },
7020     { "(bad)",          { XX } },
7021     { "(bad)",          { XX } },
7022     /* 50 */
7023     { "(bad)",          { XX } },
7024     { "(bad)",          { XX } },
7025     { "(bad)",          { XX } },
7026     { "(bad)",          { XX } },
7027     { "(bad)",          { XX } },
7028     { "(bad)",          { XX } },
7029     { "(bad)",          { XX } },
7030     { "(bad)",          { XX } },
7031     /* 58 */
7032     { "(bad)",          { XX } },
7033     { "(bad)",          { XX } },
7034     { "(bad)",          { XX } },
7035     { "(bad)",          { XX } },
7036     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7037     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7038     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7039     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7040     /* 60 */
7041     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7042     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7043     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7044     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7045     { "(bad)",          { XX } },
7046     { "(bad)",          { XX } },
7047     { "(bad)",          { XX } },
7048     { "(bad)",          { XX } },
7049     /* 68 */
7050     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7051     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7052     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7053     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7054     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7055     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7056     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7057     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7058     /* 70 */
7059     { "(bad)",          { XX } },
7060     { "(bad)",          { XX } },
7061     { "(bad)",          { XX } },
7062     { "(bad)",          { XX } },
7063     { "(bad)",          { XX } },
7064     { "(bad)",          { XX } },
7065     { "(bad)",          { XX } },
7066     { "(bad)",          { XX } },
7067     /* 78 */
7068     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7069     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7070     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7071     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7072     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7073     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7074     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7075     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7076     /* 80 */
7077     { "(bad)",          { XX } },
7078     { "(bad)",          { XX } },
7079     { "(bad)",          { XX } },
7080     { "(bad)",          { XX } },
7081     { "(bad)",          { XX } },
7082     { "(bad)",          { XX } },
7083     { "(bad)",          { XX } },
7084     { "(bad)",          { XX } },
7085     /* 88 */
7086     { "(bad)",          { XX } },
7087     { "(bad)",          { XX } },
7088     { "(bad)",          { XX } },
7089     { "(bad)",          { XX } },
7090     { "(bad)",          { XX } },
7091     { "(bad)",          { XX } },
7092     { "(bad)",          { XX } },
7093     { "(bad)",          { XX } },
7094     /* 90 */
7095     { "(bad)",          { XX } },
7096     { "(bad)",          { XX } },
7097     { "(bad)",          { XX } },
7098     { "(bad)",          { XX } },
7099     { "(bad)",          { XX } },
7100     { "(bad)",          { XX } },
7101     { "(bad)",          { XX } },
7102     { "(bad)",          { XX } },
7103     /* 98 */
7104     { "(bad)",          { XX } },
7105     { "(bad)",          { XX } },
7106     { "(bad)",          { XX } },
7107     { "(bad)",          { XX } },
7108     { "(bad)",          { XX } },
7109     { "(bad)",          { XX } },
7110     { "(bad)",          { XX } },
7111     { "(bad)",          { XX } },
7112     /* a0 */
7113     { "(bad)",          { XX } },
7114     { "(bad)",          { XX } },
7115     { "(bad)",          { XX } },
7116     { "(bad)",          { XX } },
7117     { "(bad)",          { XX } },
7118     { "(bad)",          { XX } },
7119     { "(bad)",          { XX } },
7120     { "(bad)",          { XX } },
7121     /* a8 */
7122     { "(bad)",          { XX } },
7123     { "(bad)",          { XX } },
7124     { "(bad)",          { XX } },
7125     { "(bad)",          { XX } },
7126     { "(bad)",          { XX } },
7127     { "(bad)",          { XX } },
7128     { "(bad)",          { XX } },
7129     { "(bad)",          { XX } },
7130     /* b0 */
7131     { "(bad)",          { XX } },
7132     { "(bad)",          { XX } },
7133     { "(bad)",          { XX } },
7134     { "(bad)",          { XX } },
7135     { "(bad)",          { XX } },
7136     { "(bad)",          { XX } },
7137     { "(bad)",          { XX } },
7138     { "(bad)",          { XX } },
7139     /* b8 */
7140     { "(bad)",          { XX } },
7141     { "(bad)",          { XX } },
7142     { "(bad)",          { XX } },
7143     { "(bad)",          { XX } },
7144     { "(bad)",          { XX } },
7145     { "(bad)",          { XX } },
7146     { "(bad)",          { XX } },
7147     { "(bad)",          { XX } },
7148     /* c0 */
7149     { "(bad)",          { XX } },
7150     { "(bad)",          { XX } },
7151     { "(bad)",          { XX } },
7152     { "(bad)",          { XX } },
7153     { "(bad)",          { XX } },
7154     { "(bad)",          { XX } },
7155     { "(bad)",          { XX } },
7156     { "(bad)",          { XX } },
7157     /* c8 */
7158     { "(bad)",          { XX } },
7159     { "(bad)",          { XX } },
7160     { "(bad)",          { XX } },
7161     { "(bad)",          { XX } },
7162     { "(bad)",          { XX } },
7163     { "(bad)",          { XX } },
7164     { "(bad)",          { XX } },
7165     { "(bad)",          { XX } },
7166     /* d0 */
7167     { "(bad)",          { XX } },
7168     { "(bad)",          { XX } },
7169     { "(bad)",          { XX } },
7170     { "(bad)",          { XX } },
7171     { "(bad)",          { XX } },
7172     { "(bad)",          { XX } },
7173     { "(bad)",          { XX } },
7174     { "(bad)",          { XX } },
7175     /* d8 */
7176     { "(bad)",          { XX } },
7177     { "(bad)",          { XX } },
7178     { "(bad)",          { XX } },
7179     { "(bad)",          { XX } },
7180     { "(bad)",          { XX } },
7181     { "(bad)",          { XX } },
7182     { "(bad)",          { XX } },
7183     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
7184     /* e0 */
7185     { "(bad)",          { XX } },
7186     { "(bad)",          { XX } },
7187     { "(bad)",          { XX } },
7188     { "(bad)",          { XX } },
7189     { "(bad)",          { XX } },
7190     { "(bad)",          { XX } },
7191     { "(bad)",          { XX } },
7192     { "(bad)",          { XX } },
7193     /* e8 */
7194     { "(bad)",          { XX } },
7195     { "(bad)",          { XX } },
7196     { "(bad)",          { XX } },
7197     { "(bad)",          { XX } },
7198     { "(bad)",          { XX } },
7199     { "(bad)",          { XX } },
7200     { "(bad)",          { XX } },
7201     { "(bad)",          { XX } },
7202     /* f0 */
7203     { "(bad)",          { XX } },
7204     { "(bad)",          { XX } },
7205     { "(bad)",          { XX } },
7206     { "(bad)",          { XX } },
7207     { "(bad)",          { XX } },
7208     { "(bad)",          { XX } },
7209     { "(bad)",          { XX } },
7210     { "(bad)",          { XX } },
7211     /* f8 */
7212     { "(bad)",          { XX } },
7213     { "(bad)",          { XX } },
7214     { "(bad)",          { XX } },
7215     { "(bad)",          { XX } },
7216     { "(bad)",          { XX } },
7217     { "(bad)",          { XX } },
7218     { "(bad)",          { XX } },
7219     { "(bad)",          { XX } },
7220   },
7221 };
7222
7223 static const struct dis386 vex_len_table[][2] = {
7224   /* VEX_LEN_10_P_1 */
7225   {
7226     { "vmovss",         { XMVex, Vex128, EXd } },
7227     { "(bad)",          { XX } },
7228   },
7229
7230   /* VEX_LEN_10_P_3 */
7231   {
7232     { "vmovsd",         { XMVex, Vex128, EXq } },
7233     { "(bad)",          { XX } },
7234   },
7235
7236   /* VEX_LEN_11_P_1 */
7237   {
7238     { "vmovss",         { EXdVexS, Vex128, XM } },
7239     { "(bad)",          { XX } },
7240   },
7241
7242   /* VEX_LEN_11_P_3 */
7243   {
7244     { "vmovsd",         { EXqVexS, Vex128, XM } },
7245     { "(bad)",          { XX } },
7246   },
7247
7248   /* VEX_LEN_12_P_0_M_0 */
7249   {
7250     { "vmovlps",        { XM, Vex128, EXq } },
7251     { "(bad)",          { XX } },
7252   },
7253
7254   /* VEX_LEN_12_P_0_M_1 */
7255   {
7256     { "vmovhlps",       { XM, Vex128, EXq } },
7257     { "(bad)",          { XX } },
7258   },
7259
7260   /* VEX_LEN_12_P_2 */
7261   {
7262     { "vmovlpd",        { XM, Vex128, EXq } },
7263     { "(bad)",          { XX } },
7264   },
7265
7266   /* VEX_LEN_13_M_0 */
7267   {
7268     { "vmovlpX",        { EXq, XM } },
7269     { "(bad)",          { XX } },
7270   },
7271
7272   /* VEX_LEN_16_P_0_M_0 */
7273   {
7274     { "vmovhps",        { XM, Vex128, EXq } },
7275     { "(bad)",          { XX } },
7276   },
7277
7278   /* VEX_LEN_16_P_0_M_1 */
7279   {
7280     { "vmovlhps",       { XM, Vex128, EXq } },
7281     { "(bad)",          { XX } },
7282   },
7283
7284   /* VEX_LEN_16_P_2 */
7285   {
7286     { "vmovhpd",        { XM, Vex128, EXq } },
7287     { "(bad)",          { XX } },
7288   },
7289
7290   /* VEX_LEN_17_M_0 */
7291   {
7292     { "vmovhpX",        { EXq, XM } },
7293     { "(bad)",          { XX } },
7294   },
7295
7296   /* VEX_LEN_2A_P_1 */
7297   {
7298     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
7299     { "(bad)",          { XX } },
7300   },
7301
7302   /* VEX_LEN_2A_P_3 */
7303   {
7304     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
7305     { "(bad)",          { XX } },
7306   },
7307
7308   /* VEX_LEN_2C_P_1 */
7309   {
7310     { "vcvttss2siY",    { Gv, EXd } },
7311     { "(bad)",          { XX } },
7312   },
7313
7314   /* VEX_LEN_2C_P_3 */
7315   {
7316     { "vcvttsd2siY",    { Gv, EXq } },
7317     { "(bad)",          { XX } },
7318   },
7319
7320   /* VEX_LEN_2D_P_1 */
7321   {
7322     { "vcvtss2siY",     { Gv, EXd } },
7323     { "(bad)",          { XX } },
7324   },
7325
7326   /* VEX_LEN_2D_P_3 */
7327   {
7328     { "vcvtsd2siY",     { Gv, EXq } },
7329     { "(bad)",          { XX } },
7330   },
7331
7332   /* VEX_LEN_2E_P_0 */
7333   {
7334     { "vucomiss",       { XM, EXd } },
7335     { "(bad)",          { XX } },
7336   },
7337
7338   /* VEX_LEN_2E_P_2 */
7339   {
7340     { "vucomisd",       { XM, EXq } },
7341     { "(bad)",          { XX } },
7342   },
7343
7344   /* VEX_LEN_2F_P_0 */
7345   {
7346     { "vcomiss",        { XM, EXd } },
7347     { "(bad)",          { XX } },
7348   },
7349
7350   /* VEX_LEN_2F_P_2 */
7351   {
7352     { "vcomisd",        { XM, EXq } },
7353     { "(bad)",          { XX } },
7354   },
7355
7356   /* VEX_LEN_51_P_1 */
7357   {
7358     { "vsqrtss",        { XM, Vex128, EXd } },
7359     { "(bad)",          { XX } },
7360   },
7361
7362   /* VEX_LEN_51_P_3 */
7363   {
7364     { "vsqrtsd",        { XM, Vex128, EXq } },
7365     { "(bad)",          { XX } },
7366   },
7367
7368   /* VEX_LEN_52_P_1 */
7369   {
7370     { "vrsqrtss",       { XM, Vex128, EXd } },
7371     { "(bad)",          { XX } },
7372   },
7373
7374   /* VEX_LEN_53_P_1 */
7375   {
7376     { "vrcpss",         { XM, Vex128, EXd } },
7377     { "(bad)",          { XX } },
7378   },
7379
7380   /* VEX_LEN_58_P_1 */
7381   {
7382     { "vaddss",         { XM, Vex128, EXd } },
7383     { "(bad)",          { XX } },
7384   },
7385
7386   /* VEX_LEN_58_P_3 */
7387   {
7388     { "vaddsd",         { XM, Vex128, EXq } },
7389     { "(bad)",          { XX } },
7390   },
7391
7392   /* VEX_LEN_59_P_1 */
7393   {
7394     { "vmulss",         { XM, Vex128, EXd } },
7395     { "(bad)",          { XX } },
7396   },
7397
7398   /* VEX_LEN_59_P_3 */
7399   {
7400     { "vmulsd",         { XM, Vex128, EXq } },
7401     { "(bad)",          { XX } },
7402   },
7403
7404   /* VEX_LEN_5A_P_1 */
7405   {
7406     { "vcvtss2sd",      { XM, Vex128, EXd } },
7407     { "(bad)",          { XX } },
7408   },
7409
7410   /* VEX_LEN_5A_P_3 */
7411   {
7412     { "vcvtsd2ss",      { XM, Vex128, EXq } },
7413     { "(bad)",          { XX } },
7414   },
7415
7416   /* VEX_LEN_5C_P_1 */
7417   {
7418     { "vsubss",         { XM, Vex128, EXd } },
7419     { "(bad)",          { XX } },
7420   },
7421
7422   /* VEX_LEN_5C_P_3 */
7423   {
7424     { "vsubsd",         { XM, Vex128, EXq } },
7425     { "(bad)",          { XX } },
7426   },
7427
7428   /* VEX_LEN_5D_P_1 */
7429   {
7430     { "vminss",         { XM, Vex128, EXd } },
7431     { "(bad)",          { XX } },
7432   },
7433
7434   /* VEX_LEN_5D_P_3 */
7435   {
7436     { "vminsd",         { XM, Vex128, EXq } },
7437     { "(bad)",          { XX } },
7438   },
7439
7440   /* VEX_LEN_5E_P_1 */
7441   {
7442     { "vdivss",         { XM, Vex128, EXd } },
7443     { "(bad)",          { XX } },
7444   },
7445
7446   /* VEX_LEN_5E_P_3 */
7447   {
7448     { "vdivsd",         { XM, Vex128, EXq } },
7449     { "(bad)",          { XX } },
7450   },
7451
7452   /* VEX_LEN_5F_P_1 */
7453   {
7454     { "vmaxss",         { XM, Vex128, EXd } },
7455     { "(bad)",          { XX } },
7456   },
7457
7458   /* VEX_LEN_5F_P_3 */
7459   {
7460     { "vmaxsd",         { XM, Vex128, EXq } },
7461     { "(bad)",          { XX } },
7462   },
7463
7464   /* VEX_LEN_60_P_2 */
7465   {
7466     { "vpunpcklbw",     { XM, Vex128, EXx } },
7467     { "(bad)",          { XX } },
7468   },
7469
7470   /* VEX_LEN_61_P_2 */
7471   {
7472     { "vpunpcklwd",     { XM, Vex128, EXx } },
7473     { "(bad)",          { XX } },
7474   },
7475
7476   /* VEX_LEN_62_P_2 */
7477   {
7478     { "vpunpckldq",     { XM, Vex128, EXx } },
7479     { "(bad)",          { XX } },
7480   },
7481
7482   /* VEX_LEN_63_P_2 */
7483   {
7484     { "vpacksswb",      { XM, Vex128, EXx } },
7485     { "(bad)",          { XX } },
7486   },
7487
7488   /* VEX_LEN_64_P_2 */
7489   {
7490     { "vpcmpgtb",       { XM, Vex128, EXx } },
7491     { "(bad)",          { XX } },
7492   },
7493
7494   /* VEX_LEN_65_P_2 */
7495   {
7496     { "vpcmpgtw",       { XM, Vex128, EXx } },
7497     { "(bad)",          { XX } },
7498   },
7499
7500   /* VEX_LEN_66_P_2 */
7501   {
7502     { "vpcmpgtd",       { XM, Vex128, EXx } },
7503     { "(bad)",          { XX } },
7504   },
7505
7506   /* VEX_LEN_67_P_2 */
7507   {
7508     { "vpackuswb",      { XM, Vex128, EXx } },
7509     { "(bad)",          { XX } },
7510   },
7511
7512   /* VEX_LEN_68_P_2 */
7513   {
7514     { "vpunpckhbw",     { XM, Vex128, EXx } },
7515     { "(bad)",          { XX } },
7516   },
7517
7518   /* VEX_LEN_69_P_2 */
7519   {
7520     { "vpunpckhwd",     { XM, Vex128, EXx } },
7521     { "(bad)",          { XX } },
7522   },
7523
7524   /* VEX_LEN_6A_P_2 */
7525   {
7526     { "vpunpckhdq",     { XM, Vex128, EXx } },
7527     { "(bad)",          { XX } },
7528   },
7529
7530   /* VEX_LEN_6B_P_2 */
7531   {
7532     { "vpackssdw",      { XM, Vex128, EXx } },
7533     { "(bad)",          { XX } },
7534   },
7535
7536   /* VEX_LEN_6C_P_2 */
7537   {
7538     { "vpunpcklqdq",    { XM, Vex128, EXx } },
7539     { "(bad)",          { XX } },
7540   },
7541
7542   /* VEX_LEN_6D_P_2 */
7543   {
7544     { "vpunpckhqdq",    { XM, Vex128, EXx } },
7545     { "(bad)",          { XX } },
7546   },
7547
7548   /* VEX_LEN_6E_P_2 */
7549   {
7550     { "vmovK",          { XM, Edq } },
7551     { "(bad)",          { XX } },
7552   },
7553
7554   /* VEX_LEN_70_P_1 */
7555   {
7556     { "vpshufhw",       { XM, EXx, Ib } },
7557     { "(bad)",          { XX } },
7558   },
7559
7560   /* VEX_LEN_70_P_2 */
7561   {
7562     { "vpshufd",        { XM, EXx, Ib } },
7563     { "(bad)",          { XX } },
7564   },
7565
7566   /* VEX_LEN_70_P_3 */
7567   {
7568     { "vpshuflw",       { XM, EXx, Ib } },
7569     { "(bad)",          { XX } },
7570   },
7571
7572   /* VEX_LEN_71_R_2_P_2 */
7573   {
7574     { "vpsrlw",         { Vex128, XS, Ib } },
7575     { "(bad)",          { XX } },
7576   },
7577
7578   /* VEX_LEN_71_R_4_P_2 */
7579   {
7580     { "vpsraw",         { Vex128, XS, Ib } },
7581     { "(bad)",          { XX } },
7582   },
7583
7584   /* VEX_LEN_71_R_6_P_2 */
7585   {
7586     { "vpsllw",         { Vex128, XS, Ib } },
7587     { "(bad)",          { XX } },
7588   },
7589
7590   /* VEX_LEN_72_R_2_P_2 */
7591   {
7592     { "vpsrld",         { Vex128, XS, Ib } },
7593     { "(bad)",          { XX } },
7594   },
7595
7596   /* VEX_LEN_72_R_4_P_2 */
7597   {
7598     { "vpsrad",         { Vex128, XS, Ib } },
7599     { "(bad)",          { XX } },
7600   },
7601
7602   /* VEX_LEN_72_R_6_P_2 */
7603   {
7604     { "vpslld",         { Vex128, XS, Ib } },
7605     { "(bad)",          { XX } },
7606   },
7607
7608   /* VEX_LEN_73_R_2_P_2 */
7609   {
7610     { "vpsrlq",         { Vex128, XS, Ib } },
7611     { "(bad)",          { XX } },
7612   },
7613
7614   /* VEX_LEN_73_R_3_P_2 */
7615   {
7616     { "vpsrldq",        { Vex128, XS, Ib } },
7617     { "(bad)",          { XX } },
7618   },
7619
7620   /* VEX_LEN_73_R_6_P_2 */
7621   {
7622     { "vpsllq",         { Vex128, XS, Ib } },
7623     { "(bad)",          { XX } },
7624   },
7625
7626   /* VEX_LEN_73_R_7_P_2 */
7627   {
7628     { "vpslldq",        { Vex128, XS, Ib } },
7629     { "(bad)",          { XX } },
7630   },
7631
7632   /* VEX_LEN_74_P_2 */
7633   {
7634     { "vpcmpeqb",       { XM, Vex128, EXx } },
7635     { "(bad)",          { XX } },
7636   },
7637
7638   /* VEX_LEN_75_P_2 */
7639   {
7640     { "vpcmpeqw",       { XM, Vex128, EXx } },
7641     { "(bad)",          { XX } },
7642   },
7643
7644   /* VEX_LEN_76_P_2 */
7645   {
7646     { "vpcmpeqd",       { XM, Vex128, EXx } },
7647     { "(bad)",          { XX } },
7648   },
7649
7650   /* VEX_LEN_7E_P_1 */
7651   {
7652     { "vmovq",          { XM, EXq } },
7653     { "(bad)",          { XX } },
7654   },
7655
7656   /* VEX_LEN_7E_P_2 */
7657   {
7658     { "vmovK",          { Edq, XM } },
7659     { "(bad)",          { XX } },
7660   },
7661
7662   /* VEX_LEN_AE_R_2_M_0 */
7663   {
7664     { "vldmxcsr",       { Md } },
7665     { "(bad)",          { XX } },
7666   },
7667
7668   /* VEX_LEN_AE_R_3_M_0 */
7669   {
7670     { "vstmxcsr",       { Md } },
7671     { "(bad)",          { XX } },
7672   },
7673
7674   /* VEX_LEN_C2_P_1 */
7675   {
7676     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
7677     { "(bad)",          { XX } },
7678   },
7679
7680   /* VEX_LEN_C2_P_3 */
7681   {
7682     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
7683     { "(bad)",          { XX } },
7684   },
7685
7686   /* VEX_LEN_C4_P_2 */
7687   {
7688     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
7689     { "(bad)",          { XX } },
7690   },
7691
7692   /* VEX_LEN_C5_P_2 */
7693   {
7694     { "vpextrw",        { Gdq, XS, Ib } },
7695     { "(bad)",          { XX } },
7696   },
7697
7698   /* VEX_LEN_D1_P_2 */
7699   {
7700     { "vpsrlw",         { XM, Vex128, EXx } },
7701     { "(bad)",          { XX } },
7702   },
7703
7704   /* VEX_LEN_D2_P_2 */
7705   {
7706     { "vpsrld",         { XM, Vex128, EXx } },
7707     { "(bad)",          { XX } },
7708   },
7709
7710   /* VEX_LEN_D3_P_2 */
7711   {
7712     { "vpsrlq",         { XM, Vex128, EXx } },
7713     { "(bad)",          { XX } },
7714   },
7715
7716   /* VEX_LEN_D4_P_2 */
7717   {
7718     { "vpaddq",         { XM, Vex128, EXx } },
7719     { "(bad)",          { XX } },
7720   },
7721
7722   /* VEX_LEN_D5_P_2 */
7723   {
7724     { "vpmullw",        { XM, Vex128, EXx } },
7725     { "(bad)",          { XX } },
7726   },
7727
7728   /* VEX_LEN_D6_P_2 */
7729   {
7730     { "vmovq",          { EXqS, XM } },
7731     { "(bad)",          { XX } },
7732   },
7733
7734   /* VEX_LEN_D7_P_2_M_1 */
7735   {
7736     { "vpmovmskb",      { Gdq, XS } },
7737     { "(bad)",          { XX } },
7738   },
7739
7740   /* VEX_LEN_D8_P_2 */
7741   {
7742     { "vpsubusb",       { XM, Vex128, EXx } },
7743     { "(bad)",          { XX } },
7744   },
7745
7746   /* VEX_LEN_D9_P_2 */
7747   {
7748     { "vpsubusw",       { XM, Vex128, EXx } },
7749     { "(bad)",          { XX } },
7750   },
7751
7752   /* VEX_LEN_DA_P_2 */
7753   {
7754     { "vpminub",        { XM, Vex128, EXx } },
7755     { "(bad)",          { XX } },
7756   },
7757
7758   /* VEX_LEN_DB_P_2 */
7759   {
7760     { "vpand",          { XM, Vex128, EXx } },
7761     { "(bad)",          { XX } },
7762   },
7763
7764   /* VEX_LEN_DC_P_2 */
7765   {
7766     { "vpaddusb",       { XM, Vex128, EXx } },
7767     { "(bad)",          { XX } },
7768   },
7769
7770   /* VEX_LEN_DD_P_2 */
7771   {
7772     { "vpaddusw",       { XM, Vex128, EXx } },
7773     { "(bad)",          { XX } },
7774   },
7775
7776   /* VEX_LEN_DE_P_2 */
7777   {
7778     { "vpmaxub",        { XM, Vex128, EXx } },
7779     { "(bad)",          { XX } },
7780   },
7781
7782   /* VEX_LEN_DF_P_2 */
7783   {
7784     { "vpandn",         { XM, Vex128, EXx } },
7785     { "(bad)",          { XX } },
7786   },
7787
7788   /* VEX_LEN_E0_P_2 */
7789   {
7790     { "vpavgb",         { XM, Vex128, EXx } },
7791     { "(bad)",          { XX } },
7792   },
7793
7794   /* VEX_LEN_E1_P_2 */
7795   {
7796     { "vpsraw",         { XM, Vex128, EXx } },
7797     { "(bad)",          { XX } },
7798   },
7799
7800   /* VEX_LEN_E2_P_2 */
7801   {
7802     { "vpsrad",         { XM, Vex128, EXx } },
7803     { "(bad)",          { XX } },
7804   },
7805
7806   /* VEX_LEN_E3_P_2 */
7807   {
7808     { "vpavgw",         { XM, Vex128, EXx } },
7809     { "(bad)",          { XX } },
7810   },
7811
7812   /* VEX_LEN_E4_P_2 */
7813   {
7814     { "vpmulhuw",       { XM, Vex128, EXx } },
7815     { "(bad)",          { XX } },
7816   },
7817
7818   /* VEX_LEN_E5_P_2 */
7819   {
7820     { "vpmulhw",        { XM, Vex128, EXx } },
7821     { "(bad)",          { XX } },
7822   },
7823
7824   /* VEX_LEN_E8_P_2 */
7825   {
7826     { "vpsubsb",        { XM, Vex128, EXx } },
7827     { "(bad)",          { XX } },
7828   },
7829
7830   /* VEX_LEN_E9_P_2 */
7831   {
7832     { "vpsubsw",        { XM, Vex128, EXx } },
7833     { "(bad)",          { XX } },
7834   },
7835
7836   /* VEX_LEN_EA_P_2 */
7837   {
7838     { "vpminsw",        { XM, Vex128, EXx } },
7839     { "(bad)",          { XX } },
7840   },
7841
7842   /* VEX_LEN_EB_P_2 */
7843   {
7844     { "vpor",           { XM, Vex128, EXx } },
7845     { "(bad)",          { XX } },
7846   },
7847
7848   /* VEX_LEN_EC_P_2 */
7849   {
7850     { "vpaddsb",        { XM, Vex128, EXx } },
7851     { "(bad)",          { XX } },
7852   },
7853
7854   /* VEX_LEN_ED_P_2 */
7855   {
7856     { "vpaddsw",        { XM, Vex128, EXx } },
7857     { "(bad)",          { XX } },
7858   },
7859
7860   /* VEX_LEN_EE_P_2 */
7861   {
7862     { "vpmaxsw",        { XM, Vex128, EXx } },
7863     { "(bad)",          { XX } },
7864   },
7865
7866   /* VEX_LEN_EF_P_2 */
7867   {
7868     { "vpxor",          { XM, Vex128, EXx } },
7869     { "(bad)",          { XX } },
7870   },
7871
7872   /* VEX_LEN_F1_P_2 */
7873   {
7874     { "vpsllw",         { XM, Vex128, EXx } },
7875     { "(bad)",          { XX } },
7876   },
7877
7878   /* VEX_LEN_F2_P_2 */
7879   {
7880     { "vpslld",         { XM, Vex128, EXx } },
7881     { "(bad)",          { XX } },
7882   },
7883
7884   /* VEX_LEN_F3_P_2 */
7885   {
7886     { "vpsllq",         { XM, Vex128, EXx } },
7887     { "(bad)",          { XX } },
7888   },
7889
7890   /* VEX_LEN_F4_P_2 */
7891   {
7892     { "vpmuludq",       { XM, Vex128, EXx } },
7893     { "(bad)",          { XX } },
7894   },
7895
7896   /* VEX_LEN_F5_P_2 */
7897   {
7898     { "vpmaddwd",       { XM, Vex128, EXx } },
7899     { "(bad)",          { XX } },
7900   },
7901
7902   /* VEX_LEN_F6_P_2 */
7903   {
7904     { "vpsadbw",        { XM, Vex128, EXx } },
7905     { "(bad)",          { XX } },
7906   },
7907
7908   /* VEX_LEN_F7_P_2 */
7909   {
7910     { "vmaskmovdqu",    { XM, XS } },
7911     { "(bad)",          { XX } },
7912   },
7913
7914   /* VEX_LEN_F8_P_2 */
7915   {
7916     { "vpsubb",         { XM, Vex128, EXx } },
7917     { "(bad)",          { XX } },
7918   },
7919
7920   /* VEX_LEN_F9_P_2 */
7921   {
7922     { "vpsubw",         { XM, Vex128, EXx } },
7923     { "(bad)",          { XX } },
7924   },
7925
7926   /* VEX_LEN_FA_P_2 */
7927   {
7928     { "vpsubd",         { XM, Vex128, EXx } },
7929     { "(bad)",          { XX } },
7930   },
7931
7932   /* VEX_LEN_FB_P_2 */
7933   {
7934     { "vpsubq",         { XM, Vex128, EXx } },
7935     { "(bad)",          { XX } },
7936   },
7937
7938   /* VEX_LEN_FC_P_2 */
7939   {
7940     { "vpaddb",         { XM, Vex128, EXx } },
7941     { "(bad)",          { XX } },
7942   },
7943
7944   /* VEX_LEN_FD_P_2 */
7945   {
7946     { "vpaddw",         { XM, Vex128, EXx } },
7947     { "(bad)",          { XX } },
7948   },
7949
7950   /* VEX_LEN_FE_P_2 */
7951   {
7952     { "vpaddd",         { XM, Vex128, EXx } },
7953     { "(bad)",          { XX } },
7954   },
7955
7956   /* VEX_LEN_3800_P_2 */
7957   {
7958     { "vpshufb",        { XM, Vex128, EXx } },
7959     { "(bad)",          { XX } },
7960   },
7961
7962   /* VEX_LEN_3801_P_2 */
7963   {
7964     { "vphaddw",        { XM, Vex128, EXx } },
7965     { "(bad)",          { XX } },
7966   },
7967
7968   /* VEX_LEN_3802_P_2 */
7969   {
7970     { "vphaddd",        { XM, Vex128, EXx } },
7971     { "(bad)",          { XX } },
7972   },
7973
7974   /* VEX_LEN_3803_P_2 */
7975   {
7976     { "vphaddsw",       { XM, Vex128, EXx } },
7977     { "(bad)",          { XX } },
7978   },
7979
7980   /* VEX_LEN_3804_P_2 */
7981   {
7982     { "vpmaddubsw",     { XM, Vex128, EXx } },
7983     { "(bad)",          { XX } },
7984   },
7985
7986   /* VEX_LEN_3805_P_2 */
7987   {
7988     { "vphsubw",        { XM, Vex128, EXx } },
7989     { "(bad)",          { XX } },
7990   },
7991
7992   /* VEX_LEN_3806_P_2 */
7993   {
7994     { "vphsubd",        { XM, Vex128, EXx } },
7995     { "(bad)",          { XX } },
7996   },
7997
7998   /* VEX_LEN_3807_P_2 */
7999   {
8000     { "vphsubsw",       { XM, Vex128, EXx } },
8001     { "(bad)",          { XX } },
8002   },
8003
8004   /* VEX_LEN_3808_P_2 */
8005   {
8006     { "vpsignb",        { XM, Vex128, EXx } },
8007     { "(bad)",          { XX } },
8008   },
8009
8010   /* VEX_LEN_3809_P_2 */
8011   {
8012     { "vpsignw",        { XM, Vex128, EXx } },
8013     { "(bad)",          { XX } },
8014   },
8015
8016   /* VEX_LEN_380A_P_2 */
8017   {
8018     { "vpsignd",        { XM, Vex128, EXx } },
8019     { "(bad)",          { XX } },
8020   },
8021
8022   /* VEX_LEN_380B_P_2 */
8023   {
8024     { "vpmulhrsw",      { XM, Vex128, EXx } },
8025     { "(bad)",          { XX } },
8026   },
8027
8028   /* VEX_LEN_3819_P_2_M_0 */
8029   {
8030     { "(bad)",          { XX } },
8031     { "vbroadcastsd",   { XM, Mq } },
8032   },
8033
8034   /* VEX_LEN_381A_P_2_M_0 */
8035   {
8036     { "(bad)",          { XX } },
8037     { "vbroadcastf128", { XM, Mxmm } },
8038   },
8039
8040   /* VEX_LEN_381C_P_2 */
8041   {
8042     { "vpabsb",         { XM, EXx } },
8043     { "(bad)",          { XX } },
8044   },
8045
8046   /* VEX_LEN_381D_P_2 */
8047   {
8048     { "vpabsw",         { XM, EXx } },
8049     { "(bad)",          { XX } },
8050   },
8051
8052   /* VEX_LEN_381E_P_2 */
8053   {
8054     { "vpabsd",         { XM, EXx } },
8055     { "(bad)",          { XX } },
8056   },
8057
8058   /* VEX_LEN_3820_P_2 */
8059   {
8060     { "vpmovsxbw",      { XM, EXq } },
8061     { "(bad)",          { XX } },
8062   },
8063
8064   /* VEX_LEN_3821_P_2 */
8065   {
8066     { "vpmovsxbd",      { XM, EXd } },
8067     { "(bad)",          { XX } },
8068   },
8069
8070   /* VEX_LEN_3822_P_2 */
8071   {
8072     { "vpmovsxbq",      { XM, EXw } },
8073     { "(bad)",          { XX } },
8074   },
8075
8076   /* VEX_LEN_3823_P_2 */
8077   {
8078     { "vpmovsxwd",      { XM, EXq } },
8079     { "(bad)",          { XX } },
8080   },
8081
8082   /* VEX_LEN_3824_P_2 */
8083   {
8084     { "vpmovsxwq",      { XM, EXd } },
8085     { "(bad)",          { XX } },
8086   },
8087
8088   /* VEX_LEN_3825_P_2 */
8089   {
8090     { "vpmovsxdq",      { XM, EXq } },
8091     { "(bad)",          { XX } },
8092   },
8093
8094   /* VEX_LEN_3828_P_2 */
8095   {
8096     { "vpmuldq",        { XM, Vex128, EXx } },
8097     { "(bad)",          { XX } },
8098   },
8099
8100   /* VEX_LEN_3829_P_2 */
8101   {
8102     { "vpcmpeqq",       { XM, Vex128, EXx } },
8103     { "(bad)",          { XX } },
8104   },
8105
8106   /* VEX_LEN_382A_P_2_M_0 */
8107   {
8108     { "vmovntdqa",      { XM, Mx } },
8109     { "(bad)",          { XX } },
8110   },
8111
8112   /* VEX_LEN_382B_P_2 */
8113   {
8114     { "vpackusdw",      { XM, Vex128, EXx } },
8115     { "(bad)",          { XX } },
8116   },
8117
8118   /* VEX_LEN_3830_P_2 */
8119   {
8120     { "vpmovzxbw",      { XM, EXq } },
8121     { "(bad)",          { XX } },
8122   },
8123
8124   /* VEX_LEN_3831_P_2 */
8125   {
8126     { "vpmovzxbd",      { XM, EXd } },
8127     { "(bad)",          { XX } },
8128   },
8129
8130   /* VEX_LEN_3832_P_2 */
8131   {
8132     { "vpmovzxbq",      { XM, EXw } },
8133     { "(bad)",          { XX } },
8134   },
8135
8136   /* VEX_LEN_3833_P_2 */
8137   {
8138     { "vpmovzxwd",      { XM, EXq } },
8139     { "(bad)",          { XX } },
8140   },
8141
8142   /* VEX_LEN_3834_P_2 */
8143   {
8144     { "vpmovzxwq",      { XM, EXd } },
8145     { "(bad)",          { XX } },
8146   },
8147
8148   /* VEX_LEN_3835_P_2 */
8149   {
8150     { "vpmovzxdq",      { XM, EXq } },
8151     { "(bad)",          { XX } },
8152   },
8153
8154   /* VEX_LEN_3837_P_2 */
8155   {
8156     { "vpcmpgtq",       { XM, Vex128, EXx } },
8157     { "(bad)",          { XX } },
8158   },
8159
8160   /* VEX_LEN_3838_P_2 */
8161   {
8162     { "vpminsb",        { XM, Vex128, EXx } },
8163     { "(bad)",          { XX } },
8164   },
8165
8166   /* VEX_LEN_3839_P_2 */
8167   {
8168     { "vpminsd",        { XM, Vex128, EXx } },
8169     { "(bad)",          { XX } },
8170   },
8171
8172   /* VEX_LEN_383A_P_2 */
8173   {
8174     { "vpminuw",        { XM, Vex128, EXx } },
8175     { "(bad)",          { XX } },
8176   },
8177
8178   /* VEX_LEN_383B_P_2 */
8179   {
8180     { "vpminud",        { XM, Vex128, EXx } },
8181     { "(bad)",          { XX } },
8182   },
8183
8184   /* VEX_LEN_383C_P_2 */
8185   {
8186     { "vpmaxsb",        { XM, Vex128, EXx } },
8187     { "(bad)",          { XX } },
8188   },
8189
8190   /* VEX_LEN_383D_P_2 */
8191   {
8192     { "vpmaxsd",        { XM, Vex128, EXx } },
8193     { "(bad)",          { XX } },
8194   },
8195
8196   /* VEX_LEN_383E_P_2 */
8197   {
8198     { "vpmaxuw",        { XM, Vex128, EXx } },
8199     { "(bad)",          { XX } },
8200   },
8201
8202   /* VEX_LEN_383F_P_2 */
8203   {
8204     { "vpmaxud",        { XM, Vex128, EXx } },
8205     { "(bad)",          { XX } },
8206   },
8207
8208   /* VEX_LEN_3840_P_2 */
8209   {
8210     { "vpmulld",        { XM, Vex128, EXx } },
8211     { "(bad)",          { XX } },
8212   },
8213
8214   /* VEX_LEN_3841_P_2 */
8215   {
8216     { "vphminposuw",    { XM, EXx } },
8217     { "(bad)",          { XX } },
8218   },
8219
8220   /* VEX_LEN_38DB_P_2 */
8221   {
8222     { "vaesimc",        { XM, EXx } },
8223     { "(bad)",          { XX } },
8224   },
8225
8226   /* VEX_LEN_38DC_P_2 */
8227   {
8228     { "vaesenc",        { XM, Vex128, EXx } },
8229     { "(bad)",          { XX } },
8230   },
8231
8232   /* VEX_LEN_38DD_P_2 */
8233   {
8234     { "vaesenclast",    { XM, Vex128, EXx } },
8235     { "(bad)",          { XX } },
8236   },
8237
8238   /* VEX_LEN_38DE_P_2 */
8239   {
8240     { "vaesdec",        { XM, Vex128, EXx } },
8241     { "(bad)",          { XX } },
8242   },
8243
8244   /* VEX_LEN_38DF_P_2 */
8245   {
8246     { "vaesdeclast",    { XM, Vex128, EXx } },
8247     { "(bad)",          { XX } },
8248   },
8249
8250   /* VEX_LEN_3A06_P_2 */
8251   {
8252     { "(bad)",          { XX } },
8253     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
8254   },
8255
8256   /* VEX_LEN_3A0A_P_2 */
8257   {
8258     { "vroundss",       { XM, Vex128, EXd, Ib } },
8259     { "(bad)",          { XX } },
8260   },
8261
8262   /* VEX_LEN_3A0B_P_2 */
8263   {
8264     { "vroundsd",       { XM, Vex128, EXq, Ib } },
8265     { "(bad)",          { XX } },
8266   },
8267
8268   /* VEX_LEN_3A0E_P_2 */
8269   {
8270     { "vpblendw",       { XM, Vex128, EXx, Ib } },
8271     { "(bad)",          { XX } },
8272   },
8273
8274   /* VEX_LEN_3A0F_P_2 */
8275   {
8276     { "vpalignr",       { XM, Vex128, EXx, Ib } },
8277     { "(bad)",          { XX } },
8278   },
8279
8280   /* VEX_LEN_3A14_P_2 */
8281   {
8282     { "vpextrb",        { Edqb, XM, Ib } },
8283     { "(bad)",          { XX } },
8284   },
8285
8286   /* VEX_LEN_3A15_P_2 */
8287   {
8288     { "vpextrw",        { Edqw, XM, Ib } },
8289     { "(bad)",          { XX } },
8290   },
8291
8292   /* VEX_LEN_3A16_P_2  */
8293   {
8294     { "vpextrK",        { Edq, XM, Ib } },
8295     { "(bad)",          { XX } },
8296   },
8297
8298   /* VEX_LEN_3A17_P_2 */
8299   {
8300     { "vextractps",     { Edqd, XM, Ib } },
8301     { "(bad)",          { XX } },
8302   },
8303
8304   /* VEX_LEN_3A18_P_2 */
8305   {
8306     { "(bad)",          { XX } },
8307     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
8308   },
8309
8310   /* VEX_LEN_3A19_P_2 */
8311   {
8312     { "(bad)",          { XX } },
8313     { "vextractf128",   { EXxmm, XM, Ib } },
8314   },
8315
8316   /* VEX_LEN_3A20_P_2 */
8317   {
8318     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
8319     { "(bad)",          { XX } },
8320   },
8321
8322   /* VEX_LEN_3A21_P_2 */
8323   {
8324     { "vinsertps",      { XM, Vex128, EXd, Ib } },
8325     { "(bad)",          { XX } },
8326   },
8327
8328   /* VEX_LEN_3A22_P_2 */
8329   {
8330     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8331     { "(bad)",          { XX } },
8332   },
8333
8334   /* VEX_LEN_3A41_P_2 */
8335   {
8336     { "vdppd",          { XM, Vex128, EXx, Ib } },
8337     { "(bad)",          { XX } },
8338   },
8339
8340   /* VEX_LEN_3A42_P_2 */
8341   {
8342     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
8343     { "(bad)",          { XX } },
8344   },
8345
8346   /* VEX_LEN_3A44_P_2 */
8347   {
8348     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
8349     { "(bad)",          { XX } },
8350   },
8351
8352   /* VEX_LEN_3A4C_P_2 */
8353   {
8354     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
8355     { "(bad)",          { XX } },
8356   },
8357
8358   /* VEX_LEN_3A60_P_2 */
8359   {
8360     { "vpcmpestrm",     { XM, EXx, Ib } },
8361     { "(bad)",          { XX } },
8362   },
8363
8364   /* VEX_LEN_3A61_P_2 */
8365   {
8366     { "vpcmpestri",     { XM, EXx, Ib } },
8367     { "(bad)",          { XX } },
8368   },
8369
8370   /* VEX_LEN_3A62_P_2 */
8371   {
8372     { "vpcmpistrm",     { XM, EXx, Ib } },
8373     { "(bad)",          { XX } },
8374   },
8375
8376   /* VEX_LEN_3A63_P_2 */
8377   {
8378     { "vpcmpistri",     { XM, EXx, Ib } },
8379     { "(bad)",          { XX } },
8380   },
8381
8382   /* VEX_LEN_3A6A_P_2 */
8383   {
8384     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8385     { "(bad)",          { XX } },
8386   },
8387
8388   /* VEX_LEN_3A6B_P_2 */
8389   {
8390     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8391     { "(bad)",          { XX } },
8392   },
8393
8394   /* VEX_LEN_3A6E_P_2 */
8395   {
8396     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8397     { "(bad)",          { XX } },
8398   },
8399
8400   /* VEX_LEN_3A6F_P_2 */
8401   {
8402     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8403     { "(bad)",          { XX } },
8404   },
8405
8406   /* VEX_LEN_3A7A_P_2 */
8407   {
8408     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8409     { "(bad)",          { XX } },
8410   },
8411
8412   /* VEX_LEN_3A7B_P_2 */
8413   {
8414     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8415     { "(bad)",          { XX } },
8416   },
8417
8418   /* VEX_LEN_3A7E_P_2 */
8419   {
8420     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8421     { "(bad)",          { XX } },
8422   },
8423
8424   /* VEX_LEN_3A7F_P_2 */
8425   {
8426     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8427     { "(bad)",          { XX } },
8428   },
8429
8430   /* VEX_LEN_3ADF_P_2 */
8431   {
8432     { "vaeskeygenassist", { XM, EXx, Ib } },
8433     { "(bad)",          { XX } },
8434   },
8435 };
8436
8437 static const struct dis386 mod_table[][2] = {
8438   {
8439     /* MOD_8D */
8440     { "leaS",           { Gv, M } },
8441     { "(bad)",          { XX } },
8442   },
8443   {
8444     /* MOD_0F01_REG_0 */
8445     { X86_64_TABLE (X86_64_0F01_REG_0) },
8446     { RM_TABLE (RM_0F01_REG_0) },
8447   },
8448   {
8449     /* MOD_0F01_REG_1 */
8450     { X86_64_TABLE (X86_64_0F01_REG_1) },
8451     { RM_TABLE (RM_0F01_REG_1) },
8452   },
8453   {
8454     /* MOD_0F01_REG_2 */
8455     { X86_64_TABLE (X86_64_0F01_REG_2) },
8456     { RM_TABLE (RM_0F01_REG_2) },
8457   },
8458   {
8459     /* MOD_0F01_REG_3 */
8460     { X86_64_TABLE (X86_64_0F01_REG_3) },
8461     { RM_TABLE (RM_0F01_REG_3) },
8462   },
8463   {
8464     /* MOD_0F01_REG_7 */
8465     { "invlpg",         { Mb } },
8466     { RM_TABLE (RM_0F01_REG_7) },
8467   },
8468   {
8469     /* MOD_0F12_PREFIX_0 */
8470     { "movlps",         { XM, EXq } },
8471     { "movhlps",        { XM, EXq } },
8472   },
8473   {
8474     /* MOD_0F13 */
8475     { "movlpX",         { EXq, XM } },
8476     { "(bad)",          { XX } },
8477   },
8478   {
8479     /* MOD_0F16_PREFIX_0 */
8480     { "movhps",         { XM, EXq } },
8481     { "movlhps",        { XM, EXq } },
8482   },
8483   {
8484     /* MOD_0F17 */
8485     { "movhpX",         { EXq, XM } },
8486     { "(bad)",          { XX } },
8487   },
8488   {
8489     /* MOD_0F18_REG_0 */
8490     { "prefetchnta",    { Mb } },
8491     { "(bad)",          { XX } },
8492   },
8493   {
8494     /* MOD_0F18_REG_1 */
8495     { "prefetcht0",     { Mb } },
8496     { "(bad)",          { XX } },
8497   },
8498   {
8499     /* MOD_0F18_REG_2 */
8500     { "prefetcht1",     { Mb } },
8501     { "(bad)",          { XX } },
8502   },
8503   {
8504     /* MOD_0F18_REG_3 */
8505     { "prefetcht2",     { Mb } },
8506     { "(bad)",          { XX } },
8507   },
8508   {
8509     /* MOD_0F20 */
8510     { "(bad)",          { XX } },
8511     { "movZ",           { Rm, Cm } },
8512   },
8513   {
8514     /* MOD_0F21 */
8515     { "(bad)",          { XX } },
8516     { "movZ",           { Rm, Dm } },
8517   },
8518   {
8519     /* MOD_0F22 */
8520     { "(bad)",          { XX } },
8521     { "movZ",           { Cm, Rm } },
8522   },
8523   {
8524     /* MOD_0F23 */
8525     { "(bad)",          { XX } },
8526     { "movZ",           { Dm, Rm } },
8527   },
8528   {
8529     /* MOD_0F24 */
8530     { "(bad)",          { XX } },
8531     { "movL",           { Rd, Td } },
8532   },
8533   {
8534     /* MOD_0F26 */
8535     { "(bad)",          { XX } },
8536     { "movL",           { Td, Rd } },
8537   },
8538   {
8539     /* MOD_0F2B_PREFIX_0 */
8540     {"movntps",         { Mx, XM } },
8541     { "(bad)",          { XX } },
8542   },
8543   {
8544     /* MOD_0F2B_PREFIX_1 */
8545     {"movntss",         { Md, XM } },
8546     { "(bad)",          { XX } },
8547   },
8548   {
8549     /* MOD_0F2B_PREFIX_2 */
8550     {"movntpd",         { Mx, XM } },
8551     { "(bad)",          { XX } },
8552   },
8553   {
8554     /* MOD_0F2B_PREFIX_3 */
8555     {"movntsd",         { Mq, XM } },
8556     { "(bad)",          { XX } },
8557   },
8558   {
8559     /* MOD_0F51 */
8560     { "(bad)",          { XX } },
8561     { "movmskpX",       { Gdq, XS } },
8562   },
8563   {
8564     /* MOD_0F71_REG_2 */
8565     { "(bad)",          { XX } },
8566     { "psrlw",          { MS, Ib } },
8567   },
8568   {
8569     /* MOD_0F71_REG_4 */
8570     { "(bad)",          { XX } },
8571     { "psraw",          { MS, Ib } },
8572   },
8573   {
8574     /* MOD_0F71_REG_6 */
8575     { "(bad)",          { XX } },
8576     { "psllw",          { MS, Ib } },
8577   },
8578   {
8579     /* MOD_0F72_REG_2 */
8580     { "(bad)",          { XX } },
8581     { "psrld",          { MS, Ib } },
8582   },
8583   {
8584     /* MOD_0F72_REG_4 */
8585     { "(bad)",          { XX } },
8586     { "psrad",          { MS, Ib } },
8587   },
8588   {
8589     /* MOD_0F72_REG_6 */
8590     { "(bad)",          { XX } },
8591     { "pslld",          { MS, Ib } },
8592   },
8593   {
8594     /* MOD_0F73_REG_2 */
8595     { "(bad)",          { XX } },
8596     { "psrlq",          { MS, Ib } },
8597   },
8598   {
8599     /* MOD_0F73_REG_3 */
8600     { "(bad)",          { XX } },
8601     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
8602   },
8603   {
8604     /* MOD_0F73_REG_6 */
8605     { "(bad)",          { XX } },
8606     { "psllq",          { MS, Ib } },
8607   },
8608   {
8609     /* MOD_0F73_REG_7 */
8610     { "(bad)",          { XX } },
8611     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
8612   },
8613   {
8614     /* MOD_0FAE_REG_0 */
8615     { "fxsave",         { M } },
8616     { "(bad)",          { XX } },
8617   },
8618   {
8619     /* MOD_0FAE_REG_1 */
8620     { "fxrstor",        { M } },
8621     { "(bad)",          { XX } },
8622   },
8623   {
8624     /* MOD_0FAE_REG_2 */
8625     { "ldmxcsr",        { Md } },
8626     { "(bad)",          { XX } },
8627   },
8628   {
8629     /* MOD_0FAE_REG_3 */
8630     { "stmxcsr",        { Md } },
8631     { "(bad)",          { XX } },
8632   },
8633   {
8634     /* MOD_0FAE_REG_4 */
8635     { "xsave",          { M } },
8636     { "(bad)",          { XX } },
8637   },
8638   {
8639     /* MOD_0FAE_REG_5 */
8640     { "xrstor",         { M } },
8641     { RM_TABLE (RM_0FAE_REG_5) },
8642   },
8643   {
8644     /* MOD_0FAE_REG_6 */
8645     { "xsaveopt",       { M } },
8646     { RM_TABLE (RM_0FAE_REG_6) },
8647   },
8648   {
8649     /* MOD_0FAE_REG_7 */
8650     { "clflush",        { Mb } },
8651     { RM_TABLE (RM_0FAE_REG_7) },
8652   },
8653   {
8654     /* MOD_0FB2 */
8655     { "lssS",           { Gv, Mp } },
8656     { "(bad)",          { XX } },
8657   },
8658   {
8659     /* MOD_0FB4 */
8660     { "lfsS",           { Gv, Mp } },
8661     { "(bad)",          { XX } },
8662   },
8663   {
8664     /* MOD_0FB5 */
8665     { "lgsS",           { Gv, Mp } },
8666     { "(bad)",          { XX } },
8667   },
8668   {
8669     /* MOD_0FC7_REG_6 */
8670     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
8671     { "(bad)",          { XX } },
8672   },
8673   {
8674     /* MOD_0FC7_REG_7 */
8675     { "vmptrst",        { Mq } },
8676     { "(bad)",          { XX } },
8677   },
8678   {
8679     /* MOD_0FD7 */
8680     { "(bad)",          { XX } },
8681     { "pmovmskb",       { Gdq, MS } },
8682   },
8683   {
8684     /* MOD_0FE7_PREFIX_2 */
8685     { "movntdq",        { Mx, XM } },
8686     { "(bad)",          { XX } },
8687   },
8688   {
8689     /* MOD_0FF0_PREFIX_3 */
8690     { "lddqu",          { XM, M } },
8691     { "(bad)",          { XX } },
8692   },
8693   {
8694     /* MOD_0F382A_PREFIX_2 */
8695     { "movntdqa",       { XM, Mx } },
8696     { "(bad)",          { XX } },
8697   },
8698   {
8699     /* MOD_62_32BIT */
8700     { "bound{S|}",      { Gv, Ma } },
8701     { "(bad)",          { XX } },
8702   },
8703   {
8704     /* MOD_C4_32BIT */
8705     { "lesS",           { Gv, Mp } },
8706     { VEX_C4_TABLE (VEX_0F) },
8707   },
8708   {
8709     /* MOD_C5_32BIT */
8710     { "ldsS",           { Gv, Mp } },
8711     { VEX_C5_TABLE (VEX_0F) },
8712   },
8713   {
8714     /* MOD_VEX_12_PREFIX_0 */
8715     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
8716     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
8717   },
8718   {
8719     /* MOD_VEX_13 */
8720     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
8721     { "(bad)",          { XX } },
8722   },
8723   {
8724     /* MOD_VEX_16_PREFIX_0 */
8725     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
8726     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
8727   },
8728   {
8729     /* MOD_VEX_17 */
8730     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
8731     { "(bad)",          { XX } },
8732   },
8733   {
8734     /* MOD_VEX_2B */
8735     { "vmovntpX",       { Mx, XM } },
8736     { "(bad)",          { XX } },
8737   },
8738   {
8739     /* MOD_VEX_51 */
8740     { "(bad)",          { XX } },
8741     { "vmovmskpX",      { Gdq, XS } },
8742   },
8743   {
8744     /* MOD_VEX_71_REG_2 */
8745     { "(bad)",          { XX } },
8746     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
8747   },
8748   {
8749     /* MOD_VEX_71_REG_4 */
8750     { "(bad)",          { XX } },
8751     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
8752   },
8753   {
8754     /* MOD_VEX_71_REG_6 */
8755     { "(bad)",          { XX } },
8756     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
8757   },
8758   {
8759     /* MOD_VEX_72_REG_2 */
8760     { "(bad)",          { XX } },
8761     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
8762   },
8763   {
8764     /* MOD_VEX_72_REG_4 */
8765     { "(bad)",          { XX } },
8766     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
8767   },
8768   {
8769     /* MOD_VEX_72_REG_6 */
8770     { "(bad)",          { XX } },
8771     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
8772   },
8773   {
8774     /* MOD_VEX_73_REG_2 */
8775     { "(bad)",          { XX } },
8776     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
8777   },
8778   {
8779     /* MOD_VEX_73_REG_3 */
8780     { "(bad)",          { XX } },
8781     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
8782   },
8783   {
8784     /* MOD_VEX_73_REG_6 */
8785     { "(bad)",          { XX } },
8786     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
8787   },
8788   {
8789     /* MOD_VEX_73_REG_7 */
8790     { "(bad)",          { XX } },
8791     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
8792   },
8793   {
8794     /* MOD_VEX_AE_REG_2 */
8795     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
8796     { "(bad)",          { XX } },
8797   },
8798   {
8799     /* MOD_VEX_AE_REG_3 */
8800     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
8801     { "(bad)",          { XX } },
8802   },
8803   {
8804     /* MOD_VEX_D7_PREFIX_2 */
8805     { "(bad)",          { XX } },
8806     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
8807   },
8808   {
8809     /* MOD_VEX_E7_PREFIX_2 */
8810     { "vmovntdq",       { Mx, XM } },
8811     { "(bad)",          { XX } },
8812   },
8813   {
8814     /* MOD_VEX_F0_PREFIX_3 */
8815     { "vlddqu",         { XM, M } },
8816     { "(bad)",          { XX } },
8817   },
8818   {
8819     /* MOD_VEX_3818_PREFIX_2 */
8820     { "vbroadcastss",   { XM, Md } },
8821     { "(bad)",          { XX } },
8822   },
8823   {
8824     /* MOD_VEX_3819_PREFIX_2 */
8825     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
8826     { "(bad)",          { XX } },
8827   },
8828   {
8829     /* MOD_VEX_381A_PREFIX_2 */
8830     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
8831     { "(bad)",          { XX } },
8832   },
8833   {
8834     /* MOD_VEX_382A_PREFIX_2 */
8835     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
8836     { "(bad)",          { XX } },
8837   },
8838   {
8839     /* MOD_VEX_382C_PREFIX_2 */
8840     { "vmaskmovps",     { XM, Vex, Mx } },
8841     { "(bad)",          { XX } },
8842   },
8843   {
8844     /* MOD_VEX_382D_PREFIX_2 */
8845     { "vmaskmovpd",     { XM, Vex, Mx } },
8846     { "(bad)",          { XX } },
8847   },
8848   {
8849     /* MOD_VEX_382E_PREFIX_2 */
8850     { "vmaskmovps",     { Mx, Vex, XM } },
8851     { "(bad)",          { XX } },
8852   },
8853   {
8854     /* MOD_VEX_382F_PREFIX_2 */
8855     { "vmaskmovpd",     { Mx, Vex, XM } },
8856     { "(bad)",          { XX } },
8857   },
8858 };
8859
8860 static const struct dis386 rm_table[][8] = {
8861   {
8862     /* RM_0F01_REG_0 */
8863     { "(bad)",          { XX } },
8864     { "vmcall",         { Skip_MODRM } },
8865     { "vmlaunch",       { Skip_MODRM } },
8866     { "vmresume",       { Skip_MODRM } },
8867     { "vmxoff",         { Skip_MODRM } },
8868     { "(bad)",          { XX } },
8869     { "(bad)",          { XX } },
8870     { "(bad)",          { XX } },
8871   },
8872   {
8873     /* RM_0F01_REG_1 */
8874     { "monitor",        { { OP_Monitor, 0 } } },
8875     { "mwait",          { { OP_Mwait, 0 } } },
8876     { "(bad)",          { XX } },
8877     { "(bad)",          { XX } },
8878     { "(bad)",          { XX } },
8879     { "(bad)",          { XX } },
8880     { "(bad)",          { XX } },
8881     { "(bad)",          { XX } },
8882   },
8883   {
8884     /* RM_0F01_REG_2 */
8885     { "xgetbv",         { Skip_MODRM } },
8886     { "xsetbv",         { Skip_MODRM } },
8887     { "(bad)",          { XX } },
8888     { "(bad)",          { XX } },
8889     { "(bad)",          { XX } },
8890     { "(bad)",          { XX } },
8891     { "(bad)",          { XX } },
8892     { "(bad)",          { XX } },
8893   },
8894   {
8895     /* RM_0F01_REG_3 */
8896     { "vmrun",          { Skip_MODRM } },
8897     { "vmmcall",        { Skip_MODRM } },
8898     { "vmload",         { Skip_MODRM } },
8899     { "vmsave",         { Skip_MODRM } },
8900     { "stgi",           { Skip_MODRM } },
8901     { "clgi",           { Skip_MODRM } },
8902     { "skinit",         { Skip_MODRM } },
8903     { "invlpga",        { Skip_MODRM } },
8904   },
8905   {
8906     /* RM_0F01_REG_7 */
8907     { "swapgs",         { Skip_MODRM } },
8908     { "rdtscp",         { Skip_MODRM } },
8909     { "(bad)",          { XX } },
8910     { "(bad)",          { XX } },
8911     { "(bad)",          { XX } },
8912     { "(bad)",          { XX } },
8913     { "(bad)",          { XX } },
8914     { "(bad)",          { XX } },
8915   },
8916   {
8917     /* RM_0FAE_REG_5 */
8918     { "lfence",         { Skip_MODRM } },
8919     { "(bad)",          { XX } },
8920     { "(bad)",          { XX } },
8921     { "(bad)",          { XX } },
8922     { "(bad)",          { XX } },
8923     { "(bad)",          { XX } },
8924     { "(bad)",          { XX } },
8925     { "(bad)",          { XX } },
8926   },
8927   {
8928     /* RM_0FAE_REG_6 */
8929     { "mfence",         { Skip_MODRM } },
8930     { "(bad)",          { XX } },
8931     { "(bad)",          { XX } },
8932     { "(bad)",          { XX } },
8933     { "(bad)",          { XX } },
8934     { "(bad)",          { XX } },
8935     { "(bad)",          { XX } },
8936     { "(bad)",          { XX } },
8937   },
8938   {
8939     /* RM_0FAE_REG_7 */
8940     { "sfence",         { Skip_MODRM } },
8941     { "(bad)",          { XX } },
8942     { "(bad)",          { XX } },
8943     { "(bad)",          { XX } },
8944     { "(bad)",          { XX } },
8945     { "(bad)",          { XX } },
8946     { "(bad)",          { XX } },
8947     { "(bad)",          { XX } },
8948   },
8949 };
8950
8951 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8952
8953 static void
8954 ckprefix (void)
8955 {
8956   int newrex;
8957   rex = 0;
8958   rex_original = 0;
8959   rex_ignored = 0;
8960   prefixes = 0;
8961   used_prefixes = 0;
8962   rex_used = 0;
8963   while (1)
8964     {
8965       FETCH_DATA (the_info, codep + 1);
8966       newrex = 0;
8967       switch (*codep)
8968         {
8969         /* REX prefixes family.  */
8970         case 0x40:
8971         case 0x41:
8972         case 0x42:
8973         case 0x43:
8974         case 0x44:
8975         case 0x45:
8976         case 0x46:
8977         case 0x47:
8978         case 0x48:
8979         case 0x49:
8980         case 0x4a:
8981         case 0x4b:
8982         case 0x4c:
8983         case 0x4d:
8984         case 0x4e:
8985         case 0x4f:
8986             if (address_mode == mode_64bit)
8987               newrex = *codep;
8988             else
8989               return;
8990           break;
8991         case 0xf3:
8992           prefixes |= PREFIX_REPZ;
8993           break;
8994         case 0xf2:
8995           prefixes |= PREFIX_REPNZ;
8996           break;
8997         case 0xf0:
8998           prefixes |= PREFIX_LOCK;
8999           break;
9000         case 0x2e:
9001           prefixes |= PREFIX_CS;
9002           break;
9003         case 0x36:
9004           prefixes |= PREFIX_SS;
9005           break;
9006         case 0x3e:
9007           prefixes |= PREFIX_DS;
9008           break;
9009         case 0x26:
9010           prefixes |= PREFIX_ES;
9011           break;
9012         case 0x64:
9013           prefixes |= PREFIX_FS;
9014           break;
9015         case 0x65:
9016           prefixes |= PREFIX_GS;
9017           break;
9018         case 0x66:
9019           prefixes |= PREFIX_DATA;
9020           break;
9021         case 0x67:
9022           prefixes |= PREFIX_ADDR;
9023           break;
9024         case FWAIT_OPCODE:
9025           /* fwait is really an instruction.  If there are prefixes
9026              before the fwait, they belong to the fwait, *not* to the
9027              following instruction.  */
9028           if (prefixes || rex)
9029             {
9030               prefixes |= PREFIX_FWAIT;
9031               codep++;
9032               return;
9033             }
9034           prefixes = PREFIX_FWAIT;
9035           break;
9036         default:
9037           return;
9038         }
9039       /* Rex is ignored when followed by another prefix.  */
9040       if (rex)
9041         {
9042           rex_used = rex;
9043           return;
9044         }
9045       rex = newrex;
9046       rex_original = rex;
9047       codep++;
9048     }
9049 }
9050
9051 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9052    prefix byte.  */
9053
9054 static const char *
9055 prefix_name (int pref, int sizeflag)
9056 {
9057   static const char *rexes [16] =
9058     {
9059       "rex",            /* 0x40 */
9060       "rex.B",          /* 0x41 */
9061       "rex.X",          /* 0x42 */
9062       "rex.XB",         /* 0x43 */
9063       "rex.R",          /* 0x44 */
9064       "rex.RB",         /* 0x45 */
9065       "rex.RX",         /* 0x46 */
9066       "rex.RXB",        /* 0x47 */
9067       "rex.W",          /* 0x48 */
9068       "rex.WB",         /* 0x49 */
9069       "rex.WX",         /* 0x4a */
9070       "rex.WXB",        /* 0x4b */
9071       "rex.WR",         /* 0x4c */
9072       "rex.WRB",        /* 0x4d */
9073       "rex.WRX",        /* 0x4e */
9074       "rex.WRXB",       /* 0x4f */
9075     };
9076
9077   switch (pref)
9078     {
9079     /* REX prefixes family.  */
9080     case 0x40:
9081     case 0x41:
9082     case 0x42:
9083     case 0x43:
9084     case 0x44:
9085     case 0x45:
9086     case 0x46:
9087     case 0x47:
9088     case 0x48:
9089     case 0x49:
9090     case 0x4a:
9091     case 0x4b:
9092     case 0x4c:
9093     case 0x4d:
9094     case 0x4e:
9095     case 0x4f:
9096       return rexes [pref - 0x40];
9097     case 0xf3:
9098       return "repz";
9099     case 0xf2:
9100       return "repnz";
9101     case 0xf0:
9102       return "lock";
9103     case 0x2e:
9104       return "cs";
9105     case 0x36:
9106       return "ss";
9107     case 0x3e:
9108       return "ds";
9109     case 0x26:
9110       return "es";
9111     case 0x64:
9112       return "fs";
9113     case 0x65:
9114       return "gs";
9115     case 0x66:
9116       return (sizeflag & DFLAG) ? "data16" : "data32";
9117     case 0x67:
9118       if (address_mode == mode_64bit)
9119         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9120       else
9121         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9122     case FWAIT_OPCODE:
9123       return "fwait";
9124     default:
9125       return NULL;
9126     }
9127 }
9128
9129 static char op_out[MAX_OPERANDS][100];
9130 static int op_ad, op_index[MAX_OPERANDS];
9131 static int two_source_ops;
9132 static bfd_vma op_address[MAX_OPERANDS];
9133 static bfd_vma op_riprel[MAX_OPERANDS];
9134 static bfd_vma start_pc;
9135
9136 /*
9137  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9138  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9139  *   section of the "Virtual 8086 Mode" chapter.)
9140  * 'pc' should be the address of this instruction, it will
9141  *   be used to print the target address if this is a relative jump or call
9142  * The function returns the length of this instruction in bytes.
9143  */
9144
9145 static char intel_syntax;
9146 static char intel_mnemonic = !SYSV386_COMPAT;
9147 static char open_char;
9148 static char close_char;
9149 static char separator_char;
9150 static char scale_char;
9151
9152 /* Here for backwards compatibility.  When gdb stops using
9153    print_insn_i386_att and print_insn_i386_intel these functions can
9154    disappear, and print_insn_i386 be merged into print_insn.  */
9155 int
9156 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9157 {
9158   intel_syntax = 0;
9159
9160   return print_insn (pc, info);
9161 }
9162
9163 int
9164 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9165 {
9166   intel_syntax = 1;
9167
9168   return print_insn (pc, info);
9169 }
9170
9171 int
9172 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9173 {
9174   intel_syntax = -1;
9175
9176   return print_insn (pc, info);
9177 }
9178
9179 void
9180 print_i386_disassembler_options (FILE *stream)
9181 {
9182   fprintf (stream, _("\n\
9183 The following i386/x86-64 specific disassembler options are supported for use\n\
9184 with the -M switch (multiple options should be separated by commas):\n"));
9185
9186   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9187   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9188   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9189   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9190   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9191   fprintf (stream, _("  att-mnemonic\n"
9192                      "              Display instruction in AT&T mnemonic\n"));
9193   fprintf (stream, _("  intel-mnemonic\n"
9194                      "              Display instruction in Intel mnemonic\n"));
9195   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9196   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9197   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9198   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9199   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9200   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9201 }
9202
9203 /* Get a pointer to struct dis386 with a valid name.  */
9204
9205 static const struct dis386 *
9206 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9207 {
9208   int index, vex_table_index;
9209
9210   if (dp->name != NULL)
9211     return dp;
9212
9213   switch (dp->op[0].bytemode)
9214     {
9215     case USE_REG_TABLE:
9216       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9217       break;
9218
9219     case USE_MOD_TABLE:
9220       index = modrm.mod == 0x3 ? 1 : 0;
9221       dp = &mod_table[dp->op[1].bytemode][index];
9222       break;
9223
9224     case USE_RM_TABLE:
9225       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9226       break;
9227
9228     case USE_PREFIX_TABLE:
9229       if (need_vex)
9230         {
9231           /* The prefix in VEX is implicit.  */
9232           switch (vex.prefix)
9233             {
9234             case 0:
9235               index = 0;
9236               break;
9237             case REPE_PREFIX_OPCODE:
9238               index = 1;
9239               break;
9240             case DATA_PREFIX_OPCODE:
9241               index = 2;
9242               break;
9243             case REPNE_PREFIX_OPCODE:
9244               index = 3;
9245               break;
9246             default:
9247               abort ();
9248               break;
9249             }
9250         }
9251       else
9252         {
9253           index = 0;
9254           used_prefixes |= (prefixes & PREFIX_REPZ);
9255           if (prefixes & PREFIX_REPZ)
9256             {
9257               index = 1;
9258               repz_prefix = NULL;
9259             }
9260           else
9261             {
9262               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9263                  PREFIX_DATA.  */
9264               used_prefixes |= (prefixes & PREFIX_REPNZ);
9265               if (prefixes & PREFIX_REPNZ)
9266                 {
9267                   index = 3;
9268                   repnz_prefix = NULL;
9269                 }
9270               else
9271                 {
9272                   used_prefixes |= (prefixes & PREFIX_DATA);
9273                   if (prefixes & PREFIX_DATA)
9274                     {
9275                       index = 2;
9276                       data_prefix = NULL;
9277                     }
9278                 }
9279             }
9280         }
9281       dp = &prefix_table[dp->op[1].bytemode][index];
9282       break;
9283
9284     case USE_X86_64_TABLE:
9285       index = address_mode == mode_64bit ? 1 : 0;
9286       dp = &x86_64_table[dp->op[1].bytemode][index];
9287       break;
9288
9289     case USE_3BYTE_TABLE:
9290       FETCH_DATA (info, codep + 2);
9291       index = *codep++;
9292       dp = &three_byte_table[dp->op[1].bytemode][index];
9293       modrm.mod = (*codep >> 6) & 3;
9294       modrm.reg = (*codep >> 3) & 7;
9295       modrm.rm = *codep & 7;
9296       break;
9297
9298     case USE_VEX_LEN_TABLE:
9299       if (!need_vex)
9300         abort ();
9301
9302       switch (vex.length)
9303         {
9304         case 128:
9305           index = 0;
9306           break;
9307         case 256:
9308           index = 1;
9309           break;
9310         default:
9311           abort ();
9312           break;
9313         }
9314
9315       dp = &vex_len_table[dp->op[1].bytemode][index];
9316       break;
9317
9318     case USE_VEX_C4_TABLE:
9319       FETCH_DATA (info, codep + 3);
9320       /* All bits in the REX prefix are ignored.  */
9321       rex_ignored = rex;
9322       rex = ~(*codep >> 5) & 0x7;
9323       switch ((*codep & 0x1f))
9324         {
9325         default:
9326           BadOp ();
9327         case 0x1:
9328           vex_table_index = 0;
9329           break;
9330         case 0x2:
9331           vex_table_index = 1;
9332           break;
9333         case 0x3:
9334           vex_table_index = 2;
9335           break;
9336         }
9337       codep++;
9338       vex.w = *codep & 0x80;
9339       if (vex.w && address_mode == mode_64bit)
9340         rex |= REX_W;
9341
9342       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9343       if (address_mode != mode_64bit
9344           && vex.register_specifier > 0x7)
9345         BadOp ();
9346
9347       vex.length = (*codep & 0x4) ? 256 : 128;
9348       switch ((*codep & 0x3))
9349         {
9350         case 0:
9351           vex.prefix = 0;
9352           break;
9353         case 1:
9354           vex.prefix = DATA_PREFIX_OPCODE;
9355           break;
9356         case 2:
9357           vex.prefix = REPE_PREFIX_OPCODE;
9358           break;
9359         case 3:
9360           vex.prefix = REPNE_PREFIX_OPCODE;
9361           break;
9362         }
9363       need_vex = 1;
9364       need_vex_reg = 1;
9365       codep++;
9366       index = *codep++;
9367       dp = &vex_table[vex_table_index][index];
9368       /* There is no MODRM byte for VEX [82|77].  */
9369       if (index != 0x77 && index != 0x82)
9370         {
9371           FETCH_DATA (info, codep + 1);
9372           modrm.mod = (*codep >> 6) & 3;
9373           modrm.reg = (*codep >> 3) & 7;
9374           modrm.rm = *codep & 7;
9375         }
9376       break;
9377
9378     case USE_VEX_C5_TABLE:
9379       FETCH_DATA (info, codep + 2);
9380       /* All bits in the REX prefix are ignored.  */
9381       rex_ignored = rex;
9382       rex = (*codep & 0x80) ? 0 : REX_R;
9383
9384       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9385       if (address_mode != mode_64bit
9386           && vex.register_specifier > 0x7)
9387         BadOp ();
9388
9389       vex.length = (*codep & 0x4) ? 256 : 128;
9390       switch ((*codep & 0x3))
9391         {
9392         case 0:
9393           vex.prefix = 0;
9394           break;
9395         case 1:
9396           vex.prefix = DATA_PREFIX_OPCODE;
9397           break;
9398         case 2:
9399           vex.prefix = REPE_PREFIX_OPCODE;
9400           break;
9401         case 3:
9402           vex.prefix = REPNE_PREFIX_OPCODE;
9403           break;
9404         }
9405       need_vex = 1;
9406       need_vex_reg = 1;
9407       codep++;
9408       index = *codep++;
9409       dp = &vex_table[dp->op[1].bytemode][index];
9410       /* There is no MODRM byte for VEX [82|77].  */
9411       if (index != 0x77 && index != 0x82)
9412         {
9413           FETCH_DATA (info, codep + 1);
9414           modrm.mod = (*codep >> 6) & 3;
9415           modrm.reg = (*codep >> 3) & 7;
9416           modrm.rm = *codep & 7;
9417         }
9418       break;
9419
9420     default:
9421       abort ();
9422     }
9423
9424   if (dp->name != NULL)
9425     return dp;
9426   else
9427     return get_valid_dis386 (dp, info);
9428 }
9429
9430 static int
9431 print_insn (bfd_vma pc, disassemble_info *info)
9432 {
9433   const struct dis386 *dp;
9434   int i;
9435   char *op_txt[MAX_OPERANDS];
9436   int needcomma;
9437   int sizeflag;
9438   const char *p;
9439   struct dis_private priv;
9440   unsigned char op;
9441   char prefix_obuf[32];
9442   char *prefix_obufp;
9443
9444   if (info->mach == bfd_mach_x86_64_intel_syntax
9445       || info->mach == bfd_mach_x86_64
9446       || info->mach == bfd_mach_l1om
9447       || info->mach == bfd_mach_l1om_intel_syntax)
9448     address_mode = mode_64bit;
9449   else
9450     address_mode = mode_32bit;
9451
9452   if (intel_syntax == (char) -1)
9453     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
9454                     || info->mach == bfd_mach_x86_64_intel_syntax
9455                     || info->mach == bfd_mach_l1om_intel_syntax);
9456
9457   if (info->mach == bfd_mach_i386_i386
9458       || info->mach == bfd_mach_x86_64
9459       || info->mach == bfd_mach_l1om
9460       || info->mach == bfd_mach_i386_i386_intel_syntax
9461       || info->mach == bfd_mach_x86_64_intel_syntax
9462       || info->mach == bfd_mach_l1om_intel_syntax)
9463     priv.orig_sizeflag = AFLAG | DFLAG;
9464   else if (info->mach == bfd_mach_i386_i8086)
9465     priv.orig_sizeflag = 0;
9466   else
9467     abort ();
9468
9469   for (p = info->disassembler_options; p != NULL; )
9470     {
9471       if (CONST_STRNEQ (p, "x86-64"))
9472         {
9473           address_mode = mode_64bit;
9474           priv.orig_sizeflag = AFLAG | DFLAG;
9475         }
9476       else if (CONST_STRNEQ (p, "i386"))
9477         {
9478           address_mode = mode_32bit;
9479           priv.orig_sizeflag = AFLAG | DFLAG;
9480         }
9481       else if (CONST_STRNEQ (p, "i8086"))
9482         {
9483           address_mode = mode_16bit;
9484           priv.orig_sizeflag = 0;
9485         }
9486       else if (CONST_STRNEQ (p, "intel"))
9487         {
9488           intel_syntax = 1;
9489           if (CONST_STRNEQ (p + 5, "-mnemonic"))
9490             intel_mnemonic = 1;
9491         }
9492       else if (CONST_STRNEQ (p, "att"))
9493         {
9494           intel_syntax = 0;
9495           if (CONST_STRNEQ (p + 3, "-mnemonic"))
9496             intel_mnemonic = 0;
9497         }
9498       else if (CONST_STRNEQ (p, "addr"))
9499         {
9500           if (address_mode == mode_64bit)
9501             {
9502               if (p[4] == '3' && p[5] == '2')
9503                 priv.orig_sizeflag &= ~AFLAG;
9504               else if (p[4] == '6' && p[5] == '4')
9505                 priv.orig_sizeflag |= AFLAG;
9506             }
9507           else
9508             {
9509               if (p[4] == '1' && p[5] == '6')
9510                 priv.orig_sizeflag &= ~AFLAG;
9511               else if (p[4] == '3' && p[5] == '2')
9512                 priv.orig_sizeflag |= AFLAG;
9513             }
9514         }
9515       else if (CONST_STRNEQ (p, "data"))
9516         {
9517           if (p[4] == '1' && p[5] == '6')
9518             priv.orig_sizeflag &= ~DFLAG;
9519           else if (p[4] == '3' && p[5] == '2')
9520             priv.orig_sizeflag |= DFLAG;
9521         }
9522       else if (CONST_STRNEQ (p, "suffix"))
9523         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9524
9525       p = strchr (p, ',');
9526       if (p != NULL)
9527         p++;
9528     }
9529
9530   if (intel_syntax)
9531     {
9532       names64 = intel_names64;
9533       names32 = intel_names32;
9534       names16 = intel_names16;
9535       names8 = intel_names8;
9536       names8rex = intel_names8rex;
9537       names_seg = intel_names_seg;
9538       index64 = intel_index64;
9539       index32 = intel_index32;
9540       index16 = intel_index16;
9541       open_char = '[';
9542       close_char = ']';
9543       separator_char = '+';
9544       scale_char = '*';
9545     }
9546   else
9547     {
9548       names64 = att_names64;
9549       names32 = att_names32;
9550       names16 = att_names16;
9551       names8 = att_names8;
9552       names8rex = att_names8rex;
9553       names_seg = att_names_seg;
9554       index64 = att_index64;
9555       index32 = att_index32;
9556       index16 = att_index16;
9557       open_char = '(';
9558       close_char =  ')';
9559       separator_char = ',';
9560       scale_char = ',';
9561     }
9562
9563   /* The output looks better if we put 7 bytes on a line, since that
9564      puts most long word instructions on a single line.  Use 8 bytes
9565      for Intel L1OM.  */
9566   if (info->mach == bfd_mach_l1om
9567       || info->mach == bfd_mach_l1om_intel_syntax)
9568     info->bytes_per_line = 8;
9569   else
9570     info->bytes_per_line = 7;
9571
9572   info->private_data = &priv;
9573   priv.max_fetched = priv.the_buffer;
9574   priv.insn_start = pc;
9575
9576   obuf[0] = 0;
9577   for (i = 0; i < MAX_OPERANDS; ++i)
9578     {
9579       op_out[i][0] = 0;
9580       op_index[i] = -1;
9581     }
9582
9583   the_info = info;
9584   start_pc = pc;
9585   start_codep = priv.the_buffer;
9586   codep = priv.the_buffer;
9587
9588   if (setjmp (priv.bailout) != 0)
9589     {
9590       const char *name;
9591
9592       /* Getting here means we tried for data but didn't get it.  That
9593          means we have an incomplete instruction of some sort.  Just
9594          print the first byte as a prefix or a .byte pseudo-op.  */
9595       if (codep > priv.the_buffer)
9596         {
9597           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9598           if (name != NULL)
9599             (*info->fprintf_func) (info->stream, "%s", name);
9600           else
9601             {
9602               /* Just print the first byte as a .byte instruction.  */
9603               (*info->fprintf_func) (info->stream, ".byte 0x%x",
9604                                      (unsigned int) priv.the_buffer[0]);
9605             }
9606
9607           return 1;
9608         }
9609
9610       return -1;
9611     }
9612
9613   obufp = obuf;
9614   ckprefix ();
9615
9616   insn_codep = codep;
9617   sizeflag = priv.orig_sizeflag;
9618
9619   FETCH_DATA (info, codep + 1);
9620   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9621
9622   if (((prefixes & PREFIX_FWAIT)
9623        && ((*codep < 0xd8) || (*codep > 0xdf)))
9624       || (rex && rex_used))
9625     {
9626       const char *name;
9627
9628       /* fwait not followed by floating point instruction, or rex followed
9629          by other prefixes.  Print the first prefix.  */
9630       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9631       if (name == NULL)
9632         name = INTERNAL_DISASSEMBLER_ERROR;
9633       (*info->fprintf_func) (info->stream, "%s", name);
9634       return 1;
9635     }
9636
9637   op = 0;
9638
9639   if (*codep == 0x0f)
9640     {
9641       unsigned char threebyte;
9642       FETCH_DATA (info, codep + 2);
9643       threebyte = *++codep;
9644       dp = &dis386_twobyte[threebyte];
9645       need_modrm = twobyte_has_modrm[*codep];
9646       codep++;
9647     }
9648   else
9649     {
9650       dp = &dis386[*codep];
9651       need_modrm = onebyte_has_modrm[*codep];
9652       codep++;
9653     }
9654
9655   if ((prefixes & PREFIX_REPZ))
9656     {
9657       repz_prefix = "repz ";
9658       used_prefixes |= PREFIX_REPZ;
9659     }
9660   else
9661     repz_prefix = NULL;
9662
9663   if ((prefixes & PREFIX_REPNZ))
9664     {
9665       repnz_prefix = "repnz ";
9666       used_prefixes |= PREFIX_REPNZ;
9667     }
9668   else
9669     repnz_prefix = NULL;
9670
9671   if ((prefixes & PREFIX_LOCK))
9672     {
9673       lock_prefix = "lock ";
9674       used_prefixes |= PREFIX_LOCK;
9675     }
9676   else
9677     lock_prefix = NULL;
9678
9679   addr_prefix = NULL;
9680   if (prefixes & PREFIX_ADDR)
9681     {
9682       sizeflag ^= AFLAG;
9683       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
9684         {
9685           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
9686             addr_prefix = "addr32 ";
9687           else
9688             addr_prefix = "addr16 ";
9689           used_prefixes |= PREFIX_ADDR;
9690         }
9691     }
9692
9693   data_prefix = NULL;
9694   if ((prefixes & PREFIX_DATA))
9695     {
9696       sizeflag ^= DFLAG;
9697       if (dp->op[2].bytemode == cond_jump_mode
9698           && dp->op[0].bytemode == v_mode
9699           && !intel_syntax)
9700         {
9701           if (sizeflag & DFLAG)
9702             data_prefix = "data32 ";
9703           else
9704             data_prefix = "data16 ";
9705           used_prefixes |= PREFIX_DATA;
9706         }
9707     }
9708
9709   if (need_modrm)
9710     {
9711       FETCH_DATA (info, codep + 1);
9712       modrm.mod = (*codep >> 6) & 3;
9713       modrm.reg = (*codep >> 3) & 7;
9714       modrm.rm = *codep & 7;
9715     }
9716
9717    need_vex = 0;
9718    need_vex_reg = 0;
9719    vex_w_done = 0;
9720
9721   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9722     {
9723       dofloat (sizeflag);
9724     }
9725   else
9726     {
9727       dp = get_valid_dis386 (dp, info);
9728       if (dp != NULL && putop (dp->name, sizeflag) == 0)
9729         {
9730           for (i = 0; i < MAX_OPERANDS; ++i)
9731             {
9732               obufp = op_out[i];
9733               op_ad = MAX_OPERANDS - 1 - i;
9734               if (dp->op[i].rtn)
9735                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9736             }
9737         }
9738     }
9739
9740   /* See if any prefixes were not used.  If so, print the first one
9741      separately.  If we don't do this, we'll wind up printing an
9742      instruction stream which does not precisely correspond to the
9743      bytes we are disassembling.  */
9744   if ((prefixes & ~used_prefixes) != 0)
9745     {
9746       const char *name;
9747
9748       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9749       if (name == NULL)
9750         name = INTERNAL_DISASSEMBLER_ERROR;
9751       (*info->fprintf_func) (info->stream, "%s", name);
9752       return 1;
9753     }
9754   if ((rex_original & ~rex_used) || rex_ignored)
9755     {
9756       const char *name;
9757       name = prefix_name (rex_original, priv.orig_sizeflag);
9758       if (name == NULL)
9759         name = INTERNAL_DISASSEMBLER_ERROR;
9760       (*info->fprintf_func) (info->stream, "%s ", name);
9761     }
9762
9763   prefix_obuf[0] = 0;
9764   prefix_obufp = prefix_obuf;
9765   if (lock_prefix)
9766     prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
9767   if (repz_prefix)
9768     prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
9769   if (repnz_prefix)
9770     prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
9771   if (addr_prefix)
9772     prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
9773   if (data_prefix)
9774     prefix_obufp = stpcpy (prefix_obufp, data_prefix);
9775
9776   if (prefix_obuf[0] != 0)
9777     (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
9778
9779   obufp = mnemonicendp;
9780   for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
9781     oappend (" ");
9782   oappend (" ");
9783   (*info->fprintf_func) (info->stream, "%s", obuf);
9784
9785   /* The enter and bound instructions are printed with operands in the same
9786      order as the intel book; everything else is printed in reverse order.  */
9787   if (intel_syntax || two_source_ops)
9788     {
9789       bfd_vma riprel;
9790
9791       for (i = 0; i < MAX_OPERANDS; ++i)
9792         op_txt[i] = op_out[i];
9793
9794       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9795         {
9796           op_ad = op_index[i];
9797           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
9798           op_index[MAX_OPERANDS - 1 - i] = op_ad;
9799           riprel = op_riprel[i];
9800           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
9801           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9802         }
9803     }
9804   else
9805     {
9806       for (i = 0; i < MAX_OPERANDS; ++i)
9807         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
9808     }
9809
9810   needcomma = 0;
9811   for (i = 0; i < MAX_OPERANDS; ++i)
9812     if (*op_txt[i])
9813       {
9814         if (needcomma)
9815           (*info->fprintf_func) (info->stream, ",");
9816         if (op_index[i] != -1 && !op_riprel[i])
9817           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
9818         else
9819           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
9820         needcomma = 1;
9821       }
9822
9823   for (i = 0; i < MAX_OPERANDS; i++)
9824     if (op_index[i] != -1 && op_riprel[i])
9825       {
9826         (*info->fprintf_func) (info->stream, "        # ");
9827         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
9828                                                 + op_address[op_index[i]]), info);
9829         break;
9830       }
9831   return codep - priv.the_buffer;
9832 }
9833
9834 static const char *float_mem[] = {
9835   /* d8 */
9836   "fadd{s|}",
9837   "fmul{s|}",
9838   "fcom{s|}",
9839   "fcomp{s|}",
9840   "fsub{s|}",
9841   "fsubr{s|}",
9842   "fdiv{s|}",
9843   "fdivr{s|}",
9844   /* d9 */
9845   "fld{s|}",
9846   "(bad)",
9847   "fst{s|}",
9848   "fstp{s|}",
9849   "fldenvIC",
9850   "fldcw",
9851   "fNstenvIC",
9852   "fNstcw",
9853   /* da */
9854   "fiadd{l|}",
9855   "fimul{l|}",
9856   "ficom{l|}",
9857   "ficomp{l|}",
9858   "fisub{l|}",
9859   "fisubr{l|}",
9860   "fidiv{l|}",
9861   "fidivr{l|}",
9862   /* db */
9863   "fild{l|}",
9864   "fisttp{l|}",
9865   "fist{l|}",
9866   "fistp{l|}",
9867   "(bad)",
9868   "fld{t||t|}",
9869   "(bad)",
9870   "fstp{t||t|}",
9871   /* dc */
9872   "fadd{l|}",
9873   "fmul{l|}",
9874   "fcom{l|}",
9875   "fcomp{l|}",
9876   "fsub{l|}",
9877   "fsubr{l|}",
9878   "fdiv{l|}",
9879   "fdivr{l|}",
9880   /* dd */
9881   "fld{l|}",
9882   "fisttp{ll|}",
9883   "fst{l||}",
9884   "fstp{l|}",
9885   "frstorIC",
9886   "(bad)",
9887   "fNsaveIC",
9888   "fNstsw",
9889   /* de */
9890   "fiadd",
9891   "fimul",
9892   "ficom",
9893   "ficomp",
9894   "fisub",
9895   "fisubr",
9896   "fidiv",
9897   "fidivr",
9898   /* df */
9899   "fild",
9900   "fisttp",
9901   "fist",
9902   "fistp",
9903   "fbld",
9904   "fild{ll|}",
9905   "fbstp",
9906   "fistp{ll|}",
9907 };
9908
9909 static const unsigned char float_mem_mode[] = {
9910   /* d8 */
9911   d_mode,
9912   d_mode,
9913   d_mode,
9914   d_mode,
9915   d_mode,
9916   d_mode,
9917   d_mode,
9918   d_mode,
9919   /* d9 */
9920   d_mode,
9921   0,
9922   d_mode,
9923   d_mode,
9924   0,
9925   w_mode,
9926   0,
9927   w_mode,
9928   /* da */
9929   d_mode,
9930   d_mode,
9931   d_mode,
9932   d_mode,
9933   d_mode,
9934   d_mode,
9935   d_mode,
9936   d_mode,
9937   /* db */
9938   d_mode,
9939   d_mode,
9940   d_mode,
9941   d_mode,
9942   0,
9943   t_mode,
9944   0,
9945   t_mode,
9946   /* dc */
9947   q_mode,
9948   q_mode,
9949   q_mode,
9950   q_mode,
9951   q_mode,
9952   q_mode,
9953   q_mode,
9954   q_mode,
9955   /* dd */
9956   q_mode,
9957   q_mode,
9958   q_mode,
9959   q_mode,
9960   0,
9961   0,
9962   0,
9963   w_mode,
9964   /* de */
9965   w_mode,
9966   w_mode,
9967   w_mode,
9968   w_mode,
9969   w_mode,
9970   w_mode,
9971   w_mode,
9972   w_mode,
9973   /* df */
9974   w_mode,
9975   w_mode,
9976   w_mode,
9977   w_mode,
9978   t_mode,
9979   q_mode,
9980   t_mode,
9981   q_mode
9982 };
9983
9984 #define ST { OP_ST, 0 }
9985 #define STi { OP_STi, 0 }
9986
9987 #define FGRPd9_2 NULL, { { NULL, 0 } }
9988 #define FGRPd9_4 NULL, { { NULL, 1 } }
9989 #define FGRPd9_5 NULL, { { NULL, 2 } }
9990 #define FGRPd9_6 NULL, { { NULL, 3 } }
9991 #define FGRPd9_7 NULL, { { NULL, 4 } }
9992 #define FGRPda_5 NULL, { { NULL, 5 } }
9993 #define FGRPdb_4 NULL, { { NULL, 6 } }
9994 #define FGRPde_3 NULL, { { NULL, 7 } }
9995 #define FGRPdf_4 NULL, { { NULL, 8 } }
9996
9997 static const struct dis386 float_reg[][8] = {
9998   /* d8 */
9999   {
10000     { "fadd",   { ST, STi } },
10001     { "fmul",   { ST, STi } },
10002     { "fcom",   { STi } },
10003     { "fcomp",  { STi } },
10004     { "fsub",   { ST, STi } },
10005     { "fsubr",  { ST, STi } },
10006     { "fdiv",   { ST, STi } },
10007     { "fdivr",  { ST, STi } },
10008   },
10009   /* d9 */
10010   {
10011     { "fld",    { STi } },
10012     { "fxch",   { STi } },
10013     { FGRPd9_2 },
10014     { "(bad)",  { XX } },
10015     { FGRPd9_4 },
10016     { FGRPd9_5 },
10017     { FGRPd9_6 },
10018     { FGRPd9_7 },
10019   },
10020   /* da */
10021   {
10022     { "fcmovb", { ST, STi } },
10023     { "fcmove", { ST, STi } },
10024     { "fcmovbe",{ ST, STi } },
10025     { "fcmovu", { ST, STi } },
10026     { "(bad)",  { XX } },
10027     { FGRPda_5 },
10028     { "(bad)",  { XX } },
10029     { "(bad)",  { XX } },
10030   },
10031   /* db */
10032   {
10033     { "fcmovnb",{ ST, STi } },
10034     { "fcmovne",{ ST, STi } },
10035     { "fcmovnbe",{ ST, STi } },
10036     { "fcmovnu",{ ST, STi } },
10037     { FGRPdb_4 },
10038     { "fucomi", { ST, STi } },
10039     { "fcomi",  { ST, STi } },
10040     { "(bad)",  { XX } },
10041   },
10042   /* dc */
10043   {
10044     { "fadd",   { STi, ST } },
10045     { "fmul",   { STi, ST } },
10046     { "(bad)",  { XX } },
10047     { "(bad)",  { XX } },
10048     { "fsub!M", { STi, ST } },
10049     { "fsubM",  { STi, ST } },
10050     { "fdiv!M", { STi, ST } },
10051     { "fdivM",  { STi, ST } },
10052   },
10053   /* dd */
10054   {
10055     { "ffree",  { STi } },
10056     { "(bad)",  { XX } },
10057     { "fst",    { STi } },
10058     { "fstp",   { STi } },
10059     { "fucom",  { STi } },
10060     { "fucomp", { STi } },
10061     { "(bad)",  { XX } },
10062     { "(bad)",  { XX } },
10063   },
10064   /* de */
10065   {
10066     { "faddp",  { STi, ST } },
10067     { "fmulp",  { STi, ST } },
10068     { "(bad)",  { XX } },
10069     { FGRPde_3 },
10070     { "fsub!Mp", { STi, ST } },
10071     { "fsubMp", { STi, ST } },
10072     { "fdiv!Mp", { STi, ST } },
10073     { "fdivMp", { STi, ST } },
10074   },
10075   /* df */
10076   {
10077     { "ffreep", { STi } },
10078     { "(bad)",  { XX } },
10079     { "(bad)",  { XX } },
10080     { "(bad)",  { XX } },
10081     { FGRPdf_4 },
10082     { "fucomip", { ST, STi } },
10083     { "fcomip", { ST, STi } },
10084     { "(bad)",  { XX } },
10085   },
10086 };
10087
10088 static char *fgrps[][8] = {
10089   /* d9_2  0 */
10090   {
10091     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10092   },
10093
10094   /* d9_4  1 */
10095   {
10096     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10097   },
10098
10099   /* d9_5  2 */
10100   {
10101     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10102   },
10103
10104   /* d9_6  3 */
10105   {
10106     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10107   },
10108
10109   /* d9_7  4 */
10110   {
10111     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10112   },
10113
10114   /* da_5  5 */
10115   {
10116     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10117   },
10118
10119   /* db_4  6 */
10120   {
10121     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10122     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10123   },
10124
10125   /* de_3  7 */
10126   {
10127     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10128   },
10129
10130   /* df_4  8 */
10131   {
10132     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10133   },
10134 };
10135
10136 static void
10137 swap_operand (void)
10138 {
10139   mnemonicendp[0] = '.';
10140   mnemonicendp[1] = 's';
10141   mnemonicendp += 2;
10142 }
10143
10144 static void
10145 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10146                int sizeflag ATTRIBUTE_UNUSED)
10147 {
10148   /* Skip mod/rm byte.  */
10149   MODRM_CHECK;
10150   codep++;
10151 }
10152
10153 static void
10154 dofloat (int sizeflag)
10155 {
10156   const struct dis386 *dp;
10157   unsigned char floatop;
10158
10159   floatop = codep[-1];
10160
10161   if (modrm.mod != 3)
10162     {
10163       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10164
10165       putop (float_mem[fp_indx], sizeflag);
10166       obufp = op_out[0];
10167       op_ad = 2;
10168       OP_E (float_mem_mode[fp_indx], sizeflag);
10169       return;
10170     }
10171   /* Skip mod/rm byte.  */
10172   MODRM_CHECK;
10173   codep++;
10174
10175   dp = &float_reg[floatop - 0xd8][modrm.reg];
10176   if (dp->name == NULL)
10177     {
10178       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10179
10180       /* Instruction fnstsw is only one with strange arg.  */
10181       if (floatop == 0xdf && codep[-1] == 0xe0)
10182         strcpy (op_out[0], names16[0]);
10183     }
10184   else
10185     {
10186       putop (dp->name, sizeflag);
10187
10188       obufp = op_out[0];
10189       op_ad = 2;
10190       if (dp->op[0].rtn)
10191         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10192
10193       obufp = op_out[1];
10194       op_ad = 1;
10195       if (dp->op[1].rtn)
10196         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10197     }
10198 }
10199
10200 static void
10201 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10202 {
10203   oappend ("%st" + intel_syntax);
10204 }
10205
10206 static void
10207 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10208 {
10209   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10210   oappend (scratchbuf + intel_syntax);
10211 }
10212
10213 /* Capital letters in template are macros.  */
10214 static int
10215 putop (const char *in_template, int sizeflag)
10216 {
10217   const char *p;
10218   int alt = 0;
10219   int cond = 1;
10220   unsigned int l = 0, len = 1;
10221   char last[4];
10222
10223 #define SAVE_LAST(c)                    \
10224   if (l < len && l < sizeof (last))     \
10225     last[l++] = c;                      \
10226   else                                  \
10227     abort ();
10228
10229   for (p = in_template; *p; p++)
10230     {
10231       switch (*p)
10232         {
10233         default:
10234           *obufp++ = *p;
10235           break;
10236         case '%':
10237           len++;
10238           break;
10239         case '!':
10240           cond = 0;
10241           break;
10242         case '{':
10243           alt = 0;
10244           if (intel_syntax)
10245             {
10246               while (*++p != '|')
10247                 if (*p == '}' || *p == '\0')
10248                   abort ();
10249             }
10250           /* Fall through.  */
10251         case 'I':
10252           alt = 1;
10253           continue;
10254         case '|':
10255           while (*++p != '}')
10256             {
10257               if (*p == '\0')
10258                 abort ();
10259             }
10260           break;
10261         case '}':
10262           break;
10263         case 'A':
10264           if (intel_syntax)
10265             break;
10266           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10267             *obufp++ = 'b';
10268           break;
10269         case 'B':
10270           if (l == 0 && len == 1)
10271             {
10272 case_B:
10273               if (intel_syntax)
10274                 break;
10275               if (sizeflag & SUFFIX_ALWAYS)
10276                 *obufp++ = 'b';
10277             }
10278           else
10279             {
10280               if (l != 1
10281                   || len != 2
10282                   || last[0] != 'L')
10283                 {
10284                   SAVE_LAST (*p);
10285                   break;
10286                 }
10287
10288               if (address_mode == mode_64bit
10289                   && !(prefixes & PREFIX_ADDR))
10290                 {
10291                   *obufp++ = 'a';
10292                   *obufp++ = 'b';
10293                   *obufp++ = 's';
10294                 }
10295
10296               goto case_B;
10297             }
10298           break;
10299         case 'C':
10300           if (intel_syntax && !alt)
10301             break;
10302           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10303             {
10304               if (sizeflag & DFLAG)
10305                 *obufp++ = intel_syntax ? 'd' : 'l';
10306               else
10307                 *obufp++ = intel_syntax ? 'w' : 's';
10308               used_prefixes |= (prefixes & PREFIX_DATA);
10309             }
10310           break;
10311         case 'D':
10312           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10313             break;
10314           USED_REX (REX_W);
10315           if (modrm.mod == 3)
10316             {
10317               if (rex & REX_W)
10318                 *obufp++ = 'q';
10319               else if (sizeflag & DFLAG)
10320                 *obufp++ = intel_syntax ? 'd' : 'l';
10321               else
10322                 *obufp++ = 'w';
10323               used_prefixes |= (prefixes & PREFIX_DATA);
10324             }
10325           else
10326             *obufp++ = 'w';
10327           break;
10328         case 'E':               /* For jcxz/jecxz */
10329           if (address_mode == mode_64bit)
10330             {
10331               if (sizeflag & AFLAG)
10332                 *obufp++ = 'r';
10333               else
10334                 *obufp++ = 'e';
10335             }
10336           else
10337             if (sizeflag & AFLAG)
10338               *obufp++ = 'e';
10339           used_prefixes |= (prefixes & PREFIX_ADDR);
10340           break;
10341         case 'F':
10342           if (intel_syntax)
10343             break;
10344           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10345             {
10346               if (sizeflag & AFLAG)
10347                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10348               else
10349                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10350               used_prefixes |= (prefixes & PREFIX_ADDR);
10351             }
10352           break;
10353         case 'G':
10354           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10355             break;
10356           if ((rex & REX_W) || (sizeflag & DFLAG))
10357             *obufp++ = 'l';
10358           else
10359             *obufp++ = 'w';
10360           if (!(rex & REX_W))
10361             used_prefixes |= (prefixes & PREFIX_DATA);
10362           break;
10363         case 'H':
10364           if (intel_syntax)
10365             break;
10366           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10367               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10368             {
10369               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10370               *obufp++ = ',';
10371               *obufp++ = 'p';
10372               if (prefixes & PREFIX_DS)
10373                 *obufp++ = 't';
10374               else
10375                 *obufp++ = 'n';
10376             }
10377           break;
10378         case 'J':
10379           if (intel_syntax)
10380             break;
10381           *obufp++ = 'l';
10382           break;
10383         case 'K':
10384           USED_REX (REX_W);
10385           if (rex & REX_W)
10386             *obufp++ = 'q';
10387           else
10388             *obufp++ = 'd';
10389           break;
10390         case 'Z':
10391           if (intel_syntax)
10392             break;
10393           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10394             {
10395               *obufp++ = 'q';
10396               break;
10397             }
10398           /* Fall through.  */
10399           goto case_L;
10400         case 'L':
10401           if (l != 0 || len != 1)
10402             {
10403               SAVE_LAST (*p);
10404               break;
10405             }
10406 case_L:
10407           if (intel_syntax)
10408             break;
10409           if (sizeflag & SUFFIX_ALWAYS)
10410             *obufp++ = 'l';
10411           break;
10412         case 'M':
10413           if (intel_mnemonic != cond)
10414             *obufp++ = 'r';
10415           break;
10416         case 'N':
10417           if ((prefixes & PREFIX_FWAIT) == 0)
10418             *obufp++ = 'n';
10419           else
10420             used_prefixes |= PREFIX_FWAIT;
10421           break;
10422         case 'O':
10423           USED_REX (REX_W);
10424           if (rex & REX_W)
10425             *obufp++ = 'o';
10426           else if (intel_syntax && (sizeflag & DFLAG))
10427             *obufp++ = 'q';
10428           else
10429             *obufp++ = 'd';
10430           if (!(rex & REX_W))
10431             used_prefixes |= (prefixes & PREFIX_DATA);
10432           break;
10433         case 'T':
10434           if (intel_syntax)
10435             break;
10436           if (address_mode == mode_64bit && (sizeflag & DFLAG))
10437             {
10438               *obufp++ = 'q';
10439               break;
10440             }
10441           /* Fall through.  */
10442         case 'P':
10443           if (intel_syntax)
10444             break;
10445           if ((prefixes & PREFIX_DATA)
10446               || (rex & REX_W)
10447               || (sizeflag & SUFFIX_ALWAYS))
10448             {
10449               USED_REX (REX_W);
10450               if (rex & REX_W)
10451                 *obufp++ = 'q';
10452               else
10453                 {
10454                    if (sizeflag & DFLAG)
10455                       *obufp++ = 'l';
10456                    else
10457                      *obufp++ = 'w';
10458                 }
10459               used_prefixes |= (prefixes & PREFIX_DATA);
10460             }
10461           break;
10462         case 'U':
10463           if (intel_syntax)
10464             break;
10465           if (address_mode == mode_64bit && (sizeflag & DFLAG))
10466             {
10467               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10468                 *obufp++ = 'q';
10469               break;
10470             }
10471           /* Fall through.  */
10472           goto case_Q;
10473         case 'Q':
10474           if (l == 0 && len == 1)
10475             {
10476 case_Q:
10477               if (intel_syntax && !alt)
10478                 break;
10479               USED_REX (REX_W);
10480               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10481                 {
10482                   if (rex & REX_W)
10483                     *obufp++ = 'q';
10484                   else
10485                     {
10486                       if (sizeflag & DFLAG)
10487                         *obufp++ = intel_syntax ? 'd' : 'l';
10488                       else
10489                         *obufp++ = 'w';
10490                     }
10491                   used_prefixes |= (prefixes & PREFIX_DATA);
10492                 }
10493             }
10494           else
10495             {
10496               if (l != 1 || len != 2 || last[0] != 'L')
10497                 {
10498                   SAVE_LAST (*p);
10499                   break;
10500                 }
10501               if (intel_syntax
10502                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
10503                 break;
10504               if ((rex & REX_W))
10505                 {
10506                   USED_REX (REX_W);
10507                   *obufp++ = 'q';
10508                 }
10509               else
10510                 *obufp++ = 'l';
10511             }
10512           break;
10513         case 'R':
10514           USED_REX (REX_W);
10515           if (rex & REX_W)
10516             *obufp++ = 'q';
10517           else if (sizeflag & DFLAG)
10518             {
10519               if (intel_syntax)
10520                   *obufp++ = 'd';
10521               else
10522                   *obufp++ = 'l';
10523             }
10524           else
10525             *obufp++ = 'w';
10526           if (intel_syntax && !p[1]
10527               && ((rex & REX_W) || (sizeflag & DFLAG)))
10528             *obufp++ = 'e';
10529           if (!(rex & REX_W))
10530             used_prefixes |= (prefixes & PREFIX_DATA);
10531           break;
10532         case 'V':
10533           if (l == 0 && len == 1)
10534             {
10535               if (intel_syntax)
10536                 break;
10537               if (address_mode == mode_64bit && (sizeflag & DFLAG))
10538                 {
10539                   if (sizeflag & SUFFIX_ALWAYS)
10540                     *obufp++ = 'q';
10541                   break;
10542                 }
10543             }
10544           else
10545             {
10546               if (l != 1
10547                   || len != 2
10548                   || last[0] != 'L')
10549                 {
10550                   SAVE_LAST (*p);
10551                   break;
10552                 }
10553
10554               if (rex & REX_W)
10555                 {
10556                   *obufp++ = 'a';
10557                   *obufp++ = 'b';
10558                   *obufp++ = 's';
10559                 }
10560             }
10561           /* Fall through.  */
10562           goto case_S;
10563         case 'S':
10564           if (l == 0 && len == 1)
10565             {
10566 case_S:
10567               if (intel_syntax)
10568                 break;
10569               if (sizeflag & SUFFIX_ALWAYS)
10570                 {
10571                   if (rex & REX_W)
10572                     *obufp++ = 'q';
10573                   else
10574                     {
10575                       if (sizeflag & DFLAG)
10576                         *obufp++ = 'l';
10577                       else
10578                         *obufp++ = 'w';
10579                       used_prefixes |= (prefixes & PREFIX_DATA);
10580                     }
10581                 }
10582             }
10583           else
10584             {
10585               if (l != 1
10586                   || len != 2
10587                   || last[0] != 'L')
10588                 {
10589                   SAVE_LAST (*p);
10590                   break;
10591                 }
10592
10593               if (address_mode == mode_64bit
10594                   && !(prefixes & PREFIX_ADDR))
10595                 {
10596                   *obufp++ = 'a';
10597                   *obufp++ = 'b';
10598                   *obufp++ = 's';
10599                 }
10600
10601               goto case_S;
10602             }
10603           break;
10604         case 'X':
10605           if (l != 0 || len != 1)
10606             {
10607               SAVE_LAST (*p);
10608               break;
10609             }
10610           if (need_vex && vex.prefix)
10611             {
10612               if (vex.prefix == DATA_PREFIX_OPCODE)
10613                 *obufp++ = 'd';
10614               else
10615                 *obufp++ = 's';
10616             }
10617           else if (prefixes & PREFIX_DATA)
10618             *obufp++ = 'd';
10619           else
10620             *obufp++ = 's';
10621           used_prefixes |= (prefixes & PREFIX_DATA);
10622           break;
10623         case 'Y':
10624           if (l == 0 && len == 1)
10625             {
10626               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10627                 break;
10628               if (rex & REX_W)
10629                 {
10630                   USED_REX (REX_W);
10631                   *obufp++ = 'q';
10632                 }
10633               break;
10634             }
10635           else
10636             {
10637               if (l != 1 || len != 2 || last[0] != 'X')
10638                 {
10639                   SAVE_LAST (*p);
10640                   break;
10641                 }
10642               if (!need_vex)
10643                 abort ();
10644               if (intel_syntax
10645                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
10646                 break;
10647               switch (vex.length)
10648                 {
10649                 case 128:
10650                   *obufp++ = 'x';
10651                   break;
10652                 case 256:
10653                   *obufp++ = 'y';
10654                   break;
10655                 default:
10656                   abort ();
10657                 }
10658             }
10659           break;
10660         case 'W':
10661           if (l == 0 && len == 1)
10662             {
10663               /* operand size flag for cwtl, cbtw */
10664               USED_REX (REX_W);
10665               if (rex & REX_W)
10666                 {
10667                   if (intel_syntax)
10668                     *obufp++ = 'd';
10669                   else
10670                     *obufp++ = 'l';
10671                 }
10672               else if (sizeflag & DFLAG)
10673                 *obufp++ = 'w';
10674               else
10675                 *obufp++ = 'b';
10676               if (!(rex & REX_W))
10677                 used_prefixes |= (prefixes & PREFIX_DATA);
10678             }
10679           else
10680             {
10681               if (l != 1 || len != 2 || last[0] != 'X')
10682                 {
10683                   SAVE_LAST (*p);
10684                   break;
10685                 }
10686               if (!need_vex)
10687                 abort ();
10688               *obufp++ = vex.w ? 'd': 's';
10689             }
10690           break;
10691         }
10692       alt = 0;
10693     }
10694   *obufp = 0;
10695   mnemonicendp = obufp;
10696   return 0;
10697 }
10698
10699 static void
10700 oappend (const char *s)
10701 {
10702   obufp = stpcpy (obufp, s);
10703 }
10704
10705 static void
10706 append_seg (void)
10707 {
10708   if (prefixes & PREFIX_CS)
10709     {
10710       used_prefixes |= PREFIX_CS;
10711       oappend ("%cs:" + intel_syntax);
10712     }
10713   if (prefixes & PREFIX_DS)
10714     {
10715       used_prefixes |= PREFIX_DS;
10716       oappend ("%ds:" + intel_syntax);
10717     }
10718   if (prefixes & PREFIX_SS)
10719     {
10720       used_prefixes |= PREFIX_SS;
10721       oappend ("%ss:" + intel_syntax);
10722     }
10723   if (prefixes & PREFIX_ES)
10724     {
10725       used_prefixes |= PREFIX_ES;
10726       oappend ("%es:" + intel_syntax);
10727     }
10728   if (prefixes & PREFIX_FS)
10729     {
10730       used_prefixes |= PREFIX_FS;
10731       oappend ("%fs:" + intel_syntax);
10732     }
10733   if (prefixes & PREFIX_GS)
10734     {
10735       used_prefixes |= PREFIX_GS;
10736       oappend ("%gs:" + intel_syntax);
10737     }
10738 }
10739
10740 static void
10741 OP_indirE (int bytemode, int sizeflag)
10742 {
10743   if (!intel_syntax)
10744     oappend ("*");
10745   OP_E (bytemode, sizeflag);
10746 }
10747
10748 static void
10749 print_operand_value (char *buf, int hex, bfd_vma disp)
10750 {
10751   if (address_mode == mode_64bit)
10752     {
10753       if (hex)
10754         {
10755           char tmp[30];
10756           int i;
10757           buf[0] = '0';
10758           buf[1] = 'x';
10759           sprintf_vma (tmp, disp);
10760           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10761           strcpy (buf + 2, tmp + i);
10762         }
10763       else
10764         {
10765           bfd_signed_vma v = disp;
10766           char tmp[30];
10767           int i;
10768           if (v < 0)
10769             {
10770               *(buf++) = '-';
10771               v = -disp;
10772               /* Check for possible overflow on 0x8000000000000000.  */
10773               if (v < 0)
10774                 {
10775                   strcpy (buf, "9223372036854775808");
10776                   return;
10777                 }
10778             }
10779           if (!v)
10780             {
10781               strcpy (buf, "0");
10782               return;
10783             }
10784
10785           i = 0;
10786           tmp[29] = 0;
10787           while (v)
10788             {
10789               tmp[28 - i] = (v % 10) + '0';
10790               v /= 10;
10791               i++;
10792             }
10793           strcpy (buf, tmp + 29 - i);
10794         }
10795     }
10796   else
10797     {
10798       if (hex)
10799         sprintf (buf, "0x%x", (unsigned int) disp);
10800       else
10801         sprintf (buf, "%d", (int) disp);
10802     }
10803 }
10804
10805 /* Put DISP in BUF as signed hex number.  */
10806
10807 static void
10808 print_displacement (char *buf, bfd_vma disp)
10809 {
10810   bfd_signed_vma val = disp;
10811   char tmp[30];
10812   int i, j = 0;
10813
10814   if (val < 0)
10815     {
10816       buf[j++] = '-';
10817       val = -disp;
10818
10819       /* Check for possible overflow.  */
10820       if (val < 0)
10821         {
10822           switch (address_mode)
10823             {
10824             case mode_64bit:
10825               strcpy (buf + j, "0x8000000000000000");
10826               break;
10827             case mode_32bit:
10828               strcpy (buf + j, "0x80000000");
10829               break;
10830             case mode_16bit:
10831               strcpy (buf + j, "0x8000");
10832               break;
10833             }
10834           return;
10835         }
10836     }
10837
10838   buf[j++] = '0';
10839   buf[j++] = 'x';
10840
10841   sprintf_vma (tmp, (bfd_vma) val);
10842   for (i = 0; tmp[i] == '0'; i++)
10843     continue;
10844   if (tmp[i] == '\0')
10845     i--;
10846   strcpy (buf + j, tmp + i);
10847 }
10848
10849 static void
10850 intel_operand_size (int bytemode, int sizeflag)
10851 {
10852   switch (bytemode)
10853     {
10854     case b_mode:
10855     case b_swap_mode:
10856     case dqb_mode:
10857       oappend ("BYTE PTR ");
10858       break;
10859     case w_mode:
10860     case dqw_mode:
10861       oappend ("WORD PTR ");
10862       break;
10863     case stack_v_mode:
10864       if (address_mode == mode_64bit && (sizeflag & DFLAG))
10865         {
10866           oappend ("QWORD PTR ");
10867           used_prefixes |= (prefixes & PREFIX_DATA);
10868           break;
10869         }
10870       /* FALLTHRU */
10871     case v_mode:
10872     case v_swap_mode:
10873     case dq_mode:
10874       USED_REX (REX_W);
10875       if (rex & REX_W)
10876         oappend ("QWORD PTR ");
10877       else if ((sizeflag & DFLAG) || bytemode == dq_mode)
10878         oappend ("DWORD PTR ");
10879       else
10880         oappend ("WORD PTR ");
10881       used_prefixes |= (prefixes & PREFIX_DATA);
10882       break;
10883     case z_mode:
10884       if ((rex & REX_W) || (sizeflag & DFLAG))
10885         *obufp++ = 'D';
10886       oappend ("WORD PTR ");
10887       if (!(rex & REX_W))
10888         used_prefixes |= (prefixes & PREFIX_DATA);
10889       break;
10890     case a_mode:
10891       if (sizeflag & DFLAG)
10892         oappend ("QWORD PTR ");
10893       else
10894         oappend ("DWORD PTR ");
10895       used_prefixes |= (prefixes & PREFIX_DATA);
10896       break;
10897     case d_mode:
10898     case d_swap_mode:
10899     case dqd_mode:
10900       oappend ("DWORD PTR ");
10901       break;
10902     case q_mode:
10903     case q_swap_mode:
10904       oappend ("QWORD PTR ");
10905       break;
10906     case m_mode:
10907       if (address_mode == mode_64bit)
10908         oappend ("QWORD PTR ");
10909       else
10910         oappend ("DWORD PTR ");
10911       break;
10912     case f_mode:
10913       if (sizeflag & DFLAG)
10914         oappend ("FWORD PTR ");
10915       else
10916         oappend ("DWORD PTR ");
10917       used_prefixes |= (prefixes & PREFIX_DATA);
10918       break;
10919     case t_mode:
10920       oappend ("TBYTE PTR ");
10921       break;
10922     case x_mode:
10923     case x_swap_mode:
10924       if (need_vex)
10925         {
10926           switch (vex.length)
10927             {
10928             case 128:
10929               oappend ("XMMWORD PTR ");
10930               break;
10931             case 256:
10932               oappend ("YMMWORD PTR ");
10933               break;
10934             default:
10935               abort ();
10936             }
10937         }
10938       else
10939         oappend ("XMMWORD PTR ");
10940       break;
10941     case xmm_mode:
10942       oappend ("XMMWORD PTR ");
10943       break;
10944     case xmmq_mode:
10945       if (!need_vex)
10946         abort ();
10947
10948       switch (vex.length)
10949         {
10950         case 128:
10951           oappend ("QWORD PTR ");
10952           break;
10953         case 256:
10954           oappend ("XMMWORD PTR ");
10955           break;
10956         default:
10957           abort ();
10958         }
10959       break;
10960     case ymmq_mode:
10961       if (!need_vex)
10962         abort ();
10963
10964       switch (vex.length)
10965         {
10966         case 128:
10967           oappend ("QWORD PTR ");
10968           break;
10969         case 256:
10970           oappend ("YMMWORD PTR ");
10971           break;
10972         default:
10973           abort ();
10974         }
10975       break;
10976     case o_mode:
10977       oappend ("OWORD PTR ");
10978       break;
10979     case vex_w_dq_mode:
10980       if (!need_vex)
10981         abort ();
10982
10983       if (vex.w)
10984         oappend ("QWORD PTR ");
10985       else
10986         oappend ("DWORD PTR ");
10987       break;
10988     default:
10989       break;
10990     }
10991 }
10992
10993 static void
10994 OP_E_register (int bytemode, int sizeflag)
10995 {
10996   int reg = modrm.rm;
10997   const char **names;
10998
10999   USED_REX (REX_B);
11000   if ((rex & REX_B))
11001     reg += 8;
11002
11003   if ((sizeflag & SUFFIX_ALWAYS)
11004       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
11005     swap_operand ();
11006
11007   switch (bytemode)
11008     {
11009     case b_mode:
11010     case b_swap_mode:
11011       USED_REX (0);
11012       if (rex)
11013         names = names8rex;
11014       else
11015         names = names8;
11016       break;
11017     case w_mode:
11018       names = names16;
11019       break;
11020     case d_mode:
11021       names = names32;
11022       break;
11023     case q_mode:
11024       names = names64;
11025       break;
11026     case m_mode:
11027       names = address_mode == mode_64bit ? names64 : names32;
11028       break;
11029     case stack_v_mode:
11030       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11031         {
11032           names = names64;
11033           used_prefixes |= (prefixes & PREFIX_DATA);
11034           break;
11035         }
11036       bytemode = v_mode;
11037       /* FALLTHRU */
11038     case v_mode:
11039     case v_swap_mode:
11040     case dq_mode:
11041     case dqb_mode:
11042     case dqd_mode:
11043     case dqw_mode:
11044       USED_REX (REX_W);
11045       if (rex & REX_W)
11046         names = names64;
11047       else if ((sizeflag & DFLAG)
11048                || (bytemode != v_mode
11049                    && bytemode != v_swap_mode))
11050         names = names32;
11051       else
11052         names = names16;
11053       used_prefixes |= (prefixes & PREFIX_DATA);
11054       break;
11055     case 0:
11056       return;
11057     default:
11058       oappend (INTERNAL_DISASSEMBLER_ERROR);
11059       return;
11060     }
11061   oappend (names[reg]);
11062 }
11063
11064 static void
11065 OP_E_memory (int bytemode, int sizeflag)
11066 {
11067   bfd_vma disp = 0;
11068   int add = (rex & REX_B) ? 8 : 0;
11069   int riprel = 0;
11070
11071   USED_REX (REX_B);
11072   if (intel_syntax)
11073     intel_operand_size (bytemode, sizeflag);
11074   append_seg ();
11075
11076   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11077     {
11078       /* 32/64 bit address mode */
11079       int havedisp;
11080       int havesib;
11081       int havebase;
11082       int haveindex;
11083       int needindex;
11084       int base, rbase;
11085       int index = 0;
11086       int scale = 0;
11087
11088       havesib = 0;
11089       havebase = 1;
11090       haveindex = 0;
11091       base = modrm.rm;
11092
11093       if (base == 4)
11094         {
11095           havesib = 1;
11096           FETCH_DATA (the_info, codep + 1);
11097           index = (*codep >> 3) & 7;
11098           scale = (*codep >> 6) & 3;
11099           base = *codep & 7;
11100           USED_REX (REX_X);
11101           if (rex & REX_X)
11102             index += 8;
11103           haveindex = index != 4;
11104           codep++;
11105         }
11106       rbase = base + add;
11107
11108       switch (modrm.mod)
11109         {
11110         case 0:
11111           if (base == 5)
11112             {
11113               havebase = 0;
11114               if (address_mode == mode_64bit && !havesib)
11115                 riprel = 1;
11116               disp = get32s ();
11117             }
11118           break;
11119         case 1:
11120           FETCH_DATA (the_info, codep + 1);
11121           disp = *codep++;
11122           if ((disp & 0x80) != 0)
11123             disp -= 0x100;
11124           break;
11125         case 2:
11126           disp = get32s ();
11127           break;
11128         }
11129
11130       /* In 32bit mode, we need index register to tell [offset] from
11131          [eiz*1 + offset].  */
11132       needindex = (havesib
11133                    && !havebase
11134                    && !haveindex
11135                    && address_mode == mode_32bit);
11136       havedisp = (havebase
11137                   || needindex
11138                   || (havesib && (haveindex || scale != 0)));
11139
11140       if (!intel_syntax)
11141         if (modrm.mod != 0 || base == 5)
11142           {
11143             if (havedisp || riprel)
11144               print_displacement (scratchbuf, disp);
11145             else
11146               print_operand_value (scratchbuf, 1, disp);
11147             oappend (scratchbuf);
11148             if (riprel)
11149               {
11150                 set_op (disp, 1);
11151                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11152               }
11153           }
11154
11155       if (havebase || haveindex || riprel)
11156         used_prefixes |= PREFIX_ADDR;
11157
11158       if (havedisp || (intel_syntax && riprel))
11159         {
11160           *obufp++ = open_char;
11161           if (intel_syntax && riprel)
11162             {
11163               set_op (disp, 1);
11164               oappend (sizeflag & AFLAG ? "rip" : "eip");
11165             }
11166           *obufp = '\0';
11167           if (havebase)
11168             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11169                      ? names64[rbase] : names32[rbase]);
11170           if (havesib)
11171             {
11172               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11173                  print index to tell base + index from base.  */
11174               if (scale != 0
11175                   || needindex
11176                   || haveindex
11177                   || (havebase && base != ESP_REG_NUM))
11178                 {
11179                   if (!intel_syntax || havebase)
11180                     {
11181                       *obufp++ = separator_char;
11182                       *obufp = '\0';
11183                     }
11184                   if (haveindex)
11185                     oappend (address_mode == mode_64bit
11186                              && (sizeflag & AFLAG)
11187                              ? names64[index] : names32[index]);
11188                   else
11189                     oappend (address_mode == mode_64bit
11190                              && (sizeflag & AFLAG)
11191                              ? index64 : index32);
11192
11193                   *obufp++ = scale_char;
11194                   *obufp = '\0';
11195                   sprintf (scratchbuf, "%d", 1 << scale);
11196                   oappend (scratchbuf);
11197                 }
11198             }
11199           if (intel_syntax
11200               && (disp || modrm.mod != 0 || base == 5))
11201             {
11202               if (!havedisp || (bfd_signed_vma) disp >= 0)
11203                 {
11204                   *obufp++ = '+';
11205                   *obufp = '\0';
11206                 }
11207               else if (modrm.mod != 1 && disp != -disp)
11208                 {
11209                   *obufp++ = '-';
11210                   *obufp = '\0';
11211                   disp = - (bfd_signed_vma) disp;
11212                 }
11213
11214               if (havedisp)
11215                 print_displacement (scratchbuf, disp);
11216               else
11217                 print_operand_value (scratchbuf, 1, disp);
11218               oappend (scratchbuf);
11219             }
11220
11221           *obufp++ = close_char;
11222           *obufp = '\0';
11223         }
11224       else if (intel_syntax)
11225         {
11226           if (modrm.mod != 0 || base == 5)
11227             {
11228               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11229                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11230                 ;
11231               else
11232                 {
11233                   oappend (names_seg[ds_reg - es_reg]);
11234                   oappend (":");
11235                 }
11236               print_operand_value (scratchbuf, 1, disp);
11237               oappend (scratchbuf);
11238             }
11239         }
11240     }
11241   else
11242     { /* 16 bit address mode */
11243       switch (modrm.mod)
11244         {
11245         case 0:
11246           if (modrm.rm == 6)
11247             {
11248               disp = get16 ();
11249               if ((disp & 0x8000) != 0)
11250                 disp -= 0x10000;
11251             }
11252           break;
11253         case 1:
11254           FETCH_DATA (the_info, codep + 1);
11255           disp = *codep++;
11256           if ((disp & 0x80) != 0)
11257             disp -= 0x100;
11258           break;
11259         case 2:
11260           disp = get16 ();
11261           if ((disp & 0x8000) != 0)
11262             disp -= 0x10000;
11263           break;
11264         }
11265
11266       if (!intel_syntax)
11267         if (modrm.mod != 0 || modrm.rm == 6)
11268           {
11269             print_displacement (scratchbuf, disp);
11270             oappend (scratchbuf);
11271           }
11272
11273       if (modrm.mod != 0 || modrm.rm != 6)
11274         {
11275           *obufp++ = open_char;
11276           *obufp = '\0';
11277           oappend (index16[modrm.rm]);
11278           if (intel_syntax
11279               && (disp || modrm.mod != 0 || modrm.rm == 6))
11280             {
11281               if ((bfd_signed_vma) disp >= 0)
11282                 {
11283                   *obufp++ = '+';
11284                   *obufp = '\0';
11285                 }
11286               else if (modrm.mod != 1)
11287                 {
11288                   *obufp++ = '-';
11289                   *obufp = '\0';
11290                   disp = - (bfd_signed_vma) disp;
11291                 }
11292
11293               print_displacement (scratchbuf, disp);
11294               oappend (scratchbuf);
11295             }
11296
11297           *obufp++ = close_char;
11298           *obufp = '\0';
11299         }
11300       else if (intel_syntax)
11301         {
11302           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11303                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11304             ;
11305           else
11306             {
11307               oappend (names_seg[ds_reg - es_reg]);
11308               oappend (":");
11309             }
11310           print_operand_value (scratchbuf, 1, disp & 0xffff);
11311           oappend (scratchbuf);
11312         }
11313     }
11314 }
11315
11316 static void
11317 OP_E_extended (int bytemode, int sizeflag)
11318 {
11319   /* Skip mod/rm byte.  */
11320   MODRM_CHECK;
11321   codep++;
11322
11323   if (modrm.mod == 3)
11324     OP_E_register (bytemode, sizeflag);
11325   else
11326     OP_E_memory (bytemode, sizeflag);
11327 }
11328
11329 static void
11330 OP_E (int bytemode, int sizeflag)
11331 {
11332   OP_E_extended (bytemode, sizeflag);
11333 }
11334
11335
11336 static void
11337 OP_G (int bytemode, int sizeflag)
11338 {
11339   int add = 0;
11340   USED_REX (REX_R);
11341   if (rex & REX_R)
11342     add += 8;
11343   switch (bytemode)
11344     {
11345     case b_mode:
11346       USED_REX (0);
11347       if (rex)
11348         oappend (names8rex[modrm.reg + add]);
11349       else
11350         oappend (names8[modrm.reg + add]);
11351       break;
11352     case w_mode:
11353       oappend (names16[modrm.reg + add]);
11354       break;
11355     case d_mode:
11356       oappend (names32[modrm.reg + add]);
11357       break;
11358     case q_mode:
11359       oappend (names64[modrm.reg + add]);
11360       break;
11361     case v_mode:
11362     case dq_mode:
11363     case dqb_mode:
11364     case dqd_mode:
11365     case dqw_mode:
11366       USED_REX (REX_W);
11367       if (rex & REX_W)
11368         oappend (names64[modrm.reg + add]);
11369       else if ((sizeflag & DFLAG) || bytemode != v_mode)
11370         oappend (names32[modrm.reg + add]);
11371       else
11372         oappend (names16[modrm.reg + add]);
11373       used_prefixes |= (prefixes & PREFIX_DATA);
11374       break;
11375     case m_mode:
11376       if (address_mode == mode_64bit)
11377         oappend (names64[modrm.reg + add]);
11378       else
11379         oappend (names32[modrm.reg + add]);
11380       break;
11381     default:
11382       oappend (INTERNAL_DISASSEMBLER_ERROR);
11383       break;
11384     }
11385 }
11386
11387 static bfd_vma
11388 get64 (void)
11389 {
11390   bfd_vma x;
11391 #ifdef BFD64
11392   unsigned int a;
11393   unsigned int b;
11394
11395   FETCH_DATA (the_info, codep + 8);
11396   a = *codep++ & 0xff;
11397   a |= (*codep++ & 0xff) << 8;
11398   a |= (*codep++ & 0xff) << 16;
11399   a |= (*codep++ & 0xff) << 24;
11400   b = *codep++ & 0xff;
11401   b |= (*codep++ & 0xff) << 8;
11402   b |= (*codep++ & 0xff) << 16;
11403   b |= (*codep++ & 0xff) << 24;
11404   x = a + ((bfd_vma) b << 32);
11405 #else
11406   abort ();
11407   x = 0;
11408 #endif
11409   return x;
11410 }
11411
11412 static bfd_signed_vma
11413 get32 (void)
11414 {
11415   bfd_signed_vma x = 0;
11416
11417   FETCH_DATA (the_info, codep + 4);
11418   x = *codep++ & (bfd_signed_vma) 0xff;
11419   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11420   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11421   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11422   return x;
11423 }
11424
11425 static bfd_signed_vma
11426 get32s (void)
11427 {
11428   bfd_signed_vma x = 0;
11429
11430   FETCH_DATA (the_info, codep + 4);
11431   x = *codep++ & (bfd_signed_vma) 0xff;
11432   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11433   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11434   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11435
11436   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11437
11438   return x;
11439 }
11440
11441 static int
11442 get16 (void)
11443 {
11444   int x = 0;
11445
11446   FETCH_DATA (the_info, codep + 2);
11447   x = *codep++ & 0xff;
11448   x |= (*codep++ & 0xff) << 8;
11449   return x;
11450 }
11451
11452 static void
11453 set_op (bfd_vma op, int riprel)
11454 {
11455   op_index[op_ad] = op_ad;
11456   if (address_mode == mode_64bit)
11457     {
11458       op_address[op_ad] = op;
11459       op_riprel[op_ad] = riprel;
11460     }
11461   else
11462     {
11463       /* Mask to get a 32-bit address.  */
11464       op_address[op_ad] = op & 0xffffffff;
11465       op_riprel[op_ad] = riprel & 0xffffffff;
11466     }
11467 }
11468
11469 static void
11470 OP_REG (int code, int sizeflag)
11471 {
11472   const char *s;
11473   int add;
11474   USED_REX (REX_B);
11475   if (rex & REX_B)
11476     add = 8;
11477   else
11478     add = 0;
11479
11480   switch (code)
11481     {
11482     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11483     case sp_reg: case bp_reg: case si_reg: case di_reg:
11484       s = names16[code - ax_reg + add];
11485       break;
11486     case es_reg: case ss_reg: case cs_reg:
11487     case ds_reg: case fs_reg: case gs_reg:
11488       s = names_seg[code - es_reg + add];
11489       break;
11490     case al_reg: case ah_reg: case cl_reg: case ch_reg:
11491     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11492       USED_REX (0);
11493       if (rex)
11494         s = names8rex[code - al_reg + add];
11495       else
11496         s = names8[code - al_reg];
11497       break;
11498     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
11499     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
11500       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11501         {
11502           s = names64[code - rAX_reg + add];
11503           break;
11504         }
11505       code += eAX_reg - rAX_reg;
11506       /* Fall through.  */
11507     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11508     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11509       USED_REX (REX_W);
11510       if (rex & REX_W)
11511         s = names64[code - eAX_reg + add];
11512       else if (sizeflag & DFLAG)
11513         s = names32[code - eAX_reg + add];
11514       else
11515         s = names16[code - eAX_reg + add];
11516       used_prefixes |= (prefixes & PREFIX_DATA);
11517       break;
11518     default:
11519       s = INTERNAL_DISASSEMBLER_ERROR;
11520       break;
11521     }
11522   oappend (s);
11523 }
11524
11525 static void
11526 OP_IMREG (int code, int sizeflag)
11527 {
11528   const char *s;
11529
11530   switch (code)
11531     {
11532     case indir_dx_reg:
11533       if (intel_syntax)
11534         s = "dx";
11535       else
11536         s = "(%dx)";
11537       break;
11538     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11539     case sp_reg: case bp_reg: case si_reg: case di_reg:
11540       s = names16[code - ax_reg];
11541       break;
11542     case es_reg: case ss_reg: case cs_reg:
11543     case ds_reg: case fs_reg: case gs_reg:
11544       s = names_seg[code - es_reg];
11545       break;
11546     case al_reg: case ah_reg: case cl_reg: case ch_reg:
11547     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11548       USED_REX (0);
11549       if (rex)
11550         s = names8rex[code - al_reg];
11551       else
11552         s = names8[code - al_reg];
11553       break;
11554     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11555     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11556       USED_REX (REX_W);
11557       if (rex & REX_W)
11558         s = names64[code - eAX_reg];
11559       else if (sizeflag & DFLAG)
11560         s = names32[code - eAX_reg];
11561       else
11562         s = names16[code - eAX_reg];
11563       used_prefixes |= (prefixes & PREFIX_DATA);
11564       break;
11565     case z_mode_ax_reg:
11566       if ((rex & REX_W) || (sizeflag & DFLAG))
11567         s = *names32;
11568       else
11569         s = *names16;
11570       if (!(rex & REX_W))
11571         used_prefixes |= (prefixes & PREFIX_DATA);
11572       break;
11573     default:
11574       s = INTERNAL_DISASSEMBLER_ERROR;
11575       break;
11576     }
11577   oappend (s);
11578 }
11579
11580 static void
11581 OP_I (int bytemode, int sizeflag)
11582 {
11583   bfd_signed_vma op;
11584   bfd_signed_vma mask = -1;
11585
11586   switch (bytemode)
11587     {
11588     case b_mode:
11589       FETCH_DATA (the_info, codep + 1);
11590       op = *codep++;
11591       mask = 0xff;
11592       break;
11593     case q_mode:
11594       if (address_mode == mode_64bit)
11595         {
11596           op = get32s ();
11597           break;
11598         }
11599       /* Fall through.  */
11600     case v_mode:
11601       USED_REX (REX_W);
11602       if (rex & REX_W)
11603         op = get32s ();
11604       else if (sizeflag & DFLAG)
11605         {
11606           op = get32 ();
11607           mask = 0xffffffff;
11608         }
11609       else
11610         {
11611           op = get16 ();
11612           mask = 0xfffff;
11613         }
11614       used_prefixes |= (prefixes & PREFIX_DATA);
11615       break;
11616     case w_mode:
11617       mask = 0xfffff;
11618       op = get16 ();
11619       break;
11620     case const_1_mode:
11621       if (intel_syntax)
11622         oappend ("1");
11623       return;
11624     default:
11625       oappend (INTERNAL_DISASSEMBLER_ERROR);
11626       return;
11627     }
11628
11629   op &= mask;
11630   scratchbuf[0] = '$';
11631   print_operand_value (scratchbuf + 1, 1, op);
11632   oappend (scratchbuf + intel_syntax);
11633   scratchbuf[0] = '\0';
11634 }
11635
11636 static void
11637 OP_I64 (int bytemode, int sizeflag)
11638 {
11639   bfd_signed_vma op;
11640   bfd_signed_vma mask = -1;
11641
11642   if (address_mode != mode_64bit)
11643     {
11644       OP_I (bytemode, sizeflag);
11645       return;
11646     }
11647
11648   switch (bytemode)
11649     {
11650     case b_mode:
11651       FETCH_DATA (the_info, codep + 1);
11652       op = *codep++;
11653       mask = 0xff;
11654       break;
11655     case v_mode:
11656       USED_REX (REX_W);
11657       if (rex & REX_W)
11658         op = get64 ();
11659       else if (sizeflag & DFLAG)
11660         {
11661           op = get32 ();
11662           mask = 0xffffffff;
11663         }
11664       else
11665         {
11666           op = get16 ();
11667           mask = 0xfffff;
11668         }
11669       used_prefixes |= (prefixes & PREFIX_DATA);
11670       break;
11671     case w_mode:
11672       mask = 0xfffff;
11673       op = get16 ();
11674       break;
11675     default:
11676       oappend (INTERNAL_DISASSEMBLER_ERROR);
11677       return;
11678     }
11679
11680   op &= mask;
11681   scratchbuf[0] = '$';
11682   print_operand_value (scratchbuf + 1, 1, op);
11683   oappend (scratchbuf + intel_syntax);
11684   scratchbuf[0] = '\0';
11685 }
11686
11687 static void
11688 OP_sI (int bytemode, int sizeflag)
11689 {
11690   bfd_signed_vma op;
11691   bfd_signed_vma mask = -1;
11692
11693   switch (bytemode)
11694     {
11695     case b_mode:
11696       FETCH_DATA (the_info, codep + 1);
11697       op = *codep++;
11698       if ((op & 0x80) != 0)
11699         op -= 0x100;
11700       mask = 0xffffffff;
11701       break;
11702     case v_mode:
11703       USED_REX (REX_W);
11704       if (rex & REX_W)
11705         op = get32s ();
11706       else if (sizeflag & DFLAG)
11707         {
11708           op = get32s ();
11709           mask = 0xffffffff;
11710         }
11711       else
11712         {
11713           mask = 0xffffffff;
11714           op = get16 ();
11715           if ((op & 0x8000) != 0)
11716             op -= 0x10000;
11717         }
11718       used_prefixes |= (prefixes & PREFIX_DATA);
11719       break;
11720     case w_mode:
11721       op = get16 ();
11722       mask = 0xffffffff;
11723       if ((op & 0x8000) != 0)
11724         op -= 0x10000;
11725       break;
11726     default:
11727       oappend (INTERNAL_DISASSEMBLER_ERROR);
11728       return;
11729     }
11730
11731   scratchbuf[0] = '$';
11732   print_operand_value (scratchbuf + 1, 1, op);
11733   oappend (scratchbuf + intel_syntax);
11734 }
11735
11736 static void
11737 OP_J (int bytemode, int sizeflag)
11738 {
11739   bfd_vma disp;
11740   bfd_vma mask = -1;
11741   bfd_vma segment = 0;
11742
11743   switch (bytemode)
11744     {
11745     case b_mode:
11746       FETCH_DATA (the_info, codep + 1);
11747       disp = *codep++;
11748       if ((disp & 0x80) != 0)
11749         disp -= 0x100;
11750       break;
11751     case v_mode:
11752       if ((sizeflag & DFLAG) || (rex & REX_W))
11753         disp = get32s ();
11754       else
11755         {
11756           disp = get16 ();
11757           if ((disp & 0x8000) != 0)
11758             disp -= 0x10000;
11759           /* In 16bit mode, address is wrapped around at 64k within
11760              the same segment.  Otherwise, a data16 prefix on a jump
11761              instruction means that the pc is masked to 16 bits after
11762              the displacement is added!  */
11763           mask = 0xffff;
11764           if ((prefixes & PREFIX_DATA) == 0)
11765             segment = ((start_pc + codep - start_codep)
11766                        & ~((bfd_vma) 0xffff));
11767         }
11768       used_prefixes |= (prefixes & PREFIX_DATA);
11769       break;
11770     default:
11771       oappend (INTERNAL_DISASSEMBLER_ERROR);
11772       return;
11773     }
11774   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
11775   set_op (disp, 0);
11776   print_operand_value (scratchbuf, 1, disp);
11777   oappend (scratchbuf);
11778 }
11779
11780 static void
11781 OP_SEG (int bytemode, int sizeflag)
11782 {
11783   if (bytemode == w_mode)
11784     oappend (names_seg[modrm.reg]);
11785   else
11786     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
11787 }
11788
11789 static void
11790 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
11791 {
11792   int seg, offset;
11793
11794   if (sizeflag & DFLAG)
11795     {
11796       offset = get32 ();
11797       seg = get16 ();
11798     }
11799   else
11800     {
11801       offset = get16 ();
11802       seg = get16 ();
11803     }
11804   used_prefixes |= (prefixes & PREFIX_DATA);
11805   if (intel_syntax)
11806     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
11807   else
11808     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
11809   oappend (scratchbuf);
11810 }
11811
11812 static void
11813 OP_OFF (int bytemode, int sizeflag)
11814 {
11815   bfd_vma off;
11816
11817   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11818     intel_operand_size (bytemode, sizeflag);
11819   append_seg ();
11820
11821   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11822     off = get32 ();
11823   else
11824     off = get16 ();
11825
11826   if (intel_syntax)
11827     {
11828       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11829                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
11830         {
11831           oappend (names_seg[ds_reg - es_reg]);
11832           oappend (":");
11833         }
11834     }
11835   print_operand_value (scratchbuf, 1, off);
11836   oappend (scratchbuf);
11837 }
11838
11839 static void
11840 OP_OFF64 (int bytemode, int sizeflag)
11841 {
11842   bfd_vma off;
11843
11844   if (address_mode != mode_64bit
11845       || (prefixes & PREFIX_ADDR))
11846     {
11847       OP_OFF (bytemode, sizeflag);
11848       return;
11849     }
11850
11851   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11852     intel_operand_size (bytemode, sizeflag);
11853   append_seg ();
11854
11855   off = get64 ();
11856
11857   if (intel_syntax)
11858     {
11859       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11860                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
11861         {
11862           oappend (names_seg[ds_reg - es_reg]);
11863           oappend (":");
11864         }
11865     }
11866   print_operand_value (scratchbuf, 1, off);
11867   oappend (scratchbuf);
11868 }
11869
11870 static void
11871 ptr_reg (int code, int sizeflag)
11872 {
11873   const char *s;
11874
11875   *obufp++ = open_char;
11876   used_prefixes |= (prefixes & PREFIX_ADDR);
11877   if (address_mode == mode_64bit)
11878     {
11879       if (!(sizeflag & AFLAG))
11880         s = names32[code - eAX_reg];
11881       else
11882         s = names64[code - eAX_reg];
11883     }
11884   else if (sizeflag & AFLAG)
11885     s = names32[code - eAX_reg];
11886   else
11887     s = names16[code - eAX_reg];
11888   oappend (s);
11889   *obufp++ = close_char;
11890   *obufp = 0;
11891 }
11892
11893 static void
11894 OP_ESreg (int code, int sizeflag)
11895 {
11896   if (intel_syntax)
11897     {
11898       switch (codep[-1])
11899         {
11900         case 0x6d:      /* insw/insl */
11901           intel_operand_size (z_mode, sizeflag);
11902           break;
11903         case 0xa5:      /* movsw/movsl/movsq */
11904         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
11905         case 0xab:      /* stosw/stosl */
11906         case 0xaf:      /* scasw/scasl */
11907           intel_operand_size (v_mode, sizeflag);
11908           break;
11909         default:
11910           intel_operand_size (b_mode, sizeflag);
11911         }
11912     }
11913   oappend ("%es:" + intel_syntax);
11914   ptr_reg (code, sizeflag);
11915 }
11916
11917 static void
11918 OP_DSreg (int code, int sizeflag)
11919 {
11920   if (intel_syntax)
11921     {
11922       switch (codep[-1])
11923         {
11924         case 0x6f:      /* outsw/outsl */
11925           intel_operand_size (z_mode, sizeflag);
11926           break;
11927         case 0xa5:      /* movsw/movsl/movsq */
11928         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
11929         case 0xad:      /* lodsw/lodsl/lodsq */
11930           intel_operand_size (v_mode, sizeflag);
11931           break;
11932         default:
11933           intel_operand_size (b_mode, sizeflag);
11934         }
11935     }
11936   if ((prefixes
11937        & (PREFIX_CS
11938           | PREFIX_DS
11939           | PREFIX_SS
11940           | PREFIX_ES
11941           | PREFIX_FS
11942           | PREFIX_GS)) == 0)
11943     prefixes |= PREFIX_DS;
11944   append_seg ();
11945   ptr_reg (code, sizeflag);
11946 }
11947
11948 static void
11949 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11950 {
11951   int add;
11952   if (rex & REX_R)
11953     {
11954       USED_REX (REX_R);
11955       add = 8;
11956     }
11957   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
11958     {
11959       lock_prefix = NULL;
11960       used_prefixes |= PREFIX_LOCK;
11961       add = 8;
11962     }
11963   else
11964     add = 0;
11965   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
11966   oappend (scratchbuf + intel_syntax);
11967 }
11968
11969 static void
11970 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11971 {
11972   int add;
11973   USED_REX (REX_R);
11974   if (rex & REX_R)
11975     add = 8;
11976   else
11977     add = 0;
11978   if (intel_syntax)
11979     sprintf (scratchbuf, "db%d", modrm.reg + add);
11980   else
11981     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
11982   oappend (scratchbuf);
11983 }
11984
11985 static void
11986 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11987 {
11988   sprintf (scratchbuf, "%%tr%d", modrm.reg);
11989   oappend (scratchbuf + intel_syntax);
11990 }
11991
11992 static void
11993 OP_R (int bytemode, int sizeflag)
11994 {
11995   if (modrm.mod == 3)
11996     OP_E (bytemode, sizeflag);
11997   else
11998     BadOp ();
11999 }
12000
12001 static void
12002 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12003 {
12004   used_prefixes |= (prefixes & PREFIX_DATA);
12005   if (prefixes & PREFIX_DATA)
12006     {
12007       int add;
12008       USED_REX (REX_R);
12009       if (rex & REX_R)
12010         add = 8;
12011       else
12012         add = 0;
12013       sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12014     }
12015   else
12016     sprintf (scratchbuf, "%%mm%d", modrm.reg);
12017   oappend (scratchbuf + intel_syntax);
12018 }
12019
12020 static void
12021 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12022 {
12023   int add;
12024   USED_REX (REX_R);
12025   if (rex & REX_R)
12026     add = 8;
12027   else
12028     add = 0;
12029   if (need_vex && bytemode != xmm_mode)
12030     {
12031       switch (vex.length)
12032         {
12033         case 128:
12034           sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12035           break;
12036         case 256:
12037           sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12038           break;
12039         default:
12040           abort ();
12041         }
12042     }
12043   else
12044     sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12045   oappend (scratchbuf + intel_syntax);
12046 }
12047
12048 static void
12049 OP_EM (int bytemode, int sizeflag)
12050 {
12051   if (modrm.mod != 3)
12052     {
12053       if (intel_syntax
12054           && (bytemode == v_mode || bytemode == v_swap_mode))
12055         {
12056           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12057           used_prefixes |= (prefixes & PREFIX_DATA);
12058         }
12059       OP_E (bytemode, sizeflag);
12060       return;
12061     }
12062
12063   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12064     swap_operand ();
12065
12066   /* Skip mod/rm byte.  */
12067   MODRM_CHECK;
12068   codep++;
12069   used_prefixes |= (prefixes & PREFIX_DATA);
12070   if (prefixes & PREFIX_DATA)
12071     {
12072       int add;
12073
12074       USED_REX (REX_B);
12075       if (rex & REX_B)
12076         add = 8;
12077       else
12078         add = 0;
12079       sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12080     }
12081   else
12082     sprintf (scratchbuf, "%%mm%d", modrm.rm);
12083   oappend (scratchbuf + intel_syntax);
12084 }
12085
12086 /* cvt* are the only instructions in sse2 which have
12087    both SSE and MMX operands and also have 0x66 prefix
12088    in their opcode. 0x66 was originally used to differentiate
12089    between SSE and MMX instruction(operands). So we have to handle the
12090    cvt* separately using OP_EMC and OP_MXC */
12091 static void
12092 OP_EMC (int bytemode, int sizeflag)
12093 {
12094   if (modrm.mod != 3)
12095     {
12096       if (intel_syntax && bytemode == v_mode)
12097         {
12098           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12099           used_prefixes |= (prefixes & PREFIX_DATA);
12100         }
12101       OP_E (bytemode, sizeflag);
12102       return;
12103     }
12104
12105   /* Skip mod/rm byte.  */
12106   MODRM_CHECK;
12107   codep++;
12108   used_prefixes |= (prefixes & PREFIX_DATA);
12109   sprintf (scratchbuf, "%%mm%d", modrm.rm);
12110   oappend (scratchbuf + intel_syntax);
12111 }
12112
12113 static void
12114 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12115 {
12116   used_prefixes |= (prefixes & PREFIX_DATA);
12117   sprintf (scratchbuf, "%%mm%d", modrm.reg);
12118   oappend (scratchbuf + intel_syntax);
12119 }
12120
12121 static void
12122 OP_EX (int bytemode, int sizeflag)
12123 {
12124   int add;
12125
12126   /* Skip mod/rm byte.  */
12127   MODRM_CHECK;
12128   codep++;
12129
12130   if (modrm.mod != 3)
12131     {
12132       OP_E_memory (bytemode, sizeflag);
12133       return;
12134     }
12135
12136   USED_REX (REX_B);
12137   if (rex & REX_B)
12138     add = 8;
12139   else
12140     add = 0;
12141
12142   if ((sizeflag & SUFFIX_ALWAYS)
12143       && (bytemode == x_swap_mode
12144           || bytemode == d_swap_mode
12145           || bytemode == q_swap_mode))
12146     swap_operand ();
12147
12148   if (need_vex
12149       && bytemode != xmm_mode
12150       && bytemode != xmmq_mode)
12151     {
12152       switch (vex.length)
12153         {
12154         case 128:
12155           sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12156           break;
12157         case 256:
12158           sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12159           break;
12160         default:
12161           abort ();
12162         }
12163     }
12164   else
12165     sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12166   oappend (scratchbuf + intel_syntax);
12167 }
12168
12169 static void
12170 OP_MS (int bytemode, int sizeflag)
12171 {
12172   if (modrm.mod == 3)
12173     OP_EM (bytemode, sizeflag);
12174   else
12175     BadOp ();
12176 }
12177
12178 static void
12179 OP_XS (int bytemode, int sizeflag)
12180 {
12181   if (modrm.mod == 3)
12182     OP_EX (bytemode, sizeflag);
12183   else
12184     BadOp ();
12185 }
12186
12187 static void
12188 OP_M (int bytemode, int sizeflag)
12189 {
12190   if (modrm.mod == 3)
12191     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12192     BadOp ();
12193   else
12194     OP_E (bytemode, sizeflag);
12195 }
12196
12197 static void
12198 OP_0f07 (int bytemode, int sizeflag)
12199 {
12200   if (modrm.mod != 3 || modrm.rm != 0)
12201     BadOp ();
12202   else
12203     OP_E (bytemode, sizeflag);
12204 }
12205
12206 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12207    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12208
12209 static void
12210 NOP_Fixup1 (int bytemode, int sizeflag)
12211 {
12212   if ((prefixes & PREFIX_DATA) != 0
12213       || (rex != 0
12214           && rex != 0x48
12215           && address_mode == mode_64bit))
12216     OP_REG (bytemode, sizeflag);
12217   else
12218     strcpy (obuf, "nop");
12219 }
12220
12221 static void
12222 NOP_Fixup2 (int bytemode, int sizeflag)
12223 {
12224   if ((prefixes & PREFIX_DATA) != 0
12225       || (rex != 0
12226           && rex != 0x48
12227           && address_mode == mode_64bit))
12228     OP_IMREG (bytemode, sizeflag);
12229 }
12230
12231 static const char *const Suffix3DNow[] = {
12232 /* 00 */        NULL,           NULL,           NULL,           NULL,
12233 /* 04 */        NULL,           NULL,           NULL,           NULL,
12234 /* 08 */        NULL,           NULL,           NULL,           NULL,
12235 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12236 /* 10 */        NULL,           NULL,           NULL,           NULL,
12237 /* 14 */        NULL,           NULL,           NULL,           NULL,
12238 /* 18 */        NULL,           NULL,           NULL,           NULL,
12239 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12240 /* 20 */        NULL,           NULL,           NULL,           NULL,
12241 /* 24 */        NULL,           NULL,           NULL,           NULL,
12242 /* 28 */        NULL,           NULL,           NULL,           NULL,
12243 /* 2C */        NULL,           NULL,           NULL,           NULL,
12244 /* 30 */        NULL,           NULL,           NULL,           NULL,
12245 /* 34 */        NULL,           NULL,           NULL,           NULL,
12246 /* 38 */        NULL,           NULL,           NULL,           NULL,
12247 /* 3C */        NULL,           NULL,           NULL,           NULL,
12248 /* 40 */        NULL,           NULL,           NULL,           NULL,
12249 /* 44 */        NULL,           NULL,           NULL,           NULL,
12250 /* 48 */        NULL,           NULL,           NULL,           NULL,
12251 /* 4C */        NULL,           NULL,           NULL,           NULL,
12252 /* 50 */        NULL,           NULL,           NULL,           NULL,
12253 /* 54 */        NULL,           NULL,           NULL,           NULL,
12254 /* 58 */        NULL,           NULL,           NULL,           NULL,
12255 /* 5C */        NULL,           NULL,           NULL,           NULL,
12256 /* 60 */        NULL,           NULL,           NULL,           NULL,
12257 /* 64 */        NULL,           NULL,           NULL,           NULL,
12258 /* 68 */        NULL,           NULL,           NULL,           NULL,
12259 /* 6C */        NULL,           NULL,           NULL,           NULL,
12260 /* 70 */        NULL,           NULL,           NULL,           NULL,
12261 /* 74 */        NULL,           NULL,           NULL,           NULL,
12262 /* 78 */        NULL,           NULL,           NULL,           NULL,
12263 /* 7C */        NULL,           NULL,           NULL,           NULL,
12264 /* 80 */        NULL,           NULL,           NULL,           NULL,
12265 /* 84 */        NULL,           NULL,           NULL,           NULL,
12266 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12267 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12268 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12269 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12270 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12271 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12272 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12273 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12274 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12275 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12276 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12277 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12278 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12279 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12280 /* C0 */        NULL,           NULL,           NULL,           NULL,
12281 /* C4 */        NULL,           NULL,           NULL,           NULL,
12282 /* C8 */        NULL,           NULL,           NULL,           NULL,
12283 /* CC */        NULL,           NULL,           NULL,           NULL,
12284 /* D0 */        NULL,           NULL,           NULL,           NULL,
12285 /* D4 */        NULL,           NULL,           NULL,           NULL,
12286 /* D8 */        NULL,           NULL,           NULL,           NULL,
12287 /* DC */        NULL,           NULL,           NULL,           NULL,
12288 /* E0 */        NULL,           NULL,           NULL,           NULL,
12289 /* E4 */        NULL,           NULL,           NULL,           NULL,
12290 /* E8 */        NULL,           NULL,           NULL,           NULL,
12291 /* EC */        NULL,           NULL,           NULL,           NULL,
12292 /* F0 */        NULL,           NULL,           NULL,           NULL,
12293 /* F4 */        NULL,           NULL,           NULL,           NULL,
12294 /* F8 */        NULL,           NULL,           NULL,           NULL,
12295 /* FC */        NULL,           NULL,           NULL,           NULL,
12296 };
12297
12298 static void
12299 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12300 {
12301   const char *mnemonic;
12302
12303   FETCH_DATA (the_info, codep + 1);
12304   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12305      place where an 8-bit immediate would normally go.  ie. the last
12306      byte of the instruction.  */
12307   obufp = mnemonicendp;
12308   mnemonic = Suffix3DNow[*codep++ & 0xff];
12309   if (mnemonic)
12310     oappend (mnemonic);
12311   else
12312     {
12313       /* Since a variable sized modrm/sib chunk is between the start
12314          of the opcode (0x0f0f) and the opcode suffix, we need to do
12315          all the modrm processing first, and don't know until now that
12316          we have a bad opcode.  This necessitates some cleaning up.  */
12317       op_out[0][0] = '\0';
12318       op_out[1][0] = '\0';
12319       BadOp ();
12320     }
12321   mnemonicendp = obufp;
12322 }
12323
12324 static struct op simd_cmp_op[] =
12325 {
12326   { STRING_COMMA_LEN ("eq") },
12327   { STRING_COMMA_LEN ("lt") },
12328   { STRING_COMMA_LEN ("le") },
12329   { STRING_COMMA_LEN ("unord") },
12330   { STRING_COMMA_LEN ("neq") },
12331   { STRING_COMMA_LEN ("nlt") },
12332   { STRING_COMMA_LEN ("nle") },
12333   { STRING_COMMA_LEN ("ord") }
12334 };
12335
12336 static void
12337 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12338 {
12339   unsigned int cmp_type;
12340
12341   FETCH_DATA (the_info, codep + 1);
12342   cmp_type = *codep++ & 0xff;
12343   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12344     {
12345       char suffix [3];
12346       char *p = mnemonicendp - 2;
12347       suffix[0] = p[0];
12348       suffix[1] = p[1];
12349       suffix[2] = '\0';
12350       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12351       mnemonicendp += simd_cmp_op[cmp_type].len;
12352     }
12353   else
12354     {
12355       /* We have a reserved extension byte.  Output it directly.  */
12356       scratchbuf[0] = '$';
12357       print_operand_value (scratchbuf + 1, 1, cmp_type);
12358       oappend (scratchbuf + intel_syntax);
12359       scratchbuf[0] = '\0';
12360     }
12361 }
12362
12363 static void
12364 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12365           int sizeflag ATTRIBUTE_UNUSED)
12366 {
12367   /* mwait %eax,%ecx  */
12368   if (!intel_syntax)
12369     {
12370       const char **names = (address_mode == mode_64bit
12371                             ? names64 : names32);
12372       strcpy (op_out[0], names[0]);
12373       strcpy (op_out[1], names[1]);
12374       two_source_ops = 1;
12375     }
12376   /* Skip mod/rm byte.  */
12377   MODRM_CHECK;
12378   codep++;
12379 }
12380
12381 static void
12382 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12383             int sizeflag ATTRIBUTE_UNUSED)
12384 {
12385   /* monitor %eax,%ecx,%edx"  */
12386   if (!intel_syntax)
12387     {
12388       const char **op1_names;
12389       const char **names = (address_mode == mode_64bit
12390                             ? names64 : names32);
12391
12392       if (!(prefixes & PREFIX_ADDR))
12393         op1_names = (address_mode == mode_16bit
12394                      ? names16 : names);
12395       else
12396         {
12397           /* Remove "addr16/addr32".  */
12398           addr_prefix = NULL;
12399           op1_names = (address_mode != mode_32bit
12400                        ? names32 : names16);
12401           used_prefixes |= PREFIX_ADDR;
12402         }
12403       strcpy (op_out[0], op1_names[0]);
12404       strcpy (op_out[1], names[1]);
12405       strcpy (op_out[2], names[2]);
12406       two_source_ops = 1;
12407     }
12408   /* Skip mod/rm byte.  */
12409   MODRM_CHECK;
12410   codep++;
12411 }
12412
12413 static void
12414 BadOp (void)
12415 {
12416   /* Throw away prefixes and 1st. opcode byte.  */
12417   codep = insn_codep + 1;
12418   oappend ("(bad)");
12419 }
12420
12421 static void
12422 REP_Fixup (int bytemode, int sizeflag)
12423 {
12424   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12425      lods and stos.  */
12426   if (prefixes & PREFIX_REPZ)
12427     repz_prefix = "rep ";
12428
12429   switch (bytemode)
12430     {
12431     case al_reg:
12432     case eAX_reg:
12433     case indir_dx_reg:
12434       OP_IMREG (bytemode, sizeflag);
12435       break;
12436     case eDI_reg:
12437       OP_ESreg (bytemode, sizeflag);
12438       break;
12439     case eSI_reg:
12440       OP_DSreg (bytemode, sizeflag);
12441       break;
12442     default:
12443       abort ();
12444       break;
12445     }
12446 }
12447
12448 static void
12449 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12450 {
12451   USED_REX (REX_W);
12452   if (rex & REX_W)
12453     {
12454       /* Change cmpxchg8b to cmpxchg16b.  */
12455       char *p = mnemonicendp - 2;
12456       mnemonicendp = stpcpy (p, "16b");
12457       bytemode = o_mode;
12458     }
12459   OP_M (bytemode, sizeflag);
12460 }
12461
12462 static void
12463 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
12464 {
12465   if (need_vex)
12466     {
12467       switch (vex.length)
12468         {
12469         case 128:
12470           sprintf (scratchbuf, "%%xmm%d", reg);
12471           break;
12472         case 256:
12473           sprintf (scratchbuf, "%%ymm%d", reg);
12474           break;
12475         default:
12476           abort ();
12477         }
12478     }
12479   else
12480     sprintf (scratchbuf, "%%xmm%d", reg);
12481   oappend (scratchbuf + intel_syntax);
12482 }
12483
12484 static void
12485 CRC32_Fixup (int bytemode, int sizeflag)
12486 {
12487   /* Add proper suffix to "crc32".  */
12488   char *p = mnemonicendp;
12489
12490   switch (bytemode)
12491     {
12492     case b_mode:
12493       if (intel_syntax)
12494         goto skip;
12495
12496       *p++ = 'b';
12497       break;
12498     case v_mode:
12499       if (intel_syntax)
12500         goto skip;
12501
12502       USED_REX (REX_W);
12503       if (rex & REX_W)
12504         *p++ = 'q';
12505       else if (sizeflag & DFLAG)
12506         *p++ = 'l';
12507       else
12508         *p++ = 'w';
12509       used_prefixes |= (prefixes & PREFIX_DATA);
12510       break;
12511     default:
12512       oappend (INTERNAL_DISASSEMBLER_ERROR);
12513       break;
12514     }
12515   mnemonicendp = p;
12516   *p = '\0';
12517
12518 skip:
12519   if (modrm.mod == 3)
12520     {
12521       int add;
12522
12523       /* Skip mod/rm byte.  */
12524       MODRM_CHECK;
12525       codep++;
12526
12527       USED_REX (REX_B);
12528       add = (rex & REX_B) ? 8 : 0;
12529       if (bytemode == b_mode)
12530         {
12531           USED_REX (0);
12532           if (rex)
12533             oappend (names8rex[modrm.rm + add]);
12534           else
12535             oappend (names8[modrm.rm + add]);
12536         }
12537       else
12538         {
12539           USED_REX (REX_W);
12540           if (rex & REX_W)
12541             oappend (names64[modrm.rm + add]);
12542           else if ((prefixes & PREFIX_DATA))
12543             oappend (names16[modrm.rm + add]);
12544           else
12545             oappend (names32[modrm.rm + add]);
12546         }
12547     }
12548   else
12549     OP_E (bytemode, sizeflag);
12550 }
12551
12552 /* Display the destination register operand for instructions with
12553    VEX. */
12554
12555 static void
12556 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12557 {
12558   if (!need_vex)
12559     abort ();
12560
12561   if (!need_vex_reg)
12562     return;
12563
12564   switch (vex.length)
12565     {
12566     case 128:
12567       switch (bytemode)
12568         {
12569         case vex_mode:
12570         case vex128_mode:
12571           break;
12572         default:
12573           abort ();
12574           return;
12575         }
12576
12577       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
12578       break;
12579     case 256:
12580       switch (bytemode)
12581         {
12582         case vex_mode:
12583         case vex256_mode:
12584           break;
12585         default:
12586           abort ();
12587           return;
12588         }
12589
12590       sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
12591       break;
12592     default:
12593       abort ();
12594       break;
12595     }
12596   oappend (scratchbuf + intel_syntax);
12597 }
12598
12599 /* Get the VEX immediate byte without moving codep.  */
12600
12601 static unsigned char
12602 get_vex_imm8 (int sizeflag)
12603 {
12604   int bytes_before_imm = 0;
12605
12606   /* Skip mod/rm byte.   */
12607   MODRM_CHECK;
12608   codep++;
12609
12610   if (modrm.mod != 3)
12611     {
12612       /* There are SIB/displacement bytes.  */
12613       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12614         {
12615           /* 32/64 bit address mode */
12616           int base = modrm.rm;
12617
12618           /* Check SIB byte.  */
12619           if (base == 4)
12620             {
12621               FETCH_DATA (the_info, codep + 1);
12622               base = *codep & 7;
12623               bytes_before_imm++;
12624             }
12625
12626           switch (modrm.mod)
12627             {
12628             case 0:
12629               /* When modrm.rm == 5 or modrm.rm == 4 and base in
12630                  SIB == 5, there is a 4 byte displacement.  */
12631               if (base != 5)
12632                 /* No displacement. */
12633                 break;
12634             case 2:
12635               /* 4 byte displacement.  */
12636               bytes_before_imm += 4;
12637               break;
12638             case 1:
12639               /* 1 byte displacement.  */
12640               bytes_before_imm++;
12641               break;
12642             }
12643         }
12644       else
12645         { /* 16 bit address mode */
12646           switch (modrm.mod)
12647             {
12648             case 0:
12649               /* When modrm.rm == 6, there is a 2 byte displacement.  */
12650               if (modrm.rm != 6)
12651                 /* No displacement. */
12652                 break;
12653             case 2:
12654               /* 2 byte displacement.  */
12655               bytes_before_imm += 2;
12656               break;
12657             case 1:
12658               /* 1 byte displacement.  */
12659               bytes_before_imm++;
12660               break;
12661             }
12662         }
12663     }
12664
12665   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
12666   return codep [bytes_before_imm];
12667 }
12668
12669 static void
12670 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
12671 {
12672   if (reg == -1 && modrm.mod != 3)
12673     {
12674       OP_E_memory (bytemode, sizeflag);
12675       return;
12676     }
12677   else
12678     {
12679       if (reg == -1)
12680         {
12681           reg = modrm.rm;
12682           USED_REX (REX_B);
12683           if (rex & REX_B)
12684             reg += 8;
12685         }
12686       else if (reg > 7 && address_mode != mode_64bit)
12687         BadOp ();
12688     }
12689
12690   switch (vex.length)
12691     {
12692     case 128:
12693       sprintf (scratchbuf, "%%xmm%d", reg);
12694       break;
12695     case 256:
12696       sprintf (scratchbuf, "%%ymm%d", reg);
12697       break;
12698     default:
12699       abort ();
12700     }
12701   oappend (scratchbuf + intel_syntax);
12702 }
12703
12704 static void
12705 OP_EX_VexW (int bytemode, int sizeflag)
12706 {
12707   int reg = -1;
12708
12709   if (!vex_w_done)
12710     {
12711       vex_w_done = 1;
12712       if (vex.w)
12713         reg = get_vex_imm8 (sizeflag) >> 4;
12714     }
12715   else
12716     {
12717       if (!vex.w)
12718         reg = get_vex_imm8 (sizeflag) >> 4;
12719     }
12720
12721   OP_EX_VexReg (bytemode, sizeflag, reg);
12722 }
12723
12724 static void
12725 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
12726              int sizeflag ATTRIBUTE_UNUSED)
12727 {
12728   /* Skip the immediate byte and check for invalid bits.  */
12729   FETCH_DATA (the_info, codep + 1);
12730   if (*codep++ & 0xf)
12731     BadOp ();
12732 }
12733
12734 static void
12735 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12736 {
12737   int reg;
12738   FETCH_DATA (the_info, codep + 1);
12739   reg = *codep++;
12740
12741   if (bytemode != x_mode)
12742     abort ();
12743
12744   if (reg & 0xf)
12745       BadOp ();
12746
12747   reg >>= 4;
12748   if (reg > 7 && address_mode != mode_64bit)
12749     BadOp ();
12750
12751   switch (vex.length)
12752     {
12753     case 128:
12754       sprintf (scratchbuf, "%%xmm%d", reg);
12755       break;
12756     case 256:
12757       sprintf (scratchbuf, "%%ymm%d", reg);
12758       break;
12759     default:
12760       abort ();
12761     }
12762   oappend (scratchbuf + intel_syntax);
12763 }
12764
12765 static void
12766 OP_XMM_VexW (int bytemode, int sizeflag)
12767 {
12768   /* Turn off the REX.W bit since it is used for swapping operands
12769      now.  */
12770   rex &= ~REX_W;
12771   OP_XMM (bytemode, sizeflag);
12772 }
12773
12774 static void
12775 OP_EX_Vex (int bytemode, int sizeflag)
12776 {
12777   if (modrm.mod != 3)
12778     {
12779       if (vex.register_specifier != 0)
12780         BadOp ();
12781       need_vex_reg = 0;
12782     }
12783   OP_EX (bytemode, sizeflag);
12784 }
12785
12786 static void
12787 OP_XMM_Vex (int bytemode, int sizeflag)
12788 {
12789   if (modrm.mod != 3)
12790     {
12791       if (vex.register_specifier != 0)
12792         BadOp ();
12793       need_vex_reg = 0;
12794     }
12795   OP_XMM (bytemode, sizeflag);
12796 }
12797
12798 static void
12799 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12800 {
12801   switch (vex.length)
12802     {
12803     case 128:
12804       mnemonicendp = stpcpy (obuf, "vzeroupper");
12805       break;
12806     case 256:
12807       mnemonicendp = stpcpy (obuf, "vzeroall");
12808       break;
12809     default:
12810       abort ();
12811     }
12812 }
12813
12814 static struct op vex_cmp_op[] =
12815 {
12816   { STRING_COMMA_LEN ("eq") },
12817   { STRING_COMMA_LEN ("lt") },
12818   { STRING_COMMA_LEN ("le") },
12819   { STRING_COMMA_LEN ("unord") },
12820   { STRING_COMMA_LEN ("neq") },
12821   { STRING_COMMA_LEN ("nlt") },
12822   { STRING_COMMA_LEN ("nle") },
12823   { STRING_COMMA_LEN ("ord") },
12824   { STRING_COMMA_LEN ("eq_uq") },
12825   { STRING_COMMA_LEN ("nge") },
12826   { STRING_COMMA_LEN ("ngt") },
12827   { STRING_COMMA_LEN ("false") },
12828   { STRING_COMMA_LEN ("neq_oq") },
12829   { STRING_COMMA_LEN ("ge") },
12830   { STRING_COMMA_LEN ("gt") },
12831   { STRING_COMMA_LEN ("true") },
12832   { STRING_COMMA_LEN ("eq_os") },
12833   { STRING_COMMA_LEN ("lt_oq") },
12834   { STRING_COMMA_LEN ("le_oq") },
12835   { STRING_COMMA_LEN ("unord_s") },
12836   { STRING_COMMA_LEN ("neq_us") },
12837   { STRING_COMMA_LEN ("nlt_uq") },
12838   { STRING_COMMA_LEN ("nle_uq") },
12839   { STRING_COMMA_LEN ("ord_s") },
12840   { STRING_COMMA_LEN ("eq_us") },
12841   { STRING_COMMA_LEN ("nge_uq") },
12842   { STRING_COMMA_LEN ("ngt_uq") },
12843   { STRING_COMMA_LEN ("false_os") },
12844   { STRING_COMMA_LEN ("neq_os") },
12845   { STRING_COMMA_LEN ("ge_oq") },
12846   { STRING_COMMA_LEN ("gt_oq") },
12847   { STRING_COMMA_LEN ("true_us") },
12848 };
12849
12850 static void
12851 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12852 {
12853   unsigned int cmp_type;
12854
12855   FETCH_DATA (the_info, codep + 1);
12856   cmp_type = *codep++ & 0xff;
12857   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
12858     {
12859       char suffix [3];
12860       char *p = mnemonicendp - 2;
12861       suffix[0] = p[0];
12862       suffix[1] = p[1];
12863       suffix[2] = '\0';
12864       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
12865       mnemonicendp += vex_cmp_op[cmp_type].len;
12866     }
12867   else
12868     {
12869       /* We have a reserved extension byte.  Output it directly.  */
12870       scratchbuf[0] = '$';
12871       print_operand_value (scratchbuf + 1, 1, cmp_type);
12872       oappend (scratchbuf + intel_syntax);
12873       scratchbuf[0] = '\0';
12874     }
12875 }
12876
12877 static const struct op pclmul_op[] =
12878 {
12879   { STRING_COMMA_LEN ("lql") },
12880   { STRING_COMMA_LEN ("hql") },
12881   { STRING_COMMA_LEN ("lqh") },
12882   { STRING_COMMA_LEN ("hqh") }
12883 };
12884
12885 static void
12886 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
12887               int sizeflag ATTRIBUTE_UNUSED)
12888 {
12889   unsigned int pclmul_type;
12890
12891   FETCH_DATA (the_info, codep + 1);
12892   pclmul_type = *codep++ & 0xff;
12893   switch (pclmul_type)
12894     {
12895     case 0x10:
12896       pclmul_type = 2;
12897       break;
12898     case 0x11:
12899       pclmul_type = 3;
12900       break;
12901     default:
12902       break;
12903     }
12904   if (pclmul_type < ARRAY_SIZE (pclmul_op))
12905     {
12906       char suffix [4];
12907       char *p = mnemonicendp - 3;
12908       suffix[0] = p[0];
12909       suffix[1] = p[1];
12910       suffix[2] = p[2];
12911       suffix[3] = '\0';
12912       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
12913       mnemonicendp += pclmul_op[pclmul_type].len;
12914     }
12915   else
12916     {
12917       /* We have a reserved extension byte.  Output it directly.  */
12918       scratchbuf[0] = '$';
12919       print_operand_value (scratchbuf + 1, 1, pclmul_type);
12920       oappend (scratchbuf + intel_syntax);
12921       scratchbuf[0] = '\0';
12922     }
12923 }
12924
12925 static void
12926 MOVBE_Fixup (int bytemode, int sizeflag)
12927 {
12928   /* Add proper suffix to "movbe".  */
12929   char *p = mnemonicendp;
12930
12931   switch (bytemode)
12932     {
12933     case v_mode:
12934       if (intel_syntax)
12935         goto skip;
12936
12937       USED_REX (REX_W);
12938       if (sizeflag & SUFFIX_ALWAYS)
12939         {
12940           if (rex & REX_W)
12941             *p++ = 'q';
12942           else if (sizeflag & DFLAG)
12943             *p++ = 'l';
12944           else
12945             *p++ = 'w';
12946         }
12947       used_prefixes |= (prefixes & PREFIX_DATA);
12948       break;
12949     default:
12950       oappend (INTERNAL_DISASSEMBLER_ERROR);
12951       break;
12952     }
12953   mnemonicendp = p;
12954   *p = '\0';
12955
12956 skip:
12957   OP_M (bytemode, sizeflag);
12958 }