1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2016 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void OP_LWPCB_E (int, int);
121 static void OP_LWP_E (int, int);
122 static void OP_Vex_2src_1 (int, int);
123 static void OP_Vex_2src_2 (int, int);
125 static void MOVBE_Fixup (int, int);
127 static void OP_Mask (int, int);
130 /* Points to first byte not fetched. */
131 bfd_byte
*max_fetched
;
132 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
135 OPCODES_SIGJMP_BUF bailout
;
145 enum address_mode address_mode
;
147 /* Flags for the prefixes for the current instruction. See below. */
150 /* REX prefix the current instruction. See below. */
152 /* Bits of REX we've already used. */
154 /* REX bits in original REX prefix ignored. */
155 static int rex_ignored
;
156 /* Mark parts used in the REX prefix. When we are testing for
157 empty prefix (for 8bit register REX extension), just mask it
158 out. Otherwise test for REX bit is excuse for existence of REX
159 only in case value is nonzero. */
160 #define USED_REX(value) \
165 rex_used |= (value) | REX_OPCODE; \
168 rex_used |= REX_OPCODE; \
171 /* Flags for prefixes which we somehow handled when printing the
172 current instruction. */
173 static int used_prefixes
;
175 /* Flags stored in PREFIXES. */
176 #define PREFIX_REPZ 1
177 #define PREFIX_REPNZ 2
178 #define PREFIX_LOCK 4
180 #define PREFIX_SS 0x10
181 #define PREFIX_DS 0x20
182 #define PREFIX_ES 0x40
183 #define PREFIX_FS 0x80
184 #define PREFIX_GS 0x100
185 #define PREFIX_DATA 0x200
186 #define PREFIX_ADDR 0x400
187 #define PREFIX_FWAIT 0x800
189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
190 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
192 #define FETCH_DATA(info, addr) \
193 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
194 ? 1 : fetch_data ((info), (addr)))
197 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
200 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
201 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
203 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
204 status
= (*info
->read_memory_func
) (start
,
206 addr
- priv
->max_fetched
,
212 /* If we did manage to read at least one byte, then
213 print_insn_i386 will do something sensible. Otherwise, print
214 an error. We do that here because this is where we know
216 if (priv
->max_fetched
== priv
->the_buffer
)
217 (*info
->memory_error_func
) (status
, start
, info
);
218 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
221 priv
->max_fetched
= addr
;
225 /* Possible values for prefix requirement. */
226 #define PREFIX_IGNORED_SHIFT 16
227 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
228 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
233 /* Opcode prefixes. */
234 #define PREFIX_OPCODE (PREFIX_REPZ \
238 /* Prefixes ignored. */
239 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
240 | PREFIX_IGNORED_REPNZ \
241 | PREFIX_IGNORED_DATA)
243 #define XX { NULL, 0 }
244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
246 #define Eb { OP_E, b_mode }
247 #define Ebnd { OP_E, bnd_mode }
248 #define EbS { OP_E, b_swap_mode }
249 #define Ev { OP_E, v_mode }
250 #define Ev_bnd { OP_E, v_bnd_mode }
251 #define EvS { OP_E, v_swap_mode }
252 #define Ed { OP_E, d_mode }
253 #define Edq { OP_E, dq_mode }
254 #define Edqw { OP_E, dqw_mode }
255 #define EdqwS { OP_E, dqw_swap_mode }
256 #define Edqb { OP_E, dqb_mode }
257 #define Edb { OP_E, db_mode }
258 #define Edw { OP_E, dw_mode }
259 #define Edqd { OP_E, dqd_mode }
260 #define Eq { OP_E, q_mode }
261 #define indirEv { OP_indirE, indir_v_mode }
262 #define indirEp { OP_indirE, f_mode }
263 #define stackEv { OP_E, stack_v_mode }
264 #define Em { OP_E, m_mode }
265 #define Ew { OP_E, w_mode }
266 #define M { OP_M, 0 } /* lea, lgdt, etc. */
267 #define Ma { OP_M, a_mode }
268 #define Mb { OP_M, b_mode }
269 #define Md { OP_M, d_mode }
270 #define Mo { OP_M, o_mode }
271 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
272 #define Mq { OP_M, q_mode }
273 #define Mx { OP_M, x_mode }
274 #define Mxmm { OP_M, xmm_mode }
275 #define Gb { OP_G, b_mode }
276 #define Gbnd { OP_G, bnd_mode }
277 #define Gv { OP_G, v_mode }
278 #define Gd { OP_G, d_mode }
279 #define Gdq { OP_G, dq_mode }
280 #define Gm { OP_G, m_mode }
281 #define Gw { OP_G, w_mode }
282 #define Rd { OP_R, d_mode }
283 #define Rdq { OP_R, dq_mode }
284 #define Rm { OP_R, m_mode }
285 #define Ib { OP_I, b_mode }
286 #define sIb { OP_sI, b_mode } /* sign extened byte */
287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
288 #define Iv { OP_I, v_mode }
289 #define sIv { OP_sI, v_mode }
290 #define Iq { OP_I, q_mode }
291 #define Iv64 { OP_I64, v_mode }
292 #define Iw { OP_I, w_mode }
293 #define I1 { OP_I, const_1_mode }
294 #define Jb { OP_J, b_mode }
295 #define Jv { OP_J, v_mode }
296 #define Cm { OP_C, m_mode }
297 #define Dm { OP_D, m_mode }
298 #define Td { OP_T, d_mode }
299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
301 #define RMeAX { OP_REG, eAX_reg }
302 #define RMeBX { OP_REG, eBX_reg }
303 #define RMeCX { OP_REG, eCX_reg }
304 #define RMeDX { OP_REG, eDX_reg }
305 #define RMeSP { OP_REG, eSP_reg }
306 #define RMeBP { OP_REG, eBP_reg }
307 #define RMeSI { OP_REG, eSI_reg }
308 #define RMeDI { OP_REG, eDI_reg }
309 #define RMrAX { OP_REG, rAX_reg }
310 #define RMrBX { OP_REG, rBX_reg }
311 #define RMrCX { OP_REG, rCX_reg }
312 #define RMrDX { OP_REG, rDX_reg }
313 #define RMrSP { OP_REG, rSP_reg }
314 #define RMrBP { OP_REG, rBP_reg }
315 #define RMrSI { OP_REG, rSI_reg }
316 #define RMrDI { OP_REG, rDI_reg }
317 #define RMAL { OP_REG, al_reg }
318 #define RMCL { OP_REG, cl_reg }
319 #define RMDL { OP_REG, dl_reg }
320 #define RMBL { OP_REG, bl_reg }
321 #define RMAH { OP_REG, ah_reg }
322 #define RMCH { OP_REG, ch_reg }
323 #define RMDH { OP_REG, dh_reg }
324 #define RMBH { OP_REG, bh_reg }
325 #define RMAX { OP_REG, ax_reg }
326 #define RMDX { OP_REG, dx_reg }
328 #define eAX { OP_IMREG, eAX_reg }
329 #define eBX { OP_IMREG, eBX_reg }
330 #define eCX { OP_IMREG, eCX_reg }
331 #define eDX { OP_IMREG, eDX_reg }
332 #define eSP { OP_IMREG, eSP_reg }
333 #define eBP { OP_IMREG, eBP_reg }
334 #define eSI { OP_IMREG, eSI_reg }
335 #define eDI { OP_IMREG, eDI_reg }
336 #define AL { OP_IMREG, al_reg }
337 #define CL { OP_IMREG, cl_reg }
338 #define DL { OP_IMREG, dl_reg }
339 #define BL { OP_IMREG, bl_reg }
340 #define AH { OP_IMREG, ah_reg }
341 #define CH { OP_IMREG, ch_reg }
342 #define DH { OP_IMREG, dh_reg }
343 #define BH { OP_IMREG, bh_reg }
344 #define AX { OP_IMREG, ax_reg }
345 #define DX { OP_IMREG, dx_reg }
346 #define zAX { OP_IMREG, z_mode_ax_reg }
347 #define indirDX { OP_IMREG, indir_dx_reg }
349 #define Sw { OP_SEG, w_mode }
350 #define Sv { OP_SEG, v_mode }
351 #define Ap { OP_DIR, 0 }
352 #define Ob { OP_OFF64, b_mode }
353 #define Ov { OP_OFF64, v_mode }
354 #define Xb { OP_DSreg, eSI_reg }
355 #define Xv { OP_DSreg, eSI_reg }
356 #define Xz { OP_DSreg, eSI_reg }
357 #define Yb { OP_ESreg, eDI_reg }
358 #define Yv { OP_ESreg, eDI_reg }
359 #define DSBX { OP_DSreg, eBX_reg }
361 #define es { OP_REG, es_reg }
362 #define ss { OP_REG, ss_reg }
363 #define cs { OP_REG, cs_reg }
364 #define ds { OP_REG, ds_reg }
365 #define fs { OP_REG, fs_reg }
366 #define gs { OP_REG, gs_reg }
368 #define MX { OP_MMX, 0 }
369 #define XM { OP_XMM, 0 }
370 #define XMScalar { OP_XMM, scalar_mode }
371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
372 #define XMM { OP_XMM, xmm_mode }
373 #define XMxmmq { OP_XMM, xmmq_mode }
374 #define EM { OP_EM, v_mode }
375 #define EMS { OP_EM, v_swap_mode }
376 #define EMd { OP_EM, d_mode }
377 #define EMx { OP_EM, x_mode }
378 #define EXw { OP_EX, w_mode }
379 #define EXd { OP_EX, d_mode }
380 #define EXdScalar { OP_EX, d_scalar_mode }
381 #define EXdS { OP_EX, d_swap_mode }
382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
383 #define EXq { OP_EX, q_mode }
384 #define EXqScalar { OP_EX, q_scalar_mode }
385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
386 #define EXqS { OP_EX, q_swap_mode }
387 #define EXx { OP_EX, x_mode }
388 #define EXxS { OP_EX, x_swap_mode }
389 #define EXxmm { OP_EX, xmm_mode }
390 #define EXymm { OP_EX, ymm_mode }
391 #define EXxmmq { OP_EX, xmmq_mode }
392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
395 #define EXxmm_md { OP_EX, xmm_md_mode }
396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
398 #define EXxmmdw { OP_EX, xmmdw_mode }
399 #define EXxmmqd { OP_EX, xmmqd_mode }
400 #define EXymmq { OP_EX, ymmq_mode }
401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
405 #define MS { OP_MS, v_mode }
406 #define XS { OP_XS, v_mode }
407 #define EMCq { OP_EMC, q_mode }
408 #define MXC { OP_MXC, 0 }
409 #define OPSUF { OP_3DNowSuffix, 0 }
410 #define CMP { CMP_Fixup, 0 }
411 #define XMM0 { XMM_Fixup, 0 }
412 #define FXSAVE { FXSAVE_Fixup, 0 }
413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
416 #define Vex { OP_VEX, vex_mode }
417 #define VexScalar { OP_VEX, vex_scalar_mode }
418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
419 #define Vex128 { OP_VEX, vex128_mode }
420 #define Vex256 { OP_VEX, vex256_mode }
421 #define VexGdq { OP_VEX, dq_mode }
422 #define VexI4 { VEXI4_Fixup, 0}
423 #define EXdVex { OP_EX_Vex, d_mode }
424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
426 #define EXqVex { OP_EX_Vex, q_mode }
427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
429 #define EXVexW { OP_EX_VexW, x_mode }
430 #define EXdVexW { OP_EX_VexW, d_mode }
431 #define EXqVexW { OP_EX_VexW, q_mode }
432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
433 #define XMVex { OP_XMM_Vex, 0 }
434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
435 #define XMVexW { OP_XMM_VexW, 0 }
436 #define XMVexI4 { OP_REG_VexI4, x_mode }
437 #define PCLMUL { PCLMUL_Fixup, 0 }
438 #define VZERO { VZERO_Fixup, 0 }
439 #define VCMP { VCMP_Fixup, 0 }
440 #define VPCMP { VPCMP_Fixup, 0 }
442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
445 #define XMask { OP_Mask, mask_mode }
446 #define MaskG { OP_G, mask_mode }
447 #define MaskE { OP_E, mask_mode }
448 #define MaskBDE { OP_E, mask_bd_mode }
449 #define MaskR { OP_R, mask_mode }
450 #define MaskVex { OP_VEX, mask_mode }
452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
457 /* Used handle "rep" prefix for string instructions. */
458 #define Xbr { REP_Fixup, eSI_reg }
459 #define Xvr { REP_Fixup, eSI_reg }
460 #define Ybr { REP_Fixup, eDI_reg }
461 #define Yvr { REP_Fixup, eDI_reg }
462 #define Yzr { REP_Fixup, eDI_reg }
463 #define indirDXr { REP_Fixup, indir_dx_reg }
464 #define ALr { REP_Fixup, al_reg }
465 #define eAXr { REP_Fixup, eAX_reg }
467 /* Used handle HLE prefix for lockable instructions. */
468 #define Ebh1 { HLE_Fixup1, b_mode }
469 #define Evh1 { HLE_Fixup1, v_mode }
470 #define Ebh2 { HLE_Fixup2, b_mode }
471 #define Evh2 { HLE_Fixup2, v_mode }
472 #define Ebh3 { HLE_Fixup3, b_mode }
473 #define Evh3 { HLE_Fixup3, v_mode }
475 #define BND { BND_Fixup, 0 }
477 #define cond_jump_flag { NULL, cond_jump_mode }
478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
480 /* bits in sizeflag */
481 #define SUFFIX_ALWAYS 4
489 /* byte operand with operand swapped */
491 /* byte operand, sign extend like 'T' suffix */
493 /* operand size depends on prefixes */
495 /* operand size depends on prefixes with operand swapped */
499 /* double word operand */
501 /* double word operand with operand swapped */
503 /* quad word operand */
505 /* quad word operand with operand swapped */
507 /* ten-byte operand */
509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
510 broadcast enabled. */
512 /* Similar to x_mode, but with different EVEX mem shifts. */
514 /* Similar to x_mode, but with disabled broadcast. */
516 /* Similar to x_mode, but with operands swapped and disabled broadcast
519 /* 16-byte XMM operand */
521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
522 memory operand (depending on vector length). Broadcast isn't
525 /* Same as xmmq_mode, but broadcast is allowed. */
526 evex_half_bcst_xmmq_mode
,
527 /* XMM register or byte memory operand */
529 /* XMM register or word memory operand */
531 /* XMM register or double word memory operand */
533 /* XMM register or quad word memory operand */
535 /* XMM register or double/quad word memory operand, depending on
538 /* 16-byte XMM, word, double word or quad word operand. */
540 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
542 /* 32-byte YMM operand */
544 /* quad word, ymmword or zmmword memory operand. */
546 /* 32-byte YMM or 16-byte word operand */
548 /* d_mode in 32bit, q_mode in 64bit mode. */
550 /* pair of v_mode operands */
555 /* operand size depends on REX prefixes. */
557 /* registers like dq_mode, memory like w_mode. */
561 /* 4- or 6-byte pointer operand */
564 /* v_mode for indirect branch opcodes. */
566 /* v_mode for stack-related opcodes. */
568 /* non-quad operand size depends on prefixes */
570 /* 16-byte operand */
572 /* registers like dq_mode, memory like b_mode. */
574 /* registers like d_mode, memory like b_mode. */
576 /* registers like d_mode, memory like w_mode. */
578 /* registers like dq_mode, memory like d_mode. */
580 /* normal vex mode */
582 /* 128bit vex mode */
584 /* 256bit vex mode */
586 /* operand size depends on the VEX.W bit. */
589 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
590 vex_vsib_d_w_dq_mode
,
591 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
593 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
594 vex_vsib_q_w_dq_mode
,
595 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
598 /* scalar, ignore vector length. */
600 /* like d_mode, ignore vector length. */
602 /* like d_swap_mode, ignore vector length. */
604 /* like q_mode, ignore vector length. */
606 /* like q_swap_mode, ignore vector length. */
608 /* like vex_mode, ignore vector length. */
610 /* like vex_w_dq_mode, ignore vector length. */
611 vex_scalar_w_dq_mode
,
613 /* Static rounding. */
615 /* Supress all exceptions. */
618 /* Mask register operand. */
620 /* Mask register operand. */
687 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
689 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
690 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
691 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
692 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
693 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
694 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
695 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
696 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
697 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
698 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
699 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
700 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
701 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
702 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
703 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
821 MOD_VEX_0F12_PREFIX_0
,
823 MOD_VEX_0F16_PREFIX_0
,
826 MOD_VEX_W_0_0F41_P_0_LEN_1
,
827 MOD_VEX_W_1_0F41_P_0_LEN_1
,
828 MOD_VEX_W_0_0F41_P_2_LEN_1
,
829 MOD_VEX_W_1_0F41_P_2_LEN_1
,
830 MOD_VEX_W_0_0F42_P_0_LEN_1
,
831 MOD_VEX_W_1_0F42_P_0_LEN_1
,
832 MOD_VEX_W_0_0F42_P_2_LEN_1
,
833 MOD_VEX_W_1_0F42_P_2_LEN_1
,
834 MOD_VEX_W_0_0F44_P_0_LEN_1
,
835 MOD_VEX_W_1_0F44_P_0_LEN_1
,
836 MOD_VEX_W_0_0F44_P_2_LEN_1
,
837 MOD_VEX_W_1_0F44_P_2_LEN_1
,
838 MOD_VEX_W_0_0F45_P_0_LEN_1
,
839 MOD_VEX_W_1_0F45_P_0_LEN_1
,
840 MOD_VEX_W_0_0F45_P_2_LEN_1
,
841 MOD_VEX_W_1_0F45_P_2_LEN_1
,
842 MOD_VEX_W_0_0F46_P_0_LEN_1
,
843 MOD_VEX_W_1_0F46_P_0_LEN_1
,
844 MOD_VEX_W_0_0F46_P_2_LEN_1
,
845 MOD_VEX_W_1_0F46_P_2_LEN_1
,
846 MOD_VEX_W_0_0F47_P_0_LEN_1
,
847 MOD_VEX_W_1_0F47_P_0_LEN_1
,
848 MOD_VEX_W_0_0F47_P_2_LEN_1
,
849 MOD_VEX_W_1_0F47_P_2_LEN_1
,
850 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
851 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
852 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
853 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
854 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
855 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
856 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
868 MOD_VEX_W_0_0F91_P_0_LEN_0
,
869 MOD_VEX_W_1_0F91_P_0_LEN_0
,
870 MOD_VEX_W_0_0F91_P_2_LEN_0
,
871 MOD_VEX_W_1_0F91_P_2_LEN_0
,
872 MOD_VEX_W_0_0F92_P_0_LEN_0
,
873 MOD_VEX_W_0_0F92_P_2_LEN_0
,
874 MOD_VEX_W_0_0F92_P_3_LEN_0
,
875 MOD_VEX_W_1_0F92_P_3_LEN_0
,
876 MOD_VEX_W_0_0F93_P_0_LEN_0
,
877 MOD_VEX_W_0_0F93_P_2_LEN_0
,
878 MOD_VEX_W_0_0F93_P_3_LEN_0
,
879 MOD_VEX_W_1_0F93_P_3_LEN_0
,
880 MOD_VEX_W_0_0F98_P_0_LEN_0
,
881 MOD_VEX_W_1_0F98_P_0_LEN_0
,
882 MOD_VEX_W_0_0F98_P_2_LEN_0
,
883 MOD_VEX_W_1_0F98_P_2_LEN_0
,
884 MOD_VEX_W_0_0F99_P_0_LEN_0
,
885 MOD_VEX_W_1_0F99_P_0_LEN_0
,
886 MOD_VEX_W_0_0F99_P_2_LEN_0
,
887 MOD_VEX_W_1_0F99_P_2_LEN_0
,
890 MOD_VEX_0FD7_PREFIX_2
,
891 MOD_VEX_0FE7_PREFIX_2
,
892 MOD_VEX_0FF0_PREFIX_3
,
893 MOD_VEX_0F381A_PREFIX_2
,
894 MOD_VEX_0F382A_PREFIX_2
,
895 MOD_VEX_0F382C_PREFIX_2
,
896 MOD_VEX_0F382D_PREFIX_2
,
897 MOD_VEX_0F382E_PREFIX_2
,
898 MOD_VEX_0F382F_PREFIX_2
,
899 MOD_VEX_0F385A_PREFIX_2
,
900 MOD_VEX_0F388C_PREFIX_2
,
901 MOD_VEX_0F388E_PREFIX_2
,
902 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
903 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
904 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
905 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
906 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
907 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
908 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
909 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
911 MOD_EVEX_0F10_PREFIX_1
,
912 MOD_EVEX_0F10_PREFIX_3
,
913 MOD_EVEX_0F11_PREFIX_1
,
914 MOD_EVEX_0F11_PREFIX_3
,
915 MOD_EVEX_0F12_PREFIX_0
,
916 MOD_EVEX_0F16_PREFIX_0
,
917 MOD_EVEX_0F38C6_REG_1
,
918 MOD_EVEX_0F38C6_REG_2
,
919 MOD_EVEX_0F38C6_REG_5
,
920 MOD_EVEX_0F38C6_REG_6
,
921 MOD_EVEX_0F38C7_REG_1
,
922 MOD_EVEX_0F38C7_REG_2
,
923 MOD_EVEX_0F38C7_REG_5
,
924 MOD_EVEX_0F38C7_REG_6
987 PREFIX_MOD_0_0FAE_REG_4
,
988 PREFIX_MOD_3_0FAE_REG_4
,
996 PREFIX_MOD_0_0FC7_REG_6
,
997 PREFIX_MOD_3_0FC7_REG_6
,
998 PREFIX_MOD_3_0FC7_REG_7
,
1122 PREFIX_VEX_0F71_REG_2
,
1123 PREFIX_VEX_0F71_REG_4
,
1124 PREFIX_VEX_0F71_REG_6
,
1125 PREFIX_VEX_0F72_REG_2
,
1126 PREFIX_VEX_0F72_REG_4
,
1127 PREFIX_VEX_0F72_REG_6
,
1128 PREFIX_VEX_0F73_REG_2
,
1129 PREFIX_VEX_0F73_REG_3
,
1130 PREFIX_VEX_0F73_REG_6
,
1131 PREFIX_VEX_0F73_REG_7
,
1303 PREFIX_VEX_0F38F3_REG_1
,
1304 PREFIX_VEX_0F38F3_REG_2
,
1305 PREFIX_VEX_0F38F3_REG_3
,
1422 PREFIX_EVEX_0F71_REG_2
,
1423 PREFIX_EVEX_0F71_REG_4
,
1424 PREFIX_EVEX_0F71_REG_6
,
1425 PREFIX_EVEX_0F72_REG_0
,
1426 PREFIX_EVEX_0F72_REG_1
,
1427 PREFIX_EVEX_0F72_REG_2
,
1428 PREFIX_EVEX_0F72_REG_4
,
1429 PREFIX_EVEX_0F72_REG_6
,
1430 PREFIX_EVEX_0F73_REG_2
,
1431 PREFIX_EVEX_0F73_REG_3
,
1432 PREFIX_EVEX_0F73_REG_6
,
1433 PREFIX_EVEX_0F73_REG_7
,
1618 PREFIX_EVEX_0F38C6_REG_1
,
1619 PREFIX_EVEX_0F38C6_REG_2
,
1620 PREFIX_EVEX_0F38C6_REG_5
,
1621 PREFIX_EVEX_0F38C6_REG_6
,
1622 PREFIX_EVEX_0F38C7_REG_1
,
1623 PREFIX_EVEX_0F38C7_REG_2
,
1624 PREFIX_EVEX_0F38C7_REG_5
,
1625 PREFIX_EVEX_0F38C7_REG_6
,
1715 THREE_BYTE_0F38
= 0,
1743 VEX_LEN_0F10_P_1
= 0,
1747 VEX_LEN_0F12_P_0_M_0
,
1748 VEX_LEN_0F12_P_0_M_1
,
1751 VEX_LEN_0F16_P_0_M_0
,
1752 VEX_LEN_0F16_P_0_M_1
,
1816 VEX_LEN_0FAE_R_2_M_0
,
1817 VEX_LEN_0FAE_R_3_M_0
,
1826 VEX_LEN_0F381A_P_2_M_0
,
1829 VEX_LEN_0F385A_P_2_M_0
,
1836 VEX_LEN_0F38F3_R_1_P_0
,
1837 VEX_LEN_0F38F3_R_2_P_0
,
1838 VEX_LEN_0F38F3_R_3_P_0
,
1884 VEX_LEN_0FXOP_08_CC
,
1885 VEX_LEN_0FXOP_08_CD
,
1886 VEX_LEN_0FXOP_08_CE
,
1887 VEX_LEN_0FXOP_08_CF
,
1888 VEX_LEN_0FXOP_08_EC
,
1889 VEX_LEN_0FXOP_08_ED
,
1890 VEX_LEN_0FXOP_08_EE
,
1891 VEX_LEN_0FXOP_08_EF
,
1892 VEX_LEN_0FXOP_09_80
,
1926 VEX_W_0F41_P_0_LEN_1
,
1927 VEX_W_0F41_P_2_LEN_1
,
1928 VEX_W_0F42_P_0_LEN_1
,
1929 VEX_W_0F42_P_2_LEN_1
,
1930 VEX_W_0F44_P_0_LEN_0
,
1931 VEX_W_0F44_P_2_LEN_0
,
1932 VEX_W_0F45_P_0_LEN_1
,
1933 VEX_W_0F45_P_2_LEN_1
,
1934 VEX_W_0F46_P_0_LEN_1
,
1935 VEX_W_0F46_P_2_LEN_1
,
1936 VEX_W_0F47_P_0_LEN_1
,
1937 VEX_W_0F47_P_2_LEN_1
,
1938 VEX_W_0F4A_P_0_LEN_1
,
1939 VEX_W_0F4A_P_2_LEN_1
,
1940 VEX_W_0F4B_P_0_LEN_1
,
1941 VEX_W_0F4B_P_2_LEN_1
,
2021 VEX_W_0F90_P_0_LEN_0
,
2022 VEX_W_0F90_P_2_LEN_0
,
2023 VEX_W_0F91_P_0_LEN_0
,
2024 VEX_W_0F91_P_2_LEN_0
,
2025 VEX_W_0F92_P_0_LEN_0
,
2026 VEX_W_0F92_P_2_LEN_0
,
2027 VEX_W_0F92_P_3_LEN_0
,
2028 VEX_W_0F93_P_0_LEN_0
,
2029 VEX_W_0F93_P_2_LEN_0
,
2030 VEX_W_0F93_P_3_LEN_0
,
2031 VEX_W_0F98_P_0_LEN_0
,
2032 VEX_W_0F98_P_2_LEN_0
,
2033 VEX_W_0F99_P_0_LEN_0
,
2034 VEX_W_0F99_P_2_LEN_0
,
2113 VEX_W_0F381A_P_2_M_0
,
2125 VEX_W_0F382A_P_2_M_0
,
2127 VEX_W_0F382C_P_2_M_0
,
2128 VEX_W_0F382D_P_2_M_0
,
2129 VEX_W_0F382E_P_2_M_0
,
2130 VEX_W_0F382F_P_2_M_0
,
2152 VEX_W_0F385A_P_2_M_0
,
2180 VEX_W_0F3A30_P_2_LEN_0
,
2181 VEX_W_0F3A31_P_2_LEN_0
,
2182 VEX_W_0F3A32_P_2_LEN_0
,
2183 VEX_W_0F3A33_P_2_LEN_0
,
2203 EVEX_W_0F10_P_1_M_0
,
2204 EVEX_W_0F10_P_1_M_1
,
2206 EVEX_W_0F10_P_3_M_0
,
2207 EVEX_W_0F10_P_3_M_1
,
2209 EVEX_W_0F11_P_1_M_0
,
2210 EVEX_W_0F11_P_1_M_1
,
2212 EVEX_W_0F11_P_3_M_0
,
2213 EVEX_W_0F11_P_3_M_1
,
2214 EVEX_W_0F12_P_0_M_0
,
2215 EVEX_W_0F12_P_0_M_1
,
2225 EVEX_W_0F16_P_0_M_0
,
2226 EVEX_W_0F16_P_0_M_1
,
2297 EVEX_W_0F72_R_2_P_2
,
2298 EVEX_W_0F72_R_6_P_2
,
2299 EVEX_W_0F73_R_2_P_2
,
2300 EVEX_W_0F73_R_6_P_2
,
2400 EVEX_W_0F38C7_R_1_P_2
,
2401 EVEX_W_0F38C7_R_2_P_2
,
2402 EVEX_W_0F38C7_R_5_P_2
,
2403 EVEX_W_0F38C7_R_6_P_2
,
2438 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2447 unsigned int prefix_requirement
;
2450 /* Upper case letters in the instruction names here are macros.
2451 'A' => print 'b' if no register operands or suffix_always is true
2452 'B' => print 'b' if suffix_always is true
2453 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2455 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2456 suffix_always is true
2457 'E' => print 'e' if 32-bit form of jcxz
2458 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2459 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2460 'H' => print ",pt" or ",pn" branch hint
2461 'I' => honor following macro letter even in Intel mode (implemented only
2462 for some of the macro letters)
2464 'K' => print 'd' or 'q' if rex prefix is present.
2465 'L' => print 'l' if suffix_always is true
2466 'M' => print 'r' if intel_mnemonic is false.
2467 'N' => print 'n' if instruction has no wait "prefix"
2468 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2469 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2470 or suffix_always is true. print 'q' if rex prefix is present.
2471 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2473 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2474 'S' => print 'w', 'l' or 'q' if suffix_always is true
2475 'T' => print 'q' in 64bit mode if instruction has no operand size
2476 prefix and behave as 'P' otherwise
2477 'U' => print 'q' in 64bit mode if instruction has no operand size
2478 prefix and behave as 'Q' otherwise
2479 'V' => print 'q' in 64bit mode if instruction has no operand size
2480 prefix and behave as 'S' otherwise
2481 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2482 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2483 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2484 suffix_always is true.
2485 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2486 '!' => change condition from true to false or from false to true.
2487 '%' => add 1 upper case letter to the macro.
2488 '^' => print 'w' or 'l' depending on operand size prefix or
2489 suffix_always is true (lcall/ljmp).
2490 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2491 on operand size prefix.
2492 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2493 has no operand size prefix for AMD64 ISA, behave as 'P'
2496 2 upper case letter macros:
2497 "XY" => print 'x' or 'y' if suffix_always is true or no register
2498 operands and no broadcast.
2499 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2500 register operands and no broadcast.
2501 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2502 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2503 or suffix_always is true
2504 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2505 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2506 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2507 "LW" => print 'd', 'q' depending on the VEX.W bit
2508 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2509 an operand size prefix, or suffix_always is true. print
2510 'q' if rex prefix is present.
2512 Many of the above letters print nothing in Intel mode. See "putop"
2515 Braces '{' and '}', and vertical bars '|', indicate alternative
2516 mnemonic strings for AT&T and Intel. */
2518 static const struct dis386 dis386
[] = {
2520 { "addB", { Ebh1
, Gb
}, 0 },
2521 { "addS", { Evh1
, Gv
}, 0 },
2522 { "addB", { Gb
, EbS
}, 0 },
2523 { "addS", { Gv
, EvS
}, 0 },
2524 { "addB", { AL
, Ib
}, 0 },
2525 { "addS", { eAX
, Iv
}, 0 },
2526 { X86_64_TABLE (X86_64_06
) },
2527 { X86_64_TABLE (X86_64_07
) },
2529 { "orB", { Ebh1
, Gb
}, 0 },
2530 { "orS", { Evh1
, Gv
}, 0 },
2531 { "orB", { Gb
, EbS
}, 0 },
2532 { "orS", { Gv
, EvS
}, 0 },
2533 { "orB", { AL
, Ib
}, 0 },
2534 { "orS", { eAX
, Iv
}, 0 },
2535 { X86_64_TABLE (X86_64_0D
) },
2536 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2538 { "adcB", { Ebh1
, Gb
}, 0 },
2539 { "adcS", { Evh1
, Gv
}, 0 },
2540 { "adcB", { Gb
, EbS
}, 0 },
2541 { "adcS", { Gv
, EvS
}, 0 },
2542 { "adcB", { AL
, Ib
}, 0 },
2543 { "adcS", { eAX
, Iv
}, 0 },
2544 { X86_64_TABLE (X86_64_16
) },
2545 { X86_64_TABLE (X86_64_17
) },
2547 { "sbbB", { Ebh1
, Gb
}, 0 },
2548 { "sbbS", { Evh1
, Gv
}, 0 },
2549 { "sbbB", { Gb
, EbS
}, 0 },
2550 { "sbbS", { Gv
, EvS
}, 0 },
2551 { "sbbB", { AL
, Ib
}, 0 },
2552 { "sbbS", { eAX
, Iv
}, 0 },
2553 { X86_64_TABLE (X86_64_1E
) },
2554 { X86_64_TABLE (X86_64_1F
) },
2556 { "andB", { Ebh1
, Gb
}, 0 },
2557 { "andS", { Evh1
, Gv
}, 0 },
2558 { "andB", { Gb
, EbS
}, 0 },
2559 { "andS", { Gv
, EvS
}, 0 },
2560 { "andB", { AL
, Ib
}, 0 },
2561 { "andS", { eAX
, Iv
}, 0 },
2562 { Bad_Opcode
}, /* SEG ES prefix */
2563 { X86_64_TABLE (X86_64_27
) },
2565 { "subB", { Ebh1
, Gb
}, 0 },
2566 { "subS", { Evh1
, Gv
}, 0 },
2567 { "subB", { Gb
, EbS
}, 0 },
2568 { "subS", { Gv
, EvS
}, 0 },
2569 { "subB", { AL
, Ib
}, 0 },
2570 { "subS", { eAX
, Iv
}, 0 },
2571 { Bad_Opcode
}, /* SEG CS prefix */
2572 { X86_64_TABLE (X86_64_2F
) },
2574 { "xorB", { Ebh1
, Gb
}, 0 },
2575 { "xorS", { Evh1
, Gv
}, 0 },
2576 { "xorB", { Gb
, EbS
}, 0 },
2577 { "xorS", { Gv
, EvS
}, 0 },
2578 { "xorB", { AL
, Ib
}, 0 },
2579 { "xorS", { eAX
, Iv
}, 0 },
2580 { Bad_Opcode
}, /* SEG SS prefix */
2581 { X86_64_TABLE (X86_64_37
) },
2583 { "cmpB", { Eb
, Gb
}, 0 },
2584 { "cmpS", { Ev
, Gv
}, 0 },
2585 { "cmpB", { Gb
, EbS
}, 0 },
2586 { "cmpS", { Gv
, EvS
}, 0 },
2587 { "cmpB", { AL
, Ib
}, 0 },
2588 { "cmpS", { eAX
, Iv
}, 0 },
2589 { Bad_Opcode
}, /* SEG DS prefix */
2590 { X86_64_TABLE (X86_64_3F
) },
2592 { "inc{S|}", { RMeAX
}, 0 },
2593 { "inc{S|}", { RMeCX
}, 0 },
2594 { "inc{S|}", { RMeDX
}, 0 },
2595 { "inc{S|}", { RMeBX
}, 0 },
2596 { "inc{S|}", { RMeSP
}, 0 },
2597 { "inc{S|}", { RMeBP
}, 0 },
2598 { "inc{S|}", { RMeSI
}, 0 },
2599 { "inc{S|}", { RMeDI
}, 0 },
2601 { "dec{S|}", { RMeAX
}, 0 },
2602 { "dec{S|}", { RMeCX
}, 0 },
2603 { "dec{S|}", { RMeDX
}, 0 },
2604 { "dec{S|}", { RMeBX
}, 0 },
2605 { "dec{S|}", { RMeSP
}, 0 },
2606 { "dec{S|}", { RMeBP
}, 0 },
2607 { "dec{S|}", { RMeSI
}, 0 },
2608 { "dec{S|}", { RMeDI
}, 0 },
2610 { "pushV", { RMrAX
}, 0 },
2611 { "pushV", { RMrCX
}, 0 },
2612 { "pushV", { RMrDX
}, 0 },
2613 { "pushV", { RMrBX
}, 0 },
2614 { "pushV", { RMrSP
}, 0 },
2615 { "pushV", { RMrBP
}, 0 },
2616 { "pushV", { RMrSI
}, 0 },
2617 { "pushV", { RMrDI
}, 0 },
2619 { "popV", { RMrAX
}, 0 },
2620 { "popV", { RMrCX
}, 0 },
2621 { "popV", { RMrDX
}, 0 },
2622 { "popV", { RMrBX
}, 0 },
2623 { "popV", { RMrSP
}, 0 },
2624 { "popV", { RMrBP
}, 0 },
2625 { "popV", { RMrSI
}, 0 },
2626 { "popV", { RMrDI
}, 0 },
2628 { X86_64_TABLE (X86_64_60
) },
2629 { X86_64_TABLE (X86_64_61
) },
2630 { X86_64_TABLE (X86_64_62
) },
2631 { X86_64_TABLE (X86_64_63
) },
2632 { Bad_Opcode
}, /* seg fs */
2633 { Bad_Opcode
}, /* seg gs */
2634 { Bad_Opcode
}, /* op size prefix */
2635 { Bad_Opcode
}, /* adr size prefix */
2637 { "pushT", { sIv
}, 0 },
2638 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2639 { "pushT", { sIbT
}, 0 },
2640 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2641 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2642 { X86_64_TABLE (X86_64_6D
) },
2643 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2644 { X86_64_TABLE (X86_64_6F
) },
2646 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2647 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2648 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2649 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2650 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2651 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2652 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2653 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2655 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2656 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2657 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2658 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2659 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2660 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2661 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2662 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2664 { REG_TABLE (REG_80
) },
2665 { REG_TABLE (REG_81
) },
2666 { X86_64_TABLE (X86_64_82
) },
2667 { REG_TABLE (REG_83
) },
2668 { "testB", { Eb
, Gb
}, 0 },
2669 { "testS", { Ev
, Gv
}, 0 },
2670 { "xchgB", { Ebh2
, Gb
}, 0 },
2671 { "xchgS", { Evh2
, Gv
}, 0 },
2673 { "movB", { Ebh3
, Gb
}, 0 },
2674 { "movS", { Evh3
, Gv
}, 0 },
2675 { "movB", { Gb
, EbS
}, 0 },
2676 { "movS", { Gv
, EvS
}, 0 },
2677 { "movD", { Sv
, Sw
}, 0 },
2678 { MOD_TABLE (MOD_8D
) },
2679 { "movD", { Sw
, Sv
}, 0 },
2680 { REG_TABLE (REG_8F
) },
2682 { PREFIX_TABLE (PREFIX_90
) },
2683 { "xchgS", { RMeCX
, eAX
}, 0 },
2684 { "xchgS", { RMeDX
, eAX
}, 0 },
2685 { "xchgS", { RMeBX
, eAX
}, 0 },
2686 { "xchgS", { RMeSP
, eAX
}, 0 },
2687 { "xchgS", { RMeBP
, eAX
}, 0 },
2688 { "xchgS", { RMeSI
, eAX
}, 0 },
2689 { "xchgS", { RMeDI
, eAX
}, 0 },
2691 { "cW{t|}R", { XX
}, 0 },
2692 { "cR{t|}O", { XX
}, 0 },
2693 { X86_64_TABLE (X86_64_9A
) },
2694 { Bad_Opcode
}, /* fwait */
2695 { "pushfT", { XX
}, 0 },
2696 { "popfT", { XX
}, 0 },
2697 { "sahf", { XX
}, 0 },
2698 { "lahf", { XX
}, 0 },
2700 { "mov%LB", { AL
, Ob
}, 0 },
2701 { "mov%LS", { eAX
, Ov
}, 0 },
2702 { "mov%LB", { Ob
, AL
}, 0 },
2703 { "mov%LS", { Ov
, eAX
}, 0 },
2704 { "movs{b|}", { Ybr
, Xb
}, 0 },
2705 { "movs{R|}", { Yvr
, Xv
}, 0 },
2706 { "cmps{b|}", { Xb
, Yb
}, 0 },
2707 { "cmps{R|}", { Xv
, Yv
}, 0 },
2709 { "testB", { AL
, Ib
}, 0 },
2710 { "testS", { eAX
, Iv
}, 0 },
2711 { "stosB", { Ybr
, AL
}, 0 },
2712 { "stosS", { Yvr
, eAX
}, 0 },
2713 { "lodsB", { ALr
, Xb
}, 0 },
2714 { "lodsS", { eAXr
, Xv
}, 0 },
2715 { "scasB", { AL
, Yb
}, 0 },
2716 { "scasS", { eAX
, Yv
}, 0 },
2718 { "movB", { RMAL
, Ib
}, 0 },
2719 { "movB", { RMCL
, Ib
}, 0 },
2720 { "movB", { RMDL
, Ib
}, 0 },
2721 { "movB", { RMBL
, Ib
}, 0 },
2722 { "movB", { RMAH
, Ib
}, 0 },
2723 { "movB", { RMCH
, Ib
}, 0 },
2724 { "movB", { RMDH
, Ib
}, 0 },
2725 { "movB", { RMBH
, Ib
}, 0 },
2727 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2728 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2729 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2730 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2731 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2732 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2733 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2734 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2736 { REG_TABLE (REG_C0
) },
2737 { REG_TABLE (REG_C1
) },
2738 { "retT", { Iw
, BND
}, 0 },
2739 { "retT", { BND
}, 0 },
2740 { X86_64_TABLE (X86_64_C4
) },
2741 { X86_64_TABLE (X86_64_C5
) },
2742 { REG_TABLE (REG_C6
) },
2743 { REG_TABLE (REG_C7
) },
2745 { "enterT", { Iw
, Ib
}, 0 },
2746 { "leaveT", { XX
}, 0 },
2747 { "Jret{|f}P", { Iw
}, 0 },
2748 { "Jret{|f}P", { XX
}, 0 },
2749 { "int3", { XX
}, 0 },
2750 { "int", { Ib
}, 0 },
2751 { X86_64_TABLE (X86_64_CE
) },
2752 { "iret%LP", { XX
}, 0 },
2754 { REG_TABLE (REG_D0
) },
2755 { REG_TABLE (REG_D1
) },
2756 { REG_TABLE (REG_D2
) },
2757 { REG_TABLE (REG_D3
) },
2758 { X86_64_TABLE (X86_64_D4
) },
2759 { X86_64_TABLE (X86_64_D5
) },
2761 { "xlat", { DSBX
}, 0 },
2772 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2773 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2774 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2775 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2776 { "inB", { AL
, Ib
}, 0 },
2777 { "inG", { zAX
, Ib
}, 0 },
2778 { "outB", { Ib
, AL
}, 0 },
2779 { "outG", { Ib
, zAX
}, 0 },
2781 { X86_64_TABLE (X86_64_E8
) },
2782 { X86_64_TABLE (X86_64_E9
) },
2783 { X86_64_TABLE (X86_64_EA
) },
2784 { "jmp", { Jb
, BND
}, 0 },
2785 { "inB", { AL
, indirDX
}, 0 },
2786 { "inG", { zAX
, indirDX
}, 0 },
2787 { "outB", { indirDX
, AL
}, 0 },
2788 { "outG", { indirDX
, zAX
}, 0 },
2790 { Bad_Opcode
}, /* lock prefix */
2791 { "icebp", { XX
}, 0 },
2792 { Bad_Opcode
}, /* repne */
2793 { Bad_Opcode
}, /* repz */
2794 { "hlt", { XX
}, 0 },
2795 { "cmc", { XX
}, 0 },
2796 { REG_TABLE (REG_F6
) },
2797 { REG_TABLE (REG_F7
) },
2799 { "clc", { XX
}, 0 },
2800 { "stc", { XX
}, 0 },
2801 { "cli", { XX
}, 0 },
2802 { "sti", { XX
}, 0 },
2803 { "cld", { XX
}, 0 },
2804 { "std", { XX
}, 0 },
2805 { REG_TABLE (REG_FE
) },
2806 { REG_TABLE (REG_FF
) },
2809 static const struct dis386 dis386_twobyte
[] = {
2811 { REG_TABLE (REG_0F00
) },
2812 { REG_TABLE (REG_0F01
) },
2813 { "larS", { Gv
, Ew
}, 0 },
2814 { "lslS", { Gv
, Ew
}, 0 },
2816 { "syscall", { XX
}, 0 },
2817 { "clts", { XX
}, 0 },
2818 { "sysret%LP", { XX
}, 0 },
2820 { "invd", { XX
}, 0 },
2821 { "wbinvd", { XX
}, 0 },
2823 { "ud2", { XX
}, 0 },
2825 { REG_TABLE (REG_0F0D
) },
2826 { "femms", { XX
}, 0 },
2827 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2829 { PREFIX_TABLE (PREFIX_0F10
) },
2830 { PREFIX_TABLE (PREFIX_0F11
) },
2831 { PREFIX_TABLE (PREFIX_0F12
) },
2832 { MOD_TABLE (MOD_0F13
) },
2833 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2834 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2835 { PREFIX_TABLE (PREFIX_0F16
) },
2836 { MOD_TABLE (MOD_0F17
) },
2838 { REG_TABLE (REG_0F18
) },
2839 { "nopQ", { Ev
}, 0 },
2840 { PREFIX_TABLE (PREFIX_0F1A
) },
2841 { PREFIX_TABLE (PREFIX_0F1B
) },
2842 { "nopQ", { Ev
}, 0 },
2843 { "nopQ", { Ev
}, 0 },
2844 { "nopQ", { Ev
}, 0 },
2845 { "nopQ", { Ev
}, 0 },
2847 { "movZ", { Rm
, Cm
}, 0 },
2848 { "movZ", { Rm
, Dm
}, 0 },
2849 { "movZ", { Cm
, Rm
}, 0 },
2850 { "movZ", { Dm
, Rm
}, 0 },
2851 { MOD_TABLE (MOD_0F24
) },
2853 { MOD_TABLE (MOD_0F26
) },
2856 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2857 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2858 { PREFIX_TABLE (PREFIX_0F2A
) },
2859 { PREFIX_TABLE (PREFIX_0F2B
) },
2860 { PREFIX_TABLE (PREFIX_0F2C
) },
2861 { PREFIX_TABLE (PREFIX_0F2D
) },
2862 { PREFIX_TABLE (PREFIX_0F2E
) },
2863 { PREFIX_TABLE (PREFIX_0F2F
) },
2865 { "wrmsr", { XX
}, 0 },
2866 { "rdtsc", { XX
}, 0 },
2867 { "rdmsr", { XX
}, 0 },
2868 { "rdpmc", { XX
}, 0 },
2869 { "sysenter", { XX
}, 0 },
2870 { "sysexit", { XX
}, 0 },
2872 { "getsec", { XX
}, 0 },
2874 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2876 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2883 { "cmovoS", { Gv
, Ev
}, 0 },
2884 { "cmovnoS", { Gv
, Ev
}, 0 },
2885 { "cmovbS", { Gv
, Ev
}, 0 },
2886 { "cmovaeS", { Gv
, Ev
}, 0 },
2887 { "cmoveS", { Gv
, Ev
}, 0 },
2888 { "cmovneS", { Gv
, Ev
}, 0 },
2889 { "cmovbeS", { Gv
, Ev
}, 0 },
2890 { "cmovaS", { Gv
, Ev
}, 0 },
2892 { "cmovsS", { Gv
, Ev
}, 0 },
2893 { "cmovnsS", { Gv
, Ev
}, 0 },
2894 { "cmovpS", { Gv
, Ev
}, 0 },
2895 { "cmovnpS", { Gv
, Ev
}, 0 },
2896 { "cmovlS", { Gv
, Ev
}, 0 },
2897 { "cmovgeS", { Gv
, Ev
}, 0 },
2898 { "cmovleS", { Gv
, Ev
}, 0 },
2899 { "cmovgS", { Gv
, Ev
}, 0 },
2901 { MOD_TABLE (MOD_0F51
) },
2902 { PREFIX_TABLE (PREFIX_0F51
) },
2903 { PREFIX_TABLE (PREFIX_0F52
) },
2904 { PREFIX_TABLE (PREFIX_0F53
) },
2905 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2906 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2907 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2908 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2910 { PREFIX_TABLE (PREFIX_0F58
) },
2911 { PREFIX_TABLE (PREFIX_0F59
) },
2912 { PREFIX_TABLE (PREFIX_0F5A
) },
2913 { PREFIX_TABLE (PREFIX_0F5B
) },
2914 { PREFIX_TABLE (PREFIX_0F5C
) },
2915 { PREFIX_TABLE (PREFIX_0F5D
) },
2916 { PREFIX_TABLE (PREFIX_0F5E
) },
2917 { PREFIX_TABLE (PREFIX_0F5F
) },
2919 { PREFIX_TABLE (PREFIX_0F60
) },
2920 { PREFIX_TABLE (PREFIX_0F61
) },
2921 { PREFIX_TABLE (PREFIX_0F62
) },
2922 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2923 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2924 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2925 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2926 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2928 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2929 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2930 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2931 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2932 { PREFIX_TABLE (PREFIX_0F6C
) },
2933 { PREFIX_TABLE (PREFIX_0F6D
) },
2934 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2935 { PREFIX_TABLE (PREFIX_0F6F
) },
2937 { PREFIX_TABLE (PREFIX_0F70
) },
2938 { REG_TABLE (REG_0F71
) },
2939 { REG_TABLE (REG_0F72
) },
2940 { REG_TABLE (REG_0F73
) },
2941 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2942 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2943 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2944 { "emms", { XX
}, PREFIX_OPCODE
},
2946 { PREFIX_TABLE (PREFIX_0F78
) },
2947 { PREFIX_TABLE (PREFIX_0F79
) },
2948 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2950 { PREFIX_TABLE (PREFIX_0F7C
) },
2951 { PREFIX_TABLE (PREFIX_0F7D
) },
2952 { PREFIX_TABLE (PREFIX_0F7E
) },
2953 { PREFIX_TABLE (PREFIX_0F7F
) },
2955 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2956 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2957 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2958 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2959 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2960 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2961 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2962 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2964 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2965 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2966 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2967 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2968 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2969 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2970 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2971 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2973 { "seto", { Eb
}, 0 },
2974 { "setno", { Eb
}, 0 },
2975 { "setb", { Eb
}, 0 },
2976 { "setae", { Eb
}, 0 },
2977 { "sete", { Eb
}, 0 },
2978 { "setne", { Eb
}, 0 },
2979 { "setbe", { Eb
}, 0 },
2980 { "seta", { Eb
}, 0 },
2982 { "sets", { Eb
}, 0 },
2983 { "setns", { Eb
}, 0 },
2984 { "setp", { Eb
}, 0 },
2985 { "setnp", { Eb
}, 0 },
2986 { "setl", { Eb
}, 0 },
2987 { "setge", { Eb
}, 0 },
2988 { "setle", { Eb
}, 0 },
2989 { "setg", { Eb
}, 0 },
2991 { "pushT", { fs
}, 0 },
2992 { "popT", { fs
}, 0 },
2993 { "cpuid", { XX
}, 0 },
2994 { "btS", { Ev
, Gv
}, 0 },
2995 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2996 { "shldS", { Ev
, Gv
, CL
}, 0 },
2997 { REG_TABLE (REG_0FA6
) },
2998 { REG_TABLE (REG_0FA7
) },
3000 { "pushT", { gs
}, 0 },
3001 { "popT", { gs
}, 0 },
3002 { "rsm", { XX
}, 0 },
3003 { "btsS", { Evh1
, Gv
}, 0 },
3004 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
3005 { "shrdS", { Ev
, Gv
, CL
}, 0 },
3006 { REG_TABLE (REG_0FAE
) },
3007 { "imulS", { Gv
, Ev
}, 0 },
3009 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
3010 { "cmpxchgS", { Evh1
, Gv
}, 0 },
3011 { MOD_TABLE (MOD_0FB2
) },
3012 { "btrS", { Evh1
, Gv
}, 0 },
3013 { MOD_TABLE (MOD_0FB4
) },
3014 { MOD_TABLE (MOD_0FB5
) },
3015 { "movz{bR|x}", { Gv
, Eb
}, 0 },
3016 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
3018 { PREFIX_TABLE (PREFIX_0FB8
) },
3019 { "ud1", { XX
}, 0 },
3020 { REG_TABLE (REG_0FBA
) },
3021 { "btcS", { Evh1
, Gv
}, 0 },
3022 { PREFIX_TABLE (PREFIX_0FBC
) },
3023 { PREFIX_TABLE (PREFIX_0FBD
) },
3024 { "movs{bR|x}", { Gv
, Eb
}, 0 },
3025 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
3027 { "xaddB", { Ebh1
, Gb
}, 0 },
3028 { "xaddS", { Evh1
, Gv
}, 0 },
3029 { PREFIX_TABLE (PREFIX_0FC2
) },
3030 { MOD_TABLE (MOD_0FC3
) },
3031 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
3032 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
3033 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3034 { REG_TABLE (REG_0FC7
) },
3036 { "bswap", { RMeAX
}, 0 },
3037 { "bswap", { RMeCX
}, 0 },
3038 { "bswap", { RMeDX
}, 0 },
3039 { "bswap", { RMeBX
}, 0 },
3040 { "bswap", { RMeSP
}, 0 },
3041 { "bswap", { RMeBP
}, 0 },
3042 { "bswap", { RMeSI
}, 0 },
3043 { "bswap", { RMeDI
}, 0 },
3045 { PREFIX_TABLE (PREFIX_0FD0
) },
3046 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
3047 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
3048 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
3049 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
3050 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
3051 { PREFIX_TABLE (PREFIX_0FD6
) },
3052 { MOD_TABLE (MOD_0FD7
) },
3054 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
3055 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
3056 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
3057 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
3058 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
3059 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
3060 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
3061 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
3063 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
3064 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
3065 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
3066 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
3067 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
3068 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
3069 { PREFIX_TABLE (PREFIX_0FE6
) },
3070 { PREFIX_TABLE (PREFIX_0FE7
) },
3072 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
3073 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
3074 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
3075 { "por", { MX
, EM
}, PREFIX_OPCODE
},
3076 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
3077 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
3078 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
3079 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
3081 { PREFIX_TABLE (PREFIX_0FF0
) },
3082 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
3083 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
3084 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
3085 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
3086 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
3087 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
3088 { PREFIX_TABLE (PREFIX_0FF7
) },
3090 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
3091 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
3092 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
3093 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
3094 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
3095 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
3096 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
3100 static const unsigned char onebyte_has_modrm
[256] = {
3101 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3102 /* ------------------------------- */
3103 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3104 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3105 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3106 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3107 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3108 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3109 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3110 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3111 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3112 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3113 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3114 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3115 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3116 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3117 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3118 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3119 /* ------------------------------- */
3120 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3123 static const unsigned char twobyte_has_modrm
[256] = {
3124 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3125 /* ------------------------------- */
3126 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3127 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3128 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3129 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3130 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3131 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3132 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3133 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3134 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3135 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3136 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3137 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3138 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3139 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3140 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3141 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3142 /* ------------------------------- */
3143 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3146 static char obuf
[100];
3148 static char *mnemonicendp
;
3149 static char scratchbuf
[100];
3150 static unsigned char *start_codep
;
3151 static unsigned char *insn_codep
;
3152 static unsigned char *codep
;
3153 static unsigned char *end_codep
;
3154 static int last_lock_prefix
;
3155 static int last_repz_prefix
;
3156 static int last_repnz_prefix
;
3157 static int last_data_prefix
;
3158 static int last_addr_prefix
;
3159 static int last_rex_prefix
;
3160 static int last_seg_prefix
;
3161 static int fwait_prefix
;
3162 /* The active segment register prefix. */
3163 static int active_seg_prefix
;
3164 #define MAX_CODE_LENGTH 15
3165 /* We can up to 14 prefixes since the maximum instruction length is
3167 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3168 static disassemble_info
*the_info
;
3176 static unsigned char need_modrm
;
3186 int register_specifier
;
3193 int mask_register_specifier
;
3199 static unsigned char need_vex
;
3200 static unsigned char need_vex_reg
;
3201 static unsigned char vex_w_done
;
3209 /* If we are accessing mod/rm/reg without need_modrm set, then the
3210 values are stale. Hitting this abort likely indicates that you
3211 need to update onebyte_has_modrm or twobyte_has_modrm. */
3212 #define MODRM_CHECK if (!need_modrm) abort ()
3214 static const char **names64
;
3215 static const char **names32
;
3216 static const char **names16
;
3217 static const char **names8
;
3218 static const char **names8rex
;
3219 static const char **names_seg
;
3220 static const char *index64
;
3221 static const char *index32
;
3222 static const char **index16
;
3223 static const char **names_bnd
;
3225 static const char *intel_names64
[] = {
3226 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3227 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3229 static const char *intel_names32
[] = {
3230 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3231 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3233 static const char *intel_names16
[] = {
3234 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3235 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3237 static const char *intel_names8
[] = {
3238 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3240 static const char *intel_names8rex
[] = {
3241 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3242 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3244 static const char *intel_names_seg
[] = {
3245 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3247 static const char *intel_index64
= "riz";
3248 static const char *intel_index32
= "eiz";
3249 static const char *intel_index16
[] = {
3250 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3253 static const char *att_names64
[] = {
3254 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3255 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3257 static const char *att_names32
[] = {
3258 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3259 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3261 static const char *att_names16
[] = {
3262 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3263 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3265 static const char *att_names8
[] = {
3266 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3268 static const char *att_names8rex
[] = {
3269 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3270 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3272 static const char *att_names_seg
[] = {
3273 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3275 static const char *att_index64
= "%riz";
3276 static const char *att_index32
= "%eiz";
3277 static const char *att_index16
[] = {
3278 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3281 static const char **names_mm
;
3282 static const char *intel_names_mm
[] = {
3283 "mm0", "mm1", "mm2", "mm3",
3284 "mm4", "mm5", "mm6", "mm7"
3286 static const char *att_names_mm
[] = {
3287 "%mm0", "%mm1", "%mm2", "%mm3",
3288 "%mm4", "%mm5", "%mm6", "%mm7"
3291 static const char *intel_names_bnd
[] = {
3292 "bnd0", "bnd1", "bnd2", "bnd3"
3295 static const char *att_names_bnd
[] = {
3296 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3299 static const char **names_xmm
;
3300 static const char *intel_names_xmm
[] = {
3301 "xmm0", "xmm1", "xmm2", "xmm3",
3302 "xmm4", "xmm5", "xmm6", "xmm7",
3303 "xmm8", "xmm9", "xmm10", "xmm11",
3304 "xmm12", "xmm13", "xmm14", "xmm15",
3305 "xmm16", "xmm17", "xmm18", "xmm19",
3306 "xmm20", "xmm21", "xmm22", "xmm23",
3307 "xmm24", "xmm25", "xmm26", "xmm27",
3308 "xmm28", "xmm29", "xmm30", "xmm31"
3310 static const char *att_names_xmm
[] = {
3311 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3312 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3313 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3314 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3315 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3316 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3317 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3318 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3321 static const char **names_ymm
;
3322 static const char *intel_names_ymm
[] = {
3323 "ymm0", "ymm1", "ymm2", "ymm3",
3324 "ymm4", "ymm5", "ymm6", "ymm7",
3325 "ymm8", "ymm9", "ymm10", "ymm11",
3326 "ymm12", "ymm13", "ymm14", "ymm15",
3327 "ymm16", "ymm17", "ymm18", "ymm19",
3328 "ymm20", "ymm21", "ymm22", "ymm23",
3329 "ymm24", "ymm25", "ymm26", "ymm27",
3330 "ymm28", "ymm29", "ymm30", "ymm31"
3332 static const char *att_names_ymm
[] = {
3333 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3334 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3335 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3336 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3337 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3338 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3339 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3340 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3343 static const char **names_zmm
;
3344 static const char *intel_names_zmm
[] = {
3345 "zmm0", "zmm1", "zmm2", "zmm3",
3346 "zmm4", "zmm5", "zmm6", "zmm7",
3347 "zmm8", "zmm9", "zmm10", "zmm11",
3348 "zmm12", "zmm13", "zmm14", "zmm15",
3349 "zmm16", "zmm17", "zmm18", "zmm19",
3350 "zmm20", "zmm21", "zmm22", "zmm23",
3351 "zmm24", "zmm25", "zmm26", "zmm27",
3352 "zmm28", "zmm29", "zmm30", "zmm31"
3354 static const char *att_names_zmm
[] = {
3355 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3356 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3357 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3358 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3359 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3360 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3361 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3362 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3365 static const char **names_mask
;
3366 static const char *intel_names_mask
[] = {
3367 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3369 static const char *att_names_mask
[] = {
3370 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3373 static const char *names_rounding
[] =
3381 static const struct dis386 reg_table
[][8] = {
3384 { "addA", { Ebh1
, Ib
}, 0 },
3385 { "orA", { Ebh1
, Ib
}, 0 },
3386 { "adcA", { Ebh1
, Ib
}, 0 },
3387 { "sbbA", { Ebh1
, Ib
}, 0 },
3388 { "andA", { Ebh1
, Ib
}, 0 },
3389 { "subA", { Ebh1
, Ib
}, 0 },
3390 { "xorA", { Ebh1
, Ib
}, 0 },
3391 { "cmpA", { Eb
, Ib
}, 0 },
3395 { "addQ", { Evh1
, Iv
}, 0 },
3396 { "orQ", { Evh1
, Iv
}, 0 },
3397 { "adcQ", { Evh1
, Iv
}, 0 },
3398 { "sbbQ", { Evh1
, Iv
}, 0 },
3399 { "andQ", { Evh1
, Iv
}, 0 },
3400 { "subQ", { Evh1
, Iv
}, 0 },
3401 { "xorQ", { Evh1
, Iv
}, 0 },
3402 { "cmpQ", { Ev
, Iv
}, 0 },
3406 { "addQ", { Evh1
, sIb
}, 0 },
3407 { "orQ", { Evh1
, sIb
}, 0 },
3408 { "adcQ", { Evh1
, sIb
}, 0 },
3409 { "sbbQ", { Evh1
, sIb
}, 0 },
3410 { "andQ", { Evh1
, sIb
}, 0 },
3411 { "subQ", { Evh1
, sIb
}, 0 },
3412 { "xorQ", { Evh1
, sIb
}, 0 },
3413 { "cmpQ", { Ev
, sIb
}, 0 },
3417 { "popU", { stackEv
}, 0 },
3418 { XOP_8F_TABLE (XOP_09
) },
3422 { XOP_8F_TABLE (XOP_09
) },
3426 { "rolA", { Eb
, Ib
}, 0 },
3427 { "rorA", { Eb
, Ib
}, 0 },
3428 { "rclA", { Eb
, Ib
}, 0 },
3429 { "rcrA", { Eb
, Ib
}, 0 },
3430 { "shlA", { Eb
, Ib
}, 0 },
3431 { "shrA", { Eb
, Ib
}, 0 },
3433 { "sarA", { Eb
, Ib
}, 0 },
3437 { "rolQ", { Ev
, Ib
}, 0 },
3438 { "rorQ", { Ev
, Ib
}, 0 },
3439 { "rclQ", { Ev
, Ib
}, 0 },
3440 { "rcrQ", { Ev
, Ib
}, 0 },
3441 { "shlQ", { Ev
, Ib
}, 0 },
3442 { "shrQ", { Ev
, Ib
}, 0 },
3444 { "sarQ", { Ev
, Ib
}, 0 },
3448 { "movA", { Ebh3
, Ib
}, 0 },
3455 { MOD_TABLE (MOD_C6_REG_7
) },
3459 { "movQ", { Evh3
, Iv
}, 0 },
3466 { MOD_TABLE (MOD_C7_REG_7
) },
3470 { "rolA", { Eb
, I1
}, 0 },
3471 { "rorA", { Eb
, I1
}, 0 },
3472 { "rclA", { Eb
, I1
}, 0 },
3473 { "rcrA", { Eb
, I1
}, 0 },
3474 { "shlA", { Eb
, I1
}, 0 },
3475 { "shrA", { Eb
, I1
}, 0 },
3477 { "sarA", { Eb
, I1
}, 0 },
3481 { "rolQ", { Ev
, I1
}, 0 },
3482 { "rorQ", { Ev
, I1
}, 0 },
3483 { "rclQ", { Ev
, I1
}, 0 },
3484 { "rcrQ", { Ev
, I1
}, 0 },
3485 { "shlQ", { Ev
, I1
}, 0 },
3486 { "shrQ", { Ev
, I1
}, 0 },
3488 { "sarQ", { Ev
, I1
}, 0 },
3492 { "rolA", { Eb
, CL
}, 0 },
3493 { "rorA", { Eb
, CL
}, 0 },
3494 { "rclA", { Eb
, CL
}, 0 },
3495 { "rcrA", { Eb
, CL
}, 0 },
3496 { "shlA", { Eb
, CL
}, 0 },
3497 { "shrA", { Eb
, CL
}, 0 },
3499 { "sarA", { Eb
, CL
}, 0 },
3503 { "rolQ", { Ev
, CL
}, 0 },
3504 { "rorQ", { Ev
, CL
}, 0 },
3505 { "rclQ", { Ev
, CL
}, 0 },
3506 { "rcrQ", { Ev
, CL
}, 0 },
3507 { "shlQ", { Ev
, CL
}, 0 },
3508 { "shrQ", { Ev
, CL
}, 0 },
3510 { "sarQ", { Ev
, CL
}, 0 },
3514 { "testA", { Eb
, Ib
}, 0 },
3516 { "notA", { Ebh1
}, 0 },
3517 { "negA", { Ebh1
}, 0 },
3518 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3519 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3520 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3521 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3525 { "testQ", { Ev
, Iv
}, 0 },
3527 { "notQ", { Evh1
}, 0 },
3528 { "negQ", { Evh1
}, 0 },
3529 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3530 { "imulQ", { Ev
}, 0 },
3531 { "divQ", { Ev
}, 0 },
3532 { "idivQ", { Ev
}, 0 },
3536 { "incA", { Ebh1
}, 0 },
3537 { "decA", { Ebh1
}, 0 },
3541 { "incQ", { Evh1
}, 0 },
3542 { "decQ", { Evh1
}, 0 },
3543 { "call{&|}", { indirEv
, BND
}, 0 },
3544 { MOD_TABLE (MOD_FF_REG_3
) },
3545 { "jmp{&|}", { indirEv
, BND
}, 0 },
3546 { MOD_TABLE (MOD_FF_REG_5
) },
3547 { "pushU", { stackEv
}, 0 },
3552 { "sldtD", { Sv
}, 0 },
3553 { "strD", { Sv
}, 0 },
3554 { "lldt", { Ew
}, 0 },
3555 { "ltr", { Ew
}, 0 },
3556 { "verr", { Ew
}, 0 },
3557 { "verw", { Ew
}, 0 },
3563 { MOD_TABLE (MOD_0F01_REG_0
) },
3564 { MOD_TABLE (MOD_0F01_REG_1
) },
3565 { MOD_TABLE (MOD_0F01_REG_2
) },
3566 { MOD_TABLE (MOD_0F01_REG_3
) },
3567 { "smswD", { Sv
}, 0 },
3568 { MOD_TABLE (MOD_0F01_REG_5
) },
3569 { "lmsw", { Ew
}, 0 },
3570 { MOD_TABLE (MOD_0F01_REG_7
) },
3574 { "prefetch", { Mb
}, 0 },
3575 { "prefetchw", { Mb
}, 0 },
3576 { "prefetchwt1", { Mb
}, 0 },
3577 { "prefetch", { Mb
}, 0 },
3578 { "prefetch", { Mb
}, 0 },
3579 { "prefetch", { Mb
}, 0 },
3580 { "prefetch", { Mb
}, 0 },
3581 { "prefetch", { Mb
}, 0 },
3585 { MOD_TABLE (MOD_0F18_REG_0
) },
3586 { MOD_TABLE (MOD_0F18_REG_1
) },
3587 { MOD_TABLE (MOD_0F18_REG_2
) },
3588 { MOD_TABLE (MOD_0F18_REG_3
) },
3589 { MOD_TABLE (MOD_0F18_REG_4
) },
3590 { MOD_TABLE (MOD_0F18_REG_5
) },
3591 { MOD_TABLE (MOD_0F18_REG_6
) },
3592 { MOD_TABLE (MOD_0F18_REG_7
) },
3598 { MOD_TABLE (MOD_0F71_REG_2
) },
3600 { MOD_TABLE (MOD_0F71_REG_4
) },
3602 { MOD_TABLE (MOD_0F71_REG_6
) },
3608 { MOD_TABLE (MOD_0F72_REG_2
) },
3610 { MOD_TABLE (MOD_0F72_REG_4
) },
3612 { MOD_TABLE (MOD_0F72_REG_6
) },
3618 { MOD_TABLE (MOD_0F73_REG_2
) },
3619 { MOD_TABLE (MOD_0F73_REG_3
) },
3622 { MOD_TABLE (MOD_0F73_REG_6
) },
3623 { MOD_TABLE (MOD_0F73_REG_7
) },
3627 { "montmul", { { OP_0f07
, 0 } }, 0 },
3628 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3629 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3633 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3634 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3635 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3636 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3637 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3638 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3642 { MOD_TABLE (MOD_0FAE_REG_0
) },
3643 { MOD_TABLE (MOD_0FAE_REG_1
) },
3644 { MOD_TABLE (MOD_0FAE_REG_2
) },
3645 { MOD_TABLE (MOD_0FAE_REG_3
) },
3646 { MOD_TABLE (MOD_0FAE_REG_4
) },
3647 { MOD_TABLE (MOD_0FAE_REG_5
) },
3648 { MOD_TABLE (MOD_0FAE_REG_6
) },
3649 { MOD_TABLE (MOD_0FAE_REG_7
) },
3657 { "btQ", { Ev
, Ib
}, 0 },
3658 { "btsQ", { Evh1
, Ib
}, 0 },
3659 { "btrQ", { Evh1
, Ib
}, 0 },
3660 { "btcQ", { Evh1
, Ib
}, 0 },
3665 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3667 { MOD_TABLE (MOD_0FC7_REG_3
) },
3668 { MOD_TABLE (MOD_0FC7_REG_4
) },
3669 { MOD_TABLE (MOD_0FC7_REG_5
) },
3670 { MOD_TABLE (MOD_0FC7_REG_6
) },
3671 { MOD_TABLE (MOD_0FC7_REG_7
) },
3677 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3679 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3681 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3687 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3689 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3691 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3697 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3698 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3701 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3702 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3708 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3709 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3711 /* REG_VEX_0F38F3 */
3714 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3715 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3716 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3720 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3721 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3725 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3726 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3728 /* REG_XOP_TBM_01 */
3731 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3732 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3733 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3734 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3735 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3736 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3737 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3739 /* REG_XOP_TBM_02 */
3742 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3747 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3749 #define NEED_REG_TABLE
3750 #include "i386-dis-evex.h"
3751 #undef NEED_REG_TABLE
3754 static const struct dis386 prefix_table
[][4] = {
3757 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3758 { "pause", { XX
}, 0 },
3759 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3760 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3765 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3766 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3767 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3768 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3773 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3774 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3775 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3776 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3781 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3782 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3783 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3784 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3789 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3790 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3791 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3796 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3797 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3798 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3799 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3804 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3805 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3806 { "bndmov", { Ebnd
, Gbnd
}, 0 },
3807 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3812 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3813 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3814 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3815 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3820 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3821 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3822 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3823 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3828 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3829 { "cvttss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3830 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3831 { "cvttsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3836 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3837 { "cvtss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3838 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3839 { "cvtsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3844 { "ucomiss",{ XM
, EXd
}, 0 },
3846 { "ucomisd",{ XM
, EXq
}, 0 },
3851 { "comiss", { XM
, EXd
}, 0 },
3853 { "comisd", { XM
, EXq
}, 0 },
3858 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3859 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3860 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3861 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3866 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3867 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3872 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3873 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3878 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3879 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3880 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3881 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3886 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3887 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3888 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3889 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3894 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3895 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3896 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3897 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3902 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3903 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3904 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3909 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3910 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3911 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3912 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3917 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3918 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3919 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3920 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3925 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3926 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3927 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3928 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3933 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3934 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3935 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3936 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3941 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3943 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3948 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3950 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3955 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3957 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3964 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3971 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3976 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3977 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3978 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3983 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3984 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3985 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3986 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3989 /* PREFIX_0F73_REG_3 */
3993 { "psrldq", { XS
, Ib
}, 0 },
3996 /* PREFIX_0F73_REG_7 */
4000 { "pslldq", { XS
, Ib
}, 0 },
4005 {"vmread", { Em
, Gm
}, 0 },
4007 {"extrq", { XS
, Ib
, Ib
}, 0 },
4008 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
4013 {"vmwrite", { Gm
, Em
}, 0 },
4015 {"extrq", { XM
, XS
}, 0 },
4016 {"insertq", { XM
, XS
}, 0 },
4023 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
4024 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
4031 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
4032 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
4037 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
4038 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
4039 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
4044 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
4045 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
4046 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
4049 /* PREFIX_0FAE_REG_0 */
4052 { "rdfsbase", { Ev
}, 0 },
4055 /* PREFIX_0FAE_REG_1 */
4058 { "rdgsbase", { Ev
}, 0 },
4061 /* PREFIX_0FAE_REG_2 */
4064 { "wrfsbase", { Ev
}, 0 },
4067 /* PREFIX_0FAE_REG_3 */
4070 { "wrgsbase", { Ev
}, 0 },
4073 /* PREFIX_MOD_0_0FAE_REG_4 */
4075 { "xsave", { FXSAVE
}, 0 },
4076 { "ptwrite%LQ", { Edq
}, 0 },
4079 /* PREFIX_MOD_3_0FAE_REG_4 */
4082 { "ptwrite%LQ", { Edq
}, 0 },
4085 /* PREFIX_0FAE_REG_6 */
4087 { "xsaveopt", { FXSAVE
}, 0 },
4089 { "clwb", { Mb
}, 0 },
4092 /* PREFIX_0FAE_REG_7 */
4094 { "clflush", { Mb
}, 0 },
4096 { "clflushopt", { Mb
}, 0 },
4102 { "popcntS", { Gv
, Ev
}, 0 },
4107 { "bsfS", { Gv
, Ev
}, 0 },
4108 { "tzcntS", { Gv
, Ev
}, 0 },
4109 { "bsfS", { Gv
, Ev
}, 0 },
4114 { "bsrS", { Gv
, Ev
}, 0 },
4115 { "lzcntS", { Gv
, Ev
}, 0 },
4116 { "bsrS", { Gv
, Ev
}, 0 },
4121 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4122 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4123 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4124 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4127 /* PREFIX_MOD_0_0FC3 */
4129 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4132 /* PREFIX_MOD_0_0FC7_REG_6 */
4134 { "vmptrld",{ Mq
}, 0 },
4135 { "vmxon", { Mq
}, 0 },
4136 { "vmclear",{ Mq
}, 0 },
4139 /* PREFIX_MOD_3_0FC7_REG_6 */
4141 { "rdrand", { Ev
}, 0 },
4143 { "rdrand", { Ev
}, 0 }
4146 /* PREFIX_MOD_3_0FC7_REG_7 */
4148 { "rdseed", { Ev
}, 0 },
4149 { "rdpid", { Em
}, 0 },
4150 { "rdseed", { Ev
}, 0 },
4157 { "addsubpd", { XM
, EXx
}, 0 },
4158 { "addsubps", { XM
, EXx
}, 0 },
4164 { "movq2dq",{ XM
, MS
}, 0 },
4165 { "movq", { EXqS
, XM
}, 0 },
4166 { "movdq2q",{ MX
, XS
}, 0 },
4172 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4173 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4174 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4179 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4181 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4189 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4194 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4196 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4203 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4210 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4217 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4224 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4231 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4238 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4245 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4252 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4259 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4266 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4273 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4280 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4287 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4294 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4301 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4308 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4315 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4322 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4329 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4336 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4343 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4350 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4357 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4364 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4371 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4378 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4385 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4392 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4399 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4406 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4413 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4420 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4427 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4434 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4439 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4444 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4449 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4454 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4459 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4464 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4471 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4478 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4485 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4492 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4499 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4504 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4506 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4507 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4512 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4514 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4515 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4521 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4522 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4530 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4537 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4544 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4551 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4558 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4565 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4572 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4579 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4586 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4593 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4600 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4607 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4614 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4621 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4628 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4635 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4642 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4649 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4656 { "pcmpestrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4663 { "pcmpestri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4670 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4677 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4682 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4689 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4692 /* PREFIX_VEX_0F10 */
4694 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4695 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4696 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4697 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4700 /* PREFIX_VEX_0F11 */
4702 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4703 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4704 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4705 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4708 /* PREFIX_VEX_0F12 */
4710 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4711 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4712 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4713 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4716 /* PREFIX_VEX_0F16 */
4718 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4719 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4720 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4723 /* PREFIX_VEX_0F2A */
4726 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4728 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4731 /* PREFIX_VEX_0F2C */
4734 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4736 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4739 /* PREFIX_VEX_0F2D */
4742 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4744 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4747 /* PREFIX_VEX_0F2E */
4749 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4751 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4754 /* PREFIX_VEX_0F2F */
4756 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4758 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4761 /* PREFIX_VEX_0F41 */
4763 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4765 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4768 /* PREFIX_VEX_0F42 */
4770 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4772 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4775 /* PREFIX_VEX_0F44 */
4777 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4779 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4782 /* PREFIX_VEX_0F45 */
4784 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4786 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4789 /* PREFIX_VEX_0F46 */
4791 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4793 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4796 /* PREFIX_VEX_0F47 */
4798 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4800 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4803 /* PREFIX_VEX_0F4A */
4805 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4807 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4810 /* PREFIX_VEX_0F4B */
4812 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4814 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4817 /* PREFIX_VEX_0F51 */
4819 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4820 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4821 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4822 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4825 /* PREFIX_VEX_0F52 */
4827 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4828 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4831 /* PREFIX_VEX_0F53 */
4833 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4834 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4837 /* PREFIX_VEX_0F58 */
4839 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4840 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4841 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4842 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4845 /* PREFIX_VEX_0F59 */
4847 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4848 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4849 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4850 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4853 /* PREFIX_VEX_0F5A */
4855 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4856 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4857 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
4858 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4861 /* PREFIX_VEX_0F5B */
4863 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4864 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4865 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4868 /* PREFIX_VEX_0F5C */
4870 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4871 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4872 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4873 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4876 /* PREFIX_VEX_0F5D */
4878 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4879 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4880 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4881 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4884 /* PREFIX_VEX_0F5E */
4886 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4887 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4888 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4889 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4892 /* PREFIX_VEX_0F5F */
4894 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4895 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4896 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4897 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4900 /* PREFIX_VEX_0F60 */
4904 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4907 /* PREFIX_VEX_0F61 */
4911 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4914 /* PREFIX_VEX_0F62 */
4918 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4921 /* PREFIX_VEX_0F63 */
4925 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4928 /* PREFIX_VEX_0F64 */
4932 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4935 /* PREFIX_VEX_0F65 */
4939 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4942 /* PREFIX_VEX_0F66 */
4946 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4949 /* PREFIX_VEX_0F67 */
4953 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4956 /* PREFIX_VEX_0F68 */
4960 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4963 /* PREFIX_VEX_0F69 */
4967 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4970 /* PREFIX_VEX_0F6A */
4974 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4977 /* PREFIX_VEX_0F6B */
4981 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4984 /* PREFIX_VEX_0F6C */
4988 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4991 /* PREFIX_VEX_0F6D */
4995 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
4998 /* PREFIX_VEX_0F6E */
5002 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
5005 /* PREFIX_VEX_0F6F */
5008 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
5009 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
5012 /* PREFIX_VEX_0F70 */
5015 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
5016 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
5017 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
5020 /* PREFIX_VEX_0F71_REG_2 */
5024 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
5027 /* PREFIX_VEX_0F71_REG_4 */
5031 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
5034 /* PREFIX_VEX_0F71_REG_6 */
5038 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
5041 /* PREFIX_VEX_0F72_REG_2 */
5045 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
5048 /* PREFIX_VEX_0F72_REG_4 */
5052 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
5055 /* PREFIX_VEX_0F72_REG_6 */
5059 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
5062 /* PREFIX_VEX_0F73_REG_2 */
5066 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
5069 /* PREFIX_VEX_0F73_REG_3 */
5073 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
5076 /* PREFIX_VEX_0F73_REG_6 */
5080 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
5083 /* PREFIX_VEX_0F73_REG_7 */
5087 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
5090 /* PREFIX_VEX_0F74 */
5094 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
5097 /* PREFIX_VEX_0F75 */
5101 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5104 /* PREFIX_VEX_0F76 */
5108 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5111 /* PREFIX_VEX_0F77 */
5113 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5116 /* PREFIX_VEX_0F7C */
5120 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5121 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5124 /* PREFIX_VEX_0F7D */
5128 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5129 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5132 /* PREFIX_VEX_0F7E */
5135 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5136 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5139 /* PREFIX_VEX_0F7F */
5142 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5143 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5146 /* PREFIX_VEX_0F90 */
5148 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5150 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5153 /* PREFIX_VEX_0F91 */
5155 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5157 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5160 /* PREFIX_VEX_0F92 */
5162 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5164 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5165 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5168 /* PREFIX_VEX_0F93 */
5170 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5172 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5173 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5176 /* PREFIX_VEX_0F98 */
5178 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5180 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5183 /* PREFIX_VEX_0F99 */
5185 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5187 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5190 /* PREFIX_VEX_0FC2 */
5192 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5193 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5194 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5195 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5198 /* PREFIX_VEX_0FC4 */
5202 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5205 /* PREFIX_VEX_0FC5 */
5209 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5212 /* PREFIX_VEX_0FD0 */
5216 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5217 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5220 /* PREFIX_VEX_0FD1 */
5224 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5227 /* PREFIX_VEX_0FD2 */
5231 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5234 /* PREFIX_VEX_0FD3 */
5238 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5241 /* PREFIX_VEX_0FD4 */
5245 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5248 /* PREFIX_VEX_0FD5 */
5252 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5255 /* PREFIX_VEX_0FD6 */
5259 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5262 /* PREFIX_VEX_0FD7 */
5266 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5269 /* PREFIX_VEX_0FD8 */
5273 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5276 /* PREFIX_VEX_0FD9 */
5280 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5283 /* PREFIX_VEX_0FDA */
5287 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5290 /* PREFIX_VEX_0FDB */
5294 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5297 /* PREFIX_VEX_0FDC */
5301 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5304 /* PREFIX_VEX_0FDD */
5308 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5311 /* PREFIX_VEX_0FDE */
5315 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5318 /* PREFIX_VEX_0FDF */
5322 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5325 /* PREFIX_VEX_0FE0 */
5329 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5332 /* PREFIX_VEX_0FE1 */
5336 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5339 /* PREFIX_VEX_0FE2 */
5343 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5346 /* PREFIX_VEX_0FE3 */
5350 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5353 /* PREFIX_VEX_0FE4 */
5357 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5360 /* PREFIX_VEX_0FE5 */
5364 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5367 /* PREFIX_VEX_0FE6 */
5370 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5371 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5372 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5375 /* PREFIX_VEX_0FE7 */
5379 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5382 /* PREFIX_VEX_0FE8 */
5386 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5389 /* PREFIX_VEX_0FE9 */
5393 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5396 /* PREFIX_VEX_0FEA */
5400 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5403 /* PREFIX_VEX_0FEB */
5407 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5410 /* PREFIX_VEX_0FEC */
5414 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5417 /* PREFIX_VEX_0FED */
5421 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5424 /* PREFIX_VEX_0FEE */
5428 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5431 /* PREFIX_VEX_0FEF */
5435 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5438 /* PREFIX_VEX_0FF0 */
5443 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5446 /* PREFIX_VEX_0FF1 */
5450 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5453 /* PREFIX_VEX_0FF2 */
5457 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5460 /* PREFIX_VEX_0FF3 */
5464 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5467 /* PREFIX_VEX_0FF4 */
5471 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5474 /* PREFIX_VEX_0FF5 */
5478 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5481 /* PREFIX_VEX_0FF6 */
5485 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5488 /* PREFIX_VEX_0FF7 */
5492 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5495 /* PREFIX_VEX_0FF8 */
5499 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5502 /* PREFIX_VEX_0FF9 */
5506 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5509 /* PREFIX_VEX_0FFA */
5513 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5516 /* PREFIX_VEX_0FFB */
5520 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5523 /* PREFIX_VEX_0FFC */
5527 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5530 /* PREFIX_VEX_0FFD */
5534 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5537 /* PREFIX_VEX_0FFE */
5541 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5544 /* PREFIX_VEX_0F3800 */
5548 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5551 /* PREFIX_VEX_0F3801 */
5555 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5558 /* PREFIX_VEX_0F3802 */
5562 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5565 /* PREFIX_VEX_0F3803 */
5569 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5572 /* PREFIX_VEX_0F3804 */
5576 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5579 /* PREFIX_VEX_0F3805 */
5583 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5586 /* PREFIX_VEX_0F3806 */
5590 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5593 /* PREFIX_VEX_0F3807 */
5597 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5600 /* PREFIX_VEX_0F3808 */
5604 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5607 /* PREFIX_VEX_0F3809 */
5611 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5614 /* PREFIX_VEX_0F380A */
5618 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5621 /* PREFIX_VEX_0F380B */
5625 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5628 /* PREFIX_VEX_0F380C */
5632 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5635 /* PREFIX_VEX_0F380D */
5639 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5642 /* PREFIX_VEX_0F380E */
5646 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5649 /* PREFIX_VEX_0F380F */
5653 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5656 /* PREFIX_VEX_0F3813 */
5660 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5663 /* PREFIX_VEX_0F3816 */
5667 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5670 /* PREFIX_VEX_0F3817 */
5674 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5677 /* PREFIX_VEX_0F3818 */
5681 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5684 /* PREFIX_VEX_0F3819 */
5688 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5691 /* PREFIX_VEX_0F381A */
5695 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5698 /* PREFIX_VEX_0F381C */
5702 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5705 /* PREFIX_VEX_0F381D */
5709 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5712 /* PREFIX_VEX_0F381E */
5716 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5719 /* PREFIX_VEX_0F3820 */
5723 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5726 /* PREFIX_VEX_0F3821 */
5730 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5733 /* PREFIX_VEX_0F3822 */
5737 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5740 /* PREFIX_VEX_0F3823 */
5744 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5747 /* PREFIX_VEX_0F3824 */
5751 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5754 /* PREFIX_VEX_0F3825 */
5758 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5761 /* PREFIX_VEX_0F3828 */
5765 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5768 /* PREFIX_VEX_0F3829 */
5772 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5775 /* PREFIX_VEX_0F382A */
5779 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5782 /* PREFIX_VEX_0F382B */
5786 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5789 /* PREFIX_VEX_0F382C */
5793 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5796 /* PREFIX_VEX_0F382D */
5800 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5803 /* PREFIX_VEX_0F382E */
5807 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5810 /* PREFIX_VEX_0F382F */
5814 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5817 /* PREFIX_VEX_0F3830 */
5821 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5824 /* PREFIX_VEX_0F3831 */
5828 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5831 /* PREFIX_VEX_0F3832 */
5835 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5838 /* PREFIX_VEX_0F3833 */
5842 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5845 /* PREFIX_VEX_0F3834 */
5849 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5852 /* PREFIX_VEX_0F3835 */
5856 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5859 /* PREFIX_VEX_0F3836 */
5863 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5866 /* PREFIX_VEX_0F3837 */
5870 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5873 /* PREFIX_VEX_0F3838 */
5877 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5880 /* PREFIX_VEX_0F3839 */
5884 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5887 /* PREFIX_VEX_0F383A */
5891 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5894 /* PREFIX_VEX_0F383B */
5898 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5901 /* PREFIX_VEX_0F383C */
5905 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5908 /* PREFIX_VEX_0F383D */
5912 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5915 /* PREFIX_VEX_0F383E */
5919 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5922 /* PREFIX_VEX_0F383F */
5926 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5929 /* PREFIX_VEX_0F3840 */
5933 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5936 /* PREFIX_VEX_0F3841 */
5940 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5943 /* PREFIX_VEX_0F3845 */
5947 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5950 /* PREFIX_VEX_0F3846 */
5954 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5957 /* PREFIX_VEX_0F3847 */
5961 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5964 /* PREFIX_VEX_0F3858 */
5968 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5971 /* PREFIX_VEX_0F3859 */
5975 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5978 /* PREFIX_VEX_0F385A */
5982 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5985 /* PREFIX_VEX_0F3878 */
5989 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5992 /* PREFIX_VEX_0F3879 */
5996 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5999 /* PREFIX_VEX_0F388C */
6003 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
6006 /* PREFIX_VEX_0F388E */
6010 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
6013 /* PREFIX_VEX_0F3890 */
6017 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6020 /* PREFIX_VEX_0F3891 */
6024 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6027 /* PREFIX_VEX_0F3892 */
6031 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6034 /* PREFIX_VEX_0F3893 */
6038 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6041 /* PREFIX_VEX_0F3896 */
6045 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6048 /* PREFIX_VEX_0F3897 */
6052 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6055 /* PREFIX_VEX_0F3898 */
6059 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6062 /* PREFIX_VEX_0F3899 */
6066 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6069 /* PREFIX_VEX_0F389A */
6073 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6076 /* PREFIX_VEX_0F389B */
6080 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6083 /* PREFIX_VEX_0F389C */
6087 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6090 /* PREFIX_VEX_0F389D */
6094 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6097 /* PREFIX_VEX_0F389E */
6101 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6104 /* PREFIX_VEX_0F389F */
6108 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6111 /* PREFIX_VEX_0F38A6 */
6115 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6119 /* PREFIX_VEX_0F38A7 */
6123 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6126 /* PREFIX_VEX_0F38A8 */
6130 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6133 /* PREFIX_VEX_0F38A9 */
6137 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6140 /* PREFIX_VEX_0F38AA */
6144 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6147 /* PREFIX_VEX_0F38AB */
6151 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6154 /* PREFIX_VEX_0F38AC */
6158 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6161 /* PREFIX_VEX_0F38AD */
6165 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6168 /* PREFIX_VEX_0F38AE */
6172 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6175 /* PREFIX_VEX_0F38AF */
6179 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6182 /* PREFIX_VEX_0F38B6 */
6186 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6189 /* PREFIX_VEX_0F38B7 */
6193 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6196 /* PREFIX_VEX_0F38B8 */
6200 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6203 /* PREFIX_VEX_0F38B9 */
6207 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6210 /* PREFIX_VEX_0F38BA */
6214 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6217 /* PREFIX_VEX_0F38BB */
6221 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6224 /* PREFIX_VEX_0F38BC */
6228 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6231 /* PREFIX_VEX_0F38BD */
6235 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6238 /* PREFIX_VEX_0F38BE */
6242 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6245 /* PREFIX_VEX_0F38BF */
6249 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6252 /* PREFIX_VEX_0F38DB */
6256 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6259 /* PREFIX_VEX_0F38DC */
6263 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
6266 /* PREFIX_VEX_0F38DD */
6270 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
6273 /* PREFIX_VEX_0F38DE */
6277 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
6280 /* PREFIX_VEX_0F38DF */
6284 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
6287 /* PREFIX_VEX_0F38F2 */
6289 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6292 /* PREFIX_VEX_0F38F3_REG_1 */
6294 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6297 /* PREFIX_VEX_0F38F3_REG_2 */
6299 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6302 /* PREFIX_VEX_0F38F3_REG_3 */
6304 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6307 /* PREFIX_VEX_0F38F5 */
6309 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6310 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6312 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6315 /* PREFIX_VEX_0F38F6 */
6320 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6323 /* PREFIX_VEX_0F38F7 */
6325 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6326 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6327 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6328 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6331 /* PREFIX_VEX_0F3A00 */
6335 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6338 /* PREFIX_VEX_0F3A01 */
6342 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6345 /* PREFIX_VEX_0F3A02 */
6349 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6352 /* PREFIX_VEX_0F3A04 */
6356 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6359 /* PREFIX_VEX_0F3A05 */
6363 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6366 /* PREFIX_VEX_0F3A06 */
6370 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6373 /* PREFIX_VEX_0F3A08 */
6377 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6380 /* PREFIX_VEX_0F3A09 */
6384 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6387 /* PREFIX_VEX_0F3A0A */
6391 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6394 /* PREFIX_VEX_0F3A0B */
6398 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6401 /* PREFIX_VEX_0F3A0C */
6405 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6408 /* PREFIX_VEX_0F3A0D */
6412 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6415 /* PREFIX_VEX_0F3A0E */
6419 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6422 /* PREFIX_VEX_0F3A0F */
6426 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6429 /* PREFIX_VEX_0F3A14 */
6433 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6436 /* PREFIX_VEX_0F3A15 */
6440 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6443 /* PREFIX_VEX_0F3A16 */
6447 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6450 /* PREFIX_VEX_0F3A17 */
6454 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6457 /* PREFIX_VEX_0F3A18 */
6461 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6464 /* PREFIX_VEX_0F3A19 */
6468 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6471 /* PREFIX_VEX_0F3A1D */
6475 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6478 /* PREFIX_VEX_0F3A20 */
6482 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6485 /* PREFIX_VEX_0F3A21 */
6489 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6492 /* PREFIX_VEX_0F3A22 */
6496 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6499 /* PREFIX_VEX_0F3A30 */
6503 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6506 /* PREFIX_VEX_0F3A31 */
6510 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6513 /* PREFIX_VEX_0F3A32 */
6517 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6520 /* PREFIX_VEX_0F3A33 */
6524 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6527 /* PREFIX_VEX_0F3A38 */
6531 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6534 /* PREFIX_VEX_0F3A39 */
6538 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6541 /* PREFIX_VEX_0F3A40 */
6545 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6548 /* PREFIX_VEX_0F3A41 */
6552 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6555 /* PREFIX_VEX_0F3A42 */
6559 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6562 /* PREFIX_VEX_0F3A44 */
6566 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6569 /* PREFIX_VEX_0F3A46 */
6573 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6576 /* PREFIX_VEX_0F3A48 */
6580 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6583 /* PREFIX_VEX_0F3A49 */
6587 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6590 /* PREFIX_VEX_0F3A4A */
6594 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6597 /* PREFIX_VEX_0F3A4B */
6601 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6604 /* PREFIX_VEX_0F3A4C */
6608 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6611 /* PREFIX_VEX_0F3A5C */
6615 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6618 /* PREFIX_VEX_0F3A5D */
6622 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6625 /* PREFIX_VEX_0F3A5E */
6629 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6632 /* PREFIX_VEX_0F3A5F */
6636 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6639 /* PREFIX_VEX_0F3A60 */
6643 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6647 /* PREFIX_VEX_0F3A61 */
6651 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6654 /* PREFIX_VEX_0F3A62 */
6658 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6661 /* PREFIX_VEX_0F3A63 */
6665 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6668 /* PREFIX_VEX_0F3A68 */
6672 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6675 /* PREFIX_VEX_0F3A69 */
6679 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6682 /* PREFIX_VEX_0F3A6A */
6686 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6689 /* PREFIX_VEX_0F3A6B */
6693 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6696 /* PREFIX_VEX_0F3A6C */
6700 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6703 /* PREFIX_VEX_0F3A6D */
6707 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6710 /* PREFIX_VEX_0F3A6E */
6714 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6717 /* PREFIX_VEX_0F3A6F */
6721 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6724 /* PREFIX_VEX_0F3A78 */
6728 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6731 /* PREFIX_VEX_0F3A79 */
6735 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6738 /* PREFIX_VEX_0F3A7A */
6742 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6745 /* PREFIX_VEX_0F3A7B */
6749 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6752 /* PREFIX_VEX_0F3A7C */
6756 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6760 /* PREFIX_VEX_0F3A7D */
6764 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6767 /* PREFIX_VEX_0F3A7E */
6771 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6774 /* PREFIX_VEX_0F3A7F */
6778 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6781 /* PREFIX_VEX_0F3ADF */
6785 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6788 /* PREFIX_VEX_0F3AF0 */
6793 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6796 #define NEED_PREFIX_TABLE
6797 #include "i386-dis-evex.h"
6798 #undef NEED_PREFIX_TABLE
6801 static const struct dis386 x86_64_table
[][2] = {
6804 { "pushP", { es
}, 0 },
6809 { "popP", { es
}, 0 },
6814 { "pushP", { cs
}, 0 },
6819 { "pushP", { ss
}, 0 },
6824 { "popP", { ss
}, 0 },
6829 { "pushP", { ds
}, 0 },
6834 { "popP", { ds
}, 0 },
6839 { "daa", { XX
}, 0 },
6844 { "das", { XX
}, 0 },
6849 { "aaa", { XX
}, 0 },
6854 { "aas", { XX
}, 0 },
6859 { "pushaP", { XX
}, 0 },
6864 { "popaP", { XX
}, 0 },
6869 { MOD_TABLE (MOD_62_32BIT
) },
6870 { EVEX_TABLE (EVEX_0F
) },
6875 { "arpl", { Ew
, Gw
}, 0 },
6876 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6881 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6882 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6887 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6888 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6893 /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode. */
6894 { REG_TABLE (REG_80
) },
6899 { "Jcall{T|}", { Ap
}, 0 },
6904 { MOD_TABLE (MOD_C4_32BIT
) },
6905 { VEX_C4_TABLE (VEX_0F
) },
6910 { MOD_TABLE (MOD_C5_32BIT
) },
6911 { VEX_C5_TABLE (VEX_0F
) },
6916 { "into", { XX
}, 0 },
6921 { "aam", { Ib
}, 0 },
6926 { "aad", { Ib
}, 0 },
6931 { "callP", { Jv
, BND
}, 0 },
6932 { "call@", { Jv
, BND
}, 0 }
6937 { "jmpP", { Jv
, BND
}, 0 },
6938 { "jmp@", { Jv
, BND
}, 0 }
6943 { "Jjmp{T|}", { Ap
}, 0 },
6946 /* X86_64_0F01_REG_0 */
6948 { "sgdt{Q|IQ}", { M
}, 0 },
6949 { "sgdt", { M
}, 0 },
6952 /* X86_64_0F01_REG_1 */
6954 { "sidt{Q|IQ}", { M
}, 0 },
6955 { "sidt", { M
}, 0 },
6958 /* X86_64_0F01_REG_2 */
6960 { "lgdt{Q|Q}", { M
}, 0 },
6961 { "lgdt", { M
}, 0 },
6964 /* X86_64_0F01_REG_3 */
6966 { "lidt{Q|Q}", { M
}, 0 },
6967 { "lidt", { M
}, 0 },
6971 static const struct dis386 three_byte_table
[][256] = {
6973 /* THREE_BYTE_0F38 */
6976 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6977 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6978 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6979 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6980 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6981 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6982 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6983 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6985 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6986 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6987 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6988 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6994 { PREFIX_TABLE (PREFIX_0F3810
) },
6998 { PREFIX_TABLE (PREFIX_0F3814
) },
6999 { PREFIX_TABLE (PREFIX_0F3815
) },
7001 { PREFIX_TABLE (PREFIX_0F3817
) },
7007 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7008 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7009 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7012 { PREFIX_TABLE (PREFIX_0F3820
) },
7013 { PREFIX_TABLE (PREFIX_0F3821
) },
7014 { PREFIX_TABLE (PREFIX_0F3822
) },
7015 { PREFIX_TABLE (PREFIX_0F3823
) },
7016 { PREFIX_TABLE (PREFIX_0F3824
) },
7017 { PREFIX_TABLE (PREFIX_0F3825
) },
7021 { PREFIX_TABLE (PREFIX_0F3828
) },
7022 { PREFIX_TABLE (PREFIX_0F3829
) },
7023 { PREFIX_TABLE (PREFIX_0F382A
) },
7024 { PREFIX_TABLE (PREFIX_0F382B
) },
7030 { PREFIX_TABLE (PREFIX_0F3830
) },
7031 { PREFIX_TABLE (PREFIX_0F3831
) },
7032 { PREFIX_TABLE (PREFIX_0F3832
) },
7033 { PREFIX_TABLE (PREFIX_0F3833
) },
7034 { PREFIX_TABLE (PREFIX_0F3834
) },
7035 { PREFIX_TABLE (PREFIX_0F3835
) },
7037 { PREFIX_TABLE (PREFIX_0F3837
) },
7039 { PREFIX_TABLE (PREFIX_0F3838
) },
7040 { PREFIX_TABLE (PREFIX_0F3839
) },
7041 { PREFIX_TABLE (PREFIX_0F383A
) },
7042 { PREFIX_TABLE (PREFIX_0F383B
) },
7043 { PREFIX_TABLE (PREFIX_0F383C
) },
7044 { PREFIX_TABLE (PREFIX_0F383D
) },
7045 { PREFIX_TABLE (PREFIX_0F383E
) },
7046 { PREFIX_TABLE (PREFIX_0F383F
) },
7048 { PREFIX_TABLE (PREFIX_0F3840
) },
7049 { PREFIX_TABLE (PREFIX_0F3841
) },
7120 { PREFIX_TABLE (PREFIX_0F3880
) },
7121 { PREFIX_TABLE (PREFIX_0F3881
) },
7122 { PREFIX_TABLE (PREFIX_0F3882
) },
7201 { PREFIX_TABLE (PREFIX_0F38C8
) },
7202 { PREFIX_TABLE (PREFIX_0F38C9
) },
7203 { PREFIX_TABLE (PREFIX_0F38CA
) },
7204 { PREFIX_TABLE (PREFIX_0F38CB
) },
7205 { PREFIX_TABLE (PREFIX_0F38CC
) },
7206 { PREFIX_TABLE (PREFIX_0F38CD
) },
7222 { PREFIX_TABLE (PREFIX_0F38DB
) },
7223 { PREFIX_TABLE (PREFIX_0F38DC
) },
7224 { PREFIX_TABLE (PREFIX_0F38DD
) },
7225 { PREFIX_TABLE (PREFIX_0F38DE
) },
7226 { PREFIX_TABLE (PREFIX_0F38DF
) },
7246 { PREFIX_TABLE (PREFIX_0F38F0
) },
7247 { PREFIX_TABLE (PREFIX_0F38F1
) },
7252 { PREFIX_TABLE (PREFIX_0F38F6
) },
7264 /* THREE_BYTE_0F3A */
7276 { PREFIX_TABLE (PREFIX_0F3A08
) },
7277 { PREFIX_TABLE (PREFIX_0F3A09
) },
7278 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7279 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7280 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7281 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7282 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7283 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7289 { PREFIX_TABLE (PREFIX_0F3A14
) },
7290 { PREFIX_TABLE (PREFIX_0F3A15
) },
7291 { PREFIX_TABLE (PREFIX_0F3A16
) },
7292 { PREFIX_TABLE (PREFIX_0F3A17
) },
7303 { PREFIX_TABLE (PREFIX_0F3A20
) },
7304 { PREFIX_TABLE (PREFIX_0F3A21
) },
7305 { PREFIX_TABLE (PREFIX_0F3A22
) },
7339 { PREFIX_TABLE (PREFIX_0F3A40
) },
7340 { PREFIX_TABLE (PREFIX_0F3A41
) },
7341 { PREFIX_TABLE (PREFIX_0F3A42
) },
7343 { PREFIX_TABLE (PREFIX_0F3A44
) },
7375 { PREFIX_TABLE (PREFIX_0F3A60
) },
7376 { PREFIX_TABLE (PREFIX_0F3A61
) },
7377 { PREFIX_TABLE (PREFIX_0F3A62
) },
7378 { PREFIX_TABLE (PREFIX_0F3A63
) },
7496 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7517 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7556 /* THREE_BYTE_0F7A */
7632 { "phaddbw", { XM
, EXq
}, PREFIX_OPCODE
},
7633 { "phaddbd", { XM
, EXq
}, PREFIX_OPCODE
},
7634 { "phaddbq", { XM
, EXq
}, PREFIX_OPCODE
},
7637 { "phaddwd", { XM
, EXq
}, PREFIX_OPCODE
},
7638 { "phaddwq", { XM
, EXq
}, PREFIX_OPCODE
},
7643 { "phadddq", { XM
, EXq
}, PREFIX_OPCODE
},
7650 { "phaddubw", { XM
, EXq
}, PREFIX_OPCODE
},
7651 { "phaddubd", { XM
, EXq
}, PREFIX_OPCODE
},
7652 { "phaddubq", { XM
, EXq
}, PREFIX_OPCODE
},
7655 { "phadduwd", { XM
, EXq
}, PREFIX_OPCODE
},
7656 { "phadduwq", { XM
, EXq
}, PREFIX_OPCODE
},
7661 { "phaddudq", { XM
, EXq
}, PREFIX_OPCODE
},
7668 { "phsubbw", { XM
, EXq
}, PREFIX_OPCODE
},
7669 { "phsubbd", { XM
, EXq
}, PREFIX_OPCODE
},
7670 { "phsubbq", { XM
, EXq
}, PREFIX_OPCODE
},
7849 static const struct dis386 xop_table
[][256] = {
8002 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8003 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8004 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8012 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8013 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8020 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8021 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8022 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8030 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8031 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8035 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8036 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8039 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8057 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8069 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
8070 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
8071 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
8072 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
8082 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
8083 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
8084 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
8085 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
8118 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
8119 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
8120 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
8121 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8145 { REG_TABLE (REG_XOP_TBM_01
) },
8146 { REG_TABLE (REG_XOP_TBM_02
) },
8164 { REG_TABLE (REG_XOP_LWPCB
) },
8288 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8289 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8290 { "vfrczss", { XM
, EXd
}, 0 },
8291 { "vfrczsd", { XM
, EXq
}, 0 },
8306 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8307 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8308 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8309 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8310 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8311 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8312 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8313 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8315 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8316 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8317 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8318 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8361 { "vphaddbw", { XM
, EXxmm
}, 0 },
8362 { "vphaddbd", { XM
, EXxmm
}, 0 },
8363 { "vphaddbq", { XM
, EXxmm
}, 0 },
8366 { "vphaddwd", { XM
, EXxmm
}, 0 },
8367 { "vphaddwq", { XM
, EXxmm
}, 0 },
8372 { "vphadddq", { XM
, EXxmm
}, 0 },
8379 { "vphaddubw", { XM
, EXxmm
}, 0 },
8380 { "vphaddubd", { XM
, EXxmm
}, 0 },
8381 { "vphaddubq", { XM
, EXxmm
}, 0 },
8384 { "vphadduwd", { XM
, EXxmm
}, 0 },
8385 { "vphadduwq", { XM
, EXxmm
}, 0 },
8390 { "vphaddudq", { XM
, EXxmm
}, 0 },
8397 { "vphsubbw", { XM
, EXxmm
}, 0 },
8398 { "vphsubwd", { XM
, EXxmm
}, 0 },
8399 { "vphsubdq", { XM
, EXxmm
}, 0 },
8453 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8455 { REG_TABLE (REG_XOP_LWP
) },
8725 static const struct dis386 vex_table
[][256] = {
8747 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8750 { MOD_TABLE (MOD_VEX_0F13
) },
8751 { VEX_W_TABLE (VEX_W_0F14
) },
8752 { VEX_W_TABLE (VEX_W_0F15
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8754 { MOD_TABLE (MOD_VEX_0F17
) },
8774 { VEX_W_TABLE (VEX_W_0F28
) },
8775 { VEX_W_TABLE (VEX_W_0F29
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8777 { MOD_TABLE (MOD_VEX_0F2B
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8819 { MOD_TABLE (MOD_VEX_0F50
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8823 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8824 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8825 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8826 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8828 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8832 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8833 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8834 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8835 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8837 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8838 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8840 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8841 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8842 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8843 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8844 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8849 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8851 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8852 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8853 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8855 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8856 { REG_TABLE (REG_VEX_0F71
) },
8857 { REG_TABLE (REG_VEX_0F72
) },
8858 { REG_TABLE (REG_VEX_0F73
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8924 { REG_TABLE (REG_VEX_0FAE
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8951 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8963 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8981 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8982 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8985 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
9008 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9179 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9182 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9185 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9193 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9197 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9198 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9206 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9207 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9209 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9210 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9211 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9212 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9213 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9214 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9215 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9216 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9224 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9225 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9227 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9228 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9229 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9230 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9231 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9232 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9233 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9234 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9266 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9267 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9268 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9269 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9270 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9292 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9293 { REG_TABLE (REG_VEX_0F38F3
) },
9295 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9296 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9297 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9317 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9320 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9321 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9322 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9323 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9324 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9325 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9326 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9327 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9333 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9334 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9335 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9336 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9338 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9339 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9343 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9347 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9348 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9349 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9365 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9366 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9367 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9368 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9374 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9375 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9383 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9384 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9385 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9387 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9389 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9392 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9393 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9394 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9395 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9396 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9414 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9415 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9416 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9417 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9419 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9420 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9421 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9422 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9428 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9429 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9430 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9431 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9432 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9433 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9434 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9435 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9446 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9447 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9448 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9449 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9450 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9451 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9452 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9453 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9561 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9581 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9601 #define NEED_OPCODE_TABLE
9602 #include "i386-dis-evex.h"
9603 #undef NEED_OPCODE_TABLE
9604 static const struct dis386 vex_len_table
[][2] = {
9605 /* VEX_LEN_0F10_P_1 */
9607 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9608 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9611 /* VEX_LEN_0F10_P_3 */
9613 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9614 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9617 /* VEX_LEN_0F11_P_1 */
9619 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9620 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9623 /* VEX_LEN_0F11_P_3 */
9625 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9626 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9629 /* VEX_LEN_0F12_P_0_M_0 */
9631 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9634 /* VEX_LEN_0F12_P_0_M_1 */
9636 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9639 /* VEX_LEN_0F12_P_2 */
9641 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9644 /* VEX_LEN_0F13_M_0 */
9646 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9649 /* VEX_LEN_0F16_P_0_M_0 */
9651 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9654 /* VEX_LEN_0F16_P_0_M_1 */
9656 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9659 /* VEX_LEN_0F16_P_2 */
9661 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9664 /* VEX_LEN_0F17_M_0 */
9666 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9669 /* VEX_LEN_0F2A_P_1 */
9671 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9672 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9675 /* VEX_LEN_0F2A_P_3 */
9677 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9678 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9681 /* VEX_LEN_0F2C_P_1 */
9683 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9684 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9687 /* VEX_LEN_0F2C_P_3 */
9689 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9690 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9693 /* VEX_LEN_0F2D_P_1 */
9695 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9696 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9699 /* VEX_LEN_0F2D_P_3 */
9701 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9702 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9705 /* VEX_LEN_0F2E_P_0 */
9707 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9708 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9711 /* VEX_LEN_0F2E_P_2 */
9713 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9714 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9717 /* VEX_LEN_0F2F_P_0 */
9719 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9720 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9723 /* VEX_LEN_0F2F_P_2 */
9725 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9726 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9729 /* VEX_LEN_0F41_P_0 */
9732 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9734 /* VEX_LEN_0F41_P_2 */
9737 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9739 /* VEX_LEN_0F42_P_0 */
9742 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9744 /* VEX_LEN_0F42_P_2 */
9747 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9749 /* VEX_LEN_0F44_P_0 */
9751 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9753 /* VEX_LEN_0F44_P_2 */
9755 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9757 /* VEX_LEN_0F45_P_0 */
9760 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9762 /* VEX_LEN_0F45_P_2 */
9765 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9767 /* VEX_LEN_0F46_P_0 */
9770 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9772 /* VEX_LEN_0F46_P_2 */
9775 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9777 /* VEX_LEN_0F47_P_0 */
9780 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9782 /* VEX_LEN_0F47_P_2 */
9785 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9787 /* VEX_LEN_0F4A_P_0 */
9790 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9792 /* VEX_LEN_0F4A_P_2 */
9795 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9797 /* VEX_LEN_0F4B_P_0 */
9800 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9802 /* VEX_LEN_0F4B_P_2 */
9805 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9808 /* VEX_LEN_0F51_P_1 */
9810 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9811 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9814 /* VEX_LEN_0F51_P_3 */
9816 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9817 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9820 /* VEX_LEN_0F52_P_1 */
9822 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9823 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9826 /* VEX_LEN_0F53_P_1 */
9828 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9829 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9832 /* VEX_LEN_0F58_P_1 */
9834 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9835 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9838 /* VEX_LEN_0F58_P_3 */
9840 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9841 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9844 /* VEX_LEN_0F59_P_1 */
9846 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9847 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9850 /* VEX_LEN_0F59_P_3 */
9852 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9853 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9856 /* VEX_LEN_0F5A_P_1 */
9858 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9859 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9862 /* VEX_LEN_0F5A_P_3 */
9864 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9865 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9868 /* VEX_LEN_0F5C_P_1 */
9870 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9871 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9874 /* VEX_LEN_0F5C_P_3 */
9876 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9877 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9880 /* VEX_LEN_0F5D_P_1 */
9882 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9883 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9886 /* VEX_LEN_0F5D_P_3 */
9888 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9889 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9892 /* VEX_LEN_0F5E_P_1 */
9894 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9895 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9898 /* VEX_LEN_0F5E_P_3 */
9900 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9901 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9904 /* VEX_LEN_0F5F_P_1 */
9906 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9907 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9910 /* VEX_LEN_0F5F_P_3 */
9912 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9913 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9916 /* VEX_LEN_0F6E_P_2 */
9918 { "vmovK", { XMScalar
, Edq
}, 0 },
9919 { "vmovK", { XMScalar
, Edq
}, 0 },
9922 /* VEX_LEN_0F7E_P_1 */
9924 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9925 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9928 /* VEX_LEN_0F7E_P_2 */
9930 { "vmovK", { Edq
, XMScalar
}, 0 },
9931 { "vmovK", { Edq
, XMScalar
}, 0 },
9934 /* VEX_LEN_0F90_P_0 */
9936 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9939 /* VEX_LEN_0F90_P_2 */
9941 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9944 /* VEX_LEN_0F91_P_0 */
9946 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9949 /* VEX_LEN_0F91_P_2 */
9951 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9954 /* VEX_LEN_0F92_P_0 */
9956 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9959 /* VEX_LEN_0F92_P_2 */
9961 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9964 /* VEX_LEN_0F92_P_3 */
9966 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9969 /* VEX_LEN_0F93_P_0 */
9971 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9974 /* VEX_LEN_0F93_P_2 */
9976 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9979 /* VEX_LEN_0F93_P_3 */
9981 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9984 /* VEX_LEN_0F98_P_0 */
9986 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9989 /* VEX_LEN_0F98_P_2 */
9991 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9994 /* VEX_LEN_0F99_P_0 */
9996 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9999 /* VEX_LEN_0F99_P_2 */
10001 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
10004 /* VEX_LEN_0FAE_R_2_M_0 */
10006 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
10009 /* VEX_LEN_0FAE_R_3_M_0 */
10011 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
10014 /* VEX_LEN_0FC2_P_1 */
10016 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
10017 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
10020 /* VEX_LEN_0FC2_P_3 */
10022 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
10023 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
10026 /* VEX_LEN_0FC4_P_2 */
10028 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
10031 /* VEX_LEN_0FC5_P_2 */
10033 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
10036 /* VEX_LEN_0FD6_P_2 */
10038 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
10039 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
10042 /* VEX_LEN_0FF7_P_2 */
10044 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
10047 /* VEX_LEN_0F3816_P_2 */
10050 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
10053 /* VEX_LEN_0F3819_P_2 */
10056 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
10059 /* VEX_LEN_0F381A_P_2_M_0 */
10062 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
10065 /* VEX_LEN_0F3836_P_2 */
10068 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
10071 /* VEX_LEN_0F3841_P_2 */
10073 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
10076 /* VEX_LEN_0F385A_P_2_M_0 */
10079 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
10082 /* VEX_LEN_0F38DB_P_2 */
10084 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
10087 /* VEX_LEN_0F38DC_P_2 */
10089 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
10092 /* VEX_LEN_0F38DD_P_2 */
10094 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
10097 /* VEX_LEN_0F38DE_P_2 */
10099 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
10102 /* VEX_LEN_0F38DF_P_2 */
10104 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
10107 /* VEX_LEN_0F38F2_P_0 */
10109 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
10112 /* VEX_LEN_0F38F3_R_1_P_0 */
10114 { "blsrS", { VexGdq
, Edq
}, 0 },
10117 /* VEX_LEN_0F38F3_R_2_P_0 */
10119 { "blsmskS", { VexGdq
, Edq
}, 0 },
10122 /* VEX_LEN_0F38F3_R_3_P_0 */
10124 { "blsiS", { VexGdq
, Edq
}, 0 },
10127 /* VEX_LEN_0F38F5_P_0 */
10129 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
10132 /* VEX_LEN_0F38F5_P_1 */
10134 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
10137 /* VEX_LEN_0F38F5_P_3 */
10139 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
10142 /* VEX_LEN_0F38F6_P_3 */
10144 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
10147 /* VEX_LEN_0F38F7_P_0 */
10149 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
10152 /* VEX_LEN_0F38F7_P_1 */
10154 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
10157 /* VEX_LEN_0F38F7_P_2 */
10159 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
10162 /* VEX_LEN_0F38F7_P_3 */
10164 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
10167 /* VEX_LEN_0F3A00_P_2 */
10170 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10173 /* VEX_LEN_0F3A01_P_2 */
10176 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10179 /* VEX_LEN_0F3A06_P_2 */
10182 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10185 /* VEX_LEN_0F3A0A_P_2 */
10187 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10188 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10191 /* VEX_LEN_0F3A0B_P_2 */
10193 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10194 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10197 /* VEX_LEN_0F3A14_P_2 */
10199 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10202 /* VEX_LEN_0F3A15_P_2 */
10204 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10207 /* VEX_LEN_0F3A16_P_2 */
10209 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
10212 /* VEX_LEN_0F3A17_P_2 */
10214 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
10217 /* VEX_LEN_0F3A18_P_2 */
10220 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10223 /* VEX_LEN_0F3A19_P_2 */
10226 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10229 /* VEX_LEN_0F3A20_P_2 */
10231 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10234 /* VEX_LEN_0F3A21_P_2 */
10236 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10239 /* VEX_LEN_0F3A22_P_2 */
10241 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
10244 /* VEX_LEN_0F3A30_P_2 */
10246 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10249 /* VEX_LEN_0F3A31_P_2 */
10251 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10254 /* VEX_LEN_0F3A32_P_2 */
10256 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10259 /* VEX_LEN_0F3A33_P_2 */
10261 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10264 /* VEX_LEN_0F3A38_P_2 */
10267 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10270 /* VEX_LEN_0F3A39_P_2 */
10273 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10276 /* VEX_LEN_0F3A41_P_2 */
10278 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10281 /* VEX_LEN_0F3A44_P_2 */
10283 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
10286 /* VEX_LEN_0F3A46_P_2 */
10289 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10292 /* VEX_LEN_0F3A60_P_2 */
10294 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
10297 /* VEX_LEN_0F3A61_P_2 */
10299 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
10302 /* VEX_LEN_0F3A62_P_2 */
10304 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10307 /* VEX_LEN_0F3A63_P_2 */
10309 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10312 /* VEX_LEN_0F3A6A_P_2 */
10314 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10317 /* VEX_LEN_0F3A6B_P_2 */
10319 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10322 /* VEX_LEN_0F3A6E_P_2 */
10324 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10327 /* VEX_LEN_0F3A6F_P_2 */
10329 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10332 /* VEX_LEN_0F3A7A_P_2 */
10334 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10337 /* VEX_LEN_0F3A7B_P_2 */
10339 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10342 /* VEX_LEN_0F3A7E_P_2 */
10344 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10347 /* VEX_LEN_0F3A7F_P_2 */
10349 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10352 /* VEX_LEN_0F3ADF_P_2 */
10354 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10357 /* VEX_LEN_0F3AF0_P_3 */
10359 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10362 /* VEX_LEN_0FXOP_08_CC */
10364 { "vpcomb", { XM
, Vex128
, EXx
, Ib
}, 0 },
10367 /* VEX_LEN_0FXOP_08_CD */
10369 { "vpcomw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10372 /* VEX_LEN_0FXOP_08_CE */
10374 { "vpcomd", { XM
, Vex128
, EXx
, Ib
}, 0 },
10377 /* VEX_LEN_0FXOP_08_CF */
10379 { "vpcomq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10382 /* VEX_LEN_0FXOP_08_EC */
10384 { "vpcomub", { XM
, Vex128
, EXx
, Ib
}, 0 },
10387 /* VEX_LEN_0FXOP_08_ED */
10389 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10392 /* VEX_LEN_0FXOP_08_EE */
10394 { "vpcomud", { XM
, Vex128
, EXx
, Ib
}, 0 },
10397 /* VEX_LEN_0FXOP_08_EF */
10399 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10402 /* VEX_LEN_0FXOP_09_80 */
10404 { "vfrczps", { XM
, EXxmm
}, 0 },
10405 { "vfrczps", { XM
, EXymmq
}, 0 },
10408 /* VEX_LEN_0FXOP_09_81 */
10410 { "vfrczpd", { XM
, EXxmm
}, 0 },
10411 { "vfrczpd", { XM
, EXymmq
}, 0 },
10415 static const struct dis386 vex_w_table
[][2] = {
10417 /* VEX_W_0F10_P_0 */
10418 { "vmovups", { XM
, EXx
}, 0 },
10421 /* VEX_W_0F10_P_1 */
10422 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10425 /* VEX_W_0F10_P_2 */
10426 { "vmovupd", { XM
, EXx
}, 0 },
10429 /* VEX_W_0F10_P_3 */
10430 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10433 /* VEX_W_0F11_P_0 */
10434 { "vmovups", { EXxS
, XM
}, 0 },
10437 /* VEX_W_0F11_P_1 */
10438 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10441 /* VEX_W_0F11_P_2 */
10442 { "vmovupd", { EXxS
, XM
}, 0 },
10445 /* VEX_W_0F11_P_3 */
10446 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10449 /* VEX_W_0F12_P_0_M_0 */
10450 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10453 /* VEX_W_0F12_P_0_M_1 */
10454 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10457 /* VEX_W_0F12_P_1 */
10458 { "vmovsldup", { XM
, EXx
}, 0 },
10461 /* VEX_W_0F12_P_2 */
10462 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10465 /* VEX_W_0F12_P_3 */
10466 { "vmovddup", { XM
, EXymmq
}, 0 },
10469 /* VEX_W_0F13_M_0 */
10470 { "vmovlpX", { EXq
, XM
}, 0 },
10474 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10478 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10481 /* VEX_W_0F16_P_0_M_0 */
10482 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10485 /* VEX_W_0F16_P_0_M_1 */
10486 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10489 /* VEX_W_0F16_P_1 */
10490 { "vmovshdup", { XM
, EXx
}, 0 },
10493 /* VEX_W_0F16_P_2 */
10494 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10497 /* VEX_W_0F17_M_0 */
10498 { "vmovhpX", { EXq
, XM
}, 0 },
10502 { "vmovapX", { XM
, EXx
}, 0 },
10506 { "vmovapX", { EXxS
, XM
}, 0 },
10509 /* VEX_W_0F2B_M_0 */
10510 { "vmovntpX", { Mx
, XM
}, 0 },
10513 /* VEX_W_0F2E_P_0 */
10514 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10517 /* VEX_W_0F2E_P_2 */
10518 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10521 /* VEX_W_0F2F_P_0 */
10522 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10525 /* VEX_W_0F2F_P_2 */
10526 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10529 /* VEX_W_0F41_P_0_LEN_1 */
10530 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10531 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10534 /* VEX_W_0F41_P_2_LEN_1 */
10535 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10536 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10539 /* VEX_W_0F42_P_0_LEN_1 */
10540 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10541 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10544 /* VEX_W_0F42_P_2_LEN_1 */
10545 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10546 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10549 /* VEX_W_0F44_P_0_LEN_0 */
10550 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10551 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10554 /* VEX_W_0F44_P_2_LEN_0 */
10555 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10556 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10559 /* VEX_W_0F45_P_0_LEN_1 */
10560 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10561 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10564 /* VEX_W_0F45_P_2_LEN_1 */
10565 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10566 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10569 /* VEX_W_0F46_P_0_LEN_1 */
10570 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10571 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10574 /* VEX_W_0F46_P_2_LEN_1 */
10575 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10576 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10579 /* VEX_W_0F47_P_0_LEN_1 */
10580 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10581 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10584 /* VEX_W_0F47_P_2_LEN_1 */
10585 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10586 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10589 /* VEX_W_0F4A_P_0_LEN_1 */
10590 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10591 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10594 /* VEX_W_0F4A_P_2_LEN_1 */
10595 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10596 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10599 /* VEX_W_0F4B_P_0_LEN_1 */
10600 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10601 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10604 /* VEX_W_0F4B_P_2_LEN_1 */
10605 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10608 /* VEX_W_0F50_M_0 */
10609 { "vmovmskpX", { Gdq
, XS
}, 0 },
10612 /* VEX_W_0F51_P_0 */
10613 { "vsqrtps", { XM
, EXx
}, 0 },
10616 /* VEX_W_0F51_P_1 */
10617 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10620 /* VEX_W_0F51_P_2 */
10621 { "vsqrtpd", { XM
, EXx
}, 0 },
10624 /* VEX_W_0F51_P_3 */
10625 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10628 /* VEX_W_0F52_P_0 */
10629 { "vrsqrtps", { XM
, EXx
}, 0 },
10632 /* VEX_W_0F52_P_1 */
10633 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10636 /* VEX_W_0F53_P_0 */
10637 { "vrcpps", { XM
, EXx
}, 0 },
10640 /* VEX_W_0F53_P_1 */
10641 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10644 /* VEX_W_0F58_P_0 */
10645 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10648 /* VEX_W_0F58_P_1 */
10649 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10652 /* VEX_W_0F58_P_2 */
10653 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10656 /* VEX_W_0F58_P_3 */
10657 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10660 /* VEX_W_0F59_P_0 */
10661 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10664 /* VEX_W_0F59_P_1 */
10665 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10668 /* VEX_W_0F59_P_2 */
10669 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10672 /* VEX_W_0F59_P_3 */
10673 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10676 /* VEX_W_0F5A_P_0 */
10677 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10680 /* VEX_W_0F5A_P_1 */
10681 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10684 /* VEX_W_0F5A_P_3 */
10685 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10688 /* VEX_W_0F5B_P_0 */
10689 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10692 /* VEX_W_0F5B_P_1 */
10693 { "vcvttps2dq", { XM
, EXx
}, 0 },
10696 /* VEX_W_0F5B_P_2 */
10697 { "vcvtps2dq", { XM
, EXx
}, 0 },
10700 /* VEX_W_0F5C_P_0 */
10701 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10704 /* VEX_W_0F5C_P_1 */
10705 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10708 /* VEX_W_0F5C_P_2 */
10709 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10712 /* VEX_W_0F5C_P_3 */
10713 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10716 /* VEX_W_0F5D_P_0 */
10717 { "vminps", { XM
, Vex
, EXx
}, 0 },
10720 /* VEX_W_0F5D_P_1 */
10721 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10724 /* VEX_W_0F5D_P_2 */
10725 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10728 /* VEX_W_0F5D_P_3 */
10729 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10732 /* VEX_W_0F5E_P_0 */
10733 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10736 /* VEX_W_0F5E_P_1 */
10737 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10740 /* VEX_W_0F5E_P_2 */
10741 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10744 /* VEX_W_0F5E_P_3 */
10745 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10748 /* VEX_W_0F5F_P_0 */
10749 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10752 /* VEX_W_0F5F_P_1 */
10753 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10756 /* VEX_W_0F5F_P_2 */
10757 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10760 /* VEX_W_0F5F_P_3 */
10761 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10764 /* VEX_W_0F60_P_2 */
10765 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10768 /* VEX_W_0F61_P_2 */
10769 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10772 /* VEX_W_0F62_P_2 */
10773 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10776 /* VEX_W_0F63_P_2 */
10777 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10780 /* VEX_W_0F64_P_2 */
10781 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10784 /* VEX_W_0F65_P_2 */
10785 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10788 /* VEX_W_0F66_P_2 */
10789 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10792 /* VEX_W_0F67_P_2 */
10793 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10796 /* VEX_W_0F68_P_2 */
10797 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10800 /* VEX_W_0F69_P_2 */
10801 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10804 /* VEX_W_0F6A_P_2 */
10805 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10808 /* VEX_W_0F6B_P_2 */
10809 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10812 /* VEX_W_0F6C_P_2 */
10813 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10816 /* VEX_W_0F6D_P_2 */
10817 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10820 /* VEX_W_0F6F_P_1 */
10821 { "vmovdqu", { XM
, EXx
}, 0 },
10824 /* VEX_W_0F6F_P_2 */
10825 { "vmovdqa", { XM
, EXx
}, 0 },
10828 /* VEX_W_0F70_P_1 */
10829 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10832 /* VEX_W_0F70_P_2 */
10833 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10836 /* VEX_W_0F70_P_3 */
10837 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10840 /* VEX_W_0F71_R_2_P_2 */
10841 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10844 /* VEX_W_0F71_R_4_P_2 */
10845 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10848 /* VEX_W_0F71_R_6_P_2 */
10849 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10852 /* VEX_W_0F72_R_2_P_2 */
10853 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10856 /* VEX_W_0F72_R_4_P_2 */
10857 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10860 /* VEX_W_0F72_R_6_P_2 */
10861 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10864 /* VEX_W_0F73_R_2_P_2 */
10865 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10868 /* VEX_W_0F73_R_3_P_2 */
10869 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10872 /* VEX_W_0F73_R_6_P_2 */
10873 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10876 /* VEX_W_0F73_R_7_P_2 */
10877 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10880 /* VEX_W_0F74_P_2 */
10881 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10884 /* VEX_W_0F75_P_2 */
10885 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10888 /* VEX_W_0F76_P_2 */
10889 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10892 /* VEX_W_0F77_P_0 */
10893 { "", { VZERO
}, 0 },
10896 /* VEX_W_0F7C_P_2 */
10897 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10900 /* VEX_W_0F7C_P_3 */
10901 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10904 /* VEX_W_0F7D_P_2 */
10905 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10908 /* VEX_W_0F7D_P_3 */
10909 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10912 /* VEX_W_0F7E_P_1 */
10913 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10916 /* VEX_W_0F7F_P_1 */
10917 { "vmovdqu", { EXxS
, XM
}, 0 },
10920 /* VEX_W_0F7F_P_2 */
10921 { "vmovdqa", { EXxS
, XM
}, 0 },
10924 /* VEX_W_0F90_P_0_LEN_0 */
10925 { "kmovw", { MaskG
, MaskE
}, 0 },
10926 { "kmovq", { MaskG
, MaskE
}, 0 },
10929 /* VEX_W_0F90_P_2_LEN_0 */
10930 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10931 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10934 /* VEX_W_0F91_P_0_LEN_0 */
10935 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10936 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10939 /* VEX_W_0F91_P_2_LEN_0 */
10940 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10941 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10944 /* VEX_W_0F92_P_0_LEN_0 */
10945 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10948 /* VEX_W_0F92_P_2_LEN_0 */
10949 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10952 /* VEX_W_0F92_P_3_LEN_0 */
10953 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0
) },
10954 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0
) },
10957 /* VEX_W_0F93_P_0_LEN_0 */
10958 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10961 /* VEX_W_0F93_P_2_LEN_0 */
10962 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10965 /* VEX_W_0F93_P_3_LEN_0 */
10966 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0
) },
10967 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0
) },
10970 /* VEX_W_0F98_P_0_LEN_0 */
10971 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10972 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10975 /* VEX_W_0F98_P_2_LEN_0 */
10976 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10977 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10980 /* VEX_W_0F99_P_0_LEN_0 */
10981 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10982 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10985 /* VEX_W_0F99_P_2_LEN_0 */
10986 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10987 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10990 /* VEX_W_0FAE_R_2_M_0 */
10991 { "vldmxcsr", { Md
}, 0 },
10994 /* VEX_W_0FAE_R_3_M_0 */
10995 { "vstmxcsr", { Md
}, 0 },
10998 /* VEX_W_0FC2_P_0 */
10999 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
11002 /* VEX_W_0FC2_P_1 */
11003 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
11006 /* VEX_W_0FC2_P_2 */
11007 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
11010 /* VEX_W_0FC2_P_3 */
11011 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
11014 /* VEX_W_0FC4_P_2 */
11015 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
11018 /* VEX_W_0FC5_P_2 */
11019 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
11022 /* VEX_W_0FD0_P_2 */
11023 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
11026 /* VEX_W_0FD0_P_3 */
11027 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
11030 /* VEX_W_0FD1_P_2 */
11031 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
11034 /* VEX_W_0FD2_P_2 */
11035 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
11038 /* VEX_W_0FD3_P_2 */
11039 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
11042 /* VEX_W_0FD4_P_2 */
11043 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
11046 /* VEX_W_0FD5_P_2 */
11047 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
11050 /* VEX_W_0FD6_P_2 */
11051 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
11054 /* VEX_W_0FD7_P_2_M_1 */
11055 { "vpmovmskb", { Gdq
, XS
}, 0 },
11058 /* VEX_W_0FD8_P_2 */
11059 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
11062 /* VEX_W_0FD9_P_2 */
11063 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
11066 /* VEX_W_0FDA_P_2 */
11067 { "vpminub", { XM
, Vex
, EXx
}, 0 },
11070 /* VEX_W_0FDB_P_2 */
11071 { "vpand", { XM
, Vex
, EXx
}, 0 },
11074 /* VEX_W_0FDC_P_2 */
11075 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
11078 /* VEX_W_0FDD_P_2 */
11079 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
11082 /* VEX_W_0FDE_P_2 */
11083 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
11086 /* VEX_W_0FDF_P_2 */
11087 { "vpandn", { XM
, Vex
, EXx
}, 0 },
11090 /* VEX_W_0FE0_P_2 */
11091 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
11094 /* VEX_W_0FE1_P_2 */
11095 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
11098 /* VEX_W_0FE2_P_2 */
11099 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
11102 /* VEX_W_0FE3_P_2 */
11103 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
11106 /* VEX_W_0FE4_P_2 */
11107 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
11110 /* VEX_W_0FE5_P_2 */
11111 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
11114 /* VEX_W_0FE6_P_1 */
11115 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
11118 /* VEX_W_0FE6_P_2 */
11119 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
11122 /* VEX_W_0FE6_P_3 */
11123 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
11126 /* VEX_W_0FE7_P_2_M_0 */
11127 { "vmovntdq", { Mx
, XM
}, 0 },
11130 /* VEX_W_0FE8_P_2 */
11131 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
11134 /* VEX_W_0FE9_P_2 */
11135 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
11138 /* VEX_W_0FEA_P_2 */
11139 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
11142 /* VEX_W_0FEB_P_2 */
11143 { "vpor", { XM
, Vex
, EXx
}, 0 },
11146 /* VEX_W_0FEC_P_2 */
11147 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
11150 /* VEX_W_0FED_P_2 */
11151 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
11154 /* VEX_W_0FEE_P_2 */
11155 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
11158 /* VEX_W_0FEF_P_2 */
11159 { "vpxor", { XM
, Vex
, EXx
}, 0 },
11162 /* VEX_W_0FF0_P_3_M_0 */
11163 { "vlddqu", { XM
, M
}, 0 },
11166 /* VEX_W_0FF1_P_2 */
11167 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
11170 /* VEX_W_0FF2_P_2 */
11171 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
11174 /* VEX_W_0FF3_P_2 */
11175 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
11178 /* VEX_W_0FF4_P_2 */
11179 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
11182 /* VEX_W_0FF5_P_2 */
11183 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
11186 /* VEX_W_0FF6_P_2 */
11187 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
11190 /* VEX_W_0FF7_P_2 */
11191 { "vmaskmovdqu", { XM
, XS
}, 0 },
11194 /* VEX_W_0FF8_P_2 */
11195 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
11198 /* VEX_W_0FF9_P_2 */
11199 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
11202 /* VEX_W_0FFA_P_2 */
11203 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
11206 /* VEX_W_0FFB_P_2 */
11207 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
11210 /* VEX_W_0FFC_P_2 */
11211 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
11214 /* VEX_W_0FFD_P_2 */
11215 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
11218 /* VEX_W_0FFE_P_2 */
11219 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
11222 /* VEX_W_0F3800_P_2 */
11223 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
11226 /* VEX_W_0F3801_P_2 */
11227 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
11230 /* VEX_W_0F3802_P_2 */
11231 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
11234 /* VEX_W_0F3803_P_2 */
11235 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
11238 /* VEX_W_0F3804_P_2 */
11239 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
11242 /* VEX_W_0F3805_P_2 */
11243 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
11246 /* VEX_W_0F3806_P_2 */
11247 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
11250 /* VEX_W_0F3807_P_2 */
11251 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
11254 /* VEX_W_0F3808_P_2 */
11255 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
11258 /* VEX_W_0F3809_P_2 */
11259 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
11262 /* VEX_W_0F380A_P_2 */
11263 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
11266 /* VEX_W_0F380B_P_2 */
11267 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
11270 /* VEX_W_0F380C_P_2 */
11271 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
11274 /* VEX_W_0F380D_P_2 */
11275 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
11278 /* VEX_W_0F380E_P_2 */
11279 { "vtestps", { XM
, EXx
}, 0 },
11282 /* VEX_W_0F380F_P_2 */
11283 { "vtestpd", { XM
, EXx
}, 0 },
11286 /* VEX_W_0F3816_P_2 */
11287 { "vpermps", { XM
, Vex
, EXx
}, 0 },
11290 /* VEX_W_0F3817_P_2 */
11291 { "vptest", { XM
, EXx
}, 0 },
11294 /* VEX_W_0F3818_P_2 */
11295 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11298 /* VEX_W_0F3819_P_2 */
11299 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11302 /* VEX_W_0F381A_P_2_M_0 */
11303 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11306 /* VEX_W_0F381C_P_2 */
11307 { "vpabsb", { XM
, EXx
}, 0 },
11310 /* VEX_W_0F381D_P_2 */
11311 { "vpabsw", { XM
, EXx
}, 0 },
11314 /* VEX_W_0F381E_P_2 */
11315 { "vpabsd", { XM
, EXx
}, 0 },
11318 /* VEX_W_0F3820_P_2 */
11319 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11322 /* VEX_W_0F3821_P_2 */
11323 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11326 /* VEX_W_0F3822_P_2 */
11327 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11330 /* VEX_W_0F3823_P_2 */
11331 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11334 /* VEX_W_0F3824_P_2 */
11335 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11338 /* VEX_W_0F3825_P_2 */
11339 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11342 /* VEX_W_0F3828_P_2 */
11343 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11346 /* VEX_W_0F3829_P_2 */
11347 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11350 /* VEX_W_0F382A_P_2_M_0 */
11351 { "vmovntdqa", { XM
, Mx
}, 0 },
11354 /* VEX_W_0F382B_P_2 */
11355 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11358 /* VEX_W_0F382C_P_2_M_0 */
11359 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11362 /* VEX_W_0F382D_P_2_M_0 */
11363 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11366 /* VEX_W_0F382E_P_2_M_0 */
11367 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11370 /* VEX_W_0F382F_P_2_M_0 */
11371 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11374 /* VEX_W_0F3830_P_2 */
11375 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11378 /* VEX_W_0F3831_P_2 */
11379 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11382 /* VEX_W_0F3832_P_2 */
11383 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11386 /* VEX_W_0F3833_P_2 */
11387 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11390 /* VEX_W_0F3834_P_2 */
11391 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11394 /* VEX_W_0F3835_P_2 */
11395 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11398 /* VEX_W_0F3836_P_2 */
11399 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11402 /* VEX_W_0F3837_P_2 */
11403 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11406 /* VEX_W_0F3838_P_2 */
11407 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11410 /* VEX_W_0F3839_P_2 */
11411 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11414 /* VEX_W_0F383A_P_2 */
11415 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11418 /* VEX_W_0F383B_P_2 */
11419 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11422 /* VEX_W_0F383C_P_2 */
11423 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11426 /* VEX_W_0F383D_P_2 */
11427 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11430 /* VEX_W_0F383E_P_2 */
11431 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11434 /* VEX_W_0F383F_P_2 */
11435 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11438 /* VEX_W_0F3840_P_2 */
11439 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11442 /* VEX_W_0F3841_P_2 */
11443 { "vphminposuw", { XM
, EXx
}, 0 },
11446 /* VEX_W_0F3846_P_2 */
11447 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11450 /* VEX_W_0F3858_P_2 */
11451 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11454 /* VEX_W_0F3859_P_2 */
11455 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11458 /* VEX_W_0F385A_P_2_M_0 */
11459 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11462 /* VEX_W_0F3878_P_2 */
11463 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11466 /* VEX_W_0F3879_P_2 */
11467 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11470 /* VEX_W_0F38DB_P_2 */
11471 { "vaesimc", { XM
, EXx
}, 0 },
11474 /* VEX_W_0F38DC_P_2 */
11475 { "vaesenc", { XM
, Vex128
, EXx
}, 0 },
11478 /* VEX_W_0F38DD_P_2 */
11479 { "vaesenclast", { XM
, Vex128
, EXx
}, 0 },
11482 /* VEX_W_0F38DE_P_2 */
11483 { "vaesdec", { XM
, Vex128
, EXx
}, 0 },
11486 /* VEX_W_0F38DF_P_2 */
11487 { "vaesdeclast", { XM
, Vex128
, EXx
}, 0 },
11490 /* VEX_W_0F3A00_P_2 */
11492 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11495 /* VEX_W_0F3A01_P_2 */
11497 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11500 /* VEX_W_0F3A02_P_2 */
11501 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11504 /* VEX_W_0F3A04_P_2 */
11505 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11508 /* VEX_W_0F3A05_P_2 */
11509 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11512 /* VEX_W_0F3A06_P_2 */
11513 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11516 /* VEX_W_0F3A08_P_2 */
11517 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11520 /* VEX_W_0F3A09_P_2 */
11521 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11524 /* VEX_W_0F3A0A_P_2 */
11525 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11528 /* VEX_W_0F3A0B_P_2 */
11529 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11532 /* VEX_W_0F3A0C_P_2 */
11533 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11536 /* VEX_W_0F3A0D_P_2 */
11537 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11540 /* VEX_W_0F3A0E_P_2 */
11541 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11544 /* VEX_W_0F3A0F_P_2 */
11545 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11548 /* VEX_W_0F3A14_P_2 */
11549 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11552 /* VEX_W_0F3A15_P_2 */
11553 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11556 /* VEX_W_0F3A18_P_2 */
11557 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11560 /* VEX_W_0F3A19_P_2 */
11561 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11564 /* VEX_W_0F3A20_P_2 */
11565 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11568 /* VEX_W_0F3A21_P_2 */
11569 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11572 /* VEX_W_0F3A30_P_2_LEN_0 */
11573 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
11574 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
11577 /* VEX_W_0F3A31_P_2_LEN_0 */
11578 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
11579 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
11582 /* VEX_W_0F3A32_P_2_LEN_0 */
11583 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
11584 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
11587 /* VEX_W_0F3A33_P_2_LEN_0 */
11588 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
11589 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
11592 /* VEX_W_0F3A38_P_2 */
11593 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11596 /* VEX_W_0F3A39_P_2 */
11597 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11600 /* VEX_W_0F3A40_P_2 */
11601 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11604 /* VEX_W_0F3A41_P_2 */
11605 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11608 /* VEX_W_0F3A42_P_2 */
11609 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11612 /* VEX_W_0F3A44_P_2 */
11613 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
}, 0 },
11616 /* VEX_W_0F3A46_P_2 */
11617 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11620 /* VEX_W_0F3A48_P_2 */
11621 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11622 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11625 /* VEX_W_0F3A49_P_2 */
11626 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11627 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11630 /* VEX_W_0F3A4A_P_2 */
11631 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11634 /* VEX_W_0F3A4B_P_2 */
11635 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11638 /* VEX_W_0F3A4C_P_2 */
11639 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11642 /* VEX_W_0F3A60_P_2 */
11643 { "vpcmpestrm", { XM
, EXx
, Ib
}, 0 },
11646 /* VEX_W_0F3A61_P_2 */
11647 { "vpcmpestri", { XM
, EXx
, Ib
}, 0 },
11650 /* VEX_W_0F3A62_P_2 */
11651 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11654 /* VEX_W_0F3A63_P_2 */
11655 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11658 /* VEX_W_0F3ADF_P_2 */
11659 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11661 #define NEED_VEX_W_TABLE
11662 #include "i386-dis-evex.h"
11663 #undef NEED_VEX_W_TABLE
11666 static const struct dis386 mod_table
[][2] = {
11669 { "leaS", { Gv
, M
}, 0 },
11674 { RM_TABLE (RM_C6_REG_7
) },
11679 { RM_TABLE (RM_C7_REG_7
) },
11683 { "Jcall^", { indirEp
}, 0 },
11687 { "Jjmp^", { indirEp
}, 0 },
11690 /* MOD_0F01_REG_0 */
11691 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11692 { RM_TABLE (RM_0F01_REG_0
) },
11695 /* MOD_0F01_REG_1 */
11696 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11697 { RM_TABLE (RM_0F01_REG_1
) },
11700 /* MOD_0F01_REG_2 */
11701 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11702 { RM_TABLE (RM_0F01_REG_2
) },
11705 /* MOD_0F01_REG_3 */
11706 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11707 { RM_TABLE (RM_0F01_REG_3
) },
11710 /* MOD_0F01_REG_5 */
11712 { RM_TABLE (RM_0F01_REG_5
) },
11715 /* MOD_0F01_REG_7 */
11716 { "invlpg", { Mb
}, 0 },
11717 { RM_TABLE (RM_0F01_REG_7
) },
11720 /* MOD_0F12_PREFIX_0 */
11721 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
11722 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
11726 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
11729 /* MOD_0F16_PREFIX_0 */
11730 { "movhps", { XM
, EXq
}, 0 },
11731 { "movlhps", { XM
, EXq
}, 0 },
11735 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
11738 /* MOD_0F18_REG_0 */
11739 { "prefetchnta", { Mb
}, 0 },
11742 /* MOD_0F18_REG_1 */
11743 { "prefetcht0", { Mb
}, 0 },
11746 /* MOD_0F18_REG_2 */
11747 { "prefetcht1", { Mb
}, 0 },
11750 /* MOD_0F18_REG_3 */
11751 { "prefetcht2", { Mb
}, 0 },
11754 /* MOD_0F18_REG_4 */
11755 { "nop/reserved", { Mb
}, 0 },
11758 /* MOD_0F18_REG_5 */
11759 { "nop/reserved", { Mb
}, 0 },
11762 /* MOD_0F18_REG_6 */
11763 { "nop/reserved", { Mb
}, 0 },
11766 /* MOD_0F18_REG_7 */
11767 { "nop/reserved", { Mb
}, 0 },
11770 /* MOD_0F1A_PREFIX_0 */
11771 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11772 { "nopQ", { Ev
}, 0 },
11775 /* MOD_0F1B_PREFIX_0 */
11776 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11777 { "nopQ", { Ev
}, 0 },
11780 /* MOD_0F1B_PREFIX_1 */
11781 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11782 { "nopQ", { Ev
}, 0 },
11787 { "movL", { Rd
, Td
}, 0 },
11792 { "movL", { Td
, Rd
}, 0 },
11795 /* MOD_0F2B_PREFIX_0 */
11796 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
11799 /* MOD_0F2B_PREFIX_1 */
11800 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
11803 /* MOD_0F2B_PREFIX_2 */
11804 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
11807 /* MOD_0F2B_PREFIX_3 */
11808 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
11813 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11816 /* MOD_0F71_REG_2 */
11818 { "psrlw", { MS
, Ib
}, 0 },
11821 /* MOD_0F71_REG_4 */
11823 { "psraw", { MS
, Ib
}, 0 },
11826 /* MOD_0F71_REG_6 */
11828 { "psllw", { MS
, Ib
}, 0 },
11831 /* MOD_0F72_REG_2 */
11833 { "psrld", { MS
, Ib
}, 0 },
11836 /* MOD_0F72_REG_4 */
11838 { "psrad", { MS
, Ib
}, 0 },
11841 /* MOD_0F72_REG_6 */
11843 { "pslld", { MS
, Ib
}, 0 },
11846 /* MOD_0F73_REG_2 */
11848 { "psrlq", { MS
, Ib
}, 0 },
11851 /* MOD_0F73_REG_3 */
11853 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11856 /* MOD_0F73_REG_6 */
11858 { "psllq", { MS
, Ib
}, 0 },
11861 /* MOD_0F73_REG_7 */
11863 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11866 /* MOD_0FAE_REG_0 */
11867 { "fxsave", { FXSAVE
}, 0 },
11868 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11871 /* MOD_0FAE_REG_1 */
11872 { "fxrstor", { FXSAVE
}, 0 },
11873 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11876 /* MOD_0FAE_REG_2 */
11877 { "ldmxcsr", { Md
}, 0 },
11878 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11881 /* MOD_0FAE_REG_3 */
11882 { "stmxcsr", { Md
}, 0 },
11883 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11886 /* MOD_0FAE_REG_4 */
11887 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
11888 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
11891 /* MOD_0FAE_REG_5 */
11892 { "xrstor", { FXSAVE
}, 0 },
11893 { RM_TABLE (RM_0FAE_REG_5
) },
11896 /* MOD_0FAE_REG_6 */
11897 { PREFIX_TABLE (PREFIX_0FAE_REG_6
) },
11898 { RM_TABLE (RM_0FAE_REG_6
) },
11901 /* MOD_0FAE_REG_7 */
11902 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11903 { RM_TABLE (RM_0FAE_REG_7
) },
11907 { "lssS", { Gv
, Mp
}, 0 },
11911 { "lfsS", { Gv
, Mp
}, 0 },
11915 { "lgsS", { Gv
, Mp
}, 0 },
11919 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
11922 /* MOD_0FC7_REG_3 */
11923 { "xrstors", { FXSAVE
}, 0 },
11926 /* MOD_0FC7_REG_4 */
11927 { "xsavec", { FXSAVE
}, 0 },
11930 /* MOD_0FC7_REG_5 */
11931 { "xsaves", { FXSAVE
}, 0 },
11934 /* MOD_0FC7_REG_6 */
11935 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
11936 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
11939 /* MOD_0FC7_REG_7 */
11940 { "vmptrst", { Mq
}, 0 },
11941 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
11946 { "pmovmskb", { Gdq
, MS
}, 0 },
11949 /* MOD_0FE7_PREFIX_2 */
11950 { "movntdq", { Mx
, XM
}, 0 },
11953 /* MOD_0FF0_PREFIX_3 */
11954 { "lddqu", { XM
, M
}, 0 },
11957 /* MOD_0F382A_PREFIX_2 */
11958 { "movntdqa", { XM
, Mx
}, 0 },
11962 { "bound{S|}", { Gv
, Ma
}, 0 },
11963 { EVEX_TABLE (EVEX_0F
) },
11967 { "lesS", { Gv
, Mp
}, 0 },
11968 { VEX_C4_TABLE (VEX_0F
) },
11972 { "ldsS", { Gv
, Mp
}, 0 },
11973 { VEX_C5_TABLE (VEX_0F
) },
11976 /* MOD_VEX_0F12_PREFIX_0 */
11977 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11978 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11982 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11985 /* MOD_VEX_0F16_PREFIX_0 */
11986 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11987 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11991 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11995 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11998 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
12000 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
12003 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
12005 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
12008 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
12010 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
12013 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
12015 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
12018 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
12020 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
12023 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
12025 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
12028 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
12030 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
12033 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
12035 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
12038 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
12040 { "knotw", { MaskG
, MaskR
}, 0 },
12043 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
12045 { "knotq", { MaskG
, MaskR
}, 0 },
12048 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
12050 { "knotb", { MaskG
, MaskR
}, 0 },
12053 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
12055 { "knotd", { MaskG
, MaskR
}, 0 },
12058 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
12060 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
12063 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
12065 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
12068 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
12070 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
12073 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
12075 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
12078 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
12080 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
12083 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
12085 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
12088 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12090 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
12093 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12095 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
12098 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12100 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
12103 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12105 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
12108 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12110 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
12113 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12115 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
12118 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12120 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
12123 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12125 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
12128 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12130 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
12133 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12135 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
12138 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12140 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
12143 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12145 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
12148 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12150 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
12155 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
12158 /* MOD_VEX_0F71_REG_2 */
12160 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
12163 /* MOD_VEX_0F71_REG_4 */
12165 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
12168 /* MOD_VEX_0F71_REG_6 */
12170 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
12173 /* MOD_VEX_0F72_REG_2 */
12175 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
12178 /* MOD_VEX_0F72_REG_4 */
12180 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
12183 /* MOD_VEX_0F72_REG_6 */
12185 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
12188 /* MOD_VEX_0F73_REG_2 */
12190 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
12193 /* MOD_VEX_0F73_REG_3 */
12195 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
12198 /* MOD_VEX_0F73_REG_6 */
12200 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
12203 /* MOD_VEX_0F73_REG_7 */
12205 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
12208 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12209 { "kmovw", { Ew
, MaskG
}, 0 },
12213 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12214 { "kmovq", { Eq
, MaskG
}, 0 },
12218 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12219 { "kmovb", { Eb
, MaskG
}, 0 },
12223 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12224 { "kmovd", { Ed
, MaskG
}, 0 },
12228 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12230 { "kmovw", { MaskG
, Rdq
}, 0 },
12233 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12235 { "kmovb", { MaskG
, Rdq
}, 0 },
12238 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12240 { "kmovd", { MaskG
, Rdq
}, 0 },
12243 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12245 { "kmovq", { MaskG
, Rdq
}, 0 },
12248 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12250 { "kmovw", { Gdq
, MaskR
}, 0 },
12253 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12255 { "kmovb", { Gdq
, MaskR
}, 0 },
12258 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12260 { "kmovd", { Gdq
, MaskR
}, 0 },
12263 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12265 { "kmovq", { Gdq
, MaskR
}, 0 },
12268 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12270 { "kortestw", { MaskG
, MaskR
}, 0 },
12273 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12275 { "kortestq", { MaskG
, MaskR
}, 0 },
12278 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12280 { "kortestb", { MaskG
, MaskR
}, 0 },
12283 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12285 { "kortestd", { MaskG
, MaskR
}, 0 },
12288 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12290 { "ktestw", { MaskG
, MaskR
}, 0 },
12293 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12295 { "ktestq", { MaskG
, MaskR
}, 0 },
12298 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12300 { "ktestb", { MaskG
, MaskR
}, 0 },
12303 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12305 { "ktestd", { MaskG
, MaskR
}, 0 },
12308 /* MOD_VEX_0FAE_REG_2 */
12309 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
12312 /* MOD_VEX_0FAE_REG_3 */
12313 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
12316 /* MOD_VEX_0FD7_PREFIX_2 */
12318 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
12321 /* MOD_VEX_0FE7_PREFIX_2 */
12322 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
12325 /* MOD_VEX_0FF0_PREFIX_3 */
12326 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
12329 /* MOD_VEX_0F381A_PREFIX_2 */
12330 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
12333 /* MOD_VEX_0F382A_PREFIX_2 */
12334 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
12337 /* MOD_VEX_0F382C_PREFIX_2 */
12338 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
12341 /* MOD_VEX_0F382D_PREFIX_2 */
12342 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
12345 /* MOD_VEX_0F382E_PREFIX_2 */
12346 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
12349 /* MOD_VEX_0F382F_PREFIX_2 */
12350 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
12353 /* MOD_VEX_0F385A_PREFIX_2 */
12354 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
12357 /* MOD_VEX_0F388C_PREFIX_2 */
12358 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
12361 /* MOD_VEX_0F388E_PREFIX_2 */
12362 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
12365 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12367 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
12370 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12372 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
12375 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12377 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
12380 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12382 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
12385 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12387 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
12390 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12392 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
12395 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12397 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
12400 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12402 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
12404 #define NEED_MOD_TABLE
12405 #include "i386-dis-evex.h"
12406 #undef NEED_MOD_TABLE
12409 static const struct dis386 rm_table
[][8] = {
12412 { "xabort", { Skip_MODRM
, Ib
}, 0 },
12416 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
12419 /* RM_0F01_REG_0 */
12421 { "vmcall", { Skip_MODRM
}, 0 },
12422 { "vmlaunch", { Skip_MODRM
}, 0 },
12423 { "vmresume", { Skip_MODRM
}, 0 },
12424 { "vmxoff", { Skip_MODRM
}, 0 },
12427 /* RM_0F01_REG_1 */
12428 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12429 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12430 { "clac", { Skip_MODRM
}, 0 },
12431 { "stac", { Skip_MODRM
}, 0 },
12435 { "encls", { Skip_MODRM
}, 0 },
12438 /* RM_0F01_REG_2 */
12439 { "xgetbv", { Skip_MODRM
}, 0 },
12440 { "xsetbv", { Skip_MODRM
}, 0 },
12443 { "vmfunc", { Skip_MODRM
}, 0 },
12444 { "xend", { Skip_MODRM
}, 0 },
12445 { "xtest", { Skip_MODRM
}, 0 },
12446 { "enclu", { Skip_MODRM
}, 0 },
12449 /* RM_0F01_REG_3 */
12450 { "vmrun", { Skip_MODRM
}, 0 },
12451 { "vmmcall", { Skip_MODRM
}, 0 },
12452 { "vmload", { Skip_MODRM
}, 0 },
12453 { "vmsave", { Skip_MODRM
}, 0 },
12454 { "stgi", { Skip_MODRM
}, 0 },
12455 { "clgi", { Skip_MODRM
}, 0 },
12456 { "skinit", { Skip_MODRM
}, 0 },
12457 { "invlpga", { Skip_MODRM
}, 0 },
12460 /* RM_0F01_REG_5 */
12467 { "rdpkru", { Skip_MODRM
}, 0 },
12468 { "wrpkru", { Skip_MODRM
}, 0 },
12471 /* RM_0F01_REG_7 */
12472 { "swapgs", { Skip_MODRM
}, 0 },
12473 { "rdtscp", { Skip_MODRM
}, 0 },
12474 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
12475 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
12476 { "clzero", { Skip_MODRM
}, 0 },
12479 /* RM_0FAE_REG_5 */
12480 { "lfence", { Skip_MODRM
}, 0 },
12483 /* RM_0FAE_REG_6 */
12484 { "mfence", { Skip_MODRM
}, 0 },
12487 /* RM_0FAE_REG_7 */
12488 { "sfence", { Skip_MODRM
}, 0 },
12493 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12495 /* We use the high bit to indicate different name for the same
12497 #define REP_PREFIX (0xf3 | 0x100)
12498 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12499 #define XRELEASE_PREFIX (0xf3 | 0x400)
12500 #define BND_PREFIX (0xf2 | 0x400)
12505 int newrex
, i
, length
;
12511 last_lock_prefix
= -1;
12512 last_repz_prefix
= -1;
12513 last_repnz_prefix
= -1;
12514 last_data_prefix
= -1;
12515 last_addr_prefix
= -1;
12516 last_rex_prefix
= -1;
12517 last_seg_prefix
= -1;
12519 active_seg_prefix
= 0;
12520 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12521 all_prefixes
[i
] = 0;
12524 /* The maximum instruction length is 15bytes. */
12525 while (length
< MAX_CODE_LENGTH
- 1)
12527 FETCH_DATA (the_info
, codep
+ 1);
12531 /* REX prefixes family. */
12548 if (address_mode
== mode_64bit
)
12552 last_rex_prefix
= i
;
12555 prefixes
|= PREFIX_REPZ
;
12556 last_repz_prefix
= i
;
12559 prefixes
|= PREFIX_REPNZ
;
12560 last_repnz_prefix
= i
;
12563 prefixes
|= PREFIX_LOCK
;
12564 last_lock_prefix
= i
;
12567 prefixes
|= PREFIX_CS
;
12568 last_seg_prefix
= i
;
12569 active_seg_prefix
= PREFIX_CS
;
12572 prefixes
|= PREFIX_SS
;
12573 last_seg_prefix
= i
;
12574 active_seg_prefix
= PREFIX_SS
;
12577 prefixes
|= PREFIX_DS
;
12578 last_seg_prefix
= i
;
12579 active_seg_prefix
= PREFIX_DS
;
12582 prefixes
|= PREFIX_ES
;
12583 last_seg_prefix
= i
;
12584 active_seg_prefix
= PREFIX_ES
;
12587 prefixes
|= PREFIX_FS
;
12588 last_seg_prefix
= i
;
12589 active_seg_prefix
= PREFIX_FS
;
12592 prefixes
|= PREFIX_GS
;
12593 last_seg_prefix
= i
;
12594 active_seg_prefix
= PREFIX_GS
;
12597 prefixes
|= PREFIX_DATA
;
12598 last_data_prefix
= i
;
12601 prefixes
|= PREFIX_ADDR
;
12602 last_addr_prefix
= i
;
12605 /* fwait is really an instruction. If there are prefixes
12606 before the fwait, they belong to the fwait, *not* to the
12607 following instruction. */
12609 if (prefixes
|| rex
)
12611 prefixes
|= PREFIX_FWAIT
;
12613 /* This ensures that the previous REX prefixes are noticed
12614 as unused prefixes, as in the return case below. */
12618 prefixes
= PREFIX_FWAIT
;
12623 /* Rex is ignored when followed by another prefix. */
12629 if (*codep
!= FWAIT_OPCODE
)
12630 all_prefixes
[i
++] = *codep
;
12638 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12641 static const char *
12642 prefix_name (int pref
, int sizeflag
)
12644 static const char *rexes
[16] =
12647 "rex.B", /* 0x41 */
12648 "rex.X", /* 0x42 */
12649 "rex.XB", /* 0x43 */
12650 "rex.R", /* 0x44 */
12651 "rex.RB", /* 0x45 */
12652 "rex.RX", /* 0x46 */
12653 "rex.RXB", /* 0x47 */
12654 "rex.W", /* 0x48 */
12655 "rex.WB", /* 0x49 */
12656 "rex.WX", /* 0x4a */
12657 "rex.WXB", /* 0x4b */
12658 "rex.WR", /* 0x4c */
12659 "rex.WRB", /* 0x4d */
12660 "rex.WRX", /* 0x4e */
12661 "rex.WRXB", /* 0x4f */
12666 /* REX prefixes family. */
12683 return rexes
[pref
- 0x40];
12703 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12705 if (address_mode
== mode_64bit
)
12706 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12708 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12713 case XACQUIRE_PREFIX
:
12715 case XRELEASE_PREFIX
:
12724 static char op_out
[MAX_OPERANDS
][100];
12725 static int op_ad
, op_index
[MAX_OPERANDS
];
12726 static int two_source_ops
;
12727 static bfd_vma op_address
[MAX_OPERANDS
];
12728 static bfd_vma op_riprel
[MAX_OPERANDS
];
12729 static bfd_vma start_pc
;
12732 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12733 * (see topic "Redundant prefixes" in the "Differences from 8086"
12734 * section of the "Virtual 8086 Mode" chapter.)
12735 * 'pc' should be the address of this instruction, it will
12736 * be used to print the target address if this is a relative jump or call
12737 * The function returns the length of this instruction in bytes.
12740 static char intel_syntax
;
12741 static char intel_mnemonic
= !SYSV386_COMPAT
;
12742 static char open_char
;
12743 static char close_char
;
12744 static char separator_char
;
12745 static char scale_char
;
12753 static enum x86_64_isa isa64
;
12755 /* Here for backwards compatibility. When gdb stops using
12756 print_insn_i386_att and print_insn_i386_intel these functions can
12757 disappear, and print_insn_i386 be merged into print_insn. */
12759 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12763 return print_insn (pc
, info
);
12767 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12771 return print_insn (pc
, info
);
12775 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12779 return print_insn (pc
, info
);
12783 print_i386_disassembler_options (FILE *stream
)
12785 fprintf (stream
, _("\n\
12786 The following i386/x86-64 specific disassembler options are supported for use\n\
12787 with the -M switch (multiple options should be separated by commas):\n"));
12789 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12790 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12791 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12792 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12793 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12794 fprintf (stream
, _(" att-mnemonic\n"
12795 " Display instruction in AT&T mnemonic\n"));
12796 fprintf (stream
, _(" intel-mnemonic\n"
12797 " Display instruction in Intel mnemonic\n"));
12798 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12799 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12800 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12801 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12802 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12803 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12804 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
12805 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
12809 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12811 /* Get a pointer to struct dis386 with a valid name. */
12813 static const struct dis386
*
12814 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12816 int vindex
, vex_table_index
;
12818 if (dp
->name
!= NULL
)
12821 switch (dp
->op
[0].bytemode
)
12823 case USE_REG_TABLE
:
12824 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12827 case USE_MOD_TABLE
:
12828 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12829 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12833 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12836 case USE_PREFIX_TABLE
:
12839 /* The prefix in VEX is implicit. */
12840 switch (vex
.prefix
)
12845 case REPE_PREFIX_OPCODE
:
12848 case DATA_PREFIX_OPCODE
:
12851 case REPNE_PREFIX_OPCODE
:
12861 int last_prefix
= -1;
12864 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12865 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12867 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12869 if (last_repz_prefix
> last_repnz_prefix
)
12872 prefix
= PREFIX_REPZ
;
12873 last_prefix
= last_repz_prefix
;
12878 prefix
= PREFIX_REPNZ
;
12879 last_prefix
= last_repnz_prefix
;
12882 /* Check if prefix should be ignored. */
12883 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12884 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12889 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12892 prefix
= PREFIX_DATA
;
12893 last_prefix
= last_data_prefix
;
12898 used_prefixes
|= prefix
;
12899 all_prefixes
[last_prefix
] = 0;
12902 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12905 case USE_X86_64_TABLE
:
12906 vindex
= address_mode
== mode_64bit
? 1 : 0;
12907 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12910 case USE_3BYTE_TABLE
:
12911 FETCH_DATA (info
, codep
+ 2);
12913 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12915 modrm
.mod
= (*codep
>> 6) & 3;
12916 modrm
.reg
= (*codep
>> 3) & 7;
12917 modrm
.rm
= *codep
& 7;
12920 case USE_VEX_LEN_TABLE
:
12924 switch (vex
.length
)
12937 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12940 case USE_XOP_8F_TABLE
:
12941 FETCH_DATA (info
, codep
+ 3);
12942 /* All bits in the REX prefix are ignored. */
12944 rex
= ~(*codep
>> 5) & 0x7;
12946 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12947 switch ((*codep
& 0x1f))
12953 vex_table_index
= XOP_08
;
12956 vex_table_index
= XOP_09
;
12959 vex_table_index
= XOP_0A
;
12963 vex
.w
= *codep
& 0x80;
12964 if (vex
.w
&& address_mode
== mode_64bit
)
12967 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12968 if (address_mode
!= mode_64bit
12969 && vex
.register_specifier
> 0x7)
12975 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12976 switch ((*codep
& 0x3))
12982 vex
.prefix
= DATA_PREFIX_OPCODE
;
12985 vex
.prefix
= REPE_PREFIX_OPCODE
;
12988 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12995 dp
= &xop_table
[vex_table_index
][vindex
];
12998 FETCH_DATA (info
, codep
+ 1);
12999 modrm
.mod
= (*codep
>> 6) & 3;
13000 modrm
.reg
= (*codep
>> 3) & 7;
13001 modrm
.rm
= *codep
& 7;
13004 case USE_VEX_C4_TABLE
:
13006 FETCH_DATA (info
, codep
+ 3);
13007 /* All bits in the REX prefix are ignored. */
13009 rex
= ~(*codep
>> 5) & 0x7;
13010 switch ((*codep
& 0x1f))
13016 vex_table_index
= VEX_0F
;
13019 vex_table_index
= VEX_0F38
;
13022 vex_table_index
= VEX_0F3A
;
13026 vex
.w
= *codep
& 0x80;
13027 if (address_mode
== mode_64bit
)
13031 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13035 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
13036 is ignored, other REX bits are 0 and the highest bit in
13037 VEX.vvvv is also ignored. */
13039 vex
.register_specifier
= (~(*codep
>> 3)) & 0x7;
13041 vex
.length
= (*codep
& 0x4) ? 256 : 128;
13042 switch ((*codep
& 0x3))
13048 vex
.prefix
= DATA_PREFIX_OPCODE
;
13051 vex
.prefix
= REPE_PREFIX_OPCODE
;
13054 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13061 dp
= &vex_table
[vex_table_index
][vindex
];
13063 /* There is no MODRM byte for VEX [82|77]. */
13064 if (vindex
!= 0x77 && vindex
!= 0x82)
13066 FETCH_DATA (info
, codep
+ 1);
13067 modrm
.mod
= (*codep
>> 6) & 3;
13068 modrm
.reg
= (*codep
>> 3) & 7;
13069 modrm
.rm
= *codep
& 7;
13073 case USE_VEX_C5_TABLE
:
13075 FETCH_DATA (info
, codep
+ 2);
13076 /* All bits in the REX prefix are ignored. */
13078 rex
= (*codep
& 0x80) ? 0 : REX_R
;
13080 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
13082 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13084 vex
.length
= (*codep
& 0x4) ? 256 : 128;
13085 switch ((*codep
& 0x3))
13091 vex
.prefix
= DATA_PREFIX_OPCODE
;
13094 vex
.prefix
= REPE_PREFIX_OPCODE
;
13097 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13104 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
13106 /* There is no MODRM byte for VEX [82|77]. */
13107 if (vindex
!= 0x77 && vindex
!= 0x82)
13109 FETCH_DATA (info
, codep
+ 1);
13110 modrm
.mod
= (*codep
>> 6) & 3;
13111 modrm
.reg
= (*codep
>> 3) & 7;
13112 modrm
.rm
= *codep
& 7;
13116 case USE_VEX_W_TABLE
:
13120 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
13123 case USE_EVEX_TABLE
:
13124 two_source_ops
= 0;
13127 FETCH_DATA (info
, codep
+ 4);
13128 /* All bits in the REX prefix are ignored. */
13130 /* The first byte after 0x62. */
13131 rex
= ~(*codep
>> 5) & 0x7;
13132 vex
.r
= *codep
& 0x10;
13133 switch ((*codep
& 0xf))
13136 return &bad_opcode
;
13138 vex_table_index
= EVEX_0F
;
13141 vex_table_index
= EVEX_0F38
;
13144 vex_table_index
= EVEX_0F3A
;
13148 /* The second byte after 0x62. */
13150 vex
.w
= *codep
& 0x80;
13151 if (vex
.w
&& address_mode
== mode_64bit
)
13154 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13155 if (address_mode
!= mode_64bit
)
13157 /* In 16/32-bit mode silently ignore following bits. */
13161 vex
.register_specifier
&= 0x7;
13165 if (!(*codep
& 0x4))
13166 return &bad_opcode
;
13168 switch ((*codep
& 0x3))
13174 vex
.prefix
= DATA_PREFIX_OPCODE
;
13177 vex
.prefix
= REPE_PREFIX_OPCODE
;
13180 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13184 /* The third byte after 0x62. */
13187 /* Remember the static rounding bits. */
13188 vex
.ll
= (*codep
>> 5) & 3;
13189 vex
.b
= (*codep
& 0x10) != 0;
13191 vex
.v
= *codep
& 0x8;
13192 vex
.mask_register_specifier
= *codep
& 0x7;
13193 vex
.zeroing
= *codep
& 0x80;
13199 dp
= &evex_table
[vex_table_index
][vindex
];
13201 FETCH_DATA (info
, codep
+ 1);
13202 modrm
.mod
= (*codep
>> 6) & 3;
13203 modrm
.reg
= (*codep
>> 3) & 7;
13204 modrm
.rm
= *codep
& 7;
13206 /* Set vector length. */
13207 if (modrm
.mod
== 3 && vex
.b
)
13223 return &bad_opcode
;
13236 if (dp
->name
!= NULL
)
13239 return get_valid_dis386 (dp
, info
);
13243 get_sib (disassemble_info
*info
, int sizeflag
)
13245 /* If modrm.mod == 3, operand must be register. */
13247 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13251 FETCH_DATA (info
, codep
+ 2);
13252 sib
.index
= (codep
[1] >> 3) & 7;
13253 sib
.scale
= (codep
[1] >> 6) & 3;
13254 sib
.base
= codep
[1] & 7;
13259 print_insn (bfd_vma pc
, disassemble_info
*info
)
13261 const struct dis386
*dp
;
13263 char *op_txt
[MAX_OPERANDS
];
13265 int sizeflag
, orig_sizeflag
;
13267 struct dis_private priv
;
13270 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13271 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
13272 address_mode
= mode_32bit
;
13273 else if (info
->mach
== bfd_mach_i386_i8086
)
13275 address_mode
= mode_16bit
;
13276 priv
.orig_sizeflag
= 0;
13279 address_mode
= mode_64bit
;
13281 if (intel_syntax
== (char) -1)
13282 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
13284 for (p
= info
->disassembler_options
; p
!= NULL
; )
13286 if (CONST_STRNEQ (p
, "amd64"))
13288 else if (CONST_STRNEQ (p
, "intel64"))
13290 else if (CONST_STRNEQ (p
, "x86-64"))
13292 address_mode
= mode_64bit
;
13293 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13295 else if (CONST_STRNEQ (p
, "i386"))
13297 address_mode
= mode_32bit
;
13298 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13300 else if (CONST_STRNEQ (p
, "i8086"))
13302 address_mode
= mode_16bit
;
13303 priv
.orig_sizeflag
= 0;
13305 else if (CONST_STRNEQ (p
, "intel"))
13308 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
13309 intel_mnemonic
= 1;
13311 else if (CONST_STRNEQ (p
, "att"))
13314 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
13315 intel_mnemonic
= 0;
13317 else if (CONST_STRNEQ (p
, "addr"))
13319 if (address_mode
== mode_64bit
)
13321 if (p
[4] == '3' && p
[5] == '2')
13322 priv
.orig_sizeflag
&= ~AFLAG
;
13323 else if (p
[4] == '6' && p
[5] == '4')
13324 priv
.orig_sizeflag
|= AFLAG
;
13328 if (p
[4] == '1' && p
[5] == '6')
13329 priv
.orig_sizeflag
&= ~AFLAG
;
13330 else if (p
[4] == '3' && p
[5] == '2')
13331 priv
.orig_sizeflag
|= AFLAG
;
13334 else if (CONST_STRNEQ (p
, "data"))
13336 if (p
[4] == '1' && p
[5] == '6')
13337 priv
.orig_sizeflag
&= ~DFLAG
;
13338 else if (p
[4] == '3' && p
[5] == '2')
13339 priv
.orig_sizeflag
|= DFLAG
;
13341 else if (CONST_STRNEQ (p
, "suffix"))
13342 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
13344 p
= strchr (p
, ',');
13349 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
13351 (*info
->fprintf_func
) (info
->stream
,
13352 _("64-bit address is disabled"));
13358 names64
= intel_names64
;
13359 names32
= intel_names32
;
13360 names16
= intel_names16
;
13361 names8
= intel_names8
;
13362 names8rex
= intel_names8rex
;
13363 names_seg
= intel_names_seg
;
13364 names_mm
= intel_names_mm
;
13365 names_bnd
= intel_names_bnd
;
13366 names_xmm
= intel_names_xmm
;
13367 names_ymm
= intel_names_ymm
;
13368 names_zmm
= intel_names_zmm
;
13369 index64
= intel_index64
;
13370 index32
= intel_index32
;
13371 names_mask
= intel_names_mask
;
13372 index16
= intel_index16
;
13375 separator_char
= '+';
13380 names64
= att_names64
;
13381 names32
= att_names32
;
13382 names16
= att_names16
;
13383 names8
= att_names8
;
13384 names8rex
= att_names8rex
;
13385 names_seg
= att_names_seg
;
13386 names_mm
= att_names_mm
;
13387 names_bnd
= att_names_bnd
;
13388 names_xmm
= att_names_xmm
;
13389 names_ymm
= att_names_ymm
;
13390 names_zmm
= att_names_zmm
;
13391 index64
= att_index64
;
13392 index32
= att_index32
;
13393 names_mask
= att_names_mask
;
13394 index16
= att_index16
;
13397 separator_char
= ',';
13401 /* The output looks better if we put 7 bytes on a line, since that
13402 puts most long word instructions on a single line. Use 8 bytes
13404 if ((info
->mach
& bfd_mach_l1om
) != 0)
13405 info
->bytes_per_line
= 8;
13407 info
->bytes_per_line
= 7;
13409 info
->private_data
= &priv
;
13410 priv
.max_fetched
= priv
.the_buffer
;
13411 priv
.insn_start
= pc
;
13414 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13422 start_codep
= priv
.the_buffer
;
13423 codep
= priv
.the_buffer
;
13425 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
13429 /* Getting here means we tried for data but didn't get it. That
13430 means we have an incomplete instruction of some sort. Just
13431 print the first byte as a prefix or a .byte pseudo-op. */
13432 if (codep
> priv
.the_buffer
)
13434 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
13436 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
13439 /* Just print the first byte as a .byte instruction. */
13440 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
13441 (unsigned int) priv
.the_buffer
[0]);
13451 sizeflag
= priv
.orig_sizeflag
;
13453 if (!ckprefix () || rex_used
)
13455 /* Too many prefixes or unused REX prefixes. */
13457 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13459 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13461 prefix_name (all_prefixes
[i
], sizeflag
));
13465 insn_codep
= codep
;
13467 FETCH_DATA (info
, codep
+ 1);
13468 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13470 if (((prefixes
& PREFIX_FWAIT
)
13471 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13473 /* Handle prefixes before fwait. */
13474 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13476 (*info
->fprintf_func
) (info
->stream
, "%s ",
13477 prefix_name (all_prefixes
[i
], sizeflag
));
13478 (*info
->fprintf_func
) (info
->stream
, "fwait");
13482 if (*codep
== 0x0f)
13484 unsigned char threebyte
;
13487 FETCH_DATA (info
, codep
+ 1);
13488 threebyte
= *codep
;
13489 dp
= &dis386_twobyte
[threebyte
];
13490 need_modrm
= twobyte_has_modrm
[*codep
];
13495 dp
= &dis386
[*codep
];
13496 need_modrm
= onebyte_has_modrm
[*codep
];
13500 /* Save sizeflag for printing the extra prefixes later before updating
13501 it for mnemonic and operand processing. The prefix names depend
13502 only on the address mode. */
13503 orig_sizeflag
= sizeflag
;
13504 if (prefixes
& PREFIX_ADDR
)
13506 if ((prefixes
& PREFIX_DATA
))
13512 FETCH_DATA (info
, codep
+ 1);
13513 modrm
.mod
= (*codep
>> 6) & 3;
13514 modrm
.reg
= (*codep
>> 3) & 7;
13515 modrm
.rm
= *codep
& 7;
13523 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13525 get_sib (info
, sizeflag
);
13526 dofloat (sizeflag
);
13530 dp
= get_valid_dis386 (dp
, info
);
13531 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13533 get_sib (info
, sizeflag
);
13534 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13537 op_ad
= MAX_OPERANDS
- 1 - i
;
13539 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13540 /* For EVEX instruction after the last operand masking
13541 should be printed. */
13542 if (i
== 0 && vex
.evex
)
13544 /* Don't print {%k0}. */
13545 if (vex
.mask_register_specifier
)
13548 oappend (names_mask
[vex
.mask_register_specifier
]);
13558 /* Check if the REX prefix is used. */
13559 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13560 all_prefixes
[last_rex_prefix
] = 0;
13562 /* Check if the SEG prefix is used. */
13563 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13564 | PREFIX_FS
| PREFIX_GS
)) != 0
13565 && (used_prefixes
& active_seg_prefix
) != 0)
13566 all_prefixes
[last_seg_prefix
] = 0;
13568 /* Check if the ADDR prefix is used. */
13569 if ((prefixes
& PREFIX_ADDR
) != 0
13570 && (used_prefixes
& PREFIX_ADDR
) != 0)
13571 all_prefixes
[last_addr_prefix
] = 0;
13573 /* Check if the DATA prefix is used. */
13574 if ((prefixes
& PREFIX_DATA
) != 0
13575 && (used_prefixes
& PREFIX_DATA
) != 0)
13576 all_prefixes
[last_data_prefix
] = 0;
13578 /* Print the extra prefixes. */
13580 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13581 if (all_prefixes
[i
])
13584 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13587 prefix_length
+= strlen (name
) + 1;
13588 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13591 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13592 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13593 used by putop and MMX/SSE operand and may be overriden by the
13594 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13596 if (dp
->prefix_requirement
== PREFIX_OPCODE
13597 && dp
!= &bad_opcode
13599 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13601 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13603 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13605 && (used_prefixes
& PREFIX_DATA
) == 0))))
13607 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13608 return end_codep
- priv
.the_buffer
;
13611 /* Check maximum code length. */
13612 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13614 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13615 return MAX_CODE_LENGTH
;
13618 obufp
= mnemonicendp
;
13619 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13622 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13624 /* The enter and bound instructions are printed with operands in the same
13625 order as the intel book; everything else is printed in reverse order. */
13626 if (intel_syntax
|| two_source_ops
)
13630 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13631 op_txt
[i
] = op_out
[i
];
13633 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
13634 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
13636 op_txt
[2] = op_out
[3];
13637 op_txt
[3] = op_out
[2];
13640 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13642 op_ad
= op_index
[i
];
13643 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13644 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13645 riprel
= op_riprel
[i
];
13646 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13647 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13652 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13653 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13657 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13661 (*info
->fprintf_func
) (info
->stream
, ",");
13662 if (op_index
[i
] != -1 && !op_riprel
[i
])
13663 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13665 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13669 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13670 if (op_index
[i
] != -1 && op_riprel
[i
])
13672 (*info
->fprintf_func
) (info
->stream
, " # ");
13673 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
13674 + op_address
[op_index
[i
]]), info
);
13677 return codep
- priv
.the_buffer
;
13680 static const char *float_mem
[] = {
13755 static const unsigned char float_mem_mode
[] = {
13830 #define ST { OP_ST, 0 }
13831 #define STi { OP_STi, 0 }
13833 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13834 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13835 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13836 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13837 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13838 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13839 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13840 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13841 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13843 static const struct dis386 float_reg
[][8] = {
13846 { "fadd", { ST
, STi
}, 0 },
13847 { "fmul", { ST
, STi
}, 0 },
13848 { "fcom", { STi
}, 0 },
13849 { "fcomp", { STi
}, 0 },
13850 { "fsub", { ST
, STi
}, 0 },
13851 { "fsubr", { ST
, STi
}, 0 },
13852 { "fdiv", { ST
, STi
}, 0 },
13853 { "fdivr", { ST
, STi
}, 0 },
13857 { "fld", { STi
}, 0 },
13858 { "fxch", { STi
}, 0 },
13868 { "fcmovb", { ST
, STi
}, 0 },
13869 { "fcmove", { ST
, STi
}, 0 },
13870 { "fcmovbe",{ ST
, STi
}, 0 },
13871 { "fcmovu", { ST
, STi
}, 0 },
13879 { "fcmovnb",{ ST
, STi
}, 0 },
13880 { "fcmovne",{ ST
, STi
}, 0 },
13881 { "fcmovnbe",{ ST
, STi
}, 0 },
13882 { "fcmovnu",{ ST
, STi
}, 0 },
13884 { "fucomi", { ST
, STi
}, 0 },
13885 { "fcomi", { ST
, STi
}, 0 },
13890 { "fadd", { STi
, ST
}, 0 },
13891 { "fmul", { STi
, ST
}, 0 },
13894 { "fsub!M", { STi
, ST
}, 0 },
13895 { "fsubM", { STi
, ST
}, 0 },
13896 { "fdiv!M", { STi
, ST
}, 0 },
13897 { "fdivM", { STi
, ST
}, 0 },
13901 { "ffree", { STi
}, 0 },
13903 { "fst", { STi
}, 0 },
13904 { "fstp", { STi
}, 0 },
13905 { "fucom", { STi
}, 0 },
13906 { "fucomp", { STi
}, 0 },
13912 { "faddp", { STi
, ST
}, 0 },
13913 { "fmulp", { STi
, ST
}, 0 },
13916 { "fsub!Mp", { STi
, ST
}, 0 },
13917 { "fsubMp", { STi
, ST
}, 0 },
13918 { "fdiv!Mp", { STi
, ST
}, 0 },
13919 { "fdivMp", { STi
, ST
}, 0 },
13923 { "ffreep", { STi
}, 0 },
13928 { "fucomip", { ST
, STi
}, 0 },
13929 { "fcomip", { ST
, STi
}, 0 },
13934 static char *fgrps
[][8] = {
13937 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13942 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13947 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13952 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13957 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13962 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13967 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13968 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13973 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13978 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13983 swap_operand (void)
13985 mnemonicendp
[0] = '.';
13986 mnemonicendp
[1] = 's';
13991 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13992 int sizeflag ATTRIBUTE_UNUSED
)
13994 /* Skip mod/rm byte. */
14000 dofloat (int sizeflag
)
14002 const struct dis386
*dp
;
14003 unsigned char floatop
;
14005 floatop
= codep
[-1];
14007 if (modrm
.mod
!= 3)
14009 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
14011 putop (float_mem
[fp_indx
], sizeflag
);
14014 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
14017 /* Skip mod/rm byte. */
14021 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
14022 if (dp
->name
== NULL
)
14024 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
14026 /* Instruction fnstsw is only one with strange arg. */
14027 if (floatop
== 0xdf && codep
[-1] == 0xe0)
14028 strcpy (op_out
[0], names16
[0]);
14032 putop (dp
->name
, sizeflag
);
14037 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
14042 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
14046 /* Like oappend (below), but S is a string starting with '%'.
14047 In Intel syntax, the '%' is elided. */
14049 oappend_maybe_intel (const char *s
)
14051 oappend (s
+ intel_syntax
);
14055 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14057 oappend_maybe_intel ("%st");
14061 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14063 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
14064 oappend_maybe_intel (scratchbuf
);
14067 /* Capital letters in template are macros. */
14069 putop (const char *in_template
, int sizeflag
)
14074 unsigned int l
= 0, len
= 1;
14077 #define SAVE_LAST(c) \
14078 if (l < len && l < sizeof (last)) \
14083 for (p
= in_template
; *p
; p
++)
14099 while (*++p
!= '|')
14100 if (*p
== '}' || *p
== '\0')
14103 /* Fall through. */
14108 while (*++p
!= '}')
14119 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14123 if (l
== 0 && len
== 1)
14128 if (sizeflag
& SUFFIX_ALWAYS
)
14141 if (address_mode
== mode_64bit
14142 && !(prefixes
& PREFIX_ADDR
))
14153 if (intel_syntax
&& !alt
)
14155 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14157 if (sizeflag
& DFLAG
)
14158 *obufp
++ = intel_syntax
? 'd' : 'l';
14160 *obufp
++ = intel_syntax
? 'w' : 's';
14161 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14165 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14168 if (modrm
.mod
== 3)
14174 if (sizeflag
& DFLAG
)
14175 *obufp
++ = intel_syntax
? 'd' : 'l';
14178 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14184 case 'E': /* For jcxz/jecxz */
14185 if (address_mode
== mode_64bit
)
14187 if (sizeflag
& AFLAG
)
14193 if (sizeflag
& AFLAG
)
14195 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14200 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
14202 if (sizeflag
& AFLAG
)
14203 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
14205 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
14206 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14210 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
14212 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14216 if (!(rex
& REX_W
))
14217 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14222 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
14223 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
14225 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
14228 if (prefixes
& PREFIX_DS
)
14247 if (l
!= 0 || len
!= 1)
14249 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14254 if (!need_vex
|| !vex
.evex
)
14257 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14259 switch (vex
.length
)
14277 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
14282 /* Fall through. */
14285 if (l
!= 0 || len
!= 1)
14293 if (sizeflag
& SUFFIX_ALWAYS
)
14297 if (intel_mnemonic
!= cond
)
14301 if ((prefixes
& PREFIX_FWAIT
) == 0)
14304 used_prefixes
|= PREFIX_FWAIT
;
14310 else if (intel_syntax
&& (sizeflag
& DFLAG
))
14314 if (!(rex
& REX_W
))
14315 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14319 && address_mode
== mode_64bit
14320 && isa64
== intel64
)
14325 /* Fall through. */
14328 && address_mode
== mode_64bit
14329 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14334 /* Fall through. */
14337 if (l
== 0 && len
== 1)
14342 if ((rex
& REX_W
) == 0
14343 && (prefixes
& PREFIX_DATA
))
14345 if ((sizeflag
& DFLAG
) == 0)
14347 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14351 if ((prefixes
& PREFIX_DATA
)
14353 || (sizeflag
& SUFFIX_ALWAYS
))
14360 if (sizeflag
& DFLAG
)
14364 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14370 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14376 if ((prefixes
& PREFIX_DATA
)
14378 || (sizeflag
& SUFFIX_ALWAYS
))
14385 if (sizeflag
& DFLAG
)
14386 *obufp
++ = intel_syntax
? 'd' : 'l';
14389 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14397 if (address_mode
== mode_64bit
14398 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14400 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14404 /* Fall through. */
14407 if (l
== 0 && len
== 1)
14410 if (intel_syntax
&& !alt
)
14413 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14419 if (sizeflag
& DFLAG
)
14420 *obufp
++ = intel_syntax
? 'd' : 'l';
14423 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14429 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14435 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14450 else if (sizeflag
& DFLAG
)
14459 if (intel_syntax
&& !p
[1]
14460 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
14462 if (!(rex
& REX_W
))
14463 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14466 if (l
== 0 && len
== 1)
14470 if (address_mode
== mode_64bit
14471 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14473 if (sizeflag
& SUFFIX_ALWAYS
)
14495 /* Fall through. */
14498 if (l
== 0 && len
== 1)
14503 if (sizeflag
& SUFFIX_ALWAYS
)
14509 if (sizeflag
& DFLAG
)
14513 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14527 if (address_mode
== mode_64bit
14528 && !(prefixes
& PREFIX_ADDR
))
14539 if (l
!= 0 || len
!= 1)
14544 if (need_vex
&& vex
.prefix
)
14546 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14553 if (prefixes
& PREFIX_DATA
)
14557 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14561 if (l
== 0 && len
== 1)
14563 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14574 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14582 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14584 switch (vex
.length
)
14600 if (l
== 0 && len
== 1)
14602 /* operand size flag for cwtl, cbtw */
14611 else if (sizeflag
& DFLAG
)
14615 if (!(rex
& REX_W
))
14616 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14623 && last
[0] != 'L'))
14630 if (last
[0] == 'X')
14631 *obufp
++ = vex
.w
? 'd': 's';
14633 *obufp
++ = vex
.w
? 'q': 'd';
14639 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14641 if (sizeflag
& DFLAG
)
14645 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14651 if (address_mode
== mode_64bit
14652 && (isa64
== intel64
14653 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
14655 else if ((prefixes
& PREFIX_DATA
))
14657 if (!(sizeflag
& DFLAG
))
14659 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14666 mnemonicendp
= obufp
;
14671 oappend (const char *s
)
14673 obufp
= stpcpy (obufp
, s
);
14679 /* Only print the active segment register. */
14680 if (!active_seg_prefix
)
14683 used_prefixes
|= active_seg_prefix
;
14684 switch (active_seg_prefix
)
14687 oappend_maybe_intel ("%cs:");
14690 oappend_maybe_intel ("%ds:");
14693 oappend_maybe_intel ("%ss:");
14696 oappend_maybe_intel ("%es:");
14699 oappend_maybe_intel ("%fs:");
14702 oappend_maybe_intel ("%gs:");
14710 OP_indirE (int bytemode
, int sizeflag
)
14714 OP_E (bytemode
, sizeflag
);
14718 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14720 if (address_mode
== mode_64bit
)
14728 sprintf_vma (tmp
, disp
);
14729 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14730 strcpy (buf
+ 2, tmp
+ i
);
14734 bfd_signed_vma v
= disp
;
14741 /* Check for possible overflow on 0x8000000000000000. */
14744 strcpy (buf
, "9223372036854775808");
14758 tmp
[28 - i
] = (v
% 10) + '0';
14762 strcpy (buf
, tmp
+ 29 - i
);
14768 sprintf (buf
, "0x%x", (unsigned int) disp
);
14770 sprintf (buf
, "%d", (int) disp
);
14774 /* Put DISP in BUF as signed hex number. */
14777 print_displacement (char *buf
, bfd_vma disp
)
14779 bfd_signed_vma val
= disp
;
14788 /* Check for possible overflow. */
14791 switch (address_mode
)
14794 strcpy (buf
+ j
, "0x8000000000000000");
14797 strcpy (buf
+ j
, "0x80000000");
14800 strcpy (buf
+ j
, "0x8000");
14810 sprintf_vma (tmp
, (bfd_vma
) val
);
14811 for (i
= 0; tmp
[i
] == '0'; i
++)
14813 if (tmp
[i
] == '\0')
14815 strcpy (buf
+ j
, tmp
+ i
);
14819 intel_operand_size (int bytemode
, int sizeflag
)
14823 && (bytemode
== x_mode
14824 || bytemode
== evex_half_bcst_xmmq_mode
))
14827 oappend ("QWORD PTR ");
14829 oappend ("DWORD PTR ");
14838 oappend ("BYTE PTR ");
14843 case dqw_swap_mode
:
14844 oappend ("WORD PTR ");
14847 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14849 oappend ("QWORD PTR ");
14852 /* Fall through. */
14854 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14856 oappend ("QWORD PTR ");
14859 /* Fall through. */
14865 oappend ("QWORD PTR ");
14868 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14869 oappend ("DWORD PTR ");
14871 oappend ("WORD PTR ");
14872 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14876 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14878 oappend ("WORD PTR ");
14879 if (!(rex
& REX_W
))
14880 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14883 if (sizeflag
& DFLAG
)
14884 oappend ("QWORD PTR ");
14886 oappend ("DWORD PTR ");
14887 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14890 case d_scalar_mode
:
14891 case d_scalar_swap_mode
:
14894 oappend ("DWORD PTR ");
14897 case q_scalar_mode
:
14898 case q_scalar_swap_mode
:
14900 oappend ("QWORD PTR ");
14903 if (address_mode
== mode_64bit
)
14904 oappend ("QWORD PTR ");
14906 oappend ("DWORD PTR ");
14909 if (sizeflag
& DFLAG
)
14910 oappend ("FWORD PTR ");
14912 oappend ("DWORD PTR ");
14913 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14916 oappend ("TBYTE PTR ");
14920 case evex_x_gscat_mode
:
14921 case evex_x_nobcst_mode
:
14924 switch (vex
.length
)
14927 oappend ("XMMWORD PTR ");
14930 oappend ("YMMWORD PTR ");
14933 oappend ("ZMMWORD PTR ");
14940 oappend ("XMMWORD PTR ");
14943 oappend ("XMMWORD PTR ");
14946 oappend ("YMMWORD PTR ");
14949 case evex_half_bcst_xmmq_mode
:
14953 switch (vex
.length
)
14956 oappend ("QWORD PTR ");
14959 oappend ("XMMWORD PTR ");
14962 oappend ("YMMWORD PTR ");
14972 switch (vex
.length
)
14977 oappend ("BYTE PTR ");
14987 switch (vex
.length
)
14992 oappend ("WORD PTR ");
15002 switch (vex
.length
)
15007 oappend ("DWORD PTR ");
15017 switch (vex
.length
)
15022 oappend ("QWORD PTR ");
15032 switch (vex
.length
)
15035 oappend ("WORD PTR ");
15038 oappend ("DWORD PTR ");
15041 oappend ("QWORD PTR ");
15051 switch (vex
.length
)
15054 oappend ("DWORD PTR ");
15057 oappend ("QWORD PTR ");
15060 oappend ("XMMWORD PTR ");
15070 switch (vex
.length
)
15073 oappend ("QWORD PTR ");
15076 oappend ("YMMWORD PTR ");
15079 oappend ("ZMMWORD PTR ");
15089 switch (vex
.length
)
15093 oappend ("XMMWORD PTR ");
15100 oappend ("OWORD PTR ");
15103 case vex_w_dq_mode
:
15104 case vex_scalar_w_dq_mode
:
15109 oappend ("QWORD PTR ");
15111 oappend ("DWORD PTR ");
15113 case vex_vsib_d_w_dq_mode
:
15114 case vex_vsib_q_w_dq_mode
:
15121 oappend ("QWORD PTR ");
15123 oappend ("DWORD PTR ");
15127 switch (vex
.length
)
15130 oappend ("XMMWORD PTR ");
15133 oappend ("YMMWORD PTR ");
15136 oappend ("ZMMWORD PTR ");
15143 case vex_vsib_q_w_d_mode
:
15144 case vex_vsib_d_w_d_mode
:
15145 if (!need_vex
|| !vex
.evex
)
15148 switch (vex
.length
)
15151 oappend ("QWORD PTR ");
15154 oappend ("XMMWORD PTR ");
15157 oappend ("YMMWORD PTR ");
15165 if (!need_vex
|| vex
.length
!= 128)
15168 oappend ("DWORD PTR ");
15170 oappend ("BYTE PTR ");
15176 oappend ("QWORD PTR ");
15178 oappend ("WORD PTR ");
15187 OP_E_register (int bytemode
, int sizeflag
)
15189 int reg
= modrm
.rm
;
15190 const char **names
;
15196 if ((sizeflag
& SUFFIX_ALWAYS
)
15197 && (bytemode
== b_swap_mode
15198 || bytemode
== v_swap_mode
15199 || bytemode
== dqw_swap_mode
))
15225 names
= address_mode
== mode_64bit
? names64
: names32
;
15231 if (address_mode
== mode_64bit
&& isa64
== intel64
)
15236 /* Fall through. */
15238 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15244 /* Fall through. */
15251 case dqw_swap_mode
:
15257 if ((sizeflag
& DFLAG
)
15258 || (bytemode
!= v_mode
15259 && bytemode
!= v_swap_mode
))
15263 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15273 names
= names_mask
;
15278 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15281 oappend (names
[reg
]);
15285 OP_E_memory (int bytemode
, int sizeflag
)
15288 int add
= (rex
& REX_B
) ? 8 : 0;
15294 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15296 && bytemode
!= x_mode
15297 && bytemode
!= xmmq_mode
15298 && bytemode
!= evex_half_bcst_xmmq_mode
)
15307 case dqw_swap_mode
:
15314 case vex_vsib_d_w_dq_mode
:
15315 case vex_vsib_d_w_d_mode
:
15316 case vex_vsib_q_w_dq_mode
:
15317 case vex_vsib_q_w_d_mode
:
15318 case evex_x_gscat_mode
:
15320 shift
= vex
.w
? 3 : 2;
15323 case evex_half_bcst_xmmq_mode
:
15327 shift
= vex
.w
? 3 : 2;
15330 /* Fall through. */
15334 case evex_x_nobcst_mode
:
15336 switch (vex
.length
)
15359 case q_scalar_mode
:
15361 case q_scalar_swap_mode
:
15367 case d_scalar_mode
:
15369 case d_scalar_swap_mode
:
15381 /* Make necessary corrections to shift for modes that need it.
15382 For these modes we currently have shift 4, 5 or 6 depending on
15383 vex.length (it corresponds to xmmword, ymmword or zmmword
15384 operand). We might want to make it 3, 4 or 5 (e.g. for
15385 xmmq_mode). In case of broadcast enabled the corrections
15386 aren't needed, as element size is always 32 or 64 bits. */
15388 && (bytemode
== xmmq_mode
15389 || bytemode
== evex_half_bcst_xmmq_mode
))
15391 else if (bytemode
== xmmqd_mode
)
15393 else if (bytemode
== xmmdw_mode
)
15395 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
15403 intel_operand_size (bytemode
, sizeflag
);
15406 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15408 /* 32/64 bit address mode */
15417 int addr32flag
= !((sizeflag
& AFLAG
)
15418 || bytemode
== v_bnd_mode
15419 || bytemode
== bnd_mode
);
15420 const char **indexes64
= names64
;
15421 const char **indexes32
= names32
;
15431 vindex
= sib
.index
;
15437 case vex_vsib_d_w_dq_mode
:
15438 case vex_vsib_d_w_d_mode
:
15439 case vex_vsib_q_w_dq_mode
:
15440 case vex_vsib_q_w_d_mode
:
15450 switch (vex
.length
)
15453 indexes64
= indexes32
= names_xmm
;
15457 || bytemode
== vex_vsib_q_w_dq_mode
15458 || bytemode
== vex_vsib_q_w_d_mode
)
15459 indexes64
= indexes32
= names_ymm
;
15461 indexes64
= indexes32
= names_xmm
;
15465 || bytemode
== vex_vsib_q_w_dq_mode
15466 || bytemode
== vex_vsib_q_w_d_mode
)
15467 indexes64
= indexes32
= names_zmm
;
15469 indexes64
= indexes32
= names_ymm
;
15476 haveindex
= vindex
!= 4;
15483 rbase
= base
+ add
;
15491 if (address_mode
== mode_64bit
&& !havesib
)
15497 FETCH_DATA (the_info
, codep
+ 1);
15499 if ((disp
& 0x80) != 0)
15501 if (vex
.evex
&& shift
> 0)
15509 /* In 32bit mode, we need index register to tell [offset] from
15510 [eiz*1 + offset]. */
15511 needindex
= (havesib
15514 && address_mode
== mode_32bit
);
15515 havedisp
= (havebase
15517 || (havesib
&& (haveindex
|| scale
!= 0)));
15520 if (modrm
.mod
!= 0 || base
== 5)
15522 if (havedisp
|| riprel
)
15523 print_displacement (scratchbuf
, disp
);
15525 print_operand_value (scratchbuf
, 1, disp
);
15526 oappend (scratchbuf
);
15530 oappend (!addr32flag
? "(%rip)" : "(%eip)");
15534 if ((havebase
|| haveindex
|| riprel
)
15535 && (bytemode
!= v_bnd_mode
)
15536 && (bytemode
!= bnd_mode
))
15537 used_prefixes
|= PREFIX_ADDR
;
15539 if (havedisp
|| (intel_syntax
&& riprel
))
15541 *obufp
++ = open_char
;
15542 if (intel_syntax
&& riprel
)
15545 oappend (!addr32flag
? "rip" : "eip");
15549 oappend (address_mode
== mode_64bit
&& !addr32flag
15550 ? names64
[rbase
] : names32
[rbase
]);
15553 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15554 print index to tell base + index from base. */
15558 || (havebase
&& base
!= ESP_REG_NUM
))
15560 if (!intel_syntax
|| havebase
)
15562 *obufp
++ = separator_char
;
15566 oappend (address_mode
== mode_64bit
&& !addr32flag
15567 ? indexes64
[vindex
] : indexes32
[vindex
]);
15569 oappend (address_mode
== mode_64bit
&& !addr32flag
15570 ? index64
: index32
);
15572 *obufp
++ = scale_char
;
15574 sprintf (scratchbuf
, "%d", 1 << scale
);
15575 oappend (scratchbuf
);
15579 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15581 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15586 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15590 disp
= - (bfd_signed_vma
) disp
;
15594 print_displacement (scratchbuf
, disp
);
15596 print_operand_value (scratchbuf
, 1, disp
);
15597 oappend (scratchbuf
);
15600 *obufp
++ = close_char
;
15603 else if (intel_syntax
)
15605 if (modrm
.mod
!= 0 || base
== 5)
15607 if (!active_seg_prefix
)
15609 oappend (names_seg
[ds_reg
- es_reg
]);
15612 print_operand_value (scratchbuf
, 1, disp
);
15613 oappend (scratchbuf
);
15619 /* 16 bit address mode */
15620 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15627 if ((disp
& 0x8000) != 0)
15632 FETCH_DATA (the_info
, codep
+ 1);
15634 if ((disp
& 0x80) != 0)
15639 if ((disp
& 0x8000) != 0)
15645 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15647 print_displacement (scratchbuf
, disp
);
15648 oappend (scratchbuf
);
15651 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15653 *obufp
++ = open_char
;
15655 oappend (index16
[modrm
.rm
]);
15657 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15659 if ((bfd_signed_vma
) disp
>= 0)
15664 else if (modrm
.mod
!= 1)
15668 disp
= - (bfd_signed_vma
) disp
;
15671 print_displacement (scratchbuf
, disp
);
15672 oappend (scratchbuf
);
15675 *obufp
++ = close_char
;
15678 else if (intel_syntax
)
15680 if (!active_seg_prefix
)
15682 oappend (names_seg
[ds_reg
- es_reg
]);
15685 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15686 oappend (scratchbuf
);
15689 if (vex
.evex
&& vex
.b
15690 && (bytemode
== x_mode
15691 || bytemode
== xmmq_mode
15692 || bytemode
== evex_half_bcst_xmmq_mode
))
15695 || bytemode
== xmmq_mode
15696 || bytemode
== evex_half_bcst_xmmq_mode
)
15698 switch (vex
.length
)
15701 oappend ("{1to2}");
15704 oappend ("{1to4}");
15707 oappend ("{1to8}");
15715 switch (vex
.length
)
15718 oappend ("{1to4}");
15721 oappend ("{1to8}");
15724 oappend ("{1to16}");
15734 OP_E (int bytemode
, int sizeflag
)
15736 /* Skip mod/rm byte. */
15740 if (modrm
.mod
== 3)
15741 OP_E_register (bytemode
, sizeflag
);
15743 OP_E_memory (bytemode
, sizeflag
);
15747 OP_G (int bytemode
, int sizeflag
)
15758 oappend (names8rex
[modrm
.reg
+ add
]);
15760 oappend (names8
[modrm
.reg
+ add
]);
15763 oappend (names16
[modrm
.reg
+ add
]);
15768 oappend (names32
[modrm
.reg
+ add
]);
15771 oappend (names64
[modrm
.reg
+ add
]);
15774 oappend (names_bnd
[modrm
.reg
]);
15781 case dqw_swap_mode
:
15784 oappend (names64
[modrm
.reg
+ add
]);
15787 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15788 oappend (names32
[modrm
.reg
+ add
]);
15790 oappend (names16
[modrm
.reg
+ add
]);
15791 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15795 if (address_mode
== mode_64bit
)
15796 oappend (names64
[modrm
.reg
+ add
]);
15798 oappend (names32
[modrm
.reg
+ add
]);
15802 if ((modrm
.reg
+ add
) > 0x7)
15807 oappend (names_mask
[modrm
.reg
+ add
]);
15810 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15823 FETCH_DATA (the_info
, codep
+ 8);
15824 a
= *codep
++ & 0xff;
15825 a
|= (*codep
++ & 0xff) << 8;
15826 a
|= (*codep
++ & 0xff) << 16;
15827 a
|= (*codep
++ & 0xffu
) << 24;
15828 b
= *codep
++ & 0xff;
15829 b
|= (*codep
++ & 0xff) << 8;
15830 b
|= (*codep
++ & 0xff) << 16;
15831 b
|= (*codep
++ & 0xffu
) << 24;
15832 x
= a
+ ((bfd_vma
) b
<< 32);
15840 static bfd_signed_vma
15843 bfd_signed_vma x
= 0;
15845 FETCH_DATA (the_info
, codep
+ 4);
15846 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15847 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15848 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15849 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15853 static bfd_signed_vma
15856 bfd_signed_vma x
= 0;
15858 FETCH_DATA (the_info
, codep
+ 4);
15859 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15860 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15861 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15862 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15864 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15874 FETCH_DATA (the_info
, codep
+ 2);
15875 x
= *codep
++ & 0xff;
15876 x
|= (*codep
++ & 0xff) << 8;
15881 set_op (bfd_vma op
, int riprel
)
15883 op_index
[op_ad
] = op_ad
;
15884 if (address_mode
== mode_64bit
)
15886 op_address
[op_ad
] = op
;
15887 op_riprel
[op_ad
] = riprel
;
15891 /* Mask to get a 32-bit address. */
15892 op_address
[op_ad
] = op
& 0xffffffff;
15893 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15898 OP_REG (int code
, int sizeflag
)
15905 case es_reg
: case ss_reg
: case cs_reg
:
15906 case ds_reg
: case fs_reg
: case gs_reg
:
15907 oappend (names_seg
[code
- es_reg
]);
15919 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15920 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15921 s
= names16
[code
- ax_reg
+ add
];
15923 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15924 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15927 s
= names8rex
[code
- al_reg
+ add
];
15929 s
= names8
[code
- al_reg
];
15931 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15932 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15933 if (address_mode
== mode_64bit
15934 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15936 s
= names64
[code
- rAX_reg
+ add
];
15939 code
+= eAX_reg
- rAX_reg
;
15940 /* Fall through. */
15941 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15942 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15945 s
= names64
[code
- eAX_reg
+ add
];
15948 if (sizeflag
& DFLAG
)
15949 s
= names32
[code
- eAX_reg
+ add
];
15951 s
= names16
[code
- eAX_reg
+ add
];
15952 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15956 s
= INTERNAL_DISASSEMBLER_ERROR
;
15963 OP_IMREG (int code
, int sizeflag
)
15975 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15976 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15977 s
= names16
[code
- ax_reg
];
15979 case es_reg
: case ss_reg
: case cs_reg
:
15980 case ds_reg
: case fs_reg
: case gs_reg
:
15981 s
= names_seg
[code
- es_reg
];
15983 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15984 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15987 s
= names8rex
[code
- al_reg
];
15989 s
= names8
[code
- al_reg
];
15991 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15992 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15995 s
= names64
[code
- eAX_reg
];
15998 if (sizeflag
& DFLAG
)
15999 s
= names32
[code
- eAX_reg
];
16001 s
= names16
[code
- eAX_reg
];
16002 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16005 case z_mode_ax_reg
:
16006 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
16010 if (!(rex
& REX_W
))
16011 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16014 s
= INTERNAL_DISASSEMBLER_ERROR
;
16021 OP_I (int bytemode
, int sizeflag
)
16024 bfd_signed_vma mask
= -1;
16029 FETCH_DATA (the_info
, codep
+ 1);
16034 if (address_mode
== mode_64bit
)
16039 /* Fall through. */
16046 if (sizeflag
& DFLAG
)
16056 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16068 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16073 scratchbuf
[0] = '$';
16074 print_operand_value (scratchbuf
+ 1, 1, op
);
16075 oappend_maybe_intel (scratchbuf
);
16076 scratchbuf
[0] = '\0';
16080 OP_I64 (int bytemode
, int sizeflag
)
16083 bfd_signed_vma mask
= -1;
16085 if (address_mode
!= mode_64bit
)
16087 OP_I (bytemode
, sizeflag
);
16094 FETCH_DATA (the_info
, codep
+ 1);
16104 if (sizeflag
& DFLAG
)
16114 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16122 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16127 scratchbuf
[0] = '$';
16128 print_operand_value (scratchbuf
+ 1, 1, op
);
16129 oappend_maybe_intel (scratchbuf
);
16130 scratchbuf
[0] = '\0';
16134 OP_sI (int bytemode
, int sizeflag
)
16142 FETCH_DATA (the_info
, codep
+ 1);
16144 if ((op
& 0x80) != 0)
16146 if (bytemode
== b_T_mode
)
16148 if (address_mode
!= mode_64bit
16149 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
16151 /* The operand-size prefix is overridden by a REX prefix. */
16152 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16160 if (!(rex
& REX_W
))
16162 if (sizeflag
& DFLAG
)
16170 /* The operand-size prefix is overridden by a REX prefix. */
16171 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16177 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16181 scratchbuf
[0] = '$';
16182 print_operand_value (scratchbuf
+ 1, 1, op
);
16183 oappend_maybe_intel (scratchbuf
);
16187 OP_J (int bytemode
, int sizeflag
)
16191 bfd_vma segment
= 0;
16196 FETCH_DATA (the_info
, codep
+ 1);
16198 if ((disp
& 0x80) != 0)
16202 if (isa64
== amd64
)
16204 if ((sizeflag
& DFLAG
)
16205 || (address_mode
== mode_64bit
16206 && (isa64
!= amd64
|| (rex
& REX_W
))))
16211 if ((disp
& 0x8000) != 0)
16213 /* In 16bit mode, address is wrapped around at 64k within
16214 the same segment. Otherwise, a data16 prefix on a jump
16215 instruction means that the pc is masked to 16 bits after
16216 the displacement is added! */
16218 if ((prefixes
& PREFIX_DATA
) == 0)
16219 segment
= ((start_pc
+ (codep
- start_codep
))
16220 & ~((bfd_vma
) 0xffff));
16222 if (address_mode
!= mode_64bit
16223 || (isa64
== amd64
&& !(rex
& REX_W
)))
16224 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16227 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16230 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
16232 print_operand_value (scratchbuf
, 1, disp
);
16233 oappend (scratchbuf
);
16237 OP_SEG (int bytemode
, int sizeflag
)
16239 if (bytemode
== w_mode
)
16240 oappend (names_seg
[modrm
.reg
]);
16242 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
16246 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
16250 if (sizeflag
& DFLAG
)
16260 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16262 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
16264 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
16265 oappend (scratchbuf
);
16269 OP_OFF (int bytemode
, int sizeflag
)
16273 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16274 intel_operand_size (bytemode
, sizeflag
);
16277 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16284 if (!active_seg_prefix
)
16286 oappend (names_seg
[ds_reg
- es_reg
]);
16290 print_operand_value (scratchbuf
, 1, off
);
16291 oappend (scratchbuf
);
16295 OP_OFF64 (int bytemode
, int sizeflag
)
16299 if (address_mode
!= mode_64bit
16300 || (prefixes
& PREFIX_ADDR
))
16302 OP_OFF (bytemode
, sizeflag
);
16306 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16307 intel_operand_size (bytemode
, sizeflag
);
16314 if (!active_seg_prefix
)
16316 oappend (names_seg
[ds_reg
- es_reg
]);
16320 print_operand_value (scratchbuf
, 1, off
);
16321 oappend (scratchbuf
);
16325 ptr_reg (int code
, int sizeflag
)
16329 *obufp
++ = open_char
;
16330 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
16331 if (address_mode
== mode_64bit
)
16333 if (!(sizeflag
& AFLAG
))
16334 s
= names32
[code
- eAX_reg
];
16336 s
= names64
[code
- eAX_reg
];
16338 else if (sizeflag
& AFLAG
)
16339 s
= names32
[code
- eAX_reg
];
16341 s
= names16
[code
- eAX_reg
];
16343 *obufp
++ = close_char
;
16348 OP_ESreg (int code
, int sizeflag
)
16354 case 0x6d: /* insw/insl */
16355 intel_operand_size (z_mode
, sizeflag
);
16357 case 0xa5: /* movsw/movsl/movsq */
16358 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16359 case 0xab: /* stosw/stosl */
16360 case 0xaf: /* scasw/scasl */
16361 intel_operand_size (v_mode
, sizeflag
);
16364 intel_operand_size (b_mode
, sizeflag
);
16367 oappend_maybe_intel ("%es:");
16368 ptr_reg (code
, sizeflag
);
16372 OP_DSreg (int code
, int sizeflag
)
16378 case 0x6f: /* outsw/outsl */
16379 intel_operand_size (z_mode
, sizeflag
);
16381 case 0xa5: /* movsw/movsl/movsq */
16382 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16383 case 0xad: /* lodsw/lodsl/lodsq */
16384 intel_operand_size (v_mode
, sizeflag
);
16387 intel_operand_size (b_mode
, sizeflag
);
16390 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16391 default segment register DS is printed. */
16392 if (!active_seg_prefix
)
16393 active_seg_prefix
= PREFIX_DS
;
16395 ptr_reg (code
, sizeflag
);
16399 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16407 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
16409 all_prefixes
[last_lock_prefix
] = 0;
16410 used_prefixes
|= PREFIX_LOCK
;
16415 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
16416 oappend_maybe_intel (scratchbuf
);
16420 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16429 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
16431 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
16432 oappend (scratchbuf
);
16436 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16438 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
16439 oappend_maybe_intel (scratchbuf
);
16443 OP_R (int bytemode
, int sizeflag
)
16445 /* Skip mod/rm byte. */
16448 OP_E_register (bytemode
, sizeflag
);
16452 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16454 int reg
= modrm
.reg
;
16455 const char **names
;
16457 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16458 if (prefixes
& PREFIX_DATA
)
16467 oappend (names
[reg
]);
16471 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16473 int reg
= modrm
.reg
;
16474 const char **names
;
16486 && bytemode
!= xmm_mode
16487 && bytemode
!= xmmq_mode
16488 && bytemode
!= evex_half_bcst_xmmq_mode
16489 && bytemode
!= ymm_mode
16490 && bytemode
!= scalar_mode
)
16492 switch (vex
.length
)
16499 || (bytemode
!= vex_vsib_q_w_dq_mode
16500 && bytemode
!= vex_vsib_q_w_d_mode
))
16512 else if (bytemode
== xmmq_mode
16513 || bytemode
== evex_half_bcst_xmmq_mode
)
16515 switch (vex
.length
)
16528 else if (bytemode
== ymm_mode
)
16532 oappend (names
[reg
]);
16536 OP_EM (int bytemode
, int sizeflag
)
16539 const char **names
;
16541 if (modrm
.mod
!= 3)
16544 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16546 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16547 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16549 OP_E (bytemode
, sizeflag
);
16553 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16556 /* Skip mod/rm byte. */
16559 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16561 if (prefixes
& PREFIX_DATA
)
16570 oappend (names
[reg
]);
16573 /* cvt* are the only instructions in sse2 which have
16574 both SSE and MMX operands and also have 0x66 prefix
16575 in their opcode. 0x66 was originally used to differentiate
16576 between SSE and MMX instruction(operands). So we have to handle the
16577 cvt* separately using OP_EMC and OP_MXC */
16579 OP_EMC (int bytemode
, int sizeflag
)
16581 if (modrm
.mod
!= 3)
16583 if (intel_syntax
&& bytemode
== v_mode
)
16585 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16586 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16588 OP_E (bytemode
, sizeflag
);
16592 /* Skip mod/rm byte. */
16595 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16596 oappend (names_mm
[modrm
.rm
]);
16600 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16602 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16603 oappend (names_mm
[modrm
.reg
]);
16607 OP_EX (int bytemode
, int sizeflag
)
16610 const char **names
;
16612 /* Skip mod/rm byte. */
16616 if (modrm
.mod
!= 3)
16618 OP_E_memory (bytemode
, sizeflag
);
16633 if ((sizeflag
& SUFFIX_ALWAYS
)
16634 && (bytemode
== x_swap_mode
16635 || bytemode
== d_swap_mode
16636 || bytemode
== dqw_swap_mode
16637 || bytemode
== d_scalar_swap_mode
16638 || bytemode
== q_swap_mode
16639 || bytemode
== q_scalar_swap_mode
))
16643 && bytemode
!= xmm_mode
16644 && bytemode
!= xmmdw_mode
16645 && bytemode
!= xmmqd_mode
16646 && bytemode
!= xmm_mb_mode
16647 && bytemode
!= xmm_mw_mode
16648 && bytemode
!= xmm_md_mode
16649 && bytemode
!= xmm_mq_mode
16650 && bytemode
!= xmm_mdq_mode
16651 && bytemode
!= xmmq_mode
16652 && bytemode
!= evex_half_bcst_xmmq_mode
16653 && bytemode
!= ymm_mode
16654 && bytemode
!= d_scalar_mode
16655 && bytemode
!= d_scalar_swap_mode
16656 && bytemode
!= q_scalar_mode
16657 && bytemode
!= q_scalar_swap_mode
16658 && bytemode
!= vex_scalar_w_dq_mode
)
16660 switch (vex
.length
)
16675 else if (bytemode
== xmmq_mode
16676 || bytemode
== evex_half_bcst_xmmq_mode
)
16678 switch (vex
.length
)
16691 else if (bytemode
== ymm_mode
)
16695 oappend (names
[reg
]);
16699 OP_MS (int bytemode
, int sizeflag
)
16701 if (modrm
.mod
== 3)
16702 OP_EM (bytemode
, sizeflag
);
16708 OP_XS (int bytemode
, int sizeflag
)
16710 if (modrm
.mod
== 3)
16711 OP_EX (bytemode
, sizeflag
);
16717 OP_M (int bytemode
, int sizeflag
)
16719 if (modrm
.mod
== 3)
16720 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16723 OP_E (bytemode
, sizeflag
);
16727 OP_0f07 (int bytemode
, int sizeflag
)
16729 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16732 OP_E (bytemode
, sizeflag
);
16735 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16736 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16739 NOP_Fixup1 (int bytemode
, int sizeflag
)
16741 if ((prefixes
& PREFIX_DATA
) != 0
16744 && address_mode
== mode_64bit
))
16745 OP_REG (bytemode
, sizeflag
);
16747 strcpy (obuf
, "nop");
16751 NOP_Fixup2 (int bytemode
, int sizeflag
)
16753 if ((prefixes
& PREFIX_DATA
) != 0
16756 && address_mode
== mode_64bit
))
16757 OP_IMREG (bytemode
, sizeflag
);
16760 static const char *const Suffix3DNow
[] = {
16761 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16762 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16763 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16764 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16765 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16766 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16767 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16768 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16769 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16770 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16771 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16772 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16773 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16774 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16775 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16776 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16777 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16778 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16779 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16780 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16781 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16782 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16783 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16784 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16785 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16786 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16787 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16788 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16789 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16790 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16791 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16792 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16793 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16794 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16795 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16796 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16797 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16798 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16799 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16800 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16801 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16802 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16803 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16804 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16805 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16806 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16807 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16808 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16809 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16810 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16811 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16812 /* CC */ NULL
, NULL
, NULL
, NULL
,
16813 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16814 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16815 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16816 /* DC */ NULL
, NULL
, NULL
, NULL
,
16817 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16818 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16819 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16820 /* EC */ NULL
, NULL
, NULL
, NULL
,
16821 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16822 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16823 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16824 /* FC */ NULL
, NULL
, NULL
, NULL
,
16828 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16830 const char *mnemonic
;
16832 FETCH_DATA (the_info
, codep
+ 1);
16833 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16834 place where an 8-bit immediate would normally go. ie. the last
16835 byte of the instruction. */
16836 obufp
= mnemonicendp
;
16837 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16839 oappend (mnemonic
);
16842 /* Since a variable sized modrm/sib chunk is between the start
16843 of the opcode (0x0f0f) and the opcode suffix, we need to do
16844 all the modrm processing first, and don't know until now that
16845 we have a bad opcode. This necessitates some cleaning up. */
16846 op_out
[0][0] = '\0';
16847 op_out
[1][0] = '\0';
16850 mnemonicendp
= obufp
;
16853 static struct op simd_cmp_op
[] =
16855 { STRING_COMMA_LEN ("eq") },
16856 { STRING_COMMA_LEN ("lt") },
16857 { STRING_COMMA_LEN ("le") },
16858 { STRING_COMMA_LEN ("unord") },
16859 { STRING_COMMA_LEN ("neq") },
16860 { STRING_COMMA_LEN ("nlt") },
16861 { STRING_COMMA_LEN ("nle") },
16862 { STRING_COMMA_LEN ("ord") }
16866 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16868 unsigned int cmp_type
;
16870 FETCH_DATA (the_info
, codep
+ 1);
16871 cmp_type
= *codep
++ & 0xff;
16872 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16875 char *p
= mnemonicendp
- 2;
16879 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16880 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16884 /* We have a reserved extension byte. Output it directly. */
16885 scratchbuf
[0] = '$';
16886 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16887 oappend_maybe_intel (scratchbuf
);
16888 scratchbuf
[0] = '\0';
16893 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
16894 int sizeflag ATTRIBUTE_UNUSED
)
16896 /* mwaitx %eax,%ecx,%ebx */
16899 const char **names
= (address_mode
== mode_64bit
16900 ? names64
: names32
);
16901 strcpy (op_out
[0], names
[0]);
16902 strcpy (op_out
[1], names
[1]);
16903 strcpy (op_out
[2], names
[3]);
16904 two_source_ops
= 1;
16906 /* Skip mod/rm byte. */
16912 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16913 int sizeflag ATTRIBUTE_UNUSED
)
16915 /* mwait %eax,%ecx */
16918 const char **names
= (address_mode
== mode_64bit
16919 ? names64
: names32
);
16920 strcpy (op_out
[0], names
[0]);
16921 strcpy (op_out
[1], names
[1]);
16922 two_source_ops
= 1;
16924 /* Skip mod/rm byte. */
16930 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16931 int sizeflag ATTRIBUTE_UNUSED
)
16933 /* monitor %eax,%ecx,%edx" */
16936 const char **op1_names
;
16937 const char **names
= (address_mode
== mode_64bit
16938 ? names64
: names32
);
16940 if (!(prefixes
& PREFIX_ADDR
))
16941 op1_names
= (address_mode
== mode_16bit
16942 ? names16
: names
);
16945 /* Remove "addr16/addr32". */
16946 all_prefixes
[last_addr_prefix
] = 0;
16947 op1_names
= (address_mode
!= mode_32bit
16948 ? names32
: names16
);
16949 used_prefixes
|= PREFIX_ADDR
;
16951 strcpy (op_out
[0], op1_names
[0]);
16952 strcpy (op_out
[1], names
[1]);
16953 strcpy (op_out
[2], names
[2]);
16954 two_source_ops
= 1;
16956 /* Skip mod/rm byte. */
16964 /* Throw away prefixes and 1st. opcode byte. */
16965 codep
= insn_codep
+ 1;
16970 REP_Fixup (int bytemode
, int sizeflag
)
16972 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16974 if (prefixes
& PREFIX_REPZ
)
16975 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16982 OP_IMREG (bytemode
, sizeflag
);
16985 OP_ESreg (bytemode
, sizeflag
);
16988 OP_DSreg (bytemode
, sizeflag
);
16996 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
17000 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17002 if (prefixes
& PREFIX_REPNZ
)
17003 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
17006 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
17007 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
17011 HLE_Fixup1 (int bytemode
, int sizeflag
)
17014 && (prefixes
& PREFIX_LOCK
) != 0)
17016 if (prefixes
& PREFIX_REPZ
)
17017 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17018 if (prefixes
& PREFIX_REPNZ
)
17019 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
17022 OP_E (bytemode
, sizeflag
);
17025 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
17026 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
17030 HLE_Fixup2 (int bytemode
, int sizeflag
)
17032 if (modrm
.mod
!= 3)
17034 if (prefixes
& PREFIX_REPZ
)
17035 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17036 if (prefixes
& PREFIX_REPNZ
)
17037 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
17040 OP_E (bytemode
, sizeflag
);
17043 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
17044 "xrelease" for memory operand. No check for LOCK prefix. */
17047 HLE_Fixup3 (int bytemode
, int sizeflag
)
17050 && last_repz_prefix
> last_repnz_prefix
17051 && (prefixes
& PREFIX_REPZ
) != 0)
17052 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17054 OP_E (bytemode
, sizeflag
);
17058 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
17063 /* Change cmpxchg8b to cmpxchg16b. */
17064 char *p
= mnemonicendp
- 2;
17065 mnemonicendp
= stpcpy (p
, "16b");
17068 else if ((prefixes
& PREFIX_LOCK
) != 0)
17070 if (prefixes
& PREFIX_REPZ
)
17071 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17072 if (prefixes
& PREFIX_REPNZ
)
17073 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
17076 OP_M (bytemode
, sizeflag
);
17080 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
17082 const char **names
;
17086 switch (vex
.length
)
17100 oappend (names
[reg
]);
17104 CRC32_Fixup (int bytemode
, int sizeflag
)
17106 /* Add proper suffix to "crc32". */
17107 char *p
= mnemonicendp
;
17126 if (sizeflag
& DFLAG
)
17130 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17134 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17141 if (modrm
.mod
== 3)
17145 /* Skip mod/rm byte. */
17150 add
= (rex
& REX_B
) ? 8 : 0;
17151 if (bytemode
== b_mode
)
17155 oappend (names8rex
[modrm
.rm
+ add
]);
17157 oappend (names8
[modrm
.rm
+ add
]);
17163 oappend (names64
[modrm
.rm
+ add
]);
17164 else if ((prefixes
& PREFIX_DATA
))
17165 oappend (names16
[modrm
.rm
+ add
]);
17167 oappend (names32
[modrm
.rm
+ add
]);
17171 OP_E (bytemode
, sizeflag
);
17175 FXSAVE_Fixup (int bytemode
, int sizeflag
)
17177 /* Add proper suffix to "fxsave" and "fxrstor". */
17181 char *p
= mnemonicendp
;
17187 OP_M (bytemode
, sizeflag
);
17190 /* Display the destination register operand for instructions with
17194 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17197 const char **names
;
17205 reg
= vex
.register_specifier
;
17212 if (bytemode
== vex_scalar_mode
)
17214 oappend (names_xmm
[reg
]);
17218 switch (vex
.length
)
17225 case vex_vsib_q_w_dq_mode
:
17226 case vex_vsib_q_w_d_mode
:
17242 names
= names_mask
;
17256 case vex_vsib_q_w_dq_mode
:
17257 case vex_vsib_q_w_d_mode
:
17258 names
= vex
.w
? names_ymm
: names_xmm
;
17267 names
= names_mask
;
17281 oappend (names
[reg
]);
17284 /* Get the VEX immediate byte without moving codep. */
17286 static unsigned char
17287 get_vex_imm8 (int sizeflag
, int opnum
)
17289 int bytes_before_imm
= 0;
17291 if (modrm
.mod
!= 3)
17293 /* There are SIB/displacement bytes. */
17294 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
17296 /* 32/64 bit address mode */
17297 int base
= modrm
.rm
;
17299 /* Check SIB byte. */
17302 FETCH_DATA (the_info
, codep
+ 1);
17304 /* When decoding the third source, don't increase
17305 bytes_before_imm as this has already been incremented
17306 by one in OP_E_memory while decoding the second
17309 bytes_before_imm
++;
17312 /* Don't increase bytes_before_imm when decoding the third source,
17313 it has already been incremented by OP_E_memory while decoding
17314 the second source operand. */
17320 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17321 SIB == 5, there is a 4 byte displacement. */
17323 /* No displacement. */
17325 /* Fall through. */
17327 /* 4 byte displacement. */
17328 bytes_before_imm
+= 4;
17331 /* 1 byte displacement. */
17332 bytes_before_imm
++;
17339 /* 16 bit address mode */
17340 /* Don't increase bytes_before_imm when decoding the third source,
17341 it has already been incremented by OP_E_memory while decoding
17342 the second source operand. */
17348 /* When modrm.rm == 6, there is a 2 byte displacement. */
17350 /* No displacement. */
17352 /* Fall through. */
17354 /* 2 byte displacement. */
17355 bytes_before_imm
+= 2;
17358 /* 1 byte displacement: when decoding the third source,
17359 don't increase bytes_before_imm as this has already
17360 been incremented by one in OP_E_memory while decoding
17361 the second source operand. */
17363 bytes_before_imm
++;
17371 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
17372 return codep
[bytes_before_imm
];
17376 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
17378 const char **names
;
17380 if (reg
== -1 && modrm
.mod
!= 3)
17382 OP_E_memory (bytemode
, sizeflag
);
17394 else if (reg
> 7 && address_mode
!= mode_64bit
)
17398 switch (vex
.length
)
17409 oappend (names
[reg
]);
17413 OP_EX_VexImmW (int bytemode
, int sizeflag
)
17416 static unsigned char vex_imm8
;
17418 if (vex_w_done
== 0)
17422 /* Skip mod/rm byte. */
17426 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
17429 reg
= vex_imm8
>> 4;
17431 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17433 else if (vex_w_done
== 1)
17438 reg
= vex_imm8
>> 4;
17440 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17444 /* Output the imm8 directly. */
17445 scratchbuf
[0] = '$';
17446 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
17447 oappend_maybe_intel (scratchbuf
);
17448 scratchbuf
[0] = '\0';
17454 OP_Vex_2src (int bytemode
, int sizeflag
)
17456 if (modrm
.mod
== 3)
17458 int reg
= modrm
.rm
;
17462 oappend (names_xmm
[reg
]);
17467 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
17469 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
17470 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17472 OP_E (bytemode
, sizeflag
);
17477 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
17479 if (modrm
.mod
== 3)
17481 /* Skip mod/rm byte. */
17487 oappend (names_xmm
[vex
.register_specifier
]);
17489 OP_Vex_2src (bytemode
, sizeflag
);
17493 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
17496 OP_Vex_2src (bytemode
, sizeflag
);
17498 oappend (names_xmm
[vex
.register_specifier
]);
17502 OP_EX_VexW (int bytemode
, int sizeflag
)
17510 /* Skip mod/rm byte. */
17515 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
17520 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
17523 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17527 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17528 int sizeflag ATTRIBUTE_UNUSED
)
17530 /* Skip the immediate byte and check for invalid bits. */
17531 FETCH_DATA (the_info
, codep
+ 1);
17532 if (*codep
++ & 0xf)
17537 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17540 const char **names
;
17542 FETCH_DATA (the_info
, codep
+ 1);
17545 if (bytemode
!= x_mode
)
17552 if (reg
> 7 && address_mode
!= mode_64bit
)
17555 switch (vex
.length
)
17566 oappend (names
[reg
]);
17570 OP_XMM_VexW (int bytemode
, int sizeflag
)
17572 /* Turn off the REX.W bit since it is used for swapping operands
17575 OP_XMM (bytemode
, sizeflag
);
17579 OP_EX_Vex (int bytemode
, int sizeflag
)
17581 if (modrm
.mod
!= 3)
17583 if (vex
.register_specifier
!= 0)
17587 OP_EX (bytemode
, sizeflag
);
17591 OP_XMM_Vex (int bytemode
, int sizeflag
)
17593 if (modrm
.mod
!= 3)
17595 if (vex
.register_specifier
!= 0)
17599 OP_XMM (bytemode
, sizeflag
);
17603 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17605 switch (vex
.length
)
17608 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17611 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17618 static struct op vex_cmp_op
[] =
17620 { STRING_COMMA_LEN ("eq") },
17621 { STRING_COMMA_LEN ("lt") },
17622 { STRING_COMMA_LEN ("le") },
17623 { STRING_COMMA_LEN ("unord") },
17624 { STRING_COMMA_LEN ("neq") },
17625 { STRING_COMMA_LEN ("nlt") },
17626 { STRING_COMMA_LEN ("nle") },
17627 { STRING_COMMA_LEN ("ord") },
17628 { STRING_COMMA_LEN ("eq_uq") },
17629 { STRING_COMMA_LEN ("nge") },
17630 { STRING_COMMA_LEN ("ngt") },
17631 { STRING_COMMA_LEN ("false") },
17632 { STRING_COMMA_LEN ("neq_oq") },
17633 { STRING_COMMA_LEN ("ge") },
17634 { STRING_COMMA_LEN ("gt") },
17635 { STRING_COMMA_LEN ("true") },
17636 { STRING_COMMA_LEN ("eq_os") },
17637 { STRING_COMMA_LEN ("lt_oq") },
17638 { STRING_COMMA_LEN ("le_oq") },
17639 { STRING_COMMA_LEN ("unord_s") },
17640 { STRING_COMMA_LEN ("neq_us") },
17641 { STRING_COMMA_LEN ("nlt_uq") },
17642 { STRING_COMMA_LEN ("nle_uq") },
17643 { STRING_COMMA_LEN ("ord_s") },
17644 { STRING_COMMA_LEN ("eq_us") },
17645 { STRING_COMMA_LEN ("nge_uq") },
17646 { STRING_COMMA_LEN ("ngt_uq") },
17647 { STRING_COMMA_LEN ("false_os") },
17648 { STRING_COMMA_LEN ("neq_os") },
17649 { STRING_COMMA_LEN ("ge_oq") },
17650 { STRING_COMMA_LEN ("gt_oq") },
17651 { STRING_COMMA_LEN ("true_us") },
17655 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17657 unsigned int cmp_type
;
17659 FETCH_DATA (the_info
, codep
+ 1);
17660 cmp_type
= *codep
++ & 0xff;
17661 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17664 char *p
= mnemonicendp
- 2;
17668 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17669 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17673 /* We have a reserved extension byte. Output it directly. */
17674 scratchbuf
[0] = '$';
17675 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17676 oappend_maybe_intel (scratchbuf
);
17677 scratchbuf
[0] = '\0';
17682 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17683 int sizeflag ATTRIBUTE_UNUSED
)
17685 unsigned int cmp_type
;
17690 FETCH_DATA (the_info
, codep
+ 1);
17691 cmp_type
= *codep
++ & 0xff;
17692 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17693 If it's the case, print suffix, otherwise - print the immediate. */
17694 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17699 char *p
= mnemonicendp
- 2;
17701 /* vpcmp* can have both one- and two-lettered suffix. */
17715 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17716 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17720 /* We have a reserved extension byte. Output it directly. */
17721 scratchbuf
[0] = '$';
17722 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17723 oappend_maybe_intel (scratchbuf
);
17724 scratchbuf
[0] = '\0';
17728 static const struct op pclmul_op
[] =
17730 { STRING_COMMA_LEN ("lql") },
17731 { STRING_COMMA_LEN ("hql") },
17732 { STRING_COMMA_LEN ("lqh") },
17733 { STRING_COMMA_LEN ("hqh") }
17737 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17738 int sizeflag ATTRIBUTE_UNUSED
)
17740 unsigned int pclmul_type
;
17742 FETCH_DATA (the_info
, codep
+ 1);
17743 pclmul_type
= *codep
++ & 0xff;
17744 switch (pclmul_type
)
17755 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17758 char *p
= mnemonicendp
- 3;
17763 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17764 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17768 /* We have a reserved extension byte. Output it directly. */
17769 scratchbuf
[0] = '$';
17770 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17771 oappend_maybe_intel (scratchbuf
);
17772 scratchbuf
[0] = '\0';
17777 MOVBE_Fixup (int bytemode
, int sizeflag
)
17779 /* Add proper suffix to "movbe". */
17780 char *p
= mnemonicendp
;
17789 if (sizeflag
& SUFFIX_ALWAYS
)
17795 if (sizeflag
& DFLAG
)
17799 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17804 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17811 OP_M (bytemode
, sizeflag
);
17815 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17818 const char **names
;
17820 /* Skip mod/rm byte. */
17834 oappend (names
[reg
]);
17838 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17840 const char **names
;
17847 oappend (names
[vex
.register_specifier
]);
17851 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17854 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17858 if ((rex
& REX_R
) != 0 || !vex
.r
)
17864 oappend (names_mask
[modrm
.reg
]);
17868 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17871 || (bytemode
!= evex_rounding_mode
17872 && bytemode
!= evex_sae_mode
))
17874 if (modrm
.mod
== 3 && vex
.b
)
17877 case evex_rounding_mode
:
17878 oappend (names_rounding
[vex
.ll
]);
17880 case evex_sae_mode
: