opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2016 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void OP_LWPCB_E (int, int);
 121 static void OP_LWP_E (int, int);
 122 static void OP_Vex_2src_1 (int, int);
 123 static void OP_Vex_2src_2 (int, int);
 124
 125 static void MOVBE_Fixup (int, int);
 126
 127 static void OP_Mask (int, int);
 128
 129 struct dis_private {
 130   /* Points to first byte not fetched.  */
 131   bfd_byte *max_fetched;
 132   bfd_byte the_buffer[MAX_MNEM_SIZE];
 133   bfd_vma insn_start;
 134   int orig_sizeflag;
 135   OPCODES_SIGJMP_BUF bailout;
 136 };
 137
 138 enum address_mode
 139 {
 140   mode_16bit,
 141   mode_32bit,
 142   mode_64bit
 143 };
 144
 145 enum address_mode address_mode;
 146
 147 /* Flags for the prefixes for the current instruction.  See below.  */
 148 static int prefixes;
 149
 150 /* REX prefix the current instruction.  See below.  */
 151 static int rex;
 152 /* Bits of REX we've already used.  */
 153 static int rex_used;
 154 /* REX bits in original REX prefix ignored.  */
 155 static int rex_ignored;
 156 /* Mark parts used in the REX prefix.  When we are testing for
 157    empty prefix (for 8bit register REX extension), just mask it
 158    out.  Otherwise test for REX bit is excuse for existence of REX
 159    only in case value is nonzero.  */
 160 #define USED_REX(value)                                 \
 161   {                                                     \
 162     if (value)                                          \
 163       {                                                 \
 164         if ((rex & value))                              \
 165           rex_used |= (value) | REX_OPCODE;             \
 166       }                                                 \
 167     else                                                \
 168       rex_used |= REX_OPCODE;                           \
 169   }
 170
 171 /* Flags for prefixes which we somehow handled when printing the
 172    current instruction.  */
 173 static int used_prefixes;
 174
 175 /* Flags stored in PREFIXES.  */
 176 #define PREFIX_REPZ 1
 177 #define PREFIX_REPNZ 2
 178 #define PREFIX_LOCK 4
 179 #define PREFIX_CS 8
 180 #define PREFIX_SS 0x10
 181 #define PREFIX_DS 0x20
 182 #define PREFIX_ES 0x40
 183 #define PREFIX_FS 0x80
 184 #define PREFIX_GS 0x100
 185 #define PREFIX_DATA 0x200
 186 #define PREFIX_ADDR 0x400
 187 #define PREFIX_FWAIT 0x800
 188
 189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 190    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 191    on error.  */
 192 #define FETCH_DATA(info, addr) \
 193   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 194    ? 1 : fetch_data ((info), (addr)))
 195
 196 static int
 197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 198 {
 199   int status;
 200   struct dis_private *priv = (struct dis_private *) info->private_data;
 201   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 202
 203   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 204     status = (*info->read_memory_func) (start,
 205                                         priv->max_fetched,
 206                                         addr - priv->max_fetched,
 207                                         info);
 208   else
 209     status = -1;
 210   if (status != 0)
 211     {
 212       /* If we did manage to read at least one byte, then
 213          print_insn_i386 will do something sensible.  Otherwise, print
 214          an error.  We do that here because this is where we know
 215          STATUS.  */
 216       if (priv->max_fetched == priv->the_buffer)
 217         (*info->memory_error_func) (status, start, info);
 218       OPCODES_SIGLONGJMP (priv->bailout, 1);
 219     }
 220   else
 221     priv->max_fetched = addr;
 222   return 1;
 223 }
 224
 225 /* Possible values for prefix requirement.  */
 226 #define PREFIX_IGNORED_SHIFT    16
 227 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 232
 233 /* Opcode prefixes.  */
 234 #define PREFIX_OPCODE           (PREFIX_REPZ \
 235                                  | PREFIX_REPNZ \
 236                                  | PREFIX_DATA)
 237
 238 /* Prefixes ignored.  */
 239 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 240                                  | PREFIX_IGNORED_REPNZ \
 241                                  | PREFIX_IGNORED_DATA)
 242
 243 #define XX { NULL, 0 }
 244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 245
 246 #define Eb { OP_E, b_mode }
 247 #define Ebnd { OP_E, bnd_mode }
 248 #define EbS { OP_E, b_swap_mode }
 249 #define Ev { OP_E, v_mode }
 250 #define Ev_bnd { OP_E, v_bnd_mode }
 251 #define EvS { OP_E, v_swap_mode }
 252 #define Ed { OP_E, d_mode }
 253 #define Edq { OP_E, dq_mode }
 254 #define Edqw { OP_E, dqw_mode }
 255 #define EdqwS { OP_E, dqw_swap_mode }
 256 #define Edqb { OP_E, dqb_mode }
 257 #define Edb { OP_E, db_mode }
 258 #define Edw { OP_E, dw_mode }
 259 #define Edqd { OP_E, dqd_mode }
 260 #define Eq { OP_E, q_mode }
 261 #define indirEv { OP_indirE, indir_v_mode }
 262 #define indirEp { OP_indirE, f_mode }
 263 #define stackEv { OP_E, stack_v_mode }
 264 #define Em { OP_E, m_mode }
 265 #define Ew { OP_E, w_mode }
 266 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 267 #define Ma { OP_M, a_mode }
 268 #define Mb { OP_M, b_mode }
 269 #define Md { OP_M, d_mode }
 270 #define Mo { OP_M, o_mode }
 271 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 272 #define Mq { OP_M, q_mode }
 273 #define Mx { OP_M, x_mode }
 274 #define Mxmm { OP_M, xmm_mode }
 275 #define Gb { OP_G, b_mode }
 276 #define Gbnd { OP_G, bnd_mode }
 277 #define Gv { OP_G, v_mode }
 278 #define Gd { OP_G, d_mode }
 279 #define Gdq { OP_G, dq_mode }
 280 #define Gm { OP_G, m_mode }
 281 #define Gw { OP_G, w_mode }
 282 #define Rd { OP_R, d_mode }
 283 #define Rdq { OP_R, dq_mode }
 284 #define Rm { OP_R, m_mode }
 285 #define Ib { OP_I, b_mode }
 286 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 288 #define Iv { OP_I, v_mode }
 289 #define sIv { OP_sI, v_mode }
 290 #define Iq { OP_I, q_mode }
 291 #define Iv64 { OP_I64, v_mode }
 292 #define Iw { OP_I, w_mode }
 293 #define I1 { OP_I, const_1_mode }
 294 #define Jb { OP_J, b_mode }
 295 #define Jv { OP_J, v_mode }
 296 #define Cm { OP_C, m_mode }
 297 #define Dm { OP_D, m_mode }
 298 #define Td { OP_T, d_mode }
 299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 300
 301 #define RMeAX { OP_REG, eAX_reg }
 302 #define RMeBX { OP_REG, eBX_reg }
 303 #define RMeCX { OP_REG, eCX_reg }
 304 #define RMeDX { OP_REG, eDX_reg }
 305 #define RMeSP { OP_REG, eSP_reg }
 306 #define RMeBP { OP_REG, eBP_reg }
 307 #define RMeSI { OP_REG, eSI_reg }
 308 #define RMeDI { OP_REG, eDI_reg }
 309 #define RMrAX { OP_REG, rAX_reg }
 310 #define RMrBX { OP_REG, rBX_reg }
 311 #define RMrCX { OP_REG, rCX_reg }
 312 #define RMrDX { OP_REG, rDX_reg }
 313 #define RMrSP { OP_REG, rSP_reg }
 314 #define RMrBP { OP_REG, rBP_reg }
 315 #define RMrSI { OP_REG, rSI_reg }
 316 #define RMrDI { OP_REG, rDI_reg }
 317 #define RMAL { OP_REG, al_reg }
 318 #define RMCL { OP_REG, cl_reg }
 319 #define RMDL { OP_REG, dl_reg }
 320 #define RMBL { OP_REG, bl_reg }
 321 #define RMAH { OP_REG, ah_reg }
 322 #define RMCH { OP_REG, ch_reg }
 323 #define RMDH { OP_REG, dh_reg }
 324 #define RMBH { OP_REG, bh_reg }
 325 #define RMAX { OP_REG, ax_reg }
 326 #define RMDX { OP_REG, dx_reg }
 327
 328 #define eAX { OP_IMREG, eAX_reg }
 329 #define eBX { OP_IMREG, eBX_reg }
 330 #define eCX { OP_IMREG, eCX_reg }
 331 #define eDX { OP_IMREG, eDX_reg }
 332 #define eSP { OP_IMREG, eSP_reg }
 333 #define eBP { OP_IMREG, eBP_reg }
 334 #define eSI { OP_IMREG, eSI_reg }
 335 #define eDI { OP_IMREG, eDI_reg }
 336 #define AL { OP_IMREG, al_reg }
 337 #define CL { OP_IMREG, cl_reg }
 338 #define DL { OP_IMREG, dl_reg }
 339 #define BL { OP_IMREG, bl_reg }
 340 #define AH { OP_IMREG, ah_reg }
 341 #define CH { OP_IMREG, ch_reg }
 342 #define DH { OP_IMREG, dh_reg }
 343 #define BH { OP_IMREG, bh_reg }
 344 #define AX { OP_IMREG, ax_reg }
 345 #define DX { OP_IMREG, dx_reg }
 346 #define zAX { OP_IMREG, z_mode_ax_reg }
 347 #define indirDX { OP_IMREG, indir_dx_reg }
 348
 349 #define Sw { OP_SEG, w_mode }
 350 #define Sv { OP_SEG, v_mode }
 351 #define Ap { OP_DIR, 0 }
 352 #define Ob { OP_OFF64, b_mode }
 353 #define Ov { OP_OFF64, v_mode }
 354 #define Xb { OP_DSreg, eSI_reg }
 355 #define Xv { OP_DSreg, eSI_reg }
 356 #define Xz { OP_DSreg, eSI_reg }
 357 #define Yb { OP_ESreg, eDI_reg }
 358 #define Yv { OP_ESreg, eDI_reg }
 359 #define DSBX { OP_DSreg, eBX_reg }
 360
 361 #define es { OP_REG, es_reg }
 362 #define ss { OP_REG, ss_reg }
 363 #define cs { OP_REG, cs_reg }
 364 #define ds { OP_REG, ds_reg }
 365 #define fs { OP_REG, fs_reg }
 366 #define gs { OP_REG, gs_reg }
 367
 368 #define MX { OP_MMX, 0 }
 369 #define XM { OP_XMM, 0 }
 370 #define XMScalar { OP_XMM, scalar_mode }
 371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 372 #define XMM { OP_XMM, xmm_mode }
 373 #define XMxmmq { OP_XMM, xmmq_mode }
 374 #define EM { OP_EM, v_mode }
 375 #define EMS { OP_EM, v_swap_mode }
 376 #define EMd { OP_EM, d_mode }
 377 #define EMx { OP_EM, x_mode }
 378 #define EXw { OP_EX, w_mode }
 379 #define EXd { OP_EX, d_mode }
 380 #define EXdScalar { OP_EX, d_scalar_mode }
 381 #define EXdS { OP_EX, d_swap_mode }
 382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 383 #define EXq { OP_EX, q_mode }
 384 #define EXqScalar { OP_EX, q_scalar_mode }
 385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 386 #define EXqS { OP_EX, q_swap_mode }
 387 #define EXx { OP_EX, x_mode }
 388 #define EXxS { OP_EX, x_swap_mode }
 389 #define EXxmm { OP_EX, xmm_mode }
 390 #define EXymm { OP_EX, ymm_mode }
 391 #define EXxmmq { OP_EX, xmmq_mode }
 392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 395 #define EXxmm_md { OP_EX, xmm_md_mode }
 396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 398 #define EXxmmdw { OP_EX, xmmdw_mode }
 399 #define EXxmmqd { OP_EX, xmmqd_mode }
 400 #define EXymmq { OP_EX, ymmq_mode }
 401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 405 #define MS { OP_MS, v_mode }
 406 #define XS { OP_XS, v_mode }
 407 #define EMCq { OP_EMC, q_mode }
 408 #define MXC { OP_MXC, 0 }
 409 #define OPSUF { OP_3DNowSuffix, 0 }
 410 #define CMP { CMP_Fixup, 0 }
 411 #define XMM0 { XMM_Fixup, 0 }
 412 #define FXSAVE { FXSAVE_Fixup, 0 }
 413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 415
 416 #define Vex { OP_VEX, vex_mode }
 417 #define VexScalar { OP_VEX, vex_scalar_mode }
 418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 419 #define Vex128 { OP_VEX, vex128_mode }
 420 #define Vex256 { OP_VEX, vex256_mode }
 421 #define VexGdq { OP_VEX, dq_mode }
 422 #define VexI4 { VEXI4_Fixup, 0}
 423 #define EXdVex { OP_EX_Vex, d_mode }
 424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 426 #define EXqVex { OP_EX_Vex, q_mode }
 427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 429 #define EXVexW { OP_EX_VexW, x_mode }
 430 #define EXdVexW { OP_EX_VexW, d_mode }
 431 #define EXqVexW { OP_EX_VexW, q_mode }
 432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 433 #define XMVex { OP_XMM_Vex, 0 }
 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 435 #define XMVexW { OP_XMM_VexW, 0 }
 436 #define XMVexI4 { OP_REG_VexI4, x_mode }
 437 #define PCLMUL { PCLMUL_Fixup, 0 }
 438 #define VZERO { VZERO_Fixup, 0 }
 439 #define VCMP { VCMP_Fixup, 0 }
 440 #define VPCMP { VPCMP_Fixup, 0 }
 441
 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 444
 445 #define XMask { OP_Mask, mask_mode }
 446 #define MaskG { OP_G, mask_mode }
 447 #define MaskE { OP_E, mask_mode }
 448 #define MaskBDE { OP_E, mask_bd_mode }
 449 #define MaskR { OP_R, mask_mode }
 450 #define MaskVex { OP_VEX, mask_mode }
 451
 452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 456
 457 /* Used handle "rep" prefix for string instructions.  */
 458 #define Xbr { REP_Fixup, eSI_reg }
 459 #define Xvr { REP_Fixup, eSI_reg }
 460 #define Ybr { REP_Fixup, eDI_reg }
 461 #define Yvr { REP_Fixup, eDI_reg }
 462 #define Yzr { REP_Fixup, eDI_reg }
 463 #define indirDXr { REP_Fixup, indir_dx_reg }
 464 #define ALr { REP_Fixup, al_reg }
 465 #define eAXr { REP_Fixup, eAX_reg }
 466
 467 /* Used handle HLE prefix for lockable instructions.  */
 468 #define Ebh1 { HLE_Fixup1, b_mode }
 469 #define Evh1 { HLE_Fixup1, v_mode }
 470 #define Ebh2 { HLE_Fixup2, b_mode }
 471 #define Evh2 { HLE_Fixup2, v_mode }
 472 #define Ebh3 { HLE_Fixup3, b_mode }
 473 #define Evh3 { HLE_Fixup3, v_mode }
 474
 475 #define BND { BND_Fixup, 0 }
 476
 477 #define cond_jump_flag { NULL, cond_jump_mode }
 478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 479
 480 /* bits in sizeflag */
 481 #define SUFFIX_ALWAYS 4
 482 #define AFLAG 2
 483 #define DFLAG 1
 484
 485 enum
 486 {
 487   /* byte operand */
 488   b_mode = 1,
 489   /* byte operand with operand swapped */
 490   b_swap_mode,
 491   /* byte operand, sign extend like 'T' suffix */
 492   b_T_mode,
 493   /* operand size depends on prefixes */
 494   v_mode,
 495   /* operand size depends on prefixes with operand swapped */
 496   v_swap_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* XMM register or double/quad word memory operand, depending on
 536      VEX.W.  */
 537   xmm_mdq_mode,
 538   /* 16-byte XMM, word, double word or quad word operand.  */
 539   xmmdw_mode,
 540   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 541   xmmqd_mode,
 542   /* 32-byte YMM operand */
 543   ymm_mode,
 544   /* quad word, ymmword or zmmword memory operand.  */
 545   ymmq_mode,
 546   /* 32-byte YMM or 16-byte word operand */
 547   ymmxmm_mode,
 548   /* d_mode in 32bit, q_mode in 64bit mode.  */
 549   m_mode,
 550   /* pair of v_mode operands */
 551   a_mode,
 552   cond_jump_mode,
 553   loop_jcxz_mode,
 554   v_bnd_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode.  */
 558   dqw_mode,
 559   dqw_swap_mode,
 560   bnd_mode,
 561   /* 4- or 6-byte pointer operand */
 562   f_mode,
 563   const_1_mode,
 564   /* v_mode for indirect branch opcodes.  */
 565   indir_v_mode,
 566   /* v_mode for stack-related opcodes.  */
 567   stack_v_mode,
 568   /* non-quad operand size depends on prefixes */
 569   z_mode,
 570   /* 16-byte operand */
 571   o_mode,
 572   /* registers like dq_mode, memory like b_mode.  */
 573   dqb_mode,
 574   /* registers like d_mode, memory like b_mode.  */
 575   db_mode,
 576   /* registers like d_mode, memory like w_mode.  */
 577   dw_mode,
 578   /* registers like dq_mode, memory like d_mode.  */
 579   dqd_mode,
 580   /* normal vex mode */
 581   vex_mode,
 582   /* 128bit vex mode */
 583   vex128_mode,
 584   /* 256bit vex mode */
 585   vex256_mode,
 586   /* operand size depends on the VEX.W bit.  */
 587   vex_w_dq_mode,
 588
 589   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 590   vex_vsib_d_w_dq_mode,
 591   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 592   vex_vsib_d_w_d_mode,
 593   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 594   vex_vsib_q_w_dq_mode,
 595   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 596   vex_vsib_q_w_d_mode,
 597
 598   /* scalar, ignore vector length.  */
 599   scalar_mode,
 600   /* like d_mode, ignore vector length.  */
 601   d_scalar_mode,
 602   /* like d_swap_mode, ignore vector length.  */
 603   d_scalar_swap_mode,
 604   /* like q_mode, ignore vector length.  */
 605   q_scalar_mode,
 606   /* like q_swap_mode, ignore vector length.  */
 607   q_scalar_swap_mode,
 608   /* like vex_mode, ignore vector length.  */
 609   vex_scalar_mode,
 610   /* like vex_w_dq_mode, ignore vector length.  */
 611   vex_scalar_w_dq_mode,
 612
 613   /* Static rounding.  */
 614   evex_rounding_mode,
 615   /* Supress all exceptions.  */
 616   evex_sae_mode,
 617
 618   /* Mask register operand.  */
 619   mask_mode,
 620   /* Mask register operand.  */
 621   mask_bd_mode,
 622
 623   es_reg,
 624   cs_reg,
 625   ss_reg,
 626   ds_reg,
 627   fs_reg,
 628   gs_reg,
 629
 630   eAX_reg,
 631   eCX_reg,
 632   eDX_reg,
 633   eBX_reg,
 634   eSP_reg,
 635   eBP_reg,
 636   eSI_reg,
 637   eDI_reg,
 638
 639   al_reg,
 640   cl_reg,
 641   dl_reg,
 642   bl_reg,
 643   ah_reg,
 644   ch_reg,
 645   dh_reg,
 646   bh_reg,
 647
 648   ax_reg,
 649   cx_reg,
 650   dx_reg,
 651   bx_reg,
 652   sp_reg,
 653   bp_reg,
 654   si_reg,
 655   di_reg,
 656
 657   rAX_reg,
 658   rCX_reg,
 659   rDX_reg,
 660   rBX_reg,
 661   rSP_reg,
 662   rBP_reg,
 663   rSI_reg,
 664   rDI_reg,
 665
 666   z_mode_ax_reg,
 667   indir_dx_reg
 668 };
 669
 670 enum
 671 {
 672   FLOATCODE = 1,
 673   USE_REG_TABLE,
 674   USE_MOD_TABLE,
 675   USE_RM_TABLE,
 676   USE_PREFIX_TABLE,
 677   USE_X86_64_TABLE,
 678   USE_3BYTE_TABLE,
 679   USE_XOP_8F_TABLE,
 680   USE_VEX_C4_TABLE,
 681   USE_VEX_C5_TABLE,
 682   USE_VEX_LEN_TABLE,
 683   USE_VEX_W_TABLE,
 684   USE_EVEX_TABLE
 685 };
 686
 687 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 688
 689 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 690 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 691 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 692 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 693 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 694 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 695 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 696 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 697 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 698 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 699 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 700 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 701 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 702 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 703 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 704
 705 enum
 706 {
 707   REG_80 = 0,
 708   REG_81,
 709   REG_83,
 710   REG_8F,
 711   REG_C0,
 712   REG_C1,
 713   REG_C6,
 714   REG_C7,
 715   REG_D0,
 716   REG_D1,
 717   REG_D2,
 718   REG_D3,
 719   REG_F6,
 720   REG_F7,
 721   REG_FE,
 722   REG_FF,
 723   REG_0F00,
 724   REG_0F01,
 725   REG_0F0D,
 726   REG_0F18,
 727   REG_0F71,
 728   REG_0F72,
 729   REG_0F73,
 730   REG_0FA6,
 731   REG_0FA7,
 732   REG_0FAE,
 733   REG_0FBA,
 734   REG_0FC7,
 735   REG_VEX_0F71,
 736   REG_VEX_0F72,
 737   REG_VEX_0F73,
 738   REG_VEX_0FAE,
 739   REG_VEX_0F38F3,
 740   REG_XOP_LWPCB,
 741   REG_XOP_LWP,
 742   REG_XOP_TBM_01,
 743   REG_XOP_TBM_02,
 744
 745   REG_EVEX_0F71,
 746   REG_EVEX_0F72,
 747   REG_EVEX_0F73,
 748   REG_EVEX_0F38C6,
 749   REG_EVEX_0F38C7
 750 };
 751
 752 enum
 753 {
 754   MOD_8D = 0,
 755   MOD_C6_REG_7,
 756   MOD_C7_REG_7,
 757   MOD_FF_REG_3,
 758   MOD_FF_REG_5,
 759   MOD_0F01_REG_0,
 760   MOD_0F01_REG_1,
 761   MOD_0F01_REG_2,
 762   MOD_0F01_REG_3,
 763   MOD_0F01_REG_5,
 764   MOD_0F01_REG_7,
 765   MOD_0F12_PREFIX_0,
 766   MOD_0F13,
 767   MOD_0F16_PREFIX_0,
 768   MOD_0F17,
 769   MOD_0F18_REG_0,
 770   MOD_0F18_REG_1,
 771   MOD_0F18_REG_2,
 772   MOD_0F18_REG_3,
 773   MOD_0F18_REG_4,
 774   MOD_0F18_REG_5,
 775   MOD_0F18_REG_6,
 776   MOD_0F18_REG_7,
 777   MOD_0F1A_PREFIX_0,
 778   MOD_0F1B_PREFIX_0,
 779   MOD_0F1B_PREFIX_1,
 780   MOD_0F24,
 781   MOD_0F26,
 782   MOD_0F2B_PREFIX_0,
 783   MOD_0F2B_PREFIX_1,
 784   MOD_0F2B_PREFIX_2,
 785   MOD_0F2B_PREFIX_3,
 786   MOD_0F51,
 787   MOD_0F71_REG_2,
 788   MOD_0F71_REG_4,
 789   MOD_0F71_REG_6,
 790   MOD_0F72_REG_2,
 791   MOD_0F72_REG_4,
 792   MOD_0F72_REG_6,
 793   MOD_0F73_REG_2,
 794   MOD_0F73_REG_3,
 795   MOD_0F73_REG_6,
 796   MOD_0F73_REG_7,
 797   MOD_0FAE_REG_0,
 798   MOD_0FAE_REG_1,
 799   MOD_0FAE_REG_2,
 800   MOD_0FAE_REG_3,
 801   MOD_0FAE_REG_4,
 802   MOD_0FAE_REG_5,
 803   MOD_0FAE_REG_6,
 804   MOD_0FAE_REG_7,
 805   MOD_0FB2,
 806   MOD_0FB4,
 807   MOD_0FB5,
 808   MOD_0FC3,
 809   MOD_0FC7_REG_3,
 810   MOD_0FC7_REG_4,
 811   MOD_0FC7_REG_5,
 812   MOD_0FC7_REG_6,
 813   MOD_0FC7_REG_7,
 814   MOD_0FD7,
 815   MOD_0FE7_PREFIX_2,
 816   MOD_0FF0_PREFIX_3,
 817   MOD_0F382A_PREFIX_2,
 818   MOD_62_32BIT,
 819   MOD_C4_32BIT,
 820   MOD_C5_32BIT,
 821   MOD_VEX_0F12_PREFIX_0,
 822   MOD_VEX_0F13,
 823   MOD_VEX_0F16_PREFIX_0,
 824   MOD_VEX_0F17,
 825   MOD_VEX_0F2B,
 826   MOD_VEX_W_0_0F41_P_0_LEN_1,
 827   MOD_VEX_W_1_0F41_P_0_LEN_1,
 828   MOD_VEX_W_0_0F41_P_2_LEN_1,
 829   MOD_VEX_W_1_0F41_P_2_LEN_1,
 830   MOD_VEX_W_0_0F42_P_0_LEN_1,
 831   MOD_VEX_W_1_0F42_P_0_LEN_1,
 832   MOD_VEX_W_0_0F42_P_2_LEN_1,
 833   MOD_VEX_W_1_0F42_P_2_LEN_1,
 834   MOD_VEX_W_0_0F44_P_0_LEN_1,
 835   MOD_VEX_W_1_0F44_P_0_LEN_1,
 836   MOD_VEX_W_0_0F44_P_2_LEN_1,
 837   MOD_VEX_W_1_0F44_P_2_LEN_1,
 838   MOD_VEX_W_0_0F45_P_0_LEN_1,
 839   MOD_VEX_W_1_0F45_P_0_LEN_1,
 840   MOD_VEX_W_0_0F45_P_2_LEN_1,
 841   MOD_VEX_W_1_0F45_P_2_LEN_1,
 842   MOD_VEX_W_0_0F46_P_0_LEN_1,
 843   MOD_VEX_W_1_0F46_P_0_LEN_1,
 844   MOD_VEX_W_0_0F46_P_2_LEN_1,
 845   MOD_VEX_W_1_0F46_P_2_LEN_1,
 846   MOD_VEX_W_0_0F47_P_0_LEN_1,
 847   MOD_VEX_W_1_0F47_P_0_LEN_1,
 848   MOD_VEX_W_0_0F47_P_2_LEN_1,
 849   MOD_VEX_W_1_0F47_P_2_LEN_1,
 850   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 851   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 852   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 853   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 854   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 855   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 856   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 857   MOD_VEX_0F50,
 858   MOD_VEX_0F71_REG_2,
 859   MOD_VEX_0F71_REG_4,
 860   MOD_VEX_0F71_REG_6,
 861   MOD_VEX_0F72_REG_2,
 862   MOD_VEX_0F72_REG_4,
 863   MOD_VEX_0F72_REG_6,
 864   MOD_VEX_0F73_REG_2,
 865   MOD_VEX_0F73_REG_3,
 866   MOD_VEX_0F73_REG_6,
 867   MOD_VEX_0F73_REG_7,
 868   MOD_VEX_W_0_0F91_P_0_LEN_0,
 869   MOD_VEX_W_1_0F91_P_0_LEN_0,
 870   MOD_VEX_W_0_0F91_P_2_LEN_0,
 871   MOD_VEX_W_1_0F91_P_2_LEN_0,
 872   MOD_VEX_W_0_0F92_P_0_LEN_0,
 873   MOD_VEX_W_0_0F92_P_2_LEN_0,
 874   MOD_VEX_W_0_0F92_P_3_LEN_0,
 875   MOD_VEX_W_1_0F92_P_3_LEN_0,
 876   MOD_VEX_W_0_0F93_P_0_LEN_0,
 877   MOD_VEX_W_0_0F93_P_2_LEN_0,
 878   MOD_VEX_W_0_0F93_P_3_LEN_0,
 879   MOD_VEX_W_1_0F93_P_3_LEN_0,
 880   MOD_VEX_W_0_0F98_P_0_LEN_0,
 881   MOD_VEX_W_1_0F98_P_0_LEN_0,
 882   MOD_VEX_W_0_0F98_P_2_LEN_0,
 883   MOD_VEX_W_1_0F98_P_2_LEN_0,
 884   MOD_VEX_W_0_0F99_P_0_LEN_0,
 885   MOD_VEX_W_1_0F99_P_0_LEN_0,
 886   MOD_VEX_W_0_0F99_P_2_LEN_0,
 887   MOD_VEX_W_1_0F99_P_2_LEN_0,
 888   MOD_VEX_0FAE_REG_2,
 889   MOD_VEX_0FAE_REG_3,
 890   MOD_VEX_0FD7_PREFIX_2,
 891   MOD_VEX_0FE7_PREFIX_2,
 892   MOD_VEX_0FF0_PREFIX_3,
 893   MOD_VEX_0F381A_PREFIX_2,
 894   MOD_VEX_0F382A_PREFIX_2,
 895   MOD_VEX_0F382C_PREFIX_2,
 896   MOD_VEX_0F382D_PREFIX_2,
 897   MOD_VEX_0F382E_PREFIX_2,
 898   MOD_VEX_0F382F_PREFIX_2,
 899   MOD_VEX_0F385A_PREFIX_2,
 900   MOD_VEX_0F388C_PREFIX_2,
 901   MOD_VEX_0F388E_PREFIX_2,
 902   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 903   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 904   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 905   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 906   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 907   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 908   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 909   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 910
 911   MOD_EVEX_0F10_PREFIX_1,
 912   MOD_EVEX_0F10_PREFIX_3,
 913   MOD_EVEX_0F11_PREFIX_1,
 914   MOD_EVEX_0F11_PREFIX_3,
 915   MOD_EVEX_0F12_PREFIX_0,
 916   MOD_EVEX_0F16_PREFIX_0,
 917   MOD_EVEX_0F38C6_REG_1,
 918   MOD_EVEX_0F38C6_REG_2,
 919   MOD_EVEX_0F38C6_REG_5,
 920   MOD_EVEX_0F38C6_REG_6,
 921   MOD_EVEX_0F38C7_REG_1,
 922   MOD_EVEX_0F38C7_REG_2,
 923   MOD_EVEX_0F38C7_REG_5,
 924   MOD_EVEX_0F38C7_REG_6
 925 };
 926
 927 enum
 928 {
 929   RM_C6_REG_7 = 0,
 930   RM_C7_REG_7,
 931   RM_0F01_REG_0,
 932   RM_0F01_REG_1,
 933   RM_0F01_REG_2,
 934   RM_0F01_REG_3,
 935   RM_0F01_REG_5,
 936   RM_0F01_REG_7,
 937   RM_0FAE_REG_5,
 938   RM_0FAE_REG_6,
 939   RM_0FAE_REG_7
 940 };
 941
 942 enum
 943 {
 944   PREFIX_90 = 0,
 945   PREFIX_0F10,
 946   PREFIX_0F11,
 947   PREFIX_0F12,
 948   PREFIX_0F16,
 949   PREFIX_0F1A,
 950   PREFIX_0F1B,
 951   PREFIX_0F2A,
 952   PREFIX_0F2B,
 953   PREFIX_0F2C,
 954   PREFIX_0F2D,
 955   PREFIX_0F2E,
 956   PREFIX_0F2F,
 957   PREFIX_0F51,
 958   PREFIX_0F52,
 959   PREFIX_0F53,
 960   PREFIX_0F58,
 961   PREFIX_0F59,
 962   PREFIX_0F5A,
 963   PREFIX_0F5B,
 964   PREFIX_0F5C,
 965   PREFIX_0F5D,
 966   PREFIX_0F5E,
 967   PREFIX_0F5F,
 968   PREFIX_0F60,
 969   PREFIX_0F61,
 970   PREFIX_0F62,
 971   PREFIX_0F6C,
 972   PREFIX_0F6D,
 973   PREFIX_0F6F,
 974   PREFIX_0F70,
 975   PREFIX_0F73_REG_3,
 976   PREFIX_0F73_REG_7,
 977   PREFIX_0F78,
 978   PREFIX_0F79,
 979   PREFIX_0F7C,
 980   PREFIX_0F7D,
 981   PREFIX_0F7E,
 982   PREFIX_0F7F,
 983   PREFIX_0FAE_REG_0,
 984   PREFIX_0FAE_REG_1,
 985   PREFIX_0FAE_REG_2,
 986   PREFIX_0FAE_REG_3,
 987   PREFIX_MOD_0_0FAE_REG_4,
 988   PREFIX_MOD_3_0FAE_REG_4,
 989   PREFIX_0FAE_REG_6,
 990   PREFIX_0FAE_REG_7,
 991   PREFIX_0FB8,
 992   PREFIX_0FBC,
 993   PREFIX_0FBD,
 994   PREFIX_0FC2,
 995   PREFIX_MOD_0_0FC3,
 996   PREFIX_MOD_0_0FC7_REG_6,
 997   PREFIX_MOD_3_0FC7_REG_6,
 998   PREFIX_MOD_3_0FC7_REG_7,
 999   PREFIX_0FD0,
1000   PREFIX_0FD6,
1001   PREFIX_0FE6,
1002   PREFIX_0FE7,
1003   PREFIX_0FF0,
1004   PREFIX_0FF7,
1005   PREFIX_0F3810,
1006   PREFIX_0F3814,
1007   PREFIX_0F3815,
1008   PREFIX_0F3817,
1009   PREFIX_0F3820,
1010   PREFIX_0F3821,
1011   PREFIX_0F3822,
1012   PREFIX_0F3823,
1013   PREFIX_0F3824,
1014   PREFIX_0F3825,
1015   PREFIX_0F3828,
1016   PREFIX_0F3829,
1017   PREFIX_0F382A,
1018   PREFIX_0F382B,
1019   PREFIX_0F3830,
1020   PREFIX_0F3831,
1021   PREFIX_0F3832,
1022   PREFIX_0F3833,
1023   PREFIX_0F3834,
1024   PREFIX_0F3835,
1025   PREFIX_0F3837,
1026   PREFIX_0F3838,
1027   PREFIX_0F3839,
1028   PREFIX_0F383A,
1029   PREFIX_0F383B,
1030   PREFIX_0F383C,
1031   PREFIX_0F383D,
1032   PREFIX_0F383E,
1033   PREFIX_0F383F,
1034   PREFIX_0F3840,
1035   PREFIX_0F3841,
1036   PREFIX_0F3880,
1037   PREFIX_0F3881,
1038   PREFIX_0F3882,
1039   PREFIX_0F38C8,
1040   PREFIX_0F38C9,
1041   PREFIX_0F38CA,
1042   PREFIX_0F38CB,
1043   PREFIX_0F38CC,
1044   PREFIX_0F38CD,
1045   PREFIX_0F38DB,
1046   PREFIX_0F38DC,
1047   PREFIX_0F38DD,
1048   PREFIX_0F38DE,
1049   PREFIX_0F38DF,
1050   PREFIX_0F38F0,
1051   PREFIX_0F38F1,
1052   PREFIX_0F38F6,
1053   PREFIX_0F3A08,
1054   PREFIX_0F3A09,
1055   PREFIX_0F3A0A,
1056   PREFIX_0F3A0B,
1057   PREFIX_0F3A0C,
1058   PREFIX_0F3A0D,
1059   PREFIX_0F3A0E,
1060   PREFIX_0F3A14,
1061   PREFIX_0F3A15,
1062   PREFIX_0F3A16,
1063   PREFIX_0F3A17,
1064   PREFIX_0F3A20,
1065   PREFIX_0F3A21,
1066   PREFIX_0F3A22,
1067   PREFIX_0F3A40,
1068   PREFIX_0F3A41,
1069   PREFIX_0F3A42,
1070   PREFIX_0F3A44,
1071   PREFIX_0F3A60,
1072   PREFIX_0F3A61,
1073   PREFIX_0F3A62,
1074   PREFIX_0F3A63,
1075   PREFIX_0F3ACC,
1076   PREFIX_0F3ADF,
1077   PREFIX_VEX_0F10,
1078   PREFIX_VEX_0F11,
1079   PREFIX_VEX_0F12,
1080   PREFIX_VEX_0F16,
1081   PREFIX_VEX_0F2A,
1082   PREFIX_VEX_0F2C,
1083   PREFIX_VEX_0F2D,
1084   PREFIX_VEX_0F2E,
1085   PREFIX_VEX_0F2F,
1086   PREFIX_VEX_0F41,
1087   PREFIX_VEX_0F42,
1088   PREFIX_VEX_0F44,
1089   PREFIX_VEX_0F45,
1090   PREFIX_VEX_0F46,
1091   PREFIX_VEX_0F47,
1092   PREFIX_VEX_0F4A,
1093   PREFIX_VEX_0F4B,
1094   PREFIX_VEX_0F51,
1095   PREFIX_VEX_0F52,
1096   PREFIX_VEX_0F53,
1097   PREFIX_VEX_0F58,
1098   PREFIX_VEX_0F59,
1099   PREFIX_VEX_0F5A,
1100   PREFIX_VEX_0F5B,
1101   PREFIX_VEX_0F5C,
1102   PREFIX_VEX_0F5D,
1103   PREFIX_VEX_0F5E,
1104   PREFIX_VEX_0F5F,
1105   PREFIX_VEX_0F60,
1106   PREFIX_VEX_0F61,
1107   PREFIX_VEX_0F62,
1108   PREFIX_VEX_0F63,
1109   PREFIX_VEX_0F64,
1110   PREFIX_VEX_0F65,
1111   PREFIX_VEX_0F66,
1112   PREFIX_VEX_0F67,
1113   PREFIX_VEX_0F68,
1114   PREFIX_VEX_0F69,
1115   PREFIX_VEX_0F6A,
1116   PREFIX_VEX_0F6B,
1117   PREFIX_VEX_0F6C,
1118   PREFIX_VEX_0F6D,
1119   PREFIX_VEX_0F6E,
1120   PREFIX_VEX_0F6F,
1121   PREFIX_VEX_0F70,
1122   PREFIX_VEX_0F71_REG_2,
1123   PREFIX_VEX_0F71_REG_4,
1124   PREFIX_VEX_0F71_REG_6,
1125   PREFIX_VEX_0F72_REG_2,
1126   PREFIX_VEX_0F72_REG_4,
1127   PREFIX_VEX_0F72_REG_6,
1128   PREFIX_VEX_0F73_REG_2,
1129   PREFIX_VEX_0F73_REG_3,
1130   PREFIX_VEX_0F73_REG_6,
1131   PREFIX_VEX_0F73_REG_7,
1132   PREFIX_VEX_0F74,
1133   PREFIX_VEX_0F75,
1134   PREFIX_VEX_0F76,
1135   PREFIX_VEX_0F77,
1136   PREFIX_VEX_0F7C,
1137   PREFIX_VEX_0F7D,
1138   PREFIX_VEX_0F7E,
1139   PREFIX_VEX_0F7F,
1140   PREFIX_VEX_0F90,
1141   PREFIX_VEX_0F91,
1142   PREFIX_VEX_0F92,
1143   PREFIX_VEX_0F93,
1144   PREFIX_VEX_0F98,
1145   PREFIX_VEX_0F99,
1146   PREFIX_VEX_0FC2,
1147   PREFIX_VEX_0FC4,
1148   PREFIX_VEX_0FC5,
1149   PREFIX_VEX_0FD0,
1150   PREFIX_VEX_0FD1,
1151   PREFIX_VEX_0FD2,
1152   PREFIX_VEX_0FD3,
1153   PREFIX_VEX_0FD4,
1154   PREFIX_VEX_0FD5,
1155   PREFIX_VEX_0FD6,
1156   PREFIX_VEX_0FD7,
1157   PREFIX_VEX_0FD8,
1158   PREFIX_VEX_0FD9,
1159   PREFIX_VEX_0FDA,
1160   PREFIX_VEX_0FDB,
1161   PREFIX_VEX_0FDC,
1162   PREFIX_VEX_0FDD,
1163   PREFIX_VEX_0FDE,
1164   PREFIX_VEX_0FDF,
1165   PREFIX_VEX_0FE0,
1166   PREFIX_VEX_0FE1,
1167   PREFIX_VEX_0FE2,
1168   PREFIX_VEX_0FE3,
1169   PREFIX_VEX_0FE4,
1170   PREFIX_VEX_0FE5,
1171   PREFIX_VEX_0FE6,
1172   PREFIX_VEX_0FE7,
1173   PREFIX_VEX_0FE8,
1174   PREFIX_VEX_0FE9,
1175   PREFIX_VEX_0FEA,
1176   PREFIX_VEX_0FEB,
1177   PREFIX_VEX_0FEC,
1178   PREFIX_VEX_0FED,
1179   PREFIX_VEX_0FEE,
1180   PREFIX_VEX_0FEF,
1181   PREFIX_VEX_0FF0,
1182   PREFIX_VEX_0FF1,
1183   PREFIX_VEX_0FF2,
1184   PREFIX_VEX_0FF3,
1185   PREFIX_VEX_0FF4,
1186   PREFIX_VEX_0FF5,
1187   PREFIX_VEX_0FF6,
1188   PREFIX_VEX_0FF7,
1189   PREFIX_VEX_0FF8,
1190   PREFIX_VEX_0FF9,
1191   PREFIX_VEX_0FFA,
1192   PREFIX_VEX_0FFB,
1193   PREFIX_VEX_0FFC,
1194   PREFIX_VEX_0FFD,
1195   PREFIX_VEX_0FFE,
1196   PREFIX_VEX_0F3800,
1197   PREFIX_VEX_0F3801,
1198   PREFIX_VEX_0F3802,
1199   PREFIX_VEX_0F3803,
1200   PREFIX_VEX_0F3804,
1201   PREFIX_VEX_0F3805,
1202   PREFIX_VEX_0F3806,
1203   PREFIX_VEX_0F3807,
1204   PREFIX_VEX_0F3808,
1205   PREFIX_VEX_0F3809,
1206   PREFIX_VEX_0F380A,
1207   PREFIX_VEX_0F380B,
1208   PREFIX_VEX_0F380C,
1209   PREFIX_VEX_0F380D,
1210   PREFIX_VEX_0F380E,
1211   PREFIX_VEX_0F380F,
1212   PREFIX_VEX_0F3813,
1213   PREFIX_VEX_0F3816,
1214   PREFIX_VEX_0F3817,
1215   PREFIX_VEX_0F3818,
1216   PREFIX_VEX_0F3819,
1217   PREFIX_VEX_0F381A,
1218   PREFIX_VEX_0F381C,
1219   PREFIX_VEX_0F381D,
1220   PREFIX_VEX_0F381E,
1221   PREFIX_VEX_0F3820,
1222   PREFIX_VEX_0F3821,
1223   PREFIX_VEX_0F3822,
1224   PREFIX_VEX_0F3823,
1225   PREFIX_VEX_0F3824,
1226   PREFIX_VEX_0F3825,
1227   PREFIX_VEX_0F3828,
1228   PREFIX_VEX_0F3829,
1229   PREFIX_VEX_0F382A,
1230   PREFIX_VEX_0F382B,
1231   PREFIX_VEX_0F382C,
1232   PREFIX_VEX_0F382D,
1233   PREFIX_VEX_0F382E,
1234   PREFIX_VEX_0F382F,
1235   PREFIX_VEX_0F3830,
1236   PREFIX_VEX_0F3831,
1237   PREFIX_VEX_0F3832,
1238   PREFIX_VEX_0F3833,
1239   PREFIX_VEX_0F3834,
1240   PREFIX_VEX_0F3835,
1241   PREFIX_VEX_0F3836,
1242   PREFIX_VEX_0F3837,
1243   PREFIX_VEX_0F3838,
1244   PREFIX_VEX_0F3839,
1245   PREFIX_VEX_0F383A,
1246   PREFIX_VEX_0F383B,
1247   PREFIX_VEX_0F383C,
1248   PREFIX_VEX_0F383D,
1249   PREFIX_VEX_0F383E,
1250   PREFIX_VEX_0F383F,
1251   PREFIX_VEX_0F3840,
1252   PREFIX_VEX_0F3841,
1253   PREFIX_VEX_0F3845,
1254   PREFIX_VEX_0F3846,
1255   PREFIX_VEX_0F3847,
1256   PREFIX_VEX_0F3858,
1257   PREFIX_VEX_0F3859,
1258   PREFIX_VEX_0F385A,
1259   PREFIX_VEX_0F3878,
1260   PREFIX_VEX_0F3879,
1261   PREFIX_VEX_0F388C,
1262   PREFIX_VEX_0F388E,
1263   PREFIX_VEX_0F3890,
1264   PREFIX_VEX_0F3891,
1265   PREFIX_VEX_0F3892,
1266   PREFIX_VEX_0F3893,
1267   PREFIX_VEX_0F3896,
1268   PREFIX_VEX_0F3897,
1269   PREFIX_VEX_0F3898,
1270   PREFIX_VEX_0F3899,
1271   PREFIX_VEX_0F389A,
1272   PREFIX_VEX_0F389B,
1273   PREFIX_VEX_0F389C,
1274   PREFIX_VEX_0F389D,
1275   PREFIX_VEX_0F389E,
1276   PREFIX_VEX_0F389F,
1277   PREFIX_VEX_0F38A6,
1278   PREFIX_VEX_0F38A7,
1279   PREFIX_VEX_0F38A8,
1280   PREFIX_VEX_0F38A9,
1281   PREFIX_VEX_0F38AA,
1282   PREFIX_VEX_0F38AB,
1283   PREFIX_VEX_0F38AC,
1284   PREFIX_VEX_0F38AD,
1285   PREFIX_VEX_0F38AE,
1286   PREFIX_VEX_0F38AF,
1287   PREFIX_VEX_0F38B6,
1288   PREFIX_VEX_0F38B7,
1289   PREFIX_VEX_0F38B8,
1290   PREFIX_VEX_0F38B9,
1291   PREFIX_VEX_0F38BA,
1292   PREFIX_VEX_0F38BB,
1293   PREFIX_VEX_0F38BC,
1294   PREFIX_VEX_0F38BD,
1295   PREFIX_VEX_0F38BE,
1296   PREFIX_VEX_0F38BF,
1297   PREFIX_VEX_0F38DB,
1298   PREFIX_VEX_0F38DC,
1299   PREFIX_VEX_0F38DD,
1300   PREFIX_VEX_0F38DE,
1301   PREFIX_VEX_0F38DF,
1302   PREFIX_VEX_0F38F2,
1303   PREFIX_VEX_0F38F3_REG_1,
1304   PREFIX_VEX_0F38F3_REG_2,
1305   PREFIX_VEX_0F38F3_REG_3,
1306   PREFIX_VEX_0F38F5,
1307   PREFIX_VEX_0F38F6,
1308   PREFIX_VEX_0F38F7,
1309   PREFIX_VEX_0F3A00,
1310   PREFIX_VEX_0F3A01,
1311   PREFIX_VEX_0F3A02,
1312   PREFIX_VEX_0F3A04,
1313   PREFIX_VEX_0F3A05,
1314   PREFIX_VEX_0F3A06,
1315   PREFIX_VEX_0F3A08,
1316   PREFIX_VEX_0F3A09,
1317   PREFIX_VEX_0F3A0A,
1318   PREFIX_VEX_0F3A0B,
1319   PREFIX_VEX_0F3A0C,
1320   PREFIX_VEX_0F3A0D,
1321   PREFIX_VEX_0F3A0E,
1322   PREFIX_VEX_0F3A0F,
1323   PREFIX_VEX_0F3A14,
1324   PREFIX_VEX_0F3A15,
1325   PREFIX_VEX_0F3A16,
1326   PREFIX_VEX_0F3A17,
1327   PREFIX_VEX_0F3A18,
1328   PREFIX_VEX_0F3A19,
1329   PREFIX_VEX_0F3A1D,
1330   PREFIX_VEX_0F3A20,
1331   PREFIX_VEX_0F3A21,
1332   PREFIX_VEX_0F3A22,
1333   PREFIX_VEX_0F3A30,
1334   PREFIX_VEX_0F3A31,
1335   PREFIX_VEX_0F3A32,
1336   PREFIX_VEX_0F3A33,
1337   PREFIX_VEX_0F3A38,
1338   PREFIX_VEX_0F3A39,
1339   PREFIX_VEX_0F3A40,
1340   PREFIX_VEX_0F3A41,
1341   PREFIX_VEX_0F3A42,
1342   PREFIX_VEX_0F3A44,
1343   PREFIX_VEX_0F3A46,
1344   PREFIX_VEX_0F3A48,
1345   PREFIX_VEX_0F3A49,
1346   PREFIX_VEX_0F3A4A,
1347   PREFIX_VEX_0F3A4B,
1348   PREFIX_VEX_0F3A4C,
1349   PREFIX_VEX_0F3A5C,
1350   PREFIX_VEX_0F3A5D,
1351   PREFIX_VEX_0F3A5E,
1352   PREFIX_VEX_0F3A5F,
1353   PREFIX_VEX_0F3A60,
1354   PREFIX_VEX_0F3A61,
1355   PREFIX_VEX_0F3A62,
1356   PREFIX_VEX_0F3A63,
1357   PREFIX_VEX_0F3A68,
1358   PREFIX_VEX_0F3A69,
1359   PREFIX_VEX_0F3A6A,
1360   PREFIX_VEX_0F3A6B,
1361   PREFIX_VEX_0F3A6C,
1362   PREFIX_VEX_0F3A6D,
1363   PREFIX_VEX_0F3A6E,
1364   PREFIX_VEX_0F3A6F,
1365   PREFIX_VEX_0F3A78,
1366   PREFIX_VEX_0F3A79,
1367   PREFIX_VEX_0F3A7A,
1368   PREFIX_VEX_0F3A7B,
1369   PREFIX_VEX_0F3A7C,
1370   PREFIX_VEX_0F3A7D,
1371   PREFIX_VEX_0F3A7E,
1372   PREFIX_VEX_0F3A7F,
1373   PREFIX_VEX_0F3ADF,
1374   PREFIX_VEX_0F3AF0,
1375
1376   PREFIX_EVEX_0F10,
1377   PREFIX_EVEX_0F11,
1378   PREFIX_EVEX_0F12,
1379   PREFIX_EVEX_0F13,
1380   PREFIX_EVEX_0F14,
1381   PREFIX_EVEX_0F15,
1382   PREFIX_EVEX_0F16,
1383   PREFIX_EVEX_0F17,
1384   PREFIX_EVEX_0F28,
1385   PREFIX_EVEX_0F29,
1386   PREFIX_EVEX_0F2A,
1387   PREFIX_EVEX_0F2B,
1388   PREFIX_EVEX_0F2C,
1389   PREFIX_EVEX_0F2D,
1390   PREFIX_EVEX_0F2E,
1391   PREFIX_EVEX_0F2F,
1392   PREFIX_EVEX_0F51,
1393   PREFIX_EVEX_0F54,
1394   PREFIX_EVEX_0F55,
1395   PREFIX_EVEX_0F56,
1396   PREFIX_EVEX_0F57,
1397   PREFIX_EVEX_0F58,
1398   PREFIX_EVEX_0F59,
1399   PREFIX_EVEX_0F5A,
1400   PREFIX_EVEX_0F5B,
1401   PREFIX_EVEX_0F5C,
1402   PREFIX_EVEX_0F5D,
1403   PREFIX_EVEX_0F5E,
1404   PREFIX_EVEX_0F5F,
1405   PREFIX_EVEX_0F60,
1406   PREFIX_EVEX_0F61,
1407   PREFIX_EVEX_0F62,
1408   PREFIX_EVEX_0F63,
1409   PREFIX_EVEX_0F64,
1410   PREFIX_EVEX_0F65,
1411   PREFIX_EVEX_0F66,
1412   PREFIX_EVEX_0F67,
1413   PREFIX_EVEX_0F68,
1414   PREFIX_EVEX_0F69,
1415   PREFIX_EVEX_0F6A,
1416   PREFIX_EVEX_0F6B,
1417   PREFIX_EVEX_0F6C,
1418   PREFIX_EVEX_0F6D,
1419   PREFIX_EVEX_0F6E,
1420   PREFIX_EVEX_0F6F,
1421   PREFIX_EVEX_0F70,
1422   PREFIX_EVEX_0F71_REG_2,
1423   PREFIX_EVEX_0F71_REG_4,
1424   PREFIX_EVEX_0F71_REG_6,
1425   PREFIX_EVEX_0F72_REG_0,
1426   PREFIX_EVEX_0F72_REG_1,
1427   PREFIX_EVEX_0F72_REG_2,
1428   PREFIX_EVEX_0F72_REG_4,
1429   PREFIX_EVEX_0F72_REG_6,
1430   PREFIX_EVEX_0F73_REG_2,
1431   PREFIX_EVEX_0F73_REG_3,
1432   PREFIX_EVEX_0F73_REG_6,
1433   PREFIX_EVEX_0F73_REG_7,
1434   PREFIX_EVEX_0F74,
1435   PREFIX_EVEX_0F75,
1436   PREFIX_EVEX_0F76,
1437   PREFIX_EVEX_0F78,
1438   PREFIX_EVEX_0F79,
1439   PREFIX_EVEX_0F7A,
1440   PREFIX_EVEX_0F7B,
1441   PREFIX_EVEX_0F7E,
1442   PREFIX_EVEX_0F7F,
1443   PREFIX_EVEX_0FC2,
1444   PREFIX_EVEX_0FC4,
1445   PREFIX_EVEX_0FC5,
1446   PREFIX_EVEX_0FC6,
1447   PREFIX_EVEX_0FD1,
1448   PREFIX_EVEX_0FD2,
1449   PREFIX_EVEX_0FD3,
1450   PREFIX_EVEX_0FD4,
1451   PREFIX_EVEX_0FD5,
1452   PREFIX_EVEX_0FD6,
1453   PREFIX_EVEX_0FD8,
1454   PREFIX_EVEX_0FD9,
1455   PREFIX_EVEX_0FDA,
1456   PREFIX_EVEX_0FDB,
1457   PREFIX_EVEX_0FDC,
1458   PREFIX_EVEX_0FDD,
1459   PREFIX_EVEX_0FDE,
1460   PREFIX_EVEX_0FDF,
1461   PREFIX_EVEX_0FE0,
1462   PREFIX_EVEX_0FE1,
1463   PREFIX_EVEX_0FE2,
1464   PREFIX_EVEX_0FE3,
1465   PREFIX_EVEX_0FE4,
1466   PREFIX_EVEX_0FE5,
1467   PREFIX_EVEX_0FE6,
1468   PREFIX_EVEX_0FE7,
1469   PREFIX_EVEX_0FE8,
1470   PREFIX_EVEX_0FE9,
1471   PREFIX_EVEX_0FEA,
1472   PREFIX_EVEX_0FEB,
1473   PREFIX_EVEX_0FEC,
1474   PREFIX_EVEX_0FED,
1475   PREFIX_EVEX_0FEE,
1476   PREFIX_EVEX_0FEF,
1477   PREFIX_EVEX_0FF1,
1478   PREFIX_EVEX_0FF2,
1479   PREFIX_EVEX_0FF3,
1480   PREFIX_EVEX_0FF4,
1481   PREFIX_EVEX_0FF5,
1482   PREFIX_EVEX_0FF6,
1483   PREFIX_EVEX_0FF8,
1484   PREFIX_EVEX_0FF9,
1485   PREFIX_EVEX_0FFA,
1486   PREFIX_EVEX_0FFB,
1487   PREFIX_EVEX_0FFC,
1488   PREFIX_EVEX_0FFD,
1489   PREFIX_EVEX_0FFE,
1490   PREFIX_EVEX_0F3800,
1491   PREFIX_EVEX_0F3804,
1492   PREFIX_EVEX_0F380B,
1493   PREFIX_EVEX_0F380C,
1494   PREFIX_EVEX_0F380D,
1495   PREFIX_EVEX_0F3810,
1496   PREFIX_EVEX_0F3811,
1497   PREFIX_EVEX_0F3812,
1498   PREFIX_EVEX_0F3813,
1499   PREFIX_EVEX_0F3814,
1500   PREFIX_EVEX_0F3815,
1501   PREFIX_EVEX_0F3816,
1502   PREFIX_EVEX_0F3818,
1503   PREFIX_EVEX_0F3819,
1504   PREFIX_EVEX_0F381A,
1505   PREFIX_EVEX_0F381B,
1506   PREFIX_EVEX_0F381C,
1507   PREFIX_EVEX_0F381D,
1508   PREFIX_EVEX_0F381E,
1509   PREFIX_EVEX_0F381F,
1510   PREFIX_EVEX_0F3820,
1511   PREFIX_EVEX_0F3821,
1512   PREFIX_EVEX_0F3822,
1513   PREFIX_EVEX_0F3823,
1514   PREFIX_EVEX_0F3824,
1515   PREFIX_EVEX_0F3825,
1516   PREFIX_EVEX_0F3826,
1517   PREFIX_EVEX_0F3827,
1518   PREFIX_EVEX_0F3828,
1519   PREFIX_EVEX_0F3829,
1520   PREFIX_EVEX_0F382A,
1521   PREFIX_EVEX_0F382B,
1522   PREFIX_EVEX_0F382C,
1523   PREFIX_EVEX_0F382D,
1524   PREFIX_EVEX_0F3830,
1525   PREFIX_EVEX_0F3831,
1526   PREFIX_EVEX_0F3832,
1527   PREFIX_EVEX_0F3833,
1528   PREFIX_EVEX_0F3834,
1529   PREFIX_EVEX_0F3835,
1530   PREFIX_EVEX_0F3836,
1531   PREFIX_EVEX_0F3837,
1532   PREFIX_EVEX_0F3838,
1533   PREFIX_EVEX_0F3839,
1534   PREFIX_EVEX_0F383A,
1535   PREFIX_EVEX_0F383B,
1536   PREFIX_EVEX_0F383C,
1537   PREFIX_EVEX_0F383D,
1538   PREFIX_EVEX_0F383E,
1539   PREFIX_EVEX_0F383F,
1540   PREFIX_EVEX_0F3840,
1541   PREFIX_EVEX_0F3842,
1542   PREFIX_EVEX_0F3843,
1543   PREFIX_EVEX_0F3844,
1544   PREFIX_EVEX_0F3845,
1545   PREFIX_EVEX_0F3846,
1546   PREFIX_EVEX_0F3847,
1547   PREFIX_EVEX_0F384C,
1548   PREFIX_EVEX_0F384D,
1549   PREFIX_EVEX_0F384E,
1550   PREFIX_EVEX_0F384F,
1551   PREFIX_EVEX_0F3852,
1552   PREFIX_EVEX_0F3853,
1553   PREFIX_EVEX_0F3858,
1554   PREFIX_EVEX_0F3859,
1555   PREFIX_EVEX_0F385A,
1556   PREFIX_EVEX_0F385B,
1557   PREFIX_EVEX_0F3864,
1558   PREFIX_EVEX_0F3865,
1559   PREFIX_EVEX_0F3866,
1560   PREFIX_EVEX_0F3875,
1561   PREFIX_EVEX_0F3876,
1562   PREFIX_EVEX_0F3877,
1563   PREFIX_EVEX_0F3878,
1564   PREFIX_EVEX_0F3879,
1565   PREFIX_EVEX_0F387A,
1566   PREFIX_EVEX_0F387B,
1567   PREFIX_EVEX_0F387C,
1568   PREFIX_EVEX_0F387D,
1569   PREFIX_EVEX_0F387E,
1570   PREFIX_EVEX_0F387F,
1571   PREFIX_EVEX_0F3883,
1572   PREFIX_EVEX_0F3888,
1573   PREFIX_EVEX_0F3889,
1574   PREFIX_EVEX_0F388A,
1575   PREFIX_EVEX_0F388B,
1576   PREFIX_EVEX_0F388D,
1577   PREFIX_EVEX_0F3890,
1578   PREFIX_EVEX_0F3891,
1579   PREFIX_EVEX_0F3892,
1580   PREFIX_EVEX_0F3893,
1581   PREFIX_EVEX_0F3896,
1582   PREFIX_EVEX_0F3897,
1583   PREFIX_EVEX_0F3898,
1584   PREFIX_EVEX_0F3899,
1585   PREFIX_EVEX_0F389A,
1586   PREFIX_EVEX_0F389B,
1587   PREFIX_EVEX_0F389C,
1588   PREFIX_EVEX_0F389D,
1589   PREFIX_EVEX_0F389E,
1590   PREFIX_EVEX_0F389F,
1591   PREFIX_EVEX_0F38A0,
1592   PREFIX_EVEX_0F38A1,
1593   PREFIX_EVEX_0F38A2,
1594   PREFIX_EVEX_0F38A3,
1595   PREFIX_EVEX_0F38A6,
1596   PREFIX_EVEX_0F38A7,
1597   PREFIX_EVEX_0F38A8,
1598   PREFIX_EVEX_0F38A9,
1599   PREFIX_EVEX_0F38AA,
1600   PREFIX_EVEX_0F38AB,
1601   PREFIX_EVEX_0F38AC,
1602   PREFIX_EVEX_0F38AD,
1603   PREFIX_EVEX_0F38AE,
1604   PREFIX_EVEX_0F38AF,
1605   PREFIX_EVEX_0F38B4,
1606   PREFIX_EVEX_0F38B5,
1607   PREFIX_EVEX_0F38B6,
1608   PREFIX_EVEX_0F38B7,
1609   PREFIX_EVEX_0F38B8,
1610   PREFIX_EVEX_0F38B9,
1611   PREFIX_EVEX_0F38BA,
1612   PREFIX_EVEX_0F38BB,
1613   PREFIX_EVEX_0F38BC,
1614   PREFIX_EVEX_0F38BD,
1615   PREFIX_EVEX_0F38BE,
1616   PREFIX_EVEX_0F38BF,
1617   PREFIX_EVEX_0F38C4,
1618   PREFIX_EVEX_0F38C6_REG_1,
1619   PREFIX_EVEX_0F38C6_REG_2,
1620   PREFIX_EVEX_0F38C6_REG_5,
1621   PREFIX_EVEX_0F38C6_REG_6,
1622   PREFIX_EVEX_0F38C7_REG_1,
1623   PREFIX_EVEX_0F38C7_REG_2,
1624   PREFIX_EVEX_0F38C7_REG_5,
1625   PREFIX_EVEX_0F38C7_REG_6,
1626   PREFIX_EVEX_0F38C8,
1627   PREFIX_EVEX_0F38CA,
1628   PREFIX_EVEX_0F38CB,
1629   PREFIX_EVEX_0F38CC,
1630   PREFIX_EVEX_0F38CD,
1631
1632   PREFIX_EVEX_0F3A00,
1633   PREFIX_EVEX_0F3A01,
1634   PREFIX_EVEX_0F3A03,
1635   PREFIX_EVEX_0F3A04,
1636   PREFIX_EVEX_0F3A05,
1637   PREFIX_EVEX_0F3A08,
1638   PREFIX_EVEX_0F3A09,
1639   PREFIX_EVEX_0F3A0A,
1640   PREFIX_EVEX_0F3A0B,
1641   PREFIX_EVEX_0F3A0F,
1642   PREFIX_EVEX_0F3A14,
1643   PREFIX_EVEX_0F3A15,
1644   PREFIX_EVEX_0F3A16,
1645   PREFIX_EVEX_0F3A17,
1646   PREFIX_EVEX_0F3A18,
1647   PREFIX_EVEX_0F3A19,
1648   PREFIX_EVEX_0F3A1A,
1649   PREFIX_EVEX_0F3A1B,
1650   PREFIX_EVEX_0F3A1D,
1651   PREFIX_EVEX_0F3A1E,
1652   PREFIX_EVEX_0F3A1F,
1653   PREFIX_EVEX_0F3A20,
1654   PREFIX_EVEX_0F3A21,
1655   PREFIX_EVEX_0F3A22,
1656   PREFIX_EVEX_0F3A23,
1657   PREFIX_EVEX_0F3A25,
1658   PREFIX_EVEX_0F3A26,
1659   PREFIX_EVEX_0F3A27,
1660   PREFIX_EVEX_0F3A38,
1661   PREFIX_EVEX_0F3A39,
1662   PREFIX_EVEX_0F3A3A,
1663   PREFIX_EVEX_0F3A3B,
1664   PREFIX_EVEX_0F3A3E,
1665   PREFIX_EVEX_0F3A3F,
1666   PREFIX_EVEX_0F3A42,
1667   PREFIX_EVEX_0F3A43,
1668   PREFIX_EVEX_0F3A50,
1669   PREFIX_EVEX_0F3A51,
1670   PREFIX_EVEX_0F3A54,
1671   PREFIX_EVEX_0F3A55,
1672   PREFIX_EVEX_0F3A56,
1673   PREFIX_EVEX_0F3A57,
1674   PREFIX_EVEX_0F3A66,
1675   PREFIX_EVEX_0F3A67
1676 };
1677
1678 enum
1679 {
1680   X86_64_06 = 0,
1681   X86_64_07,
1682   X86_64_0D,
1683   X86_64_16,
1684   X86_64_17,
1685   X86_64_1E,
1686   X86_64_1F,
1687   X86_64_27,
1688   X86_64_2F,
1689   X86_64_37,
1690   X86_64_3F,
1691   X86_64_60,
1692   X86_64_61,
1693   X86_64_62,
1694   X86_64_63,
1695   X86_64_6D,
1696   X86_64_6F,
1697   X86_64_82,
1698   X86_64_9A,
1699   X86_64_C4,
1700   X86_64_C5,
1701   X86_64_CE,
1702   X86_64_D4,
1703   X86_64_D5,
1704   X86_64_E8,
1705   X86_64_E9,
1706   X86_64_EA,
1707   X86_64_0F01_REG_0,
1708   X86_64_0F01_REG_1,
1709   X86_64_0F01_REG_2,
1710   X86_64_0F01_REG_3
1711 };
1712
1713 enum
1714 {
1715   THREE_BYTE_0F38 = 0,
1716   THREE_BYTE_0F3A,
1717   THREE_BYTE_0F7A
1718 };
1719
1720 enum
1721 {
1722   XOP_08 = 0,
1723   XOP_09,
1724   XOP_0A
1725 };
1726
1727 enum
1728 {
1729   VEX_0F = 0,
1730   VEX_0F38,
1731   VEX_0F3A
1732 };
1733
1734 enum
1735 {
1736   EVEX_0F = 0,
1737   EVEX_0F38,
1738   EVEX_0F3A
1739 };
1740
1741 enum
1742 {
1743   VEX_LEN_0F10_P_1 = 0,
1744   VEX_LEN_0F10_P_3,
1745   VEX_LEN_0F11_P_1,
1746   VEX_LEN_0F11_P_3,
1747   VEX_LEN_0F12_P_0_M_0,
1748   VEX_LEN_0F12_P_0_M_1,
1749   VEX_LEN_0F12_P_2,
1750   VEX_LEN_0F13_M_0,
1751   VEX_LEN_0F16_P_0_M_0,
1752   VEX_LEN_0F16_P_0_M_1,
1753   VEX_LEN_0F16_P_2,
1754   VEX_LEN_0F17_M_0,
1755   VEX_LEN_0F2A_P_1,
1756   VEX_LEN_0F2A_P_3,
1757   VEX_LEN_0F2C_P_1,
1758   VEX_LEN_0F2C_P_3,
1759   VEX_LEN_0F2D_P_1,
1760   VEX_LEN_0F2D_P_3,
1761   VEX_LEN_0F2E_P_0,
1762   VEX_LEN_0F2E_P_2,
1763   VEX_LEN_0F2F_P_0,
1764   VEX_LEN_0F2F_P_2,
1765   VEX_LEN_0F41_P_0,
1766   VEX_LEN_0F41_P_2,
1767   VEX_LEN_0F42_P_0,
1768   VEX_LEN_0F42_P_2,
1769   VEX_LEN_0F44_P_0,
1770   VEX_LEN_0F44_P_2,
1771   VEX_LEN_0F45_P_0,
1772   VEX_LEN_0F45_P_2,
1773   VEX_LEN_0F46_P_0,
1774   VEX_LEN_0F46_P_2,
1775   VEX_LEN_0F47_P_0,
1776   VEX_LEN_0F47_P_2,
1777   VEX_LEN_0F4A_P_0,
1778   VEX_LEN_0F4A_P_2,
1779   VEX_LEN_0F4B_P_0,
1780   VEX_LEN_0F4B_P_2,
1781   VEX_LEN_0F51_P_1,
1782   VEX_LEN_0F51_P_3,
1783   VEX_LEN_0F52_P_1,
1784   VEX_LEN_0F53_P_1,
1785   VEX_LEN_0F58_P_1,
1786   VEX_LEN_0F58_P_3,
1787   VEX_LEN_0F59_P_1,
1788   VEX_LEN_0F59_P_3,
1789   VEX_LEN_0F5A_P_1,
1790   VEX_LEN_0F5A_P_3,
1791   VEX_LEN_0F5C_P_1,
1792   VEX_LEN_0F5C_P_3,
1793   VEX_LEN_0F5D_P_1,
1794   VEX_LEN_0F5D_P_3,
1795   VEX_LEN_0F5E_P_1,
1796   VEX_LEN_0F5E_P_3,
1797   VEX_LEN_0F5F_P_1,
1798   VEX_LEN_0F5F_P_3,
1799   VEX_LEN_0F6E_P_2,
1800   VEX_LEN_0F7E_P_1,
1801   VEX_LEN_0F7E_P_2,
1802   VEX_LEN_0F90_P_0,
1803   VEX_LEN_0F90_P_2,
1804   VEX_LEN_0F91_P_0,
1805   VEX_LEN_0F91_P_2,
1806   VEX_LEN_0F92_P_0,
1807   VEX_LEN_0F92_P_2,
1808   VEX_LEN_0F92_P_3,
1809   VEX_LEN_0F93_P_0,
1810   VEX_LEN_0F93_P_2,
1811   VEX_LEN_0F93_P_3,
1812   VEX_LEN_0F98_P_0,
1813   VEX_LEN_0F98_P_2,
1814   VEX_LEN_0F99_P_0,
1815   VEX_LEN_0F99_P_2,
1816   VEX_LEN_0FAE_R_2_M_0,
1817   VEX_LEN_0FAE_R_3_M_0,
1818   VEX_LEN_0FC2_P_1,
1819   VEX_LEN_0FC2_P_3,
1820   VEX_LEN_0FC4_P_2,
1821   VEX_LEN_0FC5_P_2,
1822   VEX_LEN_0FD6_P_2,
1823   VEX_LEN_0FF7_P_2,
1824   VEX_LEN_0F3816_P_2,
1825   VEX_LEN_0F3819_P_2,
1826   VEX_LEN_0F381A_P_2_M_0,
1827   VEX_LEN_0F3836_P_2,
1828   VEX_LEN_0F3841_P_2,
1829   VEX_LEN_0F385A_P_2_M_0,
1830   VEX_LEN_0F38DB_P_2,
1831   VEX_LEN_0F38DC_P_2,
1832   VEX_LEN_0F38DD_P_2,
1833   VEX_LEN_0F38DE_P_2,
1834   VEX_LEN_0F38DF_P_2,
1835   VEX_LEN_0F38F2_P_0,
1836   VEX_LEN_0F38F3_R_1_P_0,
1837   VEX_LEN_0F38F3_R_2_P_0,
1838   VEX_LEN_0F38F3_R_3_P_0,
1839   VEX_LEN_0F38F5_P_0,
1840   VEX_LEN_0F38F5_P_1,
1841   VEX_LEN_0F38F5_P_3,
1842   VEX_LEN_0F38F6_P_3,
1843   VEX_LEN_0F38F7_P_0,
1844   VEX_LEN_0F38F7_P_1,
1845   VEX_LEN_0F38F7_P_2,
1846   VEX_LEN_0F38F7_P_3,
1847   VEX_LEN_0F3A00_P_2,
1848   VEX_LEN_0F3A01_P_2,
1849   VEX_LEN_0F3A06_P_2,
1850   VEX_LEN_0F3A0A_P_2,
1851   VEX_LEN_0F3A0B_P_2,
1852   VEX_LEN_0F3A14_P_2,
1853   VEX_LEN_0F3A15_P_2,
1854   VEX_LEN_0F3A16_P_2,
1855   VEX_LEN_0F3A17_P_2,
1856   VEX_LEN_0F3A18_P_2,
1857   VEX_LEN_0F3A19_P_2,
1858   VEX_LEN_0F3A20_P_2,
1859   VEX_LEN_0F3A21_P_2,
1860   VEX_LEN_0F3A22_P_2,
1861   VEX_LEN_0F3A30_P_2,
1862   VEX_LEN_0F3A31_P_2,
1863   VEX_LEN_0F3A32_P_2,
1864   VEX_LEN_0F3A33_P_2,
1865   VEX_LEN_0F3A38_P_2,
1866   VEX_LEN_0F3A39_P_2,
1867   VEX_LEN_0F3A41_P_2,
1868   VEX_LEN_0F3A44_P_2,
1869   VEX_LEN_0F3A46_P_2,
1870   VEX_LEN_0F3A60_P_2,
1871   VEX_LEN_0F3A61_P_2,
1872   VEX_LEN_0F3A62_P_2,
1873   VEX_LEN_0F3A63_P_2,
1874   VEX_LEN_0F3A6A_P_2,
1875   VEX_LEN_0F3A6B_P_2,
1876   VEX_LEN_0F3A6E_P_2,
1877   VEX_LEN_0F3A6F_P_2,
1878   VEX_LEN_0F3A7A_P_2,
1879   VEX_LEN_0F3A7B_P_2,
1880   VEX_LEN_0F3A7E_P_2,
1881   VEX_LEN_0F3A7F_P_2,
1882   VEX_LEN_0F3ADF_P_2,
1883   VEX_LEN_0F3AF0_P_3,
1884   VEX_LEN_0FXOP_08_CC,
1885   VEX_LEN_0FXOP_08_CD,
1886   VEX_LEN_0FXOP_08_CE,
1887   VEX_LEN_0FXOP_08_CF,
1888   VEX_LEN_0FXOP_08_EC,
1889   VEX_LEN_0FXOP_08_ED,
1890   VEX_LEN_0FXOP_08_EE,
1891   VEX_LEN_0FXOP_08_EF,
1892   VEX_LEN_0FXOP_09_80,
1893   VEX_LEN_0FXOP_09_81
1894 };
1895
1896 enum
1897 {
1898   VEX_W_0F10_P_0 = 0,
1899   VEX_W_0F10_P_1,
1900   VEX_W_0F10_P_2,
1901   VEX_W_0F10_P_3,
1902   VEX_W_0F11_P_0,
1903   VEX_W_0F11_P_1,
1904   VEX_W_0F11_P_2,
1905   VEX_W_0F11_P_3,
1906   VEX_W_0F12_P_0_M_0,
1907   VEX_W_0F12_P_0_M_1,
1908   VEX_W_0F12_P_1,
1909   VEX_W_0F12_P_2,
1910   VEX_W_0F12_P_3,
1911   VEX_W_0F13_M_0,
1912   VEX_W_0F14,
1913   VEX_W_0F15,
1914   VEX_W_0F16_P_0_M_0,
1915   VEX_W_0F16_P_0_M_1,
1916   VEX_W_0F16_P_1,
1917   VEX_W_0F16_P_2,
1918   VEX_W_0F17_M_0,
1919   VEX_W_0F28,
1920   VEX_W_0F29,
1921   VEX_W_0F2B_M_0,
1922   VEX_W_0F2E_P_0,
1923   VEX_W_0F2E_P_2,
1924   VEX_W_0F2F_P_0,
1925   VEX_W_0F2F_P_2,
1926   VEX_W_0F41_P_0_LEN_1,
1927   VEX_W_0F41_P_2_LEN_1,
1928   VEX_W_0F42_P_0_LEN_1,
1929   VEX_W_0F42_P_2_LEN_1,
1930   VEX_W_0F44_P_0_LEN_0,
1931   VEX_W_0F44_P_2_LEN_0,
1932   VEX_W_0F45_P_0_LEN_1,
1933   VEX_W_0F45_P_2_LEN_1,
1934   VEX_W_0F46_P_0_LEN_1,
1935   VEX_W_0F46_P_2_LEN_1,
1936   VEX_W_0F47_P_0_LEN_1,
1937   VEX_W_0F47_P_2_LEN_1,
1938   VEX_W_0F4A_P_0_LEN_1,
1939   VEX_W_0F4A_P_2_LEN_1,
1940   VEX_W_0F4B_P_0_LEN_1,
1941   VEX_W_0F4B_P_2_LEN_1,
1942   VEX_W_0F50_M_0,
1943   VEX_W_0F51_P_0,
1944   VEX_W_0F51_P_1,
1945   VEX_W_0F51_P_2,
1946   VEX_W_0F51_P_3,
1947   VEX_W_0F52_P_0,
1948   VEX_W_0F52_P_1,
1949   VEX_W_0F53_P_0,
1950   VEX_W_0F53_P_1,
1951   VEX_W_0F58_P_0,
1952   VEX_W_0F58_P_1,
1953   VEX_W_0F58_P_2,
1954   VEX_W_0F58_P_3,
1955   VEX_W_0F59_P_0,
1956   VEX_W_0F59_P_1,
1957   VEX_W_0F59_P_2,
1958   VEX_W_0F59_P_3,
1959   VEX_W_0F5A_P_0,
1960   VEX_W_0F5A_P_1,
1961   VEX_W_0F5A_P_3,
1962   VEX_W_0F5B_P_0,
1963   VEX_W_0F5B_P_1,
1964   VEX_W_0F5B_P_2,
1965   VEX_W_0F5C_P_0,
1966   VEX_W_0F5C_P_1,
1967   VEX_W_0F5C_P_2,
1968   VEX_W_0F5C_P_3,
1969   VEX_W_0F5D_P_0,
1970   VEX_W_0F5D_P_1,
1971   VEX_W_0F5D_P_2,
1972   VEX_W_0F5D_P_3,
1973   VEX_W_0F5E_P_0,
1974   VEX_W_0F5E_P_1,
1975   VEX_W_0F5E_P_2,
1976   VEX_W_0F5E_P_3,
1977   VEX_W_0F5F_P_0,
1978   VEX_W_0F5F_P_1,
1979   VEX_W_0F5F_P_2,
1980   VEX_W_0F5F_P_3,
1981   VEX_W_0F60_P_2,
1982   VEX_W_0F61_P_2,
1983   VEX_W_0F62_P_2,
1984   VEX_W_0F63_P_2,
1985   VEX_W_0F64_P_2,
1986   VEX_W_0F65_P_2,
1987   VEX_W_0F66_P_2,
1988   VEX_W_0F67_P_2,
1989   VEX_W_0F68_P_2,
1990   VEX_W_0F69_P_2,
1991   VEX_W_0F6A_P_2,
1992   VEX_W_0F6B_P_2,
1993   VEX_W_0F6C_P_2,
1994   VEX_W_0F6D_P_2,
1995   VEX_W_0F6F_P_1,
1996   VEX_W_0F6F_P_2,
1997   VEX_W_0F70_P_1,
1998   VEX_W_0F70_P_2,
1999   VEX_W_0F70_P_3,
2000   VEX_W_0F71_R_2_P_2,
2001   VEX_W_0F71_R_4_P_2,
2002   VEX_W_0F71_R_6_P_2,
2003   VEX_W_0F72_R_2_P_2,
2004   VEX_W_0F72_R_4_P_2,
2005   VEX_W_0F72_R_6_P_2,
2006   VEX_W_0F73_R_2_P_2,
2007   VEX_W_0F73_R_3_P_2,
2008   VEX_W_0F73_R_6_P_2,
2009   VEX_W_0F73_R_7_P_2,
2010   VEX_W_0F74_P_2,
2011   VEX_W_0F75_P_2,
2012   VEX_W_0F76_P_2,
2013   VEX_W_0F77_P_0,
2014   VEX_W_0F7C_P_2,
2015   VEX_W_0F7C_P_3,
2016   VEX_W_0F7D_P_2,
2017   VEX_W_0F7D_P_3,
2018   VEX_W_0F7E_P_1,
2019   VEX_W_0F7F_P_1,
2020   VEX_W_0F7F_P_2,
2021   VEX_W_0F90_P_0_LEN_0,
2022   VEX_W_0F90_P_2_LEN_0,
2023   VEX_W_0F91_P_0_LEN_0,
2024   VEX_W_0F91_P_2_LEN_0,
2025   VEX_W_0F92_P_0_LEN_0,
2026   VEX_W_0F92_P_2_LEN_0,
2027   VEX_W_0F92_P_3_LEN_0,
2028   VEX_W_0F93_P_0_LEN_0,
2029   VEX_W_0F93_P_2_LEN_0,
2030   VEX_W_0F93_P_3_LEN_0,
2031   VEX_W_0F98_P_0_LEN_0,
2032   VEX_W_0F98_P_2_LEN_0,
2033   VEX_W_0F99_P_0_LEN_0,
2034   VEX_W_0F99_P_2_LEN_0,
2035   VEX_W_0FAE_R_2_M_0,
2036   VEX_W_0FAE_R_3_M_0,
2037   VEX_W_0FC2_P_0,
2038   VEX_W_0FC2_P_1,
2039   VEX_W_0FC2_P_2,
2040   VEX_W_0FC2_P_3,
2041   VEX_W_0FC4_P_2,
2042   VEX_W_0FC5_P_2,
2043   VEX_W_0FD0_P_2,
2044   VEX_W_0FD0_P_3,
2045   VEX_W_0FD1_P_2,
2046   VEX_W_0FD2_P_2,
2047   VEX_W_0FD3_P_2,
2048   VEX_W_0FD4_P_2,
2049   VEX_W_0FD5_P_2,
2050   VEX_W_0FD6_P_2,
2051   VEX_W_0FD7_P_2_M_1,
2052   VEX_W_0FD8_P_2,
2053   VEX_W_0FD9_P_2,
2054   VEX_W_0FDA_P_2,
2055   VEX_W_0FDB_P_2,
2056   VEX_W_0FDC_P_2,
2057   VEX_W_0FDD_P_2,
2058   VEX_W_0FDE_P_2,
2059   VEX_W_0FDF_P_2,
2060   VEX_W_0FE0_P_2,
2061   VEX_W_0FE1_P_2,
2062   VEX_W_0FE2_P_2,
2063   VEX_W_0FE3_P_2,
2064   VEX_W_0FE4_P_2,
2065   VEX_W_0FE5_P_2,
2066   VEX_W_0FE6_P_1,
2067   VEX_W_0FE6_P_2,
2068   VEX_W_0FE6_P_3,
2069   VEX_W_0FE7_P_2_M_0,
2070   VEX_W_0FE8_P_2,
2071   VEX_W_0FE9_P_2,
2072   VEX_W_0FEA_P_2,
2073   VEX_W_0FEB_P_2,
2074   VEX_W_0FEC_P_2,
2075   VEX_W_0FED_P_2,
2076   VEX_W_0FEE_P_2,
2077   VEX_W_0FEF_P_2,
2078   VEX_W_0FF0_P_3_M_0,
2079   VEX_W_0FF1_P_2,
2080   VEX_W_0FF2_P_2,
2081   VEX_W_0FF3_P_2,
2082   VEX_W_0FF4_P_2,
2083   VEX_W_0FF5_P_2,
2084   VEX_W_0FF6_P_2,
2085   VEX_W_0FF7_P_2,
2086   VEX_W_0FF8_P_2,
2087   VEX_W_0FF9_P_2,
2088   VEX_W_0FFA_P_2,
2089   VEX_W_0FFB_P_2,
2090   VEX_W_0FFC_P_2,
2091   VEX_W_0FFD_P_2,
2092   VEX_W_0FFE_P_2,
2093   VEX_W_0F3800_P_2,
2094   VEX_W_0F3801_P_2,
2095   VEX_W_0F3802_P_2,
2096   VEX_W_0F3803_P_2,
2097   VEX_W_0F3804_P_2,
2098   VEX_W_0F3805_P_2,
2099   VEX_W_0F3806_P_2,
2100   VEX_W_0F3807_P_2,
2101   VEX_W_0F3808_P_2,
2102   VEX_W_0F3809_P_2,
2103   VEX_W_0F380A_P_2,
2104   VEX_W_0F380B_P_2,
2105   VEX_W_0F380C_P_2,
2106   VEX_W_0F380D_P_2,
2107   VEX_W_0F380E_P_2,
2108   VEX_W_0F380F_P_2,
2109   VEX_W_0F3816_P_2,
2110   VEX_W_0F3817_P_2,
2111   VEX_W_0F3818_P_2,
2112   VEX_W_0F3819_P_2,
2113   VEX_W_0F381A_P_2_M_0,
2114   VEX_W_0F381C_P_2,
2115   VEX_W_0F381D_P_2,
2116   VEX_W_0F381E_P_2,
2117   VEX_W_0F3820_P_2,
2118   VEX_W_0F3821_P_2,
2119   VEX_W_0F3822_P_2,
2120   VEX_W_0F3823_P_2,
2121   VEX_W_0F3824_P_2,
2122   VEX_W_0F3825_P_2,
2123   VEX_W_0F3828_P_2,
2124   VEX_W_0F3829_P_2,
2125   VEX_W_0F382A_P_2_M_0,
2126   VEX_W_0F382B_P_2,
2127   VEX_W_0F382C_P_2_M_0,
2128   VEX_W_0F382D_P_2_M_0,
2129   VEX_W_0F382E_P_2_M_0,
2130   VEX_W_0F382F_P_2_M_0,
2131   VEX_W_0F3830_P_2,
2132   VEX_W_0F3831_P_2,
2133   VEX_W_0F3832_P_2,
2134   VEX_W_0F3833_P_2,
2135   VEX_W_0F3834_P_2,
2136   VEX_W_0F3835_P_2,
2137   VEX_W_0F3836_P_2,
2138   VEX_W_0F3837_P_2,
2139   VEX_W_0F3838_P_2,
2140   VEX_W_0F3839_P_2,
2141   VEX_W_0F383A_P_2,
2142   VEX_W_0F383B_P_2,
2143   VEX_W_0F383C_P_2,
2144   VEX_W_0F383D_P_2,
2145   VEX_W_0F383E_P_2,
2146   VEX_W_0F383F_P_2,
2147   VEX_W_0F3840_P_2,
2148   VEX_W_0F3841_P_2,
2149   VEX_W_0F3846_P_2,
2150   VEX_W_0F3858_P_2,
2151   VEX_W_0F3859_P_2,
2152   VEX_W_0F385A_P_2_M_0,
2153   VEX_W_0F3878_P_2,
2154   VEX_W_0F3879_P_2,
2155   VEX_W_0F38DB_P_2,
2156   VEX_W_0F38DC_P_2,
2157   VEX_W_0F38DD_P_2,
2158   VEX_W_0F38DE_P_2,
2159   VEX_W_0F38DF_P_2,
2160   VEX_W_0F3A00_P_2,
2161   VEX_W_0F3A01_P_2,
2162   VEX_W_0F3A02_P_2,
2163   VEX_W_0F3A04_P_2,
2164   VEX_W_0F3A05_P_2,
2165   VEX_W_0F3A06_P_2,
2166   VEX_W_0F3A08_P_2,
2167   VEX_W_0F3A09_P_2,
2168   VEX_W_0F3A0A_P_2,
2169   VEX_W_0F3A0B_P_2,
2170   VEX_W_0F3A0C_P_2,
2171   VEX_W_0F3A0D_P_2,
2172   VEX_W_0F3A0E_P_2,
2173   VEX_W_0F3A0F_P_2,
2174   VEX_W_0F3A14_P_2,
2175   VEX_W_0F3A15_P_2,
2176   VEX_W_0F3A18_P_2,
2177   VEX_W_0F3A19_P_2,
2178   VEX_W_0F3A20_P_2,
2179   VEX_W_0F3A21_P_2,
2180   VEX_W_0F3A30_P_2_LEN_0,
2181   VEX_W_0F3A31_P_2_LEN_0,
2182   VEX_W_0F3A32_P_2_LEN_0,
2183   VEX_W_0F3A33_P_2_LEN_0,
2184   VEX_W_0F3A38_P_2,
2185   VEX_W_0F3A39_P_2,
2186   VEX_W_0F3A40_P_2,
2187   VEX_W_0F3A41_P_2,
2188   VEX_W_0F3A42_P_2,
2189   VEX_W_0F3A44_P_2,
2190   VEX_W_0F3A46_P_2,
2191   VEX_W_0F3A48_P_2,
2192   VEX_W_0F3A49_P_2,
2193   VEX_W_0F3A4A_P_2,
2194   VEX_W_0F3A4B_P_2,
2195   VEX_W_0F3A4C_P_2,
2196   VEX_W_0F3A60_P_2,
2197   VEX_W_0F3A61_P_2,
2198   VEX_W_0F3A62_P_2,
2199   VEX_W_0F3A63_P_2,
2200   VEX_W_0F3ADF_P_2,
2201
2202   EVEX_W_0F10_P_0,
2203   EVEX_W_0F10_P_1_M_0,
2204   EVEX_W_0F10_P_1_M_1,
2205   EVEX_W_0F10_P_2,
2206   EVEX_W_0F10_P_3_M_0,
2207   EVEX_W_0F10_P_3_M_1,
2208   EVEX_W_0F11_P_0,
2209   EVEX_W_0F11_P_1_M_0,
2210   EVEX_W_0F11_P_1_M_1,
2211   EVEX_W_0F11_P_2,
2212   EVEX_W_0F11_P_3_M_0,
2213   EVEX_W_0F11_P_3_M_1,
2214   EVEX_W_0F12_P_0_M_0,
2215   EVEX_W_0F12_P_0_M_1,
2216   EVEX_W_0F12_P_1,
2217   EVEX_W_0F12_P_2,
2218   EVEX_W_0F12_P_3,
2219   EVEX_W_0F13_P_0,
2220   EVEX_W_0F13_P_2,
2221   EVEX_W_0F14_P_0,
2222   EVEX_W_0F14_P_2,
2223   EVEX_W_0F15_P_0,
2224   EVEX_W_0F15_P_2,
2225   EVEX_W_0F16_P_0_M_0,
2226   EVEX_W_0F16_P_0_M_1,
2227   EVEX_W_0F16_P_1,
2228   EVEX_W_0F16_P_2,
2229   EVEX_W_0F17_P_0,
2230   EVEX_W_0F17_P_2,
2231   EVEX_W_0F28_P_0,
2232   EVEX_W_0F28_P_2,
2233   EVEX_W_0F29_P_0,
2234   EVEX_W_0F29_P_2,
2235   EVEX_W_0F2A_P_1,
2236   EVEX_W_0F2A_P_3,
2237   EVEX_W_0F2B_P_0,
2238   EVEX_W_0F2B_P_2,
2239   EVEX_W_0F2E_P_0,
2240   EVEX_W_0F2E_P_2,
2241   EVEX_W_0F2F_P_0,
2242   EVEX_W_0F2F_P_2,
2243   EVEX_W_0F51_P_0,
2244   EVEX_W_0F51_P_1,
2245   EVEX_W_0F51_P_2,
2246   EVEX_W_0F51_P_3,
2247   EVEX_W_0F54_P_0,
2248   EVEX_W_0F54_P_2,
2249   EVEX_W_0F55_P_0,
2250   EVEX_W_0F55_P_2,
2251   EVEX_W_0F56_P_0,
2252   EVEX_W_0F56_P_2,
2253   EVEX_W_0F57_P_0,
2254   EVEX_W_0F57_P_2,
2255   EVEX_W_0F58_P_0,
2256   EVEX_W_0F58_P_1,
2257   EVEX_W_0F58_P_2,
2258   EVEX_W_0F58_P_3,
2259   EVEX_W_0F59_P_0,
2260   EVEX_W_0F59_P_1,
2261   EVEX_W_0F59_P_2,
2262   EVEX_W_0F59_P_3,
2263   EVEX_W_0F5A_P_0,
2264   EVEX_W_0F5A_P_1,
2265   EVEX_W_0F5A_P_2,
2266   EVEX_W_0F5A_P_3,
2267   EVEX_W_0F5B_P_0,
2268   EVEX_W_0F5B_P_1,
2269   EVEX_W_0F5B_P_2,
2270   EVEX_W_0F5C_P_0,
2271   EVEX_W_0F5C_P_1,
2272   EVEX_W_0F5C_P_2,
2273   EVEX_W_0F5C_P_3,
2274   EVEX_W_0F5D_P_0,
2275   EVEX_W_0F5D_P_1,
2276   EVEX_W_0F5D_P_2,
2277   EVEX_W_0F5D_P_3,
2278   EVEX_W_0F5E_P_0,
2279   EVEX_W_0F5E_P_1,
2280   EVEX_W_0F5E_P_2,
2281   EVEX_W_0F5E_P_3,
2282   EVEX_W_0F5F_P_0,
2283   EVEX_W_0F5F_P_1,
2284   EVEX_W_0F5F_P_2,
2285   EVEX_W_0F5F_P_3,
2286   EVEX_W_0F62_P_2,
2287   EVEX_W_0F66_P_2,
2288   EVEX_W_0F6A_P_2,
2289   EVEX_W_0F6B_P_2,
2290   EVEX_W_0F6C_P_2,
2291   EVEX_W_0F6D_P_2,
2292   EVEX_W_0F6E_P_2,
2293   EVEX_W_0F6F_P_1,
2294   EVEX_W_0F6F_P_2,
2295   EVEX_W_0F6F_P_3,
2296   EVEX_W_0F70_P_2,
2297   EVEX_W_0F72_R_2_P_2,
2298   EVEX_W_0F72_R_6_P_2,
2299   EVEX_W_0F73_R_2_P_2,
2300   EVEX_W_0F73_R_6_P_2,
2301   EVEX_W_0F76_P_2,
2302   EVEX_W_0F78_P_0,
2303   EVEX_W_0F78_P_2,
2304   EVEX_W_0F79_P_0,
2305   EVEX_W_0F79_P_2,
2306   EVEX_W_0F7A_P_1,
2307   EVEX_W_0F7A_P_2,
2308   EVEX_W_0F7A_P_3,
2309   EVEX_W_0F7B_P_1,
2310   EVEX_W_0F7B_P_2,
2311   EVEX_W_0F7B_P_3,
2312   EVEX_W_0F7E_P_1,
2313   EVEX_W_0F7E_P_2,
2314   EVEX_W_0F7F_P_1,
2315   EVEX_W_0F7F_P_2,
2316   EVEX_W_0F7F_P_3,
2317   EVEX_W_0FC2_P_0,
2318   EVEX_W_0FC2_P_1,
2319   EVEX_W_0FC2_P_2,
2320   EVEX_W_0FC2_P_3,
2321   EVEX_W_0FC6_P_0,
2322   EVEX_W_0FC6_P_2,
2323   EVEX_W_0FD2_P_2,
2324   EVEX_W_0FD3_P_2,
2325   EVEX_W_0FD4_P_2,
2326   EVEX_W_0FD6_P_2,
2327   EVEX_W_0FE6_P_1,
2328   EVEX_W_0FE6_P_2,
2329   EVEX_W_0FE6_P_3,
2330   EVEX_W_0FE7_P_2,
2331   EVEX_W_0FF2_P_2,
2332   EVEX_W_0FF3_P_2,
2333   EVEX_W_0FF4_P_2,
2334   EVEX_W_0FFA_P_2,
2335   EVEX_W_0FFB_P_2,
2336   EVEX_W_0FFE_P_2,
2337   EVEX_W_0F380C_P_2,
2338   EVEX_W_0F380D_P_2,
2339   EVEX_W_0F3810_P_1,
2340   EVEX_W_0F3810_P_2,
2341   EVEX_W_0F3811_P_1,
2342   EVEX_W_0F3811_P_2,
2343   EVEX_W_0F3812_P_1,
2344   EVEX_W_0F3812_P_2,
2345   EVEX_W_0F3813_P_1,
2346   EVEX_W_0F3813_P_2,
2347   EVEX_W_0F3814_P_1,
2348   EVEX_W_0F3815_P_1,
2349   EVEX_W_0F3818_P_2,
2350   EVEX_W_0F3819_P_2,
2351   EVEX_W_0F381A_P_2,
2352   EVEX_W_0F381B_P_2,
2353   EVEX_W_0F381E_P_2,
2354   EVEX_W_0F381F_P_2,
2355   EVEX_W_0F3820_P_1,
2356   EVEX_W_0F3821_P_1,
2357   EVEX_W_0F3822_P_1,
2358   EVEX_W_0F3823_P_1,
2359   EVEX_W_0F3824_P_1,
2360   EVEX_W_0F3825_P_1,
2361   EVEX_W_0F3825_P_2,
2362   EVEX_W_0F3826_P_1,
2363   EVEX_W_0F3826_P_2,
2364   EVEX_W_0F3828_P_1,
2365   EVEX_W_0F3828_P_2,
2366   EVEX_W_0F3829_P_1,
2367   EVEX_W_0F3829_P_2,
2368   EVEX_W_0F382A_P_1,
2369   EVEX_W_0F382A_P_2,
2370   EVEX_W_0F382B_P_2,
2371   EVEX_W_0F3830_P_1,
2372   EVEX_W_0F3831_P_1,
2373   EVEX_W_0F3832_P_1,
2374   EVEX_W_0F3833_P_1,
2375   EVEX_W_0F3834_P_1,
2376   EVEX_W_0F3835_P_1,
2377   EVEX_W_0F3835_P_2,
2378   EVEX_W_0F3837_P_2,
2379   EVEX_W_0F3838_P_1,
2380   EVEX_W_0F3839_P_1,
2381   EVEX_W_0F383A_P_1,
2382   EVEX_W_0F3840_P_2,
2383   EVEX_W_0F3858_P_2,
2384   EVEX_W_0F3859_P_2,
2385   EVEX_W_0F385A_P_2,
2386   EVEX_W_0F385B_P_2,
2387   EVEX_W_0F3866_P_2,
2388   EVEX_W_0F3875_P_2,
2389   EVEX_W_0F3878_P_2,
2390   EVEX_W_0F3879_P_2,
2391   EVEX_W_0F387A_P_2,
2392   EVEX_W_0F387B_P_2,
2393   EVEX_W_0F387D_P_2,
2394   EVEX_W_0F3883_P_2,
2395   EVEX_W_0F388D_P_2,
2396   EVEX_W_0F3891_P_2,
2397   EVEX_W_0F3893_P_2,
2398   EVEX_W_0F38A1_P_2,
2399   EVEX_W_0F38A3_P_2,
2400   EVEX_W_0F38C7_R_1_P_2,
2401   EVEX_W_0F38C7_R_2_P_2,
2402   EVEX_W_0F38C7_R_5_P_2,
2403   EVEX_W_0F38C7_R_6_P_2,
2404
2405   EVEX_W_0F3A00_P_2,
2406   EVEX_W_0F3A01_P_2,
2407   EVEX_W_0F3A04_P_2,
2408   EVEX_W_0F3A05_P_2,
2409   EVEX_W_0F3A08_P_2,
2410   EVEX_W_0F3A09_P_2,
2411   EVEX_W_0F3A0A_P_2,
2412   EVEX_W_0F3A0B_P_2,
2413   EVEX_W_0F3A16_P_2,
2414   EVEX_W_0F3A18_P_2,
2415   EVEX_W_0F3A19_P_2,
2416   EVEX_W_0F3A1A_P_2,
2417   EVEX_W_0F3A1B_P_2,
2418   EVEX_W_0F3A1D_P_2,
2419   EVEX_W_0F3A21_P_2,
2420   EVEX_W_0F3A22_P_2,
2421   EVEX_W_0F3A23_P_2,
2422   EVEX_W_0F3A38_P_2,
2423   EVEX_W_0F3A39_P_2,
2424   EVEX_W_0F3A3A_P_2,
2425   EVEX_W_0F3A3B_P_2,
2426   EVEX_W_0F3A3E_P_2,
2427   EVEX_W_0F3A3F_P_2,
2428   EVEX_W_0F3A42_P_2,
2429   EVEX_W_0F3A43_P_2,
2430   EVEX_W_0F3A50_P_2,
2431   EVEX_W_0F3A51_P_2,
2432   EVEX_W_0F3A56_P_2,
2433   EVEX_W_0F3A57_P_2,
2434   EVEX_W_0F3A66_P_2,
2435   EVEX_W_0F3A67_P_2
2436 };
2437
2438 typedef void (*op_rtn) (int bytemode, int sizeflag);
2439
2440 struct dis386 {
2441   const char *name;
2442   struct
2443     {
2444       op_rtn rtn;
2445       int bytemode;
2446     } op[MAX_OPERANDS];
2447   unsigned int prefix_requirement;
2448 };
2449
2450 /* Upper case letters in the instruction names here are macros.
2451    'A' => print 'b' if no register operands or suffix_always is true
2452    'B' => print 'b' if suffix_always is true
2453    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2454           size prefix
2455    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2456           suffix_always is true
2457    'E' => print 'e' if 32-bit form of jcxz
2458    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2459    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2460    'H' => print ",pt" or ",pn" branch hint
2461    'I' => honor following macro letter even in Intel mode (implemented only
2462           for some of the macro letters)
2463    'J' => print 'l'
2464    'K' => print 'd' or 'q' if rex prefix is present.
2465    'L' => print 'l' if suffix_always is true
2466    'M' => print 'r' if intel_mnemonic is false.
2467    'N' => print 'n' if instruction has no wait "prefix"
2468    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2469    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2470           or suffix_always is true.  print 'q' if rex prefix is present.
2471    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2472           is true
2473    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2474    'S' => print 'w', 'l' or 'q' if suffix_always is true
2475    'T' => print 'q' in 64bit mode if instruction has no operand size
2476           prefix and behave as 'P' otherwise
2477    'U' => print 'q' in 64bit mode if instruction has no operand size
2478           prefix and behave as 'Q' otherwise
2479    'V' => print 'q' in 64bit mode if instruction has no operand size
2480           prefix and behave as 'S' otherwise
2481    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2482    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2483    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2484           suffix_always is true.
2485    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2486    '!' => change condition from true to false or from false to true.
2487    '%' => add 1 upper case letter to the macro.
2488    '^' => print 'w' or 'l' depending on operand size prefix or
2489           suffix_always is true (lcall/ljmp).
2490    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2491           on operand size prefix.
2492    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2493           has no operand size prefix for AMD64 ISA, behave as 'P'
2494           otherwise
2495
2496    2 upper case letter macros:
2497    "XY" => print 'x' or 'y' if suffix_always is true or no register
2498            operands and no broadcast.
2499    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2500            register operands and no broadcast.
2501    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2502    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2503            or suffix_always is true
2504    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2505    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2506    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2507    "LW" => print 'd', 'q' depending on the VEX.W bit
2508    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2509            an operand size prefix, or suffix_always is true.  print
2510            'q' if rex prefix is present.
2511
2512    Many of the above letters print nothing in Intel mode.  See "putop"
2513    for the details.
2514
2515    Braces '{' and '}', and vertical bars '|', indicate alternative
2516    mnemonic strings for AT&T and Intel.  */
2517
2518 static const struct dis386 dis386[] = {
2519   /* 00 */
2520   { "addB",             { Ebh1, Gb }, 0 },
2521   { "addS",             { Evh1, Gv }, 0 },
2522   { "addB",             { Gb, EbS }, 0 },
2523   { "addS",             { Gv, EvS }, 0 },
2524   { "addB",             { AL, Ib }, 0 },
2525   { "addS",             { eAX, Iv }, 0 },
2526   { X86_64_TABLE (X86_64_06) },
2527   { X86_64_TABLE (X86_64_07) },
2528   /* 08 */
2529   { "orB",              { Ebh1, Gb }, 0 },
2530   { "orS",              { Evh1, Gv }, 0 },
2531   { "orB",              { Gb, EbS }, 0 },
2532   { "orS",              { Gv, EvS }, 0 },
2533   { "orB",              { AL, Ib }, 0 },
2534   { "orS",              { eAX, Iv }, 0 },
2535   { X86_64_TABLE (X86_64_0D) },
2536   { Bad_Opcode },       /* 0x0f extended opcode escape */
2537   /* 10 */
2538   { "adcB",             { Ebh1, Gb }, 0 },
2539   { "adcS",             { Evh1, Gv }, 0 },
2540   { "adcB",             { Gb, EbS }, 0 },
2541   { "adcS",             { Gv, EvS }, 0 },
2542   { "adcB",             { AL, Ib }, 0 },
2543   { "adcS",             { eAX, Iv }, 0 },
2544   { X86_64_TABLE (X86_64_16) },
2545   { X86_64_TABLE (X86_64_17) },
2546   /* 18 */
2547   { "sbbB",             { Ebh1, Gb }, 0 },
2548   { "sbbS",             { Evh1, Gv }, 0 },
2549   { "sbbB",             { Gb, EbS }, 0 },
2550   { "sbbS",             { Gv, EvS }, 0 },
2551   { "sbbB",             { AL, Ib }, 0 },
2552   { "sbbS",             { eAX, Iv }, 0 },
2553   { X86_64_TABLE (X86_64_1E) },
2554   { X86_64_TABLE (X86_64_1F) },
2555   /* 20 */
2556   { "andB",             { Ebh1, Gb }, 0 },
2557   { "andS",             { Evh1, Gv }, 0 },
2558   { "andB",             { Gb, EbS }, 0 },
2559   { "andS",             { Gv, EvS }, 0 },
2560   { "andB",             { AL, Ib }, 0 },
2561   { "andS",             { eAX, Iv }, 0 },
2562   { Bad_Opcode },       /* SEG ES prefix */
2563   { X86_64_TABLE (X86_64_27) },
2564   /* 28 */
2565   { "subB",             { Ebh1, Gb }, 0 },
2566   { "subS",             { Evh1, Gv }, 0 },
2567   { "subB",             { Gb, EbS }, 0 },
2568   { "subS",             { Gv, EvS }, 0 },
2569   { "subB",             { AL, Ib }, 0 },
2570   { "subS",             { eAX, Iv }, 0 },
2571   { Bad_Opcode },       /* SEG CS prefix */
2572   { X86_64_TABLE (X86_64_2F) },
2573   /* 30 */
2574   { "xorB",             { Ebh1, Gb }, 0 },
2575   { "xorS",             { Evh1, Gv }, 0 },
2576   { "xorB",             { Gb, EbS }, 0 },
2577   { "xorS",             { Gv, EvS }, 0 },
2578   { "xorB",             { AL, Ib }, 0 },
2579   { "xorS",             { eAX, Iv }, 0 },
2580   { Bad_Opcode },       /* SEG SS prefix */
2581   { X86_64_TABLE (X86_64_37) },
2582   /* 38 */
2583   { "cmpB",             { Eb, Gb }, 0 },
2584   { "cmpS",             { Ev, Gv }, 0 },
2585   { "cmpB",             { Gb, EbS }, 0 },
2586   { "cmpS",             { Gv, EvS }, 0 },
2587   { "cmpB",             { AL, Ib }, 0 },
2588   { "cmpS",             { eAX, Iv }, 0 },
2589   { Bad_Opcode },       /* SEG DS prefix */
2590   { X86_64_TABLE (X86_64_3F) },
2591   /* 40 */
2592   { "inc{S|}",          { RMeAX }, 0 },
2593   { "inc{S|}",          { RMeCX }, 0 },
2594   { "inc{S|}",          { RMeDX }, 0 },
2595   { "inc{S|}",          { RMeBX }, 0 },
2596   { "inc{S|}",          { RMeSP }, 0 },
2597   { "inc{S|}",          { RMeBP }, 0 },
2598   { "inc{S|}",          { RMeSI }, 0 },
2599   { "inc{S|}",          { RMeDI }, 0 },
2600   /* 48 */
2601   { "dec{S|}",          { RMeAX }, 0 },
2602   { "dec{S|}",          { RMeCX }, 0 },
2603   { "dec{S|}",          { RMeDX }, 0 },
2604   { "dec{S|}",          { RMeBX }, 0 },
2605   { "dec{S|}",          { RMeSP }, 0 },
2606   { "dec{S|}",          { RMeBP }, 0 },
2607   { "dec{S|}",          { RMeSI }, 0 },
2608   { "dec{S|}",          { RMeDI }, 0 },
2609   /* 50 */
2610   { "pushV",            { RMrAX }, 0 },
2611   { "pushV",            { RMrCX }, 0 },
2612   { "pushV",            { RMrDX }, 0 },
2613   { "pushV",            { RMrBX }, 0 },
2614   { "pushV",            { RMrSP }, 0 },
2615   { "pushV",            { RMrBP }, 0 },
2616   { "pushV",            { RMrSI }, 0 },
2617   { "pushV",            { RMrDI }, 0 },
2618   /* 58 */
2619   { "popV",             { RMrAX }, 0 },
2620   { "popV",             { RMrCX }, 0 },
2621   { "popV",             { RMrDX }, 0 },
2622   { "popV",             { RMrBX }, 0 },
2623   { "popV",             { RMrSP }, 0 },
2624   { "popV",             { RMrBP }, 0 },
2625   { "popV",             { RMrSI }, 0 },
2626   { "popV",             { RMrDI }, 0 },
2627   /* 60 */
2628   { X86_64_TABLE (X86_64_60) },
2629   { X86_64_TABLE (X86_64_61) },
2630   { X86_64_TABLE (X86_64_62) },
2631   { X86_64_TABLE (X86_64_63) },
2632   { Bad_Opcode },       /* seg fs */
2633   { Bad_Opcode },       /* seg gs */
2634   { Bad_Opcode },       /* op size prefix */
2635   { Bad_Opcode },       /* adr size prefix */
2636   /* 68 */
2637   { "pushT",            { sIv }, 0 },
2638   { "imulS",            { Gv, Ev, Iv }, 0 },
2639   { "pushT",            { sIbT }, 0 },
2640   { "imulS",            { Gv, Ev, sIb }, 0 },
2641   { "ins{b|}",          { Ybr, indirDX }, 0 },
2642   { X86_64_TABLE (X86_64_6D) },
2643   { "outs{b|}",         { indirDXr, Xb }, 0 },
2644   { X86_64_TABLE (X86_64_6F) },
2645   /* 70 */
2646   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2647   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2648   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2649   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2650   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2651   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2652   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2653   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2654   /* 78 */
2655   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2656   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2657   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2658   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2659   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2660   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2661   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2662   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2663   /* 80 */
2664   { REG_TABLE (REG_80) },
2665   { REG_TABLE (REG_81) },
2666   { X86_64_TABLE (X86_64_82) },
2667   { REG_TABLE (REG_83) },
2668   { "testB",            { Eb, Gb }, 0 },
2669   { "testS",            { Ev, Gv }, 0 },
2670   { "xchgB",            { Ebh2, Gb }, 0 },
2671   { "xchgS",            { Evh2, Gv }, 0 },
2672   /* 88 */
2673   { "movB",             { Ebh3, Gb }, 0 },
2674   { "movS",             { Evh3, Gv }, 0 },
2675   { "movB",             { Gb, EbS }, 0 },
2676   { "movS",             { Gv, EvS }, 0 },
2677   { "movD",             { Sv, Sw }, 0 },
2678   { MOD_TABLE (MOD_8D) },
2679   { "movD",             { Sw, Sv }, 0 },
2680   { REG_TABLE (REG_8F) },
2681   /* 90 */
2682   { PREFIX_TABLE (PREFIX_90) },
2683   { "xchgS",            { RMeCX, eAX }, 0 },
2684   { "xchgS",            { RMeDX, eAX }, 0 },
2685   { "xchgS",            { RMeBX, eAX }, 0 },
2686   { "xchgS",            { RMeSP, eAX }, 0 },
2687   { "xchgS",            { RMeBP, eAX }, 0 },
2688   { "xchgS",            { RMeSI, eAX }, 0 },
2689   { "xchgS",            { RMeDI, eAX }, 0 },
2690   /* 98 */
2691   { "cW{t|}R",          { XX }, 0 },
2692   { "cR{t|}O",          { XX }, 0 },
2693   { X86_64_TABLE (X86_64_9A) },
2694   { Bad_Opcode },       /* fwait */
2695   { "pushfT",           { XX }, 0 },
2696   { "popfT",            { XX }, 0 },
2697   { "sahf",             { XX }, 0 },
2698   { "lahf",             { XX }, 0 },
2699   /* a0 */
2700   { "mov%LB",           { AL, Ob }, 0 },
2701   { "mov%LS",           { eAX, Ov }, 0 },
2702   { "mov%LB",           { Ob, AL }, 0 },
2703   { "mov%LS",           { Ov, eAX }, 0 },
2704   { "movs{b|}",         { Ybr, Xb }, 0 },
2705   { "movs{R|}",         { Yvr, Xv }, 0 },
2706   { "cmps{b|}",         { Xb, Yb }, 0 },
2707   { "cmps{R|}",         { Xv, Yv }, 0 },
2708   /* a8 */
2709   { "testB",            { AL, Ib }, 0 },
2710   { "testS",            { eAX, Iv }, 0 },
2711   { "stosB",            { Ybr, AL }, 0 },
2712   { "stosS",            { Yvr, eAX }, 0 },
2713   { "lodsB",            { ALr, Xb }, 0 },
2714   { "lodsS",            { eAXr, Xv }, 0 },
2715   { "scasB",            { AL, Yb }, 0 },
2716   { "scasS",            { eAX, Yv }, 0 },
2717   /* b0 */
2718   { "movB",             { RMAL, Ib }, 0 },
2719   { "movB",             { RMCL, Ib }, 0 },
2720   { "movB",             { RMDL, Ib }, 0 },
2721   { "movB",             { RMBL, Ib }, 0 },
2722   { "movB",             { RMAH, Ib }, 0 },
2723   { "movB",             { RMCH, Ib }, 0 },
2724   { "movB",             { RMDH, Ib }, 0 },
2725   { "movB",             { RMBH, Ib }, 0 },
2726   /* b8 */
2727   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2728   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2729   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2730   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2731   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2732   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2733   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2734   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2735   /* c0 */
2736   { REG_TABLE (REG_C0) },
2737   { REG_TABLE (REG_C1) },
2738   { "retT",             { Iw, BND }, 0 },
2739   { "retT",             { BND }, 0 },
2740   { X86_64_TABLE (X86_64_C4) },
2741   { X86_64_TABLE (X86_64_C5) },
2742   { REG_TABLE (REG_C6) },
2743   { REG_TABLE (REG_C7) },
2744   /* c8 */
2745   { "enterT",           { Iw, Ib }, 0 },
2746   { "leaveT",           { XX }, 0 },
2747   { "Jret{|f}P",        { Iw }, 0 },
2748   { "Jret{|f}P",        { XX }, 0 },
2749   { "int3",             { XX }, 0 },
2750   { "int",              { Ib }, 0 },
2751   { X86_64_TABLE (X86_64_CE) },
2752   { "iret%LP",          { XX }, 0 },
2753   /* d0 */
2754   { REG_TABLE (REG_D0) },
2755   { REG_TABLE (REG_D1) },
2756   { REG_TABLE (REG_D2) },
2757   { REG_TABLE (REG_D3) },
2758   { X86_64_TABLE (X86_64_D4) },
2759   { X86_64_TABLE (X86_64_D5) },
2760   { Bad_Opcode },
2761   { "xlat",             { DSBX }, 0 },
2762   /* d8 */
2763   { FLOAT },
2764   { FLOAT },
2765   { FLOAT },
2766   { FLOAT },
2767   { FLOAT },
2768   { FLOAT },
2769   { FLOAT },
2770   { FLOAT },
2771   /* e0 */
2772   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2773   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2774   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2775   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2776   { "inB",              { AL, Ib }, 0 },
2777   { "inG",              { zAX, Ib }, 0 },
2778   { "outB",             { Ib, AL }, 0 },
2779   { "outG",             { Ib, zAX }, 0 },
2780   /* e8 */
2781   { X86_64_TABLE (X86_64_E8) },
2782   { X86_64_TABLE (X86_64_E9) },
2783   { X86_64_TABLE (X86_64_EA) },
2784   { "jmp",              { Jb, BND }, 0 },
2785   { "inB",              { AL, indirDX }, 0 },
2786   { "inG",              { zAX, indirDX }, 0 },
2787   { "outB",             { indirDX, AL }, 0 },
2788   { "outG",             { indirDX, zAX }, 0 },
2789   /* f0 */
2790   { Bad_Opcode },       /* lock prefix */
2791   { "icebp",            { XX }, 0 },
2792   { Bad_Opcode },       /* repne */
2793   { Bad_Opcode },       /* repz */
2794   { "hlt",              { XX }, 0 },
2795   { "cmc",              { XX }, 0 },
2796   { REG_TABLE (REG_F6) },
2797   { REG_TABLE (REG_F7) },
2798   /* f8 */
2799   { "clc",              { XX }, 0 },
2800   { "stc",              { XX }, 0 },
2801   { "cli",              { XX }, 0 },
2802   { "sti",              { XX }, 0 },
2803   { "cld",              { XX }, 0 },
2804   { "std",              { XX }, 0 },
2805   { REG_TABLE (REG_FE) },
2806   { REG_TABLE (REG_FF) },
2807 };
2808
2809 static const struct dis386 dis386_twobyte[] = {
2810   /* 00 */
2811   { REG_TABLE (REG_0F00 ) },
2812   { REG_TABLE (REG_0F01 ) },
2813   { "larS",             { Gv, Ew }, 0 },
2814   { "lslS",             { Gv, Ew }, 0 },
2815   { Bad_Opcode },
2816   { "syscall",          { XX }, 0 },
2817   { "clts",             { XX }, 0 },
2818   { "sysret%LP",                { XX }, 0 },
2819   /* 08 */
2820   { "invd",             { XX }, 0 },
2821   { "wbinvd",           { XX }, 0 },
2822   { Bad_Opcode },
2823   { "ud2",              { XX }, 0 },
2824   { Bad_Opcode },
2825   { REG_TABLE (REG_0F0D) },
2826   { "femms",            { XX }, 0 },
2827   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2828   /* 10 */
2829   { PREFIX_TABLE (PREFIX_0F10) },
2830   { PREFIX_TABLE (PREFIX_0F11) },
2831   { PREFIX_TABLE (PREFIX_0F12) },
2832   { MOD_TABLE (MOD_0F13) },
2833   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2834   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2835   { PREFIX_TABLE (PREFIX_0F16) },
2836   { MOD_TABLE (MOD_0F17) },
2837   /* 18 */
2838   { REG_TABLE (REG_0F18) },
2839   { "nopQ",             { Ev }, 0 },
2840   { PREFIX_TABLE (PREFIX_0F1A) },
2841   { PREFIX_TABLE (PREFIX_0F1B) },
2842   { "nopQ",             { Ev }, 0 },
2843   { "nopQ",             { Ev }, 0 },
2844   { "nopQ",             { Ev }, 0 },
2845   { "nopQ",             { Ev }, 0 },
2846   /* 20 */
2847   { "movZ",             { Rm, Cm }, 0 },
2848   { "movZ",             { Rm, Dm }, 0 },
2849   { "movZ",             { Cm, Rm }, 0 },
2850   { "movZ",             { Dm, Rm }, 0 },
2851   { MOD_TABLE (MOD_0F24) },
2852   { Bad_Opcode },
2853   { MOD_TABLE (MOD_0F26) },
2854   { Bad_Opcode },
2855   /* 28 */
2856   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2857   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2858   { PREFIX_TABLE (PREFIX_0F2A) },
2859   { PREFIX_TABLE (PREFIX_0F2B) },
2860   { PREFIX_TABLE (PREFIX_0F2C) },
2861   { PREFIX_TABLE (PREFIX_0F2D) },
2862   { PREFIX_TABLE (PREFIX_0F2E) },
2863   { PREFIX_TABLE (PREFIX_0F2F) },
2864   /* 30 */
2865   { "wrmsr",            { XX }, 0 },
2866   { "rdtsc",            { XX }, 0 },
2867   { "rdmsr",            { XX }, 0 },
2868   { "rdpmc",            { XX }, 0 },
2869   { "sysenter",         { XX }, 0 },
2870   { "sysexit",          { XX }, 0 },
2871   { Bad_Opcode },
2872   { "getsec",           { XX }, 0 },
2873   /* 38 */
2874   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2875   { Bad_Opcode },
2876   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2877   { Bad_Opcode },
2878   { Bad_Opcode },
2879   { Bad_Opcode },
2880   { Bad_Opcode },
2881   { Bad_Opcode },
2882   /* 40 */
2883   { "cmovoS",           { Gv, Ev }, 0 },
2884   { "cmovnoS",          { Gv, Ev }, 0 },
2885   { "cmovbS",           { Gv, Ev }, 0 },
2886   { "cmovaeS",          { Gv, Ev }, 0 },
2887   { "cmoveS",           { Gv, Ev }, 0 },
2888   { "cmovneS",          { Gv, Ev }, 0 },
2889   { "cmovbeS",          { Gv, Ev }, 0 },
2890   { "cmovaS",           { Gv, Ev }, 0 },
2891   /* 48 */
2892   { "cmovsS",           { Gv, Ev }, 0 },
2893   { "cmovnsS",          { Gv, Ev }, 0 },
2894   { "cmovpS",           { Gv, Ev }, 0 },
2895   { "cmovnpS",          { Gv, Ev }, 0 },
2896   { "cmovlS",           { Gv, Ev }, 0 },
2897   { "cmovgeS",          { Gv, Ev }, 0 },
2898   { "cmovleS",          { Gv, Ev }, 0 },
2899   { "cmovgS",           { Gv, Ev }, 0 },
2900   /* 50 */
2901   { MOD_TABLE (MOD_0F51) },
2902   { PREFIX_TABLE (PREFIX_0F51) },
2903   { PREFIX_TABLE (PREFIX_0F52) },
2904   { PREFIX_TABLE (PREFIX_0F53) },
2905   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2906   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2907   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2908   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2909   /* 58 */
2910   { PREFIX_TABLE (PREFIX_0F58) },
2911   { PREFIX_TABLE (PREFIX_0F59) },
2912   { PREFIX_TABLE (PREFIX_0F5A) },
2913   { PREFIX_TABLE (PREFIX_0F5B) },
2914   { PREFIX_TABLE (PREFIX_0F5C) },
2915   { PREFIX_TABLE (PREFIX_0F5D) },
2916   { PREFIX_TABLE (PREFIX_0F5E) },
2917   { PREFIX_TABLE (PREFIX_0F5F) },
2918   /* 60 */
2919   { PREFIX_TABLE (PREFIX_0F60) },
2920   { PREFIX_TABLE (PREFIX_0F61) },
2921   { PREFIX_TABLE (PREFIX_0F62) },
2922   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2923   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2924   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2925   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2926   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2927   /* 68 */
2928   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2929   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2930   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2931   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2932   { PREFIX_TABLE (PREFIX_0F6C) },
2933   { PREFIX_TABLE (PREFIX_0F6D) },
2934   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2935   { PREFIX_TABLE (PREFIX_0F6F) },
2936   /* 70 */
2937   { PREFIX_TABLE (PREFIX_0F70) },
2938   { REG_TABLE (REG_0F71) },
2939   { REG_TABLE (REG_0F72) },
2940   { REG_TABLE (REG_0F73) },
2941   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2942   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2943   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2944   { "emms",             { XX }, PREFIX_OPCODE },
2945   /* 78 */
2946   { PREFIX_TABLE (PREFIX_0F78) },
2947   { PREFIX_TABLE (PREFIX_0F79) },
2948   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2949   { Bad_Opcode },
2950   { PREFIX_TABLE (PREFIX_0F7C) },
2951   { PREFIX_TABLE (PREFIX_0F7D) },
2952   { PREFIX_TABLE (PREFIX_0F7E) },
2953   { PREFIX_TABLE (PREFIX_0F7F) },
2954   /* 80 */
2955   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2956   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2957   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2958   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2959   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2960   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2961   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2962   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2963   /* 88 */
2964   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2965   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2966   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2967   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2968   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2969   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2970   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2971   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2972   /* 90 */
2973   { "seto",             { Eb }, 0 },
2974   { "setno",            { Eb }, 0 },
2975   { "setb",             { Eb }, 0 },
2976   { "setae",            { Eb }, 0 },
2977   { "sete",             { Eb }, 0 },
2978   { "setne",            { Eb }, 0 },
2979   { "setbe",            { Eb }, 0 },
2980   { "seta",             { Eb }, 0 },
2981   /* 98 */
2982   { "sets",             { Eb }, 0 },
2983   { "setns",            { Eb }, 0 },
2984   { "setp",             { Eb }, 0 },
2985   { "setnp",            { Eb }, 0 },
2986   { "setl",             { Eb }, 0 },
2987   { "setge",            { Eb }, 0 },
2988   { "setle",            { Eb }, 0 },
2989   { "setg",             { Eb }, 0 },
2990   /* a0 */
2991   { "pushT",            { fs }, 0 },
2992   { "popT",             { fs }, 0 },
2993   { "cpuid",            { XX }, 0 },
2994   { "btS",              { Ev, Gv }, 0 },
2995   { "shldS",            { Ev, Gv, Ib }, 0 },
2996   { "shldS",            { Ev, Gv, CL }, 0 },
2997   { REG_TABLE (REG_0FA6) },
2998   { REG_TABLE (REG_0FA7) },
2999   /* a8 */
3000   { "pushT",            { gs }, 0 },
3001   { "popT",             { gs }, 0 },
3002   { "rsm",              { XX }, 0 },
3003   { "btsS",             { Evh1, Gv }, 0 },
3004   { "shrdS",            { Ev, Gv, Ib }, 0 },
3005   { "shrdS",            { Ev, Gv, CL }, 0 },
3006   { REG_TABLE (REG_0FAE) },
3007   { "imulS",            { Gv, Ev }, 0 },
3008   /* b0 */
3009   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3010   { "cmpxchgS",         { Evh1, Gv }, 0 },
3011   { MOD_TABLE (MOD_0FB2) },
3012   { "btrS",             { Evh1, Gv }, 0 },
3013   { MOD_TABLE (MOD_0FB4) },
3014   { MOD_TABLE (MOD_0FB5) },
3015   { "movz{bR|x}",       { Gv, Eb }, 0 },
3016   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3017   /* b8 */
3018   { PREFIX_TABLE (PREFIX_0FB8) },
3019   { "ud1",              { XX }, 0 },
3020   { REG_TABLE (REG_0FBA) },
3021   { "btcS",             { Evh1, Gv }, 0 },
3022   { PREFIX_TABLE (PREFIX_0FBC) },
3023   { PREFIX_TABLE (PREFIX_0FBD) },
3024   { "movs{bR|x}",       { Gv, Eb }, 0 },
3025   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3026   /* c0 */
3027   { "xaddB",            { Ebh1, Gb }, 0 },
3028   { "xaddS",            { Evh1, Gv }, 0 },
3029   { PREFIX_TABLE (PREFIX_0FC2) },
3030   { MOD_TABLE (MOD_0FC3) },
3031   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3032   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3033   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3034   { REG_TABLE (REG_0FC7) },
3035   /* c8 */
3036   { "bswap",            { RMeAX }, 0 },
3037   { "bswap",            { RMeCX }, 0 },
3038   { "bswap",            { RMeDX }, 0 },
3039   { "bswap",            { RMeBX }, 0 },
3040   { "bswap",            { RMeSP }, 0 },
3041   { "bswap",            { RMeBP }, 0 },
3042   { "bswap",            { RMeSI }, 0 },
3043   { "bswap",            { RMeDI }, 0 },
3044   /* d0 */
3045   { PREFIX_TABLE (PREFIX_0FD0) },
3046   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3047   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3048   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3049   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3050   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3051   { PREFIX_TABLE (PREFIX_0FD6) },
3052   { MOD_TABLE (MOD_0FD7) },
3053   /* d8 */
3054   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3055   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3056   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3057   { "pand",             { MX, EM }, PREFIX_OPCODE },
3058   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3059   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3060   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3061   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3062   /* e0 */
3063   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3064   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3065   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3066   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3067   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3068   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3069   { PREFIX_TABLE (PREFIX_0FE6) },
3070   { PREFIX_TABLE (PREFIX_0FE7) },
3071   /* e8 */
3072   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3073   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3074   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3075   { "por",              { MX, EM }, PREFIX_OPCODE },
3076   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3077   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3078   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3079   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3080   /* f0 */
3081   { PREFIX_TABLE (PREFIX_0FF0) },
3082   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3083   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3084   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3085   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3086   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3087   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3088   { PREFIX_TABLE (PREFIX_0FF7) },
3089   /* f8 */
3090   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3091   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3092   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3093   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3094   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3095   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3096   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3097   { Bad_Opcode },
3098 };
3099
3100 static const unsigned char onebyte_has_modrm[256] = {
3101   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3102   /*       -------------------------------        */
3103   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3104   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3105   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3106   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3107   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3108   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3109   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3110   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3111   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3112   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3113   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3114   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3115   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3116   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3117   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3118   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3119   /*       -------------------------------        */
3120   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3121 };
3122
3123 static const unsigned char twobyte_has_modrm[256] = {
3124   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3125   /*       -------------------------------        */
3126   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3127   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3128   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3129   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3130   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3131   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3132   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3133   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3134   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3135   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3136   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3137   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3138   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3139   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3140   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3141   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3142   /*       -------------------------------        */
3143   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3144 };
3145
3146 static char obuf[100];
3147 static char *obufp;
3148 static char *mnemonicendp;
3149 static char scratchbuf[100];
3150 static unsigned char *start_codep;
3151 static unsigned char *insn_codep;
3152 static unsigned char *codep;
3153 static unsigned char *end_codep;
3154 static int last_lock_prefix;
3155 static int last_repz_prefix;
3156 static int last_repnz_prefix;
3157 static int last_data_prefix;
3158 static int last_addr_prefix;
3159 static int last_rex_prefix;
3160 static int last_seg_prefix;
3161 static int fwait_prefix;
3162 /* The active segment register prefix.  */
3163 static int active_seg_prefix;
3164 #define MAX_CODE_LENGTH 15
3165 /* We can up to 14 prefixes since the maximum instruction length is
3166    15bytes.  */
3167 static int all_prefixes[MAX_CODE_LENGTH - 1];
3168 static disassemble_info *the_info;
3169 static struct
3170   {
3171     int mod;
3172     int reg;
3173     int rm;
3174   }
3175 modrm;
3176 static unsigned char need_modrm;
3177 static struct
3178   {
3179     int scale;
3180     int index;
3181     int base;
3182   }
3183 sib;
3184 static struct
3185   {
3186     int register_specifier;
3187     int length;
3188     int prefix;
3189     int w;
3190     int evex;
3191     int r;
3192     int v;
3193     int mask_register_specifier;
3194     int zeroing;
3195     int ll;
3196     int b;
3197   }
3198 vex;
3199 static unsigned char need_vex;
3200 static unsigned char need_vex_reg;
3201 static unsigned char vex_w_done;
3202
3203 struct op
3204   {
3205     const char *name;
3206     unsigned int len;
3207   };
3208
3209 /* If we are accessing mod/rm/reg without need_modrm set, then the
3210    values are stale.  Hitting this abort likely indicates that you
3211    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3212 #define MODRM_CHECK  if (!need_modrm) abort ()
3213
3214 static const char **names64;
3215 static const char **names32;
3216 static const char **names16;
3217 static const char **names8;
3218 static const char **names8rex;
3219 static const char **names_seg;
3220 static const char *index64;
3221 static const char *index32;
3222 static const char **index16;
3223 static const char **names_bnd;
3224
3225 static const char *intel_names64[] = {
3226   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3227   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3228 };
3229 static const char *intel_names32[] = {
3230   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3231   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3232 };
3233 static const char *intel_names16[] = {
3234   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3235   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3236 };
3237 static const char *intel_names8[] = {
3238   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3239 };
3240 static const char *intel_names8rex[] = {
3241   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3242   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3243 };
3244 static const char *intel_names_seg[] = {
3245   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3246 };
3247 static const char *intel_index64 = "riz";
3248 static const char *intel_index32 = "eiz";
3249 static const char *intel_index16[] = {
3250   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3251 };
3252
3253 static const char *att_names64[] = {
3254   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3255   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3256 };
3257 static const char *att_names32[] = {
3258   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3259   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3260 };
3261 static const char *att_names16[] = {
3262   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3263   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3264 };
3265 static const char *att_names8[] = {
3266   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3267 };
3268 static const char *att_names8rex[] = {
3269   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3270   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3271 };
3272 static const char *att_names_seg[] = {
3273   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3274 };
3275 static const char *att_index64 = "%riz";
3276 static const char *att_index32 = "%eiz";
3277 static const char *att_index16[] = {
3278   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3279 };
3280
3281 static const char **names_mm;
3282 static const char *intel_names_mm[] = {
3283   "mm0", "mm1", "mm2", "mm3",
3284   "mm4", "mm5", "mm6", "mm7"
3285 };
3286 static const char *att_names_mm[] = {
3287   "%mm0", "%mm1", "%mm2", "%mm3",
3288   "%mm4", "%mm5", "%mm6", "%mm7"
3289 };
3290
3291 static const char *intel_names_bnd[] = {
3292   "bnd0", "bnd1", "bnd2", "bnd3"
3293 };
3294
3295 static const char *att_names_bnd[] = {
3296   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3297 };
3298
3299 static const char **names_xmm;
3300 static const char *intel_names_xmm[] = {
3301   "xmm0", "xmm1", "xmm2", "xmm3",
3302   "xmm4", "xmm5", "xmm6", "xmm7",
3303   "xmm8", "xmm9", "xmm10", "xmm11",
3304   "xmm12", "xmm13", "xmm14", "xmm15",
3305   "xmm16", "xmm17", "xmm18", "xmm19",
3306   "xmm20", "xmm21", "xmm22", "xmm23",
3307   "xmm24", "xmm25", "xmm26", "xmm27",
3308   "xmm28", "xmm29", "xmm30", "xmm31"
3309 };
3310 static const char *att_names_xmm[] = {
3311   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3312   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3313   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3314   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3315   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3316   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3317   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3318   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3319 };
3320
3321 static const char **names_ymm;
3322 static const char *intel_names_ymm[] = {
3323   "ymm0", "ymm1", "ymm2", "ymm3",
3324   "ymm4", "ymm5", "ymm6", "ymm7",
3325   "ymm8", "ymm9", "ymm10", "ymm11",
3326   "ymm12", "ymm13", "ymm14", "ymm15",
3327   "ymm16", "ymm17", "ymm18", "ymm19",
3328   "ymm20", "ymm21", "ymm22", "ymm23",
3329   "ymm24", "ymm25", "ymm26", "ymm27",
3330   "ymm28", "ymm29", "ymm30", "ymm31"
3331 };
3332 static const char *att_names_ymm[] = {
3333   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3334   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3335   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3336   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3337   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3338   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3339   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3340   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3341 };
3342
3343 static const char **names_zmm;
3344 static const char *intel_names_zmm[] = {
3345   "zmm0", "zmm1", "zmm2", "zmm3",
3346   "zmm4", "zmm5", "zmm6", "zmm7",
3347   "zmm8", "zmm9", "zmm10", "zmm11",
3348   "zmm12", "zmm13", "zmm14", "zmm15",
3349   "zmm16", "zmm17", "zmm18", "zmm19",
3350   "zmm20", "zmm21", "zmm22", "zmm23",
3351   "zmm24", "zmm25", "zmm26", "zmm27",
3352   "zmm28", "zmm29", "zmm30", "zmm31"
3353 };
3354 static const char *att_names_zmm[] = {
3355   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3356   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3357   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3358   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3359   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3360   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3361   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3362   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3363 };
3364
3365 static const char **names_mask;
3366 static const char *intel_names_mask[] = {
3367   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3368 };
3369 static const char *att_names_mask[] = {
3370   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3371 };
3372
3373 static const char *names_rounding[] =
3374 {
3375   "{rn-sae}",
3376   "{rd-sae}",
3377   "{ru-sae}",
3378   "{rz-sae}"
3379 };
3380
3381 static const struct dis386 reg_table[][8] = {
3382   /* REG_80 */
3383   {
3384     { "addA",   { Ebh1, Ib }, 0 },
3385     { "orA",    { Ebh1, Ib }, 0 },
3386     { "adcA",   { Ebh1, Ib }, 0 },
3387     { "sbbA",   { Ebh1, Ib }, 0 },
3388     { "andA",   { Ebh1, Ib }, 0 },
3389     { "subA",   { Ebh1, Ib }, 0 },
3390     { "xorA",   { Ebh1, Ib }, 0 },
3391     { "cmpA",   { Eb, Ib }, 0 },
3392   },
3393   /* REG_81 */
3394   {
3395     { "addQ",   { Evh1, Iv }, 0 },
3396     { "orQ",    { Evh1, Iv }, 0 },
3397     { "adcQ",   { Evh1, Iv }, 0 },
3398     { "sbbQ",   { Evh1, Iv }, 0 },
3399     { "andQ",   { Evh1, Iv }, 0 },
3400     { "subQ",   { Evh1, Iv }, 0 },
3401     { "xorQ",   { Evh1, Iv }, 0 },
3402     { "cmpQ",   { Ev, Iv }, 0 },
3403   },
3404   /* REG_83 */
3405   {
3406     { "addQ",   { Evh1, sIb }, 0 },
3407     { "orQ",    { Evh1, sIb }, 0 },
3408     { "adcQ",   { Evh1, sIb }, 0 },
3409     { "sbbQ",   { Evh1, sIb }, 0 },
3410     { "andQ",   { Evh1, sIb }, 0 },
3411     { "subQ",   { Evh1, sIb }, 0 },
3412     { "xorQ",   { Evh1, sIb }, 0 },
3413     { "cmpQ",   { Ev, sIb }, 0 },
3414   },
3415   /* REG_8F */
3416   {
3417     { "popU",   { stackEv }, 0 },
3418     { XOP_8F_TABLE (XOP_09) },
3419     { Bad_Opcode },
3420     { Bad_Opcode },
3421     { Bad_Opcode },
3422     { XOP_8F_TABLE (XOP_09) },
3423   },
3424   /* REG_C0 */
3425   {
3426     { "rolA",   { Eb, Ib }, 0 },
3427     { "rorA",   { Eb, Ib }, 0 },
3428     { "rclA",   { Eb, Ib }, 0 },
3429     { "rcrA",   { Eb, Ib }, 0 },
3430     { "shlA",   { Eb, Ib }, 0 },
3431     { "shrA",   { Eb, Ib }, 0 },
3432     { Bad_Opcode },
3433     { "sarA",   { Eb, Ib }, 0 },
3434   },
3435   /* REG_C1 */
3436   {
3437     { "rolQ",   { Ev, Ib }, 0 },
3438     { "rorQ",   { Ev, Ib }, 0 },
3439     { "rclQ",   { Ev, Ib }, 0 },
3440     { "rcrQ",   { Ev, Ib }, 0 },
3441     { "shlQ",   { Ev, Ib }, 0 },
3442     { "shrQ",   { Ev, Ib }, 0 },
3443     { Bad_Opcode },
3444     { "sarQ",   { Ev, Ib }, 0 },
3445   },
3446   /* REG_C6 */
3447   {
3448     { "movA",   { Ebh3, Ib }, 0 },
3449     { Bad_Opcode },
3450     { Bad_Opcode },
3451     { Bad_Opcode },
3452     { Bad_Opcode },
3453     { Bad_Opcode },
3454     { Bad_Opcode },
3455     { MOD_TABLE (MOD_C6_REG_7) },
3456   },
3457   /* REG_C7 */
3458   {
3459     { "movQ",   { Evh3, Iv }, 0 },
3460     { Bad_Opcode },
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { Bad_Opcode },
3465     { Bad_Opcode },
3466     { MOD_TABLE (MOD_C7_REG_7) },
3467   },
3468   /* REG_D0 */
3469   {
3470     { "rolA",   { Eb, I1 }, 0 },
3471     { "rorA",   { Eb, I1 }, 0 },
3472     { "rclA",   { Eb, I1 }, 0 },
3473     { "rcrA",   { Eb, I1 }, 0 },
3474     { "shlA",   { Eb, I1 }, 0 },
3475     { "shrA",   { Eb, I1 }, 0 },
3476     { Bad_Opcode },
3477     { "sarA",   { Eb, I1 }, 0 },
3478   },
3479   /* REG_D1 */
3480   {
3481     { "rolQ",   { Ev, I1 }, 0 },
3482     { "rorQ",   { Ev, I1 }, 0 },
3483     { "rclQ",   { Ev, I1 }, 0 },
3484     { "rcrQ",   { Ev, I1 }, 0 },
3485     { "shlQ",   { Ev, I1 }, 0 },
3486     { "shrQ",   { Ev, I1 }, 0 },
3487     { Bad_Opcode },
3488     { "sarQ",   { Ev, I1 }, 0 },
3489   },
3490   /* REG_D2 */
3491   {
3492     { "rolA",   { Eb, CL }, 0 },
3493     { "rorA",   { Eb, CL }, 0 },
3494     { "rclA",   { Eb, CL }, 0 },
3495     { "rcrA",   { Eb, CL }, 0 },
3496     { "shlA",   { Eb, CL }, 0 },
3497     { "shrA",   { Eb, CL }, 0 },
3498     { Bad_Opcode },
3499     { "sarA",   { Eb, CL }, 0 },
3500   },
3501   /* REG_D3 */
3502   {
3503     { "rolQ",   { Ev, CL }, 0 },
3504     { "rorQ",   { Ev, CL }, 0 },
3505     { "rclQ",   { Ev, CL }, 0 },
3506     { "rcrQ",   { Ev, CL }, 0 },
3507     { "shlQ",   { Ev, CL }, 0 },
3508     { "shrQ",   { Ev, CL }, 0 },
3509     { Bad_Opcode },
3510     { "sarQ",   { Ev, CL }, 0 },
3511   },
3512   /* REG_F6 */
3513   {
3514     { "testA",  { Eb, Ib }, 0 },
3515     { Bad_Opcode },
3516     { "notA",   { Ebh1 }, 0 },
3517     { "negA",   { Ebh1 }, 0 },
3518     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3519     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3520     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3521     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3522   },
3523   /* REG_F7 */
3524   {
3525     { "testQ",  { Ev, Iv }, 0 },
3526     { Bad_Opcode },
3527     { "notQ",   { Evh1 }, 0 },
3528     { "negQ",   { Evh1 }, 0 },
3529     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3530     { "imulQ",  { Ev }, 0 },
3531     { "divQ",   { Ev }, 0 },
3532     { "idivQ",  { Ev }, 0 },
3533   },
3534   /* REG_FE */
3535   {
3536     { "incA",   { Ebh1 }, 0 },
3537     { "decA",   { Ebh1 }, 0 },
3538   },
3539   /* REG_FF */
3540   {
3541     { "incQ",   { Evh1 }, 0 },
3542     { "decQ",   { Evh1 }, 0 },
3543     { "call{&|}", { indirEv, BND }, 0 },
3544     { MOD_TABLE (MOD_FF_REG_3) },
3545     { "jmp{&|}", { indirEv, BND }, 0 },
3546     { MOD_TABLE (MOD_FF_REG_5) },
3547     { "pushU",  { stackEv }, 0 },
3548     { Bad_Opcode },
3549   },
3550   /* REG_0F00 */
3551   {
3552     { "sldtD",  { Sv }, 0 },
3553     { "strD",   { Sv }, 0 },
3554     { "lldt",   { Ew }, 0 },
3555     { "ltr",    { Ew }, 0 },
3556     { "verr",   { Ew }, 0 },
3557     { "verw",   { Ew }, 0 },
3558     { Bad_Opcode },
3559     { Bad_Opcode },
3560   },
3561   /* REG_0F01 */
3562   {
3563     { MOD_TABLE (MOD_0F01_REG_0) },
3564     { MOD_TABLE (MOD_0F01_REG_1) },
3565     { MOD_TABLE (MOD_0F01_REG_2) },
3566     { MOD_TABLE (MOD_0F01_REG_3) },
3567     { "smswD",  { Sv }, 0 },
3568     { MOD_TABLE (MOD_0F01_REG_5) },
3569     { "lmsw",   { Ew }, 0 },
3570     { MOD_TABLE (MOD_0F01_REG_7) },
3571   },
3572   /* REG_0F0D */
3573   {
3574     { "prefetch",       { Mb }, 0 },
3575     { "prefetchw",      { Mb }, 0 },
3576     { "prefetchwt1",    { Mb }, 0 },
3577     { "prefetch",       { Mb }, 0 },
3578     { "prefetch",       { Mb }, 0 },
3579     { "prefetch",       { Mb }, 0 },
3580     { "prefetch",       { Mb }, 0 },
3581     { "prefetch",       { Mb }, 0 },
3582   },
3583   /* REG_0F18 */
3584   {
3585     { MOD_TABLE (MOD_0F18_REG_0) },
3586     { MOD_TABLE (MOD_0F18_REG_1) },
3587     { MOD_TABLE (MOD_0F18_REG_2) },
3588     { MOD_TABLE (MOD_0F18_REG_3) },
3589     { MOD_TABLE (MOD_0F18_REG_4) },
3590     { MOD_TABLE (MOD_0F18_REG_5) },
3591     { MOD_TABLE (MOD_0F18_REG_6) },
3592     { MOD_TABLE (MOD_0F18_REG_7) },
3593   },
3594   /* REG_0F71 */
3595   {
3596     { Bad_Opcode },
3597     { Bad_Opcode },
3598     { MOD_TABLE (MOD_0F71_REG_2) },
3599     { Bad_Opcode },
3600     { MOD_TABLE (MOD_0F71_REG_4) },
3601     { Bad_Opcode },
3602     { MOD_TABLE (MOD_0F71_REG_6) },
3603   },
3604   /* REG_0F72 */
3605   {
3606     { Bad_Opcode },
3607     { Bad_Opcode },
3608     { MOD_TABLE (MOD_0F72_REG_2) },
3609     { Bad_Opcode },
3610     { MOD_TABLE (MOD_0F72_REG_4) },
3611     { Bad_Opcode },
3612     { MOD_TABLE (MOD_0F72_REG_6) },
3613   },
3614   /* REG_0F73 */
3615   {
3616     { Bad_Opcode },
3617     { Bad_Opcode },
3618     { MOD_TABLE (MOD_0F73_REG_2) },
3619     { MOD_TABLE (MOD_0F73_REG_3) },
3620     { Bad_Opcode },
3621     { Bad_Opcode },
3622     { MOD_TABLE (MOD_0F73_REG_6) },
3623     { MOD_TABLE (MOD_0F73_REG_7) },
3624   },
3625   /* REG_0FA6 */
3626   {
3627     { "montmul",        { { OP_0f07, 0 } }, 0 },
3628     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3629     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3630   },
3631   /* REG_0FA7 */
3632   {
3633     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3634     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3635     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3636     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3637     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3638     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3639   },
3640   /* REG_0FAE */
3641   {
3642     { MOD_TABLE (MOD_0FAE_REG_0) },
3643     { MOD_TABLE (MOD_0FAE_REG_1) },
3644     { MOD_TABLE (MOD_0FAE_REG_2) },
3645     { MOD_TABLE (MOD_0FAE_REG_3) },
3646     { MOD_TABLE (MOD_0FAE_REG_4) },
3647     { MOD_TABLE (MOD_0FAE_REG_5) },
3648     { MOD_TABLE (MOD_0FAE_REG_6) },
3649     { MOD_TABLE (MOD_0FAE_REG_7) },
3650   },
3651   /* REG_0FBA */
3652   {
3653     { Bad_Opcode },
3654     { Bad_Opcode },
3655     { Bad_Opcode },
3656     { Bad_Opcode },
3657     { "btQ",    { Ev, Ib }, 0 },
3658     { "btsQ",   { Evh1, Ib }, 0 },
3659     { "btrQ",   { Evh1, Ib }, 0 },
3660     { "btcQ",   { Evh1, Ib }, 0 },
3661   },
3662   /* REG_0FC7 */
3663   {
3664     { Bad_Opcode },
3665     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3666     { Bad_Opcode },
3667     { MOD_TABLE (MOD_0FC7_REG_3) },
3668     { MOD_TABLE (MOD_0FC7_REG_4) },
3669     { MOD_TABLE (MOD_0FC7_REG_5) },
3670     { MOD_TABLE (MOD_0FC7_REG_6) },
3671     { MOD_TABLE (MOD_0FC7_REG_7) },
3672   },
3673   /* REG_VEX_0F71 */
3674   {
3675     { Bad_Opcode },
3676     { Bad_Opcode },
3677     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3678     { Bad_Opcode },
3679     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3680     { Bad_Opcode },
3681     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3682   },
3683   /* REG_VEX_0F72 */
3684   {
3685     { Bad_Opcode },
3686     { Bad_Opcode },
3687     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3688     { Bad_Opcode },
3689     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3690     { Bad_Opcode },
3691     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3692   },
3693   /* REG_VEX_0F73 */
3694   {
3695     { Bad_Opcode },
3696     { Bad_Opcode },
3697     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3698     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3699     { Bad_Opcode },
3700     { Bad_Opcode },
3701     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3702     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3703   },
3704   /* REG_VEX_0FAE */
3705   {
3706     { Bad_Opcode },
3707     { Bad_Opcode },
3708     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3709     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3710   },
3711   /* REG_VEX_0F38F3 */
3712   {
3713     { Bad_Opcode },
3714     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3715     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3716     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3717   },
3718   /* REG_XOP_LWPCB */
3719   {
3720     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3721     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3722   },
3723   /* REG_XOP_LWP */
3724   {
3725     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3726     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3727   },
3728   /* REG_XOP_TBM_01 */
3729   {
3730     { Bad_Opcode },
3731     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3732     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3733     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3734     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3735     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3736     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3737     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3738   },
3739   /* REG_XOP_TBM_02 */
3740   {
3741     { Bad_Opcode },
3742     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3743     { Bad_Opcode },
3744     { Bad_Opcode },
3745     { Bad_Opcode },
3746     { Bad_Opcode },
3747     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3748   },
3749 #define NEED_REG_TABLE
3750 #include "i386-dis-evex.h"
3751 #undef NEED_REG_TABLE
3752 };
3753
3754 static const struct dis386 prefix_table[][4] = {
3755   /* PREFIX_90 */
3756   {
3757     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3758     { "pause", { XX }, 0 },
3759     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3760     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3761   },
3762
3763   /* PREFIX_0F10 */
3764   {
3765     { "movups", { XM, EXx }, PREFIX_OPCODE },
3766     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3767     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3768     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3769   },
3770
3771   /* PREFIX_0F11 */
3772   {
3773     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3774     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3775     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3776     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3777   },
3778
3779   /* PREFIX_0F12 */
3780   {
3781     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3782     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3783     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3784     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3785   },
3786
3787   /* PREFIX_0F16 */
3788   {
3789     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3790     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3791     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3792   },
3793
3794   /* PREFIX_0F1A */
3795   {
3796     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3797     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3798     { "bndmov", { Gbnd, Ebnd }, 0 },
3799     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3800   },
3801
3802   /* PREFIX_0F1B */
3803   {
3804     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3805     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3806     { "bndmov", { Ebnd, Gbnd }, 0 },
3807     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3808   },
3809
3810   /* PREFIX_0F2A */
3811   {
3812     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3813     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3814     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3815     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3816   },
3817
3818   /* PREFIX_0F2B */
3819   {
3820     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3821     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3822     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3823     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3824   },
3825
3826   /* PREFIX_0F2C */
3827   {
3828     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3829     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3830     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3831     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3832   },
3833
3834   /* PREFIX_0F2D */
3835   {
3836     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3837     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3838     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3839     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3840   },
3841
3842   /* PREFIX_0F2E */
3843   {
3844     { "ucomiss",{ XM, EXd }, 0 },
3845     { Bad_Opcode },
3846     { "ucomisd",{ XM, EXq }, 0 },
3847   },
3848
3849   /* PREFIX_0F2F */
3850   {
3851     { "comiss", { XM, EXd }, 0 },
3852     { Bad_Opcode },
3853     { "comisd", { XM, EXq }, 0 },
3854   },
3855
3856   /* PREFIX_0F51 */
3857   {
3858     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3859     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3860     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3861     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3862   },
3863
3864   /* PREFIX_0F52 */
3865   {
3866     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3867     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3868   },
3869
3870   /* PREFIX_0F53 */
3871   {
3872     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3873     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3874   },
3875
3876   /* PREFIX_0F58 */
3877   {
3878     { "addps", { XM, EXx }, PREFIX_OPCODE },
3879     { "addss", { XM, EXd }, PREFIX_OPCODE },
3880     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3881     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3882   },
3883
3884   /* PREFIX_0F59 */
3885   {
3886     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3887     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3888     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3889     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3890   },
3891
3892   /* PREFIX_0F5A */
3893   {
3894     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3895     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3896     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3897     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3898   },
3899
3900   /* PREFIX_0F5B */
3901   {
3902     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3903     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3904     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3905   },
3906
3907   /* PREFIX_0F5C */
3908   {
3909     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3910     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3911     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3912     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3913   },
3914
3915   /* PREFIX_0F5D */
3916   {
3917     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3918     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3919     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3920     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3921   },
3922
3923   /* PREFIX_0F5E */
3924   {
3925     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3926     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3927     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3928     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3929   },
3930
3931   /* PREFIX_0F5F */
3932   {
3933     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3934     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3935     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3936     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3937   },
3938
3939   /* PREFIX_0F60 */
3940   {
3941     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3942     { Bad_Opcode },
3943     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3944   },
3945
3946   /* PREFIX_0F61 */
3947   {
3948     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3949     { Bad_Opcode },
3950     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3951   },
3952
3953   /* PREFIX_0F62 */
3954   {
3955     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3956     { Bad_Opcode },
3957     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3958   },
3959
3960   /* PREFIX_0F6C */
3961   {
3962     { Bad_Opcode },
3963     { Bad_Opcode },
3964     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3965   },
3966
3967   /* PREFIX_0F6D */
3968   {
3969     { Bad_Opcode },
3970     { Bad_Opcode },
3971     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3972   },
3973
3974   /* PREFIX_0F6F */
3975   {
3976     { "movq",   { MX, EM }, PREFIX_OPCODE },
3977     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3978     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3979   },
3980
3981   /* PREFIX_0F70 */
3982   {
3983     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3984     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3985     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3986     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3987   },
3988
3989   /* PREFIX_0F73_REG_3 */
3990   {
3991     { Bad_Opcode },
3992     { Bad_Opcode },
3993     { "psrldq", { XS, Ib }, 0 },
3994   },
3995
3996   /* PREFIX_0F73_REG_7 */
3997   {
3998     { Bad_Opcode },
3999     { Bad_Opcode },
4000     { "pslldq", { XS, Ib }, 0 },
4001   },
4002
4003   /* PREFIX_0F78 */
4004   {
4005     {"vmread",  { Em, Gm }, 0 },
4006     { Bad_Opcode },
4007     {"extrq",   { XS, Ib, Ib }, 0 },
4008     {"insertq", { XM, XS, Ib, Ib }, 0 },
4009   },
4010
4011   /* PREFIX_0F79 */
4012   {
4013     {"vmwrite", { Gm, Em }, 0 },
4014     { Bad_Opcode },
4015     {"extrq",   { XM, XS }, 0 },
4016     {"insertq", { XM, XS }, 0 },
4017   },
4018
4019   /* PREFIX_0F7C */
4020   {
4021     { Bad_Opcode },
4022     { Bad_Opcode },
4023     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4024     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4025   },
4026
4027   /* PREFIX_0F7D */
4028   {
4029     { Bad_Opcode },
4030     { Bad_Opcode },
4031     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4032     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4033   },
4034
4035   /* PREFIX_0F7E */
4036   {
4037     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4038     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4039     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4040   },
4041
4042   /* PREFIX_0F7F */
4043   {
4044     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4045     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4046     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4047   },
4048
4049   /* PREFIX_0FAE_REG_0 */
4050   {
4051     { Bad_Opcode },
4052     { "rdfsbase", { Ev }, 0 },
4053   },
4054
4055   /* PREFIX_0FAE_REG_1 */
4056   {
4057     { Bad_Opcode },
4058     { "rdgsbase", { Ev }, 0 },
4059   },
4060
4061   /* PREFIX_0FAE_REG_2 */
4062   {
4063     { Bad_Opcode },
4064     { "wrfsbase", { Ev }, 0 },
4065   },
4066
4067   /* PREFIX_0FAE_REG_3 */
4068   {
4069     { Bad_Opcode },
4070     { "wrgsbase", { Ev }, 0 },
4071   },
4072
4073   /* PREFIX_MOD_0_0FAE_REG_4 */
4074   {
4075     { "xsave",  { FXSAVE }, 0 },
4076     { "ptwrite%LQ", { Edq }, 0 },
4077   },
4078
4079   /* PREFIX_MOD_3_0FAE_REG_4 */
4080   {
4081     { Bad_Opcode },
4082     { "ptwrite%LQ", { Edq }, 0 },
4083   },
4084
4085   /* PREFIX_0FAE_REG_6 */
4086   {
4087     { "xsaveopt",      { FXSAVE }, 0 },
4088     { Bad_Opcode },
4089     { "clwb",   { Mb }, 0 },
4090   },
4091
4092   /* PREFIX_0FAE_REG_7 */
4093   {
4094     { "clflush",        { Mb }, 0 },
4095     { Bad_Opcode },
4096     { "clflushopt",     { Mb }, 0 },
4097   },
4098
4099   /* PREFIX_0FB8 */
4100   {
4101     { Bad_Opcode },
4102     { "popcntS", { Gv, Ev }, 0 },
4103   },
4104
4105   /* PREFIX_0FBC */
4106   {
4107     { "bsfS",   { Gv, Ev }, 0 },
4108     { "tzcntS", { Gv, Ev }, 0 },
4109     { "bsfS",   { Gv, Ev }, 0 },
4110   },
4111
4112   /* PREFIX_0FBD */
4113   {
4114     { "bsrS",   { Gv, Ev }, 0 },
4115     { "lzcntS", { Gv, Ev }, 0 },
4116     { "bsrS",   { Gv, Ev }, 0 },
4117   },
4118
4119   /* PREFIX_0FC2 */
4120   {
4121     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4122     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4123     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4124     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4125   },
4126
4127   /* PREFIX_MOD_0_0FC3 */
4128   {
4129     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4130   },
4131
4132   /* PREFIX_MOD_0_0FC7_REG_6 */
4133   {
4134     { "vmptrld",{ Mq }, 0 },
4135     { "vmxon",  { Mq }, 0 },
4136     { "vmclear",{ Mq }, 0 },
4137   },
4138
4139   /* PREFIX_MOD_3_0FC7_REG_6 */
4140   {
4141     { "rdrand", { Ev }, 0 },
4142     { Bad_Opcode },
4143     { "rdrand", { Ev }, 0 }
4144   },
4145
4146   /* PREFIX_MOD_3_0FC7_REG_7 */
4147   {
4148     { "rdseed", { Ev }, 0 },
4149     { "rdpid",  { Em }, 0 },
4150     { "rdseed", { Ev }, 0 },
4151   },
4152
4153   /* PREFIX_0FD0 */
4154   {
4155     { Bad_Opcode },
4156     { Bad_Opcode },
4157     { "addsubpd", { XM, EXx }, 0 },
4158     { "addsubps", { XM, EXx }, 0 },
4159   },
4160
4161   /* PREFIX_0FD6 */
4162   {
4163     { Bad_Opcode },
4164     { "movq2dq",{ XM, MS }, 0 },
4165     { "movq",   { EXqS, XM }, 0 },
4166     { "movdq2q",{ MX, XS }, 0 },
4167   },
4168
4169   /* PREFIX_0FE6 */
4170   {
4171     { Bad_Opcode },
4172     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4173     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4174     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4175   },
4176
4177   /* PREFIX_0FE7 */
4178   {
4179     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4180     { Bad_Opcode },
4181     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4182   },
4183
4184   /* PREFIX_0FF0 */
4185   {
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4190   },
4191
4192   /* PREFIX_0FF7 */
4193   {
4194     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4195     { Bad_Opcode },
4196     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4197   },
4198
4199   /* PREFIX_0F3810 */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4204   },
4205
4206   /* PREFIX_0F3814 */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4211   },
4212
4213   /* PREFIX_0F3815 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4218   },
4219
4220   /* PREFIX_0F3817 */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4225   },
4226
4227   /* PREFIX_0F3820 */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4232   },
4233
4234   /* PREFIX_0F3821 */
4235   {
4236     { Bad_Opcode },
4237     { Bad_Opcode },
4238     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4239   },
4240
4241   /* PREFIX_0F3822 */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4246   },
4247
4248   /* PREFIX_0F3823 */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4253   },
4254
4255   /* PREFIX_0F3824 */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4260   },
4261
4262   /* PREFIX_0F3825 */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4267   },
4268
4269   /* PREFIX_0F3828 */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4274   },
4275
4276   /* PREFIX_0F3829 */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0F382A */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4288   },
4289
4290   /* PREFIX_0F382B */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4295   },
4296
4297   /* PREFIX_0F3830 */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4302   },
4303
4304   /* PREFIX_0F3831 */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4309   },
4310
4311   /* PREFIX_0F3832 */
4312   {
4313     { Bad_Opcode },
4314     { Bad_Opcode },
4315     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4316   },
4317
4318   /* PREFIX_0F3833 */
4319   {
4320     { Bad_Opcode },
4321     { Bad_Opcode },
4322     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4323   },
4324
4325   /* PREFIX_0F3834 */
4326   {
4327     { Bad_Opcode },
4328     { Bad_Opcode },
4329     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4330   },
4331
4332   /* PREFIX_0F3835 */
4333   {
4334     { Bad_Opcode },
4335     { Bad_Opcode },
4336     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4337   },
4338
4339   /* PREFIX_0F3837 */
4340   {
4341     { Bad_Opcode },
4342     { Bad_Opcode },
4343     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4344   },
4345
4346   /* PREFIX_0F3838 */
4347   {
4348     { Bad_Opcode },
4349     { Bad_Opcode },
4350     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4351   },
4352
4353   /* PREFIX_0F3839 */
4354   {
4355     { Bad_Opcode },
4356     { Bad_Opcode },
4357     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4358   },
4359
4360   /* PREFIX_0F383A */
4361   {
4362     { Bad_Opcode },
4363     { Bad_Opcode },
4364     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4365   },
4366
4367   /* PREFIX_0F383B */
4368   {
4369     { Bad_Opcode },
4370     { Bad_Opcode },
4371     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4372   },
4373
4374   /* PREFIX_0F383C */
4375   {
4376     { Bad_Opcode },
4377     { Bad_Opcode },
4378     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4379   },
4380
4381   /* PREFIX_0F383D */
4382   {
4383     { Bad_Opcode },
4384     { Bad_Opcode },
4385     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F383E */
4389   {
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4393   },
4394
4395   /* PREFIX_0F383F */
4396   {
4397     { Bad_Opcode },
4398     { Bad_Opcode },
4399     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4400   },
4401
4402   /* PREFIX_0F3840 */
4403   {
4404     { Bad_Opcode },
4405     { Bad_Opcode },
4406     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4407   },
4408
4409   /* PREFIX_0F3841 */
4410   {
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4414   },
4415
4416   /* PREFIX_0F3880 */
4417   {
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4421   },
4422
4423   /* PREFIX_0F3881 */
4424   {
4425     { Bad_Opcode },
4426     { Bad_Opcode },
4427     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4428   },
4429
4430   /* PREFIX_0F3882 */
4431   {
4432     { Bad_Opcode },
4433     { Bad_Opcode },
4434     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4435   },
4436
4437   /* PREFIX_0F38C8 */
4438   {
4439     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4440   },
4441
4442   /* PREFIX_0F38C9 */
4443   {
4444     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4445   },
4446
4447   /* PREFIX_0F38CA */
4448   {
4449     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4450   },
4451
4452   /* PREFIX_0F38CB */
4453   {
4454     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4455   },
4456
4457   /* PREFIX_0F38CC */
4458   {
4459     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4460   },
4461
4462   /* PREFIX_0F38CD */
4463   {
4464     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4465   },
4466
4467   /* PREFIX_0F38DB */
4468   {
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4472   },
4473
4474   /* PREFIX_0F38DC */
4475   {
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4479   },
4480
4481   /* PREFIX_0F38DD */
4482   {
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4486   },
4487
4488   /* PREFIX_0F38DE */
4489   {
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4493   },
4494
4495   /* PREFIX_0F38DF */
4496   {
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4500   },
4501
4502   /* PREFIX_0F38F0 */
4503   {
4504     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4505     { Bad_Opcode },
4506     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4507     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4508   },
4509
4510   /* PREFIX_0F38F1 */
4511   {
4512     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4513     { Bad_Opcode },
4514     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4515     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4516   },
4517
4518   /* PREFIX_0F38F6 */
4519   {
4520     { Bad_Opcode },
4521     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4522     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4523     { Bad_Opcode },
4524   },
4525
4526   /* PREFIX_0F3A08 */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4531   },
4532
4533   /* PREFIX_0F3A09 */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4538   },
4539
4540   /* PREFIX_0F3A0A */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4545   },
4546
4547   /* PREFIX_0F3A0B */
4548   {
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4552   },
4553
4554   /* PREFIX_0F3A0C */
4555   {
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4559   },
4560
4561   /* PREFIX_0F3A0D */
4562   {
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4566   },
4567
4568   /* PREFIX_0F3A0E */
4569   {
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4573   },
4574
4575   /* PREFIX_0F3A14 */
4576   {
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4580   },
4581
4582   /* PREFIX_0F3A15 */
4583   {
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4587   },
4588
4589   /* PREFIX_0F3A16 */
4590   {
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4594   },
4595
4596   /* PREFIX_0F3A17 */
4597   {
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4601   },
4602
4603   /* PREFIX_0F3A20 */
4604   {
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4608   },
4609
4610   /* PREFIX_0F3A21 */
4611   {
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4615   },
4616
4617   /* PREFIX_0F3A22 */
4618   {
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4622   },
4623
4624   /* PREFIX_0F3A40 */
4625   {
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4629   },
4630
4631   /* PREFIX_0F3A41 */
4632   {
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4636   },
4637
4638   /* PREFIX_0F3A42 */
4639   {
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4643   },
4644
4645   /* PREFIX_0F3A44 */
4646   {
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4650   },
4651
4652   /* PREFIX_0F3A60 */
4653   {
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4657   },
4658
4659   /* PREFIX_0F3A61 */
4660   {
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4664   },
4665
4666   /* PREFIX_0F3A62 */
4667   {
4668     { Bad_Opcode },
4669     { Bad_Opcode },
4670     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4671   },
4672
4673   /* PREFIX_0F3A63 */
4674   {
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4678   },
4679
4680   /* PREFIX_0F3ACC */
4681   {
4682     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4683   },
4684
4685   /* PREFIX_0F3ADF */
4686   {
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4690   },
4691
4692   /* PREFIX_VEX_0F10 */
4693   {
4694     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4695     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4696     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4697     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4698   },
4699
4700   /* PREFIX_VEX_0F11 */
4701   {
4702     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4703     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4704     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4705     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4706   },
4707
4708   /* PREFIX_VEX_0F12 */
4709   {
4710     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4711     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4712     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4713     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4714   },
4715
4716   /* PREFIX_VEX_0F16 */
4717   {
4718     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4719     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4720     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4721   },
4722
4723   /* PREFIX_VEX_0F2A */
4724   {
4725     { Bad_Opcode },
4726     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4727     { Bad_Opcode },
4728     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4729   },
4730
4731   /* PREFIX_VEX_0F2C */
4732   {
4733     { Bad_Opcode },
4734     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4735     { Bad_Opcode },
4736     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4737   },
4738
4739   /* PREFIX_VEX_0F2D */
4740   {
4741     { Bad_Opcode },
4742     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4743     { Bad_Opcode },
4744     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4745   },
4746
4747   /* PREFIX_VEX_0F2E */
4748   {
4749     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4750     { Bad_Opcode },
4751     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4752   },
4753
4754   /* PREFIX_VEX_0F2F */
4755   {
4756     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4757     { Bad_Opcode },
4758     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4759   },
4760
4761   /* PREFIX_VEX_0F41 */
4762   {
4763     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4764     { Bad_Opcode },
4765     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4766   },
4767
4768   /* PREFIX_VEX_0F42 */
4769   {
4770     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4771     { Bad_Opcode },
4772     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4773   },
4774
4775   /* PREFIX_VEX_0F44 */
4776   {
4777     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4778     { Bad_Opcode },
4779     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4780   },
4781
4782   /* PREFIX_VEX_0F45 */
4783   {
4784     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4785     { Bad_Opcode },
4786     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4787   },
4788
4789   /* PREFIX_VEX_0F46 */
4790   {
4791     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4792     { Bad_Opcode },
4793     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4794   },
4795
4796   /* PREFIX_VEX_0F47 */
4797   {
4798     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4799     { Bad_Opcode },
4800     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4801   },
4802
4803   /* PREFIX_VEX_0F4A */
4804   {
4805     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4806     { Bad_Opcode },
4807     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4808   },
4809
4810   /* PREFIX_VEX_0F4B */
4811   {
4812     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4813     { Bad_Opcode },
4814     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4815   },
4816
4817   /* PREFIX_VEX_0F51 */
4818   {
4819     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4820     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4821     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4822     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4823   },
4824
4825   /* PREFIX_VEX_0F52 */
4826   {
4827     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4828     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4829   },
4830
4831   /* PREFIX_VEX_0F53 */
4832   {
4833     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4834     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4835   },
4836
4837   /* PREFIX_VEX_0F58 */
4838   {
4839     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4840     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4841     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4842     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4843   },
4844
4845   /* PREFIX_VEX_0F59 */
4846   {
4847     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4848     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4849     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4850     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4851   },
4852
4853   /* PREFIX_VEX_0F5A */
4854   {
4855     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4856     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4857     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4858     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4859   },
4860
4861   /* PREFIX_VEX_0F5B */
4862   {
4863     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4864     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4865     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4866   },
4867
4868   /* PREFIX_VEX_0F5C */
4869   {
4870     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4871     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4872     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4873     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4874   },
4875
4876   /* PREFIX_VEX_0F5D */
4877   {
4878     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4879     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4880     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4881     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4882   },
4883
4884   /* PREFIX_VEX_0F5E */
4885   {
4886     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4887     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4888     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4889     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4890   },
4891
4892   /* PREFIX_VEX_0F5F */
4893   {
4894     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4895     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4896     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4897     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4898   },
4899
4900   /* PREFIX_VEX_0F60 */
4901   {
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4905   },
4906
4907   /* PREFIX_VEX_0F61 */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4912   },
4913
4914   /* PREFIX_VEX_0F62 */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4919   },
4920
4921   /* PREFIX_VEX_0F63 */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4926   },
4927
4928   /* PREFIX_VEX_0F64 */
4929   {
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4933   },
4934
4935   /* PREFIX_VEX_0F65 */
4936   {
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4940   },
4941
4942   /* PREFIX_VEX_0F66 */
4943   {
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4947   },
4948
4949   /* PREFIX_VEX_0F67 */
4950   {
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4954   },
4955
4956   /* PREFIX_VEX_0F68 */
4957   {
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4961   },
4962
4963   /* PREFIX_VEX_0F69 */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4968   },
4969
4970   /* PREFIX_VEX_0F6A */
4971   {
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4975   },
4976
4977   /* PREFIX_VEX_0F6B */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4982   },
4983
4984   /* PREFIX_VEX_0F6C */
4985   {
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4989   },
4990
4991   /* PREFIX_VEX_0F6D */
4992   {
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4996   },
4997
4998   /* PREFIX_VEX_0F6E */
4999   {
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5003   },
5004
5005   /* PREFIX_VEX_0F6F */
5006   {
5007     { Bad_Opcode },
5008     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5009     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5010   },
5011
5012   /* PREFIX_VEX_0F70 */
5013   {
5014     { Bad_Opcode },
5015     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5016     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5017     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5018   },
5019
5020   /* PREFIX_VEX_0F71_REG_2 */
5021   {
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5025   },
5026
5027   /* PREFIX_VEX_0F71_REG_4 */
5028   {
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5032   },
5033
5034   /* PREFIX_VEX_0F71_REG_6 */
5035   {
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5039   },
5040
5041   /* PREFIX_VEX_0F72_REG_2 */
5042   {
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5046   },
5047
5048   /* PREFIX_VEX_0F72_REG_4 */
5049   {
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5053   },
5054
5055   /* PREFIX_VEX_0F72_REG_6 */
5056   {
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5060   },
5061
5062   /* PREFIX_VEX_0F73_REG_2 */
5063   {
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5067   },
5068
5069   /* PREFIX_VEX_0F73_REG_3 */
5070   {
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5074   },
5075
5076   /* PREFIX_VEX_0F73_REG_6 */
5077   {
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5081   },
5082
5083   /* PREFIX_VEX_0F73_REG_7 */
5084   {
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5088   },
5089
5090   /* PREFIX_VEX_0F74 */
5091   {
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5095   },
5096
5097   /* PREFIX_VEX_0F75 */
5098   {
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5102   },
5103
5104   /* PREFIX_VEX_0F76 */
5105   {
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5109   },
5110
5111   /* PREFIX_VEX_0F77 */
5112   {
5113     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5114   },
5115
5116   /* PREFIX_VEX_0F7C */
5117   {
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5121     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5122   },
5123
5124   /* PREFIX_VEX_0F7D */
5125   {
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5129     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5130   },
5131
5132   /* PREFIX_VEX_0F7E */
5133   {
5134     { Bad_Opcode },
5135     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5136     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0F7F */
5140   {
5141     { Bad_Opcode },
5142     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5143     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5144   },
5145
5146   /* PREFIX_VEX_0F90 */
5147   {
5148     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5149     { Bad_Opcode },
5150     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5151   },
5152
5153   /* PREFIX_VEX_0F91 */
5154   {
5155     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5156     { Bad_Opcode },
5157     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5158   },
5159
5160   /* PREFIX_VEX_0F92 */
5161   {
5162     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5163     { Bad_Opcode },
5164     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5165     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5166   },
5167
5168   /* PREFIX_VEX_0F93 */
5169   {
5170     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5171     { Bad_Opcode },
5172     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5173     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5174   },
5175
5176   /* PREFIX_VEX_0F98 */
5177   {
5178     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5179     { Bad_Opcode },
5180     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5181   },
5182
5183   /* PREFIX_VEX_0F99 */
5184   {
5185     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5186     { Bad_Opcode },
5187     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5188   },
5189
5190   /* PREFIX_VEX_0FC2 */
5191   {
5192     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5193     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5194     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5195     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5196   },
5197
5198   /* PREFIX_VEX_0FC4 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5203   },
5204
5205   /* PREFIX_VEX_0FC5 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5210   },
5211
5212   /* PREFIX_VEX_0FD0 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5217     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5218   },
5219
5220   /* PREFIX_VEX_0FD1 */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5225   },
5226
5227   /* PREFIX_VEX_0FD2 */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5232   },
5233
5234   /* PREFIX_VEX_0FD3 */
5235   {
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5239   },
5240
5241   /* PREFIX_VEX_0FD4 */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5246   },
5247
5248   /* PREFIX_VEX_0FD5 */
5249   {
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5253   },
5254
5255   /* PREFIX_VEX_0FD6 */
5256   {
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5260   },
5261
5262   /* PREFIX_VEX_0FD7 */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5267   },
5268
5269   /* PREFIX_VEX_0FD8 */
5270   {
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5274   },
5275
5276   /* PREFIX_VEX_0FD9 */
5277   {
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5281   },
5282
5283   /* PREFIX_VEX_0FDA */
5284   {
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5288   },
5289
5290   /* PREFIX_VEX_0FDB */
5291   {
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5295   },
5296
5297   /* PREFIX_VEX_0FDC */
5298   {
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5302   },
5303
5304   /* PREFIX_VEX_0FDD */
5305   {
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5309   },
5310
5311   /* PREFIX_VEX_0FDE */
5312   {
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5316   },
5317
5318   /* PREFIX_VEX_0FDF */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5323   },
5324
5325   /* PREFIX_VEX_0FE0 */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5330   },
5331
5332   /* PREFIX_VEX_0FE1 */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5337   },
5338
5339   /* PREFIX_VEX_0FE2 */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5344   },
5345
5346   /* PREFIX_VEX_0FE3 */
5347   {
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5351   },
5352
5353   /* PREFIX_VEX_0FE4 */
5354   {
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5358   },
5359
5360   /* PREFIX_VEX_0FE5 */
5361   {
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5365   },
5366
5367   /* PREFIX_VEX_0FE6 */
5368   {
5369     { Bad_Opcode },
5370     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5371     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5372     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5373   },
5374
5375   /* PREFIX_VEX_0FE7 */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5380   },
5381
5382   /* PREFIX_VEX_0FE8 */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5387   },
5388
5389   /* PREFIX_VEX_0FE9 */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5394   },
5395
5396   /* PREFIX_VEX_0FEA */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5401   },
5402
5403   /* PREFIX_VEX_0FEB */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5408   },
5409
5410   /* PREFIX_VEX_0FEC */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5415   },
5416
5417   /* PREFIX_VEX_0FED */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5422   },
5423
5424   /* PREFIX_VEX_0FEE */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5429   },
5430
5431   /* PREFIX_VEX_0FEF */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5436   },
5437
5438   /* PREFIX_VEX_0FF0 */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5444   },
5445
5446   /* PREFIX_VEX_0FF1 */
5447   {
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5451   },
5452
5453   /* PREFIX_VEX_0FF2 */
5454   {
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5458   },
5459
5460   /* PREFIX_VEX_0FF3 */
5461   {
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5465   },
5466
5467   /* PREFIX_VEX_0FF4 */
5468   {
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5472   },
5473
5474   /* PREFIX_VEX_0FF5 */
5475   {
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5479   },
5480
5481   /* PREFIX_VEX_0FF6 */
5482   {
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5486   },
5487
5488   /* PREFIX_VEX_0FF7 */
5489   {
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5493   },
5494
5495   /* PREFIX_VEX_0FF8 */
5496   {
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5500   },
5501
5502   /* PREFIX_VEX_0FF9 */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5507   },
5508
5509   /* PREFIX_VEX_0FFA */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5514   },
5515
5516   /* PREFIX_VEX_0FFB */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5521   },
5522
5523   /* PREFIX_VEX_0FFC */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5528   },
5529
5530   /* PREFIX_VEX_0FFD */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5535   },
5536
5537   /* PREFIX_VEX_0FFE */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5542   },
5543
5544   /* PREFIX_VEX_0F3800 */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5549   },
5550
5551   /* PREFIX_VEX_0F3801 */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5556   },
5557
5558   /* PREFIX_VEX_0F3802 */
5559   {
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5563   },
5564
5565   /* PREFIX_VEX_0F3803 */
5566   {
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5570   },
5571
5572   /* PREFIX_VEX_0F3804 */
5573   {
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5577   },
5578
5579   /* PREFIX_VEX_0F3805 */
5580   {
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5584   },
5585
5586   /* PREFIX_VEX_0F3806 */
5587   {
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5591   },
5592
5593   /* PREFIX_VEX_0F3807 */
5594   {
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5598   },
5599
5600   /* PREFIX_VEX_0F3808 */
5601   {
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5605   },
5606
5607   /* PREFIX_VEX_0F3809 */
5608   {
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5612   },
5613
5614   /* PREFIX_VEX_0F380A */
5615   {
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5619   },
5620
5621   /* PREFIX_VEX_0F380B */
5622   {
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5626   },
5627
5628   /* PREFIX_VEX_0F380C */
5629   {
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5633   },
5634
5635   /* PREFIX_VEX_0F380D */
5636   {
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5640   },
5641
5642   /* PREFIX_VEX_0F380E */
5643   {
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5647   },
5648
5649   /* PREFIX_VEX_0F380F */
5650   {
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5654   },
5655
5656   /* PREFIX_VEX_0F3813 */
5657   {
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5661   },
5662
5663   /* PREFIX_VEX_0F3816 */
5664   {
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5668   },
5669
5670   /* PREFIX_VEX_0F3817 */
5671   {
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5675   },
5676
5677   /* PREFIX_VEX_0F3818 */
5678   {
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5682   },
5683
5684   /* PREFIX_VEX_0F3819 */
5685   {
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5689   },
5690
5691   /* PREFIX_VEX_0F381A */
5692   {
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5696   },
5697
5698   /* PREFIX_VEX_0F381C */
5699   {
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5703   },
5704
5705   /* PREFIX_VEX_0F381D */
5706   {
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5710   },
5711
5712   /* PREFIX_VEX_0F381E */
5713   {
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5717   },
5718
5719   /* PREFIX_VEX_0F3820 */
5720   {
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5724   },
5725
5726   /* PREFIX_VEX_0F3821 */
5727   {
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5731   },
5732
5733   /* PREFIX_VEX_0F3822 */
5734   {
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5738   },
5739
5740   /* PREFIX_VEX_0F3823 */
5741   {
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5745   },
5746
5747   /* PREFIX_VEX_0F3824 */
5748   {
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5752   },
5753
5754   /* PREFIX_VEX_0F3825 */
5755   {
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5759   },
5760
5761   /* PREFIX_VEX_0F3828 */
5762   {
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5766   },
5767
5768   /* PREFIX_VEX_0F3829 */
5769   {
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5773   },
5774
5775   /* PREFIX_VEX_0F382A */
5776   {
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5780   },
5781
5782   /* PREFIX_VEX_0F382B */
5783   {
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5787   },
5788
5789   /* PREFIX_VEX_0F382C */
5790   {
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5794   },
5795
5796   /* PREFIX_VEX_0F382D */
5797   {
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5801   },
5802
5803   /* PREFIX_VEX_0F382E */
5804   {
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5808   },
5809
5810   /* PREFIX_VEX_0F382F */
5811   {
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5815   },
5816
5817   /* PREFIX_VEX_0F3830 */
5818   {
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5822   },
5823
5824   /* PREFIX_VEX_0F3831 */
5825   {
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5829   },
5830
5831   /* PREFIX_VEX_0F3832 */
5832   {
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5836   },
5837
5838   /* PREFIX_VEX_0F3833 */
5839   {
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5843   },
5844
5845   /* PREFIX_VEX_0F3834 */
5846   {
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5850   },
5851
5852   /* PREFIX_VEX_0F3835 */
5853   {
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5857   },
5858
5859   /* PREFIX_VEX_0F3836 */
5860   {
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5864   },
5865
5866   /* PREFIX_VEX_0F3837 */
5867   {
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5871   },
5872
5873   /* PREFIX_VEX_0F3838 */
5874   {
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5878   },
5879
5880   /* PREFIX_VEX_0F3839 */
5881   {
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5885   },
5886
5887   /* PREFIX_VEX_0F383A */
5888   {
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5892   },
5893
5894   /* PREFIX_VEX_0F383B */
5895   {
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5899   },
5900
5901   /* PREFIX_VEX_0F383C */
5902   {
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5906   },
5907
5908   /* PREFIX_VEX_0F383D */
5909   {
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5913   },
5914
5915   /* PREFIX_VEX_0F383E */
5916   {
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5920   },
5921
5922   /* PREFIX_VEX_0F383F */
5923   {
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5927   },
5928
5929   /* PREFIX_VEX_0F3840 */
5930   {
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5934   },
5935
5936   /* PREFIX_VEX_0F3841 */
5937   {
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5941   },
5942
5943   /* PREFIX_VEX_0F3845 */
5944   {
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5948   },
5949
5950   /* PREFIX_VEX_0F3846 */
5951   {
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5955   },
5956
5957   /* PREFIX_VEX_0F3847 */
5958   {
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5962   },
5963
5964   /* PREFIX_VEX_0F3858 */
5965   {
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5969   },
5970
5971   /* PREFIX_VEX_0F3859 */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5976   },
5977
5978   /* PREFIX_VEX_0F385A */
5979   {
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5983   },
5984
5985   /* PREFIX_VEX_0F3878 */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5990   },
5991
5992   /* PREFIX_VEX_0F3879 */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5997   },
5998
5999   /* PREFIX_VEX_0F388C */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6004   },
6005
6006   /* PREFIX_VEX_0F388E */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6011   },
6012
6013   /* PREFIX_VEX_0F3890 */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6018   },
6019
6020   /* PREFIX_VEX_0F3891 */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6025   },
6026
6027   /* PREFIX_VEX_0F3892 */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6032   },
6033
6034   /* PREFIX_VEX_0F3893 */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6039   },
6040
6041   /* PREFIX_VEX_0F3896 */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6046   },
6047
6048   /* PREFIX_VEX_0F3897 */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6053   },
6054
6055   /* PREFIX_VEX_0F3898 */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6060   },
6061
6062   /* PREFIX_VEX_0F3899 */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6067   },
6068
6069   /* PREFIX_VEX_0F389A */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6074   },
6075
6076   /* PREFIX_VEX_0F389B */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6081   },
6082
6083   /* PREFIX_VEX_0F389C */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6088   },
6089
6090   /* PREFIX_VEX_0F389D */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6095   },
6096
6097   /* PREFIX_VEX_0F389E */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6102   },
6103
6104   /* PREFIX_VEX_0F389F */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6109   },
6110
6111   /* PREFIX_VEX_0F38A6 */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6116     { Bad_Opcode },
6117   },
6118
6119   /* PREFIX_VEX_0F38A7 */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6124   },
6125
6126   /* PREFIX_VEX_0F38A8 */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6131   },
6132
6133   /* PREFIX_VEX_0F38A9 */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6138   },
6139
6140   /* PREFIX_VEX_0F38AA */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6145   },
6146
6147   /* PREFIX_VEX_0F38AB */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F38AC */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F38AD */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6166   },
6167
6168   /* PREFIX_VEX_0F38AE */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6173   },
6174
6175   /* PREFIX_VEX_0F38AF */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6180   },
6181
6182   /* PREFIX_VEX_0F38B6 */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6187   },
6188
6189   /* PREFIX_VEX_0F38B7 */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6194   },
6195
6196   /* PREFIX_VEX_0F38B8 */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6201   },
6202
6203   /* PREFIX_VEX_0F38B9 */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6208   },
6209
6210   /* PREFIX_VEX_0F38BA */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6215   },
6216
6217   /* PREFIX_VEX_0F38BB */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6222   },
6223
6224   /* PREFIX_VEX_0F38BC */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6229   },
6230
6231   /* PREFIX_VEX_0F38BD */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6236   },
6237
6238   /* PREFIX_VEX_0F38BE */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6243   },
6244
6245   /* PREFIX_VEX_0F38BF */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6250   },
6251
6252   /* PREFIX_VEX_0F38DB */
6253   {
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6257   },
6258
6259   /* PREFIX_VEX_0F38DC */
6260   {
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6264   },
6265
6266   /* PREFIX_VEX_0F38DD */
6267   {
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6271   },
6272
6273   /* PREFIX_VEX_0F38DE */
6274   {
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6278   },
6279
6280   /* PREFIX_VEX_0F38DF */
6281   {
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6285   },
6286
6287   /* PREFIX_VEX_0F38F2 */
6288   {
6289     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6290   },
6291
6292   /* PREFIX_VEX_0F38F3_REG_1 */
6293   {
6294     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6295   },
6296
6297   /* PREFIX_VEX_0F38F3_REG_2 */
6298   {
6299     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6300   },
6301
6302   /* PREFIX_VEX_0F38F3_REG_3 */
6303   {
6304     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6305   },
6306
6307   /* PREFIX_VEX_0F38F5 */
6308   {
6309     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6310     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6311     { Bad_Opcode },
6312     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6313   },
6314
6315   /* PREFIX_VEX_0F38F6 */
6316   {
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6321   },
6322
6323   /* PREFIX_VEX_0F38F7 */
6324   {
6325     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6326     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6327     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6328     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6329   },
6330
6331   /* PREFIX_VEX_0F3A00 */
6332   {
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6336   },
6337
6338   /* PREFIX_VEX_0F3A01 */
6339   {
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6343   },
6344
6345   /* PREFIX_VEX_0F3A02 */
6346   {
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6350   },
6351
6352   /* PREFIX_VEX_0F3A04 */
6353   {
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6357   },
6358
6359   /* PREFIX_VEX_0F3A05 */
6360   {
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6364   },
6365
6366   /* PREFIX_VEX_0F3A06 */
6367   {
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6371   },
6372
6373   /* PREFIX_VEX_0F3A08 */
6374   {
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6378   },
6379
6380   /* PREFIX_VEX_0F3A09 */
6381   {
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6385   },
6386
6387   /* PREFIX_VEX_0F3A0A */
6388   {
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6392   },
6393
6394   /* PREFIX_VEX_0F3A0B */
6395   {
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6399   },
6400
6401   /* PREFIX_VEX_0F3A0C */
6402   {
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6406   },
6407
6408   /* PREFIX_VEX_0F3A0D */
6409   {
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6413   },
6414
6415   /* PREFIX_VEX_0F3A0E */
6416   {
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6420   },
6421
6422   /* PREFIX_VEX_0F3A0F */
6423   {
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6427   },
6428
6429   /* PREFIX_VEX_0F3A14 */
6430   {
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6434   },
6435
6436   /* PREFIX_VEX_0F3A15 */
6437   {
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6441   },
6442
6443   /* PREFIX_VEX_0F3A16 */
6444   {
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6448   },
6449
6450   /* PREFIX_VEX_0F3A17 */
6451   {
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6455   },
6456
6457   /* PREFIX_VEX_0F3A18 */
6458   {
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6462   },
6463
6464   /* PREFIX_VEX_0F3A19 */
6465   {
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6469   },
6470
6471   /* PREFIX_VEX_0F3A1D */
6472   {
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6476   },
6477
6478   /* PREFIX_VEX_0F3A20 */
6479   {
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6483   },
6484
6485   /* PREFIX_VEX_0F3A21 */
6486   {
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6490   },
6491
6492   /* PREFIX_VEX_0F3A22 */
6493   {
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6497   },
6498
6499   /* PREFIX_VEX_0F3A30 */
6500   {
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6504   },
6505
6506   /* PREFIX_VEX_0F3A31 */
6507   {
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6511   },
6512
6513   /* PREFIX_VEX_0F3A32 */
6514   {
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6518   },
6519
6520   /* PREFIX_VEX_0F3A33 */
6521   {
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6525   },
6526
6527   /* PREFIX_VEX_0F3A38 */
6528   {
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6532   },
6533
6534   /* PREFIX_VEX_0F3A39 */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6539   },
6540
6541   /* PREFIX_VEX_0F3A40 */
6542   {
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6546   },
6547
6548   /* PREFIX_VEX_0F3A41 */
6549   {
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6553   },
6554
6555   /* PREFIX_VEX_0F3A42 */
6556   {
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6560   },
6561
6562   /* PREFIX_VEX_0F3A44 */
6563   {
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6567   },
6568
6569   /* PREFIX_VEX_0F3A46 */
6570   {
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6574   },
6575
6576   /* PREFIX_VEX_0F3A48 */
6577   {
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6581   },
6582
6583   /* PREFIX_VEX_0F3A49 */
6584   {
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6588   },
6589
6590   /* PREFIX_VEX_0F3A4A */
6591   {
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6595   },
6596
6597   /* PREFIX_VEX_0F3A4B */
6598   {
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6602   },
6603
6604   /* PREFIX_VEX_0F3A4C */
6605   {
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6609   },
6610
6611   /* PREFIX_VEX_0F3A5C */
6612   {
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6616   },
6617
6618   /* PREFIX_VEX_0F3A5D */
6619   {
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6623   },
6624
6625   /* PREFIX_VEX_0F3A5E */
6626   {
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6630   },
6631
6632   /* PREFIX_VEX_0F3A5F */
6633   {
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6637   },
6638
6639   /* PREFIX_VEX_0F3A60 */
6640   {
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6644     { Bad_Opcode },
6645   },
6646
6647   /* PREFIX_VEX_0F3A61 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6652   },
6653
6654   /* PREFIX_VEX_0F3A62 */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6659   },
6660
6661   /* PREFIX_VEX_0F3A63 */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6666   },
6667
6668   /* PREFIX_VEX_0F3A68 */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6673   },
6674
6675   /* PREFIX_VEX_0F3A69 */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6680   },
6681
6682   /* PREFIX_VEX_0F3A6A */
6683   {
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6687   },
6688
6689   /* PREFIX_VEX_0F3A6B */
6690   {
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6694   },
6695
6696   /* PREFIX_VEX_0F3A6C */
6697   {
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6701   },
6702
6703   /* PREFIX_VEX_0F3A6D */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6708   },
6709
6710   /* PREFIX_VEX_0F3A6E */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6715   },
6716
6717   /* PREFIX_VEX_0F3A6F */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6722   },
6723
6724   /* PREFIX_VEX_0F3A78 */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6729   },
6730
6731   /* PREFIX_VEX_0F3A79 */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6736   },
6737
6738   /* PREFIX_VEX_0F3A7A */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6743   },
6744
6745   /* PREFIX_VEX_0F3A7B */
6746   {
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6750   },
6751
6752   /* PREFIX_VEX_0F3A7C */
6753   {
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6757     { Bad_Opcode },
6758   },
6759
6760   /* PREFIX_VEX_0F3A7D */
6761   {
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6765   },
6766
6767   /* PREFIX_VEX_0F3A7E */
6768   {
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6772   },
6773
6774   /* PREFIX_VEX_0F3A7F */
6775   {
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6779   },
6780
6781   /* PREFIX_VEX_0F3ADF */
6782   {
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6786   },
6787
6788   /* PREFIX_VEX_0F3AF0 */
6789   {
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6794   },
6795
6796 #define NEED_PREFIX_TABLE
6797 #include "i386-dis-evex.h"
6798 #undef NEED_PREFIX_TABLE
6799 };
6800
6801 static const struct dis386 x86_64_table[][2] = {
6802   /* X86_64_06 */
6803   {
6804     { "pushP", { es }, 0 },
6805   },
6806
6807   /* X86_64_07 */
6808   {
6809     { "popP", { es }, 0 },
6810   },
6811
6812   /* X86_64_0D */
6813   {
6814     { "pushP", { cs }, 0 },
6815   },
6816
6817   /* X86_64_16 */
6818   {
6819     { "pushP", { ss }, 0 },
6820   },
6821
6822   /* X86_64_17 */
6823   {
6824     { "popP", { ss }, 0 },
6825   },
6826
6827   /* X86_64_1E */
6828   {
6829     { "pushP", { ds }, 0 },
6830   },
6831
6832   /* X86_64_1F */
6833   {
6834     { "popP", { ds }, 0 },
6835   },
6836
6837   /* X86_64_27 */
6838   {
6839     { "daa", { XX }, 0 },
6840   },
6841
6842   /* X86_64_2F */
6843   {
6844     { "das", { XX }, 0 },
6845   },
6846
6847   /* X86_64_37 */
6848   {
6849     { "aaa", { XX }, 0 },
6850   },
6851
6852   /* X86_64_3F */
6853   {
6854     { "aas", { XX }, 0 },
6855   },
6856
6857   /* X86_64_60 */
6858   {
6859     { "pushaP", { XX }, 0 },
6860   },
6861
6862   /* X86_64_61 */
6863   {
6864     { "popaP", { XX }, 0 },
6865   },
6866
6867   /* X86_64_62 */
6868   {
6869     { MOD_TABLE (MOD_62_32BIT) },
6870     { EVEX_TABLE (EVEX_0F) },
6871   },
6872
6873   /* X86_64_63 */
6874   {
6875     { "arpl", { Ew, Gw }, 0 },
6876     { "movs{lq|xd}", { Gv, Ed }, 0 },
6877   },
6878
6879   /* X86_64_6D */
6880   {
6881     { "ins{R|}", { Yzr, indirDX }, 0 },
6882     { "ins{G|}", { Yzr, indirDX }, 0 },
6883   },
6884
6885   /* X86_64_6F */
6886   {
6887     { "outs{R|}", { indirDXr, Xz }, 0 },
6888     { "outs{G|}", { indirDXr, Xz }, 0 },
6889   },
6890
6891   /* X86_64_82 */
6892   {
6893     /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode.  */
6894     { REG_TABLE (REG_80) },
6895   },
6896
6897   /* X86_64_9A */
6898   {
6899     { "Jcall{T|}", { Ap }, 0 },
6900   },
6901
6902   /* X86_64_C4 */
6903   {
6904     { MOD_TABLE (MOD_C4_32BIT) },
6905     { VEX_C4_TABLE (VEX_0F) },
6906   },
6907
6908   /* X86_64_C5 */
6909   {
6910     { MOD_TABLE (MOD_C5_32BIT) },
6911     { VEX_C5_TABLE (VEX_0F) },
6912   },
6913
6914   /* X86_64_CE */
6915   {
6916     { "into", { XX }, 0 },
6917   },
6918
6919   /* X86_64_D4 */
6920   {
6921     { "aam", { Ib }, 0 },
6922   },
6923
6924   /* X86_64_D5 */
6925   {
6926     { "aad", { Ib }, 0 },
6927   },
6928
6929   /* X86_64_E8 */
6930   {
6931     { "callP",          { Jv, BND }, 0 },
6932     { "call@",          { Jv, BND }, 0 }
6933   },
6934
6935   /* X86_64_E9 */
6936   {
6937     { "jmpP",           { Jv, BND }, 0 },
6938     { "jmp@",           { Jv, BND }, 0 }
6939   },
6940
6941   /* X86_64_EA */
6942   {
6943     { "Jjmp{T|}", { Ap }, 0 },
6944   },
6945
6946   /* X86_64_0F01_REG_0 */
6947   {
6948     { "sgdt{Q|IQ}", { M }, 0 },
6949     { "sgdt", { M }, 0 },
6950   },
6951
6952   /* X86_64_0F01_REG_1 */
6953   {
6954     { "sidt{Q|IQ}", { M }, 0 },
6955     { "sidt", { M }, 0 },
6956   },
6957
6958   /* X86_64_0F01_REG_2 */
6959   {
6960     { "lgdt{Q|Q}", { M }, 0 },
6961     { "lgdt", { M }, 0 },
6962   },
6963
6964   /* X86_64_0F01_REG_3 */
6965   {
6966     { "lidt{Q|Q}", { M }, 0 },
6967     { "lidt", { M }, 0 },
6968   },
6969 };
6970
6971 static const struct dis386 three_byte_table[][256] = {
6972
6973   /* THREE_BYTE_0F38 */
6974   {
6975     /* 00 */
6976     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6977     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6978     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6979     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6980     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6981     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6982     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6983     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6984     /* 08 */
6985     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6986     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6987     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6988     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     /* 10 */
6994     { PREFIX_TABLE (PREFIX_0F3810) },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { PREFIX_TABLE (PREFIX_0F3814) },
6999     { PREFIX_TABLE (PREFIX_0F3815) },
7000     { Bad_Opcode },
7001     { PREFIX_TABLE (PREFIX_0F3817) },
7002     /* 18 */
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7008     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7009     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7010     { Bad_Opcode },
7011     /* 20 */
7012     { PREFIX_TABLE (PREFIX_0F3820) },
7013     { PREFIX_TABLE (PREFIX_0F3821) },
7014     { PREFIX_TABLE (PREFIX_0F3822) },
7015     { PREFIX_TABLE (PREFIX_0F3823) },
7016     { PREFIX_TABLE (PREFIX_0F3824) },
7017     { PREFIX_TABLE (PREFIX_0F3825) },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     /* 28 */
7021     { PREFIX_TABLE (PREFIX_0F3828) },
7022     { PREFIX_TABLE (PREFIX_0F3829) },
7023     { PREFIX_TABLE (PREFIX_0F382A) },
7024     { PREFIX_TABLE (PREFIX_0F382B) },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     /* 30 */
7030     { PREFIX_TABLE (PREFIX_0F3830) },
7031     { PREFIX_TABLE (PREFIX_0F3831) },
7032     { PREFIX_TABLE (PREFIX_0F3832) },
7033     { PREFIX_TABLE (PREFIX_0F3833) },
7034     { PREFIX_TABLE (PREFIX_0F3834) },
7035     { PREFIX_TABLE (PREFIX_0F3835) },
7036     { Bad_Opcode },
7037     { PREFIX_TABLE (PREFIX_0F3837) },
7038     /* 38 */
7039     { PREFIX_TABLE (PREFIX_0F3838) },
7040     { PREFIX_TABLE (PREFIX_0F3839) },
7041     { PREFIX_TABLE (PREFIX_0F383A) },
7042     { PREFIX_TABLE (PREFIX_0F383B) },
7043     { PREFIX_TABLE (PREFIX_0F383C) },
7044     { PREFIX_TABLE (PREFIX_0F383D) },
7045     { PREFIX_TABLE (PREFIX_0F383E) },
7046     { PREFIX_TABLE (PREFIX_0F383F) },
7047     /* 40 */
7048     { PREFIX_TABLE (PREFIX_0F3840) },
7049     { PREFIX_TABLE (PREFIX_0F3841) },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     /* 48 */
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     /* 50 */
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     /* 58 */
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     /* 60 */
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     /* 68 */
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     /* 70 */
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     /* 78 */
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     /* 80 */
7120     { PREFIX_TABLE (PREFIX_0F3880) },
7121     { PREFIX_TABLE (PREFIX_0F3881) },
7122     { PREFIX_TABLE (PREFIX_0F3882) },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     /* 88 */
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     /* 90 */
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     /* 98 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* a0 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* a8 */
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* b0 */
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     /* b8 */
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     /* c0 */
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* c8 */
7201     { PREFIX_TABLE (PREFIX_0F38C8) },
7202     { PREFIX_TABLE (PREFIX_0F38C9) },
7203     { PREFIX_TABLE (PREFIX_0F38CA) },
7204     { PREFIX_TABLE (PREFIX_0F38CB) },
7205     { PREFIX_TABLE (PREFIX_0F38CC) },
7206     { PREFIX_TABLE (PREFIX_0F38CD) },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     /* d0 */
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     /* d8 */
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { PREFIX_TABLE (PREFIX_0F38DB) },
7223     { PREFIX_TABLE (PREFIX_0F38DC) },
7224     { PREFIX_TABLE (PREFIX_0F38DD) },
7225     { PREFIX_TABLE (PREFIX_0F38DE) },
7226     { PREFIX_TABLE (PREFIX_0F38DF) },
7227     /* e0 */
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     /* e8 */
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     /* f0 */
7246     { PREFIX_TABLE (PREFIX_0F38F0) },
7247     { PREFIX_TABLE (PREFIX_0F38F1) },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { PREFIX_TABLE (PREFIX_0F38F6) },
7253     { Bad_Opcode },
7254     /* f8 */
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263   },
7264   /* THREE_BYTE_0F3A */
7265   {
7266     /* 00 */
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     /* 08 */
7276     { PREFIX_TABLE (PREFIX_0F3A08) },
7277     { PREFIX_TABLE (PREFIX_0F3A09) },
7278     { PREFIX_TABLE (PREFIX_0F3A0A) },
7279     { PREFIX_TABLE (PREFIX_0F3A0B) },
7280     { PREFIX_TABLE (PREFIX_0F3A0C) },
7281     { PREFIX_TABLE (PREFIX_0F3A0D) },
7282     { PREFIX_TABLE (PREFIX_0F3A0E) },
7283     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7284     /* 10 */
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { PREFIX_TABLE (PREFIX_0F3A14) },
7290     { PREFIX_TABLE (PREFIX_0F3A15) },
7291     { PREFIX_TABLE (PREFIX_0F3A16) },
7292     { PREFIX_TABLE (PREFIX_0F3A17) },
7293     /* 18 */
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     /* 20 */
7303     { PREFIX_TABLE (PREFIX_0F3A20) },
7304     { PREFIX_TABLE (PREFIX_0F3A21) },
7305     { PREFIX_TABLE (PREFIX_0F3A22) },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     /* 28 */
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     /* 30 */
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     /* 38 */
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     /* 40 */
7339     { PREFIX_TABLE (PREFIX_0F3A40) },
7340     { PREFIX_TABLE (PREFIX_0F3A41) },
7341     { PREFIX_TABLE (PREFIX_0F3A42) },
7342     { Bad_Opcode },
7343     { PREFIX_TABLE (PREFIX_0F3A44) },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     /* 48 */
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     /* 50 */
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     /* 58 */
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     /* 60 */
7375     { PREFIX_TABLE (PREFIX_0F3A60) },
7376     { PREFIX_TABLE (PREFIX_0F3A61) },
7377     { PREFIX_TABLE (PREFIX_0F3A62) },
7378     { PREFIX_TABLE (PREFIX_0F3A63) },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     /* 68 */
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     /* 70 */
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     /* 78 */
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     /* 80 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     /* 88 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     /* 90 */
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     /* 98 */
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     /* a0 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* a8 */
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     /* b0 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     /* b8 */
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     /* c0 */
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     /* c8 */
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { PREFIX_TABLE (PREFIX_0F3ACC) },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     /* d0 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     /* d8 */
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { PREFIX_TABLE (PREFIX_0F3ADF) },
7518     /* e0 */
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     /* e8 */
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     /* f0 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     /* f8 */
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554   },
7555
7556   /* THREE_BYTE_0F7A */
7557   {
7558     /* 00 */
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     /* 08 */
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     /* 10 */
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     /* 18 */
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     /* 20 */
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     /* 28 */
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     /* 30 */
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     /* 38 */
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     /* 40 */
7631     { Bad_Opcode },
7632     { "phaddbw",        { XM, EXq }, PREFIX_OPCODE },
7633     { "phaddbd",        { XM, EXq }, PREFIX_OPCODE },
7634     { "phaddbq",        { XM, EXq }, PREFIX_OPCODE },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { "phaddwd",        { XM, EXq }, PREFIX_OPCODE },
7638     { "phaddwq",        { XM, EXq }, PREFIX_OPCODE },
7639     /* 48 */
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { "phadddq",        { XM, EXq }, PREFIX_OPCODE },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     /* 50 */
7649     { Bad_Opcode },
7650     { "phaddubw",       { XM, EXq }, PREFIX_OPCODE },
7651     { "phaddubd",       { XM, EXq }, PREFIX_OPCODE },
7652     { "phaddubq",       { XM, EXq }, PREFIX_OPCODE },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { "phadduwd",       { XM, EXq }, PREFIX_OPCODE },
7656     { "phadduwq",       { XM, EXq }, PREFIX_OPCODE },
7657     /* 58 */
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { "phaddudq",       { XM, EXq }, PREFIX_OPCODE },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     /* 60 */
7667     { Bad_Opcode },
7668     { "phsubbw",        { XM, EXq }, PREFIX_OPCODE },
7669     { "phsubbd",        { XM, EXq }, PREFIX_OPCODE },
7670     { "phsubbq",        { XM, EXq }, PREFIX_OPCODE },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     /* 68 */
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     /* 70 */
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     /* 78 */
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     /* 80 */
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     /* 88 */
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     /* 90 */
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     /* 98 */
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     /* a0 */
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     /* a8 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     /* b0 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     /* b8 */
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* c0 */
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     /* c8 */
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     /* d0 */
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* d8 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     /* e0 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* e8 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     /* f0 */
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* f8 */
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846   },
7847 };
7848
7849 static const struct dis386 xop_table[][256] = {
7850   /* XOP_08 */
7851   {
7852     /* 00 */
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     /* 08 */
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     /* 10 */
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     /* 18 */
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     /* 20 */
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     /* 28 */
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     /* 30 */
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     /* 38 */
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     /* 40 */
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     /* 48 */
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     /* 50 */
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     /* 58 */
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     /* 60 */
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     /* 68 */
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     /* 70 */
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     /* 78 */
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     /* 80 */
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8003     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8004     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8005     /* 88 */
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8013     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8014     /* 90 */
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8021     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8022     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8023     /* 98 */
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8031     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8032     /* a0 */
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8036     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8040     { Bad_Opcode },
8041     /* a8 */
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     /* b0 */
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8058     { Bad_Opcode },
8059     /* b8 */
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     /* c0 */
8069     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
8070     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
8071     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
8072     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     /* c8 */
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8083     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8084     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8085     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8086     /* d0 */
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     /* d8 */
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     /* e0 */
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     /* e8 */
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8119     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8120     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8121     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8122     /* f0 */
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     /* f8 */
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140   },
8141   /* XOP_09 */
8142   {
8143     /* 00 */
8144     { Bad_Opcode },
8145     { REG_TABLE (REG_XOP_TBM_01) },
8146     { REG_TABLE (REG_XOP_TBM_02) },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     /* 08 */
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     /* 10 */
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { REG_TABLE (REG_XOP_LWPCB) },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     /* 18 */
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     /* 20 */
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     /* 28 */
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     /* 30 */
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     /* 38 */
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     /* 40 */
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     /* 48 */
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     /* 50 */
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     /* 58 */
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     /* 60 */
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     /* 68 */
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     /* 70 */
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     /* 78 */
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     /* 80 */
8288     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8289     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8290     { "vfrczss",        { XM, EXd }, 0 },
8291     { "vfrczsd",        { XM, EXq }, 0 },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     /* 88 */
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     /* 90 */
8306     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8307     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8308     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8309     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8310     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8311     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8312     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8313     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8314     /* 98 */
8315     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8316     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8317     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8318     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     /* a0 */
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     /* a8 */
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     /* b0 */
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     /* b8 */
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     /* c0 */
8360     { Bad_Opcode },
8361     { "vphaddbw",       { XM, EXxmm }, 0 },
8362     { "vphaddbd",       { XM, EXxmm }, 0 },
8363     { "vphaddbq",       { XM, EXxmm }, 0 },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { "vphaddwd",       { XM, EXxmm }, 0 },
8367     { "vphaddwq",       { XM, EXxmm }, 0 },
8368     /* c8 */
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { "vphadddq",       { XM, EXxmm }, 0 },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     /* d0 */
8378     { Bad_Opcode },
8379     { "vphaddubw",      { XM, EXxmm }, 0 },
8380     { "vphaddubd",      { XM, EXxmm }, 0 },
8381     { "vphaddubq",      { XM, EXxmm }, 0 },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { "vphadduwd",      { XM, EXxmm }, 0 },
8385     { "vphadduwq",      { XM, EXxmm }, 0 },
8386     /* d8 */
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { "vphaddudq",      { XM, EXxmm }, 0 },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     /* e0 */
8396     { Bad_Opcode },
8397     { "vphsubbw",       { XM, EXxmm }, 0 },
8398     { "vphsubwd",       { XM, EXxmm }, 0 },
8399     { "vphsubdq",       { XM, EXxmm }, 0 },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     /* e8 */
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     /* f0 */
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     /* f8 */
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431   },
8432   /* XOP_0A */
8433   {
8434     /* 00 */
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     /* 08 */
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     /* 10 */
8453     { "bextr",  { Gv, Ev, Iq }, 0 },
8454     { Bad_Opcode },
8455     { REG_TABLE (REG_XOP_LWP) },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     /* 18 */
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     /* 20 */
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     /* 28 */
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     /* 30 */
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     /* 38 */
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     /* 40 */
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     /* 48 */
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     /* 50 */
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     /* 58 */
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     /* 60 */
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     /* 68 */
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     /* 70 */
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     /* 78 */
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     /* 80 */
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     /* 88 */
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     /* 90 */
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     /* 98 */
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     /* a0 */
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     /* a8 */
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     /* b0 */
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     /* b8 */
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     /* c0 */
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     /* c8 */
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     /* d0 */
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     /* d8 */
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     /* e0 */
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     /* e8 */
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     /* f0 */
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     /* f8 */
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722   },
8723 };
8724
8725 static const struct dis386 vex_table[][256] = {
8726   /* VEX_0F */
8727   {
8728     /* 00 */
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     /* 08 */
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     /* 10 */
8747     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8750     { MOD_TABLE (MOD_VEX_0F13) },
8751     { VEX_W_TABLE (VEX_W_0F14) },
8752     { VEX_W_TABLE (VEX_W_0F15) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8754     { MOD_TABLE (MOD_VEX_0F17) },
8755     /* 18 */
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     /* 20 */
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     /* 28 */
8774     { VEX_W_TABLE (VEX_W_0F28) },
8775     { VEX_W_TABLE (VEX_W_0F29) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8777     { MOD_TABLE (MOD_VEX_0F2B) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8782     /* 30 */
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     /* 38 */
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     /* 40 */
8801     { Bad_Opcode },
8802     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8804     { Bad_Opcode },
8805     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8809     /* 48 */
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     /* 50 */
8819     { MOD_TABLE (MOD_VEX_0F50) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8823     { "vandpX",         { XM, Vex, EXx }, 0 },
8824     { "vandnpX",        { XM, Vex, EXx }, 0 },
8825     { "vorpX",          { XM, Vex, EXx }, 0 },
8826     { "vxorpX",         { XM, Vex, EXx }, 0 },
8827     /* 58 */
8828     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8832     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8835     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8836     /* 60 */
8837     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8838     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8839     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8840     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8841     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8842     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8843     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8844     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8845     /* 68 */
8846     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8848     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8849     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8850     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8851     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8852     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8853     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8854     /* 70 */
8855     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8856     { REG_TABLE (REG_VEX_0F71) },
8857     { REG_TABLE (REG_VEX_0F72) },
8858     { REG_TABLE (REG_VEX_0F73) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8861     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8862     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8863     /* 78 */
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8869     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8871     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8872     /* 80 */
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     /* 88 */
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     /* 90 */
8891     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     /* 98 */
8900     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     /* a0 */
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     /* a8 */
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { REG_TABLE (REG_VEX_0FAE) },
8925     { Bad_Opcode },
8926     /* b0 */
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     /* b8 */
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     /* c0 */
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8948     { Bad_Opcode },
8949     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8950     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8951     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8952     { Bad_Opcode },
8953     /* c8 */
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     /* d0 */
8963     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8964     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8965     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8966     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8967     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8968     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8969     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8970     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8971     /* d8 */
8972     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8973     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8974     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8975     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8976     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8977     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8978     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8979     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8980     /* e0 */
8981     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8982     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8983     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8984     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8985     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8986     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8987     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8988     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8989     /* e8 */
8990     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8991     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8992     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8993     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8994     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8995     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8996     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8997     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8998     /* f0 */
8999     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
9000     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
9001     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
9002     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
9003     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
9004     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
9005     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
9006     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
9007     /* f8 */
9008     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
9009     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
9010     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
9011     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
9012     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
9013     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
9014     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
9015     { Bad_Opcode },
9016   },
9017   /* VEX_0F38 */
9018   {
9019     /* 00 */
9020     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
9028     /* 08 */
9029     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
9037     /* 10 */
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
9046     /* 18 */
9047     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
9050     { Bad_Opcode },
9051     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
9054     { Bad_Opcode },
9055     /* 20 */
9056     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     /* 28 */
9065     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
9073     /* 30 */
9074     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
9080     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9081     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9082     /* 38 */
9083     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9091     /* 40 */
9092     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9100     /* 48 */
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     /* 50 */
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     /* 58 */
9119     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     /* 60 */
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     /* 68 */
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     /* 70 */
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     /* 78 */
9155     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     /* 80 */
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     /* 88 */
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9178     { Bad_Opcode },
9179     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9180     { Bad_Opcode },
9181     /* 90 */
9182     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9183     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9190     /* 98 */
9191     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9193     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9194     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9195     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9197     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9198     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9199     /* a0 */
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9207     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9208     /* a8 */
9209     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9210     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9211     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9212     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9213     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9214     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9215     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9216     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9217     /* b0 */
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9225     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9226     /* b8 */
9227     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9228     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9229     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9230     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9231     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9232     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9233     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9234     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9235     /* c0 */
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     /* c8 */
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     /* d0 */
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     /* d8 */
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9267     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9268     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9269     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9270     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9271     /* e0 */
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     /* e8 */
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     /* f0 */
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9293     { REG_TABLE (REG_VEX_0F38F3) },
9294     { Bad_Opcode },
9295     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9296     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9297     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9298     /* f8 */
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307   },
9308   /* VEX_0F3A */
9309   {
9310     /* 00 */
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9314     { Bad_Opcode },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9317     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9318     { Bad_Opcode },
9319     /* 08 */
9320     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9321     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9322     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9323     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9324     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9325     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9326     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9327     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9328     /* 10 */
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9334     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9335     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9336     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9337     /* 18 */
9338     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9339     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     /* 20 */
9347     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9348     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9349     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     /* 28 */
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     /* 30 */
9365     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9366     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9367     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9368     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     /* 38 */
9374     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9375     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     /* 40 */
9383     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9384     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9385     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9386     { Bad_Opcode },
9387     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9388     { Bad_Opcode },
9389     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9390     { Bad_Opcode },
9391     /* 48 */
9392     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9393     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9394     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9395     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9396     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     /* 50 */
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     /* 58 */
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9415     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9416     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9417     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9418     /* 60 */
9419     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9420     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9421     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9422     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     /* 68 */
9428     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9429     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9430     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9431     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9432     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9433     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9434     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9435     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9436     /* 70 */
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     /* 78 */
9446     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9447     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9448     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9449     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9450     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9451     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9452     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9453     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9454     /* 80 */
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     /* 88 */
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     { Bad_Opcode },
9472     /* 90 */
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     { Bad_Opcode },
9477     { Bad_Opcode },
9478     { Bad_Opcode },
9479     { Bad_Opcode },
9480     { Bad_Opcode },
9481     /* 98 */
9482     { Bad_Opcode },
9483     { Bad_Opcode },
9484     { Bad_Opcode },
9485     { Bad_Opcode },
9486     { Bad_Opcode },
9487     { Bad_Opcode },
9488     { Bad_Opcode },
9489     { Bad_Opcode },
9490     /* a0 */
9491     { Bad_Opcode },
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     { Bad_Opcode },
9495     { Bad_Opcode },
9496     { Bad_Opcode },
9497     { Bad_Opcode },
9498     { Bad_Opcode },
9499     /* a8 */
9500     { Bad_Opcode },
9501     { Bad_Opcode },
9502     { Bad_Opcode },
9503     { Bad_Opcode },
9504     { Bad_Opcode },
9505     { Bad_Opcode },
9506     { Bad_Opcode },
9507     { Bad_Opcode },
9508     /* b0 */
9509     { Bad_Opcode },
9510     { Bad_Opcode },
9511     { Bad_Opcode },
9512     { Bad_Opcode },
9513     { Bad_Opcode },
9514     { Bad_Opcode },
9515     { Bad_Opcode },
9516     { Bad_Opcode },
9517     /* b8 */
9518     { Bad_Opcode },
9519     { Bad_Opcode },
9520     { Bad_Opcode },
9521     { Bad_Opcode },
9522     { Bad_Opcode },
9523     { Bad_Opcode },
9524     { Bad_Opcode },
9525     { Bad_Opcode },
9526     /* c0 */
9527     { Bad_Opcode },
9528     { Bad_Opcode },
9529     { Bad_Opcode },
9530     { Bad_Opcode },
9531     { Bad_Opcode },
9532     { Bad_Opcode },
9533     { Bad_Opcode },
9534     { Bad_Opcode },
9535     /* c8 */
9536     { Bad_Opcode },
9537     { Bad_Opcode },
9538     { Bad_Opcode },
9539     { Bad_Opcode },
9540     { Bad_Opcode },
9541     { Bad_Opcode },
9542     { Bad_Opcode },
9543     { Bad_Opcode },
9544     /* d0 */
9545     { Bad_Opcode },
9546     { Bad_Opcode },
9547     { Bad_Opcode },
9548     { Bad_Opcode },
9549     { Bad_Opcode },
9550     { Bad_Opcode },
9551     { Bad_Opcode },
9552     { Bad_Opcode },
9553     /* d8 */
9554     { Bad_Opcode },
9555     { Bad_Opcode },
9556     { Bad_Opcode },
9557     { Bad_Opcode },
9558     { Bad_Opcode },
9559     { Bad_Opcode },
9560     { Bad_Opcode },
9561     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9562     /* e0 */
9563     { Bad_Opcode },
9564     { Bad_Opcode },
9565     { Bad_Opcode },
9566     { Bad_Opcode },
9567     { Bad_Opcode },
9568     { Bad_Opcode },
9569     { Bad_Opcode },
9570     { Bad_Opcode },
9571     /* e8 */
9572     { Bad_Opcode },
9573     { Bad_Opcode },
9574     { Bad_Opcode },
9575     { Bad_Opcode },
9576     { Bad_Opcode },
9577     { Bad_Opcode },
9578     { Bad_Opcode },
9579     { Bad_Opcode },
9580     /* f0 */
9581     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9582     { Bad_Opcode },
9583     { Bad_Opcode },
9584     { Bad_Opcode },
9585     { Bad_Opcode },
9586     { Bad_Opcode },
9587     { Bad_Opcode },
9588     { Bad_Opcode },
9589     /* f8 */
9590     { Bad_Opcode },
9591     { Bad_Opcode },
9592     { Bad_Opcode },
9593     { Bad_Opcode },
9594     { Bad_Opcode },
9595     { Bad_Opcode },
9596     { Bad_Opcode },
9597     { Bad_Opcode },
9598   },
9599 };
9600
9601 #define NEED_OPCODE_TABLE
9602 #include "i386-dis-evex.h"
9603 #undef NEED_OPCODE_TABLE
9604 static const struct dis386 vex_len_table[][2] = {
9605   /* VEX_LEN_0F10_P_1 */
9606   {
9607     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9608     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9609   },
9610
9611   /* VEX_LEN_0F10_P_3 */
9612   {
9613     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9614     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9615   },
9616
9617   /* VEX_LEN_0F11_P_1 */
9618   {
9619     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9620     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9621   },
9622
9623   /* VEX_LEN_0F11_P_3 */
9624   {
9625     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9626     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9627   },
9628
9629   /* VEX_LEN_0F12_P_0_M_0 */
9630   {
9631     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9632   },
9633
9634   /* VEX_LEN_0F12_P_0_M_1 */
9635   {
9636     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9637   },
9638
9639   /* VEX_LEN_0F12_P_2 */
9640   {
9641     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9642   },
9643
9644   /* VEX_LEN_0F13_M_0 */
9645   {
9646     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9647   },
9648
9649   /* VEX_LEN_0F16_P_0_M_0 */
9650   {
9651     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9652   },
9653
9654   /* VEX_LEN_0F16_P_0_M_1 */
9655   {
9656     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9657   },
9658
9659   /* VEX_LEN_0F16_P_2 */
9660   {
9661     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9662   },
9663
9664   /* VEX_LEN_0F17_M_0 */
9665   {
9666     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9667   },
9668
9669   /* VEX_LEN_0F2A_P_1 */
9670   {
9671     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9672     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9673   },
9674
9675   /* VEX_LEN_0F2A_P_3 */
9676   {
9677     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9678     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9679   },
9680
9681   /* VEX_LEN_0F2C_P_1 */
9682   {
9683     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9684     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9685   },
9686
9687   /* VEX_LEN_0F2C_P_3 */
9688   {
9689     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9690     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9691   },
9692
9693   /* VEX_LEN_0F2D_P_1 */
9694   {
9695     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9696     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9697   },
9698
9699   /* VEX_LEN_0F2D_P_3 */
9700   {
9701     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9702     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9703   },
9704
9705   /* VEX_LEN_0F2E_P_0 */
9706   {
9707     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9708     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9709   },
9710
9711   /* VEX_LEN_0F2E_P_2 */
9712   {
9713     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9714     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9715   },
9716
9717   /* VEX_LEN_0F2F_P_0 */
9718   {
9719     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9720     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9721   },
9722
9723   /* VEX_LEN_0F2F_P_2 */
9724   {
9725     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9726     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9727   },
9728
9729   /* VEX_LEN_0F41_P_0 */
9730   {
9731     { Bad_Opcode },
9732     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9733   },
9734   /* VEX_LEN_0F41_P_2 */
9735   {
9736     { Bad_Opcode },
9737     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9738   },
9739   /* VEX_LEN_0F42_P_0 */
9740   {
9741     { Bad_Opcode },
9742     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9743   },
9744   /* VEX_LEN_0F42_P_2 */
9745   {
9746     { Bad_Opcode },
9747     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9748   },
9749   /* VEX_LEN_0F44_P_0 */
9750   {
9751     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9752   },
9753   /* VEX_LEN_0F44_P_2 */
9754   {
9755     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9756   },
9757   /* VEX_LEN_0F45_P_0 */
9758   {
9759     { Bad_Opcode },
9760     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9761   },
9762   /* VEX_LEN_0F45_P_2 */
9763   {
9764     { Bad_Opcode },
9765     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9766   },
9767   /* VEX_LEN_0F46_P_0 */
9768   {
9769     { Bad_Opcode },
9770     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9771   },
9772   /* VEX_LEN_0F46_P_2 */
9773   {
9774     { Bad_Opcode },
9775     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9776   },
9777   /* VEX_LEN_0F47_P_0 */
9778   {
9779     { Bad_Opcode },
9780     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9781   },
9782   /* VEX_LEN_0F47_P_2 */
9783   {
9784     { Bad_Opcode },
9785     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9786   },
9787   /* VEX_LEN_0F4A_P_0 */
9788   {
9789     { Bad_Opcode },
9790     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9791   },
9792   /* VEX_LEN_0F4A_P_2 */
9793   {
9794     { Bad_Opcode },
9795     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9796   },
9797   /* VEX_LEN_0F4B_P_0 */
9798   {
9799     { Bad_Opcode },
9800     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9801   },
9802   /* VEX_LEN_0F4B_P_2 */
9803   {
9804     { Bad_Opcode },
9805     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9806   },
9807
9808   /* VEX_LEN_0F51_P_1 */
9809   {
9810     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9811     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9812   },
9813
9814   /* VEX_LEN_0F51_P_3 */
9815   {
9816     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9817     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9818   },
9819
9820   /* VEX_LEN_0F52_P_1 */
9821   {
9822     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9823     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9824   },
9825
9826   /* VEX_LEN_0F53_P_1 */
9827   {
9828     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9829     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9830   },
9831
9832   /* VEX_LEN_0F58_P_1 */
9833   {
9834     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9835     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9836   },
9837
9838   /* VEX_LEN_0F58_P_3 */
9839   {
9840     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9841     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9842   },
9843
9844   /* VEX_LEN_0F59_P_1 */
9845   {
9846     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9847     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9848   },
9849
9850   /* VEX_LEN_0F59_P_3 */
9851   {
9852     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9853     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9854   },
9855
9856   /* VEX_LEN_0F5A_P_1 */
9857   {
9858     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9859     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9860   },
9861
9862   /* VEX_LEN_0F5A_P_3 */
9863   {
9864     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9865     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9866   },
9867
9868   /* VEX_LEN_0F5C_P_1 */
9869   {
9870     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9871     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9872   },
9873
9874   /* VEX_LEN_0F5C_P_3 */
9875   {
9876     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9877     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9878   },
9879
9880   /* VEX_LEN_0F5D_P_1 */
9881   {
9882     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9883     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9884   },
9885
9886   /* VEX_LEN_0F5D_P_3 */
9887   {
9888     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9889     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9890   },
9891
9892   /* VEX_LEN_0F5E_P_1 */
9893   {
9894     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9895     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9896   },
9897
9898   /* VEX_LEN_0F5E_P_3 */
9899   {
9900     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9901     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9902   },
9903
9904   /* VEX_LEN_0F5F_P_1 */
9905   {
9906     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9907     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9908   },
9909
9910   /* VEX_LEN_0F5F_P_3 */
9911   {
9912     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9913     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9914   },
9915
9916   /* VEX_LEN_0F6E_P_2 */
9917   {
9918     { "vmovK",          { XMScalar, Edq }, 0 },
9919     { "vmovK",          { XMScalar, Edq }, 0 },
9920   },
9921
9922   /* VEX_LEN_0F7E_P_1 */
9923   {
9924     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9925     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9926   },
9927
9928   /* VEX_LEN_0F7E_P_2 */
9929   {
9930     { "vmovK",          { Edq, XMScalar }, 0 },
9931     { "vmovK",          { Edq, XMScalar }, 0 },
9932   },
9933
9934   /* VEX_LEN_0F90_P_0 */
9935   {
9936     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9937   },
9938
9939   /* VEX_LEN_0F90_P_2 */
9940   {
9941     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9942   },
9943
9944   /* VEX_LEN_0F91_P_0 */
9945   {
9946     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9947   },
9948
9949   /* VEX_LEN_0F91_P_2 */
9950   {
9951     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9952   },
9953
9954   /* VEX_LEN_0F92_P_0 */
9955   {
9956     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9957   },
9958
9959   /* VEX_LEN_0F92_P_2 */
9960   {
9961     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9962   },
9963
9964   /* VEX_LEN_0F92_P_3 */
9965   {
9966     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9967   },
9968
9969   /* VEX_LEN_0F93_P_0 */
9970   {
9971     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9972   },
9973
9974   /* VEX_LEN_0F93_P_2 */
9975   {
9976     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9977   },
9978
9979   /* VEX_LEN_0F93_P_3 */
9980   {
9981     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9982   },
9983
9984   /* VEX_LEN_0F98_P_0 */
9985   {
9986     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9987   },
9988
9989   /* VEX_LEN_0F98_P_2 */
9990   {
9991     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9992   },
9993
9994   /* VEX_LEN_0F99_P_0 */
9995   {
9996     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9997   },
9998
9999   /* VEX_LEN_0F99_P_2 */
10000   {
10001     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
10002   },
10003
10004   /* VEX_LEN_0FAE_R_2_M_0 */
10005   {
10006     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
10007   },
10008
10009   /* VEX_LEN_0FAE_R_3_M_0 */
10010   {
10011     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
10012   },
10013
10014   /* VEX_LEN_0FC2_P_1 */
10015   {
10016     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
10017     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
10018   },
10019
10020   /* VEX_LEN_0FC2_P_3 */
10021   {
10022     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10023     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10024   },
10025
10026   /* VEX_LEN_0FC4_P_2 */
10027   {
10028     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
10029   },
10030
10031   /* VEX_LEN_0FC5_P_2 */
10032   {
10033     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
10034   },
10035
10036   /* VEX_LEN_0FD6_P_2 */
10037   {
10038     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10039     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10040   },
10041
10042   /* VEX_LEN_0FF7_P_2 */
10043   {
10044     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
10045   },
10046
10047   /* VEX_LEN_0F3816_P_2 */
10048   {
10049     { Bad_Opcode },
10050     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
10051   },
10052
10053   /* VEX_LEN_0F3819_P_2 */
10054   {
10055     { Bad_Opcode },
10056     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
10057   },
10058
10059   /* VEX_LEN_0F381A_P_2_M_0 */
10060   {
10061     { Bad_Opcode },
10062     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
10063   },
10064
10065   /* VEX_LEN_0F3836_P_2 */
10066   {
10067     { Bad_Opcode },
10068     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
10069   },
10070
10071   /* VEX_LEN_0F3841_P_2 */
10072   {
10073     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
10074   },
10075
10076   /* VEX_LEN_0F385A_P_2_M_0 */
10077   {
10078     { Bad_Opcode },
10079     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
10080   },
10081
10082   /* VEX_LEN_0F38DB_P_2 */
10083   {
10084     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10085   },
10086
10087   /* VEX_LEN_0F38DC_P_2 */
10088   {
10089     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
10090   },
10091
10092   /* VEX_LEN_0F38DD_P_2 */
10093   {
10094     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
10095   },
10096
10097   /* VEX_LEN_0F38DE_P_2 */
10098   {
10099     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
10100   },
10101
10102   /* VEX_LEN_0F38DF_P_2 */
10103   {
10104     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10105   },
10106
10107   /* VEX_LEN_0F38F2_P_0 */
10108   {
10109     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10110   },
10111
10112   /* VEX_LEN_0F38F3_R_1_P_0 */
10113   {
10114     { "blsrS",          { VexGdq, Edq }, 0 },
10115   },
10116
10117   /* VEX_LEN_0F38F3_R_2_P_0 */
10118   {
10119     { "blsmskS",        { VexGdq, Edq }, 0 },
10120   },
10121
10122   /* VEX_LEN_0F38F3_R_3_P_0 */
10123   {
10124     { "blsiS",          { VexGdq, Edq }, 0 },
10125   },
10126
10127   /* VEX_LEN_0F38F5_P_0 */
10128   {
10129     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10130   },
10131
10132   /* VEX_LEN_0F38F5_P_1 */
10133   {
10134     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10135   },
10136
10137   /* VEX_LEN_0F38F5_P_3 */
10138   {
10139     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10140   },
10141
10142   /* VEX_LEN_0F38F6_P_3 */
10143   {
10144     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10145   },
10146
10147   /* VEX_LEN_0F38F7_P_0 */
10148   {
10149     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10150   },
10151
10152   /* VEX_LEN_0F38F7_P_1 */
10153   {
10154     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10155   },
10156
10157   /* VEX_LEN_0F38F7_P_2 */
10158   {
10159     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10160   },
10161
10162   /* VEX_LEN_0F38F7_P_3 */
10163   {
10164     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10165   },
10166
10167   /* VEX_LEN_0F3A00_P_2 */
10168   {
10169     { Bad_Opcode },
10170     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10171   },
10172
10173   /* VEX_LEN_0F3A01_P_2 */
10174   {
10175     { Bad_Opcode },
10176     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10177   },
10178
10179   /* VEX_LEN_0F3A06_P_2 */
10180   {
10181     { Bad_Opcode },
10182     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10183   },
10184
10185   /* VEX_LEN_0F3A0A_P_2 */
10186   {
10187     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10188     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10189   },
10190
10191   /* VEX_LEN_0F3A0B_P_2 */
10192   {
10193     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10194     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10195   },
10196
10197   /* VEX_LEN_0F3A14_P_2 */
10198   {
10199     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10200   },
10201
10202   /* VEX_LEN_0F3A15_P_2 */
10203   {
10204     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10205   },
10206
10207   /* VEX_LEN_0F3A16_P_2  */
10208   {
10209     { "vpextrK",        { Edq, XM, Ib }, 0 },
10210   },
10211
10212   /* VEX_LEN_0F3A17_P_2 */
10213   {
10214     { "vextractps",     { Edqd, XM, Ib }, 0 },
10215   },
10216
10217   /* VEX_LEN_0F3A18_P_2 */
10218   {
10219     { Bad_Opcode },
10220     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10221   },
10222
10223   /* VEX_LEN_0F3A19_P_2 */
10224   {
10225     { Bad_Opcode },
10226     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10227   },
10228
10229   /* VEX_LEN_0F3A20_P_2 */
10230   {
10231     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10232   },
10233
10234   /* VEX_LEN_0F3A21_P_2 */
10235   {
10236     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10237   },
10238
10239   /* VEX_LEN_0F3A22_P_2 */
10240   {
10241     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10242   },
10243
10244   /* VEX_LEN_0F3A30_P_2 */
10245   {
10246     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10247   },
10248
10249   /* VEX_LEN_0F3A31_P_2 */
10250   {
10251     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10252   },
10253
10254   /* VEX_LEN_0F3A32_P_2 */
10255   {
10256     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10257   },
10258
10259   /* VEX_LEN_0F3A33_P_2 */
10260   {
10261     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10262   },
10263
10264   /* VEX_LEN_0F3A38_P_2 */
10265   {
10266     { Bad_Opcode },
10267     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10268   },
10269
10270   /* VEX_LEN_0F3A39_P_2 */
10271   {
10272     { Bad_Opcode },
10273     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10274   },
10275
10276   /* VEX_LEN_0F3A41_P_2 */
10277   {
10278     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10279   },
10280
10281   /* VEX_LEN_0F3A44_P_2 */
10282   {
10283     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10284   },
10285
10286   /* VEX_LEN_0F3A46_P_2 */
10287   {
10288     { Bad_Opcode },
10289     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10290   },
10291
10292   /* VEX_LEN_0F3A60_P_2 */
10293   {
10294     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10295   },
10296
10297   /* VEX_LEN_0F3A61_P_2 */
10298   {
10299     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10300   },
10301
10302   /* VEX_LEN_0F3A62_P_2 */
10303   {
10304     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10305   },
10306
10307   /* VEX_LEN_0F3A63_P_2 */
10308   {
10309     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10310   },
10311
10312   /* VEX_LEN_0F3A6A_P_2 */
10313   {
10314     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10315   },
10316
10317   /* VEX_LEN_0F3A6B_P_2 */
10318   {
10319     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10320   },
10321
10322   /* VEX_LEN_0F3A6E_P_2 */
10323   {
10324     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10325   },
10326
10327   /* VEX_LEN_0F3A6F_P_2 */
10328   {
10329     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10330   },
10331
10332   /* VEX_LEN_0F3A7A_P_2 */
10333   {
10334     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10335   },
10336
10337   /* VEX_LEN_0F3A7B_P_2 */
10338   {
10339     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10340   },
10341
10342   /* VEX_LEN_0F3A7E_P_2 */
10343   {
10344     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10345   },
10346
10347   /* VEX_LEN_0F3A7F_P_2 */
10348   {
10349     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10350   },
10351
10352   /* VEX_LEN_0F3ADF_P_2 */
10353   {
10354     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10355   },
10356
10357   /* VEX_LEN_0F3AF0_P_3 */
10358   {
10359     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10360   },
10361
10362   /* VEX_LEN_0FXOP_08_CC */
10363   {
10364      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10365   },
10366
10367   /* VEX_LEN_0FXOP_08_CD */
10368   {
10369      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10370   },
10371
10372   /* VEX_LEN_0FXOP_08_CE */
10373   {
10374      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10375   },
10376
10377   /* VEX_LEN_0FXOP_08_CF */
10378   {
10379      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10380   },
10381
10382   /* VEX_LEN_0FXOP_08_EC */
10383   {
10384      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10385   },
10386
10387   /* VEX_LEN_0FXOP_08_ED */
10388   {
10389      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10390   },
10391
10392   /* VEX_LEN_0FXOP_08_EE */
10393   {
10394      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10395   },
10396
10397   /* VEX_LEN_0FXOP_08_EF */
10398   {
10399      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10400   },
10401
10402   /* VEX_LEN_0FXOP_09_80 */
10403   {
10404     { "vfrczps",        { XM, EXxmm }, 0 },
10405     { "vfrczps",        { XM, EXymmq }, 0 },
10406   },
10407
10408   /* VEX_LEN_0FXOP_09_81 */
10409   {
10410     { "vfrczpd",        { XM, EXxmm }, 0 },
10411     { "vfrczpd",        { XM, EXymmq }, 0 },
10412   },
10413 };
10414
10415 static const struct dis386 vex_w_table[][2] = {
10416   {
10417     /* VEX_W_0F10_P_0 */
10418     { "vmovups",        { XM, EXx }, 0 },
10419   },
10420   {
10421     /* VEX_W_0F10_P_1 */
10422     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10423   },
10424   {
10425     /* VEX_W_0F10_P_2 */
10426     { "vmovupd",        { XM, EXx }, 0 },
10427   },
10428   {
10429     /* VEX_W_0F10_P_3 */
10430     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10431   },
10432   {
10433     /* VEX_W_0F11_P_0 */
10434     { "vmovups",        { EXxS, XM }, 0 },
10435   },
10436   {
10437     /* VEX_W_0F11_P_1 */
10438     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10439   },
10440   {
10441     /* VEX_W_0F11_P_2 */
10442     { "vmovupd",        { EXxS, XM }, 0 },
10443   },
10444   {
10445     /* VEX_W_0F11_P_3 */
10446     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10447   },
10448   {
10449     /* VEX_W_0F12_P_0_M_0 */
10450     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10451   },
10452   {
10453     /* VEX_W_0F12_P_0_M_1 */
10454     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10455   },
10456   {
10457     /* VEX_W_0F12_P_1 */
10458     { "vmovsldup",      { XM, EXx }, 0 },
10459   },
10460   {
10461     /* VEX_W_0F12_P_2 */
10462     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10463   },
10464   {
10465     /* VEX_W_0F12_P_3 */
10466     { "vmovddup",       { XM, EXymmq }, 0 },
10467   },
10468   {
10469     /* VEX_W_0F13_M_0 */
10470     { "vmovlpX",        { EXq, XM }, 0 },
10471   },
10472   {
10473     /* VEX_W_0F14 */
10474     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10475   },
10476   {
10477     /* VEX_W_0F15 */
10478     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10479   },
10480   {
10481     /* VEX_W_0F16_P_0_M_0 */
10482     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10483   },
10484   {
10485     /* VEX_W_0F16_P_0_M_1 */
10486     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10487   },
10488   {
10489     /* VEX_W_0F16_P_1 */
10490     { "vmovshdup",      { XM, EXx }, 0 },
10491   },
10492   {
10493     /* VEX_W_0F16_P_2 */
10494     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10495   },
10496   {
10497     /* VEX_W_0F17_M_0 */
10498     { "vmovhpX",        { EXq, XM }, 0 },
10499   },
10500   {
10501     /* VEX_W_0F28 */
10502     { "vmovapX",        { XM, EXx }, 0 },
10503   },
10504   {
10505     /* VEX_W_0F29 */
10506     { "vmovapX",        { EXxS, XM }, 0 },
10507   },
10508   {
10509     /* VEX_W_0F2B_M_0 */
10510     { "vmovntpX",       { Mx, XM }, 0 },
10511   },
10512   {
10513     /* VEX_W_0F2E_P_0 */
10514     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10515   },
10516   {
10517     /* VEX_W_0F2E_P_2 */
10518     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10519   },
10520   {
10521     /* VEX_W_0F2F_P_0 */
10522     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10523   },
10524   {
10525     /* VEX_W_0F2F_P_2 */
10526     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10527   },
10528   {
10529     /* VEX_W_0F41_P_0_LEN_1 */
10530     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10531     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10532   },
10533   {
10534     /* VEX_W_0F41_P_2_LEN_1 */
10535     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10536     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10537   },
10538   {
10539     /* VEX_W_0F42_P_0_LEN_1 */
10540     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10541     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10542   },
10543   {
10544     /* VEX_W_0F42_P_2_LEN_1 */
10545     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10546     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10547   },
10548   {
10549     /* VEX_W_0F44_P_0_LEN_0 */
10550     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10551     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10552   },
10553   {
10554     /* VEX_W_0F44_P_2_LEN_0 */
10555     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10556     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10557   },
10558   {
10559     /* VEX_W_0F45_P_0_LEN_1 */
10560     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10561     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10562   },
10563   {
10564     /* VEX_W_0F45_P_2_LEN_1 */
10565     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10566     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10567   },
10568   {
10569     /* VEX_W_0F46_P_0_LEN_1 */
10570     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10571     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10572   },
10573   {
10574     /* VEX_W_0F46_P_2_LEN_1 */
10575     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10576     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10577   },
10578   {
10579     /* VEX_W_0F47_P_0_LEN_1 */
10580     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10581     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10582   },
10583   {
10584     /* VEX_W_0F47_P_2_LEN_1 */
10585     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10586     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10587   },
10588   {
10589     /* VEX_W_0F4A_P_0_LEN_1 */
10590     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10591     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10592   },
10593   {
10594     /* VEX_W_0F4A_P_2_LEN_1 */
10595     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10596     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10597   },
10598   {
10599     /* VEX_W_0F4B_P_0_LEN_1 */
10600     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10601     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10602   },
10603   {
10604     /* VEX_W_0F4B_P_2_LEN_1 */
10605     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10606   },
10607   {
10608     /* VEX_W_0F50_M_0 */
10609     { "vmovmskpX",      { Gdq, XS }, 0 },
10610   },
10611   {
10612     /* VEX_W_0F51_P_0 */
10613     { "vsqrtps",        { XM, EXx }, 0 },
10614   },
10615   {
10616     /* VEX_W_0F51_P_1 */
10617     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10618   },
10619   {
10620     /* VEX_W_0F51_P_2  */
10621     { "vsqrtpd",        { XM, EXx }, 0 },
10622   },
10623   {
10624     /* VEX_W_0F51_P_3 */
10625     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10626   },
10627   {
10628     /* VEX_W_0F52_P_0 */
10629     { "vrsqrtps",       { XM, EXx }, 0 },
10630   },
10631   {
10632     /* VEX_W_0F52_P_1 */
10633     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10634   },
10635   {
10636     /* VEX_W_0F53_P_0  */
10637     { "vrcpps",         { XM, EXx }, 0 },
10638   },
10639   {
10640     /* VEX_W_0F53_P_1  */
10641     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10642   },
10643   {
10644     /* VEX_W_0F58_P_0  */
10645     { "vaddps",         { XM, Vex, EXx }, 0 },
10646   },
10647   {
10648     /* VEX_W_0F58_P_1  */
10649     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10650   },
10651   {
10652     /* VEX_W_0F58_P_2  */
10653     { "vaddpd",         { XM, Vex, EXx }, 0 },
10654   },
10655   {
10656     /* VEX_W_0F58_P_3  */
10657     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10658   },
10659   {
10660     /* VEX_W_0F59_P_0  */
10661     { "vmulps",         { XM, Vex, EXx }, 0 },
10662   },
10663   {
10664     /* VEX_W_0F59_P_1  */
10665     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10666   },
10667   {
10668     /* VEX_W_0F59_P_2  */
10669     { "vmulpd",         { XM, Vex, EXx }, 0 },
10670   },
10671   {
10672     /* VEX_W_0F59_P_3  */
10673     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10674   },
10675   {
10676     /* VEX_W_0F5A_P_0  */
10677     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10678   },
10679   {
10680     /* VEX_W_0F5A_P_1  */
10681     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10682   },
10683   {
10684     /* VEX_W_0F5A_P_3  */
10685     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10686   },
10687   {
10688     /* VEX_W_0F5B_P_0  */
10689     { "vcvtdq2ps",      { XM, EXx }, 0 },
10690   },
10691   {
10692     /* VEX_W_0F5B_P_1  */
10693     { "vcvttps2dq",     { XM, EXx }, 0 },
10694   },
10695   {
10696     /* VEX_W_0F5B_P_2  */
10697     { "vcvtps2dq",      { XM, EXx }, 0 },
10698   },
10699   {
10700     /* VEX_W_0F5C_P_0  */
10701     { "vsubps",         { XM, Vex, EXx }, 0 },
10702   },
10703   {
10704     /* VEX_W_0F5C_P_1  */
10705     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10706   },
10707   {
10708     /* VEX_W_0F5C_P_2  */
10709     { "vsubpd",         { XM, Vex, EXx }, 0 },
10710   },
10711   {
10712     /* VEX_W_0F5C_P_3  */
10713     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10714   },
10715   {
10716     /* VEX_W_0F5D_P_0  */
10717     { "vminps",         { XM, Vex, EXx }, 0 },
10718   },
10719   {
10720     /* VEX_W_0F5D_P_1  */
10721     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10722   },
10723   {
10724     /* VEX_W_0F5D_P_2  */
10725     { "vminpd",         { XM, Vex, EXx }, 0 },
10726   },
10727   {
10728     /* VEX_W_0F5D_P_3  */
10729     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10730   },
10731   {
10732     /* VEX_W_0F5E_P_0  */
10733     { "vdivps",         { XM, Vex, EXx }, 0 },
10734   },
10735   {
10736     /* VEX_W_0F5E_P_1  */
10737     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10738   },
10739   {
10740     /* VEX_W_0F5E_P_2  */
10741     { "vdivpd",         { XM, Vex, EXx }, 0 },
10742   },
10743   {
10744     /* VEX_W_0F5E_P_3  */
10745     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10746   },
10747   {
10748     /* VEX_W_0F5F_P_0  */
10749     { "vmaxps",         { XM, Vex, EXx }, 0 },
10750   },
10751   {
10752     /* VEX_W_0F5F_P_1  */
10753     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10754   },
10755   {
10756     /* VEX_W_0F5F_P_2  */
10757     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10758   },
10759   {
10760     /* VEX_W_0F5F_P_3  */
10761     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10762   },
10763   {
10764     /* VEX_W_0F60_P_2  */
10765     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10766   },
10767   {
10768     /* VEX_W_0F61_P_2  */
10769     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10770   },
10771   {
10772     /* VEX_W_0F62_P_2  */
10773     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10774   },
10775   {
10776     /* VEX_W_0F63_P_2  */
10777     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10778   },
10779   {
10780     /* VEX_W_0F64_P_2  */
10781     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10782   },
10783   {
10784     /* VEX_W_0F65_P_2  */
10785     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10786   },
10787   {
10788     /* VEX_W_0F66_P_2  */
10789     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10790   },
10791   {
10792     /* VEX_W_0F67_P_2  */
10793     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10794   },
10795   {
10796     /* VEX_W_0F68_P_2  */
10797     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10798   },
10799   {
10800     /* VEX_W_0F69_P_2  */
10801     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10802   },
10803   {
10804     /* VEX_W_0F6A_P_2  */
10805     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10806   },
10807   {
10808     /* VEX_W_0F6B_P_2  */
10809     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10810   },
10811   {
10812     /* VEX_W_0F6C_P_2  */
10813     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10814   },
10815   {
10816     /* VEX_W_0F6D_P_2  */
10817     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10818   },
10819   {
10820     /* VEX_W_0F6F_P_1  */
10821     { "vmovdqu",        { XM, EXx }, 0 },
10822   },
10823   {
10824     /* VEX_W_0F6F_P_2  */
10825     { "vmovdqa",        { XM, EXx }, 0 },
10826   },
10827   {
10828     /* VEX_W_0F70_P_1 */
10829     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10830   },
10831   {
10832     /* VEX_W_0F70_P_2 */
10833     { "vpshufd",        { XM, EXx, Ib }, 0 },
10834   },
10835   {
10836     /* VEX_W_0F70_P_3 */
10837     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10838   },
10839   {
10840     /* VEX_W_0F71_R_2_P_2  */
10841     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10842   },
10843   {
10844     /* VEX_W_0F71_R_4_P_2  */
10845     { "vpsraw",         { Vex, XS, Ib }, 0 },
10846   },
10847   {
10848     /* VEX_W_0F71_R_6_P_2  */
10849     { "vpsllw",         { Vex, XS, Ib }, 0 },
10850   },
10851   {
10852     /* VEX_W_0F72_R_2_P_2  */
10853     { "vpsrld",         { Vex, XS, Ib }, 0 },
10854   },
10855   {
10856     /* VEX_W_0F72_R_4_P_2  */
10857     { "vpsrad",         { Vex, XS, Ib }, 0 },
10858   },
10859   {
10860     /* VEX_W_0F72_R_6_P_2  */
10861     { "vpslld",         { Vex, XS, Ib }, 0 },
10862   },
10863   {
10864     /* VEX_W_0F73_R_2_P_2  */
10865     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10866   },
10867   {
10868     /* VEX_W_0F73_R_3_P_2  */
10869     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10870   },
10871   {
10872     /* VEX_W_0F73_R_6_P_2  */
10873     { "vpsllq",         { Vex, XS, Ib }, 0 },
10874   },
10875   {
10876     /* VEX_W_0F73_R_7_P_2  */
10877     { "vpslldq",        { Vex, XS, Ib }, 0 },
10878   },
10879   {
10880     /* VEX_W_0F74_P_2 */
10881     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10882   },
10883   {
10884     /* VEX_W_0F75_P_2 */
10885     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10886   },
10887   {
10888     /* VEX_W_0F76_P_2 */
10889     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10890   },
10891   {
10892     /* VEX_W_0F77_P_0 */
10893     { "",               { VZERO }, 0 },
10894   },
10895   {
10896     /* VEX_W_0F7C_P_2 */
10897     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10898   },
10899   {
10900     /* VEX_W_0F7C_P_3 */
10901     { "vhaddps",        { XM, Vex, EXx }, 0 },
10902   },
10903   {
10904     /* VEX_W_0F7D_P_2 */
10905     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10906   },
10907   {
10908     /* VEX_W_0F7D_P_3 */
10909     { "vhsubps",        { XM, Vex, EXx }, 0 },
10910   },
10911   {
10912     /* VEX_W_0F7E_P_1 */
10913     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10914   },
10915   {
10916     /* VEX_W_0F7F_P_1 */
10917     { "vmovdqu",        { EXxS, XM }, 0 },
10918   },
10919   {
10920     /* VEX_W_0F7F_P_2 */
10921     { "vmovdqa",        { EXxS, XM }, 0 },
10922   },
10923   {
10924     /* VEX_W_0F90_P_0_LEN_0 */
10925     { "kmovw",          { MaskG, MaskE }, 0 },
10926     { "kmovq",          { MaskG, MaskE }, 0 },
10927   },
10928   {
10929     /* VEX_W_0F90_P_2_LEN_0 */
10930     { "kmovb",          { MaskG, MaskBDE }, 0 },
10931     { "kmovd",          { MaskG, MaskBDE }, 0 },
10932   },
10933   {
10934     /* VEX_W_0F91_P_0_LEN_0 */
10935     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10936     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10937   },
10938   {
10939     /* VEX_W_0F91_P_2_LEN_0 */
10940     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10941     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10942   },
10943   {
10944     /* VEX_W_0F92_P_0_LEN_0 */
10945     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10946   },
10947   {
10948     /* VEX_W_0F92_P_2_LEN_0 */
10949     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10950   },
10951   {
10952     /* VEX_W_0F92_P_3_LEN_0 */
10953     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10954     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10955   },
10956   {
10957     /* VEX_W_0F93_P_0_LEN_0 */
10958     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10959   },
10960   {
10961     /* VEX_W_0F93_P_2_LEN_0 */
10962     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10963   },
10964   {
10965     /* VEX_W_0F93_P_3_LEN_0 */
10966     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10967     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10968   },
10969   {
10970     /* VEX_W_0F98_P_0_LEN_0 */
10971     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10972     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10973   },
10974   {
10975     /* VEX_W_0F98_P_2_LEN_0 */
10976     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10977     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10978   },
10979   {
10980     /* VEX_W_0F99_P_0_LEN_0 */
10981     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10982     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10983   },
10984   {
10985     /* VEX_W_0F99_P_2_LEN_0 */
10986     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10987     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10988   },
10989   {
10990     /* VEX_W_0FAE_R_2_M_0 */
10991     { "vldmxcsr",       { Md }, 0 },
10992   },
10993   {
10994     /* VEX_W_0FAE_R_3_M_0 */
10995     { "vstmxcsr",       { Md }, 0 },
10996   },
10997   {
10998     /* VEX_W_0FC2_P_0 */
10999     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
11000   },
11001   {
11002     /* VEX_W_0FC2_P_1 */
11003     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
11004   },
11005   {
11006     /* VEX_W_0FC2_P_2 */
11007     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
11008   },
11009   {
11010     /* VEX_W_0FC2_P_3 */
11011     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
11012   },
11013   {
11014     /* VEX_W_0FC4_P_2 */
11015     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
11016   },
11017   {
11018     /* VEX_W_0FC5_P_2 */
11019     { "vpextrw",        { Gdq, XS, Ib }, 0 },
11020   },
11021   {
11022     /* VEX_W_0FD0_P_2 */
11023     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
11024   },
11025   {
11026     /* VEX_W_0FD0_P_3 */
11027     { "vaddsubps",      { XM, Vex, EXx }, 0 },
11028   },
11029   {
11030     /* VEX_W_0FD1_P_2 */
11031     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
11032   },
11033   {
11034     /* VEX_W_0FD2_P_2 */
11035     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
11036   },
11037   {
11038     /* VEX_W_0FD3_P_2 */
11039     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
11040   },
11041   {
11042     /* VEX_W_0FD4_P_2 */
11043     { "vpaddq",         { XM, Vex, EXx }, 0 },
11044   },
11045   {
11046     /* VEX_W_0FD5_P_2 */
11047     { "vpmullw",        { XM, Vex, EXx }, 0 },
11048   },
11049   {
11050     /* VEX_W_0FD6_P_2 */
11051     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
11052   },
11053   {
11054     /* VEX_W_0FD7_P_2_M_1 */
11055     { "vpmovmskb",      { Gdq, XS }, 0 },
11056   },
11057   {
11058     /* VEX_W_0FD8_P_2 */
11059     { "vpsubusb",       { XM, Vex, EXx }, 0 },
11060   },
11061   {
11062     /* VEX_W_0FD9_P_2 */
11063     { "vpsubusw",       { XM, Vex, EXx }, 0 },
11064   },
11065   {
11066     /* VEX_W_0FDA_P_2 */
11067     { "vpminub",        { XM, Vex, EXx }, 0 },
11068   },
11069   {
11070     /* VEX_W_0FDB_P_2 */
11071     { "vpand",          { XM, Vex, EXx }, 0 },
11072   },
11073   {
11074     /* VEX_W_0FDC_P_2 */
11075     { "vpaddusb",       { XM, Vex, EXx }, 0 },
11076   },
11077   {
11078     /* VEX_W_0FDD_P_2 */
11079     { "vpaddusw",       { XM, Vex, EXx }, 0 },
11080   },
11081   {
11082     /* VEX_W_0FDE_P_2 */
11083     { "vpmaxub",        { XM, Vex, EXx }, 0 },
11084   },
11085   {
11086     /* VEX_W_0FDF_P_2 */
11087     { "vpandn",         { XM, Vex, EXx }, 0 },
11088   },
11089   {
11090     /* VEX_W_0FE0_P_2  */
11091     { "vpavgb",         { XM, Vex, EXx }, 0 },
11092   },
11093   {
11094     /* VEX_W_0FE1_P_2  */
11095     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
11096   },
11097   {
11098     /* VEX_W_0FE2_P_2  */
11099     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
11100   },
11101   {
11102     /* VEX_W_0FE3_P_2  */
11103     { "vpavgw",         { XM, Vex, EXx }, 0 },
11104   },
11105   {
11106     /* VEX_W_0FE4_P_2  */
11107     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11108   },
11109   {
11110     /* VEX_W_0FE5_P_2  */
11111     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11112   },
11113   {
11114     /* VEX_W_0FE6_P_1  */
11115     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11116   },
11117   {
11118     /* VEX_W_0FE6_P_2  */
11119     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11120   },
11121   {
11122     /* VEX_W_0FE6_P_3  */
11123     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11124   },
11125   {
11126     /* VEX_W_0FE7_P_2_M_0 */
11127     { "vmovntdq",       { Mx, XM }, 0 },
11128   },
11129   {
11130     /* VEX_W_0FE8_P_2  */
11131     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11132   },
11133   {
11134     /* VEX_W_0FE9_P_2  */
11135     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11136   },
11137   {
11138     /* VEX_W_0FEA_P_2  */
11139     { "vpminsw",        { XM, Vex, EXx }, 0 },
11140   },
11141   {
11142     /* VEX_W_0FEB_P_2  */
11143     { "vpor",           { XM, Vex, EXx }, 0 },
11144   },
11145   {
11146     /* VEX_W_0FEC_P_2  */
11147     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11148   },
11149   {
11150     /* VEX_W_0FED_P_2  */
11151     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11152   },
11153   {
11154     /* VEX_W_0FEE_P_2  */
11155     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11156   },
11157   {
11158     /* VEX_W_0FEF_P_2  */
11159     { "vpxor",          { XM, Vex, EXx }, 0 },
11160   },
11161   {
11162     /* VEX_W_0FF0_P_3_M_0 */
11163     { "vlddqu",         { XM, M }, 0 },
11164   },
11165   {
11166     /* VEX_W_0FF1_P_2 */
11167     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11168   },
11169   {
11170     /* VEX_W_0FF2_P_2 */
11171     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11172   },
11173   {
11174     /* VEX_W_0FF3_P_2 */
11175     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11176   },
11177   {
11178     /* VEX_W_0FF4_P_2 */
11179     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11180   },
11181   {
11182     /* VEX_W_0FF5_P_2 */
11183     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11184   },
11185   {
11186     /* VEX_W_0FF6_P_2 */
11187     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11188   },
11189   {
11190     /* VEX_W_0FF7_P_2 */
11191     { "vmaskmovdqu",    { XM, XS }, 0 },
11192   },
11193   {
11194     /* VEX_W_0FF8_P_2 */
11195     { "vpsubb",         { XM, Vex, EXx }, 0 },
11196   },
11197   {
11198     /* VEX_W_0FF9_P_2 */
11199     { "vpsubw",         { XM, Vex, EXx }, 0 },
11200   },
11201   {
11202     /* VEX_W_0FFA_P_2 */
11203     { "vpsubd",         { XM, Vex, EXx }, 0 },
11204   },
11205   {
11206     /* VEX_W_0FFB_P_2 */
11207     { "vpsubq",         { XM, Vex, EXx }, 0 },
11208   },
11209   {
11210     /* VEX_W_0FFC_P_2 */
11211     { "vpaddb",         { XM, Vex, EXx }, 0 },
11212   },
11213   {
11214     /* VEX_W_0FFD_P_2 */
11215     { "vpaddw",         { XM, Vex, EXx }, 0 },
11216   },
11217   {
11218     /* VEX_W_0FFE_P_2 */
11219     { "vpaddd",         { XM, Vex, EXx }, 0 },
11220   },
11221   {
11222     /* VEX_W_0F3800_P_2  */
11223     { "vpshufb",        { XM, Vex, EXx }, 0 },
11224   },
11225   {
11226     /* VEX_W_0F3801_P_2  */
11227     { "vphaddw",        { XM, Vex, EXx }, 0 },
11228   },
11229   {
11230     /* VEX_W_0F3802_P_2  */
11231     { "vphaddd",        { XM, Vex, EXx }, 0 },
11232   },
11233   {
11234     /* VEX_W_0F3803_P_2  */
11235     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11236   },
11237   {
11238     /* VEX_W_0F3804_P_2  */
11239     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11240   },
11241   {
11242     /* VEX_W_0F3805_P_2  */
11243     { "vphsubw",        { XM, Vex, EXx }, 0 },
11244   },
11245   {
11246     /* VEX_W_0F3806_P_2  */
11247     { "vphsubd",        { XM, Vex, EXx }, 0 },
11248   },
11249   {
11250     /* VEX_W_0F3807_P_2  */
11251     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11252   },
11253   {
11254     /* VEX_W_0F3808_P_2  */
11255     { "vpsignb",        { XM, Vex, EXx }, 0 },
11256   },
11257   {
11258     /* VEX_W_0F3809_P_2  */
11259     { "vpsignw",        { XM, Vex, EXx }, 0 },
11260   },
11261   {
11262     /* VEX_W_0F380A_P_2  */
11263     { "vpsignd",        { XM, Vex, EXx }, 0 },
11264   },
11265   {
11266     /* VEX_W_0F380B_P_2  */
11267     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11268   },
11269   {
11270     /* VEX_W_0F380C_P_2  */
11271     { "vpermilps",      { XM, Vex, EXx }, 0 },
11272   },
11273   {
11274     /* VEX_W_0F380D_P_2  */
11275     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11276   },
11277   {
11278     /* VEX_W_0F380E_P_2  */
11279     { "vtestps",        { XM, EXx }, 0 },
11280   },
11281   {
11282     /* VEX_W_0F380F_P_2  */
11283     { "vtestpd",        { XM, EXx }, 0 },
11284   },
11285   {
11286     /* VEX_W_0F3816_P_2  */
11287     { "vpermps",        { XM, Vex, EXx }, 0 },
11288   },
11289   {
11290     /* VEX_W_0F3817_P_2 */
11291     { "vptest",         { XM, EXx }, 0 },
11292   },
11293   {
11294     /* VEX_W_0F3818_P_2 */
11295     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11296   },
11297   {
11298     /* VEX_W_0F3819_P_2 */
11299     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11300   },
11301   {
11302     /* VEX_W_0F381A_P_2_M_0 */
11303     { "vbroadcastf128", { XM, Mxmm }, 0 },
11304   },
11305   {
11306     /* VEX_W_0F381C_P_2 */
11307     { "vpabsb",         { XM, EXx }, 0 },
11308   },
11309   {
11310     /* VEX_W_0F381D_P_2 */
11311     { "vpabsw",         { XM, EXx }, 0 },
11312   },
11313   {
11314     /* VEX_W_0F381E_P_2 */
11315     { "vpabsd",         { XM, EXx }, 0 },
11316   },
11317   {
11318     /* VEX_W_0F3820_P_2 */
11319     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11320   },
11321   {
11322     /* VEX_W_0F3821_P_2 */
11323     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11324   },
11325   {
11326     /* VEX_W_0F3822_P_2 */
11327     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11328   },
11329   {
11330     /* VEX_W_0F3823_P_2 */
11331     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11332   },
11333   {
11334     /* VEX_W_0F3824_P_2 */
11335     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11336   },
11337   {
11338     /* VEX_W_0F3825_P_2 */
11339     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11340   },
11341   {
11342     /* VEX_W_0F3828_P_2 */
11343     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11344   },
11345   {
11346     /* VEX_W_0F3829_P_2 */
11347     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11348   },
11349   {
11350     /* VEX_W_0F382A_P_2_M_0 */
11351     { "vmovntdqa",      { XM, Mx }, 0 },
11352   },
11353   {
11354     /* VEX_W_0F382B_P_2 */
11355     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11356   },
11357   {
11358     /* VEX_W_0F382C_P_2_M_0 */
11359     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11360   },
11361   {
11362     /* VEX_W_0F382D_P_2_M_0 */
11363     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11364   },
11365   {
11366     /* VEX_W_0F382E_P_2_M_0 */
11367     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11368   },
11369   {
11370     /* VEX_W_0F382F_P_2_M_0 */
11371     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11372   },
11373   {
11374     /* VEX_W_0F3830_P_2 */
11375     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11376   },
11377   {
11378     /* VEX_W_0F3831_P_2 */
11379     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11380   },
11381   {
11382     /* VEX_W_0F3832_P_2 */
11383     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11384   },
11385   {
11386     /* VEX_W_0F3833_P_2 */
11387     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11388   },
11389   {
11390     /* VEX_W_0F3834_P_2 */
11391     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11392   },
11393   {
11394     /* VEX_W_0F3835_P_2 */
11395     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11396   },
11397   {
11398     /* VEX_W_0F3836_P_2  */
11399     { "vpermd",         { XM, Vex, EXx }, 0 },
11400   },
11401   {
11402     /* VEX_W_0F3837_P_2 */
11403     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11404   },
11405   {
11406     /* VEX_W_0F3838_P_2 */
11407     { "vpminsb",        { XM, Vex, EXx }, 0 },
11408   },
11409   {
11410     /* VEX_W_0F3839_P_2 */
11411     { "vpminsd",        { XM, Vex, EXx }, 0 },
11412   },
11413   {
11414     /* VEX_W_0F383A_P_2 */
11415     { "vpminuw",        { XM, Vex, EXx }, 0 },
11416   },
11417   {
11418     /* VEX_W_0F383B_P_2 */
11419     { "vpminud",        { XM, Vex, EXx }, 0 },
11420   },
11421   {
11422     /* VEX_W_0F383C_P_2 */
11423     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11424   },
11425   {
11426     /* VEX_W_0F383D_P_2 */
11427     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11428   },
11429   {
11430     /* VEX_W_0F383E_P_2 */
11431     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11432   },
11433   {
11434     /* VEX_W_0F383F_P_2 */
11435     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11436   },
11437   {
11438     /* VEX_W_0F3840_P_2 */
11439     { "vpmulld",        { XM, Vex, EXx }, 0 },
11440   },
11441   {
11442     /* VEX_W_0F3841_P_2 */
11443     { "vphminposuw",    { XM, EXx }, 0 },
11444   },
11445   {
11446     /* VEX_W_0F3846_P_2 */
11447     { "vpsravd",        { XM, Vex, EXx }, 0 },
11448   },
11449   {
11450     /* VEX_W_0F3858_P_2 */
11451     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11452   },
11453   {
11454     /* VEX_W_0F3859_P_2 */
11455     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11456   },
11457   {
11458     /* VEX_W_0F385A_P_2_M_0 */
11459     { "vbroadcasti128", { XM, Mxmm }, 0 },
11460   },
11461   {
11462     /* VEX_W_0F3878_P_2 */
11463     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11464   },
11465   {
11466     /* VEX_W_0F3879_P_2 */
11467     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11468   },
11469   {
11470     /* VEX_W_0F38DB_P_2 */
11471     { "vaesimc",        { XM, EXx }, 0 },
11472   },
11473   {
11474     /* VEX_W_0F38DC_P_2 */
11475     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11476   },
11477   {
11478     /* VEX_W_0F38DD_P_2 */
11479     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11480   },
11481   {
11482     /* VEX_W_0F38DE_P_2 */
11483     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11484   },
11485   {
11486     /* VEX_W_0F38DF_P_2 */
11487     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11488   },
11489   {
11490     /* VEX_W_0F3A00_P_2 */
11491     { Bad_Opcode },
11492     { "vpermq",         { XM, EXx, Ib }, 0 },
11493   },
11494   {
11495     /* VEX_W_0F3A01_P_2 */
11496     { Bad_Opcode },
11497     { "vpermpd",        { XM, EXx, Ib }, 0 },
11498   },
11499   {
11500     /* VEX_W_0F3A02_P_2 */
11501     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11502   },
11503   {
11504     /* VEX_W_0F3A04_P_2 */
11505     { "vpermilps",      { XM, EXx, Ib }, 0 },
11506   },
11507   {
11508     /* VEX_W_0F3A05_P_2 */
11509     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11510   },
11511   {
11512     /* VEX_W_0F3A06_P_2 */
11513     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11514   },
11515   {
11516     /* VEX_W_0F3A08_P_2 */
11517     { "vroundps",       { XM, EXx, Ib }, 0 },
11518   },
11519   {
11520     /* VEX_W_0F3A09_P_2 */
11521     { "vroundpd",       { XM, EXx, Ib }, 0 },
11522   },
11523   {
11524     /* VEX_W_0F3A0A_P_2 */
11525     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11526   },
11527   {
11528     /* VEX_W_0F3A0B_P_2 */
11529     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11530   },
11531   {
11532     /* VEX_W_0F3A0C_P_2 */
11533     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11534   },
11535   {
11536     /* VEX_W_0F3A0D_P_2 */
11537     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11538   },
11539   {
11540     /* VEX_W_0F3A0E_P_2 */
11541     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11542   },
11543   {
11544     /* VEX_W_0F3A0F_P_2 */
11545     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11546   },
11547   {
11548     /* VEX_W_0F3A14_P_2 */
11549     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11550   },
11551   {
11552     /* VEX_W_0F3A15_P_2 */
11553     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11554   },
11555   {
11556     /* VEX_W_0F3A18_P_2 */
11557     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11558   },
11559   {
11560     /* VEX_W_0F3A19_P_2 */
11561     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11562   },
11563   {
11564     /* VEX_W_0F3A20_P_2 */
11565     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11566   },
11567   {
11568     /* VEX_W_0F3A21_P_2 */
11569     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11570   },
11571   {
11572     /* VEX_W_0F3A30_P_2_LEN_0 */
11573     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11574     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11575   },
11576   {
11577     /* VEX_W_0F3A31_P_2_LEN_0 */
11578     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11579     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11580   },
11581   {
11582     /* VEX_W_0F3A32_P_2_LEN_0 */
11583     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11584     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11585   },
11586   {
11587     /* VEX_W_0F3A33_P_2_LEN_0 */
11588     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11589     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11590   },
11591   {
11592     /* VEX_W_0F3A38_P_2 */
11593     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11594   },
11595   {
11596     /* VEX_W_0F3A39_P_2 */
11597     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11598   },
11599   {
11600     /* VEX_W_0F3A40_P_2 */
11601     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11602   },
11603   {
11604     /* VEX_W_0F3A41_P_2 */
11605     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11606   },
11607   {
11608     /* VEX_W_0F3A42_P_2 */
11609     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11610   },
11611   {
11612     /* VEX_W_0F3A44_P_2 */
11613     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11614   },
11615   {
11616     /* VEX_W_0F3A46_P_2 */
11617     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11618   },
11619   {
11620     /* VEX_W_0F3A48_P_2 */
11621     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11622     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11623   },
11624   {
11625     /* VEX_W_0F3A49_P_2 */
11626     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11627     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11628   },
11629   {
11630     /* VEX_W_0F3A4A_P_2 */
11631     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11632   },
11633   {
11634     /* VEX_W_0F3A4B_P_2 */
11635     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11636   },
11637   {
11638     /* VEX_W_0F3A4C_P_2 */
11639     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11640   },
11641   {
11642     /* VEX_W_0F3A60_P_2 */
11643     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11644   },
11645   {
11646     /* VEX_W_0F3A61_P_2 */
11647     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11648   },
11649   {
11650     /* VEX_W_0F3A62_P_2 */
11651     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11652   },
11653   {
11654     /* VEX_W_0F3A63_P_2 */
11655     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11656   },
11657   {
11658     /* VEX_W_0F3ADF_P_2 */
11659     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11660   },
11661 #define NEED_VEX_W_TABLE
11662 #include "i386-dis-evex.h"
11663 #undef NEED_VEX_W_TABLE
11664 };
11665
11666 static const struct dis386 mod_table[][2] = {
11667   {
11668     /* MOD_8D */
11669     { "leaS",           { Gv, M }, 0 },
11670   },
11671   {
11672     /* MOD_C6_REG_7 */
11673     { Bad_Opcode },
11674     { RM_TABLE (RM_C6_REG_7) },
11675   },
11676   {
11677     /* MOD_C7_REG_7 */
11678     { Bad_Opcode },
11679     { RM_TABLE (RM_C7_REG_7) },
11680   },
11681   {
11682     /* MOD_FF_REG_3 */
11683     { "Jcall^", { indirEp }, 0 },
11684   },
11685   {
11686     /* MOD_FF_REG_5 */
11687     { "Jjmp^", { indirEp }, 0 },
11688   },
11689   {
11690     /* MOD_0F01_REG_0 */
11691     { X86_64_TABLE (X86_64_0F01_REG_0) },
11692     { RM_TABLE (RM_0F01_REG_0) },
11693   },
11694   {
11695     /* MOD_0F01_REG_1 */
11696     { X86_64_TABLE (X86_64_0F01_REG_1) },
11697     { RM_TABLE (RM_0F01_REG_1) },
11698   },
11699   {
11700     /* MOD_0F01_REG_2 */
11701     { X86_64_TABLE (X86_64_0F01_REG_2) },
11702     { RM_TABLE (RM_0F01_REG_2) },
11703   },
11704   {
11705     /* MOD_0F01_REG_3 */
11706     { X86_64_TABLE (X86_64_0F01_REG_3) },
11707     { RM_TABLE (RM_0F01_REG_3) },
11708   },
11709   {
11710     /* MOD_0F01_REG_5 */
11711     { Bad_Opcode },
11712     { RM_TABLE (RM_0F01_REG_5) },
11713   },
11714   {
11715     /* MOD_0F01_REG_7 */
11716     { "invlpg",         { Mb }, 0 },
11717     { RM_TABLE (RM_0F01_REG_7) },
11718   },
11719   {
11720     /* MOD_0F12_PREFIX_0 */
11721     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11722     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11723   },
11724   {
11725     /* MOD_0F13 */
11726     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11727   },
11728   {
11729     /* MOD_0F16_PREFIX_0 */
11730     { "movhps",         { XM, EXq }, 0 },
11731     { "movlhps",        { XM, EXq }, 0 },
11732   },
11733   {
11734     /* MOD_0F17 */
11735     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11736   },
11737   {
11738     /* MOD_0F18_REG_0 */
11739     { "prefetchnta",    { Mb }, 0 },
11740   },
11741   {
11742     /* MOD_0F18_REG_1 */
11743     { "prefetcht0",     { Mb }, 0 },
11744   },
11745   {
11746     /* MOD_0F18_REG_2 */
11747     { "prefetcht1",     { Mb }, 0 },
11748   },
11749   {
11750     /* MOD_0F18_REG_3 */
11751     { "prefetcht2",     { Mb }, 0 },
11752   },
11753   {
11754     /* MOD_0F18_REG_4 */
11755     { "nop/reserved",   { Mb }, 0 },
11756   },
11757   {
11758     /* MOD_0F18_REG_5 */
11759     { "nop/reserved",   { Mb }, 0 },
11760   },
11761   {
11762     /* MOD_0F18_REG_6 */
11763     { "nop/reserved",   { Mb }, 0 },
11764   },
11765   {
11766     /* MOD_0F18_REG_7 */
11767     { "nop/reserved",   { Mb }, 0 },
11768   },
11769   {
11770     /* MOD_0F1A_PREFIX_0 */
11771     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11772     { "nopQ",           { Ev }, 0 },
11773   },
11774   {
11775     /* MOD_0F1B_PREFIX_0 */
11776     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11777     { "nopQ",           { Ev }, 0 },
11778   },
11779   {
11780     /* MOD_0F1B_PREFIX_1 */
11781     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11782     { "nopQ",           { Ev }, 0 },
11783   },
11784   {
11785     /* MOD_0F24 */
11786     { Bad_Opcode },
11787     { "movL",           { Rd, Td }, 0 },
11788   },
11789   {
11790     /* MOD_0F26 */
11791     { Bad_Opcode },
11792     { "movL",           { Td, Rd }, 0 },
11793   },
11794   {
11795     /* MOD_0F2B_PREFIX_0 */
11796     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11797   },
11798   {
11799     /* MOD_0F2B_PREFIX_1 */
11800     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11801   },
11802   {
11803     /* MOD_0F2B_PREFIX_2 */
11804     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11805   },
11806   {
11807     /* MOD_0F2B_PREFIX_3 */
11808     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11809   },
11810   {
11811     /* MOD_0F51 */
11812     { Bad_Opcode },
11813     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11814   },
11815   {
11816     /* MOD_0F71_REG_2 */
11817     { Bad_Opcode },
11818     { "psrlw",          { MS, Ib }, 0 },
11819   },
11820   {
11821     /* MOD_0F71_REG_4 */
11822     { Bad_Opcode },
11823     { "psraw",          { MS, Ib }, 0 },
11824   },
11825   {
11826     /* MOD_0F71_REG_6 */
11827     { Bad_Opcode },
11828     { "psllw",          { MS, Ib }, 0 },
11829   },
11830   {
11831     /* MOD_0F72_REG_2 */
11832     { Bad_Opcode },
11833     { "psrld",          { MS, Ib }, 0 },
11834   },
11835   {
11836     /* MOD_0F72_REG_4 */
11837     { Bad_Opcode },
11838     { "psrad",          { MS, Ib }, 0 },
11839   },
11840   {
11841     /* MOD_0F72_REG_6 */
11842     { Bad_Opcode },
11843     { "pslld",          { MS, Ib }, 0 },
11844   },
11845   {
11846     /* MOD_0F73_REG_2 */
11847     { Bad_Opcode },
11848     { "psrlq",          { MS, Ib }, 0 },
11849   },
11850   {
11851     /* MOD_0F73_REG_3 */
11852     { Bad_Opcode },
11853     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11854   },
11855   {
11856     /* MOD_0F73_REG_6 */
11857     { Bad_Opcode },
11858     { "psllq",          { MS, Ib }, 0 },
11859   },
11860   {
11861     /* MOD_0F73_REG_7 */
11862     { Bad_Opcode },
11863     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11864   },
11865   {
11866     /* MOD_0FAE_REG_0 */
11867     { "fxsave",         { FXSAVE }, 0 },
11868     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11869   },
11870   {
11871     /* MOD_0FAE_REG_1 */
11872     { "fxrstor",        { FXSAVE }, 0 },
11873     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11874   },
11875   {
11876     /* MOD_0FAE_REG_2 */
11877     { "ldmxcsr",        { Md }, 0 },
11878     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11879   },
11880   {
11881     /* MOD_0FAE_REG_3 */
11882     { "stmxcsr",        { Md }, 0 },
11883     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11884   },
11885   {
11886     /* MOD_0FAE_REG_4 */
11887     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11888     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11889   },
11890   {
11891     /* MOD_0FAE_REG_5 */
11892     { "xrstor",         { FXSAVE }, 0 },
11893     { RM_TABLE (RM_0FAE_REG_5) },
11894   },
11895   {
11896     /* MOD_0FAE_REG_6 */
11897     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11898     { RM_TABLE (RM_0FAE_REG_6) },
11899   },
11900   {
11901     /* MOD_0FAE_REG_7 */
11902     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11903     { RM_TABLE (RM_0FAE_REG_7) },
11904   },
11905   {
11906     /* MOD_0FB2 */
11907     { "lssS",           { Gv, Mp }, 0 },
11908   },
11909   {
11910     /* MOD_0FB4 */
11911     { "lfsS",           { Gv, Mp }, 0 },
11912   },
11913   {
11914     /* MOD_0FB5 */
11915     { "lgsS",           { Gv, Mp }, 0 },
11916   },
11917   {
11918     /* MOD_0FC3 */
11919     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11920   },
11921   {
11922     /* MOD_0FC7_REG_3 */
11923     { "xrstors",        { FXSAVE }, 0 },
11924   },
11925   {
11926     /* MOD_0FC7_REG_4 */
11927     { "xsavec",         { FXSAVE }, 0 },
11928   },
11929   {
11930     /* MOD_0FC7_REG_5 */
11931     { "xsaves",         { FXSAVE }, 0 },
11932   },
11933   {
11934     /* MOD_0FC7_REG_6 */
11935     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11936     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11937   },
11938   {
11939     /* MOD_0FC7_REG_7 */
11940     { "vmptrst",        { Mq }, 0 },
11941     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11942   },
11943   {
11944     /* MOD_0FD7 */
11945     { Bad_Opcode },
11946     { "pmovmskb",       { Gdq, MS }, 0 },
11947   },
11948   {
11949     /* MOD_0FE7_PREFIX_2 */
11950     { "movntdq",        { Mx, XM }, 0 },
11951   },
11952   {
11953     /* MOD_0FF0_PREFIX_3 */
11954     { "lddqu",          { XM, M }, 0 },
11955   },
11956   {
11957     /* MOD_0F382A_PREFIX_2 */
11958     { "movntdqa",       { XM, Mx }, 0 },
11959   },
11960   {
11961     /* MOD_62_32BIT */
11962     { "bound{S|}",      { Gv, Ma }, 0 },
11963     { EVEX_TABLE (EVEX_0F) },
11964   },
11965   {
11966     /* MOD_C4_32BIT */
11967     { "lesS",           { Gv, Mp }, 0 },
11968     { VEX_C4_TABLE (VEX_0F) },
11969   },
11970   {
11971     /* MOD_C5_32BIT */
11972     { "ldsS",           { Gv, Mp }, 0 },
11973     { VEX_C5_TABLE (VEX_0F) },
11974   },
11975   {
11976     /* MOD_VEX_0F12_PREFIX_0 */
11977     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11978     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11979   },
11980   {
11981     /* MOD_VEX_0F13 */
11982     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11983   },
11984   {
11985     /* MOD_VEX_0F16_PREFIX_0 */
11986     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11987     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11988   },
11989   {
11990     /* MOD_VEX_0F17 */
11991     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11992   },
11993   {
11994     /* MOD_VEX_0F2B */
11995     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11996   },
11997   {
11998     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11999     { Bad_Opcode },
12000     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
12001   },
12002   {
12003     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
12004     { Bad_Opcode },
12005     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
12006   },
12007   {
12008     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
12009     { Bad_Opcode },
12010     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
12011   },
12012   {
12013     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
12014     { Bad_Opcode },
12015     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
12016   },
12017   {
12018     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
12019     { Bad_Opcode },
12020     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
12021   },
12022   {
12023     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
12024     { Bad_Opcode },
12025     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
12026   },
12027   {
12028     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
12029     { Bad_Opcode },
12030     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
12031   },
12032   {
12033     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
12034     { Bad_Opcode },
12035     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
12036   },
12037   {
12038     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
12039     { Bad_Opcode },
12040     { "knotw",          { MaskG, MaskR }, 0 },
12041   },
12042   {
12043     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
12044     { Bad_Opcode },
12045     { "knotq",          { MaskG, MaskR }, 0 },
12046   },
12047   {
12048     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
12049     { Bad_Opcode },
12050     { "knotb",          { MaskG, MaskR }, 0 },
12051   },
12052   {
12053     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
12054     { Bad_Opcode },
12055     { "knotd",          { MaskG, MaskR }, 0 },
12056   },
12057   {
12058     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
12059     { Bad_Opcode },
12060     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
12061   },
12062   {
12063     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
12064     { Bad_Opcode },
12065     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
12066   },
12067   {
12068     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
12069     { Bad_Opcode },
12070     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
12071   },
12072   {
12073     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
12074     { Bad_Opcode },
12075     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
12076   },
12077  {
12078     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
12079     { Bad_Opcode },
12080     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
12081   },
12082   {
12083     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
12084     { Bad_Opcode },
12085     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
12086   },
12087   {
12088     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12089     { Bad_Opcode },
12090     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
12091   },
12092   {
12093     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12094     { Bad_Opcode },
12095     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
12096   },
12097   {
12098     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12099     { Bad_Opcode },
12100     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
12101   },
12102   {
12103     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12104     { Bad_Opcode },
12105     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
12106   },
12107   {
12108     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12109     { Bad_Opcode },
12110     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
12111   },
12112   {
12113     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12114     { Bad_Opcode },
12115     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
12116   },
12117   {
12118     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12119     { Bad_Opcode },
12120     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
12121   },
12122   {
12123     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12124     { Bad_Opcode },
12125     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
12126   },
12127   {
12128     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12129     { Bad_Opcode },
12130     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
12131   },
12132   {
12133     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12134     { Bad_Opcode },
12135     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
12136   },
12137   {
12138     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12139     { Bad_Opcode },
12140     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
12141   },
12142   {
12143     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12144     { Bad_Opcode },
12145     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
12146   },
12147   {
12148     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12149     { Bad_Opcode },
12150     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
12151   },
12152   {
12153     /* MOD_VEX_0F50 */
12154     { Bad_Opcode },
12155     { VEX_W_TABLE (VEX_W_0F50_M_0) },
12156   },
12157   {
12158     /* MOD_VEX_0F71_REG_2 */
12159     { Bad_Opcode },
12160     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12161   },
12162   {
12163     /* MOD_VEX_0F71_REG_4 */
12164     { Bad_Opcode },
12165     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12166   },
12167   {
12168     /* MOD_VEX_0F71_REG_6 */
12169     { Bad_Opcode },
12170     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12171   },
12172   {
12173     /* MOD_VEX_0F72_REG_2 */
12174     { Bad_Opcode },
12175     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12176   },
12177   {
12178     /* MOD_VEX_0F72_REG_4 */
12179     { Bad_Opcode },
12180     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12181   },
12182   {
12183     /* MOD_VEX_0F72_REG_6 */
12184     { Bad_Opcode },
12185     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12186   },
12187   {
12188     /* MOD_VEX_0F73_REG_2 */
12189     { Bad_Opcode },
12190     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12191   },
12192   {
12193     /* MOD_VEX_0F73_REG_3 */
12194     { Bad_Opcode },
12195     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12196   },
12197   {
12198     /* MOD_VEX_0F73_REG_6 */
12199     { Bad_Opcode },
12200     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12201   },
12202   {
12203     /* MOD_VEX_0F73_REG_7 */
12204     { Bad_Opcode },
12205     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12206   },
12207   {
12208     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12209     { "kmovw",          { Ew, MaskG }, 0 },
12210     { Bad_Opcode },
12211   },
12212   {
12213     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12214     { "kmovq",          { Eq, MaskG }, 0 },
12215     { Bad_Opcode },
12216   },
12217   {
12218     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12219     { "kmovb",          { Eb, MaskG }, 0 },
12220     { Bad_Opcode },
12221   },
12222   {
12223     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12224     { "kmovd",          { Ed, MaskG }, 0 },
12225     { Bad_Opcode },
12226   },
12227   {
12228     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12229     { Bad_Opcode },
12230     { "kmovw",          { MaskG, Rdq }, 0 },
12231   },
12232   {
12233     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12234     { Bad_Opcode },
12235     { "kmovb",          { MaskG, Rdq }, 0 },
12236   },
12237   {
12238     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12239     { Bad_Opcode },
12240     { "kmovd",          { MaskG, Rdq }, 0 },
12241   },
12242   {
12243     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12244     { Bad_Opcode },
12245     { "kmovq",          { MaskG, Rdq }, 0 },
12246   },
12247   {
12248     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12249     { Bad_Opcode },
12250     { "kmovw",          { Gdq, MaskR }, 0 },
12251   },
12252   {
12253     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12254     { Bad_Opcode },
12255     { "kmovb",          { Gdq, MaskR }, 0 },
12256   },
12257   {
12258     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12259     { Bad_Opcode },
12260     { "kmovd",          { Gdq, MaskR }, 0 },
12261   },
12262   {
12263     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12264     { Bad_Opcode },
12265     { "kmovq",          { Gdq, MaskR }, 0 },
12266   },
12267   {
12268     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12269     { Bad_Opcode },
12270     { "kortestw", { MaskG, MaskR }, 0 },
12271   },
12272   {
12273     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12274     { Bad_Opcode },
12275     { "kortestq", { MaskG, MaskR }, 0 },
12276   },
12277   {
12278     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12279     { Bad_Opcode },
12280     { "kortestb", { MaskG, MaskR }, 0 },
12281   },
12282   {
12283     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12284     { Bad_Opcode },
12285     { "kortestd", { MaskG, MaskR }, 0 },
12286   },
12287   {
12288     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12289     { Bad_Opcode },
12290     { "ktestw", { MaskG, MaskR }, 0 },
12291   },
12292   {
12293     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12294     { Bad_Opcode },
12295     { "ktestq", { MaskG, MaskR }, 0 },
12296   },
12297   {
12298     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12299     { Bad_Opcode },
12300     { "ktestb", { MaskG, MaskR }, 0 },
12301   },
12302   {
12303     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12304     { Bad_Opcode },
12305     { "ktestd", { MaskG, MaskR }, 0 },
12306   },
12307   {
12308     /* MOD_VEX_0FAE_REG_2 */
12309     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12310   },
12311   {
12312     /* MOD_VEX_0FAE_REG_3 */
12313     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12314   },
12315   {
12316     /* MOD_VEX_0FD7_PREFIX_2 */
12317     { Bad_Opcode },
12318     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12319   },
12320   {
12321     /* MOD_VEX_0FE7_PREFIX_2 */
12322     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12323   },
12324   {
12325     /* MOD_VEX_0FF0_PREFIX_3 */
12326     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12327   },
12328   {
12329     /* MOD_VEX_0F381A_PREFIX_2 */
12330     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12331   },
12332   {
12333     /* MOD_VEX_0F382A_PREFIX_2 */
12334     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12335   },
12336   {
12337     /* MOD_VEX_0F382C_PREFIX_2 */
12338     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12339   },
12340   {
12341     /* MOD_VEX_0F382D_PREFIX_2 */
12342     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12343   },
12344   {
12345     /* MOD_VEX_0F382E_PREFIX_2 */
12346     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12347   },
12348   {
12349     /* MOD_VEX_0F382F_PREFIX_2 */
12350     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12351   },
12352   {
12353     /* MOD_VEX_0F385A_PREFIX_2 */
12354     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12355   },
12356   {
12357     /* MOD_VEX_0F388C_PREFIX_2 */
12358     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12359   },
12360   {
12361     /* MOD_VEX_0F388E_PREFIX_2 */
12362     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12363   },
12364   {
12365     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12366     { Bad_Opcode },
12367     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12368   },
12369   {
12370     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12371     { Bad_Opcode },
12372     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12373   },
12374   {
12375     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12376     { Bad_Opcode },
12377     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12378   },
12379   {
12380     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12381     { Bad_Opcode },
12382     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12383   },
12384   {
12385     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12386     { Bad_Opcode },
12387     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12388   },
12389   {
12390     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12391     { Bad_Opcode },
12392     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12393   },
12394   {
12395     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12396     { Bad_Opcode },
12397     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12398   },
12399   {
12400     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12401     { Bad_Opcode },
12402     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12403   },
12404 #define NEED_MOD_TABLE
12405 #include "i386-dis-evex.h"
12406 #undef NEED_MOD_TABLE
12407 };
12408
12409 static const struct dis386 rm_table[][8] = {
12410   {
12411     /* RM_C6_REG_7 */
12412     { "xabort",         { Skip_MODRM, Ib }, 0 },
12413   },
12414   {
12415     /* RM_C7_REG_7 */
12416     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12417   },
12418   {
12419     /* RM_0F01_REG_0 */
12420     { Bad_Opcode },
12421     { "vmcall",         { Skip_MODRM }, 0 },
12422     { "vmlaunch",       { Skip_MODRM }, 0 },
12423     { "vmresume",       { Skip_MODRM }, 0 },
12424     { "vmxoff",         { Skip_MODRM }, 0 },
12425   },
12426   {
12427     /* RM_0F01_REG_1 */
12428     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12429     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12430     { "clac",           { Skip_MODRM }, 0 },
12431     { "stac",           { Skip_MODRM }, 0 },
12432     { Bad_Opcode },
12433     { Bad_Opcode },
12434     { Bad_Opcode },
12435     { "encls",          { Skip_MODRM }, 0 },
12436   },
12437   {
12438     /* RM_0F01_REG_2 */
12439     { "xgetbv",         { Skip_MODRM }, 0 },
12440     { "xsetbv",         { Skip_MODRM }, 0 },
12441     { Bad_Opcode },
12442     { Bad_Opcode },
12443     { "vmfunc",         { Skip_MODRM }, 0 },
12444     { "xend",           { Skip_MODRM }, 0 },
12445     { "xtest",          { Skip_MODRM }, 0 },
12446     { "enclu",          { Skip_MODRM }, 0 },
12447   },
12448   {
12449     /* RM_0F01_REG_3 */
12450     { "vmrun",          { Skip_MODRM }, 0 },
12451     { "vmmcall",        { Skip_MODRM }, 0 },
12452     { "vmload",         { Skip_MODRM }, 0 },
12453     { "vmsave",         { Skip_MODRM }, 0 },
12454     { "stgi",           { Skip_MODRM }, 0 },
12455     { "clgi",           { Skip_MODRM }, 0 },
12456     { "skinit",         { Skip_MODRM }, 0 },
12457     { "invlpga",        { Skip_MODRM }, 0 },
12458   },
12459   {
12460     /* RM_0F01_REG_5 */
12461     { Bad_Opcode },
12462     { Bad_Opcode },
12463     { Bad_Opcode },
12464     { Bad_Opcode },
12465     { Bad_Opcode },
12466     { Bad_Opcode },
12467     { "rdpkru",         { Skip_MODRM }, 0 },
12468     { "wrpkru",         { Skip_MODRM }, 0 },
12469   },
12470   {
12471     /* RM_0F01_REG_7 */
12472     { "swapgs",         { Skip_MODRM }, 0  },
12473     { "rdtscp",         { Skip_MODRM }, 0  },
12474     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12475     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12476     { "clzero",         { Skip_MODRM }, 0  },
12477   },
12478   {
12479     /* RM_0FAE_REG_5 */
12480     { "lfence",         { Skip_MODRM }, 0 },
12481   },
12482   {
12483     /* RM_0FAE_REG_6 */
12484     { "mfence",         { Skip_MODRM }, 0 },
12485   },
12486   {
12487     /* RM_0FAE_REG_7 */
12488     { "sfence",         { Skip_MODRM }, 0 },
12489
12490   },
12491 };
12492
12493 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12494
12495 /* We use the high bit to indicate different name for the same
12496    prefix.  */
12497 #define REP_PREFIX      (0xf3 | 0x100)
12498 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12499 #define XRELEASE_PREFIX (0xf3 | 0x400)
12500 #define BND_PREFIX      (0xf2 | 0x400)
12501
12502 static int
12503 ckprefix (void)
12504 {
12505   int newrex, i, length;
12506   rex = 0;
12507   rex_ignored = 0;
12508   prefixes = 0;
12509   used_prefixes = 0;
12510   rex_used = 0;
12511   last_lock_prefix = -1;
12512   last_repz_prefix = -1;
12513   last_repnz_prefix = -1;
12514   last_data_prefix = -1;
12515   last_addr_prefix = -1;
12516   last_rex_prefix = -1;
12517   last_seg_prefix = -1;
12518   fwait_prefix = -1;
12519   active_seg_prefix = 0;
12520   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12521     all_prefixes[i] = 0;
12522   i = 0;
12523   length = 0;
12524   /* The maximum instruction length is 15bytes.  */
12525   while (length < MAX_CODE_LENGTH - 1)
12526     {
12527       FETCH_DATA (the_info, codep + 1);
12528       newrex = 0;
12529       switch (*codep)
12530         {
12531         /* REX prefixes family.  */
12532         case 0x40:
12533         case 0x41:
12534         case 0x42:
12535         case 0x43:
12536         case 0x44:
12537         case 0x45:
12538         case 0x46:
12539         case 0x47:
12540         case 0x48:
12541         case 0x49:
12542         case 0x4a:
12543         case 0x4b:
12544         case 0x4c:
12545         case 0x4d:
12546         case 0x4e:
12547         case 0x4f:
12548           if (address_mode == mode_64bit)
12549             newrex = *codep;
12550           else
12551             return 1;
12552           last_rex_prefix = i;
12553           break;
12554         case 0xf3:
12555           prefixes |= PREFIX_REPZ;
12556           last_repz_prefix = i;
12557           break;
12558         case 0xf2:
12559           prefixes |= PREFIX_REPNZ;
12560           last_repnz_prefix = i;
12561           break;
12562         case 0xf0:
12563           prefixes |= PREFIX_LOCK;
12564           last_lock_prefix = i;
12565           break;
12566         case 0x2e:
12567           prefixes |= PREFIX_CS;
12568           last_seg_prefix = i;
12569           active_seg_prefix = PREFIX_CS;
12570           break;
12571         case 0x36:
12572           prefixes |= PREFIX_SS;
12573           last_seg_prefix = i;
12574           active_seg_prefix = PREFIX_SS;
12575           break;
12576         case 0x3e:
12577           prefixes |= PREFIX_DS;
12578           last_seg_prefix = i;
12579           active_seg_prefix = PREFIX_DS;
12580           break;
12581         case 0x26:
12582           prefixes |= PREFIX_ES;
12583           last_seg_prefix = i;
12584           active_seg_prefix = PREFIX_ES;
12585           break;
12586         case 0x64:
12587           prefixes |= PREFIX_FS;
12588           last_seg_prefix = i;
12589           active_seg_prefix = PREFIX_FS;
12590           break;
12591         case 0x65:
12592           prefixes |= PREFIX_GS;
12593           last_seg_prefix = i;
12594           active_seg_prefix = PREFIX_GS;
12595           break;
12596         case 0x66:
12597           prefixes |= PREFIX_DATA;
12598           last_data_prefix = i;
12599           break;
12600         case 0x67:
12601           prefixes |= PREFIX_ADDR;
12602           last_addr_prefix = i;
12603           break;
12604         case FWAIT_OPCODE:
12605           /* fwait is really an instruction.  If there are prefixes
12606              before the fwait, they belong to the fwait, *not* to the
12607              following instruction.  */
12608           fwait_prefix = i;
12609           if (prefixes || rex)
12610             {
12611               prefixes |= PREFIX_FWAIT;
12612               codep++;
12613               /* This ensures that the previous REX prefixes are noticed
12614                  as unused prefixes, as in the return case below.  */
12615               rex_used = rex;
12616               return 1;
12617             }
12618           prefixes = PREFIX_FWAIT;
12619           break;
12620         default:
12621           return 1;
12622         }
12623       /* Rex is ignored when followed by another prefix.  */
12624       if (rex)
12625         {
12626           rex_used = rex;
12627           return 1;
12628         }
12629       if (*codep != FWAIT_OPCODE)
12630         all_prefixes[i++] = *codep;
12631       rex = newrex;
12632       codep++;
12633       length++;
12634     }
12635   return 0;
12636 }
12637
12638 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12639    prefix byte.  */
12640
12641 static const char *
12642 prefix_name (int pref, int sizeflag)
12643 {
12644   static const char *rexes [16] =
12645     {
12646       "rex",            /* 0x40 */
12647       "rex.B",          /* 0x41 */
12648       "rex.X",          /* 0x42 */
12649       "rex.XB",         /* 0x43 */
12650       "rex.R",          /* 0x44 */
12651       "rex.RB",         /* 0x45 */
12652       "rex.RX",         /* 0x46 */
12653       "rex.RXB",        /* 0x47 */
12654       "rex.W",          /* 0x48 */
12655       "rex.WB",         /* 0x49 */
12656       "rex.WX",         /* 0x4a */
12657       "rex.WXB",        /* 0x4b */
12658       "rex.WR",         /* 0x4c */
12659       "rex.WRB",        /* 0x4d */
12660       "rex.WRX",        /* 0x4e */
12661       "rex.WRXB",       /* 0x4f */
12662     };
12663
12664   switch (pref)
12665     {
12666     /* REX prefixes family.  */
12667     case 0x40:
12668     case 0x41:
12669     case 0x42:
12670     case 0x43:
12671     case 0x44:
12672     case 0x45:
12673     case 0x46:
12674     case 0x47:
12675     case 0x48:
12676     case 0x49:
12677     case 0x4a:
12678     case 0x4b:
12679     case 0x4c:
12680     case 0x4d:
12681     case 0x4e:
12682     case 0x4f:
12683       return rexes [pref - 0x40];
12684     case 0xf3:
12685       return "repz";
12686     case 0xf2:
12687       return "repnz";
12688     case 0xf0:
12689       return "lock";
12690     case 0x2e:
12691       return "cs";
12692     case 0x36:
12693       return "ss";
12694     case 0x3e:
12695       return "ds";
12696     case 0x26:
12697       return "es";
12698     case 0x64:
12699       return "fs";
12700     case 0x65:
12701       return "gs";
12702     case 0x66:
12703       return (sizeflag & DFLAG) ? "data16" : "data32";
12704     case 0x67:
12705       if (address_mode == mode_64bit)
12706         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12707       else
12708         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12709     case FWAIT_OPCODE:
12710       return "fwait";
12711     case REP_PREFIX:
12712       return "rep";
12713     case XACQUIRE_PREFIX:
12714       return "xacquire";
12715     case XRELEASE_PREFIX:
12716       return "xrelease";
12717     case BND_PREFIX:
12718       return "bnd";
12719     default:
12720       return NULL;
12721     }
12722 }
12723
12724 static char op_out[MAX_OPERANDS][100];
12725 static int op_ad, op_index[MAX_OPERANDS];
12726 static int two_source_ops;
12727 static bfd_vma op_address[MAX_OPERANDS];
12728 static bfd_vma op_riprel[MAX_OPERANDS];
12729 static bfd_vma start_pc;
12730
12731 /*
12732  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12733  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12734  *   section of the "Virtual 8086 Mode" chapter.)
12735  * 'pc' should be the address of this instruction, it will
12736  *   be used to print the target address if this is a relative jump or call
12737  * The function returns the length of this instruction in bytes.
12738  */
12739
12740 static char intel_syntax;
12741 static char intel_mnemonic = !SYSV386_COMPAT;
12742 static char open_char;
12743 static char close_char;
12744 static char separator_char;
12745 static char scale_char;
12746
12747 enum x86_64_isa
12748 {
12749   amd64 = 0,
12750   intel64
12751 };
12752
12753 static enum x86_64_isa isa64;
12754
12755 /* Here for backwards compatibility.  When gdb stops using
12756    print_insn_i386_att and print_insn_i386_intel these functions can
12757    disappear, and print_insn_i386 be merged into print_insn.  */
12758 int
12759 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12760 {
12761   intel_syntax = 0;
12762
12763   return print_insn (pc, info);
12764 }
12765
12766 int
12767 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12768 {
12769   intel_syntax = 1;
12770
12771   return print_insn (pc, info);
12772 }
12773
12774 int
12775 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12776 {
12777   intel_syntax = -1;
12778
12779   return print_insn (pc, info);
12780 }
12781
12782 void
12783 print_i386_disassembler_options (FILE *stream)
12784 {
12785   fprintf (stream, _("\n\
12786 The following i386/x86-64 specific disassembler options are supported for use\n\
12787 with the -M switch (multiple options should be separated by commas):\n"));
12788
12789   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12790   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12791   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12792   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12793   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12794   fprintf (stream, _("  att-mnemonic\n"
12795                      "              Display instruction in AT&T mnemonic\n"));
12796   fprintf (stream, _("  intel-mnemonic\n"
12797                      "              Display instruction in Intel mnemonic\n"));
12798   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12799   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12800   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12801   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12802   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12803   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12804   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12805   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12806 }
12807
12808 /* Bad opcode.  */
12809 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12810
12811 /* Get a pointer to struct dis386 with a valid name.  */
12812
12813 static const struct dis386 *
12814 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12815 {
12816   int vindex, vex_table_index;
12817
12818   if (dp->name != NULL)
12819     return dp;
12820
12821   switch (dp->op[0].bytemode)
12822     {
12823     case USE_REG_TABLE:
12824       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12825       break;
12826
12827     case USE_MOD_TABLE:
12828       vindex = modrm.mod == 0x3 ? 1 : 0;
12829       dp = &mod_table[dp->op[1].bytemode][vindex];
12830       break;
12831
12832     case USE_RM_TABLE:
12833       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12834       break;
12835
12836     case USE_PREFIX_TABLE:
12837       if (need_vex)
12838         {
12839           /* The prefix in VEX is implicit.  */
12840           switch (vex.prefix)
12841             {
12842             case 0:
12843               vindex = 0;
12844               break;
12845             case REPE_PREFIX_OPCODE:
12846               vindex = 1;
12847               break;
12848             case DATA_PREFIX_OPCODE:
12849               vindex = 2;
12850               break;
12851             case REPNE_PREFIX_OPCODE:
12852               vindex = 3;
12853               break;
12854             default:
12855               abort ();
12856               break;
12857             }
12858         }
12859       else
12860         {
12861           int last_prefix = -1;
12862           int prefix = 0;
12863           vindex = 0;
12864           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12865              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12866              last one wins.  */
12867           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12868             {
12869               if (last_repz_prefix > last_repnz_prefix)
12870                 {
12871                   vindex = 1;
12872                   prefix = PREFIX_REPZ;
12873                   last_prefix = last_repz_prefix;
12874                 }
12875               else
12876                 {
12877                   vindex = 3;
12878                   prefix = PREFIX_REPNZ;
12879                   last_prefix = last_repnz_prefix;
12880                 }
12881
12882               /* Check if prefix should be ignored.  */
12883               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12884                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12885                    & prefix) != 0)
12886                 vindex = 0;
12887             }
12888
12889           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12890             {
12891               vindex = 2;
12892               prefix = PREFIX_DATA;
12893               last_prefix = last_data_prefix;
12894             }
12895
12896           if (vindex != 0)
12897             {
12898               used_prefixes |= prefix;
12899               all_prefixes[last_prefix] = 0;
12900             }
12901         }
12902       dp = &prefix_table[dp->op[1].bytemode][vindex];
12903       break;
12904
12905     case USE_X86_64_TABLE:
12906       vindex = address_mode == mode_64bit ? 1 : 0;
12907       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12908       break;
12909
12910     case USE_3BYTE_TABLE:
12911       FETCH_DATA (info, codep + 2);
12912       vindex = *codep++;
12913       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12914       end_codep = codep;
12915       modrm.mod = (*codep >> 6) & 3;
12916       modrm.reg = (*codep >> 3) & 7;
12917       modrm.rm = *codep & 7;
12918       break;
12919
12920     case USE_VEX_LEN_TABLE:
12921       if (!need_vex)
12922         abort ();
12923
12924       switch (vex.length)
12925         {
12926         case 128:
12927           vindex = 0;
12928           break;
12929         case 256:
12930           vindex = 1;
12931           break;
12932         default:
12933           abort ();
12934           break;
12935         }
12936
12937       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12938       break;
12939
12940     case USE_XOP_8F_TABLE:
12941       FETCH_DATA (info, codep + 3);
12942       /* All bits in the REX prefix are ignored.  */
12943       rex_ignored = rex;
12944       rex = ~(*codep >> 5) & 0x7;
12945
12946       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12947       switch ((*codep & 0x1f))
12948         {
12949         default:
12950           dp = &bad_opcode;
12951           return dp;
12952         case 0x8:
12953           vex_table_index = XOP_08;
12954           break;
12955         case 0x9:
12956           vex_table_index = XOP_09;
12957           break;
12958         case 0xa:
12959           vex_table_index = XOP_0A;
12960           break;
12961         }
12962       codep++;
12963       vex.w = *codep & 0x80;
12964       if (vex.w && address_mode == mode_64bit)
12965         rex |= REX_W;
12966
12967       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12968       if (address_mode != mode_64bit
12969           && vex.register_specifier > 0x7)
12970         {
12971           dp = &bad_opcode;
12972           return dp;
12973         }
12974
12975       vex.length = (*codep & 0x4) ? 256 : 128;
12976       switch ((*codep & 0x3))
12977         {
12978         case 0:
12979           vex.prefix = 0;
12980           break;
12981         case 1:
12982           vex.prefix = DATA_PREFIX_OPCODE;
12983           break;
12984         case 2:
12985           vex.prefix = REPE_PREFIX_OPCODE;
12986           break;
12987         case 3:
12988           vex.prefix = REPNE_PREFIX_OPCODE;
12989           break;
12990         }
12991       need_vex = 1;
12992       need_vex_reg = 1;
12993       codep++;
12994       vindex = *codep++;
12995       dp = &xop_table[vex_table_index][vindex];
12996
12997       end_codep = codep;
12998       FETCH_DATA (info, codep + 1);
12999       modrm.mod = (*codep >> 6) & 3;
13000       modrm.reg = (*codep >> 3) & 7;
13001       modrm.rm = *codep & 7;
13002       break;
13003
13004     case USE_VEX_C4_TABLE:
13005       /* VEX prefix.  */
13006       FETCH_DATA (info, codep + 3);
13007       /* All bits in the REX prefix are ignored.  */
13008       rex_ignored = rex;
13009       rex = ~(*codep >> 5) & 0x7;
13010       switch ((*codep & 0x1f))
13011         {
13012         default:
13013           dp = &bad_opcode;
13014           return dp;
13015         case 0x1:
13016           vex_table_index = VEX_0F;
13017           break;
13018         case 0x2:
13019           vex_table_index = VEX_0F38;
13020           break;
13021         case 0x3:
13022           vex_table_index = VEX_0F3A;
13023           break;
13024         }
13025       codep++;
13026       vex.w = *codep & 0x80;
13027       if (address_mode == mode_64bit)
13028         {
13029           if (vex.w)
13030             rex |= REX_W;
13031           vex.register_specifier = (~(*codep >> 3)) & 0xf;
13032         }
13033       else
13034         {
13035           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
13036              is ignored, other REX bits are 0 and the highest bit in
13037              VEX.vvvv is also ignored.  */
13038           rex = 0;
13039           vex.register_specifier = (~(*codep >> 3)) & 0x7;
13040         }
13041       vex.length = (*codep & 0x4) ? 256 : 128;
13042       switch ((*codep & 0x3))
13043         {
13044         case 0:
13045           vex.prefix = 0;
13046           break;
13047         case 1:
13048           vex.prefix = DATA_PREFIX_OPCODE;
13049           break;
13050         case 2:
13051           vex.prefix = REPE_PREFIX_OPCODE;
13052           break;
13053         case 3:
13054           vex.prefix = REPNE_PREFIX_OPCODE;
13055           break;
13056         }
13057       need_vex = 1;
13058       need_vex_reg = 1;
13059       codep++;
13060       vindex = *codep++;
13061       dp = &vex_table[vex_table_index][vindex];
13062       end_codep = codep;
13063       /* There is no MODRM byte for VEX [82|77].  */
13064       if (vindex != 0x77 && vindex != 0x82)
13065         {
13066           FETCH_DATA (info, codep + 1);
13067           modrm.mod = (*codep >> 6) & 3;
13068           modrm.reg = (*codep >> 3) & 7;
13069           modrm.rm = *codep & 7;
13070         }
13071       break;
13072
13073     case USE_VEX_C5_TABLE:
13074       /* VEX prefix.  */
13075       FETCH_DATA (info, codep + 2);
13076       /* All bits in the REX prefix are ignored.  */
13077       rex_ignored = rex;
13078       rex = (*codep & 0x80) ? 0 : REX_R;
13079
13080       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
13081          VEX.vvvv is 1.  */
13082       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13083       vex.w = 0;
13084       vex.length = (*codep & 0x4) ? 256 : 128;
13085       switch ((*codep & 0x3))
13086         {
13087         case 0:
13088           vex.prefix = 0;
13089           break;
13090         case 1:
13091           vex.prefix = DATA_PREFIX_OPCODE;
13092           break;
13093         case 2:
13094           vex.prefix = REPE_PREFIX_OPCODE;
13095           break;
13096         case 3:
13097           vex.prefix = REPNE_PREFIX_OPCODE;
13098           break;
13099         }
13100       need_vex = 1;
13101       need_vex_reg = 1;
13102       codep++;
13103       vindex = *codep++;
13104       dp = &vex_table[dp->op[1].bytemode][vindex];
13105       end_codep = codep;
13106       /* There is no MODRM byte for VEX [82|77].  */
13107       if (vindex != 0x77 && vindex != 0x82)
13108         {
13109           FETCH_DATA (info, codep + 1);
13110           modrm.mod = (*codep >> 6) & 3;
13111           modrm.reg = (*codep >> 3) & 7;
13112           modrm.rm = *codep & 7;
13113         }
13114       break;
13115
13116     case USE_VEX_W_TABLE:
13117       if (!need_vex)
13118         abort ();
13119
13120       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13121       break;
13122
13123     case USE_EVEX_TABLE:
13124       two_source_ops = 0;
13125       /* EVEX prefix.  */
13126       vex.evex = 1;
13127       FETCH_DATA (info, codep + 4);
13128       /* All bits in the REX prefix are ignored.  */
13129       rex_ignored = rex;
13130       /* The first byte after 0x62.  */
13131       rex = ~(*codep >> 5) & 0x7;
13132       vex.r = *codep & 0x10;
13133       switch ((*codep & 0xf))
13134         {
13135         default:
13136           return &bad_opcode;
13137         case 0x1:
13138           vex_table_index = EVEX_0F;
13139           break;
13140         case 0x2:
13141           vex_table_index = EVEX_0F38;
13142           break;
13143         case 0x3:
13144           vex_table_index = EVEX_0F3A;
13145           break;
13146         }
13147
13148       /* The second byte after 0x62.  */
13149       codep++;
13150       vex.w = *codep & 0x80;
13151       if (vex.w && address_mode == mode_64bit)
13152         rex |= REX_W;
13153
13154       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13155       if (address_mode != mode_64bit)
13156         {
13157           /* In 16/32-bit mode silently ignore following bits.  */
13158           rex &= ~REX_B;
13159           vex.r = 1;
13160           vex.v = 1;
13161           vex.register_specifier &= 0x7;
13162         }
13163
13164       /* The U bit.  */
13165       if (!(*codep & 0x4))
13166         return &bad_opcode;
13167
13168       switch ((*codep & 0x3))
13169         {
13170         case 0:
13171           vex.prefix = 0;
13172           break;
13173         case 1:
13174           vex.prefix = DATA_PREFIX_OPCODE;
13175           break;
13176         case 2:
13177           vex.prefix = REPE_PREFIX_OPCODE;
13178           break;
13179         case 3:
13180           vex.prefix = REPNE_PREFIX_OPCODE;
13181           break;
13182         }
13183
13184       /* The third byte after 0x62.  */
13185       codep++;
13186
13187       /* Remember the static rounding bits.  */
13188       vex.ll = (*codep >> 5) & 3;
13189       vex.b = (*codep & 0x10) != 0;
13190
13191       vex.v = *codep & 0x8;
13192       vex.mask_register_specifier = *codep & 0x7;
13193       vex.zeroing = *codep & 0x80;
13194
13195       need_vex = 1;
13196       need_vex_reg = 1;
13197       codep++;
13198       vindex = *codep++;
13199       dp = &evex_table[vex_table_index][vindex];
13200       end_codep = codep;
13201       FETCH_DATA (info, codep + 1);
13202       modrm.mod = (*codep >> 6) & 3;
13203       modrm.reg = (*codep >> 3) & 7;
13204       modrm.rm = *codep & 7;
13205
13206       /* Set vector length.  */
13207       if (modrm.mod == 3 && vex.b)
13208         vex.length = 512;
13209       else
13210         {
13211           switch (vex.ll)
13212             {
13213             case 0x0:
13214               vex.length = 128;
13215               break;
13216             case 0x1:
13217               vex.length = 256;
13218               break;
13219             case 0x2:
13220               vex.length = 512;
13221               break;
13222             default:
13223               return &bad_opcode;
13224             }
13225         }
13226       break;
13227
13228     case 0:
13229       dp = &bad_opcode;
13230       break;
13231
13232     default:
13233       abort ();
13234     }
13235
13236   if (dp->name != NULL)
13237     return dp;
13238   else
13239     return get_valid_dis386 (dp, info);
13240 }
13241
13242 static void
13243 get_sib (disassemble_info *info, int sizeflag)
13244 {
13245   /* If modrm.mod == 3, operand must be register.  */
13246   if (need_modrm
13247       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13248       && modrm.mod != 3
13249       && modrm.rm == 4)
13250     {
13251       FETCH_DATA (info, codep + 2);
13252       sib.index = (codep [1] >> 3) & 7;
13253       sib.scale = (codep [1] >> 6) & 3;
13254       sib.base = codep [1] & 7;
13255     }
13256 }
13257
13258 static int
13259 print_insn (bfd_vma pc, disassemble_info *info)
13260 {
13261   const struct dis386 *dp;
13262   int i;
13263   char *op_txt[MAX_OPERANDS];
13264   int needcomma;
13265   int sizeflag, orig_sizeflag;
13266   const char *p;
13267   struct dis_private priv;
13268   int prefix_length;
13269
13270   priv.orig_sizeflag = AFLAG | DFLAG;
13271   if ((info->mach & bfd_mach_i386_i386) != 0)
13272     address_mode = mode_32bit;
13273   else if (info->mach == bfd_mach_i386_i8086)
13274     {
13275       address_mode = mode_16bit;
13276       priv.orig_sizeflag = 0;
13277     }
13278   else
13279     address_mode = mode_64bit;
13280
13281   if (intel_syntax == (char) -1)
13282     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13283
13284   for (p = info->disassembler_options; p != NULL; )
13285     {
13286       if (CONST_STRNEQ (p, "amd64"))
13287         isa64 = amd64;
13288       else if (CONST_STRNEQ (p, "intel64"))
13289         isa64 = intel64;
13290       else if (CONST_STRNEQ (p, "x86-64"))
13291         {
13292           address_mode = mode_64bit;
13293           priv.orig_sizeflag = AFLAG | DFLAG;
13294         }
13295       else if (CONST_STRNEQ (p, "i386"))
13296         {
13297           address_mode = mode_32bit;
13298           priv.orig_sizeflag = AFLAG | DFLAG;
13299         }
13300       else if (CONST_STRNEQ (p, "i8086"))
13301         {
13302           address_mode = mode_16bit;
13303           priv.orig_sizeflag = 0;
13304         }
13305       else if (CONST_STRNEQ (p, "intel"))
13306         {
13307           intel_syntax = 1;
13308           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13309             intel_mnemonic = 1;
13310         }
13311       else if (CONST_STRNEQ (p, "att"))
13312         {
13313           intel_syntax = 0;
13314           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13315             intel_mnemonic = 0;
13316         }
13317       else if (CONST_STRNEQ (p, "addr"))
13318         {
13319           if (address_mode == mode_64bit)
13320             {
13321               if (p[4] == '3' && p[5] == '2')
13322                 priv.orig_sizeflag &= ~AFLAG;
13323               else if (p[4] == '6' && p[5] == '4')
13324                 priv.orig_sizeflag |= AFLAG;
13325             }
13326           else
13327             {
13328               if (p[4] == '1' && p[5] == '6')
13329                 priv.orig_sizeflag &= ~AFLAG;
13330               else if (p[4] == '3' && p[5] == '2')
13331                 priv.orig_sizeflag |= AFLAG;
13332             }
13333         }
13334       else if (CONST_STRNEQ (p, "data"))
13335         {
13336           if (p[4] == '1' && p[5] == '6')
13337             priv.orig_sizeflag &= ~DFLAG;
13338           else if (p[4] == '3' && p[5] == '2')
13339             priv.orig_sizeflag |= DFLAG;
13340         }
13341       else if (CONST_STRNEQ (p, "suffix"))
13342         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13343
13344       p = strchr (p, ',');
13345       if (p != NULL)
13346         p++;
13347     }
13348
13349   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13350     {
13351       (*info->fprintf_func) (info->stream,
13352                              _("64-bit address is disabled"));
13353       return -1;
13354     }
13355
13356   if (intel_syntax)
13357     {
13358       names64 = intel_names64;
13359       names32 = intel_names32;
13360       names16 = intel_names16;
13361       names8 = intel_names8;
13362       names8rex = intel_names8rex;
13363       names_seg = intel_names_seg;
13364       names_mm = intel_names_mm;
13365       names_bnd = intel_names_bnd;
13366       names_xmm = intel_names_xmm;
13367       names_ymm = intel_names_ymm;
13368       names_zmm = intel_names_zmm;
13369       index64 = intel_index64;
13370       index32 = intel_index32;
13371       names_mask = intel_names_mask;
13372       index16 = intel_index16;
13373       open_char = '[';
13374       close_char = ']';
13375       separator_char = '+';
13376       scale_char = '*';
13377     }
13378   else
13379     {
13380       names64 = att_names64;
13381       names32 = att_names32;
13382       names16 = att_names16;
13383       names8 = att_names8;
13384       names8rex = att_names8rex;
13385       names_seg = att_names_seg;
13386       names_mm = att_names_mm;
13387       names_bnd = att_names_bnd;
13388       names_xmm = att_names_xmm;
13389       names_ymm = att_names_ymm;
13390       names_zmm = att_names_zmm;
13391       index64 = att_index64;
13392       index32 = att_index32;
13393       names_mask = att_names_mask;
13394       index16 = att_index16;
13395       open_char = '(';
13396       close_char =  ')';
13397       separator_char = ',';
13398       scale_char = ',';
13399     }
13400
13401   /* The output looks better if we put 7 bytes on a line, since that
13402      puts most long word instructions on a single line.  Use 8 bytes
13403      for Intel L1OM.  */
13404   if ((info->mach & bfd_mach_l1om) != 0)
13405     info->bytes_per_line = 8;
13406   else
13407     info->bytes_per_line = 7;
13408
13409   info->private_data = &priv;
13410   priv.max_fetched = priv.the_buffer;
13411   priv.insn_start = pc;
13412
13413   obuf[0] = 0;
13414   for (i = 0; i < MAX_OPERANDS; ++i)
13415     {
13416       op_out[i][0] = 0;
13417       op_index[i] = -1;
13418     }
13419
13420   the_info = info;
13421   start_pc = pc;
13422   start_codep = priv.the_buffer;
13423   codep = priv.the_buffer;
13424
13425   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13426     {
13427       const char *name;
13428
13429       /* Getting here means we tried for data but didn't get it.  That
13430          means we have an incomplete instruction of some sort.  Just
13431          print the first byte as a prefix or a .byte pseudo-op.  */
13432       if (codep > priv.the_buffer)
13433         {
13434           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13435           if (name != NULL)
13436             (*info->fprintf_func) (info->stream, "%s", name);
13437           else
13438             {
13439               /* Just print the first byte as a .byte instruction.  */
13440               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13441                                      (unsigned int) priv.the_buffer[0]);
13442             }
13443
13444           return 1;
13445         }
13446
13447       return -1;
13448     }
13449
13450   obufp = obuf;
13451   sizeflag = priv.orig_sizeflag;
13452
13453   if (!ckprefix () || rex_used)
13454     {
13455       /* Too many prefixes or unused REX prefixes.  */
13456       for (i = 0;
13457            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13458            i++)
13459         (*info->fprintf_func) (info->stream, "%s%s",
13460                                i == 0 ? "" : " ",
13461                                prefix_name (all_prefixes[i], sizeflag));
13462       return i;
13463     }
13464
13465   insn_codep = codep;
13466
13467   FETCH_DATA (info, codep + 1);
13468   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13469
13470   if (((prefixes & PREFIX_FWAIT)
13471        && ((*codep < 0xd8) || (*codep > 0xdf))))
13472     {
13473       /* Handle prefixes before fwait.  */
13474       for (i = 0; i < fwait_prefix && all_prefixes[i];
13475            i++)
13476         (*info->fprintf_func) (info->stream, "%s ",
13477                                prefix_name (all_prefixes[i], sizeflag));
13478       (*info->fprintf_func) (info->stream, "fwait");
13479       return i + 1;
13480     }
13481
13482   if (*codep == 0x0f)
13483     {
13484       unsigned char threebyte;
13485
13486       codep++;
13487       FETCH_DATA (info, codep + 1);
13488       threebyte = *codep;
13489       dp = &dis386_twobyte[threebyte];
13490       need_modrm = twobyte_has_modrm[*codep];
13491       codep++;
13492     }
13493   else
13494     {
13495       dp = &dis386[*codep];
13496       need_modrm = onebyte_has_modrm[*codep];
13497       codep++;
13498     }
13499
13500   /* Save sizeflag for printing the extra prefixes later before updating
13501      it for mnemonic and operand processing.  The prefix names depend
13502      only on the address mode.  */
13503   orig_sizeflag = sizeflag;
13504   if (prefixes & PREFIX_ADDR)
13505     sizeflag ^= AFLAG;
13506   if ((prefixes & PREFIX_DATA))
13507     sizeflag ^= DFLAG;
13508
13509   end_codep = codep;
13510   if (need_modrm)
13511     {
13512       FETCH_DATA (info, codep + 1);
13513       modrm.mod = (*codep >> 6) & 3;
13514       modrm.reg = (*codep >> 3) & 7;
13515       modrm.rm = *codep & 7;
13516     }
13517
13518   need_vex = 0;
13519   need_vex_reg = 0;
13520   vex_w_done = 0;
13521   vex.evex = 0;
13522
13523   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13524     {
13525       get_sib (info, sizeflag);
13526       dofloat (sizeflag);
13527     }
13528   else
13529     {
13530       dp = get_valid_dis386 (dp, info);
13531       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13532         {
13533           get_sib (info, sizeflag);
13534           for (i = 0; i < MAX_OPERANDS; ++i)
13535             {
13536               obufp = op_out[i];
13537               op_ad = MAX_OPERANDS - 1 - i;
13538               if (dp->op[i].rtn)
13539                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13540               /* For EVEX instruction after the last operand masking
13541                  should be printed.  */
13542               if (i == 0 && vex.evex)
13543                 {
13544                   /* Don't print {%k0}.  */
13545                   if (vex.mask_register_specifier)
13546                     {
13547                       oappend ("{");
13548                       oappend (names_mask[vex.mask_register_specifier]);
13549                       oappend ("}");
13550                     }
13551                   if (vex.zeroing)
13552                     oappend ("{z}");
13553                 }
13554             }
13555         }
13556     }
13557
13558   /* Check if the REX prefix is used.  */
13559   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13560     all_prefixes[last_rex_prefix] = 0;
13561
13562   /* Check if the SEG prefix is used.  */
13563   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13564                    | PREFIX_FS | PREFIX_GS)) != 0
13565       && (used_prefixes & active_seg_prefix) != 0)
13566     all_prefixes[last_seg_prefix] = 0;
13567
13568   /* Check if the ADDR prefix is used.  */
13569   if ((prefixes & PREFIX_ADDR) != 0
13570       && (used_prefixes & PREFIX_ADDR) != 0)
13571     all_prefixes[last_addr_prefix] = 0;
13572
13573   /* Check if the DATA prefix is used.  */
13574   if ((prefixes & PREFIX_DATA) != 0
13575       && (used_prefixes & PREFIX_DATA) != 0)
13576     all_prefixes[last_data_prefix] = 0;
13577
13578   /* Print the extra prefixes.  */
13579   prefix_length = 0;
13580   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13581     if (all_prefixes[i])
13582       {
13583         const char *name;
13584         name = prefix_name (all_prefixes[i], orig_sizeflag);
13585         if (name == NULL)
13586           abort ();
13587         prefix_length += strlen (name) + 1;
13588         (*info->fprintf_func) (info->stream, "%s ", name);
13589       }
13590
13591   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13592      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13593      used by putop and MMX/SSE operand and may be overriden by the
13594      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13595      separately.  */
13596   if (dp->prefix_requirement == PREFIX_OPCODE
13597       && dp != &bad_opcode
13598       && (((prefixes
13599             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13600            && (used_prefixes
13601                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13602           || ((((prefixes
13603                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13604                 == PREFIX_DATA)
13605                && (used_prefixes & PREFIX_DATA) == 0))))
13606     {
13607       (*info->fprintf_func) (info->stream, "(bad)");
13608       return end_codep - priv.the_buffer;
13609     }
13610
13611   /* Check maximum code length.  */
13612   if ((codep - start_codep) > MAX_CODE_LENGTH)
13613     {
13614       (*info->fprintf_func) (info->stream, "(bad)");
13615       return MAX_CODE_LENGTH;
13616     }
13617
13618   obufp = mnemonicendp;
13619   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13620     oappend (" ");
13621   oappend (" ");
13622   (*info->fprintf_func) (info->stream, "%s", obuf);
13623
13624   /* The enter and bound instructions are printed with operands in the same
13625      order as the intel book; everything else is printed in reverse order.  */
13626   if (intel_syntax || two_source_ops)
13627     {
13628       bfd_vma riprel;
13629
13630       for (i = 0; i < MAX_OPERANDS; ++i)
13631         op_txt[i] = op_out[i];
13632
13633       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13634           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13635         {
13636           op_txt[2] = op_out[3];
13637           op_txt[3] = op_out[2];
13638         }
13639
13640       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13641         {
13642           op_ad = op_index[i];
13643           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13644           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13645           riprel = op_riprel[i];
13646           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13647           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13648         }
13649     }
13650   else
13651     {
13652       for (i = 0; i < MAX_OPERANDS; ++i)
13653         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13654     }
13655
13656   needcomma = 0;
13657   for (i = 0; i < MAX_OPERANDS; ++i)
13658     if (*op_txt[i])
13659       {
13660         if (needcomma)
13661           (*info->fprintf_func) (info->stream, ",");
13662         if (op_index[i] != -1 && !op_riprel[i])
13663           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13664         else
13665           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13666         needcomma = 1;
13667       }
13668
13669   for (i = 0; i < MAX_OPERANDS; i++)
13670     if (op_index[i] != -1 && op_riprel[i])
13671       {
13672         (*info->fprintf_func) (info->stream, "        # ");
13673         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13674                                                 + op_address[op_index[i]]), info);
13675         break;
13676       }
13677   return codep - priv.the_buffer;
13678 }
13679
13680 static const char *float_mem[] = {
13681   /* d8 */
13682   "fadd{s|}",
13683   "fmul{s|}",
13684   "fcom{s|}",
13685   "fcomp{s|}",
13686   "fsub{s|}",
13687   "fsubr{s|}",
13688   "fdiv{s|}",
13689   "fdivr{s|}",
13690   /* d9 */
13691   "fld{s|}",
13692   "(bad)",
13693   "fst{s|}",
13694   "fstp{s|}",
13695   "fldenvIC",
13696   "fldcw",
13697   "fNstenvIC",
13698   "fNstcw",
13699   /* da */
13700   "fiadd{l|}",
13701   "fimul{l|}",
13702   "ficom{l|}",
13703   "ficomp{l|}",
13704   "fisub{l|}",
13705   "fisubr{l|}",
13706   "fidiv{l|}",
13707   "fidivr{l|}",
13708   /* db */
13709   "fild{l|}",
13710   "fisttp{l|}",
13711   "fist{l|}",
13712   "fistp{l|}",
13713   "(bad)",
13714   "fld{t||t|}",
13715   "(bad)",
13716   "fstp{t||t|}",
13717   /* dc */
13718   "fadd{l|}",
13719   "fmul{l|}",
13720   "fcom{l|}",
13721   "fcomp{l|}",
13722   "fsub{l|}",
13723   "fsubr{l|}",
13724   "fdiv{l|}",
13725   "fdivr{l|}",
13726   /* dd */
13727   "fld{l|}",
13728   "fisttp{ll|}",
13729   "fst{l||}",
13730   "fstp{l|}",
13731   "frstorIC",
13732   "(bad)",
13733   "fNsaveIC",
13734   "fNstsw",
13735   /* de */
13736   "fiadd",
13737   "fimul",
13738   "ficom",
13739   "ficomp",
13740   "fisub",
13741   "fisubr",
13742   "fidiv",
13743   "fidivr",
13744   /* df */
13745   "fild",
13746   "fisttp",
13747   "fist",
13748   "fistp",
13749   "fbld",
13750   "fild{ll|}",
13751   "fbstp",
13752   "fistp{ll|}",
13753 };
13754
13755 static const unsigned char float_mem_mode[] = {
13756   /* d8 */
13757   d_mode,
13758   d_mode,
13759   d_mode,
13760   d_mode,
13761   d_mode,
13762   d_mode,
13763   d_mode,
13764   d_mode,
13765   /* d9 */
13766   d_mode,
13767   0,
13768   d_mode,
13769   d_mode,
13770   0,
13771   w_mode,
13772   0,
13773   w_mode,
13774   /* da */
13775   d_mode,
13776   d_mode,
13777   d_mode,
13778   d_mode,
13779   d_mode,
13780   d_mode,
13781   d_mode,
13782   d_mode,
13783   /* db */
13784   d_mode,
13785   d_mode,
13786   d_mode,
13787   d_mode,
13788   0,
13789   t_mode,
13790   0,
13791   t_mode,
13792   /* dc */
13793   q_mode,
13794   q_mode,
13795   q_mode,
13796   q_mode,
13797   q_mode,
13798   q_mode,
13799   q_mode,
13800   q_mode,
13801   /* dd */
13802   q_mode,
13803   q_mode,
13804   q_mode,
13805   q_mode,
13806   0,
13807   0,
13808   0,
13809   w_mode,
13810   /* de */
13811   w_mode,
13812   w_mode,
13813   w_mode,
13814   w_mode,
13815   w_mode,
13816   w_mode,
13817   w_mode,
13818   w_mode,
13819   /* df */
13820   w_mode,
13821   w_mode,
13822   w_mode,
13823   w_mode,
13824   t_mode,
13825   q_mode,
13826   t_mode,
13827   q_mode
13828 };
13829
13830 #define ST { OP_ST, 0 }
13831 #define STi { OP_STi, 0 }
13832
13833 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13834 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13835 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13836 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13837 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13838 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13839 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13840 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13841 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13842
13843 static const struct dis386 float_reg[][8] = {
13844   /* d8 */
13845   {
13846     { "fadd",   { ST, STi }, 0 },
13847     { "fmul",   { ST, STi }, 0 },
13848     { "fcom",   { STi }, 0 },
13849     { "fcomp",  { STi }, 0 },
13850     { "fsub",   { ST, STi }, 0 },
13851     { "fsubr",  { ST, STi }, 0 },
13852     { "fdiv",   { ST, STi }, 0 },
13853     { "fdivr",  { ST, STi }, 0 },
13854   },
13855   /* d9 */
13856   {
13857     { "fld",    { STi }, 0 },
13858     { "fxch",   { STi }, 0 },
13859     { FGRPd9_2 },
13860     { Bad_Opcode },
13861     { FGRPd9_4 },
13862     { FGRPd9_5 },
13863     { FGRPd9_6 },
13864     { FGRPd9_7 },
13865   },
13866   /* da */
13867   {
13868     { "fcmovb", { ST, STi }, 0 },
13869     { "fcmove", { ST, STi }, 0 },
13870     { "fcmovbe",{ ST, STi }, 0 },
13871     { "fcmovu", { ST, STi }, 0 },
13872     { Bad_Opcode },
13873     { FGRPda_5 },
13874     { Bad_Opcode },
13875     { Bad_Opcode },
13876   },
13877   /* db */
13878   {
13879     { "fcmovnb",{ ST, STi }, 0 },
13880     { "fcmovne",{ ST, STi }, 0 },
13881     { "fcmovnbe",{ ST, STi }, 0 },
13882     { "fcmovnu",{ ST, STi }, 0 },
13883     { FGRPdb_4 },
13884     { "fucomi", { ST, STi }, 0 },
13885     { "fcomi",  { ST, STi }, 0 },
13886     { Bad_Opcode },
13887   },
13888   /* dc */
13889   {
13890     { "fadd",   { STi, ST }, 0 },
13891     { "fmul",   { STi, ST }, 0 },
13892     { Bad_Opcode },
13893     { Bad_Opcode },
13894     { "fsub!M", { STi, ST }, 0 },
13895     { "fsubM",  { STi, ST }, 0 },
13896     { "fdiv!M", { STi, ST }, 0 },
13897     { "fdivM",  { STi, ST }, 0 },
13898   },
13899   /* dd */
13900   {
13901     { "ffree",  { STi }, 0 },
13902     { Bad_Opcode },
13903     { "fst",    { STi }, 0 },
13904     { "fstp",   { STi }, 0 },
13905     { "fucom",  { STi }, 0 },
13906     { "fucomp", { STi }, 0 },
13907     { Bad_Opcode },
13908     { Bad_Opcode },
13909   },
13910   /* de */
13911   {
13912     { "faddp",  { STi, ST }, 0 },
13913     { "fmulp",  { STi, ST }, 0 },
13914     { Bad_Opcode },
13915     { FGRPde_3 },
13916     { "fsub!Mp", { STi, ST }, 0 },
13917     { "fsubMp", { STi, ST }, 0 },
13918     { "fdiv!Mp", { STi, ST }, 0 },
13919     { "fdivMp", { STi, ST }, 0 },
13920   },
13921   /* df */
13922   {
13923     { "ffreep", { STi }, 0 },
13924     { Bad_Opcode },
13925     { Bad_Opcode },
13926     { Bad_Opcode },
13927     { FGRPdf_4 },
13928     { "fucomip", { ST, STi }, 0 },
13929     { "fcomip", { ST, STi }, 0 },
13930     { Bad_Opcode },
13931   },
13932 };
13933
13934 static char *fgrps[][8] = {
13935   /* d9_2  0 */
13936   {
13937     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13938   },
13939
13940   /* d9_4  1 */
13941   {
13942     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13943   },
13944
13945   /* d9_5  2 */
13946   {
13947     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13948   },
13949
13950   /* d9_6  3 */
13951   {
13952     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13953   },
13954
13955   /* d9_7  4 */
13956   {
13957     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13958   },
13959
13960   /* da_5  5 */
13961   {
13962     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13963   },
13964
13965   /* db_4  6 */
13966   {
13967     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13968     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13969   },
13970
13971   /* de_3  7 */
13972   {
13973     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13974   },
13975
13976   /* df_4  8 */
13977   {
13978     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13979   },
13980 };
13981
13982 static void
13983 swap_operand (void)
13984 {
13985   mnemonicendp[0] = '.';
13986   mnemonicendp[1] = 's';
13987   mnemonicendp += 2;
13988 }
13989
13990 static void
13991 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13992                int sizeflag ATTRIBUTE_UNUSED)
13993 {
13994   /* Skip mod/rm byte.  */
13995   MODRM_CHECK;
13996   codep++;
13997 }
13998
13999 static void
14000 dofloat (int sizeflag)
14001 {
14002   const struct dis386 *dp;
14003   unsigned char floatop;
14004
14005   floatop = codep[-1];
14006
14007   if (modrm.mod != 3)
14008     {
14009       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
14010
14011       putop (float_mem[fp_indx], sizeflag);
14012       obufp = op_out[0];
14013       op_ad = 2;
14014       OP_E (float_mem_mode[fp_indx], sizeflag);
14015       return;
14016     }
14017   /* Skip mod/rm byte.  */
14018   MODRM_CHECK;
14019   codep++;
14020
14021   dp = &float_reg[floatop - 0xd8][modrm.reg];
14022   if (dp->name == NULL)
14023     {
14024       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
14025
14026       /* Instruction fnstsw is only one with strange arg.  */
14027       if (floatop == 0xdf && codep[-1] == 0xe0)
14028         strcpy (op_out[0], names16[0]);
14029     }
14030   else
14031     {
14032       putop (dp->name, sizeflag);
14033
14034       obufp = op_out[0];
14035       op_ad = 2;
14036       if (dp->op[0].rtn)
14037         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
14038
14039       obufp = op_out[1];
14040       op_ad = 1;
14041       if (dp->op[1].rtn)
14042         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
14043     }
14044 }
14045
14046 /* Like oappend (below), but S is a string starting with '%'.
14047    In Intel syntax, the '%' is elided.  */
14048 static void
14049 oappend_maybe_intel (const char *s)
14050 {
14051   oappend (s + intel_syntax);
14052 }
14053
14054 static void
14055 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14056 {
14057   oappend_maybe_intel ("%st");
14058 }
14059
14060 static void
14061 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14062 {
14063   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
14064   oappend_maybe_intel (scratchbuf);
14065 }
14066
14067 /* Capital letters in template are macros.  */
14068 static int
14069 putop (const char *in_template, int sizeflag)
14070 {
14071   const char *p;
14072   int alt = 0;
14073   int cond = 1;
14074   unsigned int l = 0, len = 1;
14075   char last[4];
14076
14077 #define SAVE_LAST(c)                    \
14078   if (l < len && l < sizeof (last))     \
14079     last[l++] = c;                      \
14080   else                                  \
14081     abort ();
14082
14083   for (p = in_template; *p; p++)
14084     {
14085       switch (*p)
14086         {
14087         default:
14088           *obufp++ = *p;
14089           break;
14090         case '%':
14091           len++;
14092           break;
14093         case '!':
14094           cond = 0;
14095           break;
14096         case '{':
14097           if (intel_syntax)
14098             {
14099               while (*++p != '|')
14100                 if (*p == '}' || *p == '\0')
14101                   abort ();
14102             }
14103           /* Fall through.  */
14104         case 'I':
14105           alt = 1;
14106           continue;
14107         case '|':
14108           while (*++p != '}')
14109             {
14110               if (*p == '\0')
14111                 abort ();
14112             }
14113           break;
14114         case '}':
14115           break;
14116         case 'A':
14117           if (intel_syntax)
14118             break;
14119           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14120             *obufp++ = 'b';
14121           break;
14122         case 'B':
14123           if (l == 0 && len == 1)
14124             {
14125 case_B:
14126               if (intel_syntax)
14127                 break;
14128               if (sizeflag & SUFFIX_ALWAYS)
14129                 *obufp++ = 'b';
14130             }
14131           else
14132             {
14133               if (l != 1
14134                   || len != 2
14135                   || last[0] != 'L')
14136                 {
14137                   SAVE_LAST (*p);
14138                   break;
14139                 }
14140
14141               if (address_mode == mode_64bit
14142                   && !(prefixes & PREFIX_ADDR))
14143                 {
14144                   *obufp++ = 'a';
14145                   *obufp++ = 'b';
14146                   *obufp++ = 's';
14147                 }
14148
14149               goto case_B;
14150             }
14151           break;
14152         case 'C':
14153           if (intel_syntax && !alt)
14154             break;
14155           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14156             {
14157               if (sizeflag & DFLAG)
14158                 *obufp++ = intel_syntax ? 'd' : 'l';
14159               else
14160                 *obufp++ = intel_syntax ? 'w' : 's';
14161               used_prefixes |= (prefixes & PREFIX_DATA);
14162             }
14163           break;
14164         case 'D':
14165           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14166             break;
14167           USED_REX (REX_W);
14168           if (modrm.mod == 3)
14169             {
14170               if (rex & REX_W)
14171                 *obufp++ = 'q';
14172               else
14173                 {
14174                   if (sizeflag & DFLAG)
14175                     *obufp++ = intel_syntax ? 'd' : 'l';
14176                   else
14177                     *obufp++ = 'w';
14178                   used_prefixes |= (prefixes & PREFIX_DATA);
14179                 }
14180             }
14181           else
14182             *obufp++ = 'w';
14183           break;
14184         case 'E':               /* For jcxz/jecxz */
14185           if (address_mode == mode_64bit)
14186             {
14187               if (sizeflag & AFLAG)
14188                 *obufp++ = 'r';
14189               else
14190                 *obufp++ = 'e';
14191             }
14192           else
14193             if (sizeflag & AFLAG)
14194               *obufp++ = 'e';
14195           used_prefixes |= (prefixes & PREFIX_ADDR);
14196           break;
14197         case 'F':
14198           if (intel_syntax)
14199             break;
14200           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14201             {
14202               if (sizeflag & AFLAG)
14203                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14204               else
14205                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14206               used_prefixes |= (prefixes & PREFIX_ADDR);
14207             }
14208           break;
14209         case 'G':
14210           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14211             break;
14212           if ((rex & REX_W) || (sizeflag & DFLAG))
14213             *obufp++ = 'l';
14214           else
14215             *obufp++ = 'w';
14216           if (!(rex & REX_W))
14217             used_prefixes |= (prefixes & PREFIX_DATA);
14218           break;
14219         case 'H':
14220           if (intel_syntax)
14221             break;
14222           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14223               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14224             {
14225               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14226               *obufp++ = ',';
14227               *obufp++ = 'p';
14228               if (prefixes & PREFIX_DS)
14229                 *obufp++ = 't';
14230               else
14231                 *obufp++ = 'n';
14232             }
14233           break;
14234         case 'J':
14235           if (intel_syntax)
14236             break;
14237           *obufp++ = 'l';
14238           break;
14239         case 'K':
14240           USED_REX (REX_W);
14241           if (rex & REX_W)
14242             *obufp++ = 'q';
14243           else
14244             *obufp++ = 'd';
14245           break;
14246         case 'Z':
14247           if (l != 0 || len != 1)
14248             {
14249               if (l != 1 || len != 2 || last[0] != 'X')
14250                 {
14251                   SAVE_LAST (*p);
14252                   break;
14253                 }
14254               if (!need_vex || !vex.evex)
14255                 abort ();
14256               if (intel_syntax
14257                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14258                 break;
14259               switch (vex.length)
14260                 {
14261                 case 128:
14262                   *obufp++ = 'x';
14263                   break;
14264                 case 256:
14265                   *obufp++ = 'y';
14266                   break;
14267                 case 512:
14268                   *obufp++ = 'z';
14269                   break;
14270                 default:
14271                   abort ();
14272                 }
14273               break;
14274             }
14275           if (intel_syntax)
14276             break;
14277           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14278             {
14279               *obufp++ = 'q';
14280               break;
14281             }
14282           /* Fall through.  */
14283           goto case_L;
14284         case 'L':
14285           if (l != 0 || len != 1)
14286             {
14287               SAVE_LAST (*p);
14288               break;
14289             }
14290 case_L:
14291           if (intel_syntax)
14292             break;
14293           if (sizeflag & SUFFIX_ALWAYS)
14294             *obufp++ = 'l';
14295           break;
14296         case 'M':
14297           if (intel_mnemonic != cond)
14298             *obufp++ = 'r';
14299           break;
14300         case 'N':
14301           if ((prefixes & PREFIX_FWAIT) == 0)
14302             *obufp++ = 'n';
14303           else
14304             used_prefixes |= PREFIX_FWAIT;
14305           break;
14306         case 'O':
14307           USED_REX (REX_W);
14308           if (rex & REX_W)
14309             *obufp++ = 'o';
14310           else if (intel_syntax && (sizeflag & DFLAG))
14311             *obufp++ = 'q';
14312           else
14313             *obufp++ = 'd';
14314           if (!(rex & REX_W))
14315             used_prefixes |= (prefixes & PREFIX_DATA);
14316           break;
14317         case '&':
14318           if (!intel_syntax
14319               && address_mode == mode_64bit
14320               && isa64 == intel64)
14321             {
14322               *obufp++ = 'q';
14323               break;
14324             }
14325           /* Fall through.  */
14326         case 'T':
14327           if (!intel_syntax
14328               && address_mode == mode_64bit
14329               && ((sizeflag & DFLAG) || (rex & REX_W)))
14330             {
14331               *obufp++ = 'q';
14332               break;
14333             }
14334           /* Fall through.  */
14335           goto case_P;
14336         case 'P':
14337           if (l == 0 && len == 1)
14338             {
14339 case_P:
14340               if (intel_syntax)
14341                 {
14342                   if ((rex & REX_W) == 0
14343                       && (prefixes & PREFIX_DATA))
14344                     {
14345                       if ((sizeflag & DFLAG) == 0)
14346                         *obufp++ = 'w';
14347                       used_prefixes |= (prefixes & PREFIX_DATA);
14348                     }
14349                   break;
14350                 }
14351               if ((prefixes & PREFIX_DATA)
14352                   || (rex & REX_W)
14353                   || (sizeflag & SUFFIX_ALWAYS))
14354                 {
14355                   USED_REX (REX_W);
14356                   if (rex & REX_W)
14357                     *obufp++ = 'q';
14358                   else
14359                     {
14360                       if (sizeflag & DFLAG)
14361                         *obufp++ = 'l';
14362                       else
14363                         *obufp++ = 'w';
14364                       used_prefixes |= (prefixes & PREFIX_DATA);
14365                     }
14366                 }
14367             }
14368           else
14369             {
14370               if (l != 1 || len != 2 || last[0] != 'L')
14371                 {
14372                   SAVE_LAST (*p);
14373                   break;
14374                 }
14375
14376               if ((prefixes & PREFIX_DATA)
14377                   || (rex & REX_W)
14378                   || (sizeflag & SUFFIX_ALWAYS))
14379                 {
14380                   USED_REX (REX_W);
14381                   if (rex & REX_W)
14382                     *obufp++ = 'q';
14383                   else
14384                     {
14385                       if (sizeflag & DFLAG)
14386                         *obufp++ = intel_syntax ? 'd' : 'l';
14387                       else
14388                         *obufp++ = 'w';
14389                       used_prefixes |= (prefixes & PREFIX_DATA);
14390                     }
14391                 }
14392             }
14393           break;
14394         case 'U':
14395           if (intel_syntax)
14396             break;
14397           if (address_mode == mode_64bit
14398               && ((sizeflag & DFLAG) || (rex & REX_W)))
14399             {
14400               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14401                 *obufp++ = 'q';
14402               break;
14403             }
14404           /* Fall through.  */
14405           goto case_Q;
14406         case 'Q':
14407           if (l == 0 && len == 1)
14408             {
14409 case_Q:
14410               if (intel_syntax && !alt)
14411                 break;
14412               USED_REX (REX_W);
14413               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14414                 {
14415                   if (rex & REX_W)
14416                     *obufp++ = 'q';
14417                   else
14418                     {
14419                       if (sizeflag & DFLAG)
14420                         *obufp++ = intel_syntax ? 'd' : 'l';
14421                       else
14422                         *obufp++ = 'w';
14423                       used_prefixes |= (prefixes & PREFIX_DATA);
14424                     }
14425                 }
14426             }
14427           else
14428             {
14429               if (l != 1 || len != 2 || last[0] != 'L')
14430                 {
14431                   SAVE_LAST (*p);
14432                   break;
14433                 }
14434               if (intel_syntax
14435                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14436                 break;
14437               if ((rex & REX_W))
14438                 {
14439                   USED_REX (REX_W);
14440                   *obufp++ = 'q';
14441                 }
14442               else
14443                 *obufp++ = 'l';
14444             }
14445           break;
14446         case 'R':
14447           USED_REX (REX_W);
14448           if (rex & REX_W)
14449             *obufp++ = 'q';
14450           else if (sizeflag & DFLAG)
14451             {
14452               if (intel_syntax)
14453                   *obufp++ = 'd';
14454               else
14455                   *obufp++ = 'l';
14456             }
14457           else
14458             *obufp++ = 'w';
14459           if (intel_syntax && !p[1]
14460               && ((rex & REX_W) || (sizeflag & DFLAG)))
14461             *obufp++ = 'e';
14462           if (!(rex & REX_W))
14463             used_prefixes |= (prefixes & PREFIX_DATA);
14464           break;
14465         case 'V':
14466           if (l == 0 && len == 1)
14467             {
14468               if (intel_syntax)
14469                 break;
14470               if (address_mode == mode_64bit
14471                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14472                 {
14473                   if (sizeflag & SUFFIX_ALWAYS)
14474                     *obufp++ = 'q';
14475                   break;
14476                 }
14477             }
14478           else
14479             {
14480               if (l != 1
14481                   || len != 2
14482                   || last[0] != 'L')
14483                 {
14484                   SAVE_LAST (*p);
14485                   break;
14486                 }
14487
14488               if (rex & REX_W)
14489                 {
14490                   *obufp++ = 'a';
14491                   *obufp++ = 'b';
14492                   *obufp++ = 's';
14493                 }
14494             }
14495           /* Fall through.  */
14496           goto case_S;
14497         case 'S':
14498           if (l == 0 && len == 1)
14499             {
14500 case_S:
14501               if (intel_syntax)
14502                 break;
14503               if (sizeflag & SUFFIX_ALWAYS)
14504                 {
14505                   if (rex & REX_W)
14506                     *obufp++ = 'q';
14507                   else
14508                     {
14509                       if (sizeflag & DFLAG)
14510                         *obufp++ = 'l';
14511                       else
14512                         *obufp++ = 'w';
14513                       used_prefixes |= (prefixes & PREFIX_DATA);
14514                     }
14515                 }
14516             }
14517           else
14518             {
14519               if (l != 1
14520                   || len != 2
14521                   || last[0] != 'L')
14522                 {
14523                   SAVE_LAST (*p);
14524                   break;
14525                 }
14526
14527               if (address_mode == mode_64bit
14528                   && !(prefixes & PREFIX_ADDR))
14529                 {
14530                   *obufp++ = 'a';
14531                   *obufp++ = 'b';
14532                   *obufp++ = 's';
14533                 }
14534
14535               goto case_S;
14536             }
14537           break;
14538         case 'X':
14539           if (l != 0 || len != 1)
14540             {
14541               SAVE_LAST (*p);
14542               break;
14543             }
14544           if (need_vex && vex.prefix)
14545             {
14546               if (vex.prefix == DATA_PREFIX_OPCODE)
14547                 *obufp++ = 'd';
14548               else
14549                 *obufp++ = 's';
14550             }
14551           else
14552             {
14553               if (prefixes & PREFIX_DATA)
14554                 *obufp++ = 'd';
14555               else
14556                 *obufp++ = 's';
14557               used_prefixes |= (prefixes & PREFIX_DATA);
14558             }
14559           break;
14560         case 'Y':
14561           if (l == 0 && len == 1)
14562             {
14563               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14564                 break;
14565               if (rex & REX_W)
14566                 {
14567                   USED_REX (REX_W);
14568                   *obufp++ = 'q';
14569                 }
14570               break;
14571             }
14572           else
14573             {
14574               if (l != 1 || len != 2 || last[0] != 'X')
14575                 {
14576                   SAVE_LAST (*p);
14577                   break;
14578                 }
14579               if (!need_vex)
14580                 abort ();
14581               if (intel_syntax
14582                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14583                 break;
14584               switch (vex.length)
14585                 {
14586                 case 128:
14587                   *obufp++ = 'x';
14588                   break;
14589                 case 256:
14590                   *obufp++ = 'y';
14591                   break;
14592                 case 512:
14593                   if (!vex.evex)
14594                 default:
14595                     abort ();
14596                 }
14597             }
14598           break;
14599         case 'W':
14600           if (l == 0 && len == 1)
14601             {
14602               /* operand size flag for cwtl, cbtw */
14603               USED_REX (REX_W);
14604               if (rex & REX_W)
14605                 {
14606                   if (intel_syntax)
14607                     *obufp++ = 'd';
14608                   else
14609                     *obufp++ = 'l';
14610                 }
14611               else if (sizeflag & DFLAG)
14612                 *obufp++ = 'w';
14613               else
14614                 *obufp++ = 'b';
14615               if (!(rex & REX_W))
14616                 used_prefixes |= (prefixes & PREFIX_DATA);
14617             }
14618           else
14619             {
14620               if (l != 1
14621                   || len != 2
14622                   || (last[0] != 'X'
14623                       && last[0] != 'L'))
14624                 {
14625                   SAVE_LAST (*p);
14626                   break;
14627                 }
14628               if (!need_vex)
14629                 abort ();
14630               if (last[0] == 'X')
14631                 *obufp++ = vex.w ? 'd': 's';
14632               else
14633                 *obufp++ = vex.w ? 'q': 'd';
14634             }
14635           break;
14636         case '^':
14637           if (intel_syntax)
14638             break;
14639           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14640             {
14641               if (sizeflag & DFLAG)
14642                 *obufp++ = 'l';
14643               else
14644                 *obufp++ = 'w';
14645               used_prefixes |= (prefixes & PREFIX_DATA);
14646             }
14647           break;
14648         case '@':
14649           if (intel_syntax)
14650             break;
14651           if (address_mode == mode_64bit
14652               && (isa64 == intel64
14653                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14654               *obufp++ = 'q';
14655           else if ((prefixes & PREFIX_DATA))
14656             {
14657               if (!(sizeflag & DFLAG))
14658                 *obufp++ = 'w';
14659               used_prefixes |= (prefixes & PREFIX_DATA);
14660             }
14661           break;
14662         }
14663       alt = 0;
14664     }
14665   *obufp = 0;
14666   mnemonicendp = obufp;
14667   return 0;
14668 }
14669
14670 static void
14671 oappend (const char *s)
14672 {
14673   obufp = stpcpy (obufp, s);
14674 }
14675
14676 static void
14677 append_seg (void)
14678 {
14679   /* Only print the active segment register.  */
14680   if (!active_seg_prefix)
14681     return;
14682
14683   used_prefixes |= active_seg_prefix;
14684   switch (active_seg_prefix)
14685     {
14686     case PREFIX_CS:
14687       oappend_maybe_intel ("%cs:");
14688       break;
14689     case PREFIX_DS:
14690       oappend_maybe_intel ("%ds:");
14691       break;
14692     case PREFIX_SS:
14693       oappend_maybe_intel ("%ss:");
14694       break;
14695     case PREFIX_ES:
14696       oappend_maybe_intel ("%es:");
14697       break;
14698     case PREFIX_FS:
14699       oappend_maybe_intel ("%fs:");
14700       break;
14701     case PREFIX_GS:
14702       oappend_maybe_intel ("%gs:");
14703       break;
14704     default:
14705       break;
14706     }
14707 }
14708
14709 static void
14710 OP_indirE (int bytemode, int sizeflag)
14711 {
14712   if (!intel_syntax)
14713     oappend ("*");
14714   OP_E (bytemode, sizeflag);
14715 }
14716
14717 static void
14718 print_operand_value (char *buf, int hex, bfd_vma disp)
14719 {
14720   if (address_mode == mode_64bit)
14721     {
14722       if (hex)
14723         {
14724           char tmp[30];
14725           int i;
14726           buf[0] = '0';
14727           buf[1] = 'x';
14728           sprintf_vma (tmp, disp);
14729           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14730           strcpy (buf + 2, tmp + i);
14731         }
14732       else
14733         {
14734           bfd_signed_vma v = disp;
14735           char tmp[30];
14736           int i;
14737           if (v < 0)
14738             {
14739               *(buf++) = '-';
14740               v = -disp;
14741               /* Check for possible overflow on 0x8000000000000000.  */
14742               if (v < 0)
14743                 {
14744                   strcpy (buf, "9223372036854775808");
14745                   return;
14746                 }
14747             }
14748           if (!v)
14749             {
14750               strcpy (buf, "0");
14751               return;
14752             }
14753
14754           i = 0;
14755           tmp[29] = 0;
14756           while (v)
14757             {
14758               tmp[28 - i] = (v % 10) + '0';
14759               v /= 10;
14760               i++;
14761             }
14762           strcpy (buf, tmp + 29 - i);
14763         }
14764     }
14765   else
14766     {
14767       if (hex)
14768         sprintf (buf, "0x%x", (unsigned int) disp);
14769       else
14770         sprintf (buf, "%d", (int) disp);
14771     }
14772 }
14773
14774 /* Put DISP in BUF as signed hex number.  */
14775
14776 static void
14777 print_displacement (char *buf, bfd_vma disp)
14778 {
14779   bfd_signed_vma val = disp;
14780   char tmp[30];
14781   int i, j = 0;
14782
14783   if (val < 0)
14784     {
14785       buf[j++] = '-';
14786       val = -disp;
14787
14788       /* Check for possible overflow.  */
14789       if (val < 0)
14790         {
14791           switch (address_mode)
14792             {
14793             case mode_64bit:
14794               strcpy (buf + j, "0x8000000000000000");
14795               break;
14796             case mode_32bit:
14797               strcpy (buf + j, "0x80000000");
14798               break;
14799             case mode_16bit:
14800               strcpy (buf + j, "0x8000");
14801               break;
14802             }
14803           return;
14804         }
14805     }
14806
14807   buf[j++] = '0';
14808   buf[j++] = 'x';
14809
14810   sprintf_vma (tmp, (bfd_vma) val);
14811   for (i = 0; tmp[i] == '0'; i++)
14812     continue;
14813   if (tmp[i] == '\0')
14814     i--;
14815   strcpy (buf + j, tmp + i);
14816 }
14817
14818 static void
14819 intel_operand_size (int bytemode, int sizeflag)
14820 {
14821   if (vex.evex
14822       && vex.b
14823       && (bytemode == x_mode
14824           || bytemode == evex_half_bcst_xmmq_mode))
14825     {
14826       if (vex.w)
14827         oappend ("QWORD PTR ");
14828       else
14829         oappend ("DWORD PTR ");
14830       return;
14831     }
14832   switch (bytemode)
14833     {
14834     case b_mode:
14835     case b_swap_mode:
14836     case dqb_mode:
14837     case db_mode:
14838       oappend ("BYTE PTR ");
14839       break;
14840     case w_mode:
14841     case dw_mode:
14842     case dqw_mode:
14843     case dqw_swap_mode:
14844       oappend ("WORD PTR ");
14845       break;
14846     case indir_v_mode:
14847       if (address_mode == mode_64bit && isa64 == intel64)
14848         {
14849           oappend ("QWORD PTR ");
14850           break;
14851         }
14852       /* Fall through.  */
14853     case stack_v_mode:
14854       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14855         {
14856           oappend ("QWORD PTR ");
14857           break;
14858         }
14859       /* Fall through.  */
14860     case v_mode:
14861     case v_swap_mode:
14862     case dq_mode:
14863       USED_REX (REX_W);
14864       if (rex & REX_W)
14865         oappend ("QWORD PTR ");
14866       else
14867         {
14868           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14869             oappend ("DWORD PTR ");
14870           else
14871             oappend ("WORD PTR ");
14872           used_prefixes |= (prefixes & PREFIX_DATA);
14873         }
14874       break;
14875     case z_mode:
14876       if ((rex & REX_W) || (sizeflag & DFLAG))
14877         *obufp++ = 'D';
14878       oappend ("WORD PTR ");
14879       if (!(rex & REX_W))
14880         used_prefixes |= (prefixes & PREFIX_DATA);
14881       break;
14882     case a_mode:
14883       if (sizeflag & DFLAG)
14884         oappend ("QWORD PTR ");
14885       else
14886         oappend ("DWORD PTR ");
14887       used_prefixes |= (prefixes & PREFIX_DATA);
14888       break;
14889     case d_mode:
14890     case d_scalar_mode:
14891     case d_scalar_swap_mode:
14892     case d_swap_mode:
14893     case dqd_mode:
14894       oappend ("DWORD PTR ");
14895       break;
14896     case q_mode:
14897     case q_scalar_mode:
14898     case q_scalar_swap_mode:
14899     case q_swap_mode:
14900       oappend ("QWORD PTR ");
14901       break;
14902     case m_mode:
14903       if (address_mode == mode_64bit)
14904         oappend ("QWORD PTR ");
14905       else
14906         oappend ("DWORD PTR ");
14907       break;
14908     case f_mode:
14909       if (sizeflag & DFLAG)
14910         oappend ("FWORD PTR ");
14911       else
14912         oappend ("DWORD PTR ");
14913       used_prefixes |= (prefixes & PREFIX_DATA);
14914       break;
14915     case t_mode:
14916       oappend ("TBYTE PTR ");
14917       break;
14918     case x_mode:
14919     case x_swap_mode:
14920     case evex_x_gscat_mode:
14921     case evex_x_nobcst_mode:
14922       if (need_vex)
14923         {
14924           switch (vex.length)
14925             {
14926             case 128:
14927               oappend ("XMMWORD PTR ");
14928               break;
14929             case 256:
14930               oappend ("YMMWORD PTR ");
14931               break;
14932             case 512:
14933               oappend ("ZMMWORD PTR ");
14934               break;
14935             default:
14936               abort ();
14937             }
14938         }
14939       else
14940         oappend ("XMMWORD PTR ");
14941       break;
14942     case xmm_mode:
14943       oappend ("XMMWORD PTR ");
14944       break;
14945     case ymm_mode:
14946       oappend ("YMMWORD PTR ");
14947       break;
14948     case xmmq_mode:
14949     case evex_half_bcst_xmmq_mode:
14950       if (!need_vex)
14951         abort ();
14952
14953       switch (vex.length)
14954         {
14955         case 128:
14956           oappend ("QWORD PTR ");
14957           break;
14958         case 256:
14959           oappend ("XMMWORD PTR ");
14960           break;
14961         case 512:
14962           oappend ("YMMWORD PTR ");
14963           break;
14964         default:
14965           abort ();
14966         }
14967       break;
14968     case xmm_mb_mode:
14969       if (!need_vex)
14970         abort ();
14971
14972       switch (vex.length)
14973         {
14974         case 128:
14975         case 256:
14976         case 512:
14977           oappend ("BYTE PTR ");
14978           break;
14979         default:
14980           abort ();
14981         }
14982       break;
14983     case xmm_mw_mode:
14984       if (!need_vex)
14985         abort ();
14986
14987       switch (vex.length)
14988         {
14989         case 128:
14990         case 256:
14991         case 512:
14992           oappend ("WORD PTR ");
14993           break;
14994         default:
14995           abort ();
14996         }
14997       break;
14998     case xmm_md_mode:
14999       if (!need_vex)
15000         abort ();
15001
15002       switch (vex.length)
15003         {
15004         case 128:
15005         case 256:
15006         case 512:
15007           oappend ("DWORD PTR ");
15008           break;
15009         default:
15010           abort ();
15011         }
15012       break;
15013     case xmm_mq_mode:
15014       if (!need_vex)
15015         abort ();
15016
15017       switch (vex.length)
15018         {
15019         case 128:
15020         case 256:
15021         case 512:
15022           oappend ("QWORD PTR ");
15023           break;
15024         default:
15025           abort ();
15026         }
15027       break;
15028     case xmmdw_mode:
15029       if (!need_vex)
15030         abort ();
15031
15032       switch (vex.length)
15033         {
15034         case 128:
15035           oappend ("WORD PTR ");
15036           break;
15037         case 256:
15038           oappend ("DWORD PTR ");
15039           break;
15040         case 512:
15041           oappend ("QWORD PTR ");
15042           break;
15043         default:
15044           abort ();
15045         }
15046       break;
15047     case xmmqd_mode:
15048       if (!need_vex)
15049         abort ();
15050
15051       switch (vex.length)
15052         {
15053         case 128:
15054           oappend ("DWORD PTR ");
15055           break;
15056         case 256:
15057           oappend ("QWORD PTR ");
15058           break;
15059         case 512:
15060           oappend ("XMMWORD PTR ");
15061           break;
15062         default:
15063           abort ();
15064         }
15065       break;
15066     case ymmq_mode:
15067       if (!need_vex)
15068         abort ();
15069
15070       switch (vex.length)
15071         {
15072         case 128:
15073           oappend ("QWORD PTR ");
15074           break;
15075         case 256:
15076           oappend ("YMMWORD PTR ");
15077           break;
15078         case 512:
15079           oappend ("ZMMWORD PTR ");
15080           break;
15081         default:
15082           abort ();
15083         }
15084       break;
15085     case ymmxmm_mode:
15086       if (!need_vex)
15087         abort ();
15088
15089       switch (vex.length)
15090         {
15091         case 128:
15092         case 256:
15093           oappend ("XMMWORD PTR ");
15094           break;
15095         default:
15096           abort ();
15097         }
15098       break;
15099     case o_mode:
15100       oappend ("OWORD PTR ");
15101       break;
15102     case xmm_mdq_mode:
15103     case vex_w_dq_mode:
15104     case vex_scalar_w_dq_mode:
15105       if (!need_vex)
15106         abort ();
15107
15108       if (vex.w)
15109         oappend ("QWORD PTR ");
15110       else
15111         oappend ("DWORD PTR ");
15112       break;
15113     case vex_vsib_d_w_dq_mode:
15114     case vex_vsib_q_w_dq_mode:
15115       if (!need_vex)
15116         abort ();
15117
15118       if (!vex.evex)
15119         {
15120           if (vex.w)
15121             oappend ("QWORD PTR ");
15122           else
15123             oappend ("DWORD PTR ");
15124         }
15125       else
15126         {
15127           switch (vex.length)
15128             {
15129             case 128:
15130               oappend ("XMMWORD PTR ");
15131               break;
15132             case 256:
15133               oappend ("YMMWORD PTR ");
15134               break;
15135             case 512:
15136               oappend ("ZMMWORD PTR ");
15137               break;
15138             default:
15139               abort ();
15140             }
15141         }
15142       break;
15143     case vex_vsib_q_w_d_mode:
15144     case vex_vsib_d_w_d_mode:
15145       if (!need_vex || !vex.evex)
15146         abort ();
15147
15148       switch (vex.length)
15149         {
15150         case 128:
15151           oappend ("QWORD PTR ");
15152           break;
15153         case 256:
15154           oappend ("XMMWORD PTR ");
15155           break;
15156         case 512:
15157           oappend ("YMMWORD PTR ");
15158           break;
15159         default:
15160           abort ();
15161         }
15162
15163       break;
15164     case mask_bd_mode:
15165       if (!need_vex || vex.length != 128)
15166         abort ();
15167       if (vex.w)
15168         oappend ("DWORD PTR ");
15169       else
15170         oappend ("BYTE PTR ");
15171       break;
15172     case mask_mode:
15173       if (!need_vex)
15174         abort ();
15175       if (vex.w)
15176         oappend ("QWORD PTR ");
15177       else
15178         oappend ("WORD PTR ");
15179       break;
15180     case v_bnd_mode:
15181     default:
15182       break;
15183     }
15184 }
15185
15186 static void
15187 OP_E_register (int bytemode, int sizeflag)
15188 {
15189   int reg = modrm.rm;
15190   const char **names;
15191
15192   USED_REX (REX_B);
15193   if ((rex & REX_B))
15194     reg += 8;
15195
15196   if ((sizeflag & SUFFIX_ALWAYS)
15197       && (bytemode == b_swap_mode
15198           || bytemode == v_swap_mode
15199           || bytemode == dqw_swap_mode))
15200     swap_operand ();
15201
15202   switch (bytemode)
15203     {
15204     case b_mode:
15205     case b_swap_mode:
15206       USED_REX (0);
15207       if (rex)
15208         names = names8rex;
15209       else
15210         names = names8;
15211       break;
15212     case w_mode:
15213       names = names16;
15214       break;
15215     case d_mode:
15216     case dw_mode:
15217     case db_mode:
15218       names = names32;
15219       break;
15220     case q_mode:
15221       names = names64;
15222       break;
15223     case m_mode:
15224     case v_bnd_mode:
15225       names = address_mode == mode_64bit ? names64 : names32;
15226       break;
15227     case bnd_mode:
15228       names = names_bnd;
15229       break;
15230     case indir_v_mode:
15231       if (address_mode == mode_64bit && isa64 == intel64)
15232         {
15233           names = names64;
15234           break;
15235         }
15236       /* Fall through.  */
15237     case stack_v_mode:
15238       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15239         {
15240           names = names64;
15241           break;
15242         }
15243       bytemode = v_mode;
15244       /* Fall through.  */
15245     case v_mode:
15246     case v_swap_mode:
15247     case dq_mode:
15248     case dqb_mode:
15249     case dqd_mode:
15250     case dqw_mode:
15251     case dqw_swap_mode:
15252       USED_REX (REX_W);
15253       if (rex & REX_W)
15254         names = names64;
15255       else
15256         {
15257           if ((sizeflag & DFLAG)
15258               || (bytemode != v_mode
15259                   && bytemode != v_swap_mode))
15260             names = names32;
15261           else
15262             names = names16;
15263           used_prefixes |= (prefixes & PREFIX_DATA);
15264         }
15265       break;
15266     case mask_bd_mode:
15267     case mask_mode:
15268       if (reg > 0x7)
15269         {
15270           oappend ("(bad)");
15271           return;
15272         }
15273       names = names_mask;
15274       break;
15275     case 0:
15276       return;
15277     default:
15278       oappend (INTERNAL_DISASSEMBLER_ERROR);
15279       return;
15280     }
15281   oappend (names[reg]);
15282 }
15283
15284 static void
15285 OP_E_memory (int bytemode, int sizeflag)
15286 {
15287   bfd_vma disp = 0;
15288   int add = (rex & REX_B) ? 8 : 0;
15289   int riprel = 0;
15290   int shift;
15291
15292   if (vex.evex)
15293     {
15294       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15295       if (vex.b
15296           && bytemode != x_mode
15297           && bytemode != xmmq_mode
15298           && bytemode != evex_half_bcst_xmmq_mode)
15299         {
15300           BadOp ();
15301           return;
15302         }
15303       switch (bytemode)
15304         {
15305         case dqw_mode:
15306         case dw_mode:
15307         case dqw_swap_mode:
15308           shift = 1;
15309           break;
15310         case dqb_mode:
15311         case db_mode:
15312           shift = 0;
15313           break;
15314         case vex_vsib_d_w_dq_mode:
15315         case vex_vsib_d_w_d_mode:
15316         case vex_vsib_q_w_dq_mode:
15317         case vex_vsib_q_w_d_mode:
15318         case evex_x_gscat_mode:
15319         case xmm_mdq_mode:
15320           shift = vex.w ? 3 : 2;
15321           break;
15322         case x_mode:
15323         case evex_half_bcst_xmmq_mode:
15324         case xmmq_mode:
15325           if (vex.b)
15326             {
15327               shift = vex.w ? 3 : 2;
15328               break;
15329             }
15330           /* Fall through.  */
15331         case xmmqd_mode:
15332         case xmmdw_mode:
15333         case ymmq_mode:
15334         case evex_x_nobcst_mode:
15335         case x_swap_mode:
15336           switch (vex.length)
15337             {
15338             case 128:
15339               shift = 4;
15340               break;
15341             case 256:
15342               shift = 5;
15343               break;
15344             case 512:
15345               shift = 6;
15346               break;
15347             default:
15348               abort ();
15349             }
15350           break;
15351         case ymm_mode:
15352           shift = 5;
15353           break;
15354         case xmm_mode:
15355           shift = 4;
15356           break;
15357         case xmm_mq_mode:
15358         case q_mode:
15359         case q_scalar_mode:
15360         case q_swap_mode:
15361         case q_scalar_swap_mode:
15362           shift = 3;
15363           break;
15364         case dqd_mode:
15365         case xmm_md_mode:
15366         case d_mode:
15367         case d_scalar_mode:
15368         case d_swap_mode:
15369         case d_scalar_swap_mode:
15370           shift = 2;
15371           break;
15372         case xmm_mw_mode:
15373           shift = 1;
15374           break;
15375         case xmm_mb_mode:
15376           shift = 0;
15377           break;
15378         default:
15379           abort ();
15380         }
15381       /* Make necessary corrections to shift for modes that need it.
15382          For these modes we currently have shift 4, 5 or 6 depending on
15383          vex.length (it corresponds to xmmword, ymmword or zmmword
15384          operand).  We might want to make it 3, 4 or 5 (e.g. for
15385          xmmq_mode).  In case of broadcast enabled the corrections
15386          aren't needed, as element size is always 32 or 64 bits.  */
15387       if (!vex.b
15388           && (bytemode == xmmq_mode
15389               || bytemode == evex_half_bcst_xmmq_mode))
15390         shift -= 1;
15391       else if (bytemode == xmmqd_mode)
15392         shift -= 2;
15393       else if (bytemode == xmmdw_mode)
15394         shift -= 3;
15395       else if (bytemode == ymmq_mode && vex.length == 128)
15396         shift -= 1;
15397     }
15398   else
15399     shift = 0;
15400
15401   USED_REX (REX_B);
15402   if (intel_syntax)
15403     intel_operand_size (bytemode, sizeflag);
15404   append_seg ();
15405
15406   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15407     {
15408       /* 32/64 bit address mode */
15409       int havedisp;
15410       int havesib;
15411       int havebase;
15412       int haveindex;
15413       int needindex;
15414       int base, rbase;
15415       int vindex = 0;
15416       int scale = 0;
15417       int addr32flag = !((sizeflag & AFLAG)
15418                          || bytemode == v_bnd_mode
15419                          || bytemode == bnd_mode);
15420       const char **indexes64 = names64;
15421       const char **indexes32 = names32;
15422
15423       havesib = 0;
15424       havebase = 1;
15425       haveindex = 0;
15426       base = modrm.rm;
15427
15428       if (base == 4)
15429         {
15430           havesib = 1;
15431           vindex = sib.index;
15432           USED_REX (REX_X);
15433           if (rex & REX_X)
15434             vindex += 8;
15435           switch (bytemode)
15436             {
15437             case vex_vsib_d_w_dq_mode:
15438             case vex_vsib_d_w_d_mode:
15439             case vex_vsib_q_w_dq_mode:
15440             case vex_vsib_q_w_d_mode:
15441               if (!need_vex)
15442                 abort ();
15443               if (vex.evex)
15444                 {
15445                   if (!vex.v)
15446                     vindex += 16;
15447                 }
15448
15449               haveindex = 1;
15450               switch (vex.length)
15451                 {
15452                 case 128:
15453                   indexes64 = indexes32 = names_xmm;
15454                   break;
15455                 case 256:
15456                   if (!vex.w
15457                       || bytemode == vex_vsib_q_w_dq_mode
15458                       || bytemode == vex_vsib_q_w_d_mode)
15459                     indexes64 = indexes32 = names_ymm;
15460                   else
15461                     indexes64 = indexes32 = names_xmm;
15462                   break;
15463                 case 512:
15464                   if (!vex.w
15465                       || bytemode == vex_vsib_q_w_dq_mode
15466                       || bytemode == vex_vsib_q_w_d_mode)
15467                     indexes64 = indexes32 = names_zmm;
15468                   else
15469                     indexes64 = indexes32 = names_ymm;
15470                   break;
15471                 default:
15472                   abort ();
15473                 }
15474               break;
15475             default:
15476               haveindex = vindex != 4;
15477               break;
15478             }
15479           scale = sib.scale;
15480           base = sib.base;
15481           codep++;
15482         }
15483       rbase = base + add;
15484
15485       switch (modrm.mod)
15486         {
15487         case 0:
15488           if (base == 5)
15489             {
15490               havebase = 0;
15491               if (address_mode == mode_64bit && !havesib)
15492                 riprel = 1;
15493               disp = get32s ();
15494             }
15495           break;
15496         case 1:
15497           FETCH_DATA (the_info, codep + 1);
15498           disp = *codep++;
15499           if ((disp & 0x80) != 0)
15500             disp -= 0x100;
15501           if (vex.evex && shift > 0)
15502             disp <<= shift;
15503           break;
15504         case 2:
15505           disp = get32s ();
15506           break;
15507         }
15508
15509       /* In 32bit mode, we need index register to tell [offset] from
15510          [eiz*1 + offset].  */
15511       needindex = (havesib
15512                    && !havebase
15513                    && !haveindex
15514                    && address_mode == mode_32bit);
15515       havedisp = (havebase
15516                   || needindex
15517                   || (havesib && (haveindex || scale != 0)));
15518
15519       if (!intel_syntax)
15520         if (modrm.mod != 0 || base == 5)
15521           {
15522             if (havedisp || riprel)
15523               print_displacement (scratchbuf, disp);
15524             else
15525               print_operand_value (scratchbuf, 1, disp);
15526             oappend (scratchbuf);
15527             if (riprel)
15528               {
15529                 set_op (disp, 1);
15530                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15531               }
15532           }
15533
15534       if ((havebase || haveindex || riprel)
15535           && (bytemode != v_bnd_mode)
15536           && (bytemode != bnd_mode))
15537         used_prefixes |= PREFIX_ADDR;
15538
15539       if (havedisp || (intel_syntax && riprel))
15540         {
15541           *obufp++ = open_char;
15542           if (intel_syntax && riprel)
15543             {
15544               set_op (disp, 1);
15545               oappend (!addr32flag ? "rip" : "eip");
15546             }
15547           *obufp = '\0';
15548           if (havebase)
15549             oappend (address_mode == mode_64bit && !addr32flag
15550                      ? names64[rbase] : names32[rbase]);
15551           if (havesib)
15552             {
15553               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15554                  print index to tell base + index from base.  */
15555               if (scale != 0
15556                   || needindex
15557                   || haveindex
15558                   || (havebase && base != ESP_REG_NUM))
15559                 {
15560                   if (!intel_syntax || havebase)
15561                     {
15562                       *obufp++ = separator_char;
15563                       *obufp = '\0';
15564                     }
15565                   if (haveindex)
15566                     oappend (address_mode == mode_64bit && !addr32flag
15567                              ? indexes64[vindex] : indexes32[vindex]);
15568                   else
15569                     oappend (address_mode == mode_64bit && !addr32flag
15570                              ? index64 : index32);
15571
15572                   *obufp++ = scale_char;
15573                   *obufp = '\0';
15574                   sprintf (scratchbuf, "%d", 1 << scale);
15575                   oappend (scratchbuf);
15576                 }
15577             }
15578           if (intel_syntax
15579               && (disp || modrm.mod != 0 || base == 5))
15580             {
15581               if (!havedisp || (bfd_signed_vma) disp >= 0)
15582                 {
15583                   *obufp++ = '+';
15584                   *obufp = '\0';
15585                 }
15586               else if (modrm.mod != 1 && disp != -disp)
15587                 {
15588                   *obufp++ = '-';
15589                   *obufp = '\0';
15590                   disp = - (bfd_signed_vma) disp;
15591                 }
15592
15593               if (havedisp)
15594                 print_displacement (scratchbuf, disp);
15595               else
15596                 print_operand_value (scratchbuf, 1, disp);
15597               oappend (scratchbuf);
15598             }
15599
15600           *obufp++ = close_char;
15601           *obufp = '\0';
15602         }
15603       else if (intel_syntax)
15604         {
15605           if (modrm.mod != 0 || base == 5)
15606             {
15607               if (!active_seg_prefix)
15608                 {
15609                   oappend (names_seg[ds_reg - es_reg]);
15610                   oappend (":");
15611                 }
15612               print_operand_value (scratchbuf, 1, disp);
15613               oappend (scratchbuf);
15614             }
15615         }
15616     }
15617   else
15618     {
15619       /* 16 bit address mode */
15620       used_prefixes |= prefixes & PREFIX_ADDR;
15621       switch (modrm.mod)
15622         {
15623         case 0:
15624           if (modrm.rm == 6)
15625             {
15626               disp = get16 ();
15627               if ((disp & 0x8000) != 0)
15628                 disp -= 0x10000;
15629             }
15630           break;
15631         case 1:
15632           FETCH_DATA (the_info, codep + 1);
15633           disp = *codep++;
15634           if ((disp & 0x80) != 0)
15635             disp -= 0x100;
15636           break;
15637         case 2:
15638           disp = get16 ();
15639           if ((disp & 0x8000) != 0)
15640             disp -= 0x10000;
15641           break;
15642         }
15643
15644       if (!intel_syntax)
15645         if (modrm.mod != 0 || modrm.rm == 6)
15646           {
15647             print_displacement (scratchbuf, disp);
15648             oappend (scratchbuf);
15649           }
15650
15651       if (modrm.mod != 0 || modrm.rm != 6)
15652         {
15653           *obufp++ = open_char;
15654           *obufp = '\0';
15655           oappend (index16[modrm.rm]);
15656           if (intel_syntax
15657               && (disp || modrm.mod != 0 || modrm.rm == 6))
15658             {
15659               if ((bfd_signed_vma) disp >= 0)
15660                 {
15661                   *obufp++ = '+';
15662                   *obufp = '\0';
15663                 }
15664               else if (modrm.mod != 1)
15665                 {
15666                   *obufp++ = '-';
15667                   *obufp = '\0';
15668                   disp = - (bfd_signed_vma) disp;
15669                 }
15670
15671               print_displacement (scratchbuf, disp);
15672               oappend (scratchbuf);
15673             }
15674
15675           *obufp++ = close_char;
15676           *obufp = '\0';
15677         }
15678       else if (intel_syntax)
15679         {
15680           if (!active_seg_prefix)
15681             {
15682               oappend (names_seg[ds_reg - es_reg]);
15683               oappend (":");
15684             }
15685           print_operand_value (scratchbuf, 1, disp & 0xffff);
15686           oappend (scratchbuf);
15687         }
15688     }
15689   if (vex.evex && vex.b
15690       && (bytemode == x_mode
15691           || bytemode == xmmq_mode
15692           || bytemode == evex_half_bcst_xmmq_mode))
15693     {
15694       if (vex.w
15695           || bytemode == xmmq_mode
15696           || bytemode == evex_half_bcst_xmmq_mode)
15697         {
15698           switch (vex.length)
15699             {
15700             case 128:
15701               oappend ("{1to2}");
15702               break;
15703             case 256:
15704               oappend ("{1to4}");
15705               break;
15706             case 512:
15707               oappend ("{1to8}");
15708               break;
15709             default:
15710               abort ();
15711             }
15712         }
15713       else
15714         {
15715           switch (vex.length)
15716             {
15717             case 128:
15718               oappend ("{1to4}");
15719               break;
15720             case 256:
15721               oappend ("{1to8}");
15722               break;
15723             case 512:
15724               oappend ("{1to16}");
15725               break;
15726             default:
15727               abort ();
15728             }
15729         }
15730     }
15731 }
15732
15733 static void
15734 OP_E (int bytemode, int sizeflag)
15735 {
15736   /* Skip mod/rm byte.  */
15737   MODRM_CHECK;
15738   codep++;
15739
15740   if (modrm.mod == 3)
15741     OP_E_register (bytemode, sizeflag);
15742   else
15743     OP_E_memory (bytemode, sizeflag);
15744 }
15745
15746 static void
15747 OP_G (int bytemode, int sizeflag)
15748 {
15749   int add = 0;
15750   USED_REX (REX_R);
15751   if (rex & REX_R)
15752     add += 8;
15753   switch (bytemode)
15754     {
15755     case b_mode:
15756       USED_REX (0);
15757       if (rex)
15758         oappend (names8rex[modrm.reg + add]);
15759       else
15760         oappend (names8[modrm.reg + add]);
15761       break;
15762     case w_mode:
15763       oappend (names16[modrm.reg + add]);
15764       break;
15765     case d_mode:
15766     case db_mode:
15767     case dw_mode:
15768       oappend (names32[modrm.reg + add]);
15769       break;
15770     case q_mode:
15771       oappend (names64[modrm.reg + add]);
15772       break;
15773     case bnd_mode:
15774       oappend (names_bnd[modrm.reg]);
15775       break;
15776     case v_mode:
15777     case dq_mode:
15778     case dqb_mode:
15779     case dqd_mode:
15780     case dqw_mode:
15781     case dqw_swap_mode:
15782       USED_REX (REX_W);
15783       if (rex & REX_W)
15784         oappend (names64[modrm.reg + add]);
15785       else
15786         {
15787           if ((sizeflag & DFLAG) || bytemode != v_mode)
15788             oappend (names32[modrm.reg + add]);
15789           else
15790             oappend (names16[modrm.reg + add]);
15791           used_prefixes |= (prefixes & PREFIX_DATA);
15792         }
15793       break;
15794     case m_mode:
15795       if (address_mode == mode_64bit)
15796         oappend (names64[modrm.reg + add]);
15797       else
15798         oappend (names32[modrm.reg + add]);
15799       break;
15800     case mask_bd_mode:
15801     case mask_mode:
15802       if ((modrm.reg + add) > 0x7)
15803         {
15804           oappend ("(bad)");
15805           return;
15806         }
15807       oappend (names_mask[modrm.reg + add]);
15808       break;
15809     default:
15810       oappend (INTERNAL_DISASSEMBLER_ERROR);
15811       break;
15812     }
15813 }
15814
15815 static bfd_vma
15816 get64 (void)
15817 {
15818   bfd_vma x;
15819 #ifdef BFD64
15820   unsigned int a;
15821   unsigned int b;
15822
15823   FETCH_DATA (the_info, codep + 8);
15824   a = *codep++ & 0xff;
15825   a |= (*codep++ & 0xff) << 8;
15826   a |= (*codep++ & 0xff) << 16;
15827   a |= (*codep++ & 0xffu) << 24;
15828   b = *codep++ & 0xff;
15829   b |= (*codep++ & 0xff) << 8;
15830   b |= (*codep++ & 0xff) << 16;
15831   b |= (*codep++ & 0xffu) << 24;
15832   x = a + ((bfd_vma) b << 32);
15833 #else
15834   abort ();
15835   x = 0;
15836 #endif
15837   return x;
15838 }
15839
15840 static bfd_signed_vma
15841 get32 (void)
15842 {
15843   bfd_signed_vma x = 0;
15844
15845   FETCH_DATA (the_info, codep + 4);
15846   x = *codep++ & (bfd_signed_vma) 0xff;
15847   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15848   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15849   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15850   return x;
15851 }
15852
15853 static bfd_signed_vma
15854 get32s (void)
15855 {
15856   bfd_signed_vma x = 0;
15857
15858   FETCH_DATA (the_info, codep + 4);
15859   x = *codep++ & (bfd_signed_vma) 0xff;
15860   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15861   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15862   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15863
15864   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15865
15866   return x;
15867 }
15868
15869 static int
15870 get16 (void)
15871 {
15872   int x = 0;
15873
15874   FETCH_DATA (the_info, codep + 2);
15875   x = *codep++ & 0xff;
15876   x |= (*codep++ & 0xff) << 8;
15877   return x;
15878 }
15879
15880 static void
15881 set_op (bfd_vma op, int riprel)
15882 {
15883   op_index[op_ad] = op_ad;
15884   if (address_mode == mode_64bit)
15885     {
15886       op_address[op_ad] = op;
15887       op_riprel[op_ad] = riprel;
15888     }
15889   else
15890     {
15891       /* Mask to get a 32-bit address.  */
15892       op_address[op_ad] = op & 0xffffffff;
15893       op_riprel[op_ad] = riprel & 0xffffffff;
15894     }
15895 }
15896
15897 static void
15898 OP_REG (int code, int sizeflag)
15899 {
15900   const char *s;
15901   int add;
15902
15903   switch (code)
15904     {
15905     case es_reg: case ss_reg: case cs_reg:
15906     case ds_reg: case fs_reg: case gs_reg:
15907       oappend (names_seg[code - es_reg]);
15908       return;
15909     }
15910
15911   USED_REX (REX_B);
15912   if (rex & REX_B)
15913     add = 8;
15914   else
15915     add = 0;
15916
15917   switch (code)
15918     {
15919     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15920     case sp_reg: case bp_reg: case si_reg: case di_reg:
15921       s = names16[code - ax_reg + add];
15922       break;
15923     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15924     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15925       USED_REX (0);
15926       if (rex)
15927         s = names8rex[code - al_reg + add];
15928       else
15929         s = names8[code - al_reg];
15930       break;
15931     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15932     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15933       if (address_mode == mode_64bit
15934           && ((sizeflag & DFLAG) || (rex & REX_W)))
15935         {
15936           s = names64[code - rAX_reg + add];
15937           break;
15938         }
15939       code += eAX_reg - rAX_reg;
15940       /* Fall through.  */
15941     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15942     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15943       USED_REX (REX_W);
15944       if (rex & REX_W)
15945         s = names64[code - eAX_reg + add];
15946       else
15947         {
15948           if (sizeflag & DFLAG)
15949             s = names32[code - eAX_reg + add];
15950           else
15951             s = names16[code - eAX_reg + add];
15952           used_prefixes |= (prefixes & PREFIX_DATA);
15953         }
15954       break;
15955     default:
15956       s = INTERNAL_DISASSEMBLER_ERROR;
15957       break;
15958     }
15959   oappend (s);
15960 }
15961
15962 static void
15963 OP_IMREG (int code, int sizeflag)
15964 {
15965   const char *s;
15966
15967   switch (code)
15968     {
15969     case indir_dx_reg:
15970       if (intel_syntax)
15971         s = "dx";
15972       else
15973         s = "(%dx)";
15974       break;
15975     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15976     case sp_reg: case bp_reg: case si_reg: case di_reg:
15977       s = names16[code - ax_reg];
15978       break;
15979     case es_reg: case ss_reg: case cs_reg:
15980     case ds_reg: case fs_reg: case gs_reg:
15981       s = names_seg[code - es_reg];
15982       break;
15983     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15984     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15985       USED_REX (0);
15986       if (rex)
15987         s = names8rex[code - al_reg];
15988       else
15989         s = names8[code - al_reg];
15990       break;
15991     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15992     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15993       USED_REX (REX_W);
15994       if (rex & REX_W)
15995         s = names64[code - eAX_reg];
15996       else
15997         {
15998           if (sizeflag & DFLAG)
15999             s = names32[code - eAX_reg];
16000           else
16001             s = names16[code - eAX_reg];
16002           used_prefixes |= (prefixes & PREFIX_DATA);
16003         }
16004       break;
16005     case z_mode_ax_reg:
16006       if ((rex & REX_W) || (sizeflag & DFLAG))
16007         s = *names32;
16008       else
16009         s = *names16;
16010       if (!(rex & REX_W))
16011         used_prefixes |= (prefixes & PREFIX_DATA);
16012       break;
16013     default:
16014       s = INTERNAL_DISASSEMBLER_ERROR;
16015       break;
16016     }
16017   oappend (s);
16018 }
16019
16020 static void
16021 OP_I (int bytemode, int sizeflag)
16022 {
16023   bfd_signed_vma op;
16024   bfd_signed_vma mask = -1;
16025
16026   switch (bytemode)
16027     {
16028     case b_mode:
16029       FETCH_DATA (the_info, codep + 1);
16030       op = *codep++;
16031       mask = 0xff;
16032       break;
16033     case q_mode:
16034       if (address_mode == mode_64bit)
16035         {
16036           op = get32s ();
16037           break;
16038         }
16039       /* Fall through.  */
16040     case v_mode:
16041       USED_REX (REX_W);
16042       if (rex & REX_W)
16043         op = get32s ();
16044       else
16045         {
16046           if (sizeflag & DFLAG)
16047             {
16048               op = get32 ();
16049               mask = 0xffffffff;
16050             }
16051           else
16052             {
16053               op = get16 ();
16054               mask = 0xfffff;
16055             }
16056           used_prefixes |= (prefixes & PREFIX_DATA);
16057         }
16058       break;
16059     case w_mode:
16060       mask = 0xfffff;
16061       op = get16 ();
16062       break;
16063     case const_1_mode:
16064       if (intel_syntax)
16065         oappend ("1");
16066       return;
16067     default:
16068       oappend (INTERNAL_DISASSEMBLER_ERROR);
16069       return;
16070     }
16071
16072   op &= mask;
16073   scratchbuf[0] = '$';
16074   print_operand_value (scratchbuf + 1, 1, op);
16075   oappend_maybe_intel (scratchbuf);
16076   scratchbuf[0] = '\0';
16077 }
16078
16079 static void
16080 OP_I64 (int bytemode, int sizeflag)
16081 {
16082   bfd_signed_vma op;
16083   bfd_signed_vma mask = -1;
16084
16085   if (address_mode != mode_64bit)
16086     {
16087       OP_I (bytemode, sizeflag);
16088       return;
16089     }
16090
16091   switch (bytemode)
16092     {
16093     case b_mode:
16094       FETCH_DATA (the_info, codep + 1);
16095       op = *codep++;
16096       mask = 0xff;
16097       break;
16098     case v_mode:
16099       USED_REX (REX_W);
16100       if (rex & REX_W)
16101         op = get64 ();
16102       else
16103         {
16104           if (sizeflag & DFLAG)
16105             {
16106               op = get32 ();
16107               mask = 0xffffffff;
16108             }
16109           else
16110             {
16111               op = get16 ();
16112               mask = 0xfffff;
16113             }
16114           used_prefixes |= (prefixes & PREFIX_DATA);
16115         }
16116       break;
16117     case w_mode:
16118       mask = 0xfffff;
16119       op = get16 ();
16120       break;
16121     default:
16122       oappend (INTERNAL_DISASSEMBLER_ERROR);
16123       return;
16124     }
16125
16126   op &= mask;
16127   scratchbuf[0] = '$';
16128   print_operand_value (scratchbuf + 1, 1, op);
16129   oappend_maybe_intel (scratchbuf);
16130   scratchbuf[0] = '\0';
16131 }
16132
16133 static void
16134 OP_sI (int bytemode, int sizeflag)
16135 {
16136   bfd_signed_vma op;
16137
16138   switch (bytemode)
16139     {
16140     case b_mode:
16141     case b_T_mode:
16142       FETCH_DATA (the_info, codep + 1);
16143       op = *codep++;
16144       if ((op & 0x80) != 0)
16145         op -= 0x100;
16146       if (bytemode == b_T_mode)
16147         {
16148           if (address_mode != mode_64bit
16149               || !((sizeflag & DFLAG) || (rex & REX_W)))
16150             {
16151               /* The operand-size prefix is overridden by a REX prefix.  */
16152               if ((sizeflag & DFLAG) || (rex & REX_W))
16153                 op &= 0xffffffff;
16154               else
16155                 op &= 0xffff;
16156           }
16157         }
16158       else
16159         {
16160           if (!(rex & REX_W))
16161             {
16162               if (sizeflag & DFLAG)
16163                 op &= 0xffffffff;
16164               else
16165                 op &= 0xffff;
16166             }
16167         }
16168       break;
16169     case v_mode:
16170       /* The operand-size prefix is overridden by a REX prefix.  */
16171       if ((sizeflag & DFLAG) || (rex & REX_W))
16172         op = get32s ();
16173       else
16174         op = get16 ();
16175       break;
16176     default:
16177       oappend (INTERNAL_DISASSEMBLER_ERROR);
16178       return;
16179     }
16180
16181   scratchbuf[0] = '$';
16182   print_operand_value (scratchbuf + 1, 1, op);
16183   oappend_maybe_intel (scratchbuf);
16184 }
16185
16186 static void
16187 OP_J (int bytemode, int sizeflag)
16188 {
16189   bfd_vma disp;
16190   bfd_vma mask = -1;
16191   bfd_vma segment = 0;
16192
16193   switch (bytemode)
16194     {
16195     case b_mode:
16196       FETCH_DATA (the_info, codep + 1);
16197       disp = *codep++;
16198       if ((disp & 0x80) != 0)
16199         disp -= 0x100;
16200       break;
16201     case v_mode:
16202       if (isa64 == amd64)
16203         USED_REX (REX_W);
16204       if ((sizeflag & DFLAG)
16205           || (address_mode == mode_64bit
16206               && (isa64 != amd64 || (rex & REX_W))))
16207         disp = get32s ();
16208       else
16209         {
16210           disp = get16 ();
16211           if ((disp & 0x8000) != 0)
16212             disp -= 0x10000;
16213           /* In 16bit mode, address is wrapped around at 64k within
16214              the same segment.  Otherwise, a data16 prefix on a jump
16215              instruction means that the pc is masked to 16 bits after
16216              the displacement is added!  */
16217           mask = 0xffff;
16218           if ((prefixes & PREFIX_DATA) == 0)
16219             segment = ((start_pc + (codep - start_codep))
16220                        & ~((bfd_vma) 0xffff));
16221         }
16222       if (address_mode != mode_64bit
16223           || (isa64 == amd64 && !(rex & REX_W)))
16224         used_prefixes |= (prefixes & PREFIX_DATA);
16225       break;
16226     default:
16227       oappend (INTERNAL_DISASSEMBLER_ERROR);
16228       return;
16229     }
16230   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16231   set_op (disp, 0);
16232   print_operand_value (scratchbuf, 1, disp);
16233   oappend (scratchbuf);
16234 }
16235
16236 static void
16237 OP_SEG (int bytemode, int sizeflag)
16238 {
16239   if (bytemode == w_mode)
16240     oappend (names_seg[modrm.reg]);
16241   else
16242     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16243 }
16244
16245 static void
16246 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16247 {
16248   int seg, offset;
16249
16250   if (sizeflag & DFLAG)
16251     {
16252       offset = get32 ();
16253       seg = get16 ();
16254     }
16255   else
16256     {
16257       offset = get16 ();
16258       seg = get16 ();
16259     }
16260   used_prefixes |= (prefixes & PREFIX_DATA);
16261   if (intel_syntax)
16262     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16263   else
16264     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16265   oappend (scratchbuf);
16266 }
16267
16268 static void
16269 OP_OFF (int bytemode, int sizeflag)
16270 {
16271   bfd_vma off;
16272
16273   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16274     intel_operand_size (bytemode, sizeflag);
16275   append_seg ();
16276
16277   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16278     off = get32 ();
16279   else
16280     off = get16 ();
16281
16282   if (intel_syntax)
16283     {
16284       if (!active_seg_prefix)
16285         {
16286           oappend (names_seg[ds_reg - es_reg]);
16287           oappend (":");
16288         }
16289     }
16290   print_operand_value (scratchbuf, 1, off);
16291   oappend (scratchbuf);
16292 }
16293
16294 static void
16295 OP_OFF64 (int bytemode, int sizeflag)
16296 {
16297   bfd_vma off;
16298
16299   if (address_mode != mode_64bit
16300       || (prefixes & PREFIX_ADDR))
16301     {
16302       OP_OFF (bytemode, sizeflag);
16303       return;
16304     }
16305
16306   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16307     intel_operand_size (bytemode, sizeflag);
16308   append_seg ();
16309
16310   off = get64 ();
16311
16312   if (intel_syntax)
16313     {
16314       if (!active_seg_prefix)
16315         {
16316           oappend (names_seg[ds_reg - es_reg]);
16317           oappend (":");
16318         }
16319     }
16320   print_operand_value (scratchbuf, 1, off);
16321   oappend (scratchbuf);
16322 }
16323
16324 static void
16325 ptr_reg (int code, int sizeflag)
16326 {
16327   const char *s;
16328
16329   *obufp++ = open_char;
16330   used_prefixes |= (prefixes & PREFIX_ADDR);
16331   if (address_mode == mode_64bit)
16332     {
16333       if (!(sizeflag & AFLAG))
16334         s = names32[code - eAX_reg];
16335       else
16336         s = names64[code - eAX_reg];
16337     }
16338   else if (sizeflag & AFLAG)
16339     s = names32[code - eAX_reg];
16340   else
16341     s = names16[code - eAX_reg];
16342   oappend (s);
16343   *obufp++ = close_char;
16344   *obufp = 0;
16345 }
16346
16347 static void
16348 OP_ESreg (int code, int sizeflag)
16349 {
16350   if (intel_syntax)
16351     {
16352       switch (codep[-1])
16353         {
16354         case 0x6d:      /* insw/insl */
16355           intel_operand_size (z_mode, sizeflag);
16356           break;
16357         case 0xa5:      /* movsw/movsl/movsq */
16358         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16359         case 0xab:      /* stosw/stosl */
16360         case 0xaf:      /* scasw/scasl */
16361           intel_operand_size (v_mode, sizeflag);
16362           break;
16363         default:
16364           intel_operand_size (b_mode, sizeflag);
16365         }
16366     }
16367   oappend_maybe_intel ("%es:");
16368   ptr_reg (code, sizeflag);
16369 }
16370
16371 static void
16372 OP_DSreg (int code, int sizeflag)
16373 {
16374   if (intel_syntax)
16375     {
16376       switch (codep[-1])
16377         {
16378         case 0x6f:      /* outsw/outsl */
16379           intel_operand_size (z_mode, sizeflag);
16380           break;
16381         case 0xa5:      /* movsw/movsl/movsq */
16382         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16383         case 0xad:      /* lodsw/lodsl/lodsq */
16384           intel_operand_size (v_mode, sizeflag);
16385           break;
16386         default:
16387           intel_operand_size (b_mode, sizeflag);
16388         }
16389     }
16390   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16391      default segment register DS is printed.  */
16392   if (!active_seg_prefix)
16393     active_seg_prefix = PREFIX_DS;
16394   append_seg ();
16395   ptr_reg (code, sizeflag);
16396 }
16397
16398 static void
16399 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16400 {
16401   int add;
16402   if (rex & REX_R)
16403     {
16404       USED_REX (REX_R);
16405       add = 8;
16406     }
16407   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16408     {
16409       all_prefixes[last_lock_prefix] = 0;
16410       used_prefixes |= PREFIX_LOCK;
16411       add = 8;
16412     }
16413   else
16414     add = 0;
16415   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16416   oappend_maybe_intel (scratchbuf);
16417 }
16418
16419 static void
16420 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16421 {
16422   int add;
16423   USED_REX (REX_R);
16424   if (rex & REX_R)
16425     add = 8;
16426   else
16427     add = 0;
16428   if (intel_syntax)
16429     sprintf (scratchbuf, "db%d", modrm.reg + add);
16430   else
16431     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16432   oappend (scratchbuf);
16433 }
16434
16435 static void
16436 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16437 {
16438   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16439   oappend_maybe_intel (scratchbuf);
16440 }
16441
16442 static void
16443 OP_R (int bytemode, int sizeflag)
16444 {
16445   /* Skip mod/rm byte.  */
16446   MODRM_CHECK;
16447   codep++;
16448   OP_E_register (bytemode, sizeflag);
16449 }
16450
16451 static void
16452 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16453 {
16454   int reg = modrm.reg;
16455   const char **names;
16456
16457   used_prefixes |= (prefixes & PREFIX_DATA);
16458   if (prefixes & PREFIX_DATA)
16459     {
16460       names = names_xmm;
16461       USED_REX (REX_R);
16462       if (rex & REX_R)
16463         reg += 8;
16464     }
16465   else
16466     names = names_mm;
16467   oappend (names[reg]);
16468 }
16469
16470 static void
16471 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16472 {
16473   int reg = modrm.reg;
16474   const char **names;
16475
16476   USED_REX (REX_R);
16477   if (rex & REX_R)
16478     reg += 8;
16479   if (vex.evex)
16480     {
16481       if (!vex.r)
16482         reg += 16;
16483     }
16484
16485   if (need_vex
16486       && bytemode != xmm_mode
16487       && bytemode != xmmq_mode
16488       && bytemode != evex_half_bcst_xmmq_mode
16489       && bytemode != ymm_mode
16490       && bytemode != scalar_mode)
16491     {
16492       switch (vex.length)
16493         {
16494         case 128:
16495           names = names_xmm;
16496           break;
16497         case 256:
16498           if (vex.w
16499               || (bytemode != vex_vsib_q_w_dq_mode
16500                   && bytemode != vex_vsib_q_w_d_mode))
16501             names = names_ymm;
16502           else
16503             names = names_xmm;
16504           break;
16505         case 512:
16506           names = names_zmm;
16507           break;
16508         default:
16509           abort ();
16510         }
16511     }
16512   else if (bytemode == xmmq_mode
16513            || bytemode == evex_half_bcst_xmmq_mode)
16514     {
16515       switch (vex.length)
16516         {
16517         case 128:
16518         case 256:
16519           names = names_xmm;
16520           break;
16521         case 512:
16522           names = names_ymm;
16523           break;
16524         default:
16525           abort ();
16526         }
16527     }
16528   else if (bytemode == ymm_mode)
16529     names = names_ymm;
16530   else
16531     names = names_xmm;
16532   oappend (names[reg]);
16533 }
16534
16535 static void
16536 OP_EM (int bytemode, int sizeflag)
16537 {
16538   int reg;
16539   const char **names;
16540
16541   if (modrm.mod != 3)
16542     {
16543       if (intel_syntax
16544           && (bytemode == v_mode || bytemode == v_swap_mode))
16545         {
16546           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16547           used_prefixes |= (prefixes & PREFIX_DATA);
16548         }
16549       OP_E (bytemode, sizeflag);
16550       return;
16551     }
16552
16553   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16554     swap_operand ();
16555
16556   /* Skip mod/rm byte.  */
16557   MODRM_CHECK;
16558   codep++;
16559   used_prefixes |= (prefixes & PREFIX_DATA);
16560   reg = modrm.rm;
16561   if (prefixes & PREFIX_DATA)
16562     {
16563       names = names_xmm;
16564       USED_REX (REX_B);
16565       if (rex & REX_B)
16566         reg += 8;
16567     }
16568   else
16569     names = names_mm;
16570   oappend (names[reg]);
16571 }
16572
16573 /* cvt* are the only instructions in sse2 which have
16574    both SSE and MMX operands and also have 0x66 prefix
16575    in their opcode. 0x66 was originally used to differentiate
16576    between SSE and MMX instruction(operands). So we have to handle the
16577    cvt* separately using OP_EMC and OP_MXC */
16578 static void
16579 OP_EMC (int bytemode, int sizeflag)
16580 {
16581   if (modrm.mod != 3)
16582     {
16583       if (intel_syntax && bytemode == v_mode)
16584         {
16585           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16586           used_prefixes |= (prefixes & PREFIX_DATA);
16587         }
16588       OP_E (bytemode, sizeflag);
16589       return;
16590     }
16591
16592   /* Skip mod/rm byte.  */
16593   MODRM_CHECK;
16594   codep++;
16595   used_prefixes |= (prefixes & PREFIX_DATA);
16596   oappend (names_mm[modrm.rm]);
16597 }
16598
16599 static void
16600 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16601 {
16602   used_prefixes |= (prefixes & PREFIX_DATA);
16603   oappend (names_mm[modrm.reg]);
16604 }
16605
16606 static void
16607 OP_EX (int bytemode, int sizeflag)
16608 {
16609   int reg;
16610   const char **names;
16611
16612   /* Skip mod/rm byte.  */
16613   MODRM_CHECK;
16614   codep++;
16615
16616   if (modrm.mod != 3)
16617     {
16618       OP_E_memory (bytemode, sizeflag);
16619       return;
16620     }
16621
16622   reg = modrm.rm;
16623   USED_REX (REX_B);
16624   if (rex & REX_B)
16625     reg += 8;
16626   if (vex.evex)
16627     {
16628       USED_REX (REX_X);
16629       if ((rex & REX_X))
16630         reg += 16;
16631     }
16632
16633   if ((sizeflag & SUFFIX_ALWAYS)
16634       && (bytemode == x_swap_mode
16635           || bytemode == d_swap_mode
16636           || bytemode == dqw_swap_mode
16637           || bytemode == d_scalar_swap_mode
16638           || bytemode == q_swap_mode
16639           || bytemode == q_scalar_swap_mode))
16640     swap_operand ();
16641
16642   if (need_vex
16643       && bytemode != xmm_mode
16644       && bytemode != xmmdw_mode
16645       && bytemode != xmmqd_mode
16646       && bytemode != xmm_mb_mode
16647       && bytemode != xmm_mw_mode
16648       && bytemode != xmm_md_mode
16649       && bytemode != xmm_mq_mode
16650       && bytemode != xmm_mdq_mode
16651       && bytemode != xmmq_mode
16652       && bytemode != evex_half_bcst_xmmq_mode
16653       && bytemode != ymm_mode
16654       && bytemode != d_scalar_mode
16655       && bytemode != d_scalar_swap_mode
16656       && bytemode != q_scalar_mode
16657       && bytemode != q_scalar_swap_mode
16658       && bytemode != vex_scalar_w_dq_mode)
16659     {
16660       switch (vex.length)
16661         {
16662         case 128:
16663           names = names_xmm;
16664           break;
16665         case 256:
16666           names = names_ymm;
16667           break;
16668         case 512:
16669           names = names_zmm;
16670           break;
16671         default:
16672           abort ();
16673         }
16674     }
16675   else if (bytemode == xmmq_mode
16676            || bytemode == evex_half_bcst_xmmq_mode)
16677     {
16678       switch (vex.length)
16679         {
16680         case 128:
16681         case 256:
16682           names = names_xmm;
16683           break;
16684         case 512:
16685           names = names_ymm;
16686           break;
16687         default:
16688           abort ();
16689         }
16690     }
16691   else if (bytemode == ymm_mode)
16692     names = names_ymm;
16693   else
16694     names = names_xmm;
16695   oappend (names[reg]);
16696 }
16697
16698 static void
16699 OP_MS (int bytemode, int sizeflag)
16700 {
16701   if (modrm.mod == 3)
16702     OP_EM (bytemode, sizeflag);
16703   else
16704     BadOp ();
16705 }
16706
16707 static void
16708 OP_XS (int bytemode, int sizeflag)
16709 {
16710   if (modrm.mod == 3)
16711     OP_EX (bytemode, sizeflag);
16712   else
16713     BadOp ();
16714 }
16715
16716 static void
16717 OP_M (int bytemode, int sizeflag)
16718 {
16719   if (modrm.mod == 3)
16720     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16721     BadOp ();
16722   else
16723     OP_E (bytemode, sizeflag);
16724 }
16725
16726 static void
16727 OP_0f07 (int bytemode, int sizeflag)
16728 {
16729   if (modrm.mod != 3 || modrm.rm != 0)
16730     BadOp ();
16731   else
16732     OP_E (bytemode, sizeflag);
16733 }
16734
16735 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16736    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16737
16738 static void
16739 NOP_Fixup1 (int bytemode, int sizeflag)
16740 {
16741   if ((prefixes & PREFIX_DATA) != 0
16742       || (rex != 0
16743           && rex != 0x48
16744           && address_mode == mode_64bit))
16745     OP_REG (bytemode, sizeflag);
16746   else
16747     strcpy (obuf, "nop");
16748 }
16749
16750 static void
16751 NOP_Fixup2 (int bytemode, int sizeflag)
16752 {
16753   if ((prefixes & PREFIX_DATA) != 0
16754       || (rex != 0
16755           && rex != 0x48
16756           && address_mode == mode_64bit))
16757     OP_IMREG (bytemode, sizeflag);
16758 }
16759
16760 static const char *const Suffix3DNow[] = {
16761 /* 00 */        NULL,           NULL,           NULL,           NULL,
16762 /* 04 */        NULL,           NULL,           NULL,           NULL,
16763 /* 08 */        NULL,           NULL,           NULL,           NULL,
16764 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16765 /* 10 */        NULL,           NULL,           NULL,           NULL,
16766 /* 14 */        NULL,           NULL,           NULL,           NULL,
16767 /* 18 */        NULL,           NULL,           NULL,           NULL,
16768 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16769 /* 20 */        NULL,           NULL,           NULL,           NULL,
16770 /* 24 */        NULL,           NULL,           NULL,           NULL,
16771 /* 28 */        NULL,           NULL,           NULL,           NULL,
16772 /* 2C */        NULL,           NULL,           NULL,           NULL,
16773 /* 30 */        NULL,           NULL,           NULL,           NULL,
16774 /* 34 */        NULL,           NULL,           NULL,           NULL,
16775 /* 38 */        NULL,           NULL,           NULL,           NULL,
16776 /* 3C */        NULL,           NULL,           NULL,           NULL,
16777 /* 40 */        NULL,           NULL,           NULL,           NULL,
16778 /* 44 */        NULL,           NULL,           NULL,           NULL,
16779 /* 48 */        NULL,           NULL,           NULL,           NULL,
16780 /* 4C */        NULL,           NULL,           NULL,           NULL,
16781 /* 50 */        NULL,           NULL,           NULL,           NULL,
16782 /* 54 */        NULL,           NULL,           NULL,           NULL,
16783 /* 58 */        NULL,           NULL,           NULL,           NULL,
16784 /* 5C */        NULL,           NULL,           NULL,           NULL,
16785 /* 60 */        NULL,           NULL,           NULL,           NULL,
16786 /* 64 */        NULL,           NULL,           NULL,           NULL,
16787 /* 68 */        NULL,           NULL,           NULL,           NULL,
16788 /* 6C */        NULL,           NULL,           NULL,           NULL,
16789 /* 70 */        NULL,           NULL,           NULL,           NULL,
16790 /* 74 */        NULL,           NULL,           NULL,           NULL,
16791 /* 78 */        NULL,           NULL,           NULL,           NULL,
16792 /* 7C */        NULL,           NULL,           NULL,           NULL,
16793 /* 80 */        NULL,           NULL,           NULL,           NULL,
16794 /* 84 */        NULL,           NULL,           NULL,           NULL,
16795 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16796 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16797 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16798 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16799 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16800 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16801 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16802 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16803 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16804 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16805 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16806 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16807 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16808 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16809 /* C0 */        NULL,           NULL,           NULL,           NULL,
16810 /* C4 */        NULL,           NULL,           NULL,           NULL,
16811 /* C8 */        NULL,           NULL,           NULL,           NULL,
16812 /* CC */        NULL,           NULL,           NULL,           NULL,
16813 /* D0 */        NULL,           NULL,           NULL,           NULL,
16814 /* D4 */        NULL,           NULL,           NULL,           NULL,
16815 /* D8 */        NULL,           NULL,           NULL,           NULL,
16816 /* DC */        NULL,           NULL,           NULL,           NULL,
16817 /* E0 */        NULL,           NULL,           NULL,           NULL,
16818 /* E4 */        NULL,           NULL,           NULL,           NULL,
16819 /* E8 */        NULL,           NULL,           NULL,           NULL,
16820 /* EC */        NULL,           NULL,           NULL,           NULL,
16821 /* F0 */        NULL,           NULL,           NULL,           NULL,
16822 /* F4 */        NULL,           NULL,           NULL,           NULL,
16823 /* F8 */        NULL,           NULL,           NULL,           NULL,
16824 /* FC */        NULL,           NULL,           NULL,           NULL,
16825 };
16826
16827 static void
16828 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16829 {
16830   const char *mnemonic;
16831
16832   FETCH_DATA (the_info, codep + 1);
16833   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16834      place where an 8-bit immediate would normally go.  ie. the last
16835      byte of the instruction.  */
16836   obufp = mnemonicendp;
16837   mnemonic = Suffix3DNow[*codep++ & 0xff];
16838   if (mnemonic)
16839     oappend (mnemonic);
16840   else
16841     {
16842       /* Since a variable sized modrm/sib chunk is between the start
16843          of the opcode (0x0f0f) and the opcode suffix, we need to do
16844          all the modrm processing first, and don't know until now that
16845          we have a bad opcode.  This necessitates some cleaning up.  */
16846       op_out[0][0] = '\0';
16847       op_out[1][0] = '\0';
16848       BadOp ();
16849     }
16850   mnemonicendp = obufp;
16851 }
16852
16853 static struct op simd_cmp_op[] =
16854 {
16855   { STRING_COMMA_LEN ("eq") },
16856   { STRING_COMMA_LEN ("lt") },
16857   { STRING_COMMA_LEN ("le") },
16858   { STRING_COMMA_LEN ("unord") },
16859   { STRING_COMMA_LEN ("neq") },
16860   { STRING_COMMA_LEN ("nlt") },
16861   { STRING_COMMA_LEN ("nle") },
16862   { STRING_COMMA_LEN ("ord") }
16863 };
16864
16865 static void
16866 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16867 {
16868   unsigned int cmp_type;
16869
16870   FETCH_DATA (the_info, codep + 1);
16871   cmp_type = *codep++ & 0xff;
16872   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16873     {
16874       char suffix [3];
16875       char *p = mnemonicendp - 2;
16876       suffix[0] = p[0];
16877       suffix[1] = p[1];
16878       suffix[2] = '\0';
16879       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16880       mnemonicendp += simd_cmp_op[cmp_type].len;
16881     }
16882   else
16883     {
16884       /* We have a reserved extension byte.  Output it directly.  */
16885       scratchbuf[0] = '$';
16886       print_operand_value (scratchbuf + 1, 1, cmp_type);
16887       oappend_maybe_intel (scratchbuf);
16888       scratchbuf[0] = '\0';
16889     }
16890 }
16891
16892 static void
16893 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16894           int sizeflag ATTRIBUTE_UNUSED)
16895 {
16896   /* mwaitx %eax,%ecx,%ebx */
16897   if (!intel_syntax)
16898     {
16899       const char **names = (address_mode == mode_64bit
16900                             ? names64 : names32);
16901       strcpy (op_out[0], names[0]);
16902       strcpy (op_out[1], names[1]);
16903       strcpy (op_out[2], names[3]);
16904       two_source_ops = 1;
16905     }
16906   /* Skip mod/rm byte.  */
16907   MODRM_CHECK;
16908   codep++;
16909 }
16910
16911 static void
16912 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16913           int sizeflag ATTRIBUTE_UNUSED)
16914 {
16915   /* mwait %eax,%ecx  */
16916   if (!intel_syntax)
16917     {
16918       const char **names = (address_mode == mode_64bit
16919                             ? names64 : names32);
16920       strcpy (op_out[0], names[0]);
16921       strcpy (op_out[1], names[1]);
16922       two_source_ops = 1;
16923     }
16924   /* Skip mod/rm byte.  */
16925   MODRM_CHECK;
16926   codep++;
16927 }
16928
16929 static void
16930 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16931             int sizeflag ATTRIBUTE_UNUSED)
16932 {
16933   /* monitor %eax,%ecx,%edx"  */
16934   if (!intel_syntax)
16935     {
16936       const char **op1_names;
16937       const char **names = (address_mode == mode_64bit
16938                             ? names64 : names32);
16939
16940       if (!(prefixes & PREFIX_ADDR))
16941         op1_names = (address_mode == mode_16bit
16942                      ? names16 : names);
16943       else
16944         {
16945           /* Remove "addr16/addr32".  */
16946           all_prefixes[last_addr_prefix] = 0;
16947           op1_names = (address_mode != mode_32bit
16948                        ? names32 : names16);
16949           used_prefixes |= PREFIX_ADDR;
16950         }
16951       strcpy (op_out[0], op1_names[0]);
16952       strcpy (op_out[1], names[1]);
16953       strcpy (op_out[2], names[2]);
16954       two_source_ops = 1;
16955     }
16956   /* Skip mod/rm byte.  */
16957   MODRM_CHECK;
16958   codep++;
16959 }
16960
16961 static void
16962 BadOp (void)
16963 {
16964   /* Throw away prefixes and 1st. opcode byte.  */
16965   codep = insn_codep + 1;
16966   oappend ("(bad)");
16967 }
16968
16969 static void
16970 REP_Fixup (int bytemode, int sizeflag)
16971 {
16972   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16973      lods and stos.  */
16974   if (prefixes & PREFIX_REPZ)
16975     all_prefixes[last_repz_prefix] = REP_PREFIX;
16976
16977   switch (bytemode)
16978     {
16979     case al_reg:
16980     case eAX_reg:
16981     case indir_dx_reg:
16982       OP_IMREG (bytemode, sizeflag);
16983       break;
16984     case eDI_reg:
16985       OP_ESreg (bytemode, sizeflag);
16986       break;
16987     case eSI_reg:
16988       OP_DSreg (bytemode, sizeflag);
16989       break;
16990     default:
16991       abort ();
16992       break;
16993     }
16994 }
16995
16996 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16997    "bnd".  */
16998
16999 static void
17000 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17001 {
17002   if (prefixes & PREFIX_REPNZ)
17003     all_prefixes[last_repnz_prefix] = BND_PREFIX;
17004 }
17005
17006 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
17007    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
17008  */
17009
17010 static void
17011 HLE_Fixup1 (int bytemode, int sizeflag)
17012 {
17013   if (modrm.mod != 3
17014       && (prefixes & PREFIX_LOCK) != 0)
17015     {
17016       if (prefixes & PREFIX_REPZ)
17017         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17018       if (prefixes & PREFIX_REPNZ)
17019         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17020     }
17021
17022   OP_E (bytemode, sizeflag);
17023 }
17024
17025 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
17026    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
17027  */
17028
17029 static void
17030 HLE_Fixup2 (int bytemode, int sizeflag)
17031 {
17032   if (modrm.mod != 3)
17033     {
17034       if (prefixes & PREFIX_REPZ)
17035         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17036       if (prefixes & PREFIX_REPNZ)
17037         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17038     }
17039
17040   OP_E (bytemode, sizeflag);
17041 }
17042
17043 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
17044    "xrelease" for memory operand.  No check for LOCK prefix.   */
17045
17046 static void
17047 HLE_Fixup3 (int bytemode, int sizeflag)
17048 {
17049   if (modrm.mod != 3
17050       && last_repz_prefix > last_repnz_prefix
17051       && (prefixes & PREFIX_REPZ) != 0)
17052     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17053
17054   OP_E (bytemode, sizeflag);
17055 }
17056
17057 static void
17058 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
17059 {
17060   USED_REX (REX_W);
17061   if (rex & REX_W)
17062     {
17063       /* Change cmpxchg8b to cmpxchg16b.  */
17064       char *p = mnemonicendp - 2;
17065       mnemonicendp = stpcpy (p, "16b");
17066       bytemode = o_mode;
17067     }
17068   else if ((prefixes & PREFIX_LOCK) != 0)
17069     {
17070       if (prefixes & PREFIX_REPZ)
17071         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17072       if (prefixes & PREFIX_REPNZ)
17073         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17074     }
17075
17076   OP_M (bytemode, sizeflag);
17077 }
17078
17079 static void
17080 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17081 {
17082   const char **names;
17083
17084   if (need_vex)
17085     {
17086       switch (vex.length)
17087         {
17088         case 128:
17089           names = names_xmm;
17090           break;
17091         case 256:
17092           names = names_ymm;
17093           break;
17094         default:
17095           abort ();
17096         }
17097     }
17098   else
17099     names = names_xmm;
17100   oappend (names[reg]);
17101 }
17102
17103 static void
17104 CRC32_Fixup (int bytemode, int sizeflag)
17105 {
17106   /* Add proper suffix to "crc32".  */
17107   char *p = mnemonicendp;
17108
17109   switch (bytemode)
17110     {
17111     case b_mode:
17112       if (intel_syntax)
17113         goto skip;
17114
17115       *p++ = 'b';
17116       break;
17117     case v_mode:
17118       if (intel_syntax)
17119         goto skip;
17120
17121       USED_REX (REX_W);
17122       if (rex & REX_W)
17123         *p++ = 'q';
17124       else
17125         {
17126           if (sizeflag & DFLAG)
17127             *p++ = 'l';
17128           else
17129             *p++ = 'w';
17130           used_prefixes |= (prefixes & PREFIX_DATA);
17131         }
17132       break;
17133     default:
17134       oappend (INTERNAL_DISASSEMBLER_ERROR);
17135       break;
17136     }
17137   mnemonicendp = p;
17138   *p = '\0';
17139
17140 skip:
17141   if (modrm.mod == 3)
17142     {
17143       int add;
17144
17145       /* Skip mod/rm byte.  */
17146       MODRM_CHECK;
17147       codep++;
17148
17149       USED_REX (REX_B);
17150       add = (rex & REX_B) ? 8 : 0;
17151       if (bytemode == b_mode)
17152         {
17153           USED_REX (0);
17154           if (rex)
17155             oappend (names8rex[modrm.rm + add]);
17156           else
17157             oappend (names8[modrm.rm + add]);
17158         }
17159       else
17160         {
17161           USED_REX (REX_W);
17162           if (rex & REX_W)
17163             oappend (names64[modrm.rm + add]);
17164           else if ((prefixes & PREFIX_DATA))
17165             oappend (names16[modrm.rm + add]);
17166           else
17167             oappend (names32[modrm.rm + add]);
17168         }
17169     }
17170   else
17171     OP_E (bytemode, sizeflag);
17172 }
17173
17174 static void
17175 FXSAVE_Fixup (int bytemode, int sizeflag)
17176 {
17177   /* Add proper suffix to "fxsave" and "fxrstor".  */
17178   USED_REX (REX_W);
17179   if (rex & REX_W)
17180     {
17181       char *p = mnemonicendp;
17182       *p++ = '6';
17183       *p++ = '4';
17184       *p = '\0';
17185       mnemonicendp = p;
17186     }
17187   OP_M (bytemode, sizeflag);
17188 }
17189
17190 /* Display the destination register operand for instructions with
17191    VEX. */
17192
17193 static void
17194 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17195 {
17196   int reg;
17197   const char **names;
17198
17199   if (!need_vex)
17200     abort ();
17201
17202   if (!need_vex_reg)
17203     return;
17204
17205   reg = vex.register_specifier;
17206   if (vex.evex)
17207     {
17208       if (!vex.v)
17209         reg += 16;
17210     }
17211
17212   if (bytemode == vex_scalar_mode)
17213     {
17214       oappend (names_xmm[reg]);
17215       return;
17216     }
17217
17218   switch (vex.length)
17219     {
17220     case 128:
17221       switch (bytemode)
17222         {
17223         case vex_mode:
17224         case vex128_mode:
17225         case vex_vsib_q_w_dq_mode:
17226         case vex_vsib_q_w_d_mode:
17227           names = names_xmm;
17228           break;
17229         case dq_mode:
17230           if (vex.w)
17231             names = names64;
17232           else
17233             names = names32;
17234           break;
17235         case mask_bd_mode:
17236         case mask_mode:
17237           if (reg > 0x7)
17238             {
17239               oappend ("(bad)");
17240               return;
17241             }
17242           names = names_mask;
17243           break;
17244         default:
17245           abort ();
17246           return;
17247         }
17248       break;
17249     case 256:
17250       switch (bytemode)
17251         {
17252         case vex_mode:
17253         case vex256_mode:
17254           names = names_ymm;
17255           break;
17256         case vex_vsib_q_w_dq_mode:
17257         case vex_vsib_q_w_d_mode:
17258           names = vex.w ? names_ymm : names_xmm;
17259           break;
17260         case mask_bd_mode:
17261         case mask_mode:
17262           if (reg > 0x7)
17263             {
17264               oappend ("(bad)");
17265               return;
17266             }
17267           names = names_mask;
17268           break;
17269         default:
17270           abort ();
17271           return;
17272         }
17273       break;
17274     case 512:
17275       names = names_zmm;
17276       break;
17277     default:
17278       abort ();
17279       break;
17280     }
17281   oappend (names[reg]);
17282 }
17283
17284 /* Get the VEX immediate byte without moving codep.  */
17285
17286 static unsigned char
17287 get_vex_imm8 (int sizeflag, int opnum)
17288 {
17289   int bytes_before_imm = 0;
17290
17291   if (modrm.mod != 3)
17292     {
17293       /* There are SIB/displacement bytes.  */
17294       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17295         {
17296           /* 32/64 bit address mode */
17297           int base = modrm.rm;
17298
17299           /* Check SIB byte.  */
17300           if (base == 4)
17301             {
17302               FETCH_DATA (the_info, codep + 1);
17303               base = *codep & 7;
17304               /* When decoding the third source, don't increase
17305                  bytes_before_imm as this has already been incremented
17306                  by one in OP_E_memory while decoding the second
17307                  source operand.  */
17308               if (opnum == 0)
17309                 bytes_before_imm++;
17310             }
17311
17312           /* Don't increase bytes_before_imm when decoding the third source,
17313              it has already been incremented by OP_E_memory while decoding
17314              the second source operand.  */
17315           if (opnum == 0)
17316             {
17317               switch (modrm.mod)
17318                 {
17319                   case 0:
17320                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17321                        SIB == 5, there is a 4 byte displacement.  */
17322                     if (base != 5)
17323                       /* No displacement. */
17324                       break;
17325                     /* Fall through.  */
17326                   case 2:
17327                     /* 4 byte displacement.  */
17328                     bytes_before_imm += 4;
17329                     break;
17330                   case 1:
17331                     /* 1 byte displacement.  */
17332                     bytes_before_imm++;
17333                     break;
17334                 }
17335             }
17336         }
17337       else
17338         {
17339           /* 16 bit address mode */
17340           /* Don't increase bytes_before_imm when decoding the third source,
17341              it has already been incremented by OP_E_memory while decoding
17342              the second source operand.  */
17343           if (opnum == 0)
17344             {
17345               switch (modrm.mod)
17346                 {
17347                 case 0:
17348                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17349                   if (modrm.rm != 6)
17350                     /* No displacement. */
17351                     break;
17352                   /* Fall through.  */
17353                 case 2:
17354                   /* 2 byte displacement.  */
17355                   bytes_before_imm += 2;
17356                   break;
17357                 case 1:
17358                   /* 1 byte displacement: when decoding the third source,
17359                      don't increase bytes_before_imm as this has already
17360                      been incremented by one in OP_E_memory while decoding
17361                      the second source operand.  */
17362                   if (opnum == 0)
17363                     bytes_before_imm++;
17364
17365                   break;
17366                 }
17367             }
17368         }
17369     }
17370
17371   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17372   return codep [bytes_before_imm];
17373 }
17374
17375 static void
17376 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17377 {
17378   const char **names;
17379
17380   if (reg == -1 && modrm.mod != 3)
17381     {
17382       OP_E_memory (bytemode, sizeflag);
17383       return;
17384     }
17385   else
17386     {
17387       if (reg == -1)
17388         {
17389           reg = modrm.rm;
17390           USED_REX (REX_B);
17391           if (rex & REX_B)
17392             reg += 8;
17393         }
17394       else if (reg > 7 && address_mode != mode_64bit)
17395         BadOp ();
17396     }
17397
17398   switch (vex.length)
17399     {
17400     case 128:
17401       names = names_xmm;
17402       break;
17403     case 256:
17404       names = names_ymm;
17405       break;
17406     default:
17407       abort ();
17408     }
17409   oappend (names[reg]);
17410 }
17411
17412 static void
17413 OP_EX_VexImmW (int bytemode, int sizeflag)
17414 {
17415   int reg = -1;
17416   static unsigned char vex_imm8;
17417
17418   if (vex_w_done == 0)
17419     {
17420       vex_w_done = 1;
17421
17422       /* Skip mod/rm byte.  */
17423       MODRM_CHECK;
17424       codep++;
17425
17426       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17427
17428       if (vex.w)
17429           reg = vex_imm8 >> 4;
17430
17431       OP_EX_VexReg (bytemode, sizeflag, reg);
17432     }
17433   else if (vex_w_done == 1)
17434     {
17435       vex_w_done = 2;
17436
17437       if (!vex.w)
17438           reg = vex_imm8 >> 4;
17439
17440       OP_EX_VexReg (bytemode, sizeflag, reg);
17441     }
17442   else
17443     {
17444       /* Output the imm8 directly.  */
17445       scratchbuf[0] = '$';
17446       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17447       oappend_maybe_intel (scratchbuf);
17448       scratchbuf[0] = '\0';
17449       codep++;
17450     }
17451 }
17452
17453 static void
17454 OP_Vex_2src (int bytemode, int sizeflag)
17455 {
17456   if (modrm.mod == 3)
17457     {
17458       int reg = modrm.rm;
17459       USED_REX (REX_B);
17460       if (rex & REX_B)
17461         reg += 8;
17462       oappend (names_xmm[reg]);
17463     }
17464   else
17465     {
17466       if (intel_syntax
17467           && (bytemode == v_mode || bytemode == v_swap_mode))
17468         {
17469           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17470           used_prefixes |= (prefixes & PREFIX_DATA);
17471         }
17472       OP_E (bytemode, sizeflag);
17473     }
17474 }
17475
17476 static void
17477 OP_Vex_2src_1 (int bytemode, int sizeflag)
17478 {
17479   if (modrm.mod == 3)
17480     {
17481       /* Skip mod/rm byte.   */
17482       MODRM_CHECK;
17483       codep++;
17484     }
17485
17486   if (vex.w)
17487     oappend (names_xmm[vex.register_specifier]);
17488   else
17489     OP_Vex_2src (bytemode, sizeflag);
17490 }
17491
17492 static void
17493 OP_Vex_2src_2 (int bytemode, int sizeflag)
17494 {
17495   if (vex.w)
17496     OP_Vex_2src (bytemode, sizeflag);
17497   else
17498     oappend (names_xmm[vex.register_specifier]);
17499 }
17500
17501 static void
17502 OP_EX_VexW (int bytemode, int sizeflag)
17503 {
17504   int reg = -1;
17505
17506   if (!vex_w_done)
17507     {
17508       vex_w_done = 1;
17509
17510       /* Skip mod/rm byte.  */
17511       MODRM_CHECK;
17512       codep++;
17513
17514       if (vex.w)
17515         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17516     }
17517   else
17518     {
17519       if (!vex.w)
17520         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17521     }
17522
17523   OP_EX_VexReg (bytemode, sizeflag, reg);
17524 }
17525
17526 static void
17527 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17528              int sizeflag ATTRIBUTE_UNUSED)
17529 {
17530   /* Skip the immediate byte and check for invalid bits.  */
17531   FETCH_DATA (the_info, codep + 1);
17532   if (*codep++ & 0xf)
17533     BadOp ();
17534 }
17535
17536 static void
17537 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17538 {
17539   int reg;
17540   const char **names;
17541
17542   FETCH_DATA (the_info, codep + 1);
17543   reg = *codep++;
17544
17545   if (bytemode != x_mode)
17546     abort ();
17547
17548   if (reg & 0xf)
17549       BadOp ();
17550
17551   reg >>= 4;
17552   if (reg > 7 && address_mode != mode_64bit)
17553     BadOp ();
17554
17555   switch (vex.length)
17556     {
17557     case 128:
17558       names = names_xmm;
17559       break;
17560     case 256:
17561       names = names_ymm;
17562       break;
17563     default:
17564       abort ();
17565     }
17566   oappend (names[reg]);
17567 }
17568
17569 static void
17570 OP_XMM_VexW (int bytemode, int sizeflag)
17571 {
17572   /* Turn off the REX.W bit since it is used for swapping operands
17573      now.  */
17574   rex &= ~REX_W;
17575   OP_XMM (bytemode, sizeflag);
17576 }
17577
17578 static void
17579 OP_EX_Vex (int bytemode, int sizeflag)
17580 {
17581   if (modrm.mod != 3)
17582     {
17583       if (vex.register_specifier != 0)
17584         BadOp ();
17585       need_vex_reg = 0;
17586     }
17587   OP_EX (bytemode, sizeflag);
17588 }
17589
17590 static void
17591 OP_XMM_Vex (int bytemode, int sizeflag)
17592 {
17593   if (modrm.mod != 3)
17594     {
17595       if (vex.register_specifier != 0)
17596         BadOp ();
17597       need_vex_reg = 0;
17598     }
17599   OP_XMM (bytemode, sizeflag);
17600 }
17601
17602 static void
17603 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17604 {
17605   switch (vex.length)
17606     {
17607     case 128:
17608       mnemonicendp = stpcpy (obuf, "vzeroupper");
17609       break;
17610     case 256:
17611       mnemonicendp = stpcpy (obuf, "vzeroall");
17612       break;
17613     default:
17614       abort ();
17615     }
17616 }
17617
17618 static struct op vex_cmp_op[] =
17619 {
17620   { STRING_COMMA_LEN ("eq") },
17621   { STRING_COMMA_LEN ("lt") },
17622   { STRING_COMMA_LEN ("le") },
17623   { STRING_COMMA_LEN ("unord") },
17624   { STRING_COMMA_LEN ("neq") },
17625   { STRING_COMMA_LEN ("nlt") },
17626   { STRING_COMMA_LEN ("nle") },
17627   { STRING_COMMA_LEN ("ord") },
17628   { STRING_COMMA_LEN ("eq_uq") },
17629   { STRING_COMMA_LEN ("nge") },
17630   { STRING_COMMA_LEN ("ngt") },
17631   { STRING_COMMA_LEN ("false") },
17632   { STRING_COMMA_LEN ("neq_oq") },
17633   { STRING_COMMA_LEN ("ge") },
17634   { STRING_COMMA_LEN ("gt") },
17635   { STRING_COMMA_LEN ("true") },
17636   { STRING_COMMA_LEN ("eq_os") },
17637   { STRING_COMMA_LEN ("lt_oq") },
17638   { STRING_COMMA_LEN ("le_oq") },
17639   { STRING_COMMA_LEN ("unord_s") },
17640   { STRING_COMMA_LEN ("neq_us") },
17641   { STRING_COMMA_LEN ("nlt_uq") },
17642   { STRING_COMMA_LEN ("nle_uq") },
17643   { STRING_COMMA_LEN ("ord_s") },
17644   { STRING_COMMA_LEN ("eq_us") },
17645   { STRING_COMMA_LEN ("nge_uq") },
17646   { STRING_COMMA_LEN ("ngt_uq") },
17647   { STRING_COMMA_LEN ("false_os") },
17648   { STRING_COMMA_LEN ("neq_os") },
17649   { STRING_COMMA_LEN ("ge_oq") },
17650   { STRING_COMMA_LEN ("gt_oq") },
17651   { STRING_COMMA_LEN ("true_us") },
17652 };
17653
17654 static void
17655 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17656 {
17657   unsigned int cmp_type;
17658
17659   FETCH_DATA (the_info, codep + 1);
17660   cmp_type = *codep++ & 0xff;
17661   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17662     {
17663       char suffix [3];
17664       char *p = mnemonicendp - 2;
17665       suffix[0] = p[0];
17666       suffix[1] = p[1];
17667       suffix[2] = '\0';
17668       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17669       mnemonicendp += vex_cmp_op[cmp_type].len;
17670     }
17671   else
17672     {
17673       /* We have a reserved extension byte.  Output it directly.  */
17674       scratchbuf[0] = '$';
17675       print_operand_value (scratchbuf + 1, 1, cmp_type);
17676       oappend_maybe_intel (scratchbuf);
17677       scratchbuf[0] = '\0';
17678     }
17679 }
17680
17681 static void
17682 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17683              int sizeflag ATTRIBUTE_UNUSED)
17684 {
17685   unsigned int cmp_type;
17686
17687   if (!vex.evex)
17688     abort ();
17689
17690   FETCH_DATA (the_info, codep + 1);
17691   cmp_type = *codep++ & 0xff;
17692   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17693      If it's the case, print suffix, otherwise - print the immediate.  */
17694   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17695       && cmp_type != 3
17696       && cmp_type != 7)
17697     {
17698       char suffix [3];
17699       char *p = mnemonicendp - 2;
17700
17701       /* vpcmp* can have both one- and two-lettered suffix.  */
17702       if (p[0] == 'p')
17703         {
17704           p++;
17705           suffix[0] = p[0];
17706           suffix[1] = '\0';
17707         }
17708       else
17709         {
17710           suffix[0] = p[0];
17711           suffix[1] = p[1];
17712           suffix[2] = '\0';
17713         }
17714
17715       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17716       mnemonicendp += simd_cmp_op[cmp_type].len;
17717     }
17718   else
17719     {
17720       /* We have a reserved extension byte.  Output it directly.  */
17721       scratchbuf[0] = '$';
17722       print_operand_value (scratchbuf + 1, 1, cmp_type);
17723       oappend_maybe_intel (scratchbuf);
17724       scratchbuf[0] = '\0';
17725     }
17726 }
17727
17728 static const struct op pclmul_op[] =
17729 {
17730   { STRING_COMMA_LEN ("lql") },
17731   { STRING_COMMA_LEN ("hql") },
17732   { STRING_COMMA_LEN ("lqh") },
17733   { STRING_COMMA_LEN ("hqh") }
17734 };
17735
17736 static void
17737 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17738               int sizeflag ATTRIBUTE_UNUSED)
17739 {
17740   unsigned int pclmul_type;
17741
17742   FETCH_DATA (the_info, codep + 1);
17743   pclmul_type = *codep++ & 0xff;
17744   switch (pclmul_type)
17745     {
17746     case 0x10:
17747       pclmul_type = 2;
17748       break;
17749     case 0x11:
17750       pclmul_type = 3;
17751       break;
17752     default:
17753       break;
17754     }
17755   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17756     {
17757       char suffix [4];
17758       char *p = mnemonicendp - 3;
17759       suffix[0] = p[0];
17760       suffix[1] = p[1];
17761       suffix[2] = p[2];
17762       suffix[3] = '\0';
17763       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17764       mnemonicendp += pclmul_op[pclmul_type].len;
17765     }
17766   else
17767     {
17768       /* We have a reserved extension byte.  Output it directly.  */
17769       scratchbuf[0] = '$';
17770       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17771       oappend_maybe_intel (scratchbuf);
17772       scratchbuf[0] = '\0';
17773     }
17774 }
17775
17776 static void
17777 MOVBE_Fixup (int bytemode, int sizeflag)
17778 {
17779   /* Add proper suffix to "movbe".  */
17780   char *p = mnemonicendp;
17781
17782   switch (bytemode)
17783     {
17784     case v_mode:
17785       if (intel_syntax)
17786         goto skip;
17787
17788       USED_REX (REX_W);
17789       if (sizeflag & SUFFIX_ALWAYS)
17790         {
17791           if (rex & REX_W)
17792             *p++ = 'q';
17793           else
17794             {
17795               if (sizeflag & DFLAG)
17796                 *p++ = 'l';
17797               else
17798                 *p++ = 'w';
17799               used_prefixes |= (prefixes & PREFIX_DATA);
17800             }
17801         }
17802       break;
17803     default:
17804       oappend (INTERNAL_DISASSEMBLER_ERROR);
17805       break;
17806     }
17807   mnemonicendp = p;
17808   *p = '\0';
17809
17810 skip:
17811   OP_M (bytemode, sizeflag);
17812 }
17813
17814 static void
17815 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17816 {
17817   int reg;
17818   const char **names;
17819
17820   /* Skip mod/rm byte.  */
17821   MODRM_CHECK;
17822   codep++;
17823
17824   if (vex.w)
17825     names = names64;
17826   else
17827     names = names32;
17828
17829   reg = modrm.rm;
17830   USED_REX (REX_B);
17831   if (rex & REX_B)
17832     reg += 8;
17833
17834   oappend (names[reg]);
17835 }
17836
17837 static void
17838 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17839 {
17840   const char **names;
17841
17842   if (vex.w)
17843     names = names64;
17844   else
17845     names = names32;
17846
17847   oappend (names[vex.register_specifier]);
17848 }
17849
17850 static void
17851 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17852 {
17853   if (!vex.evex
17854       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17855     abort ();
17856
17857   USED_REX (REX_R);
17858   if ((rex & REX_R) != 0 || !vex.r)
17859     {
17860       BadOp ();
17861       return;
17862     }
17863
17864   oappend (names_mask [modrm.reg]);
17865 }
17866
17867 static void
17868 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17869 {
17870   if (!vex.evex
17871       || (bytemode != evex_rounding_mode
17872           && bytemode != evex_sae_mode))
17873     abort ();
17874   if (modrm.mod == 3 && vex.b)
17875     switch (bytemode)
17876       {
17877       case evex_rounding_mode:
17878         oappend (names_rounding[vex.ll]);
17879         break;
17880       case evex_sae_mode:
17881         oappend ("{sae}");
17882         break;
17883       default:
17884         break;
17885       }
17886 }