1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void OP_LWPCB_E (int, int);
120 static void OP_LWP_E (int, int);
121 static void OP_Vex_2src_1 (int, int);
122 static void OP_Vex_2src_2 (int, int);
124 static void MOVBE_Fixup (int, int);
126 static void OP_Mask (int, int);
129 /* Points to first byte not fetched. */
130 bfd_byte
*max_fetched
;
131 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
134 OPCODES_SIGJMP_BUF bailout
;
144 enum address_mode address_mode
;
146 /* Flags for the prefixes for the current instruction. See below. */
149 /* REX prefix the current instruction. See below. */
151 /* Bits of REX we've already used. */
153 /* REX bits in original REX prefix ignored. */
154 static int rex_ignored
;
155 /* Mark parts used in the REX prefix. When we are testing for
156 empty prefix (for 8bit register REX extension), just mask it
157 out. Otherwise test for REX bit is excuse for existence of REX
158 only in case value is nonzero. */
159 #define USED_REX(value) \
164 rex_used |= (value) | REX_OPCODE; \
167 rex_used |= REX_OPCODE; \
170 /* Flags for prefixes which we somehow handled when printing the
171 current instruction. */
172 static int used_prefixes
;
174 /* Flags stored in PREFIXES. */
175 #define PREFIX_REPZ 1
176 #define PREFIX_REPNZ 2
177 #define PREFIX_LOCK 4
179 #define PREFIX_SS 0x10
180 #define PREFIX_DS 0x20
181 #define PREFIX_ES 0x40
182 #define PREFIX_FS 0x80
183 #define PREFIX_GS 0x100
184 #define PREFIX_DATA 0x200
185 #define PREFIX_ADDR 0x400
186 #define PREFIX_FWAIT 0x800
188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
189 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
191 #define FETCH_DATA(info, addr) \
192 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
193 ? 1 : fetch_data ((info), (addr)))
196 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
199 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
200 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
202 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
203 status
= (*info
->read_memory_func
) (start
,
205 addr
- priv
->max_fetched
,
211 /* If we did manage to read at least one byte, then
212 print_insn_i386 will do something sensible. Otherwise, print
213 an error. We do that here because this is where we know
215 if (priv
->max_fetched
== priv
->the_buffer
)
216 (*info
->memory_error_func
) (status
, start
, info
);
217 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
220 priv
->max_fetched
= addr
;
224 #define XX { NULL, 0 }
225 #define Bad_Opcode NULL, { { NULL, 0 } }
227 #define Eb { OP_E, b_mode }
228 #define Ebnd { OP_E, bnd_mode }
229 #define EbS { OP_E, b_swap_mode }
230 #define Ev { OP_E, v_mode }
231 #define Ev_bnd { OP_E, v_bnd_mode }
232 #define EvS { OP_E, v_swap_mode }
233 #define Ed { OP_E, d_mode }
234 #define Edq { OP_E, dq_mode }
235 #define Edqw { OP_E, dqw_mode }
236 #define EdqwS { OP_E, dqw_swap_mode }
237 #define Edqb { OP_E, dqb_mode }
238 #define Edb { OP_E, db_mode }
239 #define Edw { OP_E, dw_mode }
240 #define Edqd { OP_E, dqd_mode }
241 #define Eq { OP_E, q_mode }
242 #define indirEv { OP_indirE, stack_v_mode }
243 #define indirEp { OP_indirE, f_mode }
244 #define stackEv { OP_E, stack_v_mode }
245 #define Em { OP_E, m_mode }
246 #define Ew { OP_E, w_mode }
247 #define M { OP_M, 0 } /* lea, lgdt, etc. */
248 #define Ma { OP_M, a_mode }
249 #define Mb { OP_M, b_mode }
250 #define Md { OP_M, d_mode }
251 #define Mo { OP_M, o_mode }
252 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
253 #define Mq { OP_M, q_mode }
254 #define Mx { OP_M, x_mode }
255 #define Mxmm { OP_M, xmm_mode }
256 #define Gb { OP_G, b_mode }
257 #define Gbnd { OP_G, bnd_mode }
258 #define Gv { OP_G, v_mode }
259 #define Gd { OP_G, d_mode }
260 #define Gdq { OP_G, dq_mode }
261 #define Gm { OP_G, m_mode }
262 #define Gw { OP_G, w_mode }
263 #define Rd { OP_R, d_mode }
264 #define Rdq { OP_R, dq_mode }
265 #define Rm { OP_R, m_mode }
266 #define Ib { OP_I, b_mode }
267 #define sIb { OP_sI, b_mode } /* sign extened byte */
268 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
269 #define Iv { OP_I, v_mode }
270 #define sIv { OP_sI, v_mode }
271 #define Iq { OP_I, q_mode }
272 #define Iv64 { OP_I64, v_mode }
273 #define Iw { OP_I, w_mode }
274 #define I1 { OP_I, const_1_mode }
275 #define Jb { OP_J, b_mode }
276 #define Jv { OP_J, v_mode }
277 #define Cm { OP_C, m_mode }
278 #define Dm { OP_D, m_mode }
279 #define Td { OP_T, d_mode }
280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
282 #define RMeAX { OP_REG, eAX_reg }
283 #define RMeBX { OP_REG, eBX_reg }
284 #define RMeCX { OP_REG, eCX_reg }
285 #define RMeDX { OP_REG, eDX_reg }
286 #define RMeSP { OP_REG, eSP_reg }
287 #define RMeBP { OP_REG, eBP_reg }
288 #define RMeSI { OP_REG, eSI_reg }
289 #define RMeDI { OP_REG, eDI_reg }
290 #define RMrAX { OP_REG, rAX_reg }
291 #define RMrBX { OP_REG, rBX_reg }
292 #define RMrCX { OP_REG, rCX_reg }
293 #define RMrDX { OP_REG, rDX_reg }
294 #define RMrSP { OP_REG, rSP_reg }
295 #define RMrBP { OP_REG, rBP_reg }
296 #define RMrSI { OP_REG, rSI_reg }
297 #define RMrDI { OP_REG, rDI_reg }
298 #define RMAL { OP_REG, al_reg }
299 #define RMCL { OP_REG, cl_reg }
300 #define RMDL { OP_REG, dl_reg }
301 #define RMBL { OP_REG, bl_reg }
302 #define RMAH { OP_REG, ah_reg }
303 #define RMCH { OP_REG, ch_reg }
304 #define RMDH { OP_REG, dh_reg }
305 #define RMBH { OP_REG, bh_reg }
306 #define RMAX { OP_REG, ax_reg }
307 #define RMDX { OP_REG, dx_reg }
309 #define eAX { OP_IMREG, eAX_reg }
310 #define eBX { OP_IMREG, eBX_reg }
311 #define eCX { OP_IMREG, eCX_reg }
312 #define eDX { OP_IMREG, eDX_reg }
313 #define eSP { OP_IMREG, eSP_reg }
314 #define eBP { OP_IMREG, eBP_reg }
315 #define eSI { OP_IMREG, eSI_reg }
316 #define eDI { OP_IMREG, eDI_reg }
317 #define AL { OP_IMREG, al_reg }
318 #define CL { OP_IMREG, cl_reg }
319 #define DL { OP_IMREG, dl_reg }
320 #define BL { OP_IMREG, bl_reg }
321 #define AH { OP_IMREG, ah_reg }
322 #define CH { OP_IMREG, ch_reg }
323 #define DH { OP_IMREG, dh_reg }
324 #define BH { OP_IMREG, bh_reg }
325 #define AX { OP_IMREG, ax_reg }
326 #define DX { OP_IMREG, dx_reg }
327 #define zAX { OP_IMREG, z_mode_ax_reg }
328 #define indirDX { OP_IMREG, indir_dx_reg }
330 #define Sw { OP_SEG, w_mode }
331 #define Sv { OP_SEG, v_mode }
332 #define Ap { OP_DIR, 0 }
333 #define Ob { OP_OFF64, b_mode }
334 #define Ov { OP_OFF64, v_mode }
335 #define Xb { OP_DSreg, eSI_reg }
336 #define Xv { OP_DSreg, eSI_reg }
337 #define Xz { OP_DSreg, eSI_reg }
338 #define Yb { OP_ESreg, eDI_reg }
339 #define Yv { OP_ESreg, eDI_reg }
340 #define DSBX { OP_DSreg, eBX_reg }
342 #define es { OP_REG, es_reg }
343 #define ss { OP_REG, ss_reg }
344 #define cs { OP_REG, cs_reg }
345 #define ds { OP_REG, ds_reg }
346 #define fs { OP_REG, fs_reg }
347 #define gs { OP_REG, gs_reg }
349 #define MX { OP_MMX, 0 }
350 #define XM { OP_XMM, 0 }
351 #define XMScalar { OP_XMM, scalar_mode }
352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
353 #define XMM { OP_XMM, xmm_mode }
354 #define XMxmmq { OP_XMM, xmmq_mode }
355 #define EM { OP_EM, v_mode }
356 #define EMS { OP_EM, v_swap_mode }
357 #define EMd { OP_EM, d_mode }
358 #define EMx { OP_EM, x_mode }
359 #define EXw { OP_EX, w_mode }
360 #define EXd { OP_EX, d_mode }
361 #define EXdScalar { OP_EX, d_scalar_mode }
362 #define EXdS { OP_EX, d_swap_mode }
363 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
364 #define EXq { OP_EX, q_mode }
365 #define EXqScalar { OP_EX, q_scalar_mode }
366 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
367 #define EXqS { OP_EX, q_swap_mode }
368 #define EXx { OP_EX, x_mode }
369 #define EXxS { OP_EX, x_swap_mode }
370 #define EXxmm { OP_EX, xmm_mode }
371 #define EXymm { OP_EX, ymm_mode }
372 #define EXxmmq { OP_EX, xmmq_mode }
373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
376 #define EXxmm_md { OP_EX, xmm_md_mode }
377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
378 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
379 #define EXxmmdw { OP_EX, xmmdw_mode }
380 #define EXxmmqd { OP_EX, xmmqd_mode }
381 #define EXymmq { OP_EX, ymmq_mode }
382 #define EXVexWdq { OP_EX, vex_w_dq_mode }
383 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
384 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
385 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
386 #define MS { OP_MS, v_mode }
387 #define XS { OP_XS, v_mode }
388 #define EMCq { OP_EMC, q_mode }
389 #define MXC { OP_MXC, 0 }
390 #define OPSUF { OP_3DNowSuffix, 0 }
391 #define CMP { CMP_Fixup, 0 }
392 #define XMM0 { XMM_Fixup, 0 }
393 #define FXSAVE { FXSAVE_Fixup, 0 }
394 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
395 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
397 #define Vex { OP_VEX, vex_mode }
398 #define VexScalar { OP_VEX, vex_scalar_mode }
399 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
400 #define Vex128 { OP_VEX, vex128_mode }
401 #define Vex256 { OP_VEX, vex256_mode }
402 #define VexGdq { OP_VEX, dq_mode }
403 #define VexI4 { VEXI4_Fixup, 0}
404 #define EXdVex { OP_EX_Vex, d_mode }
405 #define EXdVexS { OP_EX_Vex, d_swap_mode }
406 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
407 #define EXqVex { OP_EX_Vex, q_mode }
408 #define EXqVexS { OP_EX_Vex, q_swap_mode }
409 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
410 #define EXVexW { OP_EX_VexW, x_mode }
411 #define EXdVexW { OP_EX_VexW, d_mode }
412 #define EXqVexW { OP_EX_VexW, q_mode }
413 #define EXVexImmW { OP_EX_VexImmW, x_mode }
414 #define XMVex { OP_XMM_Vex, 0 }
415 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
416 #define XMVexW { OP_XMM_VexW, 0 }
417 #define XMVexI4 { OP_REG_VexI4, x_mode }
418 #define PCLMUL { PCLMUL_Fixup, 0 }
419 #define VZERO { VZERO_Fixup, 0 }
420 #define VCMP { VCMP_Fixup, 0 }
421 #define VPCMP { VPCMP_Fixup, 0 }
423 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
424 #define EXxEVexS { OP_Rounding, evex_sae_mode }
426 #define XMask { OP_Mask, mask_mode }
427 #define MaskG { OP_G, mask_mode }
428 #define MaskE { OP_E, mask_mode }
429 #define MaskBDE { OP_E, mask_bd_mode }
430 #define MaskR { OP_R, mask_mode }
431 #define MaskVex { OP_VEX, mask_mode }
433 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
434 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
435 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
436 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
438 /* Used handle "rep" prefix for string instructions. */
439 #define Xbr { REP_Fixup, eSI_reg }
440 #define Xvr { REP_Fixup, eSI_reg }
441 #define Ybr { REP_Fixup, eDI_reg }
442 #define Yvr { REP_Fixup, eDI_reg }
443 #define Yzr { REP_Fixup, eDI_reg }
444 #define indirDXr { REP_Fixup, indir_dx_reg }
445 #define ALr { REP_Fixup, al_reg }
446 #define eAXr { REP_Fixup, eAX_reg }
448 /* Used handle HLE prefix for lockable instructions. */
449 #define Ebh1 { HLE_Fixup1, b_mode }
450 #define Evh1 { HLE_Fixup1, v_mode }
451 #define Ebh2 { HLE_Fixup2, b_mode }
452 #define Evh2 { HLE_Fixup2, v_mode }
453 #define Ebh3 { HLE_Fixup3, b_mode }
454 #define Evh3 { HLE_Fixup3, v_mode }
456 #define BND { BND_Fixup, 0 }
458 #define cond_jump_flag { NULL, cond_jump_mode }
459 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
461 /* bits in sizeflag */
462 #define SUFFIX_ALWAYS 4
470 /* byte operand with operand swapped */
472 /* byte operand, sign extend like 'T' suffix */
474 /* operand size depends on prefixes */
476 /* operand size depends on prefixes with operand swapped */
480 /* double word operand */
482 /* double word operand with operand swapped */
484 /* quad word operand */
486 /* quad word operand with operand swapped */
488 /* ten-byte operand */
490 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
491 broadcast enabled. */
493 /* Similar to x_mode, but with different EVEX mem shifts. */
495 /* Similar to x_mode, but with disabled broadcast. */
497 /* Similar to x_mode, but with operands swapped and disabled broadcast
500 /* 16-byte XMM operand */
502 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
503 memory operand (depending on vector length). Broadcast isn't
506 /* Same as xmmq_mode, but broadcast is allowed. */
507 evex_half_bcst_xmmq_mode
,
508 /* XMM register or byte memory operand */
510 /* XMM register or word memory operand */
512 /* XMM register or double word memory operand */
514 /* XMM register or quad word memory operand */
516 /* XMM register or double/quad word memory operand, depending on
519 /* 16-byte XMM, word, double word or quad word operand. */
521 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
523 /* 32-byte YMM operand */
525 /* quad word, ymmword or zmmword memory operand. */
527 /* 32-byte YMM or 16-byte word operand */
529 /* d_mode in 32bit, q_mode in 64bit mode. */
531 /* pair of v_mode operands */
536 /* operand size depends on REX prefixes. */
538 /* registers like dq_mode, memory like w_mode. */
542 /* 4- or 6-byte pointer operand */
545 /* v_mode for stack-related opcodes. */
547 /* non-quad operand size depends on prefixes */
549 /* 16-byte operand */
551 /* registers like dq_mode, memory like b_mode. */
553 /* registers like d_mode, memory like b_mode. */
555 /* registers like d_mode, memory like w_mode. */
557 /* registers like dq_mode, memory like d_mode. */
559 /* normal vex mode */
561 /* 128bit vex mode */
563 /* 256bit vex mode */
565 /* operand size depends on the VEX.W bit. */
568 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
569 vex_vsib_d_w_dq_mode
,
570 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
572 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
573 vex_vsib_q_w_dq_mode
,
574 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
577 /* scalar, ignore vector length. */
579 /* like d_mode, ignore vector length. */
581 /* like d_swap_mode, ignore vector length. */
583 /* like q_mode, ignore vector length. */
585 /* like q_swap_mode, ignore vector length. */
587 /* like vex_mode, ignore vector length. */
589 /* like vex_w_dq_mode, ignore vector length. */
590 vex_scalar_w_dq_mode
,
592 /* Static rounding. */
594 /* Supress all exceptions. */
597 /* Mask register operand. */
599 /* Mask register operand. */
666 #define FLOAT NULL, { { NULL, FLOATCODE } }
668 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
669 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
670 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
671 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
672 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
673 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
674 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
675 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
676 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
677 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
678 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
679 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
680 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
800 MOD_VEX_0F12_PREFIX_0
,
802 MOD_VEX_0F16_PREFIX_0
,
818 MOD_VEX_0FD7_PREFIX_2
,
819 MOD_VEX_0FE7_PREFIX_2
,
820 MOD_VEX_0FF0_PREFIX_3
,
821 MOD_VEX_0F381A_PREFIX_2
,
822 MOD_VEX_0F382A_PREFIX_2
,
823 MOD_VEX_0F382C_PREFIX_2
,
824 MOD_VEX_0F382D_PREFIX_2
,
825 MOD_VEX_0F382E_PREFIX_2
,
826 MOD_VEX_0F382F_PREFIX_2
,
827 MOD_VEX_0F385A_PREFIX_2
,
828 MOD_VEX_0F388C_PREFIX_2
,
829 MOD_VEX_0F388E_PREFIX_2
,
831 MOD_EVEX_0F10_PREFIX_1
,
832 MOD_EVEX_0F10_PREFIX_3
,
833 MOD_EVEX_0F11_PREFIX_1
,
834 MOD_EVEX_0F11_PREFIX_3
,
835 MOD_EVEX_0F12_PREFIX_0
,
836 MOD_EVEX_0F16_PREFIX_0
,
837 MOD_EVEX_0F38C6_REG_1
,
838 MOD_EVEX_0F38C6_REG_2
,
839 MOD_EVEX_0F38C6_REG_5
,
840 MOD_EVEX_0F38C6_REG_6
,
841 MOD_EVEX_0F38C7_REG_1
,
842 MOD_EVEX_0F38C7_REG_2
,
843 MOD_EVEX_0F38C7_REG_5
,
844 MOD_EVEX_0F38C7_REG_6
1036 PREFIX_VEX_0F71_REG_2
,
1037 PREFIX_VEX_0F71_REG_4
,
1038 PREFIX_VEX_0F71_REG_6
,
1039 PREFIX_VEX_0F72_REG_2
,
1040 PREFIX_VEX_0F72_REG_4
,
1041 PREFIX_VEX_0F72_REG_6
,
1042 PREFIX_VEX_0F73_REG_2
,
1043 PREFIX_VEX_0F73_REG_3
,
1044 PREFIX_VEX_0F73_REG_6
,
1045 PREFIX_VEX_0F73_REG_7
,
1217 PREFIX_VEX_0F38F3_REG_1
,
1218 PREFIX_VEX_0F38F3_REG_2
,
1219 PREFIX_VEX_0F38F3_REG_3
,
1336 PREFIX_EVEX_0F71_REG_2
,
1337 PREFIX_EVEX_0F71_REG_4
,
1338 PREFIX_EVEX_0F71_REG_6
,
1339 PREFIX_EVEX_0F72_REG_0
,
1340 PREFIX_EVEX_0F72_REG_1
,
1341 PREFIX_EVEX_0F72_REG_2
,
1342 PREFIX_EVEX_0F72_REG_4
,
1343 PREFIX_EVEX_0F72_REG_6
,
1344 PREFIX_EVEX_0F73_REG_2
,
1345 PREFIX_EVEX_0F73_REG_3
,
1346 PREFIX_EVEX_0F73_REG_6
,
1347 PREFIX_EVEX_0F73_REG_7
,
1527 PREFIX_EVEX_0F38C6_REG_1
,
1528 PREFIX_EVEX_0F38C6_REG_2
,
1529 PREFIX_EVEX_0F38C6_REG_5
,
1530 PREFIX_EVEX_0F38C6_REG_6
,
1531 PREFIX_EVEX_0F38C7_REG_1
,
1532 PREFIX_EVEX_0F38C7_REG_2
,
1533 PREFIX_EVEX_0F38C7_REG_5
,
1534 PREFIX_EVEX_0F38C7_REG_6
,
1621 THREE_BYTE_0F38
= 0,
1649 VEX_LEN_0F10_P_1
= 0,
1653 VEX_LEN_0F12_P_0_M_0
,
1654 VEX_LEN_0F12_P_0_M_1
,
1657 VEX_LEN_0F16_P_0_M_0
,
1658 VEX_LEN_0F16_P_0_M_1
,
1722 VEX_LEN_0FAE_R_2_M_0
,
1723 VEX_LEN_0FAE_R_3_M_0
,
1732 VEX_LEN_0F381A_P_2_M_0
,
1735 VEX_LEN_0F385A_P_2_M_0
,
1742 VEX_LEN_0F38F3_R_1_P_0
,
1743 VEX_LEN_0F38F3_R_2_P_0
,
1744 VEX_LEN_0F38F3_R_3_P_0
,
1790 VEX_LEN_0FXOP_08_CC
,
1791 VEX_LEN_0FXOP_08_CD
,
1792 VEX_LEN_0FXOP_08_CE
,
1793 VEX_LEN_0FXOP_08_CF
,
1794 VEX_LEN_0FXOP_08_EC
,
1795 VEX_LEN_0FXOP_08_ED
,
1796 VEX_LEN_0FXOP_08_EE
,
1797 VEX_LEN_0FXOP_08_EF
,
1798 VEX_LEN_0FXOP_09_80
,
1832 VEX_W_0F41_P_0_LEN_1
,
1833 VEX_W_0F41_P_2_LEN_1
,
1834 VEX_W_0F42_P_0_LEN_1
,
1835 VEX_W_0F42_P_2_LEN_1
,
1836 VEX_W_0F44_P_0_LEN_0
,
1837 VEX_W_0F44_P_2_LEN_0
,
1838 VEX_W_0F45_P_0_LEN_1
,
1839 VEX_W_0F45_P_2_LEN_1
,
1840 VEX_W_0F46_P_0_LEN_1
,
1841 VEX_W_0F46_P_2_LEN_1
,
1842 VEX_W_0F47_P_0_LEN_1
,
1843 VEX_W_0F47_P_2_LEN_1
,
1844 VEX_W_0F4A_P_0_LEN_1
,
1845 VEX_W_0F4A_P_2_LEN_1
,
1846 VEX_W_0F4B_P_0_LEN_1
,
1847 VEX_W_0F4B_P_2_LEN_1
,
1927 VEX_W_0F90_P_0_LEN_0
,
1928 VEX_W_0F90_P_2_LEN_0
,
1929 VEX_W_0F91_P_0_LEN_0
,
1930 VEX_W_0F91_P_2_LEN_0
,
1931 VEX_W_0F92_P_0_LEN_0
,
1932 VEX_W_0F92_P_2_LEN_0
,
1933 VEX_W_0F92_P_3_LEN_0
,
1934 VEX_W_0F93_P_0_LEN_0
,
1935 VEX_W_0F93_P_2_LEN_0
,
1936 VEX_W_0F93_P_3_LEN_0
,
1937 VEX_W_0F98_P_0_LEN_0
,
1938 VEX_W_0F98_P_2_LEN_0
,
1939 VEX_W_0F99_P_0_LEN_0
,
1940 VEX_W_0F99_P_2_LEN_0
,
2019 VEX_W_0F381A_P_2_M_0
,
2031 VEX_W_0F382A_P_2_M_0
,
2033 VEX_W_0F382C_P_2_M_0
,
2034 VEX_W_0F382D_P_2_M_0
,
2035 VEX_W_0F382E_P_2_M_0
,
2036 VEX_W_0F382F_P_2_M_0
,
2058 VEX_W_0F385A_P_2_M_0
,
2086 VEX_W_0F3A30_P_2_LEN_0
,
2087 VEX_W_0F3A31_P_2_LEN_0
,
2088 VEX_W_0F3A32_P_2_LEN_0
,
2089 VEX_W_0F3A33_P_2_LEN_0
,
2109 EVEX_W_0F10_P_1_M_0
,
2110 EVEX_W_0F10_P_1_M_1
,
2112 EVEX_W_0F10_P_3_M_0
,
2113 EVEX_W_0F10_P_3_M_1
,
2115 EVEX_W_0F11_P_1_M_0
,
2116 EVEX_W_0F11_P_1_M_1
,
2118 EVEX_W_0F11_P_3_M_0
,
2119 EVEX_W_0F11_P_3_M_1
,
2120 EVEX_W_0F12_P_0_M_0
,
2121 EVEX_W_0F12_P_0_M_1
,
2131 EVEX_W_0F16_P_0_M_0
,
2132 EVEX_W_0F16_P_0_M_1
,
2203 EVEX_W_0F72_R_2_P_2
,
2204 EVEX_W_0F72_R_6_P_2
,
2205 EVEX_W_0F73_R_2_P_2
,
2206 EVEX_W_0F73_R_6_P_2
,
2305 EVEX_W_0F38C7_R_1_P_2
,
2306 EVEX_W_0F38C7_R_2_P_2
,
2307 EVEX_W_0F38C7_R_5_P_2
,
2308 EVEX_W_0F38C7_R_6_P_2
,
2343 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2354 /* Upper case letters in the instruction names here are macros.
2355 'A' => print 'b' if no register operands or suffix_always is true
2356 'B' => print 'b' if suffix_always is true
2357 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2359 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2360 suffix_always is true
2361 'E' => print 'e' if 32-bit form of jcxz
2362 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2363 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2364 'H' => print ",pt" or ",pn" branch hint
2365 'I' => honor following macro letter even in Intel mode (implemented only
2366 for some of the macro letters)
2368 'K' => print 'd' or 'q' if rex prefix is present.
2369 'L' => print 'l' if suffix_always is true
2370 'M' => print 'r' if intel_mnemonic is false.
2371 'N' => print 'n' if instruction has no wait "prefix"
2372 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2373 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2374 or suffix_always is true. print 'q' if rex prefix is present.
2375 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2377 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2378 'S' => print 'w', 'l' or 'q' if suffix_always is true
2379 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2380 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2381 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2382 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2383 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2384 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2385 suffix_always is true.
2386 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2387 '!' => change condition from true to false or from false to true.
2388 '%' => add 1 upper case letter to the macro.
2390 2 upper case letter macros:
2391 "XY" => print 'x' or 'y' if no register operands or suffix_always
2393 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2394 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2395 or suffix_always is true
2396 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2397 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2398 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2399 "LW" => print 'd', 'q' depending on the VEX.W bit
2401 Many of the above letters print nothing in Intel mode. See "putop"
2404 Braces '{' and '}', and vertical bars '|', indicate alternative
2405 mnemonic strings for AT&T and Intel. */
2407 static const struct dis386 dis386
[] = {
2409 { "addB", { Ebh1
, Gb
} },
2410 { "addS", { Evh1
, Gv
} },
2411 { "addB", { Gb
, EbS
} },
2412 { "addS", { Gv
, EvS
} },
2413 { "addB", { AL
, Ib
} },
2414 { "addS", { eAX
, Iv
} },
2415 { X86_64_TABLE (X86_64_06
) },
2416 { X86_64_TABLE (X86_64_07
) },
2418 { "orB", { Ebh1
, Gb
} },
2419 { "orS", { Evh1
, Gv
} },
2420 { "orB", { Gb
, EbS
} },
2421 { "orS", { Gv
, EvS
} },
2422 { "orB", { AL
, Ib
} },
2423 { "orS", { eAX
, Iv
} },
2424 { X86_64_TABLE (X86_64_0D
) },
2425 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2427 { "adcB", { Ebh1
, Gb
} },
2428 { "adcS", { Evh1
, Gv
} },
2429 { "adcB", { Gb
, EbS
} },
2430 { "adcS", { Gv
, EvS
} },
2431 { "adcB", { AL
, Ib
} },
2432 { "adcS", { eAX
, Iv
} },
2433 { X86_64_TABLE (X86_64_16
) },
2434 { X86_64_TABLE (X86_64_17
) },
2436 { "sbbB", { Ebh1
, Gb
} },
2437 { "sbbS", { Evh1
, Gv
} },
2438 { "sbbB", { Gb
, EbS
} },
2439 { "sbbS", { Gv
, EvS
} },
2440 { "sbbB", { AL
, Ib
} },
2441 { "sbbS", { eAX
, Iv
} },
2442 { X86_64_TABLE (X86_64_1E
) },
2443 { X86_64_TABLE (X86_64_1F
) },
2445 { "andB", { Ebh1
, Gb
} },
2446 { "andS", { Evh1
, Gv
} },
2447 { "andB", { Gb
, EbS
} },
2448 { "andS", { Gv
, EvS
} },
2449 { "andB", { AL
, Ib
} },
2450 { "andS", { eAX
, Iv
} },
2451 { Bad_Opcode
}, /* SEG ES prefix */
2452 { X86_64_TABLE (X86_64_27
) },
2454 { "subB", { Ebh1
, Gb
} },
2455 { "subS", { Evh1
, Gv
} },
2456 { "subB", { Gb
, EbS
} },
2457 { "subS", { Gv
, EvS
} },
2458 { "subB", { AL
, Ib
} },
2459 { "subS", { eAX
, Iv
} },
2460 { Bad_Opcode
}, /* SEG CS prefix */
2461 { X86_64_TABLE (X86_64_2F
) },
2463 { "xorB", { Ebh1
, Gb
} },
2464 { "xorS", { Evh1
, Gv
} },
2465 { "xorB", { Gb
, EbS
} },
2466 { "xorS", { Gv
, EvS
} },
2467 { "xorB", { AL
, Ib
} },
2468 { "xorS", { eAX
, Iv
} },
2469 { Bad_Opcode
}, /* SEG SS prefix */
2470 { X86_64_TABLE (X86_64_37
) },
2472 { "cmpB", { Eb
, Gb
} },
2473 { "cmpS", { Ev
, Gv
} },
2474 { "cmpB", { Gb
, EbS
} },
2475 { "cmpS", { Gv
, EvS
} },
2476 { "cmpB", { AL
, Ib
} },
2477 { "cmpS", { eAX
, Iv
} },
2478 { Bad_Opcode
}, /* SEG DS prefix */
2479 { X86_64_TABLE (X86_64_3F
) },
2481 { "inc{S|}", { RMeAX
} },
2482 { "inc{S|}", { RMeCX
} },
2483 { "inc{S|}", { RMeDX
} },
2484 { "inc{S|}", { RMeBX
} },
2485 { "inc{S|}", { RMeSP
} },
2486 { "inc{S|}", { RMeBP
} },
2487 { "inc{S|}", { RMeSI
} },
2488 { "inc{S|}", { RMeDI
} },
2490 { "dec{S|}", { RMeAX
} },
2491 { "dec{S|}", { RMeCX
} },
2492 { "dec{S|}", { RMeDX
} },
2493 { "dec{S|}", { RMeBX
} },
2494 { "dec{S|}", { RMeSP
} },
2495 { "dec{S|}", { RMeBP
} },
2496 { "dec{S|}", { RMeSI
} },
2497 { "dec{S|}", { RMeDI
} },
2499 { "pushV", { RMrAX
} },
2500 { "pushV", { RMrCX
} },
2501 { "pushV", { RMrDX
} },
2502 { "pushV", { RMrBX
} },
2503 { "pushV", { RMrSP
} },
2504 { "pushV", { RMrBP
} },
2505 { "pushV", { RMrSI
} },
2506 { "pushV", { RMrDI
} },
2508 { "popV", { RMrAX
} },
2509 { "popV", { RMrCX
} },
2510 { "popV", { RMrDX
} },
2511 { "popV", { RMrBX
} },
2512 { "popV", { RMrSP
} },
2513 { "popV", { RMrBP
} },
2514 { "popV", { RMrSI
} },
2515 { "popV", { RMrDI
} },
2517 { X86_64_TABLE (X86_64_60
) },
2518 { X86_64_TABLE (X86_64_61
) },
2519 { X86_64_TABLE (X86_64_62
) },
2520 { X86_64_TABLE (X86_64_63
) },
2521 { Bad_Opcode
}, /* seg fs */
2522 { Bad_Opcode
}, /* seg gs */
2523 { Bad_Opcode
}, /* op size prefix */
2524 { Bad_Opcode
}, /* adr size prefix */
2526 { "pushT", { sIv
} },
2527 { "imulS", { Gv
, Ev
, Iv
} },
2528 { "pushT", { sIbT
} },
2529 { "imulS", { Gv
, Ev
, sIb
} },
2530 { "ins{b|}", { Ybr
, indirDX
} },
2531 { X86_64_TABLE (X86_64_6D
) },
2532 { "outs{b|}", { indirDXr
, Xb
} },
2533 { X86_64_TABLE (X86_64_6F
) },
2535 { "joH", { Jb
, BND
, cond_jump_flag
} },
2536 { "jnoH", { Jb
, BND
, cond_jump_flag
} },
2537 { "jbH", { Jb
, BND
, cond_jump_flag
} },
2538 { "jaeH", { Jb
, BND
, cond_jump_flag
} },
2539 { "jeH", { Jb
, BND
, cond_jump_flag
} },
2540 { "jneH", { Jb
, BND
, cond_jump_flag
} },
2541 { "jbeH", { Jb
, BND
, cond_jump_flag
} },
2542 { "jaH", { Jb
, BND
, cond_jump_flag
} },
2544 { "jsH", { Jb
, BND
, cond_jump_flag
} },
2545 { "jnsH", { Jb
, BND
, cond_jump_flag
} },
2546 { "jpH", { Jb
, BND
, cond_jump_flag
} },
2547 { "jnpH", { Jb
, BND
, cond_jump_flag
} },
2548 { "jlH", { Jb
, BND
, cond_jump_flag
} },
2549 { "jgeH", { Jb
, BND
, cond_jump_flag
} },
2550 { "jleH", { Jb
, BND
, cond_jump_flag
} },
2551 { "jgH", { Jb
, BND
, cond_jump_flag
} },
2553 { REG_TABLE (REG_80
) },
2554 { REG_TABLE (REG_81
) },
2556 { REG_TABLE (REG_82
) },
2557 { "testB", { Eb
, Gb
} },
2558 { "testS", { Ev
, Gv
} },
2559 { "xchgB", { Ebh2
, Gb
} },
2560 { "xchgS", { Evh2
, Gv
} },
2562 { "movB", { Ebh3
, Gb
} },
2563 { "movS", { Evh3
, Gv
} },
2564 { "movB", { Gb
, EbS
} },
2565 { "movS", { Gv
, EvS
} },
2566 { "movD", { Sv
, Sw
} },
2567 { MOD_TABLE (MOD_8D
) },
2568 { "movD", { Sw
, Sv
} },
2569 { REG_TABLE (REG_8F
) },
2571 { PREFIX_TABLE (PREFIX_90
) },
2572 { "xchgS", { RMeCX
, eAX
} },
2573 { "xchgS", { RMeDX
, eAX
} },
2574 { "xchgS", { RMeBX
, eAX
} },
2575 { "xchgS", { RMeSP
, eAX
} },
2576 { "xchgS", { RMeBP
, eAX
} },
2577 { "xchgS", { RMeSI
, eAX
} },
2578 { "xchgS", { RMeDI
, eAX
} },
2580 { "cW{t|}R", { XX
} },
2581 { "cR{t|}O", { XX
} },
2582 { X86_64_TABLE (X86_64_9A
) },
2583 { Bad_Opcode
}, /* fwait */
2584 { "pushfT", { XX
} },
2585 { "popfT", { XX
} },
2589 { "mov%LB", { AL
, Ob
} },
2590 { "mov%LS", { eAX
, Ov
} },
2591 { "mov%LB", { Ob
, AL
} },
2592 { "mov%LS", { Ov
, eAX
} },
2593 { "movs{b|}", { Ybr
, Xb
} },
2594 { "movs{R|}", { Yvr
, Xv
} },
2595 { "cmps{b|}", { Xb
, Yb
} },
2596 { "cmps{R|}", { Xv
, Yv
} },
2598 { "testB", { AL
, Ib
} },
2599 { "testS", { eAX
, Iv
} },
2600 { "stosB", { Ybr
, AL
} },
2601 { "stosS", { Yvr
, eAX
} },
2602 { "lodsB", { ALr
, Xb
} },
2603 { "lodsS", { eAXr
, Xv
} },
2604 { "scasB", { AL
, Yb
} },
2605 { "scasS", { eAX
, Yv
} },
2607 { "movB", { RMAL
, Ib
} },
2608 { "movB", { RMCL
, Ib
} },
2609 { "movB", { RMDL
, Ib
} },
2610 { "movB", { RMBL
, Ib
} },
2611 { "movB", { RMAH
, Ib
} },
2612 { "movB", { RMCH
, Ib
} },
2613 { "movB", { RMDH
, Ib
} },
2614 { "movB", { RMBH
, Ib
} },
2616 { "mov%LV", { RMeAX
, Iv64
} },
2617 { "mov%LV", { RMeCX
, Iv64
} },
2618 { "mov%LV", { RMeDX
, Iv64
} },
2619 { "mov%LV", { RMeBX
, Iv64
} },
2620 { "mov%LV", { RMeSP
, Iv64
} },
2621 { "mov%LV", { RMeBP
, Iv64
} },
2622 { "mov%LV", { RMeSI
, Iv64
} },
2623 { "mov%LV", { RMeDI
, Iv64
} },
2625 { REG_TABLE (REG_C0
) },
2626 { REG_TABLE (REG_C1
) },
2627 { "retT", { Iw
, BND
} },
2628 { "retT", { BND
} },
2629 { X86_64_TABLE (X86_64_C4
) },
2630 { X86_64_TABLE (X86_64_C5
) },
2631 { REG_TABLE (REG_C6
) },
2632 { REG_TABLE (REG_C7
) },
2634 { "enterT", { Iw
, Ib
} },
2635 { "leaveT", { XX
} },
2636 { "Jret{|f}P", { Iw
} },
2637 { "Jret{|f}P", { XX
} },
2640 { X86_64_TABLE (X86_64_CE
) },
2641 { "iretP", { XX
} },
2643 { REG_TABLE (REG_D0
) },
2644 { REG_TABLE (REG_D1
) },
2645 { REG_TABLE (REG_D2
) },
2646 { REG_TABLE (REG_D3
) },
2647 { X86_64_TABLE (X86_64_D4
) },
2648 { X86_64_TABLE (X86_64_D5
) },
2650 { "xlat", { DSBX
} },
2661 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
} },
2662 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
} },
2663 { "loopFH", { Jb
, XX
, loop_jcxz_flag
} },
2664 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
} },
2665 { "inB", { AL
, Ib
} },
2666 { "inG", { zAX
, Ib
} },
2667 { "outB", { Ib
, AL
} },
2668 { "outG", { Ib
, zAX
} },
2670 { "callT", { Jv
, BND
} },
2671 { "jmpT", { Jv
, BND
} },
2672 { X86_64_TABLE (X86_64_EA
) },
2673 { "jmp", { Jb
, BND
} },
2674 { "inB", { AL
, indirDX
} },
2675 { "inG", { zAX
, indirDX
} },
2676 { "outB", { indirDX
, AL
} },
2677 { "outG", { indirDX
, zAX
} },
2679 { Bad_Opcode
}, /* lock prefix */
2680 { "icebp", { XX
} },
2681 { Bad_Opcode
}, /* repne */
2682 { Bad_Opcode
}, /* repz */
2685 { REG_TABLE (REG_F6
) },
2686 { REG_TABLE (REG_F7
) },
2694 { REG_TABLE (REG_FE
) },
2695 { REG_TABLE (REG_FF
) },
2698 static const struct dis386 dis386_twobyte
[] = {
2700 { REG_TABLE (REG_0F00
) },
2701 { REG_TABLE (REG_0F01
) },
2702 { "larS", { Gv
, Ew
} },
2703 { "lslS", { Gv
, Ew
} },
2705 { "syscall", { XX
} },
2707 { "sysretP", { XX
} },
2710 { "wbinvd", { XX
} },
2714 { REG_TABLE (REG_0F0D
) },
2715 { "femms", { XX
} },
2716 { "", { MX
, EM
, OPSUF
} }, /* See OP_3DNowSuffix. */
2718 { PREFIX_TABLE (PREFIX_0F10
) },
2719 { PREFIX_TABLE (PREFIX_0F11
) },
2720 { PREFIX_TABLE (PREFIX_0F12
) },
2721 { MOD_TABLE (MOD_0F13
) },
2722 { "unpcklpX", { XM
, EXx
} },
2723 { "unpckhpX", { XM
, EXx
} },
2724 { PREFIX_TABLE (PREFIX_0F16
) },
2725 { MOD_TABLE (MOD_0F17
) },
2727 { REG_TABLE (REG_0F18
) },
2729 { PREFIX_TABLE (PREFIX_0F1A
) },
2730 { PREFIX_TABLE (PREFIX_0F1B
) },
2736 { MOD_TABLE (MOD_0F20
) },
2737 { MOD_TABLE (MOD_0F21
) },
2738 { MOD_TABLE (MOD_0F22
) },
2739 { MOD_TABLE (MOD_0F23
) },
2740 { MOD_TABLE (MOD_0F24
) },
2742 { MOD_TABLE (MOD_0F26
) },
2745 { "movapX", { XM
, EXx
} },
2746 { "movapX", { EXxS
, XM
} },
2747 { PREFIX_TABLE (PREFIX_0F2A
) },
2748 { PREFIX_TABLE (PREFIX_0F2B
) },
2749 { PREFIX_TABLE (PREFIX_0F2C
) },
2750 { PREFIX_TABLE (PREFIX_0F2D
) },
2751 { PREFIX_TABLE (PREFIX_0F2E
) },
2752 { PREFIX_TABLE (PREFIX_0F2F
) },
2754 { "wrmsr", { XX
} },
2755 { "rdtsc", { XX
} },
2756 { "rdmsr", { XX
} },
2757 { "rdpmc", { XX
} },
2758 { "sysenter", { XX
} },
2759 { "sysexit", { XX
} },
2761 { "getsec", { XX
} },
2763 { THREE_BYTE_TABLE (THREE_BYTE_0F38
) },
2765 { THREE_BYTE_TABLE (THREE_BYTE_0F3A
) },
2772 { "cmovoS", { Gv
, Ev
} },
2773 { "cmovnoS", { Gv
, Ev
} },
2774 { "cmovbS", { Gv
, Ev
} },
2775 { "cmovaeS", { Gv
, Ev
} },
2776 { "cmoveS", { Gv
, Ev
} },
2777 { "cmovneS", { Gv
, Ev
} },
2778 { "cmovbeS", { Gv
, Ev
} },
2779 { "cmovaS", { Gv
, Ev
} },
2781 { "cmovsS", { Gv
, Ev
} },
2782 { "cmovnsS", { Gv
, Ev
} },
2783 { "cmovpS", { Gv
, Ev
} },
2784 { "cmovnpS", { Gv
, Ev
} },
2785 { "cmovlS", { Gv
, Ev
} },
2786 { "cmovgeS", { Gv
, Ev
} },
2787 { "cmovleS", { Gv
, Ev
} },
2788 { "cmovgS", { Gv
, Ev
} },
2790 { MOD_TABLE (MOD_0F51
) },
2791 { PREFIX_TABLE (PREFIX_0F51
) },
2792 { PREFIX_TABLE (PREFIX_0F52
) },
2793 { PREFIX_TABLE (PREFIX_0F53
) },
2794 { "andpX", { XM
, EXx
} },
2795 { "andnpX", { XM
, EXx
} },
2796 { "orpX", { XM
, EXx
} },
2797 { "xorpX", { XM
, EXx
} },
2799 { PREFIX_TABLE (PREFIX_0F58
) },
2800 { PREFIX_TABLE (PREFIX_0F59
) },
2801 { PREFIX_TABLE (PREFIX_0F5A
) },
2802 { PREFIX_TABLE (PREFIX_0F5B
) },
2803 { PREFIX_TABLE (PREFIX_0F5C
) },
2804 { PREFIX_TABLE (PREFIX_0F5D
) },
2805 { PREFIX_TABLE (PREFIX_0F5E
) },
2806 { PREFIX_TABLE (PREFIX_0F5F
) },
2808 { PREFIX_TABLE (PREFIX_0F60
) },
2809 { PREFIX_TABLE (PREFIX_0F61
) },
2810 { PREFIX_TABLE (PREFIX_0F62
) },
2811 { "packsswb", { MX
, EM
} },
2812 { "pcmpgtb", { MX
, EM
} },
2813 { "pcmpgtw", { MX
, EM
} },
2814 { "pcmpgtd", { MX
, EM
} },
2815 { "packuswb", { MX
, EM
} },
2817 { "punpckhbw", { MX
, EM
} },
2818 { "punpckhwd", { MX
, EM
} },
2819 { "punpckhdq", { MX
, EM
} },
2820 { "packssdw", { MX
, EM
} },
2821 { PREFIX_TABLE (PREFIX_0F6C
) },
2822 { PREFIX_TABLE (PREFIX_0F6D
) },
2823 { "movK", { MX
, Edq
} },
2824 { PREFIX_TABLE (PREFIX_0F6F
) },
2826 { PREFIX_TABLE (PREFIX_0F70
) },
2827 { REG_TABLE (REG_0F71
) },
2828 { REG_TABLE (REG_0F72
) },
2829 { REG_TABLE (REG_0F73
) },
2830 { "pcmpeqb", { MX
, EM
} },
2831 { "pcmpeqw", { MX
, EM
} },
2832 { "pcmpeqd", { MX
, EM
} },
2835 { PREFIX_TABLE (PREFIX_0F78
) },
2836 { PREFIX_TABLE (PREFIX_0F79
) },
2837 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2839 { PREFIX_TABLE (PREFIX_0F7C
) },
2840 { PREFIX_TABLE (PREFIX_0F7D
) },
2841 { PREFIX_TABLE (PREFIX_0F7E
) },
2842 { PREFIX_TABLE (PREFIX_0F7F
) },
2844 { "joH", { Jv
, BND
, cond_jump_flag
} },
2845 { "jnoH", { Jv
, BND
, cond_jump_flag
} },
2846 { "jbH", { Jv
, BND
, cond_jump_flag
} },
2847 { "jaeH", { Jv
, BND
, cond_jump_flag
} },
2848 { "jeH", { Jv
, BND
, cond_jump_flag
} },
2849 { "jneH", { Jv
, BND
, cond_jump_flag
} },
2850 { "jbeH", { Jv
, BND
, cond_jump_flag
} },
2851 { "jaH", { Jv
, BND
, cond_jump_flag
} },
2853 { "jsH", { Jv
, BND
, cond_jump_flag
} },
2854 { "jnsH", { Jv
, BND
, cond_jump_flag
} },
2855 { "jpH", { Jv
, BND
, cond_jump_flag
} },
2856 { "jnpH", { Jv
, BND
, cond_jump_flag
} },
2857 { "jlH", { Jv
, BND
, cond_jump_flag
} },
2858 { "jgeH", { Jv
, BND
, cond_jump_flag
} },
2859 { "jleH", { Jv
, BND
, cond_jump_flag
} },
2860 { "jgH", { Jv
, BND
, cond_jump_flag
} },
2863 { "setno", { Eb
} },
2865 { "setae", { Eb
} },
2867 { "setne", { Eb
} },
2868 { "setbe", { Eb
} },
2872 { "setns", { Eb
} },
2874 { "setnp", { Eb
} },
2876 { "setge", { Eb
} },
2877 { "setle", { Eb
} },
2880 { "pushT", { fs
} },
2882 { "cpuid", { XX
} },
2883 { "btS", { Ev
, Gv
} },
2884 { "shldS", { Ev
, Gv
, Ib
} },
2885 { "shldS", { Ev
, Gv
, CL
} },
2886 { REG_TABLE (REG_0FA6
) },
2887 { REG_TABLE (REG_0FA7
) },
2889 { "pushT", { gs
} },
2892 { "btsS", { Evh1
, Gv
} },
2893 { "shrdS", { Ev
, Gv
, Ib
} },
2894 { "shrdS", { Ev
, Gv
, CL
} },
2895 { REG_TABLE (REG_0FAE
) },
2896 { "imulS", { Gv
, Ev
} },
2898 { "cmpxchgB", { Ebh1
, Gb
} },
2899 { "cmpxchgS", { Evh1
, Gv
} },
2900 { MOD_TABLE (MOD_0FB2
) },
2901 { "btrS", { Evh1
, Gv
} },
2902 { MOD_TABLE (MOD_0FB4
) },
2903 { MOD_TABLE (MOD_0FB5
) },
2904 { "movz{bR|x}", { Gv
, Eb
} },
2905 { "movz{wR|x}", { Gv
, Ew
} }, /* yes, there really is movzww ! */
2907 { PREFIX_TABLE (PREFIX_0FB8
) },
2909 { REG_TABLE (REG_0FBA
) },
2910 { "btcS", { Evh1
, Gv
} },
2911 { PREFIX_TABLE (PREFIX_0FBC
) },
2912 { PREFIX_TABLE (PREFIX_0FBD
) },
2913 { "movs{bR|x}", { Gv
, Eb
} },
2914 { "movs{wR|x}", { Gv
, Ew
} }, /* yes, there really is movsww ! */
2916 { "xaddB", { Ebh1
, Gb
} },
2917 { "xaddS", { Evh1
, Gv
} },
2918 { PREFIX_TABLE (PREFIX_0FC2
) },
2919 { PREFIX_TABLE (PREFIX_0FC3
) },
2920 { "pinsrw", { MX
, Edqw
, Ib
} },
2921 { "pextrw", { Gdq
, MS
, Ib
} },
2922 { "shufpX", { XM
, EXx
, Ib
} },
2923 { REG_TABLE (REG_0FC7
) },
2925 { "bswap", { RMeAX
} },
2926 { "bswap", { RMeCX
} },
2927 { "bswap", { RMeDX
} },
2928 { "bswap", { RMeBX
} },
2929 { "bswap", { RMeSP
} },
2930 { "bswap", { RMeBP
} },
2931 { "bswap", { RMeSI
} },
2932 { "bswap", { RMeDI
} },
2934 { PREFIX_TABLE (PREFIX_0FD0
) },
2935 { "psrlw", { MX
, EM
} },
2936 { "psrld", { MX
, EM
} },
2937 { "psrlq", { MX
, EM
} },
2938 { "paddq", { MX
, EM
} },
2939 { "pmullw", { MX
, EM
} },
2940 { PREFIX_TABLE (PREFIX_0FD6
) },
2941 { MOD_TABLE (MOD_0FD7
) },
2943 { "psubusb", { MX
, EM
} },
2944 { "psubusw", { MX
, EM
} },
2945 { "pminub", { MX
, EM
} },
2946 { "pand", { MX
, EM
} },
2947 { "paddusb", { MX
, EM
} },
2948 { "paddusw", { MX
, EM
} },
2949 { "pmaxub", { MX
, EM
} },
2950 { "pandn", { MX
, EM
} },
2952 { "pavgb", { MX
, EM
} },
2953 { "psraw", { MX
, EM
} },
2954 { "psrad", { MX
, EM
} },
2955 { "pavgw", { MX
, EM
} },
2956 { "pmulhuw", { MX
, EM
} },
2957 { "pmulhw", { MX
, EM
} },
2958 { PREFIX_TABLE (PREFIX_0FE6
) },
2959 { PREFIX_TABLE (PREFIX_0FE7
) },
2961 { "psubsb", { MX
, EM
} },
2962 { "psubsw", { MX
, EM
} },
2963 { "pminsw", { MX
, EM
} },
2964 { "por", { MX
, EM
} },
2965 { "paddsb", { MX
, EM
} },
2966 { "paddsw", { MX
, EM
} },
2967 { "pmaxsw", { MX
, EM
} },
2968 { "pxor", { MX
, EM
} },
2970 { PREFIX_TABLE (PREFIX_0FF0
) },
2971 { "psllw", { MX
, EM
} },
2972 { "pslld", { MX
, EM
} },
2973 { "psllq", { MX
, EM
} },
2974 { "pmuludq", { MX
, EM
} },
2975 { "pmaddwd", { MX
, EM
} },
2976 { "psadbw", { MX
, EM
} },
2977 { PREFIX_TABLE (PREFIX_0FF7
) },
2979 { "psubb", { MX
, EM
} },
2980 { "psubw", { MX
, EM
} },
2981 { "psubd", { MX
, EM
} },
2982 { "psubq", { MX
, EM
} },
2983 { "paddb", { MX
, EM
} },
2984 { "paddw", { MX
, EM
} },
2985 { "paddd", { MX
, EM
} },
2989 static const unsigned char onebyte_has_modrm
[256] = {
2990 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2991 /* ------------------------------- */
2992 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2993 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2994 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2995 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2996 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2997 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2998 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2999 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3000 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3001 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3002 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3003 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3004 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3005 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3006 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3007 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3008 /* ------------------------------- */
3009 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3012 static const unsigned char twobyte_has_modrm
[256] = {
3013 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3014 /* ------------------------------- */
3015 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3016 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3017 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3018 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3019 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3020 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3021 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3022 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3023 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3024 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3025 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3026 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3027 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3028 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3029 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3030 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3031 /* ------------------------------- */
3032 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3035 static const unsigned char twobyte_has_mandatory_prefix
[256] = {
3036 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3037 /* ------------------------------- */
3038 /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
3039 /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
3040 /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
3041 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3042 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
3043 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3044 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3045 /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
3046 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3047 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
3048 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
3049 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
3050 /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
3051 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3052 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3053 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3054 /* ------------------------------- */
3055 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3058 static char obuf
[100];
3060 static char *mnemonicendp
;
3061 static char scratchbuf
[100];
3062 static unsigned char *start_codep
;
3063 static unsigned char *insn_codep
;
3064 static unsigned char *codep
;
3065 static unsigned char *end_codep
;
3066 static int last_lock_prefix
;
3067 static int last_repz_prefix
;
3068 static int last_repnz_prefix
;
3069 static int last_data_prefix
;
3070 static int last_addr_prefix
;
3071 static int last_rex_prefix
;
3072 static int last_seg_prefix
;
3073 static int fwait_prefix
;
3074 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory. */
3075 static int mandatory_prefix
;
3076 /* The active segment register prefix. */
3077 static int active_seg_prefix
;
3078 #define MAX_CODE_LENGTH 15
3079 /* We can up to 14 prefixes since the maximum instruction length is
3081 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3082 static disassemble_info
*the_info
;
3090 static unsigned char need_modrm
;
3100 int register_specifier
;
3107 int mask_register_specifier
;
3113 static unsigned char need_vex
;
3114 static unsigned char need_vex_reg
;
3115 static unsigned char vex_w_done
;
3123 /* If we are accessing mod/rm/reg without need_modrm set, then the
3124 values are stale. Hitting this abort likely indicates that you
3125 need to update onebyte_has_modrm or twobyte_has_modrm. */
3126 #define MODRM_CHECK if (!need_modrm) abort ()
3128 static const char **names64
;
3129 static const char **names32
;
3130 static const char **names16
;
3131 static const char **names8
;
3132 static const char **names8rex
;
3133 static const char **names_seg
;
3134 static const char *index64
;
3135 static const char *index32
;
3136 static const char **index16
;
3137 static const char **names_bnd
;
3139 static const char *intel_names64
[] = {
3140 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3141 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3143 static const char *intel_names32
[] = {
3144 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3145 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3147 static const char *intel_names16
[] = {
3148 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3149 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3151 static const char *intel_names8
[] = {
3152 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3154 static const char *intel_names8rex
[] = {
3155 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3156 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3158 static const char *intel_names_seg
[] = {
3159 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3161 static const char *intel_index64
= "riz";
3162 static const char *intel_index32
= "eiz";
3163 static const char *intel_index16
[] = {
3164 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3167 static const char *att_names64
[] = {
3168 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3169 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3171 static const char *att_names32
[] = {
3172 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3173 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3175 static const char *att_names16
[] = {
3176 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3177 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3179 static const char *att_names8
[] = {
3180 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3182 static const char *att_names8rex
[] = {
3183 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3184 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3186 static const char *att_names_seg
[] = {
3187 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3189 static const char *att_index64
= "%riz";
3190 static const char *att_index32
= "%eiz";
3191 static const char *att_index16
[] = {
3192 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3195 static const char **names_mm
;
3196 static const char *intel_names_mm
[] = {
3197 "mm0", "mm1", "mm2", "mm3",
3198 "mm4", "mm5", "mm6", "mm7"
3200 static const char *att_names_mm
[] = {
3201 "%mm0", "%mm1", "%mm2", "%mm3",
3202 "%mm4", "%mm5", "%mm6", "%mm7"
3205 static const char *intel_names_bnd
[] = {
3206 "bnd0", "bnd1", "bnd2", "bnd3"
3209 static const char *att_names_bnd
[] = {
3210 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3213 static const char **names_xmm
;
3214 static const char *intel_names_xmm
[] = {
3215 "xmm0", "xmm1", "xmm2", "xmm3",
3216 "xmm4", "xmm5", "xmm6", "xmm7",
3217 "xmm8", "xmm9", "xmm10", "xmm11",
3218 "xmm12", "xmm13", "xmm14", "xmm15",
3219 "xmm16", "xmm17", "xmm18", "xmm19",
3220 "xmm20", "xmm21", "xmm22", "xmm23",
3221 "xmm24", "xmm25", "xmm26", "xmm27",
3222 "xmm28", "xmm29", "xmm30", "xmm31"
3224 static const char *att_names_xmm
[] = {
3225 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3226 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3227 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3228 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3229 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3230 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3231 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3232 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3235 static const char **names_ymm
;
3236 static const char *intel_names_ymm
[] = {
3237 "ymm0", "ymm1", "ymm2", "ymm3",
3238 "ymm4", "ymm5", "ymm6", "ymm7",
3239 "ymm8", "ymm9", "ymm10", "ymm11",
3240 "ymm12", "ymm13", "ymm14", "ymm15",
3241 "ymm16", "ymm17", "ymm18", "ymm19",
3242 "ymm20", "ymm21", "ymm22", "ymm23",
3243 "ymm24", "ymm25", "ymm26", "ymm27",
3244 "ymm28", "ymm29", "ymm30", "ymm31"
3246 static const char *att_names_ymm
[] = {
3247 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3248 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3249 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3250 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3251 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3252 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3253 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3254 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3257 static const char **names_zmm
;
3258 static const char *intel_names_zmm
[] = {
3259 "zmm0", "zmm1", "zmm2", "zmm3",
3260 "zmm4", "zmm5", "zmm6", "zmm7",
3261 "zmm8", "zmm9", "zmm10", "zmm11",
3262 "zmm12", "zmm13", "zmm14", "zmm15",
3263 "zmm16", "zmm17", "zmm18", "zmm19",
3264 "zmm20", "zmm21", "zmm22", "zmm23",
3265 "zmm24", "zmm25", "zmm26", "zmm27",
3266 "zmm28", "zmm29", "zmm30", "zmm31"
3268 static const char *att_names_zmm
[] = {
3269 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3270 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3271 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3272 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3273 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3274 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3275 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3276 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3279 static const char **names_mask
;
3280 static const char *intel_names_mask
[] = {
3281 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3283 static const char *att_names_mask
[] = {
3284 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3287 static const char *names_rounding
[] =
3295 static const struct dis386 reg_table
[][8] = {
3298 { "addA", { Ebh1
, Ib
} },
3299 { "orA", { Ebh1
, Ib
} },
3300 { "adcA", { Ebh1
, Ib
} },
3301 { "sbbA", { Ebh1
, Ib
} },
3302 { "andA", { Ebh1
, Ib
} },
3303 { "subA", { Ebh1
, Ib
} },
3304 { "xorA", { Ebh1
, Ib
} },
3305 { "cmpA", { Eb
, Ib
} },
3309 { "addQ", { Evh1
, Iv
} },
3310 { "orQ", { Evh1
, Iv
} },
3311 { "adcQ", { Evh1
, Iv
} },
3312 { "sbbQ", { Evh1
, Iv
} },
3313 { "andQ", { Evh1
, Iv
} },
3314 { "subQ", { Evh1
, Iv
} },
3315 { "xorQ", { Evh1
, Iv
} },
3316 { "cmpQ", { Ev
, Iv
} },
3320 { "addQ", { Evh1
, sIb
} },
3321 { "orQ", { Evh1
, sIb
} },
3322 { "adcQ", { Evh1
, sIb
} },
3323 { "sbbQ", { Evh1
, sIb
} },
3324 { "andQ", { Evh1
, sIb
} },
3325 { "subQ", { Evh1
, sIb
} },
3326 { "xorQ", { Evh1
, sIb
} },
3327 { "cmpQ", { Ev
, sIb
} },
3331 { "popU", { stackEv
} },
3332 { XOP_8F_TABLE (XOP_09
) },
3336 { XOP_8F_TABLE (XOP_09
) },
3340 { "rolA", { Eb
, Ib
} },
3341 { "rorA", { Eb
, Ib
} },
3342 { "rclA", { Eb
, Ib
} },
3343 { "rcrA", { Eb
, Ib
} },
3344 { "shlA", { Eb
, Ib
} },
3345 { "shrA", { Eb
, Ib
} },
3347 { "sarA", { Eb
, Ib
} },
3351 { "rolQ", { Ev
, Ib
} },
3352 { "rorQ", { Ev
, Ib
} },
3353 { "rclQ", { Ev
, Ib
} },
3354 { "rcrQ", { Ev
, Ib
} },
3355 { "shlQ", { Ev
, Ib
} },
3356 { "shrQ", { Ev
, Ib
} },
3358 { "sarQ", { Ev
, Ib
} },
3362 { "movA", { Ebh3
, Ib
} },
3369 { MOD_TABLE (MOD_C6_REG_7
) },
3373 { "movQ", { Evh3
, Iv
} },
3380 { MOD_TABLE (MOD_C7_REG_7
) },
3384 { "rolA", { Eb
, I1
} },
3385 { "rorA", { Eb
, I1
} },
3386 { "rclA", { Eb
, I1
} },
3387 { "rcrA", { Eb
, I1
} },
3388 { "shlA", { Eb
, I1
} },
3389 { "shrA", { Eb
, I1
} },
3391 { "sarA", { Eb
, I1
} },
3395 { "rolQ", { Ev
, I1
} },
3396 { "rorQ", { Ev
, I1
} },
3397 { "rclQ", { Ev
, I1
} },
3398 { "rcrQ", { Ev
, I1
} },
3399 { "shlQ", { Ev
, I1
} },
3400 { "shrQ", { Ev
, I1
} },
3402 { "sarQ", { Ev
, I1
} },
3406 { "rolA", { Eb
, CL
} },
3407 { "rorA", { Eb
, CL
} },
3408 { "rclA", { Eb
, CL
} },
3409 { "rcrA", { Eb
, CL
} },
3410 { "shlA", { Eb
, CL
} },
3411 { "shrA", { Eb
, CL
} },
3413 { "sarA", { Eb
, CL
} },
3417 { "rolQ", { Ev
, CL
} },
3418 { "rorQ", { Ev
, CL
} },
3419 { "rclQ", { Ev
, CL
} },
3420 { "rcrQ", { Ev
, CL
} },
3421 { "shlQ", { Ev
, CL
} },
3422 { "shrQ", { Ev
, CL
} },
3424 { "sarQ", { Ev
, CL
} },
3428 { "testA", { Eb
, Ib
} },
3430 { "notA", { Ebh1
} },
3431 { "negA", { Ebh1
} },
3432 { "mulA", { Eb
} }, /* Don't print the implicit %al register, */
3433 { "imulA", { Eb
} }, /* to distinguish these opcodes from other */
3434 { "divA", { Eb
} }, /* mul/imul opcodes. Do the same for div */
3435 { "idivA", { Eb
} }, /* and idiv for consistency. */
3439 { "testQ", { Ev
, Iv
} },
3441 { "notQ", { Evh1
} },
3442 { "negQ", { Evh1
} },
3443 { "mulQ", { Ev
} }, /* Don't print the implicit register. */
3444 { "imulQ", { Ev
} },
3446 { "idivQ", { Ev
} },
3450 { "incA", { Ebh1
} },
3451 { "decA", { Ebh1
} },
3455 { "incQ", { Evh1
} },
3456 { "decQ", { Evh1
} },
3457 { "call{T|}", { indirEv
, BND
} },
3458 { MOD_TABLE (MOD_FF_REG_3
) },
3459 { "jmp{T|}", { indirEv
, BND
} },
3460 { MOD_TABLE (MOD_FF_REG_5
) },
3461 { "pushU", { stackEv
} },
3466 { "sldtD", { Sv
} },
3477 { MOD_TABLE (MOD_0F01_REG_0
) },
3478 { MOD_TABLE (MOD_0F01_REG_1
) },
3479 { MOD_TABLE (MOD_0F01_REG_2
) },
3480 { MOD_TABLE (MOD_0F01_REG_3
) },
3481 { "smswD", { Sv
} },
3484 { MOD_TABLE (MOD_0F01_REG_7
) },
3488 { "prefetch", { Mb
} },
3489 { "prefetchw", { Mb
} },
3490 { "prefetchwt1", { Mb
} },
3491 { "prefetch", { Mb
} },
3492 { "prefetch", { Mb
} },
3493 { "prefetch", { Mb
} },
3494 { "prefetch", { Mb
} },
3495 { "prefetch", { Mb
} },
3499 { MOD_TABLE (MOD_0F18_REG_0
) },
3500 { MOD_TABLE (MOD_0F18_REG_1
) },
3501 { MOD_TABLE (MOD_0F18_REG_2
) },
3502 { MOD_TABLE (MOD_0F18_REG_3
) },
3503 { MOD_TABLE (MOD_0F18_REG_4
) },
3504 { MOD_TABLE (MOD_0F18_REG_5
) },
3505 { MOD_TABLE (MOD_0F18_REG_6
) },
3506 { MOD_TABLE (MOD_0F18_REG_7
) },
3512 { MOD_TABLE (MOD_0F71_REG_2
) },
3514 { MOD_TABLE (MOD_0F71_REG_4
) },
3516 { MOD_TABLE (MOD_0F71_REG_6
) },
3522 { MOD_TABLE (MOD_0F72_REG_2
) },
3524 { MOD_TABLE (MOD_0F72_REG_4
) },
3526 { MOD_TABLE (MOD_0F72_REG_6
) },
3532 { MOD_TABLE (MOD_0F73_REG_2
) },
3533 { MOD_TABLE (MOD_0F73_REG_3
) },
3536 { MOD_TABLE (MOD_0F73_REG_6
) },
3537 { MOD_TABLE (MOD_0F73_REG_7
) },
3541 { "montmul", { { OP_0f07
, 0 } } },
3542 { "xsha1", { { OP_0f07
, 0 } } },
3543 { "xsha256", { { OP_0f07
, 0 } } },
3547 { "xstore-rng", { { OP_0f07
, 0 } } },
3548 { "xcrypt-ecb", { { OP_0f07
, 0 } } },
3549 { "xcrypt-cbc", { { OP_0f07
, 0 } } },
3550 { "xcrypt-ctr", { { OP_0f07
, 0 } } },
3551 { "xcrypt-cfb", { { OP_0f07
, 0 } } },
3552 { "xcrypt-ofb", { { OP_0f07
, 0 } } },
3556 { MOD_TABLE (MOD_0FAE_REG_0
) },
3557 { MOD_TABLE (MOD_0FAE_REG_1
) },
3558 { MOD_TABLE (MOD_0FAE_REG_2
) },
3559 { MOD_TABLE (MOD_0FAE_REG_3
) },
3560 { MOD_TABLE (MOD_0FAE_REG_4
) },
3561 { MOD_TABLE (MOD_0FAE_REG_5
) },
3562 { MOD_TABLE (MOD_0FAE_REG_6
) },
3563 { MOD_TABLE (MOD_0FAE_REG_7
) },
3571 { "btQ", { Ev
, Ib
} },
3572 { "btsQ", { Evh1
, Ib
} },
3573 { "btrQ", { Evh1
, Ib
} },
3574 { "btcQ", { Evh1
, Ib
} },
3579 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} } },
3581 { MOD_TABLE (MOD_0FC7_REG_3
) },
3582 { MOD_TABLE (MOD_0FC7_REG_4
) },
3583 { MOD_TABLE (MOD_0FC7_REG_5
) },
3584 { MOD_TABLE (MOD_0FC7_REG_6
) },
3585 { MOD_TABLE (MOD_0FC7_REG_7
) },
3591 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3593 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3595 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3601 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3603 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3605 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3611 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3612 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3615 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3616 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3622 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3623 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3625 /* REG_VEX_0F38F3 */
3628 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3629 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3630 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3634 { "llwpcb", { { OP_LWPCB_E
, 0 } } },
3635 { "slwpcb", { { OP_LWPCB_E
, 0 } } },
3639 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
3640 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
3642 /* REG_XOP_TBM_01 */
3645 { "blcfill", { { OP_LWP_E
, 0 }, Ev
} },
3646 { "blsfill", { { OP_LWP_E
, 0 }, Ev
} },
3647 { "blcs", { { OP_LWP_E
, 0 }, Ev
} },
3648 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
} },
3649 { "blcic", { { OP_LWP_E
, 0 }, Ev
} },
3650 { "blsic", { { OP_LWP_E
, 0 }, Ev
} },
3651 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
} },
3653 /* REG_XOP_TBM_02 */
3656 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
} },
3661 { "blci", { { OP_LWP_E
, 0 }, Ev
} },
3663 #define NEED_REG_TABLE
3664 #include "i386-dis-evex.h"
3665 #undef NEED_REG_TABLE
3668 static const struct dis386 prefix_table
[][4] = {
3671 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
3672 { "pause", { XX
} },
3673 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
3678 { "movups", { XM
, EXx
} },
3679 { "movss", { XM
, EXd
} },
3680 { "movupd", { XM
, EXx
} },
3681 { "movsd", { XM
, EXq
} },
3686 { "movups", { EXxS
, XM
} },
3687 { "movss", { EXdS
, XM
} },
3688 { "movupd", { EXxS
, XM
} },
3689 { "movsd", { EXqS
, XM
} },
3694 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3695 { "movsldup", { XM
, EXx
} },
3696 { "movlpd", { XM
, EXq
} },
3697 { "movddup", { XM
, EXq
} },
3702 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3703 { "movshdup", { XM
, EXx
} },
3704 { "movhpd", { XM
, EXq
} },
3709 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3710 { "bndcl", { Gbnd
, Ev_bnd
} },
3711 { "bndmov", { Gbnd
, Ebnd
} },
3712 { "bndcu", { Gbnd
, Ev_bnd
} },
3717 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3718 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3719 { "bndmov", { Ebnd
, Gbnd
} },
3720 { "bndcn", { Gbnd
, Ev_bnd
} },
3725 { "cvtpi2ps", { XM
, EMCq
} },
3726 { "cvtsi2ss%LQ", { XM
, Ev
} },
3727 { "cvtpi2pd", { XM
, EMCq
} },
3728 { "cvtsi2sd%LQ", { XM
, Ev
} },
3733 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3734 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3735 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3736 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3741 { "cvttps2pi", { MXC
, EXq
} },
3742 { "cvttss2siY", { Gv
, EXd
} },
3743 { "cvttpd2pi", { MXC
, EXx
} },
3744 { "cvttsd2siY", { Gv
, EXq
} },
3749 { "cvtps2pi", { MXC
, EXq
} },
3750 { "cvtss2siY", { Gv
, EXd
} },
3751 { "cvtpd2pi", { MXC
, EXx
} },
3752 { "cvtsd2siY", { Gv
, EXq
} },
3757 { "ucomiss",{ XM
, EXd
} },
3759 { "ucomisd",{ XM
, EXq
} },
3764 { "comiss", { XM
, EXd
} },
3766 { "comisd", { XM
, EXq
} },
3771 { "sqrtps", { XM
, EXx
} },
3772 { "sqrtss", { XM
, EXd
} },
3773 { "sqrtpd", { XM
, EXx
} },
3774 { "sqrtsd", { XM
, EXq
} },
3779 { "rsqrtps",{ XM
, EXx
} },
3780 { "rsqrtss",{ XM
, EXd
} },
3785 { "rcpps", { XM
, EXx
} },
3786 { "rcpss", { XM
, EXd
} },
3791 { "addps", { XM
, EXx
} },
3792 { "addss", { XM
, EXd
} },
3793 { "addpd", { XM
, EXx
} },
3794 { "addsd", { XM
, EXq
} },
3799 { "mulps", { XM
, EXx
} },
3800 { "mulss", { XM
, EXd
} },
3801 { "mulpd", { XM
, EXx
} },
3802 { "mulsd", { XM
, EXq
} },
3807 { "cvtps2pd", { XM
, EXq
} },
3808 { "cvtss2sd", { XM
, EXd
} },
3809 { "cvtpd2ps", { XM
, EXx
} },
3810 { "cvtsd2ss", { XM
, EXq
} },
3815 { "cvtdq2ps", { XM
, EXx
} },
3816 { "cvttps2dq", { XM
, EXx
} },
3817 { "cvtps2dq", { XM
, EXx
} },
3822 { "subps", { XM
, EXx
} },
3823 { "subss", { XM
, EXd
} },
3824 { "subpd", { XM
, EXx
} },
3825 { "subsd", { XM
, EXq
} },
3830 { "minps", { XM
, EXx
} },
3831 { "minss", { XM
, EXd
} },
3832 { "minpd", { XM
, EXx
} },
3833 { "minsd", { XM
, EXq
} },
3838 { "divps", { XM
, EXx
} },
3839 { "divss", { XM
, EXd
} },
3840 { "divpd", { XM
, EXx
} },
3841 { "divsd", { XM
, EXq
} },
3846 { "maxps", { XM
, EXx
} },
3847 { "maxss", { XM
, EXd
} },
3848 { "maxpd", { XM
, EXx
} },
3849 { "maxsd", { XM
, EXq
} },
3854 { "punpcklbw",{ MX
, EMd
} },
3856 { "punpcklbw",{ MX
, EMx
} },
3861 { "punpcklwd",{ MX
, EMd
} },
3863 { "punpcklwd",{ MX
, EMx
} },
3868 { "punpckldq",{ MX
, EMd
} },
3870 { "punpckldq",{ MX
, EMx
} },
3877 { "punpcklqdq", { XM
, EXx
} },
3884 { "punpckhqdq", { XM
, EXx
} },
3889 { "movq", { MX
, EM
} },
3890 { "movdqu", { XM
, EXx
} },
3891 { "movdqa", { XM
, EXx
} },
3896 { "pshufw", { MX
, EM
, Ib
} },
3897 { "pshufhw",{ XM
, EXx
, Ib
} },
3898 { "pshufd", { XM
, EXx
, Ib
} },
3899 { "pshuflw",{ XM
, EXx
, Ib
} },
3902 /* PREFIX_0F73_REG_3 */
3906 { "psrldq", { XS
, Ib
} },
3909 /* PREFIX_0F73_REG_7 */
3913 { "pslldq", { XS
, Ib
} },
3918 {"vmread", { Em
, Gm
} },
3920 {"extrq", { XS
, Ib
, Ib
} },
3921 {"insertq", { XM
, XS
, Ib
, Ib
} },
3926 {"vmwrite", { Gm
, Em
} },
3928 {"extrq", { XM
, XS
} },
3929 {"insertq", { XM
, XS
} },
3936 { "haddpd", { XM
, EXx
} },
3937 { "haddps", { XM
, EXx
} },
3944 { "hsubpd", { XM
, EXx
} },
3945 { "hsubps", { XM
, EXx
} },
3950 { "movK", { Edq
, MX
} },
3951 { "movq", { XM
, EXq
} },
3952 { "movK", { Edq
, XM
} },
3957 { "movq", { EMS
, MX
} },
3958 { "movdqu", { EXxS
, XM
} },
3959 { "movdqa", { EXxS
, XM
} },
3962 /* PREFIX_0FAE_REG_0 */
3965 { "rdfsbase", { Ev
} },
3968 /* PREFIX_0FAE_REG_1 */
3971 { "rdgsbase", { Ev
} },
3974 /* PREFIX_0FAE_REG_2 */
3977 { "wrfsbase", { Ev
} },
3980 /* PREFIX_0FAE_REG_3 */
3983 { "wrgsbase", { Ev
} },
3986 /* PREFIX_0FAE_REG_7 */
3988 { "clflush", { Mb
} },
3990 { "clflushopt", { Mb
} },
3996 { "popcntS", { Gv
, Ev
} },
4001 { "bsfS", { Gv
, Ev
} },
4002 { "tzcntS", { Gv
, Ev
} },
4003 { "bsfS", { Gv
, Ev
} },
4008 { "bsrS", { Gv
, Ev
} },
4009 { "lzcntS", { Gv
, Ev
} },
4010 { "bsrS", { Gv
, Ev
} },
4015 { "cmpps", { XM
, EXx
, CMP
} },
4016 { "cmpss", { XM
, EXd
, CMP
} },
4017 { "cmppd", { XM
, EXx
, CMP
} },
4018 { "cmpsd", { XM
, EXq
, CMP
} },
4023 { "movntiS", { Ma
, Gv
} },
4026 /* PREFIX_0FC7_REG_6 */
4028 { "vmptrld",{ Mq
} },
4029 { "vmxon", { Mq
} },
4030 { "vmclear",{ Mq
} },
4037 { "addsubpd", { XM
, EXx
} },
4038 { "addsubps", { XM
, EXx
} },
4044 { "movq2dq",{ XM
, MS
} },
4045 { "movq", { EXqS
, XM
} },
4046 { "movdq2q",{ MX
, XS
} },
4052 { "cvtdq2pd", { XM
, EXq
} },
4053 { "cvttpd2dq", { XM
, EXx
} },
4054 { "cvtpd2dq", { XM
, EXx
} },
4059 { "movntq", { Mq
, MX
} },
4061 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4069 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4074 { "maskmovq", { MX
, MS
} },
4076 { "maskmovdqu", { XM
, XS
} },
4083 { "pblendvb", { XM
, EXx
, XMM0
} },
4090 { "blendvps", { XM
, EXx
, XMM0
} },
4097 { "blendvpd", { XM
, EXx
, XMM0
} },
4104 { "ptest", { XM
, EXx
} },
4111 { "pmovsxbw", { XM
, EXq
} },
4118 { "pmovsxbd", { XM
, EXd
} },
4125 { "pmovsxbq", { XM
, EXw
} },
4132 { "pmovsxwd", { XM
, EXq
} },
4139 { "pmovsxwq", { XM
, EXd
} },
4146 { "pmovsxdq", { XM
, EXq
} },
4153 { "pmuldq", { XM
, EXx
} },
4160 { "pcmpeqq", { XM
, EXx
} },
4167 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4174 { "packusdw", { XM
, EXx
} },
4181 { "pmovzxbw", { XM
, EXq
} },
4188 { "pmovzxbd", { XM
, EXd
} },
4195 { "pmovzxbq", { XM
, EXw
} },
4202 { "pmovzxwd", { XM
, EXq
} },
4209 { "pmovzxwq", { XM
, EXd
} },
4216 { "pmovzxdq", { XM
, EXq
} },
4223 { "pcmpgtq", { XM
, EXx
} },
4230 { "pminsb", { XM
, EXx
} },
4237 { "pminsd", { XM
, EXx
} },
4244 { "pminuw", { XM
, EXx
} },
4251 { "pminud", { XM
, EXx
} },
4258 { "pmaxsb", { XM
, EXx
} },
4265 { "pmaxsd", { XM
, EXx
} },
4272 { "pmaxuw", { XM
, EXx
} },
4279 { "pmaxud", { XM
, EXx
} },
4286 { "pmulld", { XM
, EXx
} },
4293 { "phminposuw", { XM
, EXx
} },
4300 { "invept", { Gm
, Mo
} },
4307 { "invvpid", { Gm
, Mo
} },
4314 { "invpcid", { Gm
, M
} },
4319 { "sha1nexte", { XM
, EXxmm
} },
4324 { "sha1msg1", { XM
, EXxmm
} },
4329 { "sha1msg2", { XM
, EXxmm
} },
4334 { "sha256rnds2", { XM
, EXxmm
, XMM0
} },
4339 { "sha256msg1", { XM
, EXxmm
} },
4344 { "sha256msg2", { XM
, EXxmm
} },
4351 { "aesimc", { XM
, EXx
} },
4358 { "aesenc", { XM
, EXx
} },
4365 { "aesenclast", { XM
, EXx
} },
4372 { "aesdec", { XM
, EXx
} },
4379 { "aesdeclast", { XM
, EXx
} },
4384 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
4386 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
4387 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} } },
4392 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
4394 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
4395 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} } },
4401 { "adoxS", { Gdq
, Edq
} },
4402 { "adcxS", { Gdq
, Edq
} },
4410 { "roundps", { XM
, EXx
, Ib
} },
4417 { "roundpd", { XM
, EXx
, Ib
} },
4424 { "roundss", { XM
, EXd
, Ib
} },
4431 { "roundsd", { XM
, EXq
, Ib
} },
4438 { "blendps", { XM
, EXx
, Ib
} },
4445 { "blendpd", { XM
, EXx
, Ib
} },
4452 { "pblendw", { XM
, EXx
, Ib
} },
4459 { "pextrb", { Edqb
, XM
, Ib
} },
4466 { "pextrw", { Edqw
, XM
, Ib
} },
4473 { "pextrK", { Edq
, XM
, Ib
} },
4480 { "extractps", { Edqd
, XM
, Ib
} },
4487 { "pinsrb", { XM
, Edqb
, Ib
} },
4494 { "insertps", { XM
, EXd
, Ib
} },
4501 { "pinsrK", { XM
, Edq
, Ib
} },
4508 { "dpps", { XM
, EXx
, Ib
} },
4515 { "dppd", { XM
, EXx
, Ib
} },
4522 { "mpsadbw", { XM
, EXx
, Ib
} },
4529 { "pclmulqdq", { XM
, EXx
, PCLMUL
} },
4536 { "pcmpestrm", { XM
, EXx
, Ib
} },
4543 { "pcmpestri", { XM
, EXx
, Ib
} },
4550 { "pcmpistrm", { XM
, EXx
, Ib
} },
4557 { "pcmpistri", { XM
, EXx
, Ib
} },
4562 { "sha1rnds4", { XM
, EXxmm
, Ib
} },
4569 { "aeskeygenassist", { XM
, EXx
, Ib
} },
4572 /* PREFIX_VEX_0F10 */
4574 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4575 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4576 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4577 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4580 /* PREFIX_VEX_0F11 */
4582 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4583 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4584 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4585 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4588 /* PREFIX_VEX_0F12 */
4590 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4591 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4592 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4593 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4596 /* PREFIX_VEX_0F16 */
4598 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4599 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4600 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4603 /* PREFIX_VEX_0F2A */
4606 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4608 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4611 /* PREFIX_VEX_0F2C */
4614 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4616 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4619 /* PREFIX_VEX_0F2D */
4622 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4624 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4627 /* PREFIX_VEX_0F2E */
4629 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4631 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4634 /* PREFIX_VEX_0F2F */
4636 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4638 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4641 /* PREFIX_VEX_0F41 */
4643 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4645 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4648 /* PREFIX_VEX_0F42 */
4650 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4652 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4655 /* PREFIX_VEX_0F44 */
4657 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4659 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4662 /* PREFIX_VEX_0F45 */
4664 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4666 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4669 /* PREFIX_VEX_0F46 */
4671 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4673 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4676 /* PREFIX_VEX_0F47 */
4678 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4680 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4683 /* PREFIX_VEX_0F4A */
4685 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4687 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4690 /* PREFIX_VEX_0F4B */
4692 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4694 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4697 /* PREFIX_VEX_0F51 */
4699 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4700 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4701 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4702 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4705 /* PREFIX_VEX_0F52 */
4707 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4708 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4711 /* PREFIX_VEX_0F53 */
4713 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4714 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4717 /* PREFIX_VEX_0F58 */
4719 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4720 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4721 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4722 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4725 /* PREFIX_VEX_0F59 */
4727 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4728 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4729 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4730 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4733 /* PREFIX_VEX_0F5A */
4735 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4736 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4737 { "vcvtpd2ps%XY", { XMM
, EXx
} },
4738 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4741 /* PREFIX_VEX_0F5B */
4743 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4744 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4745 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4748 /* PREFIX_VEX_0F5C */
4750 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4751 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4752 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4753 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4756 /* PREFIX_VEX_0F5D */
4758 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4759 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4760 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4761 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4764 /* PREFIX_VEX_0F5E */
4766 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4767 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4768 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4769 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4772 /* PREFIX_VEX_0F5F */
4774 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4775 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4776 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4777 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4780 /* PREFIX_VEX_0F60 */
4784 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4787 /* PREFIX_VEX_0F61 */
4791 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4794 /* PREFIX_VEX_0F62 */
4798 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4801 /* PREFIX_VEX_0F63 */
4805 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4808 /* PREFIX_VEX_0F64 */
4812 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4815 /* PREFIX_VEX_0F65 */
4819 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4822 /* PREFIX_VEX_0F66 */
4826 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4829 /* PREFIX_VEX_0F67 */
4833 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4836 /* PREFIX_VEX_0F68 */
4840 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4843 /* PREFIX_VEX_0F69 */
4847 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4850 /* PREFIX_VEX_0F6A */
4854 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4857 /* PREFIX_VEX_0F6B */
4861 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4864 /* PREFIX_VEX_0F6C */
4868 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4871 /* PREFIX_VEX_0F6D */
4875 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
4878 /* PREFIX_VEX_0F6E */
4882 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4885 /* PREFIX_VEX_0F6F */
4888 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
4889 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
4892 /* PREFIX_VEX_0F70 */
4895 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
4896 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
4897 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
4900 /* PREFIX_VEX_0F71_REG_2 */
4904 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
4907 /* PREFIX_VEX_0F71_REG_4 */
4911 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
4914 /* PREFIX_VEX_0F71_REG_6 */
4918 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
4921 /* PREFIX_VEX_0F72_REG_2 */
4925 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
4928 /* PREFIX_VEX_0F72_REG_4 */
4932 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
4935 /* PREFIX_VEX_0F72_REG_6 */
4939 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
4942 /* PREFIX_VEX_0F73_REG_2 */
4946 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
4949 /* PREFIX_VEX_0F73_REG_3 */
4953 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
4956 /* PREFIX_VEX_0F73_REG_6 */
4960 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
4963 /* PREFIX_VEX_0F73_REG_7 */
4967 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
4970 /* PREFIX_VEX_0F74 */
4974 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
4977 /* PREFIX_VEX_0F75 */
4981 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
4984 /* PREFIX_VEX_0F76 */
4988 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
4991 /* PREFIX_VEX_0F77 */
4993 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
4996 /* PREFIX_VEX_0F7C */
5000 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5001 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5004 /* PREFIX_VEX_0F7D */
5008 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5009 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5012 /* PREFIX_VEX_0F7E */
5015 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5016 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5019 /* PREFIX_VEX_0F7F */
5022 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5023 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5026 /* PREFIX_VEX_0F90 */
5028 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5030 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5033 /* PREFIX_VEX_0F91 */
5035 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5037 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5040 /* PREFIX_VEX_0F92 */
5042 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5044 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5045 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5048 /* PREFIX_VEX_0F93 */
5050 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5052 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5053 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5056 /* PREFIX_VEX_0F98 */
5058 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5060 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5063 /* PREFIX_VEX_0F99 */
5065 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5067 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5070 /* PREFIX_VEX_0FC2 */
5072 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5073 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5074 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5075 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5078 /* PREFIX_VEX_0FC4 */
5082 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5085 /* PREFIX_VEX_0FC5 */
5089 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5092 /* PREFIX_VEX_0FD0 */
5096 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5097 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5100 /* PREFIX_VEX_0FD1 */
5104 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5107 /* PREFIX_VEX_0FD2 */
5111 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5114 /* PREFIX_VEX_0FD3 */
5118 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5121 /* PREFIX_VEX_0FD4 */
5125 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5128 /* PREFIX_VEX_0FD5 */
5132 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5135 /* PREFIX_VEX_0FD6 */
5139 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5142 /* PREFIX_VEX_0FD7 */
5146 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5149 /* PREFIX_VEX_0FD8 */
5153 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5156 /* PREFIX_VEX_0FD9 */
5160 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5163 /* PREFIX_VEX_0FDA */
5167 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5170 /* PREFIX_VEX_0FDB */
5174 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5177 /* PREFIX_VEX_0FDC */
5181 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5184 /* PREFIX_VEX_0FDD */
5188 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5191 /* PREFIX_VEX_0FDE */
5195 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5198 /* PREFIX_VEX_0FDF */
5202 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5205 /* PREFIX_VEX_0FE0 */
5209 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5212 /* PREFIX_VEX_0FE1 */
5216 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5219 /* PREFIX_VEX_0FE2 */
5223 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5226 /* PREFIX_VEX_0FE3 */
5230 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5233 /* PREFIX_VEX_0FE4 */
5237 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5240 /* PREFIX_VEX_0FE5 */
5244 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5247 /* PREFIX_VEX_0FE6 */
5250 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5251 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5252 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5255 /* PREFIX_VEX_0FE7 */
5259 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5262 /* PREFIX_VEX_0FE8 */
5266 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5269 /* PREFIX_VEX_0FE9 */
5273 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5276 /* PREFIX_VEX_0FEA */
5280 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5283 /* PREFIX_VEX_0FEB */
5287 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5290 /* PREFIX_VEX_0FEC */
5294 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5297 /* PREFIX_VEX_0FED */
5301 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5304 /* PREFIX_VEX_0FEE */
5308 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5311 /* PREFIX_VEX_0FEF */
5315 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5318 /* PREFIX_VEX_0FF0 */
5323 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5326 /* PREFIX_VEX_0FF1 */
5330 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5333 /* PREFIX_VEX_0FF2 */
5337 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5340 /* PREFIX_VEX_0FF3 */
5344 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5347 /* PREFIX_VEX_0FF4 */
5351 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5354 /* PREFIX_VEX_0FF5 */
5358 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5361 /* PREFIX_VEX_0FF6 */
5365 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5368 /* PREFIX_VEX_0FF7 */
5372 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5375 /* PREFIX_VEX_0FF8 */
5379 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5382 /* PREFIX_VEX_0FF9 */
5386 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5389 /* PREFIX_VEX_0FFA */
5393 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5396 /* PREFIX_VEX_0FFB */
5400 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5403 /* PREFIX_VEX_0FFC */
5407 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5410 /* PREFIX_VEX_0FFD */
5414 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5417 /* PREFIX_VEX_0FFE */
5421 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5424 /* PREFIX_VEX_0F3800 */
5428 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5431 /* PREFIX_VEX_0F3801 */
5435 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5438 /* PREFIX_VEX_0F3802 */
5442 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5445 /* PREFIX_VEX_0F3803 */
5449 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5452 /* PREFIX_VEX_0F3804 */
5456 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5459 /* PREFIX_VEX_0F3805 */
5463 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5466 /* PREFIX_VEX_0F3806 */
5470 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5473 /* PREFIX_VEX_0F3807 */
5477 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5480 /* PREFIX_VEX_0F3808 */
5484 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5487 /* PREFIX_VEX_0F3809 */
5491 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5494 /* PREFIX_VEX_0F380A */
5498 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5501 /* PREFIX_VEX_0F380B */
5505 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5508 /* PREFIX_VEX_0F380C */
5512 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5515 /* PREFIX_VEX_0F380D */
5519 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5522 /* PREFIX_VEX_0F380E */
5526 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5529 /* PREFIX_VEX_0F380F */
5533 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5536 /* PREFIX_VEX_0F3813 */
5540 { "vcvtph2ps", { XM
, EXxmmq
} },
5543 /* PREFIX_VEX_0F3816 */
5547 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5550 /* PREFIX_VEX_0F3817 */
5554 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5557 /* PREFIX_VEX_0F3818 */
5561 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5564 /* PREFIX_VEX_0F3819 */
5568 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5571 /* PREFIX_VEX_0F381A */
5575 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5578 /* PREFIX_VEX_0F381C */
5582 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5585 /* PREFIX_VEX_0F381D */
5589 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5592 /* PREFIX_VEX_0F381E */
5596 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5599 /* PREFIX_VEX_0F3820 */
5603 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5606 /* PREFIX_VEX_0F3821 */
5610 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5613 /* PREFIX_VEX_0F3822 */
5617 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5620 /* PREFIX_VEX_0F3823 */
5624 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5627 /* PREFIX_VEX_0F3824 */
5631 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5634 /* PREFIX_VEX_0F3825 */
5638 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5641 /* PREFIX_VEX_0F3828 */
5645 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5648 /* PREFIX_VEX_0F3829 */
5652 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5655 /* PREFIX_VEX_0F382A */
5659 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5662 /* PREFIX_VEX_0F382B */
5666 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5669 /* PREFIX_VEX_0F382C */
5673 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5676 /* PREFIX_VEX_0F382D */
5680 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5683 /* PREFIX_VEX_0F382E */
5687 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5690 /* PREFIX_VEX_0F382F */
5694 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5697 /* PREFIX_VEX_0F3830 */
5701 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5704 /* PREFIX_VEX_0F3831 */
5708 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5711 /* PREFIX_VEX_0F3832 */
5715 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5718 /* PREFIX_VEX_0F3833 */
5722 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5725 /* PREFIX_VEX_0F3834 */
5729 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5732 /* PREFIX_VEX_0F3835 */
5736 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5739 /* PREFIX_VEX_0F3836 */
5743 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5746 /* PREFIX_VEX_0F3837 */
5750 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5753 /* PREFIX_VEX_0F3838 */
5757 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5760 /* PREFIX_VEX_0F3839 */
5764 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5767 /* PREFIX_VEX_0F383A */
5771 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5774 /* PREFIX_VEX_0F383B */
5778 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5781 /* PREFIX_VEX_0F383C */
5785 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5788 /* PREFIX_VEX_0F383D */
5792 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5795 /* PREFIX_VEX_0F383E */
5799 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5802 /* PREFIX_VEX_0F383F */
5806 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5809 /* PREFIX_VEX_0F3840 */
5813 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5816 /* PREFIX_VEX_0F3841 */
5820 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5823 /* PREFIX_VEX_0F3845 */
5827 { "vpsrlv%LW", { XM
, Vex
, EXx
} },
5830 /* PREFIX_VEX_0F3846 */
5834 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5837 /* PREFIX_VEX_0F3847 */
5841 { "vpsllv%LW", { XM
, Vex
, EXx
} },
5844 /* PREFIX_VEX_0F3858 */
5848 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5851 /* PREFIX_VEX_0F3859 */
5855 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5858 /* PREFIX_VEX_0F385A */
5862 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5865 /* PREFIX_VEX_0F3878 */
5869 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5872 /* PREFIX_VEX_0F3879 */
5876 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5879 /* PREFIX_VEX_0F388C */
5883 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5886 /* PREFIX_VEX_0F388E */
5890 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5893 /* PREFIX_VEX_0F3890 */
5897 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
} },
5900 /* PREFIX_VEX_0F3891 */
5904 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
} },
5907 /* PREFIX_VEX_0F3892 */
5911 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
} },
5914 /* PREFIX_VEX_0F3893 */
5918 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
} },
5921 /* PREFIX_VEX_0F3896 */
5925 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
} },
5928 /* PREFIX_VEX_0F3897 */
5932 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
} },
5935 /* PREFIX_VEX_0F3898 */
5939 { "vfmadd132p%XW", { XM
, Vex
, EXx
} },
5942 /* PREFIX_VEX_0F3899 */
5946 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5949 /* PREFIX_VEX_0F389A */
5953 { "vfmsub132p%XW", { XM
, Vex
, EXx
} },
5956 /* PREFIX_VEX_0F389B */
5960 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5963 /* PREFIX_VEX_0F389C */
5967 { "vfnmadd132p%XW", { XM
, Vex
, EXx
} },
5970 /* PREFIX_VEX_0F389D */
5974 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5977 /* PREFIX_VEX_0F389E */
5981 { "vfnmsub132p%XW", { XM
, Vex
, EXx
} },
5984 /* PREFIX_VEX_0F389F */
5988 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5991 /* PREFIX_VEX_0F38A6 */
5995 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
} },
5999 /* PREFIX_VEX_0F38A7 */
6003 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
} },
6006 /* PREFIX_VEX_0F38A8 */
6010 { "vfmadd213p%XW", { XM
, Vex
, EXx
} },
6013 /* PREFIX_VEX_0F38A9 */
6017 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6020 /* PREFIX_VEX_0F38AA */
6024 { "vfmsub213p%XW", { XM
, Vex
, EXx
} },
6027 /* PREFIX_VEX_0F38AB */
6031 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6034 /* PREFIX_VEX_0F38AC */
6038 { "vfnmadd213p%XW", { XM
, Vex
, EXx
} },
6041 /* PREFIX_VEX_0F38AD */
6045 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6048 /* PREFIX_VEX_0F38AE */
6052 { "vfnmsub213p%XW", { XM
, Vex
, EXx
} },
6055 /* PREFIX_VEX_0F38AF */
6059 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6062 /* PREFIX_VEX_0F38B6 */
6066 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
} },
6069 /* PREFIX_VEX_0F38B7 */
6073 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
} },
6076 /* PREFIX_VEX_0F38B8 */
6080 { "vfmadd231p%XW", { XM
, Vex
, EXx
} },
6083 /* PREFIX_VEX_0F38B9 */
6087 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6090 /* PREFIX_VEX_0F38BA */
6094 { "vfmsub231p%XW", { XM
, Vex
, EXx
} },
6097 /* PREFIX_VEX_0F38BB */
6101 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6104 /* PREFIX_VEX_0F38BC */
6108 { "vfnmadd231p%XW", { XM
, Vex
, EXx
} },
6111 /* PREFIX_VEX_0F38BD */
6115 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6118 /* PREFIX_VEX_0F38BE */
6122 { "vfnmsub231p%XW", { XM
, Vex
, EXx
} },
6125 /* PREFIX_VEX_0F38BF */
6129 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6132 /* PREFIX_VEX_0F38DB */
6136 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6139 /* PREFIX_VEX_0F38DC */
6143 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
6146 /* PREFIX_VEX_0F38DD */
6150 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
6153 /* PREFIX_VEX_0F38DE */
6157 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
6160 /* PREFIX_VEX_0F38DF */
6164 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
6167 /* PREFIX_VEX_0F38F2 */
6169 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6172 /* PREFIX_VEX_0F38F3_REG_1 */
6174 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6177 /* PREFIX_VEX_0F38F3_REG_2 */
6179 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6182 /* PREFIX_VEX_0F38F3_REG_3 */
6184 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6187 /* PREFIX_VEX_0F38F5 */
6189 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6190 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6192 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6195 /* PREFIX_VEX_0F38F6 */
6200 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6203 /* PREFIX_VEX_0F38F7 */
6205 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6206 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6207 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6208 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6211 /* PREFIX_VEX_0F3A00 */
6215 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6218 /* PREFIX_VEX_0F3A01 */
6222 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6225 /* PREFIX_VEX_0F3A02 */
6229 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6232 /* PREFIX_VEX_0F3A04 */
6236 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6239 /* PREFIX_VEX_0F3A05 */
6243 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6246 /* PREFIX_VEX_0F3A06 */
6250 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6253 /* PREFIX_VEX_0F3A08 */
6257 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6260 /* PREFIX_VEX_0F3A09 */
6264 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6267 /* PREFIX_VEX_0F3A0A */
6271 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6274 /* PREFIX_VEX_0F3A0B */
6278 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6281 /* PREFIX_VEX_0F3A0C */
6285 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6288 /* PREFIX_VEX_0F3A0D */
6292 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6295 /* PREFIX_VEX_0F3A0E */
6299 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6302 /* PREFIX_VEX_0F3A0F */
6306 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6309 /* PREFIX_VEX_0F3A14 */
6313 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6316 /* PREFIX_VEX_0F3A15 */
6320 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6323 /* PREFIX_VEX_0F3A16 */
6327 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6330 /* PREFIX_VEX_0F3A17 */
6334 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6337 /* PREFIX_VEX_0F3A18 */
6341 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6344 /* PREFIX_VEX_0F3A19 */
6348 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6351 /* PREFIX_VEX_0F3A1D */
6355 { "vcvtps2ph", { EXxmmq
, XM
, Ib
} },
6358 /* PREFIX_VEX_0F3A20 */
6362 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6365 /* PREFIX_VEX_0F3A21 */
6369 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6372 /* PREFIX_VEX_0F3A22 */
6376 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6379 /* PREFIX_VEX_0F3A30 */
6383 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6386 /* PREFIX_VEX_0F3A31 */
6390 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6393 /* PREFIX_VEX_0F3A32 */
6397 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6400 /* PREFIX_VEX_0F3A33 */
6404 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6407 /* PREFIX_VEX_0F3A38 */
6411 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6414 /* PREFIX_VEX_0F3A39 */
6418 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6421 /* PREFIX_VEX_0F3A40 */
6425 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6428 /* PREFIX_VEX_0F3A41 */
6432 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6435 /* PREFIX_VEX_0F3A42 */
6439 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6442 /* PREFIX_VEX_0F3A44 */
6446 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6449 /* PREFIX_VEX_0F3A46 */
6453 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6456 /* PREFIX_VEX_0F3A48 */
6460 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6463 /* PREFIX_VEX_0F3A49 */
6467 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6470 /* PREFIX_VEX_0F3A4A */
6474 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6477 /* PREFIX_VEX_0F3A4B */
6481 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6484 /* PREFIX_VEX_0F3A4C */
6488 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6491 /* PREFIX_VEX_0F3A5C */
6495 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6498 /* PREFIX_VEX_0F3A5D */
6502 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6505 /* PREFIX_VEX_0F3A5E */
6509 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6512 /* PREFIX_VEX_0F3A5F */
6516 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6519 /* PREFIX_VEX_0F3A60 */
6523 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6527 /* PREFIX_VEX_0F3A61 */
6531 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6534 /* PREFIX_VEX_0F3A62 */
6538 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6541 /* PREFIX_VEX_0F3A63 */
6545 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6548 /* PREFIX_VEX_0F3A68 */
6552 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6555 /* PREFIX_VEX_0F3A69 */
6559 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6562 /* PREFIX_VEX_0F3A6A */
6566 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6569 /* PREFIX_VEX_0F3A6B */
6573 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6576 /* PREFIX_VEX_0F3A6C */
6580 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6583 /* PREFIX_VEX_0F3A6D */
6587 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6590 /* PREFIX_VEX_0F3A6E */
6594 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6597 /* PREFIX_VEX_0F3A6F */
6601 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6604 /* PREFIX_VEX_0F3A78 */
6608 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6611 /* PREFIX_VEX_0F3A79 */
6615 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6618 /* PREFIX_VEX_0F3A7A */
6622 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6625 /* PREFIX_VEX_0F3A7B */
6629 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6632 /* PREFIX_VEX_0F3A7C */
6636 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6640 /* PREFIX_VEX_0F3A7D */
6644 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6647 /* PREFIX_VEX_0F3A7E */
6651 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6654 /* PREFIX_VEX_0F3A7F */
6658 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6661 /* PREFIX_VEX_0F3ADF */
6665 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6668 /* PREFIX_VEX_0F3AF0 */
6673 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6676 #define NEED_PREFIX_TABLE
6677 #include "i386-dis-evex.h"
6678 #undef NEED_PREFIX_TABLE
6681 static const struct dis386 x86_64_table
[][2] = {
6684 { "pushP", { es
} },
6694 { "pushP", { cs
} },
6699 { "pushP", { ss
} },
6709 { "pushP", { ds
} },
6739 { "pushaP", { XX
} },
6744 { "popaP", { XX
} },
6749 { MOD_TABLE (MOD_62_32BIT
) },
6750 { EVEX_TABLE (EVEX_0F
) },
6755 { "arpl", { Ew
, Gw
} },
6756 { "movs{lq|xd}", { Gv
, Ed
} },
6761 { "ins{R|}", { Yzr
, indirDX
} },
6762 { "ins{G|}", { Yzr
, indirDX
} },
6767 { "outs{R|}", { indirDXr
, Xz
} },
6768 { "outs{G|}", { indirDXr
, Xz
} },
6773 { "Jcall{T|}", { Ap
} },
6778 { MOD_TABLE (MOD_C4_32BIT
) },
6779 { VEX_C4_TABLE (VEX_0F
) },
6784 { MOD_TABLE (MOD_C5_32BIT
) },
6785 { VEX_C5_TABLE (VEX_0F
) },
6805 { "Jjmp{T|}", { Ap
} },
6808 /* X86_64_0F01_REG_0 */
6810 { "sgdt{Q|IQ}", { M
} },
6814 /* X86_64_0F01_REG_1 */
6816 { "sidt{Q|IQ}", { M
} },
6820 /* X86_64_0F01_REG_2 */
6822 { "lgdt{Q|Q}", { M
} },
6826 /* X86_64_0F01_REG_3 */
6828 { "lidt{Q|Q}", { M
} },
6833 static const struct dis386 three_byte_table
[][256] = {
6835 /* THREE_BYTE_0F38 */
6838 { "pshufb", { MX
, EM
} },
6839 { "phaddw", { MX
, EM
} },
6840 { "phaddd", { MX
, EM
} },
6841 { "phaddsw", { MX
, EM
} },
6842 { "pmaddubsw", { MX
, EM
} },
6843 { "phsubw", { MX
, EM
} },
6844 { "phsubd", { MX
, EM
} },
6845 { "phsubsw", { MX
, EM
} },
6847 { "psignb", { MX
, EM
} },
6848 { "psignw", { MX
, EM
} },
6849 { "psignd", { MX
, EM
} },
6850 { "pmulhrsw", { MX
, EM
} },
6856 { PREFIX_TABLE (PREFIX_0F3810
) },
6860 { PREFIX_TABLE (PREFIX_0F3814
) },
6861 { PREFIX_TABLE (PREFIX_0F3815
) },
6863 { PREFIX_TABLE (PREFIX_0F3817
) },
6869 { "pabsb", { MX
, EM
} },
6870 { "pabsw", { MX
, EM
} },
6871 { "pabsd", { MX
, EM
} },
6874 { PREFIX_TABLE (PREFIX_0F3820
) },
6875 { PREFIX_TABLE (PREFIX_0F3821
) },
6876 { PREFIX_TABLE (PREFIX_0F3822
) },
6877 { PREFIX_TABLE (PREFIX_0F3823
) },
6878 { PREFIX_TABLE (PREFIX_0F3824
) },
6879 { PREFIX_TABLE (PREFIX_0F3825
) },
6883 { PREFIX_TABLE (PREFIX_0F3828
) },
6884 { PREFIX_TABLE (PREFIX_0F3829
) },
6885 { PREFIX_TABLE (PREFIX_0F382A
) },
6886 { PREFIX_TABLE (PREFIX_0F382B
) },
6892 { PREFIX_TABLE (PREFIX_0F3830
) },
6893 { PREFIX_TABLE (PREFIX_0F3831
) },
6894 { PREFIX_TABLE (PREFIX_0F3832
) },
6895 { PREFIX_TABLE (PREFIX_0F3833
) },
6896 { PREFIX_TABLE (PREFIX_0F3834
) },
6897 { PREFIX_TABLE (PREFIX_0F3835
) },
6899 { PREFIX_TABLE (PREFIX_0F3837
) },
6901 { PREFIX_TABLE (PREFIX_0F3838
) },
6902 { PREFIX_TABLE (PREFIX_0F3839
) },
6903 { PREFIX_TABLE (PREFIX_0F383A
) },
6904 { PREFIX_TABLE (PREFIX_0F383B
) },
6905 { PREFIX_TABLE (PREFIX_0F383C
) },
6906 { PREFIX_TABLE (PREFIX_0F383D
) },
6907 { PREFIX_TABLE (PREFIX_0F383E
) },
6908 { PREFIX_TABLE (PREFIX_0F383F
) },
6910 { PREFIX_TABLE (PREFIX_0F3840
) },
6911 { PREFIX_TABLE (PREFIX_0F3841
) },
6982 { PREFIX_TABLE (PREFIX_0F3880
) },
6983 { PREFIX_TABLE (PREFIX_0F3881
) },
6984 { PREFIX_TABLE (PREFIX_0F3882
) },
7063 { PREFIX_TABLE (PREFIX_0F38C8
) },
7064 { PREFIX_TABLE (PREFIX_0F38C9
) },
7065 { PREFIX_TABLE (PREFIX_0F38CA
) },
7066 { PREFIX_TABLE (PREFIX_0F38CB
) },
7067 { PREFIX_TABLE (PREFIX_0F38CC
) },
7068 { PREFIX_TABLE (PREFIX_0F38CD
) },
7084 { PREFIX_TABLE (PREFIX_0F38DB
) },
7085 { PREFIX_TABLE (PREFIX_0F38DC
) },
7086 { PREFIX_TABLE (PREFIX_0F38DD
) },
7087 { PREFIX_TABLE (PREFIX_0F38DE
) },
7088 { PREFIX_TABLE (PREFIX_0F38DF
) },
7108 { PREFIX_TABLE (PREFIX_0F38F0
) },
7109 { PREFIX_TABLE (PREFIX_0F38F1
) },
7114 { PREFIX_TABLE (PREFIX_0F38F6
) },
7126 /* THREE_BYTE_0F3A */
7138 { PREFIX_TABLE (PREFIX_0F3A08
) },
7139 { PREFIX_TABLE (PREFIX_0F3A09
) },
7140 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7141 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7142 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7143 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7144 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7145 { "palignr", { MX
, EM
, Ib
} },
7151 { PREFIX_TABLE (PREFIX_0F3A14
) },
7152 { PREFIX_TABLE (PREFIX_0F3A15
) },
7153 { PREFIX_TABLE (PREFIX_0F3A16
) },
7154 { PREFIX_TABLE (PREFIX_0F3A17
) },
7165 { PREFIX_TABLE (PREFIX_0F3A20
) },
7166 { PREFIX_TABLE (PREFIX_0F3A21
) },
7167 { PREFIX_TABLE (PREFIX_0F3A22
) },
7201 { PREFIX_TABLE (PREFIX_0F3A40
) },
7202 { PREFIX_TABLE (PREFIX_0F3A41
) },
7203 { PREFIX_TABLE (PREFIX_0F3A42
) },
7205 { PREFIX_TABLE (PREFIX_0F3A44
) },
7237 { PREFIX_TABLE (PREFIX_0F3A60
) },
7238 { PREFIX_TABLE (PREFIX_0F3A61
) },
7239 { PREFIX_TABLE (PREFIX_0F3A62
) },
7240 { PREFIX_TABLE (PREFIX_0F3A63
) },
7358 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7379 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7418 /* THREE_BYTE_0F7A */
7457 { "ptest", { XX
} },
7494 { "phaddbw", { XM
, EXq
} },
7495 { "phaddbd", { XM
, EXq
} },
7496 { "phaddbq", { XM
, EXq
} },
7499 { "phaddwd", { XM
, EXq
} },
7500 { "phaddwq", { XM
, EXq
} },
7505 { "phadddq", { XM
, EXq
} },
7512 { "phaddubw", { XM
, EXq
} },
7513 { "phaddubd", { XM
, EXq
} },
7514 { "phaddubq", { XM
, EXq
} },
7517 { "phadduwd", { XM
, EXq
} },
7518 { "phadduwq", { XM
, EXq
} },
7523 { "phaddudq", { XM
, EXq
} },
7530 { "phsubbw", { XM
, EXq
} },
7531 { "phsubbd", { XM
, EXq
} },
7532 { "phsubbq", { XM
, EXq
} },
7711 static const struct dis386 xop_table
[][256] = {
7864 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7865 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7866 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7874 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7875 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7882 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7883 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7884 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7892 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7893 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7897 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7898 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7901 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7919 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7931 { "vprotb", { XM
, Vex_2src_1
, Ib
} },
7932 { "vprotw", { XM
, Vex_2src_1
, Ib
} },
7933 { "vprotd", { XM
, Vex_2src_1
, Ib
} },
7934 { "vprotq", { XM
, Vex_2src_1
, Ib
} },
7944 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7945 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7946 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7947 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7980 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7981 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7982 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7983 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8007 { REG_TABLE (REG_XOP_TBM_01
) },
8008 { REG_TABLE (REG_XOP_TBM_02
) },
8026 { REG_TABLE (REG_XOP_LWPCB
) },
8150 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8151 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8152 { "vfrczss", { XM
, EXd
} },
8153 { "vfrczsd", { XM
, EXq
} },
8168 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
} },
8169 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
} },
8170 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
} },
8171 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
} },
8172 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
} },
8173 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
} },
8174 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
} },
8175 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
} },
8177 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
} },
8178 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
} },
8179 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
} },
8180 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
} },
8223 { "vphaddbw", { XM
, EXxmm
} },
8224 { "vphaddbd", { XM
, EXxmm
} },
8225 { "vphaddbq", { XM
, EXxmm
} },
8228 { "vphaddwd", { XM
, EXxmm
} },
8229 { "vphaddwq", { XM
, EXxmm
} },
8234 { "vphadddq", { XM
, EXxmm
} },
8241 { "vphaddubw", { XM
, EXxmm
} },
8242 { "vphaddubd", { XM
, EXxmm
} },
8243 { "vphaddubq", { XM
, EXxmm
} },
8246 { "vphadduwd", { XM
, EXxmm
} },
8247 { "vphadduwq", { XM
, EXxmm
} },
8252 { "vphaddudq", { XM
, EXxmm
} },
8259 { "vphsubbw", { XM
, EXxmm
} },
8260 { "vphsubwd", { XM
, EXxmm
} },
8261 { "vphsubdq", { XM
, EXxmm
} },
8315 { "bextr", { Gv
, Ev
, Iq
} },
8317 { REG_TABLE (REG_XOP_LWP
) },
8587 static const struct dis386 vex_table
[][256] = {
8609 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8610 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8611 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8612 { MOD_TABLE (MOD_VEX_0F13
) },
8613 { VEX_W_TABLE (VEX_W_0F14
) },
8614 { VEX_W_TABLE (VEX_W_0F15
) },
8615 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8616 { MOD_TABLE (MOD_VEX_0F17
) },
8636 { VEX_W_TABLE (VEX_W_0F28
) },
8637 { VEX_W_TABLE (VEX_W_0F29
) },
8638 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8639 { MOD_TABLE (MOD_VEX_0F2B
) },
8640 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8641 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8681 { MOD_TABLE (MOD_VEX_0F50
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8685 { "vandpX", { XM
, Vex
, EXx
} },
8686 { "vandnpX", { XM
, Vex
, EXx
} },
8687 { "vorpX", { XM
, Vex
, EXx
} },
8688 { "vxorpX", { XM
, Vex
, EXx
} },
8690 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8718 { REG_TABLE (REG_VEX_0F71
) },
8719 { REG_TABLE (REG_VEX_0F72
) },
8720 { REG_TABLE (REG_VEX_0F73
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8786 { REG_TABLE (REG_VEX_0FAE
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8813 { "vshufpX", { XM
, Vex
, EXx
, Ib
} },
8825 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8827 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8832 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8834 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8835 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8836 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8837 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8838 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8840 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8841 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8843 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8844 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8845 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8849 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8852 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8854 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8855 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8856 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8863 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8872 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8874 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8875 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8876 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8981 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9155 { REG_TABLE (REG_VEX_0F38F3
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9179 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9182 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9185 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9197 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9198 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9200 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9201 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9209 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9210 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9211 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9227 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9228 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9229 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9230 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9236 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9237 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9245 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9247 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9249 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9251 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9254 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9255 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9256 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9257 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9258 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9276 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9277 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9278 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9279 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9281 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9282 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9283 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9284 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9290 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9291 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9292 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9293 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9294 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9295 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9296 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9297 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9308 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9309 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9423 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9443 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9463 #define NEED_OPCODE_TABLE
9464 #include "i386-dis-evex.h"
9465 #undef NEED_OPCODE_TABLE
9466 static const struct dis386 vex_len_table
[][2] = {
9467 /* VEX_LEN_0F10_P_1 */
9469 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9470 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9473 /* VEX_LEN_0F10_P_3 */
9475 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9476 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9479 /* VEX_LEN_0F11_P_1 */
9481 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9482 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9485 /* VEX_LEN_0F11_P_3 */
9487 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9488 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9491 /* VEX_LEN_0F12_P_0_M_0 */
9493 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9496 /* VEX_LEN_0F12_P_0_M_1 */
9498 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9501 /* VEX_LEN_0F12_P_2 */
9503 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9506 /* VEX_LEN_0F13_M_0 */
9508 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9511 /* VEX_LEN_0F16_P_0_M_0 */
9513 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9516 /* VEX_LEN_0F16_P_0_M_1 */
9518 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9521 /* VEX_LEN_0F16_P_2 */
9523 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9526 /* VEX_LEN_0F17_M_0 */
9528 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9531 /* VEX_LEN_0F2A_P_1 */
9533 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
9534 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
9537 /* VEX_LEN_0F2A_P_3 */
9539 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
9540 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
9543 /* VEX_LEN_0F2C_P_1 */
9545 { "vcvttss2siY", { Gv
, EXdScalar
} },
9546 { "vcvttss2siY", { Gv
, EXdScalar
} },
9549 /* VEX_LEN_0F2C_P_3 */
9551 { "vcvttsd2siY", { Gv
, EXqScalar
} },
9552 { "vcvttsd2siY", { Gv
, EXqScalar
} },
9555 /* VEX_LEN_0F2D_P_1 */
9557 { "vcvtss2siY", { Gv
, EXdScalar
} },
9558 { "vcvtss2siY", { Gv
, EXdScalar
} },
9561 /* VEX_LEN_0F2D_P_3 */
9563 { "vcvtsd2siY", { Gv
, EXqScalar
} },
9564 { "vcvtsd2siY", { Gv
, EXqScalar
} },
9567 /* VEX_LEN_0F2E_P_0 */
9569 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9570 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9573 /* VEX_LEN_0F2E_P_2 */
9575 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9576 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9579 /* VEX_LEN_0F2F_P_0 */
9581 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9582 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9585 /* VEX_LEN_0F2F_P_2 */
9587 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9588 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9591 /* VEX_LEN_0F41_P_0 */
9594 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9596 /* VEX_LEN_0F41_P_2 */
9599 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9601 /* VEX_LEN_0F42_P_0 */
9604 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9606 /* VEX_LEN_0F42_P_2 */
9609 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9611 /* VEX_LEN_0F44_P_0 */
9613 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9615 /* VEX_LEN_0F44_P_2 */
9617 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9619 /* VEX_LEN_0F45_P_0 */
9622 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9624 /* VEX_LEN_0F45_P_2 */
9627 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9629 /* VEX_LEN_0F46_P_0 */
9632 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9634 /* VEX_LEN_0F46_P_2 */
9637 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9639 /* VEX_LEN_0F47_P_0 */
9642 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9644 /* VEX_LEN_0F47_P_2 */
9647 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9649 /* VEX_LEN_0F4A_P_0 */
9652 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9654 /* VEX_LEN_0F4A_P_2 */
9657 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9659 /* VEX_LEN_0F4B_P_0 */
9662 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9664 /* VEX_LEN_0F4B_P_2 */
9667 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9670 /* VEX_LEN_0F51_P_1 */
9672 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9673 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9676 /* VEX_LEN_0F51_P_3 */
9678 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9679 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9682 /* VEX_LEN_0F52_P_1 */
9684 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9685 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9688 /* VEX_LEN_0F53_P_1 */
9690 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9691 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9694 /* VEX_LEN_0F58_P_1 */
9696 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9697 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9700 /* VEX_LEN_0F58_P_3 */
9702 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9703 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9706 /* VEX_LEN_0F59_P_1 */
9708 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9709 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9712 /* VEX_LEN_0F59_P_3 */
9714 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9715 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9718 /* VEX_LEN_0F5A_P_1 */
9720 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9721 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9724 /* VEX_LEN_0F5A_P_3 */
9726 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9727 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9730 /* VEX_LEN_0F5C_P_1 */
9732 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9733 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9736 /* VEX_LEN_0F5C_P_3 */
9738 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9739 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9742 /* VEX_LEN_0F5D_P_1 */
9744 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9745 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9748 /* VEX_LEN_0F5D_P_3 */
9750 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9751 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9754 /* VEX_LEN_0F5E_P_1 */
9756 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9757 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9760 /* VEX_LEN_0F5E_P_3 */
9762 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9763 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9766 /* VEX_LEN_0F5F_P_1 */
9768 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9769 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9772 /* VEX_LEN_0F5F_P_3 */
9774 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9775 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9778 /* VEX_LEN_0F6E_P_2 */
9780 { "vmovK", { XMScalar
, Edq
} },
9781 { "vmovK", { XMScalar
, Edq
} },
9784 /* VEX_LEN_0F7E_P_1 */
9786 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9787 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9790 /* VEX_LEN_0F7E_P_2 */
9792 { "vmovK", { Edq
, XMScalar
} },
9793 { "vmovK", { Edq
, XMScalar
} },
9796 /* VEX_LEN_0F90_P_0 */
9798 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9801 /* VEX_LEN_0F90_P_2 */
9803 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9806 /* VEX_LEN_0F91_P_0 */
9808 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9811 /* VEX_LEN_0F91_P_2 */
9813 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9816 /* VEX_LEN_0F92_P_0 */
9818 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9821 /* VEX_LEN_0F92_P_2 */
9823 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9826 /* VEX_LEN_0F92_P_3 */
9828 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9831 /* VEX_LEN_0F93_P_0 */
9833 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9836 /* VEX_LEN_0F93_P_2 */
9838 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9841 /* VEX_LEN_0F93_P_3 */
9843 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9846 /* VEX_LEN_0F98_P_0 */
9848 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9851 /* VEX_LEN_0F98_P_2 */
9853 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9856 /* VEX_LEN_0F99_P_0 */
9858 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9861 /* VEX_LEN_0F99_P_2 */
9863 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9866 /* VEX_LEN_0FAE_R_2_M_0 */
9868 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9871 /* VEX_LEN_0FAE_R_3_M_0 */
9873 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9876 /* VEX_LEN_0FC2_P_1 */
9878 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9879 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9882 /* VEX_LEN_0FC2_P_3 */
9884 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9885 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9888 /* VEX_LEN_0FC4_P_2 */
9890 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9893 /* VEX_LEN_0FC5_P_2 */
9895 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9898 /* VEX_LEN_0FD6_P_2 */
9900 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9901 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9904 /* VEX_LEN_0FF7_P_2 */
9906 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9909 /* VEX_LEN_0F3816_P_2 */
9912 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9915 /* VEX_LEN_0F3819_P_2 */
9918 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9921 /* VEX_LEN_0F381A_P_2_M_0 */
9924 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9927 /* VEX_LEN_0F3836_P_2 */
9930 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9933 /* VEX_LEN_0F3841_P_2 */
9935 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9938 /* VEX_LEN_0F385A_P_2_M_0 */
9941 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9944 /* VEX_LEN_0F38DB_P_2 */
9946 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9949 /* VEX_LEN_0F38DC_P_2 */
9951 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
9954 /* VEX_LEN_0F38DD_P_2 */
9956 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
9959 /* VEX_LEN_0F38DE_P_2 */
9961 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
9964 /* VEX_LEN_0F38DF_P_2 */
9966 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
9969 /* VEX_LEN_0F38F2_P_0 */
9971 { "andnS", { Gdq
, VexGdq
, Edq
} },
9974 /* VEX_LEN_0F38F3_R_1_P_0 */
9976 { "blsrS", { VexGdq
, Edq
} },
9979 /* VEX_LEN_0F38F3_R_2_P_0 */
9981 { "blsmskS", { VexGdq
, Edq
} },
9984 /* VEX_LEN_0F38F3_R_3_P_0 */
9986 { "blsiS", { VexGdq
, Edq
} },
9989 /* VEX_LEN_0F38F5_P_0 */
9991 { "bzhiS", { Gdq
, Edq
, VexGdq
} },
9994 /* VEX_LEN_0F38F5_P_1 */
9996 { "pextS", { Gdq
, VexGdq
, Edq
} },
9999 /* VEX_LEN_0F38F5_P_3 */
10001 { "pdepS", { Gdq
, VexGdq
, Edq
} },
10004 /* VEX_LEN_0F38F6_P_3 */
10006 { "mulxS", { Gdq
, VexGdq
, Edq
} },
10009 /* VEX_LEN_0F38F7_P_0 */
10011 { "bextrS", { Gdq
, Edq
, VexGdq
} },
10014 /* VEX_LEN_0F38F7_P_1 */
10016 { "sarxS", { Gdq
, Edq
, VexGdq
} },
10019 /* VEX_LEN_0F38F7_P_2 */
10021 { "shlxS", { Gdq
, Edq
, VexGdq
} },
10024 /* VEX_LEN_0F38F7_P_3 */
10026 { "shrxS", { Gdq
, Edq
, VexGdq
} },
10029 /* VEX_LEN_0F3A00_P_2 */
10032 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10035 /* VEX_LEN_0F3A01_P_2 */
10038 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10041 /* VEX_LEN_0F3A06_P_2 */
10044 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10047 /* VEX_LEN_0F3A0A_P_2 */
10049 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10050 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10053 /* VEX_LEN_0F3A0B_P_2 */
10055 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10056 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10059 /* VEX_LEN_0F3A14_P_2 */
10061 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10064 /* VEX_LEN_0F3A15_P_2 */
10066 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10069 /* VEX_LEN_0F3A16_P_2 */
10071 { "vpextrK", { Edq
, XM
, Ib
} },
10074 /* VEX_LEN_0F3A17_P_2 */
10076 { "vextractps", { Edqd
, XM
, Ib
} },
10079 /* VEX_LEN_0F3A18_P_2 */
10082 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10085 /* VEX_LEN_0F3A19_P_2 */
10088 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10091 /* VEX_LEN_0F3A20_P_2 */
10093 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10096 /* VEX_LEN_0F3A21_P_2 */
10098 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10101 /* VEX_LEN_0F3A22_P_2 */
10103 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
} },
10106 /* VEX_LEN_0F3A30_P_2 */
10108 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10111 /* VEX_LEN_0F3A31_P_2 */
10113 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10116 /* VEX_LEN_0F3A32_P_2 */
10118 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10121 /* VEX_LEN_0F3A33_P_2 */
10123 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10126 /* VEX_LEN_0F3A38_P_2 */
10129 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10132 /* VEX_LEN_0F3A39_P_2 */
10135 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10138 /* VEX_LEN_0F3A41_P_2 */
10140 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10143 /* VEX_LEN_0F3A44_P_2 */
10145 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
10148 /* VEX_LEN_0F3A46_P_2 */
10151 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10154 /* VEX_LEN_0F3A60_P_2 */
10156 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
10159 /* VEX_LEN_0F3A61_P_2 */
10161 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
10164 /* VEX_LEN_0F3A62_P_2 */
10166 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10169 /* VEX_LEN_0F3A63_P_2 */
10171 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10174 /* VEX_LEN_0F3A6A_P_2 */
10176 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
10179 /* VEX_LEN_0F3A6B_P_2 */
10181 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
10184 /* VEX_LEN_0F3A6E_P_2 */
10186 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
10189 /* VEX_LEN_0F3A6F_P_2 */
10191 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
10194 /* VEX_LEN_0F3A7A_P_2 */
10196 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
10199 /* VEX_LEN_0F3A7B_P_2 */
10201 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
10204 /* VEX_LEN_0F3A7E_P_2 */
10206 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
10209 /* VEX_LEN_0F3A7F_P_2 */
10211 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
10214 /* VEX_LEN_0F3ADF_P_2 */
10216 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10219 /* VEX_LEN_0F3AF0_P_3 */
10221 { "rorxS", { Gdq
, Edq
, Ib
} },
10224 /* VEX_LEN_0FXOP_08_CC */
10226 { "vpcomb", { XM
, Vex128
, EXx
, Ib
} },
10229 /* VEX_LEN_0FXOP_08_CD */
10231 { "vpcomw", { XM
, Vex128
, EXx
, Ib
} },
10234 /* VEX_LEN_0FXOP_08_CE */
10236 { "vpcomd", { XM
, Vex128
, EXx
, Ib
} },
10239 /* VEX_LEN_0FXOP_08_CF */
10241 { "vpcomq", { XM
, Vex128
, EXx
, Ib
} },
10244 /* VEX_LEN_0FXOP_08_EC */
10246 { "vpcomub", { XM
, Vex128
, EXx
, Ib
} },
10249 /* VEX_LEN_0FXOP_08_ED */
10251 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
} },
10254 /* VEX_LEN_0FXOP_08_EE */
10256 { "vpcomud", { XM
, Vex128
, EXx
, Ib
} },
10259 /* VEX_LEN_0FXOP_08_EF */
10261 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
} },
10264 /* VEX_LEN_0FXOP_09_80 */
10266 { "vfrczps", { XM
, EXxmm
} },
10267 { "vfrczps", { XM
, EXymmq
} },
10270 /* VEX_LEN_0FXOP_09_81 */
10272 { "vfrczpd", { XM
, EXxmm
} },
10273 { "vfrczpd", { XM
, EXymmq
} },
10277 static const struct dis386 vex_w_table
[][2] = {
10279 /* VEX_W_0F10_P_0 */
10280 { "vmovups", { XM
, EXx
} },
10283 /* VEX_W_0F10_P_1 */
10284 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
} },
10287 /* VEX_W_0F10_P_2 */
10288 { "vmovupd", { XM
, EXx
} },
10291 /* VEX_W_0F10_P_3 */
10292 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
} },
10295 /* VEX_W_0F11_P_0 */
10296 { "vmovups", { EXxS
, XM
} },
10299 /* VEX_W_0F11_P_1 */
10300 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
} },
10303 /* VEX_W_0F11_P_2 */
10304 { "vmovupd", { EXxS
, XM
} },
10307 /* VEX_W_0F11_P_3 */
10308 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
} },
10311 /* VEX_W_0F12_P_0_M_0 */
10312 { "vmovlps", { XM
, Vex128
, EXq
} },
10315 /* VEX_W_0F12_P_0_M_1 */
10316 { "vmovhlps", { XM
, Vex128
, EXq
} },
10319 /* VEX_W_0F12_P_1 */
10320 { "vmovsldup", { XM
, EXx
} },
10323 /* VEX_W_0F12_P_2 */
10324 { "vmovlpd", { XM
, Vex128
, EXq
} },
10327 /* VEX_W_0F12_P_3 */
10328 { "vmovddup", { XM
, EXymmq
} },
10331 /* VEX_W_0F13_M_0 */
10332 { "vmovlpX", { EXq
, XM
} },
10336 { "vunpcklpX", { XM
, Vex
, EXx
} },
10340 { "vunpckhpX", { XM
, Vex
, EXx
} },
10343 /* VEX_W_0F16_P_0_M_0 */
10344 { "vmovhps", { XM
, Vex128
, EXq
} },
10347 /* VEX_W_0F16_P_0_M_1 */
10348 { "vmovlhps", { XM
, Vex128
, EXq
} },
10351 /* VEX_W_0F16_P_1 */
10352 { "vmovshdup", { XM
, EXx
} },
10355 /* VEX_W_0F16_P_2 */
10356 { "vmovhpd", { XM
, Vex128
, EXq
} },
10359 /* VEX_W_0F17_M_0 */
10360 { "vmovhpX", { EXq
, XM
} },
10364 { "vmovapX", { XM
, EXx
} },
10368 { "vmovapX", { EXxS
, XM
} },
10371 /* VEX_W_0F2B_M_0 */
10372 { "vmovntpX", { Mx
, XM
} },
10375 /* VEX_W_0F2E_P_0 */
10376 { "vucomiss", { XMScalar
, EXdScalar
} },
10379 /* VEX_W_0F2E_P_2 */
10380 { "vucomisd", { XMScalar
, EXqScalar
} },
10383 /* VEX_W_0F2F_P_0 */
10384 { "vcomiss", { XMScalar
, EXdScalar
} },
10387 /* VEX_W_0F2F_P_2 */
10388 { "vcomisd", { XMScalar
, EXqScalar
} },
10391 /* VEX_W_0F41_P_0_LEN_1 */
10392 { "kandw", { MaskG
, MaskVex
, MaskR
} },
10393 { "kandq", { MaskG
, MaskVex
, MaskR
} },
10396 /* VEX_W_0F41_P_2_LEN_1 */
10397 { "kandb", { MaskG
, MaskVex
, MaskR
} },
10398 { "kandd", { MaskG
, MaskVex
, MaskR
} },
10401 /* VEX_W_0F42_P_0_LEN_1 */
10402 { "kandnw", { MaskG
, MaskVex
, MaskR
} },
10403 { "kandnq", { MaskG
, MaskVex
, MaskR
} },
10406 /* VEX_W_0F42_P_2_LEN_1 */
10407 { "kandnb", { MaskG
, MaskVex
, MaskR
} },
10408 { "kandnd", { MaskG
, MaskVex
, MaskR
} },
10411 /* VEX_W_0F44_P_0_LEN_0 */
10412 { "knotw", { MaskG
, MaskR
} },
10413 { "knotq", { MaskG
, MaskR
} },
10416 /* VEX_W_0F44_P_2_LEN_0 */
10417 { "knotb", { MaskG
, MaskR
} },
10418 { "knotd", { MaskG
, MaskR
} },
10421 /* VEX_W_0F45_P_0_LEN_1 */
10422 { "korw", { MaskG
, MaskVex
, MaskR
} },
10423 { "korq", { MaskG
, MaskVex
, MaskR
} },
10426 /* VEX_W_0F45_P_2_LEN_1 */
10427 { "korb", { MaskG
, MaskVex
, MaskR
} },
10428 { "kord", { MaskG
, MaskVex
, MaskR
} },
10431 /* VEX_W_0F46_P_0_LEN_1 */
10432 { "kxnorw", { MaskG
, MaskVex
, MaskR
} },
10433 { "kxnorq", { MaskG
, MaskVex
, MaskR
} },
10436 /* VEX_W_0F46_P_2_LEN_1 */
10437 { "kxnorb", { MaskG
, MaskVex
, MaskR
} },
10438 { "kxnord", { MaskG
, MaskVex
, MaskR
} },
10441 /* VEX_W_0F47_P_0_LEN_1 */
10442 { "kxorw", { MaskG
, MaskVex
, MaskR
} },
10443 { "kxorq", { MaskG
, MaskVex
, MaskR
} },
10446 /* VEX_W_0F47_P_2_LEN_1 */
10447 { "kxorb", { MaskG
, MaskVex
, MaskR
} },
10448 { "kxord", { MaskG
, MaskVex
, MaskR
} },
10451 /* VEX_W_0F4A_P_0_LEN_1 */
10452 { "kaddw", { MaskG
, MaskVex
, MaskR
} },
10453 { "kaddq", { MaskG
, MaskVex
, MaskR
} },
10456 /* VEX_W_0F4A_P_2_LEN_1 */
10457 { "kaddb", { MaskG
, MaskVex
, MaskR
} },
10458 { "kaddd", { MaskG
, MaskVex
, MaskR
} },
10461 /* VEX_W_0F4B_P_0_LEN_1 */
10462 { "kunpckwd", { MaskG
, MaskVex
, MaskR
} },
10463 { "kunpckdq", { MaskG
, MaskVex
, MaskR
} },
10466 /* VEX_W_0F4B_P_2_LEN_1 */
10467 { "kunpckbw", { MaskG
, MaskVex
, MaskR
} },
10470 /* VEX_W_0F50_M_0 */
10471 { "vmovmskpX", { Gdq
, XS
} },
10474 /* VEX_W_0F51_P_0 */
10475 { "vsqrtps", { XM
, EXx
} },
10478 /* VEX_W_0F51_P_1 */
10479 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
10482 /* VEX_W_0F51_P_2 */
10483 { "vsqrtpd", { XM
, EXx
} },
10486 /* VEX_W_0F51_P_3 */
10487 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
} },
10490 /* VEX_W_0F52_P_0 */
10491 { "vrsqrtps", { XM
, EXx
} },
10494 /* VEX_W_0F52_P_1 */
10495 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
10498 /* VEX_W_0F53_P_0 */
10499 { "vrcpps", { XM
, EXx
} },
10502 /* VEX_W_0F53_P_1 */
10503 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
} },
10506 /* VEX_W_0F58_P_0 */
10507 { "vaddps", { XM
, Vex
, EXx
} },
10510 /* VEX_W_0F58_P_1 */
10511 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
} },
10514 /* VEX_W_0F58_P_2 */
10515 { "vaddpd", { XM
, Vex
, EXx
} },
10518 /* VEX_W_0F58_P_3 */
10519 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
} },
10522 /* VEX_W_0F59_P_0 */
10523 { "vmulps", { XM
, Vex
, EXx
} },
10526 /* VEX_W_0F59_P_1 */
10527 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
} },
10530 /* VEX_W_0F59_P_2 */
10531 { "vmulpd", { XM
, Vex
, EXx
} },
10534 /* VEX_W_0F59_P_3 */
10535 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
} },
10538 /* VEX_W_0F5A_P_0 */
10539 { "vcvtps2pd", { XM
, EXxmmq
} },
10542 /* VEX_W_0F5A_P_1 */
10543 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
} },
10546 /* VEX_W_0F5A_P_3 */
10547 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
} },
10550 /* VEX_W_0F5B_P_0 */
10551 { "vcvtdq2ps", { XM
, EXx
} },
10554 /* VEX_W_0F5B_P_1 */
10555 { "vcvttps2dq", { XM
, EXx
} },
10558 /* VEX_W_0F5B_P_2 */
10559 { "vcvtps2dq", { XM
, EXx
} },
10562 /* VEX_W_0F5C_P_0 */
10563 { "vsubps", { XM
, Vex
, EXx
} },
10566 /* VEX_W_0F5C_P_1 */
10567 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
} },
10570 /* VEX_W_0F5C_P_2 */
10571 { "vsubpd", { XM
, Vex
, EXx
} },
10574 /* VEX_W_0F5C_P_3 */
10575 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
} },
10578 /* VEX_W_0F5D_P_0 */
10579 { "vminps", { XM
, Vex
, EXx
} },
10582 /* VEX_W_0F5D_P_1 */
10583 { "vminss", { XMScalar
, VexScalar
, EXdScalar
} },
10586 /* VEX_W_0F5D_P_2 */
10587 { "vminpd", { XM
, Vex
, EXx
} },
10590 /* VEX_W_0F5D_P_3 */
10591 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
} },
10594 /* VEX_W_0F5E_P_0 */
10595 { "vdivps", { XM
, Vex
, EXx
} },
10598 /* VEX_W_0F5E_P_1 */
10599 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
} },
10602 /* VEX_W_0F5E_P_2 */
10603 { "vdivpd", { XM
, Vex
, EXx
} },
10606 /* VEX_W_0F5E_P_3 */
10607 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
} },
10610 /* VEX_W_0F5F_P_0 */
10611 { "vmaxps", { XM
, Vex
, EXx
} },
10614 /* VEX_W_0F5F_P_1 */
10615 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
} },
10618 /* VEX_W_0F5F_P_2 */
10619 { "vmaxpd", { XM
, Vex
, EXx
} },
10622 /* VEX_W_0F5F_P_3 */
10623 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
} },
10626 /* VEX_W_0F60_P_2 */
10627 { "vpunpcklbw", { XM
, Vex
, EXx
} },
10630 /* VEX_W_0F61_P_2 */
10631 { "vpunpcklwd", { XM
, Vex
, EXx
} },
10634 /* VEX_W_0F62_P_2 */
10635 { "vpunpckldq", { XM
, Vex
, EXx
} },
10638 /* VEX_W_0F63_P_2 */
10639 { "vpacksswb", { XM
, Vex
, EXx
} },
10642 /* VEX_W_0F64_P_2 */
10643 { "vpcmpgtb", { XM
, Vex
, EXx
} },
10646 /* VEX_W_0F65_P_2 */
10647 { "vpcmpgtw", { XM
, Vex
, EXx
} },
10650 /* VEX_W_0F66_P_2 */
10651 { "vpcmpgtd", { XM
, Vex
, EXx
} },
10654 /* VEX_W_0F67_P_2 */
10655 { "vpackuswb", { XM
, Vex
, EXx
} },
10658 /* VEX_W_0F68_P_2 */
10659 { "vpunpckhbw", { XM
, Vex
, EXx
} },
10662 /* VEX_W_0F69_P_2 */
10663 { "vpunpckhwd", { XM
, Vex
, EXx
} },
10666 /* VEX_W_0F6A_P_2 */
10667 { "vpunpckhdq", { XM
, Vex
, EXx
} },
10670 /* VEX_W_0F6B_P_2 */
10671 { "vpackssdw", { XM
, Vex
, EXx
} },
10674 /* VEX_W_0F6C_P_2 */
10675 { "vpunpcklqdq", { XM
, Vex
, EXx
} },
10678 /* VEX_W_0F6D_P_2 */
10679 { "vpunpckhqdq", { XM
, Vex
, EXx
} },
10682 /* VEX_W_0F6F_P_1 */
10683 { "vmovdqu", { XM
, EXx
} },
10686 /* VEX_W_0F6F_P_2 */
10687 { "vmovdqa", { XM
, EXx
} },
10690 /* VEX_W_0F70_P_1 */
10691 { "vpshufhw", { XM
, EXx
, Ib
} },
10694 /* VEX_W_0F70_P_2 */
10695 { "vpshufd", { XM
, EXx
, Ib
} },
10698 /* VEX_W_0F70_P_3 */
10699 { "vpshuflw", { XM
, EXx
, Ib
} },
10702 /* VEX_W_0F71_R_2_P_2 */
10703 { "vpsrlw", { Vex
, XS
, Ib
} },
10706 /* VEX_W_0F71_R_4_P_2 */
10707 { "vpsraw", { Vex
, XS
, Ib
} },
10710 /* VEX_W_0F71_R_6_P_2 */
10711 { "vpsllw", { Vex
, XS
, Ib
} },
10714 /* VEX_W_0F72_R_2_P_2 */
10715 { "vpsrld", { Vex
, XS
, Ib
} },
10718 /* VEX_W_0F72_R_4_P_2 */
10719 { "vpsrad", { Vex
, XS
, Ib
} },
10722 /* VEX_W_0F72_R_6_P_2 */
10723 { "vpslld", { Vex
, XS
, Ib
} },
10726 /* VEX_W_0F73_R_2_P_2 */
10727 { "vpsrlq", { Vex
, XS
, Ib
} },
10730 /* VEX_W_0F73_R_3_P_2 */
10731 { "vpsrldq", { Vex
, XS
, Ib
} },
10734 /* VEX_W_0F73_R_6_P_2 */
10735 { "vpsllq", { Vex
, XS
, Ib
} },
10738 /* VEX_W_0F73_R_7_P_2 */
10739 { "vpslldq", { Vex
, XS
, Ib
} },
10742 /* VEX_W_0F74_P_2 */
10743 { "vpcmpeqb", { XM
, Vex
, EXx
} },
10746 /* VEX_W_0F75_P_2 */
10747 { "vpcmpeqw", { XM
, Vex
, EXx
} },
10750 /* VEX_W_0F76_P_2 */
10751 { "vpcmpeqd", { XM
, Vex
, EXx
} },
10754 /* VEX_W_0F77_P_0 */
10758 /* VEX_W_0F7C_P_2 */
10759 { "vhaddpd", { XM
, Vex
, EXx
} },
10762 /* VEX_W_0F7C_P_3 */
10763 { "vhaddps", { XM
, Vex
, EXx
} },
10766 /* VEX_W_0F7D_P_2 */
10767 { "vhsubpd", { XM
, Vex
, EXx
} },
10770 /* VEX_W_0F7D_P_3 */
10771 { "vhsubps", { XM
, Vex
, EXx
} },
10774 /* VEX_W_0F7E_P_1 */
10775 { "vmovq", { XMScalar
, EXqScalar
} },
10778 /* VEX_W_0F7F_P_1 */
10779 { "vmovdqu", { EXxS
, XM
} },
10782 /* VEX_W_0F7F_P_2 */
10783 { "vmovdqa", { EXxS
, XM
} },
10786 /* VEX_W_0F90_P_0_LEN_0 */
10787 { "kmovw", { MaskG
, MaskE
} },
10788 { "kmovq", { MaskG
, MaskE
} },
10791 /* VEX_W_0F90_P_2_LEN_0 */
10792 { "kmovb", { MaskG
, MaskBDE
} },
10793 { "kmovd", { MaskG
, MaskBDE
} },
10796 /* VEX_W_0F91_P_0_LEN_0 */
10797 { "kmovw", { Ew
, MaskG
} },
10798 { "kmovq", { Eq
, MaskG
} },
10801 /* VEX_W_0F91_P_2_LEN_0 */
10802 { "kmovb", { Eb
, MaskG
} },
10803 { "kmovd", { Ed
, MaskG
} },
10806 /* VEX_W_0F92_P_0_LEN_0 */
10807 { "kmovw", { MaskG
, Rdq
} },
10810 /* VEX_W_0F92_P_2_LEN_0 */
10811 { "kmovb", { MaskG
, Rdq
} },
10814 /* VEX_W_0F92_P_3_LEN_0 */
10815 { "kmovd", { MaskG
, Rdq
} },
10816 { "kmovq", { MaskG
, Rdq
} },
10819 /* VEX_W_0F93_P_0_LEN_0 */
10820 { "kmovw", { Gdq
, MaskR
} },
10823 /* VEX_W_0F93_P_2_LEN_0 */
10824 { "kmovb", { Gdq
, MaskR
} },
10827 /* VEX_W_0F93_P_3_LEN_0 */
10828 { "kmovd", { Gdq
, MaskR
} },
10829 { "kmovq", { Gdq
, MaskR
} },
10832 /* VEX_W_0F98_P_0_LEN_0 */
10833 { "kortestw", { MaskG
, MaskR
} },
10834 { "kortestq", { MaskG
, MaskR
} },
10837 /* VEX_W_0F98_P_2_LEN_0 */
10838 { "kortestb", { MaskG
, MaskR
} },
10839 { "kortestd", { MaskG
, MaskR
} },
10842 /* VEX_W_0F99_P_0_LEN_0 */
10843 { "ktestw", { MaskG
, MaskR
} },
10844 { "ktestq", { MaskG
, MaskR
} },
10847 /* VEX_W_0F99_P_2_LEN_0 */
10848 { "ktestb", { MaskG
, MaskR
} },
10849 { "ktestd", { MaskG
, MaskR
} },
10852 /* VEX_W_0FAE_R_2_M_0 */
10853 { "vldmxcsr", { Md
} },
10856 /* VEX_W_0FAE_R_3_M_0 */
10857 { "vstmxcsr", { Md
} },
10860 /* VEX_W_0FC2_P_0 */
10861 { "vcmpps", { XM
, Vex
, EXx
, VCMP
} },
10864 /* VEX_W_0FC2_P_1 */
10865 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
} },
10868 /* VEX_W_0FC2_P_2 */
10869 { "vcmppd", { XM
, Vex
, EXx
, VCMP
} },
10872 /* VEX_W_0FC2_P_3 */
10873 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
} },
10876 /* VEX_W_0FC4_P_2 */
10877 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
} },
10880 /* VEX_W_0FC5_P_2 */
10881 { "vpextrw", { Gdq
, XS
, Ib
} },
10884 /* VEX_W_0FD0_P_2 */
10885 { "vaddsubpd", { XM
, Vex
, EXx
} },
10888 /* VEX_W_0FD0_P_3 */
10889 { "vaddsubps", { XM
, Vex
, EXx
} },
10892 /* VEX_W_0FD1_P_2 */
10893 { "vpsrlw", { XM
, Vex
, EXxmm
} },
10896 /* VEX_W_0FD2_P_2 */
10897 { "vpsrld", { XM
, Vex
, EXxmm
} },
10900 /* VEX_W_0FD3_P_2 */
10901 { "vpsrlq", { XM
, Vex
, EXxmm
} },
10904 /* VEX_W_0FD4_P_2 */
10905 { "vpaddq", { XM
, Vex
, EXx
} },
10908 /* VEX_W_0FD5_P_2 */
10909 { "vpmullw", { XM
, Vex
, EXx
} },
10912 /* VEX_W_0FD6_P_2 */
10913 { "vmovq", { EXqScalarS
, XMScalar
} },
10916 /* VEX_W_0FD7_P_2_M_1 */
10917 { "vpmovmskb", { Gdq
, XS
} },
10920 /* VEX_W_0FD8_P_2 */
10921 { "vpsubusb", { XM
, Vex
, EXx
} },
10924 /* VEX_W_0FD9_P_2 */
10925 { "vpsubusw", { XM
, Vex
, EXx
} },
10928 /* VEX_W_0FDA_P_2 */
10929 { "vpminub", { XM
, Vex
, EXx
} },
10932 /* VEX_W_0FDB_P_2 */
10933 { "vpand", { XM
, Vex
, EXx
} },
10936 /* VEX_W_0FDC_P_2 */
10937 { "vpaddusb", { XM
, Vex
, EXx
} },
10940 /* VEX_W_0FDD_P_2 */
10941 { "vpaddusw", { XM
, Vex
, EXx
} },
10944 /* VEX_W_0FDE_P_2 */
10945 { "vpmaxub", { XM
, Vex
, EXx
} },
10948 /* VEX_W_0FDF_P_2 */
10949 { "vpandn", { XM
, Vex
, EXx
} },
10952 /* VEX_W_0FE0_P_2 */
10953 { "vpavgb", { XM
, Vex
, EXx
} },
10956 /* VEX_W_0FE1_P_2 */
10957 { "vpsraw", { XM
, Vex
, EXxmm
} },
10960 /* VEX_W_0FE2_P_2 */
10961 { "vpsrad", { XM
, Vex
, EXxmm
} },
10964 /* VEX_W_0FE3_P_2 */
10965 { "vpavgw", { XM
, Vex
, EXx
} },
10968 /* VEX_W_0FE4_P_2 */
10969 { "vpmulhuw", { XM
, Vex
, EXx
} },
10972 /* VEX_W_0FE5_P_2 */
10973 { "vpmulhw", { XM
, Vex
, EXx
} },
10976 /* VEX_W_0FE6_P_1 */
10977 { "vcvtdq2pd", { XM
, EXxmmq
} },
10980 /* VEX_W_0FE6_P_2 */
10981 { "vcvttpd2dq%XY", { XMM
, EXx
} },
10984 /* VEX_W_0FE6_P_3 */
10985 { "vcvtpd2dq%XY", { XMM
, EXx
} },
10988 /* VEX_W_0FE7_P_2_M_0 */
10989 { "vmovntdq", { Mx
, XM
} },
10992 /* VEX_W_0FE8_P_2 */
10993 { "vpsubsb", { XM
, Vex
, EXx
} },
10996 /* VEX_W_0FE9_P_2 */
10997 { "vpsubsw", { XM
, Vex
, EXx
} },
11000 /* VEX_W_0FEA_P_2 */
11001 { "vpminsw", { XM
, Vex
, EXx
} },
11004 /* VEX_W_0FEB_P_2 */
11005 { "vpor", { XM
, Vex
, EXx
} },
11008 /* VEX_W_0FEC_P_2 */
11009 { "vpaddsb", { XM
, Vex
, EXx
} },
11012 /* VEX_W_0FED_P_2 */
11013 { "vpaddsw", { XM
, Vex
, EXx
} },
11016 /* VEX_W_0FEE_P_2 */
11017 { "vpmaxsw", { XM
, Vex
, EXx
} },
11020 /* VEX_W_0FEF_P_2 */
11021 { "vpxor", { XM
, Vex
, EXx
} },
11024 /* VEX_W_0FF0_P_3_M_0 */
11025 { "vlddqu", { XM
, M
} },
11028 /* VEX_W_0FF1_P_2 */
11029 { "vpsllw", { XM
, Vex
, EXxmm
} },
11032 /* VEX_W_0FF2_P_2 */
11033 { "vpslld", { XM
, Vex
, EXxmm
} },
11036 /* VEX_W_0FF3_P_2 */
11037 { "vpsllq", { XM
, Vex
, EXxmm
} },
11040 /* VEX_W_0FF4_P_2 */
11041 { "vpmuludq", { XM
, Vex
, EXx
} },
11044 /* VEX_W_0FF5_P_2 */
11045 { "vpmaddwd", { XM
, Vex
, EXx
} },
11048 /* VEX_W_0FF6_P_2 */
11049 { "vpsadbw", { XM
, Vex
, EXx
} },
11052 /* VEX_W_0FF7_P_2 */
11053 { "vmaskmovdqu", { XM
, XS
} },
11056 /* VEX_W_0FF8_P_2 */
11057 { "vpsubb", { XM
, Vex
, EXx
} },
11060 /* VEX_W_0FF9_P_2 */
11061 { "vpsubw", { XM
, Vex
, EXx
} },
11064 /* VEX_W_0FFA_P_2 */
11065 { "vpsubd", { XM
, Vex
, EXx
} },
11068 /* VEX_W_0FFB_P_2 */
11069 { "vpsubq", { XM
, Vex
, EXx
} },
11072 /* VEX_W_0FFC_P_2 */
11073 { "vpaddb", { XM
, Vex
, EXx
} },
11076 /* VEX_W_0FFD_P_2 */
11077 { "vpaddw", { XM
, Vex
, EXx
} },
11080 /* VEX_W_0FFE_P_2 */
11081 { "vpaddd", { XM
, Vex
, EXx
} },
11084 /* VEX_W_0F3800_P_2 */
11085 { "vpshufb", { XM
, Vex
, EXx
} },
11088 /* VEX_W_0F3801_P_2 */
11089 { "vphaddw", { XM
, Vex
, EXx
} },
11092 /* VEX_W_0F3802_P_2 */
11093 { "vphaddd", { XM
, Vex
, EXx
} },
11096 /* VEX_W_0F3803_P_2 */
11097 { "vphaddsw", { XM
, Vex
, EXx
} },
11100 /* VEX_W_0F3804_P_2 */
11101 { "vpmaddubsw", { XM
, Vex
, EXx
} },
11104 /* VEX_W_0F3805_P_2 */
11105 { "vphsubw", { XM
, Vex
, EXx
} },
11108 /* VEX_W_0F3806_P_2 */
11109 { "vphsubd", { XM
, Vex
, EXx
} },
11112 /* VEX_W_0F3807_P_2 */
11113 { "vphsubsw", { XM
, Vex
, EXx
} },
11116 /* VEX_W_0F3808_P_2 */
11117 { "vpsignb", { XM
, Vex
, EXx
} },
11120 /* VEX_W_0F3809_P_2 */
11121 { "vpsignw", { XM
, Vex
, EXx
} },
11124 /* VEX_W_0F380A_P_2 */
11125 { "vpsignd", { XM
, Vex
, EXx
} },
11128 /* VEX_W_0F380B_P_2 */
11129 { "vpmulhrsw", { XM
, Vex
, EXx
} },
11132 /* VEX_W_0F380C_P_2 */
11133 { "vpermilps", { XM
, Vex
, EXx
} },
11136 /* VEX_W_0F380D_P_2 */
11137 { "vpermilpd", { XM
, Vex
, EXx
} },
11140 /* VEX_W_0F380E_P_2 */
11141 { "vtestps", { XM
, EXx
} },
11144 /* VEX_W_0F380F_P_2 */
11145 { "vtestpd", { XM
, EXx
} },
11148 /* VEX_W_0F3816_P_2 */
11149 { "vpermps", { XM
, Vex
, EXx
} },
11152 /* VEX_W_0F3817_P_2 */
11153 { "vptest", { XM
, EXx
} },
11156 /* VEX_W_0F3818_P_2 */
11157 { "vbroadcastss", { XM
, EXxmm_md
} },
11160 /* VEX_W_0F3819_P_2 */
11161 { "vbroadcastsd", { XM
, EXxmm_mq
} },
11164 /* VEX_W_0F381A_P_2_M_0 */
11165 { "vbroadcastf128", { XM
, Mxmm
} },
11168 /* VEX_W_0F381C_P_2 */
11169 { "vpabsb", { XM
, EXx
} },
11172 /* VEX_W_0F381D_P_2 */
11173 { "vpabsw", { XM
, EXx
} },
11176 /* VEX_W_0F381E_P_2 */
11177 { "vpabsd", { XM
, EXx
} },
11180 /* VEX_W_0F3820_P_2 */
11181 { "vpmovsxbw", { XM
, EXxmmq
} },
11184 /* VEX_W_0F3821_P_2 */
11185 { "vpmovsxbd", { XM
, EXxmmqd
} },
11188 /* VEX_W_0F3822_P_2 */
11189 { "vpmovsxbq", { XM
, EXxmmdw
} },
11192 /* VEX_W_0F3823_P_2 */
11193 { "vpmovsxwd", { XM
, EXxmmq
} },
11196 /* VEX_W_0F3824_P_2 */
11197 { "vpmovsxwq", { XM
, EXxmmqd
} },
11200 /* VEX_W_0F3825_P_2 */
11201 { "vpmovsxdq", { XM
, EXxmmq
} },
11204 /* VEX_W_0F3828_P_2 */
11205 { "vpmuldq", { XM
, Vex
, EXx
} },
11208 /* VEX_W_0F3829_P_2 */
11209 { "vpcmpeqq", { XM
, Vex
, EXx
} },
11212 /* VEX_W_0F382A_P_2_M_0 */
11213 { "vmovntdqa", { XM
, Mx
} },
11216 /* VEX_W_0F382B_P_2 */
11217 { "vpackusdw", { XM
, Vex
, EXx
} },
11220 /* VEX_W_0F382C_P_2_M_0 */
11221 { "vmaskmovps", { XM
, Vex
, Mx
} },
11224 /* VEX_W_0F382D_P_2_M_0 */
11225 { "vmaskmovpd", { XM
, Vex
, Mx
} },
11228 /* VEX_W_0F382E_P_2_M_0 */
11229 { "vmaskmovps", { Mx
, Vex
, XM
} },
11232 /* VEX_W_0F382F_P_2_M_0 */
11233 { "vmaskmovpd", { Mx
, Vex
, XM
} },
11236 /* VEX_W_0F3830_P_2 */
11237 { "vpmovzxbw", { XM
, EXxmmq
} },
11240 /* VEX_W_0F3831_P_2 */
11241 { "vpmovzxbd", { XM
, EXxmmqd
} },
11244 /* VEX_W_0F3832_P_2 */
11245 { "vpmovzxbq", { XM
, EXxmmdw
} },
11248 /* VEX_W_0F3833_P_2 */
11249 { "vpmovzxwd", { XM
, EXxmmq
} },
11252 /* VEX_W_0F3834_P_2 */
11253 { "vpmovzxwq", { XM
, EXxmmqd
} },
11256 /* VEX_W_0F3835_P_2 */
11257 { "vpmovzxdq", { XM
, EXxmmq
} },
11260 /* VEX_W_0F3836_P_2 */
11261 { "vpermd", { XM
, Vex
, EXx
} },
11264 /* VEX_W_0F3837_P_2 */
11265 { "vpcmpgtq", { XM
, Vex
, EXx
} },
11268 /* VEX_W_0F3838_P_2 */
11269 { "vpminsb", { XM
, Vex
, EXx
} },
11272 /* VEX_W_0F3839_P_2 */
11273 { "vpminsd", { XM
, Vex
, EXx
} },
11276 /* VEX_W_0F383A_P_2 */
11277 { "vpminuw", { XM
, Vex
, EXx
} },
11280 /* VEX_W_0F383B_P_2 */
11281 { "vpminud", { XM
, Vex
, EXx
} },
11284 /* VEX_W_0F383C_P_2 */
11285 { "vpmaxsb", { XM
, Vex
, EXx
} },
11288 /* VEX_W_0F383D_P_2 */
11289 { "vpmaxsd", { XM
, Vex
, EXx
} },
11292 /* VEX_W_0F383E_P_2 */
11293 { "vpmaxuw", { XM
, Vex
, EXx
} },
11296 /* VEX_W_0F383F_P_2 */
11297 { "vpmaxud", { XM
, Vex
, EXx
} },
11300 /* VEX_W_0F3840_P_2 */
11301 { "vpmulld", { XM
, Vex
, EXx
} },
11304 /* VEX_W_0F3841_P_2 */
11305 { "vphminposuw", { XM
, EXx
} },
11308 /* VEX_W_0F3846_P_2 */
11309 { "vpsravd", { XM
, Vex
, EXx
} },
11312 /* VEX_W_0F3858_P_2 */
11313 { "vpbroadcastd", { XM
, EXxmm_md
} },
11316 /* VEX_W_0F3859_P_2 */
11317 { "vpbroadcastq", { XM
, EXxmm_mq
} },
11320 /* VEX_W_0F385A_P_2_M_0 */
11321 { "vbroadcasti128", { XM
, Mxmm
} },
11324 /* VEX_W_0F3878_P_2 */
11325 { "vpbroadcastb", { XM
, EXxmm_mb
} },
11328 /* VEX_W_0F3879_P_2 */
11329 { "vpbroadcastw", { XM
, EXxmm_mw
} },
11332 /* VEX_W_0F38DB_P_2 */
11333 { "vaesimc", { XM
, EXx
} },
11336 /* VEX_W_0F38DC_P_2 */
11337 { "vaesenc", { XM
, Vex128
, EXx
} },
11340 /* VEX_W_0F38DD_P_2 */
11341 { "vaesenclast", { XM
, Vex128
, EXx
} },
11344 /* VEX_W_0F38DE_P_2 */
11345 { "vaesdec", { XM
, Vex128
, EXx
} },
11348 /* VEX_W_0F38DF_P_2 */
11349 { "vaesdeclast", { XM
, Vex128
, EXx
} },
11352 /* VEX_W_0F3A00_P_2 */
11354 { "vpermq", { XM
, EXx
, Ib
} },
11357 /* VEX_W_0F3A01_P_2 */
11359 { "vpermpd", { XM
, EXx
, Ib
} },
11362 /* VEX_W_0F3A02_P_2 */
11363 { "vpblendd", { XM
, Vex
, EXx
, Ib
} },
11366 /* VEX_W_0F3A04_P_2 */
11367 { "vpermilps", { XM
, EXx
, Ib
} },
11370 /* VEX_W_0F3A05_P_2 */
11371 { "vpermilpd", { XM
, EXx
, Ib
} },
11374 /* VEX_W_0F3A06_P_2 */
11375 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
} },
11378 /* VEX_W_0F3A08_P_2 */
11379 { "vroundps", { XM
, EXx
, Ib
} },
11382 /* VEX_W_0F3A09_P_2 */
11383 { "vroundpd", { XM
, EXx
, Ib
} },
11386 /* VEX_W_0F3A0A_P_2 */
11387 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
} },
11390 /* VEX_W_0F3A0B_P_2 */
11391 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
} },
11394 /* VEX_W_0F3A0C_P_2 */
11395 { "vblendps", { XM
, Vex
, EXx
, Ib
} },
11398 /* VEX_W_0F3A0D_P_2 */
11399 { "vblendpd", { XM
, Vex
, EXx
, Ib
} },
11402 /* VEX_W_0F3A0E_P_2 */
11403 { "vpblendw", { XM
, Vex
, EXx
, Ib
} },
11406 /* VEX_W_0F3A0F_P_2 */
11407 { "vpalignr", { XM
, Vex
, EXx
, Ib
} },
11410 /* VEX_W_0F3A14_P_2 */
11411 { "vpextrb", { Edqb
, XM
, Ib
} },
11414 /* VEX_W_0F3A15_P_2 */
11415 { "vpextrw", { Edqw
, XM
, Ib
} },
11418 /* VEX_W_0F3A18_P_2 */
11419 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
} },
11422 /* VEX_W_0F3A19_P_2 */
11423 { "vextractf128", { EXxmm
, XM
, Ib
} },
11426 /* VEX_W_0F3A20_P_2 */
11427 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
} },
11430 /* VEX_W_0F3A21_P_2 */
11431 { "vinsertps", { XM
, Vex128
, EXd
, Ib
} },
11434 /* VEX_W_0F3A30_P_2_LEN_0 */
11435 { "kshiftrb", { MaskG
, MaskR
, Ib
} },
11436 { "kshiftrw", { MaskG
, MaskR
, Ib
} },
11439 /* VEX_W_0F3A31_P_2_LEN_0 */
11440 { "kshiftrd", { MaskG
, MaskR
, Ib
} },
11441 { "kshiftrq", { MaskG
, MaskR
, Ib
} },
11444 /* VEX_W_0F3A32_P_2_LEN_0 */
11445 { "kshiftlb", { MaskG
, MaskR
, Ib
} },
11446 { "kshiftlw", { MaskG
, MaskR
, Ib
} },
11449 /* VEX_W_0F3A33_P_2_LEN_0 */
11450 { "kshiftld", { MaskG
, MaskR
, Ib
} },
11451 { "kshiftlq", { MaskG
, MaskR
, Ib
} },
11454 /* VEX_W_0F3A38_P_2 */
11455 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
} },
11458 /* VEX_W_0F3A39_P_2 */
11459 { "vextracti128", { EXxmm
, XM
, Ib
} },
11462 /* VEX_W_0F3A40_P_2 */
11463 { "vdpps", { XM
, Vex
, EXx
, Ib
} },
11466 /* VEX_W_0F3A41_P_2 */
11467 { "vdppd", { XM
, Vex128
, EXx
, Ib
} },
11470 /* VEX_W_0F3A42_P_2 */
11471 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
} },
11474 /* VEX_W_0F3A44_P_2 */
11475 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
} },
11478 /* VEX_W_0F3A46_P_2 */
11479 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
} },
11482 /* VEX_W_0F3A48_P_2 */
11483 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11484 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11487 /* VEX_W_0F3A49_P_2 */
11488 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11489 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11492 /* VEX_W_0F3A4A_P_2 */
11493 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
} },
11496 /* VEX_W_0F3A4B_P_2 */
11497 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
} },
11500 /* VEX_W_0F3A4C_P_2 */
11501 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
} },
11504 /* VEX_W_0F3A60_P_2 */
11505 { "vpcmpestrm", { XM
, EXx
, Ib
} },
11508 /* VEX_W_0F3A61_P_2 */
11509 { "vpcmpestri", { XM
, EXx
, Ib
} },
11512 /* VEX_W_0F3A62_P_2 */
11513 { "vpcmpistrm", { XM
, EXx
, Ib
} },
11516 /* VEX_W_0F3A63_P_2 */
11517 { "vpcmpistri", { XM
, EXx
, Ib
} },
11520 /* VEX_W_0F3ADF_P_2 */
11521 { "vaeskeygenassist", { XM
, EXx
, Ib
} },
11523 #define NEED_VEX_W_TABLE
11524 #include "i386-dis-evex.h"
11525 #undef NEED_VEX_W_TABLE
11528 static const struct dis386 mod_table
[][2] = {
11531 { "leaS", { Gv
, M
} },
11536 { RM_TABLE (RM_C6_REG_7
) },
11541 { RM_TABLE (RM_C7_REG_7
) },
11545 { "Jcall{T|}", { indirEp
} },
11549 { "Jjmp{T|}", { indirEp
} },
11552 /* MOD_0F01_REG_0 */
11553 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11554 { RM_TABLE (RM_0F01_REG_0
) },
11557 /* MOD_0F01_REG_1 */
11558 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11559 { RM_TABLE (RM_0F01_REG_1
) },
11562 /* MOD_0F01_REG_2 */
11563 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11564 { RM_TABLE (RM_0F01_REG_2
) },
11567 /* MOD_0F01_REG_3 */
11568 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11569 { RM_TABLE (RM_0F01_REG_3
) },
11572 /* MOD_0F01_REG_7 */
11573 { "invlpg", { Mb
} },
11574 { RM_TABLE (RM_0F01_REG_7
) },
11577 /* MOD_0F12_PREFIX_0 */
11578 { "movlps", { XM
, EXq
} },
11579 { "movhlps", { XM
, EXq
} },
11583 { "movlpX", { EXq
, XM
} },
11586 /* MOD_0F16_PREFIX_0 */
11587 { "movhps", { XM
, EXq
} },
11588 { "movlhps", { XM
, EXq
} },
11592 { "movhpX", { EXq
, XM
} },
11595 /* MOD_0F18_REG_0 */
11596 { "prefetchnta", { Mb
} },
11599 /* MOD_0F18_REG_1 */
11600 { "prefetcht0", { Mb
} },
11603 /* MOD_0F18_REG_2 */
11604 { "prefetcht1", { Mb
} },
11607 /* MOD_0F18_REG_3 */
11608 { "prefetcht2", { Mb
} },
11611 /* MOD_0F18_REG_4 */
11612 { "nop/reserved", { Mb
} },
11615 /* MOD_0F18_REG_5 */
11616 { "nop/reserved", { Mb
} },
11619 /* MOD_0F18_REG_6 */
11620 { "nop/reserved", { Mb
} },
11623 /* MOD_0F18_REG_7 */
11624 { "nop/reserved", { Mb
} },
11627 /* MOD_0F1A_PREFIX_0 */
11628 { "bndldx", { Gbnd
, Ev_bnd
} },
11629 { "nopQ", { Ev
} },
11632 /* MOD_0F1B_PREFIX_0 */
11633 { "bndstx", { Ev_bnd
, Gbnd
} },
11634 { "nopQ", { Ev
} },
11637 /* MOD_0F1B_PREFIX_1 */
11638 { "bndmk", { Gbnd
, Ev_bnd
} },
11639 { "nopQ", { Ev
} },
11644 { "movZ", { Rm
, Cm
} },
11649 { "movZ", { Rm
, Dm
} },
11654 { "movZ", { Cm
, Rm
} },
11659 { "movZ", { Dm
, Rm
} },
11664 { "movL", { Rd
, Td
} },
11669 { "movL", { Td
, Rd
} },
11672 /* MOD_0F2B_PREFIX_0 */
11673 {"movntps", { Mx
, XM
} },
11676 /* MOD_0F2B_PREFIX_1 */
11677 {"movntss", { Md
, XM
} },
11680 /* MOD_0F2B_PREFIX_2 */
11681 {"movntpd", { Mx
, XM
} },
11684 /* MOD_0F2B_PREFIX_3 */
11685 {"movntsd", { Mq
, XM
} },
11690 { "movmskpX", { Gdq
, XS
} },
11693 /* MOD_0F71_REG_2 */
11695 { "psrlw", { MS
, Ib
} },
11698 /* MOD_0F71_REG_4 */
11700 { "psraw", { MS
, Ib
} },
11703 /* MOD_0F71_REG_6 */
11705 { "psllw", { MS
, Ib
} },
11708 /* MOD_0F72_REG_2 */
11710 { "psrld", { MS
, Ib
} },
11713 /* MOD_0F72_REG_4 */
11715 { "psrad", { MS
, Ib
} },
11718 /* MOD_0F72_REG_6 */
11720 { "pslld", { MS
, Ib
} },
11723 /* MOD_0F73_REG_2 */
11725 { "psrlq", { MS
, Ib
} },
11728 /* MOD_0F73_REG_3 */
11730 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11733 /* MOD_0F73_REG_6 */
11735 { "psllq", { MS
, Ib
} },
11738 /* MOD_0F73_REG_7 */
11740 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11743 /* MOD_0FAE_REG_0 */
11744 { "fxsave", { FXSAVE
} },
11745 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11748 /* MOD_0FAE_REG_1 */
11749 { "fxrstor", { FXSAVE
} },
11750 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11753 /* MOD_0FAE_REG_2 */
11754 { "ldmxcsr", { Md
} },
11755 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11758 /* MOD_0FAE_REG_3 */
11759 { "stmxcsr", { Md
} },
11760 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11763 /* MOD_0FAE_REG_4 */
11764 { "xsave", { FXSAVE
} },
11767 /* MOD_0FAE_REG_5 */
11768 { "xrstor", { FXSAVE
} },
11769 { RM_TABLE (RM_0FAE_REG_5
) },
11772 /* MOD_0FAE_REG_6 */
11773 { "xsaveopt", { FXSAVE
} },
11774 { RM_TABLE (RM_0FAE_REG_6
) },
11777 /* MOD_0FAE_REG_7 */
11778 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11779 { RM_TABLE (RM_0FAE_REG_7
) },
11783 { "lssS", { Gv
, Mp
} },
11787 { "lfsS", { Gv
, Mp
} },
11791 { "lgsS", { Gv
, Mp
} },
11794 /* MOD_0FC7_REG_3 */
11795 { "xrstors", { FXSAVE
} },
11798 /* MOD_0FC7_REG_4 */
11799 { "xsavec", { FXSAVE
} },
11802 /* MOD_0FC7_REG_5 */
11803 { "xsaves", { FXSAVE
} },
11806 /* MOD_0FC7_REG_6 */
11807 { PREFIX_TABLE (PREFIX_0FC7_REG_6
) },
11808 { "rdrand", { Ev
} },
11811 /* MOD_0FC7_REG_7 */
11812 { "vmptrst", { Mq
} },
11813 { "rdseed", { Ev
} },
11818 { "pmovmskb", { Gdq
, MS
} },
11821 /* MOD_0FE7_PREFIX_2 */
11822 { "movntdq", { Mx
, XM
} },
11825 /* MOD_0FF0_PREFIX_3 */
11826 { "lddqu", { XM
, M
} },
11829 /* MOD_0F382A_PREFIX_2 */
11830 { "movntdqa", { XM
, Mx
} },
11834 { "bound{S|}", { Gv
, Ma
} },
11835 { EVEX_TABLE (EVEX_0F
) },
11839 { "lesS", { Gv
, Mp
} },
11840 { VEX_C4_TABLE (VEX_0F
) },
11844 { "ldsS", { Gv
, Mp
} },
11845 { VEX_C5_TABLE (VEX_0F
) },
11848 /* MOD_VEX_0F12_PREFIX_0 */
11849 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11850 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11854 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11857 /* MOD_VEX_0F16_PREFIX_0 */
11858 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11859 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11863 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11867 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11872 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
11875 /* MOD_VEX_0F71_REG_2 */
11877 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11880 /* MOD_VEX_0F71_REG_4 */
11882 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11885 /* MOD_VEX_0F71_REG_6 */
11887 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
11890 /* MOD_VEX_0F72_REG_2 */
11892 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
11895 /* MOD_VEX_0F72_REG_4 */
11897 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
11900 /* MOD_VEX_0F72_REG_6 */
11902 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
11905 /* MOD_VEX_0F73_REG_2 */
11907 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
11910 /* MOD_VEX_0F73_REG_3 */
11912 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
11915 /* MOD_VEX_0F73_REG_6 */
11917 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
11920 /* MOD_VEX_0F73_REG_7 */
11922 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
11925 /* MOD_VEX_0FAE_REG_2 */
11926 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
11929 /* MOD_VEX_0FAE_REG_3 */
11930 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
11933 /* MOD_VEX_0FD7_PREFIX_2 */
11935 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
11938 /* MOD_VEX_0FE7_PREFIX_2 */
11939 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
11942 /* MOD_VEX_0FF0_PREFIX_3 */
11943 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
11946 /* MOD_VEX_0F381A_PREFIX_2 */
11947 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
11950 /* MOD_VEX_0F382A_PREFIX_2 */
11951 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
11954 /* MOD_VEX_0F382C_PREFIX_2 */
11955 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
11958 /* MOD_VEX_0F382D_PREFIX_2 */
11959 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
11962 /* MOD_VEX_0F382E_PREFIX_2 */
11963 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
11966 /* MOD_VEX_0F382F_PREFIX_2 */
11967 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
11970 /* MOD_VEX_0F385A_PREFIX_2 */
11971 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
11974 /* MOD_VEX_0F388C_PREFIX_2 */
11975 { "vpmaskmov%LW", { XM
, Vex
, Mx
} },
11978 /* MOD_VEX_0F388E_PREFIX_2 */
11979 { "vpmaskmov%LW", { Mx
, Vex
, XM
} },
11981 #define NEED_MOD_TABLE
11982 #include "i386-dis-evex.h"
11983 #undef NEED_MOD_TABLE
11986 static const struct dis386 rm_table
[][8] = {
11989 { "xabort", { Skip_MODRM
, Ib
} },
11993 { "xbeginT", { Skip_MODRM
, Jv
} },
11996 /* RM_0F01_REG_0 */
11998 { "vmcall", { Skip_MODRM
} },
11999 { "vmlaunch", { Skip_MODRM
} },
12000 { "vmresume", { Skip_MODRM
} },
12001 { "vmxoff", { Skip_MODRM
} },
12004 /* RM_0F01_REG_1 */
12005 { "monitor", { { OP_Monitor
, 0 } } },
12006 { "mwait", { { OP_Mwait
, 0 } } },
12007 { "clac", { Skip_MODRM
} },
12008 { "stac", { Skip_MODRM
} },
12012 { "encls", { Skip_MODRM
} },
12015 /* RM_0F01_REG_2 */
12016 { "xgetbv", { Skip_MODRM
} },
12017 { "xsetbv", { Skip_MODRM
} },
12020 { "vmfunc", { Skip_MODRM
} },
12021 { "xend", { Skip_MODRM
} },
12022 { "xtest", { Skip_MODRM
} },
12023 { "enclu", { Skip_MODRM
} },
12026 /* RM_0F01_REG_3 */
12027 { "vmrun", { Skip_MODRM
} },
12028 { "vmmcall", { Skip_MODRM
} },
12029 { "vmload", { Skip_MODRM
} },
12030 { "vmsave", { Skip_MODRM
} },
12031 { "stgi", { Skip_MODRM
} },
12032 { "clgi", { Skip_MODRM
} },
12033 { "skinit", { Skip_MODRM
} },
12034 { "invlpga", { Skip_MODRM
} },
12037 /* RM_0F01_REG_7 */
12038 { "swapgs", { Skip_MODRM
} },
12039 { "rdtscp", { Skip_MODRM
} },
12042 /* RM_0FAE_REG_5 */
12043 { "lfence", { Skip_MODRM
} },
12046 /* RM_0FAE_REG_6 */
12047 { "mfence", { Skip_MODRM
} },
12050 /* RM_0FAE_REG_7 */
12051 { "sfence", { Skip_MODRM
} },
12055 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12057 /* We use the high bit to indicate different name for the same
12059 #define REP_PREFIX (0xf3 | 0x100)
12060 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12061 #define XRELEASE_PREFIX (0xf3 | 0x400)
12062 #define BND_PREFIX (0xf2 | 0x400)
12067 int newrex
, i
, length
;
12073 last_lock_prefix
= -1;
12074 last_repz_prefix
= -1;
12075 last_repnz_prefix
= -1;
12076 last_data_prefix
= -1;
12077 last_addr_prefix
= -1;
12078 last_rex_prefix
= -1;
12079 last_seg_prefix
= -1;
12081 active_seg_prefix
= 0;
12082 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12083 all_prefixes
[i
] = 0;
12086 /* The maximum instruction length is 15bytes. */
12087 while (length
< MAX_CODE_LENGTH
- 1)
12089 FETCH_DATA (the_info
, codep
+ 1);
12093 /* REX prefixes family. */
12110 if (address_mode
== mode_64bit
)
12114 last_rex_prefix
= i
;
12117 prefixes
|= PREFIX_REPZ
;
12118 last_repz_prefix
= i
;
12121 prefixes
|= PREFIX_REPNZ
;
12122 last_repnz_prefix
= i
;
12125 prefixes
|= PREFIX_LOCK
;
12126 last_lock_prefix
= i
;
12129 prefixes
|= PREFIX_CS
;
12130 last_seg_prefix
= i
;
12131 active_seg_prefix
= PREFIX_CS
;
12134 prefixes
|= PREFIX_SS
;
12135 last_seg_prefix
= i
;
12136 active_seg_prefix
= PREFIX_SS
;
12139 prefixes
|= PREFIX_DS
;
12140 last_seg_prefix
= i
;
12141 active_seg_prefix
= PREFIX_DS
;
12144 prefixes
|= PREFIX_ES
;
12145 last_seg_prefix
= i
;
12146 active_seg_prefix
= PREFIX_ES
;
12149 prefixes
|= PREFIX_FS
;
12150 last_seg_prefix
= i
;
12151 active_seg_prefix
= PREFIX_FS
;
12154 prefixes
|= PREFIX_GS
;
12155 last_seg_prefix
= i
;
12156 active_seg_prefix
= PREFIX_GS
;
12159 prefixes
|= PREFIX_DATA
;
12160 last_data_prefix
= i
;
12163 prefixes
|= PREFIX_ADDR
;
12164 last_addr_prefix
= i
;
12167 /* fwait is really an instruction. If there are prefixes
12168 before the fwait, they belong to the fwait, *not* to the
12169 following instruction. */
12171 if (prefixes
|| rex
)
12173 prefixes
|= PREFIX_FWAIT
;
12175 /* This ensures that the previous REX prefixes are noticed
12176 as unused prefixes, as in the return case below. */
12180 prefixes
= PREFIX_FWAIT
;
12185 /* Rex is ignored when followed by another prefix. */
12191 if (*codep
!= FWAIT_OPCODE
)
12192 all_prefixes
[i
++] = *codep
;
12200 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12203 static const char *
12204 prefix_name (int pref
, int sizeflag
)
12206 static const char *rexes
[16] =
12209 "rex.B", /* 0x41 */
12210 "rex.X", /* 0x42 */
12211 "rex.XB", /* 0x43 */
12212 "rex.R", /* 0x44 */
12213 "rex.RB", /* 0x45 */
12214 "rex.RX", /* 0x46 */
12215 "rex.RXB", /* 0x47 */
12216 "rex.W", /* 0x48 */
12217 "rex.WB", /* 0x49 */
12218 "rex.WX", /* 0x4a */
12219 "rex.WXB", /* 0x4b */
12220 "rex.WR", /* 0x4c */
12221 "rex.WRB", /* 0x4d */
12222 "rex.WRX", /* 0x4e */
12223 "rex.WRXB", /* 0x4f */
12228 /* REX prefixes family. */
12245 return rexes
[pref
- 0x40];
12265 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12267 if (address_mode
== mode_64bit
)
12268 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12270 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12275 case XACQUIRE_PREFIX
:
12277 case XRELEASE_PREFIX
:
12286 static char op_out
[MAX_OPERANDS
][100];
12287 static int op_ad
, op_index
[MAX_OPERANDS
];
12288 static int two_source_ops
;
12289 static bfd_vma op_address
[MAX_OPERANDS
];
12290 static bfd_vma op_riprel
[MAX_OPERANDS
];
12291 static bfd_vma start_pc
;
12294 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12295 * (see topic "Redundant prefixes" in the "Differences from 8086"
12296 * section of the "Virtual 8086 Mode" chapter.)
12297 * 'pc' should be the address of this instruction, it will
12298 * be used to print the target address if this is a relative jump or call
12299 * The function returns the length of this instruction in bytes.
12302 static char intel_syntax
;
12303 static char intel_mnemonic
= !SYSV386_COMPAT
;
12304 static char open_char
;
12305 static char close_char
;
12306 static char separator_char
;
12307 static char scale_char
;
12309 /* Here for backwards compatibility. When gdb stops using
12310 print_insn_i386_att and print_insn_i386_intel these functions can
12311 disappear, and print_insn_i386 be merged into print_insn. */
12313 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12317 return print_insn (pc
, info
);
12321 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12325 return print_insn (pc
, info
);
12329 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12333 return print_insn (pc
, info
);
12337 print_i386_disassembler_options (FILE *stream
)
12339 fprintf (stream
, _("\n\
12340 The following i386/x86-64 specific disassembler options are supported for use\n\
12341 with the -M switch (multiple options should be separated by commas):\n"));
12343 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12344 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12345 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12346 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12347 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12348 fprintf (stream
, _(" att-mnemonic\n"
12349 " Display instruction in AT&T mnemonic\n"));
12350 fprintf (stream
, _(" intel-mnemonic\n"
12351 " Display instruction in Intel mnemonic\n"));
12352 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12353 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12354 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12355 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12356 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12357 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12361 static const struct dis386 bad_opcode
= { "(bad)", { XX
} };
12363 /* Get a pointer to struct dis386 with a valid name. */
12365 static const struct dis386
*
12366 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12368 int vindex
, vex_table_index
;
12370 if (dp
->name
!= NULL
)
12373 switch (dp
->op
[0].bytemode
)
12375 case USE_REG_TABLE
:
12376 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12379 case USE_MOD_TABLE
:
12380 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12381 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12385 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12388 case USE_PREFIX_TABLE
:
12391 /* The prefix in VEX is implicit. */
12392 switch (vex
.prefix
)
12397 case REPE_PREFIX_OPCODE
:
12400 case DATA_PREFIX_OPCODE
:
12403 case REPNE_PREFIX_OPCODE
:
12413 int last_prefix
= -1;
12416 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12417 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12419 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12421 if (last_repz_prefix
> last_repnz_prefix
)
12424 prefix
= PREFIX_REPZ
;
12425 last_prefix
= last_repz_prefix
;
12430 prefix
= PREFIX_REPNZ
;
12431 last_prefix
= last_repnz_prefix
;
12434 /* Ignore the invalid index if it isn't mandatory. */
12435 if (!mandatory_prefix
12436 && (prefix_table
[dp
->op
[1].bytemode
][vindex
].name
12438 && (prefix_table
[dp
->op
[1].bytemode
][vindex
].op
[0].bytemode
12443 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12446 prefix
= PREFIX_DATA
;
12447 last_prefix
= last_data_prefix
;
12452 used_prefixes
|= prefix
;
12453 all_prefixes
[last_prefix
] = 0;
12456 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12459 case USE_X86_64_TABLE
:
12460 vindex
= address_mode
== mode_64bit
? 1 : 0;
12461 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12464 case USE_3BYTE_TABLE
:
12465 FETCH_DATA (info
, codep
+ 2);
12467 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12469 modrm
.mod
= (*codep
>> 6) & 3;
12470 modrm
.reg
= (*codep
>> 3) & 7;
12471 modrm
.rm
= *codep
& 7;
12474 case USE_VEX_LEN_TABLE
:
12478 switch (vex
.length
)
12491 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12494 case USE_XOP_8F_TABLE
:
12495 FETCH_DATA (info
, codep
+ 3);
12496 /* All bits in the REX prefix are ignored. */
12498 rex
= ~(*codep
>> 5) & 0x7;
12500 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12501 switch ((*codep
& 0x1f))
12507 vex_table_index
= XOP_08
;
12510 vex_table_index
= XOP_09
;
12513 vex_table_index
= XOP_0A
;
12517 vex
.w
= *codep
& 0x80;
12518 if (vex
.w
&& address_mode
== mode_64bit
)
12521 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12522 if (address_mode
!= mode_64bit
12523 && vex
.register_specifier
> 0x7)
12529 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12530 switch ((*codep
& 0x3))
12536 vex
.prefix
= DATA_PREFIX_OPCODE
;
12539 vex
.prefix
= REPE_PREFIX_OPCODE
;
12542 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12549 dp
= &xop_table
[vex_table_index
][vindex
];
12552 FETCH_DATA (info
, codep
+ 1);
12553 modrm
.mod
= (*codep
>> 6) & 3;
12554 modrm
.reg
= (*codep
>> 3) & 7;
12555 modrm
.rm
= *codep
& 7;
12558 case USE_VEX_C4_TABLE
:
12560 FETCH_DATA (info
, codep
+ 3);
12561 /* All bits in the REX prefix are ignored. */
12563 rex
= ~(*codep
>> 5) & 0x7;
12564 switch ((*codep
& 0x1f))
12570 vex_table_index
= VEX_0F
;
12573 vex_table_index
= VEX_0F38
;
12576 vex_table_index
= VEX_0F3A
;
12580 vex
.w
= *codep
& 0x80;
12581 if (vex
.w
&& address_mode
== mode_64bit
)
12584 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12585 if (address_mode
!= mode_64bit
12586 && vex
.register_specifier
> 0x7)
12592 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12593 switch ((*codep
& 0x3))
12599 vex
.prefix
= DATA_PREFIX_OPCODE
;
12602 vex
.prefix
= REPE_PREFIX_OPCODE
;
12605 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12612 dp
= &vex_table
[vex_table_index
][vindex
];
12614 /* There is no MODRM byte for VEX [82|77]. */
12615 if (vindex
!= 0x77 && vindex
!= 0x82)
12617 FETCH_DATA (info
, codep
+ 1);
12618 modrm
.mod
= (*codep
>> 6) & 3;
12619 modrm
.reg
= (*codep
>> 3) & 7;
12620 modrm
.rm
= *codep
& 7;
12624 case USE_VEX_C5_TABLE
:
12626 FETCH_DATA (info
, codep
+ 2);
12627 /* All bits in the REX prefix are ignored. */
12629 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12631 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12632 if (address_mode
!= mode_64bit
12633 && vex
.register_specifier
> 0x7)
12641 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12642 switch ((*codep
& 0x3))
12648 vex
.prefix
= DATA_PREFIX_OPCODE
;
12651 vex
.prefix
= REPE_PREFIX_OPCODE
;
12654 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12661 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12663 /* There is no MODRM byte for VEX [82|77]. */
12664 if (vindex
!= 0x77 && vindex
!= 0x82)
12666 FETCH_DATA (info
, codep
+ 1);
12667 modrm
.mod
= (*codep
>> 6) & 3;
12668 modrm
.reg
= (*codep
>> 3) & 7;
12669 modrm
.rm
= *codep
& 7;
12673 case USE_VEX_W_TABLE
:
12677 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12680 case USE_EVEX_TABLE
:
12681 two_source_ops
= 0;
12684 FETCH_DATA (info
, codep
+ 4);
12685 /* All bits in the REX prefix are ignored. */
12687 /* The first byte after 0x62. */
12688 rex
= ~(*codep
>> 5) & 0x7;
12689 vex
.r
= *codep
& 0x10;
12690 switch ((*codep
& 0xf))
12693 return &bad_opcode
;
12695 vex_table_index
= EVEX_0F
;
12698 vex_table_index
= EVEX_0F38
;
12701 vex_table_index
= EVEX_0F3A
;
12705 /* The second byte after 0x62. */
12707 vex
.w
= *codep
& 0x80;
12708 if (vex
.w
&& address_mode
== mode_64bit
)
12711 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12712 if (address_mode
!= mode_64bit
)
12714 /* In 16/32-bit mode silently ignore following bits. */
12718 vex
.register_specifier
&= 0x7;
12722 if (!(*codep
& 0x4))
12723 return &bad_opcode
;
12725 switch ((*codep
& 0x3))
12731 vex
.prefix
= DATA_PREFIX_OPCODE
;
12734 vex
.prefix
= REPE_PREFIX_OPCODE
;
12737 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12741 /* The third byte after 0x62. */
12744 /* Remember the static rounding bits. */
12745 vex
.ll
= (*codep
>> 5) & 3;
12746 vex
.b
= (*codep
& 0x10) != 0;
12748 vex
.v
= *codep
& 0x8;
12749 vex
.mask_register_specifier
= *codep
& 0x7;
12750 vex
.zeroing
= *codep
& 0x80;
12756 dp
= &evex_table
[vex_table_index
][vindex
];
12758 FETCH_DATA (info
, codep
+ 1);
12759 modrm
.mod
= (*codep
>> 6) & 3;
12760 modrm
.reg
= (*codep
>> 3) & 7;
12761 modrm
.rm
= *codep
& 7;
12763 /* Set vector length. */
12764 if (modrm
.mod
== 3 && vex
.b
)
12780 return &bad_opcode
;
12793 if (dp
->name
!= NULL
)
12796 return get_valid_dis386 (dp
, info
);
12800 get_sib (disassemble_info
*info
, int sizeflag
)
12802 /* If modrm.mod == 3, operand must be register. */
12804 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12808 FETCH_DATA (info
, codep
+ 2);
12809 sib
.index
= (codep
[1] >> 3) & 7;
12810 sib
.scale
= (codep
[1] >> 6) & 3;
12811 sib
.base
= codep
[1] & 7;
12816 print_insn (bfd_vma pc
, disassemble_info
*info
)
12818 const struct dis386
*dp
;
12820 char *op_txt
[MAX_OPERANDS
];
12822 int sizeflag
, orig_sizeflag
;
12824 struct dis_private priv
;
12827 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12828 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
12829 address_mode
= mode_32bit
;
12830 else if (info
->mach
== bfd_mach_i386_i8086
)
12832 address_mode
= mode_16bit
;
12833 priv
.orig_sizeflag
= 0;
12836 address_mode
= mode_64bit
;
12838 if (intel_syntax
== (char) -1)
12839 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
12841 for (p
= info
->disassembler_options
; p
!= NULL
; )
12843 if (CONST_STRNEQ (p
, "x86-64"))
12845 address_mode
= mode_64bit
;
12846 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12848 else if (CONST_STRNEQ (p
, "i386"))
12850 address_mode
= mode_32bit
;
12851 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12853 else if (CONST_STRNEQ (p
, "i8086"))
12855 address_mode
= mode_16bit
;
12856 priv
.orig_sizeflag
= 0;
12858 else if (CONST_STRNEQ (p
, "intel"))
12861 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
12862 intel_mnemonic
= 1;
12864 else if (CONST_STRNEQ (p
, "att"))
12867 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
12868 intel_mnemonic
= 0;
12870 else if (CONST_STRNEQ (p
, "addr"))
12872 if (address_mode
== mode_64bit
)
12874 if (p
[4] == '3' && p
[5] == '2')
12875 priv
.orig_sizeflag
&= ~AFLAG
;
12876 else if (p
[4] == '6' && p
[5] == '4')
12877 priv
.orig_sizeflag
|= AFLAG
;
12881 if (p
[4] == '1' && p
[5] == '6')
12882 priv
.orig_sizeflag
&= ~AFLAG
;
12883 else if (p
[4] == '3' && p
[5] == '2')
12884 priv
.orig_sizeflag
|= AFLAG
;
12887 else if (CONST_STRNEQ (p
, "data"))
12889 if (p
[4] == '1' && p
[5] == '6')
12890 priv
.orig_sizeflag
&= ~DFLAG
;
12891 else if (p
[4] == '3' && p
[5] == '2')
12892 priv
.orig_sizeflag
|= DFLAG
;
12894 else if (CONST_STRNEQ (p
, "suffix"))
12895 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
12897 p
= strchr (p
, ',');
12904 names64
= intel_names64
;
12905 names32
= intel_names32
;
12906 names16
= intel_names16
;
12907 names8
= intel_names8
;
12908 names8rex
= intel_names8rex
;
12909 names_seg
= intel_names_seg
;
12910 names_mm
= intel_names_mm
;
12911 names_bnd
= intel_names_bnd
;
12912 names_xmm
= intel_names_xmm
;
12913 names_ymm
= intel_names_ymm
;
12914 names_zmm
= intel_names_zmm
;
12915 index64
= intel_index64
;
12916 index32
= intel_index32
;
12917 names_mask
= intel_names_mask
;
12918 index16
= intel_index16
;
12921 separator_char
= '+';
12926 names64
= att_names64
;
12927 names32
= att_names32
;
12928 names16
= att_names16
;
12929 names8
= att_names8
;
12930 names8rex
= att_names8rex
;
12931 names_seg
= att_names_seg
;
12932 names_mm
= att_names_mm
;
12933 names_bnd
= att_names_bnd
;
12934 names_xmm
= att_names_xmm
;
12935 names_ymm
= att_names_ymm
;
12936 names_zmm
= att_names_zmm
;
12937 index64
= att_index64
;
12938 index32
= att_index32
;
12939 names_mask
= att_names_mask
;
12940 index16
= att_index16
;
12943 separator_char
= ',';
12947 /* The output looks better if we put 7 bytes on a line, since that
12948 puts most long word instructions on a single line. Use 8 bytes
12950 if ((info
->mach
& bfd_mach_l1om
) != 0)
12951 info
->bytes_per_line
= 8;
12953 info
->bytes_per_line
= 7;
12955 info
->private_data
= &priv
;
12956 priv
.max_fetched
= priv
.the_buffer
;
12957 priv
.insn_start
= pc
;
12960 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12968 start_codep
= priv
.the_buffer
;
12969 codep
= priv
.the_buffer
;
12971 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12975 /* Getting here means we tried for data but didn't get it. That
12976 means we have an incomplete instruction of some sort. Just
12977 print the first byte as a prefix or a .byte pseudo-op. */
12978 if (codep
> priv
.the_buffer
)
12980 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12982 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12985 /* Just print the first byte as a .byte instruction. */
12986 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12987 (unsigned int) priv
.the_buffer
[0]);
12997 sizeflag
= priv
.orig_sizeflag
;
12999 if (!ckprefix () || rex_used
)
13001 /* Too many prefixes or unused REX prefixes. */
13003 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13005 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13007 prefix_name (all_prefixes
[i
], sizeflag
));
13011 insn_codep
= codep
;
13013 FETCH_DATA (info
, codep
+ 1);
13014 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13016 if (((prefixes
& PREFIX_FWAIT
)
13017 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13019 /* Handle prefixes before fwait. */
13020 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13022 (*info
->fprintf_func
) (info
->stream
, "%s ",
13023 prefix_name (all_prefixes
[i
], sizeflag
));
13024 (*info
->fprintf_func
) (info
->stream
, "fwait");
13028 if (*codep
== 0x0f)
13030 unsigned char threebyte
;
13031 FETCH_DATA (info
, codep
+ 2);
13032 threebyte
= *++codep
;
13033 dp
= &dis386_twobyte
[threebyte
];
13034 need_modrm
= twobyte_has_modrm
[*codep
];
13035 mandatory_prefix
= twobyte_has_mandatory_prefix
[*codep
];
13040 dp
= &dis386
[*codep
];
13041 need_modrm
= onebyte_has_modrm
[*codep
];
13042 mandatory_prefix
= 0;
13046 /* Save sizeflag for printing the extra prefixes later before updating
13047 it for mnemonic and operand processing. The prefix names depend
13048 only on the address mode. */
13049 orig_sizeflag
= sizeflag
;
13050 if (prefixes
& PREFIX_ADDR
)
13052 if ((prefixes
& PREFIX_DATA
))
13058 FETCH_DATA (info
, codep
+ 1);
13059 modrm
.mod
= (*codep
>> 6) & 3;
13060 modrm
.reg
= (*codep
>> 3) & 7;
13061 modrm
.rm
= *codep
& 7;
13069 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13071 get_sib (info
, sizeflag
);
13072 dofloat (sizeflag
);
13076 dp
= get_valid_dis386 (dp
, info
);
13077 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13079 get_sib (info
, sizeflag
);
13080 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13083 op_ad
= MAX_OPERANDS
- 1 - i
;
13085 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13086 /* For EVEX instruction after the last operand masking
13087 should be printed. */
13088 if (i
== 0 && vex
.evex
)
13090 /* Don't print {%k0}. */
13091 if (vex
.mask_register_specifier
)
13094 oappend (names_mask
[vex
.mask_register_specifier
]);
13104 /* Check if the REX prefix is used. */
13105 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13106 all_prefixes
[last_rex_prefix
] = 0;
13108 /* Check if the SEG prefix is used. */
13109 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13110 | PREFIX_FS
| PREFIX_GS
)) != 0
13111 && (used_prefixes
& active_seg_prefix
) != 0)
13112 all_prefixes
[last_seg_prefix
] = 0;
13114 /* Check if the ADDR prefix is used. */
13115 if ((prefixes
& PREFIX_ADDR
) != 0
13116 && (used_prefixes
& PREFIX_ADDR
) != 0)
13117 all_prefixes
[last_addr_prefix
] = 0;
13119 /* Check if the DATA prefix is used. */
13120 if ((prefixes
& PREFIX_DATA
) != 0
13121 && (used_prefixes
& PREFIX_DATA
) != 0)
13122 all_prefixes
[last_data_prefix
] = 0;
13124 /* Print the extra prefixes. */
13126 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13127 if (all_prefixes
[i
])
13130 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13133 prefix_length
+= strlen (name
) + 1;
13134 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13137 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13138 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13139 used by putop and MMX/SSE operand and may be overriden by the
13140 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13142 if (mandatory_prefix
13143 && dp
!= &bad_opcode
13145 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13147 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13149 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13151 && (used_prefixes
& PREFIX_DATA
) == 0))))
13153 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13154 return end_codep
- priv
.the_buffer
;
13157 /* Check maximum code length. */
13158 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13160 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13161 return MAX_CODE_LENGTH
;
13164 obufp
= mnemonicendp
;
13165 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13168 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13170 /* The enter and bound instructions are printed with operands in the same
13171 order as the intel book; everything else is printed in reverse order. */
13172 if (intel_syntax
|| two_source_ops
)
13176 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13177 op_txt
[i
] = op_out
[i
];
13179 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13181 op_ad
= op_index
[i
];
13182 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13183 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13184 riprel
= op_riprel
[i
];
13185 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13186 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13191 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13192 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13196 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13200 (*info
->fprintf_func
) (info
->stream
, ",");
13201 if (op_index
[i
] != -1 && !op_riprel
[i
])
13202 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13204 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13208 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13209 if (op_index
[i
] != -1 && op_riprel
[i
])
13211 (*info
->fprintf_func
) (info
->stream
, " # ");
13212 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
13213 + op_address
[op_index
[i
]]), info
);
13216 return codep
- priv
.the_buffer
;
13219 static const char *float_mem
[] = {
13294 static const unsigned char float_mem_mode
[] = {
13369 #define ST { OP_ST, 0 }
13370 #define STi { OP_STi, 0 }
13372 #define FGRPd9_2 NULL, { { NULL, 0 } }
13373 #define FGRPd9_4 NULL, { { NULL, 1 } }
13374 #define FGRPd9_5 NULL, { { NULL, 2 } }
13375 #define FGRPd9_6 NULL, { { NULL, 3 } }
13376 #define FGRPd9_7 NULL, { { NULL, 4 } }
13377 #define FGRPda_5 NULL, { { NULL, 5 } }
13378 #define FGRPdb_4 NULL, { { NULL, 6 } }
13379 #define FGRPde_3 NULL, { { NULL, 7 } }
13380 #define FGRPdf_4 NULL, { { NULL, 8 } }
13382 static const struct dis386 float_reg
[][8] = {
13385 { "fadd", { ST
, STi
} },
13386 { "fmul", { ST
, STi
} },
13387 { "fcom", { STi
} },
13388 { "fcomp", { STi
} },
13389 { "fsub", { ST
, STi
} },
13390 { "fsubr", { ST
, STi
} },
13391 { "fdiv", { ST
, STi
} },
13392 { "fdivr", { ST
, STi
} },
13396 { "fld", { STi
} },
13397 { "fxch", { STi
} },
13407 { "fcmovb", { ST
, STi
} },
13408 { "fcmove", { ST
, STi
} },
13409 { "fcmovbe",{ ST
, STi
} },
13410 { "fcmovu", { ST
, STi
} },
13418 { "fcmovnb",{ ST
, STi
} },
13419 { "fcmovne",{ ST
, STi
} },
13420 { "fcmovnbe",{ ST
, STi
} },
13421 { "fcmovnu",{ ST
, STi
} },
13423 { "fucomi", { ST
, STi
} },
13424 { "fcomi", { ST
, STi
} },
13429 { "fadd", { STi
, ST
} },
13430 { "fmul", { STi
, ST
} },
13433 { "fsub!M", { STi
, ST
} },
13434 { "fsubM", { STi
, ST
} },
13435 { "fdiv!M", { STi
, ST
} },
13436 { "fdivM", { STi
, ST
} },
13440 { "ffree", { STi
} },
13442 { "fst", { STi
} },
13443 { "fstp", { STi
} },
13444 { "fucom", { STi
} },
13445 { "fucomp", { STi
} },
13451 { "faddp", { STi
, ST
} },
13452 { "fmulp", { STi
, ST
} },
13455 { "fsub!Mp", { STi
, ST
} },
13456 { "fsubMp", { STi
, ST
} },
13457 { "fdiv!Mp", { STi
, ST
} },
13458 { "fdivMp", { STi
, ST
} },
13462 { "ffreep", { STi
} },
13467 { "fucomip", { ST
, STi
} },
13468 { "fcomip", { ST
, STi
} },
13473 static char *fgrps
[][8] = {
13476 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13481 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13486 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13491 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13496 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13501 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13506 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13507 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13512 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13517 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13522 swap_operand (void)
13524 mnemonicendp
[0] = '.';
13525 mnemonicendp
[1] = 's';
13530 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13531 int sizeflag ATTRIBUTE_UNUSED
)
13533 /* Skip mod/rm byte. */
13539 dofloat (int sizeflag
)
13541 const struct dis386
*dp
;
13542 unsigned char floatop
;
13544 floatop
= codep
[-1];
13546 if (modrm
.mod
!= 3)
13548 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13550 putop (float_mem
[fp_indx
], sizeflag
);
13553 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13556 /* Skip mod/rm byte. */
13560 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13561 if (dp
->name
== NULL
)
13563 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13565 /* Instruction fnstsw is only one with strange arg. */
13566 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13567 strcpy (op_out
[0], names16
[0]);
13571 putop (dp
->name
, sizeflag
);
13576 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13581 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13585 /* Like oappend (below), but S is a string starting with '%'.
13586 In Intel syntax, the '%' is elided. */
13588 oappend_maybe_intel (const char *s
)
13590 oappend (s
+ intel_syntax
);
13594 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13596 oappend_maybe_intel ("%st");
13600 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13602 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13603 oappend_maybe_intel (scratchbuf
);
13606 /* Capital letters in template are macros. */
13608 putop (const char *in_template
, int sizeflag
)
13613 unsigned int l
= 0, len
= 1;
13616 #define SAVE_LAST(c) \
13617 if (l < len && l < sizeof (last)) \
13622 for (p
= in_template
; *p
; p
++)
13639 while (*++p
!= '|')
13640 if (*p
== '}' || *p
== '\0')
13643 /* Fall through. */
13648 while (*++p
!= '}')
13659 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13663 if (l
== 0 && len
== 1)
13668 if (sizeflag
& SUFFIX_ALWAYS
)
13681 if (address_mode
== mode_64bit
13682 && !(prefixes
& PREFIX_ADDR
))
13693 if (intel_syntax
&& !alt
)
13695 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13697 if (sizeflag
& DFLAG
)
13698 *obufp
++ = intel_syntax
? 'd' : 'l';
13700 *obufp
++ = intel_syntax
? 'w' : 's';
13701 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13705 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13708 if (modrm
.mod
== 3)
13714 if (sizeflag
& DFLAG
)
13715 *obufp
++ = intel_syntax
? 'd' : 'l';
13718 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13724 case 'E': /* For jcxz/jecxz */
13725 if (address_mode
== mode_64bit
)
13727 if (sizeflag
& AFLAG
)
13733 if (sizeflag
& AFLAG
)
13735 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13740 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
13742 if (sizeflag
& AFLAG
)
13743 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
13745 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
13746 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13750 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
13752 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13756 if (!(rex
& REX_W
))
13757 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13762 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
13763 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
13765 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
13768 if (prefixes
& PREFIX_DS
)
13789 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
13794 /* Fall through. */
13797 if (l
!= 0 || len
!= 1)
13805 if (sizeflag
& SUFFIX_ALWAYS
)
13809 if (intel_mnemonic
!= cond
)
13813 if ((prefixes
& PREFIX_FWAIT
) == 0)
13816 used_prefixes
|= PREFIX_FWAIT
;
13822 else if (intel_syntax
&& (sizeflag
& DFLAG
))
13826 if (!(rex
& REX_W
))
13827 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13831 && address_mode
== mode_64bit
13832 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13837 /* Fall through. */
13841 if ((rex
& REX_W
) == 0
13842 && (prefixes
& PREFIX_DATA
))
13844 if ((sizeflag
& DFLAG
) == 0)
13846 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13850 if ((prefixes
& PREFIX_DATA
)
13852 || (sizeflag
& SUFFIX_ALWAYS
))
13859 if (sizeflag
& DFLAG
)
13863 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13870 if (address_mode
== mode_64bit
13871 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13873 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13877 /* Fall through. */
13880 if (l
== 0 && len
== 1)
13883 if (intel_syntax
&& !alt
)
13886 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13892 if (sizeflag
& DFLAG
)
13893 *obufp
++ = intel_syntax
? 'd' : 'l';
13896 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13902 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13908 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13923 else if (sizeflag
& DFLAG
)
13932 if (intel_syntax
&& !p
[1]
13933 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13935 if (!(rex
& REX_W
))
13936 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13939 if (l
== 0 && len
== 1)
13943 if (address_mode
== mode_64bit
13944 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13946 if (sizeflag
& SUFFIX_ALWAYS
)
13968 /* Fall through. */
13971 if (l
== 0 && len
== 1)
13976 if (sizeflag
& SUFFIX_ALWAYS
)
13982 if (sizeflag
& DFLAG
)
13986 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14000 if (address_mode
== mode_64bit
14001 && !(prefixes
& PREFIX_ADDR
))
14012 if (l
!= 0 || len
!= 1)
14017 if (need_vex
&& vex
.prefix
)
14019 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14026 if (prefixes
& PREFIX_DATA
)
14030 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14034 if (l
== 0 && len
== 1)
14036 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14047 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14055 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14057 switch (vex
.length
)
14071 if (l
== 0 && len
== 1)
14073 /* operand size flag for cwtl, cbtw */
14082 else if (sizeflag
& DFLAG
)
14086 if (!(rex
& REX_W
))
14087 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14094 && last
[0] != 'L'))
14101 if (last
[0] == 'X')
14102 *obufp
++ = vex
.w
? 'd': 's';
14104 *obufp
++ = vex
.w
? 'q': 'd';
14111 mnemonicendp
= obufp
;
14116 oappend (const char *s
)
14118 obufp
= stpcpy (obufp
, s
);
14124 /* Only print the active segment register. */
14125 if (!active_seg_prefix
)
14128 used_prefixes
|= active_seg_prefix
;
14129 switch (active_seg_prefix
)
14132 oappend_maybe_intel ("%cs:");
14135 oappend_maybe_intel ("%ds:");
14138 oappend_maybe_intel ("%ss:");
14141 oappend_maybe_intel ("%es:");
14144 oappend_maybe_intel ("%fs:");
14147 oappend_maybe_intel ("%gs:");
14155 OP_indirE (int bytemode
, int sizeflag
)
14159 OP_E (bytemode
, sizeflag
);
14163 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14165 if (address_mode
== mode_64bit
)
14173 sprintf_vma (tmp
, disp
);
14174 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14175 strcpy (buf
+ 2, tmp
+ i
);
14179 bfd_signed_vma v
= disp
;
14186 /* Check for possible overflow on 0x8000000000000000. */
14189 strcpy (buf
, "9223372036854775808");
14203 tmp
[28 - i
] = (v
% 10) + '0';
14207 strcpy (buf
, tmp
+ 29 - i
);
14213 sprintf (buf
, "0x%x", (unsigned int) disp
);
14215 sprintf (buf
, "%d", (int) disp
);
14219 /* Put DISP in BUF as signed hex number. */
14222 print_displacement (char *buf
, bfd_vma disp
)
14224 bfd_signed_vma val
= disp
;
14233 /* Check for possible overflow. */
14236 switch (address_mode
)
14239 strcpy (buf
+ j
, "0x8000000000000000");
14242 strcpy (buf
+ j
, "0x80000000");
14245 strcpy (buf
+ j
, "0x8000");
14255 sprintf_vma (tmp
, (bfd_vma
) val
);
14256 for (i
= 0; tmp
[i
] == '0'; i
++)
14258 if (tmp
[i
] == '\0')
14260 strcpy (buf
+ j
, tmp
+ i
);
14264 intel_operand_size (int bytemode
, int sizeflag
)
14268 && (bytemode
== x_mode
14269 || bytemode
== evex_half_bcst_xmmq_mode
))
14272 oappend ("QWORD PTR ");
14274 oappend ("DWORD PTR ");
14283 oappend ("BYTE PTR ");
14288 case dqw_swap_mode
:
14289 oappend ("WORD PTR ");
14292 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14294 oappend ("QWORD PTR ");
14303 oappend ("QWORD PTR ");
14306 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14307 oappend ("DWORD PTR ");
14309 oappend ("WORD PTR ");
14310 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14314 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14316 oappend ("WORD PTR ");
14317 if (!(rex
& REX_W
))
14318 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14321 if (sizeflag
& DFLAG
)
14322 oappend ("QWORD PTR ");
14324 oappend ("DWORD PTR ");
14325 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14328 case d_scalar_mode
:
14329 case d_scalar_swap_mode
:
14332 oappend ("DWORD PTR ");
14335 case q_scalar_mode
:
14336 case q_scalar_swap_mode
:
14338 oappend ("QWORD PTR ");
14341 if (address_mode
== mode_64bit
)
14342 oappend ("QWORD PTR ");
14344 oappend ("DWORD PTR ");
14347 if (sizeflag
& DFLAG
)
14348 oappend ("FWORD PTR ");
14350 oappend ("DWORD PTR ");
14351 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14354 oappend ("TBYTE PTR ");
14358 case evex_x_gscat_mode
:
14359 case evex_x_nobcst_mode
:
14362 switch (vex
.length
)
14365 oappend ("XMMWORD PTR ");
14368 oappend ("YMMWORD PTR ");
14371 oappend ("ZMMWORD PTR ");
14378 oappend ("XMMWORD PTR ");
14381 oappend ("XMMWORD PTR ");
14384 oappend ("YMMWORD PTR ");
14387 case evex_half_bcst_xmmq_mode
:
14391 switch (vex
.length
)
14394 oappend ("QWORD PTR ");
14397 oappend ("XMMWORD PTR ");
14400 oappend ("YMMWORD PTR ");
14410 switch (vex
.length
)
14415 oappend ("BYTE PTR ");
14425 switch (vex
.length
)
14430 oappend ("WORD PTR ");
14440 switch (vex
.length
)
14445 oappend ("DWORD PTR ");
14455 switch (vex
.length
)
14460 oappend ("QWORD PTR ");
14470 switch (vex
.length
)
14473 oappend ("WORD PTR ");
14476 oappend ("DWORD PTR ");
14479 oappend ("QWORD PTR ");
14489 switch (vex
.length
)
14492 oappend ("DWORD PTR ");
14495 oappend ("QWORD PTR ");
14498 oappend ("XMMWORD PTR ");
14508 switch (vex
.length
)
14511 oappend ("QWORD PTR ");
14514 oappend ("YMMWORD PTR ");
14517 oappend ("ZMMWORD PTR ");
14527 switch (vex
.length
)
14531 oappend ("XMMWORD PTR ");
14538 oappend ("OWORD PTR ");
14541 case vex_w_dq_mode
:
14542 case vex_scalar_w_dq_mode
:
14547 oappend ("QWORD PTR ");
14549 oappend ("DWORD PTR ");
14551 case vex_vsib_d_w_dq_mode
:
14552 case vex_vsib_q_w_dq_mode
:
14559 oappend ("QWORD PTR ");
14561 oappend ("DWORD PTR ");
14565 switch (vex
.length
)
14568 oappend ("XMMWORD PTR ");
14571 oappend ("YMMWORD PTR ");
14574 oappend ("ZMMWORD PTR ");
14581 case vex_vsib_q_w_d_mode
:
14582 case vex_vsib_d_w_d_mode
:
14583 if (!need_vex
|| !vex
.evex
)
14586 switch (vex
.length
)
14589 oappend ("QWORD PTR ");
14592 oappend ("XMMWORD PTR ");
14595 oappend ("YMMWORD PTR ");
14603 if (!need_vex
|| vex
.length
!= 128)
14606 oappend ("DWORD PTR ");
14608 oappend ("BYTE PTR ");
14614 oappend ("QWORD PTR ");
14616 oappend ("WORD PTR ");
14625 OP_E_register (int bytemode
, int sizeflag
)
14627 int reg
= modrm
.rm
;
14628 const char **names
;
14634 if ((sizeflag
& SUFFIX_ALWAYS
)
14635 && (bytemode
== b_swap_mode
14636 || bytemode
== v_swap_mode
14637 || bytemode
== dqw_swap_mode
))
14663 names
= address_mode
== mode_64bit
? names64
: names32
;
14669 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14682 case dqw_swap_mode
:
14688 if ((sizeflag
& DFLAG
)
14689 || (bytemode
!= v_mode
14690 && bytemode
!= v_swap_mode
))
14694 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14699 names
= names_mask
;
14704 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14707 oappend (names
[reg
]);
14711 OP_E_memory (int bytemode
, int sizeflag
)
14714 int add
= (rex
& REX_B
) ? 8 : 0;
14720 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14722 && bytemode
!= x_mode
14723 && bytemode
!= xmmq_mode
14724 && bytemode
!= evex_half_bcst_xmmq_mode
)
14733 case dqw_swap_mode
:
14740 case vex_vsib_d_w_dq_mode
:
14741 case vex_vsib_d_w_d_mode
:
14742 case vex_vsib_q_w_dq_mode
:
14743 case vex_vsib_q_w_d_mode
:
14744 case evex_x_gscat_mode
:
14746 shift
= vex
.w
? 3 : 2;
14749 case evex_half_bcst_xmmq_mode
:
14753 shift
= vex
.w
? 3 : 2;
14756 /* Fall through if vex.b == 0. */
14760 case evex_x_nobcst_mode
:
14762 switch (vex
.length
)
14785 case q_scalar_mode
:
14787 case q_scalar_swap_mode
:
14793 case d_scalar_mode
:
14795 case d_scalar_swap_mode
:
14807 /* Make necessary corrections to shift for modes that need it.
14808 For these modes we currently have shift 4, 5 or 6 depending on
14809 vex.length (it corresponds to xmmword, ymmword or zmmword
14810 operand). We might want to make it 3, 4 or 5 (e.g. for
14811 xmmq_mode). In case of broadcast enabled the corrections
14812 aren't needed, as element size is always 32 or 64 bits. */
14814 && (bytemode
== xmmq_mode
14815 || bytemode
== evex_half_bcst_xmmq_mode
))
14817 else if (bytemode
== xmmqd_mode
)
14819 else if (bytemode
== xmmdw_mode
)
14821 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14829 intel_operand_size (bytemode
, sizeflag
);
14832 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14834 /* 32/64 bit address mode */
14843 int addr32flag
= !((sizeflag
& AFLAG
)
14844 || bytemode
== v_bnd_mode
14845 || bytemode
== bnd_mode
);
14846 const char **indexes64
= names64
;
14847 const char **indexes32
= names32
;
14857 vindex
= sib
.index
;
14863 case vex_vsib_d_w_dq_mode
:
14864 case vex_vsib_d_w_d_mode
:
14865 case vex_vsib_q_w_dq_mode
:
14866 case vex_vsib_q_w_d_mode
:
14876 switch (vex
.length
)
14879 indexes64
= indexes32
= names_xmm
;
14883 || bytemode
== vex_vsib_q_w_dq_mode
14884 || bytemode
== vex_vsib_q_w_d_mode
)
14885 indexes64
= indexes32
= names_ymm
;
14887 indexes64
= indexes32
= names_xmm
;
14891 || bytemode
== vex_vsib_q_w_dq_mode
14892 || bytemode
== vex_vsib_q_w_d_mode
)
14893 indexes64
= indexes32
= names_zmm
;
14895 indexes64
= indexes32
= names_ymm
;
14902 haveindex
= vindex
!= 4;
14909 rbase
= base
+ add
;
14917 if (address_mode
== mode_64bit
&& !havesib
)
14923 FETCH_DATA (the_info
, codep
+ 1);
14925 if ((disp
& 0x80) != 0)
14927 if (vex
.evex
&& shift
> 0)
14935 /* In 32bit mode, we need index register to tell [offset] from
14936 [eiz*1 + offset]. */
14937 needindex
= (havesib
14940 && address_mode
== mode_32bit
);
14941 havedisp
= (havebase
14943 || (havesib
&& (haveindex
|| scale
!= 0)));
14946 if (modrm
.mod
!= 0 || base
== 5)
14948 if (havedisp
|| riprel
)
14949 print_displacement (scratchbuf
, disp
);
14951 print_operand_value (scratchbuf
, 1, disp
);
14952 oappend (scratchbuf
);
14956 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
14960 if ((havebase
|| haveindex
|| riprel
)
14961 && (bytemode
!= v_bnd_mode
)
14962 && (bytemode
!= bnd_mode
))
14963 used_prefixes
|= PREFIX_ADDR
;
14965 if (havedisp
|| (intel_syntax
&& riprel
))
14967 *obufp
++ = open_char
;
14968 if (intel_syntax
&& riprel
)
14971 oappend (sizeflag
& AFLAG
? "rip" : "eip");
14975 oappend (address_mode
== mode_64bit
&& !addr32flag
14976 ? names64
[rbase
] : names32
[rbase
]);
14979 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14980 print index to tell base + index from base. */
14984 || (havebase
&& base
!= ESP_REG_NUM
))
14986 if (!intel_syntax
|| havebase
)
14988 *obufp
++ = separator_char
;
14992 oappend (address_mode
== mode_64bit
&& !addr32flag
14993 ? indexes64
[vindex
] : indexes32
[vindex
]);
14995 oappend (address_mode
== mode_64bit
&& !addr32flag
14996 ? index64
: index32
);
14998 *obufp
++ = scale_char
;
15000 sprintf (scratchbuf
, "%d", 1 << scale
);
15001 oappend (scratchbuf
);
15005 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15007 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15012 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15016 disp
= - (bfd_signed_vma
) disp
;
15020 print_displacement (scratchbuf
, disp
);
15022 print_operand_value (scratchbuf
, 1, disp
);
15023 oappend (scratchbuf
);
15026 *obufp
++ = close_char
;
15029 else if (intel_syntax
)
15031 if (modrm
.mod
!= 0 || base
== 5)
15033 if (!active_seg_prefix
)
15035 oappend (names_seg
[ds_reg
- es_reg
]);
15038 print_operand_value (scratchbuf
, 1, disp
);
15039 oappend (scratchbuf
);
15045 /* 16 bit address mode */
15046 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15053 if ((disp
& 0x8000) != 0)
15058 FETCH_DATA (the_info
, codep
+ 1);
15060 if ((disp
& 0x80) != 0)
15065 if ((disp
& 0x8000) != 0)
15071 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15073 print_displacement (scratchbuf
, disp
);
15074 oappend (scratchbuf
);
15077 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15079 *obufp
++ = open_char
;
15081 oappend (index16
[modrm
.rm
]);
15083 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15085 if ((bfd_signed_vma
) disp
>= 0)
15090 else if (modrm
.mod
!= 1)
15094 disp
= - (bfd_signed_vma
) disp
;
15097 print_displacement (scratchbuf
, disp
);
15098 oappend (scratchbuf
);
15101 *obufp
++ = close_char
;
15104 else if (intel_syntax
)
15106 if (!active_seg_prefix
)
15108 oappend (names_seg
[ds_reg
- es_reg
]);
15111 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15112 oappend (scratchbuf
);
15115 if (vex
.evex
&& vex
.b
15116 && (bytemode
== x_mode
15117 || bytemode
== xmmq_mode
15118 || bytemode
== evex_half_bcst_xmmq_mode
))
15121 || bytemode
== xmmq_mode
15122 || bytemode
== evex_half_bcst_xmmq_mode
)
15124 switch (vex
.length
)
15127 oappend ("{1to2}");
15130 oappend ("{1to4}");
15133 oappend ("{1to8}");
15141 switch (vex
.length
)
15144 oappend ("{1to4}");
15147 oappend ("{1to8}");
15150 oappend ("{1to16}");
15160 OP_E (int bytemode
, int sizeflag
)
15162 /* Skip mod/rm byte. */
15166 if (modrm
.mod
== 3)
15167 OP_E_register (bytemode
, sizeflag
);
15169 OP_E_memory (bytemode
, sizeflag
);
15173 OP_G (int bytemode
, int sizeflag
)
15184 oappend (names8rex
[modrm
.reg
+ add
]);
15186 oappend (names8
[modrm
.reg
+ add
]);
15189 oappend (names16
[modrm
.reg
+ add
]);
15194 oappend (names32
[modrm
.reg
+ add
]);
15197 oappend (names64
[modrm
.reg
+ add
]);
15200 oappend (names_bnd
[modrm
.reg
]);
15207 case dqw_swap_mode
:
15210 oappend (names64
[modrm
.reg
+ add
]);
15213 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15214 oappend (names32
[modrm
.reg
+ add
]);
15216 oappend (names16
[modrm
.reg
+ add
]);
15217 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15221 if (address_mode
== mode_64bit
)
15222 oappend (names64
[modrm
.reg
+ add
]);
15224 oappend (names32
[modrm
.reg
+ add
]);
15228 oappend (names_mask
[modrm
.reg
+ add
]);
15231 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15244 FETCH_DATA (the_info
, codep
+ 8);
15245 a
= *codep
++ & 0xff;
15246 a
|= (*codep
++ & 0xff) << 8;
15247 a
|= (*codep
++ & 0xff) << 16;
15248 a
|= (*codep
++ & 0xff) << 24;
15249 b
= *codep
++ & 0xff;
15250 b
|= (*codep
++ & 0xff) << 8;
15251 b
|= (*codep
++ & 0xff) << 16;
15252 b
|= (*codep
++ & 0xff) << 24;
15253 x
= a
+ ((bfd_vma
) b
<< 32);
15261 static bfd_signed_vma
15264 bfd_signed_vma x
= 0;
15266 FETCH_DATA (the_info
, codep
+ 4);
15267 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15268 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15269 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15270 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15274 static bfd_signed_vma
15277 bfd_signed_vma x
= 0;
15279 FETCH_DATA (the_info
, codep
+ 4);
15280 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15281 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15282 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15283 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15285 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15295 FETCH_DATA (the_info
, codep
+ 2);
15296 x
= *codep
++ & 0xff;
15297 x
|= (*codep
++ & 0xff) << 8;
15302 set_op (bfd_vma op
, int riprel
)
15304 op_index
[op_ad
] = op_ad
;
15305 if (address_mode
== mode_64bit
)
15307 op_address
[op_ad
] = op
;
15308 op_riprel
[op_ad
] = riprel
;
15312 /* Mask to get a 32-bit address. */
15313 op_address
[op_ad
] = op
& 0xffffffff;
15314 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15319 OP_REG (int code
, int sizeflag
)
15326 case es_reg
: case ss_reg
: case cs_reg
:
15327 case ds_reg
: case fs_reg
: case gs_reg
:
15328 oappend (names_seg
[code
- es_reg
]);
15340 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15341 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15342 s
= names16
[code
- ax_reg
+ add
];
15344 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15345 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15348 s
= names8rex
[code
- al_reg
+ add
];
15350 s
= names8
[code
- al_reg
];
15352 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15353 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15354 if (address_mode
== mode_64bit
15355 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15357 s
= names64
[code
- rAX_reg
+ add
];
15360 code
+= eAX_reg
- rAX_reg
;
15361 /* Fall through. */
15362 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15363 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15366 s
= names64
[code
- eAX_reg
+ add
];
15369 if (sizeflag
& DFLAG
)
15370 s
= names32
[code
- eAX_reg
+ add
];
15372 s
= names16
[code
- eAX_reg
+ add
];
15373 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15377 s
= INTERNAL_DISASSEMBLER_ERROR
;
15384 OP_IMREG (int code
, int sizeflag
)
15396 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15397 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15398 s
= names16
[code
- ax_reg
];
15400 case es_reg
: case ss_reg
: case cs_reg
:
15401 case ds_reg
: case fs_reg
: case gs_reg
:
15402 s
= names_seg
[code
- es_reg
];
15404 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15405 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15408 s
= names8rex
[code
- al_reg
];
15410 s
= names8
[code
- al_reg
];
15412 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15413 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15416 s
= names64
[code
- eAX_reg
];
15419 if (sizeflag
& DFLAG
)
15420 s
= names32
[code
- eAX_reg
];
15422 s
= names16
[code
- eAX_reg
];
15423 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15426 case z_mode_ax_reg
:
15427 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15431 if (!(rex
& REX_W
))
15432 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15435 s
= INTERNAL_DISASSEMBLER_ERROR
;
15442 OP_I (int bytemode
, int sizeflag
)
15445 bfd_signed_vma mask
= -1;
15450 FETCH_DATA (the_info
, codep
+ 1);
15455 if (address_mode
== mode_64bit
)
15460 /* Fall through. */
15467 if (sizeflag
& DFLAG
)
15477 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15489 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15494 scratchbuf
[0] = '$';
15495 print_operand_value (scratchbuf
+ 1, 1, op
);
15496 oappend_maybe_intel (scratchbuf
);
15497 scratchbuf
[0] = '\0';
15501 OP_I64 (int bytemode
, int sizeflag
)
15504 bfd_signed_vma mask
= -1;
15506 if (address_mode
!= mode_64bit
)
15508 OP_I (bytemode
, sizeflag
);
15515 FETCH_DATA (the_info
, codep
+ 1);
15525 if (sizeflag
& DFLAG
)
15535 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15543 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15548 scratchbuf
[0] = '$';
15549 print_operand_value (scratchbuf
+ 1, 1, op
);
15550 oappend_maybe_intel (scratchbuf
);
15551 scratchbuf
[0] = '\0';
15555 OP_sI (int bytemode
, int sizeflag
)
15563 FETCH_DATA (the_info
, codep
+ 1);
15565 if ((op
& 0x80) != 0)
15567 if (bytemode
== b_T_mode
)
15569 if (address_mode
!= mode_64bit
15570 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15572 /* The operand-size prefix is overridden by a REX prefix. */
15573 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15581 if (!(rex
& REX_W
))
15583 if (sizeflag
& DFLAG
)
15591 /* The operand-size prefix is overridden by a REX prefix. */
15592 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15598 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15602 scratchbuf
[0] = '$';
15603 print_operand_value (scratchbuf
+ 1, 1, op
);
15604 oappend_maybe_intel (scratchbuf
);
15608 OP_J (int bytemode
, int sizeflag
)
15612 bfd_vma segment
= 0;
15617 FETCH_DATA (the_info
, codep
+ 1);
15619 if ((disp
& 0x80) != 0)
15624 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15629 if ((disp
& 0x8000) != 0)
15631 /* In 16bit mode, address is wrapped around at 64k within
15632 the same segment. Otherwise, a data16 prefix on a jump
15633 instruction means that the pc is masked to 16 bits after
15634 the displacement is added! */
15636 if ((prefixes
& PREFIX_DATA
) == 0)
15637 segment
= ((start_pc
+ codep
- start_codep
)
15638 & ~((bfd_vma
) 0xffff));
15640 if (!(rex
& REX_W
))
15641 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15644 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15647 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
15649 print_operand_value (scratchbuf
, 1, disp
);
15650 oappend (scratchbuf
);
15654 OP_SEG (int bytemode
, int sizeflag
)
15656 if (bytemode
== w_mode
)
15657 oappend (names_seg
[modrm
.reg
]);
15659 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
15663 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
15667 if (sizeflag
& DFLAG
)
15677 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15679 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15681 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15682 oappend (scratchbuf
);
15686 OP_OFF (int bytemode
, int sizeflag
)
15690 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15691 intel_operand_size (bytemode
, sizeflag
);
15694 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15701 if (!active_seg_prefix
)
15703 oappend (names_seg
[ds_reg
- es_reg
]);
15707 print_operand_value (scratchbuf
, 1, off
);
15708 oappend (scratchbuf
);
15712 OP_OFF64 (int bytemode
, int sizeflag
)
15716 if (address_mode
!= mode_64bit
15717 || (prefixes
& PREFIX_ADDR
))
15719 OP_OFF (bytemode
, sizeflag
);
15723 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15724 intel_operand_size (bytemode
, sizeflag
);
15731 if (!active_seg_prefix
)
15733 oappend (names_seg
[ds_reg
- es_reg
]);
15737 print_operand_value (scratchbuf
, 1, off
);
15738 oappend (scratchbuf
);
15742 ptr_reg (int code
, int sizeflag
)
15746 *obufp
++ = open_char
;
15747 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15748 if (address_mode
== mode_64bit
)
15750 if (!(sizeflag
& AFLAG
))
15751 s
= names32
[code
- eAX_reg
];
15753 s
= names64
[code
- eAX_reg
];
15755 else if (sizeflag
& AFLAG
)
15756 s
= names32
[code
- eAX_reg
];
15758 s
= names16
[code
- eAX_reg
];
15760 *obufp
++ = close_char
;
15765 OP_ESreg (int code
, int sizeflag
)
15771 case 0x6d: /* insw/insl */
15772 intel_operand_size (z_mode
, sizeflag
);
15774 case 0xa5: /* movsw/movsl/movsq */
15775 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15776 case 0xab: /* stosw/stosl */
15777 case 0xaf: /* scasw/scasl */
15778 intel_operand_size (v_mode
, sizeflag
);
15781 intel_operand_size (b_mode
, sizeflag
);
15784 oappend_maybe_intel ("%es:");
15785 ptr_reg (code
, sizeflag
);
15789 OP_DSreg (int code
, int sizeflag
)
15795 case 0x6f: /* outsw/outsl */
15796 intel_operand_size (z_mode
, sizeflag
);
15798 case 0xa5: /* movsw/movsl/movsq */
15799 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15800 case 0xad: /* lodsw/lodsl/lodsq */
15801 intel_operand_size (v_mode
, sizeflag
);
15804 intel_operand_size (b_mode
, sizeflag
);
15807 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15808 default segment register DS is printed. */
15809 if (!active_seg_prefix
)
15810 active_seg_prefix
= PREFIX_DS
;
15812 ptr_reg (code
, sizeflag
);
15816 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15824 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15826 all_prefixes
[last_lock_prefix
] = 0;
15827 used_prefixes
|= PREFIX_LOCK
;
15832 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15833 oappend_maybe_intel (scratchbuf
);
15837 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15846 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15848 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15849 oappend (scratchbuf
);
15853 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15855 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15856 oappend_maybe_intel (scratchbuf
);
15860 OP_R (int bytemode
, int sizeflag
)
15862 if (modrm
.mod
== 3)
15863 OP_E (bytemode
, sizeflag
);
15869 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15871 int reg
= modrm
.reg
;
15872 const char **names
;
15874 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15875 if (prefixes
& PREFIX_DATA
)
15884 oappend (names
[reg
]);
15888 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15890 int reg
= modrm
.reg
;
15891 const char **names
;
15903 && bytemode
!= xmm_mode
15904 && bytemode
!= xmmq_mode
15905 && bytemode
!= evex_half_bcst_xmmq_mode
15906 && bytemode
!= ymm_mode
15907 && bytemode
!= scalar_mode
)
15909 switch (vex
.length
)
15916 || (bytemode
!= vex_vsib_q_w_dq_mode
15917 && bytemode
!= vex_vsib_q_w_d_mode
))
15929 else if (bytemode
== xmmq_mode
15930 || bytemode
== evex_half_bcst_xmmq_mode
)
15932 switch (vex
.length
)
15945 else if (bytemode
== ymm_mode
)
15949 oappend (names
[reg
]);
15953 OP_EM (int bytemode
, int sizeflag
)
15956 const char **names
;
15958 if (modrm
.mod
!= 3)
15961 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15963 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15964 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15966 OP_E (bytemode
, sizeflag
);
15970 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15973 /* Skip mod/rm byte. */
15976 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15978 if (prefixes
& PREFIX_DATA
)
15987 oappend (names
[reg
]);
15990 /* cvt* are the only instructions in sse2 which have
15991 both SSE and MMX operands and also have 0x66 prefix
15992 in their opcode. 0x66 was originally used to differentiate
15993 between SSE and MMX instruction(operands). So we have to handle the
15994 cvt* separately using OP_EMC and OP_MXC */
15996 OP_EMC (int bytemode
, int sizeflag
)
15998 if (modrm
.mod
!= 3)
16000 if (intel_syntax
&& bytemode
== v_mode
)
16002 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16003 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16005 OP_E (bytemode
, sizeflag
);
16009 /* Skip mod/rm byte. */
16012 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16013 oappend (names_mm
[modrm
.rm
]);
16017 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16019 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16020 oappend (names_mm
[modrm
.reg
]);
16024 OP_EX (int bytemode
, int sizeflag
)
16027 const char **names
;
16029 /* Skip mod/rm byte. */
16033 if (modrm
.mod
!= 3)
16035 OP_E_memory (bytemode
, sizeflag
);
16050 if ((sizeflag
& SUFFIX_ALWAYS
)
16051 && (bytemode
== x_swap_mode
16052 || bytemode
== d_swap_mode
16053 || bytemode
== dqw_swap_mode
16054 || bytemode
== d_scalar_swap_mode
16055 || bytemode
== q_swap_mode
16056 || bytemode
== q_scalar_swap_mode
))
16060 && bytemode
!= xmm_mode
16061 && bytemode
!= xmmdw_mode
16062 && bytemode
!= xmmqd_mode
16063 && bytemode
!= xmm_mb_mode
16064 && bytemode
!= xmm_mw_mode
16065 && bytemode
!= xmm_md_mode
16066 && bytemode
!= xmm_mq_mode
16067 && bytemode
!= xmm_mdq_mode
16068 && bytemode
!= xmmq_mode
16069 && bytemode
!= evex_half_bcst_xmmq_mode
16070 && bytemode
!= ymm_mode
16071 && bytemode
!= d_scalar_mode
16072 && bytemode
!= d_scalar_swap_mode
16073 && bytemode
!= q_scalar_mode
16074 && bytemode
!= q_scalar_swap_mode
16075 && bytemode
!= vex_scalar_w_dq_mode
)
16077 switch (vex
.length
)
16092 else if (bytemode
== xmmq_mode
16093 || bytemode
== evex_half_bcst_xmmq_mode
)
16095 switch (vex
.length
)
16108 else if (bytemode
== ymm_mode
)
16112 oappend (names
[reg
]);
16116 OP_MS (int bytemode
, int sizeflag
)
16118 if (modrm
.mod
== 3)
16119 OP_EM (bytemode
, sizeflag
);
16125 OP_XS (int bytemode
, int sizeflag
)
16127 if (modrm
.mod
== 3)
16128 OP_EX (bytemode
, sizeflag
);
16134 OP_M (int bytemode
, int sizeflag
)
16136 if (modrm
.mod
== 3)
16137 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16140 OP_E (bytemode
, sizeflag
);
16144 OP_0f07 (int bytemode
, int sizeflag
)
16146 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16149 OP_E (bytemode
, sizeflag
);
16152 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16153 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16156 NOP_Fixup1 (int bytemode
, int sizeflag
)
16158 if ((prefixes
& PREFIX_DATA
) != 0
16161 && address_mode
== mode_64bit
))
16162 OP_REG (bytemode
, sizeflag
);
16164 strcpy (obuf
, "nop");
16168 NOP_Fixup2 (int bytemode
, int sizeflag
)
16170 if ((prefixes
& PREFIX_DATA
) != 0
16173 && address_mode
== mode_64bit
))
16174 OP_IMREG (bytemode
, sizeflag
);
16177 static const char *const Suffix3DNow
[] = {
16178 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16179 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16180 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16181 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16182 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16183 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16184 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16185 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16186 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16187 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16188 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16189 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16190 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16191 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16192 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16193 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16194 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16195 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16196 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16197 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16198 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16199 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16200 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16201 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16202 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16203 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16204 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16205 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16206 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16207 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16208 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16209 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16210 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16211 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16212 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16213 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16214 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16215 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16216 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16217 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16218 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16219 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16220 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16221 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16222 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16223 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16224 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16225 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16226 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16227 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16228 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16229 /* CC */ NULL
, NULL
, NULL
, NULL
,
16230 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16231 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16232 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16233 /* DC */ NULL
, NULL
, NULL
, NULL
,
16234 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16235 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16236 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16237 /* EC */ NULL
, NULL
, NULL
, NULL
,
16238 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16239 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16240 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16241 /* FC */ NULL
, NULL
, NULL
, NULL
,
16245 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16247 const char *mnemonic
;
16249 FETCH_DATA (the_info
, codep
+ 1);
16250 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16251 place where an 8-bit immediate would normally go. ie. the last
16252 byte of the instruction. */
16253 obufp
= mnemonicendp
;
16254 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16256 oappend (mnemonic
);
16259 /* Since a variable sized modrm/sib chunk is between the start
16260 of the opcode (0x0f0f) and the opcode suffix, we need to do
16261 all the modrm processing first, and don't know until now that
16262 we have a bad opcode. This necessitates some cleaning up. */
16263 op_out
[0][0] = '\0';
16264 op_out
[1][0] = '\0';
16267 mnemonicendp
= obufp
;
16270 static struct op simd_cmp_op
[] =
16272 { STRING_COMMA_LEN ("eq") },
16273 { STRING_COMMA_LEN ("lt") },
16274 { STRING_COMMA_LEN ("le") },
16275 { STRING_COMMA_LEN ("unord") },
16276 { STRING_COMMA_LEN ("neq") },
16277 { STRING_COMMA_LEN ("nlt") },
16278 { STRING_COMMA_LEN ("nle") },
16279 { STRING_COMMA_LEN ("ord") }
16283 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16285 unsigned int cmp_type
;
16287 FETCH_DATA (the_info
, codep
+ 1);
16288 cmp_type
= *codep
++ & 0xff;
16289 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16292 char *p
= mnemonicendp
- 2;
16296 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16297 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16301 /* We have a reserved extension byte. Output it directly. */
16302 scratchbuf
[0] = '$';
16303 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16304 oappend_maybe_intel (scratchbuf
);
16305 scratchbuf
[0] = '\0';
16310 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16311 int sizeflag ATTRIBUTE_UNUSED
)
16313 /* mwait %eax,%ecx */
16316 const char **names
= (address_mode
== mode_64bit
16317 ? names64
: names32
);
16318 strcpy (op_out
[0], names
[0]);
16319 strcpy (op_out
[1], names
[1]);
16320 two_source_ops
= 1;
16322 /* Skip mod/rm byte. */
16328 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16329 int sizeflag ATTRIBUTE_UNUSED
)
16331 /* monitor %eax,%ecx,%edx" */
16334 const char **op1_names
;
16335 const char **names
= (address_mode
== mode_64bit
16336 ? names64
: names32
);
16338 if (!(prefixes
& PREFIX_ADDR
))
16339 op1_names
= (address_mode
== mode_16bit
16340 ? names16
: names
);
16343 /* Remove "addr16/addr32". */
16344 all_prefixes
[last_addr_prefix
] = 0;
16345 op1_names
= (address_mode
!= mode_32bit
16346 ? names32
: names16
);
16347 used_prefixes
|= PREFIX_ADDR
;
16349 strcpy (op_out
[0], op1_names
[0]);
16350 strcpy (op_out
[1], names
[1]);
16351 strcpy (op_out
[2], names
[2]);
16352 two_source_ops
= 1;
16354 /* Skip mod/rm byte. */
16362 /* Throw away prefixes and 1st. opcode byte. */
16363 codep
= insn_codep
+ 1;
16368 REP_Fixup (int bytemode
, int sizeflag
)
16370 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16372 if (prefixes
& PREFIX_REPZ
)
16373 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16380 OP_IMREG (bytemode
, sizeflag
);
16383 OP_ESreg (bytemode
, sizeflag
);
16386 OP_DSreg (bytemode
, sizeflag
);
16394 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16398 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16400 if (prefixes
& PREFIX_REPNZ
)
16401 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16404 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16405 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16409 HLE_Fixup1 (int bytemode
, int sizeflag
)
16412 && (prefixes
& PREFIX_LOCK
) != 0)
16414 if (prefixes
& PREFIX_REPZ
)
16415 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16416 if (prefixes
& PREFIX_REPNZ
)
16417 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16420 OP_E (bytemode
, sizeflag
);
16423 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16424 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16428 HLE_Fixup2 (int bytemode
, int sizeflag
)
16430 if (modrm
.mod
!= 3)
16432 if (prefixes
& PREFIX_REPZ
)
16433 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16434 if (prefixes
& PREFIX_REPNZ
)
16435 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16438 OP_E (bytemode
, sizeflag
);
16441 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16442 "xrelease" for memory operand. No check for LOCK prefix. */
16445 HLE_Fixup3 (int bytemode
, int sizeflag
)
16448 && last_repz_prefix
> last_repnz_prefix
16449 && (prefixes
& PREFIX_REPZ
) != 0)
16450 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16452 OP_E (bytemode
, sizeflag
);
16456 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16461 /* Change cmpxchg8b to cmpxchg16b. */
16462 char *p
= mnemonicendp
- 2;
16463 mnemonicendp
= stpcpy (p
, "16b");
16466 else if ((prefixes
& PREFIX_LOCK
) != 0)
16468 if (prefixes
& PREFIX_REPZ
)
16469 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16470 if (prefixes
& PREFIX_REPNZ
)
16471 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16474 OP_M (bytemode
, sizeflag
);
16478 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
16480 const char **names
;
16484 switch (vex
.length
)
16498 oappend (names
[reg
]);
16502 CRC32_Fixup (int bytemode
, int sizeflag
)
16504 /* Add proper suffix to "crc32". */
16505 char *p
= mnemonicendp
;
16524 if (sizeflag
& DFLAG
)
16528 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16532 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16539 if (modrm
.mod
== 3)
16543 /* Skip mod/rm byte. */
16548 add
= (rex
& REX_B
) ? 8 : 0;
16549 if (bytemode
== b_mode
)
16553 oappend (names8rex
[modrm
.rm
+ add
]);
16555 oappend (names8
[modrm
.rm
+ add
]);
16561 oappend (names64
[modrm
.rm
+ add
]);
16562 else if ((prefixes
& PREFIX_DATA
))
16563 oappend (names16
[modrm
.rm
+ add
]);
16565 oappend (names32
[modrm
.rm
+ add
]);
16569 OP_E (bytemode
, sizeflag
);
16573 FXSAVE_Fixup (int bytemode
, int sizeflag
)
16575 /* Add proper suffix to "fxsave" and "fxrstor". */
16579 char *p
= mnemonicendp
;
16585 OP_M (bytemode
, sizeflag
);
16588 /* Display the destination register operand for instructions with
16592 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16595 const char **names
;
16603 reg
= vex
.register_specifier
;
16610 if (bytemode
== vex_scalar_mode
)
16612 oappend (names_xmm
[reg
]);
16616 switch (vex
.length
)
16623 case vex_vsib_q_w_dq_mode
:
16624 case vex_vsib_q_w_d_mode
:
16635 names
= names_mask
;
16649 case vex_vsib_q_w_dq_mode
:
16650 case vex_vsib_q_w_d_mode
:
16651 names
= vex
.w
? names_ymm
: names_xmm
;
16655 names
= names_mask
;
16669 oappend (names
[reg
]);
16672 /* Get the VEX immediate byte without moving codep. */
16674 static unsigned char
16675 get_vex_imm8 (int sizeflag
, int opnum
)
16677 int bytes_before_imm
= 0;
16679 if (modrm
.mod
!= 3)
16681 /* There are SIB/displacement bytes. */
16682 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16684 /* 32/64 bit address mode */
16685 int base
= modrm
.rm
;
16687 /* Check SIB byte. */
16690 FETCH_DATA (the_info
, codep
+ 1);
16692 /* When decoding the third source, don't increase
16693 bytes_before_imm as this has already been incremented
16694 by one in OP_E_memory while decoding the second
16697 bytes_before_imm
++;
16700 /* Don't increase bytes_before_imm when decoding the third source,
16701 it has already been incremented by OP_E_memory while decoding
16702 the second source operand. */
16708 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16709 SIB == 5, there is a 4 byte displacement. */
16711 /* No displacement. */
16714 /* 4 byte displacement. */
16715 bytes_before_imm
+= 4;
16718 /* 1 byte displacement. */
16719 bytes_before_imm
++;
16726 /* 16 bit address mode */
16727 /* Don't increase bytes_before_imm when decoding the third source,
16728 it has already been incremented by OP_E_memory while decoding
16729 the second source operand. */
16735 /* When modrm.rm == 6, there is a 2 byte displacement. */
16737 /* No displacement. */
16740 /* 2 byte displacement. */
16741 bytes_before_imm
+= 2;
16744 /* 1 byte displacement: when decoding the third source,
16745 don't increase bytes_before_imm as this has already
16746 been incremented by one in OP_E_memory while decoding
16747 the second source operand. */
16749 bytes_before_imm
++;
16757 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16758 return codep
[bytes_before_imm
];
16762 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16764 const char **names
;
16766 if (reg
== -1 && modrm
.mod
!= 3)
16768 OP_E_memory (bytemode
, sizeflag
);
16780 else if (reg
> 7 && address_mode
!= mode_64bit
)
16784 switch (vex
.length
)
16795 oappend (names
[reg
]);
16799 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16802 static unsigned char vex_imm8
;
16804 if (vex_w_done
== 0)
16808 /* Skip mod/rm byte. */
16812 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16815 reg
= vex_imm8
>> 4;
16817 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16819 else if (vex_w_done
== 1)
16824 reg
= vex_imm8
>> 4;
16826 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16830 /* Output the imm8 directly. */
16831 scratchbuf
[0] = '$';
16832 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16833 oappend_maybe_intel (scratchbuf
);
16834 scratchbuf
[0] = '\0';
16840 OP_Vex_2src (int bytemode
, int sizeflag
)
16842 if (modrm
.mod
== 3)
16844 int reg
= modrm
.rm
;
16848 oappend (names_xmm
[reg
]);
16853 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16855 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16856 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16858 OP_E (bytemode
, sizeflag
);
16863 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16865 if (modrm
.mod
== 3)
16867 /* Skip mod/rm byte. */
16873 oappend (names_xmm
[vex
.register_specifier
]);
16875 OP_Vex_2src (bytemode
, sizeflag
);
16879 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16882 OP_Vex_2src (bytemode
, sizeflag
);
16884 oappend (names_xmm
[vex
.register_specifier
]);
16888 OP_EX_VexW (int bytemode
, int sizeflag
)
16896 /* Skip mod/rm byte. */
16901 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16906 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16909 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16913 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16914 int sizeflag ATTRIBUTE_UNUSED
)
16916 /* Skip the immediate byte and check for invalid bits. */
16917 FETCH_DATA (the_info
, codep
+ 1);
16918 if (*codep
++ & 0xf)
16923 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16926 const char **names
;
16928 FETCH_DATA (the_info
, codep
+ 1);
16931 if (bytemode
!= x_mode
)
16938 if (reg
> 7 && address_mode
!= mode_64bit
)
16941 switch (vex
.length
)
16952 oappend (names
[reg
]);
16956 OP_XMM_VexW (int bytemode
, int sizeflag
)
16958 /* Turn off the REX.W bit since it is used for swapping operands
16961 OP_XMM (bytemode
, sizeflag
);
16965 OP_EX_Vex (int bytemode
, int sizeflag
)
16967 if (modrm
.mod
!= 3)
16969 if (vex
.register_specifier
!= 0)
16973 OP_EX (bytemode
, sizeflag
);
16977 OP_XMM_Vex (int bytemode
, int sizeflag
)
16979 if (modrm
.mod
!= 3)
16981 if (vex
.register_specifier
!= 0)
16985 OP_XMM (bytemode
, sizeflag
);
16989 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16991 switch (vex
.length
)
16994 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
16997 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17004 static struct op vex_cmp_op
[] =
17006 { STRING_COMMA_LEN ("eq") },
17007 { STRING_COMMA_LEN ("lt") },
17008 { STRING_COMMA_LEN ("le") },
17009 { STRING_COMMA_LEN ("unord") },
17010 { STRING_COMMA_LEN ("neq") },
17011 { STRING_COMMA_LEN ("nlt") },
17012 { STRING_COMMA_LEN ("nle") },
17013 { STRING_COMMA_LEN ("ord") },
17014 { STRING_COMMA_LEN ("eq_uq") },
17015 { STRING_COMMA_LEN ("nge") },
17016 { STRING_COMMA_LEN ("ngt") },
17017 { STRING_COMMA_LEN ("false") },
17018 { STRING_COMMA_LEN ("neq_oq") },
17019 { STRING_COMMA_LEN ("ge") },
17020 { STRING_COMMA_LEN ("gt") },
17021 { STRING_COMMA_LEN ("true") },
17022 { STRING_COMMA_LEN ("eq_os") },
17023 { STRING_COMMA_LEN ("lt_oq") },
17024 { STRING_COMMA_LEN ("le_oq") },
17025 { STRING_COMMA_LEN ("unord_s") },
17026 { STRING_COMMA_LEN ("neq_us") },
17027 { STRING_COMMA_LEN ("nlt_uq") },
17028 { STRING_COMMA_LEN ("nle_uq") },
17029 { STRING_COMMA_LEN ("ord_s") },
17030 { STRING_COMMA_LEN ("eq_us") },
17031 { STRING_COMMA_LEN ("nge_uq") },
17032 { STRING_COMMA_LEN ("ngt_uq") },
17033 { STRING_COMMA_LEN ("false_os") },
17034 { STRING_COMMA_LEN ("neq_os") },
17035 { STRING_COMMA_LEN ("ge_oq") },
17036 { STRING_COMMA_LEN ("gt_oq") },
17037 { STRING_COMMA_LEN ("true_us") },
17041 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17043 unsigned int cmp_type
;
17045 FETCH_DATA (the_info
, codep
+ 1);
17046 cmp_type
= *codep
++ & 0xff;
17047 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17050 char *p
= mnemonicendp
- 2;
17054 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17055 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17059 /* We have a reserved extension byte. Output it directly. */
17060 scratchbuf
[0] = '$';
17061 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17062 oappend_maybe_intel (scratchbuf
);
17063 scratchbuf
[0] = '\0';
17068 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17069 int sizeflag ATTRIBUTE_UNUSED
)
17071 unsigned int cmp_type
;
17076 FETCH_DATA (the_info
, codep
+ 1);
17077 cmp_type
= *codep
++ & 0xff;
17078 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17079 If it's the case, print suffix, otherwise - print the immediate. */
17080 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17085 char *p
= mnemonicendp
- 2;
17087 /* vpcmp* can have both one- and two-lettered suffix. */
17101 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17102 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17106 /* We have a reserved extension byte. Output it directly. */
17107 scratchbuf
[0] = '$';
17108 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17109 oappend_maybe_intel (scratchbuf
);
17110 scratchbuf
[0] = '\0';
17114 static const struct op pclmul_op
[] =
17116 { STRING_COMMA_LEN ("lql") },
17117 { STRING_COMMA_LEN ("hql") },
17118 { STRING_COMMA_LEN ("lqh") },
17119 { STRING_COMMA_LEN ("hqh") }
17123 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17124 int sizeflag ATTRIBUTE_UNUSED
)
17126 unsigned int pclmul_type
;
17128 FETCH_DATA (the_info
, codep
+ 1);
17129 pclmul_type
= *codep
++ & 0xff;
17130 switch (pclmul_type
)
17141 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17144 char *p
= mnemonicendp
- 3;
17149 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17150 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17154 /* We have a reserved extension byte. Output it directly. */
17155 scratchbuf
[0] = '$';
17156 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17157 oappend_maybe_intel (scratchbuf
);
17158 scratchbuf
[0] = '\0';
17163 MOVBE_Fixup (int bytemode
, int sizeflag
)
17165 /* Add proper suffix to "movbe". */
17166 char *p
= mnemonicendp
;
17175 if (sizeflag
& SUFFIX_ALWAYS
)
17181 if (sizeflag
& DFLAG
)
17185 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17190 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17197 OP_M (bytemode
, sizeflag
);
17201 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17204 const char **names
;
17206 /* Skip mod/rm byte. */
17220 oappend (names
[reg
]);
17224 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17226 const char **names
;
17233 oappend (names
[vex
.register_specifier
]);
17237 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17240 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17244 if ((rex
& REX_R
) != 0 || !vex
.r
)
17250 oappend (names_mask
[modrm
.reg
]);
17254 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17257 || (bytemode
!= evex_rounding_mode
17258 && bytemode
!= evex_sae_mode
))
17260 if (modrm
.mod
== 3 && vex
.b
)
17263 case evex_rounding_mode
:
17264 oappend (names_rounding
[vex
.ll
]);
17266 case evex_sae_mode
: