opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 #define XX { NULL, 0 }
 225 #define Bad_Opcode NULL, { { NULL, 0 } }
 226
 227 #define Eb { OP_E, b_mode }
 228 #define Ebnd { OP_E, bnd_mode }
 229 #define EbS { OP_E, b_swap_mode }
 230 #define Ev { OP_E, v_mode }
 231 #define Ev_bnd { OP_E, v_bnd_mode }
 232 #define EvS { OP_E, v_swap_mode }
 233 #define Ed { OP_E, d_mode }
 234 #define Edq { OP_E, dq_mode }
 235 #define Edqw { OP_E, dqw_mode }
 236 #define EdqwS { OP_E, dqw_swap_mode }
 237 #define Edqb { OP_E, dqb_mode }
 238 #define Edb { OP_E, db_mode }
 239 #define Edw { OP_E, dw_mode }
 240 #define Edqd { OP_E, dqd_mode }
 241 #define Eq { OP_E, q_mode }
 242 #define indirEv { OP_indirE, stack_v_mode }
 243 #define indirEp { OP_indirE, f_mode }
 244 #define stackEv { OP_E, stack_v_mode }
 245 #define Em { OP_E, m_mode }
 246 #define Ew { OP_E, w_mode }
 247 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 248 #define Ma { OP_M, a_mode }
 249 #define Mb { OP_M, b_mode }
 250 #define Md { OP_M, d_mode }
 251 #define Mo { OP_M, o_mode }
 252 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 253 #define Mq { OP_M, q_mode }
 254 #define Mx { OP_M, x_mode }
 255 #define Mxmm { OP_M, xmm_mode }
 256 #define Gb { OP_G, b_mode }
 257 #define Gbnd { OP_G, bnd_mode }
 258 #define Gv { OP_G, v_mode }
 259 #define Gd { OP_G, d_mode }
 260 #define Gdq { OP_G, dq_mode }
 261 #define Gm { OP_G, m_mode }
 262 #define Gw { OP_G, w_mode }
 263 #define Rd { OP_R, d_mode }
 264 #define Rdq { OP_R, dq_mode }
 265 #define Rm { OP_R, m_mode }
 266 #define Ib { OP_I, b_mode }
 267 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 268 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 269 #define Iv { OP_I, v_mode }
 270 #define sIv { OP_sI, v_mode }
 271 #define Iq { OP_I, q_mode }
 272 #define Iv64 { OP_I64, v_mode }
 273 #define Iw { OP_I, w_mode }
 274 #define I1 { OP_I, const_1_mode }
 275 #define Jb { OP_J, b_mode }
 276 #define Jv { OP_J, v_mode }
 277 #define Cm { OP_C, m_mode }
 278 #define Dm { OP_D, m_mode }
 279 #define Td { OP_T, d_mode }
 280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 281
 282 #define RMeAX { OP_REG, eAX_reg }
 283 #define RMeBX { OP_REG, eBX_reg }
 284 #define RMeCX { OP_REG, eCX_reg }
 285 #define RMeDX { OP_REG, eDX_reg }
 286 #define RMeSP { OP_REG, eSP_reg }
 287 #define RMeBP { OP_REG, eBP_reg }
 288 #define RMeSI { OP_REG, eSI_reg }
 289 #define RMeDI { OP_REG, eDI_reg }
 290 #define RMrAX { OP_REG, rAX_reg }
 291 #define RMrBX { OP_REG, rBX_reg }
 292 #define RMrCX { OP_REG, rCX_reg }
 293 #define RMrDX { OP_REG, rDX_reg }
 294 #define RMrSP { OP_REG, rSP_reg }
 295 #define RMrBP { OP_REG, rBP_reg }
 296 #define RMrSI { OP_REG, rSI_reg }
 297 #define RMrDI { OP_REG, rDI_reg }
 298 #define RMAL { OP_REG, al_reg }
 299 #define RMCL { OP_REG, cl_reg }
 300 #define RMDL { OP_REG, dl_reg }
 301 #define RMBL { OP_REG, bl_reg }
 302 #define RMAH { OP_REG, ah_reg }
 303 #define RMCH { OP_REG, ch_reg }
 304 #define RMDH { OP_REG, dh_reg }
 305 #define RMBH { OP_REG, bh_reg }
 306 #define RMAX { OP_REG, ax_reg }
 307 #define RMDX { OP_REG, dx_reg }
 308
 309 #define eAX { OP_IMREG, eAX_reg }
 310 #define eBX { OP_IMREG, eBX_reg }
 311 #define eCX { OP_IMREG, eCX_reg }
 312 #define eDX { OP_IMREG, eDX_reg }
 313 #define eSP { OP_IMREG, eSP_reg }
 314 #define eBP { OP_IMREG, eBP_reg }
 315 #define eSI { OP_IMREG, eSI_reg }
 316 #define eDI { OP_IMREG, eDI_reg }
 317 #define AL { OP_IMREG, al_reg }
 318 #define CL { OP_IMREG, cl_reg }
 319 #define DL { OP_IMREG, dl_reg }
 320 #define BL { OP_IMREG, bl_reg }
 321 #define AH { OP_IMREG, ah_reg }
 322 #define CH { OP_IMREG, ch_reg }
 323 #define DH { OP_IMREG, dh_reg }
 324 #define BH { OP_IMREG, bh_reg }
 325 #define AX { OP_IMREG, ax_reg }
 326 #define DX { OP_IMREG, dx_reg }
 327 #define zAX { OP_IMREG, z_mode_ax_reg }
 328 #define indirDX { OP_IMREG, indir_dx_reg }
 329
 330 #define Sw { OP_SEG, w_mode }
 331 #define Sv { OP_SEG, v_mode }
 332 #define Ap { OP_DIR, 0 }
 333 #define Ob { OP_OFF64, b_mode }
 334 #define Ov { OP_OFF64, v_mode }
 335 #define Xb { OP_DSreg, eSI_reg }
 336 #define Xv { OP_DSreg, eSI_reg }
 337 #define Xz { OP_DSreg, eSI_reg }
 338 #define Yb { OP_ESreg, eDI_reg }
 339 #define Yv { OP_ESreg, eDI_reg }
 340 #define DSBX { OP_DSreg, eBX_reg }
 341
 342 #define es { OP_REG, es_reg }
 343 #define ss { OP_REG, ss_reg }
 344 #define cs { OP_REG, cs_reg }
 345 #define ds { OP_REG, ds_reg }
 346 #define fs { OP_REG, fs_reg }
 347 #define gs { OP_REG, gs_reg }
 348
 349 #define MX { OP_MMX, 0 }
 350 #define XM { OP_XMM, 0 }
 351 #define XMScalar { OP_XMM, scalar_mode }
 352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 353 #define XMM { OP_XMM, xmm_mode }
 354 #define XMxmmq { OP_XMM, xmmq_mode }
 355 #define EM { OP_EM, v_mode }
 356 #define EMS { OP_EM, v_swap_mode }
 357 #define EMd { OP_EM, d_mode }
 358 #define EMx { OP_EM, x_mode }
 359 #define EXw { OP_EX, w_mode }
 360 #define EXd { OP_EX, d_mode }
 361 #define EXdScalar { OP_EX, d_scalar_mode }
 362 #define EXdS { OP_EX, d_swap_mode }
 363 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 364 #define EXq { OP_EX, q_mode }
 365 #define EXqScalar { OP_EX, q_scalar_mode }
 366 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 367 #define EXqS { OP_EX, q_swap_mode }
 368 #define EXx { OP_EX, x_mode }
 369 #define EXxS { OP_EX, x_swap_mode }
 370 #define EXxmm { OP_EX, xmm_mode }
 371 #define EXymm { OP_EX, ymm_mode }
 372 #define EXxmmq { OP_EX, xmmq_mode }
 373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 376 #define EXxmm_md { OP_EX, xmm_md_mode }
 377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 378 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 379 #define EXxmmdw { OP_EX, xmmdw_mode }
 380 #define EXxmmqd { OP_EX, xmmqd_mode }
 381 #define EXymmq { OP_EX, ymmq_mode }
 382 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 383 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 384 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 385 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 386 #define MS { OP_MS, v_mode }
 387 #define XS { OP_XS, v_mode }
 388 #define EMCq { OP_EMC, q_mode }
 389 #define MXC { OP_MXC, 0 }
 390 #define OPSUF { OP_3DNowSuffix, 0 }
 391 #define CMP { CMP_Fixup, 0 }
 392 #define XMM0 { XMM_Fixup, 0 }
 393 #define FXSAVE { FXSAVE_Fixup, 0 }
 394 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 395 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 396
 397 #define Vex { OP_VEX, vex_mode }
 398 #define VexScalar { OP_VEX, vex_scalar_mode }
 399 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 400 #define Vex128 { OP_VEX, vex128_mode }
 401 #define Vex256 { OP_VEX, vex256_mode }
 402 #define VexGdq { OP_VEX, dq_mode }
 403 #define VexI4 { VEXI4_Fixup, 0}
 404 #define EXdVex { OP_EX_Vex, d_mode }
 405 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 406 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 407 #define EXqVex { OP_EX_Vex, q_mode }
 408 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 409 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 410 #define EXVexW { OP_EX_VexW, x_mode }
 411 #define EXdVexW { OP_EX_VexW, d_mode }
 412 #define EXqVexW { OP_EX_VexW, q_mode }
 413 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 414 #define XMVex { OP_XMM_Vex, 0 }
 415 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 416 #define XMVexW { OP_XMM_VexW, 0 }
 417 #define XMVexI4 { OP_REG_VexI4, x_mode }
 418 #define PCLMUL { PCLMUL_Fixup, 0 }
 419 #define VZERO { VZERO_Fixup, 0 }
 420 #define VCMP { VCMP_Fixup, 0 }
 421 #define VPCMP { VPCMP_Fixup, 0 }
 422
 423 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 424 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 425
 426 #define XMask { OP_Mask, mask_mode }
 427 #define MaskG { OP_G, mask_mode }
 428 #define MaskE { OP_E, mask_mode }
 429 #define MaskBDE { OP_E, mask_bd_mode }
 430 #define MaskR { OP_R, mask_mode }
 431 #define MaskVex { OP_VEX, mask_mode }
 432
 433 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 434 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 435 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 436 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 437
 438 /* Used handle "rep" prefix for string instructions.  */
 439 #define Xbr { REP_Fixup, eSI_reg }
 440 #define Xvr { REP_Fixup, eSI_reg }
 441 #define Ybr { REP_Fixup, eDI_reg }
 442 #define Yvr { REP_Fixup, eDI_reg }
 443 #define Yzr { REP_Fixup, eDI_reg }
 444 #define indirDXr { REP_Fixup, indir_dx_reg }
 445 #define ALr { REP_Fixup, al_reg }
 446 #define eAXr { REP_Fixup, eAX_reg }
 447
 448 /* Used handle HLE prefix for lockable instructions.  */
 449 #define Ebh1 { HLE_Fixup1, b_mode }
 450 #define Evh1 { HLE_Fixup1, v_mode }
 451 #define Ebh2 { HLE_Fixup2, b_mode }
 452 #define Evh2 { HLE_Fixup2, v_mode }
 453 #define Ebh3 { HLE_Fixup3, b_mode }
 454 #define Evh3 { HLE_Fixup3, v_mode }
 455
 456 #define BND { BND_Fixup, 0 }
 457
 458 #define cond_jump_flag { NULL, cond_jump_mode }
 459 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 460
 461 /* bits in sizeflag */
 462 #define SUFFIX_ALWAYS 4
 463 #define AFLAG 2
 464 #define DFLAG 1
 465
 466 enum
 467 {
 468   /* byte operand */
 469   b_mode = 1,
 470   /* byte operand with operand swapped */
 471   b_swap_mode,
 472   /* byte operand, sign extend like 'T' suffix */
 473   b_T_mode,
 474   /* operand size depends on prefixes */
 475   v_mode,
 476   /* operand size depends on prefixes with operand swapped */
 477   v_swap_mode,
 478   /* word operand */
 479   w_mode,
 480   /* double word operand  */
 481   d_mode,
 482   /* double word operand with operand swapped */
 483   d_swap_mode,
 484   /* quad word operand */
 485   q_mode,
 486   /* quad word operand with operand swapped */
 487   q_swap_mode,
 488   /* ten-byte operand */
 489   t_mode,
 490   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 491      broadcast enabled.  */
 492   x_mode,
 493   /* Similar to x_mode, but with different EVEX mem shifts.  */
 494   evex_x_gscat_mode,
 495   /* Similar to x_mode, but with disabled broadcast.  */
 496   evex_x_nobcst_mode,
 497   /* Similar to x_mode, but with operands swapped and disabled broadcast
 498      in EVEX.  */
 499   x_swap_mode,
 500   /* 16-byte XMM operand */
 501   xmm_mode,
 502   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 503      memory operand (depending on vector length).  Broadcast isn't
 504      allowed.  */
 505   xmmq_mode,
 506   /* Same as xmmq_mode, but broadcast is allowed.  */
 507   evex_half_bcst_xmmq_mode,
 508   /* XMM register or byte memory operand */
 509   xmm_mb_mode,
 510   /* XMM register or word memory operand */
 511   xmm_mw_mode,
 512   /* XMM register or double word memory operand */
 513   xmm_md_mode,
 514   /* XMM register or quad word memory operand */
 515   xmm_mq_mode,
 516   /* XMM register or double/quad word memory operand, depending on
 517      VEX.W.  */
 518   xmm_mdq_mode,
 519   /* 16-byte XMM, word, double word or quad word operand.  */
 520   xmmdw_mode,
 521   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 522   xmmqd_mode,
 523   /* 32-byte YMM operand */
 524   ymm_mode,
 525   /* quad word, ymmword or zmmword memory operand.  */
 526   ymmq_mode,
 527   /* 32-byte YMM or 16-byte word operand */
 528   ymmxmm_mode,
 529   /* d_mode in 32bit, q_mode in 64bit mode.  */
 530   m_mode,
 531   /* pair of v_mode operands */
 532   a_mode,
 533   cond_jump_mode,
 534   loop_jcxz_mode,
 535   v_bnd_mode,
 536   /* operand size depends on REX prefixes.  */
 537   dq_mode,
 538   /* registers like dq_mode, memory like w_mode.  */
 539   dqw_mode,
 540   dqw_swap_mode,
 541   bnd_mode,
 542   /* 4- or 6-byte pointer operand */
 543   f_mode,
 544   const_1_mode,
 545   /* v_mode for stack-related opcodes.  */
 546   stack_v_mode,
 547   /* non-quad operand size depends on prefixes */
 548   z_mode,
 549   /* 16-byte operand */
 550   o_mode,
 551   /* registers like dq_mode, memory like b_mode.  */
 552   dqb_mode,
 553   /* registers like d_mode, memory like b_mode.  */
 554   db_mode,
 555   /* registers like d_mode, memory like w_mode.  */
 556   dw_mode,
 557   /* registers like dq_mode, memory like d_mode.  */
 558   dqd_mode,
 559   /* normal vex mode */
 560   vex_mode,
 561   /* 128bit vex mode */
 562   vex128_mode,
 563   /* 256bit vex mode */
 564   vex256_mode,
 565   /* operand size depends on the VEX.W bit.  */
 566   vex_w_dq_mode,
 567
 568   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 569   vex_vsib_d_w_dq_mode,
 570   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 571   vex_vsib_d_w_d_mode,
 572   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 573   vex_vsib_q_w_dq_mode,
 574   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 575   vex_vsib_q_w_d_mode,
 576
 577   /* scalar, ignore vector length.  */
 578   scalar_mode,
 579   /* like d_mode, ignore vector length.  */
 580   d_scalar_mode,
 581   /* like d_swap_mode, ignore vector length.  */
 582   d_scalar_swap_mode,
 583   /* like q_mode, ignore vector length.  */
 584   q_scalar_mode,
 585   /* like q_swap_mode, ignore vector length.  */
 586   q_scalar_swap_mode,
 587   /* like vex_mode, ignore vector length.  */
 588   vex_scalar_mode,
 589   /* like vex_w_dq_mode, ignore vector length.  */
 590   vex_scalar_w_dq_mode,
 591
 592   /* Static rounding.  */
 593   evex_rounding_mode,
 594   /* Supress all exceptions.  */
 595   evex_sae_mode,
 596
 597   /* Mask register operand.  */
 598   mask_mode,
 599   /* Mask register operand.  */
 600   mask_bd_mode,
 601
 602   es_reg,
 603   cs_reg,
 604   ss_reg,
 605   ds_reg,
 606   fs_reg,
 607   gs_reg,
 608
 609   eAX_reg,
 610   eCX_reg,
 611   eDX_reg,
 612   eBX_reg,
 613   eSP_reg,
 614   eBP_reg,
 615   eSI_reg,
 616   eDI_reg,
 617
 618   al_reg,
 619   cl_reg,
 620   dl_reg,
 621   bl_reg,
 622   ah_reg,
 623   ch_reg,
 624   dh_reg,
 625   bh_reg,
 626
 627   ax_reg,
 628   cx_reg,
 629   dx_reg,
 630   bx_reg,
 631   sp_reg,
 632   bp_reg,
 633   si_reg,
 634   di_reg,
 635
 636   rAX_reg,
 637   rCX_reg,
 638   rDX_reg,
 639   rBX_reg,
 640   rSP_reg,
 641   rBP_reg,
 642   rSI_reg,
 643   rDI_reg,
 644
 645   z_mode_ax_reg,
 646   indir_dx_reg
 647 };
 648
 649 enum
 650 {
 651   FLOATCODE = 1,
 652   USE_REG_TABLE,
 653   USE_MOD_TABLE,
 654   USE_RM_TABLE,
 655   USE_PREFIX_TABLE,
 656   USE_X86_64_TABLE,
 657   USE_3BYTE_TABLE,
 658   USE_XOP_8F_TABLE,
 659   USE_VEX_C4_TABLE,
 660   USE_VEX_C5_TABLE,
 661   USE_VEX_LEN_TABLE,
 662   USE_VEX_W_TABLE,
 663   USE_EVEX_TABLE
 664 };
 665
 666 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 667
 668 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 669 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 670 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 671 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 672 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 673 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 674 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 675 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 676 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 677 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 678 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 679 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 680 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 681
 682 enum
 683 {
 684   REG_80 = 0,
 685   REG_81,
 686   REG_82,
 687   REG_8F,
 688   REG_C0,
 689   REG_C1,
 690   REG_C6,
 691   REG_C7,
 692   REG_D0,
 693   REG_D1,
 694   REG_D2,
 695   REG_D3,
 696   REG_F6,
 697   REG_F7,
 698   REG_FE,
 699   REG_FF,
 700   REG_0F00,
 701   REG_0F01,
 702   REG_0F0D,
 703   REG_0F18,
 704   REG_0F71,
 705   REG_0F72,
 706   REG_0F73,
 707   REG_0FA6,
 708   REG_0FA7,
 709   REG_0FAE,
 710   REG_0FBA,
 711   REG_0FC7,
 712   REG_VEX_0F71,
 713   REG_VEX_0F72,
 714   REG_VEX_0F73,
 715   REG_VEX_0FAE,
 716   REG_VEX_0F38F3,
 717   REG_XOP_LWPCB,
 718   REG_XOP_LWP,
 719   REG_XOP_TBM_01,
 720   REG_XOP_TBM_02,
 721
 722   REG_EVEX_0F71,
 723   REG_EVEX_0F72,
 724   REG_EVEX_0F73,
 725   REG_EVEX_0F38C6,
 726   REG_EVEX_0F38C7
 727 };
 728
 729 enum
 730 {
 731   MOD_8D = 0,
 732   MOD_C6_REG_7,
 733   MOD_C7_REG_7,
 734   MOD_FF_REG_3,
 735   MOD_FF_REG_5,
 736   MOD_0F01_REG_0,
 737   MOD_0F01_REG_1,
 738   MOD_0F01_REG_2,
 739   MOD_0F01_REG_3,
 740   MOD_0F01_REG_7,
 741   MOD_0F12_PREFIX_0,
 742   MOD_0F13,
 743   MOD_0F16_PREFIX_0,
 744   MOD_0F17,
 745   MOD_0F18_REG_0,
 746   MOD_0F18_REG_1,
 747   MOD_0F18_REG_2,
 748   MOD_0F18_REG_3,
 749   MOD_0F18_REG_4,
 750   MOD_0F18_REG_5,
 751   MOD_0F18_REG_6,
 752   MOD_0F18_REG_7,
 753   MOD_0F1A_PREFIX_0,
 754   MOD_0F1B_PREFIX_0,
 755   MOD_0F1B_PREFIX_1,
 756   MOD_0F20,
 757   MOD_0F21,
 758   MOD_0F22,
 759   MOD_0F23,
 760   MOD_0F24,
 761   MOD_0F26,
 762   MOD_0F2B_PREFIX_0,
 763   MOD_0F2B_PREFIX_1,
 764   MOD_0F2B_PREFIX_2,
 765   MOD_0F2B_PREFIX_3,
 766   MOD_0F51,
 767   MOD_0F71_REG_2,
 768   MOD_0F71_REG_4,
 769   MOD_0F71_REG_6,
 770   MOD_0F72_REG_2,
 771   MOD_0F72_REG_4,
 772   MOD_0F72_REG_6,
 773   MOD_0F73_REG_2,
 774   MOD_0F73_REG_3,
 775   MOD_0F73_REG_6,
 776   MOD_0F73_REG_7,
 777   MOD_0FAE_REG_0,
 778   MOD_0FAE_REG_1,
 779   MOD_0FAE_REG_2,
 780   MOD_0FAE_REG_3,
 781   MOD_0FAE_REG_4,
 782   MOD_0FAE_REG_5,
 783   MOD_0FAE_REG_6,
 784   MOD_0FAE_REG_7,
 785   MOD_0FB2,
 786   MOD_0FB4,
 787   MOD_0FB5,
 788   MOD_0FC7_REG_3,
 789   MOD_0FC7_REG_4,
 790   MOD_0FC7_REG_5,
 791   MOD_0FC7_REG_6,
 792   MOD_0FC7_REG_7,
 793   MOD_0FD7,
 794   MOD_0FE7_PREFIX_2,
 795   MOD_0FF0_PREFIX_3,
 796   MOD_0F382A_PREFIX_2,
 797   MOD_62_32BIT,
 798   MOD_C4_32BIT,
 799   MOD_C5_32BIT,
 800   MOD_VEX_0F12_PREFIX_0,
 801   MOD_VEX_0F13,
 802   MOD_VEX_0F16_PREFIX_0,
 803   MOD_VEX_0F17,
 804   MOD_VEX_0F2B,
 805   MOD_VEX_0F50,
 806   MOD_VEX_0F71_REG_2,
 807   MOD_VEX_0F71_REG_4,
 808   MOD_VEX_0F71_REG_6,
 809   MOD_VEX_0F72_REG_2,
 810   MOD_VEX_0F72_REG_4,
 811   MOD_VEX_0F72_REG_6,
 812   MOD_VEX_0F73_REG_2,
 813   MOD_VEX_0F73_REG_3,
 814   MOD_VEX_0F73_REG_6,
 815   MOD_VEX_0F73_REG_7,
 816   MOD_VEX_0FAE_REG_2,
 817   MOD_VEX_0FAE_REG_3,
 818   MOD_VEX_0FD7_PREFIX_2,
 819   MOD_VEX_0FE7_PREFIX_2,
 820   MOD_VEX_0FF0_PREFIX_3,
 821   MOD_VEX_0F381A_PREFIX_2,
 822   MOD_VEX_0F382A_PREFIX_2,
 823   MOD_VEX_0F382C_PREFIX_2,
 824   MOD_VEX_0F382D_PREFIX_2,
 825   MOD_VEX_0F382E_PREFIX_2,
 826   MOD_VEX_0F382F_PREFIX_2,
 827   MOD_VEX_0F385A_PREFIX_2,
 828   MOD_VEX_0F388C_PREFIX_2,
 829   MOD_VEX_0F388E_PREFIX_2,
 830
 831   MOD_EVEX_0F10_PREFIX_1,
 832   MOD_EVEX_0F10_PREFIX_3,
 833   MOD_EVEX_0F11_PREFIX_1,
 834   MOD_EVEX_0F11_PREFIX_3,
 835   MOD_EVEX_0F12_PREFIX_0,
 836   MOD_EVEX_0F16_PREFIX_0,
 837   MOD_EVEX_0F38C6_REG_1,
 838   MOD_EVEX_0F38C6_REG_2,
 839   MOD_EVEX_0F38C6_REG_5,
 840   MOD_EVEX_0F38C6_REG_6,
 841   MOD_EVEX_0F38C7_REG_1,
 842   MOD_EVEX_0F38C7_REG_2,
 843   MOD_EVEX_0F38C7_REG_5,
 844   MOD_EVEX_0F38C7_REG_6
 845 };
 846
 847 enum
 848 {
 849   RM_C6_REG_7 = 0,
 850   RM_C7_REG_7,
 851   RM_0F01_REG_0,
 852   RM_0F01_REG_1,
 853   RM_0F01_REG_2,
 854   RM_0F01_REG_3,
 855   RM_0F01_REG_7,
 856   RM_0FAE_REG_5,
 857   RM_0FAE_REG_6,
 858   RM_0FAE_REG_7
 859 };
 860
 861 enum
 862 {
 863   PREFIX_90 = 0,
 864   PREFIX_0F10,
 865   PREFIX_0F11,
 866   PREFIX_0F12,
 867   PREFIX_0F16,
 868   PREFIX_0F1A,
 869   PREFIX_0F1B,
 870   PREFIX_0F2A,
 871   PREFIX_0F2B,
 872   PREFIX_0F2C,
 873   PREFIX_0F2D,
 874   PREFIX_0F2E,
 875   PREFIX_0F2F,
 876   PREFIX_0F51,
 877   PREFIX_0F52,
 878   PREFIX_0F53,
 879   PREFIX_0F58,
 880   PREFIX_0F59,
 881   PREFIX_0F5A,
 882   PREFIX_0F5B,
 883   PREFIX_0F5C,
 884   PREFIX_0F5D,
 885   PREFIX_0F5E,
 886   PREFIX_0F5F,
 887   PREFIX_0F60,
 888   PREFIX_0F61,
 889   PREFIX_0F62,
 890   PREFIX_0F6C,
 891   PREFIX_0F6D,
 892   PREFIX_0F6F,
 893   PREFIX_0F70,
 894   PREFIX_0F73_REG_3,
 895   PREFIX_0F73_REG_7,
 896   PREFIX_0F78,
 897   PREFIX_0F79,
 898   PREFIX_0F7C,
 899   PREFIX_0F7D,
 900   PREFIX_0F7E,
 901   PREFIX_0F7F,
 902   PREFIX_0FAE_REG_0,
 903   PREFIX_0FAE_REG_1,
 904   PREFIX_0FAE_REG_2,
 905   PREFIX_0FAE_REG_3,
 906   PREFIX_0FAE_REG_7,
 907   PREFIX_0FB8,
 908   PREFIX_0FBC,
 909   PREFIX_0FBD,
 910   PREFIX_0FC2,
 911   PREFIX_0FC3,
 912   PREFIX_0FC7_REG_6,
 913   PREFIX_0FD0,
 914   PREFIX_0FD6,
 915   PREFIX_0FE6,
 916   PREFIX_0FE7,
 917   PREFIX_0FF0,
 918   PREFIX_0FF7,
 919   PREFIX_0F3810,
 920   PREFIX_0F3814,
 921   PREFIX_0F3815,
 922   PREFIX_0F3817,
 923   PREFIX_0F3820,
 924   PREFIX_0F3821,
 925   PREFIX_0F3822,
 926   PREFIX_0F3823,
 927   PREFIX_0F3824,
 928   PREFIX_0F3825,
 929   PREFIX_0F3828,
 930   PREFIX_0F3829,
 931   PREFIX_0F382A,
 932   PREFIX_0F382B,
 933   PREFIX_0F3830,
 934   PREFIX_0F3831,
 935   PREFIX_0F3832,
 936   PREFIX_0F3833,
 937   PREFIX_0F3834,
 938   PREFIX_0F3835,
 939   PREFIX_0F3837,
 940   PREFIX_0F3838,
 941   PREFIX_0F3839,
 942   PREFIX_0F383A,
 943   PREFIX_0F383B,
 944   PREFIX_0F383C,
 945   PREFIX_0F383D,
 946   PREFIX_0F383E,
 947   PREFIX_0F383F,
 948   PREFIX_0F3840,
 949   PREFIX_0F3841,
 950   PREFIX_0F3880,
 951   PREFIX_0F3881,
 952   PREFIX_0F3882,
 953   PREFIX_0F38C8,
 954   PREFIX_0F38C9,
 955   PREFIX_0F38CA,
 956   PREFIX_0F38CB,
 957   PREFIX_0F38CC,
 958   PREFIX_0F38CD,
 959   PREFIX_0F38DB,
 960   PREFIX_0F38DC,
 961   PREFIX_0F38DD,
 962   PREFIX_0F38DE,
 963   PREFIX_0F38DF,
 964   PREFIX_0F38F0,
 965   PREFIX_0F38F1,
 966   PREFIX_0F38F6,
 967   PREFIX_0F3A08,
 968   PREFIX_0F3A09,
 969   PREFIX_0F3A0A,
 970   PREFIX_0F3A0B,
 971   PREFIX_0F3A0C,
 972   PREFIX_0F3A0D,
 973   PREFIX_0F3A0E,
 974   PREFIX_0F3A14,
 975   PREFIX_0F3A15,
 976   PREFIX_0F3A16,
 977   PREFIX_0F3A17,
 978   PREFIX_0F3A20,
 979   PREFIX_0F3A21,
 980   PREFIX_0F3A22,
 981   PREFIX_0F3A40,
 982   PREFIX_0F3A41,
 983   PREFIX_0F3A42,
 984   PREFIX_0F3A44,
 985   PREFIX_0F3A60,
 986   PREFIX_0F3A61,
 987   PREFIX_0F3A62,
 988   PREFIX_0F3A63,
 989   PREFIX_0F3ACC,
 990   PREFIX_0F3ADF,
 991   PREFIX_VEX_0F10,
 992   PREFIX_VEX_0F11,
 993   PREFIX_VEX_0F12,
 994   PREFIX_VEX_0F16,
 995   PREFIX_VEX_0F2A,
 996   PREFIX_VEX_0F2C,
 997   PREFIX_VEX_0F2D,
 998   PREFIX_VEX_0F2E,
 999   PREFIX_VEX_0F2F,
1000   PREFIX_VEX_0F41,
1001   PREFIX_VEX_0F42,
1002   PREFIX_VEX_0F44,
1003   PREFIX_VEX_0F45,
1004   PREFIX_VEX_0F46,
1005   PREFIX_VEX_0F47,
1006   PREFIX_VEX_0F4A,
1007   PREFIX_VEX_0F4B,
1008   PREFIX_VEX_0F51,
1009   PREFIX_VEX_0F52,
1010   PREFIX_VEX_0F53,
1011   PREFIX_VEX_0F58,
1012   PREFIX_VEX_0F59,
1013   PREFIX_VEX_0F5A,
1014   PREFIX_VEX_0F5B,
1015   PREFIX_VEX_0F5C,
1016   PREFIX_VEX_0F5D,
1017   PREFIX_VEX_0F5E,
1018   PREFIX_VEX_0F5F,
1019   PREFIX_VEX_0F60,
1020   PREFIX_VEX_0F61,
1021   PREFIX_VEX_0F62,
1022   PREFIX_VEX_0F63,
1023   PREFIX_VEX_0F64,
1024   PREFIX_VEX_0F65,
1025   PREFIX_VEX_0F66,
1026   PREFIX_VEX_0F67,
1027   PREFIX_VEX_0F68,
1028   PREFIX_VEX_0F69,
1029   PREFIX_VEX_0F6A,
1030   PREFIX_VEX_0F6B,
1031   PREFIX_VEX_0F6C,
1032   PREFIX_VEX_0F6D,
1033   PREFIX_VEX_0F6E,
1034   PREFIX_VEX_0F6F,
1035   PREFIX_VEX_0F70,
1036   PREFIX_VEX_0F71_REG_2,
1037   PREFIX_VEX_0F71_REG_4,
1038   PREFIX_VEX_0F71_REG_6,
1039   PREFIX_VEX_0F72_REG_2,
1040   PREFIX_VEX_0F72_REG_4,
1041   PREFIX_VEX_0F72_REG_6,
1042   PREFIX_VEX_0F73_REG_2,
1043   PREFIX_VEX_0F73_REG_3,
1044   PREFIX_VEX_0F73_REG_6,
1045   PREFIX_VEX_0F73_REG_7,
1046   PREFIX_VEX_0F74,
1047   PREFIX_VEX_0F75,
1048   PREFIX_VEX_0F76,
1049   PREFIX_VEX_0F77,
1050   PREFIX_VEX_0F7C,
1051   PREFIX_VEX_0F7D,
1052   PREFIX_VEX_0F7E,
1053   PREFIX_VEX_0F7F,
1054   PREFIX_VEX_0F90,
1055   PREFIX_VEX_0F91,
1056   PREFIX_VEX_0F92,
1057   PREFIX_VEX_0F93,
1058   PREFIX_VEX_0F98,
1059   PREFIX_VEX_0F99,
1060   PREFIX_VEX_0FC2,
1061   PREFIX_VEX_0FC4,
1062   PREFIX_VEX_0FC5,
1063   PREFIX_VEX_0FD0,
1064   PREFIX_VEX_0FD1,
1065   PREFIX_VEX_0FD2,
1066   PREFIX_VEX_0FD3,
1067   PREFIX_VEX_0FD4,
1068   PREFIX_VEX_0FD5,
1069   PREFIX_VEX_0FD6,
1070   PREFIX_VEX_0FD7,
1071   PREFIX_VEX_0FD8,
1072   PREFIX_VEX_0FD9,
1073   PREFIX_VEX_0FDA,
1074   PREFIX_VEX_0FDB,
1075   PREFIX_VEX_0FDC,
1076   PREFIX_VEX_0FDD,
1077   PREFIX_VEX_0FDE,
1078   PREFIX_VEX_0FDF,
1079   PREFIX_VEX_0FE0,
1080   PREFIX_VEX_0FE1,
1081   PREFIX_VEX_0FE2,
1082   PREFIX_VEX_0FE3,
1083   PREFIX_VEX_0FE4,
1084   PREFIX_VEX_0FE5,
1085   PREFIX_VEX_0FE6,
1086   PREFIX_VEX_0FE7,
1087   PREFIX_VEX_0FE8,
1088   PREFIX_VEX_0FE9,
1089   PREFIX_VEX_0FEA,
1090   PREFIX_VEX_0FEB,
1091   PREFIX_VEX_0FEC,
1092   PREFIX_VEX_0FED,
1093   PREFIX_VEX_0FEE,
1094   PREFIX_VEX_0FEF,
1095   PREFIX_VEX_0FF0,
1096   PREFIX_VEX_0FF1,
1097   PREFIX_VEX_0FF2,
1098   PREFIX_VEX_0FF3,
1099   PREFIX_VEX_0FF4,
1100   PREFIX_VEX_0FF5,
1101   PREFIX_VEX_0FF6,
1102   PREFIX_VEX_0FF7,
1103   PREFIX_VEX_0FF8,
1104   PREFIX_VEX_0FF9,
1105   PREFIX_VEX_0FFA,
1106   PREFIX_VEX_0FFB,
1107   PREFIX_VEX_0FFC,
1108   PREFIX_VEX_0FFD,
1109   PREFIX_VEX_0FFE,
1110   PREFIX_VEX_0F3800,
1111   PREFIX_VEX_0F3801,
1112   PREFIX_VEX_0F3802,
1113   PREFIX_VEX_0F3803,
1114   PREFIX_VEX_0F3804,
1115   PREFIX_VEX_0F3805,
1116   PREFIX_VEX_0F3806,
1117   PREFIX_VEX_0F3807,
1118   PREFIX_VEX_0F3808,
1119   PREFIX_VEX_0F3809,
1120   PREFIX_VEX_0F380A,
1121   PREFIX_VEX_0F380B,
1122   PREFIX_VEX_0F380C,
1123   PREFIX_VEX_0F380D,
1124   PREFIX_VEX_0F380E,
1125   PREFIX_VEX_0F380F,
1126   PREFIX_VEX_0F3813,
1127   PREFIX_VEX_0F3816,
1128   PREFIX_VEX_0F3817,
1129   PREFIX_VEX_0F3818,
1130   PREFIX_VEX_0F3819,
1131   PREFIX_VEX_0F381A,
1132   PREFIX_VEX_0F381C,
1133   PREFIX_VEX_0F381D,
1134   PREFIX_VEX_0F381E,
1135   PREFIX_VEX_0F3820,
1136   PREFIX_VEX_0F3821,
1137   PREFIX_VEX_0F3822,
1138   PREFIX_VEX_0F3823,
1139   PREFIX_VEX_0F3824,
1140   PREFIX_VEX_0F3825,
1141   PREFIX_VEX_0F3828,
1142   PREFIX_VEX_0F3829,
1143   PREFIX_VEX_0F382A,
1144   PREFIX_VEX_0F382B,
1145   PREFIX_VEX_0F382C,
1146   PREFIX_VEX_0F382D,
1147   PREFIX_VEX_0F382E,
1148   PREFIX_VEX_0F382F,
1149   PREFIX_VEX_0F3830,
1150   PREFIX_VEX_0F3831,
1151   PREFIX_VEX_0F3832,
1152   PREFIX_VEX_0F3833,
1153   PREFIX_VEX_0F3834,
1154   PREFIX_VEX_0F3835,
1155   PREFIX_VEX_0F3836,
1156   PREFIX_VEX_0F3837,
1157   PREFIX_VEX_0F3838,
1158   PREFIX_VEX_0F3839,
1159   PREFIX_VEX_0F383A,
1160   PREFIX_VEX_0F383B,
1161   PREFIX_VEX_0F383C,
1162   PREFIX_VEX_0F383D,
1163   PREFIX_VEX_0F383E,
1164   PREFIX_VEX_0F383F,
1165   PREFIX_VEX_0F3840,
1166   PREFIX_VEX_0F3841,
1167   PREFIX_VEX_0F3845,
1168   PREFIX_VEX_0F3846,
1169   PREFIX_VEX_0F3847,
1170   PREFIX_VEX_0F3858,
1171   PREFIX_VEX_0F3859,
1172   PREFIX_VEX_0F385A,
1173   PREFIX_VEX_0F3878,
1174   PREFIX_VEX_0F3879,
1175   PREFIX_VEX_0F388C,
1176   PREFIX_VEX_0F388E,
1177   PREFIX_VEX_0F3890,
1178   PREFIX_VEX_0F3891,
1179   PREFIX_VEX_0F3892,
1180   PREFIX_VEX_0F3893,
1181   PREFIX_VEX_0F3896,
1182   PREFIX_VEX_0F3897,
1183   PREFIX_VEX_0F3898,
1184   PREFIX_VEX_0F3899,
1185   PREFIX_VEX_0F389A,
1186   PREFIX_VEX_0F389B,
1187   PREFIX_VEX_0F389C,
1188   PREFIX_VEX_0F389D,
1189   PREFIX_VEX_0F389E,
1190   PREFIX_VEX_0F389F,
1191   PREFIX_VEX_0F38A6,
1192   PREFIX_VEX_0F38A7,
1193   PREFIX_VEX_0F38A8,
1194   PREFIX_VEX_0F38A9,
1195   PREFIX_VEX_0F38AA,
1196   PREFIX_VEX_0F38AB,
1197   PREFIX_VEX_0F38AC,
1198   PREFIX_VEX_0F38AD,
1199   PREFIX_VEX_0F38AE,
1200   PREFIX_VEX_0F38AF,
1201   PREFIX_VEX_0F38B6,
1202   PREFIX_VEX_0F38B7,
1203   PREFIX_VEX_0F38B8,
1204   PREFIX_VEX_0F38B9,
1205   PREFIX_VEX_0F38BA,
1206   PREFIX_VEX_0F38BB,
1207   PREFIX_VEX_0F38BC,
1208   PREFIX_VEX_0F38BD,
1209   PREFIX_VEX_0F38BE,
1210   PREFIX_VEX_0F38BF,
1211   PREFIX_VEX_0F38DB,
1212   PREFIX_VEX_0F38DC,
1213   PREFIX_VEX_0F38DD,
1214   PREFIX_VEX_0F38DE,
1215   PREFIX_VEX_0F38DF,
1216   PREFIX_VEX_0F38F2,
1217   PREFIX_VEX_0F38F3_REG_1,
1218   PREFIX_VEX_0F38F3_REG_2,
1219   PREFIX_VEX_0F38F3_REG_3,
1220   PREFIX_VEX_0F38F5,
1221   PREFIX_VEX_0F38F6,
1222   PREFIX_VEX_0F38F7,
1223   PREFIX_VEX_0F3A00,
1224   PREFIX_VEX_0F3A01,
1225   PREFIX_VEX_0F3A02,
1226   PREFIX_VEX_0F3A04,
1227   PREFIX_VEX_0F3A05,
1228   PREFIX_VEX_0F3A06,
1229   PREFIX_VEX_0F3A08,
1230   PREFIX_VEX_0F3A09,
1231   PREFIX_VEX_0F3A0A,
1232   PREFIX_VEX_0F3A0B,
1233   PREFIX_VEX_0F3A0C,
1234   PREFIX_VEX_0F3A0D,
1235   PREFIX_VEX_0F3A0E,
1236   PREFIX_VEX_0F3A0F,
1237   PREFIX_VEX_0F3A14,
1238   PREFIX_VEX_0F3A15,
1239   PREFIX_VEX_0F3A16,
1240   PREFIX_VEX_0F3A17,
1241   PREFIX_VEX_0F3A18,
1242   PREFIX_VEX_0F3A19,
1243   PREFIX_VEX_0F3A1D,
1244   PREFIX_VEX_0F3A20,
1245   PREFIX_VEX_0F3A21,
1246   PREFIX_VEX_0F3A22,
1247   PREFIX_VEX_0F3A30,
1248   PREFIX_VEX_0F3A31,
1249   PREFIX_VEX_0F3A32,
1250   PREFIX_VEX_0F3A33,
1251   PREFIX_VEX_0F3A38,
1252   PREFIX_VEX_0F3A39,
1253   PREFIX_VEX_0F3A40,
1254   PREFIX_VEX_0F3A41,
1255   PREFIX_VEX_0F3A42,
1256   PREFIX_VEX_0F3A44,
1257   PREFIX_VEX_0F3A46,
1258   PREFIX_VEX_0F3A48,
1259   PREFIX_VEX_0F3A49,
1260   PREFIX_VEX_0F3A4A,
1261   PREFIX_VEX_0F3A4B,
1262   PREFIX_VEX_0F3A4C,
1263   PREFIX_VEX_0F3A5C,
1264   PREFIX_VEX_0F3A5D,
1265   PREFIX_VEX_0F3A5E,
1266   PREFIX_VEX_0F3A5F,
1267   PREFIX_VEX_0F3A60,
1268   PREFIX_VEX_0F3A61,
1269   PREFIX_VEX_0F3A62,
1270   PREFIX_VEX_0F3A63,
1271   PREFIX_VEX_0F3A68,
1272   PREFIX_VEX_0F3A69,
1273   PREFIX_VEX_0F3A6A,
1274   PREFIX_VEX_0F3A6B,
1275   PREFIX_VEX_0F3A6C,
1276   PREFIX_VEX_0F3A6D,
1277   PREFIX_VEX_0F3A6E,
1278   PREFIX_VEX_0F3A6F,
1279   PREFIX_VEX_0F3A78,
1280   PREFIX_VEX_0F3A79,
1281   PREFIX_VEX_0F3A7A,
1282   PREFIX_VEX_0F3A7B,
1283   PREFIX_VEX_0F3A7C,
1284   PREFIX_VEX_0F3A7D,
1285   PREFIX_VEX_0F3A7E,
1286   PREFIX_VEX_0F3A7F,
1287   PREFIX_VEX_0F3ADF,
1288   PREFIX_VEX_0F3AF0,
1289
1290   PREFIX_EVEX_0F10,
1291   PREFIX_EVEX_0F11,
1292   PREFIX_EVEX_0F12,
1293   PREFIX_EVEX_0F13,
1294   PREFIX_EVEX_0F14,
1295   PREFIX_EVEX_0F15,
1296   PREFIX_EVEX_0F16,
1297   PREFIX_EVEX_0F17,
1298   PREFIX_EVEX_0F28,
1299   PREFIX_EVEX_0F29,
1300   PREFIX_EVEX_0F2A,
1301   PREFIX_EVEX_0F2B,
1302   PREFIX_EVEX_0F2C,
1303   PREFIX_EVEX_0F2D,
1304   PREFIX_EVEX_0F2E,
1305   PREFIX_EVEX_0F2F,
1306   PREFIX_EVEX_0F51,
1307   PREFIX_EVEX_0F54,
1308   PREFIX_EVEX_0F55,
1309   PREFIX_EVEX_0F56,
1310   PREFIX_EVEX_0F57,
1311   PREFIX_EVEX_0F58,
1312   PREFIX_EVEX_0F59,
1313   PREFIX_EVEX_0F5A,
1314   PREFIX_EVEX_0F5B,
1315   PREFIX_EVEX_0F5C,
1316   PREFIX_EVEX_0F5D,
1317   PREFIX_EVEX_0F5E,
1318   PREFIX_EVEX_0F5F,
1319   PREFIX_EVEX_0F60,
1320   PREFIX_EVEX_0F61,
1321   PREFIX_EVEX_0F62,
1322   PREFIX_EVEX_0F63,
1323   PREFIX_EVEX_0F64,
1324   PREFIX_EVEX_0F65,
1325   PREFIX_EVEX_0F66,
1326   PREFIX_EVEX_0F67,
1327   PREFIX_EVEX_0F68,
1328   PREFIX_EVEX_0F69,
1329   PREFIX_EVEX_0F6A,
1330   PREFIX_EVEX_0F6B,
1331   PREFIX_EVEX_0F6C,
1332   PREFIX_EVEX_0F6D,
1333   PREFIX_EVEX_0F6E,
1334   PREFIX_EVEX_0F6F,
1335   PREFIX_EVEX_0F70,
1336   PREFIX_EVEX_0F71_REG_2,
1337   PREFIX_EVEX_0F71_REG_4,
1338   PREFIX_EVEX_0F71_REG_6,
1339   PREFIX_EVEX_0F72_REG_0,
1340   PREFIX_EVEX_0F72_REG_1,
1341   PREFIX_EVEX_0F72_REG_2,
1342   PREFIX_EVEX_0F72_REG_4,
1343   PREFIX_EVEX_0F72_REG_6,
1344   PREFIX_EVEX_0F73_REG_2,
1345   PREFIX_EVEX_0F73_REG_3,
1346   PREFIX_EVEX_0F73_REG_6,
1347   PREFIX_EVEX_0F73_REG_7,
1348   PREFIX_EVEX_0F74,
1349   PREFIX_EVEX_0F75,
1350   PREFIX_EVEX_0F76,
1351   PREFIX_EVEX_0F78,
1352   PREFIX_EVEX_0F79,
1353   PREFIX_EVEX_0F7A,
1354   PREFIX_EVEX_0F7B,
1355   PREFIX_EVEX_0F7E,
1356   PREFIX_EVEX_0F7F,
1357   PREFIX_EVEX_0FC2,
1358   PREFIX_EVEX_0FC4,
1359   PREFIX_EVEX_0FC5,
1360   PREFIX_EVEX_0FC6,
1361   PREFIX_EVEX_0FD1,
1362   PREFIX_EVEX_0FD2,
1363   PREFIX_EVEX_0FD3,
1364   PREFIX_EVEX_0FD4,
1365   PREFIX_EVEX_0FD5,
1366   PREFIX_EVEX_0FD6,
1367   PREFIX_EVEX_0FD8,
1368   PREFIX_EVEX_0FD9,
1369   PREFIX_EVEX_0FDA,
1370   PREFIX_EVEX_0FDB,
1371   PREFIX_EVEX_0FDC,
1372   PREFIX_EVEX_0FDD,
1373   PREFIX_EVEX_0FDE,
1374   PREFIX_EVEX_0FDF,
1375   PREFIX_EVEX_0FE0,
1376   PREFIX_EVEX_0FE1,
1377   PREFIX_EVEX_0FE2,
1378   PREFIX_EVEX_0FE3,
1379   PREFIX_EVEX_0FE4,
1380   PREFIX_EVEX_0FE5,
1381   PREFIX_EVEX_0FE6,
1382   PREFIX_EVEX_0FE7,
1383   PREFIX_EVEX_0FE8,
1384   PREFIX_EVEX_0FE9,
1385   PREFIX_EVEX_0FEA,
1386   PREFIX_EVEX_0FEB,
1387   PREFIX_EVEX_0FEC,
1388   PREFIX_EVEX_0FED,
1389   PREFIX_EVEX_0FEE,
1390   PREFIX_EVEX_0FEF,
1391   PREFIX_EVEX_0FF1,
1392   PREFIX_EVEX_0FF2,
1393   PREFIX_EVEX_0FF3,
1394   PREFIX_EVEX_0FF4,
1395   PREFIX_EVEX_0FF5,
1396   PREFIX_EVEX_0FF6,
1397   PREFIX_EVEX_0FF8,
1398   PREFIX_EVEX_0FF9,
1399   PREFIX_EVEX_0FFA,
1400   PREFIX_EVEX_0FFB,
1401   PREFIX_EVEX_0FFC,
1402   PREFIX_EVEX_0FFD,
1403   PREFIX_EVEX_0FFE,
1404   PREFIX_EVEX_0F3800,
1405   PREFIX_EVEX_0F3804,
1406   PREFIX_EVEX_0F380B,
1407   PREFIX_EVEX_0F380C,
1408   PREFIX_EVEX_0F380D,
1409   PREFIX_EVEX_0F3810,
1410   PREFIX_EVEX_0F3811,
1411   PREFIX_EVEX_0F3812,
1412   PREFIX_EVEX_0F3813,
1413   PREFIX_EVEX_0F3814,
1414   PREFIX_EVEX_0F3815,
1415   PREFIX_EVEX_0F3816,
1416   PREFIX_EVEX_0F3818,
1417   PREFIX_EVEX_0F3819,
1418   PREFIX_EVEX_0F381A,
1419   PREFIX_EVEX_0F381B,
1420   PREFIX_EVEX_0F381C,
1421   PREFIX_EVEX_0F381D,
1422   PREFIX_EVEX_0F381E,
1423   PREFIX_EVEX_0F381F,
1424   PREFIX_EVEX_0F3820,
1425   PREFIX_EVEX_0F3821,
1426   PREFIX_EVEX_0F3822,
1427   PREFIX_EVEX_0F3823,
1428   PREFIX_EVEX_0F3824,
1429   PREFIX_EVEX_0F3825,
1430   PREFIX_EVEX_0F3826,
1431   PREFIX_EVEX_0F3827,
1432   PREFIX_EVEX_0F3828,
1433   PREFIX_EVEX_0F3829,
1434   PREFIX_EVEX_0F382A,
1435   PREFIX_EVEX_0F382B,
1436   PREFIX_EVEX_0F382C,
1437   PREFIX_EVEX_0F382D,
1438   PREFIX_EVEX_0F3830,
1439   PREFIX_EVEX_0F3831,
1440   PREFIX_EVEX_0F3832,
1441   PREFIX_EVEX_0F3833,
1442   PREFIX_EVEX_0F3834,
1443   PREFIX_EVEX_0F3835,
1444   PREFIX_EVEX_0F3836,
1445   PREFIX_EVEX_0F3837,
1446   PREFIX_EVEX_0F3838,
1447   PREFIX_EVEX_0F3839,
1448   PREFIX_EVEX_0F383A,
1449   PREFIX_EVEX_0F383B,
1450   PREFIX_EVEX_0F383C,
1451   PREFIX_EVEX_0F383D,
1452   PREFIX_EVEX_0F383E,
1453   PREFIX_EVEX_0F383F,
1454   PREFIX_EVEX_0F3840,
1455   PREFIX_EVEX_0F3842,
1456   PREFIX_EVEX_0F3843,
1457   PREFIX_EVEX_0F3844,
1458   PREFIX_EVEX_0F3845,
1459   PREFIX_EVEX_0F3846,
1460   PREFIX_EVEX_0F3847,
1461   PREFIX_EVEX_0F384C,
1462   PREFIX_EVEX_0F384D,
1463   PREFIX_EVEX_0F384E,
1464   PREFIX_EVEX_0F384F,
1465   PREFIX_EVEX_0F3858,
1466   PREFIX_EVEX_0F3859,
1467   PREFIX_EVEX_0F385A,
1468   PREFIX_EVEX_0F385B,
1469   PREFIX_EVEX_0F3864,
1470   PREFIX_EVEX_0F3865,
1471   PREFIX_EVEX_0F3866,
1472   PREFIX_EVEX_0F3875,
1473   PREFIX_EVEX_0F3876,
1474   PREFIX_EVEX_0F3877,
1475   PREFIX_EVEX_0F3878,
1476   PREFIX_EVEX_0F3879,
1477   PREFIX_EVEX_0F387A,
1478   PREFIX_EVEX_0F387B,
1479   PREFIX_EVEX_0F387C,
1480   PREFIX_EVEX_0F387D,
1481   PREFIX_EVEX_0F387E,
1482   PREFIX_EVEX_0F387F,
1483   PREFIX_EVEX_0F3888,
1484   PREFIX_EVEX_0F3889,
1485   PREFIX_EVEX_0F388A,
1486   PREFIX_EVEX_0F388B,
1487   PREFIX_EVEX_0F388D,
1488   PREFIX_EVEX_0F3890,
1489   PREFIX_EVEX_0F3891,
1490   PREFIX_EVEX_0F3892,
1491   PREFIX_EVEX_0F3893,
1492   PREFIX_EVEX_0F3896,
1493   PREFIX_EVEX_0F3897,
1494   PREFIX_EVEX_0F3898,
1495   PREFIX_EVEX_0F3899,
1496   PREFIX_EVEX_0F389A,
1497   PREFIX_EVEX_0F389B,
1498   PREFIX_EVEX_0F389C,
1499   PREFIX_EVEX_0F389D,
1500   PREFIX_EVEX_0F389E,
1501   PREFIX_EVEX_0F389F,
1502   PREFIX_EVEX_0F38A0,
1503   PREFIX_EVEX_0F38A1,
1504   PREFIX_EVEX_0F38A2,
1505   PREFIX_EVEX_0F38A3,
1506   PREFIX_EVEX_0F38A6,
1507   PREFIX_EVEX_0F38A7,
1508   PREFIX_EVEX_0F38A8,
1509   PREFIX_EVEX_0F38A9,
1510   PREFIX_EVEX_0F38AA,
1511   PREFIX_EVEX_0F38AB,
1512   PREFIX_EVEX_0F38AC,
1513   PREFIX_EVEX_0F38AD,
1514   PREFIX_EVEX_0F38AE,
1515   PREFIX_EVEX_0F38AF,
1516   PREFIX_EVEX_0F38B6,
1517   PREFIX_EVEX_0F38B7,
1518   PREFIX_EVEX_0F38B8,
1519   PREFIX_EVEX_0F38B9,
1520   PREFIX_EVEX_0F38BA,
1521   PREFIX_EVEX_0F38BB,
1522   PREFIX_EVEX_0F38BC,
1523   PREFIX_EVEX_0F38BD,
1524   PREFIX_EVEX_0F38BE,
1525   PREFIX_EVEX_0F38BF,
1526   PREFIX_EVEX_0F38C4,
1527   PREFIX_EVEX_0F38C6_REG_1,
1528   PREFIX_EVEX_0F38C6_REG_2,
1529   PREFIX_EVEX_0F38C6_REG_5,
1530   PREFIX_EVEX_0F38C6_REG_6,
1531   PREFIX_EVEX_0F38C7_REG_1,
1532   PREFIX_EVEX_0F38C7_REG_2,
1533   PREFIX_EVEX_0F38C7_REG_5,
1534   PREFIX_EVEX_0F38C7_REG_6,
1535   PREFIX_EVEX_0F38C8,
1536   PREFIX_EVEX_0F38CA,
1537   PREFIX_EVEX_0F38CB,
1538   PREFIX_EVEX_0F38CC,
1539   PREFIX_EVEX_0F38CD,
1540
1541   PREFIX_EVEX_0F3A00,
1542   PREFIX_EVEX_0F3A01,
1543   PREFIX_EVEX_0F3A03,
1544   PREFIX_EVEX_0F3A04,
1545   PREFIX_EVEX_0F3A05,
1546   PREFIX_EVEX_0F3A08,
1547   PREFIX_EVEX_0F3A09,
1548   PREFIX_EVEX_0F3A0A,
1549   PREFIX_EVEX_0F3A0B,
1550   PREFIX_EVEX_0F3A0F,
1551   PREFIX_EVEX_0F3A14,
1552   PREFIX_EVEX_0F3A15,
1553   PREFIX_EVEX_0F3A16,
1554   PREFIX_EVEX_0F3A17,
1555   PREFIX_EVEX_0F3A18,
1556   PREFIX_EVEX_0F3A19,
1557   PREFIX_EVEX_0F3A1A,
1558   PREFIX_EVEX_0F3A1B,
1559   PREFIX_EVEX_0F3A1D,
1560   PREFIX_EVEX_0F3A1E,
1561   PREFIX_EVEX_0F3A1F,
1562   PREFIX_EVEX_0F3A20,
1563   PREFIX_EVEX_0F3A21,
1564   PREFIX_EVEX_0F3A22,
1565   PREFIX_EVEX_0F3A23,
1566   PREFIX_EVEX_0F3A25,
1567   PREFIX_EVEX_0F3A26,
1568   PREFIX_EVEX_0F3A27,
1569   PREFIX_EVEX_0F3A38,
1570   PREFIX_EVEX_0F3A39,
1571   PREFIX_EVEX_0F3A3A,
1572   PREFIX_EVEX_0F3A3B,
1573   PREFIX_EVEX_0F3A3E,
1574   PREFIX_EVEX_0F3A3F,
1575   PREFIX_EVEX_0F3A42,
1576   PREFIX_EVEX_0F3A43,
1577   PREFIX_EVEX_0F3A50,
1578   PREFIX_EVEX_0F3A51,
1579   PREFIX_EVEX_0F3A54,
1580   PREFIX_EVEX_0F3A55,
1581   PREFIX_EVEX_0F3A56,
1582   PREFIX_EVEX_0F3A57,
1583   PREFIX_EVEX_0F3A66,
1584   PREFIX_EVEX_0F3A67
1585 };
1586
1587 enum
1588 {
1589   X86_64_06 = 0,
1590   X86_64_07,
1591   X86_64_0D,
1592   X86_64_16,
1593   X86_64_17,
1594   X86_64_1E,
1595   X86_64_1F,
1596   X86_64_27,
1597   X86_64_2F,
1598   X86_64_37,
1599   X86_64_3F,
1600   X86_64_60,
1601   X86_64_61,
1602   X86_64_62,
1603   X86_64_63,
1604   X86_64_6D,
1605   X86_64_6F,
1606   X86_64_9A,
1607   X86_64_C4,
1608   X86_64_C5,
1609   X86_64_CE,
1610   X86_64_D4,
1611   X86_64_D5,
1612   X86_64_EA,
1613   X86_64_0F01_REG_0,
1614   X86_64_0F01_REG_1,
1615   X86_64_0F01_REG_2,
1616   X86_64_0F01_REG_3
1617 };
1618
1619 enum
1620 {
1621   THREE_BYTE_0F38 = 0,
1622   THREE_BYTE_0F3A,
1623   THREE_BYTE_0F7A
1624 };
1625
1626 enum
1627 {
1628   XOP_08 = 0,
1629   XOP_09,
1630   XOP_0A
1631 };
1632
1633 enum
1634 {
1635   VEX_0F = 0,
1636   VEX_0F38,
1637   VEX_0F3A
1638 };
1639
1640 enum
1641 {
1642   EVEX_0F = 0,
1643   EVEX_0F38,
1644   EVEX_0F3A
1645 };
1646
1647 enum
1648 {
1649   VEX_LEN_0F10_P_1 = 0,
1650   VEX_LEN_0F10_P_3,
1651   VEX_LEN_0F11_P_1,
1652   VEX_LEN_0F11_P_3,
1653   VEX_LEN_0F12_P_0_M_0,
1654   VEX_LEN_0F12_P_0_M_1,
1655   VEX_LEN_0F12_P_2,
1656   VEX_LEN_0F13_M_0,
1657   VEX_LEN_0F16_P_0_M_0,
1658   VEX_LEN_0F16_P_0_M_1,
1659   VEX_LEN_0F16_P_2,
1660   VEX_LEN_0F17_M_0,
1661   VEX_LEN_0F2A_P_1,
1662   VEX_LEN_0F2A_P_3,
1663   VEX_LEN_0F2C_P_1,
1664   VEX_LEN_0F2C_P_3,
1665   VEX_LEN_0F2D_P_1,
1666   VEX_LEN_0F2D_P_3,
1667   VEX_LEN_0F2E_P_0,
1668   VEX_LEN_0F2E_P_2,
1669   VEX_LEN_0F2F_P_0,
1670   VEX_LEN_0F2F_P_2,
1671   VEX_LEN_0F41_P_0,
1672   VEX_LEN_0F41_P_2,
1673   VEX_LEN_0F42_P_0,
1674   VEX_LEN_0F42_P_2,
1675   VEX_LEN_0F44_P_0,
1676   VEX_LEN_0F44_P_2,
1677   VEX_LEN_0F45_P_0,
1678   VEX_LEN_0F45_P_2,
1679   VEX_LEN_0F46_P_0,
1680   VEX_LEN_0F46_P_2,
1681   VEX_LEN_0F47_P_0,
1682   VEX_LEN_0F47_P_2,
1683   VEX_LEN_0F4A_P_0,
1684   VEX_LEN_0F4A_P_2,
1685   VEX_LEN_0F4B_P_0,
1686   VEX_LEN_0F4B_P_2,
1687   VEX_LEN_0F51_P_1,
1688   VEX_LEN_0F51_P_3,
1689   VEX_LEN_0F52_P_1,
1690   VEX_LEN_0F53_P_1,
1691   VEX_LEN_0F58_P_1,
1692   VEX_LEN_0F58_P_3,
1693   VEX_LEN_0F59_P_1,
1694   VEX_LEN_0F59_P_3,
1695   VEX_LEN_0F5A_P_1,
1696   VEX_LEN_0F5A_P_3,
1697   VEX_LEN_0F5C_P_1,
1698   VEX_LEN_0F5C_P_3,
1699   VEX_LEN_0F5D_P_1,
1700   VEX_LEN_0F5D_P_3,
1701   VEX_LEN_0F5E_P_1,
1702   VEX_LEN_0F5E_P_3,
1703   VEX_LEN_0F5F_P_1,
1704   VEX_LEN_0F5F_P_3,
1705   VEX_LEN_0F6E_P_2,
1706   VEX_LEN_0F7E_P_1,
1707   VEX_LEN_0F7E_P_2,
1708   VEX_LEN_0F90_P_0,
1709   VEX_LEN_0F90_P_2,
1710   VEX_LEN_0F91_P_0,
1711   VEX_LEN_0F91_P_2,
1712   VEX_LEN_0F92_P_0,
1713   VEX_LEN_0F92_P_2,
1714   VEX_LEN_0F92_P_3,
1715   VEX_LEN_0F93_P_0,
1716   VEX_LEN_0F93_P_2,
1717   VEX_LEN_0F93_P_3,
1718   VEX_LEN_0F98_P_0,
1719   VEX_LEN_0F98_P_2,
1720   VEX_LEN_0F99_P_0,
1721   VEX_LEN_0F99_P_2,
1722   VEX_LEN_0FAE_R_2_M_0,
1723   VEX_LEN_0FAE_R_3_M_0,
1724   VEX_LEN_0FC2_P_1,
1725   VEX_LEN_0FC2_P_3,
1726   VEX_LEN_0FC4_P_2,
1727   VEX_LEN_0FC5_P_2,
1728   VEX_LEN_0FD6_P_2,
1729   VEX_LEN_0FF7_P_2,
1730   VEX_LEN_0F3816_P_2,
1731   VEX_LEN_0F3819_P_2,
1732   VEX_LEN_0F381A_P_2_M_0,
1733   VEX_LEN_0F3836_P_2,
1734   VEX_LEN_0F3841_P_2,
1735   VEX_LEN_0F385A_P_2_M_0,
1736   VEX_LEN_0F38DB_P_2,
1737   VEX_LEN_0F38DC_P_2,
1738   VEX_LEN_0F38DD_P_2,
1739   VEX_LEN_0F38DE_P_2,
1740   VEX_LEN_0F38DF_P_2,
1741   VEX_LEN_0F38F2_P_0,
1742   VEX_LEN_0F38F3_R_1_P_0,
1743   VEX_LEN_0F38F3_R_2_P_0,
1744   VEX_LEN_0F38F3_R_3_P_0,
1745   VEX_LEN_0F38F5_P_0,
1746   VEX_LEN_0F38F5_P_1,
1747   VEX_LEN_0F38F5_P_3,
1748   VEX_LEN_0F38F6_P_3,
1749   VEX_LEN_0F38F7_P_0,
1750   VEX_LEN_0F38F7_P_1,
1751   VEX_LEN_0F38F7_P_2,
1752   VEX_LEN_0F38F7_P_3,
1753   VEX_LEN_0F3A00_P_2,
1754   VEX_LEN_0F3A01_P_2,
1755   VEX_LEN_0F3A06_P_2,
1756   VEX_LEN_0F3A0A_P_2,
1757   VEX_LEN_0F3A0B_P_2,
1758   VEX_LEN_0F3A14_P_2,
1759   VEX_LEN_0F3A15_P_2,
1760   VEX_LEN_0F3A16_P_2,
1761   VEX_LEN_0F3A17_P_2,
1762   VEX_LEN_0F3A18_P_2,
1763   VEX_LEN_0F3A19_P_2,
1764   VEX_LEN_0F3A20_P_2,
1765   VEX_LEN_0F3A21_P_2,
1766   VEX_LEN_0F3A22_P_2,
1767   VEX_LEN_0F3A30_P_2,
1768   VEX_LEN_0F3A31_P_2,
1769   VEX_LEN_0F3A32_P_2,
1770   VEX_LEN_0F3A33_P_2,
1771   VEX_LEN_0F3A38_P_2,
1772   VEX_LEN_0F3A39_P_2,
1773   VEX_LEN_0F3A41_P_2,
1774   VEX_LEN_0F3A44_P_2,
1775   VEX_LEN_0F3A46_P_2,
1776   VEX_LEN_0F3A60_P_2,
1777   VEX_LEN_0F3A61_P_2,
1778   VEX_LEN_0F3A62_P_2,
1779   VEX_LEN_0F3A63_P_2,
1780   VEX_LEN_0F3A6A_P_2,
1781   VEX_LEN_0F3A6B_P_2,
1782   VEX_LEN_0F3A6E_P_2,
1783   VEX_LEN_0F3A6F_P_2,
1784   VEX_LEN_0F3A7A_P_2,
1785   VEX_LEN_0F3A7B_P_2,
1786   VEX_LEN_0F3A7E_P_2,
1787   VEX_LEN_0F3A7F_P_2,
1788   VEX_LEN_0F3ADF_P_2,
1789   VEX_LEN_0F3AF0_P_3,
1790   VEX_LEN_0FXOP_08_CC,
1791   VEX_LEN_0FXOP_08_CD,
1792   VEX_LEN_0FXOP_08_CE,
1793   VEX_LEN_0FXOP_08_CF,
1794   VEX_LEN_0FXOP_08_EC,
1795   VEX_LEN_0FXOP_08_ED,
1796   VEX_LEN_0FXOP_08_EE,
1797   VEX_LEN_0FXOP_08_EF,
1798   VEX_LEN_0FXOP_09_80,
1799   VEX_LEN_0FXOP_09_81
1800 };
1801
1802 enum
1803 {
1804   VEX_W_0F10_P_0 = 0,
1805   VEX_W_0F10_P_1,
1806   VEX_W_0F10_P_2,
1807   VEX_W_0F10_P_3,
1808   VEX_W_0F11_P_0,
1809   VEX_W_0F11_P_1,
1810   VEX_W_0F11_P_2,
1811   VEX_W_0F11_P_3,
1812   VEX_W_0F12_P_0_M_0,
1813   VEX_W_0F12_P_0_M_1,
1814   VEX_W_0F12_P_1,
1815   VEX_W_0F12_P_2,
1816   VEX_W_0F12_P_3,
1817   VEX_W_0F13_M_0,
1818   VEX_W_0F14,
1819   VEX_W_0F15,
1820   VEX_W_0F16_P_0_M_0,
1821   VEX_W_0F16_P_0_M_1,
1822   VEX_W_0F16_P_1,
1823   VEX_W_0F16_P_2,
1824   VEX_W_0F17_M_0,
1825   VEX_W_0F28,
1826   VEX_W_0F29,
1827   VEX_W_0F2B_M_0,
1828   VEX_W_0F2E_P_0,
1829   VEX_W_0F2E_P_2,
1830   VEX_W_0F2F_P_0,
1831   VEX_W_0F2F_P_2,
1832   VEX_W_0F41_P_0_LEN_1,
1833   VEX_W_0F41_P_2_LEN_1,
1834   VEX_W_0F42_P_0_LEN_1,
1835   VEX_W_0F42_P_2_LEN_1,
1836   VEX_W_0F44_P_0_LEN_0,
1837   VEX_W_0F44_P_2_LEN_0,
1838   VEX_W_0F45_P_0_LEN_1,
1839   VEX_W_0F45_P_2_LEN_1,
1840   VEX_W_0F46_P_0_LEN_1,
1841   VEX_W_0F46_P_2_LEN_1,
1842   VEX_W_0F47_P_0_LEN_1,
1843   VEX_W_0F47_P_2_LEN_1,
1844   VEX_W_0F4A_P_0_LEN_1,
1845   VEX_W_0F4A_P_2_LEN_1,
1846   VEX_W_0F4B_P_0_LEN_1,
1847   VEX_W_0F4B_P_2_LEN_1,
1848   VEX_W_0F50_M_0,
1849   VEX_W_0F51_P_0,
1850   VEX_W_0F51_P_1,
1851   VEX_W_0F51_P_2,
1852   VEX_W_0F51_P_3,
1853   VEX_W_0F52_P_0,
1854   VEX_W_0F52_P_1,
1855   VEX_W_0F53_P_0,
1856   VEX_W_0F53_P_1,
1857   VEX_W_0F58_P_0,
1858   VEX_W_0F58_P_1,
1859   VEX_W_0F58_P_2,
1860   VEX_W_0F58_P_3,
1861   VEX_W_0F59_P_0,
1862   VEX_W_0F59_P_1,
1863   VEX_W_0F59_P_2,
1864   VEX_W_0F59_P_3,
1865   VEX_W_0F5A_P_0,
1866   VEX_W_0F5A_P_1,
1867   VEX_W_0F5A_P_3,
1868   VEX_W_0F5B_P_0,
1869   VEX_W_0F5B_P_1,
1870   VEX_W_0F5B_P_2,
1871   VEX_W_0F5C_P_0,
1872   VEX_W_0F5C_P_1,
1873   VEX_W_0F5C_P_2,
1874   VEX_W_0F5C_P_3,
1875   VEX_W_0F5D_P_0,
1876   VEX_W_0F5D_P_1,
1877   VEX_W_0F5D_P_2,
1878   VEX_W_0F5D_P_3,
1879   VEX_W_0F5E_P_0,
1880   VEX_W_0F5E_P_1,
1881   VEX_W_0F5E_P_2,
1882   VEX_W_0F5E_P_3,
1883   VEX_W_0F5F_P_0,
1884   VEX_W_0F5F_P_1,
1885   VEX_W_0F5F_P_2,
1886   VEX_W_0F5F_P_3,
1887   VEX_W_0F60_P_2,
1888   VEX_W_0F61_P_2,
1889   VEX_W_0F62_P_2,
1890   VEX_W_0F63_P_2,
1891   VEX_W_0F64_P_2,
1892   VEX_W_0F65_P_2,
1893   VEX_W_0F66_P_2,
1894   VEX_W_0F67_P_2,
1895   VEX_W_0F68_P_2,
1896   VEX_W_0F69_P_2,
1897   VEX_W_0F6A_P_2,
1898   VEX_W_0F6B_P_2,
1899   VEX_W_0F6C_P_2,
1900   VEX_W_0F6D_P_2,
1901   VEX_W_0F6F_P_1,
1902   VEX_W_0F6F_P_2,
1903   VEX_W_0F70_P_1,
1904   VEX_W_0F70_P_2,
1905   VEX_W_0F70_P_3,
1906   VEX_W_0F71_R_2_P_2,
1907   VEX_W_0F71_R_4_P_2,
1908   VEX_W_0F71_R_6_P_2,
1909   VEX_W_0F72_R_2_P_2,
1910   VEX_W_0F72_R_4_P_2,
1911   VEX_W_0F72_R_6_P_2,
1912   VEX_W_0F73_R_2_P_2,
1913   VEX_W_0F73_R_3_P_2,
1914   VEX_W_0F73_R_6_P_2,
1915   VEX_W_0F73_R_7_P_2,
1916   VEX_W_0F74_P_2,
1917   VEX_W_0F75_P_2,
1918   VEX_W_0F76_P_2,
1919   VEX_W_0F77_P_0,
1920   VEX_W_0F7C_P_2,
1921   VEX_W_0F7C_P_3,
1922   VEX_W_0F7D_P_2,
1923   VEX_W_0F7D_P_3,
1924   VEX_W_0F7E_P_1,
1925   VEX_W_0F7F_P_1,
1926   VEX_W_0F7F_P_2,
1927   VEX_W_0F90_P_0_LEN_0,
1928   VEX_W_0F90_P_2_LEN_0,
1929   VEX_W_0F91_P_0_LEN_0,
1930   VEX_W_0F91_P_2_LEN_0,
1931   VEX_W_0F92_P_0_LEN_0,
1932   VEX_W_0F92_P_2_LEN_0,
1933   VEX_W_0F92_P_3_LEN_0,
1934   VEX_W_0F93_P_0_LEN_0,
1935   VEX_W_0F93_P_2_LEN_0,
1936   VEX_W_0F93_P_3_LEN_0,
1937   VEX_W_0F98_P_0_LEN_0,
1938   VEX_W_0F98_P_2_LEN_0,
1939   VEX_W_0F99_P_0_LEN_0,
1940   VEX_W_0F99_P_2_LEN_0,
1941   VEX_W_0FAE_R_2_M_0,
1942   VEX_W_0FAE_R_3_M_0,
1943   VEX_W_0FC2_P_0,
1944   VEX_W_0FC2_P_1,
1945   VEX_W_0FC2_P_2,
1946   VEX_W_0FC2_P_3,
1947   VEX_W_0FC4_P_2,
1948   VEX_W_0FC5_P_2,
1949   VEX_W_0FD0_P_2,
1950   VEX_W_0FD0_P_3,
1951   VEX_W_0FD1_P_2,
1952   VEX_W_0FD2_P_2,
1953   VEX_W_0FD3_P_2,
1954   VEX_W_0FD4_P_2,
1955   VEX_W_0FD5_P_2,
1956   VEX_W_0FD6_P_2,
1957   VEX_W_0FD7_P_2_M_1,
1958   VEX_W_0FD8_P_2,
1959   VEX_W_0FD9_P_2,
1960   VEX_W_0FDA_P_2,
1961   VEX_W_0FDB_P_2,
1962   VEX_W_0FDC_P_2,
1963   VEX_W_0FDD_P_2,
1964   VEX_W_0FDE_P_2,
1965   VEX_W_0FDF_P_2,
1966   VEX_W_0FE0_P_2,
1967   VEX_W_0FE1_P_2,
1968   VEX_W_0FE2_P_2,
1969   VEX_W_0FE3_P_2,
1970   VEX_W_0FE4_P_2,
1971   VEX_W_0FE5_P_2,
1972   VEX_W_0FE6_P_1,
1973   VEX_W_0FE6_P_2,
1974   VEX_W_0FE6_P_3,
1975   VEX_W_0FE7_P_2_M_0,
1976   VEX_W_0FE8_P_2,
1977   VEX_W_0FE9_P_2,
1978   VEX_W_0FEA_P_2,
1979   VEX_W_0FEB_P_2,
1980   VEX_W_0FEC_P_2,
1981   VEX_W_0FED_P_2,
1982   VEX_W_0FEE_P_2,
1983   VEX_W_0FEF_P_2,
1984   VEX_W_0FF0_P_3_M_0,
1985   VEX_W_0FF1_P_2,
1986   VEX_W_0FF2_P_2,
1987   VEX_W_0FF3_P_2,
1988   VEX_W_0FF4_P_2,
1989   VEX_W_0FF5_P_2,
1990   VEX_W_0FF6_P_2,
1991   VEX_W_0FF7_P_2,
1992   VEX_W_0FF8_P_2,
1993   VEX_W_0FF9_P_2,
1994   VEX_W_0FFA_P_2,
1995   VEX_W_0FFB_P_2,
1996   VEX_W_0FFC_P_2,
1997   VEX_W_0FFD_P_2,
1998   VEX_W_0FFE_P_2,
1999   VEX_W_0F3800_P_2,
2000   VEX_W_0F3801_P_2,
2001   VEX_W_0F3802_P_2,
2002   VEX_W_0F3803_P_2,
2003   VEX_W_0F3804_P_2,
2004   VEX_W_0F3805_P_2,
2005   VEX_W_0F3806_P_2,
2006   VEX_W_0F3807_P_2,
2007   VEX_W_0F3808_P_2,
2008   VEX_W_0F3809_P_2,
2009   VEX_W_0F380A_P_2,
2010   VEX_W_0F380B_P_2,
2011   VEX_W_0F380C_P_2,
2012   VEX_W_0F380D_P_2,
2013   VEX_W_0F380E_P_2,
2014   VEX_W_0F380F_P_2,
2015   VEX_W_0F3816_P_2,
2016   VEX_W_0F3817_P_2,
2017   VEX_W_0F3818_P_2,
2018   VEX_W_0F3819_P_2,
2019   VEX_W_0F381A_P_2_M_0,
2020   VEX_W_0F381C_P_2,
2021   VEX_W_0F381D_P_2,
2022   VEX_W_0F381E_P_2,
2023   VEX_W_0F3820_P_2,
2024   VEX_W_0F3821_P_2,
2025   VEX_W_0F3822_P_2,
2026   VEX_W_0F3823_P_2,
2027   VEX_W_0F3824_P_2,
2028   VEX_W_0F3825_P_2,
2029   VEX_W_0F3828_P_2,
2030   VEX_W_0F3829_P_2,
2031   VEX_W_0F382A_P_2_M_0,
2032   VEX_W_0F382B_P_2,
2033   VEX_W_0F382C_P_2_M_0,
2034   VEX_W_0F382D_P_2_M_0,
2035   VEX_W_0F382E_P_2_M_0,
2036   VEX_W_0F382F_P_2_M_0,
2037   VEX_W_0F3830_P_2,
2038   VEX_W_0F3831_P_2,
2039   VEX_W_0F3832_P_2,
2040   VEX_W_0F3833_P_2,
2041   VEX_W_0F3834_P_2,
2042   VEX_W_0F3835_P_2,
2043   VEX_W_0F3836_P_2,
2044   VEX_W_0F3837_P_2,
2045   VEX_W_0F3838_P_2,
2046   VEX_W_0F3839_P_2,
2047   VEX_W_0F383A_P_2,
2048   VEX_W_0F383B_P_2,
2049   VEX_W_0F383C_P_2,
2050   VEX_W_0F383D_P_2,
2051   VEX_W_0F383E_P_2,
2052   VEX_W_0F383F_P_2,
2053   VEX_W_0F3840_P_2,
2054   VEX_W_0F3841_P_2,
2055   VEX_W_0F3846_P_2,
2056   VEX_W_0F3858_P_2,
2057   VEX_W_0F3859_P_2,
2058   VEX_W_0F385A_P_2_M_0,
2059   VEX_W_0F3878_P_2,
2060   VEX_W_0F3879_P_2,
2061   VEX_W_0F38DB_P_2,
2062   VEX_W_0F38DC_P_2,
2063   VEX_W_0F38DD_P_2,
2064   VEX_W_0F38DE_P_2,
2065   VEX_W_0F38DF_P_2,
2066   VEX_W_0F3A00_P_2,
2067   VEX_W_0F3A01_P_2,
2068   VEX_W_0F3A02_P_2,
2069   VEX_W_0F3A04_P_2,
2070   VEX_W_0F3A05_P_2,
2071   VEX_W_0F3A06_P_2,
2072   VEX_W_0F3A08_P_2,
2073   VEX_W_0F3A09_P_2,
2074   VEX_W_0F3A0A_P_2,
2075   VEX_W_0F3A0B_P_2,
2076   VEX_W_0F3A0C_P_2,
2077   VEX_W_0F3A0D_P_2,
2078   VEX_W_0F3A0E_P_2,
2079   VEX_W_0F3A0F_P_2,
2080   VEX_W_0F3A14_P_2,
2081   VEX_W_0F3A15_P_2,
2082   VEX_W_0F3A18_P_2,
2083   VEX_W_0F3A19_P_2,
2084   VEX_W_0F3A20_P_2,
2085   VEX_W_0F3A21_P_2,
2086   VEX_W_0F3A30_P_2_LEN_0,
2087   VEX_W_0F3A31_P_2_LEN_0,
2088   VEX_W_0F3A32_P_2_LEN_0,
2089   VEX_W_0F3A33_P_2_LEN_0,
2090   VEX_W_0F3A38_P_2,
2091   VEX_W_0F3A39_P_2,
2092   VEX_W_0F3A40_P_2,
2093   VEX_W_0F3A41_P_2,
2094   VEX_W_0F3A42_P_2,
2095   VEX_W_0F3A44_P_2,
2096   VEX_W_0F3A46_P_2,
2097   VEX_W_0F3A48_P_2,
2098   VEX_W_0F3A49_P_2,
2099   VEX_W_0F3A4A_P_2,
2100   VEX_W_0F3A4B_P_2,
2101   VEX_W_0F3A4C_P_2,
2102   VEX_W_0F3A60_P_2,
2103   VEX_W_0F3A61_P_2,
2104   VEX_W_0F3A62_P_2,
2105   VEX_W_0F3A63_P_2,
2106   VEX_W_0F3ADF_P_2,
2107
2108   EVEX_W_0F10_P_0,
2109   EVEX_W_0F10_P_1_M_0,
2110   EVEX_W_0F10_P_1_M_1,
2111   EVEX_W_0F10_P_2,
2112   EVEX_W_0F10_P_3_M_0,
2113   EVEX_W_0F10_P_3_M_1,
2114   EVEX_W_0F11_P_0,
2115   EVEX_W_0F11_P_1_M_0,
2116   EVEX_W_0F11_P_1_M_1,
2117   EVEX_W_0F11_P_2,
2118   EVEX_W_0F11_P_3_M_0,
2119   EVEX_W_0F11_P_3_M_1,
2120   EVEX_W_0F12_P_0_M_0,
2121   EVEX_W_0F12_P_0_M_1,
2122   EVEX_W_0F12_P_1,
2123   EVEX_W_0F12_P_2,
2124   EVEX_W_0F12_P_3,
2125   EVEX_W_0F13_P_0,
2126   EVEX_W_0F13_P_2,
2127   EVEX_W_0F14_P_0,
2128   EVEX_W_0F14_P_2,
2129   EVEX_W_0F15_P_0,
2130   EVEX_W_0F15_P_2,
2131   EVEX_W_0F16_P_0_M_0,
2132   EVEX_W_0F16_P_0_M_1,
2133   EVEX_W_0F16_P_1,
2134   EVEX_W_0F16_P_2,
2135   EVEX_W_0F17_P_0,
2136   EVEX_W_0F17_P_2,
2137   EVEX_W_0F28_P_0,
2138   EVEX_W_0F28_P_2,
2139   EVEX_W_0F29_P_0,
2140   EVEX_W_0F29_P_2,
2141   EVEX_W_0F2A_P_1,
2142   EVEX_W_0F2A_P_3,
2143   EVEX_W_0F2B_P_0,
2144   EVEX_W_0F2B_P_2,
2145   EVEX_W_0F2E_P_0,
2146   EVEX_W_0F2E_P_2,
2147   EVEX_W_0F2F_P_0,
2148   EVEX_W_0F2F_P_2,
2149   EVEX_W_0F51_P_0,
2150   EVEX_W_0F51_P_1,
2151   EVEX_W_0F51_P_2,
2152   EVEX_W_0F51_P_3,
2153   EVEX_W_0F54_P_0,
2154   EVEX_W_0F54_P_2,
2155   EVEX_W_0F55_P_0,
2156   EVEX_W_0F55_P_2,
2157   EVEX_W_0F56_P_0,
2158   EVEX_W_0F56_P_2,
2159   EVEX_W_0F57_P_0,
2160   EVEX_W_0F57_P_2,
2161   EVEX_W_0F58_P_0,
2162   EVEX_W_0F58_P_1,
2163   EVEX_W_0F58_P_2,
2164   EVEX_W_0F58_P_3,
2165   EVEX_W_0F59_P_0,
2166   EVEX_W_0F59_P_1,
2167   EVEX_W_0F59_P_2,
2168   EVEX_W_0F59_P_3,
2169   EVEX_W_0F5A_P_0,
2170   EVEX_W_0F5A_P_1,
2171   EVEX_W_0F5A_P_2,
2172   EVEX_W_0F5A_P_3,
2173   EVEX_W_0F5B_P_0,
2174   EVEX_W_0F5B_P_1,
2175   EVEX_W_0F5B_P_2,
2176   EVEX_W_0F5C_P_0,
2177   EVEX_W_0F5C_P_1,
2178   EVEX_W_0F5C_P_2,
2179   EVEX_W_0F5C_P_3,
2180   EVEX_W_0F5D_P_0,
2181   EVEX_W_0F5D_P_1,
2182   EVEX_W_0F5D_P_2,
2183   EVEX_W_0F5D_P_3,
2184   EVEX_W_0F5E_P_0,
2185   EVEX_W_0F5E_P_1,
2186   EVEX_W_0F5E_P_2,
2187   EVEX_W_0F5E_P_3,
2188   EVEX_W_0F5F_P_0,
2189   EVEX_W_0F5F_P_1,
2190   EVEX_W_0F5F_P_2,
2191   EVEX_W_0F5F_P_3,
2192   EVEX_W_0F62_P_2,
2193   EVEX_W_0F66_P_2,
2194   EVEX_W_0F6A_P_2,
2195   EVEX_W_0F6B_P_2,
2196   EVEX_W_0F6C_P_2,
2197   EVEX_W_0F6D_P_2,
2198   EVEX_W_0F6E_P_2,
2199   EVEX_W_0F6F_P_1,
2200   EVEX_W_0F6F_P_2,
2201   EVEX_W_0F6F_P_3,
2202   EVEX_W_0F70_P_2,
2203   EVEX_W_0F72_R_2_P_2,
2204   EVEX_W_0F72_R_6_P_2,
2205   EVEX_W_0F73_R_2_P_2,
2206   EVEX_W_0F73_R_6_P_2,
2207   EVEX_W_0F76_P_2,
2208   EVEX_W_0F78_P_0,
2209   EVEX_W_0F78_P_2,
2210   EVEX_W_0F79_P_0,
2211   EVEX_W_0F79_P_2,
2212   EVEX_W_0F7A_P_1,
2213   EVEX_W_0F7A_P_2,
2214   EVEX_W_0F7A_P_3,
2215   EVEX_W_0F7B_P_1,
2216   EVEX_W_0F7B_P_2,
2217   EVEX_W_0F7B_P_3,
2218   EVEX_W_0F7E_P_1,
2219   EVEX_W_0F7E_P_2,
2220   EVEX_W_0F7F_P_1,
2221   EVEX_W_0F7F_P_2,
2222   EVEX_W_0F7F_P_3,
2223   EVEX_W_0FC2_P_0,
2224   EVEX_W_0FC2_P_1,
2225   EVEX_W_0FC2_P_2,
2226   EVEX_W_0FC2_P_3,
2227   EVEX_W_0FC6_P_0,
2228   EVEX_W_0FC6_P_2,
2229   EVEX_W_0FD2_P_2,
2230   EVEX_W_0FD3_P_2,
2231   EVEX_W_0FD4_P_2,
2232   EVEX_W_0FD6_P_2,
2233   EVEX_W_0FE6_P_1,
2234   EVEX_W_0FE6_P_2,
2235   EVEX_W_0FE6_P_3,
2236   EVEX_W_0FE7_P_2,
2237   EVEX_W_0FF2_P_2,
2238   EVEX_W_0FF3_P_2,
2239   EVEX_W_0FF4_P_2,
2240   EVEX_W_0FFA_P_2,
2241   EVEX_W_0FFB_P_2,
2242   EVEX_W_0FFE_P_2,
2243   EVEX_W_0F380C_P_2,
2244   EVEX_W_0F380D_P_2,
2245   EVEX_W_0F3810_P_1,
2246   EVEX_W_0F3810_P_2,
2247   EVEX_W_0F3811_P_1,
2248   EVEX_W_0F3811_P_2,
2249   EVEX_W_0F3812_P_1,
2250   EVEX_W_0F3812_P_2,
2251   EVEX_W_0F3813_P_1,
2252   EVEX_W_0F3813_P_2,
2253   EVEX_W_0F3814_P_1,
2254   EVEX_W_0F3815_P_1,
2255   EVEX_W_0F3818_P_2,
2256   EVEX_W_0F3819_P_2,
2257   EVEX_W_0F381A_P_2,
2258   EVEX_W_0F381B_P_2,
2259   EVEX_W_0F381E_P_2,
2260   EVEX_W_0F381F_P_2,
2261   EVEX_W_0F3820_P_1,
2262   EVEX_W_0F3821_P_1,
2263   EVEX_W_0F3822_P_1,
2264   EVEX_W_0F3823_P_1,
2265   EVEX_W_0F3824_P_1,
2266   EVEX_W_0F3825_P_1,
2267   EVEX_W_0F3825_P_2,
2268   EVEX_W_0F3826_P_1,
2269   EVEX_W_0F3826_P_2,
2270   EVEX_W_0F3828_P_1,
2271   EVEX_W_0F3828_P_2,
2272   EVEX_W_0F3829_P_1,
2273   EVEX_W_0F3829_P_2,
2274   EVEX_W_0F382A_P_1,
2275   EVEX_W_0F382A_P_2,
2276   EVEX_W_0F382B_P_2,
2277   EVEX_W_0F3830_P_1,
2278   EVEX_W_0F3831_P_1,
2279   EVEX_W_0F3832_P_1,
2280   EVEX_W_0F3833_P_1,
2281   EVEX_W_0F3834_P_1,
2282   EVEX_W_0F3835_P_1,
2283   EVEX_W_0F3835_P_2,
2284   EVEX_W_0F3837_P_2,
2285   EVEX_W_0F3838_P_1,
2286   EVEX_W_0F3839_P_1,
2287   EVEX_W_0F383A_P_1,
2288   EVEX_W_0F3840_P_2,
2289   EVEX_W_0F3858_P_2,
2290   EVEX_W_0F3859_P_2,
2291   EVEX_W_0F385A_P_2,
2292   EVEX_W_0F385B_P_2,
2293   EVEX_W_0F3866_P_2,
2294   EVEX_W_0F3875_P_2,
2295   EVEX_W_0F3878_P_2,
2296   EVEX_W_0F3879_P_2,
2297   EVEX_W_0F387A_P_2,
2298   EVEX_W_0F387B_P_2,
2299   EVEX_W_0F387D_P_2,
2300   EVEX_W_0F388D_P_2,
2301   EVEX_W_0F3891_P_2,
2302   EVEX_W_0F3893_P_2,
2303   EVEX_W_0F38A1_P_2,
2304   EVEX_W_0F38A3_P_2,
2305   EVEX_W_0F38C7_R_1_P_2,
2306   EVEX_W_0F38C7_R_2_P_2,
2307   EVEX_W_0F38C7_R_5_P_2,
2308   EVEX_W_0F38C7_R_6_P_2,
2309
2310   EVEX_W_0F3A00_P_2,
2311   EVEX_W_0F3A01_P_2,
2312   EVEX_W_0F3A04_P_2,
2313   EVEX_W_0F3A05_P_2,
2314   EVEX_W_0F3A08_P_2,
2315   EVEX_W_0F3A09_P_2,
2316   EVEX_W_0F3A0A_P_2,
2317   EVEX_W_0F3A0B_P_2,
2318   EVEX_W_0F3A16_P_2,
2319   EVEX_W_0F3A18_P_2,
2320   EVEX_W_0F3A19_P_2,
2321   EVEX_W_0F3A1A_P_2,
2322   EVEX_W_0F3A1B_P_2,
2323   EVEX_W_0F3A1D_P_2,
2324   EVEX_W_0F3A21_P_2,
2325   EVEX_W_0F3A22_P_2,
2326   EVEX_W_0F3A23_P_2,
2327   EVEX_W_0F3A38_P_2,
2328   EVEX_W_0F3A39_P_2,
2329   EVEX_W_0F3A3A_P_2,
2330   EVEX_W_0F3A3B_P_2,
2331   EVEX_W_0F3A3E_P_2,
2332   EVEX_W_0F3A3F_P_2,
2333   EVEX_W_0F3A42_P_2,
2334   EVEX_W_0F3A43_P_2,
2335   EVEX_W_0F3A50_P_2,
2336   EVEX_W_0F3A51_P_2,
2337   EVEX_W_0F3A56_P_2,
2338   EVEX_W_0F3A57_P_2,
2339   EVEX_W_0F3A66_P_2,
2340   EVEX_W_0F3A67_P_2
2341 };
2342
2343 typedef void (*op_rtn) (int bytemode, int sizeflag);
2344
2345 struct dis386 {
2346   const char *name;
2347   struct
2348     {
2349       op_rtn rtn;
2350       int bytemode;
2351     } op[MAX_OPERANDS];
2352 };
2353
2354 /* Upper case letters in the instruction names here are macros.
2355    'A' => print 'b' if no register operands or suffix_always is true
2356    'B' => print 'b' if suffix_always is true
2357    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2358           size prefix
2359    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2360           suffix_always is true
2361    'E' => print 'e' if 32-bit form of jcxz
2362    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2363    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2364    'H' => print ",pt" or ",pn" branch hint
2365    'I' => honor following macro letter even in Intel mode (implemented only
2366           for some of the macro letters)
2367    'J' => print 'l'
2368    'K' => print 'd' or 'q' if rex prefix is present.
2369    'L' => print 'l' if suffix_always is true
2370    'M' => print 'r' if intel_mnemonic is false.
2371    'N' => print 'n' if instruction has no wait "prefix"
2372    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2373    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2374           or suffix_always is true.  print 'q' if rex prefix is present.
2375    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2376           is true
2377    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2378    'S' => print 'w', 'l' or 'q' if suffix_always is true
2379    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2380    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2381    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2382    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2383    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2384    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2385           suffix_always is true.
2386    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2387    '!' => change condition from true to false or from false to true.
2388    '%' => add 1 upper case letter to the macro.
2389
2390    2 upper case letter macros:
2391    "XY" => print 'x' or 'y' if no register operands or suffix_always
2392            is true.
2393    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2394    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2395            or suffix_always is true
2396    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2397    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2398    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2399    "LW" => print 'd', 'q' depending on the VEX.W bit
2400
2401    Many of the above letters print nothing in Intel mode.  See "putop"
2402    for the details.
2403
2404    Braces '{' and '}', and vertical bars '|', indicate alternative
2405    mnemonic strings for AT&T and Intel.  */
2406
2407 static const struct dis386 dis386[] = {
2408   /* 00 */
2409   { "addB",             { Ebh1, Gb } },
2410   { "addS",             { Evh1, Gv } },
2411   { "addB",             { Gb, EbS } },
2412   { "addS",             { Gv, EvS } },
2413   { "addB",             { AL, Ib } },
2414   { "addS",             { eAX, Iv } },
2415   { X86_64_TABLE (X86_64_06) },
2416   { X86_64_TABLE (X86_64_07) },
2417   /* 08 */
2418   { "orB",              { Ebh1, Gb } },
2419   { "orS",              { Evh1, Gv } },
2420   { "orB",              { Gb, EbS } },
2421   { "orS",              { Gv, EvS } },
2422   { "orB",              { AL, Ib } },
2423   { "orS",              { eAX, Iv } },
2424   { X86_64_TABLE (X86_64_0D) },
2425   { Bad_Opcode },       /* 0x0f extended opcode escape */
2426   /* 10 */
2427   { "adcB",             { Ebh1, Gb } },
2428   { "adcS",             { Evh1, Gv } },
2429   { "adcB",             { Gb, EbS } },
2430   { "adcS",             { Gv, EvS } },
2431   { "adcB",             { AL, Ib } },
2432   { "adcS",             { eAX, Iv } },
2433   { X86_64_TABLE (X86_64_16) },
2434   { X86_64_TABLE (X86_64_17) },
2435   /* 18 */
2436   { "sbbB",             { Ebh1, Gb } },
2437   { "sbbS",             { Evh1, Gv } },
2438   { "sbbB",             { Gb, EbS } },
2439   { "sbbS",             { Gv, EvS } },
2440   { "sbbB",             { AL, Ib } },
2441   { "sbbS",             { eAX, Iv } },
2442   { X86_64_TABLE (X86_64_1E) },
2443   { X86_64_TABLE (X86_64_1F) },
2444   /* 20 */
2445   { "andB",             { Ebh1, Gb } },
2446   { "andS",             { Evh1, Gv } },
2447   { "andB",             { Gb, EbS } },
2448   { "andS",             { Gv, EvS } },
2449   { "andB",             { AL, Ib } },
2450   { "andS",             { eAX, Iv } },
2451   { Bad_Opcode },       /* SEG ES prefix */
2452   { X86_64_TABLE (X86_64_27) },
2453   /* 28 */
2454   { "subB",             { Ebh1, Gb } },
2455   { "subS",             { Evh1, Gv } },
2456   { "subB",             { Gb, EbS } },
2457   { "subS",             { Gv, EvS } },
2458   { "subB",             { AL, Ib } },
2459   { "subS",             { eAX, Iv } },
2460   { Bad_Opcode },       /* SEG CS prefix */
2461   { X86_64_TABLE (X86_64_2F) },
2462   /* 30 */
2463   { "xorB",             { Ebh1, Gb } },
2464   { "xorS",             { Evh1, Gv } },
2465   { "xorB",             { Gb, EbS } },
2466   { "xorS",             { Gv, EvS } },
2467   { "xorB",             { AL, Ib } },
2468   { "xorS",             { eAX, Iv } },
2469   { Bad_Opcode },       /* SEG SS prefix */
2470   { X86_64_TABLE (X86_64_37) },
2471   /* 38 */
2472   { "cmpB",             { Eb, Gb } },
2473   { "cmpS",             { Ev, Gv } },
2474   { "cmpB",             { Gb, EbS } },
2475   { "cmpS",             { Gv, EvS } },
2476   { "cmpB",             { AL, Ib } },
2477   { "cmpS",             { eAX, Iv } },
2478   { Bad_Opcode },       /* SEG DS prefix */
2479   { X86_64_TABLE (X86_64_3F) },
2480   /* 40 */
2481   { "inc{S|}",          { RMeAX } },
2482   { "inc{S|}",          { RMeCX } },
2483   { "inc{S|}",          { RMeDX } },
2484   { "inc{S|}",          { RMeBX } },
2485   { "inc{S|}",          { RMeSP } },
2486   { "inc{S|}",          { RMeBP } },
2487   { "inc{S|}",          { RMeSI } },
2488   { "inc{S|}",          { RMeDI } },
2489   /* 48 */
2490   { "dec{S|}",          { RMeAX } },
2491   { "dec{S|}",          { RMeCX } },
2492   { "dec{S|}",          { RMeDX } },
2493   { "dec{S|}",          { RMeBX } },
2494   { "dec{S|}",          { RMeSP } },
2495   { "dec{S|}",          { RMeBP } },
2496   { "dec{S|}",          { RMeSI } },
2497   { "dec{S|}",          { RMeDI } },
2498   /* 50 */
2499   { "pushV",            { RMrAX } },
2500   { "pushV",            { RMrCX } },
2501   { "pushV",            { RMrDX } },
2502   { "pushV",            { RMrBX } },
2503   { "pushV",            { RMrSP } },
2504   { "pushV",            { RMrBP } },
2505   { "pushV",            { RMrSI } },
2506   { "pushV",            { RMrDI } },
2507   /* 58 */
2508   { "popV",             { RMrAX } },
2509   { "popV",             { RMrCX } },
2510   { "popV",             { RMrDX } },
2511   { "popV",             { RMrBX } },
2512   { "popV",             { RMrSP } },
2513   { "popV",             { RMrBP } },
2514   { "popV",             { RMrSI } },
2515   { "popV",             { RMrDI } },
2516   /* 60 */
2517   { X86_64_TABLE (X86_64_60) },
2518   { X86_64_TABLE (X86_64_61) },
2519   { X86_64_TABLE (X86_64_62) },
2520   { X86_64_TABLE (X86_64_63) },
2521   { Bad_Opcode },       /* seg fs */
2522   { Bad_Opcode },       /* seg gs */
2523   { Bad_Opcode },       /* op size prefix */
2524   { Bad_Opcode },       /* adr size prefix */
2525   /* 68 */
2526   { "pushT",            { sIv } },
2527   { "imulS",            { Gv, Ev, Iv } },
2528   { "pushT",            { sIbT } },
2529   { "imulS",            { Gv, Ev, sIb } },
2530   { "ins{b|}",          { Ybr, indirDX } },
2531   { X86_64_TABLE (X86_64_6D) },
2532   { "outs{b|}",         { indirDXr, Xb } },
2533   { X86_64_TABLE (X86_64_6F) },
2534   /* 70 */
2535   { "joH",              { Jb, BND, cond_jump_flag } },
2536   { "jnoH",             { Jb, BND, cond_jump_flag } },
2537   { "jbH",              { Jb, BND, cond_jump_flag } },
2538   { "jaeH",             { Jb, BND, cond_jump_flag } },
2539   { "jeH",              { Jb, BND, cond_jump_flag } },
2540   { "jneH",             { Jb, BND, cond_jump_flag } },
2541   { "jbeH",             { Jb, BND, cond_jump_flag } },
2542   { "jaH",              { Jb, BND, cond_jump_flag } },
2543   /* 78 */
2544   { "jsH",              { Jb, BND, cond_jump_flag } },
2545   { "jnsH",             { Jb, BND, cond_jump_flag } },
2546   { "jpH",              { Jb, BND, cond_jump_flag } },
2547   { "jnpH",             { Jb, BND, cond_jump_flag } },
2548   { "jlH",              { Jb, BND, cond_jump_flag } },
2549   { "jgeH",             { Jb, BND, cond_jump_flag } },
2550   { "jleH",             { Jb, BND, cond_jump_flag } },
2551   { "jgH",              { Jb, BND, cond_jump_flag } },
2552   /* 80 */
2553   { REG_TABLE (REG_80) },
2554   { REG_TABLE (REG_81) },
2555   { Bad_Opcode },
2556   { REG_TABLE (REG_82) },
2557   { "testB",            { Eb, Gb } },
2558   { "testS",            { Ev, Gv } },
2559   { "xchgB",            { Ebh2, Gb } },
2560   { "xchgS",            { Evh2, Gv } },
2561   /* 88 */
2562   { "movB",             { Ebh3, Gb } },
2563   { "movS",             { Evh3, Gv } },
2564   { "movB",             { Gb, EbS } },
2565   { "movS",             { Gv, EvS } },
2566   { "movD",             { Sv, Sw } },
2567   { MOD_TABLE (MOD_8D) },
2568   { "movD",             { Sw, Sv } },
2569   { REG_TABLE (REG_8F) },
2570   /* 90 */
2571   { PREFIX_TABLE (PREFIX_90) },
2572   { "xchgS",            { RMeCX, eAX } },
2573   { "xchgS",            { RMeDX, eAX } },
2574   { "xchgS",            { RMeBX, eAX } },
2575   { "xchgS",            { RMeSP, eAX } },
2576   { "xchgS",            { RMeBP, eAX } },
2577   { "xchgS",            { RMeSI, eAX } },
2578   { "xchgS",            { RMeDI, eAX } },
2579   /* 98 */
2580   { "cW{t|}R",          { XX } },
2581   { "cR{t|}O",          { XX } },
2582   { X86_64_TABLE (X86_64_9A) },
2583   { Bad_Opcode },       /* fwait */
2584   { "pushfT",           { XX } },
2585   { "popfT",            { XX } },
2586   { "sahf",             { XX } },
2587   { "lahf",             { XX } },
2588   /* a0 */
2589   { "mov%LB",           { AL, Ob } },
2590   { "mov%LS",           { eAX, Ov } },
2591   { "mov%LB",           { Ob, AL } },
2592   { "mov%LS",           { Ov, eAX } },
2593   { "movs{b|}",         { Ybr, Xb } },
2594   { "movs{R|}",         { Yvr, Xv } },
2595   { "cmps{b|}",         { Xb, Yb } },
2596   { "cmps{R|}",         { Xv, Yv } },
2597   /* a8 */
2598   { "testB",            { AL, Ib } },
2599   { "testS",            { eAX, Iv } },
2600   { "stosB",            { Ybr, AL } },
2601   { "stosS",            { Yvr, eAX } },
2602   { "lodsB",            { ALr, Xb } },
2603   { "lodsS",            { eAXr, Xv } },
2604   { "scasB",            { AL, Yb } },
2605   { "scasS",            { eAX, Yv } },
2606   /* b0 */
2607   { "movB",             { RMAL, Ib } },
2608   { "movB",             { RMCL, Ib } },
2609   { "movB",             { RMDL, Ib } },
2610   { "movB",             { RMBL, Ib } },
2611   { "movB",             { RMAH, Ib } },
2612   { "movB",             { RMCH, Ib } },
2613   { "movB",             { RMDH, Ib } },
2614   { "movB",             { RMBH, Ib } },
2615   /* b8 */
2616   { "mov%LV",           { RMeAX, Iv64 } },
2617   { "mov%LV",           { RMeCX, Iv64 } },
2618   { "mov%LV",           { RMeDX, Iv64 } },
2619   { "mov%LV",           { RMeBX, Iv64 } },
2620   { "mov%LV",           { RMeSP, Iv64 } },
2621   { "mov%LV",           { RMeBP, Iv64 } },
2622   { "mov%LV",           { RMeSI, Iv64 } },
2623   { "mov%LV",           { RMeDI, Iv64 } },
2624   /* c0 */
2625   { REG_TABLE (REG_C0) },
2626   { REG_TABLE (REG_C1) },
2627   { "retT",             { Iw, BND } },
2628   { "retT",             { BND } },
2629   { X86_64_TABLE (X86_64_C4) },
2630   { X86_64_TABLE (X86_64_C5) },
2631   { REG_TABLE (REG_C6) },
2632   { REG_TABLE (REG_C7) },
2633   /* c8 */
2634   { "enterT",           { Iw, Ib } },
2635   { "leaveT",           { XX } },
2636   { "Jret{|f}P",        { Iw } },
2637   { "Jret{|f}P",        { XX } },
2638   { "int3",             { XX } },
2639   { "int",              { Ib } },
2640   { X86_64_TABLE (X86_64_CE) },
2641   { "iretP",            { XX } },
2642   /* d0 */
2643   { REG_TABLE (REG_D0) },
2644   { REG_TABLE (REG_D1) },
2645   { REG_TABLE (REG_D2) },
2646   { REG_TABLE (REG_D3) },
2647   { X86_64_TABLE (X86_64_D4) },
2648   { X86_64_TABLE (X86_64_D5) },
2649   { Bad_Opcode },
2650   { "xlat",             { DSBX } },
2651   /* d8 */
2652   { FLOAT },
2653   { FLOAT },
2654   { FLOAT },
2655   { FLOAT },
2656   { FLOAT },
2657   { FLOAT },
2658   { FLOAT },
2659   { FLOAT },
2660   /* e0 */
2661   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
2662   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
2663   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
2664   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
2665   { "inB",              { AL, Ib } },
2666   { "inG",              { zAX, Ib } },
2667   { "outB",             { Ib, AL } },
2668   { "outG",             { Ib, zAX } },
2669   /* e8 */
2670   { "callT",            { Jv, BND } },
2671   { "jmpT",             { Jv, BND } },
2672   { X86_64_TABLE (X86_64_EA) },
2673   { "jmp",              { Jb, BND } },
2674   { "inB",              { AL, indirDX } },
2675   { "inG",              { zAX, indirDX } },
2676   { "outB",             { indirDX, AL } },
2677   { "outG",             { indirDX, zAX } },
2678   /* f0 */
2679   { Bad_Opcode },       /* lock prefix */
2680   { "icebp",            { XX } },
2681   { Bad_Opcode },       /* repne */
2682   { Bad_Opcode },       /* repz */
2683   { "hlt",              { XX } },
2684   { "cmc",              { XX } },
2685   { REG_TABLE (REG_F6) },
2686   { REG_TABLE (REG_F7) },
2687   /* f8 */
2688   { "clc",              { XX } },
2689   { "stc",              { XX } },
2690   { "cli",              { XX } },
2691   { "sti",              { XX } },
2692   { "cld",              { XX } },
2693   { "std",              { XX } },
2694   { REG_TABLE (REG_FE) },
2695   { REG_TABLE (REG_FF) },
2696 };
2697
2698 static const struct dis386 dis386_twobyte[] = {
2699   /* 00 */
2700   { REG_TABLE (REG_0F00 ) },
2701   { REG_TABLE (REG_0F01 ) },
2702   { "larS",             { Gv, Ew } },
2703   { "lslS",             { Gv, Ew } },
2704   { Bad_Opcode },
2705   { "syscall",          { XX } },
2706   { "clts",             { XX } },
2707   { "sysretP",          { XX } },
2708   /* 08 */
2709   { "invd",             { XX } },
2710   { "wbinvd",           { XX } },
2711   { Bad_Opcode },
2712   { "ud2",              { XX } },
2713   { Bad_Opcode },
2714   { REG_TABLE (REG_0F0D) },
2715   { "femms",            { XX } },
2716   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2717   /* 10 */
2718   { PREFIX_TABLE (PREFIX_0F10) },
2719   { PREFIX_TABLE (PREFIX_0F11) },
2720   { PREFIX_TABLE (PREFIX_0F12) },
2721   { MOD_TABLE (MOD_0F13) },
2722   { "unpcklpX",         { XM, EXx } },
2723   { "unpckhpX",         { XM, EXx } },
2724   { PREFIX_TABLE (PREFIX_0F16) },
2725   { MOD_TABLE (MOD_0F17) },
2726   /* 18 */
2727   { REG_TABLE (REG_0F18) },
2728   { "nopQ",             { Ev } },
2729   { PREFIX_TABLE (PREFIX_0F1A) },
2730   { PREFIX_TABLE (PREFIX_0F1B) },
2731   { "nopQ",             { Ev } },
2732   { "nopQ",             { Ev } },
2733   { "nopQ",             { Ev } },
2734   { "nopQ",             { Ev } },
2735   /* 20 */
2736   { MOD_TABLE (MOD_0F20) },
2737   { MOD_TABLE (MOD_0F21) },
2738   { MOD_TABLE (MOD_0F22) },
2739   { MOD_TABLE (MOD_0F23) },
2740   { MOD_TABLE (MOD_0F24) },
2741   { Bad_Opcode },
2742   { MOD_TABLE (MOD_0F26) },
2743   { Bad_Opcode },
2744   /* 28 */
2745   { "movapX",           { XM, EXx } },
2746   { "movapX",           { EXxS, XM } },
2747   { PREFIX_TABLE (PREFIX_0F2A) },
2748   { PREFIX_TABLE (PREFIX_0F2B) },
2749   { PREFIX_TABLE (PREFIX_0F2C) },
2750   { PREFIX_TABLE (PREFIX_0F2D) },
2751   { PREFIX_TABLE (PREFIX_0F2E) },
2752   { PREFIX_TABLE (PREFIX_0F2F) },
2753   /* 30 */
2754   { "wrmsr",            { XX } },
2755   { "rdtsc",            { XX } },
2756   { "rdmsr",            { XX } },
2757   { "rdpmc",            { XX } },
2758   { "sysenter",         { XX } },
2759   { "sysexit",          { XX } },
2760   { Bad_Opcode },
2761   { "getsec",           { XX } },
2762   /* 38 */
2763   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2764   { Bad_Opcode },
2765   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2766   { Bad_Opcode },
2767   { Bad_Opcode },
2768   { Bad_Opcode },
2769   { Bad_Opcode },
2770   { Bad_Opcode },
2771   /* 40 */
2772   { "cmovoS",           { Gv, Ev } },
2773   { "cmovnoS",          { Gv, Ev } },
2774   { "cmovbS",           { Gv, Ev } },
2775   { "cmovaeS",          { Gv, Ev } },
2776   { "cmoveS",           { Gv, Ev } },
2777   { "cmovneS",          { Gv, Ev } },
2778   { "cmovbeS",          { Gv, Ev } },
2779   { "cmovaS",           { Gv, Ev } },
2780   /* 48 */
2781   { "cmovsS",           { Gv, Ev } },
2782   { "cmovnsS",          { Gv, Ev } },
2783   { "cmovpS",           { Gv, Ev } },
2784   { "cmovnpS",          { Gv, Ev } },
2785   { "cmovlS",           { Gv, Ev } },
2786   { "cmovgeS",          { Gv, Ev } },
2787   { "cmovleS",          { Gv, Ev } },
2788   { "cmovgS",           { Gv, Ev } },
2789   /* 50 */
2790   { MOD_TABLE (MOD_0F51) },
2791   { PREFIX_TABLE (PREFIX_0F51) },
2792   { PREFIX_TABLE (PREFIX_0F52) },
2793   { PREFIX_TABLE (PREFIX_0F53) },
2794   { "andpX",            { XM, EXx } },
2795   { "andnpX",           { XM, EXx } },
2796   { "orpX",             { XM, EXx } },
2797   { "xorpX",            { XM, EXx } },
2798   /* 58 */
2799   { PREFIX_TABLE (PREFIX_0F58) },
2800   { PREFIX_TABLE (PREFIX_0F59) },
2801   { PREFIX_TABLE (PREFIX_0F5A) },
2802   { PREFIX_TABLE (PREFIX_0F5B) },
2803   { PREFIX_TABLE (PREFIX_0F5C) },
2804   { PREFIX_TABLE (PREFIX_0F5D) },
2805   { PREFIX_TABLE (PREFIX_0F5E) },
2806   { PREFIX_TABLE (PREFIX_0F5F) },
2807   /* 60 */
2808   { PREFIX_TABLE (PREFIX_0F60) },
2809   { PREFIX_TABLE (PREFIX_0F61) },
2810   { PREFIX_TABLE (PREFIX_0F62) },
2811   { "packsswb",         { MX, EM } },
2812   { "pcmpgtb",          { MX, EM } },
2813   { "pcmpgtw",          { MX, EM } },
2814   { "pcmpgtd",          { MX, EM } },
2815   { "packuswb",         { MX, EM } },
2816   /* 68 */
2817   { "punpckhbw",        { MX, EM } },
2818   { "punpckhwd",        { MX, EM } },
2819   { "punpckhdq",        { MX, EM } },
2820   { "packssdw",         { MX, EM } },
2821   { PREFIX_TABLE (PREFIX_0F6C) },
2822   { PREFIX_TABLE (PREFIX_0F6D) },
2823   { "movK",             { MX, Edq } },
2824   { PREFIX_TABLE (PREFIX_0F6F) },
2825   /* 70 */
2826   { PREFIX_TABLE (PREFIX_0F70) },
2827   { REG_TABLE (REG_0F71) },
2828   { REG_TABLE (REG_0F72) },
2829   { REG_TABLE (REG_0F73) },
2830   { "pcmpeqb",          { MX, EM } },
2831   { "pcmpeqw",          { MX, EM } },
2832   { "pcmpeqd",          { MX, EM } },
2833   { "emms",             { XX } },
2834   /* 78 */
2835   { PREFIX_TABLE (PREFIX_0F78) },
2836   { PREFIX_TABLE (PREFIX_0F79) },
2837   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2838   { Bad_Opcode },
2839   { PREFIX_TABLE (PREFIX_0F7C) },
2840   { PREFIX_TABLE (PREFIX_0F7D) },
2841   { PREFIX_TABLE (PREFIX_0F7E) },
2842   { PREFIX_TABLE (PREFIX_0F7F) },
2843   /* 80 */
2844   { "joH",              { Jv, BND, cond_jump_flag } },
2845   { "jnoH",             { Jv, BND, cond_jump_flag } },
2846   { "jbH",              { Jv, BND, cond_jump_flag } },
2847   { "jaeH",             { Jv, BND, cond_jump_flag } },
2848   { "jeH",              { Jv, BND, cond_jump_flag } },
2849   { "jneH",             { Jv, BND, cond_jump_flag } },
2850   { "jbeH",             { Jv, BND, cond_jump_flag } },
2851   { "jaH",              { Jv, BND, cond_jump_flag } },
2852   /* 88 */
2853   { "jsH",              { Jv, BND, cond_jump_flag } },
2854   { "jnsH",             { Jv, BND, cond_jump_flag } },
2855   { "jpH",              { Jv, BND, cond_jump_flag } },
2856   { "jnpH",             { Jv, BND, cond_jump_flag } },
2857   { "jlH",              { Jv, BND, cond_jump_flag } },
2858   { "jgeH",             { Jv, BND, cond_jump_flag } },
2859   { "jleH",             { Jv, BND, cond_jump_flag } },
2860   { "jgH",              { Jv, BND, cond_jump_flag } },
2861   /* 90 */
2862   { "seto",             { Eb } },
2863   { "setno",            { Eb } },
2864   { "setb",             { Eb } },
2865   { "setae",            { Eb } },
2866   { "sete",             { Eb } },
2867   { "setne",            { Eb } },
2868   { "setbe",            { Eb } },
2869   { "seta",             { Eb } },
2870   /* 98 */
2871   { "sets",             { Eb } },
2872   { "setns",            { Eb } },
2873   { "setp",             { Eb } },
2874   { "setnp",            { Eb } },
2875   { "setl",             { Eb } },
2876   { "setge",            { Eb } },
2877   { "setle",            { Eb } },
2878   { "setg",             { Eb } },
2879   /* a0 */
2880   { "pushT",            { fs } },
2881   { "popT",             { fs } },
2882   { "cpuid",            { XX } },
2883   { "btS",              { Ev, Gv } },
2884   { "shldS",            { Ev, Gv, Ib } },
2885   { "shldS",            { Ev, Gv, CL } },
2886   { REG_TABLE (REG_0FA6) },
2887   { REG_TABLE (REG_0FA7) },
2888   /* a8 */
2889   { "pushT",            { gs } },
2890   { "popT",             { gs } },
2891   { "rsm",              { XX } },
2892   { "btsS",             { Evh1, Gv } },
2893   { "shrdS",            { Ev, Gv, Ib } },
2894   { "shrdS",            { Ev, Gv, CL } },
2895   { REG_TABLE (REG_0FAE) },
2896   { "imulS",            { Gv, Ev } },
2897   /* b0 */
2898   { "cmpxchgB",         { Ebh1, Gb } },
2899   { "cmpxchgS",         { Evh1, Gv } },
2900   { MOD_TABLE (MOD_0FB2) },
2901   { "btrS",             { Evh1, Gv } },
2902   { MOD_TABLE (MOD_0FB4) },
2903   { MOD_TABLE (MOD_0FB5) },
2904   { "movz{bR|x}",       { Gv, Eb } },
2905   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2906   /* b8 */
2907   { PREFIX_TABLE (PREFIX_0FB8) },
2908   { "ud1",              { XX } },
2909   { REG_TABLE (REG_0FBA) },
2910   { "btcS",             { Evh1, Gv } },
2911   { PREFIX_TABLE (PREFIX_0FBC) },
2912   { PREFIX_TABLE (PREFIX_0FBD) },
2913   { "movs{bR|x}",       { Gv, Eb } },
2914   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2915   /* c0 */
2916   { "xaddB",            { Ebh1, Gb } },
2917   { "xaddS",            { Evh1, Gv } },
2918   { PREFIX_TABLE (PREFIX_0FC2) },
2919   { PREFIX_TABLE (PREFIX_0FC3) },
2920   { "pinsrw",           { MX, Edqw, Ib } },
2921   { "pextrw",           { Gdq, MS, Ib } },
2922   { "shufpX",           { XM, EXx, Ib } },
2923   { REG_TABLE (REG_0FC7) },
2924   /* c8 */
2925   { "bswap",            { RMeAX } },
2926   { "bswap",            { RMeCX } },
2927   { "bswap",            { RMeDX } },
2928   { "bswap",            { RMeBX } },
2929   { "bswap",            { RMeSP } },
2930   { "bswap",            { RMeBP } },
2931   { "bswap",            { RMeSI } },
2932   { "bswap",            { RMeDI } },
2933   /* d0 */
2934   { PREFIX_TABLE (PREFIX_0FD0) },
2935   { "psrlw",            { MX, EM } },
2936   { "psrld",            { MX, EM } },
2937   { "psrlq",            { MX, EM } },
2938   { "paddq",            { MX, EM } },
2939   { "pmullw",           { MX, EM } },
2940   { PREFIX_TABLE (PREFIX_0FD6) },
2941   { MOD_TABLE (MOD_0FD7) },
2942   /* d8 */
2943   { "psubusb",          { MX, EM } },
2944   { "psubusw",          { MX, EM } },
2945   { "pminub",           { MX, EM } },
2946   { "pand",             { MX, EM } },
2947   { "paddusb",          { MX, EM } },
2948   { "paddusw",          { MX, EM } },
2949   { "pmaxub",           { MX, EM } },
2950   { "pandn",            { MX, EM } },
2951   /* e0 */
2952   { "pavgb",            { MX, EM } },
2953   { "psraw",            { MX, EM } },
2954   { "psrad",            { MX, EM } },
2955   { "pavgw",            { MX, EM } },
2956   { "pmulhuw",          { MX, EM } },
2957   { "pmulhw",           { MX, EM } },
2958   { PREFIX_TABLE (PREFIX_0FE6) },
2959   { PREFIX_TABLE (PREFIX_0FE7) },
2960   /* e8 */
2961   { "psubsb",           { MX, EM } },
2962   { "psubsw",           { MX, EM } },
2963   { "pminsw",           { MX, EM } },
2964   { "por",              { MX, EM } },
2965   { "paddsb",           { MX, EM } },
2966   { "paddsw",           { MX, EM } },
2967   { "pmaxsw",           { MX, EM } },
2968   { "pxor",             { MX, EM } },
2969   /* f0 */
2970   { PREFIX_TABLE (PREFIX_0FF0) },
2971   { "psllw",            { MX, EM } },
2972   { "pslld",            { MX, EM } },
2973   { "psllq",            { MX, EM } },
2974   { "pmuludq",          { MX, EM } },
2975   { "pmaddwd",          { MX, EM } },
2976   { "psadbw",           { MX, EM } },
2977   { PREFIX_TABLE (PREFIX_0FF7) },
2978   /* f8 */
2979   { "psubb",            { MX, EM } },
2980   { "psubw",            { MX, EM } },
2981   { "psubd",            { MX, EM } },
2982   { "psubq",            { MX, EM } },
2983   { "paddb",            { MX, EM } },
2984   { "paddw",            { MX, EM } },
2985   { "paddd",            { MX, EM } },
2986   { Bad_Opcode },
2987 };
2988
2989 static const unsigned char onebyte_has_modrm[256] = {
2990   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2991   /*       -------------------------------        */
2992   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2993   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2994   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2995   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2996   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2997   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2998   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2999   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3000   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3001   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3002   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3003   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3004   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3005   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3006   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3007   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3008   /*       -------------------------------        */
3009   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3010 };
3011
3012 static const unsigned char twobyte_has_modrm[256] = {
3013   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3014   /*       -------------------------------        */
3015   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3016   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3017   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3018   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3019   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3020   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3021   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3022   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3023   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3024   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3025   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3026   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3027   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3028   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3029   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3030   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3031   /*       -------------------------------        */
3032   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3033 };
3034
3035 static const unsigned char twobyte_has_mandatory_prefix[256] = {
3036   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3037   /*       -------------------------------        */
3038   /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
3039   /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
3040   /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
3041   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3042   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
3043   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3044   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3045   /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
3046   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3047   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
3048   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
3049   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
3050   /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
3051   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3052   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3053   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3054   /*       -------------------------------        */
3055   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3056 };
3057
3058 static char obuf[100];
3059 static char *obufp;
3060 static char *mnemonicendp;
3061 static char scratchbuf[100];
3062 static unsigned char *start_codep;
3063 static unsigned char *insn_codep;
3064 static unsigned char *codep;
3065 static unsigned char *end_codep;
3066 static int last_lock_prefix;
3067 static int last_repz_prefix;
3068 static int last_repnz_prefix;
3069 static int last_data_prefix;
3070 static int last_addr_prefix;
3071 static int last_rex_prefix;
3072 static int last_seg_prefix;
3073 static int fwait_prefix;
3074 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory.  */
3075 static int mandatory_prefix;
3076 /* The active segment register prefix.  */
3077 static int active_seg_prefix;
3078 #define MAX_CODE_LENGTH 15
3079 /* We can up to 14 prefixes since the maximum instruction length is
3080    15bytes.  */
3081 static int all_prefixes[MAX_CODE_LENGTH - 1];
3082 static disassemble_info *the_info;
3083 static struct
3084   {
3085     int mod;
3086     int reg;
3087     int rm;
3088   }
3089 modrm;
3090 static unsigned char need_modrm;
3091 static struct
3092   {
3093     int scale;
3094     int index;
3095     int base;
3096   }
3097 sib;
3098 static struct
3099   {
3100     int register_specifier;
3101     int length;
3102     int prefix;
3103     int w;
3104     int evex;
3105     int r;
3106     int v;
3107     int mask_register_specifier;
3108     int zeroing;
3109     int ll;
3110     int b;
3111   }
3112 vex;
3113 static unsigned char need_vex;
3114 static unsigned char need_vex_reg;
3115 static unsigned char vex_w_done;
3116
3117 struct op
3118   {
3119     const char *name;
3120     unsigned int len;
3121   };
3122
3123 /* If we are accessing mod/rm/reg without need_modrm set, then the
3124    values are stale.  Hitting this abort likely indicates that you
3125    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3126 #define MODRM_CHECK  if (!need_modrm) abort ()
3127
3128 static const char **names64;
3129 static const char **names32;
3130 static const char **names16;
3131 static const char **names8;
3132 static const char **names8rex;
3133 static const char **names_seg;
3134 static const char *index64;
3135 static const char *index32;
3136 static const char **index16;
3137 static const char **names_bnd;
3138
3139 static const char *intel_names64[] = {
3140   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3141   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3142 };
3143 static const char *intel_names32[] = {
3144   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3145   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3146 };
3147 static const char *intel_names16[] = {
3148   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3149   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3150 };
3151 static const char *intel_names8[] = {
3152   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3153 };
3154 static const char *intel_names8rex[] = {
3155   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3156   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3157 };
3158 static const char *intel_names_seg[] = {
3159   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3160 };
3161 static const char *intel_index64 = "riz";
3162 static const char *intel_index32 = "eiz";
3163 static const char *intel_index16[] = {
3164   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3165 };
3166
3167 static const char *att_names64[] = {
3168   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3169   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3170 };
3171 static const char *att_names32[] = {
3172   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3173   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3174 };
3175 static const char *att_names16[] = {
3176   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3177   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3178 };
3179 static const char *att_names8[] = {
3180   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3181 };
3182 static const char *att_names8rex[] = {
3183   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3184   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3185 };
3186 static const char *att_names_seg[] = {
3187   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3188 };
3189 static const char *att_index64 = "%riz";
3190 static const char *att_index32 = "%eiz";
3191 static const char *att_index16[] = {
3192   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3193 };
3194
3195 static const char **names_mm;
3196 static const char *intel_names_mm[] = {
3197   "mm0", "mm1", "mm2", "mm3",
3198   "mm4", "mm5", "mm6", "mm7"
3199 };
3200 static const char *att_names_mm[] = {
3201   "%mm0", "%mm1", "%mm2", "%mm3",
3202   "%mm4", "%mm5", "%mm6", "%mm7"
3203 };
3204
3205 static const char *intel_names_bnd[] = {
3206   "bnd0", "bnd1", "bnd2", "bnd3"
3207 };
3208
3209 static const char *att_names_bnd[] = {
3210   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3211 };
3212
3213 static const char **names_xmm;
3214 static const char *intel_names_xmm[] = {
3215   "xmm0", "xmm1", "xmm2", "xmm3",
3216   "xmm4", "xmm5", "xmm6", "xmm7",
3217   "xmm8", "xmm9", "xmm10", "xmm11",
3218   "xmm12", "xmm13", "xmm14", "xmm15",
3219   "xmm16", "xmm17", "xmm18", "xmm19",
3220   "xmm20", "xmm21", "xmm22", "xmm23",
3221   "xmm24", "xmm25", "xmm26", "xmm27",
3222   "xmm28", "xmm29", "xmm30", "xmm31"
3223 };
3224 static const char *att_names_xmm[] = {
3225   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3226   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3227   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3228   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3229   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3230   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3231   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3232   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3233 };
3234
3235 static const char **names_ymm;
3236 static const char *intel_names_ymm[] = {
3237   "ymm0", "ymm1", "ymm2", "ymm3",
3238   "ymm4", "ymm5", "ymm6", "ymm7",
3239   "ymm8", "ymm9", "ymm10", "ymm11",
3240   "ymm12", "ymm13", "ymm14", "ymm15",
3241   "ymm16", "ymm17", "ymm18", "ymm19",
3242   "ymm20", "ymm21", "ymm22", "ymm23",
3243   "ymm24", "ymm25", "ymm26", "ymm27",
3244   "ymm28", "ymm29", "ymm30", "ymm31"
3245 };
3246 static const char *att_names_ymm[] = {
3247   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3248   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3249   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3250   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3251   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3252   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3253   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3254   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3255 };
3256
3257 static const char **names_zmm;
3258 static const char *intel_names_zmm[] = {
3259   "zmm0", "zmm1", "zmm2", "zmm3",
3260   "zmm4", "zmm5", "zmm6", "zmm7",
3261   "zmm8", "zmm9", "zmm10", "zmm11",
3262   "zmm12", "zmm13", "zmm14", "zmm15",
3263   "zmm16", "zmm17", "zmm18", "zmm19",
3264   "zmm20", "zmm21", "zmm22", "zmm23",
3265   "zmm24", "zmm25", "zmm26", "zmm27",
3266   "zmm28", "zmm29", "zmm30", "zmm31"
3267 };
3268 static const char *att_names_zmm[] = {
3269   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3270   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3271   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3272   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3273   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3274   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3275   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3276   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3277 };
3278
3279 static const char **names_mask;
3280 static const char *intel_names_mask[] = {
3281   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3282 };
3283 static const char *att_names_mask[] = {
3284   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3285 };
3286
3287 static const char *names_rounding[] =
3288 {
3289   "{rn-sae}",
3290   "{rd-sae}",
3291   "{ru-sae}",
3292   "{rz-sae}"
3293 };
3294
3295 static const struct dis386 reg_table[][8] = {
3296   /* REG_80 */
3297   {
3298     { "addA",   { Ebh1, Ib } },
3299     { "orA",    { Ebh1, Ib } },
3300     { "adcA",   { Ebh1, Ib } },
3301     { "sbbA",   { Ebh1, Ib } },
3302     { "andA",   { Ebh1, Ib } },
3303     { "subA",   { Ebh1, Ib } },
3304     { "xorA",   { Ebh1, Ib } },
3305     { "cmpA",   { Eb, Ib } },
3306   },
3307   /* REG_81 */
3308   {
3309     { "addQ",   { Evh1, Iv } },
3310     { "orQ",    { Evh1, Iv } },
3311     { "adcQ",   { Evh1, Iv } },
3312     { "sbbQ",   { Evh1, Iv } },
3313     { "andQ",   { Evh1, Iv } },
3314     { "subQ",   { Evh1, Iv } },
3315     { "xorQ",   { Evh1, Iv } },
3316     { "cmpQ",   { Ev, Iv } },
3317   },
3318   /* REG_82 */
3319   {
3320     { "addQ",   { Evh1, sIb } },
3321     { "orQ",    { Evh1, sIb } },
3322     { "adcQ",   { Evh1, sIb } },
3323     { "sbbQ",   { Evh1, sIb } },
3324     { "andQ",   { Evh1, sIb } },
3325     { "subQ",   { Evh1, sIb } },
3326     { "xorQ",   { Evh1, sIb } },
3327     { "cmpQ",   { Ev, sIb } },
3328   },
3329   /* REG_8F */
3330   {
3331     { "popU",   { stackEv } },
3332     { XOP_8F_TABLE (XOP_09) },
3333     { Bad_Opcode },
3334     { Bad_Opcode },
3335     { Bad_Opcode },
3336     { XOP_8F_TABLE (XOP_09) },
3337   },
3338   /* REG_C0 */
3339   {
3340     { "rolA",   { Eb, Ib } },
3341     { "rorA",   { Eb, Ib } },
3342     { "rclA",   { Eb, Ib } },
3343     { "rcrA",   { Eb, Ib } },
3344     { "shlA",   { Eb, Ib } },
3345     { "shrA",   { Eb, Ib } },
3346     { Bad_Opcode },
3347     { "sarA",   { Eb, Ib } },
3348   },
3349   /* REG_C1 */
3350   {
3351     { "rolQ",   { Ev, Ib } },
3352     { "rorQ",   { Ev, Ib } },
3353     { "rclQ",   { Ev, Ib } },
3354     { "rcrQ",   { Ev, Ib } },
3355     { "shlQ",   { Ev, Ib } },
3356     { "shrQ",   { Ev, Ib } },
3357     { Bad_Opcode },
3358     { "sarQ",   { Ev, Ib } },
3359   },
3360   /* REG_C6 */
3361   {
3362     { "movA",   { Ebh3, Ib } },
3363     { Bad_Opcode },
3364     { Bad_Opcode },
3365     { Bad_Opcode },
3366     { Bad_Opcode },
3367     { Bad_Opcode },
3368     { Bad_Opcode },
3369     { MOD_TABLE (MOD_C6_REG_7) },
3370   },
3371   /* REG_C7 */
3372   {
3373     { "movQ",   { Evh3, Iv } },
3374     { Bad_Opcode },
3375     { Bad_Opcode },
3376     { Bad_Opcode },
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380     { MOD_TABLE (MOD_C7_REG_7) },
3381   },
3382   /* REG_D0 */
3383   {
3384     { "rolA",   { Eb, I1 } },
3385     { "rorA",   { Eb, I1 } },
3386     { "rclA",   { Eb, I1 } },
3387     { "rcrA",   { Eb, I1 } },
3388     { "shlA",   { Eb, I1 } },
3389     { "shrA",   { Eb, I1 } },
3390     { Bad_Opcode },
3391     { "sarA",   { Eb, I1 } },
3392   },
3393   /* REG_D1 */
3394   {
3395     { "rolQ",   { Ev, I1 } },
3396     { "rorQ",   { Ev, I1 } },
3397     { "rclQ",   { Ev, I1 } },
3398     { "rcrQ",   { Ev, I1 } },
3399     { "shlQ",   { Ev, I1 } },
3400     { "shrQ",   { Ev, I1 } },
3401     { Bad_Opcode },
3402     { "sarQ",   { Ev, I1 } },
3403   },
3404   /* REG_D2 */
3405   {
3406     { "rolA",   { Eb, CL } },
3407     { "rorA",   { Eb, CL } },
3408     { "rclA",   { Eb, CL } },
3409     { "rcrA",   { Eb, CL } },
3410     { "shlA",   { Eb, CL } },
3411     { "shrA",   { Eb, CL } },
3412     { Bad_Opcode },
3413     { "sarA",   { Eb, CL } },
3414   },
3415   /* REG_D3 */
3416   {
3417     { "rolQ",   { Ev, CL } },
3418     { "rorQ",   { Ev, CL } },
3419     { "rclQ",   { Ev, CL } },
3420     { "rcrQ",   { Ev, CL } },
3421     { "shlQ",   { Ev, CL } },
3422     { "shrQ",   { Ev, CL } },
3423     { Bad_Opcode },
3424     { "sarQ",   { Ev, CL } },
3425   },
3426   /* REG_F6 */
3427   {
3428     { "testA",  { Eb, Ib } },
3429     { Bad_Opcode },
3430     { "notA",   { Ebh1 } },
3431     { "negA",   { Ebh1 } },
3432     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
3433     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
3434     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
3435     { "idivA",  { Eb } },       /* and idiv for consistency.               */
3436   },
3437   /* REG_F7 */
3438   {
3439     { "testQ",  { Ev, Iv } },
3440     { Bad_Opcode },
3441     { "notQ",   { Evh1 } },
3442     { "negQ",   { Evh1 } },
3443     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
3444     { "imulQ",  { Ev } },
3445     { "divQ",   { Ev } },
3446     { "idivQ",  { Ev } },
3447   },
3448   /* REG_FE */
3449   {
3450     { "incA",   { Ebh1 } },
3451     { "decA",   { Ebh1 } },
3452   },
3453   /* REG_FF */
3454   {
3455     { "incQ",   { Evh1 } },
3456     { "decQ",   { Evh1 } },
3457     { "call{T|}", { indirEv, BND } },
3458     { MOD_TABLE (MOD_FF_REG_3) },
3459     { "jmp{T|}", { indirEv, BND } },
3460     { MOD_TABLE (MOD_FF_REG_5) },
3461     { "pushU",  { stackEv } },
3462     { Bad_Opcode },
3463   },
3464   /* REG_0F00 */
3465   {
3466     { "sldtD",  { Sv } },
3467     { "strD",   { Sv } },
3468     { "lldt",   { Ew } },
3469     { "ltr",    { Ew } },
3470     { "verr",   { Ew } },
3471     { "verw",   { Ew } },
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474   },
3475   /* REG_0F01 */
3476   {
3477     { MOD_TABLE (MOD_0F01_REG_0) },
3478     { MOD_TABLE (MOD_0F01_REG_1) },
3479     { MOD_TABLE (MOD_0F01_REG_2) },
3480     { MOD_TABLE (MOD_0F01_REG_3) },
3481     { "smswD",  { Sv } },
3482     { Bad_Opcode },
3483     { "lmsw",   { Ew } },
3484     { MOD_TABLE (MOD_0F01_REG_7) },
3485   },
3486   /* REG_0F0D */
3487   {
3488     { "prefetch",       { Mb } },
3489     { "prefetchw",      { Mb } },
3490     { "prefetchwt1",    { Mb } },
3491     { "prefetch",       { Mb } },
3492     { "prefetch",       { Mb } },
3493     { "prefetch",       { Mb } },
3494     { "prefetch",       { Mb } },
3495     { "prefetch",       { Mb } },
3496   },
3497   /* REG_0F18 */
3498   {
3499     { MOD_TABLE (MOD_0F18_REG_0) },
3500     { MOD_TABLE (MOD_0F18_REG_1) },
3501     { MOD_TABLE (MOD_0F18_REG_2) },
3502     { MOD_TABLE (MOD_0F18_REG_3) },
3503     { MOD_TABLE (MOD_0F18_REG_4) },
3504     { MOD_TABLE (MOD_0F18_REG_5) },
3505     { MOD_TABLE (MOD_0F18_REG_6) },
3506     { MOD_TABLE (MOD_0F18_REG_7) },
3507   },
3508   /* REG_0F71 */
3509   {
3510     { Bad_Opcode },
3511     { Bad_Opcode },
3512     { MOD_TABLE (MOD_0F71_REG_2) },
3513     { Bad_Opcode },
3514     { MOD_TABLE (MOD_0F71_REG_4) },
3515     { Bad_Opcode },
3516     { MOD_TABLE (MOD_0F71_REG_6) },
3517   },
3518   /* REG_0F72 */
3519   {
3520     { Bad_Opcode },
3521     { Bad_Opcode },
3522     { MOD_TABLE (MOD_0F72_REG_2) },
3523     { Bad_Opcode },
3524     { MOD_TABLE (MOD_0F72_REG_4) },
3525     { Bad_Opcode },
3526     { MOD_TABLE (MOD_0F72_REG_6) },
3527   },
3528   /* REG_0F73 */
3529   {
3530     { Bad_Opcode },
3531     { Bad_Opcode },
3532     { MOD_TABLE (MOD_0F73_REG_2) },
3533     { MOD_TABLE (MOD_0F73_REG_3) },
3534     { Bad_Opcode },
3535     { Bad_Opcode },
3536     { MOD_TABLE (MOD_0F73_REG_6) },
3537     { MOD_TABLE (MOD_0F73_REG_7) },
3538   },
3539   /* REG_0FA6 */
3540   {
3541     { "montmul",        { { OP_0f07, 0 } } },
3542     { "xsha1",          { { OP_0f07, 0 } } },
3543     { "xsha256",        { { OP_0f07, 0 } } },
3544   },
3545   /* REG_0FA7 */
3546   {
3547     { "xstore-rng",     { { OP_0f07, 0 } } },
3548     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
3549     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
3550     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
3551     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
3552     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
3553   },
3554   /* REG_0FAE */
3555   {
3556     { MOD_TABLE (MOD_0FAE_REG_0) },
3557     { MOD_TABLE (MOD_0FAE_REG_1) },
3558     { MOD_TABLE (MOD_0FAE_REG_2) },
3559     { MOD_TABLE (MOD_0FAE_REG_3) },
3560     { MOD_TABLE (MOD_0FAE_REG_4) },
3561     { MOD_TABLE (MOD_0FAE_REG_5) },
3562     { MOD_TABLE (MOD_0FAE_REG_6) },
3563     { MOD_TABLE (MOD_0FAE_REG_7) },
3564   },
3565   /* REG_0FBA */
3566   {
3567     { Bad_Opcode },
3568     { Bad_Opcode },
3569     { Bad_Opcode },
3570     { Bad_Opcode },
3571     { "btQ",    { Ev, Ib } },
3572     { "btsQ",   { Evh1, Ib } },
3573     { "btrQ",   { Evh1, Ib } },
3574     { "btcQ",   { Evh1, Ib } },
3575   },
3576   /* REG_0FC7 */
3577   {
3578     { Bad_Opcode },
3579     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3580     { Bad_Opcode },
3581     { MOD_TABLE (MOD_0FC7_REG_3) },
3582     { MOD_TABLE (MOD_0FC7_REG_4) },
3583     { MOD_TABLE (MOD_0FC7_REG_5) },
3584     { MOD_TABLE (MOD_0FC7_REG_6) },
3585     { MOD_TABLE (MOD_0FC7_REG_7) },
3586   },
3587   /* REG_VEX_0F71 */
3588   {
3589     { Bad_Opcode },
3590     { Bad_Opcode },
3591     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3592     { Bad_Opcode },
3593     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3594     { Bad_Opcode },
3595     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3596   },
3597   /* REG_VEX_0F72 */
3598   {
3599     { Bad_Opcode },
3600     { Bad_Opcode },
3601     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3602     { Bad_Opcode },
3603     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3604     { Bad_Opcode },
3605     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3606   },
3607   /* REG_VEX_0F73 */
3608   {
3609     { Bad_Opcode },
3610     { Bad_Opcode },
3611     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3612     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3613     { Bad_Opcode },
3614     { Bad_Opcode },
3615     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3616     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3617   },
3618   /* REG_VEX_0FAE */
3619   {
3620     { Bad_Opcode },
3621     { Bad_Opcode },
3622     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3623     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3624   },
3625   /* REG_VEX_0F38F3 */
3626   {
3627     { Bad_Opcode },
3628     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3629     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3630     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3631   },
3632   /* REG_XOP_LWPCB */
3633   {
3634     { "llwpcb", { { OP_LWPCB_E, 0 } } },
3635     { "slwpcb", { { OP_LWPCB_E, 0 } } },
3636   },
3637   /* REG_XOP_LWP */
3638   {
3639     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3640     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3641   },
3642   /* REG_XOP_TBM_01 */
3643   {
3644     { Bad_Opcode },
3645     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
3646     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
3647     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
3648     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
3649     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
3650     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
3651     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3652   },
3653   /* REG_XOP_TBM_02 */
3654   {
3655     { Bad_Opcode },
3656     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3657     { Bad_Opcode },
3658     { Bad_Opcode },
3659     { Bad_Opcode },
3660     { Bad_Opcode },
3661     { "blci",   { { OP_LWP_E, 0 }, Ev } },
3662   },
3663 #define NEED_REG_TABLE
3664 #include "i386-dis-evex.h"
3665 #undef NEED_REG_TABLE
3666 };
3667
3668 static const struct dis386 prefix_table[][4] = {
3669   /* PREFIX_90 */
3670   {
3671     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3672     { "pause", { XX } },
3673     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3674   },
3675
3676   /* PREFIX_0F10 */
3677   {
3678     { "movups", { XM, EXx } },
3679     { "movss",  { XM, EXd } },
3680     { "movupd", { XM, EXx } },
3681     { "movsd",  { XM, EXq } },
3682   },
3683
3684   /* PREFIX_0F11 */
3685   {
3686     { "movups", { EXxS, XM } },
3687     { "movss",  { EXdS, XM } },
3688     { "movupd", { EXxS, XM } },
3689     { "movsd",  { EXqS, XM } },
3690   },
3691
3692   /* PREFIX_0F12 */
3693   {
3694     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3695     { "movsldup", { XM, EXx } },
3696     { "movlpd", { XM, EXq } },
3697     { "movddup", { XM, EXq } },
3698   },
3699
3700   /* PREFIX_0F16 */
3701   {
3702     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3703     { "movshdup", { XM, EXx } },
3704     { "movhpd", { XM, EXq } },
3705   },
3706
3707   /* PREFIX_0F1A */
3708   {
3709     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3710     { "bndcl",  { Gbnd, Ev_bnd } },
3711     { "bndmov", { Gbnd, Ebnd } },
3712     { "bndcu",  { Gbnd, Ev_bnd } },
3713   },
3714
3715   /* PREFIX_0F1B */
3716   {
3717     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3718     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3719     { "bndmov", { Ebnd, Gbnd } },
3720     { "bndcn",  { Gbnd, Ev_bnd } },
3721   },
3722
3723   /* PREFIX_0F2A */
3724   {
3725     { "cvtpi2ps", { XM, EMCq } },
3726     { "cvtsi2ss%LQ", { XM, Ev } },
3727     { "cvtpi2pd", { XM, EMCq } },
3728     { "cvtsi2sd%LQ", { XM, Ev } },
3729   },
3730
3731   /* PREFIX_0F2B */
3732   {
3733     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3734     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3735     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3736     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3737   },
3738
3739   /* PREFIX_0F2C */
3740   {
3741     { "cvttps2pi", { MXC, EXq } },
3742     { "cvttss2siY", { Gv, EXd } },
3743     { "cvttpd2pi", { MXC, EXx } },
3744     { "cvttsd2siY", { Gv, EXq } },
3745   },
3746
3747   /* PREFIX_0F2D */
3748   {
3749     { "cvtps2pi", { MXC, EXq } },
3750     { "cvtss2siY", { Gv, EXd } },
3751     { "cvtpd2pi", { MXC, EXx } },
3752     { "cvtsd2siY", { Gv, EXq } },
3753   },
3754
3755   /* PREFIX_0F2E */
3756   {
3757     { "ucomiss",{ XM, EXd } },
3758     { Bad_Opcode },
3759     { "ucomisd",{ XM, EXq } },
3760   },
3761
3762   /* PREFIX_0F2F */
3763   {
3764     { "comiss", { XM, EXd } },
3765     { Bad_Opcode },
3766     { "comisd", { XM, EXq } },
3767   },
3768
3769   /* PREFIX_0F51 */
3770   {
3771     { "sqrtps", { XM, EXx } },
3772     { "sqrtss", { XM, EXd } },
3773     { "sqrtpd", { XM, EXx } },
3774     { "sqrtsd", { XM, EXq } },
3775   },
3776
3777   /* PREFIX_0F52 */
3778   {
3779     { "rsqrtps",{ XM, EXx } },
3780     { "rsqrtss",{ XM, EXd } },
3781   },
3782
3783   /* PREFIX_0F53 */
3784   {
3785     { "rcpps",  { XM, EXx } },
3786     { "rcpss",  { XM, EXd } },
3787   },
3788
3789   /* PREFIX_0F58 */
3790   {
3791     { "addps", { XM, EXx } },
3792     { "addss", { XM, EXd } },
3793     { "addpd", { XM, EXx } },
3794     { "addsd", { XM, EXq } },
3795   },
3796
3797   /* PREFIX_0F59 */
3798   {
3799     { "mulps",  { XM, EXx } },
3800     { "mulss",  { XM, EXd } },
3801     { "mulpd",  { XM, EXx } },
3802     { "mulsd",  { XM, EXq } },
3803   },
3804
3805   /* PREFIX_0F5A */
3806   {
3807     { "cvtps2pd", { XM, EXq } },
3808     { "cvtss2sd", { XM, EXd } },
3809     { "cvtpd2ps", { XM, EXx } },
3810     { "cvtsd2ss", { XM, EXq } },
3811   },
3812
3813   /* PREFIX_0F5B */
3814   {
3815     { "cvtdq2ps", { XM, EXx } },
3816     { "cvttps2dq", { XM, EXx } },
3817     { "cvtps2dq", { XM, EXx } },
3818   },
3819
3820   /* PREFIX_0F5C */
3821   {
3822     { "subps",  { XM, EXx } },
3823     { "subss",  { XM, EXd } },
3824     { "subpd",  { XM, EXx } },
3825     { "subsd",  { XM, EXq } },
3826   },
3827
3828   /* PREFIX_0F5D */
3829   {
3830     { "minps",  { XM, EXx } },
3831     { "minss",  { XM, EXd } },
3832     { "minpd",  { XM, EXx } },
3833     { "minsd",  { XM, EXq } },
3834   },
3835
3836   /* PREFIX_0F5E */
3837   {
3838     { "divps",  { XM, EXx } },
3839     { "divss",  { XM, EXd } },
3840     { "divpd",  { XM, EXx } },
3841     { "divsd",  { XM, EXq } },
3842   },
3843
3844   /* PREFIX_0F5F */
3845   {
3846     { "maxps",  { XM, EXx } },
3847     { "maxss",  { XM, EXd } },
3848     { "maxpd",  { XM, EXx } },
3849     { "maxsd",  { XM, EXq } },
3850   },
3851
3852   /* PREFIX_0F60 */
3853   {
3854     { "punpcklbw",{ MX, EMd } },
3855     { Bad_Opcode },
3856     { "punpcklbw",{ MX, EMx } },
3857   },
3858
3859   /* PREFIX_0F61 */
3860   {
3861     { "punpcklwd",{ MX, EMd } },
3862     { Bad_Opcode },
3863     { "punpcklwd",{ MX, EMx } },
3864   },
3865
3866   /* PREFIX_0F62 */
3867   {
3868     { "punpckldq",{ MX, EMd } },
3869     { Bad_Opcode },
3870     { "punpckldq",{ MX, EMx } },
3871   },
3872
3873   /* PREFIX_0F6C */
3874   {
3875     { Bad_Opcode },
3876     { Bad_Opcode },
3877     { "punpcklqdq", { XM, EXx } },
3878   },
3879
3880   /* PREFIX_0F6D */
3881   {
3882     { Bad_Opcode },
3883     { Bad_Opcode },
3884     { "punpckhqdq", { XM, EXx } },
3885   },
3886
3887   /* PREFIX_0F6F */
3888   {
3889     { "movq",   { MX, EM } },
3890     { "movdqu", { XM, EXx } },
3891     { "movdqa", { XM, EXx } },
3892   },
3893
3894   /* PREFIX_0F70 */
3895   {
3896     { "pshufw", { MX, EM, Ib } },
3897     { "pshufhw",{ XM, EXx, Ib } },
3898     { "pshufd", { XM, EXx, Ib } },
3899     { "pshuflw",{ XM, EXx, Ib } },
3900   },
3901
3902   /* PREFIX_0F73_REG_3 */
3903   {
3904     { Bad_Opcode },
3905     { Bad_Opcode },
3906     { "psrldq", { XS, Ib } },
3907   },
3908
3909   /* PREFIX_0F73_REG_7 */
3910   {
3911     { Bad_Opcode },
3912     { Bad_Opcode },
3913     { "pslldq", { XS, Ib } },
3914   },
3915
3916   /* PREFIX_0F78 */
3917   {
3918     {"vmread",  { Em, Gm } },
3919     { Bad_Opcode },
3920     {"extrq",   { XS, Ib, Ib } },
3921     {"insertq", { XM, XS, Ib, Ib } },
3922   },
3923
3924   /* PREFIX_0F79 */
3925   {
3926     {"vmwrite", { Gm, Em } },
3927     { Bad_Opcode },
3928     {"extrq",   { XM, XS } },
3929     {"insertq", { XM, XS } },
3930   },
3931
3932   /* PREFIX_0F7C */
3933   {
3934     { Bad_Opcode },
3935     { Bad_Opcode },
3936     { "haddpd", { XM, EXx } },
3937     { "haddps", { XM, EXx } },
3938   },
3939
3940   /* PREFIX_0F7D */
3941   {
3942     { Bad_Opcode },
3943     { Bad_Opcode },
3944     { "hsubpd", { XM, EXx } },
3945     { "hsubps", { XM, EXx } },
3946   },
3947
3948   /* PREFIX_0F7E */
3949   {
3950     { "movK",   { Edq, MX } },
3951     { "movq",   { XM, EXq } },
3952     { "movK",   { Edq, XM } },
3953   },
3954
3955   /* PREFIX_0F7F */
3956   {
3957     { "movq",   { EMS, MX } },
3958     { "movdqu", { EXxS, XM } },
3959     { "movdqa", { EXxS, XM } },
3960   },
3961
3962   /* PREFIX_0FAE_REG_0 */
3963   {
3964     { Bad_Opcode },
3965     { "rdfsbase", { Ev } },
3966   },
3967
3968   /* PREFIX_0FAE_REG_1 */
3969   {
3970     { Bad_Opcode },
3971     { "rdgsbase", { Ev } },
3972   },
3973
3974   /* PREFIX_0FAE_REG_2 */
3975   {
3976     { Bad_Opcode },
3977     { "wrfsbase", { Ev } },
3978   },
3979
3980   /* PREFIX_0FAE_REG_3 */
3981   {
3982     { Bad_Opcode },
3983     { "wrgsbase", { Ev } },
3984   },
3985
3986   /* PREFIX_0FAE_REG_7 */
3987   {
3988     { "clflush",        { Mb } },
3989     { Bad_Opcode },
3990     { "clflushopt",     { Mb } },
3991   },
3992
3993   /* PREFIX_0FB8 */
3994   {
3995     { Bad_Opcode },
3996     { "popcntS", { Gv, Ev } },
3997   },
3998
3999   /* PREFIX_0FBC */
4000   {
4001     { "bsfS",   { Gv, Ev } },
4002     { "tzcntS", { Gv, Ev } },
4003     { "bsfS",   { Gv, Ev } },
4004   },
4005
4006   /* PREFIX_0FBD */
4007   {
4008     { "bsrS",   { Gv, Ev } },
4009     { "lzcntS", { Gv, Ev } },
4010     { "bsrS",   { Gv, Ev } },
4011   },
4012
4013   /* PREFIX_0FC2 */
4014   {
4015     { "cmpps",  { XM, EXx, CMP } },
4016     { "cmpss",  { XM, EXd, CMP } },
4017     { "cmppd",  { XM, EXx, CMP } },
4018     { "cmpsd",  { XM, EXq, CMP } },
4019   },
4020
4021   /* PREFIX_0FC3 */
4022   {
4023     { "movntiS", { Ma, Gv } },
4024   },
4025
4026   /* PREFIX_0FC7_REG_6 */
4027   {
4028     { "vmptrld",{ Mq } },
4029     { "vmxon",  { Mq } },
4030     { "vmclear",{ Mq } },
4031   },
4032
4033   /* PREFIX_0FD0 */
4034   {
4035     { Bad_Opcode },
4036     { Bad_Opcode },
4037     { "addsubpd", { XM, EXx } },
4038     { "addsubps", { XM, EXx } },
4039   },
4040
4041   /* PREFIX_0FD6 */
4042   {
4043     { Bad_Opcode },
4044     { "movq2dq",{ XM, MS } },
4045     { "movq",   { EXqS, XM } },
4046     { "movdq2q",{ MX, XS } },
4047   },
4048
4049   /* PREFIX_0FE6 */
4050   {
4051     { Bad_Opcode },
4052     { "cvtdq2pd", { XM, EXq } },
4053     { "cvttpd2dq", { XM, EXx } },
4054     { "cvtpd2dq", { XM, EXx } },
4055   },
4056
4057   /* PREFIX_0FE7 */
4058   {
4059     { "movntq", { Mq, MX } },
4060     { Bad_Opcode },
4061     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4062   },
4063
4064   /* PREFIX_0FF0 */
4065   {
4066     { Bad_Opcode },
4067     { Bad_Opcode },
4068     { Bad_Opcode },
4069     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4070   },
4071
4072   /* PREFIX_0FF7 */
4073   {
4074     { "maskmovq", { MX, MS } },
4075     { Bad_Opcode },
4076     { "maskmovdqu", { XM, XS } },
4077   },
4078
4079   /* PREFIX_0F3810 */
4080   {
4081     { Bad_Opcode },
4082     { Bad_Opcode },
4083     { "pblendvb", { XM, EXx, XMM0 } },
4084   },
4085
4086   /* PREFIX_0F3814 */
4087   {
4088     { Bad_Opcode },
4089     { Bad_Opcode },
4090     { "blendvps", { XM, EXx, XMM0 } },
4091   },
4092
4093   /* PREFIX_0F3815 */
4094   {
4095     { Bad_Opcode },
4096     { Bad_Opcode },
4097     { "blendvpd", { XM, EXx, XMM0 } },
4098   },
4099
4100   /* PREFIX_0F3817 */
4101   {
4102     { Bad_Opcode },
4103     { Bad_Opcode },
4104     { "ptest",  { XM, EXx } },
4105   },
4106
4107   /* PREFIX_0F3820 */
4108   {
4109     { Bad_Opcode },
4110     { Bad_Opcode },
4111     { "pmovsxbw", { XM, EXq } },
4112   },
4113
4114   /* PREFIX_0F3821 */
4115   {
4116     { Bad_Opcode },
4117     { Bad_Opcode },
4118     { "pmovsxbd", { XM, EXd } },
4119   },
4120
4121   /* PREFIX_0F3822 */
4122   {
4123     { Bad_Opcode },
4124     { Bad_Opcode },
4125     { "pmovsxbq", { XM, EXw } },
4126   },
4127
4128   /* PREFIX_0F3823 */
4129   {
4130     { Bad_Opcode },
4131     { Bad_Opcode },
4132     { "pmovsxwd", { XM, EXq } },
4133   },
4134
4135   /* PREFIX_0F3824 */
4136   {
4137     { Bad_Opcode },
4138     { Bad_Opcode },
4139     { "pmovsxwq", { XM, EXd } },
4140   },
4141
4142   /* PREFIX_0F3825 */
4143   {
4144     { Bad_Opcode },
4145     { Bad_Opcode },
4146     { "pmovsxdq", { XM, EXq } },
4147   },
4148
4149   /* PREFIX_0F3828 */
4150   {
4151     { Bad_Opcode },
4152     { Bad_Opcode },
4153     { "pmuldq", { XM, EXx } },
4154   },
4155
4156   /* PREFIX_0F3829 */
4157   {
4158     { Bad_Opcode },
4159     { Bad_Opcode },
4160     { "pcmpeqq", { XM, EXx } },
4161   },
4162
4163   /* PREFIX_0F382A */
4164   {
4165     { Bad_Opcode },
4166     { Bad_Opcode },
4167     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4168   },
4169
4170   /* PREFIX_0F382B */
4171   {
4172     { Bad_Opcode },
4173     { Bad_Opcode },
4174     { "packusdw", { XM, EXx } },
4175   },
4176
4177   /* PREFIX_0F3830 */
4178   {
4179     { Bad_Opcode },
4180     { Bad_Opcode },
4181     { "pmovzxbw", { XM, EXq } },
4182   },
4183
4184   /* PREFIX_0F3831 */
4185   {
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { "pmovzxbd", { XM, EXd } },
4189   },
4190
4191   /* PREFIX_0F3832 */
4192   {
4193     { Bad_Opcode },
4194     { Bad_Opcode },
4195     { "pmovzxbq", { XM, EXw } },
4196   },
4197
4198   /* PREFIX_0F3833 */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { "pmovzxwd", { XM, EXq } },
4203   },
4204
4205   /* PREFIX_0F3834 */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { "pmovzxwq", { XM, EXd } },
4210   },
4211
4212   /* PREFIX_0F3835 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { "pmovzxdq", { XM, EXq } },
4217   },
4218
4219   /* PREFIX_0F3837 */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { "pcmpgtq", { XM, EXx } },
4224   },
4225
4226   /* PREFIX_0F3838 */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { "pminsb", { XM, EXx } },
4231   },
4232
4233   /* PREFIX_0F3839 */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { "pminsd", { XM, EXx } },
4238   },
4239
4240   /* PREFIX_0F383A */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { "pminuw", { XM, EXx } },
4245   },
4246
4247   /* PREFIX_0F383B */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { "pminud", { XM, EXx } },
4252   },
4253
4254   /* PREFIX_0F383C */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "pmaxsb", { XM, EXx } },
4259   },
4260
4261   /* PREFIX_0F383D */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { "pmaxsd", { XM, EXx } },
4266   },
4267
4268   /* PREFIX_0F383E */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { "pmaxuw", { XM, EXx } },
4273   },
4274
4275   /* PREFIX_0F383F */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { "pmaxud", { XM, EXx } },
4280   },
4281
4282   /* PREFIX_0F3840 */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { "pmulld", { XM, EXx } },
4287   },
4288
4289   /* PREFIX_0F3841 */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "phminposuw", { XM, EXx } },
4294   },
4295
4296   /* PREFIX_0F3880 */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "invept", { Gm, Mo } },
4301   },
4302
4303   /* PREFIX_0F3881 */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "invvpid", { Gm, Mo } },
4308   },
4309
4310   /* PREFIX_0F3882 */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "invpcid", { Gm, M } },
4315   },
4316
4317   /* PREFIX_0F38C8 */
4318   {
4319     { "sha1nexte", { XM, EXxmm } },
4320   },
4321
4322   /* PREFIX_0F38C9 */
4323   {
4324     { "sha1msg1", { XM, EXxmm } },
4325   },
4326
4327   /* PREFIX_0F38CA */
4328   {
4329     { "sha1msg2", { XM, EXxmm } },
4330   },
4331
4332   /* PREFIX_0F38CB */
4333   {
4334     { "sha256rnds2", { XM, EXxmm, XMM0 } },
4335   },
4336
4337   /* PREFIX_0F38CC */
4338   {
4339     { "sha256msg1", { XM, EXxmm } },
4340   },
4341
4342   /* PREFIX_0F38CD */
4343   {
4344     { "sha256msg2", { XM, EXxmm } },
4345   },
4346
4347   /* PREFIX_0F38DB */
4348   {
4349     { Bad_Opcode },
4350     { Bad_Opcode },
4351     { "aesimc", { XM, EXx } },
4352   },
4353
4354   /* PREFIX_0F38DC */
4355   {
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     { "aesenc", { XM, EXx } },
4359   },
4360
4361   /* PREFIX_0F38DD */
4362   {
4363     { Bad_Opcode },
4364     { Bad_Opcode },
4365     { "aesenclast", { XM, EXx } },
4366   },
4367
4368   /* PREFIX_0F38DE */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { "aesdec", { XM, EXx } },
4373   },
4374
4375   /* PREFIX_0F38DF */
4376   {
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { "aesdeclast", { XM, EXx } },
4380   },
4381
4382   /* PREFIX_0F38F0 */
4383   {
4384     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4385     { Bad_Opcode },
4386     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4387     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
4388   },
4389
4390   /* PREFIX_0F38F1 */
4391   {
4392     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4393     { Bad_Opcode },
4394     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4395     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
4396   },
4397
4398   /* PREFIX_0F38F6 */
4399   {
4400     { Bad_Opcode },
4401     { "adoxS",  { Gdq, Edq} },
4402     { "adcxS",  { Gdq, Edq} },
4403     { Bad_Opcode },
4404   },
4405
4406   /* PREFIX_0F3A08 */
4407   {
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { "roundps", { XM, EXx, Ib } },
4411   },
4412
4413   /* PREFIX_0F3A09 */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { "roundpd", { XM, EXx, Ib } },
4418   },
4419
4420   /* PREFIX_0F3A0A */
4421   {
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { "roundss", { XM, EXd, Ib } },
4425   },
4426
4427   /* PREFIX_0F3A0B */
4428   {
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { "roundsd", { XM, EXq, Ib } },
4432   },
4433
4434   /* PREFIX_0F3A0C */
4435   {
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     { "blendps", { XM, EXx, Ib } },
4439   },
4440
4441   /* PREFIX_0F3A0D */
4442   {
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { "blendpd", { XM, EXx, Ib } },
4446   },
4447
4448   /* PREFIX_0F3A0E */
4449   {
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { "pblendw", { XM, EXx, Ib } },
4453   },
4454
4455   /* PREFIX_0F3A14 */
4456   {
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { "pextrb", { Edqb, XM, Ib } },
4460   },
4461
4462   /* PREFIX_0F3A15 */
4463   {
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { "pextrw", { Edqw, XM, Ib } },
4467   },
4468
4469   /* PREFIX_0F3A16 */
4470   {
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { "pextrK", { Edq, XM, Ib } },
4474   },
4475
4476   /* PREFIX_0F3A17 */
4477   {
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { "extractps", { Edqd, XM, Ib } },
4481   },
4482
4483   /* PREFIX_0F3A20 */
4484   {
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { "pinsrb", { XM, Edqb, Ib } },
4488   },
4489
4490   /* PREFIX_0F3A21 */
4491   {
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { "insertps", { XM, EXd, Ib } },
4495   },
4496
4497   /* PREFIX_0F3A22 */
4498   {
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { "pinsrK", { XM, Edq, Ib } },
4502   },
4503
4504   /* PREFIX_0F3A40 */
4505   {
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { "dpps",   { XM, EXx, Ib } },
4509   },
4510
4511   /* PREFIX_0F3A41 */
4512   {
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { "dppd",   { XM, EXx, Ib } },
4516   },
4517
4518   /* PREFIX_0F3A42 */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "mpsadbw", { XM, EXx, Ib } },
4523   },
4524
4525   /* PREFIX_0F3A44 */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "pclmulqdq", { XM, EXx, PCLMUL } },
4530   },
4531
4532   /* PREFIX_0F3A60 */
4533   {
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { "pcmpestrm", { XM, EXx, Ib } },
4537   },
4538
4539   /* PREFIX_0F3A61 */
4540   {
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { "pcmpestri", { XM, EXx, Ib } },
4544   },
4545
4546   /* PREFIX_0F3A62 */
4547   {
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { "pcmpistrm", { XM, EXx, Ib } },
4551   },
4552
4553   /* PREFIX_0F3A63 */
4554   {
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { "pcmpistri", { XM, EXx, Ib } },
4558   },
4559
4560   /* PREFIX_0F3ACC */
4561   {
4562     { "sha1rnds4", { XM, EXxmm, Ib } },
4563   },
4564
4565   /* PREFIX_0F3ADF */
4566   {
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { "aeskeygenassist", { XM, EXx, Ib } },
4570   },
4571
4572   /* PREFIX_VEX_0F10 */
4573   {
4574     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4575     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4576     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4577     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4578   },
4579
4580   /* PREFIX_VEX_0F11 */
4581   {
4582     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4583     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4584     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4585     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4586   },
4587
4588   /* PREFIX_VEX_0F12 */
4589   {
4590     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4591     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4592     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4593     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4594   },
4595
4596   /* PREFIX_VEX_0F16 */
4597   {
4598     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4599     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4600     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4601   },
4602
4603   /* PREFIX_VEX_0F2A */
4604   {
4605     { Bad_Opcode },
4606     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4607     { Bad_Opcode },
4608     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4609   },
4610
4611   /* PREFIX_VEX_0F2C */
4612   {
4613     { Bad_Opcode },
4614     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4615     { Bad_Opcode },
4616     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4617   },
4618
4619   /* PREFIX_VEX_0F2D */
4620   {
4621     { Bad_Opcode },
4622     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4623     { Bad_Opcode },
4624     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4625   },
4626
4627   /* PREFIX_VEX_0F2E */
4628   {
4629     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4630     { Bad_Opcode },
4631     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4632   },
4633
4634   /* PREFIX_VEX_0F2F */
4635   {
4636     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4637     { Bad_Opcode },
4638     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4639   },
4640
4641   /* PREFIX_VEX_0F41 */
4642   {
4643     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4644     { Bad_Opcode },
4645     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4646   },
4647
4648   /* PREFIX_VEX_0F42 */
4649   {
4650     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4651     { Bad_Opcode },
4652     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4653   },
4654
4655   /* PREFIX_VEX_0F44 */
4656   {
4657     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4658     { Bad_Opcode },
4659     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4660   },
4661
4662   /* PREFIX_VEX_0F45 */
4663   {
4664     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4665     { Bad_Opcode },
4666     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4667   },
4668
4669   /* PREFIX_VEX_0F46 */
4670   {
4671     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4672     { Bad_Opcode },
4673     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4674   },
4675
4676   /* PREFIX_VEX_0F47 */
4677   {
4678     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4679     { Bad_Opcode },
4680     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4681   },
4682
4683   /* PREFIX_VEX_0F4A */
4684   {
4685     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4686     { Bad_Opcode },
4687     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4688   },
4689
4690   /* PREFIX_VEX_0F4B */
4691   {
4692     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4693     { Bad_Opcode },
4694     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4695   },
4696
4697   /* PREFIX_VEX_0F51 */
4698   {
4699     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4700     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4701     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4702     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4703   },
4704
4705   /* PREFIX_VEX_0F52 */
4706   {
4707     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4708     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4709   },
4710
4711   /* PREFIX_VEX_0F53 */
4712   {
4713     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4714     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4715   },
4716
4717   /* PREFIX_VEX_0F58 */
4718   {
4719     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4720     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4721     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4722     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4723   },
4724
4725   /* PREFIX_VEX_0F59 */
4726   {
4727     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4728     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4729     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4730     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4731   },
4732
4733   /* PREFIX_VEX_0F5A */
4734   {
4735     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4736     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4737     { "vcvtpd2ps%XY", { XMM, EXx } },
4738     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4739   },
4740
4741   /* PREFIX_VEX_0F5B */
4742   {
4743     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4744     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4745     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4746   },
4747
4748   /* PREFIX_VEX_0F5C */
4749   {
4750     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4751     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4752     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4753     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4754   },
4755
4756   /* PREFIX_VEX_0F5D */
4757   {
4758     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4759     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4760     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4761     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4762   },
4763
4764   /* PREFIX_VEX_0F5E */
4765   {
4766     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4767     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4768     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4769     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4770   },
4771
4772   /* PREFIX_VEX_0F5F */
4773   {
4774     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4775     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4776     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4777     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4778   },
4779
4780   /* PREFIX_VEX_0F60 */
4781   {
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4785   },
4786
4787   /* PREFIX_VEX_0F61 */
4788   {
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4792   },
4793
4794   /* PREFIX_VEX_0F62 */
4795   {
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4799   },
4800
4801   /* PREFIX_VEX_0F63 */
4802   {
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4806   },
4807
4808   /* PREFIX_VEX_0F64 */
4809   {
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4813   },
4814
4815   /* PREFIX_VEX_0F65 */
4816   {
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4820   },
4821
4822   /* PREFIX_VEX_0F66 */
4823   {
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4827   },
4828
4829   /* PREFIX_VEX_0F67 */
4830   {
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4834   },
4835
4836   /* PREFIX_VEX_0F68 */
4837   {
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4841   },
4842
4843   /* PREFIX_VEX_0F69 */
4844   {
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4848   },
4849
4850   /* PREFIX_VEX_0F6A */
4851   {
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4855   },
4856
4857   /* PREFIX_VEX_0F6B */
4858   {
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4862   },
4863
4864   /* PREFIX_VEX_0F6C */
4865   {
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4869   },
4870
4871   /* PREFIX_VEX_0F6D */
4872   {
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4876   },
4877
4878   /* PREFIX_VEX_0F6E */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4883   },
4884
4885   /* PREFIX_VEX_0F6F */
4886   {
4887     { Bad_Opcode },
4888     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4889     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4890   },
4891
4892   /* PREFIX_VEX_0F70 */
4893   {
4894     { Bad_Opcode },
4895     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4896     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4897     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4898   },
4899
4900   /* PREFIX_VEX_0F71_REG_2 */
4901   {
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4905   },
4906
4907   /* PREFIX_VEX_0F71_REG_4 */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4912   },
4913
4914   /* PREFIX_VEX_0F71_REG_6 */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4919   },
4920
4921   /* PREFIX_VEX_0F72_REG_2 */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4926   },
4927
4928   /* PREFIX_VEX_0F72_REG_4 */
4929   {
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4933   },
4934
4935   /* PREFIX_VEX_0F72_REG_6 */
4936   {
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4940   },
4941
4942   /* PREFIX_VEX_0F73_REG_2 */
4943   {
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4947   },
4948
4949   /* PREFIX_VEX_0F73_REG_3 */
4950   {
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4954   },
4955
4956   /* PREFIX_VEX_0F73_REG_6 */
4957   {
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4961   },
4962
4963   /* PREFIX_VEX_0F73_REG_7 */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4968   },
4969
4970   /* PREFIX_VEX_0F74 */
4971   {
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4975   },
4976
4977   /* PREFIX_VEX_0F75 */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4982   },
4983
4984   /* PREFIX_VEX_0F76 */
4985   {
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4989   },
4990
4991   /* PREFIX_VEX_0F77 */
4992   {
4993     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4994   },
4995
4996   /* PREFIX_VEX_0F7C */
4997   {
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5001     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5002   },
5003
5004   /* PREFIX_VEX_0F7D */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5009     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5010   },
5011
5012   /* PREFIX_VEX_0F7E */
5013   {
5014     { Bad_Opcode },
5015     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5016     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5017   },
5018
5019   /* PREFIX_VEX_0F7F */
5020   {
5021     { Bad_Opcode },
5022     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5023     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5024   },
5025
5026   /* PREFIX_VEX_0F90 */
5027   {
5028     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5029     { Bad_Opcode },
5030     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5031   },
5032
5033   /* PREFIX_VEX_0F91 */
5034   {
5035     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5036     { Bad_Opcode },
5037     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5038   },
5039
5040   /* PREFIX_VEX_0F92 */
5041   {
5042     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5043     { Bad_Opcode },
5044     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5045     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5046   },
5047
5048   /* PREFIX_VEX_0F93 */
5049   {
5050     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5051     { Bad_Opcode },
5052     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5053     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5054   },
5055
5056   /* PREFIX_VEX_0F98 */
5057   {
5058     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5059     { Bad_Opcode },
5060     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5061   },
5062
5063   /* PREFIX_VEX_0F99 */
5064   {
5065     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5066     { Bad_Opcode },
5067     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5068   },
5069
5070   /* PREFIX_VEX_0FC2 */
5071   {
5072     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5073     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5074     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5075     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5076   },
5077
5078   /* PREFIX_VEX_0FC4 */
5079   {
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5083   },
5084
5085   /* PREFIX_VEX_0FC5 */
5086   {
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5090   },
5091
5092   /* PREFIX_VEX_0FD0 */
5093   {
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5097     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5098   },
5099
5100   /* PREFIX_VEX_0FD1 */
5101   {
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5105   },
5106
5107   /* PREFIX_VEX_0FD2 */
5108   {
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5112   },
5113
5114   /* PREFIX_VEX_0FD3 */
5115   {
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5119   },
5120
5121   /* PREFIX_VEX_0FD4 */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5126   },
5127
5128   /* PREFIX_VEX_0FD5 */
5129   {
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5133   },
5134
5135   /* PREFIX_VEX_0FD6 */
5136   {
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5140   },
5141
5142   /* PREFIX_VEX_0FD7 */
5143   {
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5147   },
5148
5149   /* PREFIX_VEX_0FD8 */
5150   {
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5154   },
5155
5156   /* PREFIX_VEX_0FD9 */
5157   {
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5161   },
5162
5163   /* PREFIX_VEX_0FDA */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5168   },
5169
5170   /* PREFIX_VEX_0FDB */
5171   {
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5175   },
5176
5177   /* PREFIX_VEX_0FDC */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5182   },
5183
5184   /* PREFIX_VEX_0FDD */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5189   },
5190
5191   /* PREFIX_VEX_0FDE */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5196   },
5197
5198   /* PREFIX_VEX_0FDF */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5203   },
5204
5205   /* PREFIX_VEX_0FE0 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5210   },
5211
5212   /* PREFIX_VEX_0FE1 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5217   },
5218
5219   /* PREFIX_VEX_0FE2 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5224   },
5225
5226   /* PREFIX_VEX_0FE3 */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5231   },
5232
5233   /* PREFIX_VEX_0FE4 */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5238   },
5239
5240   /* PREFIX_VEX_0FE5 */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5245   },
5246
5247   /* PREFIX_VEX_0FE6 */
5248   {
5249     { Bad_Opcode },
5250     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5251     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5252     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5253   },
5254
5255   /* PREFIX_VEX_0FE7 */
5256   {
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5260   },
5261
5262   /* PREFIX_VEX_0FE8 */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5267   },
5268
5269   /* PREFIX_VEX_0FE9 */
5270   {
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5274   },
5275
5276   /* PREFIX_VEX_0FEA */
5277   {
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5281   },
5282
5283   /* PREFIX_VEX_0FEB */
5284   {
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5288   },
5289
5290   /* PREFIX_VEX_0FEC */
5291   {
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5295   },
5296
5297   /* PREFIX_VEX_0FED */
5298   {
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5302   },
5303
5304   /* PREFIX_VEX_0FEE */
5305   {
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5309   },
5310
5311   /* PREFIX_VEX_0FEF */
5312   {
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5316   },
5317
5318   /* PREFIX_VEX_0FF0 */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5324   },
5325
5326   /* PREFIX_VEX_0FF1 */
5327   {
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5331   },
5332
5333   /* PREFIX_VEX_0FF2 */
5334   {
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5338   },
5339
5340   /* PREFIX_VEX_0FF3 */
5341   {
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5345   },
5346
5347   /* PREFIX_VEX_0FF4 */
5348   {
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5352   },
5353
5354   /* PREFIX_VEX_0FF5 */
5355   {
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5359   },
5360
5361   /* PREFIX_VEX_0FF6 */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5366   },
5367
5368   /* PREFIX_VEX_0FF7 */
5369   {
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5373   },
5374
5375   /* PREFIX_VEX_0FF8 */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5380   },
5381
5382   /* PREFIX_VEX_0FF9 */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5387   },
5388
5389   /* PREFIX_VEX_0FFA */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5394   },
5395
5396   /* PREFIX_VEX_0FFB */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5401   },
5402
5403   /* PREFIX_VEX_0FFC */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5408   },
5409
5410   /* PREFIX_VEX_0FFD */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5415   },
5416
5417   /* PREFIX_VEX_0FFE */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5422   },
5423
5424   /* PREFIX_VEX_0F3800 */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5429   },
5430
5431   /* PREFIX_VEX_0F3801 */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5436   },
5437
5438   /* PREFIX_VEX_0F3802 */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5443   },
5444
5445   /* PREFIX_VEX_0F3803 */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5450   },
5451
5452   /* PREFIX_VEX_0F3804 */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5457   },
5458
5459   /* PREFIX_VEX_0F3805 */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5464   },
5465
5466   /* PREFIX_VEX_0F3806 */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5471   },
5472
5473   /* PREFIX_VEX_0F3807 */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5478   },
5479
5480   /* PREFIX_VEX_0F3808 */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5485   },
5486
5487   /* PREFIX_VEX_0F3809 */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5492   },
5493
5494   /* PREFIX_VEX_0F380A */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5499   },
5500
5501   /* PREFIX_VEX_0F380B */
5502   {
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5506   },
5507
5508   /* PREFIX_VEX_0F380C */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5513   },
5514
5515   /* PREFIX_VEX_0F380D */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5520   },
5521
5522   /* PREFIX_VEX_0F380E */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5527   },
5528
5529   /* PREFIX_VEX_0F380F */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5534   },
5535
5536   /* PREFIX_VEX_0F3813 */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { "vcvtph2ps", { XM, EXxmmq } },
5541   },
5542
5543   /* PREFIX_VEX_0F3816 */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5548   },
5549
5550   /* PREFIX_VEX_0F3817 */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5555   },
5556
5557   /* PREFIX_VEX_0F3818 */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5562   },
5563
5564   /* PREFIX_VEX_0F3819 */
5565   {
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5569   },
5570
5571   /* PREFIX_VEX_0F381A */
5572   {
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5576   },
5577
5578   /* PREFIX_VEX_0F381C */
5579   {
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5583   },
5584
5585   /* PREFIX_VEX_0F381D */
5586   {
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5590   },
5591
5592   /* PREFIX_VEX_0F381E */
5593   {
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5597   },
5598
5599   /* PREFIX_VEX_0F3820 */
5600   {
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5604   },
5605
5606   /* PREFIX_VEX_0F3821 */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5611   },
5612
5613   /* PREFIX_VEX_0F3822 */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5618   },
5619
5620   /* PREFIX_VEX_0F3823 */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5625   },
5626
5627   /* PREFIX_VEX_0F3824 */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5632   },
5633
5634   /* PREFIX_VEX_0F3825 */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5639   },
5640
5641   /* PREFIX_VEX_0F3828 */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5646   },
5647
5648   /* PREFIX_VEX_0F3829 */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5653   },
5654
5655   /* PREFIX_VEX_0F382A */
5656   {
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5660   },
5661
5662   /* PREFIX_VEX_0F382B */
5663   {
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5667   },
5668
5669   /* PREFIX_VEX_0F382C */
5670   {
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5674   },
5675
5676   /* PREFIX_VEX_0F382D */
5677   {
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5681   },
5682
5683   /* PREFIX_VEX_0F382E */
5684   {
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5688   },
5689
5690   /* PREFIX_VEX_0F382F */
5691   {
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5695   },
5696
5697   /* PREFIX_VEX_0F3830 */
5698   {
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5702   },
5703
5704   /* PREFIX_VEX_0F3831 */
5705   {
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5709   },
5710
5711   /* PREFIX_VEX_0F3832 */
5712   {
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5716   },
5717
5718   /* PREFIX_VEX_0F3833 */
5719   {
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5723   },
5724
5725   /* PREFIX_VEX_0F3834 */
5726   {
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5730   },
5731
5732   /* PREFIX_VEX_0F3835 */
5733   {
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5737   },
5738
5739   /* PREFIX_VEX_0F3836 */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5744   },
5745
5746   /* PREFIX_VEX_0F3837 */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5751   },
5752
5753   /* PREFIX_VEX_0F3838 */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5758   },
5759
5760   /* PREFIX_VEX_0F3839 */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5765   },
5766
5767   /* PREFIX_VEX_0F383A */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5772   },
5773
5774   /* PREFIX_VEX_0F383B */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5779   },
5780
5781   /* PREFIX_VEX_0F383C */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5786   },
5787
5788   /* PREFIX_VEX_0F383D */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5793   },
5794
5795   /* PREFIX_VEX_0F383E */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5800   },
5801
5802   /* PREFIX_VEX_0F383F */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5807   },
5808
5809   /* PREFIX_VEX_0F3840 */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5814   },
5815
5816   /* PREFIX_VEX_0F3841 */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5821   },
5822
5823   /* PREFIX_VEX_0F3845 */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { "vpsrlv%LW", { XM, Vex, EXx } },
5828   },
5829
5830   /* PREFIX_VEX_0F3846 */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5835   },
5836
5837   /* PREFIX_VEX_0F3847 */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { "vpsllv%LW", { XM, Vex, EXx } },
5842   },
5843
5844   /* PREFIX_VEX_0F3858 */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5849   },
5850
5851   /* PREFIX_VEX_0F3859 */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5856   },
5857
5858   /* PREFIX_VEX_0F385A */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5863   },
5864
5865   /* PREFIX_VEX_0F3878 */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5870   },
5871
5872   /* PREFIX_VEX_0F3879 */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5877   },
5878
5879   /* PREFIX_VEX_0F388C */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5884   },
5885
5886   /* PREFIX_VEX_0F388E */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5891   },
5892
5893   /* PREFIX_VEX_0F3890 */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5898   },
5899
5900   /* PREFIX_VEX_0F3891 */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5905   },
5906
5907   /* PREFIX_VEX_0F3892 */
5908   {
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5912   },
5913
5914   /* PREFIX_VEX_0F3893 */
5915   {
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5919   },
5920
5921   /* PREFIX_VEX_0F3896 */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5926   },
5927
5928   /* PREFIX_VEX_0F3897 */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5933   },
5934
5935   /* PREFIX_VEX_0F3898 */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { "vfmadd132p%XW", { XM, Vex, EXx } },
5940   },
5941
5942   /* PREFIX_VEX_0F3899 */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5947   },
5948
5949   /* PREFIX_VEX_0F389A */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { "vfmsub132p%XW", { XM, Vex, EXx } },
5954   },
5955
5956   /* PREFIX_VEX_0F389B */
5957   {
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5961   },
5962
5963   /* PREFIX_VEX_0F389C */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5968   },
5969
5970   /* PREFIX_VEX_0F389D */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5975   },
5976
5977   /* PREFIX_VEX_0F389E */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5982   },
5983
5984   /* PREFIX_VEX_0F389F */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5989   },
5990
5991   /* PREFIX_VEX_0F38A6 */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5996     { Bad_Opcode },
5997   },
5998
5999   /* PREFIX_VEX_0F38A7 */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
6004   },
6005
6006   /* PREFIX_VEX_0F38A8 */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { "vfmadd213p%XW", { XM, Vex, EXx } },
6011   },
6012
6013   /* PREFIX_VEX_0F38A9 */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6018   },
6019
6020   /* PREFIX_VEX_0F38AA */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { "vfmsub213p%XW", { XM, Vex, EXx } },
6025   },
6026
6027   /* PREFIX_VEX_0F38AB */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6032   },
6033
6034   /* PREFIX_VEX_0F38AC */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { "vfnmadd213p%XW", { XM, Vex, EXx } },
6039   },
6040
6041   /* PREFIX_VEX_0F38AD */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6046   },
6047
6048   /* PREFIX_VEX_0F38AE */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { "vfnmsub213p%XW", { XM, Vex, EXx } },
6053   },
6054
6055   /* PREFIX_VEX_0F38AF */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6060   },
6061
6062   /* PREFIX_VEX_0F38B6 */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
6067   },
6068
6069   /* PREFIX_VEX_0F38B7 */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
6074   },
6075
6076   /* PREFIX_VEX_0F38B8 */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfmadd231p%XW", { XM, Vex, EXx } },
6081   },
6082
6083   /* PREFIX_VEX_0F38B9 */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6088   },
6089
6090   /* PREFIX_VEX_0F38BA */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { "vfmsub231p%XW", { XM, Vex, EXx } },
6095   },
6096
6097   /* PREFIX_VEX_0F38BB */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6102   },
6103
6104   /* PREFIX_VEX_0F38BC */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "vfnmadd231p%XW", { XM, Vex, EXx } },
6109   },
6110
6111   /* PREFIX_VEX_0F38BD */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6116   },
6117
6118   /* PREFIX_VEX_0F38BE */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { "vfnmsub231p%XW", { XM, Vex, EXx } },
6123   },
6124
6125   /* PREFIX_VEX_0F38BF */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6130   },
6131
6132   /* PREFIX_VEX_0F38DB */
6133   {
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6137   },
6138
6139   /* PREFIX_VEX_0F38DC */
6140   {
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6144   },
6145
6146   /* PREFIX_VEX_0F38DD */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6151   },
6152
6153   /* PREFIX_VEX_0F38DE */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6158   },
6159
6160   /* PREFIX_VEX_0F38DF */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6165   },
6166
6167   /* PREFIX_VEX_0F38F2 */
6168   {
6169     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6170   },
6171
6172   /* PREFIX_VEX_0F38F3_REG_1 */
6173   {
6174     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6175   },
6176
6177   /* PREFIX_VEX_0F38F3_REG_2 */
6178   {
6179     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6180   },
6181
6182   /* PREFIX_VEX_0F38F3_REG_3 */
6183   {
6184     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6185   },
6186
6187   /* PREFIX_VEX_0F38F5 */
6188   {
6189     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6190     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6191     { Bad_Opcode },
6192     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6193   },
6194
6195   /* PREFIX_VEX_0F38F6 */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6201   },
6202
6203   /* PREFIX_VEX_0F38F7 */
6204   {
6205     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6206     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6207     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6208     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6209   },
6210
6211   /* PREFIX_VEX_0F3A00 */
6212   {
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6216   },
6217
6218   /* PREFIX_VEX_0F3A01 */
6219   {
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6223   },
6224
6225   /* PREFIX_VEX_0F3A02 */
6226   {
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6230   },
6231
6232   /* PREFIX_VEX_0F3A04 */
6233   {
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6237   },
6238
6239   /* PREFIX_VEX_0F3A05 */
6240   {
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6244   },
6245
6246   /* PREFIX_VEX_0F3A06 */
6247   {
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6251   },
6252
6253   /* PREFIX_VEX_0F3A08 */
6254   {
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6258   },
6259
6260   /* PREFIX_VEX_0F3A09 */
6261   {
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6265   },
6266
6267   /* PREFIX_VEX_0F3A0A */
6268   {
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6272   },
6273
6274   /* PREFIX_VEX_0F3A0B */
6275   {
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6279   },
6280
6281   /* PREFIX_VEX_0F3A0C */
6282   {
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6286   },
6287
6288   /* PREFIX_VEX_0F3A0D */
6289   {
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6293   },
6294
6295   /* PREFIX_VEX_0F3A0E */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6300   },
6301
6302   /* PREFIX_VEX_0F3A0F */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6307   },
6308
6309   /* PREFIX_VEX_0F3A14 */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6314   },
6315
6316   /* PREFIX_VEX_0F3A15 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6321   },
6322
6323   /* PREFIX_VEX_0F3A16 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6328   },
6329
6330   /* PREFIX_VEX_0F3A17 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6335   },
6336
6337   /* PREFIX_VEX_0F3A18 */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6342   },
6343
6344   /* PREFIX_VEX_0F3A19 */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6349   },
6350
6351   /* PREFIX_VEX_0F3A1D */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { "vcvtps2ph", { EXxmmq, XM, Ib } },
6356   },
6357
6358   /* PREFIX_VEX_0F3A20 */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6363   },
6364
6365   /* PREFIX_VEX_0F3A21 */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6370   },
6371
6372   /* PREFIX_VEX_0F3A22 */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6377   },
6378
6379   /* PREFIX_VEX_0F3A30 */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6384   },
6385
6386   /* PREFIX_VEX_0F3A31 */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6391   },
6392
6393   /* PREFIX_VEX_0F3A32 */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6398   },
6399
6400   /* PREFIX_VEX_0F3A33 */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6405   },
6406
6407   /* PREFIX_VEX_0F3A38 */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6412   },
6413
6414   /* PREFIX_VEX_0F3A39 */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6419   },
6420
6421   /* PREFIX_VEX_0F3A40 */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6426   },
6427
6428   /* PREFIX_VEX_0F3A41 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A42 */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6440   },
6441
6442   /* PREFIX_VEX_0F3A44 */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6447   },
6448
6449   /* PREFIX_VEX_0F3A46 */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F3A48 */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6461   },
6462
6463   /* PREFIX_VEX_0F3A49 */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6468   },
6469
6470   /* PREFIX_VEX_0F3A4A */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6475   },
6476
6477   /* PREFIX_VEX_0F3A4B */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6482   },
6483
6484   /* PREFIX_VEX_0F3A4C */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6489   },
6490
6491   /* PREFIX_VEX_0F3A5C */
6492   {
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6496   },
6497
6498   /* PREFIX_VEX_0F3A5D */
6499   {
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6503   },
6504
6505   /* PREFIX_VEX_0F3A5E */
6506   {
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6510   },
6511
6512   /* PREFIX_VEX_0F3A5F */
6513   {
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6517   },
6518
6519   /* PREFIX_VEX_0F3A60 */
6520   {
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6524     { Bad_Opcode },
6525   },
6526
6527   /* PREFIX_VEX_0F3A61 */
6528   {
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6532   },
6533
6534   /* PREFIX_VEX_0F3A62 */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6539   },
6540
6541   /* PREFIX_VEX_0F3A63 */
6542   {
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6546   },
6547
6548   /* PREFIX_VEX_0F3A68 */
6549   {
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6553   },
6554
6555   /* PREFIX_VEX_0F3A69 */
6556   {
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6560   },
6561
6562   /* PREFIX_VEX_0F3A6A */
6563   {
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6567   },
6568
6569   /* PREFIX_VEX_0F3A6B */
6570   {
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6574   },
6575
6576   /* PREFIX_VEX_0F3A6C */
6577   {
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6581   },
6582
6583   /* PREFIX_VEX_0F3A6D */
6584   {
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6588   },
6589
6590   /* PREFIX_VEX_0F3A6E */
6591   {
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6595   },
6596
6597   /* PREFIX_VEX_0F3A6F */
6598   {
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6602   },
6603
6604   /* PREFIX_VEX_0F3A78 */
6605   {
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6609   },
6610
6611   /* PREFIX_VEX_0F3A79 */
6612   {
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6616   },
6617
6618   /* PREFIX_VEX_0F3A7A */
6619   {
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6623   },
6624
6625   /* PREFIX_VEX_0F3A7B */
6626   {
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6630   },
6631
6632   /* PREFIX_VEX_0F3A7C */
6633   {
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6637     { Bad_Opcode },
6638   },
6639
6640   /* PREFIX_VEX_0F3A7D */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6645   },
6646
6647   /* PREFIX_VEX_0F3A7E */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6652   },
6653
6654   /* PREFIX_VEX_0F3A7F */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6659   },
6660
6661   /* PREFIX_VEX_0F3ADF */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6666   },
6667
6668   /* PREFIX_VEX_0F3AF0 */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6674   },
6675
6676 #define NEED_PREFIX_TABLE
6677 #include "i386-dis-evex.h"
6678 #undef NEED_PREFIX_TABLE
6679 };
6680
6681 static const struct dis386 x86_64_table[][2] = {
6682   /* X86_64_06 */
6683   {
6684     { "pushP", { es } },
6685   },
6686
6687   /* X86_64_07 */
6688   {
6689     { "popP", { es } },
6690   },
6691
6692   /* X86_64_0D */
6693   {
6694     { "pushP", { cs } },
6695   },
6696
6697   /* X86_64_16 */
6698   {
6699     { "pushP", { ss } },
6700   },
6701
6702   /* X86_64_17 */
6703   {
6704     { "popP", { ss } },
6705   },
6706
6707   /* X86_64_1E */
6708   {
6709     { "pushP", { ds } },
6710   },
6711
6712   /* X86_64_1F */
6713   {
6714     { "popP", { ds } },
6715   },
6716
6717   /* X86_64_27 */
6718   {
6719     { "daa", { XX } },
6720   },
6721
6722   /* X86_64_2F */
6723   {
6724     { "das", { XX } },
6725   },
6726
6727   /* X86_64_37 */
6728   {
6729     { "aaa", { XX } },
6730   },
6731
6732   /* X86_64_3F */
6733   {
6734     { "aas", { XX } },
6735   },
6736
6737   /* X86_64_60 */
6738   {
6739     { "pushaP", { XX } },
6740   },
6741
6742   /* X86_64_61 */
6743   {
6744     { "popaP", { XX } },
6745   },
6746
6747   /* X86_64_62 */
6748   {
6749     { MOD_TABLE (MOD_62_32BIT) },
6750     { EVEX_TABLE (EVEX_0F) },
6751   },
6752
6753   /* X86_64_63 */
6754   {
6755     { "arpl", { Ew, Gw } },
6756     { "movs{lq|xd}", { Gv, Ed } },
6757   },
6758
6759   /* X86_64_6D */
6760   {
6761     { "ins{R|}", { Yzr, indirDX } },
6762     { "ins{G|}", { Yzr, indirDX } },
6763   },
6764
6765   /* X86_64_6F */
6766   {
6767     { "outs{R|}", { indirDXr, Xz } },
6768     { "outs{G|}", { indirDXr, Xz } },
6769   },
6770
6771   /* X86_64_9A */
6772   {
6773     { "Jcall{T|}", { Ap } },
6774   },
6775
6776   /* X86_64_C4 */
6777   {
6778     { MOD_TABLE (MOD_C4_32BIT) },
6779     { VEX_C4_TABLE (VEX_0F) },
6780   },
6781
6782   /* X86_64_C5 */
6783   {
6784     { MOD_TABLE (MOD_C5_32BIT) },
6785     { VEX_C5_TABLE (VEX_0F) },
6786   },
6787
6788   /* X86_64_CE */
6789   {
6790     { "into", { XX } },
6791   },
6792
6793   /* X86_64_D4 */
6794   {
6795     { "aam", { Ib } },
6796   },
6797
6798   /* X86_64_D5 */
6799   {
6800     { "aad", { Ib } },
6801   },
6802
6803   /* X86_64_EA */
6804   {
6805     { "Jjmp{T|}", { Ap } },
6806   },
6807
6808   /* X86_64_0F01_REG_0 */
6809   {
6810     { "sgdt{Q|IQ}", { M } },
6811     { "sgdt", { M } },
6812   },
6813
6814   /* X86_64_0F01_REG_1 */
6815   {
6816     { "sidt{Q|IQ}", { M } },
6817     { "sidt", { M } },
6818   },
6819
6820   /* X86_64_0F01_REG_2 */
6821   {
6822     { "lgdt{Q|Q}", { M } },
6823     { "lgdt", { M } },
6824   },
6825
6826   /* X86_64_0F01_REG_3 */
6827   {
6828     { "lidt{Q|Q}", { M } },
6829     { "lidt", { M } },
6830   },
6831 };
6832
6833 static const struct dis386 three_byte_table[][256] = {
6834
6835   /* THREE_BYTE_0F38 */
6836   {
6837     /* 00 */
6838     { "pshufb",         { MX, EM } },
6839     { "phaddw",         { MX, EM } },
6840     { "phaddd",         { MX, EM } },
6841     { "phaddsw",        { MX, EM } },
6842     { "pmaddubsw",      { MX, EM } },
6843     { "phsubw",         { MX, EM } },
6844     { "phsubd",         { MX, EM } },
6845     { "phsubsw",        { MX, EM } },
6846     /* 08 */
6847     { "psignb",         { MX, EM } },
6848     { "psignw",         { MX, EM } },
6849     { "psignd",         { MX, EM } },
6850     { "pmulhrsw",       { MX, EM } },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     /* 10 */
6856     { PREFIX_TABLE (PREFIX_0F3810) },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { PREFIX_TABLE (PREFIX_0F3814) },
6861     { PREFIX_TABLE (PREFIX_0F3815) },
6862     { Bad_Opcode },
6863     { PREFIX_TABLE (PREFIX_0F3817) },
6864     /* 18 */
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { "pabsb",          { MX, EM } },
6870     { "pabsw",          { MX, EM } },
6871     { "pabsd",          { MX, EM } },
6872     { Bad_Opcode },
6873     /* 20 */
6874     { PREFIX_TABLE (PREFIX_0F3820) },
6875     { PREFIX_TABLE (PREFIX_0F3821) },
6876     { PREFIX_TABLE (PREFIX_0F3822) },
6877     { PREFIX_TABLE (PREFIX_0F3823) },
6878     { PREFIX_TABLE (PREFIX_0F3824) },
6879     { PREFIX_TABLE (PREFIX_0F3825) },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     /* 28 */
6883     { PREFIX_TABLE (PREFIX_0F3828) },
6884     { PREFIX_TABLE (PREFIX_0F3829) },
6885     { PREFIX_TABLE (PREFIX_0F382A) },
6886     { PREFIX_TABLE (PREFIX_0F382B) },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     /* 30 */
6892     { PREFIX_TABLE (PREFIX_0F3830) },
6893     { PREFIX_TABLE (PREFIX_0F3831) },
6894     { PREFIX_TABLE (PREFIX_0F3832) },
6895     { PREFIX_TABLE (PREFIX_0F3833) },
6896     { PREFIX_TABLE (PREFIX_0F3834) },
6897     { PREFIX_TABLE (PREFIX_0F3835) },
6898     { Bad_Opcode },
6899     { PREFIX_TABLE (PREFIX_0F3837) },
6900     /* 38 */
6901     { PREFIX_TABLE (PREFIX_0F3838) },
6902     { PREFIX_TABLE (PREFIX_0F3839) },
6903     { PREFIX_TABLE (PREFIX_0F383A) },
6904     { PREFIX_TABLE (PREFIX_0F383B) },
6905     { PREFIX_TABLE (PREFIX_0F383C) },
6906     { PREFIX_TABLE (PREFIX_0F383D) },
6907     { PREFIX_TABLE (PREFIX_0F383E) },
6908     { PREFIX_TABLE (PREFIX_0F383F) },
6909     /* 40 */
6910     { PREFIX_TABLE (PREFIX_0F3840) },
6911     { PREFIX_TABLE (PREFIX_0F3841) },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     /* 48 */
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     /* 50 */
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     /* 58 */
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     /* 60 */
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     /* 68 */
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     /* 70 */
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     /* 78 */
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     /* 80 */
6982     { PREFIX_TABLE (PREFIX_0F3880) },
6983     { PREFIX_TABLE (PREFIX_0F3881) },
6984     { PREFIX_TABLE (PREFIX_0F3882) },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     /* 88 */
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     /* 90 */
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     /* 98 */
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     /* a0 */
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     /* a8 */
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     /* b0 */
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     /* b8 */
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     /* c0 */
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     /* c8 */
7063     { PREFIX_TABLE (PREFIX_0F38C8) },
7064     { PREFIX_TABLE (PREFIX_0F38C9) },
7065     { PREFIX_TABLE (PREFIX_0F38CA) },
7066     { PREFIX_TABLE (PREFIX_0F38CB) },
7067     { PREFIX_TABLE (PREFIX_0F38CC) },
7068     { PREFIX_TABLE (PREFIX_0F38CD) },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     /* d0 */
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     /* d8 */
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { PREFIX_TABLE (PREFIX_0F38DB) },
7085     { PREFIX_TABLE (PREFIX_0F38DC) },
7086     { PREFIX_TABLE (PREFIX_0F38DD) },
7087     { PREFIX_TABLE (PREFIX_0F38DE) },
7088     { PREFIX_TABLE (PREFIX_0F38DF) },
7089     /* e0 */
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     /* e8 */
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     /* f0 */
7108     { PREFIX_TABLE (PREFIX_0F38F0) },
7109     { PREFIX_TABLE (PREFIX_0F38F1) },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { PREFIX_TABLE (PREFIX_0F38F6) },
7115     { Bad_Opcode },
7116     /* f8 */
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125   },
7126   /* THREE_BYTE_0F3A */
7127   {
7128     /* 00 */
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     /* 08 */
7138     { PREFIX_TABLE (PREFIX_0F3A08) },
7139     { PREFIX_TABLE (PREFIX_0F3A09) },
7140     { PREFIX_TABLE (PREFIX_0F3A0A) },
7141     { PREFIX_TABLE (PREFIX_0F3A0B) },
7142     { PREFIX_TABLE (PREFIX_0F3A0C) },
7143     { PREFIX_TABLE (PREFIX_0F3A0D) },
7144     { PREFIX_TABLE (PREFIX_0F3A0E) },
7145     { "palignr",        { MX, EM, Ib } },
7146     /* 10 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { PREFIX_TABLE (PREFIX_0F3A14) },
7152     { PREFIX_TABLE (PREFIX_0F3A15) },
7153     { PREFIX_TABLE (PREFIX_0F3A16) },
7154     { PREFIX_TABLE (PREFIX_0F3A17) },
7155     /* 18 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* 20 */
7165     { PREFIX_TABLE (PREFIX_0F3A20) },
7166     { PREFIX_TABLE (PREFIX_0F3A21) },
7167     { PREFIX_TABLE (PREFIX_0F3A22) },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* 28 */
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     /* 30 */
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     /* 38 */
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* 40 */
7201     { PREFIX_TABLE (PREFIX_0F3A40) },
7202     { PREFIX_TABLE (PREFIX_0F3A41) },
7203     { PREFIX_TABLE (PREFIX_0F3A42) },
7204     { Bad_Opcode },
7205     { PREFIX_TABLE (PREFIX_0F3A44) },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     /* 48 */
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     /* 50 */
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     /* 58 */
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     /* 60 */
7237     { PREFIX_TABLE (PREFIX_0F3A60) },
7238     { PREFIX_TABLE (PREFIX_0F3A61) },
7239     { PREFIX_TABLE (PREFIX_0F3A62) },
7240     { PREFIX_TABLE (PREFIX_0F3A63) },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     /* 68 */
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     /* 70 */
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     /* 78 */
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     /* 80 */
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     /* 88 */
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     /* 90 */
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     /* 98 */
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     /* a0 */
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     /* a8 */
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     /* b0 */
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     /* b8 */
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     /* c0 */
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     /* c8 */
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { PREFIX_TABLE (PREFIX_0F3ACC) },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     /* d0 */
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     /* d8 */
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { PREFIX_TABLE (PREFIX_0F3ADF) },
7380     /* e0 */
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     /* e8 */
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     /* f0 */
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     /* f8 */
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416   },
7417
7418   /* THREE_BYTE_0F7A */
7419   {
7420     /* 00 */
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     /* 08 */
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     /* 10 */
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     /* 18 */
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     /* 20 */
7457     { "ptest",          { XX } },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     /* 28 */
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     /* 30 */
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     /* 38 */
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     /* 40 */
7493     { Bad_Opcode },
7494     { "phaddbw",        { XM, EXq } },
7495     { "phaddbd",        { XM, EXq } },
7496     { "phaddbq",        { XM, EXq } },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { "phaddwd",        { XM, EXq } },
7500     { "phaddwq",        { XM, EXq } },
7501     /* 48 */
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { "phadddq",        { XM, EXq } },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     /* 50 */
7511     { Bad_Opcode },
7512     { "phaddubw",       { XM, EXq } },
7513     { "phaddubd",       { XM, EXq } },
7514     { "phaddubq",       { XM, EXq } },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { "phadduwd",       { XM, EXq } },
7518     { "phadduwq",       { XM, EXq } },
7519     /* 58 */
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { "phaddudq",       { XM, EXq } },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     /* 60 */
7529     { Bad_Opcode },
7530     { "phsubbw",        { XM, EXq } },
7531     { "phsubbd",        { XM, EXq } },
7532     { "phsubbq",        { XM, EXq } },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     /* 68 */
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     /* 70 */
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     /* 78 */
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     /* 80 */
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     /* 88 */
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     /* 90 */
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     /* 98 */
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     /* a0 */
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     /* a8 */
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     /* b0 */
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     /* b8 */
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     /* c0 */
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     /* c8 */
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     /* d0 */
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     /* d8 */
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     /* e0 */
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     /* e8 */
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     /* f0 */
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     /* f8 */
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708   },
7709 };
7710
7711 static const struct dis386 xop_table[][256] = {
7712   /* XOP_08 */
7713   {
7714     /* 00 */
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     /* 08 */
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     /* 10 */
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     /* 18 */
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     /* 20 */
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     /* 28 */
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     /* 30 */
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     /* 38 */
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     /* 40 */
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     /* 48 */
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     /* 50 */
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     /* 58 */
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     /* 60 */
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     /* 68 */
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     /* 70 */
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     /* 78 */
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     /* 80 */
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7865     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7866     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7867     /* 88 */
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7875     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7876     /* 90 */
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7883     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7884     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7885     /* 98 */
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7893     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7894     /* a0 */
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7898     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7902     { Bad_Opcode },
7903     /* a8 */
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     /* b0 */
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7920     { Bad_Opcode },
7921     /* b8 */
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     /* c0 */
7931     { "vprotb",         { XM, Vex_2src_1, Ib } },
7932     { "vprotw",         { XM, Vex_2src_1, Ib } },
7933     { "vprotd",         { XM, Vex_2src_1, Ib } },
7934     { "vprotq",         { XM, Vex_2src_1, Ib } },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     /* c8 */
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7945     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7946     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7947     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7948     /* d0 */
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     /* d8 */
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     /* e0 */
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     /* e8 */
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7981     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7982     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7983     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7984     /* f0 */
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     /* f8 */
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002   },
8003   /* XOP_09 */
8004   {
8005     /* 00 */
8006     { Bad_Opcode },
8007     { REG_TABLE (REG_XOP_TBM_01) },
8008     { REG_TABLE (REG_XOP_TBM_02) },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     /* 08 */
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     /* 10 */
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { REG_TABLE (REG_XOP_LWPCB) },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     /* 18 */
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     /* 20 */
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     /* 28 */
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     /* 30 */
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     /* 38 */
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     /* 40 */
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     /* 48 */
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     /* 50 */
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     /* 58 */
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     /* 60 */
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     /* 68 */
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     /* 70 */
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     /* 78 */
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     /* 80 */
8150     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8151     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8152     { "vfrczss",        { XM, EXd } },
8153     { "vfrczsd",        { XM, EXq } },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     /* 88 */
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     /* 90 */
8168     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
8169     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
8170     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
8171     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
8172     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
8173     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
8174     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
8175     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
8176     /* 98 */
8177     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
8178     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
8179     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
8180     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     /* a0 */
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     /* a8 */
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     /* b0 */
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     /* b8 */
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     /* c0 */
8222     { Bad_Opcode },
8223     { "vphaddbw",       { XM, EXxmm } },
8224     { "vphaddbd",       { XM, EXxmm } },
8225     { "vphaddbq",       { XM, EXxmm } },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { "vphaddwd",       { XM, EXxmm } },
8229     { "vphaddwq",       { XM, EXxmm } },
8230     /* c8 */
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { "vphadddq",       { XM, EXxmm } },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     /* d0 */
8240     { Bad_Opcode },
8241     { "vphaddubw",      { XM, EXxmm } },
8242     { "vphaddubd",      { XM, EXxmm } },
8243     { "vphaddubq",      { XM, EXxmm } },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { "vphadduwd",      { XM, EXxmm } },
8247     { "vphadduwq",      { XM, EXxmm } },
8248     /* d8 */
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { "vphaddudq",      { XM, EXxmm } },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     /* e0 */
8258     { Bad_Opcode },
8259     { "vphsubbw",       { XM, EXxmm } },
8260     { "vphsubwd",       { XM, EXxmm } },
8261     { "vphsubdq",       { XM, EXxmm } },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     /* e8 */
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     /* f0 */
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     /* f8 */
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293   },
8294   /* XOP_0A */
8295   {
8296     /* 00 */
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     /* 08 */
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     /* 10 */
8315     { "bextr",  { Gv, Ev, Iq } },
8316     { Bad_Opcode },
8317     { REG_TABLE (REG_XOP_LWP) },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     /* 18 */
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     /* 20 */
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     /* 28 */
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     /* 30 */
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     /* 38 */
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     /* 40 */
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     /* 48 */
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     /* 50 */
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     /* 58 */
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     /* 60 */
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     /* 68 */
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     /* 70 */
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     /* 78 */
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     /* 80 */
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     /* 88 */
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     /* 90 */
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     /* 98 */
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     /* a0 */
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     /* a8 */
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     /* b0 */
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     /* b8 */
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     /* c0 */
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     /* c8 */
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     /* d0 */
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     /* d8 */
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     /* e0 */
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     /* e8 */
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     /* f0 */
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     /* f8 */
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584   },
8585 };
8586
8587 static const struct dis386 vex_table[][256] = {
8588   /* VEX_0F */
8589   {
8590     /* 00 */
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     /* 08 */
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     /* 10 */
8609     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8612     { MOD_TABLE (MOD_VEX_0F13) },
8613     { VEX_W_TABLE (VEX_W_0F14) },
8614     { VEX_W_TABLE (VEX_W_0F15) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8616     { MOD_TABLE (MOD_VEX_0F17) },
8617     /* 18 */
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     /* 20 */
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     /* 28 */
8636     { VEX_W_TABLE (VEX_W_0F28) },
8637     { VEX_W_TABLE (VEX_W_0F29) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8639     { MOD_TABLE (MOD_VEX_0F2B) },
8640     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8641     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8644     /* 30 */
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     /* 38 */
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     /* 40 */
8663     { Bad_Opcode },
8664     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8666     { Bad_Opcode },
8667     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8671     /* 48 */
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     /* 50 */
8681     { MOD_TABLE (MOD_VEX_0F50) },
8682     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8684     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8685     { "vandpX",         { XM, Vex, EXx } },
8686     { "vandnpX",        { XM, Vex, EXx } },
8687     { "vorpX",          { XM, Vex, EXx } },
8688     { "vxorpX",         { XM, Vex, EXx } },
8689     /* 58 */
8690     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8691     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8698     /* 60 */
8699     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8707     /* 68 */
8708     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8716     /* 70 */
8717     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8718     { REG_TABLE (REG_VEX_0F71) },
8719     { REG_TABLE (REG_VEX_0F72) },
8720     { REG_TABLE (REG_VEX_0F73) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8725     /* 78 */
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8734     /* 80 */
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     /* 88 */
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     /* 90 */
8753     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     /* 98 */
8762     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     /* a0 */
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     /* a8 */
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { REG_TABLE (REG_VEX_0FAE) },
8787     { Bad_Opcode },
8788     /* b0 */
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     /* b8 */
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     /* c0 */
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8810     { Bad_Opcode },
8811     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8812     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8813     { "vshufpX",        { XM, Vex, EXx, Ib } },
8814     { Bad_Opcode },
8815     /* c8 */
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     /* d0 */
8825     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8826     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8827     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8828     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8829     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8830     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8831     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8832     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8833     /* d8 */
8834     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8835     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8836     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8837     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8838     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8839     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8840     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8841     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8842     /* e0 */
8843     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8844     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8845     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8846     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8847     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8848     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8849     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8850     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8851     /* e8 */
8852     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8853     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8854     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8855     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8856     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8857     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8858     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8859     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8860     /* f0 */
8861     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8862     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8863     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8865     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8866     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8867     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8868     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8869     /* f8 */
8870     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8871     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8872     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8873     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8874     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8875     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8876     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8877     { Bad_Opcode },
8878   },
8879   /* VEX_0F38 */
8880   {
8881     /* 00 */
8882     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8890     /* 08 */
8891     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8899     /* 10 */
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8908     /* 18 */
8909     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8912     { Bad_Opcode },
8913     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8916     { Bad_Opcode },
8917     /* 20 */
8918     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     /* 28 */
8927     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8935     /* 30 */
8936     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8944     /* 38 */
8945     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8953     /* 40 */
8954     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8962     /* 48 */
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     /* 50 */
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     /* 58 */
8981     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     /* 60 */
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     /* 68 */
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     /* 70 */
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     /* 78 */
9017     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     /* 80 */
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     /* 88 */
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9040     { Bad_Opcode },
9041     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9042     { Bad_Opcode },
9043     /* 90 */
9044     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9052     /* 98 */
9053     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9061     /* a0 */
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9070     /* a8 */
9071     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9079     /* b0 */
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9088     /* b8 */
9089     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9097     /* c0 */
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     /* c8 */
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     /* d0 */
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     /* d8 */
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9133     /* e0 */
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     /* e8 */
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     /* f0 */
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9155     { REG_TABLE (REG_VEX_0F38F3) },
9156     { Bad_Opcode },
9157     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9160     /* f8 */
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169   },
9170   /* VEX_0F3A */
9171   {
9172     /* 00 */
9173     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9176     { Bad_Opcode },
9177     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9178     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9179     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9180     { Bad_Opcode },
9181     /* 08 */
9182     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9183     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9186     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9190     /* 10 */
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9197     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9198     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9199     /* 18 */
9200     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9201     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     /* 20 */
9209     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9210     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9211     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     /* 28 */
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     /* 30 */
9227     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9228     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9229     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9230     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     /* 38 */
9236     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9237     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     /* 40 */
9245     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9246     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9247     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9248     { Bad_Opcode },
9249     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9250     { Bad_Opcode },
9251     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9252     { Bad_Opcode },
9253     /* 48 */
9254     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9255     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9256     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9257     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9258     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     /* 50 */
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     /* 58 */
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9277     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9278     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9279     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9280     /* 60 */
9281     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9282     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9283     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9284     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     /* 68 */
9290     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9292     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9293     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9295     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9296     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9297     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9298     /* 70 */
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     /* 78 */
9308     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9309     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9316     /* 80 */
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     /* 88 */
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     /* 90 */
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     /* 98 */
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     /* a0 */
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     /* a8 */
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     /* b0 */
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     /* b8 */
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     /* c0 */
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     /* c8 */
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     /* d0 */
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     /* d8 */
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9424     /* e0 */
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     /* e8 */
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     /* f0 */
9443     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     /* f8 */
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460   },
9461 };
9462
9463 #define NEED_OPCODE_TABLE
9464 #include "i386-dis-evex.h"
9465 #undef NEED_OPCODE_TABLE
9466 static const struct dis386 vex_len_table[][2] = {
9467   /* VEX_LEN_0F10_P_1 */
9468   {
9469     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9470     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9471   },
9472
9473   /* VEX_LEN_0F10_P_3 */
9474   {
9475     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9476     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9477   },
9478
9479   /* VEX_LEN_0F11_P_1 */
9480   {
9481     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9482     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9483   },
9484
9485   /* VEX_LEN_0F11_P_3 */
9486   {
9487     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9488     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9489   },
9490
9491   /* VEX_LEN_0F12_P_0_M_0 */
9492   {
9493     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9494   },
9495
9496   /* VEX_LEN_0F12_P_0_M_1 */
9497   {
9498     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9499   },
9500
9501   /* VEX_LEN_0F12_P_2 */
9502   {
9503     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9504   },
9505
9506   /* VEX_LEN_0F13_M_0 */
9507   {
9508     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9509   },
9510
9511   /* VEX_LEN_0F16_P_0_M_0 */
9512   {
9513     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9514   },
9515
9516   /* VEX_LEN_0F16_P_0_M_1 */
9517   {
9518     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9519   },
9520
9521   /* VEX_LEN_0F16_P_2 */
9522   {
9523     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9524   },
9525
9526   /* VEX_LEN_0F17_M_0 */
9527   {
9528     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9529   },
9530
9531   /* VEX_LEN_0F2A_P_1 */
9532   {
9533     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9534     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9535   },
9536
9537   /* VEX_LEN_0F2A_P_3 */
9538   {
9539     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9540     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9541   },
9542
9543   /* VEX_LEN_0F2C_P_1 */
9544   {
9545     { "vcvttss2siY",    { Gv, EXdScalar } },
9546     { "vcvttss2siY",    { Gv, EXdScalar } },
9547   },
9548
9549   /* VEX_LEN_0F2C_P_3 */
9550   {
9551     { "vcvttsd2siY",    { Gv, EXqScalar } },
9552     { "vcvttsd2siY",    { Gv, EXqScalar } },
9553   },
9554
9555   /* VEX_LEN_0F2D_P_1 */
9556   {
9557     { "vcvtss2siY",     { Gv, EXdScalar } },
9558     { "vcvtss2siY",     { Gv, EXdScalar } },
9559   },
9560
9561   /* VEX_LEN_0F2D_P_3 */
9562   {
9563     { "vcvtsd2siY",     { Gv, EXqScalar } },
9564     { "vcvtsd2siY",     { Gv, EXqScalar } },
9565   },
9566
9567   /* VEX_LEN_0F2E_P_0 */
9568   {
9569     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9570     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9571   },
9572
9573   /* VEX_LEN_0F2E_P_2 */
9574   {
9575     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9576     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9577   },
9578
9579   /* VEX_LEN_0F2F_P_0 */
9580   {
9581     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9582     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9583   },
9584
9585   /* VEX_LEN_0F2F_P_2 */
9586   {
9587     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9588     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9589   },
9590
9591   /* VEX_LEN_0F41_P_0 */
9592   {
9593     { Bad_Opcode },
9594     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9595   },
9596   /* VEX_LEN_0F41_P_2 */
9597   {
9598     { Bad_Opcode },
9599     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9600   },
9601   /* VEX_LEN_0F42_P_0 */
9602   {
9603     { Bad_Opcode },
9604     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9605   },
9606   /* VEX_LEN_0F42_P_2 */
9607   {
9608     { Bad_Opcode },
9609     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9610   },
9611   /* VEX_LEN_0F44_P_0 */
9612   {
9613     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9614   },
9615   /* VEX_LEN_0F44_P_2 */
9616   {
9617     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9618   },
9619   /* VEX_LEN_0F45_P_0 */
9620   {
9621     { Bad_Opcode },
9622     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9623   },
9624   /* VEX_LEN_0F45_P_2 */
9625   {
9626     { Bad_Opcode },
9627     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9628   },
9629   /* VEX_LEN_0F46_P_0 */
9630   {
9631     { Bad_Opcode },
9632     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9633   },
9634   /* VEX_LEN_0F46_P_2 */
9635   {
9636     { Bad_Opcode },
9637     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9638   },
9639   /* VEX_LEN_0F47_P_0 */
9640   {
9641     { Bad_Opcode },
9642     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9643   },
9644   /* VEX_LEN_0F47_P_2 */
9645   {
9646     { Bad_Opcode },
9647     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9648   },
9649   /* VEX_LEN_0F4A_P_0 */
9650   {
9651     { Bad_Opcode },
9652     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9653   },
9654   /* VEX_LEN_0F4A_P_2 */
9655   {
9656     { Bad_Opcode },
9657     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9658   },
9659   /* VEX_LEN_0F4B_P_0 */
9660   {
9661     { Bad_Opcode },
9662     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9663   },
9664   /* VEX_LEN_0F4B_P_2 */
9665   {
9666     { Bad_Opcode },
9667     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9668   },
9669
9670   /* VEX_LEN_0F51_P_1 */
9671   {
9672     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9673     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9674   },
9675
9676   /* VEX_LEN_0F51_P_3 */
9677   {
9678     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9679     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9680   },
9681
9682   /* VEX_LEN_0F52_P_1 */
9683   {
9684     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9685     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9686   },
9687
9688   /* VEX_LEN_0F53_P_1 */
9689   {
9690     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9691     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9692   },
9693
9694   /* VEX_LEN_0F58_P_1 */
9695   {
9696     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9697     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9698   },
9699
9700   /* VEX_LEN_0F58_P_3 */
9701   {
9702     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9703     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9704   },
9705
9706   /* VEX_LEN_0F59_P_1 */
9707   {
9708     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9709     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9710   },
9711
9712   /* VEX_LEN_0F59_P_3 */
9713   {
9714     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9715     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9716   },
9717
9718   /* VEX_LEN_0F5A_P_1 */
9719   {
9720     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9721     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9722   },
9723
9724   /* VEX_LEN_0F5A_P_3 */
9725   {
9726     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9727     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9728   },
9729
9730   /* VEX_LEN_0F5C_P_1 */
9731   {
9732     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9733     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9734   },
9735
9736   /* VEX_LEN_0F5C_P_3 */
9737   {
9738     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9739     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9740   },
9741
9742   /* VEX_LEN_0F5D_P_1 */
9743   {
9744     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9745     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9746   },
9747
9748   /* VEX_LEN_0F5D_P_3 */
9749   {
9750     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9751     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9752   },
9753
9754   /* VEX_LEN_0F5E_P_1 */
9755   {
9756     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9757     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9758   },
9759
9760   /* VEX_LEN_0F5E_P_3 */
9761   {
9762     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9763     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9764   },
9765
9766   /* VEX_LEN_0F5F_P_1 */
9767   {
9768     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9769     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9770   },
9771
9772   /* VEX_LEN_0F5F_P_3 */
9773   {
9774     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9775     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9776   },
9777
9778   /* VEX_LEN_0F6E_P_2 */
9779   {
9780     { "vmovK",          { XMScalar, Edq } },
9781     { "vmovK",          { XMScalar, Edq } },
9782   },
9783
9784   /* VEX_LEN_0F7E_P_1 */
9785   {
9786     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9787     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9788   },
9789
9790   /* VEX_LEN_0F7E_P_2 */
9791   {
9792     { "vmovK",          { Edq, XMScalar } },
9793     { "vmovK",          { Edq, XMScalar } },
9794   },
9795
9796   /* VEX_LEN_0F90_P_0 */
9797   {
9798     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9799   },
9800
9801   /* VEX_LEN_0F90_P_2 */
9802   {
9803     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9804   },
9805
9806   /* VEX_LEN_0F91_P_0 */
9807   {
9808     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9809   },
9810
9811   /* VEX_LEN_0F91_P_2 */
9812   {
9813     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9814   },
9815
9816   /* VEX_LEN_0F92_P_0 */
9817   {
9818     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9819   },
9820
9821   /* VEX_LEN_0F92_P_2 */
9822   {
9823     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9824   },
9825
9826   /* VEX_LEN_0F92_P_3 */
9827   {
9828     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9829   },
9830
9831   /* VEX_LEN_0F93_P_0 */
9832   {
9833     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9834   },
9835
9836   /* VEX_LEN_0F93_P_2 */
9837   {
9838     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9839   },
9840
9841   /* VEX_LEN_0F93_P_3 */
9842   {
9843     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9844   },
9845
9846   /* VEX_LEN_0F98_P_0 */
9847   {
9848     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9849   },
9850
9851   /* VEX_LEN_0F98_P_2 */
9852   {
9853     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9854   },
9855
9856   /* VEX_LEN_0F99_P_0 */
9857   {
9858     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9859   },
9860
9861   /* VEX_LEN_0F99_P_2 */
9862   {
9863     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9864   },
9865
9866   /* VEX_LEN_0FAE_R_2_M_0 */
9867   {
9868     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9869   },
9870
9871   /* VEX_LEN_0FAE_R_3_M_0 */
9872   {
9873     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9874   },
9875
9876   /* VEX_LEN_0FC2_P_1 */
9877   {
9878     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9879     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9880   },
9881
9882   /* VEX_LEN_0FC2_P_3 */
9883   {
9884     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9885     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9886   },
9887
9888   /* VEX_LEN_0FC4_P_2 */
9889   {
9890     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9891   },
9892
9893   /* VEX_LEN_0FC5_P_2 */
9894   {
9895     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9896   },
9897
9898   /* VEX_LEN_0FD6_P_2 */
9899   {
9900     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9901     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9902   },
9903
9904   /* VEX_LEN_0FF7_P_2 */
9905   {
9906     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9907   },
9908
9909   /* VEX_LEN_0F3816_P_2 */
9910   {
9911     { Bad_Opcode },
9912     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9913   },
9914
9915   /* VEX_LEN_0F3819_P_2 */
9916   {
9917     { Bad_Opcode },
9918     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9919   },
9920
9921   /* VEX_LEN_0F381A_P_2_M_0 */
9922   {
9923     { Bad_Opcode },
9924     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9925   },
9926
9927   /* VEX_LEN_0F3836_P_2 */
9928   {
9929     { Bad_Opcode },
9930     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9931   },
9932
9933   /* VEX_LEN_0F3841_P_2 */
9934   {
9935     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9936   },
9937
9938   /* VEX_LEN_0F385A_P_2_M_0 */
9939   {
9940     { Bad_Opcode },
9941     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9942   },
9943
9944   /* VEX_LEN_0F38DB_P_2 */
9945   {
9946     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9947   },
9948
9949   /* VEX_LEN_0F38DC_P_2 */
9950   {
9951     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9952   },
9953
9954   /* VEX_LEN_0F38DD_P_2 */
9955   {
9956     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9957   },
9958
9959   /* VEX_LEN_0F38DE_P_2 */
9960   {
9961     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9962   },
9963
9964   /* VEX_LEN_0F38DF_P_2 */
9965   {
9966     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9967   },
9968
9969   /* VEX_LEN_0F38F2_P_0 */
9970   {
9971     { "andnS",          { Gdq, VexGdq, Edq } },
9972   },
9973
9974   /* VEX_LEN_0F38F3_R_1_P_0 */
9975   {
9976     { "blsrS",          { VexGdq, Edq } },
9977   },
9978
9979   /* VEX_LEN_0F38F3_R_2_P_0 */
9980   {
9981     { "blsmskS",        { VexGdq, Edq } },
9982   },
9983
9984   /* VEX_LEN_0F38F3_R_3_P_0 */
9985   {
9986     { "blsiS",          { VexGdq, Edq } },
9987   },
9988
9989   /* VEX_LEN_0F38F5_P_0 */
9990   {
9991     { "bzhiS",          { Gdq, Edq, VexGdq } },
9992   },
9993
9994   /* VEX_LEN_0F38F5_P_1 */
9995   {
9996     { "pextS",          { Gdq, VexGdq, Edq } },
9997   },
9998
9999   /* VEX_LEN_0F38F5_P_3 */
10000   {
10001     { "pdepS",          { Gdq, VexGdq, Edq } },
10002   },
10003
10004   /* VEX_LEN_0F38F6_P_3 */
10005   {
10006     { "mulxS",          { Gdq, VexGdq, Edq } },
10007   },
10008
10009   /* VEX_LEN_0F38F7_P_0 */
10010   {
10011     { "bextrS",         { Gdq, Edq, VexGdq } },
10012   },
10013
10014   /* VEX_LEN_0F38F7_P_1 */
10015   {
10016     { "sarxS",          { Gdq, Edq, VexGdq } },
10017   },
10018
10019   /* VEX_LEN_0F38F7_P_2 */
10020   {
10021     { "shlxS",          { Gdq, Edq, VexGdq } },
10022   },
10023
10024   /* VEX_LEN_0F38F7_P_3 */
10025   {
10026     { "shrxS",          { Gdq, Edq, VexGdq } },
10027   },
10028
10029   /* VEX_LEN_0F3A00_P_2 */
10030   {
10031     { Bad_Opcode },
10032     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10033   },
10034
10035   /* VEX_LEN_0F3A01_P_2 */
10036   {
10037     { Bad_Opcode },
10038     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10039   },
10040
10041   /* VEX_LEN_0F3A06_P_2 */
10042   {
10043     { Bad_Opcode },
10044     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10045   },
10046
10047   /* VEX_LEN_0F3A0A_P_2 */
10048   {
10049     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10050     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10051   },
10052
10053   /* VEX_LEN_0F3A0B_P_2 */
10054   {
10055     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10056     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10057   },
10058
10059   /* VEX_LEN_0F3A14_P_2 */
10060   {
10061     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10062   },
10063
10064   /* VEX_LEN_0F3A15_P_2 */
10065   {
10066     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10067   },
10068
10069   /* VEX_LEN_0F3A16_P_2  */
10070   {
10071     { "vpextrK",        { Edq, XM, Ib } },
10072   },
10073
10074   /* VEX_LEN_0F3A17_P_2 */
10075   {
10076     { "vextractps",     { Edqd, XM, Ib } },
10077   },
10078
10079   /* VEX_LEN_0F3A18_P_2 */
10080   {
10081     { Bad_Opcode },
10082     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10083   },
10084
10085   /* VEX_LEN_0F3A19_P_2 */
10086   {
10087     { Bad_Opcode },
10088     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10089   },
10090
10091   /* VEX_LEN_0F3A20_P_2 */
10092   {
10093     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10094   },
10095
10096   /* VEX_LEN_0F3A21_P_2 */
10097   {
10098     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10099   },
10100
10101   /* VEX_LEN_0F3A22_P_2 */
10102   {
10103     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
10104   },
10105
10106   /* VEX_LEN_0F3A30_P_2 */
10107   {
10108     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10109   },
10110
10111   /* VEX_LEN_0F3A31_P_2 */
10112   {
10113     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10114   },
10115
10116   /* VEX_LEN_0F3A32_P_2 */
10117   {
10118     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10119   },
10120
10121   /* VEX_LEN_0F3A33_P_2 */
10122   {
10123     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10124   },
10125
10126   /* VEX_LEN_0F3A38_P_2 */
10127   {
10128     { Bad_Opcode },
10129     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10130   },
10131
10132   /* VEX_LEN_0F3A39_P_2 */
10133   {
10134     { Bad_Opcode },
10135     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10136   },
10137
10138   /* VEX_LEN_0F3A41_P_2 */
10139   {
10140     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10141   },
10142
10143   /* VEX_LEN_0F3A44_P_2 */
10144   {
10145     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10146   },
10147
10148   /* VEX_LEN_0F3A46_P_2 */
10149   {
10150     { Bad_Opcode },
10151     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10152   },
10153
10154   /* VEX_LEN_0F3A60_P_2 */
10155   {
10156     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10157   },
10158
10159   /* VEX_LEN_0F3A61_P_2 */
10160   {
10161     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10162   },
10163
10164   /* VEX_LEN_0F3A62_P_2 */
10165   {
10166     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10167   },
10168
10169   /* VEX_LEN_0F3A63_P_2 */
10170   {
10171     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10172   },
10173
10174   /* VEX_LEN_0F3A6A_P_2 */
10175   {
10176     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10177   },
10178
10179   /* VEX_LEN_0F3A6B_P_2 */
10180   {
10181     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10182   },
10183
10184   /* VEX_LEN_0F3A6E_P_2 */
10185   {
10186     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10187   },
10188
10189   /* VEX_LEN_0F3A6F_P_2 */
10190   {
10191     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10192   },
10193
10194   /* VEX_LEN_0F3A7A_P_2 */
10195   {
10196     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10197   },
10198
10199   /* VEX_LEN_0F3A7B_P_2 */
10200   {
10201     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10202   },
10203
10204   /* VEX_LEN_0F3A7E_P_2 */
10205   {
10206     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10207   },
10208
10209   /* VEX_LEN_0F3A7F_P_2 */
10210   {
10211     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10212   },
10213
10214   /* VEX_LEN_0F3ADF_P_2 */
10215   {
10216     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10217   },
10218
10219   /* VEX_LEN_0F3AF0_P_3 */
10220   {
10221     { "rorxS",          { Gdq, Edq, Ib } },
10222   },
10223
10224   /* VEX_LEN_0FXOP_08_CC */
10225   {
10226      { "vpcomb",        { XM, Vex128, EXx, Ib } },
10227   },
10228
10229   /* VEX_LEN_0FXOP_08_CD */
10230   {
10231      { "vpcomw",        { XM, Vex128, EXx, Ib } },
10232   },
10233
10234   /* VEX_LEN_0FXOP_08_CE */
10235   {
10236      { "vpcomd",        { XM, Vex128, EXx, Ib } },
10237   },
10238
10239   /* VEX_LEN_0FXOP_08_CF */
10240   {
10241      { "vpcomq",        { XM, Vex128, EXx, Ib } },
10242   },
10243
10244   /* VEX_LEN_0FXOP_08_EC */
10245   {
10246      { "vpcomub",       { XM, Vex128, EXx, Ib } },
10247   },
10248
10249   /* VEX_LEN_0FXOP_08_ED */
10250   {
10251      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
10252   },
10253
10254   /* VEX_LEN_0FXOP_08_EE */
10255   {
10256      { "vpcomud",       { XM, Vex128, EXx, Ib } },
10257   },
10258
10259   /* VEX_LEN_0FXOP_08_EF */
10260   {
10261      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
10262   },
10263
10264   /* VEX_LEN_0FXOP_09_80 */
10265   {
10266     { "vfrczps",        { XM, EXxmm } },
10267     { "vfrczps",        { XM, EXymmq } },
10268   },
10269
10270   /* VEX_LEN_0FXOP_09_81 */
10271   {
10272     { "vfrczpd",        { XM, EXxmm } },
10273     { "vfrczpd",        { XM, EXymmq } },
10274   },
10275 };
10276
10277 static const struct dis386 vex_w_table[][2] = {
10278   {
10279     /* VEX_W_0F10_P_0 */
10280     { "vmovups",        { XM, EXx } },
10281   },
10282   {
10283     /* VEX_W_0F10_P_1 */
10284     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
10285   },
10286   {
10287     /* VEX_W_0F10_P_2 */
10288     { "vmovupd",        { XM, EXx } },
10289   },
10290   {
10291     /* VEX_W_0F10_P_3 */
10292     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
10293   },
10294   {
10295     /* VEX_W_0F11_P_0 */
10296     { "vmovups",        { EXxS, XM } },
10297   },
10298   {
10299     /* VEX_W_0F11_P_1 */
10300     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
10301   },
10302   {
10303     /* VEX_W_0F11_P_2 */
10304     { "vmovupd",        { EXxS, XM } },
10305   },
10306   {
10307     /* VEX_W_0F11_P_3 */
10308     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
10309   },
10310   {
10311     /* VEX_W_0F12_P_0_M_0 */
10312     { "vmovlps",        { XM, Vex128, EXq } },
10313   },
10314   {
10315     /* VEX_W_0F12_P_0_M_1 */
10316     { "vmovhlps",       { XM, Vex128, EXq } },
10317   },
10318   {
10319     /* VEX_W_0F12_P_1 */
10320     { "vmovsldup",      { XM, EXx } },
10321   },
10322   {
10323     /* VEX_W_0F12_P_2 */
10324     { "vmovlpd",        { XM, Vex128, EXq } },
10325   },
10326   {
10327     /* VEX_W_0F12_P_3 */
10328     { "vmovddup",       { XM, EXymmq } },
10329   },
10330   {
10331     /* VEX_W_0F13_M_0 */
10332     { "vmovlpX",        { EXq, XM } },
10333   },
10334   {
10335     /* VEX_W_0F14 */
10336     { "vunpcklpX",      { XM, Vex, EXx } },
10337   },
10338   {
10339     /* VEX_W_0F15 */
10340     { "vunpckhpX",      { XM, Vex, EXx } },
10341   },
10342   {
10343     /* VEX_W_0F16_P_0_M_0 */
10344     { "vmovhps",        { XM, Vex128, EXq } },
10345   },
10346   {
10347     /* VEX_W_0F16_P_0_M_1 */
10348     { "vmovlhps",       { XM, Vex128, EXq } },
10349   },
10350   {
10351     /* VEX_W_0F16_P_1 */
10352     { "vmovshdup",      { XM, EXx } },
10353   },
10354   {
10355     /* VEX_W_0F16_P_2 */
10356     { "vmovhpd",        { XM, Vex128, EXq } },
10357   },
10358   {
10359     /* VEX_W_0F17_M_0 */
10360     { "vmovhpX",        { EXq, XM } },
10361   },
10362   {
10363     /* VEX_W_0F28 */
10364     { "vmovapX",        { XM, EXx } },
10365   },
10366   {
10367     /* VEX_W_0F29 */
10368     { "vmovapX",        { EXxS, XM } },
10369   },
10370   {
10371     /* VEX_W_0F2B_M_0 */
10372     { "vmovntpX",       { Mx, XM } },
10373   },
10374   {
10375     /* VEX_W_0F2E_P_0 */
10376     { "vucomiss",       { XMScalar, EXdScalar } },
10377   },
10378   {
10379     /* VEX_W_0F2E_P_2 */
10380     { "vucomisd",       { XMScalar, EXqScalar } },
10381   },
10382   {
10383     /* VEX_W_0F2F_P_0 */
10384     { "vcomiss",        { XMScalar, EXdScalar } },
10385   },
10386   {
10387     /* VEX_W_0F2F_P_2 */
10388     { "vcomisd",        { XMScalar, EXqScalar } },
10389   },
10390   {
10391     /* VEX_W_0F41_P_0_LEN_1 */
10392     { "kandw",          { MaskG, MaskVex, MaskR } },
10393     { "kandq",          { MaskG, MaskVex, MaskR } },
10394   },
10395   {
10396     /* VEX_W_0F41_P_2_LEN_1 */
10397     { "kandb",          { MaskG, MaskVex, MaskR } },
10398     { "kandd",          { MaskG, MaskVex, MaskR } },
10399   },
10400   {
10401     /* VEX_W_0F42_P_0_LEN_1 */
10402     { "kandnw",         { MaskG, MaskVex, MaskR } },
10403     { "kandnq",         { MaskG, MaskVex, MaskR } },
10404   },
10405   {
10406     /* VEX_W_0F42_P_2_LEN_1 */
10407     { "kandnb",         { MaskG, MaskVex, MaskR } },
10408     { "kandnd",         { MaskG, MaskVex, MaskR } },
10409   },
10410   {
10411     /* VEX_W_0F44_P_0_LEN_0 */
10412     { "knotw",          { MaskG, MaskR } },
10413     { "knotq",          { MaskG, MaskR } },
10414   },
10415   {
10416     /* VEX_W_0F44_P_2_LEN_0 */
10417     { "knotb",          { MaskG, MaskR } },
10418     { "knotd",          { MaskG, MaskR } },
10419   },
10420   {
10421     /* VEX_W_0F45_P_0_LEN_1 */
10422     { "korw",           { MaskG, MaskVex, MaskR } },
10423     { "korq",           { MaskG, MaskVex, MaskR } },
10424   },
10425   {
10426     /* VEX_W_0F45_P_2_LEN_1 */
10427     { "korb",           { MaskG, MaskVex, MaskR } },
10428     { "kord",           { MaskG, MaskVex, MaskR } },
10429   },
10430   {
10431     /* VEX_W_0F46_P_0_LEN_1 */
10432     { "kxnorw",         { MaskG, MaskVex, MaskR } },
10433     { "kxnorq",         { MaskG, MaskVex, MaskR } },
10434   },
10435   {
10436     /* VEX_W_0F46_P_2_LEN_1 */
10437     { "kxnorb",         { MaskG, MaskVex, MaskR } },
10438     { "kxnord",         { MaskG, MaskVex, MaskR } },
10439   },
10440   {
10441     /* VEX_W_0F47_P_0_LEN_1 */
10442     { "kxorw",          { MaskG, MaskVex, MaskR } },
10443     { "kxorq",          { MaskG, MaskVex, MaskR } },
10444   },
10445   {
10446     /* VEX_W_0F47_P_2_LEN_1 */
10447     { "kxorb",          { MaskG, MaskVex, MaskR } },
10448     { "kxord",          { MaskG, MaskVex, MaskR } },
10449   },
10450   {
10451     /* VEX_W_0F4A_P_0_LEN_1 */
10452     { "kaddw",          { MaskG, MaskVex, MaskR } },
10453     { "kaddq",          { MaskG, MaskVex, MaskR } },
10454   },
10455   {
10456     /* VEX_W_0F4A_P_2_LEN_1 */
10457     { "kaddb",          { MaskG, MaskVex, MaskR } },
10458     { "kaddd",          { MaskG, MaskVex, MaskR } },
10459   },
10460   {
10461     /* VEX_W_0F4B_P_0_LEN_1 */
10462     { "kunpckwd",       { MaskG, MaskVex, MaskR } },
10463     { "kunpckdq",       { MaskG, MaskVex, MaskR } },
10464   },
10465   {
10466     /* VEX_W_0F4B_P_2_LEN_1 */
10467     { "kunpckbw",       { MaskG, MaskVex, MaskR } },
10468   },
10469   {
10470     /* VEX_W_0F50_M_0 */
10471     { "vmovmskpX",      { Gdq, XS } },
10472   },
10473   {
10474     /* VEX_W_0F51_P_0 */
10475     { "vsqrtps",        { XM, EXx } },
10476   },
10477   {
10478     /* VEX_W_0F51_P_1 */
10479     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
10480   },
10481   {
10482     /* VEX_W_0F51_P_2  */
10483     { "vsqrtpd",        { XM, EXx } },
10484   },
10485   {
10486     /* VEX_W_0F51_P_3 */
10487     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
10488   },
10489   {
10490     /* VEX_W_0F52_P_0 */
10491     { "vrsqrtps",       { XM, EXx } },
10492   },
10493   {
10494     /* VEX_W_0F52_P_1 */
10495     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
10496   },
10497   {
10498     /* VEX_W_0F53_P_0  */
10499     { "vrcpps",         { XM, EXx } },
10500   },
10501   {
10502     /* VEX_W_0F53_P_1  */
10503     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
10504   },
10505   {
10506     /* VEX_W_0F58_P_0  */
10507     { "vaddps",         { XM, Vex, EXx } },
10508   },
10509   {
10510     /* VEX_W_0F58_P_1  */
10511     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
10512   },
10513   {
10514     /* VEX_W_0F58_P_2  */
10515     { "vaddpd",         { XM, Vex, EXx } },
10516   },
10517   {
10518     /* VEX_W_0F58_P_3  */
10519     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
10520   },
10521   {
10522     /* VEX_W_0F59_P_0  */
10523     { "vmulps",         { XM, Vex, EXx } },
10524   },
10525   {
10526     /* VEX_W_0F59_P_1  */
10527     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
10528   },
10529   {
10530     /* VEX_W_0F59_P_2  */
10531     { "vmulpd",         { XM, Vex, EXx } },
10532   },
10533   {
10534     /* VEX_W_0F59_P_3  */
10535     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
10536   },
10537   {
10538     /* VEX_W_0F5A_P_0  */
10539     { "vcvtps2pd",      { XM, EXxmmq } },
10540   },
10541   {
10542     /* VEX_W_0F5A_P_1  */
10543     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
10544   },
10545   {
10546     /* VEX_W_0F5A_P_3  */
10547     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
10548   },
10549   {
10550     /* VEX_W_0F5B_P_0  */
10551     { "vcvtdq2ps",      { XM, EXx } },
10552   },
10553   {
10554     /* VEX_W_0F5B_P_1  */
10555     { "vcvttps2dq",     { XM, EXx } },
10556   },
10557   {
10558     /* VEX_W_0F5B_P_2  */
10559     { "vcvtps2dq",      { XM, EXx } },
10560   },
10561   {
10562     /* VEX_W_0F5C_P_0  */
10563     { "vsubps",         { XM, Vex, EXx } },
10564   },
10565   {
10566     /* VEX_W_0F5C_P_1  */
10567     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
10568   },
10569   {
10570     /* VEX_W_0F5C_P_2  */
10571     { "vsubpd",         { XM, Vex, EXx } },
10572   },
10573   {
10574     /* VEX_W_0F5C_P_3  */
10575     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
10576   },
10577   {
10578     /* VEX_W_0F5D_P_0  */
10579     { "vminps",         { XM, Vex, EXx } },
10580   },
10581   {
10582     /* VEX_W_0F5D_P_1  */
10583     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
10584   },
10585   {
10586     /* VEX_W_0F5D_P_2  */
10587     { "vminpd",         { XM, Vex, EXx } },
10588   },
10589   {
10590     /* VEX_W_0F5D_P_3  */
10591     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
10592   },
10593   {
10594     /* VEX_W_0F5E_P_0  */
10595     { "vdivps",         { XM, Vex, EXx } },
10596   },
10597   {
10598     /* VEX_W_0F5E_P_1  */
10599     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
10600   },
10601   {
10602     /* VEX_W_0F5E_P_2  */
10603     { "vdivpd",         { XM, Vex, EXx } },
10604   },
10605   {
10606     /* VEX_W_0F5E_P_3  */
10607     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
10608   },
10609   {
10610     /* VEX_W_0F5F_P_0  */
10611     { "vmaxps",         { XM, Vex, EXx } },
10612   },
10613   {
10614     /* VEX_W_0F5F_P_1  */
10615     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
10616   },
10617   {
10618     /* VEX_W_0F5F_P_2  */
10619     { "vmaxpd",         { XM, Vex, EXx } },
10620   },
10621   {
10622     /* VEX_W_0F5F_P_3  */
10623     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
10624   },
10625   {
10626     /* VEX_W_0F60_P_2  */
10627     { "vpunpcklbw",     { XM, Vex, EXx } },
10628   },
10629   {
10630     /* VEX_W_0F61_P_2  */
10631     { "vpunpcklwd",     { XM, Vex, EXx } },
10632   },
10633   {
10634     /* VEX_W_0F62_P_2  */
10635     { "vpunpckldq",     { XM, Vex, EXx } },
10636   },
10637   {
10638     /* VEX_W_0F63_P_2  */
10639     { "vpacksswb",      { XM, Vex, EXx } },
10640   },
10641   {
10642     /* VEX_W_0F64_P_2  */
10643     { "vpcmpgtb",       { XM, Vex, EXx } },
10644   },
10645   {
10646     /* VEX_W_0F65_P_2  */
10647     { "vpcmpgtw",       { XM, Vex, EXx } },
10648   },
10649   {
10650     /* VEX_W_0F66_P_2  */
10651     { "vpcmpgtd",       { XM, Vex, EXx } },
10652   },
10653   {
10654     /* VEX_W_0F67_P_2  */
10655     { "vpackuswb",      { XM, Vex, EXx } },
10656   },
10657   {
10658     /* VEX_W_0F68_P_2  */
10659     { "vpunpckhbw",     { XM, Vex, EXx } },
10660   },
10661   {
10662     /* VEX_W_0F69_P_2  */
10663     { "vpunpckhwd",     { XM, Vex, EXx } },
10664   },
10665   {
10666     /* VEX_W_0F6A_P_2  */
10667     { "vpunpckhdq",     { XM, Vex, EXx } },
10668   },
10669   {
10670     /* VEX_W_0F6B_P_2  */
10671     { "vpackssdw",      { XM, Vex, EXx } },
10672   },
10673   {
10674     /* VEX_W_0F6C_P_2  */
10675     { "vpunpcklqdq",    { XM, Vex, EXx } },
10676   },
10677   {
10678     /* VEX_W_0F6D_P_2  */
10679     { "vpunpckhqdq",    { XM, Vex, EXx } },
10680   },
10681   {
10682     /* VEX_W_0F6F_P_1  */
10683     { "vmovdqu",        { XM, EXx } },
10684   },
10685   {
10686     /* VEX_W_0F6F_P_2  */
10687     { "vmovdqa",        { XM, EXx } },
10688   },
10689   {
10690     /* VEX_W_0F70_P_1 */
10691     { "vpshufhw",       { XM, EXx, Ib } },
10692   },
10693   {
10694     /* VEX_W_0F70_P_2 */
10695     { "vpshufd",        { XM, EXx, Ib } },
10696   },
10697   {
10698     /* VEX_W_0F70_P_3 */
10699     { "vpshuflw",       { XM, EXx, Ib } },
10700   },
10701   {
10702     /* VEX_W_0F71_R_2_P_2  */
10703     { "vpsrlw",         { Vex, XS, Ib } },
10704   },
10705   {
10706     /* VEX_W_0F71_R_4_P_2  */
10707     { "vpsraw",         { Vex, XS, Ib } },
10708   },
10709   {
10710     /* VEX_W_0F71_R_6_P_2  */
10711     { "vpsllw",         { Vex, XS, Ib } },
10712   },
10713   {
10714     /* VEX_W_0F72_R_2_P_2  */
10715     { "vpsrld",         { Vex, XS, Ib } },
10716   },
10717   {
10718     /* VEX_W_0F72_R_4_P_2  */
10719     { "vpsrad",         { Vex, XS, Ib } },
10720   },
10721   {
10722     /* VEX_W_0F72_R_6_P_2  */
10723     { "vpslld",         { Vex, XS, Ib } },
10724   },
10725   {
10726     /* VEX_W_0F73_R_2_P_2  */
10727     { "vpsrlq",         { Vex, XS, Ib } },
10728   },
10729   {
10730     /* VEX_W_0F73_R_3_P_2  */
10731     { "vpsrldq",        { Vex, XS, Ib } },
10732   },
10733   {
10734     /* VEX_W_0F73_R_6_P_2  */
10735     { "vpsllq",         { Vex, XS, Ib } },
10736   },
10737   {
10738     /* VEX_W_0F73_R_7_P_2  */
10739     { "vpslldq",        { Vex, XS, Ib } },
10740   },
10741   {
10742     /* VEX_W_0F74_P_2 */
10743     { "vpcmpeqb",       { XM, Vex, EXx } },
10744   },
10745   {
10746     /* VEX_W_0F75_P_2 */
10747     { "vpcmpeqw",       { XM, Vex, EXx } },
10748   },
10749   {
10750     /* VEX_W_0F76_P_2 */
10751     { "vpcmpeqd",       { XM, Vex, EXx } },
10752   },
10753   {
10754     /* VEX_W_0F77_P_0 */
10755     { "",               { VZERO } },
10756   },
10757   {
10758     /* VEX_W_0F7C_P_2 */
10759     { "vhaddpd",        { XM, Vex, EXx } },
10760   },
10761   {
10762     /* VEX_W_0F7C_P_3 */
10763     { "vhaddps",        { XM, Vex, EXx } },
10764   },
10765   {
10766     /* VEX_W_0F7D_P_2 */
10767     { "vhsubpd",        { XM, Vex, EXx } },
10768   },
10769   {
10770     /* VEX_W_0F7D_P_3 */
10771     { "vhsubps",        { XM, Vex, EXx } },
10772   },
10773   {
10774     /* VEX_W_0F7E_P_1 */
10775     { "vmovq",          { XMScalar, EXqScalar } },
10776   },
10777   {
10778     /* VEX_W_0F7F_P_1 */
10779     { "vmovdqu",        { EXxS, XM } },
10780   },
10781   {
10782     /* VEX_W_0F7F_P_2 */
10783     { "vmovdqa",        { EXxS, XM } },
10784   },
10785   {
10786     /* VEX_W_0F90_P_0_LEN_0 */
10787     { "kmovw",          { MaskG, MaskE } },
10788     { "kmovq",          { MaskG, MaskE } },
10789   },
10790   {
10791     /* VEX_W_0F90_P_2_LEN_0 */
10792     { "kmovb",          { MaskG, MaskBDE } },
10793     { "kmovd",          { MaskG, MaskBDE } },
10794   },
10795   {
10796     /* VEX_W_0F91_P_0_LEN_0 */
10797     { "kmovw",          { Ew, MaskG } },
10798     { "kmovq",          { Eq, MaskG } },
10799   },
10800   {
10801     /* VEX_W_0F91_P_2_LEN_0 */
10802     { "kmovb",          { Eb, MaskG } },
10803     { "kmovd",          { Ed, MaskG } },
10804   },
10805   {
10806     /* VEX_W_0F92_P_0_LEN_0 */
10807     { "kmovw",          { MaskG, Rdq } },
10808   },
10809   {
10810     /* VEX_W_0F92_P_2_LEN_0 */
10811     { "kmovb",          { MaskG, Rdq } },
10812   },
10813   {
10814     /* VEX_W_0F92_P_3_LEN_0 */
10815     { "kmovd",          { MaskG, Rdq } },
10816     { "kmovq",          { MaskG, Rdq } },
10817   },
10818   {
10819     /* VEX_W_0F93_P_0_LEN_0 */
10820     { "kmovw",          { Gdq, MaskR } },
10821   },
10822   {
10823     /* VEX_W_0F93_P_2_LEN_0 */
10824     { "kmovb",          { Gdq, MaskR } },
10825   },
10826   {
10827     /* VEX_W_0F93_P_3_LEN_0 */
10828     { "kmovd",          { Gdq, MaskR } },
10829     { "kmovq",          { Gdq, MaskR } },
10830   },
10831   {
10832     /* VEX_W_0F98_P_0_LEN_0 */
10833     { "kortestw",       { MaskG, MaskR } },
10834     { "kortestq",       { MaskG, MaskR } },
10835   },
10836   {
10837     /* VEX_W_0F98_P_2_LEN_0 */
10838     { "kortestb",       { MaskG, MaskR } },
10839     { "kortestd",       { MaskG, MaskR } },
10840   },
10841   {
10842     /* VEX_W_0F99_P_0_LEN_0 */
10843     { "ktestw", { MaskG, MaskR } },
10844     { "ktestq", { MaskG, MaskR } },
10845   },
10846   {
10847     /* VEX_W_0F99_P_2_LEN_0 */
10848     { "ktestb", { MaskG, MaskR } },
10849     { "ktestd", { MaskG, MaskR } },
10850   },
10851   {
10852     /* VEX_W_0FAE_R_2_M_0 */
10853     { "vldmxcsr",       { Md } },
10854   },
10855   {
10856     /* VEX_W_0FAE_R_3_M_0 */
10857     { "vstmxcsr",       { Md } },
10858   },
10859   {
10860     /* VEX_W_0FC2_P_0 */
10861     { "vcmpps",         { XM, Vex, EXx, VCMP } },
10862   },
10863   {
10864     /* VEX_W_0FC2_P_1 */
10865     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
10866   },
10867   {
10868     /* VEX_W_0FC2_P_2 */
10869     { "vcmppd",         { XM, Vex, EXx, VCMP } },
10870   },
10871   {
10872     /* VEX_W_0FC2_P_3 */
10873     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
10874   },
10875   {
10876     /* VEX_W_0FC4_P_2 */
10877     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
10878   },
10879   {
10880     /* VEX_W_0FC5_P_2 */
10881     { "vpextrw",        { Gdq, XS, Ib } },
10882   },
10883   {
10884     /* VEX_W_0FD0_P_2 */
10885     { "vaddsubpd",      { XM, Vex, EXx } },
10886   },
10887   {
10888     /* VEX_W_0FD0_P_3 */
10889     { "vaddsubps",      { XM, Vex, EXx } },
10890   },
10891   {
10892     /* VEX_W_0FD1_P_2 */
10893     { "vpsrlw",         { XM, Vex, EXxmm } },
10894   },
10895   {
10896     /* VEX_W_0FD2_P_2 */
10897     { "vpsrld",         { XM, Vex, EXxmm } },
10898   },
10899   {
10900     /* VEX_W_0FD3_P_2 */
10901     { "vpsrlq",         { XM, Vex, EXxmm } },
10902   },
10903   {
10904     /* VEX_W_0FD4_P_2 */
10905     { "vpaddq",         { XM, Vex, EXx } },
10906   },
10907   {
10908     /* VEX_W_0FD5_P_2 */
10909     { "vpmullw",        { XM, Vex, EXx } },
10910   },
10911   {
10912     /* VEX_W_0FD6_P_2 */
10913     { "vmovq",          { EXqScalarS, XMScalar } },
10914   },
10915   {
10916     /* VEX_W_0FD7_P_2_M_1 */
10917     { "vpmovmskb",      { Gdq, XS } },
10918   },
10919   {
10920     /* VEX_W_0FD8_P_2 */
10921     { "vpsubusb",       { XM, Vex, EXx } },
10922   },
10923   {
10924     /* VEX_W_0FD9_P_2 */
10925     { "vpsubusw",       { XM, Vex, EXx } },
10926   },
10927   {
10928     /* VEX_W_0FDA_P_2 */
10929     { "vpminub",        { XM, Vex, EXx } },
10930   },
10931   {
10932     /* VEX_W_0FDB_P_2 */
10933     { "vpand",          { XM, Vex, EXx } },
10934   },
10935   {
10936     /* VEX_W_0FDC_P_2 */
10937     { "vpaddusb",       { XM, Vex, EXx } },
10938   },
10939   {
10940     /* VEX_W_0FDD_P_2 */
10941     { "vpaddusw",       { XM, Vex, EXx } },
10942   },
10943   {
10944     /* VEX_W_0FDE_P_2 */
10945     { "vpmaxub",        { XM, Vex, EXx } },
10946   },
10947   {
10948     /* VEX_W_0FDF_P_2 */
10949     { "vpandn",         { XM, Vex, EXx } },
10950   },
10951   {
10952     /* VEX_W_0FE0_P_2  */
10953     { "vpavgb",         { XM, Vex, EXx } },
10954   },
10955   {
10956     /* VEX_W_0FE1_P_2  */
10957     { "vpsraw",         { XM, Vex, EXxmm } },
10958   },
10959   {
10960     /* VEX_W_0FE2_P_2  */
10961     { "vpsrad",         { XM, Vex, EXxmm } },
10962   },
10963   {
10964     /* VEX_W_0FE3_P_2  */
10965     { "vpavgw",         { XM, Vex, EXx } },
10966   },
10967   {
10968     /* VEX_W_0FE4_P_2  */
10969     { "vpmulhuw",       { XM, Vex, EXx } },
10970   },
10971   {
10972     /* VEX_W_0FE5_P_2  */
10973     { "vpmulhw",        { XM, Vex, EXx } },
10974   },
10975   {
10976     /* VEX_W_0FE6_P_1  */
10977     { "vcvtdq2pd",      { XM, EXxmmq } },
10978   },
10979   {
10980     /* VEX_W_0FE6_P_2  */
10981     { "vcvttpd2dq%XY",  { XMM, EXx } },
10982   },
10983   {
10984     /* VEX_W_0FE6_P_3  */
10985     { "vcvtpd2dq%XY",   { XMM, EXx } },
10986   },
10987   {
10988     /* VEX_W_0FE7_P_2_M_0 */
10989     { "vmovntdq",       { Mx, XM } },
10990   },
10991   {
10992     /* VEX_W_0FE8_P_2  */
10993     { "vpsubsb",        { XM, Vex, EXx } },
10994   },
10995   {
10996     /* VEX_W_0FE9_P_2  */
10997     { "vpsubsw",        { XM, Vex, EXx } },
10998   },
10999   {
11000     /* VEX_W_0FEA_P_2  */
11001     { "vpminsw",        { XM, Vex, EXx } },
11002   },
11003   {
11004     /* VEX_W_0FEB_P_2  */
11005     { "vpor",           { XM, Vex, EXx } },
11006   },
11007   {
11008     /* VEX_W_0FEC_P_2  */
11009     { "vpaddsb",        { XM, Vex, EXx } },
11010   },
11011   {
11012     /* VEX_W_0FED_P_2  */
11013     { "vpaddsw",        { XM, Vex, EXx } },
11014   },
11015   {
11016     /* VEX_W_0FEE_P_2  */
11017     { "vpmaxsw",        { XM, Vex, EXx } },
11018   },
11019   {
11020     /* VEX_W_0FEF_P_2  */
11021     { "vpxor",          { XM, Vex, EXx } },
11022   },
11023   {
11024     /* VEX_W_0FF0_P_3_M_0 */
11025     { "vlddqu",         { XM, M } },
11026   },
11027   {
11028     /* VEX_W_0FF1_P_2 */
11029     { "vpsllw",         { XM, Vex, EXxmm } },
11030   },
11031   {
11032     /* VEX_W_0FF2_P_2 */
11033     { "vpslld",         { XM, Vex, EXxmm } },
11034   },
11035   {
11036     /* VEX_W_0FF3_P_2 */
11037     { "vpsllq",         { XM, Vex, EXxmm } },
11038   },
11039   {
11040     /* VEX_W_0FF4_P_2 */
11041     { "vpmuludq",       { XM, Vex, EXx } },
11042   },
11043   {
11044     /* VEX_W_0FF5_P_2 */
11045     { "vpmaddwd",       { XM, Vex, EXx } },
11046   },
11047   {
11048     /* VEX_W_0FF6_P_2 */
11049     { "vpsadbw",        { XM, Vex, EXx } },
11050   },
11051   {
11052     /* VEX_W_0FF7_P_2 */
11053     { "vmaskmovdqu",    { XM, XS } },
11054   },
11055   {
11056     /* VEX_W_0FF8_P_2 */
11057     { "vpsubb",         { XM, Vex, EXx } },
11058   },
11059   {
11060     /* VEX_W_0FF9_P_2 */
11061     { "vpsubw",         { XM, Vex, EXx } },
11062   },
11063   {
11064     /* VEX_W_0FFA_P_2 */
11065     { "vpsubd",         { XM, Vex, EXx } },
11066   },
11067   {
11068     /* VEX_W_0FFB_P_2 */
11069     { "vpsubq",         { XM, Vex, EXx } },
11070   },
11071   {
11072     /* VEX_W_0FFC_P_2 */
11073     { "vpaddb",         { XM, Vex, EXx } },
11074   },
11075   {
11076     /* VEX_W_0FFD_P_2 */
11077     { "vpaddw",         { XM, Vex, EXx } },
11078   },
11079   {
11080     /* VEX_W_0FFE_P_2 */
11081     { "vpaddd",         { XM, Vex, EXx } },
11082   },
11083   {
11084     /* VEX_W_0F3800_P_2  */
11085     { "vpshufb",        { XM, Vex, EXx } },
11086   },
11087   {
11088     /* VEX_W_0F3801_P_2  */
11089     { "vphaddw",        { XM, Vex, EXx } },
11090   },
11091   {
11092     /* VEX_W_0F3802_P_2  */
11093     { "vphaddd",        { XM, Vex, EXx } },
11094   },
11095   {
11096     /* VEX_W_0F3803_P_2  */
11097     { "vphaddsw",       { XM, Vex, EXx } },
11098   },
11099   {
11100     /* VEX_W_0F3804_P_2  */
11101     { "vpmaddubsw",     { XM, Vex, EXx } },
11102   },
11103   {
11104     /* VEX_W_0F3805_P_2  */
11105     { "vphsubw",        { XM, Vex, EXx } },
11106   },
11107   {
11108     /* VEX_W_0F3806_P_2  */
11109     { "vphsubd",        { XM, Vex, EXx } },
11110   },
11111   {
11112     /* VEX_W_0F3807_P_2  */
11113     { "vphsubsw",       { XM, Vex, EXx } },
11114   },
11115   {
11116     /* VEX_W_0F3808_P_2  */
11117     { "vpsignb",        { XM, Vex, EXx } },
11118   },
11119   {
11120     /* VEX_W_0F3809_P_2  */
11121     { "vpsignw",        { XM, Vex, EXx } },
11122   },
11123   {
11124     /* VEX_W_0F380A_P_2  */
11125     { "vpsignd",        { XM, Vex, EXx } },
11126   },
11127   {
11128     /* VEX_W_0F380B_P_2  */
11129     { "vpmulhrsw",      { XM, Vex, EXx } },
11130   },
11131   {
11132     /* VEX_W_0F380C_P_2  */
11133     { "vpermilps",      { XM, Vex, EXx } },
11134   },
11135   {
11136     /* VEX_W_0F380D_P_2  */
11137     { "vpermilpd",      { XM, Vex, EXx } },
11138   },
11139   {
11140     /* VEX_W_0F380E_P_2  */
11141     { "vtestps",        { XM, EXx } },
11142   },
11143   {
11144     /* VEX_W_0F380F_P_2  */
11145     { "vtestpd",        { XM, EXx } },
11146   },
11147   {
11148     /* VEX_W_0F3816_P_2  */
11149     { "vpermps",        { XM, Vex, EXx } },
11150   },
11151   {
11152     /* VEX_W_0F3817_P_2 */
11153     { "vptest",         { XM, EXx } },
11154   },
11155   {
11156     /* VEX_W_0F3818_P_2 */
11157     { "vbroadcastss",   { XM, EXxmm_md } },
11158   },
11159   {
11160     /* VEX_W_0F3819_P_2 */
11161     { "vbroadcastsd",   { XM, EXxmm_mq } },
11162   },
11163   {
11164     /* VEX_W_0F381A_P_2_M_0 */
11165     { "vbroadcastf128", { XM, Mxmm } },
11166   },
11167   {
11168     /* VEX_W_0F381C_P_2 */
11169     { "vpabsb",         { XM, EXx } },
11170   },
11171   {
11172     /* VEX_W_0F381D_P_2 */
11173     { "vpabsw",         { XM, EXx } },
11174   },
11175   {
11176     /* VEX_W_0F381E_P_2 */
11177     { "vpabsd",         { XM, EXx } },
11178   },
11179   {
11180     /* VEX_W_0F3820_P_2 */
11181     { "vpmovsxbw",      { XM, EXxmmq } },
11182   },
11183   {
11184     /* VEX_W_0F3821_P_2 */
11185     { "vpmovsxbd",      { XM, EXxmmqd } },
11186   },
11187   {
11188     /* VEX_W_0F3822_P_2 */
11189     { "vpmovsxbq",      { XM, EXxmmdw } },
11190   },
11191   {
11192     /* VEX_W_0F3823_P_2 */
11193     { "vpmovsxwd",      { XM, EXxmmq } },
11194   },
11195   {
11196     /* VEX_W_0F3824_P_2 */
11197     { "vpmovsxwq",      { XM, EXxmmqd } },
11198   },
11199   {
11200     /* VEX_W_0F3825_P_2 */
11201     { "vpmovsxdq",      { XM, EXxmmq } },
11202   },
11203   {
11204     /* VEX_W_0F3828_P_2 */
11205     { "vpmuldq",        { XM, Vex, EXx } },
11206   },
11207   {
11208     /* VEX_W_0F3829_P_2 */
11209     { "vpcmpeqq",       { XM, Vex, EXx } },
11210   },
11211   {
11212     /* VEX_W_0F382A_P_2_M_0 */
11213     { "vmovntdqa",      { XM, Mx } },
11214   },
11215   {
11216     /* VEX_W_0F382B_P_2 */
11217     { "vpackusdw",      { XM, Vex, EXx } },
11218   },
11219   {
11220     /* VEX_W_0F382C_P_2_M_0 */
11221     { "vmaskmovps",     { XM, Vex, Mx } },
11222   },
11223   {
11224     /* VEX_W_0F382D_P_2_M_0 */
11225     { "vmaskmovpd",     { XM, Vex, Mx } },
11226   },
11227   {
11228     /* VEX_W_0F382E_P_2_M_0 */
11229     { "vmaskmovps",     { Mx, Vex, XM } },
11230   },
11231   {
11232     /* VEX_W_0F382F_P_2_M_0 */
11233     { "vmaskmovpd",     { Mx, Vex, XM } },
11234   },
11235   {
11236     /* VEX_W_0F3830_P_2 */
11237     { "vpmovzxbw",      { XM, EXxmmq } },
11238   },
11239   {
11240     /* VEX_W_0F3831_P_2 */
11241     { "vpmovzxbd",      { XM, EXxmmqd } },
11242   },
11243   {
11244     /* VEX_W_0F3832_P_2 */
11245     { "vpmovzxbq",      { XM, EXxmmdw } },
11246   },
11247   {
11248     /* VEX_W_0F3833_P_2 */
11249     { "vpmovzxwd",      { XM, EXxmmq } },
11250   },
11251   {
11252     /* VEX_W_0F3834_P_2 */
11253     { "vpmovzxwq",      { XM, EXxmmqd } },
11254   },
11255   {
11256     /* VEX_W_0F3835_P_2 */
11257     { "vpmovzxdq",      { XM, EXxmmq } },
11258   },
11259   {
11260     /* VEX_W_0F3836_P_2  */
11261     { "vpermd",         { XM, Vex, EXx } },
11262   },
11263   {
11264     /* VEX_W_0F3837_P_2 */
11265     { "vpcmpgtq",       { XM, Vex, EXx } },
11266   },
11267   {
11268     /* VEX_W_0F3838_P_2 */
11269     { "vpminsb",        { XM, Vex, EXx } },
11270   },
11271   {
11272     /* VEX_W_0F3839_P_2 */
11273     { "vpminsd",        { XM, Vex, EXx } },
11274   },
11275   {
11276     /* VEX_W_0F383A_P_2 */
11277     { "vpminuw",        { XM, Vex, EXx } },
11278   },
11279   {
11280     /* VEX_W_0F383B_P_2 */
11281     { "vpminud",        { XM, Vex, EXx } },
11282   },
11283   {
11284     /* VEX_W_0F383C_P_2 */
11285     { "vpmaxsb",        { XM, Vex, EXx } },
11286   },
11287   {
11288     /* VEX_W_0F383D_P_2 */
11289     { "vpmaxsd",        { XM, Vex, EXx } },
11290   },
11291   {
11292     /* VEX_W_0F383E_P_2 */
11293     { "vpmaxuw",        { XM, Vex, EXx } },
11294   },
11295   {
11296     /* VEX_W_0F383F_P_2 */
11297     { "vpmaxud",        { XM, Vex, EXx } },
11298   },
11299   {
11300     /* VEX_W_0F3840_P_2 */
11301     { "vpmulld",        { XM, Vex, EXx } },
11302   },
11303   {
11304     /* VEX_W_0F3841_P_2 */
11305     { "vphminposuw",    { XM, EXx } },
11306   },
11307   {
11308     /* VEX_W_0F3846_P_2 */
11309     { "vpsravd",        { XM, Vex, EXx } },
11310   },
11311   {
11312     /* VEX_W_0F3858_P_2 */
11313     { "vpbroadcastd", { XM, EXxmm_md } },
11314   },
11315   {
11316     /* VEX_W_0F3859_P_2 */
11317     { "vpbroadcastq",   { XM, EXxmm_mq } },
11318   },
11319   {
11320     /* VEX_W_0F385A_P_2_M_0 */
11321     { "vbroadcasti128", { XM, Mxmm } },
11322   },
11323   {
11324     /* VEX_W_0F3878_P_2 */
11325     { "vpbroadcastb",   { XM, EXxmm_mb } },
11326   },
11327   {
11328     /* VEX_W_0F3879_P_2 */
11329     { "vpbroadcastw",   { XM, EXxmm_mw } },
11330   },
11331   {
11332     /* VEX_W_0F38DB_P_2 */
11333     { "vaesimc",        { XM, EXx } },
11334   },
11335   {
11336     /* VEX_W_0F38DC_P_2 */
11337     { "vaesenc",        { XM, Vex128, EXx } },
11338   },
11339   {
11340     /* VEX_W_0F38DD_P_2 */
11341     { "vaesenclast",    { XM, Vex128, EXx } },
11342   },
11343   {
11344     /* VEX_W_0F38DE_P_2 */
11345     { "vaesdec",        { XM, Vex128, EXx } },
11346   },
11347   {
11348     /* VEX_W_0F38DF_P_2 */
11349     { "vaesdeclast",    { XM, Vex128, EXx } },
11350   },
11351   {
11352     /* VEX_W_0F3A00_P_2 */
11353     { Bad_Opcode },
11354     { "vpermq",         { XM, EXx, Ib } },
11355   },
11356   {
11357     /* VEX_W_0F3A01_P_2 */
11358     { Bad_Opcode },
11359     { "vpermpd",        { XM, EXx, Ib } },
11360   },
11361   {
11362     /* VEX_W_0F3A02_P_2 */
11363     { "vpblendd",       { XM, Vex, EXx, Ib } },
11364   },
11365   {
11366     /* VEX_W_0F3A04_P_2 */
11367     { "vpermilps",      { XM, EXx, Ib } },
11368   },
11369   {
11370     /* VEX_W_0F3A05_P_2 */
11371     { "vpermilpd",      { XM, EXx, Ib } },
11372   },
11373   {
11374     /* VEX_W_0F3A06_P_2 */
11375     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
11376   },
11377   {
11378     /* VEX_W_0F3A08_P_2 */
11379     { "vroundps",       { XM, EXx, Ib } },
11380   },
11381   {
11382     /* VEX_W_0F3A09_P_2 */
11383     { "vroundpd",       { XM, EXx, Ib } },
11384   },
11385   {
11386     /* VEX_W_0F3A0A_P_2 */
11387     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
11388   },
11389   {
11390     /* VEX_W_0F3A0B_P_2 */
11391     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
11392   },
11393   {
11394     /* VEX_W_0F3A0C_P_2 */
11395     { "vblendps",       { XM, Vex, EXx, Ib } },
11396   },
11397   {
11398     /* VEX_W_0F3A0D_P_2 */
11399     { "vblendpd",       { XM, Vex, EXx, Ib } },
11400   },
11401   {
11402     /* VEX_W_0F3A0E_P_2 */
11403     { "vpblendw",       { XM, Vex, EXx, Ib } },
11404   },
11405   {
11406     /* VEX_W_0F3A0F_P_2 */
11407     { "vpalignr",       { XM, Vex, EXx, Ib } },
11408   },
11409   {
11410     /* VEX_W_0F3A14_P_2 */
11411     { "vpextrb",        { Edqb, XM, Ib } },
11412   },
11413   {
11414     /* VEX_W_0F3A15_P_2 */
11415     { "vpextrw",        { Edqw, XM, Ib } },
11416   },
11417   {
11418     /* VEX_W_0F3A18_P_2 */
11419     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
11420   },
11421   {
11422     /* VEX_W_0F3A19_P_2 */
11423     { "vextractf128",   { EXxmm, XM, Ib } },
11424   },
11425   {
11426     /* VEX_W_0F3A20_P_2 */
11427     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
11428   },
11429   {
11430     /* VEX_W_0F3A21_P_2 */
11431     { "vinsertps",      { XM, Vex128, EXd, Ib } },
11432   },
11433   {
11434     /* VEX_W_0F3A30_P_2_LEN_0 */
11435     { "kshiftrb",       { MaskG, MaskR, Ib } },
11436     { "kshiftrw",       { MaskG, MaskR, Ib } },
11437   },
11438   {
11439     /* VEX_W_0F3A31_P_2_LEN_0 */
11440     { "kshiftrd",       { MaskG, MaskR, Ib } },
11441     { "kshiftrq",       { MaskG, MaskR, Ib } },
11442   },
11443   {
11444     /* VEX_W_0F3A32_P_2_LEN_0 */
11445     { "kshiftlb",       { MaskG, MaskR, Ib } },
11446     { "kshiftlw",       { MaskG, MaskR, Ib } },
11447   },
11448   {
11449     /* VEX_W_0F3A33_P_2_LEN_0 */
11450     { "kshiftld",       { MaskG, MaskR, Ib } },
11451     { "kshiftlq",       { MaskG, MaskR, Ib } },
11452   },
11453   {
11454     /* VEX_W_0F3A38_P_2 */
11455     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
11456   },
11457   {
11458     /* VEX_W_0F3A39_P_2 */
11459     { "vextracti128",   { EXxmm, XM, Ib } },
11460   },
11461   {
11462     /* VEX_W_0F3A40_P_2 */
11463     { "vdpps",          { XM, Vex, EXx, Ib } },
11464   },
11465   {
11466     /* VEX_W_0F3A41_P_2 */
11467     { "vdppd",          { XM, Vex128, EXx, Ib } },
11468   },
11469   {
11470     /* VEX_W_0F3A42_P_2 */
11471     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
11472   },
11473   {
11474     /* VEX_W_0F3A44_P_2 */
11475     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
11476   },
11477   {
11478     /* VEX_W_0F3A46_P_2 */
11479     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
11480   },
11481   {
11482     /* VEX_W_0F3A48_P_2 */
11483     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11484     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11485   },
11486   {
11487     /* VEX_W_0F3A49_P_2 */
11488     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11489     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11490   },
11491   {
11492     /* VEX_W_0F3A4A_P_2 */
11493     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
11494   },
11495   {
11496     /* VEX_W_0F3A4B_P_2 */
11497     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
11498   },
11499   {
11500     /* VEX_W_0F3A4C_P_2 */
11501     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
11502   },
11503   {
11504     /* VEX_W_0F3A60_P_2 */
11505     { "vpcmpestrm",     { XM, EXx, Ib } },
11506   },
11507   {
11508     /* VEX_W_0F3A61_P_2 */
11509     { "vpcmpestri",     { XM, EXx, Ib } },
11510   },
11511   {
11512     /* VEX_W_0F3A62_P_2 */
11513     { "vpcmpistrm",     { XM, EXx, Ib } },
11514   },
11515   {
11516     /* VEX_W_0F3A63_P_2 */
11517     { "vpcmpistri",     { XM, EXx, Ib } },
11518   },
11519   {
11520     /* VEX_W_0F3ADF_P_2 */
11521     { "vaeskeygenassist", { XM, EXx, Ib } },
11522   },
11523 #define NEED_VEX_W_TABLE
11524 #include "i386-dis-evex.h"
11525 #undef NEED_VEX_W_TABLE
11526 };
11527
11528 static const struct dis386 mod_table[][2] = {
11529   {
11530     /* MOD_8D */
11531     { "leaS",           { Gv, M } },
11532   },
11533   {
11534     /* MOD_C6_REG_7 */
11535     { Bad_Opcode },
11536     { RM_TABLE (RM_C6_REG_7) },
11537   },
11538   {
11539     /* MOD_C7_REG_7 */
11540     { Bad_Opcode },
11541     { RM_TABLE (RM_C7_REG_7) },
11542   },
11543   {
11544     /* MOD_FF_REG_3 */
11545     { "Jcall{T|}", { indirEp } },
11546   },
11547   {
11548     /* MOD_FF_REG_5 */
11549     { "Jjmp{T|}", { indirEp } },
11550   },
11551   {
11552     /* MOD_0F01_REG_0 */
11553     { X86_64_TABLE (X86_64_0F01_REG_0) },
11554     { RM_TABLE (RM_0F01_REG_0) },
11555   },
11556   {
11557     /* MOD_0F01_REG_1 */
11558     { X86_64_TABLE (X86_64_0F01_REG_1) },
11559     { RM_TABLE (RM_0F01_REG_1) },
11560   },
11561   {
11562     /* MOD_0F01_REG_2 */
11563     { X86_64_TABLE (X86_64_0F01_REG_2) },
11564     { RM_TABLE (RM_0F01_REG_2) },
11565   },
11566   {
11567     /* MOD_0F01_REG_3 */
11568     { X86_64_TABLE (X86_64_0F01_REG_3) },
11569     { RM_TABLE (RM_0F01_REG_3) },
11570   },
11571   {
11572     /* MOD_0F01_REG_7 */
11573     { "invlpg",         { Mb } },
11574     { RM_TABLE (RM_0F01_REG_7) },
11575   },
11576   {
11577     /* MOD_0F12_PREFIX_0 */
11578     { "movlps",         { XM, EXq } },
11579     { "movhlps",        { XM, EXq } },
11580   },
11581   {
11582     /* MOD_0F13 */
11583     { "movlpX",         { EXq, XM } },
11584   },
11585   {
11586     /* MOD_0F16_PREFIX_0 */
11587     { "movhps",         { XM, EXq } },
11588     { "movlhps",        { XM, EXq } },
11589   },
11590   {
11591     /* MOD_0F17 */
11592     { "movhpX",         { EXq, XM } },
11593   },
11594   {
11595     /* MOD_0F18_REG_0 */
11596     { "prefetchnta",    { Mb } },
11597   },
11598   {
11599     /* MOD_0F18_REG_1 */
11600     { "prefetcht0",     { Mb } },
11601   },
11602   {
11603     /* MOD_0F18_REG_2 */
11604     { "prefetcht1",     { Mb } },
11605   },
11606   {
11607     /* MOD_0F18_REG_3 */
11608     { "prefetcht2",     { Mb } },
11609   },
11610   {
11611     /* MOD_0F18_REG_4 */
11612     { "nop/reserved",   { Mb } },
11613   },
11614   {
11615     /* MOD_0F18_REG_5 */
11616     { "nop/reserved",   { Mb } },
11617   },
11618   {
11619     /* MOD_0F18_REG_6 */
11620     { "nop/reserved",   { Mb } },
11621   },
11622   {
11623     /* MOD_0F18_REG_7 */
11624     { "nop/reserved",   { Mb } },
11625   },
11626   {
11627     /* MOD_0F1A_PREFIX_0 */
11628     { "bndldx",         { Gbnd, Ev_bnd } },
11629     { "nopQ",           { Ev } },
11630   },
11631   {
11632     /* MOD_0F1B_PREFIX_0 */
11633     { "bndstx",         { Ev_bnd, Gbnd } },
11634     { "nopQ",           { Ev } },
11635   },
11636   {
11637     /* MOD_0F1B_PREFIX_1 */
11638     { "bndmk",          { Gbnd, Ev_bnd } },
11639     { "nopQ",           { Ev } },
11640   },
11641   {
11642     /* MOD_0F20 */
11643     { Bad_Opcode },
11644     { "movZ",           { Rm, Cm } },
11645   },
11646   {
11647     /* MOD_0F21 */
11648     { Bad_Opcode },
11649     { "movZ",           { Rm, Dm } },
11650   },
11651   {
11652     /* MOD_0F22 */
11653     { Bad_Opcode },
11654     { "movZ",           { Cm, Rm } },
11655   },
11656   {
11657     /* MOD_0F23 */
11658     { Bad_Opcode },
11659     { "movZ",           { Dm, Rm } },
11660   },
11661   {
11662     /* MOD_0F24 */
11663     { Bad_Opcode },
11664     { "movL",           { Rd, Td } },
11665   },
11666   {
11667     /* MOD_0F26 */
11668     { Bad_Opcode },
11669     { "movL",           { Td, Rd } },
11670   },
11671   {
11672     /* MOD_0F2B_PREFIX_0 */
11673     {"movntps",         { Mx, XM } },
11674   },
11675   {
11676     /* MOD_0F2B_PREFIX_1 */
11677     {"movntss",         { Md, XM } },
11678   },
11679   {
11680     /* MOD_0F2B_PREFIX_2 */
11681     {"movntpd",         { Mx, XM } },
11682   },
11683   {
11684     /* MOD_0F2B_PREFIX_3 */
11685     {"movntsd",         { Mq, XM } },
11686   },
11687   {
11688     /* MOD_0F51 */
11689     { Bad_Opcode },
11690     { "movmskpX",       { Gdq, XS } },
11691   },
11692   {
11693     /* MOD_0F71_REG_2 */
11694     { Bad_Opcode },
11695     { "psrlw",          { MS, Ib } },
11696   },
11697   {
11698     /* MOD_0F71_REG_4 */
11699     { Bad_Opcode },
11700     { "psraw",          { MS, Ib } },
11701   },
11702   {
11703     /* MOD_0F71_REG_6 */
11704     { Bad_Opcode },
11705     { "psllw",          { MS, Ib } },
11706   },
11707   {
11708     /* MOD_0F72_REG_2 */
11709     { Bad_Opcode },
11710     { "psrld",          { MS, Ib } },
11711   },
11712   {
11713     /* MOD_0F72_REG_4 */
11714     { Bad_Opcode },
11715     { "psrad",          { MS, Ib } },
11716   },
11717   {
11718     /* MOD_0F72_REG_6 */
11719     { Bad_Opcode },
11720     { "pslld",          { MS, Ib } },
11721   },
11722   {
11723     /* MOD_0F73_REG_2 */
11724     { Bad_Opcode },
11725     { "psrlq",          { MS, Ib } },
11726   },
11727   {
11728     /* MOD_0F73_REG_3 */
11729     { Bad_Opcode },
11730     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11731   },
11732   {
11733     /* MOD_0F73_REG_6 */
11734     { Bad_Opcode },
11735     { "psllq",          { MS, Ib } },
11736   },
11737   {
11738     /* MOD_0F73_REG_7 */
11739     { Bad_Opcode },
11740     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11741   },
11742   {
11743     /* MOD_0FAE_REG_0 */
11744     { "fxsave",         { FXSAVE } },
11745     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11746   },
11747   {
11748     /* MOD_0FAE_REG_1 */
11749     { "fxrstor",        { FXSAVE } },
11750     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11751   },
11752   {
11753     /* MOD_0FAE_REG_2 */
11754     { "ldmxcsr",        { Md } },
11755     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11756   },
11757   {
11758     /* MOD_0FAE_REG_3 */
11759     { "stmxcsr",        { Md } },
11760     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11761   },
11762   {
11763     /* MOD_0FAE_REG_4 */
11764     { "xsave",          { FXSAVE } },
11765   },
11766   {
11767     /* MOD_0FAE_REG_5 */
11768     { "xrstor",         { FXSAVE } },
11769     { RM_TABLE (RM_0FAE_REG_5) },
11770   },
11771   {
11772     /* MOD_0FAE_REG_6 */
11773     { "xsaveopt",       { FXSAVE } },
11774     { RM_TABLE (RM_0FAE_REG_6) },
11775   },
11776   {
11777     /* MOD_0FAE_REG_7 */
11778     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11779     { RM_TABLE (RM_0FAE_REG_7) },
11780   },
11781   {
11782     /* MOD_0FB2 */
11783     { "lssS",           { Gv, Mp } },
11784   },
11785   {
11786     /* MOD_0FB4 */
11787     { "lfsS",           { Gv, Mp } },
11788   },
11789   {
11790     /* MOD_0FB5 */
11791     { "lgsS",           { Gv, Mp } },
11792   },
11793   {
11794     /* MOD_0FC7_REG_3 */
11795     { "xrstors",                { FXSAVE } },
11796   },
11797   {
11798     /* MOD_0FC7_REG_4 */
11799     { "xsavec",         { FXSAVE } },
11800   },
11801   {
11802     /* MOD_0FC7_REG_5 */
11803     { "xsaves",         { FXSAVE } },
11804   },
11805   {
11806     /* MOD_0FC7_REG_6 */
11807     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11808     { "rdrand",         { Ev } },
11809   },
11810   {
11811     /* MOD_0FC7_REG_7 */
11812     { "vmptrst",        { Mq } },
11813     { "rdseed",         { Ev } },
11814   },
11815   {
11816     /* MOD_0FD7 */
11817     { Bad_Opcode },
11818     { "pmovmskb",       { Gdq, MS } },
11819   },
11820   {
11821     /* MOD_0FE7_PREFIX_2 */
11822     { "movntdq",        { Mx, XM } },
11823   },
11824   {
11825     /* MOD_0FF0_PREFIX_3 */
11826     { "lddqu",          { XM, M } },
11827   },
11828   {
11829     /* MOD_0F382A_PREFIX_2 */
11830     { "movntdqa",       { XM, Mx } },
11831   },
11832   {
11833     /* MOD_62_32BIT */
11834     { "bound{S|}",      { Gv, Ma } },
11835     { EVEX_TABLE (EVEX_0F) },
11836   },
11837   {
11838     /* MOD_C4_32BIT */
11839     { "lesS",           { Gv, Mp } },
11840     { VEX_C4_TABLE (VEX_0F) },
11841   },
11842   {
11843     /* MOD_C5_32BIT */
11844     { "ldsS",           { Gv, Mp } },
11845     { VEX_C5_TABLE (VEX_0F) },
11846   },
11847   {
11848     /* MOD_VEX_0F12_PREFIX_0 */
11849     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11850     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11851   },
11852   {
11853     /* MOD_VEX_0F13 */
11854     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11855   },
11856   {
11857     /* MOD_VEX_0F16_PREFIX_0 */
11858     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11859     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11860   },
11861   {
11862     /* MOD_VEX_0F17 */
11863     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11864   },
11865   {
11866     /* MOD_VEX_0F2B */
11867     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11868   },
11869   {
11870     /* MOD_VEX_0F50 */
11871     { Bad_Opcode },
11872     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11873   },
11874   {
11875     /* MOD_VEX_0F71_REG_2 */
11876     { Bad_Opcode },
11877     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11878   },
11879   {
11880     /* MOD_VEX_0F71_REG_4 */
11881     { Bad_Opcode },
11882     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11883   },
11884   {
11885     /* MOD_VEX_0F71_REG_6 */
11886     { Bad_Opcode },
11887     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11888   },
11889   {
11890     /* MOD_VEX_0F72_REG_2 */
11891     { Bad_Opcode },
11892     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11893   },
11894   {
11895     /* MOD_VEX_0F72_REG_4 */
11896     { Bad_Opcode },
11897     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11898   },
11899   {
11900     /* MOD_VEX_0F72_REG_6 */
11901     { Bad_Opcode },
11902     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11903   },
11904   {
11905     /* MOD_VEX_0F73_REG_2 */
11906     { Bad_Opcode },
11907     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11908   },
11909   {
11910     /* MOD_VEX_0F73_REG_3 */
11911     { Bad_Opcode },
11912     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11913   },
11914   {
11915     /* MOD_VEX_0F73_REG_6 */
11916     { Bad_Opcode },
11917     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11918   },
11919   {
11920     /* MOD_VEX_0F73_REG_7 */
11921     { Bad_Opcode },
11922     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11923   },
11924   {
11925     /* MOD_VEX_0FAE_REG_2 */
11926     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11927   },
11928   {
11929     /* MOD_VEX_0FAE_REG_3 */
11930     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11931   },
11932   {
11933     /* MOD_VEX_0FD7_PREFIX_2 */
11934     { Bad_Opcode },
11935     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11936   },
11937   {
11938     /* MOD_VEX_0FE7_PREFIX_2 */
11939     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11940   },
11941   {
11942     /* MOD_VEX_0FF0_PREFIX_3 */
11943     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11944   },
11945   {
11946     /* MOD_VEX_0F381A_PREFIX_2 */
11947     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11948   },
11949   {
11950     /* MOD_VEX_0F382A_PREFIX_2 */
11951     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11952   },
11953   {
11954     /* MOD_VEX_0F382C_PREFIX_2 */
11955     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11956   },
11957   {
11958     /* MOD_VEX_0F382D_PREFIX_2 */
11959     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11960   },
11961   {
11962     /* MOD_VEX_0F382E_PREFIX_2 */
11963     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11964   },
11965   {
11966     /* MOD_VEX_0F382F_PREFIX_2 */
11967     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11968   },
11969   {
11970     /* MOD_VEX_0F385A_PREFIX_2 */
11971     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11972   },
11973   {
11974     /* MOD_VEX_0F388C_PREFIX_2 */
11975     { "vpmaskmov%LW",   { XM, Vex, Mx } },
11976   },
11977   {
11978     /* MOD_VEX_0F388E_PREFIX_2 */
11979     { "vpmaskmov%LW",   { Mx, Vex, XM } },
11980   },
11981 #define NEED_MOD_TABLE
11982 #include "i386-dis-evex.h"
11983 #undef NEED_MOD_TABLE
11984 };
11985
11986 static const struct dis386 rm_table[][8] = {
11987   {
11988     /* RM_C6_REG_7 */
11989     { "xabort",         { Skip_MODRM, Ib } },
11990   },
11991   {
11992     /* RM_C7_REG_7 */
11993     { "xbeginT",        { Skip_MODRM, Jv } },
11994   },
11995   {
11996     /* RM_0F01_REG_0 */
11997     { Bad_Opcode },
11998     { "vmcall",         { Skip_MODRM } },
11999     { "vmlaunch",       { Skip_MODRM } },
12000     { "vmresume",       { Skip_MODRM } },
12001     { "vmxoff",         { Skip_MODRM } },
12002   },
12003   {
12004     /* RM_0F01_REG_1 */
12005     { "monitor",        { { OP_Monitor, 0 } } },
12006     { "mwait",          { { OP_Mwait, 0 } } },
12007     { "clac",           { Skip_MODRM } },
12008     { "stac",           { Skip_MODRM } },
12009     { Bad_Opcode },
12010     { Bad_Opcode },
12011     { Bad_Opcode },
12012     { "encls",          { Skip_MODRM } },
12013   },
12014   {
12015     /* RM_0F01_REG_2 */
12016     { "xgetbv",         { Skip_MODRM } },
12017     { "xsetbv",         { Skip_MODRM } },
12018     { Bad_Opcode },
12019     { Bad_Opcode },
12020     { "vmfunc",         { Skip_MODRM } },
12021     { "xend",           { Skip_MODRM } },
12022     { "xtest",          { Skip_MODRM } },
12023     { "enclu",          { Skip_MODRM } },
12024   },
12025   {
12026     /* RM_0F01_REG_3 */
12027     { "vmrun",          { Skip_MODRM } },
12028     { "vmmcall",        { Skip_MODRM } },
12029     { "vmload",         { Skip_MODRM } },
12030     { "vmsave",         { Skip_MODRM } },
12031     { "stgi",           { Skip_MODRM } },
12032     { "clgi",           { Skip_MODRM } },
12033     { "skinit",         { Skip_MODRM } },
12034     { "invlpga",        { Skip_MODRM } },
12035   },
12036   {
12037     /* RM_0F01_REG_7 */
12038     { "swapgs",         { Skip_MODRM } },
12039     { "rdtscp",         { Skip_MODRM } },
12040   },
12041   {
12042     /* RM_0FAE_REG_5 */
12043     { "lfence",         { Skip_MODRM } },
12044   },
12045   {
12046     /* RM_0FAE_REG_6 */
12047     { "mfence",         { Skip_MODRM } },
12048   },
12049   {
12050     /* RM_0FAE_REG_7 */
12051     { "sfence",         { Skip_MODRM } },
12052   },
12053 };
12054
12055 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12056
12057 /* We use the high bit to indicate different name for the same
12058    prefix.  */
12059 #define REP_PREFIX      (0xf3 | 0x100)
12060 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12061 #define XRELEASE_PREFIX (0xf3 | 0x400)
12062 #define BND_PREFIX      (0xf2 | 0x400)
12063
12064 static int
12065 ckprefix (void)
12066 {
12067   int newrex, i, length;
12068   rex = 0;
12069   rex_ignored = 0;
12070   prefixes = 0;
12071   used_prefixes = 0;
12072   rex_used = 0;
12073   last_lock_prefix = -1;
12074   last_repz_prefix = -1;
12075   last_repnz_prefix = -1;
12076   last_data_prefix = -1;
12077   last_addr_prefix = -1;
12078   last_rex_prefix = -1;
12079   last_seg_prefix = -1;
12080   fwait_prefix = -1;
12081   active_seg_prefix = 0;
12082   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12083     all_prefixes[i] = 0;
12084   i = 0;
12085   length = 0;
12086   /* The maximum instruction length is 15bytes.  */
12087   while (length < MAX_CODE_LENGTH - 1)
12088     {
12089       FETCH_DATA (the_info, codep + 1);
12090       newrex = 0;
12091       switch (*codep)
12092         {
12093         /* REX prefixes family.  */
12094         case 0x40:
12095         case 0x41:
12096         case 0x42:
12097         case 0x43:
12098         case 0x44:
12099         case 0x45:
12100         case 0x46:
12101         case 0x47:
12102         case 0x48:
12103         case 0x49:
12104         case 0x4a:
12105         case 0x4b:
12106         case 0x4c:
12107         case 0x4d:
12108         case 0x4e:
12109         case 0x4f:
12110           if (address_mode == mode_64bit)
12111             newrex = *codep;
12112           else
12113             return 1;
12114           last_rex_prefix = i;
12115           break;
12116         case 0xf3:
12117           prefixes |= PREFIX_REPZ;
12118           last_repz_prefix = i;
12119           break;
12120         case 0xf2:
12121           prefixes |= PREFIX_REPNZ;
12122           last_repnz_prefix = i;
12123           break;
12124         case 0xf0:
12125           prefixes |= PREFIX_LOCK;
12126           last_lock_prefix = i;
12127           break;
12128         case 0x2e:
12129           prefixes |= PREFIX_CS;
12130           last_seg_prefix = i;
12131           active_seg_prefix = PREFIX_CS;
12132           break;
12133         case 0x36:
12134           prefixes |= PREFIX_SS;
12135           last_seg_prefix = i;
12136           active_seg_prefix = PREFIX_SS;
12137           break;
12138         case 0x3e:
12139           prefixes |= PREFIX_DS;
12140           last_seg_prefix = i;
12141           active_seg_prefix = PREFIX_DS;
12142           break;
12143         case 0x26:
12144           prefixes |= PREFIX_ES;
12145           last_seg_prefix = i;
12146           active_seg_prefix = PREFIX_ES;
12147           break;
12148         case 0x64:
12149           prefixes |= PREFIX_FS;
12150           last_seg_prefix = i;
12151           active_seg_prefix = PREFIX_FS;
12152           break;
12153         case 0x65:
12154           prefixes |= PREFIX_GS;
12155           last_seg_prefix = i;
12156           active_seg_prefix = PREFIX_GS;
12157           break;
12158         case 0x66:
12159           prefixes |= PREFIX_DATA;
12160           last_data_prefix = i;
12161           break;
12162         case 0x67:
12163           prefixes |= PREFIX_ADDR;
12164           last_addr_prefix = i;
12165           break;
12166         case FWAIT_OPCODE:
12167           /* fwait is really an instruction.  If there are prefixes
12168              before the fwait, they belong to the fwait, *not* to the
12169              following instruction.  */
12170           fwait_prefix = i;
12171           if (prefixes || rex)
12172             {
12173               prefixes |= PREFIX_FWAIT;
12174               codep++;
12175               /* This ensures that the previous REX prefixes are noticed
12176                  as unused prefixes, as in the return case below.  */
12177               rex_used = rex;
12178               return 1;
12179             }
12180           prefixes = PREFIX_FWAIT;
12181           break;
12182         default:
12183           return 1;
12184         }
12185       /* Rex is ignored when followed by another prefix.  */
12186       if (rex)
12187         {
12188           rex_used = rex;
12189           return 1;
12190         }
12191       if (*codep != FWAIT_OPCODE)
12192         all_prefixes[i++] = *codep;
12193       rex = newrex;
12194       codep++;
12195       length++;
12196     }
12197   return 0;
12198 }
12199
12200 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12201    prefix byte.  */
12202
12203 static const char *
12204 prefix_name (int pref, int sizeflag)
12205 {
12206   static const char *rexes [16] =
12207     {
12208       "rex",            /* 0x40 */
12209       "rex.B",          /* 0x41 */
12210       "rex.X",          /* 0x42 */
12211       "rex.XB",         /* 0x43 */
12212       "rex.R",          /* 0x44 */
12213       "rex.RB",         /* 0x45 */
12214       "rex.RX",         /* 0x46 */
12215       "rex.RXB",        /* 0x47 */
12216       "rex.W",          /* 0x48 */
12217       "rex.WB",         /* 0x49 */
12218       "rex.WX",         /* 0x4a */
12219       "rex.WXB",        /* 0x4b */
12220       "rex.WR",         /* 0x4c */
12221       "rex.WRB",        /* 0x4d */
12222       "rex.WRX",        /* 0x4e */
12223       "rex.WRXB",       /* 0x4f */
12224     };
12225
12226   switch (pref)
12227     {
12228     /* REX prefixes family.  */
12229     case 0x40:
12230     case 0x41:
12231     case 0x42:
12232     case 0x43:
12233     case 0x44:
12234     case 0x45:
12235     case 0x46:
12236     case 0x47:
12237     case 0x48:
12238     case 0x49:
12239     case 0x4a:
12240     case 0x4b:
12241     case 0x4c:
12242     case 0x4d:
12243     case 0x4e:
12244     case 0x4f:
12245       return rexes [pref - 0x40];
12246     case 0xf3:
12247       return "repz";
12248     case 0xf2:
12249       return "repnz";
12250     case 0xf0:
12251       return "lock";
12252     case 0x2e:
12253       return "cs";
12254     case 0x36:
12255       return "ss";
12256     case 0x3e:
12257       return "ds";
12258     case 0x26:
12259       return "es";
12260     case 0x64:
12261       return "fs";
12262     case 0x65:
12263       return "gs";
12264     case 0x66:
12265       return (sizeflag & DFLAG) ? "data16" : "data32";
12266     case 0x67:
12267       if (address_mode == mode_64bit)
12268         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12269       else
12270         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12271     case FWAIT_OPCODE:
12272       return "fwait";
12273     case REP_PREFIX:
12274       return "rep";
12275     case XACQUIRE_PREFIX:
12276       return "xacquire";
12277     case XRELEASE_PREFIX:
12278       return "xrelease";
12279     case BND_PREFIX:
12280       return "bnd";
12281     default:
12282       return NULL;
12283     }
12284 }
12285
12286 static char op_out[MAX_OPERANDS][100];
12287 static int op_ad, op_index[MAX_OPERANDS];
12288 static int two_source_ops;
12289 static bfd_vma op_address[MAX_OPERANDS];
12290 static bfd_vma op_riprel[MAX_OPERANDS];
12291 static bfd_vma start_pc;
12292
12293 /*
12294  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12295  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12296  *   section of the "Virtual 8086 Mode" chapter.)
12297  * 'pc' should be the address of this instruction, it will
12298  *   be used to print the target address if this is a relative jump or call
12299  * The function returns the length of this instruction in bytes.
12300  */
12301
12302 static char intel_syntax;
12303 static char intel_mnemonic = !SYSV386_COMPAT;
12304 static char open_char;
12305 static char close_char;
12306 static char separator_char;
12307 static char scale_char;
12308
12309 /* Here for backwards compatibility.  When gdb stops using
12310    print_insn_i386_att and print_insn_i386_intel these functions can
12311    disappear, and print_insn_i386 be merged into print_insn.  */
12312 int
12313 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12314 {
12315   intel_syntax = 0;
12316
12317   return print_insn (pc, info);
12318 }
12319
12320 int
12321 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12322 {
12323   intel_syntax = 1;
12324
12325   return print_insn (pc, info);
12326 }
12327
12328 int
12329 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12330 {
12331   intel_syntax = -1;
12332
12333   return print_insn (pc, info);
12334 }
12335
12336 void
12337 print_i386_disassembler_options (FILE *stream)
12338 {
12339   fprintf (stream, _("\n\
12340 The following i386/x86-64 specific disassembler options are supported for use\n\
12341 with the -M switch (multiple options should be separated by commas):\n"));
12342
12343   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12344   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12345   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12346   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12347   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12348   fprintf (stream, _("  att-mnemonic\n"
12349                      "              Display instruction in AT&T mnemonic\n"));
12350   fprintf (stream, _("  intel-mnemonic\n"
12351                      "              Display instruction in Intel mnemonic\n"));
12352   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12353   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12354   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12355   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12356   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12357   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12358 }
12359
12360 /* Bad opcode.  */
12361 static const struct dis386 bad_opcode = { "(bad)", { XX } };
12362
12363 /* Get a pointer to struct dis386 with a valid name.  */
12364
12365 static const struct dis386 *
12366 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12367 {
12368   int vindex, vex_table_index;
12369
12370   if (dp->name != NULL)
12371     return dp;
12372
12373   switch (dp->op[0].bytemode)
12374     {
12375     case USE_REG_TABLE:
12376       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12377       break;
12378
12379     case USE_MOD_TABLE:
12380       vindex = modrm.mod == 0x3 ? 1 : 0;
12381       dp = &mod_table[dp->op[1].bytemode][vindex];
12382       break;
12383
12384     case USE_RM_TABLE:
12385       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12386       break;
12387
12388     case USE_PREFIX_TABLE:
12389       if (need_vex)
12390         {
12391           /* The prefix in VEX is implicit.  */
12392           switch (vex.prefix)
12393             {
12394             case 0:
12395               vindex = 0;
12396               break;
12397             case REPE_PREFIX_OPCODE:
12398               vindex = 1;
12399               break;
12400             case DATA_PREFIX_OPCODE:
12401               vindex = 2;
12402               break;
12403             case REPNE_PREFIX_OPCODE:
12404               vindex = 3;
12405               break;
12406             default:
12407               abort ();
12408               break;
12409             }
12410         }
12411       else
12412         {
12413           int last_prefix = -1;
12414           int prefix = 0;
12415           vindex = 0;
12416           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12417              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12418              last one wins.  */
12419           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12420             {
12421               if (last_repz_prefix > last_repnz_prefix)
12422                 {
12423                   vindex = 1;
12424                   prefix = PREFIX_REPZ;
12425                   last_prefix = last_repz_prefix;
12426                 }
12427               else
12428                 {
12429                   vindex = 3;
12430                   prefix = PREFIX_REPNZ;
12431                   last_prefix = last_repnz_prefix;
12432                 }
12433
12434               /* Ignore the invalid index if it isn't mandatory.  */
12435               if (!mandatory_prefix
12436                   && (prefix_table[dp->op[1].bytemode][vindex].name
12437                       == NULL)
12438                   && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
12439                       == 0))
12440                 vindex = 0;
12441             }
12442
12443           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12444             {
12445               vindex = 2;
12446               prefix = PREFIX_DATA;
12447               last_prefix = last_data_prefix;
12448             }
12449
12450           if (vindex != 0)
12451             {
12452               used_prefixes |= prefix;
12453               all_prefixes[last_prefix] = 0;
12454             }
12455         }
12456       dp = &prefix_table[dp->op[1].bytemode][vindex];
12457       break;
12458
12459     case USE_X86_64_TABLE:
12460       vindex = address_mode == mode_64bit ? 1 : 0;
12461       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12462       break;
12463
12464     case USE_3BYTE_TABLE:
12465       FETCH_DATA (info, codep + 2);
12466       vindex = *codep++;
12467       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12468       end_codep = codep;
12469       modrm.mod = (*codep >> 6) & 3;
12470       modrm.reg = (*codep >> 3) & 7;
12471       modrm.rm = *codep & 7;
12472       break;
12473
12474     case USE_VEX_LEN_TABLE:
12475       if (!need_vex)
12476         abort ();
12477
12478       switch (vex.length)
12479         {
12480         case 128:
12481           vindex = 0;
12482           break;
12483         case 256:
12484           vindex = 1;
12485           break;
12486         default:
12487           abort ();
12488           break;
12489         }
12490
12491       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12492       break;
12493
12494     case USE_XOP_8F_TABLE:
12495       FETCH_DATA (info, codep + 3);
12496       /* All bits in the REX prefix are ignored.  */
12497       rex_ignored = rex;
12498       rex = ~(*codep >> 5) & 0x7;
12499
12500       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12501       switch ((*codep & 0x1f))
12502         {
12503         default:
12504           dp = &bad_opcode;
12505           return dp;
12506         case 0x8:
12507           vex_table_index = XOP_08;
12508           break;
12509         case 0x9:
12510           vex_table_index = XOP_09;
12511           break;
12512         case 0xa:
12513           vex_table_index = XOP_0A;
12514           break;
12515         }
12516       codep++;
12517       vex.w = *codep & 0x80;
12518       if (vex.w && address_mode == mode_64bit)
12519         rex |= REX_W;
12520
12521       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12522       if (address_mode != mode_64bit
12523           && vex.register_specifier > 0x7)
12524         {
12525           dp = &bad_opcode;
12526           return dp;
12527         }
12528
12529       vex.length = (*codep & 0x4) ? 256 : 128;
12530       switch ((*codep & 0x3))
12531         {
12532         case 0:
12533           vex.prefix = 0;
12534           break;
12535         case 1:
12536           vex.prefix = DATA_PREFIX_OPCODE;
12537           break;
12538         case 2:
12539           vex.prefix = REPE_PREFIX_OPCODE;
12540           break;
12541         case 3:
12542           vex.prefix = REPNE_PREFIX_OPCODE;
12543           break;
12544         }
12545       need_vex = 1;
12546       need_vex_reg = 1;
12547       codep++;
12548       vindex = *codep++;
12549       dp = &xop_table[vex_table_index][vindex];
12550
12551       end_codep = codep;
12552       FETCH_DATA (info, codep + 1);
12553       modrm.mod = (*codep >> 6) & 3;
12554       modrm.reg = (*codep >> 3) & 7;
12555       modrm.rm = *codep & 7;
12556       break;
12557
12558     case USE_VEX_C4_TABLE:
12559       /* VEX prefix.  */
12560       FETCH_DATA (info, codep + 3);
12561       /* All bits in the REX prefix are ignored.  */
12562       rex_ignored = rex;
12563       rex = ~(*codep >> 5) & 0x7;
12564       switch ((*codep & 0x1f))
12565         {
12566         default:
12567           dp = &bad_opcode;
12568           return dp;
12569         case 0x1:
12570           vex_table_index = VEX_0F;
12571           break;
12572         case 0x2:
12573           vex_table_index = VEX_0F38;
12574           break;
12575         case 0x3:
12576           vex_table_index = VEX_0F3A;
12577           break;
12578         }
12579       codep++;
12580       vex.w = *codep & 0x80;
12581       if (vex.w && address_mode == mode_64bit)
12582         rex |= REX_W;
12583
12584       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12585       if (address_mode != mode_64bit
12586           && vex.register_specifier > 0x7)
12587         {
12588           dp = &bad_opcode;
12589           return dp;
12590         }
12591
12592       vex.length = (*codep & 0x4) ? 256 : 128;
12593       switch ((*codep & 0x3))
12594         {
12595         case 0:
12596           vex.prefix = 0;
12597           break;
12598         case 1:
12599           vex.prefix = DATA_PREFIX_OPCODE;
12600           break;
12601         case 2:
12602           vex.prefix = REPE_PREFIX_OPCODE;
12603           break;
12604         case 3:
12605           vex.prefix = REPNE_PREFIX_OPCODE;
12606           break;
12607         }
12608       need_vex = 1;
12609       need_vex_reg = 1;
12610       codep++;
12611       vindex = *codep++;
12612       dp = &vex_table[vex_table_index][vindex];
12613       end_codep = codep;
12614       /* There is no MODRM byte for VEX [82|77].  */
12615       if (vindex != 0x77 && vindex != 0x82)
12616         {
12617           FETCH_DATA (info, codep + 1);
12618           modrm.mod = (*codep >> 6) & 3;
12619           modrm.reg = (*codep >> 3) & 7;
12620           modrm.rm = *codep & 7;
12621         }
12622       break;
12623
12624     case USE_VEX_C5_TABLE:
12625       /* VEX prefix.  */
12626       FETCH_DATA (info, codep + 2);
12627       /* All bits in the REX prefix are ignored.  */
12628       rex_ignored = rex;
12629       rex = (*codep & 0x80) ? 0 : REX_R;
12630
12631       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12632       if (address_mode != mode_64bit
12633           && vex.register_specifier > 0x7)
12634         {
12635           dp = &bad_opcode;
12636           return dp;
12637         }
12638
12639       vex.w = 0;
12640
12641       vex.length = (*codep & 0x4) ? 256 : 128;
12642       switch ((*codep & 0x3))
12643         {
12644         case 0:
12645           vex.prefix = 0;
12646           break;
12647         case 1:
12648           vex.prefix = DATA_PREFIX_OPCODE;
12649           break;
12650         case 2:
12651           vex.prefix = REPE_PREFIX_OPCODE;
12652           break;
12653         case 3:
12654           vex.prefix = REPNE_PREFIX_OPCODE;
12655           break;
12656         }
12657       need_vex = 1;
12658       need_vex_reg = 1;
12659       codep++;
12660       vindex = *codep++;
12661       dp = &vex_table[dp->op[1].bytemode][vindex];
12662       end_codep = codep;
12663       /* There is no MODRM byte for VEX [82|77].  */
12664       if (vindex != 0x77 && vindex != 0x82)
12665         {
12666           FETCH_DATA (info, codep + 1);
12667           modrm.mod = (*codep >> 6) & 3;
12668           modrm.reg = (*codep >> 3) & 7;
12669           modrm.rm = *codep & 7;
12670         }
12671       break;
12672
12673     case USE_VEX_W_TABLE:
12674       if (!need_vex)
12675         abort ();
12676
12677       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12678       break;
12679
12680     case USE_EVEX_TABLE:
12681       two_source_ops = 0;
12682       /* EVEX prefix.  */
12683       vex.evex = 1;
12684       FETCH_DATA (info, codep + 4);
12685       /* All bits in the REX prefix are ignored.  */
12686       rex_ignored = rex;
12687       /* The first byte after 0x62.  */
12688       rex = ~(*codep >> 5) & 0x7;
12689       vex.r = *codep & 0x10;
12690       switch ((*codep & 0xf))
12691         {
12692         default:
12693           return &bad_opcode;
12694         case 0x1:
12695           vex_table_index = EVEX_0F;
12696           break;
12697         case 0x2:
12698           vex_table_index = EVEX_0F38;
12699           break;
12700         case 0x3:
12701           vex_table_index = EVEX_0F3A;
12702           break;
12703         }
12704
12705       /* The second byte after 0x62.  */
12706       codep++;
12707       vex.w = *codep & 0x80;
12708       if (vex.w && address_mode == mode_64bit)
12709         rex |= REX_W;
12710
12711       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12712       if (address_mode != mode_64bit)
12713         {
12714           /* In 16/32-bit mode silently ignore following bits.  */
12715           rex &= ~REX_B;
12716           vex.r = 1;
12717           vex.v = 1;
12718           vex.register_specifier &= 0x7;
12719         }
12720
12721       /* The U bit.  */
12722       if (!(*codep & 0x4))
12723         return &bad_opcode;
12724
12725       switch ((*codep & 0x3))
12726         {
12727         case 0:
12728           vex.prefix = 0;
12729           break;
12730         case 1:
12731           vex.prefix = DATA_PREFIX_OPCODE;
12732           break;
12733         case 2:
12734           vex.prefix = REPE_PREFIX_OPCODE;
12735           break;
12736         case 3:
12737           vex.prefix = REPNE_PREFIX_OPCODE;
12738           break;
12739         }
12740
12741       /* The third byte after 0x62.  */
12742       codep++;
12743
12744       /* Remember the static rounding bits.  */
12745       vex.ll = (*codep >> 5) & 3;
12746       vex.b = (*codep & 0x10) != 0;
12747
12748       vex.v = *codep & 0x8;
12749       vex.mask_register_specifier = *codep & 0x7;
12750       vex.zeroing = *codep & 0x80;
12751
12752       need_vex = 1;
12753       need_vex_reg = 1;
12754       codep++;
12755       vindex = *codep++;
12756       dp = &evex_table[vex_table_index][vindex];
12757       end_codep = codep;
12758       FETCH_DATA (info, codep + 1);
12759       modrm.mod = (*codep >> 6) & 3;
12760       modrm.reg = (*codep >> 3) & 7;
12761       modrm.rm = *codep & 7;
12762
12763       /* Set vector length.  */
12764       if (modrm.mod == 3 && vex.b)
12765         vex.length = 512;
12766       else
12767         {
12768           switch (vex.ll)
12769             {
12770             case 0x0:
12771               vex.length = 128;
12772               break;
12773             case 0x1:
12774               vex.length = 256;
12775               break;
12776             case 0x2:
12777               vex.length = 512;
12778               break;
12779             default:
12780               return &bad_opcode;
12781             }
12782         }
12783       break;
12784
12785     case 0:
12786       dp = &bad_opcode;
12787       break;
12788
12789     default:
12790       abort ();
12791     }
12792
12793   if (dp->name != NULL)
12794     return dp;
12795   else
12796     return get_valid_dis386 (dp, info);
12797 }
12798
12799 static void
12800 get_sib (disassemble_info *info, int sizeflag)
12801 {
12802   /* If modrm.mod == 3, operand must be register.  */
12803   if (need_modrm
12804       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12805       && modrm.mod != 3
12806       && modrm.rm == 4)
12807     {
12808       FETCH_DATA (info, codep + 2);
12809       sib.index = (codep [1] >> 3) & 7;
12810       sib.scale = (codep [1] >> 6) & 3;
12811       sib.base = codep [1] & 7;
12812     }
12813 }
12814
12815 static int
12816 print_insn (bfd_vma pc, disassemble_info *info)
12817 {
12818   const struct dis386 *dp;
12819   int i;
12820   char *op_txt[MAX_OPERANDS];
12821   int needcomma;
12822   int sizeflag, orig_sizeflag;
12823   const char *p;
12824   struct dis_private priv;
12825   int prefix_length;
12826
12827   priv.orig_sizeflag = AFLAG | DFLAG;
12828   if ((info->mach & bfd_mach_i386_i386) != 0)
12829     address_mode = mode_32bit;
12830   else if (info->mach == bfd_mach_i386_i8086)
12831     {
12832       address_mode = mode_16bit;
12833       priv.orig_sizeflag = 0;
12834     }
12835   else
12836     address_mode = mode_64bit;
12837
12838   if (intel_syntax == (char) -1)
12839     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12840
12841   for (p = info->disassembler_options; p != NULL; )
12842     {
12843       if (CONST_STRNEQ (p, "x86-64"))
12844         {
12845           address_mode = mode_64bit;
12846           priv.orig_sizeflag = AFLAG | DFLAG;
12847         }
12848       else if (CONST_STRNEQ (p, "i386"))
12849         {
12850           address_mode = mode_32bit;
12851           priv.orig_sizeflag = AFLAG | DFLAG;
12852         }
12853       else if (CONST_STRNEQ (p, "i8086"))
12854         {
12855           address_mode = mode_16bit;
12856           priv.orig_sizeflag = 0;
12857         }
12858       else if (CONST_STRNEQ (p, "intel"))
12859         {
12860           intel_syntax = 1;
12861           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12862             intel_mnemonic = 1;
12863         }
12864       else if (CONST_STRNEQ (p, "att"))
12865         {
12866           intel_syntax = 0;
12867           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12868             intel_mnemonic = 0;
12869         }
12870       else if (CONST_STRNEQ (p, "addr"))
12871         {
12872           if (address_mode == mode_64bit)
12873             {
12874               if (p[4] == '3' && p[5] == '2')
12875                 priv.orig_sizeflag &= ~AFLAG;
12876               else if (p[4] == '6' && p[5] == '4')
12877                 priv.orig_sizeflag |= AFLAG;
12878             }
12879           else
12880             {
12881               if (p[4] == '1' && p[5] == '6')
12882                 priv.orig_sizeflag &= ~AFLAG;
12883               else if (p[4] == '3' && p[5] == '2')
12884                 priv.orig_sizeflag |= AFLAG;
12885             }
12886         }
12887       else if (CONST_STRNEQ (p, "data"))
12888         {
12889           if (p[4] == '1' && p[5] == '6')
12890             priv.orig_sizeflag &= ~DFLAG;
12891           else if (p[4] == '3' && p[5] == '2')
12892             priv.orig_sizeflag |= DFLAG;
12893         }
12894       else if (CONST_STRNEQ (p, "suffix"))
12895         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12896
12897       p = strchr (p, ',');
12898       if (p != NULL)
12899         p++;
12900     }
12901
12902   if (intel_syntax)
12903     {
12904       names64 = intel_names64;
12905       names32 = intel_names32;
12906       names16 = intel_names16;
12907       names8 = intel_names8;
12908       names8rex = intel_names8rex;
12909       names_seg = intel_names_seg;
12910       names_mm = intel_names_mm;
12911       names_bnd = intel_names_bnd;
12912       names_xmm = intel_names_xmm;
12913       names_ymm = intel_names_ymm;
12914       names_zmm = intel_names_zmm;
12915       index64 = intel_index64;
12916       index32 = intel_index32;
12917       names_mask = intel_names_mask;
12918       index16 = intel_index16;
12919       open_char = '[';
12920       close_char = ']';
12921       separator_char = '+';
12922       scale_char = '*';
12923     }
12924   else
12925     {
12926       names64 = att_names64;
12927       names32 = att_names32;
12928       names16 = att_names16;
12929       names8 = att_names8;
12930       names8rex = att_names8rex;
12931       names_seg = att_names_seg;
12932       names_mm = att_names_mm;
12933       names_bnd = att_names_bnd;
12934       names_xmm = att_names_xmm;
12935       names_ymm = att_names_ymm;
12936       names_zmm = att_names_zmm;
12937       index64 = att_index64;
12938       index32 = att_index32;
12939       names_mask = att_names_mask;
12940       index16 = att_index16;
12941       open_char = '(';
12942       close_char =  ')';
12943       separator_char = ',';
12944       scale_char = ',';
12945     }
12946
12947   /* The output looks better if we put 7 bytes on a line, since that
12948      puts most long word instructions on a single line.  Use 8 bytes
12949      for Intel L1OM.  */
12950   if ((info->mach & bfd_mach_l1om) != 0)
12951     info->bytes_per_line = 8;
12952   else
12953     info->bytes_per_line = 7;
12954
12955   info->private_data = &priv;
12956   priv.max_fetched = priv.the_buffer;
12957   priv.insn_start = pc;
12958
12959   obuf[0] = 0;
12960   for (i = 0; i < MAX_OPERANDS; ++i)
12961     {
12962       op_out[i][0] = 0;
12963       op_index[i] = -1;
12964     }
12965
12966   the_info = info;
12967   start_pc = pc;
12968   start_codep = priv.the_buffer;
12969   codep = priv.the_buffer;
12970
12971   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12972     {
12973       const char *name;
12974
12975       /* Getting here means we tried for data but didn't get it.  That
12976          means we have an incomplete instruction of some sort.  Just
12977          print the first byte as a prefix or a .byte pseudo-op.  */
12978       if (codep > priv.the_buffer)
12979         {
12980           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12981           if (name != NULL)
12982             (*info->fprintf_func) (info->stream, "%s", name);
12983           else
12984             {
12985               /* Just print the first byte as a .byte instruction.  */
12986               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12987                                      (unsigned int) priv.the_buffer[0]);
12988             }
12989
12990           return 1;
12991         }
12992
12993       return -1;
12994     }
12995
12996   obufp = obuf;
12997   sizeflag = priv.orig_sizeflag;
12998
12999   if (!ckprefix () || rex_used)
13000     {
13001       /* Too many prefixes or unused REX prefixes.  */
13002       for (i = 0;
13003            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13004            i++)
13005         (*info->fprintf_func) (info->stream, "%s%s",
13006                                i == 0 ? "" : " ",
13007                                prefix_name (all_prefixes[i], sizeflag));
13008       return i;
13009     }
13010
13011   insn_codep = codep;
13012
13013   FETCH_DATA (info, codep + 1);
13014   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13015
13016   if (((prefixes & PREFIX_FWAIT)
13017        && ((*codep < 0xd8) || (*codep > 0xdf))))
13018     {
13019       /* Handle prefixes before fwait.  */
13020       for (i = 0; i < fwait_prefix && all_prefixes[i];
13021            i++)
13022         (*info->fprintf_func) (info->stream, "%s ",
13023                                prefix_name (all_prefixes[i], sizeflag));
13024       (*info->fprintf_func) (info->stream, "fwait");
13025       return i + 1;
13026     }
13027
13028   if (*codep == 0x0f)
13029     {
13030       unsigned char threebyte;
13031       FETCH_DATA (info, codep + 2);
13032       threebyte = *++codep;
13033       dp = &dis386_twobyte[threebyte];
13034       need_modrm = twobyte_has_modrm[*codep];
13035       mandatory_prefix = twobyte_has_mandatory_prefix[*codep];
13036       codep++;
13037     }
13038   else
13039     {
13040       dp = &dis386[*codep];
13041       need_modrm = onebyte_has_modrm[*codep];
13042       mandatory_prefix = 0;
13043       codep++;
13044     }
13045
13046   /* Save sizeflag for printing the extra prefixes later before updating
13047      it for mnemonic and operand processing.  The prefix names depend
13048      only on the address mode.  */
13049   orig_sizeflag = sizeflag;
13050   if (prefixes & PREFIX_ADDR)
13051     sizeflag ^= AFLAG;
13052   if ((prefixes & PREFIX_DATA))
13053     sizeflag ^= DFLAG;
13054
13055   end_codep = codep;
13056   if (need_modrm)
13057     {
13058       FETCH_DATA (info, codep + 1);
13059       modrm.mod = (*codep >> 6) & 3;
13060       modrm.reg = (*codep >> 3) & 7;
13061       modrm.rm = *codep & 7;
13062     }
13063
13064   need_vex = 0;
13065   need_vex_reg = 0;
13066   vex_w_done = 0;
13067   vex.evex = 0;
13068
13069   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13070     {
13071       get_sib (info, sizeflag);
13072       dofloat (sizeflag);
13073     }
13074   else
13075     {
13076       dp = get_valid_dis386 (dp, info);
13077       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13078         {
13079           get_sib (info, sizeflag);
13080           for (i = 0; i < MAX_OPERANDS; ++i)
13081             {
13082               obufp = op_out[i];
13083               op_ad = MAX_OPERANDS - 1 - i;
13084               if (dp->op[i].rtn)
13085                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13086               /* For EVEX instruction after the last operand masking
13087                  should be printed.  */
13088               if (i == 0 && vex.evex)
13089                 {
13090                   /* Don't print {%k0}.  */
13091                   if (vex.mask_register_specifier)
13092                     {
13093                       oappend ("{");
13094                       oappend (names_mask[vex.mask_register_specifier]);
13095                       oappend ("}");
13096                     }
13097                   if (vex.zeroing)
13098                     oappend ("{z}");
13099                 }
13100             }
13101         }
13102     }
13103
13104   /* Check if the REX prefix is used.  */
13105   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13106     all_prefixes[last_rex_prefix] = 0;
13107
13108   /* Check if the SEG prefix is used.  */
13109   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13110                    | PREFIX_FS | PREFIX_GS)) != 0
13111       && (used_prefixes & active_seg_prefix) != 0)
13112     all_prefixes[last_seg_prefix] = 0;
13113
13114   /* Check if the ADDR prefix is used.  */
13115   if ((prefixes & PREFIX_ADDR) != 0
13116       && (used_prefixes & PREFIX_ADDR) != 0)
13117     all_prefixes[last_addr_prefix] = 0;
13118
13119   /* Check if the DATA prefix is used.  */
13120   if ((prefixes & PREFIX_DATA) != 0
13121       && (used_prefixes & PREFIX_DATA) != 0)
13122     all_prefixes[last_data_prefix] = 0;
13123
13124   /* Print the extra prefixes.  */
13125   prefix_length = 0;
13126   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13127     if (all_prefixes[i])
13128       {
13129         const char *name;
13130         name = prefix_name (all_prefixes[i], orig_sizeflag);
13131         if (name == NULL)
13132           abort ();
13133         prefix_length += strlen (name) + 1;
13134         (*info->fprintf_func) (info->stream, "%s ", name);
13135       }
13136
13137   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13138      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13139      used by putop and MMX/SSE operand and may be overriden by the
13140      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13141      separately.  */
13142   if (mandatory_prefix
13143       && dp != &bad_opcode
13144       && (((prefixes
13145             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13146            && (used_prefixes
13147                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13148           || ((((prefixes
13149                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13150                 == PREFIX_DATA)
13151                && (used_prefixes & PREFIX_DATA) == 0))))
13152     {
13153       (*info->fprintf_func) (info->stream, "(bad)");
13154       return end_codep - priv.the_buffer;
13155     }
13156
13157   /* Check maximum code length.  */
13158   if ((codep - start_codep) > MAX_CODE_LENGTH)
13159     {
13160       (*info->fprintf_func) (info->stream, "(bad)");
13161       return MAX_CODE_LENGTH;
13162     }
13163
13164   obufp = mnemonicendp;
13165   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13166     oappend (" ");
13167   oappend (" ");
13168   (*info->fprintf_func) (info->stream, "%s", obuf);
13169
13170   /* The enter and bound instructions are printed with operands in the same
13171      order as the intel book; everything else is printed in reverse order.  */
13172   if (intel_syntax || two_source_ops)
13173     {
13174       bfd_vma riprel;
13175
13176       for (i = 0; i < MAX_OPERANDS; ++i)
13177         op_txt[i] = op_out[i];
13178
13179       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13180         {
13181           op_ad = op_index[i];
13182           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13183           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13184           riprel = op_riprel[i];
13185           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13186           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13187         }
13188     }
13189   else
13190     {
13191       for (i = 0; i < MAX_OPERANDS; ++i)
13192         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13193     }
13194
13195   needcomma = 0;
13196   for (i = 0; i < MAX_OPERANDS; ++i)
13197     if (*op_txt[i])
13198       {
13199         if (needcomma)
13200           (*info->fprintf_func) (info->stream, ",");
13201         if (op_index[i] != -1 && !op_riprel[i])
13202           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13203         else
13204           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13205         needcomma = 1;
13206       }
13207
13208   for (i = 0; i < MAX_OPERANDS; i++)
13209     if (op_index[i] != -1 && op_riprel[i])
13210       {
13211         (*info->fprintf_func) (info->stream, "        # ");
13212         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13213                                                 + op_address[op_index[i]]), info);
13214         break;
13215       }
13216   return codep - priv.the_buffer;
13217 }
13218
13219 static const char *float_mem[] = {
13220   /* d8 */
13221   "fadd{s|}",
13222   "fmul{s|}",
13223   "fcom{s|}",
13224   "fcomp{s|}",
13225   "fsub{s|}",
13226   "fsubr{s|}",
13227   "fdiv{s|}",
13228   "fdivr{s|}",
13229   /* d9 */
13230   "fld{s|}",
13231   "(bad)",
13232   "fst{s|}",
13233   "fstp{s|}",
13234   "fldenvIC",
13235   "fldcw",
13236   "fNstenvIC",
13237   "fNstcw",
13238   /* da */
13239   "fiadd{l|}",
13240   "fimul{l|}",
13241   "ficom{l|}",
13242   "ficomp{l|}",
13243   "fisub{l|}",
13244   "fisubr{l|}",
13245   "fidiv{l|}",
13246   "fidivr{l|}",
13247   /* db */
13248   "fild{l|}",
13249   "fisttp{l|}",
13250   "fist{l|}",
13251   "fistp{l|}",
13252   "(bad)",
13253   "fld{t||t|}",
13254   "(bad)",
13255   "fstp{t||t|}",
13256   /* dc */
13257   "fadd{l|}",
13258   "fmul{l|}",
13259   "fcom{l|}",
13260   "fcomp{l|}",
13261   "fsub{l|}",
13262   "fsubr{l|}",
13263   "fdiv{l|}",
13264   "fdivr{l|}",
13265   /* dd */
13266   "fld{l|}",
13267   "fisttp{ll|}",
13268   "fst{l||}",
13269   "fstp{l|}",
13270   "frstorIC",
13271   "(bad)",
13272   "fNsaveIC",
13273   "fNstsw",
13274   /* de */
13275   "fiadd",
13276   "fimul",
13277   "ficom",
13278   "ficomp",
13279   "fisub",
13280   "fisubr",
13281   "fidiv",
13282   "fidivr",
13283   /* df */
13284   "fild",
13285   "fisttp",
13286   "fist",
13287   "fistp",
13288   "fbld",
13289   "fild{ll|}",
13290   "fbstp",
13291   "fistp{ll|}",
13292 };
13293
13294 static const unsigned char float_mem_mode[] = {
13295   /* d8 */
13296   d_mode,
13297   d_mode,
13298   d_mode,
13299   d_mode,
13300   d_mode,
13301   d_mode,
13302   d_mode,
13303   d_mode,
13304   /* d9 */
13305   d_mode,
13306   0,
13307   d_mode,
13308   d_mode,
13309   0,
13310   w_mode,
13311   0,
13312   w_mode,
13313   /* da */
13314   d_mode,
13315   d_mode,
13316   d_mode,
13317   d_mode,
13318   d_mode,
13319   d_mode,
13320   d_mode,
13321   d_mode,
13322   /* db */
13323   d_mode,
13324   d_mode,
13325   d_mode,
13326   d_mode,
13327   0,
13328   t_mode,
13329   0,
13330   t_mode,
13331   /* dc */
13332   q_mode,
13333   q_mode,
13334   q_mode,
13335   q_mode,
13336   q_mode,
13337   q_mode,
13338   q_mode,
13339   q_mode,
13340   /* dd */
13341   q_mode,
13342   q_mode,
13343   q_mode,
13344   q_mode,
13345   0,
13346   0,
13347   0,
13348   w_mode,
13349   /* de */
13350   w_mode,
13351   w_mode,
13352   w_mode,
13353   w_mode,
13354   w_mode,
13355   w_mode,
13356   w_mode,
13357   w_mode,
13358   /* df */
13359   w_mode,
13360   w_mode,
13361   w_mode,
13362   w_mode,
13363   t_mode,
13364   q_mode,
13365   t_mode,
13366   q_mode
13367 };
13368
13369 #define ST { OP_ST, 0 }
13370 #define STi { OP_STi, 0 }
13371
13372 #define FGRPd9_2 NULL, { { NULL, 0 } }
13373 #define FGRPd9_4 NULL, { { NULL, 1 } }
13374 #define FGRPd9_5 NULL, { { NULL, 2 } }
13375 #define FGRPd9_6 NULL, { { NULL, 3 } }
13376 #define FGRPd9_7 NULL, { { NULL, 4 } }
13377 #define FGRPda_5 NULL, { { NULL, 5 } }
13378 #define FGRPdb_4 NULL, { { NULL, 6 } }
13379 #define FGRPde_3 NULL, { { NULL, 7 } }
13380 #define FGRPdf_4 NULL, { { NULL, 8 } }
13381
13382 static const struct dis386 float_reg[][8] = {
13383   /* d8 */
13384   {
13385     { "fadd",   { ST, STi } },
13386     { "fmul",   { ST, STi } },
13387     { "fcom",   { STi } },
13388     { "fcomp",  { STi } },
13389     { "fsub",   { ST, STi } },
13390     { "fsubr",  { ST, STi } },
13391     { "fdiv",   { ST, STi } },
13392     { "fdivr",  { ST, STi } },
13393   },
13394   /* d9 */
13395   {
13396     { "fld",    { STi } },
13397     { "fxch",   { STi } },
13398     { FGRPd9_2 },
13399     { Bad_Opcode },
13400     { FGRPd9_4 },
13401     { FGRPd9_5 },
13402     { FGRPd9_6 },
13403     { FGRPd9_7 },
13404   },
13405   /* da */
13406   {
13407     { "fcmovb", { ST, STi } },
13408     { "fcmove", { ST, STi } },
13409     { "fcmovbe",{ ST, STi } },
13410     { "fcmovu", { ST, STi } },
13411     { Bad_Opcode },
13412     { FGRPda_5 },
13413     { Bad_Opcode },
13414     { Bad_Opcode },
13415   },
13416   /* db */
13417   {
13418     { "fcmovnb",{ ST, STi } },
13419     { "fcmovne",{ ST, STi } },
13420     { "fcmovnbe",{ ST, STi } },
13421     { "fcmovnu",{ ST, STi } },
13422     { FGRPdb_4 },
13423     { "fucomi", { ST, STi } },
13424     { "fcomi",  { ST, STi } },
13425     { Bad_Opcode },
13426   },
13427   /* dc */
13428   {
13429     { "fadd",   { STi, ST } },
13430     { "fmul",   { STi, ST } },
13431     { Bad_Opcode },
13432     { Bad_Opcode },
13433     { "fsub!M", { STi, ST } },
13434     { "fsubM",  { STi, ST } },
13435     { "fdiv!M", { STi, ST } },
13436     { "fdivM",  { STi, ST } },
13437   },
13438   /* dd */
13439   {
13440     { "ffree",  { STi } },
13441     { Bad_Opcode },
13442     { "fst",    { STi } },
13443     { "fstp",   { STi } },
13444     { "fucom",  { STi } },
13445     { "fucomp", { STi } },
13446     { Bad_Opcode },
13447     { Bad_Opcode },
13448   },
13449   /* de */
13450   {
13451     { "faddp",  { STi, ST } },
13452     { "fmulp",  { STi, ST } },
13453     { Bad_Opcode },
13454     { FGRPde_3 },
13455     { "fsub!Mp", { STi, ST } },
13456     { "fsubMp", { STi, ST } },
13457     { "fdiv!Mp", { STi, ST } },
13458     { "fdivMp", { STi, ST } },
13459   },
13460   /* df */
13461   {
13462     { "ffreep", { STi } },
13463     { Bad_Opcode },
13464     { Bad_Opcode },
13465     { Bad_Opcode },
13466     { FGRPdf_4 },
13467     { "fucomip", { ST, STi } },
13468     { "fcomip", { ST, STi } },
13469     { Bad_Opcode },
13470   },
13471 };
13472
13473 static char *fgrps[][8] = {
13474   /* d9_2  0 */
13475   {
13476     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13477   },
13478
13479   /* d9_4  1 */
13480   {
13481     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13482   },
13483
13484   /* d9_5  2 */
13485   {
13486     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13487   },
13488
13489   /* d9_6  3 */
13490   {
13491     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13492   },
13493
13494   /* d9_7  4 */
13495   {
13496     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13497   },
13498
13499   /* da_5  5 */
13500   {
13501     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13502   },
13503
13504   /* db_4  6 */
13505   {
13506     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13507     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13508   },
13509
13510   /* de_3  7 */
13511   {
13512     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13513   },
13514
13515   /* df_4  8 */
13516   {
13517     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13518   },
13519 };
13520
13521 static void
13522 swap_operand (void)
13523 {
13524   mnemonicendp[0] = '.';
13525   mnemonicendp[1] = 's';
13526   mnemonicendp += 2;
13527 }
13528
13529 static void
13530 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13531                int sizeflag ATTRIBUTE_UNUSED)
13532 {
13533   /* Skip mod/rm byte.  */
13534   MODRM_CHECK;
13535   codep++;
13536 }
13537
13538 static void
13539 dofloat (int sizeflag)
13540 {
13541   const struct dis386 *dp;
13542   unsigned char floatop;
13543
13544   floatop = codep[-1];
13545
13546   if (modrm.mod != 3)
13547     {
13548       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13549
13550       putop (float_mem[fp_indx], sizeflag);
13551       obufp = op_out[0];
13552       op_ad = 2;
13553       OP_E (float_mem_mode[fp_indx], sizeflag);
13554       return;
13555     }
13556   /* Skip mod/rm byte.  */
13557   MODRM_CHECK;
13558   codep++;
13559
13560   dp = &float_reg[floatop - 0xd8][modrm.reg];
13561   if (dp->name == NULL)
13562     {
13563       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13564
13565       /* Instruction fnstsw is only one with strange arg.  */
13566       if (floatop == 0xdf && codep[-1] == 0xe0)
13567         strcpy (op_out[0], names16[0]);
13568     }
13569   else
13570     {
13571       putop (dp->name, sizeflag);
13572
13573       obufp = op_out[0];
13574       op_ad = 2;
13575       if (dp->op[0].rtn)
13576         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13577
13578       obufp = op_out[1];
13579       op_ad = 1;
13580       if (dp->op[1].rtn)
13581         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13582     }
13583 }
13584
13585 /* Like oappend (below), but S is a string starting with '%'.
13586    In Intel syntax, the '%' is elided.  */
13587 static void
13588 oappend_maybe_intel (const char *s)
13589 {
13590   oappend (s + intel_syntax);
13591 }
13592
13593 static void
13594 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13595 {
13596   oappend_maybe_intel ("%st");
13597 }
13598
13599 static void
13600 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13601 {
13602   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13603   oappend_maybe_intel (scratchbuf);
13604 }
13605
13606 /* Capital letters in template are macros.  */
13607 static int
13608 putop (const char *in_template, int sizeflag)
13609 {
13610   const char *p;
13611   int alt = 0;
13612   int cond = 1;
13613   unsigned int l = 0, len = 1;
13614   char last[4];
13615
13616 #define SAVE_LAST(c)                    \
13617   if (l < len && l < sizeof (last))     \
13618     last[l++] = c;                      \
13619   else                                  \
13620     abort ();
13621
13622   for (p = in_template; *p; p++)
13623     {
13624       switch (*p)
13625         {
13626         default:
13627           *obufp++ = *p;
13628           break;
13629         case '%':
13630           len++;
13631           break;
13632         case '!':
13633           cond = 0;
13634           break;
13635         case '{':
13636           alt = 0;
13637           if (intel_syntax)
13638             {
13639               while (*++p != '|')
13640                 if (*p == '}' || *p == '\0')
13641                   abort ();
13642             }
13643           /* Fall through.  */
13644         case 'I':
13645           alt = 1;
13646           continue;
13647         case '|':
13648           while (*++p != '}')
13649             {
13650               if (*p == '\0')
13651                 abort ();
13652             }
13653           break;
13654         case '}':
13655           break;
13656         case 'A':
13657           if (intel_syntax)
13658             break;
13659           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13660             *obufp++ = 'b';
13661           break;
13662         case 'B':
13663           if (l == 0 && len == 1)
13664             {
13665 case_B:
13666               if (intel_syntax)
13667                 break;
13668               if (sizeflag & SUFFIX_ALWAYS)
13669                 *obufp++ = 'b';
13670             }
13671           else
13672             {
13673               if (l != 1
13674                   || len != 2
13675                   || last[0] != 'L')
13676                 {
13677                   SAVE_LAST (*p);
13678                   break;
13679                 }
13680
13681               if (address_mode == mode_64bit
13682                   && !(prefixes & PREFIX_ADDR))
13683                 {
13684                   *obufp++ = 'a';
13685                   *obufp++ = 'b';
13686                   *obufp++ = 's';
13687                 }
13688
13689               goto case_B;
13690             }
13691           break;
13692         case 'C':
13693           if (intel_syntax && !alt)
13694             break;
13695           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13696             {
13697               if (sizeflag & DFLAG)
13698                 *obufp++ = intel_syntax ? 'd' : 'l';
13699               else
13700                 *obufp++ = intel_syntax ? 'w' : 's';
13701               used_prefixes |= (prefixes & PREFIX_DATA);
13702             }
13703           break;
13704         case 'D':
13705           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13706             break;
13707           USED_REX (REX_W);
13708           if (modrm.mod == 3)
13709             {
13710               if (rex & REX_W)
13711                 *obufp++ = 'q';
13712               else
13713                 {
13714                   if (sizeflag & DFLAG)
13715                     *obufp++ = intel_syntax ? 'd' : 'l';
13716                   else
13717                     *obufp++ = 'w';
13718                   used_prefixes |= (prefixes & PREFIX_DATA);
13719                 }
13720             }
13721           else
13722             *obufp++ = 'w';
13723           break;
13724         case 'E':               /* For jcxz/jecxz */
13725           if (address_mode == mode_64bit)
13726             {
13727               if (sizeflag & AFLAG)
13728                 *obufp++ = 'r';
13729               else
13730                 *obufp++ = 'e';
13731             }
13732           else
13733             if (sizeflag & AFLAG)
13734               *obufp++ = 'e';
13735           used_prefixes |= (prefixes & PREFIX_ADDR);
13736           break;
13737         case 'F':
13738           if (intel_syntax)
13739             break;
13740           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13741             {
13742               if (sizeflag & AFLAG)
13743                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13744               else
13745                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13746               used_prefixes |= (prefixes & PREFIX_ADDR);
13747             }
13748           break;
13749         case 'G':
13750           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13751             break;
13752           if ((rex & REX_W) || (sizeflag & DFLAG))
13753             *obufp++ = 'l';
13754           else
13755             *obufp++ = 'w';
13756           if (!(rex & REX_W))
13757             used_prefixes |= (prefixes & PREFIX_DATA);
13758           break;
13759         case 'H':
13760           if (intel_syntax)
13761             break;
13762           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13763               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13764             {
13765               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13766               *obufp++ = ',';
13767               *obufp++ = 'p';
13768               if (prefixes & PREFIX_DS)
13769                 *obufp++ = 't';
13770               else
13771                 *obufp++ = 'n';
13772             }
13773           break;
13774         case 'J':
13775           if (intel_syntax)
13776             break;
13777           *obufp++ = 'l';
13778           break;
13779         case 'K':
13780           USED_REX (REX_W);
13781           if (rex & REX_W)
13782             *obufp++ = 'q';
13783           else
13784             *obufp++ = 'd';
13785           break;
13786         case 'Z':
13787           if (intel_syntax)
13788             break;
13789           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13790             {
13791               *obufp++ = 'q';
13792               break;
13793             }
13794           /* Fall through.  */
13795           goto case_L;
13796         case 'L':
13797           if (l != 0 || len != 1)
13798             {
13799               SAVE_LAST (*p);
13800               break;
13801             }
13802 case_L:
13803           if (intel_syntax)
13804             break;
13805           if (sizeflag & SUFFIX_ALWAYS)
13806             *obufp++ = 'l';
13807           break;
13808         case 'M':
13809           if (intel_mnemonic != cond)
13810             *obufp++ = 'r';
13811           break;
13812         case 'N':
13813           if ((prefixes & PREFIX_FWAIT) == 0)
13814             *obufp++ = 'n';
13815           else
13816             used_prefixes |= PREFIX_FWAIT;
13817           break;
13818         case 'O':
13819           USED_REX (REX_W);
13820           if (rex & REX_W)
13821             *obufp++ = 'o';
13822           else if (intel_syntax && (sizeflag & DFLAG))
13823             *obufp++ = 'q';
13824           else
13825             *obufp++ = 'd';
13826           if (!(rex & REX_W))
13827             used_prefixes |= (prefixes & PREFIX_DATA);
13828           break;
13829         case 'T':
13830           if (!intel_syntax
13831               && address_mode == mode_64bit
13832               && ((sizeflag & DFLAG) || (rex & REX_W)))
13833             {
13834               *obufp++ = 'q';
13835               break;
13836             }
13837           /* Fall through.  */
13838         case 'P':
13839           if (intel_syntax)
13840             {
13841               if ((rex & REX_W) == 0
13842                   && (prefixes & PREFIX_DATA))
13843                 {
13844                   if ((sizeflag & DFLAG) == 0)
13845                     *obufp++ = 'w';
13846                    used_prefixes |= (prefixes & PREFIX_DATA);
13847                 }
13848               break;
13849             }
13850           if ((prefixes & PREFIX_DATA)
13851               || (rex & REX_W)
13852               || (sizeflag & SUFFIX_ALWAYS))
13853             {
13854               USED_REX (REX_W);
13855               if (rex & REX_W)
13856                 *obufp++ = 'q';
13857               else
13858                 {
13859                    if (sizeflag & DFLAG)
13860                       *obufp++ = 'l';
13861                    else
13862                      *obufp++ = 'w';
13863                    used_prefixes |= (prefixes & PREFIX_DATA);
13864                 }
13865             }
13866           break;
13867         case 'U':
13868           if (intel_syntax)
13869             break;
13870           if (address_mode == mode_64bit
13871               && ((sizeflag & DFLAG) || (rex & REX_W)))
13872             {
13873               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13874                 *obufp++ = 'q';
13875               break;
13876             }
13877           /* Fall through.  */
13878           goto case_Q;
13879         case 'Q':
13880           if (l == 0 && len == 1)
13881             {
13882 case_Q:
13883               if (intel_syntax && !alt)
13884                 break;
13885               USED_REX (REX_W);
13886               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13887                 {
13888                   if (rex & REX_W)
13889                     *obufp++ = 'q';
13890                   else
13891                     {
13892                       if (sizeflag & DFLAG)
13893                         *obufp++ = intel_syntax ? 'd' : 'l';
13894                       else
13895                         *obufp++ = 'w';
13896                       used_prefixes |= (prefixes & PREFIX_DATA);
13897                     }
13898                 }
13899             }
13900           else
13901             {
13902               if (l != 1 || len != 2 || last[0] != 'L')
13903                 {
13904                   SAVE_LAST (*p);
13905                   break;
13906                 }
13907               if (intel_syntax
13908                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13909                 break;
13910               if ((rex & REX_W))
13911                 {
13912                   USED_REX (REX_W);
13913                   *obufp++ = 'q';
13914                 }
13915               else
13916                 *obufp++ = 'l';
13917             }
13918           break;
13919         case 'R':
13920           USED_REX (REX_W);
13921           if (rex & REX_W)
13922             *obufp++ = 'q';
13923           else if (sizeflag & DFLAG)
13924             {
13925               if (intel_syntax)
13926                   *obufp++ = 'd';
13927               else
13928                   *obufp++ = 'l';
13929             }
13930           else
13931             *obufp++ = 'w';
13932           if (intel_syntax && !p[1]
13933               && ((rex & REX_W) || (sizeflag & DFLAG)))
13934             *obufp++ = 'e';
13935           if (!(rex & REX_W))
13936             used_prefixes |= (prefixes & PREFIX_DATA);
13937           break;
13938         case 'V':
13939           if (l == 0 && len == 1)
13940             {
13941               if (intel_syntax)
13942                 break;
13943               if (address_mode == mode_64bit
13944                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13945                 {
13946                   if (sizeflag & SUFFIX_ALWAYS)
13947                     *obufp++ = 'q';
13948                   break;
13949                 }
13950             }
13951           else
13952             {
13953               if (l != 1
13954                   || len != 2
13955                   || last[0] != 'L')
13956                 {
13957                   SAVE_LAST (*p);
13958                   break;
13959                 }
13960
13961               if (rex & REX_W)
13962                 {
13963                   *obufp++ = 'a';
13964                   *obufp++ = 'b';
13965                   *obufp++ = 's';
13966                 }
13967             }
13968           /* Fall through.  */
13969           goto case_S;
13970         case 'S':
13971           if (l == 0 && len == 1)
13972             {
13973 case_S:
13974               if (intel_syntax)
13975                 break;
13976               if (sizeflag & SUFFIX_ALWAYS)
13977                 {
13978                   if (rex & REX_W)
13979                     *obufp++ = 'q';
13980                   else
13981                     {
13982                       if (sizeflag & DFLAG)
13983                         *obufp++ = 'l';
13984                       else
13985                         *obufp++ = 'w';
13986                       used_prefixes |= (prefixes & PREFIX_DATA);
13987                     }
13988                 }
13989             }
13990           else
13991             {
13992               if (l != 1
13993                   || len != 2
13994                   || last[0] != 'L')
13995                 {
13996                   SAVE_LAST (*p);
13997                   break;
13998                 }
13999
14000               if (address_mode == mode_64bit
14001                   && !(prefixes & PREFIX_ADDR))
14002                 {
14003                   *obufp++ = 'a';
14004                   *obufp++ = 'b';
14005                   *obufp++ = 's';
14006                 }
14007
14008               goto case_S;
14009             }
14010           break;
14011         case 'X':
14012           if (l != 0 || len != 1)
14013             {
14014               SAVE_LAST (*p);
14015               break;
14016             }
14017           if (need_vex && vex.prefix)
14018             {
14019               if (vex.prefix == DATA_PREFIX_OPCODE)
14020                 *obufp++ = 'd';
14021               else
14022                 *obufp++ = 's';
14023             }
14024           else
14025             {
14026               if (prefixes & PREFIX_DATA)
14027                 *obufp++ = 'd';
14028               else
14029                 *obufp++ = 's';
14030               used_prefixes |= (prefixes & PREFIX_DATA);
14031             }
14032           break;
14033         case 'Y':
14034           if (l == 0 && len == 1)
14035             {
14036               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14037                 break;
14038               if (rex & REX_W)
14039                 {
14040                   USED_REX (REX_W);
14041                   *obufp++ = 'q';
14042                 }
14043               break;
14044             }
14045           else
14046             {
14047               if (l != 1 || len != 2 || last[0] != 'X')
14048                 {
14049                   SAVE_LAST (*p);
14050                   break;
14051                 }
14052               if (!need_vex)
14053                 abort ();
14054               if (intel_syntax
14055                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14056                 break;
14057               switch (vex.length)
14058                 {
14059                 case 128:
14060                   *obufp++ = 'x';
14061                   break;
14062                 case 256:
14063                   *obufp++ = 'y';
14064                   break;
14065                 default:
14066                   abort ();
14067                 }
14068             }
14069           break;
14070         case 'W':
14071           if (l == 0 && len == 1)
14072             {
14073               /* operand size flag for cwtl, cbtw */
14074               USED_REX (REX_W);
14075               if (rex & REX_W)
14076                 {
14077                   if (intel_syntax)
14078                     *obufp++ = 'd';
14079                   else
14080                     *obufp++ = 'l';
14081                 }
14082               else if (sizeflag & DFLAG)
14083                 *obufp++ = 'w';
14084               else
14085                 *obufp++ = 'b';
14086               if (!(rex & REX_W))
14087                 used_prefixes |= (prefixes & PREFIX_DATA);
14088             }
14089           else
14090             {
14091               if (l != 1
14092                   || len != 2
14093                   || (last[0] != 'X'
14094                       && last[0] != 'L'))
14095                 {
14096                   SAVE_LAST (*p);
14097                   break;
14098                 }
14099               if (!need_vex)
14100                 abort ();
14101               if (last[0] == 'X')
14102                 *obufp++ = vex.w ? 'd': 's';
14103               else
14104                 *obufp++ = vex.w ? 'q': 'd';
14105             }
14106           break;
14107         }
14108       alt = 0;
14109     }
14110   *obufp = 0;
14111   mnemonicendp = obufp;
14112   return 0;
14113 }
14114
14115 static void
14116 oappend (const char *s)
14117 {
14118   obufp = stpcpy (obufp, s);
14119 }
14120
14121 static void
14122 append_seg (void)
14123 {
14124   /* Only print the active segment register.  */
14125   if (!active_seg_prefix)
14126     return;
14127
14128   used_prefixes |= active_seg_prefix;
14129   switch (active_seg_prefix)
14130     {
14131     case PREFIX_CS:
14132       oappend_maybe_intel ("%cs:");
14133       break;
14134     case PREFIX_DS:
14135       oappend_maybe_intel ("%ds:");
14136       break;
14137     case PREFIX_SS:
14138       oappend_maybe_intel ("%ss:");
14139       break;
14140     case PREFIX_ES:
14141       oappend_maybe_intel ("%es:");
14142       break;
14143     case PREFIX_FS:
14144       oappend_maybe_intel ("%fs:");
14145       break;
14146     case PREFIX_GS:
14147       oappend_maybe_intel ("%gs:");
14148       break;
14149     default:
14150       break;
14151     }
14152 }
14153
14154 static void
14155 OP_indirE (int bytemode, int sizeflag)
14156 {
14157   if (!intel_syntax)
14158     oappend ("*");
14159   OP_E (bytemode, sizeflag);
14160 }
14161
14162 static void
14163 print_operand_value (char *buf, int hex, bfd_vma disp)
14164 {
14165   if (address_mode == mode_64bit)
14166     {
14167       if (hex)
14168         {
14169           char tmp[30];
14170           int i;
14171           buf[0] = '0';
14172           buf[1] = 'x';
14173           sprintf_vma (tmp, disp);
14174           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14175           strcpy (buf + 2, tmp + i);
14176         }
14177       else
14178         {
14179           bfd_signed_vma v = disp;
14180           char tmp[30];
14181           int i;
14182           if (v < 0)
14183             {
14184               *(buf++) = '-';
14185               v = -disp;
14186               /* Check for possible overflow on 0x8000000000000000.  */
14187               if (v < 0)
14188                 {
14189                   strcpy (buf, "9223372036854775808");
14190                   return;
14191                 }
14192             }
14193           if (!v)
14194             {
14195               strcpy (buf, "0");
14196               return;
14197             }
14198
14199           i = 0;
14200           tmp[29] = 0;
14201           while (v)
14202             {
14203               tmp[28 - i] = (v % 10) + '0';
14204               v /= 10;
14205               i++;
14206             }
14207           strcpy (buf, tmp + 29 - i);
14208         }
14209     }
14210   else
14211     {
14212       if (hex)
14213         sprintf (buf, "0x%x", (unsigned int) disp);
14214       else
14215         sprintf (buf, "%d", (int) disp);
14216     }
14217 }
14218
14219 /* Put DISP in BUF as signed hex number.  */
14220
14221 static void
14222 print_displacement (char *buf, bfd_vma disp)
14223 {
14224   bfd_signed_vma val = disp;
14225   char tmp[30];
14226   int i, j = 0;
14227
14228   if (val < 0)
14229     {
14230       buf[j++] = '-';
14231       val = -disp;
14232
14233       /* Check for possible overflow.  */
14234       if (val < 0)
14235         {
14236           switch (address_mode)
14237             {
14238             case mode_64bit:
14239               strcpy (buf + j, "0x8000000000000000");
14240               break;
14241             case mode_32bit:
14242               strcpy (buf + j, "0x80000000");
14243               break;
14244             case mode_16bit:
14245               strcpy (buf + j, "0x8000");
14246               break;
14247             }
14248           return;
14249         }
14250     }
14251
14252   buf[j++] = '0';
14253   buf[j++] = 'x';
14254
14255   sprintf_vma (tmp, (bfd_vma) val);
14256   for (i = 0; tmp[i] == '0'; i++)
14257     continue;
14258   if (tmp[i] == '\0')
14259     i--;
14260   strcpy (buf + j, tmp + i);
14261 }
14262
14263 static void
14264 intel_operand_size (int bytemode, int sizeflag)
14265 {
14266   if (vex.evex
14267       && vex.b
14268       && (bytemode == x_mode
14269           || bytemode == evex_half_bcst_xmmq_mode))
14270     {
14271       if (vex.w)
14272         oappend ("QWORD PTR ");
14273       else
14274         oappend ("DWORD PTR ");
14275       return;
14276     }
14277   switch (bytemode)
14278     {
14279     case b_mode:
14280     case b_swap_mode:
14281     case dqb_mode:
14282     case db_mode:
14283       oappend ("BYTE PTR ");
14284       break;
14285     case w_mode:
14286     case dw_mode:
14287     case dqw_mode:
14288     case dqw_swap_mode:
14289       oappend ("WORD PTR ");
14290       break;
14291     case stack_v_mode:
14292       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14293         {
14294           oappend ("QWORD PTR ");
14295           break;
14296         }
14297       /* FALLTHRU */
14298     case v_mode:
14299     case v_swap_mode:
14300     case dq_mode:
14301       USED_REX (REX_W);
14302       if (rex & REX_W)
14303         oappend ("QWORD PTR ");
14304       else
14305         {
14306           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14307             oappend ("DWORD PTR ");
14308           else
14309             oappend ("WORD PTR ");
14310           used_prefixes |= (prefixes & PREFIX_DATA);
14311         }
14312       break;
14313     case z_mode:
14314       if ((rex & REX_W) || (sizeflag & DFLAG))
14315         *obufp++ = 'D';
14316       oappend ("WORD PTR ");
14317       if (!(rex & REX_W))
14318         used_prefixes |= (prefixes & PREFIX_DATA);
14319       break;
14320     case a_mode:
14321       if (sizeflag & DFLAG)
14322         oappend ("QWORD PTR ");
14323       else
14324         oappend ("DWORD PTR ");
14325       used_prefixes |= (prefixes & PREFIX_DATA);
14326       break;
14327     case d_mode:
14328     case d_scalar_mode:
14329     case d_scalar_swap_mode:
14330     case d_swap_mode:
14331     case dqd_mode:
14332       oappend ("DWORD PTR ");
14333       break;
14334     case q_mode:
14335     case q_scalar_mode:
14336     case q_scalar_swap_mode:
14337     case q_swap_mode:
14338       oappend ("QWORD PTR ");
14339       break;
14340     case m_mode:
14341       if (address_mode == mode_64bit)
14342         oappend ("QWORD PTR ");
14343       else
14344         oappend ("DWORD PTR ");
14345       break;
14346     case f_mode:
14347       if (sizeflag & DFLAG)
14348         oappend ("FWORD PTR ");
14349       else
14350         oappend ("DWORD PTR ");
14351       used_prefixes |= (prefixes & PREFIX_DATA);
14352       break;
14353     case t_mode:
14354       oappend ("TBYTE PTR ");
14355       break;
14356     case x_mode:
14357     case x_swap_mode:
14358     case evex_x_gscat_mode:
14359     case evex_x_nobcst_mode:
14360       if (need_vex)
14361         {
14362           switch (vex.length)
14363             {
14364             case 128:
14365               oappend ("XMMWORD PTR ");
14366               break;
14367             case 256:
14368               oappend ("YMMWORD PTR ");
14369               break;
14370             case 512:
14371               oappend ("ZMMWORD PTR ");
14372               break;
14373             default:
14374               abort ();
14375             }
14376         }
14377       else
14378         oappend ("XMMWORD PTR ");
14379       break;
14380     case xmm_mode:
14381       oappend ("XMMWORD PTR ");
14382       break;
14383     case ymm_mode:
14384       oappend ("YMMWORD PTR ");
14385       break;
14386     case xmmq_mode:
14387     case evex_half_bcst_xmmq_mode:
14388       if (!need_vex)
14389         abort ();
14390
14391       switch (vex.length)
14392         {
14393         case 128:
14394           oappend ("QWORD PTR ");
14395           break;
14396         case 256:
14397           oappend ("XMMWORD PTR ");
14398           break;
14399         case 512:
14400           oappend ("YMMWORD PTR ");
14401           break;
14402         default:
14403           abort ();
14404         }
14405       break;
14406     case xmm_mb_mode:
14407       if (!need_vex)
14408         abort ();
14409
14410       switch (vex.length)
14411         {
14412         case 128:
14413         case 256:
14414         case 512:
14415           oappend ("BYTE PTR ");
14416           break;
14417         default:
14418           abort ();
14419         }
14420       break;
14421     case xmm_mw_mode:
14422       if (!need_vex)
14423         abort ();
14424
14425       switch (vex.length)
14426         {
14427         case 128:
14428         case 256:
14429         case 512:
14430           oappend ("WORD PTR ");
14431           break;
14432         default:
14433           abort ();
14434         }
14435       break;
14436     case xmm_md_mode:
14437       if (!need_vex)
14438         abort ();
14439
14440       switch (vex.length)
14441         {
14442         case 128:
14443         case 256:
14444         case 512:
14445           oappend ("DWORD PTR ");
14446           break;
14447         default:
14448           abort ();
14449         }
14450       break;
14451     case xmm_mq_mode:
14452       if (!need_vex)
14453         abort ();
14454
14455       switch (vex.length)
14456         {
14457         case 128:
14458         case 256:
14459         case 512:
14460           oappend ("QWORD PTR ");
14461           break;
14462         default:
14463           abort ();
14464         }
14465       break;
14466     case xmmdw_mode:
14467       if (!need_vex)
14468         abort ();
14469
14470       switch (vex.length)
14471         {
14472         case 128:
14473           oappend ("WORD PTR ");
14474           break;
14475         case 256:
14476           oappend ("DWORD PTR ");
14477           break;
14478         case 512:
14479           oappend ("QWORD PTR ");
14480           break;
14481         default:
14482           abort ();
14483         }
14484       break;
14485     case xmmqd_mode:
14486       if (!need_vex)
14487         abort ();
14488
14489       switch (vex.length)
14490         {
14491         case 128:
14492           oappend ("DWORD PTR ");
14493           break;
14494         case 256:
14495           oappend ("QWORD PTR ");
14496           break;
14497         case 512:
14498           oappend ("XMMWORD PTR ");
14499           break;
14500         default:
14501           abort ();
14502         }
14503       break;
14504     case ymmq_mode:
14505       if (!need_vex)
14506         abort ();
14507
14508       switch (vex.length)
14509         {
14510         case 128:
14511           oappend ("QWORD PTR ");
14512           break;
14513         case 256:
14514           oappend ("YMMWORD PTR ");
14515           break;
14516         case 512:
14517           oappend ("ZMMWORD PTR ");
14518           break;
14519         default:
14520           abort ();
14521         }
14522       break;
14523     case ymmxmm_mode:
14524       if (!need_vex)
14525         abort ();
14526
14527       switch (vex.length)
14528         {
14529         case 128:
14530         case 256:
14531           oappend ("XMMWORD PTR ");
14532           break;
14533         default:
14534           abort ();
14535         }
14536       break;
14537     case o_mode:
14538       oappend ("OWORD PTR ");
14539       break;
14540     case xmm_mdq_mode:
14541     case vex_w_dq_mode:
14542     case vex_scalar_w_dq_mode:
14543       if (!need_vex)
14544         abort ();
14545
14546       if (vex.w)
14547         oappend ("QWORD PTR ");
14548       else
14549         oappend ("DWORD PTR ");
14550       break;
14551     case vex_vsib_d_w_dq_mode:
14552     case vex_vsib_q_w_dq_mode:
14553       if (!need_vex)
14554         abort ();
14555
14556       if (!vex.evex)
14557         {
14558           if (vex.w)
14559             oappend ("QWORD PTR ");
14560           else
14561             oappend ("DWORD PTR ");
14562         }
14563       else
14564         {
14565           switch (vex.length)
14566             {
14567             case 128:
14568               oappend ("XMMWORD PTR ");
14569               break;
14570             case 256:
14571               oappend ("YMMWORD PTR ");
14572               break;
14573             case 512:
14574               oappend ("ZMMWORD PTR ");
14575               break;
14576             default:
14577               abort ();
14578             }
14579         }
14580       break;
14581     case vex_vsib_q_w_d_mode:
14582     case vex_vsib_d_w_d_mode:
14583       if (!need_vex || !vex.evex)
14584         abort ();
14585
14586       switch (vex.length)
14587         {
14588         case 128:
14589           oappend ("QWORD PTR ");
14590           break;
14591         case 256:
14592           oappend ("XMMWORD PTR ");
14593           break;
14594         case 512:
14595           oappend ("YMMWORD PTR ");
14596           break;
14597         default:
14598           abort ();
14599         }
14600
14601       break;
14602     case mask_bd_mode:
14603       if (!need_vex || vex.length != 128)
14604         abort ();
14605       if (vex.w)
14606         oappend ("DWORD PTR ");
14607       else
14608         oappend ("BYTE PTR ");
14609       break;
14610     case mask_mode:
14611       if (!need_vex)
14612         abort ();
14613       if (vex.w)
14614         oappend ("QWORD PTR ");
14615       else
14616         oappend ("WORD PTR ");
14617       break;
14618     case v_bnd_mode:
14619     default:
14620       break;
14621     }
14622 }
14623
14624 static void
14625 OP_E_register (int bytemode, int sizeflag)
14626 {
14627   int reg = modrm.rm;
14628   const char **names;
14629
14630   USED_REX (REX_B);
14631   if ((rex & REX_B))
14632     reg += 8;
14633
14634   if ((sizeflag & SUFFIX_ALWAYS)
14635       && (bytemode == b_swap_mode
14636           || bytemode == v_swap_mode
14637           || bytemode == dqw_swap_mode))
14638     swap_operand ();
14639
14640   switch (bytemode)
14641     {
14642     case b_mode:
14643     case b_swap_mode:
14644       USED_REX (0);
14645       if (rex)
14646         names = names8rex;
14647       else
14648         names = names8;
14649       break;
14650     case w_mode:
14651       names = names16;
14652       break;
14653     case d_mode:
14654     case dw_mode:
14655     case db_mode:
14656       names = names32;
14657       break;
14658     case q_mode:
14659       names = names64;
14660       break;
14661     case m_mode:
14662     case v_bnd_mode:
14663       names = address_mode == mode_64bit ? names64 : names32;
14664       break;
14665     case bnd_mode:
14666       names = names_bnd;
14667       break;
14668     case stack_v_mode:
14669       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14670         {
14671           names = names64;
14672           break;
14673         }
14674       bytemode = v_mode;
14675       /* FALLTHRU */
14676     case v_mode:
14677     case v_swap_mode:
14678     case dq_mode:
14679     case dqb_mode:
14680     case dqd_mode:
14681     case dqw_mode:
14682     case dqw_swap_mode:
14683       USED_REX (REX_W);
14684       if (rex & REX_W)
14685         names = names64;
14686       else
14687         {
14688           if ((sizeflag & DFLAG)
14689               || (bytemode != v_mode
14690                   && bytemode != v_swap_mode))
14691             names = names32;
14692           else
14693             names = names16;
14694           used_prefixes |= (prefixes & PREFIX_DATA);
14695         }
14696       break;
14697     case mask_bd_mode:
14698     case mask_mode:
14699       names = names_mask;
14700       break;
14701     case 0:
14702       return;
14703     default:
14704       oappend (INTERNAL_DISASSEMBLER_ERROR);
14705       return;
14706     }
14707   oappend (names[reg]);
14708 }
14709
14710 static void
14711 OP_E_memory (int bytemode, int sizeflag)
14712 {
14713   bfd_vma disp = 0;
14714   int add = (rex & REX_B) ? 8 : 0;
14715   int riprel = 0;
14716   int shift;
14717
14718   if (vex.evex)
14719     {
14720       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14721       if (vex.b
14722           && bytemode != x_mode
14723           && bytemode != xmmq_mode
14724           && bytemode != evex_half_bcst_xmmq_mode)
14725         {
14726           BadOp ();
14727           return;
14728         }
14729       switch (bytemode)
14730         {
14731         case dqw_mode:
14732         case dw_mode:
14733         case dqw_swap_mode:
14734           shift = 1;
14735           break;
14736         case dqb_mode:
14737         case db_mode:
14738           shift = 0;
14739           break;
14740         case vex_vsib_d_w_dq_mode:
14741         case vex_vsib_d_w_d_mode:
14742         case vex_vsib_q_w_dq_mode:
14743         case vex_vsib_q_w_d_mode:
14744         case evex_x_gscat_mode:
14745         case xmm_mdq_mode:
14746           shift = vex.w ? 3 : 2;
14747           break;
14748         case x_mode:
14749         case evex_half_bcst_xmmq_mode:
14750         case xmmq_mode:
14751           if (vex.b)
14752             {
14753               shift = vex.w ? 3 : 2;
14754               break;
14755             }
14756           /* Fall through if vex.b == 0.  */
14757         case xmmqd_mode:
14758         case xmmdw_mode:
14759         case ymmq_mode:
14760         case evex_x_nobcst_mode:
14761         case x_swap_mode:
14762           switch (vex.length)
14763             {
14764             case 128:
14765               shift = 4;
14766               break;
14767             case 256:
14768               shift = 5;
14769               break;
14770             case 512:
14771               shift = 6;
14772               break;
14773             default:
14774               abort ();
14775             }
14776           break;
14777         case ymm_mode:
14778           shift = 5;
14779           break;
14780         case xmm_mode:
14781           shift = 4;
14782           break;
14783         case xmm_mq_mode:
14784         case q_mode:
14785         case q_scalar_mode:
14786         case q_swap_mode:
14787         case q_scalar_swap_mode:
14788           shift = 3;
14789           break;
14790         case dqd_mode:
14791         case xmm_md_mode:
14792         case d_mode:
14793         case d_scalar_mode:
14794         case d_swap_mode:
14795         case d_scalar_swap_mode:
14796           shift = 2;
14797           break;
14798         case xmm_mw_mode:
14799           shift = 1;
14800           break;
14801         case xmm_mb_mode:
14802           shift = 0;
14803           break;
14804         default:
14805           abort ();
14806         }
14807       /* Make necessary corrections to shift for modes that need it.
14808          For these modes we currently have shift 4, 5 or 6 depending on
14809          vex.length (it corresponds to xmmword, ymmword or zmmword
14810          operand).  We might want to make it 3, 4 or 5 (e.g. for
14811          xmmq_mode).  In case of broadcast enabled the corrections
14812          aren't needed, as element size is always 32 or 64 bits.  */
14813       if (!vex.b
14814           && (bytemode == xmmq_mode
14815               || bytemode == evex_half_bcst_xmmq_mode))
14816         shift -= 1;
14817       else if (bytemode == xmmqd_mode)
14818         shift -= 2;
14819       else if (bytemode == xmmdw_mode)
14820         shift -= 3;
14821       else if (bytemode == ymmq_mode && vex.length == 128)
14822         shift -= 1;
14823     }
14824   else
14825     shift = 0;
14826
14827   USED_REX (REX_B);
14828   if (intel_syntax)
14829     intel_operand_size (bytemode, sizeflag);
14830   append_seg ();
14831
14832   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14833     {
14834       /* 32/64 bit address mode */
14835       int havedisp;
14836       int havesib;
14837       int havebase;
14838       int haveindex;
14839       int needindex;
14840       int base, rbase;
14841       int vindex = 0;
14842       int scale = 0;
14843       int addr32flag = !((sizeflag & AFLAG)
14844                          || bytemode == v_bnd_mode
14845                          || bytemode == bnd_mode);
14846       const char **indexes64 = names64;
14847       const char **indexes32 = names32;
14848
14849       havesib = 0;
14850       havebase = 1;
14851       haveindex = 0;
14852       base = modrm.rm;
14853
14854       if (base == 4)
14855         {
14856           havesib = 1;
14857           vindex = sib.index;
14858           USED_REX (REX_X);
14859           if (rex & REX_X)
14860             vindex += 8;
14861           switch (bytemode)
14862             {
14863             case vex_vsib_d_w_dq_mode:
14864             case vex_vsib_d_w_d_mode:
14865             case vex_vsib_q_w_dq_mode:
14866             case vex_vsib_q_w_d_mode:
14867               if (!need_vex)
14868                 abort ();
14869               if (vex.evex)
14870                 {
14871                   if (!vex.v)
14872                     vindex += 16;
14873                 }
14874
14875               haveindex = 1;
14876               switch (vex.length)
14877                 {
14878                 case 128:
14879                   indexes64 = indexes32 = names_xmm;
14880                   break;
14881                 case 256:
14882                   if (!vex.w
14883                       || bytemode == vex_vsib_q_w_dq_mode
14884                       || bytemode == vex_vsib_q_w_d_mode)
14885                     indexes64 = indexes32 = names_ymm;
14886                   else
14887                     indexes64 = indexes32 = names_xmm;
14888                   break;
14889                 case 512:
14890                   if (!vex.w
14891                       || bytemode == vex_vsib_q_w_dq_mode
14892                       || bytemode == vex_vsib_q_w_d_mode)
14893                     indexes64 = indexes32 = names_zmm;
14894                   else
14895                     indexes64 = indexes32 = names_ymm;
14896                   break;
14897                 default:
14898                   abort ();
14899                 }
14900               break;
14901             default:
14902               haveindex = vindex != 4;
14903               break;
14904             }
14905           scale = sib.scale;
14906           base = sib.base;
14907           codep++;
14908         }
14909       rbase = base + add;
14910
14911       switch (modrm.mod)
14912         {
14913         case 0:
14914           if (base == 5)
14915             {
14916               havebase = 0;
14917               if (address_mode == mode_64bit && !havesib)
14918                 riprel = 1;
14919               disp = get32s ();
14920             }
14921           break;
14922         case 1:
14923           FETCH_DATA (the_info, codep + 1);
14924           disp = *codep++;
14925           if ((disp & 0x80) != 0)
14926             disp -= 0x100;
14927           if (vex.evex && shift > 0)
14928             disp <<= shift;
14929           break;
14930         case 2:
14931           disp = get32s ();
14932           break;
14933         }
14934
14935       /* In 32bit mode, we need index register to tell [offset] from
14936          [eiz*1 + offset].  */
14937       needindex = (havesib
14938                    && !havebase
14939                    && !haveindex
14940                    && address_mode == mode_32bit);
14941       havedisp = (havebase
14942                   || needindex
14943                   || (havesib && (haveindex || scale != 0)));
14944
14945       if (!intel_syntax)
14946         if (modrm.mod != 0 || base == 5)
14947           {
14948             if (havedisp || riprel)
14949               print_displacement (scratchbuf, disp);
14950             else
14951               print_operand_value (scratchbuf, 1, disp);
14952             oappend (scratchbuf);
14953             if (riprel)
14954               {
14955                 set_op (disp, 1);
14956                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14957               }
14958           }
14959
14960       if ((havebase || haveindex || riprel)
14961           && (bytemode != v_bnd_mode)
14962           && (bytemode != bnd_mode))
14963         used_prefixes |= PREFIX_ADDR;
14964
14965       if (havedisp || (intel_syntax && riprel))
14966         {
14967           *obufp++ = open_char;
14968           if (intel_syntax && riprel)
14969             {
14970               set_op (disp, 1);
14971               oappend (sizeflag & AFLAG ? "rip" : "eip");
14972             }
14973           *obufp = '\0';
14974           if (havebase)
14975             oappend (address_mode == mode_64bit && !addr32flag
14976                      ? names64[rbase] : names32[rbase]);
14977           if (havesib)
14978             {
14979               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14980                  print index to tell base + index from base.  */
14981               if (scale != 0
14982                   || needindex
14983                   || haveindex
14984                   || (havebase && base != ESP_REG_NUM))
14985                 {
14986                   if (!intel_syntax || havebase)
14987                     {
14988                       *obufp++ = separator_char;
14989                       *obufp = '\0';
14990                     }
14991                   if (haveindex)
14992                     oappend (address_mode == mode_64bit && !addr32flag
14993                              ? indexes64[vindex] : indexes32[vindex]);
14994                   else
14995                     oappend (address_mode == mode_64bit && !addr32flag
14996                              ? index64 : index32);
14997
14998                   *obufp++ = scale_char;
14999                   *obufp = '\0';
15000                   sprintf (scratchbuf, "%d", 1 << scale);
15001                   oappend (scratchbuf);
15002                 }
15003             }
15004           if (intel_syntax
15005               && (disp || modrm.mod != 0 || base == 5))
15006             {
15007               if (!havedisp || (bfd_signed_vma) disp >= 0)
15008                 {
15009                   *obufp++ = '+';
15010                   *obufp = '\0';
15011                 }
15012               else if (modrm.mod != 1 && disp != -disp)
15013                 {
15014                   *obufp++ = '-';
15015                   *obufp = '\0';
15016                   disp = - (bfd_signed_vma) disp;
15017                 }
15018
15019               if (havedisp)
15020                 print_displacement (scratchbuf, disp);
15021               else
15022                 print_operand_value (scratchbuf, 1, disp);
15023               oappend (scratchbuf);
15024             }
15025
15026           *obufp++ = close_char;
15027           *obufp = '\0';
15028         }
15029       else if (intel_syntax)
15030         {
15031           if (modrm.mod != 0 || base == 5)
15032             {
15033               if (!active_seg_prefix)
15034                 {
15035                   oappend (names_seg[ds_reg - es_reg]);
15036                   oappend (":");
15037                 }
15038               print_operand_value (scratchbuf, 1, disp);
15039               oappend (scratchbuf);
15040             }
15041         }
15042     }
15043   else
15044     {
15045       /* 16 bit address mode */
15046       used_prefixes |= prefixes & PREFIX_ADDR;
15047       switch (modrm.mod)
15048         {
15049         case 0:
15050           if (modrm.rm == 6)
15051             {
15052               disp = get16 ();
15053               if ((disp & 0x8000) != 0)
15054                 disp -= 0x10000;
15055             }
15056           break;
15057         case 1:
15058           FETCH_DATA (the_info, codep + 1);
15059           disp = *codep++;
15060           if ((disp & 0x80) != 0)
15061             disp -= 0x100;
15062           break;
15063         case 2:
15064           disp = get16 ();
15065           if ((disp & 0x8000) != 0)
15066             disp -= 0x10000;
15067           break;
15068         }
15069
15070       if (!intel_syntax)
15071         if (modrm.mod != 0 || modrm.rm == 6)
15072           {
15073             print_displacement (scratchbuf, disp);
15074             oappend (scratchbuf);
15075           }
15076
15077       if (modrm.mod != 0 || modrm.rm != 6)
15078         {
15079           *obufp++ = open_char;
15080           *obufp = '\0';
15081           oappend (index16[modrm.rm]);
15082           if (intel_syntax
15083               && (disp || modrm.mod != 0 || modrm.rm == 6))
15084             {
15085               if ((bfd_signed_vma) disp >= 0)
15086                 {
15087                   *obufp++ = '+';
15088                   *obufp = '\0';
15089                 }
15090               else if (modrm.mod != 1)
15091                 {
15092                   *obufp++ = '-';
15093                   *obufp = '\0';
15094                   disp = - (bfd_signed_vma) disp;
15095                 }
15096
15097               print_displacement (scratchbuf, disp);
15098               oappend (scratchbuf);
15099             }
15100
15101           *obufp++ = close_char;
15102           *obufp = '\0';
15103         }
15104       else if (intel_syntax)
15105         {
15106           if (!active_seg_prefix)
15107             {
15108               oappend (names_seg[ds_reg - es_reg]);
15109               oappend (":");
15110             }
15111           print_operand_value (scratchbuf, 1, disp & 0xffff);
15112           oappend (scratchbuf);
15113         }
15114     }
15115   if (vex.evex && vex.b
15116       && (bytemode == x_mode
15117           || bytemode == xmmq_mode
15118           || bytemode == evex_half_bcst_xmmq_mode))
15119     {
15120       if (vex.w
15121           || bytemode == xmmq_mode
15122           || bytemode == evex_half_bcst_xmmq_mode)
15123         {
15124           switch (vex.length)
15125             {
15126             case 128:
15127               oappend ("{1to2}");
15128               break;
15129             case 256:
15130               oappend ("{1to4}");
15131               break;
15132             case 512:
15133               oappend ("{1to8}");
15134               break;
15135             default:
15136               abort ();
15137             }
15138         }
15139       else
15140         {
15141           switch (vex.length)
15142             {
15143             case 128:
15144               oappend ("{1to4}");
15145               break;
15146             case 256:
15147               oappend ("{1to8}");
15148               break;
15149             case 512:
15150               oappend ("{1to16}");
15151               break;
15152             default:
15153               abort ();
15154             }
15155         }
15156     }
15157 }
15158
15159 static void
15160 OP_E (int bytemode, int sizeflag)
15161 {
15162   /* Skip mod/rm byte.  */
15163   MODRM_CHECK;
15164   codep++;
15165
15166   if (modrm.mod == 3)
15167     OP_E_register (bytemode, sizeflag);
15168   else
15169     OP_E_memory (bytemode, sizeflag);
15170 }
15171
15172 static void
15173 OP_G (int bytemode, int sizeflag)
15174 {
15175   int add = 0;
15176   USED_REX (REX_R);
15177   if (rex & REX_R)
15178     add += 8;
15179   switch (bytemode)
15180     {
15181     case b_mode:
15182       USED_REX (0);
15183       if (rex)
15184         oappend (names8rex[modrm.reg + add]);
15185       else
15186         oappend (names8[modrm.reg + add]);
15187       break;
15188     case w_mode:
15189       oappend (names16[modrm.reg + add]);
15190       break;
15191     case d_mode:
15192     case db_mode:
15193     case dw_mode:
15194       oappend (names32[modrm.reg + add]);
15195       break;
15196     case q_mode:
15197       oappend (names64[modrm.reg + add]);
15198       break;
15199     case bnd_mode:
15200       oappend (names_bnd[modrm.reg]);
15201       break;
15202     case v_mode:
15203     case dq_mode:
15204     case dqb_mode:
15205     case dqd_mode:
15206     case dqw_mode:
15207     case dqw_swap_mode:
15208       USED_REX (REX_W);
15209       if (rex & REX_W)
15210         oappend (names64[modrm.reg + add]);
15211       else
15212         {
15213           if ((sizeflag & DFLAG) || bytemode != v_mode)
15214             oappend (names32[modrm.reg + add]);
15215           else
15216             oappend (names16[modrm.reg + add]);
15217           used_prefixes |= (prefixes & PREFIX_DATA);
15218         }
15219       break;
15220     case m_mode:
15221       if (address_mode == mode_64bit)
15222         oappend (names64[modrm.reg + add]);
15223       else
15224         oappend (names32[modrm.reg + add]);
15225       break;
15226     case mask_bd_mode:
15227     case mask_mode:
15228       oappend (names_mask[modrm.reg + add]);
15229       break;
15230     default:
15231       oappend (INTERNAL_DISASSEMBLER_ERROR);
15232       break;
15233     }
15234 }
15235
15236 static bfd_vma
15237 get64 (void)
15238 {
15239   bfd_vma x;
15240 #ifdef BFD64
15241   unsigned int a;
15242   unsigned int b;
15243
15244   FETCH_DATA (the_info, codep + 8);
15245   a = *codep++ & 0xff;
15246   a |= (*codep++ & 0xff) << 8;
15247   a |= (*codep++ & 0xff) << 16;
15248   a |= (*codep++ & 0xff) << 24;
15249   b = *codep++ & 0xff;
15250   b |= (*codep++ & 0xff) << 8;
15251   b |= (*codep++ & 0xff) << 16;
15252   b |= (*codep++ & 0xff) << 24;
15253   x = a + ((bfd_vma) b << 32);
15254 #else
15255   abort ();
15256   x = 0;
15257 #endif
15258   return x;
15259 }
15260
15261 static bfd_signed_vma
15262 get32 (void)
15263 {
15264   bfd_signed_vma x = 0;
15265
15266   FETCH_DATA (the_info, codep + 4);
15267   x = *codep++ & (bfd_signed_vma) 0xff;
15268   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15269   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15270   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15271   return x;
15272 }
15273
15274 static bfd_signed_vma
15275 get32s (void)
15276 {
15277   bfd_signed_vma x = 0;
15278
15279   FETCH_DATA (the_info, codep + 4);
15280   x = *codep++ & (bfd_signed_vma) 0xff;
15281   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15282   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15283   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15284
15285   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15286
15287   return x;
15288 }
15289
15290 static int
15291 get16 (void)
15292 {
15293   int x = 0;
15294
15295   FETCH_DATA (the_info, codep + 2);
15296   x = *codep++ & 0xff;
15297   x |= (*codep++ & 0xff) << 8;
15298   return x;
15299 }
15300
15301 static void
15302 set_op (bfd_vma op, int riprel)
15303 {
15304   op_index[op_ad] = op_ad;
15305   if (address_mode == mode_64bit)
15306     {
15307       op_address[op_ad] = op;
15308       op_riprel[op_ad] = riprel;
15309     }
15310   else
15311     {
15312       /* Mask to get a 32-bit address.  */
15313       op_address[op_ad] = op & 0xffffffff;
15314       op_riprel[op_ad] = riprel & 0xffffffff;
15315     }
15316 }
15317
15318 static void
15319 OP_REG (int code, int sizeflag)
15320 {
15321   const char *s;
15322   int add;
15323
15324   switch (code)
15325     {
15326     case es_reg: case ss_reg: case cs_reg:
15327     case ds_reg: case fs_reg: case gs_reg:
15328       oappend (names_seg[code - es_reg]);
15329       return;
15330     }
15331
15332   USED_REX (REX_B);
15333   if (rex & REX_B)
15334     add = 8;
15335   else
15336     add = 0;
15337
15338   switch (code)
15339     {
15340     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15341     case sp_reg: case bp_reg: case si_reg: case di_reg:
15342       s = names16[code - ax_reg + add];
15343       break;
15344     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15345     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15346       USED_REX (0);
15347       if (rex)
15348         s = names8rex[code - al_reg + add];
15349       else
15350         s = names8[code - al_reg];
15351       break;
15352     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15353     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15354       if (address_mode == mode_64bit
15355           && ((sizeflag & DFLAG) || (rex & REX_W)))
15356         {
15357           s = names64[code - rAX_reg + add];
15358           break;
15359         }
15360       code += eAX_reg - rAX_reg;
15361       /* Fall through.  */
15362     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15363     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15364       USED_REX (REX_W);
15365       if (rex & REX_W)
15366         s = names64[code - eAX_reg + add];
15367       else
15368         {
15369           if (sizeflag & DFLAG)
15370             s = names32[code - eAX_reg + add];
15371           else
15372             s = names16[code - eAX_reg + add];
15373           used_prefixes |= (prefixes & PREFIX_DATA);
15374         }
15375       break;
15376     default:
15377       s = INTERNAL_DISASSEMBLER_ERROR;
15378       break;
15379     }
15380   oappend (s);
15381 }
15382
15383 static void
15384 OP_IMREG (int code, int sizeflag)
15385 {
15386   const char *s;
15387
15388   switch (code)
15389     {
15390     case indir_dx_reg:
15391       if (intel_syntax)
15392         s = "dx";
15393       else
15394         s = "(%dx)";
15395       break;
15396     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15397     case sp_reg: case bp_reg: case si_reg: case di_reg:
15398       s = names16[code - ax_reg];
15399       break;
15400     case es_reg: case ss_reg: case cs_reg:
15401     case ds_reg: case fs_reg: case gs_reg:
15402       s = names_seg[code - es_reg];
15403       break;
15404     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15405     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15406       USED_REX (0);
15407       if (rex)
15408         s = names8rex[code - al_reg];
15409       else
15410         s = names8[code - al_reg];
15411       break;
15412     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15413     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15414       USED_REX (REX_W);
15415       if (rex & REX_W)
15416         s = names64[code - eAX_reg];
15417       else
15418         {
15419           if (sizeflag & DFLAG)
15420             s = names32[code - eAX_reg];
15421           else
15422             s = names16[code - eAX_reg];
15423           used_prefixes |= (prefixes & PREFIX_DATA);
15424         }
15425       break;
15426     case z_mode_ax_reg:
15427       if ((rex & REX_W) || (sizeflag & DFLAG))
15428         s = *names32;
15429       else
15430         s = *names16;
15431       if (!(rex & REX_W))
15432         used_prefixes |= (prefixes & PREFIX_DATA);
15433       break;
15434     default:
15435       s = INTERNAL_DISASSEMBLER_ERROR;
15436       break;
15437     }
15438   oappend (s);
15439 }
15440
15441 static void
15442 OP_I (int bytemode, int sizeflag)
15443 {
15444   bfd_signed_vma op;
15445   bfd_signed_vma mask = -1;
15446
15447   switch (bytemode)
15448     {
15449     case b_mode:
15450       FETCH_DATA (the_info, codep + 1);
15451       op = *codep++;
15452       mask = 0xff;
15453       break;
15454     case q_mode:
15455       if (address_mode == mode_64bit)
15456         {
15457           op = get32s ();
15458           break;
15459         }
15460       /* Fall through.  */
15461     case v_mode:
15462       USED_REX (REX_W);
15463       if (rex & REX_W)
15464         op = get32s ();
15465       else
15466         {
15467           if (sizeflag & DFLAG)
15468             {
15469               op = get32 ();
15470               mask = 0xffffffff;
15471             }
15472           else
15473             {
15474               op = get16 ();
15475               mask = 0xfffff;
15476             }
15477           used_prefixes |= (prefixes & PREFIX_DATA);
15478         }
15479       break;
15480     case w_mode:
15481       mask = 0xfffff;
15482       op = get16 ();
15483       break;
15484     case const_1_mode:
15485       if (intel_syntax)
15486         oappend ("1");
15487       return;
15488     default:
15489       oappend (INTERNAL_DISASSEMBLER_ERROR);
15490       return;
15491     }
15492
15493   op &= mask;
15494   scratchbuf[0] = '$';
15495   print_operand_value (scratchbuf + 1, 1, op);
15496   oappend_maybe_intel (scratchbuf);
15497   scratchbuf[0] = '\0';
15498 }
15499
15500 static void
15501 OP_I64 (int bytemode, int sizeflag)
15502 {
15503   bfd_signed_vma op;
15504   bfd_signed_vma mask = -1;
15505
15506   if (address_mode != mode_64bit)
15507     {
15508       OP_I (bytemode, sizeflag);
15509       return;
15510     }
15511
15512   switch (bytemode)
15513     {
15514     case b_mode:
15515       FETCH_DATA (the_info, codep + 1);
15516       op = *codep++;
15517       mask = 0xff;
15518       break;
15519     case v_mode:
15520       USED_REX (REX_W);
15521       if (rex & REX_W)
15522         op = get64 ();
15523       else
15524         {
15525           if (sizeflag & DFLAG)
15526             {
15527               op = get32 ();
15528               mask = 0xffffffff;
15529             }
15530           else
15531             {
15532               op = get16 ();
15533               mask = 0xfffff;
15534             }
15535           used_prefixes |= (prefixes & PREFIX_DATA);
15536         }
15537       break;
15538     case w_mode:
15539       mask = 0xfffff;
15540       op = get16 ();
15541       break;
15542     default:
15543       oappend (INTERNAL_DISASSEMBLER_ERROR);
15544       return;
15545     }
15546
15547   op &= mask;
15548   scratchbuf[0] = '$';
15549   print_operand_value (scratchbuf + 1, 1, op);
15550   oappend_maybe_intel (scratchbuf);
15551   scratchbuf[0] = '\0';
15552 }
15553
15554 static void
15555 OP_sI (int bytemode, int sizeflag)
15556 {
15557   bfd_signed_vma op;
15558
15559   switch (bytemode)
15560     {
15561     case b_mode:
15562     case b_T_mode:
15563       FETCH_DATA (the_info, codep + 1);
15564       op = *codep++;
15565       if ((op & 0x80) != 0)
15566         op -= 0x100;
15567       if (bytemode == b_T_mode)
15568         {
15569           if (address_mode != mode_64bit
15570               || !((sizeflag & DFLAG) || (rex & REX_W)))
15571             {
15572               /* The operand-size prefix is overridden by a REX prefix.  */
15573               if ((sizeflag & DFLAG) || (rex & REX_W))
15574                 op &= 0xffffffff;
15575               else
15576                 op &= 0xffff;
15577           }
15578         }
15579       else
15580         {
15581           if (!(rex & REX_W))
15582             {
15583               if (sizeflag & DFLAG)
15584                 op &= 0xffffffff;
15585               else
15586                 op &= 0xffff;
15587             }
15588         }
15589       break;
15590     case v_mode:
15591       /* The operand-size prefix is overridden by a REX prefix.  */
15592       if ((sizeflag & DFLAG) || (rex & REX_W))
15593         op = get32s ();
15594       else
15595         op = get16 ();
15596       break;
15597     default:
15598       oappend (INTERNAL_DISASSEMBLER_ERROR);
15599       return;
15600     }
15601
15602   scratchbuf[0] = '$';
15603   print_operand_value (scratchbuf + 1, 1, op);
15604   oappend_maybe_intel (scratchbuf);
15605 }
15606
15607 static void
15608 OP_J (int bytemode, int sizeflag)
15609 {
15610   bfd_vma disp;
15611   bfd_vma mask = -1;
15612   bfd_vma segment = 0;
15613
15614   switch (bytemode)
15615     {
15616     case b_mode:
15617       FETCH_DATA (the_info, codep + 1);
15618       disp = *codep++;
15619       if ((disp & 0x80) != 0)
15620         disp -= 0x100;
15621       break;
15622     case v_mode:
15623       USED_REX (REX_W);
15624       if ((sizeflag & DFLAG) || (rex & REX_W))
15625         disp = get32s ();
15626       else
15627         {
15628           disp = get16 ();
15629           if ((disp & 0x8000) != 0)
15630             disp -= 0x10000;
15631           /* In 16bit mode, address is wrapped around at 64k within
15632              the same segment.  Otherwise, a data16 prefix on a jump
15633              instruction means that the pc is masked to 16 bits after
15634              the displacement is added!  */
15635           mask = 0xffff;
15636           if ((prefixes & PREFIX_DATA) == 0)
15637             segment = ((start_pc + codep - start_codep)
15638                        & ~((bfd_vma) 0xffff));
15639         }
15640       if (!(rex & REX_W))
15641         used_prefixes |= (prefixes & PREFIX_DATA);
15642       break;
15643     default:
15644       oappend (INTERNAL_DISASSEMBLER_ERROR);
15645       return;
15646     }
15647   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15648   set_op (disp, 0);
15649   print_operand_value (scratchbuf, 1, disp);
15650   oappend (scratchbuf);
15651 }
15652
15653 static void
15654 OP_SEG (int bytemode, int sizeflag)
15655 {
15656   if (bytemode == w_mode)
15657     oappend (names_seg[modrm.reg]);
15658   else
15659     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15660 }
15661
15662 static void
15663 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15664 {
15665   int seg, offset;
15666
15667   if (sizeflag & DFLAG)
15668     {
15669       offset = get32 ();
15670       seg = get16 ();
15671     }
15672   else
15673     {
15674       offset = get16 ();
15675       seg = get16 ();
15676     }
15677   used_prefixes |= (prefixes & PREFIX_DATA);
15678   if (intel_syntax)
15679     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15680   else
15681     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15682   oappend (scratchbuf);
15683 }
15684
15685 static void
15686 OP_OFF (int bytemode, int sizeflag)
15687 {
15688   bfd_vma off;
15689
15690   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15691     intel_operand_size (bytemode, sizeflag);
15692   append_seg ();
15693
15694   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15695     off = get32 ();
15696   else
15697     off = get16 ();
15698
15699   if (intel_syntax)
15700     {
15701       if (!active_seg_prefix)
15702         {
15703           oappend (names_seg[ds_reg - es_reg]);
15704           oappend (":");
15705         }
15706     }
15707   print_operand_value (scratchbuf, 1, off);
15708   oappend (scratchbuf);
15709 }
15710
15711 static void
15712 OP_OFF64 (int bytemode, int sizeflag)
15713 {
15714   bfd_vma off;
15715
15716   if (address_mode != mode_64bit
15717       || (prefixes & PREFIX_ADDR))
15718     {
15719       OP_OFF (bytemode, sizeflag);
15720       return;
15721     }
15722
15723   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15724     intel_operand_size (bytemode, sizeflag);
15725   append_seg ();
15726
15727   off = get64 ();
15728
15729   if (intel_syntax)
15730     {
15731       if (!active_seg_prefix)
15732         {
15733           oappend (names_seg[ds_reg - es_reg]);
15734           oappend (":");
15735         }
15736     }
15737   print_operand_value (scratchbuf, 1, off);
15738   oappend (scratchbuf);
15739 }
15740
15741 static void
15742 ptr_reg (int code, int sizeflag)
15743 {
15744   const char *s;
15745
15746   *obufp++ = open_char;
15747   used_prefixes |= (prefixes & PREFIX_ADDR);
15748   if (address_mode == mode_64bit)
15749     {
15750       if (!(sizeflag & AFLAG))
15751         s = names32[code - eAX_reg];
15752       else
15753         s = names64[code - eAX_reg];
15754     }
15755   else if (sizeflag & AFLAG)
15756     s = names32[code - eAX_reg];
15757   else
15758     s = names16[code - eAX_reg];
15759   oappend (s);
15760   *obufp++ = close_char;
15761   *obufp = 0;
15762 }
15763
15764 static void
15765 OP_ESreg (int code, int sizeflag)
15766 {
15767   if (intel_syntax)
15768     {
15769       switch (codep[-1])
15770         {
15771         case 0x6d:      /* insw/insl */
15772           intel_operand_size (z_mode, sizeflag);
15773           break;
15774         case 0xa5:      /* movsw/movsl/movsq */
15775         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15776         case 0xab:      /* stosw/stosl */
15777         case 0xaf:      /* scasw/scasl */
15778           intel_operand_size (v_mode, sizeflag);
15779           break;
15780         default:
15781           intel_operand_size (b_mode, sizeflag);
15782         }
15783     }
15784   oappend_maybe_intel ("%es:");
15785   ptr_reg (code, sizeflag);
15786 }
15787
15788 static void
15789 OP_DSreg (int code, int sizeflag)
15790 {
15791   if (intel_syntax)
15792     {
15793       switch (codep[-1])
15794         {
15795         case 0x6f:      /* outsw/outsl */
15796           intel_operand_size (z_mode, sizeflag);
15797           break;
15798         case 0xa5:      /* movsw/movsl/movsq */
15799         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15800         case 0xad:      /* lodsw/lodsl/lodsq */
15801           intel_operand_size (v_mode, sizeflag);
15802           break;
15803         default:
15804           intel_operand_size (b_mode, sizeflag);
15805         }
15806     }
15807   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15808      default segment register DS is printed.  */
15809   if (!active_seg_prefix)
15810     active_seg_prefix = PREFIX_DS;
15811   append_seg ();
15812   ptr_reg (code, sizeflag);
15813 }
15814
15815 static void
15816 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15817 {
15818   int add;
15819   if (rex & REX_R)
15820     {
15821       USED_REX (REX_R);
15822       add = 8;
15823     }
15824   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15825     {
15826       all_prefixes[last_lock_prefix] = 0;
15827       used_prefixes |= PREFIX_LOCK;
15828       add = 8;
15829     }
15830   else
15831     add = 0;
15832   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15833   oappend_maybe_intel (scratchbuf);
15834 }
15835
15836 static void
15837 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15838 {
15839   int add;
15840   USED_REX (REX_R);
15841   if (rex & REX_R)
15842     add = 8;
15843   else
15844     add = 0;
15845   if (intel_syntax)
15846     sprintf (scratchbuf, "db%d", modrm.reg + add);
15847   else
15848     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15849   oappend (scratchbuf);
15850 }
15851
15852 static void
15853 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15854 {
15855   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15856   oappend_maybe_intel (scratchbuf);
15857 }
15858
15859 static void
15860 OP_R (int bytemode, int sizeflag)
15861 {
15862   if (modrm.mod == 3)
15863     OP_E (bytemode, sizeflag);
15864   else
15865     BadOp ();
15866 }
15867
15868 static void
15869 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15870 {
15871   int reg = modrm.reg;
15872   const char **names;
15873
15874   used_prefixes |= (prefixes & PREFIX_DATA);
15875   if (prefixes & PREFIX_DATA)
15876     {
15877       names = names_xmm;
15878       USED_REX (REX_R);
15879       if (rex & REX_R)
15880         reg += 8;
15881     }
15882   else
15883     names = names_mm;
15884   oappend (names[reg]);
15885 }
15886
15887 static void
15888 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15889 {
15890   int reg = modrm.reg;
15891   const char **names;
15892
15893   USED_REX (REX_R);
15894   if (rex & REX_R)
15895     reg += 8;
15896   if (vex.evex)
15897     {
15898       if (!vex.r)
15899         reg += 16;
15900     }
15901
15902   if (need_vex
15903       && bytemode != xmm_mode
15904       && bytemode != xmmq_mode
15905       && bytemode != evex_half_bcst_xmmq_mode
15906       && bytemode != ymm_mode
15907       && bytemode != scalar_mode)
15908     {
15909       switch (vex.length)
15910         {
15911         case 128:
15912           names = names_xmm;
15913           break;
15914         case 256:
15915           if (vex.w
15916               || (bytemode != vex_vsib_q_w_dq_mode
15917                   && bytemode != vex_vsib_q_w_d_mode))
15918             names = names_ymm;
15919           else
15920             names = names_xmm;
15921           break;
15922         case 512:
15923           names = names_zmm;
15924           break;
15925         default:
15926           abort ();
15927         }
15928     }
15929   else if (bytemode == xmmq_mode
15930            || bytemode == evex_half_bcst_xmmq_mode)
15931     {
15932       switch (vex.length)
15933         {
15934         case 128:
15935         case 256:
15936           names = names_xmm;
15937           break;
15938         case 512:
15939           names = names_ymm;
15940           break;
15941         default:
15942           abort ();
15943         }
15944     }
15945   else if (bytemode == ymm_mode)
15946     names = names_ymm;
15947   else
15948     names = names_xmm;
15949   oappend (names[reg]);
15950 }
15951
15952 static void
15953 OP_EM (int bytemode, int sizeflag)
15954 {
15955   int reg;
15956   const char **names;
15957
15958   if (modrm.mod != 3)
15959     {
15960       if (intel_syntax
15961           && (bytemode == v_mode || bytemode == v_swap_mode))
15962         {
15963           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15964           used_prefixes |= (prefixes & PREFIX_DATA);
15965         }
15966       OP_E (bytemode, sizeflag);
15967       return;
15968     }
15969
15970   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15971     swap_operand ();
15972
15973   /* Skip mod/rm byte.  */
15974   MODRM_CHECK;
15975   codep++;
15976   used_prefixes |= (prefixes & PREFIX_DATA);
15977   reg = modrm.rm;
15978   if (prefixes & PREFIX_DATA)
15979     {
15980       names = names_xmm;
15981       USED_REX (REX_B);
15982       if (rex & REX_B)
15983         reg += 8;
15984     }
15985   else
15986     names = names_mm;
15987   oappend (names[reg]);
15988 }
15989
15990 /* cvt* are the only instructions in sse2 which have
15991    both SSE and MMX operands and also have 0x66 prefix
15992    in their opcode. 0x66 was originally used to differentiate
15993    between SSE and MMX instruction(operands). So we have to handle the
15994    cvt* separately using OP_EMC and OP_MXC */
15995 static void
15996 OP_EMC (int bytemode, int sizeflag)
15997 {
15998   if (modrm.mod != 3)
15999     {
16000       if (intel_syntax && bytemode == v_mode)
16001         {
16002           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16003           used_prefixes |= (prefixes & PREFIX_DATA);
16004         }
16005       OP_E (bytemode, sizeflag);
16006       return;
16007     }
16008
16009   /* Skip mod/rm byte.  */
16010   MODRM_CHECK;
16011   codep++;
16012   used_prefixes |= (prefixes & PREFIX_DATA);
16013   oappend (names_mm[modrm.rm]);
16014 }
16015
16016 static void
16017 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16018 {
16019   used_prefixes |= (prefixes & PREFIX_DATA);
16020   oappend (names_mm[modrm.reg]);
16021 }
16022
16023 static void
16024 OP_EX (int bytemode, int sizeflag)
16025 {
16026   int reg;
16027   const char **names;
16028
16029   /* Skip mod/rm byte.  */
16030   MODRM_CHECK;
16031   codep++;
16032
16033   if (modrm.mod != 3)
16034     {
16035       OP_E_memory (bytemode, sizeflag);
16036       return;
16037     }
16038
16039   reg = modrm.rm;
16040   USED_REX (REX_B);
16041   if (rex & REX_B)
16042     reg += 8;
16043   if (vex.evex)
16044     {
16045       USED_REX (REX_X);
16046       if ((rex & REX_X))
16047         reg += 16;
16048     }
16049
16050   if ((sizeflag & SUFFIX_ALWAYS)
16051       && (bytemode == x_swap_mode
16052           || bytemode == d_swap_mode
16053           || bytemode == dqw_swap_mode
16054           || bytemode == d_scalar_swap_mode
16055           || bytemode == q_swap_mode
16056           || bytemode == q_scalar_swap_mode))
16057     swap_operand ();
16058
16059   if (need_vex
16060       && bytemode != xmm_mode
16061       && bytemode != xmmdw_mode
16062       && bytemode != xmmqd_mode
16063       && bytemode != xmm_mb_mode
16064       && bytemode != xmm_mw_mode
16065       && bytemode != xmm_md_mode
16066       && bytemode != xmm_mq_mode
16067       && bytemode != xmm_mdq_mode
16068       && bytemode != xmmq_mode
16069       && bytemode != evex_half_bcst_xmmq_mode
16070       && bytemode != ymm_mode
16071       && bytemode != d_scalar_mode
16072       && bytemode != d_scalar_swap_mode
16073       && bytemode != q_scalar_mode
16074       && bytemode != q_scalar_swap_mode
16075       && bytemode != vex_scalar_w_dq_mode)
16076     {
16077       switch (vex.length)
16078         {
16079         case 128:
16080           names = names_xmm;
16081           break;
16082         case 256:
16083           names = names_ymm;
16084           break;
16085         case 512:
16086           names = names_zmm;
16087           break;
16088         default:
16089           abort ();
16090         }
16091     }
16092   else if (bytemode == xmmq_mode
16093            || bytemode == evex_half_bcst_xmmq_mode)
16094     {
16095       switch (vex.length)
16096         {
16097         case 128:
16098         case 256:
16099           names = names_xmm;
16100           break;
16101         case 512:
16102           names = names_ymm;
16103           break;
16104         default:
16105           abort ();
16106         }
16107     }
16108   else if (bytemode == ymm_mode)
16109     names = names_ymm;
16110   else
16111     names = names_xmm;
16112   oappend (names[reg]);
16113 }
16114
16115 static void
16116 OP_MS (int bytemode, int sizeflag)
16117 {
16118   if (modrm.mod == 3)
16119     OP_EM (bytemode, sizeflag);
16120   else
16121     BadOp ();
16122 }
16123
16124 static void
16125 OP_XS (int bytemode, int sizeflag)
16126 {
16127   if (modrm.mod == 3)
16128     OP_EX (bytemode, sizeflag);
16129   else
16130     BadOp ();
16131 }
16132
16133 static void
16134 OP_M (int bytemode, int sizeflag)
16135 {
16136   if (modrm.mod == 3)
16137     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16138     BadOp ();
16139   else
16140     OP_E (bytemode, sizeflag);
16141 }
16142
16143 static void
16144 OP_0f07 (int bytemode, int sizeflag)
16145 {
16146   if (modrm.mod != 3 || modrm.rm != 0)
16147     BadOp ();
16148   else
16149     OP_E (bytemode, sizeflag);
16150 }
16151
16152 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16153    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16154
16155 static void
16156 NOP_Fixup1 (int bytemode, int sizeflag)
16157 {
16158   if ((prefixes & PREFIX_DATA) != 0
16159       || (rex != 0
16160           && rex != 0x48
16161           && address_mode == mode_64bit))
16162     OP_REG (bytemode, sizeflag);
16163   else
16164     strcpy (obuf, "nop");
16165 }
16166
16167 static void
16168 NOP_Fixup2 (int bytemode, int sizeflag)
16169 {
16170   if ((prefixes & PREFIX_DATA) != 0
16171       || (rex != 0
16172           && rex != 0x48
16173           && address_mode == mode_64bit))
16174     OP_IMREG (bytemode, sizeflag);
16175 }
16176
16177 static const char *const Suffix3DNow[] = {
16178 /* 00 */        NULL,           NULL,           NULL,           NULL,
16179 /* 04 */        NULL,           NULL,           NULL,           NULL,
16180 /* 08 */        NULL,           NULL,           NULL,           NULL,
16181 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16182 /* 10 */        NULL,           NULL,           NULL,           NULL,
16183 /* 14 */        NULL,           NULL,           NULL,           NULL,
16184 /* 18 */        NULL,           NULL,           NULL,           NULL,
16185 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16186 /* 20 */        NULL,           NULL,           NULL,           NULL,
16187 /* 24 */        NULL,           NULL,           NULL,           NULL,
16188 /* 28 */        NULL,           NULL,           NULL,           NULL,
16189 /* 2C */        NULL,           NULL,           NULL,           NULL,
16190 /* 30 */        NULL,           NULL,           NULL,           NULL,
16191 /* 34 */        NULL,           NULL,           NULL,           NULL,
16192 /* 38 */        NULL,           NULL,           NULL,           NULL,
16193 /* 3C */        NULL,           NULL,           NULL,           NULL,
16194 /* 40 */        NULL,           NULL,           NULL,           NULL,
16195 /* 44 */        NULL,           NULL,           NULL,           NULL,
16196 /* 48 */        NULL,           NULL,           NULL,           NULL,
16197 /* 4C */        NULL,           NULL,           NULL,           NULL,
16198 /* 50 */        NULL,           NULL,           NULL,           NULL,
16199 /* 54 */        NULL,           NULL,           NULL,           NULL,
16200 /* 58 */        NULL,           NULL,           NULL,           NULL,
16201 /* 5C */        NULL,           NULL,           NULL,           NULL,
16202 /* 60 */        NULL,           NULL,           NULL,           NULL,
16203 /* 64 */        NULL,           NULL,           NULL,           NULL,
16204 /* 68 */        NULL,           NULL,           NULL,           NULL,
16205 /* 6C */        NULL,           NULL,           NULL,           NULL,
16206 /* 70 */        NULL,           NULL,           NULL,           NULL,
16207 /* 74 */        NULL,           NULL,           NULL,           NULL,
16208 /* 78 */        NULL,           NULL,           NULL,           NULL,
16209 /* 7C */        NULL,           NULL,           NULL,           NULL,
16210 /* 80 */        NULL,           NULL,           NULL,           NULL,
16211 /* 84 */        NULL,           NULL,           NULL,           NULL,
16212 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16213 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16214 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16215 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16216 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16217 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16218 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16219 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16220 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16221 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16222 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16223 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16224 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16225 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16226 /* C0 */        NULL,           NULL,           NULL,           NULL,
16227 /* C4 */        NULL,           NULL,           NULL,           NULL,
16228 /* C8 */        NULL,           NULL,           NULL,           NULL,
16229 /* CC */        NULL,           NULL,           NULL,           NULL,
16230 /* D0 */        NULL,           NULL,           NULL,           NULL,
16231 /* D4 */        NULL,           NULL,           NULL,           NULL,
16232 /* D8 */        NULL,           NULL,           NULL,           NULL,
16233 /* DC */        NULL,           NULL,           NULL,           NULL,
16234 /* E0 */        NULL,           NULL,           NULL,           NULL,
16235 /* E4 */        NULL,           NULL,           NULL,           NULL,
16236 /* E8 */        NULL,           NULL,           NULL,           NULL,
16237 /* EC */        NULL,           NULL,           NULL,           NULL,
16238 /* F0 */        NULL,           NULL,           NULL,           NULL,
16239 /* F4 */        NULL,           NULL,           NULL,           NULL,
16240 /* F8 */        NULL,           NULL,           NULL,           NULL,
16241 /* FC */        NULL,           NULL,           NULL,           NULL,
16242 };
16243
16244 static void
16245 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16246 {
16247   const char *mnemonic;
16248
16249   FETCH_DATA (the_info, codep + 1);
16250   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16251      place where an 8-bit immediate would normally go.  ie. the last
16252      byte of the instruction.  */
16253   obufp = mnemonicendp;
16254   mnemonic = Suffix3DNow[*codep++ & 0xff];
16255   if (mnemonic)
16256     oappend (mnemonic);
16257   else
16258     {
16259       /* Since a variable sized modrm/sib chunk is between the start
16260          of the opcode (0x0f0f) and the opcode suffix, we need to do
16261          all the modrm processing first, and don't know until now that
16262          we have a bad opcode.  This necessitates some cleaning up.  */
16263       op_out[0][0] = '\0';
16264       op_out[1][0] = '\0';
16265       BadOp ();
16266     }
16267   mnemonicendp = obufp;
16268 }
16269
16270 static struct op simd_cmp_op[] =
16271 {
16272   { STRING_COMMA_LEN ("eq") },
16273   { STRING_COMMA_LEN ("lt") },
16274   { STRING_COMMA_LEN ("le") },
16275   { STRING_COMMA_LEN ("unord") },
16276   { STRING_COMMA_LEN ("neq") },
16277   { STRING_COMMA_LEN ("nlt") },
16278   { STRING_COMMA_LEN ("nle") },
16279   { STRING_COMMA_LEN ("ord") }
16280 };
16281
16282 static void
16283 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16284 {
16285   unsigned int cmp_type;
16286
16287   FETCH_DATA (the_info, codep + 1);
16288   cmp_type = *codep++ & 0xff;
16289   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16290     {
16291       char suffix [3];
16292       char *p = mnemonicendp - 2;
16293       suffix[0] = p[0];
16294       suffix[1] = p[1];
16295       suffix[2] = '\0';
16296       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16297       mnemonicendp += simd_cmp_op[cmp_type].len;
16298     }
16299   else
16300     {
16301       /* We have a reserved extension byte.  Output it directly.  */
16302       scratchbuf[0] = '$';
16303       print_operand_value (scratchbuf + 1, 1, cmp_type);
16304       oappend_maybe_intel (scratchbuf);
16305       scratchbuf[0] = '\0';
16306     }
16307 }
16308
16309 static void
16310 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16311           int sizeflag ATTRIBUTE_UNUSED)
16312 {
16313   /* mwait %eax,%ecx  */
16314   if (!intel_syntax)
16315     {
16316       const char **names = (address_mode == mode_64bit
16317                             ? names64 : names32);
16318       strcpy (op_out[0], names[0]);
16319       strcpy (op_out[1], names[1]);
16320       two_source_ops = 1;
16321     }
16322   /* Skip mod/rm byte.  */
16323   MODRM_CHECK;
16324   codep++;
16325 }
16326
16327 static void
16328 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16329             int sizeflag ATTRIBUTE_UNUSED)
16330 {
16331   /* monitor %eax,%ecx,%edx"  */
16332   if (!intel_syntax)
16333     {
16334       const char **op1_names;
16335       const char **names = (address_mode == mode_64bit
16336                             ? names64 : names32);
16337
16338       if (!(prefixes & PREFIX_ADDR))
16339         op1_names = (address_mode == mode_16bit
16340                      ? names16 : names);
16341       else
16342         {
16343           /* Remove "addr16/addr32".  */
16344           all_prefixes[last_addr_prefix] = 0;
16345           op1_names = (address_mode != mode_32bit
16346                        ? names32 : names16);
16347           used_prefixes |= PREFIX_ADDR;
16348         }
16349       strcpy (op_out[0], op1_names[0]);
16350       strcpy (op_out[1], names[1]);
16351       strcpy (op_out[2], names[2]);
16352       two_source_ops = 1;
16353     }
16354   /* Skip mod/rm byte.  */
16355   MODRM_CHECK;
16356   codep++;
16357 }
16358
16359 static void
16360 BadOp (void)
16361 {
16362   /* Throw away prefixes and 1st. opcode byte.  */
16363   codep = insn_codep + 1;
16364   oappend ("(bad)");
16365 }
16366
16367 static void
16368 REP_Fixup (int bytemode, int sizeflag)
16369 {
16370   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16371      lods and stos.  */
16372   if (prefixes & PREFIX_REPZ)
16373     all_prefixes[last_repz_prefix] = REP_PREFIX;
16374
16375   switch (bytemode)
16376     {
16377     case al_reg:
16378     case eAX_reg:
16379     case indir_dx_reg:
16380       OP_IMREG (bytemode, sizeflag);
16381       break;
16382     case eDI_reg:
16383       OP_ESreg (bytemode, sizeflag);
16384       break;
16385     case eSI_reg:
16386       OP_DSreg (bytemode, sizeflag);
16387       break;
16388     default:
16389       abort ();
16390       break;
16391     }
16392 }
16393
16394 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16395    "bnd".  */
16396
16397 static void
16398 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16399 {
16400   if (prefixes & PREFIX_REPNZ)
16401     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16402 }
16403
16404 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16405    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16406  */
16407
16408 static void
16409 HLE_Fixup1 (int bytemode, int sizeflag)
16410 {
16411   if (modrm.mod != 3
16412       && (prefixes & PREFIX_LOCK) != 0)
16413     {
16414       if (prefixes & PREFIX_REPZ)
16415         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16416       if (prefixes & PREFIX_REPNZ)
16417         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16418     }
16419
16420   OP_E (bytemode, sizeflag);
16421 }
16422
16423 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16424    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16425  */
16426
16427 static void
16428 HLE_Fixup2 (int bytemode, int sizeflag)
16429 {
16430   if (modrm.mod != 3)
16431     {
16432       if (prefixes & PREFIX_REPZ)
16433         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16434       if (prefixes & PREFIX_REPNZ)
16435         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16436     }
16437
16438   OP_E (bytemode, sizeflag);
16439 }
16440
16441 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16442    "xrelease" for memory operand.  No check for LOCK prefix.   */
16443
16444 static void
16445 HLE_Fixup3 (int bytemode, int sizeflag)
16446 {
16447   if (modrm.mod != 3
16448       && last_repz_prefix > last_repnz_prefix
16449       && (prefixes & PREFIX_REPZ) != 0)
16450     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16451
16452   OP_E (bytemode, sizeflag);
16453 }
16454
16455 static void
16456 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16457 {
16458   USED_REX (REX_W);
16459   if (rex & REX_W)
16460     {
16461       /* Change cmpxchg8b to cmpxchg16b.  */
16462       char *p = mnemonicendp - 2;
16463       mnemonicendp = stpcpy (p, "16b");
16464       bytemode = o_mode;
16465     }
16466   else if ((prefixes & PREFIX_LOCK) != 0)
16467     {
16468       if (prefixes & PREFIX_REPZ)
16469         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16470       if (prefixes & PREFIX_REPNZ)
16471         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16472     }
16473
16474   OP_M (bytemode, sizeflag);
16475 }
16476
16477 static void
16478 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16479 {
16480   const char **names;
16481
16482   if (need_vex)
16483     {
16484       switch (vex.length)
16485         {
16486         case 128:
16487           names = names_xmm;
16488           break;
16489         case 256:
16490           names = names_ymm;
16491           break;
16492         default:
16493           abort ();
16494         }
16495     }
16496   else
16497     names = names_xmm;
16498   oappend (names[reg]);
16499 }
16500
16501 static void
16502 CRC32_Fixup (int bytemode, int sizeflag)
16503 {
16504   /* Add proper suffix to "crc32".  */
16505   char *p = mnemonicendp;
16506
16507   switch (bytemode)
16508     {
16509     case b_mode:
16510       if (intel_syntax)
16511         goto skip;
16512
16513       *p++ = 'b';
16514       break;
16515     case v_mode:
16516       if (intel_syntax)
16517         goto skip;
16518
16519       USED_REX (REX_W);
16520       if (rex & REX_W)
16521         *p++ = 'q';
16522       else
16523         {
16524           if (sizeflag & DFLAG)
16525             *p++ = 'l';
16526           else
16527             *p++ = 'w';
16528           used_prefixes |= (prefixes & PREFIX_DATA);
16529         }
16530       break;
16531     default:
16532       oappend (INTERNAL_DISASSEMBLER_ERROR);
16533       break;
16534     }
16535   mnemonicendp = p;
16536   *p = '\0';
16537
16538 skip:
16539   if (modrm.mod == 3)
16540     {
16541       int add;
16542
16543       /* Skip mod/rm byte.  */
16544       MODRM_CHECK;
16545       codep++;
16546
16547       USED_REX (REX_B);
16548       add = (rex & REX_B) ? 8 : 0;
16549       if (bytemode == b_mode)
16550         {
16551           USED_REX (0);
16552           if (rex)
16553             oappend (names8rex[modrm.rm + add]);
16554           else
16555             oappend (names8[modrm.rm + add]);
16556         }
16557       else
16558         {
16559           USED_REX (REX_W);
16560           if (rex & REX_W)
16561             oappend (names64[modrm.rm + add]);
16562           else if ((prefixes & PREFIX_DATA))
16563             oappend (names16[modrm.rm + add]);
16564           else
16565             oappend (names32[modrm.rm + add]);
16566         }
16567     }
16568   else
16569     OP_E (bytemode, sizeflag);
16570 }
16571
16572 static void
16573 FXSAVE_Fixup (int bytemode, int sizeflag)
16574 {
16575   /* Add proper suffix to "fxsave" and "fxrstor".  */
16576   USED_REX (REX_W);
16577   if (rex & REX_W)
16578     {
16579       char *p = mnemonicendp;
16580       *p++ = '6';
16581       *p++ = '4';
16582       *p = '\0';
16583       mnemonicendp = p;
16584     }
16585   OP_M (bytemode, sizeflag);
16586 }
16587
16588 /* Display the destination register operand for instructions with
16589    VEX. */
16590
16591 static void
16592 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16593 {
16594   int reg;
16595   const char **names;
16596
16597   if (!need_vex)
16598     abort ();
16599
16600   if (!need_vex_reg)
16601     return;
16602
16603   reg = vex.register_specifier;
16604   if (vex.evex)
16605     {
16606       if (!vex.v)
16607         reg += 16;
16608     }
16609
16610   if (bytemode == vex_scalar_mode)
16611     {
16612       oappend (names_xmm[reg]);
16613       return;
16614     }
16615
16616   switch (vex.length)
16617     {
16618     case 128:
16619       switch (bytemode)
16620         {
16621         case vex_mode:
16622         case vex128_mode:
16623         case vex_vsib_q_w_dq_mode:
16624         case vex_vsib_q_w_d_mode:
16625           names = names_xmm;
16626           break;
16627         case dq_mode:
16628           if (vex.w)
16629             names = names64;
16630           else
16631             names = names32;
16632           break;
16633         case mask_bd_mode:
16634         case mask_mode:
16635           names = names_mask;
16636           break;
16637         default:
16638           abort ();
16639           return;
16640         }
16641       break;
16642     case 256:
16643       switch (bytemode)
16644         {
16645         case vex_mode:
16646         case vex256_mode:
16647           names = names_ymm;
16648           break;
16649         case vex_vsib_q_w_dq_mode:
16650         case vex_vsib_q_w_d_mode:
16651           names = vex.w ? names_ymm : names_xmm;
16652           break;
16653         case mask_bd_mode:
16654         case mask_mode:
16655           names = names_mask;
16656           break;
16657         default:
16658           abort ();
16659           return;
16660         }
16661       break;
16662     case 512:
16663       names = names_zmm;
16664       break;
16665     default:
16666       abort ();
16667       break;
16668     }
16669   oappend (names[reg]);
16670 }
16671
16672 /* Get the VEX immediate byte without moving codep.  */
16673
16674 static unsigned char
16675 get_vex_imm8 (int sizeflag, int opnum)
16676 {
16677   int bytes_before_imm = 0;
16678
16679   if (modrm.mod != 3)
16680     {
16681       /* There are SIB/displacement bytes.  */
16682       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16683         {
16684           /* 32/64 bit address mode */
16685           int base = modrm.rm;
16686
16687           /* Check SIB byte.  */
16688           if (base == 4)
16689             {
16690               FETCH_DATA (the_info, codep + 1);
16691               base = *codep & 7;
16692               /* When decoding the third source, don't increase
16693                  bytes_before_imm as this has already been incremented
16694                  by one in OP_E_memory while decoding the second
16695                  source operand.  */
16696               if (opnum == 0)
16697                 bytes_before_imm++;
16698             }
16699
16700           /* Don't increase bytes_before_imm when decoding the third source,
16701              it has already been incremented by OP_E_memory while decoding
16702              the second source operand.  */
16703           if (opnum == 0)
16704             {
16705               switch (modrm.mod)
16706                 {
16707                   case 0:
16708                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16709                        SIB == 5, there is a 4 byte displacement.  */
16710                     if (base != 5)
16711                       /* No displacement. */
16712                       break;
16713                   case 2:
16714                     /* 4 byte displacement.  */
16715                     bytes_before_imm += 4;
16716                     break;
16717                   case 1:
16718                     /* 1 byte displacement.  */
16719                     bytes_before_imm++;
16720                     break;
16721                 }
16722             }
16723         }
16724       else
16725         {
16726           /* 16 bit address mode */
16727           /* Don't increase bytes_before_imm when decoding the third source,
16728              it has already been incremented by OP_E_memory while decoding
16729              the second source operand.  */
16730           if (opnum == 0)
16731             {
16732               switch (modrm.mod)
16733                 {
16734                 case 0:
16735                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16736                   if (modrm.rm != 6)
16737                     /* No displacement. */
16738                     break;
16739                 case 2:
16740                   /* 2 byte displacement.  */
16741                   bytes_before_imm += 2;
16742                   break;
16743                 case 1:
16744                   /* 1 byte displacement: when decoding the third source,
16745                      don't increase bytes_before_imm as this has already
16746                      been incremented by one in OP_E_memory while decoding
16747                      the second source operand.  */
16748                   if (opnum == 0)
16749                     bytes_before_imm++;
16750
16751                   break;
16752                 }
16753             }
16754         }
16755     }
16756
16757   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16758   return codep [bytes_before_imm];
16759 }
16760
16761 static void
16762 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16763 {
16764   const char **names;
16765
16766   if (reg == -1 && modrm.mod != 3)
16767     {
16768       OP_E_memory (bytemode, sizeflag);
16769       return;
16770     }
16771   else
16772     {
16773       if (reg == -1)
16774         {
16775           reg = modrm.rm;
16776           USED_REX (REX_B);
16777           if (rex & REX_B)
16778             reg += 8;
16779         }
16780       else if (reg > 7 && address_mode != mode_64bit)
16781         BadOp ();
16782     }
16783
16784   switch (vex.length)
16785     {
16786     case 128:
16787       names = names_xmm;
16788       break;
16789     case 256:
16790       names = names_ymm;
16791       break;
16792     default:
16793       abort ();
16794     }
16795   oappend (names[reg]);
16796 }
16797
16798 static void
16799 OP_EX_VexImmW (int bytemode, int sizeflag)
16800 {
16801   int reg = -1;
16802   static unsigned char vex_imm8;
16803
16804   if (vex_w_done == 0)
16805     {
16806       vex_w_done = 1;
16807
16808       /* Skip mod/rm byte.  */
16809       MODRM_CHECK;
16810       codep++;
16811
16812       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16813
16814       if (vex.w)
16815           reg = vex_imm8 >> 4;
16816
16817       OP_EX_VexReg (bytemode, sizeflag, reg);
16818     }
16819   else if (vex_w_done == 1)
16820     {
16821       vex_w_done = 2;
16822
16823       if (!vex.w)
16824           reg = vex_imm8 >> 4;
16825
16826       OP_EX_VexReg (bytemode, sizeflag, reg);
16827     }
16828   else
16829     {
16830       /* Output the imm8 directly.  */
16831       scratchbuf[0] = '$';
16832       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16833       oappend_maybe_intel (scratchbuf);
16834       scratchbuf[0] = '\0';
16835       codep++;
16836     }
16837 }
16838
16839 static void
16840 OP_Vex_2src (int bytemode, int sizeflag)
16841 {
16842   if (modrm.mod == 3)
16843     {
16844       int reg = modrm.rm;
16845       USED_REX (REX_B);
16846       if (rex & REX_B)
16847         reg += 8;
16848       oappend (names_xmm[reg]);
16849     }
16850   else
16851     {
16852       if (intel_syntax
16853           && (bytemode == v_mode || bytemode == v_swap_mode))
16854         {
16855           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16856           used_prefixes |= (prefixes & PREFIX_DATA);
16857         }
16858       OP_E (bytemode, sizeflag);
16859     }
16860 }
16861
16862 static void
16863 OP_Vex_2src_1 (int bytemode, int sizeflag)
16864 {
16865   if (modrm.mod == 3)
16866     {
16867       /* Skip mod/rm byte.   */
16868       MODRM_CHECK;
16869       codep++;
16870     }
16871
16872   if (vex.w)
16873     oappend (names_xmm[vex.register_specifier]);
16874   else
16875     OP_Vex_2src (bytemode, sizeflag);
16876 }
16877
16878 static void
16879 OP_Vex_2src_2 (int bytemode, int sizeflag)
16880 {
16881   if (vex.w)
16882     OP_Vex_2src (bytemode, sizeflag);
16883   else
16884     oappend (names_xmm[vex.register_specifier]);
16885 }
16886
16887 static void
16888 OP_EX_VexW (int bytemode, int sizeflag)
16889 {
16890   int reg = -1;
16891
16892   if (!vex_w_done)
16893     {
16894       vex_w_done = 1;
16895
16896       /* Skip mod/rm byte.  */
16897       MODRM_CHECK;
16898       codep++;
16899
16900       if (vex.w)
16901         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16902     }
16903   else
16904     {
16905       if (!vex.w)
16906         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16907     }
16908
16909   OP_EX_VexReg (bytemode, sizeflag, reg);
16910 }
16911
16912 static void
16913 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16914              int sizeflag ATTRIBUTE_UNUSED)
16915 {
16916   /* Skip the immediate byte and check for invalid bits.  */
16917   FETCH_DATA (the_info, codep + 1);
16918   if (*codep++ & 0xf)
16919     BadOp ();
16920 }
16921
16922 static void
16923 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16924 {
16925   int reg;
16926   const char **names;
16927
16928   FETCH_DATA (the_info, codep + 1);
16929   reg = *codep++;
16930
16931   if (bytemode != x_mode)
16932     abort ();
16933
16934   if (reg & 0xf)
16935       BadOp ();
16936
16937   reg >>= 4;
16938   if (reg > 7 && address_mode != mode_64bit)
16939     BadOp ();
16940
16941   switch (vex.length)
16942     {
16943     case 128:
16944       names = names_xmm;
16945       break;
16946     case 256:
16947       names = names_ymm;
16948       break;
16949     default:
16950       abort ();
16951     }
16952   oappend (names[reg]);
16953 }
16954
16955 static void
16956 OP_XMM_VexW (int bytemode, int sizeflag)
16957 {
16958   /* Turn off the REX.W bit since it is used for swapping operands
16959      now.  */
16960   rex &= ~REX_W;
16961   OP_XMM (bytemode, sizeflag);
16962 }
16963
16964 static void
16965 OP_EX_Vex (int bytemode, int sizeflag)
16966 {
16967   if (modrm.mod != 3)
16968     {
16969       if (vex.register_specifier != 0)
16970         BadOp ();
16971       need_vex_reg = 0;
16972     }
16973   OP_EX (bytemode, sizeflag);
16974 }
16975
16976 static void
16977 OP_XMM_Vex (int bytemode, int sizeflag)
16978 {
16979   if (modrm.mod != 3)
16980     {
16981       if (vex.register_specifier != 0)
16982         BadOp ();
16983       need_vex_reg = 0;
16984     }
16985   OP_XMM (bytemode, sizeflag);
16986 }
16987
16988 static void
16989 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16990 {
16991   switch (vex.length)
16992     {
16993     case 128:
16994       mnemonicendp = stpcpy (obuf, "vzeroupper");
16995       break;
16996     case 256:
16997       mnemonicendp = stpcpy (obuf, "vzeroall");
16998       break;
16999     default:
17000       abort ();
17001     }
17002 }
17003
17004 static struct op vex_cmp_op[] =
17005 {
17006   { STRING_COMMA_LEN ("eq") },
17007   { STRING_COMMA_LEN ("lt") },
17008   { STRING_COMMA_LEN ("le") },
17009   { STRING_COMMA_LEN ("unord") },
17010   { STRING_COMMA_LEN ("neq") },
17011   { STRING_COMMA_LEN ("nlt") },
17012   { STRING_COMMA_LEN ("nle") },
17013   { STRING_COMMA_LEN ("ord") },
17014   { STRING_COMMA_LEN ("eq_uq") },
17015   { STRING_COMMA_LEN ("nge") },
17016   { STRING_COMMA_LEN ("ngt") },
17017   { STRING_COMMA_LEN ("false") },
17018   { STRING_COMMA_LEN ("neq_oq") },
17019   { STRING_COMMA_LEN ("ge") },
17020   { STRING_COMMA_LEN ("gt") },
17021   { STRING_COMMA_LEN ("true") },
17022   { STRING_COMMA_LEN ("eq_os") },
17023   { STRING_COMMA_LEN ("lt_oq") },
17024   { STRING_COMMA_LEN ("le_oq") },
17025   { STRING_COMMA_LEN ("unord_s") },
17026   { STRING_COMMA_LEN ("neq_us") },
17027   { STRING_COMMA_LEN ("nlt_uq") },
17028   { STRING_COMMA_LEN ("nle_uq") },
17029   { STRING_COMMA_LEN ("ord_s") },
17030   { STRING_COMMA_LEN ("eq_us") },
17031   { STRING_COMMA_LEN ("nge_uq") },
17032   { STRING_COMMA_LEN ("ngt_uq") },
17033   { STRING_COMMA_LEN ("false_os") },
17034   { STRING_COMMA_LEN ("neq_os") },
17035   { STRING_COMMA_LEN ("ge_oq") },
17036   { STRING_COMMA_LEN ("gt_oq") },
17037   { STRING_COMMA_LEN ("true_us") },
17038 };
17039
17040 static void
17041 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17042 {
17043   unsigned int cmp_type;
17044
17045   FETCH_DATA (the_info, codep + 1);
17046   cmp_type = *codep++ & 0xff;
17047   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17048     {
17049       char suffix [3];
17050       char *p = mnemonicendp - 2;
17051       suffix[0] = p[0];
17052       suffix[1] = p[1];
17053       suffix[2] = '\0';
17054       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17055       mnemonicendp += vex_cmp_op[cmp_type].len;
17056     }
17057   else
17058     {
17059       /* We have a reserved extension byte.  Output it directly.  */
17060       scratchbuf[0] = '$';
17061       print_operand_value (scratchbuf + 1, 1, cmp_type);
17062       oappend_maybe_intel (scratchbuf);
17063       scratchbuf[0] = '\0';
17064     }
17065 }
17066
17067 static void
17068 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17069              int sizeflag ATTRIBUTE_UNUSED)
17070 {
17071   unsigned int cmp_type;
17072
17073   if (!vex.evex)
17074     abort ();
17075
17076   FETCH_DATA (the_info, codep + 1);
17077   cmp_type = *codep++ & 0xff;
17078   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17079      If it's the case, print suffix, otherwise - print the immediate.  */
17080   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17081       && cmp_type != 3
17082       && cmp_type != 7)
17083     {
17084       char suffix [3];
17085       char *p = mnemonicendp - 2;
17086
17087       /* vpcmp* can have both one- and two-lettered suffix.  */
17088       if (p[0] == 'p')
17089         {
17090           p++;
17091           suffix[0] = p[0];
17092           suffix[1] = '\0';
17093         }
17094       else
17095         {
17096           suffix[0] = p[0];
17097           suffix[1] = p[1];
17098           suffix[2] = '\0';
17099         }
17100
17101       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17102       mnemonicendp += simd_cmp_op[cmp_type].len;
17103     }
17104   else
17105     {
17106       /* We have a reserved extension byte.  Output it directly.  */
17107       scratchbuf[0] = '$';
17108       print_operand_value (scratchbuf + 1, 1, cmp_type);
17109       oappend_maybe_intel (scratchbuf);
17110       scratchbuf[0] = '\0';
17111     }
17112 }
17113
17114 static const struct op pclmul_op[] =
17115 {
17116   { STRING_COMMA_LEN ("lql") },
17117   { STRING_COMMA_LEN ("hql") },
17118   { STRING_COMMA_LEN ("lqh") },
17119   { STRING_COMMA_LEN ("hqh") }
17120 };
17121
17122 static void
17123 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17124               int sizeflag ATTRIBUTE_UNUSED)
17125 {
17126   unsigned int pclmul_type;
17127
17128   FETCH_DATA (the_info, codep + 1);
17129   pclmul_type = *codep++ & 0xff;
17130   switch (pclmul_type)
17131     {
17132     case 0x10:
17133       pclmul_type = 2;
17134       break;
17135     case 0x11:
17136       pclmul_type = 3;
17137       break;
17138     default:
17139       break;
17140     }
17141   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17142     {
17143       char suffix [4];
17144       char *p = mnemonicendp - 3;
17145       suffix[0] = p[0];
17146       suffix[1] = p[1];
17147       suffix[2] = p[2];
17148       suffix[3] = '\0';
17149       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17150       mnemonicendp += pclmul_op[pclmul_type].len;
17151     }
17152   else
17153     {
17154       /* We have a reserved extension byte.  Output it directly.  */
17155       scratchbuf[0] = '$';
17156       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17157       oappend_maybe_intel (scratchbuf);
17158       scratchbuf[0] = '\0';
17159     }
17160 }
17161
17162 static void
17163 MOVBE_Fixup (int bytemode, int sizeflag)
17164 {
17165   /* Add proper suffix to "movbe".  */
17166   char *p = mnemonicendp;
17167
17168   switch (bytemode)
17169     {
17170     case v_mode:
17171       if (intel_syntax)
17172         goto skip;
17173
17174       USED_REX (REX_W);
17175       if (sizeflag & SUFFIX_ALWAYS)
17176         {
17177           if (rex & REX_W)
17178             *p++ = 'q';
17179           else
17180             {
17181               if (sizeflag & DFLAG)
17182                 *p++ = 'l';
17183               else
17184                 *p++ = 'w';
17185               used_prefixes |= (prefixes & PREFIX_DATA);
17186             }
17187         }
17188       break;
17189     default:
17190       oappend (INTERNAL_DISASSEMBLER_ERROR);
17191       break;
17192     }
17193   mnemonicendp = p;
17194   *p = '\0';
17195
17196 skip:
17197   OP_M (bytemode, sizeflag);
17198 }
17199
17200 static void
17201 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17202 {
17203   int reg;
17204   const char **names;
17205
17206   /* Skip mod/rm byte.  */
17207   MODRM_CHECK;
17208   codep++;
17209
17210   if (vex.w)
17211     names = names64;
17212   else
17213     names = names32;
17214
17215   reg = modrm.rm;
17216   USED_REX (REX_B);
17217   if (rex & REX_B)
17218     reg += 8;
17219
17220   oappend (names[reg]);
17221 }
17222
17223 static void
17224 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17225 {
17226   const char **names;
17227
17228   if (vex.w)
17229     names = names64;
17230   else
17231     names = names32;
17232
17233   oappend (names[vex.register_specifier]);
17234 }
17235
17236 static void
17237 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17238 {
17239   if (!vex.evex
17240       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17241     abort ();
17242
17243   USED_REX (REX_R);
17244   if ((rex & REX_R) != 0 || !vex.r)
17245     {
17246       BadOp ();
17247       return;
17248     }
17249
17250   oappend (names_mask [modrm.reg]);
17251 }
17252
17253 static void
17254 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17255 {
17256   if (!vex.evex
17257       || (bytemode != evex_rounding_mode
17258           && bytemode != evex_sae_mode))
17259     abort ();
17260   if (modrm.mod == 3 && vex.b)
17261     switch (bytemode)
17262       {
17263       case evex_rounding_mode:
17264         oappend (names_rounding[vex.ll]);
17265         break;
17266       case evex_sae_mode:
17267         oappend ("{sae}");
17268         break;
17269       default:
17270         break;
17271       }
17272 }