1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void OP_Mwaitx (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte
*max_fetched
;
133 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
136 OPCODES_SIGJMP_BUF bailout
;
146 enum address_mode address_mode
;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored
;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Edqa { OP_E, dqa_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mv_bnd { OP_M, v_bndmk_mode }
277 #define Mx { OP_M, x_mode }
278 #define Mxmm { OP_M, xmm_mode }
279 #define Gb { OP_G, b_mode }
280 #define Gbnd { OP_G, bnd_mode }
281 #define Gv { OP_G, v_mode }
282 #define Gd { OP_G, d_mode }
283 #define Gdq { OP_G, dq_mode }
284 #define Gm { OP_G, m_mode }
285 #define Gva { OP_G, va_mode }
286 #define Gw { OP_G, w_mode }
287 #define Rd { OP_R, d_mode }
288 #define Rdq { OP_R, dq_mode }
289 #define Rm { OP_R, m_mode }
290 #define Ib { OP_I, b_mode }
291 #define sIb { OP_sI, b_mode } /* sign extened byte */
292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
293 #define Iv { OP_I, v_mode }
294 #define sIv { OP_sI, v_mode }
295 #define Iq { OP_I, q_mode }
296 #define Iv64 { OP_I64, v_mode }
297 #define Iw { OP_I, w_mode }
298 #define I1 { OP_I, const_1_mode }
299 #define Jb { OP_J, b_mode }
300 #define Jv { OP_J, v_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXbScalar { OP_EX, b_scalar_mode }
384 #define EXw { OP_EX, w_mode }
385 #define EXwScalar { OP_EX, w_scalar_mode }
386 #define EXd { OP_EX, d_mode }
387 #define EXdScalar { OP_EX, d_scalar_mode }
388 #define EXdS { OP_EX, d_swap_mode }
389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
390 #define EXq { OP_EX, q_mode }
391 #define EXqScalar { OP_EX, q_scalar_mode }
392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
393 #define EXqS { OP_EX, q_swap_mode }
394 #define EXx { OP_EX, x_mode }
395 #define EXxS { OP_EX, x_swap_mode }
396 #define EXxmm { OP_EX, xmm_mode }
397 #define EXymm { OP_EX, ymm_mode }
398 #define EXxmmq { OP_EX, xmmq_mode }
399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
402 #define EXxmm_md { OP_EX, xmm_md_mode }
403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
405 #define EXxmmdw { OP_EX, xmmdw_mode }
406 #define EXxmmqd { OP_EX, xmmqd_mode }
407 #define EXymmq { OP_EX, ymmq_mode }
408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
412 #define MS { OP_MS, v_mode }
413 #define XS { OP_XS, v_mode }
414 #define EMCq { OP_EMC, q_mode }
415 #define MXC { OP_MXC, 0 }
416 #define OPSUF { OP_3DNowSuffix, 0 }
417 #define CMP { CMP_Fixup, 0 }
418 #define XMM0 { XMM_Fixup, 0 }
419 #define FXSAVE { FXSAVE_Fixup, 0 }
420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
423 #define Vex { OP_VEX, vex_mode }
424 #define VexScalar { OP_VEX, vex_scalar_mode }
425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
426 #define Vex128 { OP_VEX, vex128_mode }
427 #define Vex256 { OP_VEX, vex256_mode }
428 #define VexGdq { OP_VEX, dq_mode }
429 #define EXdVex { OP_EX_Vex, d_mode }
430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
432 #define EXqVex { OP_EX_Vex, q_mode }
433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
435 #define EXVexW { OP_EX_VexW, x_mode }
436 #define EXdVexW { OP_EX_VexW, d_mode }
437 #define EXqVexW { OP_EX_VexW, q_mode }
438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
439 #define XMVex { OP_XMM_Vex, 0 }
440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
441 #define XMVexW { OP_XMM_VexW, 0 }
442 #define XMVexI4 { OP_REG_VexI4, x_mode }
443 #define PCLMUL { PCLMUL_Fixup, 0 }
444 #define VCMP { VCMP_Fixup, 0 }
445 #define VPCMP { VPCMP_Fixup, 0 }
446 #define VPCOM { VPCOM_Fixup, 0 }
448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
452 #define XMask { OP_Mask, mask_mode }
453 #define MaskG { OP_G, mask_mode }
454 #define MaskE { OP_E, mask_mode }
455 #define MaskBDE { OP_E, mask_bd_mode }
456 #define MaskR { OP_R, mask_mode }
457 #define MaskVex { OP_VEX, mask_mode }
459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
464 /* Used handle "rep" prefix for string instructions. */
465 #define Xbr { REP_Fixup, eSI_reg }
466 #define Xvr { REP_Fixup, eSI_reg }
467 #define Ybr { REP_Fixup, eDI_reg }
468 #define Yvr { REP_Fixup, eDI_reg }
469 #define Yzr { REP_Fixup, eDI_reg }
470 #define indirDXr { REP_Fixup, indir_dx_reg }
471 #define ALr { REP_Fixup, al_reg }
472 #define eAXr { REP_Fixup, eAX_reg }
474 /* Used handle HLE prefix for lockable instructions. */
475 #define Ebh1 { HLE_Fixup1, b_mode }
476 #define Evh1 { HLE_Fixup1, v_mode }
477 #define Ebh2 { HLE_Fixup2, b_mode }
478 #define Evh2 { HLE_Fixup2, v_mode }
479 #define Ebh3 { HLE_Fixup3, b_mode }
480 #define Evh3 { HLE_Fixup3, v_mode }
482 #define BND { BND_Fixup, 0 }
483 #define NOTRACK { NOTRACK_Fixup, 0 }
485 #define cond_jump_flag { NULL, cond_jump_mode }
486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
488 /* bits in sizeflag */
489 #define SUFFIX_ALWAYS 4
497 /* byte operand with operand swapped */
499 /* byte operand, sign extend like 'T' suffix */
501 /* operand size depends on prefixes */
503 /* operand size depends on prefixes with operand swapped */
505 /* operand size depends on address prefix */
509 /* double word operand */
511 /* double word operand with operand swapped */
513 /* quad word operand */
515 /* quad word operand with operand swapped */
517 /* ten-byte operand */
519 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
520 broadcast enabled. */
522 /* Similar to x_mode, but with different EVEX mem shifts. */
524 /* Similar to x_mode, but with disabled broadcast. */
526 /* Similar to x_mode, but with operands swapped and disabled broadcast
529 /* 16-byte XMM operand */
531 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
532 memory operand (depending on vector length). Broadcast isn't
535 /* Same as xmmq_mode, but broadcast is allowed. */
536 evex_half_bcst_xmmq_mode
,
537 /* XMM register or byte memory operand */
539 /* XMM register or word memory operand */
541 /* XMM register or double word memory operand */
543 /* XMM register or quad word memory operand */
545 /* XMM register or double/quad word memory operand, depending on
548 /* 16-byte XMM, word, double word or quad word operand. */
550 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
552 /* 32-byte YMM operand */
554 /* quad word, ymmword or zmmword memory operand. */
556 /* 32-byte YMM or 16-byte word operand */
558 /* d_mode in 32bit, q_mode in 64bit mode. */
560 /* pair of v_mode operands */
565 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
567 /* operand size depends on REX prefixes. */
569 /* registers like dq_mode, memory like w_mode. */
573 /* bounds operand with operand swapped */
575 /* 4- or 6-byte pointer operand */
578 /* v_mode for indirect branch opcodes. */
580 /* v_mode for stack-related opcodes. */
582 /* non-quad operand size depends on prefixes */
584 /* 16-byte operand */
586 /* registers like dq_mode, memory like b_mode. */
588 /* registers like d_mode, memory like b_mode. */
590 /* registers like d_mode, memory like w_mode. */
592 /* registers like dq_mode, memory like d_mode. */
594 /* operand size depends on the W bit as well as address mode. */
596 /* normal vex mode */
598 /* 128bit vex mode */
600 /* 256bit vex mode */
602 /* operand size depends on the VEX.W bit. */
605 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
606 vex_vsib_d_w_dq_mode
,
607 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
609 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
610 vex_vsib_q_w_dq_mode
,
611 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
614 /* scalar, ignore vector length. */
616 /* like b_mode, ignore vector length. */
618 /* like w_mode, ignore vector length. */
620 /* like d_mode, ignore vector length. */
622 /* like d_swap_mode, ignore vector length. */
624 /* like q_mode, ignore vector length. */
626 /* like q_swap_mode, ignore vector length. */
628 /* like vex_mode, ignore vector length. */
630 /* like vex_w_dq_mode, ignore vector length. */
631 vex_scalar_w_dq_mode
,
633 /* Static rounding. */
635 /* Static rounding, 64-bit mode only. */
636 evex_rounding_64_mode
,
637 /* Supress all exceptions. */
640 /* Mask register operand. */
642 /* Mask register operand. */
710 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
712 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
713 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
714 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
715 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
716 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
717 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
718 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
719 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
720 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
721 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
722 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
723 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
724 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
725 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
726 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
727 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
853 MOD_VEX_0F12_PREFIX_0
,
855 MOD_VEX_0F16_PREFIX_0
,
858 MOD_VEX_W_0_0F41_P_0_LEN_1
,
859 MOD_VEX_W_1_0F41_P_0_LEN_1
,
860 MOD_VEX_W_0_0F41_P_2_LEN_1
,
861 MOD_VEX_W_1_0F41_P_2_LEN_1
,
862 MOD_VEX_W_0_0F42_P_0_LEN_1
,
863 MOD_VEX_W_1_0F42_P_0_LEN_1
,
864 MOD_VEX_W_0_0F42_P_2_LEN_1
,
865 MOD_VEX_W_1_0F42_P_2_LEN_1
,
866 MOD_VEX_W_0_0F44_P_0_LEN_1
,
867 MOD_VEX_W_1_0F44_P_0_LEN_1
,
868 MOD_VEX_W_0_0F44_P_2_LEN_1
,
869 MOD_VEX_W_1_0F44_P_2_LEN_1
,
870 MOD_VEX_W_0_0F45_P_0_LEN_1
,
871 MOD_VEX_W_1_0F45_P_0_LEN_1
,
872 MOD_VEX_W_0_0F45_P_2_LEN_1
,
873 MOD_VEX_W_1_0F45_P_2_LEN_1
,
874 MOD_VEX_W_0_0F46_P_0_LEN_1
,
875 MOD_VEX_W_1_0F46_P_0_LEN_1
,
876 MOD_VEX_W_0_0F46_P_2_LEN_1
,
877 MOD_VEX_W_1_0F46_P_2_LEN_1
,
878 MOD_VEX_W_0_0F47_P_0_LEN_1
,
879 MOD_VEX_W_1_0F47_P_0_LEN_1
,
880 MOD_VEX_W_0_0F47_P_2_LEN_1
,
881 MOD_VEX_W_1_0F47_P_2_LEN_1
,
882 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
883 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
884 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
885 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
886 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
887 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
888 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
900 MOD_VEX_W_0_0F91_P_0_LEN_0
,
901 MOD_VEX_W_1_0F91_P_0_LEN_0
,
902 MOD_VEX_W_0_0F91_P_2_LEN_0
,
903 MOD_VEX_W_1_0F91_P_2_LEN_0
,
904 MOD_VEX_W_0_0F92_P_0_LEN_0
,
905 MOD_VEX_W_0_0F92_P_2_LEN_0
,
906 MOD_VEX_0F92_P_3_LEN_0
,
907 MOD_VEX_W_0_0F93_P_0_LEN_0
,
908 MOD_VEX_W_0_0F93_P_2_LEN_0
,
909 MOD_VEX_0F93_P_3_LEN_0
,
910 MOD_VEX_W_0_0F98_P_0_LEN_0
,
911 MOD_VEX_W_1_0F98_P_0_LEN_0
,
912 MOD_VEX_W_0_0F98_P_2_LEN_0
,
913 MOD_VEX_W_1_0F98_P_2_LEN_0
,
914 MOD_VEX_W_0_0F99_P_0_LEN_0
,
915 MOD_VEX_W_1_0F99_P_0_LEN_0
,
916 MOD_VEX_W_0_0F99_P_2_LEN_0
,
917 MOD_VEX_W_1_0F99_P_2_LEN_0
,
920 MOD_VEX_0FD7_PREFIX_2
,
921 MOD_VEX_0FE7_PREFIX_2
,
922 MOD_VEX_0FF0_PREFIX_3
,
923 MOD_VEX_0F381A_PREFIX_2
,
924 MOD_VEX_0F382A_PREFIX_2
,
925 MOD_VEX_0F382C_PREFIX_2
,
926 MOD_VEX_0F382D_PREFIX_2
,
927 MOD_VEX_0F382E_PREFIX_2
,
928 MOD_VEX_0F382F_PREFIX_2
,
929 MOD_VEX_0F385A_PREFIX_2
,
930 MOD_VEX_0F388C_PREFIX_2
,
931 MOD_VEX_0F388E_PREFIX_2
,
932 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
933 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
934 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
935 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
936 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
937 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
938 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
939 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
941 MOD_EVEX_0F10_PREFIX_1
,
942 MOD_EVEX_0F10_PREFIX_3
,
943 MOD_EVEX_0F11_PREFIX_1
,
944 MOD_EVEX_0F11_PREFIX_3
,
945 MOD_EVEX_0F12_PREFIX_0
,
946 MOD_EVEX_0F16_PREFIX_0
,
947 MOD_EVEX_0F38C6_REG_1
,
948 MOD_EVEX_0F38C6_REG_2
,
949 MOD_EVEX_0F38C6_REG_5
,
950 MOD_EVEX_0F38C6_REG_6
,
951 MOD_EVEX_0F38C7_REG_1
,
952 MOD_EVEX_0F38C7_REG_2
,
953 MOD_EVEX_0F38C7_REG_5
,
954 MOD_EVEX_0F38C7_REG_6
975 PREFIX_MOD_0_0F01_REG_5
,
976 PREFIX_MOD_3_0F01_REG_5_RM_0
,
977 PREFIX_MOD_3_0F01_REG_5_RM_2
,
1023 PREFIX_MOD_0_0FAE_REG_4
,
1024 PREFIX_MOD_3_0FAE_REG_4
,
1025 PREFIX_MOD_0_0FAE_REG_5
,
1026 PREFIX_MOD_3_0FAE_REG_5
,
1027 PREFIX_MOD_0_0FAE_REG_6
,
1028 PREFIX_MOD_1_0FAE_REG_6
,
1035 PREFIX_MOD_0_0FC7_REG_6
,
1036 PREFIX_MOD_3_0FC7_REG_6
,
1037 PREFIX_MOD_3_0FC7_REG_7
,
1167 PREFIX_VEX_0F71_REG_2
,
1168 PREFIX_VEX_0F71_REG_4
,
1169 PREFIX_VEX_0F71_REG_6
,
1170 PREFIX_VEX_0F72_REG_2
,
1171 PREFIX_VEX_0F72_REG_4
,
1172 PREFIX_VEX_0F72_REG_6
,
1173 PREFIX_VEX_0F73_REG_2
,
1174 PREFIX_VEX_0F73_REG_3
,
1175 PREFIX_VEX_0F73_REG_6
,
1176 PREFIX_VEX_0F73_REG_7
,
1349 PREFIX_VEX_0F38F3_REG_1
,
1350 PREFIX_VEX_0F38F3_REG_2
,
1351 PREFIX_VEX_0F38F3_REG_3
,
1470 PREFIX_EVEX_0F71_REG_2
,
1471 PREFIX_EVEX_0F71_REG_4
,
1472 PREFIX_EVEX_0F71_REG_6
,
1473 PREFIX_EVEX_0F72_REG_0
,
1474 PREFIX_EVEX_0F72_REG_1
,
1475 PREFIX_EVEX_0F72_REG_2
,
1476 PREFIX_EVEX_0F72_REG_4
,
1477 PREFIX_EVEX_0F72_REG_6
,
1478 PREFIX_EVEX_0F73_REG_2
,
1479 PREFIX_EVEX_0F73_REG_3
,
1480 PREFIX_EVEX_0F73_REG_6
,
1481 PREFIX_EVEX_0F73_REG_7
,
1677 PREFIX_EVEX_0F38C6_REG_1
,
1678 PREFIX_EVEX_0F38C6_REG_2
,
1679 PREFIX_EVEX_0F38C6_REG_5
,
1680 PREFIX_EVEX_0F38C6_REG_6
,
1681 PREFIX_EVEX_0F38C7_REG_1
,
1682 PREFIX_EVEX_0F38C7_REG_2
,
1683 PREFIX_EVEX_0F38C7_REG_5
,
1684 PREFIX_EVEX_0F38C7_REG_6
,
1786 THREE_BYTE_0F38
= 0,
1813 VEX_LEN_0F12_P_0_M_0
= 0,
1814 VEX_LEN_0F12_P_0_M_1
,
1817 VEX_LEN_0F16_P_0_M_0
,
1818 VEX_LEN_0F16_P_0_M_1
,
1861 VEX_LEN_0FAE_R_2_M_0
,
1862 VEX_LEN_0FAE_R_3_M_0
,
1869 VEX_LEN_0F381A_P_2_M_0
,
1872 VEX_LEN_0F385A_P_2_M_0
,
1875 VEX_LEN_0F38F3_R_1_P_0
,
1876 VEX_LEN_0F38F3_R_2_P_0
,
1877 VEX_LEN_0F38F3_R_3_P_0
,
1920 VEX_LEN_0FXOP_08_CC
,
1921 VEX_LEN_0FXOP_08_CD
,
1922 VEX_LEN_0FXOP_08_CE
,
1923 VEX_LEN_0FXOP_08_CF
,
1924 VEX_LEN_0FXOP_08_EC
,
1925 VEX_LEN_0FXOP_08_ED
,
1926 VEX_LEN_0FXOP_08_EE
,
1927 VEX_LEN_0FXOP_08_EF
,
1928 VEX_LEN_0FXOP_09_80
,
1934 EVEX_LEN_0F6E_P_2
= 0,
1942 VEX_W_0F41_P_0_LEN_1
= 0,
1943 VEX_W_0F41_P_2_LEN_1
,
1944 VEX_W_0F42_P_0_LEN_1
,
1945 VEX_W_0F42_P_2_LEN_1
,
1946 VEX_W_0F44_P_0_LEN_0
,
1947 VEX_W_0F44_P_2_LEN_0
,
1948 VEX_W_0F45_P_0_LEN_1
,
1949 VEX_W_0F45_P_2_LEN_1
,
1950 VEX_W_0F46_P_0_LEN_1
,
1951 VEX_W_0F46_P_2_LEN_1
,
1952 VEX_W_0F47_P_0_LEN_1
,
1953 VEX_W_0F47_P_2_LEN_1
,
1954 VEX_W_0F4A_P_0_LEN_1
,
1955 VEX_W_0F4A_P_2_LEN_1
,
1956 VEX_W_0F4B_P_0_LEN_1
,
1957 VEX_W_0F4B_P_2_LEN_1
,
1958 VEX_W_0F90_P_0_LEN_0
,
1959 VEX_W_0F90_P_2_LEN_0
,
1960 VEX_W_0F91_P_0_LEN_0
,
1961 VEX_W_0F91_P_2_LEN_0
,
1962 VEX_W_0F92_P_0_LEN_0
,
1963 VEX_W_0F92_P_2_LEN_0
,
1964 VEX_W_0F93_P_0_LEN_0
,
1965 VEX_W_0F93_P_2_LEN_0
,
1966 VEX_W_0F98_P_0_LEN_0
,
1967 VEX_W_0F98_P_2_LEN_0
,
1968 VEX_W_0F99_P_0_LEN_0
,
1969 VEX_W_0F99_P_2_LEN_0
,
1977 VEX_W_0F381A_P_2_M_0
,
1978 VEX_W_0F382C_P_2_M_0
,
1979 VEX_W_0F382D_P_2_M_0
,
1980 VEX_W_0F382E_P_2_M_0
,
1981 VEX_W_0F382F_P_2_M_0
,
1986 VEX_W_0F385A_P_2_M_0
,
1998 VEX_W_0F3A30_P_2_LEN_0
,
1999 VEX_W_0F3A31_P_2_LEN_0
,
2000 VEX_W_0F3A32_P_2_LEN_0
,
2001 VEX_W_0F3A33_P_2_LEN_0
,
2014 EVEX_W_0F10_P_1_M_0
,
2015 EVEX_W_0F10_P_1_M_1
,
2017 EVEX_W_0F10_P_3_M_0
,
2018 EVEX_W_0F10_P_3_M_1
,
2020 EVEX_W_0F11_P_1_M_0
,
2021 EVEX_W_0F11_P_1_M_1
,
2023 EVEX_W_0F11_P_3_M_0
,
2024 EVEX_W_0F11_P_3_M_1
,
2025 EVEX_W_0F12_P_0_M_0
,
2026 EVEX_W_0F12_P_0_M_1
,
2036 EVEX_W_0F16_P_0_M_0
,
2037 EVEX_W_0F16_P_0_M_1
,
2107 EVEX_W_0F72_R_2_P_2
,
2108 EVEX_W_0F72_R_6_P_2
,
2109 EVEX_W_0F73_R_2_P_2
,
2110 EVEX_W_0F73_R_6_P_2
,
2217 EVEX_W_0F38C7_R_1_P_2
,
2218 EVEX_W_0F38C7_R_2_P_2
,
2219 EVEX_W_0F38C7_R_5_P_2
,
2220 EVEX_W_0F38C7_R_6_P_2
,
2259 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2268 unsigned int prefix_requirement
;
2271 /* Upper case letters in the instruction names here are macros.
2272 'A' => print 'b' if no register operands or suffix_always is true
2273 'B' => print 'b' if suffix_always is true
2274 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2276 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2277 suffix_always is true
2278 'E' => print 'e' if 32-bit form of jcxz
2279 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2280 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2281 'H' => print ",pt" or ",pn" branch hint
2282 'I' => honor following macro letter even in Intel mode (implemented only
2283 for some of the macro letters)
2285 'K' => print 'd' or 'q' if rex prefix is present.
2286 'L' => print 'l' if suffix_always is true
2287 'M' => print 'r' if intel_mnemonic is false.
2288 'N' => print 'n' if instruction has no wait "prefix"
2289 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2290 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2291 or suffix_always is true. print 'q' if rex prefix is present.
2292 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2294 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2295 'S' => print 'w', 'l' or 'q' if suffix_always is true
2296 'T' => print 'q' in 64bit mode if instruction has no operand size
2297 prefix and behave as 'P' otherwise
2298 'U' => print 'q' in 64bit mode if instruction has no operand size
2299 prefix and behave as 'Q' otherwise
2300 'V' => print 'q' in 64bit mode if instruction has no operand size
2301 prefix and behave as 'S' otherwise
2302 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2303 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2305 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2306 '!' => change condition from true to false or from false to true.
2307 '%' => add 1 upper case letter to the macro.
2308 '^' => print 'w' or 'l' depending on operand size prefix or
2309 suffix_always is true (lcall/ljmp).
2310 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2311 on operand size prefix.
2312 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2313 has no operand size prefix for AMD64 ISA, behave as 'P'
2316 2 upper case letter macros:
2317 "XY" => print 'x' or 'y' if suffix_always is true or no register
2318 operands and no broadcast.
2319 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2320 register operands and no broadcast.
2321 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2322 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2323 or suffix_always is true
2324 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2325 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2326 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2327 "LW" => print 'd', 'q' depending on the VEX.W bit
2328 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2329 an operand size prefix, or suffix_always is true. print
2330 'q' if rex prefix is present.
2332 Many of the above letters print nothing in Intel mode. See "putop"
2335 Braces '{' and '}', and vertical bars '|', indicate alternative
2336 mnemonic strings for AT&T and Intel. */
2338 static const struct dis386 dis386
[] = {
2340 { "addB", { Ebh1
, Gb
}, 0 },
2341 { "addS", { Evh1
, Gv
}, 0 },
2342 { "addB", { Gb
, EbS
}, 0 },
2343 { "addS", { Gv
, EvS
}, 0 },
2344 { "addB", { AL
, Ib
}, 0 },
2345 { "addS", { eAX
, Iv
}, 0 },
2346 { X86_64_TABLE (X86_64_06
) },
2347 { X86_64_TABLE (X86_64_07
) },
2349 { "orB", { Ebh1
, Gb
}, 0 },
2350 { "orS", { Evh1
, Gv
}, 0 },
2351 { "orB", { Gb
, EbS
}, 0 },
2352 { "orS", { Gv
, EvS
}, 0 },
2353 { "orB", { AL
, Ib
}, 0 },
2354 { "orS", { eAX
, Iv
}, 0 },
2355 { X86_64_TABLE (X86_64_0D
) },
2356 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2358 { "adcB", { Ebh1
, Gb
}, 0 },
2359 { "adcS", { Evh1
, Gv
}, 0 },
2360 { "adcB", { Gb
, EbS
}, 0 },
2361 { "adcS", { Gv
, EvS
}, 0 },
2362 { "adcB", { AL
, Ib
}, 0 },
2363 { "adcS", { eAX
, Iv
}, 0 },
2364 { X86_64_TABLE (X86_64_16
) },
2365 { X86_64_TABLE (X86_64_17
) },
2367 { "sbbB", { Ebh1
, Gb
}, 0 },
2368 { "sbbS", { Evh1
, Gv
}, 0 },
2369 { "sbbB", { Gb
, EbS
}, 0 },
2370 { "sbbS", { Gv
, EvS
}, 0 },
2371 { "sbbB", { AL
, Ib
}, 0 },
2372 { "sbbS", { eAX
, Iv
}, 0 },
2373 { X86_64_TABLE (X86_64_1E
) },
2374 { X86_64_TABLE (X86_64_1F
) },
2376 { "andB", { Ebh1
, Gb
}, 0 },
2377 { "andS", { Evh1
, Gv
}, 0 },
2378 { "andB", { Gb
, EbS
}, 0 },
2379 { "andS", { Gv
, EvS
}, 0 },
2380 { "andB", { AL
, Ib
}, 0 },
2381 { "andS", { eAX
, Iv
}, 0 },
2382 { Bad_Opcode
}, /* SEG ES prefix */
2383 { X86_64_TABLE (X86_64_27
) },
2385 { "subB", { Ebh1
, Gb
}, 0 },
2386 { "subS", { Evh1
, Gv
}, 0 },
2387 { "subB", { Gb
, EbS
}, 0 },
2388 { "subS", { Gv
, EvS
}, 0 },
2389 { "subB", { AL
, Ib
}, 0 },
2390 { "subS", { eAX
, Iv
}, 0 },
2391 { Bad_Opcode
}, /* SEG CS prefix */
2392 { X86_64_TABLE (X86_64_2F
) },
2394 { "xorB", { Ebh1
, Gb
}, 0 },
2395 { "xorS", { Evh1
, Gv
}, 0 },
2396 { "xorB", { Gb
, EbS
}, 0 },
2397 { "xorS", { Gv
, EvS
}, 0 },
2398 { "xorB", { AL
, Ib
}, 0 },
2399 { "xorS", { eAX
, Iv
}, 0 },
2400 { Bad_Opcode
}, /* SEG SS prefix */
2401 { X86_64_TABLE (X86_64_37
) },
2403 { "cmpB", { Eb
, Gb
}, 0 },
2404 { "cmpS", { Ev
, Gv
}, 0 },
2405 { "cmpB", { Gb
, EbS
}, 0 },
2406 { "cmpS", { Gv
, EvS
}, 0 },
2407 { "cmpB", { AL
, Ib
}, 0 },
2408 { "cmpS", { eAX
, Iv
}, 0 },
2409 { Bad_Opcode
}, /* SEG DS prefix */
2410 { X86_64_TABLE (X86_64_3F
) },
2412 { "inc{S|}", { RMeAX
}, 0 },
2413 { "inc{S|}", { RMeCX
}, 0 },
2414 { "inc{S|}", { RMeDX
}, 0 },
2415 { "inc{S|}", { RMeBX
}, 0 },
2416 { "inc{S|}", { RMeSP
}, 0 },
2417 { "inc{S|}", { RMeBP
}, 0 },
2418 { "inc{S|}", { RMeSI
}, 0 },
2419 { "inc{S|}", { RMeDI
}, 0 },
2421 { "dec{S|}", { RMeAX
}, 0 },
2422 { "dec{S|}", { RMeCX
}, 0 },
2423 { "dec{S|}", { RMeDX
}, 0 },
2424 { "dec{S|}", { RMeBX
}, 0 },
2425 { "dec{S|}", { RMeSP
}, 0 },
2426 { "dec{S|}", { RMeBP
}, 0 },
2427 { "dec{S|}", { RMeSI
}, 0 },
2428 { "dec{S|}", { RMeDI
}, 0 },
2430 { "pushV", { RMrAX
}, 0 },
2431 { "pushV", { RMrCX
}, 0 },
2432 { "pushV", { RMrDX
}, 0 },
2433 { "pushV", { RMrBX
}, 0 },
2434 { "pushV", { RMrSP
}, 0 },
2435 { "pushV", { RMrBP
}, 0 },
2436 { "pushV", { RMrSI
}, 0 },
2437 { "pushV", { RMrDI
}, 0 },
2439 { "popV", { RMrAX
}, 0 },
2440 { "popV", { RMrCX
}, 0 },
2441 { "popV", { RMrDX
}, 0 },
2442 { "popV", { RMrBX
}, 0 },
2443 { "popV", { RMrSP
}, 0 },
2444 { "popV", { RMrBP
}, 0 },
2445 { "popV", { RMrSI
}, 0 },
2446 { "popV", { RMrDI
}, 0 },
2448 { X86_64_TABLE (X86_64_60
) },
2449 { X86_64_TABLE (X86_64_61
) },
2450 { X86_64_TABLE (X86_64_62
) },
2451 { X86_64_TABLE (X86_64_63
) },
2452 { Bad_Opcode
}, /* seg fs */
2453 { Bad_Opcode
}, /* seg gs */
2454 { Bad_Opcode
}, /* op size prefix */
2455 { Bad_Opcode
}, /* adr size prefix */
2457 { "pushT", { sIv
}, 0 },
2458 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2459 { "pushT", { sIbT
}, 0 },
2460 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2461 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2462 { X86_64_TABLE (X86_64_6D
) },
2463 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2464 { X86_64_TABLE (X86_64_6F
) },
2466 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2467 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2468 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2469 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2470 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2471 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2472 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2473 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2475 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2476 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2477 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2478 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2479 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2480 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2481 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2482 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2484 { REG_TABLE (REG_80
) },
2485 { REG_TABLE (REG_81
) },
2486 { X86_64_TABLE (X86_64_82
) },
2487 { REG_TABLE (REG_83
) },
2488 { "testB", { Eb
, Gb
}, 0 },
2489 { "testS", { Ev
, Gv
}, 0 },
2490 { "xchgB", { Ebh2
, Gb
}, 0 },
2491 { "xchgS", { Evh2
, Gv
}, 0 },
2493 { "movB", { Ebh3
, Gb
}, 0 },
2494 { "movS", { Evh3
, Gv
}, 0 },
2495 { "movB", { Gb
, EbS
}, 0 },
2496 { "movS", { Gv
, EvS
}, 0 },
2497 { "movD", { Sv
, Sw
}, 0 },
2498 { MOD_TABLE (MOD_8D
) },
2499 { "movD", { Sw
, Sv
}, 0 },
2500 { REG_TABLE (REG_8F
) },
2502 { PREFIX_TABLE (PREFIX_90
) },
2503 { "xchgS", { RMeCX
, eAX
}, 0 },
2504 { "xchgS", { RMeDX
, eAX
}, 0 },
2505 { "xchgS", { RMeBX
, eAX
}, 0 },
2506 { "xchgS", { RMeSP
, eAX
}, 0 },
2507 { "xchgS", { RMeBP
, eAX
}, 0 },
2508 { "xchgS", { RMeSI
, eAX
}, 0 },
2509 { "xchgS", { RMeDI
, eAX
}, 0 },
2511 { "cW{t|}R", { XX
}, 0 },
2512 { "cR{t|}O", { XX
}, 0 },
2513 { X86_64_TABLE (X86_64_9A
) },
2514 { Bad_Opcode
}, /* fwait */
2515 { "pushfT", { XX
}, 0 },
2516 { "popfT", { XX
}, 0 },
2517 { "sahf", { XX
}, 0 },
2518 { "lahf", { XX
}, 0 },
2520 { "mov%LB", { AL
, Ob
}, 0 },
2521 { "mov%LS", { eAX
, Ov
}, 0 },
2522 { "mov%LB", { Ob
, AL
}, 0 },
2523 { "mov%LS", { Ov
, eAX
}, 0 },
2524 { "movs{b|}", { Ybr
, Xb
}, 0 },
2525 { "movs{R|}", { Yvr
, Xv
}, 0 },
2526 { "cmps{b|}", { Xb
, Yb
}, 0 },
2527 { "cmps{R|}", { Xv
, Yv
}, 0 },
2529 { "testB", { AL
, Ib
}, 0 },
2530 { "testS", { eAX
, Iv
}, 0 },
2531 { "stosB", { Ybr
, AL
}, 0 },
2532 { "stosS", { Yvr
, eAX
}, 0 },
2533 { "lodsB", { ALr
, Xb
}, 0 },
2534 { "lodsS", { eAXr
, Xv
}, 0 },
2535 { "scasB", { AL
, Yb
}, 0 },
2536 { "scasS", { eAX
, Yv
}, 0 },
2538 { "movB", { RMAL
, Ib
}, 0 },
2539 { "movB", { RMCL
, Ib
}, 0 },
2540 { "movB", { RMDL
, Ib
}, 0 },
2541 { "movB", { RMBL
, Ib
}, 0 },
2542 { "movB", { RMAH
, Ib
}, 0 },
2543 { "movB", { RMCH
, Ib
}, 0 },
2544 { "movB", { RMDH
, Ib
}, 0 },
2545 { "movB", { RMBH
, Ib
}, 0 },
2547 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2548 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2549 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2550 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2551 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2552 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2553 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2554 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2556 { REG_TABLE (REG_C0
) },
2557 { REG_TABLE (REG_C1
) },
2558 { "retT", { Iw
, BND
}, 0 },
2559 { "retT", { BND
}, 0 },
2560 { X86_64_TABLE (X86_64_C4
) },
2561 { X86_64_TABLE (X86_64_C5
) },
2562 { REG_TABLE (REG_C6
) },
2563 { REG_TABLE (REG_C7
) },
2565 { "enterT", { Iw
, Ib
}, 0 },
2566 { "leaveT", { XX
}, 0 },
2567 { "Jret{|f}P", { Iw
}, 0 },
2568 { "Jret{|f}P", { XX
}, 0 },
2569 { "int3", { XX
}, 0 },
2570 { "int", { Ib
}, 0 },
2571 { X86_64_TABLE (X86_64_CE
) },
2572 { "iret%LP", { XX
}, 0 },
2574 { REG_TABLE (REG_D0
) },
2575 { REG_TABLE (REG_D1
) },
2576 { REG_TABLE (REG_D2
) },
2577 { REG_TABLE (REG_D3
) },
2578 { X86_64_TABLE (X86_64_D4
) },
2579 { X86_64_TABLE (X86_64_D5
) },
2581 { "xlat", { DSBX
}, 0 },
2592 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2593 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2594 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2595 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2596 { "inB", { AL
, Ib
}, 0 },
2597 { "inG", { zAX
, Ib
}, 0 },
2598 { "outB", { Ib
, AL
}, 0 },
2599 { "outG", { Ib
, zAX
}, 0 },
2601 { X86_64_TABLE (X86_64_E8
) },
2602 { X86_64_TABLE (X86_64_E9
) },
2603 { X86_64_TABLE (X86_64_EA
) },
2604 { "jmp", { Jb
, BND
}, 0 },
2605 { "inB", { AL
, indirDX
}, 0 },
2606 { "inG", { zAX
, indirDX
}, 0 },
2607 { "outB", { indirDX
, AL
}, 0 },
2608 { "outG", { indirDX
, zAX
}, 0 },
2610 { Bad_Opcode
}, /* lock prefix */
2611 { "icebp", { XX
}, 0 },
2612 { Bad_Opcode
}, /* repne */
2613 { Bad_Opcode
}, /* repz */
2614 { "hlt", { XX
}, 0 },
2615 { "cmc", { XX
}, 0 },
2616 { REG_TABLE (REG_F6
) },
2617 { REG_TABLE (REG_F7
) },
2619 { "clc", { XX
}, 0 },
2620 { "stc", { XX
}, 0 },
2621 { "cli", { XX
}, 0 },
2622 { "sti", { XX
}, 0 },
2623 { "cld", { XX
}, 0 },
2624 { "std", { XX
}, 0 },
2625 { REG_TABLE (REG_FE
) },
2626 { REG_TABLE (REG_FF
) },
2629 static const struct dis386 dis386_twobyte
[] = {
2631 { REG_TABLE (REG_0F00
) },
2632 { REG_TABLE (REG_0F01
) },
2633 { "larS", { Gv
, Ew
}, 0 },
2634 { "lslS", { Gv
, Ew
}, 0 },
2636 { "syscall", { XX
}, 0 },
2637 { "clts", { XX
}, 0 },
2638 { "sysret%LP", { XX
}, 0 },
2640 { "invd", { XX
}, 0 },
2641 { PREFIX_TABLE (PREFIX_0F09
) },
2643 { "ud2", { XX
}, 0 },
2645 { REG_TABLE (REG_0F0D
) },
2646 { "femms", { XX
}, 0 },
2647 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2649 { PREFIX_TABLE (PREFIX_0F10
) },
2650 { PREFIX_TABLE (PREFIX_0F11
) },
2651 { PREFIX_TABLE (PREFIX_0F12
) },
2652 { MOD_TABLE (MOD_0F13
) },
2653 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2654 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2655 { PREFIX_TABLE (PREFIX_0F16
) },
2656 { MOD_TABLE (MOD_0F17
) },
2658 { REG_TABLE (REG_0F18
) },
2659 { "nopQ", { Ev
}, 0 },
2660 { PREFIX_TABLE (PREFIX_0F1A
) },
2661 { PREFIX_TABLE (PREFIX_0F1B
) },
2662 { PREFIX_TABLE (PREFIX_0F1C
) },
2663 { "nopQ", { Ev
}, 0 },
2664 { PREFIX_TABLE (PREFIX_0F1E
) },
2665 { "nopQ", { Ev
}, 0 },
2667 { "movZ", { Rm
, Cm
}, 0 },
2668 { "movZ", { Rm
, Dm
}, 0 },
2669 { "movZ", { Cm
, Rm
}, 0 },
2670 { "movZ", { Dm
, Rm
}, 0 },
2671 { MOD_TABLE (MOD_0F24
) },
2673 { MOD_TABLE (MOD_0F26
) },
2676 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2677 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2678 { PREFIX_TABLE (PREFIX_0F2A
) },
2679 { PREFIX_TABLE (PREFIX_0F2B
) },
2680 { PREFIX_TABLE (PREFIX_0F2C
) },
2681 { PREFIX_TABLE (PREFIX_0F2D
) },
2682 { PREFIX_TABLE (PREFIX_0F2E
) },
2683 { PREFIX_TABLE (PREFIX_0F2F
) },
2685 { "wrmsr", { XX
}, 0 },
2686 { "rdtsc", { XX
}, 0 },
2687 { "rdmsr", { XX
}, 0 },
2688 { "rdpmc", { XX
}, 0 },
2689 { "sysenter", { XX
}, 0 },
2690 { "sysexit", { XX
}, 0 },
2692 { "getsec", { XX
}, 0 },
2694 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2696 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2703 { "cmovoS", { Gv
, Ev
}, 0 },
2704 { "cmovnoS", { Gv
, Ev
}, 0 },
2705 { "cmovbS", { Gv
, Ev
}, 0 },
2706 { "cmovaeS", { Gv
, Ev
}, 0 },
2707 { "cmoveS", { Gv
, Ev
}, 0 },
2708 { "cmovneS", { Gv
, Ev
}, 0 },
2709 { "cmovbeS", { Gv
, Ev
}, 0 },
2710 { "cmovaS", { Gv
, Ev
}, 0 },
2712 { "cmovsS", { Gv
, Ev
}, 0 },
2713 { "cmovnsS", { Gv
, Ev
}, 0 },
2714 { "cmovpS", { Gv
, Ev
}, 0 },
2715 { "cmovnpS", { Gv
, Ev
}, 0 },
2716 { "cmovlS", { Gv
, Ev
}, 0 },
2717 { "cmovgeS", { Gv
, Ev
}, 0 },
2718 { "cmovleS", { Gv
, Ev
}, 0 },
2719 { "cmovgS", { Gv
, Ev
}, 0 },
2721 { MOD_TABLE (MOD_0F51
) },
2722 { PREFIX_TABLE (PREFIX_0F51
) },
2723 { PREFIX_TABLE (PREFIX_0F52
) },
2724 { PREFIX_TABLE (PREFIX_0F53
) },
2725 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2726 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2727 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2728 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2730 { PREFIX_TABLE (PREFIX_0F58
) },
2731 { PREFIX_TABLE (PREFIX_0F59
) },
2732 { PREFIX_TABLE (PREFIX_0F5A
) },
2733 { PREFIX_TABLE (PREFIX_0F5B
) },
2734 { PREFIX_TABLE (PREFIX_0F5C
) },
2735 { PREFIX_TABLE (PREFIX_0F5D
) },
2736 { PREFIX_TABLE (PREFIX_0F5E
) },
2737 { PREFIX_TABLE (PREFIX_0F5F
) },
2739 { PREFIX_TABLE (PREFIX_0F60
) },
2740 { PREFIX_TABLE (PREFIX_0F61
) },
2741 { PREFIX_TABLE (PREFIX_0F62
) },
2742 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2743 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2744 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2745 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2746 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2748 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2749 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2750 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2751 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2752 { PREFIX_TABLE (PREFIX_0F6C
) },
2753 { PREFIX_TABLE (PREFIX_0F6D
) },
2754 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2755 { PREFIX_TABLE (PREFIX_0F6F
) },
2757 { PREFIX_TABLE (PREFIX_0F70
) },
2758 { REG_TABLE (REG_0F71
) },
2759 { REG_TABLE (REG_0F72
) },
2760 { REG_TABLE (REG_0F73
) },
2761 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2762 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2763 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2764 { "emms", { XX
}, PREFIX_OPCODE
},
2766 { PREFIX_TABLE (PREFIX_0F78
) },
2767 { PREFIX_TABLE (PREFIX_0F79
) },
2770 { PREFIX_TABLE (PREFIX_0F7C
) },
2771 { PREFIX_TABLE (PREFIX_0F7D
) },
2772 { PREFIX_TABLE (PREFIX_0F7E
) },
2773 { PREFIX_TABLE (PREFIX_0F7F
) },
2775 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2776 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2777 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2778 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2779 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2780 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2781 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2782 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2784 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2785 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2786 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2787 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2788 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2789 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2790 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2791 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2793 { "seto", { Eb
}, 0 },
2794 { "setno", { Eb
}, 0 },
2795 { "setb", { Eb
}, 0 },
2796 { "setae", { Eb
}, 0 },
2797 { "sete", { Eb
}, 0 },
2798 { "setne", { Eb
}, 0 },
2799 { "setbe", { Eb
}, 0 },
2800 { "seta", { Eb
}, 0 },
2802 { "sets", { Eb
}, 0 },
2803 { "setns", { Eb
}, 0 },
2804 { "setp", { Eb
}, 0 },
2805 { "setnp", { Eb
}, 0 },
2806 { "setl", { Eb
}, 0 },
2807 { "setge", { Eb
}, 0 },
2808 { "setle", { Eb
}, 0 },
2809 { "setg", { Eb
}, 0 },
2811 { "pushT", { fs
}, 0 },
2812 { "popT", { fs
}, 0 },
2813 { "cpuid", { XX
}, 0 },
2814 { "btS", { Ev
, Gv
}, 0 },
2815 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2816 { "shldS", { Ev
, Gv
, CL
}, 0 },
2817 { REG_TABLE (REG_0FA6
) },
2818 { REG_TABLE (REG_0FA7
) },
2820 { "pushT", { gs
}, 0 },
2821 { "popT", { gs
}, 0 },
2822 { "rsm", { XX
}, 0 },
2823 { "btsS", { Evh1
, Gv
}, 0 },
2824 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2825 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2826 { REG_TABLE (REG_0FAE
) },
2827 { "imulS", { Gv
, Ev
}, 0 },
2829 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2830 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2831 { MOD_TABLE (MOD_0FB2
) },
2832 { "btrS", { Evh1
, Gv
}, 0 },
2833 { MOD_TABLE (MOD_0FB4
) },
2834 { MOD_TABLE (MOD_0FB5
) },
2835 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2836 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2838 { PREFIX_TABLE (PREFIX_0FB8
) },
2839 { "ud1S", { Gv
, Ev
}, 0 },
2840 { REG_TABLE (REG_0FBA
) },
2841 { "btcS", { Evh1
, Gv
}, 0 },
2842 { PREFIX_TABLE (PREFIX_0FBC
) },
2843 { PREFIX_TABLE (PREFIX_0FBD
) },
2844 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2845 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2847 { "xaddB", { Ebh1
, Gb
}, 0 },
2848 { "xaddS", { Evh1
, Gv
}, 0 },
2849 { PREFIX_TABLE (PREFIX_0FC2
) },
2850 { MOD_TABLE (MOD_0FC3
) },
2851 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2852 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2853 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2854 { REG_TABLE (REG_0FC7
) },
2856 { "bswap", { RMeAX
}, 0 },
2857 { "bswap", { RMeCX
}, 0 },
2858 { "bswap", { RMeDX
}, 0 },
2859 { "bswap", { RMeBX
}, 0 },
2860 { "bswap", { RMeSP
}, 0 },
2861 { "bswap", { RMeBP
}, 0 },
2862 { "bswap", { RMeSI
}, 0 },
2863 { "bswap", { RMeDI
}, 0 },
2865 { PREFIX_TABLE (PREFIX_0FD0
) },
2866 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2867 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2868 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2869 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2870 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2871 { PREFIX_TABLE (PREFIX_0FD6
) },
2872 { MOD_TABLE (MOD_0FD7
) },
2874 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2875 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2876 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2877 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2878 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2879 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2880 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2881 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2883 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2884 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2885 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2886 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2887 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2888 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2889 { PREFIX_TABLE (PREFIX_0FE6
) },
2890 { PREFIX_TABLE (PREFIX_0FE7
) },
2892 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2893 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2894 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2895 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2896 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2897 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2898 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2899 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2901 { PREFIX_TABLE (PREFIX_0FF0
) },
2902 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2903 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2904 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2905 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2906 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2907 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2908 { PREFIX_TABLE (PREFIX_0FF7
) },
2910 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2911 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2913 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2915 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2916 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2917 { "ud0S", { Gv
, Ev
}, 0 },
2920 static const unsigned char onebyte_has_modrm
[256] = {
2921 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2922 /* ------------------------------- */
2923 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2924 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2925 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2926 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2927 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2928 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2929 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2930 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2931 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2932 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2933 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2934 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2935 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2936 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2937 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2938 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2939 /* ------------------------------- */
2940 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2943 static const unsigned char twobyte_has_modrm
[256] = {
2944 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2945 /* ------------------------------- */
2946 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2947 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2948 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2949 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2950 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2951 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2952 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2953 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2954 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2955 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2956 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2957 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2958 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2959 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2960 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2961 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2962 /* ------------------------------- */
2963 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2966 static char obuf
[100];
2968 static char *mnemonicendp
;
2969 static char scratchbuf
[100];
2970 static unsigned char *start_codep
;
2971 static unsigned char *insn_codep
;
2972 static unsigned char *codep
;
2973 static unsigned char *end_codep
;
2974 static int last_lock_prefix
;
2975 static int last_repz_prefix
;
2976 static int last_repnz_prefix
;
2977 static int last_data_prefix
;
2978 static int last_addr_prefix
;
2979 static int last_rex_prefix
;
2980 static int last_seg_prefix
;
2981 static int fwait_prefix
;
2982 /* The active segment register prefix. */
2983 static int active_seg_prefix
;
2984 #define MAX_CODE_LENGTH 15
2985 /* We can up to 14 prefixes since the maximum instruction length is
2987 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2988 static disassemble_info
*the_info
;
2996 static unsigned char need_modrm
;
3006 int register_specifier
;
3013 int mask_register_specifier
;
3019 static unsigned char need_vex
;
3020 static unsigned char need_vex_reg
;
3021 static unsigned char vex_w_done
;
3029 /* If we are accessing mod/rm/reg without need_modrm set, then the
3030 values are stale. Hitting this abort likely indicates that you
3031 need to update onebyte_has_modrm or twobyte_has_modrm. */
3032 #define MODRM_CHECK if (!need_modrm) abort ()
3034 static const char **names64
;
3035 static const char **names32
;
3036 static const char **names16
;
3037 static const char **names8
;
3038 static const char **names8rex
;
3039 static const char **names_seg
;
3040 static const char *index64
;
3041 static const char *index32
;
3042 static const char **index16
;
3043 static const char **names_bnd
;
3045 static const char *intel_names64
[] = {
3046 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3047 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3049 static const char *intel_names32
[] = {
3050 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3051 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3053 static const char *intel_names16
[] = {
3054 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3055 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3057 static const char *intel_names8
[] = {
3058 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3060 static const char *intel_names8rex
[] = {
3061 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3062 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3064 static const char *intel_names_seg
[] = {
3065 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3067 static const char *intel_index64
= "riz";
3068 static const char *intel_index32
= "eiz";
3069 static const char *intel_index16
[] = {
3070 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3073 static const char *att_names64
[] = {
3074 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3075 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3077 static const char *att_names32
[] = {
3078 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3079 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3081 static const char *att_names16
[] = {
3082 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3083 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3085 static const char *att_names8
[] = {
3086 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3088 static const char *att_names8rex
[] = {
3089 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3090 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3092 static const char *att_names_seg
[] = {
3093 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3095 static const char *att_index64
= "%riz";
3096 static const char *att_index32
= "%eiz";
3097 static const char *att_index16
[] = {
3098 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3101 static const char **names_mm
;
3102 static const char *intel_names_mm
[] = {
3103 "mm0", "mm1", "mm2", "mm3",
3104 "mm4", "mm5", "mm6", "mm7"
3106 static const char *att_names_mm
[] = {
3107 "%mm0", "%mm1", "%mm2", "%mm3",
3108 "%mm4", "%mm5", "%mm6", "%mm7"
3111 static const char *intel_names_bnd
[] = {
3112 "bnd0", "bnd1", "bnd2", "bnd3"
3115 static const char *att_names_bnd
[] = {
3116 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3119 static const char **names_xmm
;
3120 static const char *intel_names_xmm
[] = {
3121 "xmm0", "xmm1", "xmm2", "xmm3",
3122 "xmm4", "xmm5", "xmm6", "xmm7",
3123 "xmm8", "xmm9", "xmm10", "xmm11",
3124 "xmm12", "xmm13", "xmm14", "xmm15",
3125 "xmm16", "xmm17", "xmm18", "xmm19",
3126 "xmm20", "xmm21", "xmm22", "xmm23",
3127 "xmm24", "xmm25", "xmm26", "xmm27",
3128 "xmm28", "xmm29", "xmm30", "xmm31"
3130 static const char *att_names_xmm
[] = {
3131 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3132 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3133 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3134 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3135 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3136 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3137 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3138 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3141 static const char **names_ymm
;
3142 static const char *intel_names_ymm
[] = {
3143 "ymm0", "ymm1", "ymm2", "ymm3",
3144 "ymm4", "ymm5", "ymm6", "ymm7",
3145 "ymm8", "ymm9", "ymm10", "ymm11",
3146 "ymm12", "ymm13", "ymm14", "ymm15",
3147 "ymm16", "ymm17", "ymm18", "ymm19",
3148 "ymm20", "ymm21", "ymm22", "ymm23",
3149 "ymm24", "ymm25", "ymm26", "ymm27",
3150 "ymm28", "ymm29", "ymm30", "ymm31"
3152 static const char *att_names_ymm
[] = {
3153 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3154 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3155 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3156 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3157 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3158 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3159 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3160 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3163 static const char **names_zmm
;
3164 static const char *intel_names_zmm
[] = {
3165 "zmm0", "zmm1", "zmm2", "zmm3",
3166 "zmm4", "zmm5", "zmm6", "zmm7",
3167 "zmm8", "zmm9", "zmm10", "zmm11",
3168 "zmm12", "zmm13", "zmm14", "zmm15",
3169 "zmm16", "zmm17", "zmm18", "zmm19",
3170 "zmm20", "zmm21", "zmm22", "zmm23",
3171 "zmm24", "zmm25", "zmm26", "zmm27",
3172 "zmm28", "zmm29", "zmm30", "zmm31"
3174 static const char *att_names_zmm
[] = {
3175 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3176 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3177 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3178 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3179 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3180 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3181 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3182 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3185 static const char **names_mask
;
3186 static const char *intel_names_mask
[] = {
3187 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3189 static const char *att_names_mask
[] = {
3190 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3193 static const char *names_rounding
[] =
3201 static const struct dis386 reg_table
[][8] = {
3204 { "addA", { Ebh1
, Ib
}, 0 },
3205 { "orA", { Ebh1
, Ib
}, 0 },
3206 { "adcA", { Ebh1
, Ib
}, 0 },
3207 { "sbbA", { Ebh1
, Ib
}, 0 },
3208 { "andA", { Ebh1
, Ib
}, 0 },
3209 { "subA", { Ebh1
, Ib
}, 0 },
3210 { "xorA", { Ebh1
, Ib
}, 0 },
3211 { "cmpA", { Eb
, Ib
}, 0 },
3215 { "addQ", { Evh1
, Iv
}, 0 },
3216 { "orQ", { Evh1
, Iv
}, 0 },
3217 { "adcQ", { Evh1
, Iv
}, 0 },
3218 { "sbbQ", { Evh1
, Iv
}, 0 },
3219 { "andQ", { Evh1
, Iv
}, 0 },
3220 { "subQ", { Evh1
, Iv
}, 0 },
3221 { "xorQ", { Evh1
, Iv
}, 0 },
3222 { "cmpQ", { Ev
, Iv
}, 0 },
3226 { "addQ", { Evh1
, sIb
}, 0 },
3227 { "orQ", { Evh1
, sIb
}, 0 },
3228 { "adcQ", { Evh1
, sIb
}, 0 },
3229 { "sbbQ", { Evh1
, sIb
}, 0 },
3230 { "andQ", { Evh1
, sIb
}, 0 },
3231 { "subQ", { Evh1
, sIb
}, 0 },
3232 { "xorQ", { Evh1
, sIb
}, 0 },
3233 { "cmpQ", { Ev
, sIb
}, 0 },
3237 { "popU", { stackEv
}, 0 },
3238 { XOP_8F_TABLE (XOP_09
) },
3242 { XOP_8F_TABLE (XOP_09
) },
3246 { "rolA", { Eb
, Ib
}, 0 },
3247 { "rorA", { Eb
, Ib
}, 0 },
3248 { "rclA", { Eb
, Ib
}, 0 },
3249 { "rcrA", { Eb
, Ib
}, 0 },
3250 { "shlA", { Eb
, Ib
}, 0 },
3251 { "shrA", { Eb
, Ib
}, 0 },
3252 { "shlA", { Eb
, Ib
}, 0 },
3253 { "sarA", { Eb
, Ib
}, 0 },
3257 { "rolQ", { Ev
, Ib
}, 0 },
3258 { "rorQ", { Ev
, Ib
}, 0 },
3259 { "rclQ", { Ev
, Ib
}, 0 },
3260 { "rcrQ", { Ev
, Ib
}, 0 },
3261 { "shlQ", { Ev
, Ib
}, 0 },
3262 { "shrQ", { Ev
, Ib
}, 0 },
3263 { "shlQ", { Ev
, Ib
}, 0 },
3264 { "sarQ", { Ev
, Ib
}, 0 },
3268 { "movA", { Ebh3
, Ib
}, 0 },
3275 { MOD_TABLE (MOD_C6_REG_7
) },
3279 { "movQ", { Evh3
, Iv
}, 0 },
3286 { MOD_TABLE (MOD_C7_REG_7
) },
3290 { "rolA", { Eb
, I1
}, 0 },
3291 { "rorA", { Eb
, I1
}, 0 },
3292 { "rclA", { Eb
, I1
}, 0 },
3293 { "rcrA", { Eb
, I1
}, 0 },
3294 { "shlA", { Eb
, I1
}, 0 },
3295 { "shrA", { Eb
, I1
}, 0 },
3296 { "shlA", { Eb
, I1
}, 0 },
3297 { "sarA", { Eb
, I1
}, 0 },
3301 { "rolQ", { Ev
, I1
}, 0 },
3302 { "rorQ", { Ev
, I1
}, 0 },
3303 { "rclQ", { Ev
, I1
}, 0 },
3304 { "rcrQ", { Ev
, I1
}, 0 },
3305 { "shlQ", { Ev
, I1
}, 0 },
3306 { "shrQ", { Ev
, I1
}, 0 },
3307 { "shlQ", { Ev
, I1
}, 0 },
3308 { "sarQ", { Ev
, I1
}, 0 },
3312 { "rolA", { Eb
, CL
}, 0 },
3313 { "rorA", { Eb
, CL
}, 0 },
3314 { "rclA", { Eb
, CL
}, 0 },
3315 { "rcrA", { Eb
, CL
}, 0 },
3316 { "shlA", { Eb
, CL
}, 0 },
3317 { "shrA", { Eb
, CL
}, 0 },
3318 { "shlA", { Eb
, CL
}, 0 },
3319 { "sarA", { Eb
, CL
}, 0 },
3323 { "rolQ", { Ev
, CL
}, 0 },
3324 { "rorQ", { Ev
, CL
}, 0 },
3325 { "rclQ", { Ev
, CL
}, 0 },
3326 { "rcrQ", { Ev
, CL
}, 0 },
3327 { "shlQ", { Ev
, CL
}, 0 },
3328 { "shrQ", { Ev
, CL
}, 0 },
3329 { "shlQ", { Ev
, CL
}, 0 },
3330 { "sarQ", { Ev
, CL
}, 0 },
3334 { "testA", { Eb
, Ib
}, 0 },
3335 { "testA", { Eb
, Ib
}, 0 },
3336 { "notA", { Ebh1
}, 0 },
3337 { "negA", { Ebh1
}, 0 },
3338 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3339 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3340 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3341 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3345 { "testQ", { Ev
, Iv
}, 0 },
3346 { "testQ", { Ev
, Iv
}, 0 },
3347 { "notQ", { Evh1
}, 0 },
3348 { "negQ", { Evh1
}, 0 },
3349 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3350 { "imulQ", { Ev
}, 0 },
3351 { "divQ", { Ev
}, 0 },
3352 { "idivQ", { Ev
}, 0 },
3356 { "incA", { Ebh1
}, 0 },
3357 { "decA", { Ebh1
}, 0 },
3361 { "incQ", { Evh1
}, 0 },
3362 { "decQ", { Evh1
}, 0 },
3363 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3364 { MOD_TABLE (MOD_FF_REG_3
) },
3365 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3366 { MOD_TABLE (MOD_FF_REG_5
) },
3367 { "pushU", { stackEv
}, 0 },
3372 { "sldtD", { Sv
}, 0 },
3373 { "strD", { Sv
}, 0 },
3374 { "lldt", { Ew
}, 0 },
3375 { "ltr", { Ew
}, 0 },
3376 { "verr", { Ew
}, 0 },
3377 { "verw", { Ew
}, 0 },
3383 { MOD_TABLE (MOD_0F01_REG_0
) },
3384 { MOD_TABLE (MOD_0F01_REG_1
) },
3385 { MOD_TABLE (MOD_0F01_REG_2
) },
3386 { MOD_TABLE (MOD_0F01_REG_3
) },
3387 { "smswD", { Sv
}, 0 },
3388 { MOD_TABLE (MOD_0F01_REG_5
) },
3389 { "lmsw", { Ew
}, 0 },
3390 { MOD_TABLE (MOD_0F01_REG_7
) },
3394 { "prefetch", { Mb
}, 0 },
3395 { "prefetchw", { Mb
}, 0 },
3396 { "prefetchwt1", { Mb
}, 0 },
3397 { "prefetch", { Mb
}, 0 },
3398 { "prefetch", { Mb
}, 0 },
3399 { "prefetch", { Mb
}, 0 },
3400 { "prefetch", { Mb
}, 0 },
3401 { "prefetch", { Mb
}, 0 },
3405 { MOD_TABLE (MOD_0F18_REG_0
) },
3406 { MOD_TABLE (MOD_0F18_REG_1
) },
3407 { MOD_TABLE (MOD_0F18_REG_2
) },
3408 { MOD_TABLE (MOD_0F18_REG_3
) },
3409 { MOD_TABLE (MOD_0F18_REG_4
) },
3410 { MOD_TABLE (MOD_0F18_REG_5
) },
3411 { MOD_TABLE (MOD_0F18_REG_6
) },
3412 { MOD_TABLE (MOD_0F18_REG_7
) },
3414 /* REG_0F1C_MOD_0 */
3416 { "cldemote", { Mb
}, 0 },
3417 { "nopQ", { Ev
}, 0 },
3418 { "nopQ", { Ev
}, 0 },
3419 { "nopQ", { Ev
}, 0 },
3420 { "nopQ", { Ev
}, 0 },
3421 { "nopQ", { Ev
}, 0 },
3422 { "nopQ", { Ev
}, 0 },
3423 { "nopQ", { Ev
}, 0 },
3425 /* REG_0F1E_MOD_3 */
3427 { "nopQ", { Ev
}, 0 },
3428 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3429 { "nopQ", { Ev
}, 0 },
3430 { "nopQ", { Ev
}, 0 },
3431 { "nopQ", { Ev
}, 0 },
3432 { "nopQ", { Ev
}, 0 },
3433 { "nopQ", { Ev
}, 0 },
3434 { RM_TABLE (RM_0F1E_MOD_3_REG_7
) },
3440 { MOD_TABLE (MOD_0F71_REG_2
) },
3442 { MOD_TABLE (MOD_0F71_REG_4
) },
3444 { MOD_TABLE (MOD_0F71_REG_6
) },
3450 { MOD_TABLE (MOD_0F72_REG_2
) },
3452 { MOD_TABLE (MOD_0F72_REG_4
) },
3454 { MOD_TABLE (MOD_0F72_REG_6
) },
3460 { MOD_TABLE (MOD_0F73_REG_2
) },
3461 { MOD_TABLE (MOD_0F73_REG_3
) },
3464 { MOD_TABLE (MOD_0F73_REG_6
) },
3465 { MOD_TABLE (MOD_0F73_REG_7
) },
3469 { "montmul", { { OP_0f07
, 0 } }, 0 },
3470 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3471 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3475 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3476 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3477 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3478 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3479 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3480 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3484 { MOD_TABLE (MOD_0FAE_REG_0
) },
3485 { MOD_TABLE (MOD_0FAE_REG_1
) },
3486 { MOD_TABLE (MOD_0FAE_REG_2
) },
3487 { MOD_TABLE (MOD_0FAE_REG_3
) },
3488 { MOD_TABLE (MOD_0FAE_REG_4
) },
3489 { MOD_TABLE (MOD_0FAE_REG_5
) },
3490 { MOD_TABLE (MOD_0FAE_REG_6
) },
3491 { MOD_TABLE (MOD_0FAE_REG_7
) },
3499 { "btQ", { Ev
, Ib
}, 0 },
3500 { "btsQ", { Evh1
, Ib
}, 0 },
3501 { "btrQ", { Evh1
, Ib
}, 0 },
3502 { "btcQ", { Evh1
, Ib
}, 0 },
3507 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3509 { MOD_TABLE (MOD_0FC7_REG_3
) },
3510 { MOD_TABLE (MOD_0FC7_REG_4
) },
3511 { MOD_TABLE (MOD_0FC7_REG_5
) },
3512 { MOD_TABLE (MOD_0FC7_REG_6
) },
3513 { MOD_TABLE (MOD_0FC7_REG_7
) },
3519 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3521 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3523 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3529 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3531 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3533 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3539 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3540 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3543 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3544 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3550 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3551 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3553 /* REG_VEX_0F38F3 */
3556 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3557 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3558 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3562 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3563 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3567 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3568 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3570 /* REG_XOP_TBM_01 */
3573 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3574 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3575 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3576 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3577 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3578 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3579 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3581 /* REG_XOP_TBM_02 */
3584 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3589 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3591 #define NEED_REG_TABLE
3592 #include "i386-dis-evex.h"
3593 #undef NEED_REG_TABLE
3596 static const struct dis386 prefix_table
[][4] = {
3599 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3600 { "pause", { XX
}, 0 },
3601 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3602 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3605 /* PREFIX_MOD_0_0F01_REG_5 */
3608 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3611 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3614 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3617 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3620 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3625 { "wbinvd", { XX
}, 0 },
3626 { "wbnoinvd", { XX
}, 0 },
3631 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3632 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3633 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3634 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3639 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3640 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3641 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3642 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3647 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3648 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3649 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3650 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3655 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3656 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3657 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3662 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3663 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3664 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3665 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3670 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3671 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3672 { "bndmov", { EbndS
, Gbnd
}, 0 },
3673 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3678 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3679 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3680 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3681 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3686 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3687 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3688 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3689 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3694 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3695 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3696 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3697 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3702 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3703 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3704 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3705 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3710 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3711 { "cvttss2si", { Gv
, EXd
}, PREFIX_OPCODE
},
3712 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3713 { "cvttsd2si", { Gv
, EXq
}, PREFIX_OPCODE
},
3718 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3719 { "cvtss2si", { Gv
, EXd
}, PREFIX_OPCODE
},
3720 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3721 { "cvtsd2si", { Gv
, EXq
}, PREFIX_OPCODE
},
3726 { "ucomiss",{ XM
, EXd
}, 0 },
3728 { "ucomisd",{ XM
, EXq
}, 0 },
3733 { "comiss", { XM
, EXd
}, 0 },
3735 { "comisd", { XM
, EXq
}, 0 },
3740 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3741 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3742 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3743 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3748 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3749 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3754 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3755 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3760 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3761 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3762 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3763 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3768 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3769 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3770 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3771 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3776 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3777 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3778 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3779 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3784 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3785 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3786 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3791 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3792 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3793 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3794 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3799 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3800 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3801 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3802 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3807 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3808 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3809 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3810 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3815 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3816 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3817 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3818 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3823 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3825 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3830 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3832 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3837 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3839 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3846 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3853 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3858 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3859 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3860 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3865 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3866 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3867 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3868 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3871 /* PREFIX_0F73_REG_3 */
3875 { "psrldq", { XS
, Ib
}, 0 },
3878 /* PREFIX_0F73_REG_7 */
3882 { "pslldq", { XS
, Ib
}, 0 },
3887 {"vmread", { Em
, Gm
}, 0 },
3889 {"extrq", { XS
, Ib
, Ib
}, 0 },
3890 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3895 {"vmwrite", { Gm
, Em
}, 0 },
3897 {"extrq", { XM
, XS
}, 0 },
3898 {"insertq", { XM
, XS
}, 0 },
3905 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3906 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3913 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3914 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3919 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3920 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3921 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3926 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3927 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3928 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3931 /* PREFIX_0FAE_REG_0 */
3934 { "rdfsbase", { Ev
}, 0 },
3937 /* PREFIX_0FAE_REG_1 */
3940 { "rdgsbase", { Ev
}, 0 },
3943 /* PREFIX_0FAE_REG_2 */
3946 { "wrfsbase", { Ev
}, 0 },
3949 /* PREFIX_0FAE_REG_3 */
3952 { "wrgsbase", { Ev
}, 0 },
3955 /* PREFIX_MOD_0_0FAE_REG_4 */
3957 { "xsave", { FXSAVE
}, 0 },
3958 { "ptwrite%LQ", { Edq
}, 0 },
3961 /* PREFIX_MOD_3_0FAE_REG_4 */
3964 { "ptwrite%LQ", { Edq
}, 0 },
3967 /* PREFIX_MOD_0_0FAE_REG_5 */
3969 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3972 /* PREFIX_MOD_3_0FAE_REG_5 */
3974 { "lfence", { Skip_MODRM
}, 0 },
3975 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
3978 /* PREFIX_MOD_0_0FAE_REG_6 */
3980 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3981 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3982 { "clwb", { Mb
}, PREFIX_OPCODE
},
3985 /* PREFIX_MOD_1_0FAE_REG_6 */
3987 { RM_TABLE (RM_0FAE_REG_6
) },
3988 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3989 { "tpause", { Edq
}, PREFIX_OPCODE
},
3990 { "umwait", { Edq
}, PREFIX_OPCODE
},
3993 /* PREFIX_0FAE_REG_7 */
3995 { "clflush", { Mb
}, 0 },
3997 { "clflushopt", { Mb
}, 0 },
4003 { "popcntS", { Gv
, Ev
}, 0 },
4008 { "bsfS", { Gv
, Ev
}, 0 },
4009 { "tzcntS", { Gv
, Ev
}, 0 },
4010 { "bsfS", { Gv
, Ev
}, 0 },
4015 { "bsrS", { Gv
, Ev
}, 0 },
4016 { "lzcntS", { Gv
, Ev
}, 0 },
4017 { "bsrS", { Gv
, Ev
}, 0 },
4022 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4023 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4024 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4025 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4028 /* PREFIX_MOD_0_0FC3 */
4030 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4033 /* PREFIX_MOD_0_0FC7_REG_6 */
4035 { "vmptrld",{ Mq
}, 0 },
4036 { "vmxon", { Mq
}, 0 },
4037 { "vmclear",{ Mq
}, 0 },
4040 /* PREFIX_MOD_3_0FC7_REG_6 */
4042 { "rdrand", { Ev
}, 0 },
4044 { "rdrand", { Ev
}, 0 }
4047 /* PREFIX_MOD_3_0FC7_REG_7 */
4049 { "rdseed", { Ev
}, 0 },
4050 { "rdpid", { Em
}, 0 },
4051 { "rdseed", { Ev
}, 0 },
4058 { "addsubpd", { XM
, EXx
}, 0 },
4059 { "addsubps", { XM
, EXx
}, 0 },
4065 { "movq2dq",{ XM
, MS
}, 0 },
4066 { "movq", { EXqS
, XM
}, 0 },
4067 { "movdq2q",{ MX
, XS
}, 0 },
4073 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4074 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4075 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4080 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4082 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4090 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4095 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4097 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4104 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4111 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4118 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4125 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4132 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4139 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4146 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4153 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4160 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4167 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4174 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4181 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4188 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4195 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4202 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4209 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4216 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4223 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4230 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4237 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4244 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4251 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4258 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4265 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4272 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4279 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4286 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4293 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4300 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4307 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4314 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4321 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4328 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4335 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4340 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4345 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4350 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4355 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4360 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4365 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4372 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4379 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4386 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4393 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4400 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4407 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4412 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4414 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4415 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4420 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4422 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4423 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4430 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4435 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4436 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4437 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4445 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4450 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4457 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4464 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4471 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4478 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4485 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4492 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4499 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4506 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4513 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4520 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4527 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4534 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4541 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4548 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4555 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4562 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4569 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4576 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4583 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4590 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4597 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4604 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4609 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4616 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4623 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4630 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4633 /* PREFIX_VEX_0F10 */
4635 { "vmovups", { XM
, EXx
}, 0 },
4636 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4637 { "vmovupd", { XM
, EXx
}, 0 },
4638 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4641 /* PREFIX_VEX_0F11 */
4643 { "vmovups", { EXxS
, XM
}, 0 },
4644 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4645 { "vmovupd", { EXxS
, XM
}, 0 },
4646 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4649 /* PREFIX_VEX_0F12 */
4651 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4652 { "vmovsldup", { XM
, EXx
}, 0 },
4653 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4654 { "vmovddup", { XM
, EXymmq
}, 0 },
4657 /* PREFIX_VEX_0F16 */
4659 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4660 { "vmovshdup", { XM
, EXx
}, 0 },
4661 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4664 /* PREFIX_VEX_0F2A */
4667 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4669 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4672 /* PREFIX_VEX_0F2C */
4675 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4677 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4680 /* PREFIX_VEX_0F2D */
4683 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4685 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4688 /* PREFIX_VEX_0F2E */
4690 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4692 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4695 /* PREFIX_VEX_0F2F */
4697 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4699 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4702 /* PREFIX_VEX_0F41 */
4704 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4706 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4709 /* PREFIX_VEX_0F42 */
4711 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4713 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4716 /* PREFIX_VEX_0F44 */
4718 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4720 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4723 /* PREFIX_VEX_0F45 */
4725 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4727 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4730 /* PREFIX_VEX_0F46 */
4732 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4734 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4737 /* PREFIX_VEX_0F47 */
4739 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4741 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4744 /* PREFIX_VEX_0F4A */
4746 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4748 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4751 /* PREFIX_VEX_0F4B */
4753 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4755 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4758 /* PREFIX_VEX_0F51 */
4760 { "vsqrtps", { XM
, EXx
}, 0 },
4761 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4762 { "vsqrtpd", { XM
, EXx
}, 0 },
4763 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4766 /* PREFIX_VEX_0F52 */
4768 { "vrsqrtps", { XM
, EXx
}, 0 },
4769 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4772 /* PREFIX_VEX_0F53 */
4774 { "vrcpps", { XM
, EXx
}, 0 },
4775 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4778 /* PREFIX_VEX_0F58 */
4780 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4781 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4782 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4783 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4786 /* PREFIX_VEX_0F59 */
4788 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4789 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4790 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4791 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4794 /* PREFIX_VEX_0F5A */
4796 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4797 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4798 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4799 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4802 /* PREFIX_VEX_0F5B */
4804 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4805 { "vcvttps2dq", { XM
, EXx
}, 0 },
4806 { "vcvtps2dq", { XM
, EXx
}, 0 },
4809 /* PREFIX_VEX_0F5C */
4811 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4812 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4813 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4814 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4817 /* PREFIX_VEX_0F5D */
4819 { "vminps", { XM
, Vex
, EXx
}, 0 },
4820 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4821 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4822 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4825 /* PREFIX_VEX_0F5E */
4827 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4828 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4829 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4830 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4833 /* PREFIX_VEX_0F5F */
4835 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4836 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4837 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4838 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4841 /* PREFIX_VEX_0F60 */
4845 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4848 /* PREFIX_VEX_0F61 */
4852 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4855 /* PREFIX_VEX_0F62 */
4859 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4862 /* PREFIX_VEX_0F63 */
4866 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4869 /* PREFIX_VEX_0F64 */
4873 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4876 /* PREFIX_VEX_0F65 */
4880 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4883 /* PREFIX_VEX_0F66 */
4887 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4890 /* PREFIX_VEX_0F67 */
4894 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4897 /* PREFIX_VEX_0F68 */
4901 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4904 /* PREFIX_VEX_0F69 */
4908 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4911 /* PREFIX_VEX_0F6A */
4915 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4918 /* PREFIX_VEX_0F6B */
4922 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4925 /* PREFIX_VEX_0F6C */
4929 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4932 /* PREFIX_VEX_0F6D */
4936 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4939 /* PREFIX_VEX_0F6E */
4943 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4946 /* PREFIX_VEX_0F6F */
4949 { "vmovdqu", { XM
, EXx
}, 0 },
4950 { "vmovdqa", { XM
, EXx
}, 0 },
4953 /* PREFIX_VEX_0F70 */
4956 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4957 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4958 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4961 /* PREFIX_VEX_0F71_REG_2 */
4965 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4968 /* PREFIX_VEX_0F71_REG_4 */
4972 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4975 /* PREFIX_VEX_0F71_REG_6 */
4979 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
4982 /* PREFIX_VEX_0F72_REG_2 */
4986 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
4989 /* PREFIX_VEX_0F72_REG_4 */
4993 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
4996 /* PREFIX_VEX_0F72_REG_6 */
5000 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5003 /* PREFIX_VEX_0F73_REG_2 */
5007 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5010 /* PREFIX_VEX_0F73_REG_3 */
5014 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5017 /* PREFIX_VEX_0F73_REG_6 */
5021 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5024 /* PREFIX_VEX_0F73_REG_7 */
5028 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5031 /* PREFIX_VEX_0F74 */
5035 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5038 /* PREFIX_VEX_0F75 */
5042 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5045 /* PREFIX_VEX_0F76 */
5049 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5052 /* PREFIX_VEX_0F77 */
5054 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5057 /* PREFIX_VEX_0F7C */
5061 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5062 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5065 /* PREFIX_VEX_0F7D */
5069 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5070 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5073 /* PREFIX_VEX_0F7E */
5076 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5077 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5080 /* PREFIX_VEX_0F7F */
5083 { "vmovdqu", { EXxS
, XM
}, 0 },
5084 { "vmovdqa", { EXxS
, XM
}, 0 },
5087 /* PREFIX_VEX_0F90 */
5089 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5091 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5094 /* PREFIX_VEX_0F91 */
5096 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5098 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5101 /* PREFIX_VEX_0F92 */
5103 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5105 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5106 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5109 /* PREFIX_VEX_0F93 */
5111 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5113 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5114 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5117 /* PREFIX_VEX_0F98 */
5119 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5121 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5124 /* PREFIX_VEX_0F99 */
5126 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5128 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5131 /* PREFIX_VEX_0FC2 */
5133 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5134 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5135 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5136 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5139 /* PREFIX_VEX_0FC4 */
5143 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5146 /* PREFIX_VEX_0FC5 */
5150 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5153 /* PREFIX_VEX_0FD0 */
5157 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5158 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5161 /* PREFIX_VEX_0FD1 */
5165 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5168 /* PREFIX_VEX_0FD2 */
5172 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5175 /* PREFIX_VEX_0FD3 */
5179 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5182 /* PREFIX_VEX_0FD4 */
5186 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5189 /* PREFIX_VEX_0FD5 */
5193 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5196 /* PREFIX_VEX_0FD6 */
5200 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5203 /* PREFIX_VEX_0FD7 */
5207 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5210 /* PREFIX_VEX_0FD8 */
5214 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5217 /* PREFIX_VEX_0FD9 */
5221 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5224 /* PREFIX_VEX_0FDA */
5228 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5231 /* PREFIX_VEX_0FDB */
5235 { "vpand", { XM
, Vex
, EXx
}, 0 },
5238 /* PREFIX_VEX_0FDC */
5242 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5245 /* PREFIX_VEX_0FDD */
5249 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5252 /* PREFIX_VEX_0FDE */
5256 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5259 /* PREFIX_VEX_0FDF */
5263 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5266 /* PREFIX_VEX_0FE0 */
5270 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5273 /* PREFIX_VEX_0FE1 */
5277 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5280 /* PREFIX_VEX_0FE2 */
5284 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5287 /* PREFIX_VEX_0FE3 */
5291 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5294 /* PREFIX_VEX_0FE4 */
5298 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5301 /* PREFIX_VEX_0FE5 */
5305 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5308 /* PREFIX_VEX_0FE6 */
5311 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5312 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5313 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5316 /* PREFIX_VEX_0FE7 */
5320 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5323 /* PREFIX_VEX_0FE8 */
5327 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5330 /* PREFIX_VEX_0FE9 */
5334 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5337 /* PREFIX_VEX_0FEA */
5341 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5344 /* PREFIX_VEX_0FEB */
5348 { "vpor", { XM
, Vex
, EXx
}, 0 },
5351 /* PREFIX_VEX_0FEC */
5355 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5358 /* PREFIX_VEX_0FED */
5362 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5365 /* PREFIX_VEX_0FEE */
5369 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5372 /* PREFIX_VEX_0FEF */
5376 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5379 /* PREFIX_VEX_0FF0 */
5384 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5387 /* PREFIX_VEX_0FF1 */
5391 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5394 /* PREFIX_VEX_0FF2 */
5398 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5401 /* PREFIX_VEX_0FF3 */
5405 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5408 /* PREFIX_VEX_0FF4 */
5412 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5415 /* PREFIX_VEX_0FF5 */
5419 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5422 /* PREFIX_VEX_0FF6 */
5426 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5429 /* PREFIX_VEX_0FF7 */
5433 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5436 /* PREFIX_VEX_0FF8 */
5440 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5443 /* PREFIX_VEX_0FF9 */
5447 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5450 /* PREFIX_VEX_0FFA */
5454 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5457 /* PREFIX_VEX_0FFB */
5461 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5464 /* PREFIX_VEX_0FFC */
5468 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5471 /* PREFIX_VEX_0FFD */
5475 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5478 /* PREFIX_VEX_0FFE */
5482 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5485 /* PREFIX_VEX_0F3800 */
5489 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5492 /* PREFIX_VEX_0F3801 */
5496 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5499 /* PREFIX_VEX_0F3802 */
5503 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5506 /* PREFIX_VEX_0F3803 */
5510 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5513 /* PREFIX_VEX_0F3804 */
5517 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5520 /* PREFIX_VEX_0F3805 */
5524 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5527 /* PREFIX_VEX_0F3806 */
5531 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5534 /* PREFIX_VEX_0F3807 */
5538 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5541 /* PREFIX_VEX_0F3808 */
5545 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5548 /* PREFIX_VEX_0F3809 */
5552 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5555 /* PREFIX_VEX_0F380A */
5559 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5562 /* PREFIX_VEX_0F380B */
5566 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5569 /* PREFIX_VEX_0F380C */
5573 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5576 /* PREFIX_VEX_0F380D */
5580 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5583 /* PREFIX_VEX_0F380E */
5587 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5590 /* PREFIX_VEX_0F380F */
5594 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5597 /* PREFIX_VEX_0F3813 */
5601 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5604 /* PREFIX_VEX_0F3816 */
5608 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5611 /* PREFIX_VEX_0F3817 */
5615 { "vptest", { XM
, EXx
}, 0 },
5618 /* PREFIX_VEX_0F3818 */
5622 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5625 /* PREFIX_VEX_0F3819 */
5629 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5632 /* PREFIX_VEX_0F381A */
5636 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5639 /* PREFIX_VEX_0F381C */
5643 { "vpabsb", { XM
, EXx
}, 0 },
5646 /* PREFIX_VEX_0F381D */
5650 { "vpabsw", { XM
, EXx
}, 0 },
5653 /* PREFIX_VEX_0F381E */
5657 { "vpabsd", { XM
, EXx
}, 0 },
5660 /* PREFIX_VEX_0F3820 */
5664 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5667 /* PREFIX_VEX_0F3821 */
5671 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5674 /* PREFIX_VEX_0F3822 */
5678 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5681 /* PREFIX_VEX_0F3823 */
5685 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5688 /* PREFIX_VEX_0F3824 */
5692 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5695 /* PREFIX_VEX_0F3825 */
5699 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5702 /* PREFIX_VEX_0F3828 */
5706 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5709 /* PREFIX_VEX_0F3829 */
5713 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5716 /* PREFIX_VEX_0F382A */
5720 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5723 /* PREFIX_VEX_0F382B */
5727 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5730 /* PREFIX_VEX_0F382C */
5734 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5737 /* PREFIX_VEX_0F382D */
5741 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5744 /* PREFIX_VEX_0F382E */
5748 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5751 /* PREFIX_VEX_0F382F */
5755 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5758 /* PREFIX_VEX_0F3830 */
5762 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5765 /* PREFIX_VEX_0F3831 */
5769 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5772 /* PREFIX_VEX_0F3832 */
5776 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5779 /* PREFIX_VEX_0F3833 */
5783 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5786 /* PREFIX_VEX_0F3834 */
5790 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5793 /* PREFIX_VEX_0F3835 */
5797 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5800 /* PREFIX_VEX_0F3836 */
5804 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5807 /* PREFIX_VEX_0F3837 */
5811 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5814 /* PREFIX_VEX_0F3838 */
5818 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5821 /* PREFIX_VEX_0F3839 */
5825 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5828 /* PREFIX_VEX_0F383A */
5832 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5835 /* PREFIX_VEX_0F383B */
5839 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5842 /* PREFIX_VEX_0F383C */
5846 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5849 /* PREFIX_VEX_0F383D */
5853 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5856 /* PREFIX_VEX_0F383E */
5860 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5863 /* PREFIX_VEX_0F383F */
5867 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5870 /* PREFIX_VEX_0F3840 */
5874 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5877 /* PREFIX_VEX_0F3841 */
5881 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5884 /* PREFIX_VEX_0F3845 */
5888 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5891 /* PREFIX_VEX_0F3846 */
5895 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5898 /* PREFIX_VEX_0F3847 */
5902 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5905 /* PREFIX_VEX_0F3858 */
5909 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5912 /* PREFIX_VEX_0F3859 */
5916 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5919 /* PREFIX_VEX_0F385A */
5923 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5926 /* PREFIX_VEX_0F3878 */
5930 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5933 /* PREFIX_VEX_0F3879 */
5937 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5940 /* PREFIX_VEX_0F388C */
5944 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5947 /* PREFIX_VEX_0F388E */
5951 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5954 /* PREFIX_VEX_0F3890 */
5958 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5961 /* PREFIX_VEX_0F3891 */
5965 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5968 /* PREFIX_VEX_0F3892 */
5972 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5975 /* PREFIX_VEX_0F3893 */
5979 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5982 /* PREFIX_VEX_0F3896 */
5986 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
5989 /* PREFIX_VEX_0F3897 */
5993 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
5996 /* PREFIX_VEX_0F3898 */
6000 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6003 /* PREFIX_VEX_0F3899 */
6007 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6010 /* PREFIX_VEX_0F389A */
6014 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6017 /* PREFIX_VEX_0F389B */
6021 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6024 /* PREFIX_VEX_0F389C */
6028 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6031 /* PREFIX_VEX_0F389D */
6035 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6038 /* PREFIX_VEX_0F389E */
6042 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6045 /* PREFIX_VEX_0F389F */
6049 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6052 /* PREFIX_VEX_0F38A6 */
6056 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6060 /* PREFIX_VEX_0F38A7 */
6064 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6067 /* PREFIX_VEX_0F38A8 */
6071 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6074 /* PREFIX_VEX_0F38A9 */
6078 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6081 /* PREFIX_VEX_0F38AA */
6085 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6088 /* PREFIX_VEX_0F38AB */
6092 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6095 /* PREFIX_VEX_0F38AC */
6099 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6102 /* PREFIX_VEX_0F38AD */
6106 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6109 /* PREFIX_VEX_0F38AE */
6113 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6116 /* PREFIX_VEX_0F38AF */
6120 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6123 /* PREFIX_VEX_0F38B6 */
6127 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6130 /* PREFIX_VEX_0F38B7 */
6134 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6137 /* PREFIX_VEX_0F38B8 */
6141 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6144 /* PREFIX_VEX_0F38B9 */
6148 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6151 /* PREFIX_VEX_0F38BA */
6155 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6158 /* PREFIX_VEX_0F38BB */
6162 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6165 /* PREFIX_VEX_0F38BC */
6169 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6172 /* PREFIX_VEX_0F38BD */
6176 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6179 /* PREFIX_VEX_0F38BE */
6183 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6186 /* PREFIX_VEX_0F38BF */
6190 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6193 /* PREFIX_VEX_0F38CF */
6197 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6200 /* PREFIX_VEX_0F38DB */
6204 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6207 /* PREFIX_VEX_0F38DC */
6211 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6214 /* PREFIX_VEX_0F38DD */
6218 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6221 /* PREFIX_VEX_0F38DE */
6225 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6228 /* PREFIX_VEX_0F38DF */
6232 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6235 /* PREFIX_VEX_0F38F2 */
6237 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6240 /* PREFIX_VEX_0F38F3_REG_1 */
6242 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6245 /* PREFIX_VEX_0F38F3_REG_2 */
6247 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6250 /* PREFIX_VEX_0F38F3_REG_3 */
6252 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6255 /* PREFIX_VEX_0F38F5 */
6257 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6258 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6260 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6263 /* PREFIX_VEX_0F38F6 */
6268 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6271 /* PREFIX_VEX_0F38F7 */
6273 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6274 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6275 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6276 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6279 /* PREFIX_VEX_0F3A00 */
6283 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6286 /* PREFIX_VEX_0F3A01 */
6290 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6293 /* PREFIX_VEX_0F3A02 */
6297 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6300 /* PREFIX_VEX_0F3A04 */
6304 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6307 /* PREFIX_VEX_0F3A05 */
6311 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6314 /* PREFIX_VEX_0F3A06 */
6318 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6321 /* PREFIX_VEX_0F3A08 */
6325 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6328 /* PREFIX_VEX_0F3A09 */
6332 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6335 /* PREFIX_VEX_0F3A0A */
6339 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6342 /* PREFIX_VEX_0F3A0B */
6346 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6349 /* PREFIX_VEX_0F3A0C */
6353 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6356 /* PREFIX_VEX_0F3A0D */
6360 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6363 /* PREFIX_VEX_0F3A0E */
6367 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6370 /* PREFIX_VEX_0F3A0F */
6374 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6377 /* PREFIX_VEX_0F3A14 */
6381 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6384 /* PREFIX_VEX_0F3A15 */
6388 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6391 /* PREFIX_VEX_0F3A16 */
6395 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6398 /* PREFIX_VEX_0F3A17 */
6402 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6405 /* PREFIX_VEX_0F3A18 */
6409 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6412 /* PREFIX_VEX_0F3A19 */
6416 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6419 /* PREFIX_VEX_0F3A1D */
6423 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6426 /* PREFIX_VEX_0F3A20 */
6430 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6433 /* PREFIX_VEX_0F3A21 */
6437 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6440 /* PREFIX_VEX_0F3A22 */
6444 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6447 /* PREFIX_VEX_0F3A30 */
6451 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6454 /* PREFIX_VEX_0F3A31 */
6458 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6461 /* PREFIX_VEX_0F3A32 */
6465 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6468 /* PREFIX_VEX_0F3A33 */
6472 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6475 /* PREFIX_VEX_0F3A38 */
6479 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6482 /* PREFIX_VEX_0F3A39 */
6486 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6489 /* PREFIX_VEX_0F3A40 */
6493 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6496 /* PREFIX_VEX_0F3A41 */
6500 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6503 /* PREFIX_VEX_0F3A42 */
6507 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6510 /* PREFIX_VEX_0F3A44 */
6514 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6517 /* PREFIX_VEX_0F3A46 */
6521 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6524 /* PREFIX_VEX_0F3A48 */
6528 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6531 /* PREFIX_VEX_0F3A49 */
6535 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6538 /* PREFIX_VEX_0F3A4A */
6542 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6545 /* PREFIX_VEX_0F3A4B */
6549 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6552 /* PREFIX_VEX_0F3A4C */
6556 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6559 /* PREFIX_VEX_0F3A5C */
6563 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6566 /* PREFIX_VEX_0F3A5D */
6570 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6573 /* PREFIX_VEX_0F3A5E */
6577 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6580 /* PREFIX_VEX_0F3A5F */
6584 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6587 /* PREFIX_VEX_0F3A60 */
6591 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6595 /* PREFIX_VEX_0F3A61 */
6599 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6602 /* PREFIX_VEX_0F3A62 */
6606 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6609 /* PREFIX_VEX_0F3A63 */
6613 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6616 /* PREFIX_VEX_0F3A68 */
6620 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6623 /* PREFIX_VEX_0F3A69 */
6627 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6630 /* PREFIX_VEX_0F3A6A */
6634 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6637 /* PREFIX_VEX_0F3A6B */
6641 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6644 /* PREFIX_VEX_0F3A6C */
6648 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6651 /* PREFIX_VEX_0F3A6D */
6655 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6658 /* PREFIX_VEX_0F3A6E */
6662 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6665 /* PREFIX_VEX_0F3A6F */
6669 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6672 /* PREFIX_VEX_0F3A78 */
6676 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6679 /* PREFIX_VEX_0F3A79 */
6683 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6686 /* PREFIX_VEX_0F3A7A */
6690 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6693 /* PREFIX_VEX_0F3A7B */
6697 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6700 /* PREFIX_VEX_0F3A7C */
6704 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6708 /* PREFIX_VEX_0F3A7D */
6712 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6715 /* PREFIX_VEX_0F3A7E */
6719 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6722 /* PREFIX_VEX_0F3A7F */
6726 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6729 /* PREFIX_VEX_0F3ACE */
6733 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6736 /* PREFIX_VEX_0F3ACF */
6740 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6743 /* PREFIX_VEX_0F3ADF */
6747 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6750 /* PREFIX_VEX_0F3AF0 */
6755 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6758 #define NEED_PREFIX_TABLE
6759 #include "i386-dis-evex.h"
6760 #undef NEED_PREFIX_TABLE
6763 static const struct dis386 x86_64_table
[][2] = {
6766 { "pushP", { es
}, 0 },
6771 { "popP", { es
}, 0 },
6776 { "pushP", { cs
}, 0 },
6781 { "pushP", { ss
}, 0 },
6786 { "popP", { ss
}, 0 },
6791 { "pushP", { ds
}, 0 },
6796 { "popP", { ds
}, 0 },
6801 { "daa", { XX
}, 0 },
6806 { "das", { XX
}, 0 },
6811 { "aaa", { XX
}, 0 },
6816 { "aas", { XX
}, 0 },
6821 { "pushaP", { XX
}, 0 },
6826 { "popaP", { XX
}, 0 },
6831 { MOD_TABLE (MOD_62_32BIT
) },
6832 { EVEX_TABLE (EVEX_0F
) },
6837 { "arpl", { Ew
, Gw
}, 0 },
6838 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6843 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6844 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6849 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6850 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6855 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6856 { REG_TABLE (REG_80
) },
6861 { "Jcall{T|}", { Ap
}, 0 },
6866 { MOD_TABLE (MOD_C4_32BIT
) },
6867 { VEX_C4_TABLE (VEX_0F
) },
6872 { MOD_TABLE (MOD_C5_32BIT
) },
6873 { VEX_C5_TABLE (VEX_0F
) },
6878 { "into", { XX
}, 0 },
6883 { "aam", { Ib
}, 0 },
6888 { "aad", { Ib
}, 0 },
6893 { "callP", { Jv
, BND
}, 0 },
6894 { "call@", { Jv
, BND
}, 0 }
6899 { "jmpP", { Jv
, BND
}, 0 },
6900 { "jmp@", { Jv
, BND
}, 0 }
6905 { "Jjmp{T|}", { Ap
}, 0 },
6908 /* X86_64_0F01_REG_0 */
6910 { "sgdt{Q|IQ}", { M
}, 0 },
6911 { "sgdt", { M
}, 0 },
6914 /* X86_64_0F01_REG_1 */
6916 { "sidt{Q|IQ}", { M
}, 0 },
6917 { "sidt", { M
}, 0 },
6920 /* X86_64_0F01_REG_2 */
6922 { "lgdt{Q|Q}", { M
}, 0 },
6923 { "lgdt", { M
}, 0 },
6926 /* X86_64_0F01_REG_3 */
6928 { "lidt{Q|Q}", { M
}, 0 },
6929 { "lidt", { M
}, 0 },
6933 static const struct dis386 three_byte_table
[][256] = {
6935 /* THREE_BYTE_0F38 */
6938 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6939 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6940 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6941 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6942 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6943 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6944 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6945 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6947 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6948 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6949 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6950 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6956 { PREFIX_TABLE (PREFIX_0F3810
) },
6960 { PREFIX_TABLE (PREFIX_0F3814
) },
6961 { PREFIX_TABLE (PREFIX_0F3815
) },
6963 { PREFIX_TABLE (PREFIX_0F3817
) },
6969 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6970 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6971 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6974 { PREFIX_TABLE (PREFIX_0F3820
) },
6975 { PREFIX_TABLE (PREFIX_0F3821
) },
6976 { PREFIX_TABLE (PREFIX_0F3822
) },
6977 { PREFIX_TABLE (PREFIX_0F3823
) },
6978 { PREFIX_TABLE (PREFIX_0F3824
) },
6979 { PREFIX_TABLE (PREFIX_0F3825
) },
6983 { PREFIX_TABLE (PREFIX_0F3828
) },
6984 { PREFIX_TABLE (PREFIX_0F3829
) },
6985 { PREFIX_TABLE (PREFIX_0F382A
) },
6986 { PREFIX_TABLE (PREFIX_0F382B
) },
6992 { PREFIX_TABLE (PREFIX_0F3830
) },
6993 { PREFIX_TABLE (PREFIX_0F3831
) },
6994 { PREFIX_TABLE (PREFIX_0F3832
) },
6995 { PREFIX_TABLE (PREFIX_0F3833
) },
6996 { PREFIX_TABLE (PREFIX_0F3834
) },
6997 { PREFIX_TABLE (PREFIX_0F3835
) },
6999 { PREFIX_TABLE (PREFIX_0F3837
) },
7001 { PREFIX_TABLE (PREFIX_0F3838
) },
7002 { PREFIX_TABLE (PREFIX_0F3839
) },
7003 { PREFIX_TABLE (PREFIX_0F383A
) },
7004 { PREFIX_TABLE (PREFIX_0F383B
) },
7005 { PREFIX_TABLE (PREFIX_0F383C
) },
7006 { PREFIX_TABLE (PREFIX_0F383D
) },
7007 { PREFIX_TABLE (PREFIX_0F383E
) },
7008 { PREFIX_TABLE (PREFIX_0F383F
) },
7010 { PREFIX_TABLE (PREFIX_0F3840
) },
7011 { PREFIX_TABLE (PREFIX_0F3841
) },
7082 { PREFIX_TABLE (PREFIX_0F3880
) },
7083 { PREFIX_TABLE (PREFIX_0F3881
) },
7084 { PREFIX_TABLE (PREFIX_0F3882
) },
7163 { PREFIX_TABLE (PREFIX_0F38C8
) },
7164 { PREFIX_TABLE (PREFIX_0F38C9
) },
7165 { PREFIX_TABLE (PREFIX_0F38CA
) },
7166 { PREFIX_TABLE (PREFIX_0F38CB
) },
7167 { PREFIX_TABLE (PREFIX_0F38CC
) },
7168 { PREFIX_TABLE (PREFIX_0F38CD
) },
7170 { PREFIX_TABLE (PREFIX_0F38CF
) },
7184 { PREFIX_TABLE (PREFIX_0F38DB
) },
7185 { PREFIX_TABLE (PREFIX_0F38DC
) },
7186 { PREFIX_TABLE (PREFIX_0F38DD
) },
7187 { PREFIX_TABLE (PREFIX_0F38DE
) },
7188 { PREFIX_TABLE (PREFIX_0F38DF
) },
7208 { PREFIX_TABLE (PREFIX_0F38F0
) },
7209 { PREFIX_TABLE (PREFIX_0F38F1
) },
7213 { PREFIX_TABLE (PREFIX_0F38F5
) },
7214 { PREFIX_TABLE (PREFIX_0F38F6
) },
7217 { PREFIX_TABLE (PREFIX_0F38F8
) },
7218 { PREFIX_TABLE (PREFIX_0F38F9
) },
7226 /* THREE_BYTE_0F3A */
7238 { PREFIX_TABLE (PREFIX_0F3A08
) },
7239 { PREFIX_TABLE (PREFIX_0F3A09
) },
7240 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7241 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7242 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7243 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7244 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7245 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7251 { PREFIX_TABLE (PREFIX_0F3A14
) },
7252 { PREFIX_TABLE (PREFIX_0F3A15
) },
7253 { PREFIX_TABLE (PREFIX_0F3A16
) },
7254 { PREFIX_TABLE (PREFIX_0F3A17
) },
7265 { PREFIX_TABLE (PREFIX_0F3A20
) },
7266 { PREFIX_TABLE (PREFIX_0F3A21
) },
7267 { PREFIX_TABLE (PREFIX_0F3A22
) },
7301 { PREFIX_TABLE (PREFIX_0F3A40
) },
7302 { PREFIX_TABLE (PREFIX_0F3A41
) },
7303 { PREFIX_TABLE (PREFIX_0F3A42
) },
7305 { PREFIX_TABLE (PREFIX_0F3A44
) },
7337 { PREFIX_TABLE (PREFIX_0F3A60
) },
7338 { PREFIX_TABLE (PREFIX_0F3A61
) },
7339 { PREFIX_TABLE (PREFIX_0F3A62
) },
7340 { PREFIX_TABLE (PREFIX_0F3A63
) },
7458 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7460 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7461 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7479 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7519 static const struct dis386 xop_table
[][256] = {
7672 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7673 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7674 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7682 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7683 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7690 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7691 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7692 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7700 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7701 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7705 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7706 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7709 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7727 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7739 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7740 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7741 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7742 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7752 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7753 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7754 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7755 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7788 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7789 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7790 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7791 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7815 { REG_TABLE (REG_XOP_TBM_01
) },
7816 { REG_TABLE (REG_XOP_TBM_02
) },
7834 { REG_TABLE (REG_XOP_LWPCB
) },
7958 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7959 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7960 { "vfrczss", { XM
, EXd
}, 0 },
7961 { "vfrczsd", { XM
, EXq
}, 0 },
7976 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7977 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7978 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7979 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7980 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7981 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7982 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7983 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7985 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7986 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7987 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7988 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8031 { "vphaddbw", { XM
, EXxmm
}, 0 },
8032 { "vphaddbd", { XM
, EXxmm
}, 0 },
8033 { "vphaddbq", { XM
, EXxmm
}, 0 },
8036 { "vphaddwd", { XM
, EXxmm
}, 0 },
8037 { "vphaddwq", { XM
, EXxmm
}, 0 },
8042 { "vphadddq", { XM
, EXxmm
}, 0 },
8049 { "vphaddubw", { XM
, EXxmm
}, 0 },
8050 { "vphaddubd", { XM
, EXxmm
}, 0 },
8051 { "vphaddubq", { XM
, EXxmm
}, 0 },
8054 { "vphadduwd", { XM
, EXxmm
}, 0 },
8055 { "vphadduwq", { XM
, EXxmm
}, 0 },
8060 { "vphaddudq", { XM
, EXxmm
}, 0 },
8067 { "vphsubbw", { XM
, EXxmm
}, 0 },
8068 { "vphsubwd", { XM
, EXxmm
}, 0 },
8069 { "vphsubdq", { XM
, EXxmm
}, 0 },
8123 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8125 { REG_TABLE (REG_XOP_LWP
) },
8395 static const struct dis386 vex_table
[][256] = {
8417 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8418 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8419 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8420 { MOD_TABLE (MOD_VEX_0F13
) },
8421 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8422 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8423 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8424 { MOD_TABLE (MOD_VEX_0F17
) },
8444 { "vmovapX", { XM
, EXx
}, 0 },
8445 { "vmovapX", { EXxS
, XM
}, 0 },
8446 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8447 { MOD_TABLE (MOD_VEX_0F2B
) },
8448 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8449 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8450 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8451 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8472 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8473 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8475 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8476 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8477 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8478 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8482 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8483 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8489 { MOD_TABLE (MOD_VEX_0F50
) },
8490 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8491 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8492 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8493 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8494 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8495 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8496 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8498 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8499 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8500 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8501 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8502 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8503 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8504 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8505 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8507 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8508 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8509 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8510 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8511 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8512 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8517 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8519 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8520 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8521 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8522 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8525 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8526 { REG_TABLE (REG_VEX_0F71
) },
8527 { REG_TABLE (REG_VEX_0F72
) },
8528 { REG_TABLE (REG_VEX_0F73
) },
8529 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8531 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8532 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8564 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8594 { REG_TABLE (REG_VEX_0FAE
) },
8617 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8619 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8620 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8621 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8633 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8634 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8635 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8636 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8637 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8638 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8639 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8640 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8644 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8645 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8646 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8647 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8648 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8649 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8651 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8652 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8654 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8663 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8849 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8852 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8853 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8854 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8855 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8863 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8876 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8877 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8879 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8880 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8881 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8963 { REG_TABLE (REG_VEX_0F38F3
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8981 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9116 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9212 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9213 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9231 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9251 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9271 #define NEED_OPCODE_TABLE
9272 #include "i386-dis-evex.h"
9273 #undef NEED_OPCODE_TABLE
9274 static const struct dis386 vex_len_table
[][2] = {
9275 /* VEX_LEN_0F12_P_0_M_0 */
9277 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9280 /* VEX_LEN_0F12_P_0_M_1 */
9282 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9285 /* VEX_LEN_0F12_P_2 */
9287 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9290 /* VEX_LEN_0F13_M_0 */
9292 { "vmovlpX", { EXq
, XM
}, 0 },
9295 /* VEX_LEN_0F16_P_0_M_0 */
9297 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9300 /* VEX_LEN_0F16_P_0_M_1 */
9302 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9305 /* VEX_LEN_0F16_P_2 */
9307 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9310 /* VEX_LEN_0F17_M_0 */
9312 { "vmovhpX", { EXq
, XM
}, 0 },
9315 /* VEX_LEN_0F2A_P_1 */
9317 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9318 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9321 /* VEX_LEN_0F2A_P_3 */
9323 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9324 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9327 /* VEX_LEN_0F2C_P_1 */
9329 { "vcvttss2si", { Gv
, EXdScalar
}, 0 },
9330 { "vcvttss2si", { Gv
, EXdScalar
}, 0 },
9333 /* VEX_LEN_0F2C_P_3 */
9335 { "vcvttsd2si", { Gv
, EXqScalar
}, 0 },
9336 { "vcvttsd2si", { Gv
, EXqScalar
}, 0 },
9339 /* VEX_LEN_0F2D_P_1 */
9341 { "vcvtss2si", { Gv
, EXdScalar
}, 0 },
9342 { "vcvtss2si", { Gv
, EXdScalar
}, 0 },
9345 /* VEX_LEN_0F2D_P_3 */
9347 { "vcvtsd2si", { Gv
, EXqScalar
}, 0 },
9348 { "vcvtsd2si", { Gv
, EXqScalar
}, 0 },
9351 /* VEX_LEN_0F41_P_0 */
9354 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9356 /* VEX_LEN_0F41_P_2 */
9359 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9361 /* VEX_LEN_0F42_P_0 */
9364 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9366 /* VEX_LEN_0F42_P_2 */
9369 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9371 /* VEX_LEN_0F44_P_0 */
9373 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9375 /* VEX_LEN_0F44_P_2 */
9377 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9379 /* VEX_LEN_0F45_P_0 */
9382 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9384 /* VEX_LEN_0F45_P_2 */
9387 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9389 /* VEX_LEN_0F46_P_0 */
9392 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9394 /* VEX_LEN_0F46_P_2 */
9397 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9399 /* VEX_LEN_0F47_P_0 */
9402 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9404 /* VEX_LEN_0F47_P_2 */
9407 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9409 /* VEX_LEN_0F4A_P_0 */
9412 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9414 /* VEX_LEN_0F4A_P_2 */
9417 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9419 /* VEX_LEN_0F4B_P_0 */
9422 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9424 /* VEX_LEN_0F4B_P_2 */
9427 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9430 /* VEX_LEN_0F6E_P_2 */
9432 { "vmovK", { XMScalar
, Edq
}, 0 },
9435 /* VEX_LEN_0F77_P_1 */
9437 { "vzeroupper", { XX
}, 0 },
9438 { "vzeroall", { XX
}, 0 },
9441 /* VEX_LEN_0F7E_P_1 */
9443 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9446 /* VEX_LEN_0F7E_P_2 */
9448 { "vmovK", { Edq
, XMScalar
}, 0 },
9451 /* VEX_LEN_0F90_P_0 */
9453 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9456 /* VEX_LEN_0F90_P_2 */
9458 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9461 /* VEX_LEN_0F91_P_0 */
9463 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9466 /* VEX_LEN_0F91_P_2 */
9468 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9471 /* VEX_LEN_0F92_P_0 */
9473 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9476 /* VEX_LEN_0F92_P_2 */
9478 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9481 /* VEX_LEN_0F92_P_3 */
9483 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9486 /* VEX_LEN_0F93_P_0 */
9488 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9491 /* VEX_LEN_0F93_P_2 */
9493 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9496 /* VEX_LEN_0F93_P_3 */
9498 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9501 /* VEX_LEN_0F98_P_0 */
9503 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9506 /* VEX_LEN_0F98_P_2 */
9508 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9511 /* VEX_LEN_0F99_P_0 */
9513 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9516 /* VEX_LEN_0F99_P_2 */
9518 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9521 /* VEX_LEN_0FAE_R_2_M_0 */
9523 { "vldmxcsr", { Md
}, 0 },
9526 /* VEX_LEN_0FAE_R_3_M_0 */
9528 { "vstmxcsr", { Md
}, 0 },
9531 /* VEX_LEN_0FC4_P_2 */
9533 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9536 /* VEX_LEN_0FC5_P_2 */
9538 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9541 /* VEX_LEN_0FD6_P_2 */
9543 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9546 /* VEX_LEN_0FF7_P_2 */
9548 { "vmaskmovdqu", { XM
, XS
}, 0 },
9551 /* VEX_LEN_0F3816_P_2 */
9554 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9557 /* VEX_LEN_0F3819_P_2 */
9560 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9563 /* VEX_LEN_0F381A_P_2_M_0 */
9566 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9569 /* VEX_LEN_0F3836_P_2 */
9572 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9575 /* VEX_LEN_0F3841_P_2 */
9577 { "vphminposuw", { XM
, EXx
}, 0 },
9580 /* VEX_LEN_0F385A_P_2_M_0 */
9583 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9586 /* VEX_LEN_0F38DB_P_2 */
9588 { "vaesimc", { XM
, EXx
}, 0 },
9591 /* VEX_LEN_0F38F2_P_0 */
9593 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9596 /* VEX_LEN_0F38F3_R_1_P_0 */
9598 { "blsrS", { VexGdq
, Edq
}, 0 },
9601 /* VEX_LEN_0F38F3_R_2_P_0 */
9603 { "blsmskS", { VexGdq
, Edq
}, 0 },
9606 /* VEX_LEN_0F38F3_R_3_P_0 */
9608 { "blsiS", { VexGdq
, Edq
}, 0 },
9611 /* VEX_LEN_0F38F5_P_0 */
9613 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9616 /* VEX_LEN_0F38F5_P_1 */
9618 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9621 /* VEX_LEN_0F38F5_P_3 */
9623 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9626 /* VEX_LEN_0F38F6_P_3 */
9628 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9631 /* VEX_LEN_0F38F7_P_0 */
9633 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9636 /* VEX_LEN_0F38F7_P_1 */
9638 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9641 /* VEX_LEN_0F38F7_P_2 */
9643 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9646 /* VEX_LEN_0F38F7_P_3 */
9648 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9651 /* VEX_LEN_0F3A00_P_2 */
9654 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9657 /* VEX_LEN_0F3A01_P_2 */
9660 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9663 /* VEX_LEN_0F3A06_P_2 */
9666 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9669 /* VEX_LEN_0F3A14_P_2 */
9671 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9674 /* VEX_LEN_0F3A15_P_2 */
9676 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9679 /* VEX_LEN_0F3A16_P_2 */
9681 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9684 /* VEX_LEN_0F3A17_P_2 */
9686 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9689 /* VEX_LEN_0F3A18_P_2 */
9692 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9695 /* VEX_LEN_0F3A19_P_2 */
9698 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9701 /* VEX_LEN_0F3A20_P_2 */
9703 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9706 /* VEX_LEN_0F3A21_P_2 */
9708 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9711 /* VEX_LEN_0F3A22_P_2 */
9713 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9716 /* VEX_LEN_0F3A30_P_2 */
9718 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9721 /* VEX_LEN_0F3A31_P_2 */
9723 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9726 /* VEX_LEN_0F3A32_P_2 */
9728 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9731 /* VEX_LEN_0F3A33_P_2 */
9733 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9736 /* VEX_LEN_0F3A38_P_2 */
9739 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9742 /* VEX_LEN_0F3A39_P_2 */
9745 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9748 /* VEX_LEN_0F3A41_P_2 */
9750 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9753 /* VEX_LEN_0F3A46_P_2 */
9756 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9759 /* VEX_LEN_0F3A60_P_2 */
9761 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9764 /* VEX_LEN_0F3A61_P_2 */
9766 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9769 /* VEX_LEN_0F3A62_P_2 */
9771 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9774 /* VEX_LEN_0F3A63_P_2 */
9776 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9779 /* VEX_LEN_0F3A6A_P_2 */
9781 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9784 /* VEX_LEN_0F3A6B_P_2 */
9786 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9789 /* VEX_LEN_0F3A6E_P_2 */
9791 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9794 /* VEX_LEN_0F3A6F_P_2 */
9796 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9799 /* VEX_LEN_0F3A7A_P_2 */
9801 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9804 /* VEX_LEN_0F3A7B_P_2 */
9806 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9809 /* VEX_LEN_0F3A7E_P_2 */
9811 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9814 /* VEX_LEN_0F3A7F_P_2 */
9816 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9819 /* VEX_LEN_0F3ADF_P_2 */
9821 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9824 /* VEX_LEN_0F3AF0_P_3 */
9826 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9829 /* VEX_LEN_0FXOP_08_CC */
9831 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9834 /* VEX_LEN_0FXOP_08_CD */
9836 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9839 /* VEX_LEN_0FXOP_08_CE */
9841 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9844 /* VEX_LEN_0FXOP_08_CF */
9846 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9849 /* VEX_LEN_0FXOP_08_EC */
9851 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9854 /* VEX_LEN_0FXOP_08_ED */
9856 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9859 /* VEX_LEN_0FXOP_08_EE */
9861 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9864 /* VEX_LEN_0FXOP_08_EF */
9866 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9869 /* VEX_LEN_0FXOP_09_80 */
9871 { "vfrczps", { XM
, EXxmm
}, 0 },
9872 { "vfrczps", { XM
, EXymmq
}, 0 },
9875 /* VEX_LEN_0FXOP_09_81 */
9877 { "vfrczpd", { XM
, EXxmm
}, 0 },
9878 { "vfrczpd", { XM
, EXymmq
}, 0 },
9882 static const struct dis386 evex_len_table
[][3] = {
9883 #define NEED_EVEX_LEN_TABLE
9884 #include "i386-dis-evex.h"
9885 #undef NEED_EVEX_LEN_TABLE
9888 static const struct dis386 vex_w_table
[][2] = {
9890 /* VEX_W_0F41_P_0_LEN_1 */
9891 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9892 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9895 /* VEX_W_0F41_P_2_LEN_1 */
9896 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9897 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9900 /* VEX_W_0F42_P_0_LEN_1 */
9901 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9902 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9905 /* VEX_W_0F42_P_2_LEN_1 */
9906 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9907 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9910 /* VEX_W_0F44_P_0_LEN_0 */
9911 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9912 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9915 /* VEX_W_0F44_P_2_LEN_0 */
9916 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9917 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9920 /* VEX_W_0F45_P_0_LEN_1 */
9921 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9922 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9925 /* VEX_W_0F45_P_2_LEN_1 */
9926 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9927 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9930 /* VEX_W_0F46_P_0_LEN_1 */
9931 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9932 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9935 /* VEX_W_0F46_P_2_LEN_1 */
9936 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9937 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9940 /* VEX_W_0F47_P_0_LEN_1 */
9941 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9942 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9945 /* VEX_W_0F47_P_2_LEN_1 */
9946 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9947 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9950 /* VEX_W_0F4A_P_0_LEN_1 */
9951 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9952 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9955 /* VEX_W_0F4A_P_2_LEN_1 */
9956 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9957 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9960 /* VEX_W_0F4B_P_0_LEN_1 */
9961 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9962 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9965 /* VEX_W_0F4B_P_2_LEN_1 */
9966 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9969 /* VEX_W_0F90_P_0_LEN_0 */
9970 { "kmovw", { MaskG
, MaskE
}, 0 },
9971 { "kmovq", { MaskG
, MaskE
}, 0 },
9974 /* VEX_W_0F90_P_2_LEN_0 */
9975 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9976 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9979 /* VEX_W_0F91_P_0_LEN_0 */
9980 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9981 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9984 /* VEX_W_0F91_P_2_LEN_0 */
9985 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9986 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9989 /* VEX_W_0F92_P_0_LEN_0 */
9990 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9993 /* VEX_W_0F92_P_2_LEN_0 */
9994 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9997 /* VEX_W_0F93_P_0_LEN_0 */
9998 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10001 /* VEX_W_0F93_P_2_LEN_0 */
10002 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10005 /* VEX_W_0F98_P_0_LEN_0 */
10006 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10007 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10010 /* VEX_W_0F98_P_2_LEN_0 */
10011 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10012 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10015 /* VEX_W_0F99_P_0_LEN_0 */
10016 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10017 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10020 /* VEX_W_0F99_P_2_LEN_0 */
10021 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10022 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10025 /* VEX_W_0F380C_P_2 */
10026 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10029 /* VEX_W_0F380D_P_2 */
10030 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10033 /* VEX_W_0F380E_P_2 */
10034 { "vtestps", { XM
, EXx
}, 0 },
10037 /* VEX_W_0F380F_P_2 */
10038 { "vtestpd", { XM
, EXx
}, 0 },
10041 /* VEX_W_0F3816_P_2 */
10042 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10045 /* VEX_W_0F3818_P_2 */
10046 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10049 /* VEX_W_0F3819_P_2 */
10050 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10053 /* VEX_W_0F381A_P_2_M_0 */
10054 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10057 /* VEX_W_0F382C_P_2_M_0 */
10058 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10061 /* VEX_W_0F382D_P_2_M_0 */
10062 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10065 /* VEX_W_0F382E_P_2_M_0 */
10066 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10069 /* VEX_W_0F382F_P_2_M_0 */
10070 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10073 /* VEX_W_0F3836_P_2 */
10074 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10077 /* VEX_W_0F3846_P_2 */
10078 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10081 /* VEX_W_0F3858_P_2 */
10082 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10085 /* VEX_W_0F3859_P_2 */
10086 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10089 /* VEX_W_0F385A_P_2_M_0 */
10090 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10093 /* VEX_W_0F3878_P_2 */
10094 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10097 /* VEX_W_0F3879_P_2 */
10098 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10101 /* VEX_W_0F38CF_P_2 */
10102 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10105 /* VEX_W_0F3A00_P_2 */
10107 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10110 /* VEX_W_0F3A01_P_2 */
10112 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10115 /* VEX_W_0F3A02_P_2 */
10116 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10119 /* VEX_W_0F3A04_P_2 */
10120 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10123 /* VEX_W_0F3A05_P_2 */
10124 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10127 /* VEX_W_0F3A06_P_2 */
10128 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10131 /* VEX_W_0F3A18_P_2 */
10132 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10135 /* VEX_W_0F3A19_P_2 */
10136 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10139 /* VEX_W_0F3A30_P_2_LEN_0 */
10140 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10141 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10144 /* VEX_W_0F3A31_P_2_LEN_0 */
10145 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10146 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10149 /* VEX_W_0F3A32_P_2_LEN_0 */
10150 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10151 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10154 /* VEX_W_0F3A33_P_2_LEN_0 */
10155 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10156 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10159 /* VEX_W_0F3A38_P_2 */
10160 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10163 /* VEX_W_0F3A39_P_2 */
10164 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10167 /* VEX_W_0F3A46_P_2 */
10168 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10171 /* VEX_W_0F3A48_P_2 */
10172 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10173 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10176 /* VEX_W_0F3A49_P_2 */
10177 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10178 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10181 /* VEX_W_0F3A4A_P_2 */
10182 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10185 /* VEX_W_0F3A4B_P_2 */
10186 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10189 /* VEX_W_0F3A4C_P_2 */
10190 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10193 /* VEX_W_0F3ACE_P_2 */
10195 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10198 /* VEX_W_0F3ACF_P_2 */
10200 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10202 #define NEED_VEX_W_TABLE
10203 #include "i386-dis-evex.h"
10204 #undef NEED_VEX_W_TABLE
10207 static const struct dis386 mod_table
[][2] = {
10210 { "leaS", { Gv
, M
}, 0 },
10215 { RM_TABLE (RM_C6_REG_7
) },
10220 { RM_TABLE (RM_C7_REG_7
) },
10224 { "Jcall^", { indirEp
}, 0 },
10228 { "Jjmp^", { indirEp
}, 0 },
10231 /* MOD_0F01_REG_0 */
10232 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10233 { RM_TABLE (RM_0F01_REG_0
) },
10236 /* MOD_0F01_REG_1 */
10237 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10238 { RM_TABLE (RM_0F01_REG_1
) },
10241 /* MOD_0F01_REG_2 */
10242 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10243 { RM_TABLE (RM_0F01_REG_2
) },
10246 /* MOD_0F01_REG_3 */
10247 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10248 { RM_TABLE (RM_0F01_REG_3
) },
10251 /* MOD_0F01_REG_5 */
10252 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5
) },
10253 { RM_TABLE (RM_0F01_REG_5
) },
10256 /* MOD_0F01_REG_7 */
10257 { "invlpg", { Mb
}, 0 },
10258 { RM_TABLE (RM_0F01_REG_7
) },
10261 /* MOD_0F12_PREFIX_0 */
10262 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10263 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10267 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10270 /* MOD_0F16_PREFIX_0 */
10271 { "movhps", { XM
, EXq
}, 0 },
10272 { "movlhps", { XM
, EXq
}, 0 },
10276 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10279 /* MOD_0F18_REG_0 */
10280 { "prefetchnta", { Mb
}, 0 },
10283 /* MOD_0F18_REG_1 */
10284 { "prefetcht0", { Mb
}, 0 },
10287 /* MOD_0F18_REG_2 */
10288 { "prefetcht1", { Mb
}, 0 },
10291 /* MOD_0F18_REG_3 */
10292 { "prefetcht2", { Mb
}, 0 },
10295 /* MOD_0F18_REG_4 */
10296 { "nop/reserved", { Mb
}, 0 },
10299 /* MOD_0F18_REG_5 */
10300 { "nop/reserved", { Mb
}, 0 },
10303 /* MOD_0F18_REG_6 */
10304 { "nop/reserved", { Mb
}, 0 },
10307 /* MOD_0F18_REG_7 */
10308 { "nop/reserved", { Mb
}, 0 },
10311 /* MOD_0F1A_PREFIX_0 */
10312 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10313 { "nopQ", { Ev
}, 0 },
10316 /* MOD_0F1B_PREFIX_0 */
10317 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10318 { "nopQ", { Ev
}, 0 },
10321 /* MOD_0F1B_PREFIX_1 */
10322 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10323 { "nopQ", { Ev
}, 0 },
10326 /* MOD_0F1C_PREFIX_0 */
10327 { REG_TABLE (REG_0F1C_MOD_0
) },
10328 { "nopQ", { Ev
}, 0 },
10331 /* MOD_0F1E_PREFIX_1 */
10332 { "nopQ", { Ev
}, 0 },
10333 { REG_TABLE (REG_0F1E_MOD_3
) },
10338 { "movL", { Rd
, Td
}, 0 },
10343 { "movL", { Td
, Rd
}, 0 },
10346 /* MOD_0F2B_PREFIX_0 */
10347 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10350 /* MOD_0F2B_PREFIX_1 */
10351 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10354 /* MOD_0F2B_PREFIX_2 */
10355 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10358 /* MOD_0F2B_PREFIX_3 */
10359 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10364 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10367 /* MOD_0F71_REG_2 */
10369 { "psrlw", { MS
, Ib
}, 0 },
10372 /* MOD_0F71_REG_4 */
10374 { "psraw", { MS
, Ib
}, 0 },
10377 /* MOD_0F71_REG_6 */
10379 { "psllw", { MS
, Ib
}, 0 },
10382 /* MOD_0F72_REG_2 */
10384 { "psrld", { MS
, Ib
}, 0 },
10387 /* MOD_0F72_REG_4 */
10389 { "psrad", { MS
, Ib
}, 0 },
10392 /* MOD_0F72_REG_6 */
10394 { "pslld", { MS
, Ib
}, 0 },
10397 /* MOD_0F73_REG_2 */
10399 { "psrlq", { MS
, Ib
}, 0 },
10402 /* MOD_0F73_REG_3 */
10404 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10407 /* MOD_0F73_REG_6 */
10409 { "psllq", { MS
, Ib
}, 0 },
10412 /* MOD_0F73_REG_7 */
10414 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10417 /* MOD_0FAE_REG_0 */
10418 { "fxsave", { FXSAVE
}, 0 },
10419 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
10422 /* MOD_0FAE_REG_1 */
10423 { "fxrstor", { FXSAVE
}, 0 },
10424 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
10427 /* MOD_0FAE_REG_2 */
10428 { "ldmxcsr", { Md
}, 0 },
10429 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
10432 /* MOD_0FAE_REG_3 */
10433 { "stmxcsr", { Md
}, 0 },
10434 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
10437 /* MOD_0FAE_REG_4 */
10438 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
10439 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
10442 /* MOD_0FAE_REG_5 */
10443 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5
) },
10444 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5
) },
10447 /* MOD_0FAE_REG_6 */
10448 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6
) },
10449 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6
) },
10452 /* MOD_0FAE_REG_7 */
10453 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
10454 { RM_TABLE (RM_0FAE_REG_7
) },
10458 { "lssS", { Gv
, Mp
}, 0 },
10462 { "lfsS", { Gv
, Mp
}, 0 },
10466 { "lgsS", { Gv
, Mp
}, 0 },
10470 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
10473 /* MOD_0FC7_REG_3 */
10474 { "xrstors", { FXSAVE
}, 0 },
10477 /* MOD_0FC7_REG_4 */
10478 { "xsavec", { FXSAVE
}, 0 },
10481 /* MOD_0FC7_REG_5 */
10482 { "xsaves", { FXSAVE
}, 0 },
10485 /* MOD_0FC7_REG_6 */
10486 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
10487 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
10490 /* MOD_0FC7_REG_7 */
10491 { "vmptrst", { Mq
}, 0 },
10492 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
10497 { "pmovmskb", { Gdq
, MS
}, 0 },
10500 /* MOD_0FE7_PREFIX_2 */
10501 { "movntdq", { Mx
, XM
}, 0 },
10504 /* MOD_0FF0_PREFIX_3 */
10505 { "lddqu", { XM
, M
}, 0 },
10508 /* MOD_0F382A_PREFIX_2 */
10509 { "movntdqa", { XM
, Mx
}, 0 },
10512 /* MOD_0F38F5_PREFIX_2 */
10513 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10516 /* MOD_0F38F6_PREFIX_0 */
10517 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10520 /* MOD_0F38F8_PREFIX_2 */
10521 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10524 /* MOD_0F38F9_PREFIX_0 */
10525 { "movdiri", { Em
, Gv
}, PREFIX_OPCODE
},
10529 { "bound{S|}", { Gv
, Ma
}, 0 },
10530 { EVEX_TABLE (EVEX_0F
) },
10534 { "lesS", { Gv
, Mp
}, 0 },
10535 { VEX_C4_TABLE (VEX_0F
) },
10539 { "ldsS", { Gv
, Mp
}, 0 },
10540 { VEX_C5_TABLE (VEX_0F
) },
10543 /* MOD_VEX_0F12_PREFIX_0 */
10544 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10545 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10549 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10552 /* MOD_VEX_0F16_PREFIX_0 */
10553 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10554 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10558 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10562 { "vmovntpX", { Mx
, XM
}, 0 },
10565 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10567 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10570 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10572 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10575 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10577 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10580 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10582 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10585 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10587 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10590 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10592 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10595 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10597 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10600 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10602 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10605 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10607 { "knotw", { MaskG
, MaskR
}, 0 },
10610 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10612 { "knotq", { MaskG
, MaskR
}, 0 },
10615 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10617 { "knotb", { MaskG
, MaskR
}, 0 },
10620 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10622 { "knotd", { MaskG
, MaskR
}, 0 },
10625 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10627 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10630 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10632 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10635 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10637 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10640 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10642 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10645 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10647 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10650 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10652 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10655 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10657 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10660 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10662 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10665 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10667 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10670 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10672 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10675 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10677 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10680 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10682 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10685 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10687 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10690 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10692 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10695 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10697 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10700 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10702 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10705 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10707 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10710 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10712 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10715 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10717 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10722 { "vmovmskpX", { Gdq
, XS
}, 0 },
10725 /* MOD_VEX_0F71_REG_2 */
10727 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10730 /* MOD_VEX_0F71_REG_4 */
10732 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10735 /* MOD_VEX_0F71_REG_6 */
10737 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10740 /* MOD_VEX_0F72_REG_2 */
10742 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10745 /* MOD_VEX_0F72_REG_4 */
10747 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10750 /* MOD_VEX_0F72_REG_6 */
10752 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10755 /* MOD_VEX_0F73_REG_2 */
10757 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10760 /* MOD_VEX_0F73_REG_3 */
10762 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10765 /* MOD_VEX_0F73_REG_6 */
10767 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10770 /* MOD_VEX_0F73_REG_7 */
10772 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10775 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10776 { "kmovw", { Ew
, MaskG
}, 0 },
10780 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10781 { "kmovq", { Eq
, MaskG
}, 0 },
10785 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10786 { "kmovb", { Eb
, MaskG
}, 0 },
10790 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10791 { "kmovd", { Ed
, MaskG
}, 0 },
10795 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10797 { "kmovw", { MaskG
, Rdq
}, 0 },
10800 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10802 { "kmovb", { MaskG
, Rdq
}, 0 },
10805 /* MOD_VEX_0F92_P_3_LEN_0 */
10807 { "kmovK", { MaskG
, Rdq
}, 0 },
10810 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10812 { "kmovw", { Gdq
, MaskR
}, 0 },
10815 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10817 { "kmovb", { Gdq
, MaskR
}, 0 },
10820 /* MOD_VEX_0F93_P_3_LEN_0 */
10822 { "kmovK", { Gdq
, MaskR
}, 0 },
10825 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10827 { "kortestw", { MaskG
, MaskR
}, 0 },
10830 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10832 { "kortestq", { MaskG
, MaskR
}, 0 },
10835 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10837 { "kortestb", { MaskG
, MaskR
}, 0 },
10840 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10842 { "kortestd", { MaskG
, MaskR
}, 0 },
10845 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10847 { "ktestw", { MaskG
, MaskR
}, 0 },
10850 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10852 { "ktestq", { MaskG
, MaskR
}, 0 },
10855 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10857 { "ktestb", { MaskG
, MaskR
}, 0 },
10860 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10862 { "ktestd", { MaskG
, MaskR
}, 0 },
10865 /* MOD_VEX_0FAE_REG_2 */
10866 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10869 /* MOD_VEX_0FAE_REG_3 */
10870 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10873 /* MOD_VEX_0FD7_PREFIX_2 */
10875 { "vpmovmskb", { Gdq
, XS
}, 0 },
10878 /* MOD_VEX_0FE7_PREFIX_2 */
10879 { "vmovntdq", { Mx
, XM
}, 0 },
10882 /* MOD_VEX_0FF0_PREFIX_3 */
10883 { "vlddqu", { XM
, M
}, 0 },
10886 /* MOD_VEX_0F381A_PREFIX_2 */
10887 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10890 /* MOD_VEX_0F382A_PREFIX_2 */
10891 { "vmovntdqa", { XM
, Mx
}, 0 },
10894 /* MOD_VEX_0F382C_PREFIX_2 */
10895 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10898 /* MOD_VEX_0F382D_PREFIX_2 */
10899 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10902 /* MOD_VEX_0F382E_PREFIX_2 */
10903 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10906 /* MOD_VEX_0F382F_PREFIX_2 */
10907 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10910 /* MOD_VEX_0F385A_PREFIX_2 */
10911 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10914 /* MOD_VEX_0F388C_PREFIX_2 */
10915 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10918 /* MOD_VEX_0F388E_PREFIX_2 */
10919 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10922 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10924 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10927 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10929 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10932 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10934 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10937 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10939 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10942 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10944 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10947 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10949 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10952 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10954 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10957 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10959 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10961 #define NEED_MOD_TABLE
10962 #include "i386-dis-evex.h"
10963 #undef NEED_MOD_TABLE
10966 static const struct dis386 rm_table
[][8] = {
10969 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10973 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
10976 /* RM_0F01_REG_0 */
10977 { "enclv", { Skip_MODRM
}, 0 },
10978 { "vmcall", { Skip_MODRM
}, 0 },
10979 { "vmlaunch", { Skip_MODRM
}, 0 },
10980 { "vmresume", { Skip_MODRM
}, 0 },
10981 { "vmxoff", { Skip_MODRM
}, 0 },
10982 { "pconfig", { Skip_MODRM
}, 0 },
10985 /* RM_0F01_REG_1 */
10986 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10987 { "mwait", { { OP_Mwait
, 0 } }, 0 },
10988 { "clac", { Skip_MODRM
}, 0 },
10989 { "stac", { Skip_MODRM
}, 0 },
10993 { "encls", { Skip_MODRM
}, 0 },
10996 /* RM_0F01_REG_2 */
10997 { "xgetbv", { Skip_MODRM
}, 0 },
10998 { "xsetbv", { Skip_MODRM
}, 0 },
11001 { "vmfunc", { Skip_MODRM
}, 0 },
11002 { "xend", { Skip_MODRM
}, 0 },
11003 { "xtest", { Skip_MODRM
}, 0 },
11004 { "enclu", { Skip_MODRM
}, 0 },
11007 /* RM_0F01_REG_3 */
11008 { "vmrun", { Skip_MODRM
}, 0 },
11009 { "vmmcall", { Skip_MODRM
}, 0 },
11010 { "vmload", { Skip_MODRM
}, 0 },
11011 { "vmsave", { Skip_MODRM
}, 0 },
11012 { "stgi", { Skip_MODRM
}, 0 },
11013 { "clgi", { Skip_MODRM
}, 0 },
11014 { "skinit", { Skip_MODRM
}, 0 },
11015 { "invlpga", { Skip_MODRM
}, 0 },
11018 /* RM_0F01_REG_5 */
11019 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0
) },
11021 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2
) },
11025 { "rdpkru", { Skip_MODRM
}, 0 },
11026 { "wrpkru", { Skip_MODRM
}, 0 },
11029 /* RM_0F01_REG_7 */
11030 { "swapgs", { Skip_MODRM
}, 0 },
11031 { "rdtscp", { Skip_MODRM
}, 0 },
11032 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
11033 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
11034 { "clzero", { Skip_MODRM
}, 0 },
11037 /* RM_0F1E_MOD_3_REG_7 */
11038 { "nopQ", { Ev
}, 0 },
11039 { "nopQ", { Ev
}, 0 },
11040 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11041 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11042 { "nopQ", { Ev
}, 0 },
11043 { "nopQ", { Ev
}, 0 },
11044 { "nopQ", { Ev
}, 0 },
11045 { "nopQ", { Ev
}, 0 },
11048 /* RM_0FAE_REG_6 */
11049 { "mfence", { Skip_MODRM
}, 0 },
11052 /* RM_0FAE_REG_7 */
11053 { "sfence", { Skip_MODRM
}, 0 },
11058 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11060 /* We use the high bit to indicate different name for the same
11062 #define REP_PREFIX (0xf3 | 0x100)
11063 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11064 #define XRELEASE_PREFIX (0xf3 | 0x400)
11065 #define BND_PREFIX (0xf2 | 0x400)
11066 #define NOTRACK_PREFIX (0x3e | 0x100)
11071 int newrex
, i
, length
;
11077 last_lock_prefix
= -1;
11078 last_repz_prefix
= -1;
11079 last_repnz_prefix
= -1;
11080 last_data_prefix
= -1;
11081 last_addr_prefix
= -1;
11082 last_rex_prefix
= -1;
11083 last_seg_prefix
= -1;
11085 active_seg_prefix
= 0;
11086 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11087 all_prefixes
[i
] = 0;
11090 /* The maximum instruction length is 15bytes. */
11091 while (length
< MAX_CODE_LENGTH
- 1)
11093 FETCH_DATA (the_info
, codep
+ 1);
11097 /* REX prefixes family. */
11114 if (address_mode
== mode_64bit
)
11118 last_rex_prefix
= i
;
11121 prefixes
|= PREFIX_REPZ
;
11122 last_repz_prefix
= i
;
11125 prefixes
|= PREFIX_REPNZ
;
11126 last_repnz_prefix
= i
;
11129 prefixes
|= PREFIX_LOCK
;
11130 last_lock_prefix
= i
;
11133 prefixes
|= PREFIX_CS
;
11134 last_seg_prefix
= i
;
11135 active_seg_prefix
= PREFIX_CS
;
11138 prefixes
|= PREFIX_SS
;
11139 last_seg_prefix
= i
;
11140 active_seg_prefix
= PREFIX_SS
;
11143 prefixes
|= PREFIX_DS
;
11144 last_seg_prefix
= i
;
11145 active_seg_prefix
= PREFIX_DS
;
11148 prefixes
|= PREFIX_ES
;
11149 last_seg_prefix
= i
;
11150 active_seg_prefix
= PREFIX_ES
;
11153 prefixes
|= PREFIX_FS
;
11154 last_seg_prefix
= i
;
11155 active_seg_prefix
= PREFIX_FS
;
11158 prefixes
|= PREFIX_GS
;
11159 last_seg_prefix
= i
;
11160 active_seg_prefix
= PREFIX_GS
;
11163 prefixes
|= PREFIX_DATA
;
11164 last_data_prefix
= i
;
11167 prefixes
|= PREFIX_ADDR
;
11168 last_addr_prefix
= i
;
11171 /* fwait is really an instruction. If there are prefixes
11172 before the fwait, they belong to the fwait, *not* to the
11173 following instruction. */
11175 if (prefixes
|| rex
)
11177 prefixes
|= PREFIX_FWAIT
;
11179 /* This ensures that the previous REX prefixes are noticed
11180 as unused prefixes, as in the return case below. */
11184 prefixes
= PREFIX_FWAIT
;
11189 /* Rex is ignored when followed by another prefix. */
11195 if (*codep
!= FWAIT_OPCODE
)
11196 all_prefixes
[i
++] = *codep
;
11204 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11207 static const char *
11208 prefix_name (int pref
, int sizeflag
)
11210 static const char *rexes
[16] =
11213 "rex.B", /* 0x41 */
11214 "rex.X", /* 0x42 */
11215 "rex.XB", /* 0x43 */
11216 "rex.R", /* 0x44 */
11217 "rex.RB", /* 0x45 */
11218 "rex.RX", /* 0x46 */
11219 "rex.RXB", /* 0x47 */
11220 "rex.W", /* 0x48 */
11221 "rex.WB", /* 0x49 */
11222 "rex.WX", /* 0x4a */
11223 "rex.WXB", /* 0x4b */
11224 "rex.WR", /* 0x4c */
11225 "rex.WRB", /* 0x4d */
11226 "rex.WRX", /* 0x4e */
11227 "rex.WRXB", /* 0x4f */
11232 /* REX prefixes family. */
11249 return rexes
[pref
- 0x40];
11269 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11271 if (address_mode
== mode_64bit
)
11272 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11274 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11279 case XACQUIRE_PREFIX
:
11281 case XRELEASE_PREFIX
:
11285 case NOTRACK_PREFIX
:
11292 static char op_out
[MAX_OPERANDS
][100];
11293 static int op_ad
, op_index
[MAX_OPERANDS
];
11294 static int two_source_ops
;
11295 static bfd_vma op_address
[MAX_OPERANDS
];
11296 static bfd_vma op_riprel
[MAX_OPERANDS
];
11297 static bfd_vma start_pc
;
11300 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11301 * (see topic "Redundant prefixes" in the "Differences from 8086"
11302 * section of the "Virtual 8086 Mode" chapter.)
11303 * 'pc' should be the address of this instruction, it will
11304 * be used to print the target address if this is a relative jump or call
11305 * The function returns the length of this instruction in bytes.
11308 static char intel_syntax
;
11309 static char intel_mnemonic
= !SYSV386_COMPAT
;
11310 static char open_char
;
11311 static char close_char
;
11312 static char separator_char
;
11313 static char scale_char
;
11321 static enum x86_64_isa isa64
;
11323 /* Here for backwards compatibility. When gdb stops using
11324 print_insn_i386_att and print_insn_i386_intel these functions can
11325 disappear, and print_insn_i386 be merged into print_insn. */
11327 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11331 return print_insn (pc
, info
);
11335 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11339 return print_insn (pc
, info
);
11343 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11347 return print_insn (pc
, info
);
11351 print_i386_disassembler_options (FILE *stream
)
11353 fprintf (stream
, _("\n\
11354 The following i386/x86-64 specific disassembler options are supported for use\n\
11355 with the -M switch (multiple options should be separated by commas):\n"));
11357 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11358 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11359 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11360 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11361 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11362 fprintf (stream
, _(" att-mnemonic\n"
11363 " Display instruction in AT&T mnemonic\n"));
11364 fprintf (stream
, _(" intel-mnemonic\n"
11365 " Display instruction in Intel mnemonic\n"));
11366 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11367 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11368 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11369 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11370 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11371 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11372 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11373 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11377 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11379 /* Get a pointer to struct dis386 with a valid name. */
11381 static const struct dis386
*
11382 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11384 int vindex
, vex_table_index
;
11386 if (dp
->name
!= NULL
)
11389 switch (dp
->op
[0].bytemode
)
11391 case USE_REG_TABLE
:
11392 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11395 case USE_MOD_TABLE
:
11396 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11397 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11401 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11404 case USE_PREFIX_TABLE
:
11407 /* The prefix in VEX is implicit. */
11408 switch (vex
.prefix
)
11413 case REPE_PREFIX_OPCODE
:
11416 case DATA_PREFIX_OPCODE
:
11419 case REPNE_PREFIX_OPCODE
:
11429 int last_prefix
= -1;
11432 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11433 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11435 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11437 if (last_repz_prefix
> last_repnz_prefix
)
11440 prefix
= PREFIX_REPZ
;
11441 last_prefix
= last_repz_prefix
;
11446 prefix
= PREFIX_REPNZ
;
11447 last_prefix
= last_repnz_prefix
;
11450 /* Check if prefix should be ignored. */
11451 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11452 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11457 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11460 prefix
= PREFIX_DATA
;
11461 last_prefix
= last_data_prefix
;
11466 used_prefixes
|= prefix
;
11467 all_prefixes
[last_prefix
] = 0;
11470 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11473 case USE_X86_64_TABLE
:
11474 vindex
= address_mode
== mode_64bit
? 1 : 0;
11475 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11478 case USE_3BYTE_TABLE
:
11479 FETCH_DATA (info
, codep
+ 2);
11481 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11483 modrm
.mod
= (*codep
>> 6) & 3;
11484 modrm
.reg
= (*codep
>> 3) & 7;
11485 modrm
.rm
= *codep
& 7;
11488 case USE_VEX_LEN_TABLE
:
11492 switch (vex
.length
)
11505 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11508 case USE_EVEX_LEN_TABLE
:
11512 switch (vex
.length
)
11528 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11531 case USE_XOP_8F_TABLE
:
11532 FETCH_DATA (info
, codep
+ 3);
11533 /* All bits in the REX prefix are ignored. */
11535 rex
= ~(*codep
>> 5) & 0x7;
11537 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11538 switch ((*codep
& 0x1f))
11544 vex_table_index
= XOP_08
;
11547 vex_table_index
= XOP_09
;
11550 vex_table_index
= XOP_0A
;
11554 vex
.w
= *codep
& 0x80;
11555 if (vex
.w
&& address_mode
== mode_64bit
)
11558 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11559 if (address_mode
!= mode_64bit
)
11561 /* In 16/32-bit mode REX_B is silently ignored. */
11565 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11566 switch ((*codep
& 0x3))
11571 vex
.prefix
= DATA_PREFIX_OPCODE
;
11574 vex
.prefix
= REPE_PREFIX_OPCODE
;
11577 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11584 dp
= &xop_table
[vex_table_index
][vindex
];
11587 FETCH_DATA (info
, codep
+ 1);
11588 modrm
.mod
= (*codep
>> 6) & 3;
11589 modrm
.reg
= (*codep
>> 3) & 7;
11590 modrm
.rm
= *codep
& 7;
11593 case USE_VEX_C4_TABLE
:
11595 FETCH_DATA (info
, codep
+ 3);
11596 /* All bits in the REX prefix are ignored. */
11598 rex
= ~(*codep
>> 5) & 0x7;
11599 switch ((*codep
& 0x1f))
11605 vex_table_index
= VEX_0F
;
11608 vex_table_index
= VEX_0F38
;
11611 vex_table_index
= VEX_0F3A
;
11615 vex
.w
= *codep
& 0x80;
11616 if (address_mode
== mode_64bit
)
11623 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11624 is ignored, other REX bits are 0 and the highest bit in
11625 VEX.vvvv is also ignored (but we mustn't clear it here). */
11628 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11629 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11630 switch ((*codep
& 0x3))
11635 vex
.prefix
= DATA_PREFIX_OPCODE
;
11638 vex
.prefix
= REPE_PREFIX_OPCODE
;
11641 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11648 dp
= &vex_table
[vex_table_index
][vindex
];
11650 /* There is no MODRM byte for VEX0F 77. */
11651 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11653 FETCH_DATA (info
, codep
+ 1);
11654 modrm
.mod
= (*codep
>> 6) & 3;
11655 modrm
.reg
= (*codep
>> 3) & 7;
11656 modrm
.rm
= *codep
& 7;
11660 case USE_VEX_C5_TABLE
:
11662 FETCH_DATA (info
, codep
+ 2);
11663 /* All bits in the REX prefix are ignored. */
11665 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11667 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11669 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11670 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11671 switch ((*codep
& 0x3))
11676 vex
.prefix
= DATA_PREFIX_OPCODE
;
11679 vex
.prefix
= REPE_PREFIX_OPCODE
;
11682 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11689 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11691 /* There is no MODRM byte for VEX 77. */
11692 if (vindex
!= 0x77)
11694 FETCH_DATA (info
, codep
+ 1);
11695 modrm
.mod
= (*codep
>> 6) & 3;
11696 modrm
.reg
= (*codep
>> 3) & 7;
11697 modrm
.rm
= *codep
& 7;
11701 case USE_VEX_W_TABLE
:
11705 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11708 case USE_EVEX_TABLE
:
11709 two_source_ops
= 0;
11712 FETCH_DATA (info
, codep
+ 4);
11713 /* All bits in the REX prefix are ignored. */
11715 /* The first byte after 0x62. */
11716 rex
= ~(*codep
>> 5) & 0x7;
11717 vex
.r
= *codep
& 0x10;
11718 switch ((*codep
& 0xf))
11721 return &bad_opcode
;
11723 vex_table_index
= EVEX_0F
;
11726 vex_table_index
= EVEX_0F38
;
11729 vex_table_index
= EVEX_0F3A
;
11733 /* The second byte after 0x62. */
11735 vex
.w
= *codep
& 0x80;
11736 if (vex
.w
&& address_mode
== mode_64bit
)
11739 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11742 if (!(*codep
& 0x4))
11743 return &bad_opcode
;
11745 switch ((*codep
& 0x3))
11750 vex
.prefix
= DATA_PREFIX_OPCODE
;
11753 vex
.prefix
= REPE_PREFIX_OPCODE
;
11756 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11760 /* The third byte after 0x62. */
11763 /* Remember the static rounding bits. */
11764 vex
.ll
= (*codep
>> 5) & 3;
11765 vex
.b
= (*codep
& 0x10) != 0;
11767 vex
.v
= *codep
& 0x8;
11768 vex
.mask_register_specifier
= *codep
& 0x7;
11769 vex
.zeroing
= *codep
& 0x80;
11771 if (address_mode
!= mode_64bit
)
11773 /* In 16/32-bit mode silently ignore following bits. */
11783 dp
= &evex_table
[vex_table_index
][vindex
];
11785 FETCH_DATA (info
, codep
+ 1);
11786 modrm
.mod
= (*codep
>> 6) & 3;
11787 modrm
.reg
= (*codep
>> 3) & 7;
11788 modrm
.rm
= *codep
& 7;
11790 /* Set vector length. */
11791 if (modrm
.mod
== 3 && vex
.b
)
11807 return &bad_opcode
;
11820 if (dp
->name
!= NULL
)
11823 return get_valid_dis386 (dp
, info
);
11827 get_sib (disassemble_info
*info
, int sizeflag
)
11829 /* If modrm.mod == 3, operand must be register. */
11831 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11835 FETCH_DATA (info
, codep
+ 2);
11836 sib
.index
= (codep
[1] >> 3) & 7;
11837 sib
.scale
= (codep
[1] >> 6) & 3;
11838 sib
.base
= codep
[1] & 7;
11843 print_insn (bfd_vma pc
, disassemble_info
*info
)
11845 const struct dis386
*dp
;
11847 char *op_txt
[MAX_OPERANDS
];
11849 int sizeflag
, orig_sizeflag
;
11851 struct dis_private priv
;
11854 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11855 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11856 address_mode
= mode_32bit
;
11857 else if (info
->mach
== bfd_mach_i386_i8086
)
11859 address_mode
= mode_16bit
;
11860 priv
.orig_sizeflag
= 0;
11863 address_mode
= mode_64bit
;
11865 if (intel_syntax
== (char) -1)
11866 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11868 for (p
= info
->disassembler_options
; p
!= NULL
; )
11870 if (CONST_STRNEQ (p
, "amd64"))
11872 else if (CONST_STRNEQ (p
, "intel64"))
11874 else if (CONST_STRNEQ (p
, "x86-64"))
11876 address_mode
= mode_64bit
;
11877 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11879 else if (CONST_STRNEQ (p
, "i386"))
11881 address_mode
= mode_32bit
;
11882 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11884 else if (CONST_STRNEQ (p
, "i8086"))
11886 address_mode
= mode_16bit
;
11887 priv
.orig_sizeflag
= 0;
11889 else if (CONST_STRNEQ (p
, "intel"))
11892 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11893 intel_mnemonic
= 1;
11895 else if (CONST_STRNEQ (p
, "att"))
11898 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11899 intel_mnemonic
= 0;
11901 else if (CONST_STRNEQ (p
, "addr"))
11903 if (address_mode
== mode_64bit
)
11905 if (p
[4] == '3' && p
[5] == '2')
11906 priv
.orig_sizeflag
&= ~AFLAG
;
11907 else if (p
[4] == '6' && p
[5] == '4')
11908 priv
.orig_sizeflag
|= AFLAG
;
11912 if (p
[4] == '1' && p
[5] == '6')
11913 priv
.orig_sizeflag
&= ~AFLAG
;
11914 else if (p
[4] == '3' && p
[5] == '2')
11915 priv
.orig_sizeflag
|= AFLAG
;
11918 else if (CONST_STRNEQ (p
, "data"))
11920 if (p
[4] == '1' && p
[5] == '6')
11921 priv
.orig_sizeflag
&= ~DFLAG
;
11922 else if (p
[4] == '3' && p
[5] == '2')
11923 priv
.orig_sizeflag
|= DFLAG
;
11925 else if (CONST_STRNEQ (p
, "suffix"))
11926 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11928 p
= strchr (p
, ',');
11933 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11935 (*info
->fprintf_func
) (info
->stream
,
11936 _("64-bit address is disabled"));
11942 names64
= intel_names64
;
11943 names32
= intel_names32
;
11944 names16
= intel_names16
;
11945 names8
= intel_names8
;
11946 names8rex
= intel_names8rex
;
11947 names_seg
= intel_names_seg
;
11948 names_mm
= intel_names_mm
;
11949 names_bnd
= intel_names_bnd
;
11950 names_xmm
= intel_names_xmm
;
11951 names_ymm
= intel_names_ymm
;
11952 names_zmm
= intel_names_zmm
;
11953 index64
= intel_index64
;
11954 index32
= intel_index32
;
11955 names_mask
= intel_names_mask
;
11956 index16
= intel_index16
;
11959 separator_char
= '+';
11964 names64
= att_names64
;
11965 names32
= att_names32
;
11966 names16
= att_names16
;
11967 names8
= att_names8
;
11968 names8rex
= att_names8rex
;
11969 names_seg
= att_names_seg
;
11970 names_mm
= att_names_mm
;
11971 names_bnd
= att_names_bnd
;
11972 names_xmm
= att_names_xmm
;
11973 names_ymm
= att_names_ymm
;
11974 names_zmm
= att_names_zmm
;
11975 index64
= att_index64
;
11976 index32
= att_index32
;
11977 names_mask
= att_names_mask
;
11978 index16
= att_index16
;
11981 separator_char
= ',';
11985 /* The output looks better if we put 7 bytes on a line, since that
11986 puts most long word instructions on a single line. Use 8 bytes
11988 if ((info
->mach
& bfd_mach_l1om
) != 0)
11989 info
->bytes_per_line
= 8;
11991 info
->bytes_per_line
= 7;
11993 info
->private_data
= &priv
;
11994 priv
.max_fetched
= priv
.the_buffer
;
11995 priv
.insn_start
= pc
;
11998 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12006 start_codep
= priv
.the_buffer
;
12007 codep
= priv
.the_buffer
;
12009 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12013 /* Getting here means we tried for data but didn't get it. That
12014 means we have an incomplete instruction of some sort. Just
12015 print the first byte as a prefix or a .byte pseudo-op. */
12016 if (codep
> priv
.the_buffer
)
12018 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12020 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12023 /* Just print the first byte as a .byte instruction. */
12024 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12025 (unsigned int) priv
.the_buffer
[0]);
12035 sizeflag
= priv
.orig_sizeflag
;
12037 if (!ckprefix () || rex_used
)
12039 /* Too many prefixes or unused REX prefixes. */
12041 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12043 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12045 prefix_name (all_prefixes
[i
], sizeflag
));
12049 insn_codep
= codep
;
12051 FETCH_DATA (info
, codep
+ 1);
12052 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12054 if (((prefixes
& PREFIX_FWAIT
)
12055 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12057 /* Handle prefixes before fwait. */
12058 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12060 (*info
->fprintf_func
) (info
->stream
, "%s ",
12061 prefix_name (all_prefixes
[i
], sizeflag
));
12062 (*info
->fprintf_func
) (info
->stream
, "fwait");
12066 if (*codep
== 0x0f)
12068 unsigned char threebyte
;
12071 FETCH_DATA (info
, codep
+ 1);
12072 threebyte
= *codep
;
12073 dp
= &dis386_twobyte
[threebyte
];
12074 need_modrm
= twobyte_has_modrm
[*codep
];
12079 dp
= &dis386
[*codep
];
12080 need_modrm
= onebyte_has_modrm
[*codep
];
12084 /* Save sizeflag for printing the extra prefixes later before updating
12085 it for mnemonic and operand processing. The prefix names depend
12086 only on the address mode. */
12087 orig_sizeflag
= sizeflag
;
12088 if (prefixes
& PREFIX_ADDR
)
12090 if ((prefixes
& PREFIX_DATA
))
12096 FETCH_DATA (info
, codep
+ 1);
12097 modrm
.mod
= (*codep
>> 6) & 3;
12098 modrm
.reg
= (*codep
>> 3) & 7;
12099 modrm
.rm
= *codep
& 7;
12105 memset (&vex
, 0, sizeof (vex
));
12107 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12109 get_sib (info
, sizeflag
);
12110 dofloat (sizeflag
);
12114 dp
= get_valid_dis386 (dp
, info
);
12115 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12117 get_sib (info
, sizeflag
);
12118 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12121 op_ad
= MAX_OPERANDS
- 1 - i
;
12123 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12124 /* For EVEX instruction after the last operand masking
12125 should be printed. */
12126 if (i
== 0 && vex
.evex
)
12128 /* Don't print {%k0}. */
12129 if (vex
.mask_register_specifier
)
12132 oappend (names_mask
[vex
.mask_register_specifier
]);
12142 /* Check if the REX prefix is used. */
12143 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12144 all_prefixes
[last_rex_prefix
] = 0;
12146 /* Check if the SEG prefix is used. */
12147 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12148 | PREFIX_FS
| PREFIX_GS
)) != 0
12149 && (used_prefixes
& active_seg_prefix
) != 0)
12150 all_prefixes
[last_seg_prefix
] = 0;
12152 /* Check if the ADDR prefix is used. */
12153 if ((prefixes
& PREFIX_ADDR
) != 0
12154 && (used_prefixes
& PREFIX_ADDR
) != 0)
12155 all_prefixes
[last_addr_prefix
] = 0;
12157 /* Check if the DATA prefix is used. */
12158 if ((prefixes
& PREFIX_DATA
) != 0
12159 && (used_prefixes
& PREFIX_DATA
) != 0)
12160 all_prefixes
[last_data_prefix
] = 0;
12162 /* Print the extra prefixes. */
12164 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12165 if (all_prefixes
[i
])
12168 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12171 prefix_length
+= strlen (name
) + 1;
12172 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12175 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12176 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12177 used by putop and MMX/SSE operand and may be overriden by the
12178 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12180 if (dp
->prefix_requirement
== PREFIX_OPCODE
12181 && dp
!= &bad_opcode
12183 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12185 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12187 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12189 && (used_prefixes
& PREFIX_DATA
) == 0))))
12191 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12192 return end_codep
- priv
.the_buffer
;
12195 /* Check maximum code length. */
12196 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12198 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12199 return MAX_CODE_LENGTH
;
12202 obufp
= mnemonicendp
;
12203 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12206 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12208 /* The enter and bound instructions are printed with operands in the same
12209 order as the intel book; everything else is printed in reverse order. */
12210 if (intel_syntax
|| two_source_ops
)
12214 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12215 op_txt
[i
] = op_out
[i
];
12217 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12218 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12220 op_txt
[2] = op_out
[3];
12221 op_txt
[3] = op_out
[2];
12224 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12226 op_ad
= op_index
[i
];
12227 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12228 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12229 riprel
= op_riprel
[i
];
12230 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12231 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12236 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12237 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12241 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12245 (*info
->fprintf_func
) (info
->stream
, ",");
12246 if (op_index
[i
] != -1 && !op_riprel
[i
])
12247 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
12249 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12253 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12254 if (op_index
[i
] != -1 && op_riprel
[i
])
12256 (*info
->fprintf_func
) (info
->stream
, " # ");
12257 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12258 + op_address
[op_index
[i
]]), info
);
12261 return codep
- priv
.the_buffer
;
12264 static const char *float_mem
[] = {
12339 static const unsigned char float_mem_mode
[] = {
12414 #define ST { OP_ST, 0 }
12415 #define STi { OP_STi, 0 }
12417 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12418 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12419 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12420 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12421 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12422 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12423 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12424 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12425 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12427 static const struct dis386 float_reg
[][8] = {
12430 { "fadd", { ST
, STi
}, 0 },
12431 { "fmul", { ST
, STi
}, 0 },
12432 { "fcom", { STi
}, 0 },
12433 { "fcomp", { STi
}, 0 },
12434 { "fsub", { ST
, STi
}, 0 },
12435 { "fsubr", { ST
, STi
}, 0 },
12436 { "fdiv", { ST
, STi
}, 0 },
12437 { "fdivr", { ST
, STi
}, 0 },
12441 { "fld", { STi
}, 0 },
12442 { "fxch", { STi
}, 0 },
12452 { "fcmovb", { ST
, STi
}, 0 },
12453 { "fcmove", { ST
, STi
}, 0 },
12454 { "fcmovbe",{ ST
, STi
}, 0 },
12455 { "fcmovu", { ST
, STi
}, 0 },
12463 { "fcmovnb",{ ST
, STi
}, 0 },
12464 { "fcmovne",{ ST
, STi
}, 0 },
12465 { "fcmovnbe",{ ST
, STi
}, 0 },
12466 { "fcmovnu",{ ST
, STi
}, 0 },
12468 { "fucomi", { ST
, STi
}, 0 },
12469 { "fcomi", { ST
, STi
}, 0 },
12474 { "fadd", { STi
, ST
}, 0 },
12475 { "fmul", { STi
, ST
}, 0 },
12478 { "fsub{!M|r}", { STi
, ST
}, 0 },
12479 { "fsub{M|}", { STi
, ST
}, 0 },
12480 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12481 { "fdiv{M|}", { STi
, ST
}, 0 },
12485 { "ffree", { STi
}, 0 },
12487 { "fst", { STi
}, 0 },
12488 { "fstp", { STi
}, 0 },
12489 { "fucom", { STi
}, 0 },
12490 { "fucomp", { STi
}, 0 },
12496 { "faddp", { STi
, ST
}, 0 },
12497 { "fmulp", { STi
, ST
}, 0 },
12500 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12501 { "fsub{M|}p", { STi
, ST
}, 0 },
12502 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12503 { "fdiv{M|}p", { STi
, ST
}, 0 },
12507 { "ffreep", { STi
}, 0 },
12512 { "fucomip", { ST
, STi
}, 0 },
12513 { "fcomip", { ST
, STi
}, 0 },
12518 static char *fgrps
[][8] = {
12521 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12526 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12531 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12536 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12541 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12546 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12551 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12556 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12557 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12562 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12567 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12572 swap_operand (void)
12574 mnemonicendp
[0] = '.';
12575 mnemonicendp
[1] = 's';
12580 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12581 int sizeflag ATTRIBUTE_UNUSED
)
12583 /* Skip mod/rm byte. */
12589 dofloat (int sizeflag
)
12591 const struct dis386
*dp
;
12592 unsigned char floatop
;
12594 floatop
= codep
[-1];
12596 if (modrm
.mod
!= 3)
12598 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12600 putop (float_mem
[fp_indx
], sizeflag
);
12603 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12606 /* Skip mod/rm byte. */
12610 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12611 if (dp
->name
== NULL
)
12613 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12615 /* Instruction fnstsw is only one with strange arg. */
12616 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12617 strcpy (op_out
[0], names16
[0]);
12621 putop (dp
->name
, sizeflag
);
12626 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12631 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12635 /* Like oappend (below), but S is a string starting with '%'.
12636 In Intel syntax, the '%' is elided. */
12638 oappend_maybe_intel (const char *s
)
12640 oappend (s
+ intel_syntax
);
12644 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12646 oappend_maybe_intel ("%st");
12650 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12652 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12653 oappend_maybe_intel (scratchbuf
);
12656 /* Capital letters in template are macros. */
12658 putop (const char *in_template
, int sizeflag
)
12663 unsigned int l
= 0, len
= 1;
12666 #define SAVE_LAST(c) \
12667 if (l < len && l < sizeof (last)) \
12672 for (p
= in_template
; *p
; p
++)
12688 while (*++p
!= '|')
12689 if (*p
== '}' || *p
== '\0')
12692 /* Fall through. */
12697 while (*++p
!= '}')
12708 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12712 if (l
== 0 && len
== 1)
12717 if (sizeflag
& SUFFIX_ALWAYS
)
12730 if (address_mode
== mode_64bit
12731 && !(prefixes
& PREFIX_ADDR
))
12742 if (intel_syntax
&& !alt
)
12744 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12746 if (sizeflag
& DFLAG
)
12747 *obufp
++ = intel_syntax
? 'd' : 'l';
12749 *obufp
++ = intel_syntax
? 'w' : 's';
12750 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12754 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12757 if (modrm
.mod
== 3)
12763 if (sizeflag
& DFLAG
)
12764 *obufp
++ = intel_syntax
? 'd' : 'l';
12767 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12773 case 'E': /* For jcxz/jecxz */
12774 if (address_mode
== mode_64bit
)
12776 if (sizeflag
& AFLAG
)
12782 if (sizeflag
& AFLAG
)
12784 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12789 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12791 if (sizeflag
& AFLAG
)
12792 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12794 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12795 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12799 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12801 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12805 if (!(rex
& REX_W
))
12806 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12811 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12812 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12814 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12817 if (prefixes
& PREFIX_DS
)
12836 if (l
!= 0 || len
!= 1)
12838 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12843 if (!need_vex
|| !vex
.evex
)
12846 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12848 switch (vex
.length
)
12866 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12871 /* Fall through. */
12874 if (l
!= 0 || len
!= 1)
12882 if (sizeflag
& SUFFIX_ALWAYS
)
12886 if (intel_mnemonic
!= cond
)
12890 if ((prefixes
& PREFIX_FWAIT
) == 0)
12893 used_prefixes
|= PREFIX_FWAIT
;
12899 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12903 if (!(rex
& REX_W
))
12904 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12908 && address_mode
== mode_64bit
12909 && isa64
== intel64
)
12914 /* Fall through. */
12917 && address_mode
== mode_64bit
12918 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12923 /* Fall through. */
12926 if (l
== 0 && len
== 1)
12931 if ((rex
& REX_W
) == 0
12932 && (prefixes
& PREFIX_DATA
))
12934 if ((sizeflag
& DFLAG
) == 0)
12936 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12940 if ((prefixes
& PREFIX_DATA
)
12942 || (sizeflag
& SUFFIX_ALWAYS
))
12949 if (sizeflag
& DFLAG
)
12953 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12959 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12965 if ((prefixes
& PREFIX_DATA
)
12967 || (sizeflag
& SUFFIX_ALWAYS
))
12974 if (sizeflag
& DFLAG
)
12975 *obufp
++ = intel_syntax
? 'd' : 'l';
12978 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12986 if (address_mode
== mode_64bit
12987 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12989 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12993 /* Fall through. */
12996 if (l
== 0 && len
== 1)
12999 if (intel_syntax
&& !alt
)
13002 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13008 if (sizeflag
& DFLAG
)
13009 *obufp
++ = intel_syntax
? 'd' : 'l';
13012 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13018 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13024 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13039 else if (sizeflag
& DFLAG
)
13048 if (intel_syntax
&& !p
[1]
13049 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13051 if (!(rex
& REX_W
))
13052 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13055 if (l
== 0 && len
== 1)
13059 if (address_mode
== mode_64bit
13060 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13062 if (sizeflag
& SUFFIX_ALWAYS
)
13084 /* Fall through. */
13087 if (l
== 0 && len
== 1)
13092 if (sizeflag
& SUFFIX_ALWAYS
)
13098 if (sizeflag
& DFLAG
)
13102 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13116 if (address_mode
== mode_64bit
13117 && !(prefixes
& PREFIX_ADDR
))
13128 if (l
!= 0 || len
!= 1)
13133 if (need_vex
&& vex
.prefix
)
13135 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13142 if (prefixes
& PREFIX_DATA
)
13146 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13150 if (l
== 0 && len
== 1)
13154 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13162 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13164 switch (vex
.length
)
13180 if (l
== 0 && len
== 1)
13182 /* operand size flag for cwtl, cbtw */
13191 else if (sizeflag
& DFLAG
)
13195 if (!(rex
& REX_W
))
13196 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13203 && last
[0] != 'L'))
13210 if (last
[0] == 'X')
13211 *obufp
++ = vex
.w
? 'd': 's';
13213 *obufp
++ = vex
.w
? 'q': 'd';
13219 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13221 if (sizeflag
& DFLAG
)
13225 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13231 if (address_mode
== mode_64bit
13232 && (isa64
== intel64
13233 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13235 else if ((prefixes
& PREFIX_DATA
))
13237 if (!(sizeflag
& DFLAG
))
13239 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13246 mnemonicendp
= obufp
;
13251 oappend (const char *s
)
13253 obufp
= stpcpy (obufp
, s
);
13259 /* Only print the active segment register. */
13260 if (!active_seg_prefix
)
13263 used_prefixes
|= active_seg_prefix
;
13264 switch (active_seg_prefix
)
13267 oappend_maybe_intel ("%cs:");
13270 oappend_maybe_intel ("%ds:");
13273 oappend_maybe_intel ("%ss:");
13276 oappend_maybe_intel ("%es:");
13279 oappend_maybe_intel ("%fs:");
13282 oappend_maybe_intel ("%gs:");
13290 OP_indirE (int bytemode
, int sizeflag
)
13294 OP_E (bytemode
, sizeflag
);
13298 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13300 if (address_mode
== mode_64bit
)
13308 sprintf_vma (tmp
, disp
);
13309 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13310 strcpy (buf
+ 2, tmp
+ i
);
13314 bfd_signed_vma v
= disp
;
13321 /* Check for possible overflow on 0x8000000000000000. */
13324 strcpy (buf
, "9223372036854775808");
13338 tmp
[28 - i
] = (v
% 10) + '0';
13342 strcpy (buf
, tmp
+ 29 - i
);
13348 sprintf (buf
, "0x%x", (unsigned int) disp
);
13350 sprintf (buf
, "%d", (int) disp
);
13354 /* Put DISP in BUF as signed hex number. */
13357 print_displacement (char *buf
, bfd_vma disp
)
13359 bfd_signed_vma val
= disp
;
13368 /* Check for possible overflow. */
13371 switch (address_mode
)
13374 strcpy (buf
+ j
, "0x8000000000000000");
13377 strcpy (buf
+ j
, "0x80000000");
13380 strcpy (buf
+ j
, "0x8000");
13390 sprintf_vma (tmp
, (bfd_vma
) val
);
13391 for (i
= 0; tmp
[i
] == '0'; i
++)
13393 if (tmp
[i
] == '\0')
13395 strcpy (buf
+ j
, tmp
+ i
);
13399 intel_operand_size (int bytemode
, int sizeflag
)
13403 && (bytemode
== x_mode
13404 || bytemode
== evex_half_bcst_xmmq_mode
))
13407 oappend ("QWORD PTR ");
13409 oappend ("DWORD PTR ");
13418 oappend ("BYTE PTR ");
13423 oappend ("WORD PTR ");
13426 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13428 oappend ("QWORD PTR ");
13431 /* Fall through. */
13433 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13435 oappend ("QWORD PTR ");
13438 /* Fall through. */
13444 oappend ("QWORD PTR ");
13447 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13448 oappend ("DWORD PTR ");
13450 oappend ("WORD PTR ");
13451 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13455 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13457 oappend ("WORD PTR ");
13458 if (!(rex
& REX_W
))
13459 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13462 if (sizeflag
& DFLAG
)
13463 oappend ("QWORD PTR ");
13465 oappend ("DWORD PTR ");
13466 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13469 case d_scalar_mode
:
13470 case d_scalar_swap_mode
:
13473 oappend ("DWORD PTR ");
13476 case q_scalar_mode
:
13477 case q_scalar_swap_mode
:
13479 oappend ("QWORD PTR ");
13483 if (address_mode
== mode_64bit
)
13484 oappend ("QWORD PTR ");
13486 oappend ("DWORD PTR ");
13489 if (sizeflag
& DFLAG
)
13490 oappend ("FWORD PTR ");
13492 oappend ("DWORD PTR ");
13493 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13496 oappend ("TBYTE PTR ");
13500 case evex_x_gscat_mode
:
13501 case evex_x_nobcst_mode
:
13502 case b_scalar_mode
:
13503 case w_scalar_mode
:
13506 switch (vex
.length
)
13509 oappend ("XMMWORD PTR ");
13512 oappend ("YMMWORD PTR ");
13515 oappend ("ZMMWORD PTR ");
13522 oappend ("XMMWORD PTR ");
13525 oappend ("XMMWORD PTR ");
13528 oappend ("YMMWORD PTR ");
13531 case evex_half_bcst_xmmq_mode
:
13535 switch (vex
.length
)
13538 oappend ("QWORD PTR ");
13541 oappend ("XMMWORD PTR ");
13544 oappend ("YMMWORD PTR ");
13554 switch (vex
.length
)
13559 oappend ("BYTE PTR ");
13569 switch (vex
.length
)
13574 oappend ("WORD PTR ");
13584 switch (vex
.length
)
13589 oappend ("DWORD PTR ");
13599 switch (vex
.length
)
13604 oappend ("QWORD PTR ");
13614 switch (vex
.length
)
13617 oappend ("WORD PTR ");
13620 oappend ("DWORD PTR ");
13623 oappend ("QWORD PTR ");
13633 switch (vex
.length
)
13636 oappend ("DWORD PTR ");
13639 oappend ("QWORD PTR ");
13642 oappend ("XMMWORD PTR ");
13652 switch (vex
.length
)
13655 oappend ("QWORD PTR ");
13658 oappend ("YMMWORD PTR ");
13661 oappend ("ZMMWORD PTR ");
13671 switch (vex
.length
)
13675 oappend ("XMMWORD PTR ");
13682 oappend ("OWORD PTR ");
13685 case vex_w_dq_mode
:
13686 case vex_scalar_w_dq_mode
:
13691 oappend ("QWORD PTR ");
13693 oappend ("DWORD PTR ");
13695 case vex_vsib_d_w_dq_mode
:
13696 case vex_vsib_q_w_dq_mode
:
13703 oappend ("QWORD PTR ");
13705 oappend ("DWORD PTR ");
13709 switch (vex
.length
)
13712 oappend ("XMMWORD PTR ");
13715 oappend ("YMMWORD PTR ");
13718 oappend ("ZMMWORD PTR ");
13725 case vex_vsib_q_w_d_mode
:
13726 case vex_vsib_d_w_d_mode
:
13727 if (!need_vex
|| !vex
.evex
)
13730 switch (vex
.length
)
13733 oappend ("QWORD PTR ");
13736 oappend ("XMMWORD PTR ");
13739 oappend ("YMMWORD PTR ");
13747 if (!need_vex
|| vex
.length
!= 128)
13750 oappend ("DWORD PTR ");
13752 oappend ("BYTE PTR ");
13758 oappend ("QWORD PTR ");
13760 oappend ("WORD PTR ");
13770 OP_E_register (int bytemode
, int sizeflag
)
13772 int reg
= modrm
.rm
;
13773 const char **names
;
13779 if ((sizeflag
& SUFFIX_ALWAYS
)
13780 && (bytemode
== b_swap_mode
13781 || bytemode
== bnd_swap_mode
13782 || bytemode
== v_swap_mode
))
13808 names
= address_mode
== mode_64bit
? names64
: names32
;
13811 case bnd_swap_mode
:
13820 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13825 /* Fall through. */
13827 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13833 /* Fall through. */
13846 if ((sizeflag
& DFLAG
)
13847 || (bytemode
!= v_mode
13848 && bytemode
!= v_swap_mode
))
13852 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13856 names
= (address_mode
== mode_64bit
13857 ? names64
: names32
);
13858 if (!(prefixes
& PREFIX_ADDR
))
13859 names
= (address_mode
== mode_16bit
13860 ? names16
: names
);
13863 /* Remove "addr16/addr32". */
13864 all_prefixes
[last_addr_prefix
] = 0;
13865 names
= (address_mode
!= mode_32bit
13866 ? names32
: names16
);
13867 used_prefixes
|= PREFIX_ADDR
;
13877 names
= names_mask
;
13882 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13885 oappend (names
[reg
]);
13889 OP_E_memory (int bytemode
, int sizeflag
)
13892 int add
= (rex
& REX_B
) ? 8 : 0;
13898 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13900 && bytemode
!= x_mode
13901 && bytemode
!= xmmq_mode
13902 && bytemode
!= evex_half_bcst_xmmq_mode
)
13918 if (address_mode
!= mode_64bit
)
13924 case vex_vsib_d_w_dq_mode
:
13925 case vex_vsib_d_w_d_mode
:
13926 case vex_vsib_q_w_dq_mode
:
13927 case vex_vsib_q_w_d_mode
:
13928 case evex_x_gscat_mode
:
13930 shift
= vex
.w
? 3 : 2;
13933 case evex_half_bcst_xmmq_mode
:
13937 shift
= vex
.w
? 3 : 2;
13940 /* Fall through. */
13944 case evex_x_nobcst_mode
:
13946 switch (vex
.length
)
13969 case q_scalar_mode
:
13971 case q_scalar_swap_mode
:
13977 case d_scalar_mode
:
13979 case d_scalar_swap_mode
:
13982 case w_scalar_mode
:
13986 case b_scalar_mode
:
13991 shift
= address_mode
== mode_64bit
? 3 : 2;
13996 /* Make necessary corrections to shift for modes that need it.
13997 For these modes we currently have shift 4, 5 or 6 depending on
13998 vex.length (it corresponds to xmmword, ymmword or zmmword
13999 operand). We might want to make it 3, 4 or 5 (e.g. for
14000 xmmq_mode). In case of broadcast enabled the corrections
14001 aren't needed, as element size is always 32 or 64 bits. */
14003 && (bytemode
== xmmq_mode
14004 || bytemode
== evex_half_bcst_xmmq_mode
))
14006 else if (bytemode
== xmmqd_mode
)
14008 else if (bytemode
== xmmdw_mode
)
14010 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14018 intel_operand_size (bytemode
, sizeflag
);
14021 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14023 /* 32/64 bit address mode */
14033 int addr32flag
= !((sizeflag
& AFLAG
)
14034 || bytemode
== v_bnd_mode
14035 || bytemode
== v_bndmk_mode
14036 || bytemode
== bnd_mode
14037 || bytemode
== bnd_swap_mode
);
14038 const char **indexes64
= names64
;
14039 const char **indexes32
= names32
;
14049 vindex
= sib
.index
;
14055 case vex_vsib_d_w_dq_mode
:
14056 case vex_vsib_d_w_d_mode
:
14057 case vex_vsib_q_w_dq_mode
:
14058 case vex_vsib_q_w_d_mode
:
14068 switch (vex
.length
)
14071 indexes64
= indexes32
= names_xmm
;
14075 || bytemode
== vex_vsib_q_w_dq_mode
14076 || bytemode
== vex_vsib_q_w_d_mode
)
14077 indexes64
= indexes32
= names_ymm
;
14079 indexes64
= indexes32
= names_xmm
;
14083 || bytemode
== vex_vsib_q_w_dq_mode
14084 || bytemode
== vex_vsib_q_w_d_mode
)
14085 indexes64
= indexes32
= names_zmm
;
14087 indexes64
= indexes32
= names_ymm
;
14094 haveindex
= vindex
!= 4;
14101 rbase
= base
+ add
;
14109 if (address_mode
== mode_64bit
&& !havesib
)
14112 if (riprel
&& bytemode
== v_bndmk_mode
)
14120 FETCH_DATA (the_info
, codep
+ 1);
14122 if ((disp
& 0x80) != 0)
14124 if (vex
.evex
&& shift
> 0)
14137 && address_mode
!= mode_16bit
)
14139 if (address_mode
== mode_64bit
)
14141 /* Display eiz instead of addr32. */
14142 needindex
= addr32flag
;
14147 /* In 32-bit mode, we need index register to tell [offset]
14148 from [eiz*1 + offset]. */
14153 havedisp
= (havebase
14155 || (havesib
&& (haveindex
|| scale
!= 0)));
14158 if (modrm
.mod
!= 0 || base
== 5)
14160 if (havedisp
|| riprel
)
14161 print_displacement (scratchbuf
, disp
);
14163 print_operand_value (scratchbuf
, 1, disp
);
14164 oappend (scratchbuf
);
14168 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14172 if ((havebase
|| haveindex
|| needaddr32
|| riprel
)
14173 && (bytemode
!= v_bnd_mode
)
14174 && (bytemode
!= v_bndmk_mode
)
14175 && (bytemode
!= bnd_mode
)
14176 && (bytemode
!= bnd_swap_mode
))
14177 used_prefixes
|= PREFIX_ADDR
;
14179 if (havedisp
|| (intel_syntax
&& riprel
))
14181 *obufp
++ = open_char
;
14182 if (intel_syntax
&& riprel
)
14185 oappend (!addr32flag
? "rip" : "eip");
14189 oappend (address_mode
== mode_64bit
&& !addr32flag
14190 ? names64
[rbase
] : names32
[rbase
]);
14193 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14194 print index to tell base + index from base. */
14198 || (havebase
&& base
!= ESP_REG_NUM
))
14200 if (!intel_syntax
|| havebase
)
14202 *obufp
++ = separator_char
;
14206 oappend (address_mode
== mode_64bit
&& !addr32flag
14207 ? indexes64
[vindex
] : indexes32
[vindex
]);
14209 oappend (address_mode
== mode_64bit
&& !addr32flag
14210 ? index64
: index32
);
14212 *obufp
++ = scale_char
;
14214 sprintf (scratchbuf
, "%d", 1 << scale
);
14215 oappend (scratchbuf
);
14219 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14221 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14226 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14230 disp
= - (bfd_signed_vma
) disp
;
14234 print_displacement (scratchbuf
, disp
);
14236 print_operand_value (scratchbuf
, 1, disp
);
14237 oappend (scratchbuf
);
14240 *obufp
++ = close_char
;
14243 else if (intel_syntax
)
14245 if (modrm
.mod
!= 0 || base
== 5)
14247 if (!active_seg_prefix
)
14249 oappend (names_seg
[ds_reg
- es_reg
]);
14252 print_operand_value (scratchbuf
, 1, disp
);
14253 oappend (scratchbuf
);
14259 /* 16 bit address mode */
14260 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14267 if ((disp
& 0x8000) != 0)
14272 FETCH_DATA (the_info
, codep
+ 1);
14274 if ((disp
& 0x80) != 0)
14276 if (vex
.evex
&& shift
> 0)
14281 if ((disp
& 0x8000) != 0)
14287 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14289 print_displacement (scratchbuf
, disp
);
14290 oappend (scratchbuf
);
14293 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14295 *obufp
++ = open_char
;
14297 oappend (index16
[modrm
.rm
]);
14299 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14301 if ((bfd_signed_vma
) disp
>= 0)
14306 else if (modrm
.mod
!= 1)
14310 disp
= - (bfd_signed_vma
) disp
;
14313 print_displacement (scratchbuf
, disp
);
14314 oappend (scratchbuf
);
14317 *obufp
++ = close_char
;
14320 else if (intel_syntax
)
14322 if (!active_seg_prefix
)
14324 oappend (names_seg
[ds_reg
- es_reg
]);
14327 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14328 oappend (scratchbuf
);
14331 if (vex
.evex
&& vex
.b
14332 && (bytemode
== x_mode
14333 || bytemode
== xmmq_mode
14334 || bytemode
== evex_half_bcst_xmmq_mode
))
14337 || bytemode
== xmmq_mode
14338 || bytemode
== evex_half_bcst_xmmq_mode
)
14340 switch (vex
.length
)
14343 oappend ("{1to2}");
14346 oappend ("{1to4}");
14349 oappend ("{1to8}");
14357 switch (vex
.length
)
14360 oappend ("{1to4}");
14363 oappend ("{1to8}");
14366 oappend ("{1to16}");
14376 OP_E (int bytemode
, int sizeflag
)
14378 /* Skip mod/rm byte. */
14382 if (modrm
.mod
== 3)
14383 OP_E_register (bytemode
, sizeflag
);
14385 OP_E_memory (bytemode
, sizeflag
);
14389 OP_G (int bytemode
, int sizeflag
)
14392 const char **names
;
14401 oappend (names8rex
[modrm
.reg
+ add
]);
14403 oappend (names8
[modrm
.reg
+ add
]);
14406 oappend (names16
[modrm
.reg
+ add
]);
14411 oappend (names32
[modrm
.reg
+ add
]);
14414 oappend (names64
[modrm
.reg
+ add
]);
14417 if (modrm
.reg
> 0x3)
14422 oappend (names_bnd
[modrm
.reg
]);
14431 oappend (names64
[modrm
.reg
+ add
]);
14434 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
14435 oappend (names32
[modrm
.reg
+ add
]);
14437 oappend (names16
[modrm
.reg
+ add
]);
14438 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14442 names
= (address_mode
== mode_64bit
14443 ? names64
: names32
);
14444 if (!(prefixes
& PREFIX_ADDR
))
14446 if (address_mode
== mode_16bit
)
14451 /* Remove "addr16/addr32". */
14452 all_prefixes
[last_addr_prefix
] = 0;
14453 names
= (address_mode
!= mode_32bit
14454 ? names32
: names16
);
14455 used_prefixes
|= PREFIX_ADDR
;
14457 oappend (names
[modrm
.reg
+ add
]);
14460 if (address_mode
== mode_64bit
)
14461 oappend (names64
[modrm
.reg
+ add
]);
14463 oappend (names32
[modrm
.reg
+ add
]);
14467 if ((modrm
.reg
+ add
) > 0x7)
14472 oappend (names_mask
[modrm
.reg
+ add
]);
14475 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14488 FETCH_DATA (the_info
, codep
+ 8);
14489 a
= *codep
++ & 0xff;
14490 a
|= (*codep
++ & 0xff) << 8;
14491 a
|= (*codep
++ & 0xff) << 16;
14492 a
|= (*codep
++ & 0xffu
) << 24;
14493 b
= *codep
++ & 0xff;
14494 b
|= (*codep
++ & 0xff) << 8;
14495 b
|= (*codep
++ & 0xff) << 16;
14496 b
|= (*codep
++ & 0xffu
) << 24;
14497 x
= a
+ ((bfd_vma
) b
<< 32);
14505 static bfd_signed_vma
14508 bfd_signed_vma x
= 0;
14510 FETCH_DATA (the_info
, codep
+ 4);
14511 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14512 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14513 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14514 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14518 static bfd_signed_vma
14521 bfd_signed_vma x
= 0;
14523 FETCH_DATA (the_info
, codep
+ 4);
14524 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14525 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14526 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14527 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14529 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14539 FETCH_DATA (the_info
, codep
+ 2);
14540 x
= *codep
++ & 0xff;
14541 x
|= (*codep
++ & 0xff) << 8;
14546 set_op (bfd_vma op
, int riprel
)
14548 op_index
[op_ad
] = op_ad
;
14549 if (address_mode
== mode_64bit
)
14551 op_address
[op_ad
] = op
;
14552 op_riprel
[op_ad
] = riprel
;
14556 /* Mask to get a 32-bit address. */
14557 op_address
[op_ad
] = op
& 0xffffffff;
14558 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14563 OP_REG (int code
, int sizeflag
)
14570 case es_reg
: case ss_reg
: case cs_reg
:
14571 case ds_reg
: case fs_reg
: case gs_reg
:
14572 oappend (names_seg
[code
- es_reg
]);
14584 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14585 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14586 s
= names16
[code
- ax_reg
+ add
];
14588 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14589 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14592 s
= names8rex
[code
- al_reg
+ add
];
14594 s
= names8
[code
- al_reg
];
14596 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14597 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14598 if (address_mode
== mode_64bit
14599 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14601 s
= names64
[code
- rAX_reg
+ add
];
14604 code
+= eAX_reg
- rAX_reg
;
14605 /* Fall through. */
14606 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14607 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14610 s
= names64
[code
- eAX_reg
+ add
];
14613 if (sizeflag
& DFLAG
)
14614 s
= names32
[code
- eAX_reg
+ add
];
14616 s
= names16
[code
- eAX_reg
+ add
];
14617 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14621 s
= INTERNAL_DISASSEMBLER_ERROR
;
14628 OP_IMREG (int code
, int sizeflag
)
14640 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14641 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14642 s
= names16
[code
- ax_reg
];
14644 case es_reg
: case ss_reg
: case cs_reg
:
14645 case ds_reg
: case fs_reg
: case gs_reg
:
14646 s
= names_seg
[code
- es_reg
];
14648 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14649 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14652 s
= names8rex
[code
- al_reg
];
14654 s
= names8
[code
- al_reg
];
14656 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14657 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14660 s
= names64
[code
- eAX_reg
];
14663 if (sizeflag
& DFLAG
)
14664 s
= names32
[code
- eAX_reg
];
14666 s
= names16
[code
- eAX_reg
];
14667 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14670 case z_mode_ax_reg
:
14671 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14675 if (!(rex
& REX_W
))
14676 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14679 s
= INTERNAL_DISASSEMBLER_ERROR
;
14686 OP_I (int bytemode
, int sizeflag
)
14689 bfd_signed_vma mask
= -1;
14694 FETCH_DATA (the_info
, codep
+ 1);
14699 if (address_mode
== mode_64bit
)
14704 /* Fall through. */
14711 if (sizeflag
& DFLAG
)
14721 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14733 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14738 scratchbuf
[0] = '$';
14739 print_operand_value (scratchbuf
+ 1, 1, op
);
14740 oappend_maybe_intel (scratchbuf
);
14741 scratchbuf
[0] = '\0';
14745 OP_I64 (int bytemode
, int sizeflag
)
14748 bfd_signed_vma mask
= -1;
14750 if (address_mode
!= mode_64bit
)
14752 OP_I (bytemode
, sizeflag
);
14759 FETCH_DATA (the_info
, codep
+ 1);
14769 if (sizeflag
& DFLAG
)
14779 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14787 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14792 scratchbuf
[0] = '$';
14793 print_operand_value (scratchbuf
+ 1, 1, op
);
14794 oappend_maybe_intel (scratchbuf
);
14795 scratchbuf
[0] = '\0';
14799 OP_sI (int bytemode
, int sizeflag
)
14807 FETCH_DATA (the_info
, codep
+ 1);
14809 if ((op
& 0x80) != 0)
14811 if (bytemode
== b_T_mode
)
14813 if (address_mode
!= mode_64bit
14814 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14816 /* The operand-size prefix is overridden by a REX prefix. */
14817 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14825 if (!(rex
& REX_W
))
14827 if (sizeflag
& DFLAG
)
14835 /* The operand-size prefix is overridden by a REX prefix. */
14836 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14842 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14846 scratchbuf
[0] = '$';
14847 print_operand_value (scratchbuf
+ 1, 1, op
);
14848 oappend_maybe_intel (scratchbuf
);
14852 OP_J (int bytemode
, int sizeflag
)
14856 bfd_vma segment
= 0;
14861 FETCH_DATA (the_info
, codep
+ 1);
14863 if ((disp
& 0x80) != 0)
14867 if (isa64
== amd64
)
14869 if ((sizeflag
& DFLAG
)
14870 || (address_mode
== mode_64bit
14871 && (isa64
!= amd64
|| (rex
& REX_W
))))
14876 if ((disp
& 0x8000) != 0)
14878 /* In 16bit mode, address is wrapped around at 64k within
14879 the same segment. Otherwise, a data16 prefix on a jump
14880 instruction means that the pc is masked to 16 bits after
14881 the displacement is added! */
14883 if ((prefixes
& PREFIX_DATA
) == 0)
14884 segment
= ((start_pc
+ (codep
- start_codep
))
14885 & ~((bfd_vma
) 0xffff));
14887 if (address_mode
!= mode_64bit
14888 || (isa64
== amd64
&& !(rex
& REX_W
)))
14889 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14892 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14895 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14897 print_operand_value (scratchbuf
, 1, disp
);
14898 oappend (scratchbuf
);
14902 OP_SEG (int bytemode
, int sizeflag
)
14904 if (bytemode
== w_mode
)
14905 oappend (names_seg
[modrm
.reg
]);
14907 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14911 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14915 if (sizeflag
& DFLAG
)
14925 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14927 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14929 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14930 oappend (scratchbuf
);
14934 OP_OFF (int bytemode
, int sizeflag
)
14938 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14939 intel_operand_size (bytemode
, sizeflag
);
14942 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14949 if (!active_seg_prefix
)
14951 oappend (names_seg
[ds_reg
- es_reg
]);
14955 print_operand_value (scratchbuf
, 1, off
);
14956 oappend (scratchbuf
);
14960 OP_OFF64 (int bytemode
, int sizeflag
)
14964 if (address_mode
!= mode_64bit
14965 || (prefixes
& PREFIX_ADDR
))
14967 OP_OFF (bytemode
, sizeflag
);
14971 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14972 intel_operand_size (bytemode
, sizeflag
);
14979 if (!active_seg_prefix
)
14981 oappend (names_seg
[ds_reg
- es_reg
]);
14985 print_operand_value (scratchbuf
, 1, off
);
14986 oappend (scratchbuf
);
14990 ptr_reg (int code
, int sizeflag
)
14994 *obufp
++ = open_char
;
14995 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14996 if (address_mode
== mode_64bit
)
14998 if (!(sizeflag
& AFLAG
))
14999 s
= names32
[code
- eAX_reg
];
15001 s
= names64
[code
- eAX_reg
];
15003 else if (sizeflag
& AFLAG
)
15004 s
= names32
[code
- eAX_reg
];
15006 s
= names16
[code
- eAX_reg
];
15008 *obufp
++ = close_char
;
15013 OP_ESreg (int code
, int sizeflag
)
15019 case 0x6d: /* insw/insl */
15020 intel_operand_size (z_mode
, sizeflag
);
15022 case 0xa5: /* movsw/movsl/movsq */
15023 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15024 case 0xab: /* stosw/stosl */
15025 case 0xaf: /* scasw/scasl */
15026 intel_operand_size (v_mode
, sizeflag
);
15029 intel_operand_size (b_mode
, sizeflag
);
15032 oappend_maybe_intel ("%es:");
15033 ptr_reg (code
, sizeflag
);
15037 OP_DSreg (int code
, int sizeflag
)
15043 case 0x6f: /* outsw/outsl */
15044 intel_operand_size (z_mode
, sizeflag
);
15046 case 0xa5: /* movsw/movsl/movsq */
15047 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15048 case 0xad: /* lodsw/lodsl/lodsq */
15049 intel_operand_size (v_mode
, sizeflag
);
15052 intel_operand_size (b_mode
, sizeflag
);
15055 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15056 default segment register DS is printed. */
15057 if (!active_seg_prefix
)
15058 active_seg_prefix
= PREFIX_DS
;
15060 ptr_reg (code
, sizeflag
);
15064 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15072 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15074 all_prefixes
[last_lock_prefix
] = 0;
15075 used_prefixes
|= PREFIX_LOCK
;
15080 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15081 oappend_maybe_intel (scratchbuf
);
15085 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15094 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15096 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15097 oappend (scratchbuf
);
15101 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15103 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15104 oappend_maybe_intel (scratchbuf
);
15108 OP_R (int bytemode
, int sizeflag
)
15110 /* Skip mod/rm byte. */
15113 OP_E_register (bytemode
, sizeflag
);
15117 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15119 int reg
= modrm
.reg
;
15120 const char **names
;
15122 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15123 if (prefixes
& PREFIX_DATA
)
15132 oappend (names
[reg
]);
15136 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15138 int reg
= modrm
.reg
;
15139 const char **names
;
15151 && bytemode
!= xmm_mode
15152 && bytemode
!= xmmq_mode
15153 && bytemode
!= evex_half_bcst_xmmq_mode
15154 && bytemode
!= ymm_mode
15155 && bytemode
!= scalar_mode
)
15157 switch (vex
.length
)
15164 || (bytemode
!= vex_vsib_q_w_dq_mode
15165 && bytemode
!= vex_vsib_q_w_d_mode
))
15177 else if (bytemode
== xmmq_mode
15178 || bytemode
== evex_half_bcst_xmmq_mode
)
15180 switch (vex
.length
)
15193 else if (bytemode
== ymm_mode
)
15197 oappend (names
[reg
]);
15201 OP_EM (int bytemode
, int sizeflag
)
15204 const char **names
;
15206 if (modrm
.mod
!= 3)
15209 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15211 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15212 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15214 OP_E (bytemode
, sizeflag
);
15218 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15221 /* Skip mod/rm byte. */
15224 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15226 if (prefixes
& PREFIX_DATA
)
15235 oappend (names
[reg
]);
15238 /* cvt* are the only instructions in sse2 which have
15239 both SSE and MMX operands and also have 0x66 prefix
15240 in their opcode. 0x66 was originally used to differentiate
15241 between SSE and MMX instruction(operands). So we have to handle the
15242 cvt* separately using OP_EMC and OP_MXC */
15244 OP_EMC (int bytemode
, int sizeflag
)
15246 if (modrm
.mod
!= 3)
15248 if (intel_syntax
&& bytemode
== v_mode
)
15250 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15251 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15253 OP_E (bytemode
, sizeflag
);
15257 /* Skip mod/rm byte. */
15260 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15261 oappend (names_mm
[modrm
.rm
]);
15265 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15267 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15268 oappend (names_mm
[modrm
.reg
]);
15272 OP_EX (int bytemode
, int sizeflag
)
15275 const char **names
;
15277 /* Skip mod/rm byte. */
15281 if (modrm
.mod
!= 3)
15283 OP_E_memory (bytemode
, sizeflag
);
15298 if ((sizeflag
& SUFFIX_ALWAYS
)
15299 && (bytemode
== x_swap_mode
15300 || bytemode
== d_swap_mode
15301 || bytemode
== d_scalar_swap_mode
15302 || bytemode
== q_swap_mode
15303 || bytemode
== q_scalar_swap_mode
))
15307 && bytemode
!= xmm_mode
15308 && bytemode
!= xmmdw_mode
15309 && bytemode
!= xmmqd_mode
15310 && bytemode
!= xmm_mb_mode
15311 && bytemode
!= xmm_mw_mode
15312 && bytemode
!= xmm_md_mode
15313 && bytemode
!= xmm_mq_mode
15314 && bytemode
!= xmm_mdq_mode
15315 && bytemode
!= xmmq_mode
15316 && bytemode
!= evex_half_bcst_xmmq_mode
15317 && bytemode
!= ymm_mode
15318 && bytemode
!= d_scalar_mode
15319 && bytemode
!= d_scalar_swap_mode
15320 && bytemode
!= q_scalar_mode
15321 && bytemode
!= q_scalar_swap_mode
15322 && bytemode
!= vex_scalar_w_dq_mode
)
15324 switch (vex
.length
)
15339 else if (bytemode
== xmmq_mode
15340 || bytemode
== evex_half_bcst_xmmq_mode
)
15342 switch (vex
.length
)
15355 else if (bytemode
== ymm_mode
)
15359 oappend (names
[reg
]);
15363 OP_MS (int bytemode
, int sizeflag
)
15365 if (modrm
.mod
== 3)
15366 OP_EM (bytemode
, sizeflag
);
15372 OP_XS (int bytemode
, int sizeflag
)
15374 if (modrm
.mod
== 3)
15375 OP_EX (bytemode
, sizeflag
);
15381 OP_M (int bytemode
, int sizeflag
)
15383 if (modrm
.mod
== 3)
15384 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15387 OP_E (bytemode
, sizeflag
);
15391 OP_0f07 (int bytemode
, int sizeflag
)
15393 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15396 OP_E (bytemode
, sizeflag
);
15399 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15400 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15403 NOP_Fixup1 (int bytemode
, int sizeflag
)
15405 if ((prefixes
& PREFIX_DATA
) != 0
15408 && address_mode
== mode_64bit
))
15409 OP_REG (bytemode
, sizeflag
);
15411 strcpy (obuf
, "nop");
15415 NOP_Fixup2 (int bytemode
, int sizeflag
)
15417 if ((prefixes
& PREFIX_DATA
) != 0
15420 && address_mode
== mode_64bit
))
15421 OP_IMREG (bytemode
, sizeflag
);
15424 static const char *const Suffix3DNow
[] = {
15425 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15426 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15427 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15428 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15429 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15430 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15431 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15432 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15433 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15434 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15435 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15436 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15437 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15438 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15439 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15440 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15441 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15442 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15443 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15444 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15445 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15446 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15447 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15448 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15449 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15450 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15451 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15452 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15453 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15454 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15455 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15456 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15457 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15458 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15459 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15460 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15461 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15462 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15463 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15464 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15465 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15466 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15467 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15468 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15469 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15470 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15471 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15472 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15473 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15474 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15475 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15476 /* CC */ NULL
, NULL
, NULL
, NULL
,
15477 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15478 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15479 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15480 /* DC */ NULL
, NULL
, NULL
, NULL
,
15481 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15482 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15483 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15484 /* EC */ NULL
, NULL
, NULL
, NULL
,
15485 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15486 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15487 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15488 /* FC */ NULL
, NULL
, NULL
, NULL
,
15492 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15494 const char *mnemonic
;
15496 FETCH_DATA (the_info
, codep
+ 1);
15497 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15498 place where an 8-bit immediate would normally go. ie. the last
15499 byte of the instruction. */
15500 obufp
= mnemonicendp
;
15501 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15503 oappend (mnemonic
);
15506 /* Since a variable sized modrm/sib chunk is between the start
15507 of the opcode (0x0f0f) and the opcode suffix, we need to do
15508 all the modrm processing first, and don't know until now that
15509 we have a bad opcode. This necessitates some cleaning up. */
15510 op_out
[0][0] = '\0';
15511 op_out
[1][0] = '\0';
15514 mnemonicendp
= obufp
;
15517 static struct op simd_cmp_op
[] =
15519 { STRING_COMMA_LEN ("eq") },
15520 { STRING_COMMA_LEN ("lt") },
15521 { STRING_COMMA_LEN ("le") },
15522 { STRING_COMMA_LEN ("unord") },
15523 { STRING_COMMA_LEN ("neq") },
15524 { STRING_COMMA_LEN ("nlt") },
15525 { STRING_COMMA_LEN ("nle") },
15526 { STRING_COMMA_LEN ("ord") }
15530 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15532 unsigned int cmp_type
;
15534 FETCH_DATA (the_info
, codep
+ 1);
15535 cmp_type
= *codep
++ & 0xff;
15536 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15539 char *p
= mnemonicendp
- 2;
15543 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15544 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15548 /* We have a reserved extension byte. Output it directly. */
15549 scratchbuf
[0] = '$';
15550 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15551 oappend_maybe_intel (scratchbuf
);
15552 scratchbuf
[0] = '\0';
15557 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
15558 int sizeflag ATTRIBUTE_UNUSED
)
15560 /* mwaitx %eax,%ecx,%ebx */
15563 const char **names
= (address_mode
== mode_64bit
15564 ? names64
: names32
);
15565 strcpy (op_out
[0], names
[0]);
15566 strcpy (op_out
[1], names
[1]);
15567 strcpy (op_out
[2], names
[3]);
15568 two_source_ops
= 1;
15570 /* Skip mod/rm byte. */
15576 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
15577 int sizeflag ATTRIBUTE_UNUSED
)
15579 /* mwait %eax,%ecx */
15582 const char **names
= (address_mode
== mode_64bit
15583 ? names64
: names32
);
15584 strcpy (op_out
[0], names
[0]);
15585 strcpy (op_out
[1], names
[1]);
15586 two_source_ops
= 1;
15588 /* Skip mod/rm byte. */
15594 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15595 int sizeflag ATTRIBUTE_UNUSED
)
15597 /* monitor %eax,%ecx,%edx" */
15600 const char **op1_names
;
15601 const char **names
= (address_mode
== mode_64bit
15602 ? names64
: names32
);
15604 if (!(prefixes
& PREFIX_ADDR
))
15605 op1_names
= (address_mode
== mode_16bit
15606 ? names16
: names
);
15609 /* Remove "addr16/addr32". */
15610 all_prefixes
[last_addr_prefix
] = 0;
15611 op1_names
= (address_mode
!= mode_32bit
15612 ? names32
: names16
);
15613 used_prefixes
|= PREFIX_ADDR
;
15615 strcpy (op_out
[0], op1_names
[0]);
15616 strcpy (op_out
[1], names
[1]);
15617 strcpy (op_out
[2], names
[2]);
15618 two_source_ops
= 1;
15620 /* Skip mod/rm byte. */
15628 /* Throw away prefixes and 1st. opcode byte. */
15629 codep
= insn_codep
+ 1;
15634 REP_Fixup (int bytemode
, int sizeflag
)
15636 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15638 if (prefixes
& PREFIX_REPZ
)
15639 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15646 OP_IMREG (bytemode
, sizeflag
);
15649 OP_ESreg (bytemode
, sizeflag
);
15652 OP_DSreg (bytemode
, sizeflag
);
15660 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15664 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15666 if (prefixes
& PREFIX_REPNZ
)
15667 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15670 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15674 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15675 int sizeflag ATTRIBUTE_UNUSED
)
15677 if (active_seg_prefix
== PREFIX_DS
15678 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15680 /* NOTRACK prefix is only valid on indirect branch instructions.
15681 NB: DATA prefix is unsupported for Intel64. */
15682 active_seg_prefix
= 0;
15683 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15687 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15688 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15692 HLE_Fixup1 (int bytemode
, int sizeflag
)
15695 && (prefixes
& PREFIX_LOCK
) != 0)
15697 if (prefixes
& PREFIX_REPZ
)
15698 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15699 if (prefixes
& PREFIX_REPNZ
)
15700 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15703 OP_E (bytemode
, sizeflag
);
15706 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15707 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15711 HLE_Fixup2 (int bytemode
, int sizeflag
)
15713 if (modrm
.mod
!= 3)
15715 if (prefixes
& PREFIX_REPZ
)
15716 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15717 if (prefixes
& PREFIX_REPNZ
)
15718 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15721 OP_E (bytemode
, sizeflag
);
15724 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15725 "xrelease" for memory operand. No check for LOCK prefix. */
15728 HLE_Fixup3 (int bytemode
, int sizeflag
)
15731 && last_repz_prefix
> last_repnz_prefix
15732 && (prefixes
& PREFIX_REPZ
) != 0)
15733 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15735 OP_E (bytemode
, sizeflag
);
15739 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15744 /* Change cmpxchg8b to cmpxchg16b. */
15745 char *p
= mnemonicendp
- 2;
15746 mnemonicendp
= stpcpy (p
, "16b");
15749 else if ((prefixes
& PREFIX_LOCK
) != 0)
15751 if (prefixes
& PREFIX_REPZ
)
15752 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15753 if (prefixes
& PREFIX_REPNZ
)
15754 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15757 OP_M (bytemode
, sizeflag
);
15761 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15763 const char **names
;
15767 switch (vex
.length
)
15781 oappend (names
[reg
]);
15785 CRC32_Fixup (int bytemode
, int sizeflag
)
15787 /* Add proper suffix to "crc32". */
15788 char *p
= mnemonicendp
;
15807 if (sizeflag
& DFLAG
)
15811 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15815 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15822 if (modrm
.mod
== 3)
15826 /* Skip mod/rm byte. */
15831 add
= (rex
& REX_B
) ? 8 : 0;
15832 if (bytemode
== b_mode
)
15836 oappend (names8rex
[modrm
.rm
+ add
]);
15838 oappend (names8
[modrm
.rm
+ add
]);
15844 oappend (names64
[modrm
.rm
+ add
]);
15845 else if ((prefixes
& PREFIX_DATA
))
15846 oappend (names16
[modrm
.rm
+ add
]);
15848 oappend (names32
[modrm
.rm
+ add
]);
15852 OP_E (bytemode
, sizeflag
);
15856 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15858 /* Add proper suffix to "fxsave" and "fxrstor". */
15862 char *p
= mnemonicendp
;
15868 OP_M (bytemode
, sizeflag
);
15872 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15874 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15877 char *p
= mnemonicendp
;
15882 else if (sizeflag
& SUFFIX_ALWAYS
)
15889 OP_EX (bytemode
, sizeflag
);
15892 /* Display the destination register operand for instructions with
15896 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15899 const char **names
;
15907 reg
= vex
.register_specifier
;
15908 if (address_mode
!= mode_64bit
)
15910 else if (vex
.evex
&& !vex
.v
)
15913 if (bytemode
== vex_scalar_mode
)
15915 oappend (names_xmm
[reg
]);
15919 switch (vex
.length
)
15926 case vex_vsib_q_w_dq_mode
:
15927 case vex_vsib_q_w_d_mode
:
15943 names
= names_mask
;
15957 case vex_vsib_q_w_dq_mode
:
15958 case vex_vsib_q_w_d_mode
:
15959 names
= vex
.w
? names_ymm
: names_xmm
;
15968 names
= names_mask
;
15971 /* See PR binutils/20893 for a reproducer. */
15983 oappend (names
[reg
]);
15986 /* Get the VEX immediate byte without moving codep. */
15988 static unsigned char
15989 get_vex_imm8 (int sizeflag
, int opnum
)
15991 int bytes_before_imm
= 0;
15993 if (modrm
.mod
!= 3)
15995 /* There are SIB/displacement bytes. */
15996 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15998 /* 32/64 bit address mode */
15999 int base
= modrm
.rm
;
16001 /* Check SIB byte. */
16004 FETCH_DATA (the_info
, codep
+ 1);
16006 /* When decoding the third source, don't increase
16007 bytes_before_imm as this has already been incremented
16008 by one in OP_E_memory while decoding the second
16011 bytes_before_imm
++;
16014 /* Don't increase bytes_before_imm when decoding the third source,
16015 it has already been incremented by OP_E_memory while decoding
16016 the second source operand. */
16022 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16023 SIB == 5, there is a 4 byte displacement. */
16025 /* No displacement. */
16027 /* Fall through. */
16029 /* 4 byte displacement. */
16030 bytes_before_imm
+= 4;
16033 /* 1 byte displacement. */
16034 bytes_before_imm
++;
16041 /* 16 bit address mode */
16042 /* Don't increase bytes_before_imm when decoding the third source,
16043 it has already been incremented by OP_E_memory while decoding
16044 the second source operand. */
16050 /* When modrm.rm == 6, there is a 2 byte displacement. */
16052 /* No displacement. */
16054 /* Fall through. */
16056 /* 2 byte displacement. */
16057 bytes_before_imm
+= 2;
16060 /* 1 byte displacement: when decoding the third source,
16061 don't increase bytes_before_imm as this has already
16062 been incremented by one in OP_E_memory while decoding
16063 the second source operand. */
16065 bytes_before_imm
++;
16073 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16074 return codep
[bytes_before_imm
];
16078 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16080 const char **names
;
16082 if (reg
== -1 && modrm
.mod
!= 3)
16084 OP_E_memory (bytemode
, sizeflag
);
16096 if (address_mode
!= mode_64bit
)
16100 switch (vex
.length
)
16111 oappend (names
[reg
]);
16115 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16118 static unsigned char vex_imm8
;
16120 if (vex_w_done
== 0)
16124 /* Skip mod/rm byte. */
16128 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16131 reg
= vex_imm8
>> 4;
16133 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16135 else if (vex_w_done
== 1)
16140 reg
= vex_imm8
>> 4;
16142 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16146 /* Output the imm8 directly. */
16147 scratchbuf
[0] = '$';
16148 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16149 oappend_maybe_intel (scratchbuf
);
16150 scratchbuf
[0] = '\0';
16156 OP_Vex_2src (int bytemode
, int sizeflag
)
16158 if (modrm
.mod
== 3)
16160 int reg
= modrm
.rm
;
16164 oappend (names_xmm
[reg
]);
16169 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16171 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16172 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16174 OP_E (bytemode
, sizeflag
);
16179 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16181 if (modrm
.mod
== 3)
16183 /* Skip mod/rm byte. */
16190 unsigned int reg
= vex
.register_specifier
;
16192 if (address_mode
!= mode_64bit
)
16194 oappend (names_xmm
[reg
]);
16197 OP_Vex_2src (bytemode
, sizeflag
);
16201 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16204 OP_Vex_2src (bytemode
, sizeflag
);
16207 unsigned int reg
= vex
.register_specifier
;
16209 if (address_mode
!= mode_64bit
)
16211 oappend (names_xmm
[reg
]);
16216 OP_EX_VexW (int bytemode
, int sizeflag
)
16222 /* Skip mod/rm byte. */
16227 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16232 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16235 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16243 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16246 const char **names
;
16248 FETCH_DATA (the_info
, codep
+ 1);
16251 if (bytemode
!= x_mode
)
16255 if (address_mode
!= mode_64bit
)
16258 switch (vex
.length
)
16269 oappend (names
[reg
]);
16273 OP_XMM_VexW (int bytemode
, int sizeflag
)
16275 /* Turn off the REX.W bit since it is used for swapping operands
16278 OP_XMM (bytemode
, sizeflag
);
16282 OP_EX_Vex (int bytemode
, int sizeflag
)
16284 if (modrm
.mod
!= 3)
16286 if (vex
.register_specifier
!= 0)
16290 OP_EX (bytemode
, sizeflag
);
16294 OP_XMM_Vex (int bytemode
, int sizeflag
)
16296 if (modrm
.mod
!= 3)
16298 if (vex
.register_specifier
!= 0)
16302 OP_XMM (bytemode
, sizeflag
);
16305 static struct op vex_cmp_op
[] =
16307 { STRING_COMMA_LEN ("eq") },
16308 { STRING_COMMA_LEN ("lt") },
16309 { STRING_COMMA_LEN ("le") },
16310 { STRING_COMMA_LEN ("unord") },
16311 { STRING_COMMA_LEN ("neq") },
16312 { STRING_COMMA_LEN ("nlt") },
16313 { STRING_COMMA_LEN ("nle") },
16314 { STRING_COMMA_LEN ("ord") },
16315 { STRING_COMMA_LEN ("eq_uq") },
16316 { STRING_COMMA_LEN ("nge") },
16317 { STRING_COMMA_LEN ("ngt") },
16318 { STRING_COMMA_LEN ("false") },
16319 { STRING_COMMA_LEN ("neq_oq") },
16320 { STRING_COMMA_LEN ("ge") },
16321 { STRING_COMMA_LEN ("gt") },
16322 { STRING_COMMA_LEN ("true") },
16323 { STRING_COMMA_LEN ("eq_os") },
16324 { STRING_COMMA_LEN ("lt_oq") },
16325 { STRING_COMMA_LEN ("le_oq") },
16326 { STRING_COMMA_LEN ("unord_s") },
16327 { STRING_COMMA_LEN ("neq_us") },
16328 { STRING_COMMA_LEN ("nlt_uq") },
16329 { STRING_COMMA_LEN ("nle_uq") },
16330 { STRING_COMMA_LEN ("ord_s") },
16331 { STRING_COMMA_LEN ("eq_us") },
16332 { STRING_COMMA_LEN ("nge_uq") },
16333 { STRING_COMMA_LEN ("ngt_uq") },
16334 { STRING_COMMA_LEN ("false_os") },
16335 { STRING_COMMA_LEN ("neq_os") },
16336 { STRING_COMMA_LEN ("ge_oq") },
16337 { STRING_COMMA_LEN ("gt_oq") },
16338 { STRING_COMMA_LEN ("true_us") },
16342 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16344 unsigned int cmp_type
;
16346 FETCH_DATA (the_info
, codep
+ 1);
16347 cmp_type
= *codep
++ & 0xff;
16348 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16351 char *p
= mnemonicendp
- 2;
16355 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16356 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16360 /* We have a reserved extension byte. Output it directly. */
16361 scratchbuf
[0] = '$';
16362 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16363 oappend_maybe_intel (scratchbuf
);
16364 scratchbuf
[0] = '\0';
16369 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16370 int sizeflag ATTRIBUTE_UNUSED
)
16372 unsigned int cmp_type
;
16377 FETCH_DATA (the_info
, codep
+ 1);
16378 cmp_type
= *codep
++ & 0xff;
16379 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16380 If it's the case, print suffix, otherwise - print the immediate. */
16381 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16386 char *p
= mnemonicendp
- 2;
16388 /* vpcmp* can have both one- and two-lettered suffix. */
16402 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16403 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16407 /* We have a reserved extension byte. Output it directly. */
16408 scratchbuf
[0] = '$';
16409 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16410 oappend_maybe_intel (scratchbuf
);
16411 scratchbuf
[0] = '\0';
16415 static const struct op xop_cmp_op
[] =
16417 { STRING_COMMA_LEN ("lt") },
16418 { STRING_COMMA_LEN ("le") },
16419 { STRING_COMMA_LEN ("gt") },
16420 { STRING_COMMA_LEN ("ge") },
16421 { STRING_COMMA_LEN ("eq") },
16422 { STRING_COMMA_LEN ("neq") },
16423 { STRING_COMMA_LEN ("false") },
16424 { STRING_COMMA_LEN ("true") }
16428 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16429 int sizeflag ATTRIBUTE_UNUSED
)
16431 unsigned int cmp_type
;
16433 FETCH_DATA (the_info
, codep
+ 1);
16434 cmp_type
= *codep
++ & 0xff;
16435 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16438 char *p
= mnemonicendp
- 2;
16440 /* vpcom* can have both one- and two-lettered suffix. */
16454 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16455 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16459 /* We have a reserved extension byte. Output it directly. */
16460 scratchbuf
[0] = '$';
16461 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16462 oappend_maybe_intel (scratchbuf
);
16463 scratchbuf
[0] = '\0';
16467 static const struct op pclmul_op
[] =
16469 { STRING_COMMA_LEN ("lql") },
16470 { STRING_COMMA_LEN ("hql") },
16471 { STRING_COMMA_LEN ("lqh") },
16472 { STRING_COMMA_LEN ("hqh") }
16476 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16477 int sizeflag ATTRIBUTE_UNUSED
)
16479 unsigned int pclmul_type
;
16481 FETCH_DATA (the_info
, codep
+ 1);
16482 pclmul_type
= *codep
++ & 0xff;
16483 switch (pclmul_type
)
16494 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16497 char *p
= mnemonicendp
- 3;
16502 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16503 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16507 /* We have a reserved extension byte. Output it directly. */
16508 scratchbuf
[0] = '$';
16509 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16510 oappend_maybe_intel (scratchbuf
);
16511 scratchbuf
[0] = '\0';
16516 MOVBE_Fixup (int bytemode
, int sizeflag
)
16518 /* Add proper suffix to "movbe". */
16519 char *p
= mnemonicendp
;
16528 if (sizeflag
& SUFFIX_ALWAYS
)
16534 if (sizeflag
& DFLAG
)
16538 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16543 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16550 OP_M (bytemode
, sizeflag
);
16554 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16557 const char **names
;
16559 /* Skip mod/rm byte. */
16573 oappend (names
[reg
]);
16577 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16579 const char **names
;
16580 unsigned int reg
= vex
.register_specifier
;
16587 if (address_mode
!= mode_64bit
)
16589 oappend (names
[reg
]);
16593 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16596 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16600 if ((rex
& REX_R
) != 0 || !vex
.r
)
16606 oappend (names_mask
[modrm
.reg
]);
16610 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16613 || (bytemode
!= evex_rounding_mode
16614 && bytemode
!= evex_rounding_64_mode
16615 && bytemode
!= evex_sae_mode
))
16617 if (modrm
.mod
== 3 && vex
.b
)
16620 case evex_rounding_64_mode
:
16621 if (address_mode
!= mode_64bit
)
16626 /* Fall through. */
16627 case evex_rounding_mode
:
16628 oappend (names_rounding
[vex
.ll
]);
16630 case evex_sae_mode
: