1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VZERO_Fixup (int, int);
99 static void VCMP_Fixup (int, int);
100 static void VPCMP_Fixup (int, int);
101 static void VPCOM_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte
*max_fetched
;
134 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
137 OPCODES_SIGJMP_BUF bailout
;
147 enum address_mode address_mode
;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored
;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes
;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
202 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
203 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
205 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
206 status
= (*info
->read_memory_func
) (start
,
208 addr
- priv
->max_fetched
,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv
->max_fetched
== priv
->the_buffer
)
219 (*info
->memory_error_func
) (status
, start
, info
);
220 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
223 priv
->max_fetched
= addr
;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Ev_bnd { OP_E, v_bnd_mode }
253 #define EvS { OP_E, v_swap_mode }
254 #define Ed { OP_E, d_mode }
255 #define Edq { OP_E, dq_mode }
256 #define Edqw { OP_E, dqw_mode }
257 #define Edqb { OP_E, dqb_mode }
258 #define Edb { OP_E, db_mode }
259 #define Edw { OP_E, dw_mode }
260 #define Edqd { OP_E, dqd_mode }
261 #define Eq { OP_E, q_mode }
262 #define indirEv { OP_indirE, indir_v_mode }
263 #define indirEp { OP_indirE, f_mode }
264 #define stackEv { OP_E, stack_v_mode }
265 #define Em { OP_E, m_mode }
266 #define Ew { OP_E, w_mode }
267 #define M { OP_M, 0 } /* lea, lgdt, etc. */
268 #define Ma { OP_M, a_mode }
269 #define Mb { OP_M, b_mode }
270 #define Md { OP_M, d_mode }
271 #define Mo { OP_M, o_mode }
272 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
273 #define Mq { OP_M, q_mode }
274 #define Mx { OP_M, x_mode }
275 #define Mxmm { OP_M, xmm_mode }
276 #define Gb { OP_G, b_mode }
277 #define Gbnd { OP_G, bnd_mode }
278 #define Gv { OP_G, v_mode }
279 #define Gd { OP_G, d_mode }
280 #define Gdq { OP_G, dq_mode }
281 #define Gm { OP_G, m_mode }
282 #define Gw { OP_G, w_mode }
283 #define Rd { OP_R, d_mode }
284 #define Rdq { OP_R, dq_mode }
285 #define Rm { OP_R, m_mode }
286 #define Ib { OP_I, b_mode }
287 #define sIb { OP_sI, b_mode } /* sign extened byte */
288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
289 #define Iv { OP_I, v_mode }
290 #define sIv { OP_sI, v_mode }
291 #define Iq { OP_I, q_mode }
292 #define Iv64 { OP_I64, v_mode }
293 #define Iw { OP_I, w_mode }
294 #define I1 { OP_I, const_1_mode }
295 #define Jb { OP_J, b_mode }
296 #define Jv { OP_J, v_mode }
297 #define Cm { OP_C, m_mode }
298 #define Dm { OP_D, m_mode }
299 #define Td { OP_T, d_mode }
300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
302 #define RMeAX { OP_REG, eAX_reg }
303 #define RMeBX { OP_REG, eBX_reg }
304 #define RMeCX { OP_REG, eCX_reg }
305 #define RMeDX { OP_REG, eDX_reg }
306 #define RMeSP { OP_REG, eSP_reg }
307 #define RMeBP { OP_REG, eBP_reg }
308 #define RMeSI { OP_REG, eSI_reg }
309 #define RMeDI { OP_REG, eDI_reg }
310 #define RMrAX { OP_REG, rAX_reg }
311 #define RMrBX { OP_REG, rBX_reg }
312 #define RMrCX { OP_REG, rCX_reg }
313 #define RMrDX { OP_REG, rDX_reg }
314 #define RMrSP { OP_REG, rSP_reg }
315 #define RMrBP { OP_REG, rBP_reg }
316 #define RMrSI { OP_REG, rSI_reg }
317 #define RMrDI { OP_REG, rDI_reg }
318 #define RMAL { OP_REG, al_reg }
319 #define RMCL { OP_REG, cl_reg }
320 #define RMDL { OP_REG, dl_reg }
321 #define RMBL { OP_REG, bl_reg }
322 #define RMAH { OP_REG, ah_reg }
323 #define RMCH { OP_REG, ch_reg }
324 #define RMDH { OP_REG, dh_reg }
325 #define RMBH { OP_REG, bh_reg }
326 #define RMAX { OP_REG, ax_reg }
327 #define RMDX { OP_REG, dx_reg }
329 #define eAX { OP_IMREG, eAX_reg }
330 #define eBX { OP_IMREG, eBX_reg }
331 #define eCX { OP_IMREG, eCX_reg }
332 #define eDX { OP_IMREG, eDX_reg }
333 #define eSP { OP_IMREG, eSP_reg }
334 #define eBP { OP_IMREG, eBP_reg }
335 #define eSI { OP_IMREG, eSI_reg }
336 #define eDI { OP_IMREG, eDI_reg }
337 #define AL { OP_IMREG, al_reg }
338 #define CL { OP_IMREG, cl_reg }
339 #define DL { OP_IMREG, dl_reg }
340 #define BL { OP_IMREG, bl_reg }
341 #define AH { OP_IMREG, ah_reg }
342 #define CH { OP_IMREG, ch_reg }
343 #define DH { OP_IMREG, dh_reg }
344 #define BH { OP_IMREG, bh_reg }
345 #define AX { OP_IMREG, ax_reg }
346 #define DX { OP_IMREG, dx_reg }
347 #define zAX { OP_IMREG, z_mode_ax_reg }
348 #define indirDX { OP_IMREG, indir_dx_reg }
350 #define Sw { OP_SEG, w_mode }
351 #define Sv { OP_SEG, v_mode }
352 #define Ap { OP_DIR, 0 }
353 #define Ob { OP_OFF64, b_mode }
354 #define Ov { OP_OFF64, v_mode }
355 #define Xb { OP_DSreg, eSI_reg }
356 #define Xv { OP_DSreg, eSI_reg }
357 #define Xz { OP_DSreg, eSI_reg }
358 #define Yb { OP_ESreg, eDI_reg }
359 #define Yv { OP_ESreg, eDI_reg }
360 #define DSBX { OP_DSreg, eBX_reg }
362 #define es { OP_REG, es_reg }
363 #define ss { OP_REG, ss_reg }
364 #define cs { OP_REG, cs_reg }
365 #define ds { OP_REG, ds_reg }
366 #define fs { OP_REG, fs_reg }
367 #define gs { OP_REG, gs_reg }
369 #define MX { OP_MMX, 0 }
370 #define XM { OP_XMM, 0 }
371 #define XMScalar { OP_XMM, scalar_mode }
372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
373 #define XMM { OP_XMM, xmm_mode }
374 #define XMxmmq { OP_XMM, xmmq_mode }
375 #define EM { OP_EM, v_mode }
376 #define EMS { OP_EM, v_swap_mode }
377 #define EMd { OP_EM, d_mode }
378 #define EMx { OP_EM, x_mode }
379 #define EXbScalar { OP_EX, b_scalar_mode }
380 #define EXw { OP_EX, w_mode }
381 #define EXwScalar { OP_EX, w_scalar_mode }
382 #define EXd { OP_EX, d_mode }
383 #define EXdScalar { OP_EX, d_scalar_mode }
384 #define EXdS { OP_EX, d_swap_mode }
385 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
386 #define EXq { OP_EX, q_mode }
387 #define EXqScalar { OP_EX, q_scalar_mode }
388 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
389 #define EXqS { OP_EX, q_swap_mode }
390 #define EXx { OP_EX, x_mode }
391 #define EXxS { OP_EX, x_swap_mode }
392 #define EXxmm { OP_EX, xmm_mode }
393 #define EXymm { OP_EX, ymm_mode }
394 #define EXxmmq { OP_EX, xmmq_mode }
395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
398 #define EXxmm_md { OP_EX, xmm_md_mode }
399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
400 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
401 #define EXxmmdw { OP_EX, xmmdw_mode }
402 #define EXxmmqd { OP_EX, xmmqd_mode }
403 #define EXymmq { OP_EX, ymmq_mode }
404 #define EXVexWdq { OP_EX, vex_w_dq_mode }
405 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
406 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
407 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
408 #define MS { OP_MS, v_mode }
409 #define XS { OP_XS, v_mode }
410 #define EMCq { OP_EMC, q_mode }
411 #define MXC { OP_MXC, 0 }
412 #define OPSUF { OP_3DNowSuffix, 0 }
413 #define CMP { CMP_Fixup, 0 }
414 #define XMM0 { XMM_Fixup, 0 }
415 #define FXSAVE { FXSAVE_Fixup, 0 }
416 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
417 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
419 #define Vex { OP_VEX, vex_mode }
420 #define VexScalar { OP_VEX, vex_scalar_mode }
421 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
422 #define Vex128 { OP_VEX, vex128_mode }
423 #define Vex256 { OP_VEX, vex256_mode }
424 #define VexGdq { OP_VEX, dq_mode }
425 #define EXdVex { OP_EX_Vex, d_mode }
426 #define EXdVexS { OP_EX_Vex, d_swap_mode }
427 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
428 #define EXqVex { OP_EX_Vex, q_mode }
429 #define EXqVexS { OP_EX_Vex, q_swap_mode }
430 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
431 #define EXVexW { OP_EX_VexW, x_mode }
432 #define EXdVexW { OP_EX_VexW, d_mode }
433 #define EXqVexW { OP_EX_VexW, q_mode }
434 #define EXVexImmW { OP_EX_VexImmW, x_mode }
435 #define XMVex { OP_XMM_Vex, 0 }
436 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
437 #define XMVexW { OP_XMM_VexW, 0 }
438 #define XMVexI4 { OP_REG_VexI4, x_mode }
439 #define PCLMUL { PCLMUL_Fixup, 0 }
440 #define VZERO { VZERO_Fixup, 0 }
441 #define VCMP { VCMP_Fixup, 0 }
442 #define VPCMP { VPCMP_Fixup, 0 }
443 #define VPCOM { VPCOM_Fixup, 0 }
445 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
446 #define EXxEVexS { OP_Rounding, evex_sae_mode }
448 #define XMask { OP_Mask, mask_mode }
449 #define MaskG { OP_G, mask_mode }
450 #define MaskE { OP_E, mask_mode }
451 #define MaskBDE { OP_E, mask_bd_mode }
452 #define MaskR { OP_R, mask_mode }
453 #define MaskVex { OP_VEX, mask_mode }
455 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
456 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
457 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
458 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
460 /* Used handle "rep" prefix for string instructions. */
461 #define Xbr { REP_Fixup, eSI_reg }
462 #define Xvr { REP_Fixup, eSI_reg }
463 #define Ybr { REP_Fixup, eDI_reg }
464 #define Yvr { REP_Fixup, eDI_reg }
465 #define Yzr { REP_Fixup, eDI_reg }
466 #define indirDXr { REP_Fixup, indir_dx_reg }
467 #define ALr { REP_Fixup, al_reg }
468 #define eAXr { REP_Fixup, eAX_reg }
470 /* Used handle HLE prefix for lockable instructions. */
471 #define Ebh1 { HLE_Fixup1, b_mode }
472 #define Evh1 { HLE_Fixup1, v_mode }
473 #define Ebh2 { HLE_Fixup2, b_mode }
474 #define Evh2 { HLE_Fixup2, v_mode }
475 #define Ebh3 { HLE_Fixup3, b_mode }
476 #define Evh3 { HLE_Fixup3, v_mode }
478 #define BND { BND_Fixup, 0 }
479 #define NOTRACK { NOTRACK_Fixup, 0 }
481 #define cond_jump_flag { NULL, cond_jump_mode }
482 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
484 /* bits in sizeflag */
485 #define SUFFIX_ALWAYS 4
493 /* byte operand with operand swapped */
495 /* byte operand, sign extend like 'T' suffix */
497 /* operand size depends on prefixes */
499 /* operand size depends on prefixes with operand swapped */
503 /* double word operand */
505 /* double word operand with operand swapped */
507 /* quad word operand */
509 /* quad word operand with operand swapped */
511 /* ten-byte operand */
513 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
514 broadcast enabled. */
516 /* Similar to x_mode, but with different EVEX mem shifts. */
518 /* Similar to x_mode, but with disabled broadcast. */
520 /* Similar to x_mode, but with operands swapped and disabled broadcast
523 /* 16-byte XMM operand */
525 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
526 memory operand (depending on vector length). Broadcast isn't
529 /* Same as xmmq_mode, but broadcast is allowed. */
530 evex_half_bcst_xmmq_mode
,
531 /* XMM register or byte memory operand */
533 /* XMM register or word memory operand */
535 /* XMM register or double word memory operand */
537 /* XMM register or quad word memory operand */
539 /* XMM register or double/quad word memory operand, depending on
542 /* 16-byte XMM, word, double word or quad word operand. */
544 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
546 /* 32-byte YMM operand */
548 /* quad word, ymmword or zmmword memory operand. */
550 /* 32-byte YMM or 16-byte word operand */
552 /* d_mode in 32bit, q_mode in 64bit mode. */
554 /* pair of v_mode operands */
559 /* operand size depends on REX prefixes. */
561 /* registers like dq_mode, memory like w_mode. */
564 /* 4- or 6-byte pointer operand */
567 /* v_mode for indirect branch opcodes. */
569 /* v_mode for stack-related opcodes. */
571 /* non-quad operand size depends on prefixes */
573 /* 16-byte operand */
575 /* registers like dq_mode, memory like b_mode. */
577 /* registers like d_mode, memory like b_mode. */
579 /* registers like d_mode, memory like w_mode. */
581 /* registers like dq_mode, memory like d_mode. */
583 /* normal vex mode */
585 /* 128bit vex mode */
587 /* 256bit vex mode */
589 /* operand size depends on the VEX.W bit. */
592 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
593 vex_vsib_d_w_dq_mode
,
594 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
596 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
597 vex_vsib_q_w_dq_mode
,
598 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
601 /* scalar, ignore vector length. */
603 /* like b_mode, ignore vector length. */
605 /* like w_mode, ignore vector length. */
607 /* like d_mode, ignore vector length. */
609 /* like d_swap_mode, ignore vector length. */
611 /* like q_mode, ignore vector length. */
613 /* like q_swap_mode, ignore vector length. */
615 /* like vex_mode, ignore vector length. */
617 /* like vex_w_dq_mode, ignore vector length. */
618 vex_scalar_w_dq_mode
,
620 /* Static rounding. */
622 /* Supress all exceptions. */
625 /* Mask register operand. */
627 /* Mask register operand. */
694 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
696 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
697 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
698 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
699 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
700 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
701 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
702 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
703 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
704 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
705 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
706 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
707 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
708 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
709 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
710 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
832 MOD_VEX_0F12_PREFIX_0
,
834 MOD_VEX_0F16_PREFIX_0
,
837 MOD_VEX_W_0_0F41_P_0_LEN_1
,
838 MOD_VEX_W_1_0F41_P_0_LEN_1
,
839 MOD_VEX_W_0_0F41_P_2_LEN_1
,
840 MOD_VEX_W_1_0F41_P_2_LEN_1
,
841 MOD_VEX_W_0_0F42_P_0_LEN_1
,
842 MOD_VEX_W_1_0F42_P_0_LEN_1
,
843 MOD_VEX_W_0_0F42_P_2_LEN_1
,
844 MOD_VEX_W_1_0F42_P_2_LEN_1
,
845 MOD_VEX_W_0_0F44_P_0_LEN_1
,
846 MOD_VEX_W_1_0F44_P_0_LEN_1
,
847 MOD_VEX_W_0_0F44_P_2_LEN_1
,
848 MOD_VEX_W_1_0F44_P_2_LEN_1
,
849 MOD_VEX_W_0_0F45_P_0_LEN_1
,
850 MOD_VEX_W_1_0F45_P_0_LEN_1
,
851 MOD_VEX_W_0_0F45_P_2_LEN_1
,
852 MOD_VEX_W_1_0F45_P_2_LEN_1
,
853 MOD_VEX_W_0_0F46_P_0_LEN_1
,
854 MOD_VEX_W_1_0F46_P_0_LEN_1
,
855 MOD_VEX_W_0_0F46_P_2_LEN_1
,
856 MOD_VEX_W_1_0F46_P_2_LEN_1
,
857 MOD_VEX_W_0_0F47_P_0_LEN_1
,
858 MOD_VEX_W_1_0F47_P_0_LEN_1
,
859 MOD_VEX_W_0_0F47_P_2_LEN_1
,
860 MOD_VEX_W_1_0F47_P_2_LEN_1
,
861 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
862 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
863 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
864 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
865 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
866 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
867 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
879 MOD_VEX_W_0_0F91_P_0_LEN_0
,
880 MOD_VEX_W_1_0F91_P_0_LEN_0
,
881 MOD_VEX_W_0_0F91_P_2_LEN_0
,
882 MOD_VEX_W_1_0F91_P_2_LEN_0
,
883 MOD_VEX_W_0_0F92_P_0_LEN_0
,
884 MOD_VEX_W_0_0F92_P_2_LEN_0
,
885 MOD_VEX_W_0_0F92_P_3_LEN_0
,
886 MOD_VEX_W_1_0F92_P_3_LEN_0
,
887 MOD_VEX_W_0_0F93_P_0_LEN_0
,
888 MOD_VEX_W_0_0F93_P_2_LEN_0
,
889 MOD_VEX_W_0_0F93_P_3_LEN_0
,
890 MOD_VEX_W_1_0F93_P_3_LEN_0
,
891 MOD_VEX_W_0_0F98_P_0_LEN_0
,
892 MOD_VEX_W_1_0F98_P_0_LEN_0
,
893 MOD_VEX_W_0_0F98_P_2_LEN_0
,
894 MOD_VEX_W_1_0F98_P_2_LEN_0
,
895 MOD_VEX_W_0_0F99_P_0_LEN_0
,
896 MOD_VEX_W_1_0F99_P_0_LEN_0
,
897 MOD_VEX_W_0_0F99_P_2_LEN_0
,
898 MOD_VEX_W_1_0F99_P_2_LEN_0
,
901 MOD_VEX_0FD7_PREFIX_2
,
902 MOD_VEX_0FE7_PREFIX_2
,
903 MOD_VEX_0FF0_PREFIX_3
,
904 MOD_VEX_0F381A_PREFIX_2
,
905 MOD_VEX_0F382A_PREFIX_2
,
906 MOD_VEX_0F382C_PREFIX_2
,
907 MOD_VEX_0F382D_PREFIX_2
,
908 MOD_VEX_0F382E_PREFIX_2
,
909 MOD_VEX_0F382F_PREFIX_2
,
910 MOD_VEX_0F385A_PREFIX_2
,
911 MOD_VEX_0F388C_PREFIX_2
,
912 MOD_VEX_0F388E_PREFIX_2
,
913 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
914 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
915 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
916 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
917 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
918 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
919 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
920 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
922 MOD_EVEX_0F10_PREFIX_1
,
923 MOD_EVEX_0F10_PREFIX_3
,
924 MOD_EVEX_0F11_PREFIX_1
,
925 MOD_EVEX_0F11_PREFIX_3
,
926 MOD_EVEX_0F12_PREFIX_0
,
927 MOD_EVEX_0F16_PREFIX_0
,
928 MOD_EVEX_0F38C6_REG_1
,
929 MOD_EVEX_0F38C6_REG_2
,
930 MOD_EVEX_0F38C6_REG_5
,
931 MOD_EVEX_0F38C6_REG_6
,
932 MOD_EVEX_0F38C7_REG_1
,
933 MOD_EVEX_0F38C7_REG_2
,
934 MOD_EVEX_0F38C7_REG_5
,
935 MOD_EVEX_0F38C7_REG_6
956 PREFIX_MOD_0_0F01_REG_5
,
957 PREFIX_MOD_3_0F01_REG_5_RM_0
,
958 PREFIX_MOD_3_0F01_REG_5_RM_2
,
1003 PREFIX_MOD_0_0FAE_REG_4
,
1004 PREFIX_MOD_3_0FAE_REG_4
,
1005 PREFIX_MOD_0_0FAE_REG_5
,
1006 PREFIX_MOD_3_0FAE_REG_5
,
1014 PREFIX_MOD_0_0FC7_REG_6
,
1015 PREFIX_MOD_3_0FC7_REG_6
,
1016 PREFIX_MOD_3_0FC7_REG_7
,
1144 PREFIX_VEX_0F71_REG_2
,
1145 PREFIX_VEX_0F71_REG_4
,
1146 PREFIX_VEX_0F71_REG_6
,
1147 PREFIX_VEX_0F72_REG_2
,
1148 PREFIX_VEX_0F72_REG_4
,
1149 PREFIX_VEX_0F72_REG_6
,
1150 PREFIX_VEX_0F73_REG_2
,
1151 PREFIX_VEX_0F73_REG_3
,
1152 PREFIX_VEX_0F73_REG_6
,
1153 PREFIX_VEX_0F73_REG_7
,
1326 PREFIX_VEX_0F38F3_REG_1
,
1327 PREFIX_VEX_0F38F3_REG_2
,
1328 PREFIX_VEX_0F38F3_REG_3
,
1447 PREFIX_EVEX_0F71_REG_2
,
1448 PREFIX_EVEX_0F71_REG_4
,
1449 PREFIX_EVEX_0F71_REG_6
,
1450 PREFIX_EVEX_0F72_REG_0
,
1451 PREFIX_EVEX_0F72_REG_1
,
1452 PREFIX_EVEX_0F72_REG_2
,
1453 PREFIX_EVEX_0F72_REG_4
,
1454 PREFIX_EVEX_0F72_REG_6
,
1455 PREFIX_EVEX_0F73_REG_2
,
1456 PREFIX_EVEX_0F73_REG_3
,
1457 PREFIX_EVEX_0F73_REG_6
,
1458 PREFIX_EVEX_0F73_REG_7
,
1654 PREFIX_EVEX_0F38C6_REG_1
,
1655 PREFIX_EVEX_0F38C6_REG_2
,
1656 PREFIX_EVEX_0F38C6_REG_5
,
1657 PREFIX_EVEX_0F38C6_REG_6
,
1658 PREFIX_EVEX_0F38C7_REG_1
,
1659 PREFIX_EVEX_0F38C7_REG_2
,
1660 PREFIX_EVEX_0F38C7_REG_5
,
1661 PREFIX_EVEX_0F38C7_REG_6
,
1763 THREE_BYTE_0F38
= 0,
1790 VEX_LEN_0F10_P_1
= 0,
1794 VEX_LEN_0F12_P_0_M_0
,
1795 VEX_LEN_0F12_P_0_M_1
,
1798 VEX_LEN_0F16_P_0_M_0
,
1799 VEX_LEN_0F16_P_0_M_1
,
1863 VEX_LEN_0FAE_R_2_M_0
,
1864 VEX_LEN_0FAE_R_3_M_0
,
1873 VEX_LEN_0F381A_P_2_M_0
,
1876 VEX_LEN_0F385A_P_2_M_0
,
1879 VEX_LEN_0F38F3_R_1_P_0
,
1880 VEX_LEN_0F38F3_R_2_P_0
,
1881 VEX_LEN_0F38F3_R_3_P_0
,
1926 VEX_LEN_0FXOP_08_CC
,
1927 VEX_LEN_0FXOP_08_CD
,
1928 VEX_LEN_0FXOP_08_CE
,
1929 VEX_LEN_0FXOP_08_CF
,
1930 VEX_LEN_0FXOP_08_EC
,
1931 VEX_LEN_0FXOP_08_ED
,
1932 VEX_LEN_0FXOP_08_EE
,
1933 VEX_LEN_0FXOP_08_EF
,
1934 VEX_LEN_0FXOP_09_80
,
1968 VEX_W_0F41_P_0_LEN_1
,
1969 VEX_W_0F41_P_2_LEN_1
,
1970 VEX_W_0F42_P_0_LEN_1
,
1971 VEX_W_0F42_P_2_LEN_1
,
1972 VEX_W_0F44_P_0_LEN_0
,
1973 VEX_W_0F44_P_2_LEN_0
,
1974 VEX_W_0F45_P_0_LEN_1
,
1975 VEX_W_0F45_P_2_LEN_1
,
1976 VEX_W_0F46_P_0_LEN_1
,
1977 VEX_W_0F46_P_2_LEN_1
,
1978 VEX_W_0F47_P_0_LEN_1
,
1979 VEX_W_0F47_P_2_LEN_1
,
1980 VEX_W_0F4A_P_0_LEN_1
,
1981 VEX_W_0F4A_P_2_LEN_1
,
1982 VEX_W_0F4B_P_0_LEN_1
,
1983 VEX_W_0F4B_P_2_LEN_1
,
2063 VEX_W_0F90_P_0_LEN_0
,
2064 VEX_W_0F90_P_2_LEN_0
,
2065 VEX_W_0F91_P_0_LEN_0
,
2066 VEX_W_0F91_P_2_LEN_0
,
2067 VEX_W_0F92_P_0_LEN_0
,
2068 VEX_W_0F92_P_2_LEN_0
,
2069 VEX_W_0F92_P_3_LEN_0
,
2070 VEX_W_0F93_P_0_LEN_0
,
2071 VEX_W_0F93_P_2_LEN_0
,
2072 VEX_W_0F93_P_3_LEN_0
,
2073 VEX_W_0F98_P_0_LEN_0
,
2074 VEX_W_0F98_P_2_LEN_0
,
2075 VEX_W_0F99_P_0_LEN_0
,
2076 VEX_W_0F99_P_2_LEN_0
,
2155 VEX_W_0F381A_P_2_M_0
,
2167 VEX_W_0F382A_P_2_M_0
,
2169 VEX_W_0F382C_P_2_M_0
,
2170 VEX_W_0F382D_P_2_M_0
,
2171 VEX_W_0F382E_P_2_M_0
,
2172 VEX_W_0F382F_P_2_M_0
,
2194 VEX_W_0F385A_P_2_M_0
,
2219 VEX_W_0F3A30_P_2_LEN_0
,
2220 VEX_W_0F3A31_P_2_LEN_0
,
2221 VEX_W_0F3A32_P_2_LEN_0
,
2222 VEX_W_0F3A33_P_2_LEN_0
,
2241 EVEX_W_0F10_P_1_M_0
,
2242 EVEX_W_0F10_P_1_M_1
,
2244 EVEX_W_0F10_P_3_M_0
,
2245 EVEX_W_0F10_P_3_M_1
,
2247 EVEX_W_0F11_P_1_M_0
,
2248 EVEX_W_0F11_P_1_M_1
,
2250 EVEX_W_0F11_P_3_M_0
,
2251 EVEX_W_0F11_P_3_M_1
,
2252 EVEX_W_0F12_P_0_M_0
,
2253 EVEX_W_0F12_P_0_M_1
,
2263 EVEX_W_0F16_P_0_M_0
,
2264 EVEX_W_0F16_P_0_M_1
,
2335 EVEX_W_0F72_R_2_P_2
,
2336 EVEX_W_0F72_R_6_P_2
,
2337 EVEX_W_0F73_R_2_P_2
,
2338 EVEX_W_0F73_R_6_P_2
,
2446 EVEX_W_0F38C7_R_1_P_2
,
2447 EVEX_W_0F38C7_R_2_P_2
,
2448 EVEX_W_0F38C7_R_5_P_2
,
2449 EVEX_W_0F38C7_R_6_P_2
,
2490 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2499 unsigned int prefix_requirement
;
2502 /* Upper case letters in the instruction names here are macros.
2503 'A' => print 'b' if no register operands or suffix_always is true
2504 'B' => print 'b' if suffix_always is true
2505 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2507 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2508 suffix_always is true
2509 'E' => print 'e' if 32-bit form of jcxz
2510 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2511 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2512 'H' => print ",pt" or ",pn" branch hint
2513 'I' => honor following macro letter even in Intel mode (implemented only
2514 for some of the macro letters)
2516 'K' => print 'd' or 'q' if rex prefix is present.
2517 'L' => print 'l' if suffix_always is true
2518 'M' => print 'r' if intel_mnemonic is false.
2519 'N' => print 'n' if instruction has no wait "prefix"
2520 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2521 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2522 or suffix_always is true. print 'q' if rex prefix is present.
2523 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2525 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2526 'S' => print 'w', 'l' or 'q' if suffix_always is true
2527 'T' => print 'q' in 64bit mode if instruction has no operand size
2528 prefix and behave as 'P' otherwise
2529 'U' => print 'q' in 64bit mode if instruction has no operand size
2530 prefix and behave as 'Q' otherwise
2531 'V' => print 'q' in 64bit mode if instruction has no operand size
2532 prefix and behave as 'S' otherwise
2533 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2534 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2535 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2536 suffix_always is true.
2537 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2538 '!' => change condition from true to false or from false to true.
2539 '%' => add 1 upper case letter to the macro.
2540 '^' => print 'w' or 'l' depending on operand size prefix or
2541 suffix_always is true (lcall/ljmp).
2542 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2543 on operand size prefix.
2544 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2545 has no operand size prefix for AMD64 ISA, behave as 'P'
2548 2 upper case letter macros:
2549 "XY" => print 'x' or 'y' if suffix_always is true or no register
2550 operands and no broadcast.
2551 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2552 register operands and no broadcast.
2553 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2554 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2555 or suffix_always is true
2556 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2557 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2558 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2559 "LW" => print 'd', 'q' depending on the VEX.W bit
2560 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2561 an operand size prefix, or suffix_always is true. print
2562 'q' if rex prefix is present.
2564 Many of the above letters print nothing in Intel mode. See "putop"
2567 Braces '{' and '}', and vertical bars '|', indicate alternative
2568 mnemonic strings for AT&T and Intel. */
2570 static const struct dis386 dis386
[] = {
2572 { "addB", { Ebh1
, Gb
}, 0 },
2573 { "addS", { Evh1
, Gv
}, 0 },
2574 { "addB", { Gb
, EbS
}, 0 },
2575 { "addS", { Gv
, EvS
}, 0 },
2576 { "addB", { AL
, Ib
}, 0 },
2577 { "addS", { eAX
, Iv
}, 0 },
2578 { X86_64_TABLE (X86_64_06
) },
2579 { X86_64_TABLE (X86_64_07
) },
2581 { "orB", { Ebh1
, Gb
}, 0 },
2582 { "orS", { Evh1
, Gv
}, 0 },
2583 { "orB", { Gb
, EbS
}, 0 },
2584 { "orS", { Gv
, EvS
}, 0 },
2585 { "orB", { AL
, Ib
}, 0 },
2586 { "orS", { eAX
, Iv
}, 0 },
2587 { X86_64_TABLE (X86_64_0D
) },
2588 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2590 { "adcB", { Ebh1
, Gb
}, 0 },
2591 { "adcS", { Evh1
, Gv
}, 0 },
2592 { "adcB", { Gb
, EbS
}, 0 },
2593 { "adcS", { Gv
, EvS
}, 0 },
2594 { "adcB", { AL
, Ib
}, 0 },
2595 { "adcS", { eAX
, Iv
}, 0 },
2596 { X86_64_TABLE (X86_64_16
) },
2597 { X86_64_TABLE (X86_64_17
) },
2599 { "sbbB", { Ebh1
, Gb
}, 0 },
2600 { "sbbS", { Evh1
, Gv
}, 0 },
2601 { "sbbB", { Gb
, EbS
}, 0 },
2602 { "sbbS", { Gv
, EvS
}, 0 },
2603 { "sbbB", { AL
, Ib
}, 0 },
2604 { "sbbS", { eAX
, Iv
}, 0 },
2605 { X86_64_TABLE (X86_64_1E
) },
2606 { X86_64_TABLE (X86_64_1F
) },
2608 { "andB", { Ebh1
, Gb
}, 0 },
2609 { "andS", { Evh1
, Gv
}, 0 },
2610 { "andB", { Gb
, EbS
}, 0 },
2611 { "andS", { Gv
, EvS
}, 0 },
2612 { "andB", { AL
, Ib
}, 0 },
2613 { "andS", { eAX
, Iv
}, 0 },
2614 { Bad_Opcode
}, /* SEG ES prefix */
2615 { X86_64_TABLE (X86_64_27
) },
2617 { "subB", { Ebh1
, Gb
}, 0 },
2618 { "subS", { Evh1
, Gv
}, 0 },
2619 { "subB", { Gb
, EbS
}, 0 },
2620 { "subS", { Gv
, EvS
}, 0 },
2621 { "subB", { AL
, Ib
}, 0 },
2622 { "subS", { eAX
, Iv
}, 0 },
2623 { Bad_Opcode
}, /* SEG CS prefix */
2624 { X86_64_TABLE (X86_64_2F
) },
2626 { "xorB", { Ebh1
, Gb
}, 0 },
2627 { "xorS", { Evh1
, Gv
}, 0 },
2628 { "xorB", { Gb
, EbS
}, 0 },
2629 { "xorS", { Gv
, EvS
}, 0 },
2630 { "xorB", { AL
, Ib
}, 0 },
2631 { "xorS", { eAX
, Iv
}, 0 },
2632 { Bad_Opcode
}, /* SEG SS prefix */
2633 { X86_64_TABLE (X86_64_37
) },
2635 { "cmpB", { Eb
, Gb
}, 0 },
2636 { "cmpS", { Ev
, Gv
}, 0 },
2637 { "cmpB", { Gb
, EbS
}, 0 },
2638 { "cmpS", { Gv
, EvS
}, 0 },
2639 { "cmpB", { AL
, Ib
}, 0 },
2640 { "cmpS", { eAX
, Iv
}, 0 },
2641 { Bad_Opcode
}, /* SEG DS prefix */
2642 { X86_64_TABLE (X86_64_3F
) },
2644 { "inc{S|}", { RMeAX
}, 0 },
2645 { "inc{S|}", { RMeCX
}, 0 },
2646 { "inc{S|}", { RMeDX
}, 0 },
2647 { "inc{S|}", { RMeBX
}, 0 },
2648 { "inc{S|}", { RMeSP
}, 0 },
2649 { "inc{S|}", { RMeBP
}, 0 },
2650 { "inc{S|}", { RMeSI
}, 0 },
2651 { "inc{S|}", { RMeDI
}, 0 },
2653 { "dec{S|}", { RMeAX
}, 0 },
2654 { "dec{S|}", { RMeCX
}, 0 },
2655 { "dec{S|}", { RMeDX
}, 0 },
2656 { "dec{S|}", { RMeBX
}, 0 },
2657 { "dec{S|}", { RMeSP
}, 0 },
2658 { "dec{S|}", { RMeBP
}, 0 },
2659 { "dec{S|}", { RMeSI
}, 0 },
2660 { "dec{S|}", { RMeDI
}, 0 },
2662 { "pushV", { RMrAX
}, 0 },
2663 { "pushV", { RMrCX
}, 0 },
2664 { "pushV", { RMrDX
}, 0 },
2665 { "pushV", { RMrBX
}, 0 },
2666 { "pushV", { RMrSP
}, 0 },
2667 { "pushV", { RMrBP
}, 0 },
2668 { "pushV", { RMrSI
}, 0 },
2669 { "pushV", { RMrDI
}, 0 },
2671 { "popV", { RMrAX
}, 0 },
2672 { "popV", { RMrCX
}, 0 },
2673 { "popV", { RMrDX
}, 0 },
2674 { "popV", { RMrBX
}, 0 },
2675 { "popV", { RMrSP
}, 0 },
2676 { "popV", { RMrBP
}, 0 },
2677 { "popV", { RMrSI
}, 0 },
2678 { "popV", { RMrDI
}, 0 },
2680 { X86_64_TABLE (X86_64_60
) },
2681 { X86_64_TABLE (X86_64_61
) },
2682 { X86_64_TABLE (X86_64_62
) },
2683 { X86_64_TABLE (X86_64_63
) },
2684 { Bad_Opcode
}, /* seg fs */
2685 { Bad_Opcode
}, /* seg gs */
2686 { Bad_Opcode
}, /* op size prefix */
2687 { Bad_Opcode
}, /* adr size prefix */
2689 { "pushT", { sIv
}, 0 },
2690 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2691 { "pushT", { sIbT
}, 0 },
2692 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2693 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2694 { X86_64_TABLE (X86_64_6D
) },
2695 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2696 { X86_64_TABLE (X86_64_6F
) },
2698 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2699 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2700 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2701 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2702 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2703 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2704 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2705 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2707 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2708 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2709 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2710 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2711 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2712 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2713 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2714 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2716 { REG_TABLE (REG_80
) },
2717 { REG_TABLE (REG_81
) },
2718 { X86_64_TABLE (X86_64_82
) },
2719 { REG_TABLE (REG_83
) },
2720 { "testB", { Eb
, Gb
}, 0 },
2721 { "testS", { Ev
, Gv
}, 0 },
2722 { "xchgB", { Ebh2
, Gb
}, 0 },
2723 { "xchgS", { Evh2
, Gv
}, 0 },
2725 { "movB", { Ebh3
, Gb
}, 0 },
2726 { "movS", { Evh3
, Gv
}, 0 },
2727 { "movB", { Gb
, EbS
}, 0 },
2728 { "movS", { Gv
, EvS
}, 0 },
2729 { "movD", { Sv
, Sw
}, 0 },
2730 { MOD_TABLE (MOD_8D
) },
2731 { "movD", { Sw
, Sv
}, 0 },
2732 { REG_TABLE (REG_8F
) },
2734 { PREFIX_TABLE (PREFIX_90
) },
2735 { "xchgS", { RMeCX
, eAX
}, 0 },
2736 { "xchgS", { RMeDX
, eAX
}, 0 },
2737 { "xchgS", { RMeBX
, eAX
}, 0 },
2738 { "xchgS", { RMeSP
, eAX
}, 0 },
2739 { "xchgS", { RMeBP
, eAX
}, 0 },
2740 { "xchgS", { RMeSI
, eAX
}, 0 },
2741 { "xchgS", { RMeDI
, eAX
}, 0 },
2743 { "cW{t|}R", { XX
}, 0 },
2744 { "cR{t|}O", { XX
}, 0 },
2745 { X86_64_TABLE (X86_64_9A
) },
2746 { Bad_Opcode
}, /* fwait */
2747 { "pushfT", { XX
}, 0 },
2748 { "popfT", { XX
}, 0 },
2749 { "sahf", { XX
}, 0 },
2750 { "lahf", { XX
}, 0 },
2752 { "mov%LB", { AL
, Ob
}, 0 },
2753 { "mov%LS", { eAX
, Ov
}, 0 },
2754 { "mov%LB", { Ob
, AL
}, 0 },
2755 { "mov%LS", { Ov
, eAX
}, 0 },
2756 { "movs{b|}", { Ybr
, Xb
}, 0 },
2757 { "movs{R|}", { Yvr
, Xv
}, 0 },
2758 { "cmps{b|}", { Xb
, Yb
}, 0 },
2759 { "cmps{R|}", { Xv
, Yv
}, 0 },
2761 { "testB", { AL
, Ib
}, 0 },
2762 { "testS", { eAX
, Iv
}, 0 },
2763 { "stosB", { Ybr
, AL
}, 0 },
2764 { "stosS", { Yvr
, eAX
}, 0 },
2765 { "lodsB", { ALr
, Xb
}, 0 },
2766 { "lodsS", { eAXr
, Xv
}, 0 },
2767 { "scasB", { AL
, Yb
}, 0 },
2768 { "scasS", { eAX
, Yv
}, 0 },
2770 { "movB", { RMAL
, Ib
}, 0 },
2771 { "movB", { RMCL
, Ib
}, 0 },
2772 { "movB", { RMDL
, Ib
}, 0 },
2773 { "movB", { RMBL
, Ib
}, 0 },
2774 { "movB", { RMAH
, Ib
}, 0 },
2775 { "movB", { RMCH
, Ib
}, 0 },
2776 { "movB", { RMDH
, Ib
}, 0 },
2777 { "movB", { RMBH
, Ib
}, 0 },
2779 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2780 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2781 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2782 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2783 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2784 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2785 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2786 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2788 { REG_TABLE (REG_C0
) },
2789 { REG_TABLE (REG_C1
) },
2790 { "retT", { Iw
, BND
}, 0 },
2791 { "retT", { BND
}, 0 },
2792 { X86_64_TABLE (X86_64_C4
) },
2793 { X86_64_TABLE (X86_64_C5
) },
2794 { REG_TABLE (REG_C6
) },
2795 { REG_TABLE (REG_C7
) },
2797 { "enterT", { Iw
, Ib
}, 0 },
2798 { "leaveT", { XX
}, 0 },
2799 { "Jret{|f}P", { Iw
}, 0 },
2800 { "Jret{|f}P", { XX
}, 0 },
2801 { "int3", { XX
}, 0 },
2802 { "int", { Ib
}, 0 },
2803 { X86_64_TABLE (X86_64_CE
) },
2804 { "iret%LP", { XX
}, 0 },
2806 { REG_TABLE (REG_D0
) },
2807 { REG_TABLE (REG_D1
) },
2808 { REG_TABLE (REG_D2
) },
2809 { REG_TABLE (REG_D3
) },
2810 { X86_64_TABLE (X86_64_D4
) },
2811 { X86_64_TABLE (X86_64_D5
) },
2813 { "xlat", { DSBX
}, 0 },
2824 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2825 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2826 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2827 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2828 { "inB", { AL
, Ib
}, 0 },
2829 { "inG", { zAX
, Ib
}, 0 },
2830 { "outB", { Ib
, AL
}, 0 },
2831 { "outG", { Ib
, zAX
}, 0 },
2833 { X86_64_TABLE (X86_64_E8
) },
2834 { X86_64_TABLE (X86_64_E9
) },
2835 { X86_64_TABLE (X86_64_EA
) },
2836 { "jmp", { Jb
, BND
}, 0 },
2837 { "inB", { AL
, indirDX
}, 0 },
2838 { "inG", { zAX
, indirDX
}, 0 },
2839 { "outB", { indirDX
, AL
}, 0 },
2840 { "outG", { indirDX
, zAX
}, 0 },
2842 { Bad_Opcode
}, /* lock prefix */
2843 { "icebp", { XX
}, 0 },
2844 { Bad_Opcode
}, /* repne */
2845 { Bad_Opcode
}, /* repz */
2846 { "hlt", { XX
}, 0 },
2847 { "cmc", { XX
}, 0 },
2848 { REG_TABLE (REG_F6
) },
2849 { REG_TABLE (REG_F7
) },
2851 { "clc", { XX
}, 0 },
2852 { "stc", { XX
}, 0 },
2853 { "cli", { XX
}, 0 },
2854 { "sti", { XX
}, 0 },
2855 { "cld", { XX
}, 0 },
2856 { "std", { XX
}, 0 },
2857 { REG_TABLE (REG_FE
) },
2858 { REG_TABLE (REG_FF
) },
2861 static const struct dis386 dis386_twobyte
[] = {
2863 { REG_TABLE (REG_0F00
) },
2864 { REG_TABLE (REG_0F01
) },
2865 { "larS", { Gv
, Ew
}, 0 },
2866 { "lslS", { Gv
, Ew
}, 0 },
2868 { "syscall", { XX
}, 0 },
2869 { "clts", { XX
}, 0 },
2870 { "sysret%LP", { XX
}, 0 },
2872 { "invd", { XX
}, 0 },
2873 { PREFIX_TABLE (PREFIX_0F09
) },
2875 { "ud2", { XX
}, 0 },
2877 { REG_TABLE (REG_0F0D
) },
2878 { "femms", { XX
}, 0 },
2879 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2881 { PREFIX_TABLE (PREFIX_0F10
) },
2882 { PREFIX_TABLE (PREFIX_0F11
) },
2883 { PREFIX_TABLE (PREFIX_0F12
) },
2884 { MOD_TABLE (MOD_0F13
) },
2885 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2886 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2887 { PREFIX_TABLE (PREFIX_0F16
) },
2888 { MOD_TABLE (MOD_0F17
) },
2890 { REG_TABLE (REG_0F18
) },
2891 { "nopQ", { Ev
}, 0 },
2892 { PREFIX_TABLE (PREFIX_0F1A
) },
2893 { PREFIX_TABLE (PREFIX_0F1B
) },
2894 { "nopQ", { Ev
}, 0 },
2895 { "nopQ", { Ev
}, 0 },
2896 { PREFIX_TABLE (PREFIX_0F1E
) },
2897 { "nopQ", { Ev
}, 0 },
2899 { "movZ", { Rm
, Cm
}, 0 },
2900 { "movZ", { Rm
, Dm
}, 0 },
2901 { "movZ", { Cm
, Rm
}, 0 },
2902 { "movZ", { Dm
, Rm
}, 0 },
2903 { MOD_TABLE (MOD_0F24
) },
2905 { MOD_TABLE (MOD_0F26
) },
2908 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2909 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2910 { PREFIX_TABLE (PREFIX_0F2A
) },
2911 { PREFIX_TABLE (PREFIX_0F2B
) },
2912 { PREFIX_TABLE (PREFIX_0F2C
) },
2913 { PREFIX_TABLE (PREFIX_0F2D
) },
2914 { PREFIX_TABLE (PREFIX_0F2E
) },
2915 { PREFIX_TABLE (PREFIX_0F2F
) },
2917 { "wrmsr", { XX
}, 0 },
2918 { "rdtsc", { XX
}, 0 },
2919 { "rdmsr", { XX
}, 0 },
2920 { "rdpmc", { XX
}, 0 },
2921 { "sysenter", { XX
}, 0 },
2922 { "sysexit", { XX
}, 0 },
2924 { "getsec", { XX
}, 0 },
2926 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2928 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2935 { "cmovoS", { Gv
, Ev
}, 0 },
2936 { "cmovnoS", { Gv
, Ev
}, 0 },
2937 { "cmovbS", { Gv
, Ev
}, 0 },
2938 { "cmovaeS", { Gv
, Ev
}, 0 },
2939 { "cmoveS", { Gv
, Ev
}, 0 },
2940 { "cmovneS", { Gv
, Ev
}, 0 },
2941 { "cmovbeS", { Gv
, Ev
}, 0 },
2942 { "cmovaS", { Gv
, Ev
}, 0 },
2944 { "cmovsS", { Gv
, Ev
}, 0 },
2945 { "cmovnsS", { Gv
, Ev
}, 0 },
2946 { "cmovpS", { Gv
, Ev
}, 0 },
2947 { "cmovnpS", { Gv
, Ev
}, 0 },
2948 { "cmovlS", { Gv
, Ev
}, 0 },
2949 { "cmovgeS", { Gv
, Ev
}, 0 },
2950 { "cmovleS", { Gv
, Ev
}, 0 },
2951 { "cmovgS", { Gv
, Ev
}, 0 },
2953 { MOD_TABLE (MOD_0F51
) },
2954 { PREFIX_TABLE (PREFIX_0F51
) },
2955 { PREFIX_TABLE (PREFIX_0F52
) },
2956 { PREFIX_TABLE (PREFIX_0F53
) },
2957 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2958 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2959 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2960 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2962 { PREFIX_TABLE (PREFIX_0F58
) },
2963 { PREFIX_TABLE (PREFIX_0F59
) },
2964 { PREFIX_TABLE (PREFIX_0F5A
) },
2965 { PREFIX_TABLE (PREFIX_0F5B
) },
2966 { PREFIX_TABLE (PREFIX_0F5C
) },
2967 { PREFIX_TABLE (PREFIX_0F5D
) },
2968 { PREFIX_TABLE (PREFIX_0F5E
) },
2969 { PREFIX_TABLE (PREFIX_0F5F
) },
2971 { PREFIX_TABLE (PREFIX_0F60
) },
2972 { PREFIX_TABLE (PREFIX_0F61
) },
2973 { PREFIX_TABLE (PREFIX_0F62
) },
2974 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2975 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2976 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2977 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2978 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2980 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2981 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2982 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2983 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2984 { PREFIX_TABLE (PREFIX_0F6C
) },
2985 { PREFIX_TABLE (PREFIX_0F6D
) },
2986 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2987 { PREFIX_TABLE (PREFIX_0F6F
) },
2989 { PREFIX_TABLE (PREFIX_0F70
) },
2990 { REG_TABLE (REG_0F71
) },
2991 { REG_TABLE (REG_0F72
) },
2992 { REG_TABLE (REG_0F73
) },
2993 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2994 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2995 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2996 { "emms", { XX
}, PREFIX_OPCODE
},
2998 { PREFIX_TABLE (PREFIX_0F78
) },
2999 { PREFIX_TABLE (PREFIX_0F79
) },
3002 { PREFIX_TABLE (PREFIX_0F7C
) },
3003 { PREFIX_TABLE (PREFIX_0F7D
) },
3004 { PREFIX_TABLE (PREFIX_0F7E
) },
3005 { PREFIX_TABLE (PREFIX_0F7F
) },
3007 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
3008 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
3009 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
3010 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3011 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3012 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
3013 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3014 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
3016 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
3017 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
3018 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
3019 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
3020 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
3021 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3022 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
3023 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
3025 { "seto", { Eb
}, 0 },
3026 { "setno", { Eb
}, 0 },
3027 { "setb", { Eb
}, 0 },
3028 { "setae", { Eb
}, 0 },
3029 { "sete", { Eb
}, 0 },
3030 { "setne", { Eb
}, 0 },
3031 { "setbe", { Eb
}, 0 },
3032 { "seta", { Eb
}, 0 },
3034 { "sets", { Eb
}, 0 },
3035 { "setns", { Eb
}, 0 },
3036 { "setp", { Eb
}, 0 },
3037 { "setnp", { Eb
}, 0 },
3038 { "setl", { Eb
}, 0 },
3039 { "setge", { Eb
}, 0 },
3040 { "setle", { Eb
}, 0 },
3041 { "setg", { Eb
}, 0 },
3043 { "pushT", { fs
}, 0 },
3044 { "popT", { fs
}, 0 },
3045 { "cpuid", { XX
}, 0 },
3046 { "btS", { Ev
, Gv
}, 0 },
3047 { "shldS", { Ev
, Gv
, Ib
}, 0 },
3048 { "shldS", { Ev
, Gv
, CL
}, 0 },
3049 { REG_TABLE (REG_0FA6
) },
3050 { REG_TABLE (REG_0FA7
) },
3052 { "pushT", { gs
}, 0 },
3053 { "popT", { gs
}, 0 },
3054 { "rsm", { XX
}, 0 },
3055 { "btsS", { Evh1
, Gv
}, 0 },
3056 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
3057 { "shrdS", { Ev
, Gv
, CL
}, 0 },
3058 { REG_TABLE (REG_0FAE
) },
3059 { "imulS", { Gv
, Ev
}, 0 },
3061 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
3062 { "cmpxchgS", { Evh1
, Gv
}, 0 },
3063 { MOD_TABLE (MOD_0FB2
) },
3064 { "btrS", { Evh1
, Gv
}, 0 },
3065 { MOD_TABLE (MOD_0FB4
) },
3066 { MOD_TABLE (MOD_0FB5
) },
3067 { "movz{bR|x}", { Gv
, Eb
}, 0 },
3068 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
3070 { PREFIX_TABLE (PREFIX_0FB8
) },
3071 { "ud1S", { Gv
, Ev
}, 0 },
3072 { REG_TABLE (REG_0FBA
) },
3073 { "btcS", { Evh1
, Gv
}, 0 },
3074 { PREFIX_TABLE (PREFIX_0FBC
) },
3075 { PREFIX_TABLE (PREFIX_0FBD
) },
3076 { "movs{bR|x}", { Gv
, Eb
}, 0 },
3077 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
3079 { "xaddB", { Ebh1
, Gb
}, 0 },
3080 { "xaddS", { Evh1
, Gv
}, 0 },
3081 { PREFIX_TABLE (PREFIX_0FC2
) },
3082 { MOD_TABLE (MOD_0FC3
) },
3083 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
3084 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
3085 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3086 { REG_TABLE (REG_0FC7
) },
3088 { "bswap", { RMeAX
}, 0 },
3089 { "bswap", { RMeCX
}, 0 },
3090 { "bswap", { RMeDX
}, 0 },
3091 { "bswap", { RMeBX
}, 0 },
3092 { "bswap", { RMeSP
}, 0 },
3093 { "bswap", { RMeBP
}, 0 },
3094 { "bswap", { RMeSI
}, 0 },
3095 { "bswap", { RMeDI
}, 0 },
3097 { PREFIX_TABLE (PREFIX_0FD0
) },
3098 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
3099 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
3100 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
3101 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
3102 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
3103 { PREFIX_TABLE (PREFIX_0FD6
) },
3104 { MOD_TABLE (MOD_0FD7
) },
3106 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
3107 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
3108 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
3109 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
3110 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
3111 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
3112 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
3113 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
3115 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
3116 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
3117 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
3118 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
3119 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
3120 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
3121 { PREFIX_TABLE (PREFIX_0FE6
) },
3122 { PREFIX_TABLE (PREFIX_0FE7
) },
3124 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
3125 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
3126 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
3127 { "por", { MX
, EM
}, PREFIX_OPCODE
},
3128 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
3129 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
3130 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
3131 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
3133 { PREFIX_TABLE (PREFIX_0FF0
) },
3134 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
3135 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
3136 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
3137 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
3138 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
3139 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
3140 { PREFIX_TABLE (PREFIX_0FF7
) },
3142 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
3143 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
3144 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
3145 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
3146 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
3147 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
3148 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
3149 { "ud0S", { Gv
, Ev
}, 0 },
3152 static const unsigned char onebyte_has_modrm
[256] = {
3153 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3154 /* ------------------------------- */
3155 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3156 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3157 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3158 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3159 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3160 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3161 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3162 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3163 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3164 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3165 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3166 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3167 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3168 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3169 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3170 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3171 /* ------------------------------- */
3172 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3175 static const unsigned char twobyte_has_modrm
[256] = {
3176 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3177 /* ------------------------------- */
3178 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3179 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3180 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3181 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3182 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3183 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3184 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3185 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3186 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3187 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3188 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3189 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3190 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3191 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3192 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3193 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
3194 /* ------------------------------- */
3195 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3198 static char obuf
[100];
3200 static char *mnemonicendp
;
3201 static char scratchbuf
[100];
3202 static unsigned char *start_codep
;
3203 static unsigned char *insn_codep
;
3204 static unsigned char *codep
;
3205 static unsigned char *end_codep
;
3206 static int last_lock_prefix
;
3207 static int last_repz_prefix
;
3208 static int last_repnz_prefix
;
3209 static int last_data_prefix
;
3210 static int last_addr_prefix
;
3211 static int last_rex_prefix
;
3212 static int last_seg_prefix
;
3213 static int fwait_prefix
;
3214 /* The active segment register prefix. */
3215 static int active_seg_prefix
;
3216 #define MAX_CODE_LENGTH 15
3217 /* We can up to 14 prefixes since the maximum instruction length is
3219 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3220 static disassemble_info
*the_info
;
3228 static unsigned char need_modrm
;
3238 int register_specifier
;
3245 int mask_register_specifier
;
3251 static unsigned char need_vex
;
3252 static unsigned char need_vex_reg
;
3253 static unsigned char vex_w_done
;
3261 /* If we are accessing mod/rm/reg without need_modrm set, then the
3262 values are stale. Hitting this abort likely indicates that you
3263 need to update onebyte_has_modrm or twobyte_has_modrm. */
3264 #define MODRM_CHECK if (!need_modrm) abort ()
3266 static const char **names64
;
3267 static const char **names32
;
3268 static const char **names16
;
3269 static const char **names8
;
3270 static const char **names8rex
;
3271 static const char **names_seg
;
3272 static const char *index64
;
3273 static const char *index32
;
3274 static const char **index16
;
3275 static const char **names_bnd
;
3277 static const char *intel_names64
[] = {
3278 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3279 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3281 static const char *intel_names32
[] = {
3282 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3283 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3285 static const char *intel_names16
[] = {
3286 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3287 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3289 static const char *intel_names8
[] = {
3290 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3292 static const char *intel_names8rex
[] = {
3293 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3294 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3296 static const char *intel_names_seg
[] = {
3297 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3299 static const char *intel_index64
= "riz";
3300 static const char *intel_index32
= "eiz";
3301 static const char *intel_index16
[] = {
3302 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3305 static const char *att_names64
[] = {
3306 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3307 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3309 static const char *att_names32
[] = {
3310 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3311 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3313 static const char *att_names16
[] = {
3314 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3315 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3317 static const char *att_names8
[] = {
3318 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3320 static const char *att_names8rex
[] = {
3321 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3322 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3324 static const char *att_names_seg
[] = {
3325 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3327 static const char *att_index64
= "%riz";
3328 static const char *att_index32
= "%eiz";
3329 static const char *att_index16
[] = {
3330 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3333 static const char **names_mm
;
3334 static const char *intel_names_mm
[] = {
3335 "mm0", "mm1", "mm2", "mm3",
3336 "mm4", "mm5", "mm6", "mm7"
3338 static const char *att_names_mm
[] = {
3339 "%mm0", "%mm1", "%mm2", "%mm3",
3340 "%mm4", "%mm5", "%mm6", "%mm7"
3343 static const char *intel_names_bnd
[] = {
3344 "bnd0", "bnd1", "bnd2", "bnd3"
3347 static const char *att_names_bnd
[] = {
3348 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3351 static const char **names_xmm
;
3352 static const char *intel_names_xmm
[] = {
3353 "xmm0", "xmm1", "xmm2", "xmm3",
3354 "xmm4", "xmm5", "xmm6", "xmm7",
3355 "xmm8", "xmm9", "xmm10", "xmm11",
3356 "xmm12", "xmm13", "xmm14", "xmm15",
3357 "xmm16", "xmm17", "xmm18", "xmm19",
3358 "xmm20", "xmm21", "xmm22", "xmm23",
3359 "xmm24", "xmm25", "xmm26", "xmm27",
3360 "xmm28", "xmm29", "xmm30", "xmm31"
3362 static const char *att_names_xmm
[] = {
3363 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3364 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3365 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3366 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3367 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3368 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3369 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3370 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3373 static const char **names_ymm
;
3374 static const char *intel_names_ymm
[] = {
3375 "ymm0", "ymm1", "ymm2", "ymm3",
3376 "ymm4", "ymm5", "ymm6", "ymm7",
3377 "ymm8", "ymm9", "ymm10", "ymm11",
3378 "ymm12", "ymm13", "ymm14", "ymm15",
3379 "ymm16", "ymm17", "ymm18", "ymm19",
3380 "ymm20", "ymm21", "ymm22", "ymm23",
3381 "ymm24", "ymm25", "ymm26", "ymm27",
3382 "ymm28", "ymm29", "ymm30", "ymm31"
3384 static const char *att_names_ymm
[] = {
3385 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3386 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3387 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3388 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3389 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3390 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3391 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3392 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3395 static const char **names_zmm
;
3396 static const char *intel_names_zmm
[] = {
3397 "zmm0", "zmm1", "zmm2", "zmm3",
3398 "zmm4", "zmm5", "zmm6", "zmm7",
3399 "zmm8", "zmm9", "zmm10", "zmm11",
3400 "zmm12", "zmm13", "zmm14", "zmm15",
3401 "zmm16", "zmm17", "zmm18", "zmm19",
3402 "zmm20", "zmm21", "zmm22", "zmm23",
3403 "zmm24", "zmm25", "zmm26", "zmm27",
3404 "zmm28", "zmm29", "zmm30", "zmm31"
3406 static const char *att_names_zmm
[] = {
3407 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3408 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3409 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3410 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3411 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3412 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3413 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3414 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3417 static const char **names_mask
;
3418 static const char *intel_names_mask
[] = {
3419 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3421 static const char *att_names_mask
[] = {
3422 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3425 static const char *names_rounding
[] =
3433 static const struct dis386 reg_table
[][8] = {
3436 { "addA", { Ebh1
, Ib
}, 0 },
3437 { "orA", { Ebh1
, Ib
}, 0 },
3438 { "adcA", { Ebh1
, Ib
}, 0 },
3439 { "sbbA", { Ebh1
, Ib
}, 0 },
3440 { "andA", { Ebh1
, Ib
}, 0 },
3441 { "subA", { Ebh1
, Ib
}, 0 },
3442 { "xorA", { Ebh1
, Ib
}, 0 },
3443 { "cmpA", { Eb
, Ib
}, 0 },
3447 { "addQ", { Evh1
, Iv
}, 0 },
3448 { "orQ", { Evh1
, Iv
}, 0 },
3449 { "adcQ", { Evh1
, Iv
}, 0 },
3450 { "sbbQ", { Evh1
, Iv
}, 0 },
3451 { "andQ", { Evh1
, Iv
}, 0 },
3452 { "subQ", { Evh1
, Iv
}, 0 },
3453 { "xorQ", { Evh1
, Iv
}, 0 },
3454 { "cmpQ", { Ev
, Iv
}, 0 },
3458 { "addQ", { Evh1
, sIb
}, 0 },
3459 { "orQ", { Evh1
, sIb
}, 0 },
3460 { "adcQ", { Evh1
, sIb
}, 0 },
3461 { "sbbQ", { Evh1
, sIb
}, 0 },
3462 { "andQ", { Evh1
, sIb
}, 0 },
3463 { "subQ", { Evh1
, sIb
}, 0 },
3464 { "xorQ", { Evh1
, sIb
}, 0 },
3465 { "cmpQ", { Ev
, sIb
}, 0 },
3469 { "popU", { stackEv
}, 0 },
3470 { XOP_8F_TABLE (XOP_09
) },
3474 { XOP_8F_TABLE (XOP_09
) },
3478 { "rolA", { Eb
, Ib
}, 0 },
3479 { "rorA", { Eb
, Ib
}, 0 },
3480 { "rclA", { Eb
, Ib
}, 0 },
3481 { "rcrA", { Eb
, Ib
}, 0 },
3482 { "shlA", { Eb
, Ib
}, 0 },
3483 { "shrA", { Eb
, Ib
}, 0 },
3484 { "shlA", { Eb
, Ib
}, 0 },
3485 { "sarA", { Eb
, Ib
}, 0 },
3489 { "rolQ", { Ev
, Ib
}, 0 },
3490 { "rorQ", { Ev
, Ib
}, 0 },
3491 { "rclQ", { Ev
, Ib
}, 0 },
3492 { "rcrQ", { Ev
, Ib
}, 0 },
3493 { "shlQ", { Ev
, Ib
}, 0 },
3494 { "shrQ", { Ev
, Ib
}, 0 },
3495 { "shlQ", { Ev
, Ib
}, 0 },
3496 { "sarQ", { Ev
, Ib
}, 0 },
3500 { "movA", { Ebh3
, Ib
}, 0 },
3507 { MOD_TABLE (MOD_C6_REG_7
) },
3511 { "movQ", { Evh3
, Iv
}, 0 },
3518 { MOD_TABLE (MOD_C7_REG_7
) },
3522 { "rolA", { Eb
, I1
}, 0 },
3523 { "rorA", { Eb
, I1
}, 0 },
3524 { "rclA", { Eb
, I1
}, 0 },
3525 { "rcrA", { Eb
, I1
}, 0 },
3526 { "shlA", { Eb
, I1
}, 0 },
3527 { "shrA", { Eb
, I1
}, 0 },
3528 { "shlA", { Eb
, I1
}, 0 },
3529 { "sarA", { Eb
, I1
}, 0 },
3533 { "rolQ", { Ev
, I1
}, 0 },
3534 { "rorQ", { Ev
, I1
}, 0 },
3535 { "rclQ", { Ev
, I1
}, 0 },
3536 { "rcrQ", { Ev
, I1
}, 0 },
3537 { "shlQ", { Ev
, I1
}, 0 },
3538 { "shrQ", { Ev
, I1
}, 0 },
3539 { "shlQ", { Ev
, I1
}, 0 },
3540 { "sarQ", { Ev
, I1
}, 0 },
3544 { "rolA", { Eb
, CL
}, 0 },
3545 { "rorA", { Eb
, CL
}, 0 },
3546 { "rclA", { Eb
, CL
}, 0 },
3547 { "rcrA", { Eb
, CL
}, 0 },
3548 { "shlA", { Eb
, CL
}, 0 },
3549 { "shrA", { Eb
, CL
}, 0 },
3550 { "shlA", { Eb
, CL
}, 0 },
3551 { "sarA", { Eb
, CL
}, 0 },
3555 { "rolQ", { Ev
, CL
}, 0 },
3556 { "rorQ", { Ev
, CL
}, 0 },
3557 { "rclQ", { Ev
, CL
}, 0 },
3558 { "rcrQ", { Ev
, CL
}, 0 },
3559 { "shlQ", { Ev
, CL
}, 0 },
3560 { "shrQ", { Ev
, CL
}, 0 },
3561 { "shlQ", { Ev
, CL
}, 0 },
3562 { "sarQ", { Ev
, CL
}, 0 },
3566 { "testA", { Eb
, Ib
}, 0 },
3567 { "testA", { Eb
, Ib
}, 0 },
3568 { "notA", { Ebh1
}, 0 },
3569 { "negA", { Ebh1
}, 0 },
3570 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3571 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3572 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3573 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3577 { "testQ", { Ev
, Iv
}, 0 },
3578 { "testQ", { Ev
, Iv
}, 0 },
3579 { "notQ", { Evh1
}, 0 },
3580 { "negQ", { Evh1
}, 0 },
3581 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3582 { "imulQ", { Ev
}, 0 },
3583 { "divQ", { Ev
}, 0 },
3584 { "idivQ", { Ev
}, 0 },
3588 { "incA", { Ebh1
}, 0 },
3589 { "decA", { Ebh1
}, 0 },
3593 { "incQ", { Evh1
}, 0 },
3594 { "decQ", { Evh1
}, 0 },
3595 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3596 { MOD_TABLE (MOD_FF_REG_3
) },
3597 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3598 { MOD_TABLE (MOD_FF_REG_5
) },
3599 { "pushU", { stackEv
}, 0 },
3604 { "sldtD", { Sv
}, 0 },
3605 { "strD", { Sv
}, 0 },
3606 { "lldt", { Ew
}, 0 },
3607 { "ltr", { Ew
}, 0 },
3608 { "verr", { Ew
}, 0 },
3609 { "verw", { Ew
}, 0 },
3615 { MOD_TABLE (MOD_0F01_REG_0
) },
3616 { MOD_TABLE (MOD_0F01_REG_1
) },
3617 { MOD_TABLE (MOD_0F01_REG_2
) },
3618 { MOD_TABLE (MOD_0F01_REG_3
) },
3619 { "smswD", { Sv
}, 0 },
3620 { MOD_TABLE (MOD_0F01_REG_5
) },
3621 { "lmsw", { Ew
}, 0 },
3622 { MOD_TABLE (MOD_0F01_REG_7
) },
3626 { "prefetch", { Mb
}, 0 },
3627 { "prefetchw", { Mb
}, 0 },
3628 { "prefetchwt1", { Mb
}, 0 },
3629 { "prefetch", { Mb
}, 0 },
3630 { "prefetch", { Mb
}, 0 },
3631 { "prefetch", { Mb
}, 0 },
3632 { "prefetch", { Mb
}, 0 },
3633 { "prefetch", { Mb
}, 0 },
3637 { MOD_TABLE (MOD_0F18_REG_0
) },
3638 { MOD_TABLE (MOD_0F18_REG_1
) },
3639 { MOD_TABLE (MOD_0F18_REG_2
) },
3640 { MOD_TABLE (MOD_0F18_REG_3
) },
3641 { MOD_TABLE (MOD_0F18_REG_4
) },
3642 { MOD_TABLE (MOD_0F18_REG_5
) },
3643 { MOD_TABLE (MOD_0F18_REG_6
) },
3644 { MOD_TABLE (MOD_0F18_REG_7
) },
3646 /* REG_0F1E_MOD_3 */
3648 { "nopQ", { Ev
}, 0 },
3649 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3650 { "nopQ", { Ev
}, 0 },
3651 { "nopQ", { Ev
}, 0 },
3652 { "nopQ", { Ev
}, 0 },
3653 { "nopQ", { Ev
}, 0 },
3654 { "nopQ", { Ev
}, 0 },
3655 { RM_TABLE (RM_0F1E_MOD_3_REG_7
) },
3661 { MOD_TABLE (MOD_0F71_REG_2
) },
3663 { MOD_TABLE (MOD_0F71_REG_4
) },
3665 { MOD_TABLE (MOD_0F71_REG_6
) },
3671 { MOD_TABLE (MOD_0F72_REG_2
) },
3673 { MOD_TABLE (MOD_0F72_REG_4
) },
3675 { MOD_TABLE (MOD_0F72_REG_6
) },
3681 { MOD_TABLE (MOD_0F73_REG_2
) },
3682 { MOD_TABLE (MOD_0F73_REG_3
) },
3685 { MOD_TABLE (MOD_0F73_REG_6
) },
3686 { MOD_TABLE (MOD_0F73_REG_7
) },
3690 { "montmul", { { OP_0f07
, 0 } }, 0 },
3691 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3692 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3696 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3697 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3698 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3699 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3700 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3701 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3705 { MOD_TABLE (MOD_0FAE_REG_0
) },
3706 { MOD_TABLE (MOD_0FAE_REG_1
) },
3707 { MOD_TABLE (MOD_0FAE_REG_2
) },
3708 { MOD_TABLE (MOD_0FAE_REG_3
) },
3709 { MOD_TABLE (MOD_0FAE_REG_4
) },
3710 { MOD_TABLE (MOD_0FAE_REG_5
) },
3711 { MOD_TABLE (MOD_0FAE_REG_6
) },
3712 { MOD_TABLE (MOD_0FAE_REG_7
) },
3720 { "btQ", { Ev
, Ib
}, 0 },
3721 { "btsQ", { Evh1
, Ib
}, 0 },
3722 { "btrQ", { Evh1
, Ib
}, 0 },
3723 { "btcQ", { Evh1
, Ib
}, 0 },
3728 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3730 { MOD_TABLE (MOD_0FC7_REG_3
) },
3731 { MOD_TABLE (MOD_0FC7_REG_4
) },
3732 { MOD_TABLE (MOD_0FC7_REG_5
) },
3733 { MOD_TABLE (MOD_0FC7_REG_6
) },
3734 { MOD_TABLE (MOD_0FC7_REG_7
) },
3740 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3742 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3744 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3750 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3752 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3754 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3760 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3761 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3764 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3765 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3771 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3772 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3774 /* REG_VEX_0F38F3 */
3777 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3778 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3779 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3783 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3784 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3788 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3789 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3791 /* REG_XOP_TBM_01 */
3794 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3795 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3796 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3797 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3798 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3799 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3800 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3802 /* REG_XOP_TBM_02 */
3805 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3810 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3812 #define NEED_REG_TABLE
3813 #include "i386-dis-evex.h"
3814 #undef NEED_REG_TABLE
3817 static const struct dis386 prefix_table
[][4] = {
3820 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3821 { "pause", { XX
}, 0 },
3822 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3823 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3826 /* PREFIX_MOD_0_0F01_REG_5 */
3829 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3832 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3835 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3838 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3841 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3846 { "wbinvd", { XX
}, 0 },
3847 { "wbnoinvd", { XX
}, 0 },
3852 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3853 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3854 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3855 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3860 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3861 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3862 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3863 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3868 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3869 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3870 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3871 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3876 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3877 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3878 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3883 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3884 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3885 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3886 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3891 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3892 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3893 { "bndmov", { Ebnd
, Gbnd
}, 0 },
3894 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3899 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3900 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3901 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3902 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3907 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3908 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3909 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3910 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3915 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3916 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3917 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3918 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3923 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3924 { "cvttss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3925 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3926 { "cvttsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3931 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3932 { "cvtss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3933 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3934 { "cvtsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3939 { "ucomiss",{ XM
, EXd
}, 0 },
3941 { "ucomisd",{ XM
, EXq
}, 0 },
3946 { "comiss", { XM
, EXd
}, 0 },
3948 { "comisd", { XM
, EXq
}, 0 },
3953 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3954 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3955 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3956 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3961 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3962 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3967 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3968 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3973 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3974 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3975 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3976 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3981 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3982 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3983 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3984 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3989 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3990 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3991 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3992 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3997 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3998 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3999 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4004 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
4005 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
4006 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
4007 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
4012 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
4013 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
4014 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
4015 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
4020 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
4021 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
4022 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
4023 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
4028 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
4029 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
4030 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
4031 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
4036 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
4038 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
4043 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
4045 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
4050 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
4052 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
4059 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
4066 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
4071 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
4072 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
4073 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
4078 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4079 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4080 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4081 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4084 /* PREFIX_0F73_REG_3 */
4088 { "psrldq", { XS
, Ib
}, 0 },
4091 /* PREFIX_0F73_REG_7 */
4095 { "pslldq", { XS
, Ib
}, 0 },
4100 {"vmread", { Em
, Gm
}, 0 },
4102 {"extrq", { XS
, Ib
, Ib
}, 0 },
4103 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
4108 {"vmwrite", { Gm
, Em
}, 0 },
4110 {"extrq", { XM
, XS
}, 0 },
4111 {"insertq", { XM
, XS
}, 0 },
4118 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
4119 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
4126 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
4127 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
4132 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
4133 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
4134 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
4139 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
4140 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
4141 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
4144 /* PREFIX_0FAE_REG_0 */
4147 { "rdfsbase", { Ev
}, 0 },
4150 /* PREFIX_0FAE_REG_1 */
4153 { "rdgsbase", { Ev
}, 0 },
4156 /* PREFIX_0FAE_REG_2 */
4159 { "wrfsbase", { Ev
}, 0 },
4162 /* PREFIX_0FAE_REG_3 */
4165 { "wrgsbase", { Ev
}, 0 },
4168 /* PREFIX_MOD_0_0FAE_REG_4 */
4170 { "xsave", { FXSAVE
}, 0 },
4171 { "ptwrite%LQ", { Edq
}, 0 },
4174 /* PREFIX_MOD_3_0FAE_REG_4 */
4177 { "ptwrite%LQ", { Edq
}, 0 },
4180 /* PREFIX_MOD_0_0FAE_REG_5 */
4182 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4185 /* PREFIX_MOD_3_0FAE_REG_5 */
4187 { "lfence", { Skip_MODRM
}, 0 },
4188 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4191 /* PREFIX_0FAE_REG_6 */
4193 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4194 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4195 { "clwb", { Mb
}, PREFIX_OPCODE
},
4198 /* PREFIX_0FAE_REG_7 */
4200 { "clflush", { Mb
}, 0 },
4202 { "clflushopt", { Mb
}, 0 },
4208 { "popcntS", { Gv
, Ev
}, 0 },
4213 { "bsfS", { Gv
, Ev
}, 0 },
4214 { "tzcntS", { Gv
, Ev
}, 0 },
4215 { "bsfS", { Gv
, Ev
}, 0 },
4220 { "bsrS", { Gv
, Ev
}, 0 },
4221 { "lzcntS", { Gv
, Ev
}, 0 },
4222 { "bsrS", { Gv
, Ev
}, 0 },
4227 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4228 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4229 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4230 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4233 /* PREFIX_MOD_0_0FC3 */
4235 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4238 /* PREFIX_MOD_0_0FC7_REG_6 */
4240 { "vmptrld",{ Mq
}, 0 },
4241 { "vmxon", { Mq
}, 0 },
4242 { "vmclear",{ Mq
}, 0 },
4245 /* PREFIX_MOD_3_0FC7_REG_6 */
4247 { "rdrand", { Ev
}, 0 },
4249 { "rdrand", { Ev
}, 0 }
4252 /* PREFIX_MOD_3_0FC7_REG_7 */
4254 { "rdseed", { Ev
}, 0 },
4255 { "rdpid", { Em
}, 0 },
4256 { "rdseed", { Ev
}, 0 },
4263 { "addsubpd", { XM
, EXx
}, 0 },
4264 { "addsubps", { XM
, EXx
}, 0 },
4270 { "movq2dq",{ XM
, MS
}, 0 },
4271 { "movq", { EXqS
, XM
}, 0 },
4272 { "movdq2q",{ MX
, XS
}, 0 },
4278 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4279 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4280 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4285 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4287 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4295 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4300 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4302 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4309 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4316 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4323 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4330 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4337 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4344 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4351 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4358 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4365 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4372 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4379 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4386 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4393 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4400 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4407 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4414 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4421 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4428 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4435 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4442 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4449 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4456 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4463 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4470 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4477 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4484 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4491 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4498 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4505 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4512 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4519 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4526 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4533 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4540 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4545 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4550 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4555 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4560 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4565 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4570 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4577 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4584 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4591 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4598 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4605 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4612 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4617 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4619 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4620 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4625 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4627 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4628 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4635 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4640 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4641 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4642 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4650 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4657 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4664 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4671 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4678 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4685 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4692 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4699 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4706 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4713 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4720 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4727 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4734 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4741 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4748 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4755 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4762 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4769 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4776 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4783 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4790 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4797 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4802 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4809 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4816 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4823 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4826 /* PREFIX_VEX_0F10 */
4828 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4829 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4830 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4831 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4834 /* PREFIX_VEX_0F11 */
4836 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4837 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4838 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4839 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4842 /* PREFIX_VEX_0F12 */
4844 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4845 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4846 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4847 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4850 /* PREFIX_VEX_0F16 */
4852 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4853 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4854 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4857 /* PREFIX_VEX_0F2A */
4860 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4862 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4865 /* PREFIX_VEX_0F2C */
4868 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4870 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4873 /* PREFIX_VEX_0F2D */
4876 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4878 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4881 /* PREFIX_VEX_0F2E */
4883 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4885 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4888 /* PREFIX_VEX_0F2F */
4890 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4892 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4895 /* PREFIX_VEX_0F41 */
4897 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4899 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4902 /* PREFIX_VEX_0F42 */
4904 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4906 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4909 /* PREFIX_VEX_0F44 */
4911 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4913 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4916 /* PREFIX_VEX_0F45 */
4918 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4920 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4923 /* PREFIX_VEX_0F46 */
4925 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4927 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4930 /* PREFIX_VEX_0F47 */
4932 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4934 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4937 /* PREFIX_VEX_0F4A */
4939 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4941 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4944 /* PREFIX_VEX_0F4B */
4946 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4948 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4951 /* PREFIX_VEX_0F51 */
4953 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4954 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4955 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4956 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4959 /* PREFIX_VEX_0F52 */
4961 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4962 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4965 /* PREFIX_VEX_0F53 */
4967 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4968 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4971 /* PREFIX_VEX_0F58 */
4973 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4974 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4975 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4976 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4979 /* PREFIX_VEX_0F59 */
4981 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4982 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4983 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4984 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4987 /* PREFIX_VEX_0F5A */
4989 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4990 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4991 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
4992 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4995 /* PREFIX_VEX_0F5B */
4997 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4998 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4999 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
5002 /* PREFIX_VEX_0F5C */
5004 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
5005 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
5006 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
5007 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
5010 /* PREFIX_VEX_0F5D */
5012 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
5013 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
5014 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
5015 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
5018 /* PREFIX_VEX_0F5E */
5020 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
5021 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
5022 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
5023 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
5026 /* PREFIX_VEX_0F5F */
5028 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
5029 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
5030 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
5031 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
5034 /* PREFIX_VEX_0F60 */
5038 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
5041 /* PREFIX_VEX_0F61 */
5045 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
5048 /* PREFIX_VEX_0F62 */
5052 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
5055 /* PREFIX_VEX_0F63 */
5059 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
5062 /* PREFIX_VEX_0F64 */
5066 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
5069 /* PREFIX_VEX_0F65 */
5073 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
5076 /* PREFIX_VEX_0F66 */
5080 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
5083 /* PREFIX_VEX_0F67 */
5087 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
5090 /* PREFIX_VEX_0F68 */
5094 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
5097 /* PREFIX_VEX_0F69 */
5101 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
5104 /* PREFIX_VEX_0F6A */
5108 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
5111 /* PREFIX_VEX_0F6B */
5115 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
5118 /* PREFIX_VEX_0F6C */
5122 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
5125 /* PREFIX_VEX_0F6D */
5129 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
5132 /* PREFIX_VEX_0F6E */
5136 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
5139 /* PREFIX_VEX_0F6F */
5142 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
5143 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
5146 /* PREFIX_VEX_0F70 */
5149 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
5150 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
5151 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
5154 /* PREFIX_VEX_0F71_REG_2 */
5158 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
5161 /* PREFIX_VEX_0F71_REG_4 */
5165 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
5168 /* PREFIX_VEX_0F71_REG_6 */
5172 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
5175 /* PREFIX_VEX_0F72_REG_2 */
5179 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
5182 /* PREFIX_VEX_0F72_REG_4 */
5186 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
5189 /* PREFIX_VEX_0F72_REG_6 */
5193 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
5196 /* PREFIX_VEX_0F73_REG_2 */
5200 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
5203 /* PREFIX_VEX_0F73_REG_3 */
5207 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
5210 /* PREFIX_VEX_0F73_REG_6 */
5214 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
5217 /* PREFIX_VEX_0F73_REG_7 */
5221 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
5224 /* PREFIX_VEX_0F74 */
5228 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
5231 /* PREFIX_VEX_0F75 */
5235 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5238 /* PREFIX_VEX_0F76 */
5242 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5245 /* PREFIX_VEX_0F77 */
5247 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5250 /* PREFIX_VEX_0F7C */
5254 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5255 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5258 /* PREFIX_VEX_0F7D */
5262 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5263 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5266 /* PREFIX_VEX_0F7E */
5269 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5270 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5273 /* PREFIX_VEX_0F7F */
5276 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5277 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5280 /* PREFIX_VEX_0F90 */
5282 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5284 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5287 /* PREFIX_VEX_0F91 */
5289 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5291 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5294 /* PREFIX_VEX_0F92 */
5296 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5298 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5299 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5302 /* PREFIX_VEX_0F93 */
5304 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5306 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5307 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5310 /* PREFIX_VEX_0F98 */
5312 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5314 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5317 /* PREFIX_VEX_0F99 */
5319 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5321 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5324 /* PREFIX_VEX_0FC2 */
5326 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5327 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5328 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5329 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5332 /* PREFIX_VEX_0FC4 */
5336 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5339 /* PREFIX_VEX_0FC5 */
5343 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5346 /* PREFIX_VEX_0FD0 */
5350 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5351 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5354 /* PREFIX_VEX_0FD1 */
5358 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5361 /* PREFIX_VEX_0FD2 */
5365 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5368 /* PREFIX_VEX_0FD3 */
5372 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5375 /* PREFIX_VEX_0FD4 */
5379 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5382 /* PREFIX_VEX_0FD5 */
5386 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5389 /* PREFIX_VEX_0FD6 */
5393 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5396 /* PREFIX_VEX_0FD7 */
5400 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5403 /* PREFIX_VEX_0FD8 */
5407 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5410 /* PREFIX_VEX_0FD9 */
5414 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5417 /* PREFIX_VEX_0FDA */
5421 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5424 /* PREFIX_VEX_0FDB */
5428 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5431 /* PREFIX_VEX_0FDC */
5435 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5438 /* PREFIX_VEX_0FDD */
5442 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5445 /* PREFIX_VEX_0FDE */
5449 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5452 /* PREFIX_VEX_0FDF */
5456 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5459 /* PREFIX_VEX_0FE0 */
5463 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5466 /* PREFIX_VEX_0FE1 */
5470 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5473 /* PREFIX_VEX_0FE2 */
5477 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5480 /* PREFIX_VEX_0FE3 */
5484 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5487 /* PREFIX_VEX_0FE4 */
5491 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5494 /* PREFIX_VEX_0FE5 */
5498 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5501 /* PREFIX_VEX_0FE6 */
5504 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5505 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5506 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5509 /* PREFIX_VEX_0FE7 */
5513 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5516 /* PREFIX_VEX_0FE8 */
5520 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5523 /* PREFIX_VEX_0FE9 */
5527 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5530 /* PREFIX_VEX_0FEA */
5534 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5537 /* PREFIX_VEX_0FEB */
5541 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5544 /* PREFIX_VEX_0FEC */
5548 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5551 /* PREFIX_VEX_0FED */
5555 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5558 /* PREFIX_VEX_0FEE */
5562 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5565 /* PREFIX_VEX_0FEF */
5569 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5572 /* PREFIX_VEX_0FF0 */
5577 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5580 /* PREFIX_VEX_0FF1 */
5584 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5587 /* PREFIX_VEX_0FF2 */
5591 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5594 /* PREFIX_VEX_0FF3 */
5598 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5601 /* PREFIX_VEX_0FF4 */
5605 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5608 /* PREFIX_VEX_0FF5 */
5612 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5615 /* PREFIX_VEX_0FF6 */
5619 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5622 /* PREFIX_VEX_0FF7 */
5626 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5629 /* PREFIX_VEX_0FF8 */
5633 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5636 /* PREFIX_VEX_0FF9 */
5640 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5643 /* PREFIX_VEX_0FFA */
5647 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5650 /* PREFIX_VEX_0FFB */
5654 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5657 /* PREFIX_VEX_0FFC */
5661 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5664 /* PREFIX_VEX_0FFD */
5668 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5671 /* PREFIX_VEX_0FFE */
5675 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5678 /* PREFIX_VEX_0F3800 */
5682 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5685 /* PREFIX_VEX_0F3801 */
5689 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5692 /* PREFIX_VEX_0F3802 */
5696 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5699 /* PREFIX_VEX_0F3803 */
5703 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5706 /* PREFIX_VEX_0F3804 */
5710 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5713 /* PREFIX_VEX_0F3805 */
5717 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5720 /* PREFIX_VEX_0F3806 */
5724 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5727 /* PREFIX_VEX_0F3807 */
5731 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5734 /* PREFIX_VEX_0F3808 */
5738 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5741 /* PREFIX_VEX_0F3809 */
5745 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5748 /* PREFIX_VEX_0F380A */
5752 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5755 /* PREFIX_VEX_0F380B */
5759 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5762 /* PREFIX_VEX_0F380C */
5766 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5769 /* PREFIX_VEX_0F380D */
5773 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5776 /* PREFIX_VEX_0F380E */
5780 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5783 /* PREFIX_VEX_0F380F */
5787 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5790 /* PREFIX_VEX_0F3813 */
5794 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5797 /* PREFIX_VEX_0F3816 */
5801 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5804 /* PREFIX_VEX_0F3817 */
5808 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5811 /* PREFIX_VEX_0F3818 */
5815 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5818 /* PREFIX_VEX_0F3819 */
5822 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5825 /* PREFIX_VEX_0F381A */
5829 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5832 /* PREFIX_VEX_0F381C */
5836 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5839 /* PREFIX_VEX_0F381D */
5843 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5846 /* PREFIX_VEX_0F381E */
5850 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5853 /* PREFIX_VEX_0F3820 */
5857 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5860 /* PREFIX_VEX_0F3821 */
5864 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5867 /* PREFIX_VEX_0F3822 */
5871 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5874 /* PREFIX_VEX_0F3823 */
5878 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5881 /* PREFIX_VEX_0F3824 */
5885 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5888 /* PREFIX_VEX_0F3825 */
5892 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5895 /* PREFIX_VEX_0F3828 */
5899 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5902 /* PREFIX_VEX_0F3829 */
5906 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5909 /* PREFIX_VEX_0F382A */
5913 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5916 /* PREFIX_VEX_0F382B */
5920 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5923 /* PREFIX_VEX_0F382C */
5927 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5930 /* PREFIX_VEX_0F382D */
5934 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5937 /* PREFIX_VEX_0F382E */
5941 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5944 /* PREFIX_VEX_0F382F */
5948 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5951 /* PREFIX_VEX_0F3830 */
5955 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5958 /* PREFIX_VEX_0F3831 */
5962 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5965 /* PREFIX_VEX_0F3832 */
5969 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5972 /* PREFIX_VEX_0F3833 */
5976 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5979 /* PREFIX_VEX_0F3834 */
5983 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5986 /* PREFIX_VEX_0F3835 */
5990 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5993 /* PREFIX_VEX_0F3836 */
5997 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
6000 /* PREFIX_VEX_0F3837 */
6004 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
6007 /* PREFIX_VEX_0F3838 */
6011 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
6014 /* PREFIX_VEX_0F3839 */
6018 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
6021 /* PREFIX_VEX_0F383A */
6025 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
6028 /* PREFIX_VEX_0F383B */
6032 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
6035 /* PREFIX_VEX_0F383C */
6039 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
6042 /* PREFIX_VEX_0F383D */
6046 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
6049 /* PREFIX_VEX_0F383E */
6053 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
6056 /* PREFIX_VEX_0F383F */
6060 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
6063 /* PREFIX_VEX_0F3840 */
6067 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
6070 /* PREFIX_VEX_0F3841 */
6074 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
6077 /* PREFIX_VEX_0F3845 */
6081 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
6084 /* PREFIX_VEX_0F3846 */
6088 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
6091 /* PREFIX_VEX_0F3847 */
6095 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
6098 /* PREFIX_VEX_0F3858 */
6102 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
6105 /* PREFIX_VEX_0F3859 */
6109 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
6112 /* PREFIX_VEX_0F385A */
6116 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
6119 /* PREFIX_VEX_0F3878 */
6123 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
6126 /* PREFIX_VEX_0F3879 */
6130 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
6133 /* PREFIX_VEX_0F388C */
6137 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
6140 /* PREFIX_VEX_0F388E */
6144 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
6147 /* PREFIX_VEX_0F3890 */
6151 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6154 /* PREFIX_VEX_0F3891 */
6158 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6161 /* PREFIX_VEX_0F3892 */
6165 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6168 /* PREFIX_VEX_0F3893 */
6172 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6175 /* PREFIX_VEX_0F3896 */
6179 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6182 /* PREFIX_VEX_0F3897 */
6186 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6189 /* PREFIX_VEX_0F3898 */
6193 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6196 /* PREFIX_VEX_0F3899 */
6200 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6203 /* PREFIX_VEX_0F389A */
6207 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6210 /* PREFIX_VEX_0F389B */
6214 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6217 /* PREFIX_VEX_0F389C */
6221 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6224 /* PREFIX_VEX_0F389D */
6228 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6231 /* PREFIX_VEX_0F389E */
6235 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6238 /* PREFIX_VEX_0F389F */
6242 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6245 /* PREFIX_VEX_0F38A6 */
6249 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6253 /* PREFIX_VEX_0F38A7 */
6257 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6260 /* PREFIX_VEX_0F38A8 */
6264 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6267 /* PREFIX_VEX_0F38A9 */
6271 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6274 /* PREFIX_VEX_0F38AA */
6278 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6281 /* PREFIX_VEX_0F38AB */
6285 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6288 /* PREFIX_VEX_0F38AC */
6292 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6295 /* PREFIX_VEX_0F38AD */
6299 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6302 /* PREFIX_VEX_0F38AE */
6306 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6309 /* PREFIX_VEX_0F38AF */
6313 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6316 /* PREFIX_VEX_0F38B6 */
6320 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6323 /* PREFIX_VEX_0F38B7 */
6327 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6330 /* PREFIX_VEX_0F38B8 */
6334 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6337 /* PREFIX_VEX_0F38B9 */
6341 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6344 /* PREFIX_VEX_0F38BA */
6348 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6351 /* PREFIX_VEX_0F38BB */
6355 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6358 /* PREFIX_VEX_0F38BC */
6362 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6365 /* PREFIX_VEX_0F38BD */
6369 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6372 /* PREFIX_VEX_0F38BE */
6376 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6379 /* PREFIX_VEX_0F38BF */
6383 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6386 /* PREFIX_VEX_0F38CF */
6390 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6393 /* PREFIX_VEX_0F38DB */
6397 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6400 /* PREFIX_VEX_0F38DC */
6404 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6407 /* PREFIX_VEX_0F38DD */
6411 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6414 /* PREFIX_VEX_0F38DE */
6418 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6421 /* PREFIX_VEX_0F38DF */
6425 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6428 /* PREFIX_VEX_0F38F2 */
6430 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6433 /* PREFIX_VEX_0F38F3_REG_1 */
6435 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6438 /* PREFIX_VEX_0F38F3_REG_2 */
6440 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6443 /* PREFIX_VEX_0F38F3_REG_3 */
6445 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6448 /* PREFIX_VEX_0F38F5 */
6450 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6451 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6453 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6456 /* PREFIX_VEX_0F38F6 */
6461 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6464 /* PREFIX_VEX_0F38F7 */
6466 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6467 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6468 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6469 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6472 /* PREFIX_VEX_0F3A00 */
6476 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6479 /* PREFIX_VEX_0F3A01 */
6483 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6486 /* PREFIX_VEX_0F3A02 */
6490 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6493 /* PREFIX_VEX_0F3A04 */
6497 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6500 /* PREFIX_VEX_0F3A05 */
6504 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6507 /* PREFIX_VEX_0F3A06 */
6511 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6514 /* PREFIX_VEX_0F3A08 */
6518 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6521 /* PREFIX_VEX_0F3A09 */
6525 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6528 /* PREFIX_VEX_0F3A0A */
6532 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6535 /* PREFIX_VEX_0F3A0B */
6539 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6542 /* PREFIX_VEX_0F3A0C */
6546 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6549 /* PREFIX_VEX_0F3A0D */
6553 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6556 /* PREFIX_VEX_0F3A0E */
6560 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6563 /* PREFIX_VEX_0F3A0F */
6567 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6570 /* PREFIX_VEX_0F3A14 */
6574 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6577 /* PREFIX_VEX_0F3A15 */
6581 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6584 /* PREFIX_VEX_0F3A16 */
6588 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6591 /* PREFIX_VEX_0F3A17 */
6595 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6598 /* PREFIX_VEX_0F3A18 */
6602 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6605 /* PREFIX_VEX_0F3A19 */
6609 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6612 /* PREFIX_VEX_0F3A1D */
6616 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6619 /* PREFIX_VEX_0F3A20 */
6623 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6626 /* PREFIX_VEX_0F3A21 */
6630 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6633 /* PREFIX_VEX_0F3A22 */
6637 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6640 /* PREFIX_VEX_0F3A30 */
6644 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6647 /* PREFIX_VEX_0F3A31 */
6651 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6654 /* PREFIX_VEX_0F3A32 */
6658 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6661 /* PREFIX_VEX_0F3A33 */
6665 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6668 /* PREFIX_VEX_0F3A38 */
6672 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6675 /* PREFIX_VEX_0F3A39 */
6679 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6682 /* PREFIX_VEX_0F3A40 */
6686 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6689 /* PREFIX_VEX_0F3A41 */
6693 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6696 /* PREFIX_VEX_0F3A42 */
6700 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6703 /* PREFIX_VEX_0F3A44 */
6707 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6710 /* PREFIX_VEX_0F3A46 */
6714 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6717 /* PREFIX_VEX_0F3A48 */
6721 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6724 /* PREFIX_VEX_0F3A49 */
6728 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6731 /* PREFIX_VEX_0F3A4A */
6735 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6738 /* PREFIX_VEX_0F3A4B */
6742 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6745 /* PREFIX_VEX_0F3A4C */
6749 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6752 /* PREFIX_VEX_0F3A5C */
6756 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6759 /* PREFIX_VEX_0F3A5D */
6763 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6766 /* PREFIX_VEX_0F3A5E */
6770 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6773 /* PREFIX_VEX_0F3A5F */
6777 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6780 /* PREFIX_VEX_0F3A60 */
6784 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6788 /* PREFIX_VEX_0F3A61 */
6792 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6795 /* PREFIX_VEX_0F3A62 */
6799 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6802 /* PREFIX_VEX_0F3A63 */
6806 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6809 /* PREFIX_VEX_0F3A68 */
6813 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6816 /* PREFIX_VEX_0F3A69 */
6820 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6823 /* PREFIX_VEX_0F3A6A */
6827 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6830 /* PREFIX_VEX_0F3A6B */
6834 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6837 /* PREFIX_VEX_0F3A6C */
6841 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6844 /* PREFIX_VEX_0F3A6D */
6848 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6851 /* PREFIX_VEX_0F3A6E */
6855 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6858 /* PREFIX_VEX_0F3A6F */
6862 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6865 /* PREFIX_VEX_0F3A78 */
6869 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6872 /* PREFIX_VEX_0F3A79 */
6876 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6879 /* PREFIX_VEX_0F3A7A */
6883 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6886 /* PREFIX_VEX_0F3A7B */
6890 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6893 /* PREFIX_VEX_0F3A7C */
6897 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6901 /* PREFIX_VEX_0F3A7D */
6905 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6908 /* PREFIX_VEX_0F3A7E */
6912 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6915 /* PREFIX_VEX_0F3A7F */
6919 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6922 /* PREFIX_VEX_0F3ACE */
6926 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6929 /* PREFIX_VEX_0F3ACF */
6933 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6936 /* PREFIX_VEX_0F3ADF */
6940 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6943 /* PREFIX_VEX_0F3AF0 */
6948 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6951 #define NEED_PREFIX_TABLE
6952 #include "i386-dis-evex.h"
6953 #undef NEED_PREFIX_TABLE
6956 static const struct dis386 x86_64_table
[][2] = {
6959 { "pushP", { es
}, 0 },
6964 { "popP", { es
}, 0 },
6969 { "pushP", { cs
}, 0 },
6974 { "pushP", { ss
}, 0 },
6979 { "popP", { ss
}, 0 },
6984 { "pushP", { ds
}, 0 },
6989 { "popP", { ds
}, 0 },
6994 { "daa", { XX
}, 0 },
6999 { "das", { XX
}, 0 },
7004 { "aaa", { XX
}, 0 },
7009 { "aas", { XX
}, 0 },
7014 { "pushaP", { XX
}, 0 },
7019 { "popaP", { XX
}, 0 },
7024 { MOD_TABLE (MOD_62_32BIT
) },
7025 { EVEX_TABLE (EVEX_0F
) },
7030 { "arpl", { Ew
, Gw
}, 0 },
7031 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
7036 { "ins{R|}", { Yzr
, indirDX
}, 0 },
7037 { "ins{G|}", { Yzr
, indirDX
}, 0 },
7042 { "outs{R|}", { indirDXr
, Xz
}, 0 },
7043 { "outs{G|}", { indirDXr
, Xz
}, 0 },
7048 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
7049 { REG_TABLE (REG_80
) },
7054 { "Jcall{T|}", { Ap
}, 0 },
7059 { MOD_TABLE (MOD_C4_32BIT
) },
7060 { VEX_C4_TABLE (VEX_0F
) },
7065 { MOD_TABLE (MOD_C5_32BIT
) },
7066 { VEX_C5_TABLE (VEX_0F
) },
7071 { "into", { XX
}, 0 },
7076 { "aam", { Ib
}, 0 },
7081 { "aad", { Ib
}, 0 },
7086 { "callP", { Jv
, BND
}, 0 },
7087 { "call@", { Jv
, BND
}, 0 }
7092 { "jmpP", { Jv
, BND
}, 0 },
7093 { "jmp@", { Jv
, BND
}, 0 }
7098 { "Jjmp{T|}", { Ap
}, 0 },
7101 /* X86_64_0F01_REG_0 */
7103 { "sgdt{Q|IQ}", { M
}, 0 },
7104 { "sgdt", { M
}, 0 },
7107 /* X86_64_0F01_REG_1 */
7109 { "sidt{Q|IQ}", { M
}, 0 },
7110 { "sidt", { M
}, 0 },
7113 /* X86_64_0F01_REG_2 */
7115 { "lgdt{Q|Q}", { M
}, 0 },
7116 { "lgdt", { M
}, 0 },
7119 /* X86_64_0F01_REG_3 */
7121 { "lidt{Q|Q}", { M
}, 0 },
7122 { "lidt", { M
}, 0 },
7126 static const struct dis386 three_byte_table
[][256] = {
7128 /* THREE_BYTE_0F38 */
7131 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
7132 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
7133 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
7134 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
7135 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
7136 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
7137 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
7138 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
7140 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
7141 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
7142 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
7143 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
7149 { PREFIX_TABLE (PREFIX_0F3810
) },
7153 { PREFIX_TABLE (PREFIX_0F3814
) },
7154 { PREFIX_TABLE (PREFIX_0F3815
) },
7156 { PREFIX_TABLE (PREFIX_0F3817
) },
7162 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7163 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7164 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7167 { PREFIX_TABLE (PREFIX_0F3820
) },
7168 { PREFIX_TABLE (PREFIX_0F3821
) },
7169 { PREFIX_TABLE (PREFIX_0F3822
) },
7170 { PREFIX_TABLE (PREFIX_0F3823
) },
7171 { PREFIX_TABLE (PREFIX_0F3824
) },
7172 { PREFIX_TABLE (PREFIX_0F3825
) },
7176 { PREFIX_TABLE (PREFIX_0F3828
) },
7177 { PREFIX_TABLE (PREFIX_0F3829
) },
7178 { PREFIX_TABLE (PREFIX_0F382A
) },
7179 { PREFIX_TABLE (PREFIX_0F382B
) },
7185 { PREFIX_TABLE (PREFIX_0F3830
) },
7186 { PREFIX_TABLE (PREFIX_0F3831
) },
7187 { PREFIX_TABLE (PREFIX_0F3832
) },
7188 { PREFIX_TABLE (PREFIX_0F3833
) },
7189 { PREFIX_TABLE (PREFIX_0F3834
) },
7190 { PREFIX_TABLE (PREFIX_0F3835
) },
7192 { PREFIX_TABLE (PREFIX_0F3837
) },
7194 { PREFIX_TABLE (PREFIX_0F3838
) },
7195 { PREFIX_TABLE (PREFIX_0F3839
) },
7196 { PREFIX_TABLE (PREFIX_0F383A
) },
7197 { PREFIX_TABLE (PREFIX_0F383B
) },
7198 { PREFIX_TABLE (PREFIX_0F383C
) },
7199 { PREFIX_TABLE (PREFIX_0F383D
) },
7200 { PREFIX_TABLE (PREFIX_0F383E
) },
7201 { PREFIX_TABLE (PREFIX_0F383F
) },
7203 { PREFIX_TABLE (PREFIX_0F3840
) },
7204 { PREFIX_TABLE (PREFIX_0F3841
) },
7275 { PREFIX_TABLE (PREFIX_0F3880
) },
7276 { PREFIX_TABLE (PREFIX_0F3881
) },
7277 { PREFIX_TABLE (PREFIX_0F3882
) },
7356 { PREFIX_TABLE (PREFIX_0F38C8
) },
7357 { PREFIX_TABLE (PREFIX_0F38C9
) },
7358 { PREFIX_TABLE (PREFIX_0F38CA
) },
7359 { PREFIX_TABLE (PREFIX_0F38CB
) },
7360 { PREFIX_TABLE (PREFIX_0F38CC
) },
7361 { PREFIX_TABLE (PREFIX_0F38CD
) },
7363 { PREFIX_TABLE (PREFIX_0F38CF
) },
7377 { PREFIX_TABLE (PREFIX_0F38DB
) },
7378 { PREFIX_TABLE (PREFIX_0F38DC
) },
7379 { PREFIX_TABLE (PREFIX_0F38DD
) },
7380 { PREFIX_TABLE (PREFIX_0F38DE
) },
7381 { PREFIX_TABLE (PREFIX_0F38DF
) },
7401 { PREFIX_TABLE (PREFIX_0F38F0
) },
7402 { PREFIX_TABLE (PREFIX_0F38F1
) },
7406 { PREFIX_TABLE (PREFIX_0F38F5
) },
7407 { PREFIX_TABLE (PREFIX_0F38F6
) },
7419 /* THREE_BYTE_0F3A */
7431 { PREFIX_TABLE (PREFIX_0F3A08
) },
7432 { PREFIX_TABLE (PREFIX_0F3A09
) },
7433 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7434 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7435 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7436 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7437 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7438 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7444 { PREFIX_TABLE (PREFIX_0F3A14
) },
7445 { PREFIX_TABLE (PREFIX_0F3A15
) },
7446 { PREFIX_TABLE (PREFIX_0F3A16
) },
7447 { PREFIX_TABLE (PREFIX_0F3A17
) },
7458 { PREFIX_TABLE (PREFIX_0F3A20
) },
7459 { PREFIX_TABLE (PREFIX_0F3A21
) },
7460 { PREFIX_TABLE (PREFIX_0F3A22
) },
7494 { PREFIX_TABLE (PREFIX_0F3A40
) },
7495 { PREFIX_TABLE (PREFIX_0F3A41
) },
7496 { PREFIX_TABLE (PREFIX_0F3A42
) },
7498 { PREFIX_TABLE (PREFIX_0F3A44
) },
7530 { PREFIX_TABLE (PREFIX_0F3A60
) },
7531 { PREFIX_TABLE (PREFIX_0F3A61
) },
7532 { PREFIX_TABLE (PREFIX_0F3A62
) },
7533 { PREFIX_TABLE (PREFIX_0F3A63
) },
7651 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7653 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7654 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7672 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7712 static const struct dis386 xop_table
[][256] = {
7865 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7866 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7867 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7875 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7876 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7883 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7884 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7885 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7893 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7894 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7898 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7899 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7902 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7920 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7932 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7933 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7934 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7935 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7945 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7946 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7947 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7948 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7981 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7982 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7983 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7984 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8008 { REG_TABLE (REG_XOP_TBM_01
) },
8009 { REG_TABLE (REG_XOP_TBM_02
) },
8027 { REG_TABLE (REG_XOP_LWPCB
) },
8151 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8152 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8153 { "vfrczss", { XM
, EXd
}, 0 },
8154 { "vfrczsd", { XM
, EXq
}, 0 },
8169 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8170 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8171 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8172 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8173 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8174 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8175 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8176 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8178 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8179 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8180 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8181 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8224 { "vphaddbw", { XM
, EXxmm
}, 0 },
8225 { "vphaddbd", { XM
, EXxmm
}, 0 },
8226 { "vphaddbq", { XM
, EXxmm
}, 0 },
8229 { "vphaddwd", { XM
, EXxmm
}, 0 },
8230 { "vphaddwq", { XM
, EXxmm
}, 0 },
8235 { "vphadddq", { XM
, EXxmm
}, 0 },
8242 { "vphaddubw", { XM
, EXxmm
}, 0 },
8243 { "vphaddubd", { XM
, EXxmm
}, 0 },
8244 { "vphaddubq", { XM
, EXxmm
}, 0 },
8247 { "vphadduwd", { XM
, EXxmm
}, 0 },
8248 { "vphadduwq", { XM
, EXxmm
}, 0 },
8253 { "vphaddudq", { XM
, EXxmm
}, 0 },
8260 { "vphsubbw", { XM
, EXxmm
}, 0 },
8261 { "vphsubwd", { XM
, EXxmm
}, 0 },
8262 { "vphsubdq", { XM
, EXxmm
}, 0 },
8316 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8318 { REG_TABLE (REG_XOP_LWP
) },
8588 static const struct dis386 vex_table
[][256] = {
8610 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8611 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8612 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8613 { MOD_TABLE (MOD_VEX_0F13
) },
8614 { VEX_W_TABLE (VEX_W_0F14
) },
8615 { VEX_W_TABLE (VEX_W_0F15
) },
8616 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8617 { MOD_TABLE (MOD_VEX_0F17
) },
8637 { VEX_W_TABLE (VEX_W_0F28
) },
8638 { VEX_W_TABLE (VEX_W_0F29
) },
8639 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8640 { MOD_TABLE (MOD_VEX_0F2B
) },
8641 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8644 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8682 { MOD_TABLE (MOD_VEX_0F50
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8686 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8687 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8688 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8689 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8691 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8719 { REG_TABLE (REG_VEX_0F71
) },
8720 { REG_TABLE (REG_VEX_0F72
) },
8721 { REG_TABLE (REG_VEX_0F73
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8787 { REG_TABLE (REG_VEX_0FAE
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8813 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8814 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8826 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8827 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8832 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8833 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8835 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8836 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8837 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8838 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8840 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8841 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8842 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8844 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8845 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8849 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8851 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8854 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8855 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8856 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8863 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8872 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8874 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8875 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8876 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8877 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9156 { REG_TABLE (REG_VEX_0F38F3
) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9160 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9179 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9180 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9185 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9197 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9198 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9199 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9201 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9206 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9210 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9211 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9212 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9228 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9229 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9230 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9231 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9237 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9238 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9247 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9248 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9250 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9252 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9255 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9256 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9257 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9258 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9259 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9277 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9278 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9279 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9280 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9282 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9283 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9284 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9291 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9292 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9293 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9294 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9295 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9296 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9297 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9298 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9309 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9405 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9406 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9424 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9444 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9464 #define NEED_OPCODE_TABLE
9465 #include "i386-dis-evex.h"
9466 #undef NEED_OPCODE_TABLE
9467 static const struct dis386 vex_len_table
[][2] = {
9468 /* VEX_LEN_0F10_P_1 */
9470 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9471 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9474 /* VEX_LEN_0F10_P_3 */
9476 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9477 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9480 /* VEX_LEN_0F11_P_1 */
9482 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9483 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9486 /* VEX_LEN_0F11_P_3 */
9488 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9489 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9492 /* VEX_LEN_0F12_P_0_M_0 */
9494 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9497 /* VEX_LEN_0F12_P_0_M_1 */
9499 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9502 /* VEX_LEN_0F12_P_2 */
9504 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9507 /* VEX_LEN_0F13_M_0 */
9509 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9512 /* VEX_LEN_0F16_P_0_M_0 */
9514 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9517 /* VEX_LEN_0F16_P_0_M_1 */
9519 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9522 /* VEX_LEN_0F16_P_2 */
9524 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9527 /* VEX_LEN_0F17_M_0 */
9529 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9532 /* VEX_LEN_0F2A_P_1 */
9534 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9535 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9538 /* VEX_LEN_0F2A_P_3 */
9540 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9541 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9544 /* VEX_LEN_0F2C_P_1 */
9546 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9547 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9550 /* VEX_LEN_0F2C_P_3 */
9552 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9553 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9556 /* VEX_LEN_0F2D_P_1 */
9558 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9559 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9562 /* VEX_LEN_0F2D_P_3 */
9564 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9565 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9568 /* VEX_LEN_0F2E_P_0 */
9570 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9571 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9574 /* VEX_LEN_0F2E_P_2 */
9576 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9577 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9580 /* VEX_LEN_0F2F_P_0 */
9582 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9583 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9586 /* VEX_LEN_0F2F_P_2 */
9588 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9589 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9592 /* VEX_LEN_0F41_P_0 */
9595 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9597 /* VEX_LEN_0F41_P_2 */
9600 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9602 /* VEX_LEN_0F42_P_0 */
9605 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9607 /* VEX_LEN_0F42_P_2 */
9610 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9612 /* VEX_LEN_0F44_P_0 */
9614 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9616 /* VEX_LEN_0F44_P_2 */
9618 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9620 /* VEX_LEN_0F45_P_0 */
9623 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9625 /* VEX_LEN_0F45_P_2 */
9628 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9630 /* VEX_LEN_0F46_P_0 */
9633 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9635 /* VEX_LEN_0F46_P_2 */
9638 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9640 /* VEX_LEN_0F47_P_0 */
9643 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9645 /* VEX_LEN_0F47_P_2 */
9648 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9650 /* VEX_LEN_0F4A_P_0 */
9653 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9655 /* VEX_LEN_0F4A_P_2 */
9658 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9660 /* VEX_LEN_0F4B_P_0 */
9663 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9665 /* VEX_LEN_0F4B_P_2 */
9668 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9671 /* VEX_LEN_0F51_P_1 */
9673 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9674 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9677 /* VEX_LEN_0F51_P_3 */
9679 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9680 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9683 /* VEX_LEN_0F52_P_1 */
9685 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9686 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9689 /* VEX_LEN_0F53_P_1 */
9691 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9692 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9695 /* VEX_LEN_0F58_P_1 */
9697 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9698 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9701 /* VEX_LEN_0F58_P_3 */
9703 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9704 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9707 /* VEX_LEN_0F59_P_1 */
9709 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9710 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9713 /* VEX_LEN_0F59_P_3 */
9715 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9716 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9719 /* VEX_LEN_0F5A_P_1 */
9721 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9722 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9725 /* VEX_LEN_0F5A_P_3 */
9727 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9728 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9731 /* VEX_LEN_0F5C_P_1 */
9733 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9734 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9737 /* VEX_LEN_0F5C_P_3 */
9739 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9740 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9743 /* VEX_LEN_0F5D_P_1 */
9745 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9746 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9749 /* VEX_LEN_0F5D_P_3 */
9751 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9752 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9755 /* VEX_LEN_0F5E_P_1 */
9757 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9758 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9761 /* VEX_LEN_0F5E_P_3 */
9763 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9764 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9767 /* VEX_LEN_0F5F_P_1 */
9769 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9770 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9773 /* VEX_LEN_0F5F_P_3 */
9775 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9776 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9779 /* VEX_LEN_0F6E_P_2 */
9781 { "vmovK", { XMScalar
, Edq
}, 0 },
9782 { "vmovK", { XMScalar
, Edq
}, 0 },
9785 /* VEX_LEN_0F7E_P_1 */
9787 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9788 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9791 /* VEX_LEN_0F7E_P_2 */
9793 { "vmovK", { Edq
, XMScalar
}, 0 },
9794 { "vmovK", { Edq
, XMScalar
}, 0 },
9797 /* VEX_LEN_0F90_P_0 */
9799 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9802 /* VEX_LEN_0F90_P_2 */
9804 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9807 /* VEX_LEN_0F91_P_0 */
9809 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9812 /* VEX_LEN_0F91_P_2 */
9814 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9817 /* VEX_LEN_0F92_P_0 */
9819 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9822 /* VEX_LEN_0F92_P_2 */
9824 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9827 /* VEX_LEN_0F92_P_3 */
9829 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9832 /* VEX_LEN_0F93_P_0 */
9834 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9837 /* VEX_LEN_0F93_P_2 */
9839 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9842 /* VEX_LEN_0F93_P_3 */
9844 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9847 /* VEX_LEN_0F98_P_0 */
9849 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9852 /* VEX_LEN_0F98_P_2 */
9854 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9857 /* VEX_LEN_0F99_P_0 */
9859 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9862 /* VEX_LEN_0F99_P_2 */
9864 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9867 /* VEX_LEN_0FAE_R_2_M_0 */
9869 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9872 /* VEX_LEN_0FAE_R_3_M_0 */
9874 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9877 /* VEX_LEN_0FC2_P_1 */
9879 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9880 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9883 /* VEX_LEN_0FC2_P_3 */
9885 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9886 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9889 /* VEX_LEN_0FC4_P_2 */
9891 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9894 /* VEX_LEN_0FC5_P_2 */
9896 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9899 /* VEX_LEN_0FD6_P_2 */
9901 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9902 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9905 /* VEX_LEN_0FF7_P_2 */
9907 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9910 /* VEX_LEN_0F3816_P_2 */
9913 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9916 /* VEX_LEN_0F3819_P_2 */
9919 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9922 /* VEX_LEN_0F381A_P_2_M_0 */
9925 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9928 /* VEX_LEN_0F3836_P_2 */
9931 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9934 /* VEX_LEN_0F3841_P_2 */
9936 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9939 /* VEX_LEN_0F385A_P_2_M_0 */
9942 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9945 /* VEX_LEN_0F38DB_P_2 */
9947 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9950 /* VEX_LEN_0F38F2_P_0 */
9952 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9955 /* VEX_LEN_0F38F3_R_1_P_0 */
9957 { "blsrS", { VexGdq
, Edq
}, 0 },
9960 /* VEX_LEN_0F38F3_R_2_P_0 */
9962 { "blsmskS", { VexGdq
, Edq
}, 0 },
9965 /* VEX_LEN_0F38F3_R_3_P_0 */
9967 { "blsiS", { VexGdq
, Edq
}, 0 },
9970 /* VEX_LEN_0F38F5_P_0 */
9972 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9975 /* VEX_LEN_0F38F5_P_1 */
9977 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9980 /* VEX_LEN_0F38F5_P_3 */
9982 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9985 /* VEX_LEN_0F38F6_P_3 */
9987 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9990 /* VEX_LEN_0F38F7_P_0 */
9992 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9995 /* VEX_LEN_0F38F7_P_1 */
9997 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
10000 /* VEX_LEN_0F38F7_P_2 */
10002 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
10005 /* VEX_LEN_0F38F7_P_3 */
10007 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
10010 /* VEX_LEN_0F3A00_P_2 */
10013 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10016 /* VEX_LEN_0F3A01_P_2 */
10019 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10022 /* VEX_LEN_0F3A06_P_2 */
10025 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10028 /* VEX_LEN_0F3A0A_P_2 */
10030 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10031 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10034 /* VEX_LEN_0F3A0B_P_2 */
10036 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10037 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10040 /* VEX_LEN_0F3A14_P_2 */
10042 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10045 /* VEX_LEN_0F3A15_P_2 */
10047 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10050 /* VEX_LEN_0F3A16_P_2 */
10052 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
10055 /* VEX_LEN_0F3A17_P_2 */
10057 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
10060 /* VEX_LEN_0F3A18_P_2 */
10063 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10066 /* VEX_LEN_0F3A19_P_2 */
10069 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10072 /* VEX_LEN_0F3A20_P_2 */
10074 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10077 /* VEX_LEN_0F3A21_P_2 */
10079 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10082 /* VEX_LEN_0F3A22_P_2 */
10084 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
10087 /* VEX_LEN_0F3A30_P_2 */
10089 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10092 /* VEX_LEN_0F3A31_P_2 */
10094 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10097 /* VEX_LEN_0F3A32_P_2 */
10099 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10102 /* VEX_LEN_0F3A33_P_2 */
10104 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10107 /* VEX_LEN_0F3A38_P_2 */
10110 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10113 /* VEX_LEN_0F3A39_P_2 */
10116 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10119 /* VEX_LEN_0F3A41_P_2 */
10121 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10124 /* VEX_LEN_0F3A46_P_2 */
10127 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10130 /* VEX_LEN_0F3A60_P_2 */
10132 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
10135 /* VEX_LEN_0F3A61_P_2 */
10137 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
10140 /* VEX_LEN_0F3A62_P_2 */
10142 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10145 /* VEX_LEN_0F3A63_P_2 */
10147 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10150 /* VEX_LEN_0F3A6A_P_2 */
10152 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10155 /* VEX_LEN_0F3A6B_P_2 */
10157 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10160 /* VEX_LEN_0F3A6E_P_2 */
10162 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10165 /* VEX_LEN_0F3A6F_P_2 */
10167 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10170 /* VEX_LEN_0F3A7A_P_2 */
10172 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10175 /* VEX_LEN_0F3A7B_P_2 */
10177 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10180 /* VEX_LEN_0F3A7E_P_2 */
10182 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10185 /* VEX_LEN_0F3A7F_P_2 */
10187 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10190 /* VEX_LEN_0F3ADF_P_2 */
10192 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10195 /* VEX_LEN_0F3AF0_P_3 */
10197 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10200 /* VEX_LEN_0FXOP_08_CC */
10202 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10205 /* VEX_LEN_0FXOP_08_CD */
10207 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10210 /* VEX_LEN_0FXOP_08_CE */
10212 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10215 /* VEX_LEN_0FXOP_08_CF */
10217 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10220 /* VEX_LEN_0FXOP_08_EC */
10222 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10225 /* VEX_LEN_0FXOP_08_ED */
10227 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10230 /* VEX_LEN_0FXOP_08_EE */
10232 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10235 /* VEX_LEN_0FXOP_08_EF */
10237 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10240 /* VEX_LEN_0FXOP_09_80 */
10242 { "vfrczps", { XM
, EXxmm
}, 0 },
10243 { "vfrczps", { XM
, EXymmq
}, 0 },
10246 /* VEX_LEN_0FXOP_09_81 */
10248 { "vfrczpd", { XM
, EXxmm
}, 0 },
10249 { "vfrczpd", { XM
, EXymmq
}, 0 },
10253 static const struct dis386 vex_w_table
[][2] = {
10255 /* VEX_W_0F10_P_0 */
10256 { "vmovups", { XM
, EXx
}, 0 },
10259 /* VEX_W_0F10_P_1 */
10260 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10263 /* VEX_W_0F10_P_2 */
10264 { "vmovupd", { XM
, EXx
}, 0 },
10267 /* VEX_W_0F10_P_3 */
10268 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10271 /* VEX_W_0F11_P_0 */
10272 { "vmovups", { EXxS
, XM
}, 0 },
10275 /* VEX_W_0F11_P_1 */
10276 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10279 /* VEX_W_0F11_P_2 */
10280 { "vmovupd", { EXxS
, XM
}, 0 },
10283 /* VEX_W_0F11_P_3 */
10284 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10287 /* VEX_W_0F12_P_0_M_0 */
10288 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10291 /* VEX_W_0F12_P_0_M_1 */
10292 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10295 /* VEX_W_0F12_P_1 */
10296 { "vmovsldup", { XM
, EXx
}, 0 },
10299 /* VEX_W_0F12_P_2 */
10300 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10303 /* VEX_W_0F12_P_3 */
10304 { "vmovddup", { XM
, EXymmq
}, 0 },
10307 /* VEX_W_0F13_M_0 */
10308 { "vmovlpX", { EXq
, XM
}, 0 },
10312 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10316 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10319 /* VEX_W_0F16_P_0_M_0 */
10320 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10323 /* VEX_W_0F16_P_0_M_1 */
10324 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10327 /* VEX_W_0F16_P_1 */
10328 { "vmovshdup", { XM
, EXx
}, 0 },
10331 /* VEX_W_0F16_P_2 */
10332 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10335 /* VEX_W_0F17_M_0 */
10336 { "vmovhpX", { EXq
, XM
}, 0 },
10340 { "vmovapX", { XM
, EXx
}, 0 },
10344 { "vmovapX", { EXxS
, XM
}, 0 },
10347 /* VEX_W_0F2B_M_0 */
10348 { "vmovntpX", { Mx
, XM
}, 0 },
10351 /* VEX_W_0F2E_P_0 */
10352 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10355 /* VEX_W_0F2E_P_2 */
10356 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10359 /* VEX_W_0F2F_P_0 */
10360 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10363 /* VEX_W_0F2F_P_2 */
10364 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10367 /* VEX_W_0F41_P_0_LEN_1 */
10368 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10369 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10372 /* VEX_W_0F41_P_2_LEN_1 */
10373 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10374 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10377 /* VEX_W_0F42_P_0_LEN_1 */
10378 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10379 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10382 /* VEX_W_0F42_P_2_LEN_1 */
10383 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10384 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10387 /* VEX_W_0F44_P_0_LEN_0 */
10388 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10389 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10392 /* VEX_W_0F44_P_2_LEN_0 */
10393 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10394 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10397 /* VEX_W_0F45_P_0_LEN_1 */
10398 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10399 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10402 /* VEX_W_0F45_P_2_LEN_1 */
10403 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10404 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10407 /* VEX_W_0F46_P_0_LEN_1 */
10408 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10409 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10412 /* VEX_W_0F46_P_2_LEN_1 */
10413 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10414 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10417 /* VEX_W_0F47_P_0_LEN_1 */
10418 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10419 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10422 /* VEX_W_0F47_P_2_LEN_1 */
10423 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10424 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10427 /* VEX_W_0F4A_P_0_LEN_1 */
10428 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10429 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10432 /* VEX_W_0F4A_P_2_LEN_1 */
10433 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10434 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10437 /* VEX_W_0F4B_P_0_LEN_1 */
10438 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10439 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10442 /* VEX_W_0F4B_P_2_LEN_1 */
10443 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10446 /* VEX_W_0F50_M_0 */
10447 { "vmovmskpX", { Gdq
, XS
}, 0 },
10450 /* VEX_W_0F51_P_0 */
10451 { "vsqrtps", { XM
, EXx
}, 0 },
10454 /* VEX_W_0F51_P_1 */
10455 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10458 /* VEX_W_0F51_P_2 */
10459 { "vsqrtpd", { XM
, EXx
}, 0 },
10462 /* VEX_W_0F51_P_3 */
10463 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10466 /* VEX_W_0F52_P_0 */
10467 { "vrsqrtps", { XM
, EXx
}, 0 },
10470 /* VEX_W_0F52_P_1 */
10471 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10474 /* VEX_W_0F53_P_0 */
10475 { "vrcpps", { XM
, EXx
}, 0 },
10478 /* VEX_W_0F53_P_1 */
10479 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10482 /* VEX_W_0F58_P_0 */
10483 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10486 /* VEX_W_0F58_P_1 */
10487 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10490 /* VEX_W_0F58_P_2 */
10491 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10494 /* VEX_W_0F58_P_3 */
10495 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10498 /* VEX_W_0F59_P_0 */
10499 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10502 /* VEX_W_0F59_P_1 */
10503 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10506 /* VEX_W_0F59_P_2 */
10507 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10510 /* VEX_W_0F59_P_3 */
10511 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10514 /* VEX_W_0F5A_P_0 */
10515 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10518 /* VEX_W_0F5A_P_1 */
10519 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10522 /* VEX_W_0F5A_P_3 */
10523 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10526 /* VEX_W_0F5B_P_0 */
10527 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10530 /* VEX_W_0F5B_P_1 */
10531 { "vcvttps2dq", { XM
, EXx
}, 0 },
10534 /* VEX_W_0F5B_P_2 */
10535 { "vcvtps2dq", { XM
, EXx
}, 0 },
10538 /* VEX_W_0F5C_P_0 */
10539 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10542 /* VEX_W_0F5C_P_1 */
10543 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10546 /* VEX_W_0F5C_P_2 */
10547 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10550 /* VEX_W_0F5C_P_3 */
10551 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10554 /* VEX_W_0F5D_P_0 */
10555 { "vminps", { XM
, Vex
, EXx
}, 0 },
10558 /* VEX_W_0F5D_P_1 */
10559 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10562 /* VEX_W_0F5D_P_2 */
10563 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10566 /* VEX_W_0F5D_P_3 */
10567 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10570 /* VEX_W_0F5E_P_0 */
10571 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10574 /* VEX_W_0F5E_P_1 */
10575 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10578 /* VEX_W_0F5E_P_2 */
10579 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10582 /* VEX_W_0F5E_P_3 */
10583 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10586 /* VEX_W_0F5F_P_0 */
10587 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10590 /* VEX_W_0F5F_P_1 */
10591 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10594 /* VEX_W_0F5F_P_2 */
10595 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10598 /* VEX_W_0F5F_P_3 */
10599 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10602 /* VEX_W_0F60_P_2 */
10603 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10606 /* VEX_W_0F61_P_2 */
10607 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10610 /* VEX_W_0F62_P_2 */
10611 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10614 /* VEX_W_0F63_P_2 */
10615 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10618 /* VEX_W_0F64_P_2 */
10619 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10622 /* VEX_W_0F65_P_2 */
10623 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10626 /* VEX_W_0F66_P_2 */
10627 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10630 /* VEX_W_0F67_P_2 */
10631 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10634 /* VEX_W_0F68_P_2 */
10635 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10638 /* VEX_W_0F69_P_2 */
10639 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10642 /* VEX_W_0F6A_P_2 */
10643 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10646 /* VEX_W_0F6B_P_2 */
10647 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10650 /* VEX_W_0F6C_P_2 */
10651 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10654 /* VEX_W_0F6D_P_2 */
10655 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10658 /* VEX_W_0F6F_P_1 */
10659 { "vmovdqu", { XM
, EXx
}, 0 },
10662 /* VEX_W_0F6F_P_2 */
10663 { "vmovdqa", { XM
, EXx
}, 0 },
10666 /* VEX_W_0F70_P_1 */
10667 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10670 /* VEX_W_0F70_P_2 */
10671 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10674 /* VEX_W_0F70_P_3 */
10675 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10678 /* VEX_W_0F71_R_2_P_2 */
10679 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10682 /* VEX_W_0F71_R_4_P_2 */
10683 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10686 /* VEX_W_0F71_R_6_P_2 */
10687 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10690 /* VEX_W_0F72_R_2_P_2 */
10691 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10694 /* VEX_W_0F72_R_4_P_2 */
10695 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10698 /* VEX_W_0F72_R_6_P_2 */
10699 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10702 /* VEX_W_0F73_R_2_P_2 */
10703 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10706 /* VEX_W_0F73_R_3_P_2 */
10707 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10710 /* VEX_W_0F73_R_6_P_2 */
10711 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10714 /* VEX_W_0F73_R_7_P_2 */
10715 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10718 /* VEX_W_0F74_P_2 */
10719 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10722 /* VEX_W_0F75_P_2 */
10723 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10726 /* VEX_W_0F76_P_2 */
10727 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10730 /* VEX_W_0F77_P_0 */
10731 { "", { VZERO
}, 0 },
10734 /* VEX_W_0F7C_P_2 */
10735 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10738 /* VEX_W_0F7C_P_3 */
10739 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10742 /* VEX_W_0F7D_P_2 */
10743 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10746 /* VEX_W_0F7D_P_3 */
10747 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10750 /* VEX_W_0F7E_P_1 */
10751 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10754 /* VEX_W_0F7F_P_1 */
10755 { "vmovdqu", { EXxS
, XM
}, 0 },
10758 /* VEX_W_0F7F_P_2 */
10759 { "vmovdqa", { EXxS
, XM
}, 0 },
10762 /* VEX_W_0F90_P_0_LEN_0 */
10763 { "kmovw", { MaskG
, MaskE
}, 0 },
10764 { "kmovq", { MaskG
, MaskE
}, 0 },
10767 /* VEX_W_0F90_P_2_LEN_0 */
10768 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10769 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10772 /* VEX_W_0F91_P_0_LEN_0 */
10773 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10774 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10777 /* VEX_W_0F91_P_2_LEN_0 */
10778 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10779 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10782 /* VEX_W_0F92_P_0_LEN_0 */
10783 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10786 /* VEX_W_0F92_P_2_LEN_0 */
10787 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10790 /* VEX_W_0F92_P_3_LEN_0 */
10791 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0
) },
10792 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0
) },
10795 /* VEX_W_0F93_P_0_LEN_0 */
10796 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10799 /* VEX_W_0F93_P_2_LEN_0 */
10800 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10803 /* VEX_W_0F93_P_3_LEN_0 */
10804 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0
) },
10805 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0
) },
10808 /* VEX_W_0F98_P_0_LEN_0 */
10809 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10810 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10813 /* VEX_W_0F98_P_2_LEN_0 */
10814 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10815 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10818 /* VEX_W_0F99_P_0_LEN_0 */
10819 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10820 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10823 /* VEX_W_0F99_P_2_LEN_0 */
10824 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10825 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10828 /* VEX_W_0FAE_R_2_M_0 */
10829 { "vldmxcsr", { Md
}, 0 },
10832 /* VEX_W_0FAE_R_3_M_0 */
10833 { "vstmxcsr", { Md
}, 0 },
10836 /* VEX_W_0FC2_P_0 */
10837 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
10840 /* VEX_W_0FC2_P_1 */
10841 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
10844 /* VEX_W_0FC2_P_2 */
10845 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
10848 /* VEX_W_0FC2_P_3 */
10849 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
10852 /* VEX_W_0FC4_P_2 */
10853 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
10856 /* VEX_W_0FC5_P_2 */
10857 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
10860 /* VEX_W_0FD0_P_2 */
10861 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
10864 /* VEX_W_0FD0_P_3 */
10865 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
10868 /* VEX_W_0FD1_P_2 */
10869 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
10872 /* VEX_W_0FD2_P_2 */
10873 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
10876 /* VEX_W_0FD3_P_2 */
10877 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
10880 /* VEX_W_0FD4_P_2 */
10881 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
10884 /* VEX_W_0FD5_P_2 */
10885 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
10888 /* VEX_W_0FD6_P_2 */
10889 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
10892 /* VEX_W_0FD7_P_2_M_1 */
10893 { "vpmovmskb", { Gdq
, XS
}, 0 },
10896 /* VEX_W_0FD8_P_2 */
10897 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
10900 /* VEX_W_0FD9_P_2 */
10901 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
10904 /* VEX_W_0FDA_P_2 */
10905 { "vpminub", { XM
, Vex
, EXx
}, 0 },
10908 /* VEX_W_0FDB_P_2 */
10909 { "vpand", { XM
, Vex
, EXx
}, 0 },
10912 /* VEX_W_0FDC_P_2 */
10913 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
10916 /* VEX_W_0FDD_P_2 */
10917 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
10920 /* VEX_W_0FDE_P_2 */
10921 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
10924 /* VEX_W_0FDF_P_2 */
10925 { "vpandn", { XM
, Vex
, EXx
}, 0 },
10928 /* VEX_W_0FE0_P_2 */
10929 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
10932 /* VEX_W_0FE1_P_2 */
10933 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
10936 /* VEX_W_0FE2_P_2 */
10937 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
10940 /* VEX_W_0FE3_P_2 */
10941 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
10944 /* VEX_W_0FE4_P_2 */
10945 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
10948 /* VEX_W_0FE5_P_2 */
10949 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
10952 /* VEX_W_0FE6_P_1 */
10953 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
10956 /* VEX_W_0FE6_P_2 */
10957 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
10960 /* VEX_W_0FE6_P_3 */
10961 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
10964 /* VEX_W_0FE7_P_2_M_0 */
10965 { "vmovntdq", { Mx
, XM
}, 0 },
10968 /* VEX_W_0FE8_P_2 */
10969 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
10972 /* VEX_W_0FE9_P_2 */
10973 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
10976 /* VEX_W_0FEA_P_2 */
10977 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
10980 /* VEX_W_0FEB_P_2 */
10981 { "vpor", { XM
, Vex
, EXx
}, 0 },
10984 /* VEX_W_0FEC_P_2 */
10985 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
10988 /* VEX_W_0FED_P_2 */
10989 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
10992 /* VEX_W_0FEE_P_2 */
10993 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
10996 /* VEX_W_0FEF_P_2 */
10997 { "vpxor", { XM
, Vex
, EXx
}, 0 },
11000 /* VEX_W_0FF0_P_3_M_0 */
11001 { "vlddqu", { XM
, M
}, 0 },
11004 /* VEX_W_0FF1_P_2 */
11005 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
11008 /* VEX_W_0FF2_P_2 */
11009 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
11012 /* VEX_W_0FF3_P_2 */
11013 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
11016 /* VEX_W_0FF4_P_2 */
11017 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
11020 /* VEX_W_0FF5_P_2 */
11021 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
11024 /* VEX_W_0FF6_P_2 */
11025 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
11028 /* VEX_W_0FF7_P_2 */
11029 { "vmaskmovdqu", { XM
, XS
}, 0 },
11032 /* VEX_W_0FF8_P_2 */
11033 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
11036 /* VEX_W_0FF9_P_2 */
11037 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
11040 /* VEX_W_0FFA_P_2 */
11041 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
11044 /* VEX_W_0FFB_P_2 */
11045 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
11048 /* VEX_W_0FFC_P_2 */
11049 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
11052 /* VEX_W_0FFD_P_2 */
11053 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
11056 /* VEX_W_0FFE_P_2 */
11057 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
11060 /* VEX_W_0F3800_P_2 */
11061 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
11064 /* VEX_W_0F3801_P_2 */
11065 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
11068 /* VEX_W_0F3802_P_2 */
11069 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
11072 /* VEX_W_0F3803_P_2 */
11073 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
11076 /* VEX_W_0F3804_P_2 */
11077 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
11080 /* VEX_W_0F3805_P_2 */
11081 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
11084 /* VEX_W_0F3806_P_2 */
11085 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
11088 /* VEX_W_0F3807_P_2 */
11089 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
11092 /* VEX_W_0F3808_P_2 */
11093 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
11096 /* VEX_W_0F3809_P_2 */
11097 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
11100 /* VEX_W_0F380A_P_2 */
11101 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
11104 /* VEX_W_0F380B_P_2 */
11105 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
11108 /* VEX_W_0F380C_P_2 */
11109 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
11112 /* VEX_W_0F380D_P_2 */
11113 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
11116 /* VEX_W_0F380E_P_2 */
11117 { "vtestps", { XM
, EXx
}, 0 },
11120 /* VEX_W_0F380F_P_2 */
11121 { "vtestpd", { XM
, EXx
}, 0 },
11124 /* VEX_W_0F3816_P_2 */
11125 { "vpermps", { XM
, Vex
, EXx
}, 0 },
11128 /* VEX_W_0F3817_P_2 */
11129 { "vptest", { XM
, EXx
}, 0 },
11132 /* VEX_W_0F3818_P_2 */
11133 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11136 /* VEX_W_0F3819_P_2 */
11137 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11140 /* VEX_W_0F381A_P_2_M_0 */
11141 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11144 /* VEX_W_0F381C_P_2 */
11145 { "vpabsb", { XM
, EXx
}, 0 },
11148 /* VEX_W_0F381D_P_2 */
11149 { "vpabsw", { XM
, EXx
}, 0 },
11152 /* VEX_W_0F381E_P_2 */
11153 { "vpabsd", { XM
, EXx
}, 0 },
11156 /* VEX_W_0F3820_P_2 */
11157 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11160 /* VEX_W_0F3821_P_2 */
11161 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11164 /* VEX_W_0F3822_P_2 */
11165 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11168 /* VEX_W_0F3823_P_2 */
11169 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11172 /* VEX_W_0F3824_P_2 */
11173 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11176 /* VEX_W_0F3825_P_2 */
11177 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11180 /* VEX_W_0F3828_P_2 */
11181 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11184 /* VEX_W_0F3829_P_2 */
11185 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11188 /* VEX_W_0F382A_P_2_M_0 */
11189 { "vmovntdqa", { XM
, Mx
}, 0 },
11192 /* VEX_W_0F382B_P_2 */
11193 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11196 /* VEX_W_0F382C_P_2_M_0 */
11197 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11200 /* VEX_W_0F382D_P_2_M_0 */
11201 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11204 /* VEX_W_0F382E_P_2_M_0 */
11205 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11208 /* VEX_W_0F382F_P_2_M_0 */
11209 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11212 /* VEX_W_0F3830_P_2 */
11213 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11216 /* VEX_W_0F3831_P_2 */
11217 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11220 /* VEX_W_0F3832_P_2 */
11221 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11224 /* VEX_W_0F3833_P_2 */
11225 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11228 /* VEX_W_0F3834_P_2 */
11229 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11232 /* VEX_W_0F3835_P_2 */
11233 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11236 /* VEX_W_0F3836_P_2 */
11237 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11240 /* VEX_W_0F3837_P_2 */
11241 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11244 /* VEX_W_0F3838_P_2 */
11245 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11248 /* VEX_W_0F3839_P_2 */
11249 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11252 /* VEX_W_0F383A_P_2 */
11253 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11256 /* VEX_W_0F383B_P_2 */
11257 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11260 /* VEX_W_0F383C_P_2 */
11261 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11264 /* VEX_W_0F383D_P_2 */
11265 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11268 /* VEX_W_0F383E_P_2 */
11269 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11272 /* VEX_W_0F383F_P_2 */
11273 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11276 /* VEX_W_0F3840_P_2 */
11277 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11280 /* VEX_W_0F3841_P_2 */
11281 { "vphminposuw", { XM
, EXx
}, 0 },
11284 /* VEX_W_0F3846_P_2 */
11285 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11288 /* VEX_W_0F3858_P_2 */
11289 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11292 /* VEX_W_0F3859_P_2 */
11293 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11296 /* VEX_W_0F385A_P_2_M_0 */
11297 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11300 /* VEX_W_0F3878_P_2 */
11301 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11304 /* VEX_W_0F3879_P_2 */
11305 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11308 /* VEX_W_0F38CF_P_2 */
11309 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
11312 /* VEX_W_0F38DB_P_2 */
11313 { "vaesimc", { XM
, EXx
}, 0 },
11316 /* VEX_W_0F3A00_P_2 */
11318 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11321 /* VEX_W_0F3A01_P_2 */
11323 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11326 /* VEX_W_0F3A02_P_2 */
11327 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11330 /* VEX_W_0F3A04_P_2 */
11331 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11334 /* VEX_W_0F3A05_P_2 */
11335 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11338 /* VEX_W_0F3A06_P_2 */
11339 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11342 /* VEX_W_0F3A08_P_2 */
11343 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11346 /* VEX_W_0F3A09_P_2 */
11347 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11350 /* VEX_W_0F3A0A_P_2 */
11351 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11354 /* VEX_W_0F3A0B_P_2 */
11355 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11358 /* VEX_W_0F3A0C_P_2 */
11359 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11362 /* VEX_W_0F3A0D_P_2 */
11363 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11366 /* VEX_W_0F3A0E_P_2 */
11367 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11370 /* VEX_W_0F3A0F_P_2 */
11371 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11374 /* VEX_W_0F3A14_P_2 */
11375 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11378 /* VEX_W_0F3A15_P_2 */
11379 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11382 /* VEX_W_0F3A18_P_2 */
11383 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11386 /* VEX_W_0F3A19_P_2 */
11387 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11390 /* VEX_W_0F3A20_P_2 */
11391 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11394 /* VEX_W_0F3A21_P_2 */
11395 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11398 /* VEX_W_0F3A30_P_2_LEN_0 */
11399 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
11400 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
11403 /* VEX_W_0F3A31_P_2_LEN_0 */
11404 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
11405 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
11408 /* VEX_W_0F3A32_P_2_LEN_0 */
11409 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
11410 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
11413 /* VEX_W_0F3A33_P_2_LEN_0 */
11414 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
11415 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
11418 /* VEX_W_0F3A38_P_2 */
11419 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11422 /* VEX_W_0F3A39_P_2 */
11423 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11426 /* VEX_W_0F3A40_P_2 */
11427 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11430 /* VEX_W_0F3A41_P_2 */
11431 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11434 /* VEX_W_0F3A42_P_2 */
11435 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11438 /* VEX_W_0F3A46_P_2 */
11439 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11442 /* VEX_W_0F3A48_P_2 */
11443 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11444 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11447 /* VEX_W_0F3A49_P_2 */
11448 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11449 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11452 /* VEX_W_0F3A4A_P_2 */
11453 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11456 /* VEX_W_0F3A4B_P_2 */
11457 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11460 /* VEX_W_0F3A4C_P_2 */
11461 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11464 /* VEX_W_0F3A62_P_2 */
11465 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11468 /* VEX_W_0F3A63_P_2 */
11469 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11472 /* VEX_W_0F3ACE_P_2 */
11474 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
11477 /* VEX_W_0F3ACF_P_2 */
11479 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
11482 /* VEX_W_0F3ADF_P_2 */
11483 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11485 #define NEED_VEX_W_TABLE
11486 #include "i386-dis-evex.h"
11487 #undef NEED_VEX_W_TABLE
11490 static const struct dis386 mod_table
[][2] = {
11493 { "leaS", { Gv
, M
}, 0 },
11498 { RM_TABLE (RM_C6_REG_7
) },
11503 { RM_TABLE (RM_C7_REG_7
) },
11507 { "Jcall^", { indirEp
}, 0 },
11511 { "Jjmp^", { indirEp
}, 0 },
11514 /* MOD_0F01_REG_0 */
11515 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11516 { RM_TABLE (RM_0F01_REG_0
) },
11519 /* MOD_0F01_REG_1 */
11520 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11521 { RM_TABLE (RM_0F01_REG_1
) },
11524 /* MOD_0F01_REG_2 */
11525 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11526 { RM_TABLE (RM_0F01_REG_2
) },
11529 /* MOD_0F01_REG_3 */
11530 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11531 { RM_TABLE (RM_0F01_REG_3
) },
11534 /* MOD_0F01_REG_5 */
11535 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5
) },
11536 { RM_TABLE (RM_0F01_REG_5
) },
11539 /* MOD_0F01_REG_7 */
11540 { "invlpg", { Mb
}, 0 },
11541 { RM_TABLE (RM_0F01_REG_7
) },
11544 /* MOD_0F12_PREFIX_0 */
11545 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
11546 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
11550 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
11553 /* MOD_0F16_PREFIX_0 */
11554 { "movhps", { XM
, EXq
}, 0 },
11555 { "movlhps", { XM
, EXq
}, 0 },
11559 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
11562 /* MOD_0F18_REG_0 */
11563 { "prefetchnta", { Mb
}, 0 },
11566 /* MOD_0F18_REG_1 */
11567 { "prefetcht0", { Mb
}, 0 },
11570 /* MOD_0F18_REG_2 */
11571 { "prefetcht1", { Mb
}, 0 },
11574 /* MOD_0F18_REG_3 */
11575 { "prefetcht2", { Mb
}, 0 },
11578 /* MOD_0F18_REG_4 */
11579 { "nop/reserved", { Mb
}, 0 },
11582 /* MOD_0F18_REG_5 */
11583 { "nop/reserved", { Mb
}, 0 },
11586 /* MOD_0F18_REG_6 */
11587 { "nop/reserved", { Mb
}, 0 },
11590 /* MOD_0F18_REG_7 */
11591 { "nop/reserved", { Mb
}, 0 },
11594 /* MOD_0F1A_PREFIX_0 */
11595 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11596 { "nopQ", { Ev
}, 0 },
11599 /* MOD_0F1B_PREFIX_0 */
11600 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11601 { "nopQ", { Ev
}, 0 },
11604 /* MOD_0F1B_PREFIX_1 */
11605 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11606 { "nopQ", { Ev
}, 0 },
11609 /* MOD_0F1E_PREFIX_1 */
11610 { "nopQ", { Ev
}, 0 },
11611 { REG_TABLE (REG_0F1E_MOD_3
) },
11616 { "movL", { Rd
, Td
}, 0 },
11621 { "movL", { Td
, Rd
}, 0 },
11624 /* MOD_0F2B_PREFIX_0 */
11625 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
11628 /* MOD_0F2B_PREFIX_1 */
11629 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
11632 /* MOD_0F2B_PREFIX_2 */
11633 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
11636 /* MOD_0F2B_PREFIX_3 */
11637 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
11642 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11645 /* MOD_0F71_REG_2 */
11647 { "psrlw", { MS
, Ib
}, 0 },
11650 /* MOD_0F71_REG_4 */
11652 { "psraw", { MS
, Ib
}, 0 },
11655 /* MOD_0F71_REG_6 */
11657 { "psllw", { MS
, Ib
}, 0 },
11660 /* MOD_0F72_REG_2 */
11662 { "psrld", { MS
, Ib
}, 0 },
11665 /* MOD_0F72_REG_4 */
11667 { "psrad", { MS
, Ib
}, 0 },
11670 /* MOD_0F72_REG_6 */
11672 { "pslld", { MS
, Ib
}, 0 },
11675 /* MOD_0F73_REG_2 */
11677 { "psrlq", { MS
, Ib
}, 0 },
11680 /* MOD_0F73_REG_3 */
11682 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11685 /* MOD_0F73_REG_6 */
11687 { "psllq", { MS
, Ib
}, 0 },
11690 /* MOD_0F73_REG_7 */
11692 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11695 /* MOD_0FAE_REG_0 */
11696 { "fxsave", { FXSAVE
}, 0 },
11697 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11700 /* MOD_0FAE_REG_1 */
11701 { "fxrstor", { FXSAVE
}, 0 },
11702 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11705 /* MOD_0FAE_REG_2 */
11706 { "ldmxcsr", { Md
}, 0 },
11707 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11710 /* MOD_0FAE_REG_3 */
11711 { "stmxcsr", { Md
}, 0 },
11712 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11715 /* MOD_0FAE_REG_4 */
11716 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
11717 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
11720 /* MOD_0FAE_REG_5 */
11721 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5
) },
11722 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5
) },
11725 /* MOD_0FAE_REG_6 */
11726 { PREFIX_TABLE (PREFIX_0FAE_REG_6
) },
11727 { RM_TABLE (RM_0FAE_REG_6
) },
11730 /* MOD_0FAE_REG_7 */
11731 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11732 { RM_TABLE (RM_0FAE_REG_7
) },
11736 { "lssS", { Gv
, Mp
}, 0 },
11740 { "lfsS", { Gv
, Mp
}, 0 },
11744 { "lgsS", { Gv
, Mp
}, 0 },
11748 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
11751 /* MOD_0FC7_REG_3 */
11752 { "xrstors", { FXSAVE
}, 0 },
11755 /* MOD_0FC7_REG_4 */
11756 { "xsavec", { FXSAVE
}, 0 },
11759 /* MOD_0FC7_REG_5 */
11760 { "xsaves", { FXSAVE
}, 0 },
11763 /* MOD_0FC7_REG_6 */
11764 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
11765 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
11768 /* MOD_0FC7_REG_7 */
11769 { "vmptrst", { Mq
}, 0 },
11770 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
11775 { "pmovmskb", { Gdq
, MS
}, 0 },
11778 /* MOD_0FE7_PREFIX_2 */
11779 { "movntdq", { Mx
, XM
}, 0 },
11782 /* MOD_0FF0_PREFIX_3 */
11783 { "lddqu", { XM
, M
}, 0 },
11786 /* MOD_0F382A_PREFIX_2 */
11787 { "movntdqa", { XM
, Mx
}, 0 },
11790 /* MOD_0F38F5_PREFIX_2 */
11791 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
11794 /* MOD_0F38F6_PREFIX_0 */
11795 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
11799 { "bound{S|}", { Gv
, Ma
}, 0 },
11800 { EVEX_TABLE (EVEX_0F
) },
11804 { "lesS", { Gv
, Mp
}, 0 },
11805 { VEX_C4_TABLE (VEX_0F
) },
11809 { "ldsS", { Gv
, Mp
}, 0 },
11810 { VEX_C5_TABLE (VEX_0F
) },
11813 /* MOD_VEX_0F12_PREFIX_0 */
11814 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11815 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11819 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11822 /* MOD_VEX_0F16_PREFIX_0 */
11823 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11824 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11828 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11832 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11835 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11837 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
11840 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11842 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
11845 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11847 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
11850 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11852 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
11855 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11857 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
11860 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11862 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
11865 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11867 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
11870 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11872 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
11875 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11877 { "knotw", { MaskG
, MaskR
}, 0 },
11880 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11882 { "knotq", { MaskG
, MaskR
}, 0 },
11885 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11887 { "knotb", { MaskG
, MaskR
}, 0 },
11890 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11892 { "knotd", { MaskG
, MaskR
}, 0 },
11895 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11897 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
11900 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11902 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
11905 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11907 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
11910 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11912 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
11915 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11917 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11920 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11922 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11925 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11927 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11930 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11932 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
11935 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11937 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11940 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11942 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11945 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11947 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11950 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11952 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
11955 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11957 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
11960 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11962 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
11965 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11967 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
11970 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11972 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
11975 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11977 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
11980 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11982 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
11985 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11987 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
11992 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
11995 /* MOD_VEX_0F71_REG_2 */
11997 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
12000 /* MOD_VEX_0F71_REG_4 */
12002 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
12005 /* MOD_VEX_0F71_REG_6 */
12007 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
12010 /* MOD_VEX_0F72_REG_2 */
12012 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
12015 /* MOD_VEX_0F72_REG_4 */
12017 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
12020 /* MOD_VEX_0F72_REG_6 */
12022 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
12025 /* MOD_VEX_0F73_REG_2 */
12027 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
12030 /* MOD_VEX_0F73_REG_3 */
12032 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
12035 /* MOD_VEX_0F73_REG_6 */
12037 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
12040 /* MOD_VEX_0F73_REG_7 */
12042 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
12045 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12046 { "kmovw", { Ew
, MaskG
}, 0 },
12050 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12051 { "kmovq", { Eq
, MaskG
}, 0 },
12055 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12056 { "kmovb", { Eb
, MaskG
}, 0 },
12060 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12061 { "kmovd", { Ed
, MaskG
}, 0 },
12065 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12067 { "kmovw", { MaskG
, Rdq
}, 0 },
12070 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12072 { "kmovb", { MaskG
, Rdq
}, 0 },
12075 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12077 { "kmovd", { MaskG
, Rdq
}, 0 },
12080 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12082 { "kmovq", { MaskG
, Rdq
}, 0 },
12085 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12087 { "kmovw", { Gdq
, MaskR
}, 0 },
12090 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12092 { "kmovb", { Gdq
, MaskR
}, 0 },
12095 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12097 { "kmovd", { Gdq
, MaskR
}, 0 },
12100 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12102 { "kmovq", { Gdq
, MaskR
}, 0 },
12105 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12107 { "kortestw", { MaskG
, MaskR
}, 0 },
12110 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12112 { "kortestq", { MaskG
, MaskR
}, 0 },
12115 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12117 { "kortestb", { MaskG
, MaskR
}, 0 },
12120 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12122 { "kortestd", { MaskG
, MaskR
}, 0 },
12125 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12127 { "ktestw", { MaskG
, MaskR
}, 0 },
12130 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12132 { "ktestq", { MaskG
, MaskR
}, 0 },
12135 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12137 { "ktestb", { MaskG
, MaskR
}, 0 },
12140 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12142 { "ktestd", { MaskG
, MaskR
}, 0 },
12145 /* MOD_VEX_0FAE_REG_2 */
12146 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
12149 /* MOD_VEX_0FAE_REG_3 */
12150 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
12153 /* MOD_VEX_0FD7_PREFIX_2 */
12155 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
12158 /* MOD_VEX_0FE7_PREFIX_2 */
12159 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
12162 /* MOD_VEX_0FF0_PREFIX_3 */
12163 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
12166 /* MOD_VEX_0F381A_PREFIX_2 */
12167 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
12170 /* MOD_VEX_0F382A_PREFIX_2 */
12171 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
12174 /* MOD_VEX_0F382C_PREFIX_2 */
12175 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
12178 /* MOD_VEX_0F382D_PREFIX_2 */
12179 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
12182 /* MOD_VEX_0F382E_PREFIX_2 */
12183 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
12186 /* MOD_VEX_0F382F_PREFIX_2 */
12187 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
12190 /* MOD_VEX_0F385A_PREFIX_2 */
12191 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
12194 /* MOD_VEX_0F388C_PREFIX_2 */
12195 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
12198 /* MOD_VEX_0F388E_PREFIX_2 */
12199 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
12202 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12204 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
12207 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12209 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
12212 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12214 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
12217 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12219 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
12222 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12224 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
12227 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12229 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
12232 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12234 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
12237 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12239 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
12241 #define NEED_MOD_TABLE
12242 #include "i386-dis-evex.h"
12243 #undef NEED_MOD_TABLE
12246 static const struct dis386 rm_table
[][8] = {
12249 { "xabort", { Skip_MODRM
, Ib
}, 0 },
12253 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
12256 /* RM_0F01_REG_0 */
12258 { "vmcall", { Skip_MODRM
}, 0 },
12259 { "vmlaunch", { Skip_MODRM
}, 0 },
12260 { "vmresume", { Skip_MODRM
}, 0 },
12261 { "vmxoff", { Skip_MODRM
}, 0 },
12264 /* RM_0F01_REG_1 */
12265 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12266 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12267 { "clac", { Skip_MODRM
}, 0 },
12268 { "stac", { Skip_MODRM
}, 0 },
12272 { "encls", { Skip_MODRM
}, 0 },
12275 /* RM_0F01_REG_2 */
12276 { "xgetbv", { Skip_MODRM
}, 0 },
12277 { "xsetbv", { Skip_MODRM
}, 0 },
12280 { "vmfunc", { Skip_MODRM
}, 0 },
12281 { "xend", { Skip_MODRM
}, 0 },
12282 { "xtest", { Skip_MODRM
}, 0 },
12283 { "enclu", { Skip_MODRM
}, 0 },
12286 /* RM_0F01_REG_3 */
12287 { "vmrun", { Skip_MODRM
}, 0 },
12288 { "vmmcall", { Skip_MODRM
}, 0 },
12289 { "vmload", { Skip_MODRM
}, 0 },
12290 { "vmsave", { Skip_MODRM
}, 0 },
12291 { "stgi", { Skip_MODRM
}, 0 },
12292 { "clgi", { Skip_MODRM
}, 0 },
12293 { "skinit", { Skip_MODRM
}, 0 },
12294 { "invlpga", { Skip_MODRM
}, 0 },
12297 /* RM_0F01_REG_5 */
12298 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0
) },
12300 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2
) },
12304 { "rdpkru", { Skip_MODRM
}, 0 },
12305 { "wrpkru", { Skip_MODRM
}, 0 },
12308 /* RM_0F01_REG_7 */
12309 { "swapgs", { Skip_MODRM
}, 0 },
12310 { "rdtscp", { Skip_MODRM
}, 0 },
12311 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
12312 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
12313 { "clzero", { Skip_MODRM
}, 0 },
12316 /* RM_0F1E_MOD_3_REG_7 */
12317 { "nopQ", { Ev
}, 0 },
12318 { "nopQ", { Ev
}, 0 },
12319 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
12320 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
12321 { "nopQ", { Ev
}, 0 },
12322 { "nopQ", { Ev
}, 0 },
12323 { "nopQ", { Ev
}, 0 },
12324 { "nopQ", { Ev
}, 0 },
12327 /* RM_0FAE_REG_6 */
12328 { "mfence", { Skip_MODRM
}, 0 },
12331 /* RM_0FAE_REG_7 */
12332 { "sfence", { Skip_MODRM
}, 0 },
12337 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12339 /* We use the high bit to indicate different name for the same
12341 #define REP_PREFIX (0xf3 | 0x100)
12342 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12343 #define XRELEASE_PREFIX (0xf3 | 0x400)
12344 #define BND_PREFIX (0xf2 | 0x400)
12345 #define NOTRACK_PREFIX (0x3e | 0x100)
12350 int newrex
, i
, length
;
12356 last_lock_prefix
= -1;
12357 last_repz_prefix
= -1;
12358 last_repnz_prefix
= -1;
12359 last_data_prefix
= -1;
12360 last_addr_prefix
= -1;
12361 last_rex_prefix
= -1;
12362 last_seg_prefix
= -1;
12364 active_seg_prefix
= 0;
12365 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12366 all_prefixes
[i
] = 0;
12369 /* The maximum instruction length is 15bytes. */
12370 while (length
< MAX_CODE_LENGTH
- 1)
12372 FETCH_DATA (the_info
, codep
+ 1);
12376 /* REX prefixes family. */
12393 if (address_mode
== mode_64bit
)
12397 last_rex_prefix
= i
;
12400 prefixes
|= PREFIX_REPZ
;
12401 last_repz_prefix
= i
;
12404 prefixes
|= PREFIX_REPNZ
;
12405 last_repnz_prefix
= i
;
12408 prefixes
|= PREFIX_LOCK
;
12409 last_lock_prefix
= i
;
12412 prefixes
|= PREFIX_CS
;
12413 last_seg_prefix
= i
;
12414 active_seg_prefix
= PREFIX_CS
;
12417 prefixes
|= PREFIX_SS
;
12418 last_seg_prefix
= i
;
12419 active_seg_prefix
= PREFIX_SS
;
12422 prefixes
|= PREFIX_DS
;
12423 last_seg_prefix
= i
;
12424 active_seg_prefix
= PREFIX_DS
;
12427 prefixes
|= PREFIX_ES
;
12428 last_seg_prefix
= i
;
12429 active_seg_prefix
= PREFIX_ES
;
12432 prefixes
|= PREFIX_FS
;
12433 last_seg_prefix
= i
;
12434 active_seg_prefix
= PREFIX_FS
;
12437 prefixes
|= PREFIX_GS
;
12438 last_seg_prefix
= i
;
12439 active_seg_prefix
= PREFIX_GS
;
12442 prefixes
|= PREFIX_DATA
;
12443 last_data_prefix
= i
;
12446 prefixes
|= PREFIX_ADDR
;
12447 last_addr_prefix
= i
;
12450 /* fwait is really an instruction. If there are prefixes
12451 before the fwait, they belong to the fwait, *not* to the
12452 following instruction. */
12454 if (prefixes
|| rex
)
12456 prefixes
|= PREFIX_FWAIT
;
12458 /* This ensures that the previous REX prefixes are noticed
12459 as unused prefixes, as in the return case below. */
12463 prefixes
= PREFIX_FWAIT
;
12468 /* Rex is ignored when followed by another prefix. */
12474 if (*codep
!= FWAIT_OPCODE
)
12475 all_prefixes
[i
++] = *codep
;
12483 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12486 static const char *
12487 prefix_name (int pref
, int sizeflag
)
12489 static const char *rexes
[16] =
12492 "rex.B", /* 0x41 */
12493 "rex.X", /* 0x42 */
12494 "rex.XB", /* 0x43 */
12495 "rex.R", /* 0x44 */
12496 "rex.RB", /* 0x45 */
12497 "rex.RX", /* 0x46 */
12498 "rex.RXB", /* 0x47 */
12499 "rex.W", /* 0x48 */
12500 "rex.WB", /* 0x49 */
12501 "rex.WX", /* 0x4a */
12502 "rex.WXB", /* 0x4b */
12503 "rex.WR", /* 0x4c */
12504 "rex.WRB", /* 0x4d */
12505 "rex.WRX", /* 0x4e */
12506 "rex.WRXB", /* 0x4f */
12511 /* REX prefixes family. */
12528 return rexes
[pref
- 0x40];
12548 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12550 if (address_mode
== mode_64bit
)
12551 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12553 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12558 case XACQUIRE_PREFIX
:
12560 case XRELEASE_PREFIX
:
12564 case NOTRACK_PREFIX
:
12571 static char op_out
[MAX_OPERANDS
][100];
12572 static int op_ad
, op_index
[MAX_OPERANDS
];
12573 static int two_source_ops
;
12574 static bfd_vma op_address
[MAX_OPERANDS
];
12575 static bfd_vma op_riprel
[MAX_OPERANDS
];
12576 static bfd_vma start_pc
;
12579 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12580 * (see topic "Redundant prefixes" in the "Differences from 8086"
12581 * section of the "Virtual 8086 Mode" chapter.)
12582 * 'pc' should be the address of this instruction, it will
12583 * be used to print the target address if this is a relative jump or call
12584 * The function returns the length of this instruction in bytes.
12587 static char intel_syntax
;
12588 static char intel_mnemonic
= !SYSV386_COMPAT
;
12589 static char open_char
;
12590 static char close_char
;
12591 static char separator_char
;
12592 static char scale_char
;
12600 static enum x86_64_isa isa64
;
12602 /* Here for backwards compatibility. When gdb stops using
12603 print_insn_i386_att and print_insn_i386_intel these functions can
12604 disappear, and print_insn_i386 be merged into print_insn. */
12606 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12610 return print_insn (pc
, info
);
12614 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12618 return print_insn (pc
, info
);
12622 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12626 return print_insn (pc
, info
);
12630 print_i386_disassembler_options (FILE *stream
)
12632 fprintf (stream
, _("\n\
12633 The following i386/x86-64 specific disassembler options are supported for use\n\
12634 with the -M switch (multiple options should be separated by commas):\n"));
12636 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12637 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12638 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12639 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12640 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12641 fprintf (stream
, _(" att-mnemonic\n"
12642 " Display instruction in AT&T mnemonic\n"));
12643 fprintf (stream
, _(" intel-mnemonic\n"
12644 " Display instruction in Intel mnemonic\n"));
12645 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12646 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12647 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12648 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12649 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12650 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12651 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
12652 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
12656 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12658 /* Get a pointer to struct dis386 with a valid name. */
12660 static const struct dis386
*
12661 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12663 int vindex
, vex_table_index
;
12665 if (dp
->name
!= NULL
)
12668 switch (dp
->op
[0].bytemode
)
12670 case USE_REG_TABLE
:
12671 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12674 case USE_MOD_TABLE
:
12675 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12676 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12680 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12683 case USE_PREFIX_TABLE
:
12686 /* The prefix in VEX is implicit. */
12687 switch (vex
.prefix
)
12692 case REPE_PREFIX_OPCODE
:
12695 case DATA_PREFIX_OPCODE
:
12698 case REPNE_PREFIX_OPCODE
:
12708 int last_prefix
= -1;
12711 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12712 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12714 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12716 if (last_repz_prefix
> last_repnz_prefix
)
12719 prefix
= PREFIX_REPZ
;
12720 last_prefix
= last_repz_prefix
;
12725 prefix
= PREFIX_REPNZ
;
12726 last_prefix
= last_repnz_prefix
;
12729 /* Check if prefix should be ignored. */
12730 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12731 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12736 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12739 prefix
= PREFIX_DATA
;
12740 last_prefix
= last_data_prefix
;
12745 used_prefixes
|= prefix
;
12746 all_prefixes
[last_prefix
] = 0;
12749 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12752 case USE_X86_64_TABLE
:
12753 vindex
= address_mode
== mode_64bit
? 1 : 0;
12754 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12757 case USE_3BYTE_TABLE
:
12758 FETCH_DATA (info
, codep
+ 2);
12760 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12762 modrm
.mod
= (*codep
>> 6) & 3;
12763 modrm
.reg
= (*codep
>> 3) & 7;
12764 modrm
.rm
= *codep
& 7;
12767 case USE_VEX_LEN_TABLE
:
12771 switch (vex
.length
)
12784 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12787 case USE_XOP_8F_TABLE
:
12788 FETCH_DATA (info
, codep
+ 3);
12789 /* All bits in the REX prefix are ignored. */
12791 rex
= ~(*codep
>> 5) & 0x7;
12793 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12794 switch ((*codep
& 0x1f))
12800 vex_table_index
= XOP_08
;
12803 vex_table_index
= XOP_09
;
12806 vex_table_index
= XOP_0A
;
12810 vex
.w
= *codep
& 0x80;
12811 if (vex
.w
&& address_mode
== mode_64bit
)
12814 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12815 if (address_mode
!= mode_64bit
)
12817 /* In 16/32-bit mode REX_B is silently ignored. */
12821 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12822 switch ((*codep
& 0x3))
12828 vex
.prefix
= DATA_PREFIX_OPCODE
;
12831 vex
.prefix
= REPE_PREFIX_OPCODE
;
12834 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12841 dp
= &xop_table
[vex_table_index
][vindex
];
12844 FETCH_DATA (info
, codep
+ 1);
12845 modrm
.mod
= (*codep
>> 6) & 3;
12846 modrm
.reg
= (*codep
>> 3) & 7;
12847 modrm
.rm
= *codep
& 7;
12850 case USE_VEX_C4_TABLE
:
12852 FETCH_DATA (info
, codep
+ 3);
12853 /* All bits in the REX prefix are ignored. */
12855 rex
= ~(*codep
>> 5) & 0x7;
12856 switch ((*codep
& 0x1f))
12862 vex_table_index
= VEX_0F
;
12865 vex_table_index
= VEX_0F38
;
12868 vex_table_index
= VEX_0F3A
;
12872 vex
.w
= *codep
& 0x80;
12873 if (address_mode
== mode_64bit
)
12880 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12881 is ignored, other REX bits are 0 and the highest bit in
12882 VEX.vvvv is also ignored (but we mustn't clear it here). */
12885 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12886 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12887 switch ((*codep
& 0x3))
12893 vex
.prefix
= DATA_PREFIX_OPCODE
;
12896 vex
.prefix
= REPE_PREFIX_OPCODE
;
12899 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12906 dp
= &vex_table
[vex_table_index
][vindex
];
12908 /* There is no MODRM byte for VEX0F 77. */
12909 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
12911 FETCH_DATA (info
, codep
+ 1);
12912 modrm
.mod
= (*codep
>> 6) & 3;
12913 modrm
.reg
= (*codep
>> 3) & 7;
12914 modrm
.rm
= *codep
& 7;
12918 case USE_VEX_C5_TABLE
:
12920 FETCH_DATA (info
, codep
+ 2);
12921 /* All bits in the REX prefix are ignored. */
12923 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12925 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12927 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12929 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12930 switch ((*codep
& 0x3))
12936 vex
.prefix
= DATA_PREFIX_OPCODE
;
12939 vex
.prefix
= REPE_PREFIX_OPCODE
;
12942 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12949 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12951 /* There is no MODRM byte for VEX 77. */
12952 if (vindex
!= 0x77)
12954 FETCH_DATA (info
, codep
+ 1);
12955 modrm
.mod
= (*codep
>> 6) & 3;
12956 modrm
.reg
= (*codep
>> 3) & 7;
12957 modrm
.rm
= *codep
& 7;
12961 case USE_VEX_W_TABLE
:
12965 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12968 case USE_EVEX_TABLE
:
12969 two_source_ops
= 0;
12972 FETCH_DATA (info
, codep
+ 4);
12973 /* All bits in the REX prefix are ignored. */
12975 /* The first byte after 0x62. */
12976 rex
= ~(*codep
>> 5) & 0x7;
12977 vex
.r
= *codep
& 0x10;
12978 switch ((*codep
& 0xf))
12981 return &bad_opcode
;
12983 vex_table_index
= EVEX_0F
;
12986 vex_table_index
= EVEX_0F38
;
12989 vex_table_index
= EVEX_0F3A
;
12993 /* The second byte after 0x62. */
12995 vex
.w
= *codep
& 0x80;
12996 if (vex
.w
&& address_mode
== mode_64bit
)
12999 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13002 if (!(*codep
& 0x4))
13003 return &bad_opcode
;
13005 switch ((*codep
& 0x3))
13011 vex
.prefix
= DATA_PREFIX_OPCODE
;
13014 vex
.prefix
= REPE_PREFIX_OPCODE
;
13017 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13021 /* The third byte after 0x62. */
13024 /* Remember the static rounding bits. */
13025 vex
.ll
= (*codep
>> 5) & 3;
13026 vex
.b
= (*codep
& 0x10) != 0;
13028 vex
.v
= *codep
& 0x8;
13029 vex
.mask_register_specifier
= *codep
& 0x7;
13030 vex
.zeroing
= *codep
& 0x80;
13032 if (address_mode
!= mode_64bit
)
13034 /* In 16/32-bit mode silently ignore following bits. */
13044 dp
= &evex_table
[vex_table_index
][vindex
];
13046 FETCH_DATA (info
, codep
+ 1);
13047 modrm
.mod
= (*codep
>> 6) & 3;
13048 modrm
.reg
= (*codep
>> 3) & 7;
13049 modrm
.rm
= *codep
& 7;
13051 /* Set vector length. */
13052 if (modrm
.mod
== 3 && vex
.b
)
13068 return &bad_opcode
;
13081 if (dp
->name
!= NULL
)
13084 return get_valid_dis386 (dp
, info
);
13088 get_sib (disassemble_info
*info
, int sizeflag
)
13090 /* If modrm.mod == 3, operand must be register. */
13092 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13096 FETCH_DATA (info
, codep
+ 2);
13097 sib
.index
= (codep
[1] >> 3) & 7;
13098 sib
.scale
= (codep
[1] >> 6) & 3;
13099 sib
.base
= codep
[1] & 7;
13104 print_insn (bfd_vma pc
, disassemble_info
*info
)
13106 const struct dis386
*dp
;
13108 char *op_txt
[MAX_OPERANDS
];
13110 int sizeflag
, orig_sizeflag
;
13112 struct dis_private priv
;
13115 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13116 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
13117 address_mode
= mode_32bit
;
13118 else if (info
->mach
== bfd_mach_i386_i8086
)
13120 address_mode
= mode_16bit
;
13121 priv
.orig_sizeflag
= 0;
13124 address_mode
= mode_64bit
;
13126 if (intel_syntax
== (char) -1)
13127 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
13129 for (p
= info
->disassembler_options
; p
!= NULL
; )
13131 if (CONST_STRNEQ (p
, "amd64"))
13133 else if (CONST_STRNEQ (p
, "intel64"))
13135 else if (CONST_STRNEQ (p
, "x86-64"))
13137 address_mode
= mode_64bit
;
13138 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13140 else if (CONST_STRNEQ (p
, "i386"))
13142 address_mode
= mode_32bit
;
13143 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13145 else if (CONST_STRNEQ (p
, "i8086"))
13147 address_mode
= mode_16bit
;
13148 priv
.orig_sizeflag
= 0;
13150 else if (CONST_STRNEQ (p
, "intel"))
13153 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
13154 intel_mnemonic
= 1;
13156 else if (CONST_STRNEQ (p
, "att"))
13159 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
13160 intel_mnemonic
= 0;
13162 else if (CONST_STRNEQ (p
, "addr"))
13164 if (address_mode
== mode_64bit
)
13166 if (p
[4] == '3' && p
[5] == '2')
13167 priv
.orig_sizeflag
&= ~AFLAG
;
13168 else if (p
[4] == '6' && p
[5] == '4')
13169 priv
.orig_sizeflag
|= AFLAG
;
13173 if (p
[4] == '1' && p
[5] == '6')
13174 priv
.orig_sizeflag
&= ~AFLAG
;
13175 else if (p
[4] == '3' && p
[5] == '2')
13176 priv
.orig_sizeflag
|= AFLAG
;
13179 else if (CONST_STRNEQ (p
, "data"))
13181 if (p
[4] == '1' && p
[5] == '6')
13182 priv
.orig_sizeflag
&= ~DFLAG
;
13183 else if (p
[4] == '3' && p
[5] == '2')
13184 priv
.orig_sizeflag
|= DFLAG
;
13186 else if (CONST_STRNEQ (p
, "suffix"))
13187 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
13189 p
= strchr (p
, ',');
13194 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
13196 (*info
->fprintf_func
) (info
->stream
,
13197 _("64-bit address is disabled"));
13203 names64
= intel_names64
;
13204 names32
= intel_names32
;
13205 names16
= intel_names16
;
13206 names8
= intel_names8
;
13207 names8rex
= intel_names8rex
;
13208 names_seg
= intel_names_seg
;
13209 names_mm
= intel_names_mm
;
13210 names_bnd
= intel_names_bnd
;
13211 names_xmm
= intel_names_xmm
;
13212 names_ymm
= intel_names_ymm
;
13213 names_zmm
= intel_names_zmm
;
13214 index64
= intel_index64
;
13215 index32
= intel_index32
;
13216 names_mask
= intel_names_mask
;
13217 index16
= intel_index16
;
13220 separator_char
= '+';
13225 names64
= att_names64
;
13226 names32
= att_names32
;
13227 names16
= att_names16
;
13228 names8
= att_names8
;
13229 names8rex
= att_names8rex
;
13230 names_seg
= att_names_seg
;
13231 names_mm
= att_names_mm
;
13232 names_bnd
= att_names_bnd
;
13233 names_xmm
= att_names_xmm
;
13234 names_ymm
= att_names_ymm
;
13235 names_zmm
= att_names_zmm
;
13236 index64
= att_index64
;
13237 index32
= att_index32
;
13238 names_mask
= att_names_mask
;
13239 index16
= att_index16
;
13242 separator_char
= ',';
13246 /* The output looks better if we put 7 bytes on a line, since that
13247 puts most long word instructions on a single line. Use 8 bytes
13249 if ((info
->mach
& bfd_mach_l1om
) != 0)
13250 info
->bytes_per_line
= 8;
13252 info
->bytes_per_line
= 7;
13254 info
->private_data
= &priv
;
13255 priv
.max_fetched
= priv
.the_buffer
;
13256 priv
.insn_start
= pc
;
13259 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13267 start_codep
= priv
.the_buffer
;
13268 codep
= priv
.the_buffer
;
13270 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
13274 /* Getting here means we tried for data but didn't get it. That
13275 means we have an incomplete instruction of some sort. Just
13276 print the first byte as a prefix or a .byte pseudo-op. */
13277 if (codep
> priv
.the_buffer
)
13279 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
13281 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
13284 /* Just print the first byte as a .byte instruction. */
13285 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
13286 (unsigned int) priv
.the_buffer
[0]);
13296 sizeflag
= priv
.orig_sizeflag
;
13298 if (!ckprefix () || rex_used
)
13300 /* Too many prefixes or unused REX prefixes. */
13302 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13304 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13306 prefix_name (all_prefixes
[i
], sizeflag
));
13310 insn_codep
= codep
;
13312 FETCH_DATA (info
, codep
+ 1);
13313 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13315 if (((prefixes
& PREFIX_FWAIT
)
13316 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13318 /* Handle prefixes before fwait. */
13319 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13321 (*info
->fprintf_func
) (info
->stream
, "%s ",
13322 prefix_name (all_prefixes
[i
], sizeflag
));
13323 (*info
->fprintf_func
) (info
->stream
, "fwait");
13327 if (*codep
== 0x0f)
13329 unsigned char threebyte
;
13332 FETCH_DATA (info
, codep
+ 1);
13333 threebyte
= *codep
;
13334 dp
= &dis386_twobyte
[threebyte
];
13335 need_modrm
= twobyte_has_modrm
[*codep
];
13340 dp
= &dis386
[*codep
];
13341 need_modrm
= onebyte_has_modrm
[*codep
];
13345 /* Save sizeflag for printing the extra prefixes later before updating
13346 it for mnemonic and operand processing. The prefix names depend
13347 only on the address mode. */
13348 orig_sizeflag
= sizeflag
;
13349 if (prefixes
& PREFIX_ADDR
)
13351 if ((prefixes
& PREFIX_DATA
))
13357 FETCH_DATA (info
, codep
+ 1);
13358 modrm
.mod
= (*codep
>> 6) & 3;
13359 modrm
.reg
= (*codep
>> 3) & 7;
13360 modrm
.rm
= *codep
& 7;
13368 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13370 get_sib (info
, sizeflag
);
13371 dofloat (sizeflag
);
13375 dp
= get_valid_dis386 (dp
, info
);
13376 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13378 get_sib (info
, sizeflag
);
13379 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13382 op_ad
= MAX_OPERANDS
- 1 - i
;
13384 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13385 /* For EVEX instruction after the last operand masking
13386 should be printed. */
13387 if (i
== 0 && vex
.evex
)
13389 /* Don't print {%k0}. */
13390 if (vex
.mask_register_specifier
)
13393 oappend (names_mask
[vex
.mask_register_specifier
]);
13403 /* Check if the REX prefix is used. */
13404 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13405 all_prefixes
[last_rex_prefix
] = 0;
13407 /* Check if the SEG prefix is used. */
13408 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13409 | PREFIX_FS
| PREFIX_GS
)) != 0
13410 && (used_prefixes
& active_seg_prefix
) != 0)
13411 all_prefixes
[last_seg_prefix
] = 0;
13413 /* Check if the ADDR prefix is used. */
13414 if ((prefixes
& PREFIX_ADDR
) != 0
13415 && (used_prefixes
& PREFIX_ADDR
) != 0)
13416 all_prefixes
[last_addr_prefix
] = 0;
13418 /* Check if the DATA prefix is used. */
13419 if ((prefixes
& PREFIX_DATA
) != 0
13420 && (used_prefixes
& PREFIX_DATA
) != 0)
13421 all_prefixes
[last_data_prefix
] = 0;
13423 /* Print the extra prefixes. */
13425 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13426 if (all_prefixes
[i
])
13429 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13432 prefix_length
+= strlen (name
) + 1;
13433 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13436 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13437 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13438 used by putop and MMX/SSE operand and may be overriden by the
13439 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13441 if (dp
->prefix_requirement
== PREFIX_OPCODE
13442 && dp
!= &bad_opcode
13444 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13446 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13448 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13450 && (used_prefixes
& PREFIX_DATA
) == 0))))
13452 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13453 return end_codep
- priv
.the_buffer
;
13456 /* Check maximum code length. */
13457 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13459 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13460 return MAX_CODE_LENGTH
;
13463 obufp
= mnemonicendp
;
13464 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13467 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13469 /* The enter and bound instructions are printed with operands in the same
13470 order as the intel book; everything else is printed in reverse order. */
13471 if (intel_syntax
|| two_source_ops
)
13475 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13476 op_txt
[i
] = op_out
[i
];
13478 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
13479 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
13481 op_txt
[2] = op_out
[3];
13482 op_txt
[3] = op_out
[2];
13485 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13487 op_ad
= op_index
[i
];
13488 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13489 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13490 riprel
= op_riprel
[i
];
13491 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13492 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13497 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13498 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13502 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13506 (*info
->fprintf_func
) (info
->stream
, ",");
13507 if (op_index
[i
] != -1 && !op_riprel
[i
])
13508 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13510 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13514 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13515 if (op_index
[i
] != -1 && op_riprel
[i
])
13517 (*info
->fprintf_func
) (info
->stream
, " # ");
13518 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
13519 + op_address
[op_index
[i
]]), info
);
13522 return codep
- priv
.the_buffer
;
13525 static const char *float_mem
[] = {
13600 static const unsigned char float_mem_mode
[] = {
13675 #define ST { OP_ST, 0 }
13676 #define STi { OP_STi, 0 }
13678 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13679 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13680 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13681 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13682 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13683 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13684 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13685 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13686 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13688 static const struct dis386 float_reg
[][8] = {
13691 { "fadd", { ST
, STi
}, 0 },
13692 { "fmul", { ST
, STi
}, 0 },
13693 { "fcom", { STi
}, 0 },
13694 { "fcomp", { STi
}, 0 },
13695 { "fsub", { ST
, STi
}, 0 },
13696 { "fsubr", { ST
, STi
}, 0 },
13697 { "fdiv", { ST
, STi
}, 0 },
13698 { "fdivr", { ST
, STi
}, 0 },
13702 { "fld", { STi
}, 0 },
13703 { "fxch", { STi
}, 0 },
13713 { "fcmovb", { ST
, STi
}, 0 },
13714 { "fcmove", { ST
, STi
}, 0 },
13715 { "fcmovbe",{ ST
, STi
}, 0 },
13716 { "fcmovu", { ST
, STi
}, 0 },
13724 { "fcmovnb",{ ST
, STi
}, 0 },
13725 { "fcmovne",{ ST
, STi
}, 0 },
13726 { "fcmovnbe",{ ST
, STi
}, 0 },
13727 { "fcmovnu",{ ST
, STi
}, 0 },
13729 { "fucomi", { ST
, STi
}, 0 },
13730 { "fcomi", { ST
, STi
}, 0 },
13735 { "fadd", { STi
, ST
}, 0 },
13736 { "fmul", { STi
, ST
}, 0 },
13739 { "fsub!M", { STi
, ST
}, 0 },
13740 { "fsubM", { STi
, ST
}, 0 },
13741 { "fdiv!M", { STi
, ST
}, 0 },
13742 { "fdivM", { STi
, ST
}, 0 },
13746 { "ffree", { STi
}, 0 },
13748 { "fst", { STi
}, 0 },
13749 { "fstp", { STi
}, 0 },
13750 { "fucom", { STi
}, 0 },
13751 { "fucomp", { STi
}, 0 },
13757 { "faddp", { STi
, ST
}, 0 },
13758 { "fmulp", { STi
, ST
}, 0 },
13761 { "fsub!Mp", { STi
, ST
}, 0 },
13762 { "fsubMp", { STi
, ST
}, 0 },
13763 { "fdiv!Mp", { STi
, ST
}, 0 },
13764 { "fdivMp", { STi
, ST
}, 0 },
13768 { "ffreep", { STi
}, 0 },
13773 { "fucomip", { ST
, STi
}, 0 },
13774 { "fcomip", { ST
, STi
}, 0 },
13779 static char *fgrps
[][8] = {
13782 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13787 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13792 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13797 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13802 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13807 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13812 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13817 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13818 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13823 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13828 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13833 swap_operand (void)
13835 mnemonicendp
[0] = '.';
13836 mnemonicendp
[1] = 's';
13841 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13842 int sizeflag ATTRIBUTE_UNUSED
)
13844 /* Skip mod/rm byte. */
13850 dofloat (int sizeflag
)
13852 const struct dis386
*dp
;
13853 unsigned char floatop
;
13855 floatop
= codep
[-1];
13857 if (modrm
.mod
!= 3)
13859 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13861 putop (float_mem
[fp_indx
], sizeflag
);
13864 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13867 /* Skip mod/rm byte. */
13871 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13872 if (dp
->name
== NULL
)
13874 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13876 /* Instruction fnstsw is only one with strange arg. */
13877 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13878 strcpy (op_out
[0], names16
[0]);
13882 putop (dp
->name
, sizeflag
);
13887 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13892 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13896 /* Like oappend (below), but S is a string starting with '%'.
13897 In Intel syntax, the '%' is elided. */
13899 oappend_maybe_intel (const char *s
)
13901 oappend (s
+ intel_syntax
);
13905 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13907 oappend_maybe_intel ("%st");
13911 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13913 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13914 oappend_maybe_intel (scratchbuf
);
13917 /* Capital letters in template are macros. */
13919 putop (const char *in_template
, int sizeflag
)
13924 unsigned int l
= 0, len
= 1;
13927 #define SAVE_LAST(c) \
13928 if (l < len && l < sizeof (last)) \
13933 for (p
= in_template
; *p
; p
++)
13949 while (*++p
!= '|')
13950 if (*p
== '}' || *p
== '\0')
13953 /* Fall through. */
13958 while (*++p
!= '}')
13969 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13973 if (l
== 0 && len
== 1)
13978 if (sizeflag
& SUFFIX_ALWAYS
)
13991 if (address_mode
== mode_64bit
13992 && !(prefixes
& PREFIX_ADDR
))
14003 if (intel_syntax
&& !alt
)
14005 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14007 if (sizeflag
& DFLAG
)
14008 *obufp
++ = intel_syntax
? 'd' : 'l';
14010 *obufp
++ = intel_syntax
? 'w' : 's';
14011 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14015 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14018 if (modrm
.mod
== 3)
14024 if (sizeflag
& DFLAG
)
14025 *obufp
++ = intel_syntax
? 'd' : 'l';
14028 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14034 case 'E': /* For jcxz/jecxz */
14035 if (address_mode
== mode_64bit
)
14037 if (sizeflag
& AFLAG
)
14043 if (sizeflag
& AFLAG
)
14045 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14050 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
14052 if (sizeflag
& AFLAG
)
14053 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
14055 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
14056 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14060 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
14062 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14066 if (!(rex
& REX_W
))
14067 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14072 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
14073 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
14075 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
14078 if (prefixes
& PREFIX_DS
)
14097 if (l
!= 0 || len
!= 1)
14099 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14104 if (!need_vex
|| !vex
.evex
)
14107 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14109 switch (vex
.length
)
14127 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
14132 /* Fall through. */
14135 if (l
!= 0 || len
!= 1)
14143 if (sizeflag
& SUFFIX_ALWAYS
)
14147 if (intel_mnemonic
!= cond
)
14151 if ((prefixes
& PREFIX_FWAIT
) == 0)
14154 used_prefixes
|= PREFIX_FWAIT
;
14160 else if (intel_syntax
&& (sizeflag
& DFLAG
))
14164 if (!(rex
& REX_W
))
14165 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14169 && address_mode
== mode_64bit
14170 && isa64
== intel64
)
14175 /* Fall through. */
14178 && address_mode
== mode_64bit
14179 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14184 /* Fall through. */
14187 if (l
== 0 && len
== 1)
14192 if ((rex
& REX_W
) == 0
14193 && (prefixes
& PREFIX_DATA
))
14195 if ((sizeflag
& DFLAG
) == 0)
14197 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14201 if ((prefixes
& PREFIX_DATA
)
14203 || (sizeflag
& SUFFIX_ALWAYS
))
14210 if (sizeflag
& DFLAG
)
14214 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14220 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14226 if ((prefixes
& PREFIX_DATA
)
14228 || (sizeflag
& SUFFIX_ALWAYS
))
14235 if (sizeflag
& DFLAG
)
14236 *obufp
++ = intel_syntax
? 'd' : 'l';
14239 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14247 if (address_mode
== mode_64bit
14248 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14250 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14254 /* Fall through. */
14257 if (l
== 0 && len
== 1)
14260 if (intel_syntax
&& !alt
)
14263 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14269 if (sizeflag
& DFLAG
)
14270 *obufp
++ = intel_syntax
? 'd' : 'l';
14273 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14279 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14285 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14300 else if (sizeflag
& DFLAG
)
14309 if (intel_syntax
&& !p
[1]
14310 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
14312 if (!(rex
& REX_W
))
14313 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14316 if (l
== 0 && len
== 1)
14320 if (address_mode
== mode_64bit
14321 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14323 if (sizeflag
& SUFFIX_ALWAYS
)
14345 /* Fall through. */
14348 if (l
== 0 && len
== 1)
14353 if (sizeflag
& SUFFIX_ALWAYS
)
14359 if (sizeflag
& DFLAG
)
14363 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14377 if (address_mode
== mode_64bit
14378 && !(prefixes
& PREFIX_ADDR
))
14389 if (l
!= 0 || len
!= 1)
14394 if (need_vex
&& vex
.prefix
)
14396 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14403 if (prefixes
& PREFIX_DATA
)
14407 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14411 if (l
== 0 && len
== 1)
14413 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14424 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14432 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14434 switch (vex
.length
)
14450 if (l
== 0 && len
== 1)
14452 /* operand size flag for cwtl, cbtw */
14461 else if (sizeflag
& DFLAG
)
14465 if (!(rex
& REX_W
))
14466 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14473 && last
[0] != 'L'))
14480 if (last
[0] == 'X')
14481 *obufp
++ = vex
.w
? 'd': 's';
14483 *obufp
++ = vex
.w
? 'q': 'd';
14489 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14491 if (sizeflag
& DFLAG
)
14495 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14501 if (address_mode
== mode_64bit
14502 && (isa64
== intel64
14503 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
14505 else if ((prefixes
& PREFIX_DATA
))
14507 if (!(sizeflag
& DFLAG
))
14509 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14516 mnemonicendp
= obufp
;
14521 oappend (const char *s
)
14523 obufp
= stpcpy (obufp
, s
);
14529 /* Only print the active segment register. */
14530 if (!active_seg_prefix
)
14533 used_prefixes
|= active_seg_prefix
;
14534 switch (active_seg_prefix
)
14537 oappend_maybe_intel ("%cs:");
14540 oappend_maybe_intel ("%ds:");
14543 oappend_maybe_intel ("%ss:");
14546 oappend_maybe_intel ("%es:");
14549 oappend_maybe_intel ("%fs:");
14552 oappend_maybe_intel ("%gs:");
14560 OP_indirE (int bytemode
, int sizeflag
)
14564 OP_E (bytemode
, sizeflag
);
14568 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14570 if (address_mode
== mode_64bit
)
14578 sprintf_vma (tmp
, disp
);
14579 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14580 strcpy (buf
+ 2, tmp
+ i
);
14584 bfd_signed_vma v
= disp
;
14591 /* Check for possible overflow on 0x8000000000000000. */
14594 strcpy (buf
, "9223372036854775808");
14608 tmp
[28 - i
] = (v
% 10) + '0';
14612 strcpy (buf
, tmp
+ 29 - i
);
14618 sprintf (buf
, "0x%x", (unsigned int) disp
);
14620 sprintf (buf
, "%d", (int) disp
);
14624 /* Put DISP in BUF as signed hex number. */
14627 print_displacement (char *buf
, bfd_vma disp
)
14629 bfd_signed_vma val
= disp
;
14638 /* Check for possible overflow. */
14641 switch (address_mode
)
14644 strcpy (buf
+ j
, "0x8000000000000000");
14647 strcpy (buf
+ j
, "0x80000000");
14650 strcpy (buf
+ j
, "0x8000");
14660 sprintf_vma (tmp
, (bfd_vma
) val
);
14661 for (i
= 0; tmp
[i
] == '0'; i
++)
14663 if (tmp
[i
] == '\0')
14665 strcpy (buf
+ j
, tmp
+ i
);
14669 intel_operand_size (int bytemode
, int sizeflag
)
14673 && (bytemode
== x_mode
14674 || bytemode
== evex_half_bcst_xmmq_mode
))
14677 oappend ("QWORD PTR ");
14679 oappend ("DWORD PTR ");
14688 oappend ("BYTE PTR ");
14693 oappend ("WORD PTR ");
14696 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14698 oappend ("QWORD PTR ");
14701 /* Fall through. */
14703 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14705 oappend ("QWORD PTR ");
14708 /* Fall through. */
14714 oappend ("QWORD PTR ");
14717 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14718 oappend ("DWORD PTR ");
14720 oappend ("WORD PTR ");
14721 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14725 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14727 oappend ("WORD PTR ");
14728 if (!(rex
& REX_W
))
14729 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14732 if (sizeflag
& DFLAG
)
14733 oappend ("QWORD PTR ");
14735 oappend ("DWORD PTR ");
14736 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14739 case d_scalar_mode
:
14740 case d_scalar_swap_mode
:
14743 oappend ("DWORD PTR ");
14746 case q_scalar_mode
:
14747 case q_scalar_swap_mode
:
14749 oappend ("QWORD PTR ");
14752 if (address_mode
== mode_64bit
)
14753 oappend ("QWORD PTR ");
14755 oappend ("DWORD PTR ");
14758 if (sizeflag
& DFLAG
)
14759 oappend ("FWORD PTR ");
14761 oappend ("DWORD PTR ");
14762 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14765 oappend ("TBYTE PTR ");
14769 case evex_x_gscat_mode
:
14770 case evex_x_nobcst_mode
:
14771 case b_scalar_mode
:
14772 case w_scalar_mode
:
14775 switch (vex
.length
)
14778 oappend ("XMMWORD PTR ");
14781 oappend ("YMMWORD PTR ");
14784 oappend ("ZMMWORD PTR ");
14791 oappend ("XMMWORD PTR ");
14794 oappend ("XMMWORD PTR ");
14797 oappend ("YMMWORD PTR ");
14800 case evex_half_bcst_xmmq_mode
:
14804 switch (vex
.length
)
14807 oappend ("QWORD PTR ");
14810 oappend ("XMMWORD PTR ");
14813 oappend ("YMMWORD PTR ");
14823 switch (vex
.length
)
14828 oappend ("BYTE PTR ");
14838 switch (vex
.length
)
14843 oappend ("WORD PTR ");
14853 switch (vex
.length
)
14858 oappend ("DWORD PTR ");
14868 switch (vex
.length
)
14873 oappend ("QWORD PTR ");
14883 switch (vex
.length
)
14886 oappend ("WORD PTR ");
14889 oappend ("DWORD PTR ");
14892 oappend ("QWORD PTR ");
14902 switch (vex
.length
)
14905 oappend ("DWORD PTR ");
14908 oappend ("QWORD PTR ");
14911 oappend ("XMMWORD PTR ");
14921 switch (vex
.length
)
14924 oappend ("QWORD PTR ");
14927 oappend ("YMMWORD PTR ");
14930 oappend ("ZMMWORD PTR ");
14940 switch (vex
.length
)
14944 oappend ("XMMWORD PTR ");
14951 oappend ("OWORD PTR ");
14954 case vex_w_dq_mode
:
14955 case vex_scalar_w_dq_mode
:
14960 oappend ("QWORD PTR ");
14962 oappend ("DWORD PTR ");
14964 case vex_vsib_d_w_dq_mode
:
14965 case vex_vsib_q_w_dq_mode
:
14972 oappend ("QWORD PTR ");
14974 oappend ("DWORD PTR ");
14978 switch (vex
.length
)
14981 oappend ("XMMWORD PTR ");
14984 oappend ("YMMWORD PTR ");
14987 oappend ("ZMMWORD PTR ");
14994 case vex_vsib_q_w_d_mode
:
14995 case vex_vsib_d_w_d_mode
:
14996 if (!need_vex
|| !vex
.evex
)
14999 switch (vex
.length
)
15002 oappend ("QWORD PTR ");
15005 oappend ("XMMWORD PTR ");
15008 oappend ("YMMWORD PTR ");
15016 if (!need_vex
|| vex
.length
!= 128)
15019 oappend ("DWORD PTR ");
15021 oappend ("BYTE PTR ");
15027 oappend ("QWORD PTR ");
15029 oappend ("WORD PTR ");
15038 OP_E_register (int bytemode
, int sizeflag
)
15040 int reg
= modrm
.rm
;
15041 const char **names
;
15047 if ((sizeflag
& SUFFIX_ALWAYS
)
15048 && (bytemode
== b_swap_mode
15049 || bytemode
== v_swap_mode
))
15075 names
= address_mode
== mode_64bit
? names64
: names32
;
15086 if (address_mode
== mode_64bit
&& isa64
== intel64
)
15091 /* Fall through. */
15093 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15099 /* Fall through. */
15111 if ((sizeflag
& DFLAG
)
15112 || (bytemode
!= v_mode
15113 && bytemode
!= v_swap_mode
))
15117 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15127 names
= names_mask
;
15132 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15135 oappend (names
[reg
]);
15139 OP_E_memory (int bytemode
, int sizeflag
)
15142 int add
= (rex
& REX_B
) ? 8 : 0;
15148 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15150 && bytemode
!= x_mode
15151 && bytemode
!= xmmq_mode
15152 && bytemode
!= evex_half_bcst_xmmq_mode
)
15167 case vex_vsib_d_w_dq_mode
:
15168 case vex_vsib_d_w_d_mode
:
15169 case vex_vsib_q_w_dq_mode
:
15170 case vex_vsib_q_w_d_mode
:
15171 case evex_x_gscat_mode
:
15173 shift
= vex
.w
? 3 : 2;
15176 case evex_half_bcst_xmmq_mode
:
15180 shift
= vex
.w
? 3 : 2;
15183 /* Fall through. */
15187 case evex_x_nobcst_mode
:
15189 switch (vex
.length
)
15212 case q_scalar_mode
:
15214 case q_scalar_swap_mode
:
15220 case d_scalar_mode
:
15222 case d_scalar_swap_mode
:
15225 case w_scalar_mode
:
15229 case b_scalar_mode
:
15236 /* Make necessary corrections to shift for modes that need it.
15237 For these modes we currently have shift 4, 5 or 6 depending on
15238 vex.length (it corresponds to xmmword, ymmword or zmmword
15239 operand). We might want to make it 3, 4 or 5 (e.g. for
15240 xmmq_mode). In case of broadcast enabled the corrections
15241 aren't needed, as element size is always 32 or 64 bits. */
15243 && (bytemode
== xmmq_mode
15244 || bytemode
== evex_half_bcst_xmmq_mode
))
15246 else if (bytemode
== xmmqd_mode
)
15248 else if (bytemode
== xmmdw_mode
)
15250 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
15258 intel_operand_size (bytemode
, sizeflag
);
15261 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15263 /* 32/64 bit address mode */
15272 int addr32flag
= !((sizeflag
& AFLAG
)
15273 || bytemode
== v_bnd_mode
15274 || bytemode
== bnd_mode
);
15275 const char **indexes64
= names64
;
15276 const char **indexes32
= names32
;
15286 vindex
= sib
.index
;
15292 case vex_vsib_d_w_dq_mode
:
15293 case vex_vsib_d_w_d_mode
:
15294 case vex_vsib_q_w_dq_mode
:
15295 case vex_vsib_q_w_d_mode
:
15305 switch (vex
.length
)
15308 indexes64
= indexes32
= names_xmm
;
15312 || bytemode
== vex_vsib_q_w_dq_mode
15313 || bytemode
== vex_vsib_q_w_d_mode
)
15314 indexes64
= indexes32
= names_ymm
;
15316 indexes64
= indexes32
= names_xmm
;
15320 || bytemode
== vex_vsib_q_w_dq_mode
15321 || bytemode
== vex_vsib_q_w_d_mode
)
15322 indexes64
= indexes32
= names_zmm
;
15324 indexes64
= indexes32
= names_ymm
;
15331 haveindex
= vindex
!= 4;
15338 rbase
= base
+ add
;
15346 if (address_mode
== mode_64bit
&& !havesib
)
15352 FETCH_DATA (the_info
, codep
+ 1);
15354 if ((disp
& 0x80) != 0)
15356 if (vex
.evex
&& shift
> 0)
15364 /* In 32bit mode, we need index register to tell [offset] from
15365 [eiz*1 + offset]. */
15366 needindex
= (havesib
15369 && address_mode
== mode_32bit
);
15370 havedisp
= (havebase
15372 || (havesib
&& (haveindex
|| scale
!= 0)));
15375 if (modrm
.mod
!= 0 || base
== 5)
15377 if (havedisp
|| riprel
)
15378 print_displacement (scratchbuf
, disp
);
15380 print_operand_value (scratchbuf
, 1, disp
);
15381 oappend (scratchbuf
);
15385 oappend (!addr32flag
? "(%rip)" : "(%eip)");
15389 if ((havebase
|| haveindex
|| riprel
)
15390 && (bytemode
!= v_bnd_mode
)
15391 && (bytemode
!= bnd_mode
))
15392 used_prefixes
|= PREFIX_ADDR
;
15394 if (havedisp
|| (intel_syntax
&& riprel
))
15396 *obufp
++ = open_char
;
15397 if (intel_syntax
&& riprel
)
15400 oappend (!addr32flag
? "rip" : "eip");
15404 oappend (address_mode
== mode_64bit
&& !addr32flag
15405 ? names64
[rbase
] : names32
[rbase
]);
15408 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15409 print index to tell base + index from base. */
15413 || (havebase
&& base
!= ESP_REG_NUM
))
15415 if (!intel_syntax
|| havebase
)
15417 *obufp
++ = separator_char
;
15421 oappend (address_mode
== mode_64bit
&& !addr32flag
15422 ? indexes64
[vindex
] : indexes32
[vindex
]);
15424 oappend (address_mode
== mode_64bit
&& !addr32flag
15425 ? index64
: index32
);
15427 *obufp
++ = scale_char
;
15429 sprintf (scratchbuf
, "%d", 1 << scale
);
15430 oappend (scratchbuf
);
15434 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15436 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15441 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15445 disp
= - (bfd_signed_vma
) disp
;
15449 print_displacement (scratchbuf
, disp
);
15451 print_operand_value (scratchbuf
, 1, disp
);
15452 oappend (scratchbuf
);
15455 *obufp
++ = close_char
;
15458 else if (intel_syntax
)
15460 if (modrm
.mod
!= 0 || base
== 5)
15462 if (!active_seg_prefix
)
15464 oappend (names_seg
[ds_reg
- es_reg
]);
15467 print_operand_value (scratchbuf
, 1, disp
);
15468 oappend (scratchbuf
);
15474 /* 16 bit address mode */
15475 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15482 if ((disp
& 0x8000) != 0)
15487 FETCH_DATA (the_info
, codep
+ 1);
15489 if ((disp
& 0x80) != 0)
15491 if (vex
.evex
&& shift
> 0)
15496 if ((disp
& 0x8000) != 0)
15502 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15504 print_displacement (scratchbuf
, disp
);
15505 oappend (scratchbuf
);
15508 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15510 *obufp
++ = open_char
;
15512 oappend (index16
[modrm
.rm
]);
15514 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15516 if ((bfd_signed_vma
) disp
>= 0)
15521 else if (modrm
.mod
!= 1)
15525 disp
= - (bfd_signed_vma
) disp
;
15528 print_displacement (scratchbuf
, disp
);
15529 oappend (scratchbuf
);
15532 *obufp
++ = close_char
;
15535 else if (intel_syntax
)
15537 if (!active_seg_prefix
)
15539 oappend (names_seg
[ds_reg
- es_reg
]);
15542 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15543 oappend (scratchbuf
);
15546 if (vex
.evex
&& vex
.b
15547 && (bytemode
== x_mode
15548 || bytemode
== xmmq_mode
15549 || bytemode
== evex_half_bcst_xmmq_mode
))
15552 || bytemode
== xmmq_mode
15553 || bytemode
== evex_half_bcst_xmmq_mode
)
15555 switch (vex
.length
)
15558 oappend ("{1to2}");
15561 oappend ("{1to4}");
15564 oappend ("{1to8}");
15572 switch (vex
.length
)
15575 oappend ("{1to4}");
15578 oappend ("{1to8}");
15581 oappend ("{1to16}");
15591 OP_E (int bytemode
, int sizeflag
)
15593 /* Skip mod/rm byte. */
15597 if (modrm
.mod
== 3)
15598 OP_E_register (bytemode
, sizeflag
);
15600 OP_E_memory (bytemode
, sizeflag
);
15604 OP_G (int bytemode
, int sizeflag
)
15615 oappend (names8rex
[modrm
.reg
+ add
]);
15617 oappend (names8
[modrm
.reg
+ add
]);
15620 oappend (names16
[modrm
.reg
+ add
]);
15625 oappend (names32
[modrm
.reg
+ add
]);
15628 oappend (names64
[modrm
.reg
+ add
]);
15631 if (modrm
.reg
> 0x3)
15636 oappend (names_bnd
[modrm
.reg
]);
15645 oappend (names64
[modrm
.reg
+ add
]);
15648 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15649 oappend (names32
[modrm
.reg
+ add
]);
15651 oappend (names16
[modrm
.reg
+ add
]);
15652 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15656 if (address_mode
== mode_64bit
)
15657 oappend (names64
[modrm
.reg
+ add
]);
15659 oappend (names32
[modrm
.reg
+ add
]);
15663 if ((modrm
.reg
+ add
) > 0x7)
15668 oappend (names_mask
[modrm
.reg
+ add
]);
15671 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15684 FETCH_DATA (the_info
, codep
+ 8);
15685 a
= *codep
++ & 0xff;
15686 a
|= (*codep
++ & 0xff) << 8;
15687 a
|= (*codep
++ & 0xff) << 16;
15688 a
|= (*codep
++ & 0xffu
) << 24;
15689 b
= *codep
++ & 0xff;
15690 b
|= (*codep
++ & 0xff) << 8;
15691 b
|= (*codep
++ & 0xff) << 16;
15692 b
|= (*codep
++ & 0xffu
) << 24;
15693 x
= a
+ ((bfd_vma
) b
<< 32);
15701 static bfd_signed_vma
15704 bfd_signed_vma x
= 0;
15706 FETCH_DATA (the_info
, codep
+ 4);
15707 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15708 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15709 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15710 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15714 static bfd_signed_vma
15717 bfd_signed_vma x
= 0;
15719 FETCH_DATA (the_info
, codep
+ 4);
15720 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15721 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15722 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15723 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15725 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15735 FETCH_DATA (the_info
, codep
+ 2);
15736 x
= *codep
++ & 0xff;
15737 x
|= (*codep
++ & 0xff) << 8;
15742 set_op (bfd_vma op
, int riprel
)
15744 op_index
[op_ad
] = op_ad
;
15745 if (address_mode
== mode_64bit
)
15747 op_address
[op_ad
] = op
;
15748 op_riprel
[op_ad
] = riprel
;
15752 /* Mask to get a 32-bit address. */
15753 op_address
[op_ad
] = op
& 0xffffffff;
15754 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15759 OP_REG (int code
, int sizeflag
)
15766 case es_reg
: case ss_reg
: case cs_reg
:
15767 case ds_reg
: case fs_reg
: case gs_reg
:
15768 oappend (names_seg
[code
- es_reg
]);
15780 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15781 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15782 s
= names16
[code
- ax_reg
+ add
];
15784 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15785 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15788 s
= names8rex
[code
- al_reg
+ add
];
15790 s
= names8
[code
- al_reg
];
15792 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15793 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15794 if (address_mode
== mode_64bit
15795 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15797 s
= names64
[code
- rAX_reg
+ add
];
15800 code
+= eAX_reg
- rAX_reg
;
15801 /* Fall through. */
15802 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15803 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15806 s
= names64
[code
- eAX_reg
+ add
];
15809 if (sizeflag
& DFLAG
)
15810 s
= names32
[code
- eAX_reg
+ add
];
15812 s
= names16
[code
- eAX_reg
+ add
];
15813 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15817 s
= INTERNAL_DISASSEMBLER_ERROR
;
15824 OP_IMREG (int code
, int sizeflag
)
15836 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15837 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15838 s
= names16
[code
- ax_reg
];
15840 case es_reg
: case ss_reg
: case cs_reg
:
15841 case ds_reg
: case fs_reg
: case gs_reg
:
15842 s
= names_seg
[code
- es_reg
];
15844 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15845 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15848 s
= names8rex
[code
- al_reg
];
15850 s
= names8
[code
- al_reg
];
15852 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15853 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15856 s
= names64
[code
- eAX_reg
];
15859 if (sizeflag
& DFLAG
)
15860 s
= names32
[code
- eAX_reg
];
15862 s
= names16
[code
- eAX_reg
];
15863 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15866 case z_mode_ax_reg
:
15867 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15871 if (!(rex
& REX_W
))
15872 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15875 s
= INTERNAL_DISASSEMBLER_ERROR
;
15882 OP_I (int bytemode
, int sizeflag
)
15885 bfd_signed_vma mask
= -1;
15890 FETCH_DATA (the_info
, codep
+ 1);
15895 if (address_mode
== mode_64bit
)
15900 /* Fall through. */
15907 if (sizeflag
& DFLAG
)
15917 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15929 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15934 scratchbuf
[0] = '$';
15935 print_operand_value (scratchbuf
+ 1, 1, op
);
15936 oappend_maybe_intel (scratchbuf
);
15937 scratchbuf
[0] = '\0';
15941 OP_I64 (int bytemode
, int sizeflag
)
15944 bfd_signed_vma mask
= -1;
15946 if (address_mode
!= mode_64bit
)
15948 OP_I (bytemode
, sizeflag
);
15955 FETCH_DATA (the_info
, codep
+ 1);
15965 if (sizeflag
& DFLAG
)
15975 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15983 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15988 scratchbuf
[0] = '$';
15989 print_operand_value (scratchbuf
+ 1, 1, op
);
15990 oappend_maybe_intel (scratchbuf
);
15991 scratchbuf
[0] = '\0';
15995 OP_sI (int bytemode
, int sizeflag
)
16003 FETCH_DATA (the_info
, codep
+ 1);
16005 if ((op
& 0x80) != 0)
16007 if (bytemode
== b_T_mode
)
16009 if (address_mode
!= mode_64bit
16010 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
16012 /* The operand-size prefix is overridden by a REX prefix. */
16013 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16021 if (!(rex
& REX_W
))
16023 if (sizeflag
& DFLAG
)
16031 /* The operand-size prefix is overridden by a REX prefix. */
16032 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16038 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16042 scratchbuf
[0] = '$';
16043 print_operand_value (scratchbuf
+ 1, 1, op
);
16044 oappend_maybe_intel (scratchbuf
);
16048 OP_J (int bytemode
, int sizeflag
)
16052 bfd_vma segment
= 0;
16057 FETCH_DATA (the_info
, codep
+ 1);
16059 if ((disp
& 0x80) != 0)
16063 if (isa64
== amd64
)
16065 if ((sizeflag
& DFLAG
)
16066 || (address_mode
== mode_64bit
16067 && (isa64
!= amd64
|| (rex
& REX_W
))))
16072 if ((disp
& 0x8000) != 0)
16074 /* In 16bit mode, address is wrapped around at 64k within
16075 the same segment. Otherwise, a data16 prefix on a jump
16076 instruction means that the pc is masked to 16 bits after
16077 the displacement is added! */
16079 if ((prefixes
& PREFIX_DATA
) == 0)
16080 segment
= ((start_pc
+ (codep
- start_codep
))
16081 & ~((bfd_vma
) 0xffff));
16083 if (address_mode
!= mode_64bit
16084 || (isa64
== amd64
&& !(rex
& REX_W
)))
16085 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16088 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16091 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
16093 print_operand_value (scratchbuf
, 1, disp
);
16094 oappend (scratchbuf
);
16098 OP_SEG (int bytemode
, int sizeflag
)
16100 if (bytemode
== w_mode
)
16101 oappend (names_seg
[modrm
.reg
]);
16103 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
16107 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
16111 if (sizeflag
& DFLAG
)
16121 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16123 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
16125 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
16126 oappend (scratchbuf
);
16130 OP_OFF (int bytemode
, int sizeflag
)
16134 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16135 intel_operand_size (bytemode
, sizeflag
);
16138 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16145 if (!active_seg_prefix
)
16147 oappend (names_seg
[ds_reg
- es_reg
]);
16151 print_operand_value (scratchbuf
, 1, off
);
16152 oappend (scratchbuf
);
16156 OP_OFF64 (int bytemode
, int sizeflag
)
16160 if (address_mode
!= mode_64bit
16161 || (prefixes
& PREFIX_ADDR
))
16163 OP_OFF (bytemode
, sizeflag
);
16167 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16168 intel_operand_size (bytemode
, sizeflag
);
16175 if (!active_seg_prefix
)
16177 oappend (names_seg
[ds_reg
- es_reg
]);
16181 print_operand_value (scratchbuf
, 1, off
);
16182 oappend (scratchbuf
);
16186 ptr_reg (int code
, int sizeflag
)
16190 *obufp
++ = open_char
;
16191 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
16192 if (address_mode
== mode_64bit
)
16194 if (!(sizeflag
& AFLAG
))
16195 s
= names32
[code
- eAX_reg
];
16197 s
= names64
[code
- eAX_reg
];
16199 else if (sizeflag
& AFLAG
)
16200 s
= names32
[code
- eAX_reg
];
16202 s
= names16
[code
- eAX_reg
];
16204 *obufp
++ = close_char
;
16209 OP_ESreg (int code
, int sizeflag
)
16215 case 0x6d: /* insw/insl */
16216 intel_operand_size (z_mode
, sizeflag
);
16218 case 0xa5: /* movsw/movsl/movsq */
16219 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16220 case 0xab: /* stosw/stosl */
16221 case 0xaf: /* scasw/scasl */
16222 intel_operand_size (v_mode
, sizeflag
);
16225 intel_operand_size (b_mode
, sizeflag
);
16228 oappend_maybe_intel ("%es:");
16229 ptr_reg (code
, sizeflag
);
16233 OP_DSreg (int code
, int sizeflag
)
16239 case 0x6f: /* outsw/outsl */
16240 intel_operand_size (z_mode
, sizeflag
);
16242 case 0xa5: /* movsw/movsl/movsq */
16243 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16244 case 0xad: /* lodsw/lodsl/lodsq */
16245 intel_operand_size (v_mode
, sizeflag
);
16248 intel_operand_size (b_mode
, sizeflag
);
16251 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16252 default segment register DS is printed. */
16253 if (!active_seg_prefix
)
16254 active_seg_prefix
= PREFIX_DS
;
16256 ptr_reg (code
, sizeflag
);
16260 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16268 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
16270 all_prefixes
[last_lock_prefix
] = 0;
16271 used_prefixes
|= PREFIX_LOCK
;
16276 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
16277 oappend_maybe_intel (scratchbuf
);
16281 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16290 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
16292 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
16293 oappend (scratchbuf
);
16297 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16299 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
16300 oappend_maybe_intel (scratchbuf
);
16304 OP_R (int bytemode
, int sizeflag
)
16306 /* Skip mod/rm byte. */
16309 OP_E_register (bytemode
, sizeflag
);
16313 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16315 int reg
= modrm
.reg
;
16316 const char **names
;
16318 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16319 if (prefixes
& PREFIX_DATA
)
16328 oappend (names
[reg
]);
16332 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16334 int reg
= modrm
.reg
;
16335 const char **names
;
16347 && bytemode
!= xmm_mode
16348 && bytemode
!= xmmq_mode
16349 && bytemode
!= evex_half_bcst_xmmq_mode
16350 && bytemode
!= ymm_mode
16351 && bytemode
!= scalar_mode
)
16353 switch (vex
.length
)
16360 || (bytemode
!= vex_vsib_q_w_dq_mode
16361 && bytemode
!= vex_vsib_q_w_d_mode
))
16373 else if (bytemode
== xmmq_mode
16374 || bytemode
== evex_half_bcst_xmmq_mode
)
16376 switch (vex
.length
)
16389 else if (bytemode
== ymm_mode
)
16393 oappend (names
[reg
]);
16397 OP_EM (int bytemode
, int sizeflag
)
16400 const char **names
;
16402 if (modrm
.mod
!= 3)
16405 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16407 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16408 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16410 OP_E (bytemode
, sizeflag
);
16414 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16417 /* Skip mod/rm byte. */
16420 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16422 if (prefixes
& PREFIX_DATA
)
16431 oappend (names
[reg
]);
16434 /* cvt* are the only instructions in sse2 which have
16435 both SSE and MMX operands and also have 0x66 prefix
16436 in their opcode. 0x66 was originally used to differentiate
16437 between SSE and MMX instruction(operands). So we have to handle the
16438 cvt* separately using OP_EMC and OP_MXC */
16440 OP_EMC (int bytemode
, int sizeflag
)
16442 if (modrm
.mod
!= 3)
16444 if (intel_syntax
&& bytemode
== v_mode
)
16446 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16447 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16449 OP_E (bytemode
, sizeflag
);
16453 /* Skip mod/rm byte. */
16456 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16457 oappend (names_mm
[modrm
.rm
]);
16461 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16463 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16464 oappend (names_mm
[modrm
.reg
]);
16468 OP_EX (int bytemode
, int sizeflag
)
16471 const char **names
;
16473 /* Skip mod/rm byte. */
16477 if (modrm
.mod
!= 3)
16479 OP_E_memory (bytemode
, sizeflag
);
16494 if ((sizeflag
& SUFFIX_ALWAYS
)
16495 && (bytemode
== x_swap_mode
16496 || bytemode
== d_swap_mode
16497 || bytemode
== d_scalar_swap_mode
16498 || bytemode
== q_swap_mode
16499 || bytemode
== q_scalar_swap_mode
))
16503 && bytemode
!= xmm_mode
16504 && bytemode
!= xmmdw_mode
16505 && bytemode
!= xmmqd_mode
16506 && bytemode
!= xmm_mb_mode
16507 && bytemode
!= xmm_mw_mode
16508 && bytemode
!= xmm_md_mode
16509 && bytemode
!= xmm_mq_mode
16510 && bytemode
!= xmm_mdq_mode
16511 && bytemode
!= xmmq_mode
16512 && bytemode
!= evex_half_bcst_xmmq_mode
16513 && bytemode
!= ymm_mode
16514 && bytemode
!= d_scalar_mode
16515 && bytemode
!= d_scalar_swap_mode
16516 && bytemode
!= q_scalar_mode
16517 && bytemode
!= q_scalar_swap_mode
16518 && bytemode
!= vex_scalar_w_dq_mode
)
16520 switch (vex
.length
)
16535 else if (bytemode
== xmmq_mode
16536 || bytemode
== evex_half_bcst_xmmq_mode
)
16538 switch (vex
.length
)
16551 else if (bytemode
== ymm_mode
)
16555 oappend (names
[reg
]);
16559 OP_MS (int bytemode
, int sizeflag
)
16561 if (modrm
.mod
== 3)
16562 OP_EM (bytemode
, sizeflag
);
16568 OP_XS (int bytemode
, int sizeflag
)
16570 if (modrm
.mod
== 3)
16571 OP_EX (bytemode
, sizeflag
);
16577 OP_M (int bytemode
, int sizeflag
)
16579 if (modrm
.mod
== 3)
16580 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16583 OP_E (bytemode
, sizeflag
);
16587 OP_0f07 (int bytemode
, int sizeflag
)
16589 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16592 OP_E (bytemode
, sizeflag
);
16595 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16596 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16599 NOP_Fixup1 (int bytemode
, int sizeflag
)
16601 if ((prefixes
& PREFIX_DATA
) != 0
16604 && address_mode
== mode_64bit
))
16605 OP_REG (bytemode
, sizeflag
);
16607 strcpy (obuf
, "nop");
16611 NOP_Fixup2 (int bytemode
, int sizeflag
)
16613 if ((prefixes
& PREFIX_DATA
) != 0
16616 && address_mode
== mode_64bit
))
16617 OP_IMREG (bytemode
, sizeflag
);
16620 static const char *const Suffix3DNow
[] = {
16621 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16622 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16623 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16624 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16625 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16626 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16627 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16628 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16629 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16630 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16631 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16632 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16633 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16634 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16635 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16636 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16637 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16638 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16639 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16640 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16641 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16642 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16643 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16644 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16645 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16646 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16647 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16648 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16649 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16650 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16651 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16652 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16653 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16654 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16655 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16656 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16657 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16658 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16659 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16660 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16661 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16662 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16663 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16664 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16665 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16666 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16667 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16668 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16669 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16670 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16671 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16672 /* CC */ NULL
, NULL
, NULL
, NULL
,
16673 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16674 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16675 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16676 /* DC */ NULL
, NULL
, NULL
, NULL
,
16677 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16678 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16679 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16680 /* EC */ NULL
, NULL
, NULL
, NULL
,
16681 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16682 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16683 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16684 /* FC */ NULL
, NULL
, NULL
, NULL
,
16688 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16690 const char *mnemonic
;
16692 FETCH_DATA (the_info
, codep
+ 1);
16693 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16694 place where an 8-bit immediate would normally go. ie. the last
16695 byte of the instruction. */
16696 obufp
= mnemonicendp
;
16697 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16699 oappend (mnemonic
);
16702 /* Since a variable sized modrm/sib chunk is between the start
16703 of the opcode (0x0f0f) and the opcode suffix, we need to do
16704 all the modrm processing first, and don't know until now that
16705 we have a bad opcode. This necessitates some cleaning up. */
16706 op_out
[0][0] = '\0';
16707 op_out
[1][0] = '\0';
16710 mnemonicendp
= obufp
;
16713 static struct op simd_cmp_op
[] =
16715 { STRING_COMMA_LEN ("eq") },
16716 { STRING_COMMA_LEN ("lt") },
16717 { STRING_COMMA_LEN ("le") },
16718 { STRING_COMMA_LEN ("unord") },
16719 { STRING_COMMA_LEN ("neq") },
16720 { STRING_COMMA_LEN ("nlt") },
16721 { STRING_COMMA_LEN ("nle") },
16722 { STRING_COMMA_LEN ("ord") }
16726 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16728 unsigned int cmp_type
;
16730 FETCH_DATA (the_info
, codep
+ 1);
16731 cmp_type
= *codep
++ & 0xff;
16732 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16735 char *p
= mnemonicendp
- 2;
16739 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16740 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16744 /* We have a reserved extension byte. Output it directly. */
16745 scratchbuf
[0] = '$';
16746 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16747 oappend_maybe_intel (scratchbuf
);
16748 scratchbuf
[0] = '\0';
16753 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
16754 int sizeflag ATTRIBUTE_UNUSED
)
16756 /* mwaitx %eax,%ecx,%ebx */
16759 const char **names
= (address_mode
== mode_64bit
16760 ? names64
: names32
);
16761 strcpy (op_out
[0], names
[0]);
16762 strcpy (op_out
[1], names
[1]);
16763 strcpy (op_out
[2], names
[3]);
16764 two_source_ops
= 1;
16766 /* Skip mod/rm byte. */
16772 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16773 int sizeflag ATTRIBUTE_UNUSED
)
16775 /* mwait %eax,%ecx */
16778 const char **names
= (address_mode
== mode_64bit
16779 ? names64
: names32
);
16780 strcpy (op_out
[0], names
[0]);
16781 strcpy (op_out
[1], names
[1]);
16782 two_source_ops
= 1;
16784 /* Skip mod/rm byte. */
16790 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16791 int sizeflag ATTRIBUTE_UNUSED
)
16793 /* monitor %eax,%ecx,%edx" */
16796 const char **op1_names
;
16797 const char **names
= (address_mode
== mode_64bit
16798 ? names64
: names32
);
16800 if (!(prefixes
& PREFIX_ADDR
))
16801 op1_names
= (address_mode
== mode_16bit
16802 ? names16
: names
);
16805 /* Remove "addr16/addr32". */
16806 all_prefixes
[last_addr_prefix
] = 0;
16807 op1_names
= (address_mode
!= mode_32bit
16808 ? names32
: names16
);
16809 used_prefixes
|= PREFIX_ADDR
;
16811 strcpy (op_out
[0], op1_names
[0]);
16812 strcpy (op_out
[1], names
[1]);
16813 strcpy (op_out
[2], names
[2]);
16814 two_source_ops
= 1;
16816 /* Skip mod/rm byte. */
16824 /* Throw away prefixes and 1st. opcode byte. */
16825 codep
= insn_codep
+ 1;
16830 REP_Fixup (int bytemode
, int sizeflag
)
16832 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16834 if (prefixes
& PREFIX_REPZ
)
16835 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16842 OP_IMREG (bytemode
, sizeflag
);
16845 OP_ESreg (bytemode
, sizeflag
);
16848 OP_DSreg (bytemode
, sizeflag
);
16856 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16860 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16862 if (prefixes
& PREFIX_REPNZ
)
16863 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16866 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16870 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16871 int sizeflag ATTRIBUTE_UNUSED
)
16873 if (active_seg_prefix
== PREFIX_DS
16874 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
16876 /* NOTRACK prefix is only valid on indirect branch instructions.
16877 NB: DATA prefix is unsupported for Intel64. */
16878 active_seg_prefix
= 0;
16879 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
16883 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16884 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16888 HLE_Fixup1 (int bytemode
, int sizeflag
)
16891 && (prefixes
& PREFIX_LOCK
) != 0)
16893 if (prefixes
& PREFIX_REPZ
)
16894 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16895 if (prefixes
& PREFIX_REPNZ
)
16896 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16899 OP_E (bytemode
, sizeflag
);
16902 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16903 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16907 HLE_Fixup2 (int bytemode
, int sizeflag
)
16909 if (modrm
.mod
!= 3)
16911 if (prefixes
& PREFIX_REPZ
)
16912 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16913 if (prefixes
& PREFIX_REPNZ
)
16914 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16917 OP_E (bytemode
, sizeflag
);
16920 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16921 "xrelease" for memory operand. No check for LOCK prefix. */
16924 HLE_Fixup3 (int bytemode
, int sizeflag
)
16927 && last_repz_prefix
> last_repnz_prefix
16928 && (prefixes
& PREFIX_REPZ
) != 0)
16929 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16931 OP_E (bytemode
, sizeflag
);
16935 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16940 /* Change cmpxchg8b to cmpxchg16b. */
16941 char *p
= mnemonicendp
- 2;
16942 mnemonicendp
= stpcpy (p
, "16b");
16945 else if ((prefixes
& PREFIX_LOCK
) != 0)
16947 if (prefixes
& PREFIX_REPZ
)
16948 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16949 if (prefixes
& PREFIX_REPNZ
)
16950 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16953 OP_M (bytemode
, sizeflag
);
16957 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
16959 const char **names
;
16963 switch (vex
.length
)
16977 oappend (names
[reg
]);
16981 CRC32_Fixup (int bytemode
, int sizeflag
)
16983 /* Add proper suffix to "crc32". */
16984 char *p
= mnemonicendp
;
17003 if (sizeflag
& DFLAG
)
17007 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17011 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17018 if (modrm
.mod
== 3)
17022 /* Skip mod/rm byte. */
17027 add
= (rex
& REX_B
) ? 8 : 0;
17028 if (bytemode
== b_mode
)
17032 oappend (names8rex
[modrm
.rm
+ add
]);
17034 oappend (names8
[modrm
.rm
+ add
]);
17040 oappend (names64
[modrm
.rm
+ add
]);
17041 else if ((prefixes
& PREFIX_DATA
))
17042 oappend (names16
[modrm
.rm
+ add
]);
17044 oappend (names32
[modrm
.rm
+ add
]);
17048 OP_E (bytemode
, sizeflag
);
17052 FXSAVE_Fixup (int bytemode
, int sizeflag
)
17054 /* Add proper suffix to "fxsave" and "fxrstor". */
17058 char *p
= mnemonicendp
;
17064 OP_M (bytemode
, sizeflag
);
17068 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
17070 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17073 char *p
= mnemonicendp
;
17078 else if (sizeflag
& SUFFIX_ALWAYS
)
17085 OP_EX (bytemode
, sizeflag
);
17088 /* Display the destination register operand for instructions with
17092 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17095 const char **names
;
17103 reg
= vex
.register_specifier
;
17104 if (address_mode
!= mode_64bit
)
17106 else if (vex
.evex
&& !vex
.v
)
17109 if (bytemode
== vex_scalar_mode
)
17111 oappend (names_xmm
[reg
]);
17115 switch (vex
.length
)
17122 case vex_vsib_q_w_dq_mode
:
17123 case vex_vsib_q_w_d_mode
:
17139 names
= names_mask
;
17153 case vex_vsib_q_w_dq_mode
:
17154 case vex_vsib_q_w_d_mode
:
17155 names
= vex
.w
? names_ymm
: names_xmm
;
17164 names
= names_mask
;
17167 /* See PR binutils/20893 for a reproducer. */
17179 oappend (names
[reg
]);
17182 /* Get the VEX immediate byte without moving codep. */
17184 static unsigned char
17185 get_vex_imm8 (int sizeflag
, int opnum
)
17187 int bytes_before_imm
= 0;
17189 if (modrm
.mod
!= 3)
17191 /* There are SIB/displacement bytes. */
17192 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
17194 /* 32/64 bit address mode */
17195 int base
= modrm
.rm
;
17197 /* Check SIB byte. */
17200 FETCH_DATA (the_info
, codep
+ 1);
17202 /* When decoding the third source, don't increase
17203 bytes_before_imm as this has already been incremented
17204 by one in OP_E_memory while decoding the second
17207 bytes_before_imm
++;
17210 /* Don't increase bytes_before_imm when decoding the third source,
17211 it has already been incremented by OP_E_memory while decoding
17212 the second source operand. */
17218 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17219 SIB == 5, there is a 4 byte displacement. */
17221 /* No displacement. */
17223 /* Fall through. */
17225 /* 4 byte displacement. */
17226 bytes_before_imm
+= 4;
17229 /* 1 byte displacement. */
17230 bytes_before_imm
++;
17237 /* 16 bit address mode */
17238 /* Don't increase bytes_before_imm when decoding the third source,
17239 it has already been incremented by OP_E_memory while decoding
17240 the second source operand. */
17246 /* When modrm.rm == 6, there is a 2 byte displacement. */
17248 /* No displacement. */
17250 /* Fall through. */
17252 /* 2 byte displacement. */
17253 bytes_before_imm
+= 2;
17256 /* 1 byte displacement: when decoding the third source,
17257 don't increase bytes_before_imm as this has already
17258 been incremented by one in OP_E_memory while decoding
17259 the second source operand. */
17261 bytes_before_imm
++;
17269 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
17270 return codep
[bytes_before_imm
];
17274 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
17276 const char **names
;
17278 if (reg
== -1 && modrm
.mod
!= 3)
17280 OP_E_memory (bytemode
, sizeflag
);
17292 if (address_mode
!= mode_64bit
)
17296 switch (vex
.length
)
17307 oappend (names
[reg
]);
17311 OP_EX_VexImmW (int bytemode
, int sizeflag
)
17314 static unsigned char vex_imm8
;
17316 if (vex_w_done
== 0)
17320 /* Skip mod/rm byte. */
17324 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
17327 reg
= vex_imm8
>> 4;
17329 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17331 else if (vex_w_done
== 1)
17336 reg
= vex_imm8
>> 4;
17338 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17342 /* Output the imm8 directly. */
17343 scratchbuf
[0] = '$';
17344 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
17345 oappend_maybe_intel (scratchbuf
);
17346 scratchbuf
[0] = '\0';
17352 OP_Vex_2src (int bytemode
, int sizeflag
)
17354 if (modrm
.mod
== 3)
17356 int reg
= modrm
.rm
;
17360 oappend (names_xmm
[reg
]);
17365 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
17367 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
17368 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17370 OP_E (bytemode
, sizeflag
);
17375 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
17377 if (modrm
.mod
== 3)
17379 /* Skip mod/rm byte. */
17386 unsigned int reg
= vex
.register_specifier
;
17388 if (address_mode
!= mode_64bit
)
17390 oappend (names_xmm
[reg
]);
17393 OP_Vex_2src (bytemode
, sizeflag
);
17397 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
17400 OP_Vex_2src (bytemode
, sizeflag
);
17403 unsigned int reg
= vex
.register_specifier
;
17405 if (address_mode
!= mode_64bit
)
17407 oappend (names_xmm
[reg
]);
17412 OP_EX_VexW (int bytemode
, int sizeflag
)
17418 /* Skip mod/rm byte. */
17423 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
17428 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
17431 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17439 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17442 const char **names
;
17444 FETCH_DATA (the_info
, codep
+ 1);
17447 if (bytemode
!= x_mode
)
17451 if (address_mode
!= mode_64bit
)
17454 switch (vex
.length
)
17465 oappend (names
[reg
]);
17469 OP_XMM_VexW (int bytemode
, int sizeflag
)
17471 /* Turn off the REX.W bit since it is used for swapping operands
17474 OP_XMM (bytemode
, sizeflag
);
17478 OP_EX_Vex (int bytemode
, int sizeflag
)
17480 if (modrm
.mod
!= 3)
17482 if (vex
.register_specifier
!= 0)
17486 OP_EX (bytemode
, sizeflag
);
17490 OP_XMM_Vex (int bytemode
, int sizeflag
)
17492 if (modrm
.mod
!= 3)
17494 if (vex
.register_specifier
!= 0)
17498 OP_XMM (bytemode
, sizeflag
);
17502 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17504 switch (vex
.length
)
17507 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17510 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17517 static struct op vex_cmp_op
[] =
17519 { STRING_COMMA_LEN ("eq") },
17520 { STRING_COMMA_LEN ("lt") },
17521 { STRING_COMMA_LEN ("le") },
17522 { STRING_COMMA_LEN ("unord") },
17523 { STRING_COMMA_LEN ("neq") },
17524 { STRING_COMMA_LEN ("nlt") },
17525 { STRING_COMMA_LEN ("nle") },
17526 { STRING_COMMA_LEN ("ord") },
17527 { STRING_COMMA_LEN ("eq_uq") },
17528 { STRING_COMMA_LEN ("nge") },
17529 { STRING_COMMA_LEN ("ngt") },
17530 { STRING_COMMA_LEN ("false") },
17531 { STRING_COMMA_LEN ("neq_oq") },
17532 { STRING_COMMA_LEN ("ge") },
17533 { STRING_COMMA_LEN ("gt") },
17534 { STRING_COMMA_LEN ("true") },
17535 { STRING_COMMA_LEN ("eq_os") },
17536 { STRING_COMMA_LEN ("lt_oq") },
17537 { STRING_COMMA_LEN ("le_oq") },
17538 { STRING_COMMA_LEN ("unord_s") },
17539 { STRING_COMMA_LEN ("neq_us") },
17540 { STRING_COMMA_LEN ("nlt_uq") },
17541 { STRING_COMMA_LEN ("nle_uq") },
17542 { STRING_COMMA_LEN ("ord_s") },
17543 { STRING_COMMA_LEN ("eq_us") },
17544 { STRING_COMMA_LEN ("nge_uq") },
17545 { STRING_COMMA_LEN ("ngt_uq") },
17546 { STRING_COMMA_LEN ("false_os") },
17547 { STRING_COMMA_LEN ("neq_os") },
17548 { STRING_COMMA_LEN ("ge_oq") },
17549 { STRING_COMMA_LEN ("gt_oq") },
17550 { STRING_COMMA_LEN ("true_us") },
17554 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17556 unsigned int cmp_type
;
17558 FETCH_DATA (the_info
, codep
+ 1);
17559 cmp_type
= *codep
++ & 0xff;
17560 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17563 char *p
= mnemonicendp
- 2;
17567 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17568 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17572 /* We have a reserved extension byte. Output it directly. */
17573 scratchbuf
[0] = '$';
17574 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17575 oappend_maybe_intel (scratchbuf
);
17576 scratchbuf
[0] = '\0';
17581 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17582 int sizeflag ATTRIBUTE_UNUSED
)
17584 unsigned int cmp_type
;
17589 FETCH_DATA (the_info
, codep
+ 1);
17590 cmp_type
= *codep
++ & 0xff;
17591 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17592 If it's the case, print suffix, otherwise - print the immediate. */
17593 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17598 char *p
= mnemonicendp
- 2;
17600 /* vpcmp* can have both one- and two-lettered suffix. */
17614 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17615 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17619 /* We have a reserved extension byte. Output it directly. */
17620 scratchbuf
[0] = '$';
17621 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17622 oappend_maybe_intel (scratchbuf
);
17623 scratchbuf
[0] = '\0';
17627 static const struct op xop_cmp_op
[] =
17629 { STRING_COMMA_LEN ("lt") },
17630 { STRING_COMMA_LEN ("le") },
17631 { STRING_COMMA_LEN ("gt") },
17632 { STRING_COMMA_LEN ("ge") },
17633 { STRING_COMMA_LEN ("eq") },
17634 { STRING_COMMA_LEN ("neq") },
17635 { STRING_COMMA_LEN ("false") },
17636 { STRING_COMMA_LEN ("true") }
17640 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17641 int sizeflag ATTRIBUTE_UNUSED
)
17643 unsigned int cmp_type
;
17645 FETCH_DATA (the_info
, codep
+ 1);
17646 cmp_type
= *codep
++ & 0xff;
17647 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
17650 char *p
= mnemonicendp
- 2;
17652 /* vpcom* can have both one- and two-lettered suffix. */
17666 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
17667 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
17671 /* We have a reserved extension byte. Output it directly. */
17672 scratchbuf
[0] = '$';
17673 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17674 oappend_maybe_intel (scratchbuf
);
17675 scratchbuf
[0] = '\0';
17679 static const struct op pclmul_op
[] =
17681 { STRING_COMMA_LEN ("lql") },
17682 { STRING_COMMA_LEN ("hql") },
17683 { STRING_COMMA_LEN ("lqh") },
17684 { STRING_COMMA_LEN ("hqh") }
17688 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17689 int sizeflag ATTRIBUTE_UNUSED
)
17691 unsigned int pclmul_type
;
17693 FETCH_DATA (the_info
, codep
+ 1);
17694 pclmul_type
= *codep
++ & 0xff;
17695 switch (pclmul_type
)
17706 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17709 char *p
= mnemonicendp
- 3;
17714 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17715 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17719 /* We have a reserved extension byte. Output it directly. */
17720 scratchbuf
[0] = '$';
17721 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17722 oappend_maybe_intel (scratchbuf
);
17723 scratchbuf
[0] = '\0';
17728 MOVBE_Fixup (int bytemode
, int sizeflag
)
17730 /* Add proper suffix to "movbe". */
17731 char *p
= mnemonicendp
;
17740 if (sizeflag
& SUFFIX_ALWAYS
)
17746 if (sizeflag
& DFLAG
)
17750 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17755 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17762 OP_M (bytemode
, sizeflag
);
17766 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17769 const char **names
;
17771 /* Skip mod/rm byte. */
17785 oappend (names
[reg
]);
17789 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17791 const char **names
;
17792 unsigned int reg
= vex
.register_specifier
;
17799 if (address_mode
!= mode_64bit
)
17801 oappend (names
[reg
]);
17805 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17808 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17812 if ((rex
& REX_R
) != 0 || !vex
.r
)
17818 oappend (names_mask
[modrm
.reg
]);
17822 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17825 || (bytemode
!= evex_rounding_mode
17826 && bytemode
!= evex_sae_mode
))
17828 if (modrm
.mod
== 3 && vex
.b
)
17831 case evex_rounding_mode
:
17832 oappend (names_rounding
[vex
.ll
]);
17834 case evex_sae_mode
: