opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2015 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 /* Possible values for prefix requirement.  */
 225 #define PREFIX_IGNORED_SHIFT    16
 226 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 227 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 231
 232 /* Opcode prefixes.  */
 233 #define PREFIX_OPCODE           (PREFIX_REPZ \
 234                                  | PREFIX_REPNZ \
 235                                  | PREFIX_DATA)
 236
 237 /* Prefixes ignored.  */
 238 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 239                                  | PREFIX_IGNORED_REPNZ \
 240                                  | PREFIX_IGNORED_DATA)
 241
 242 #define XX { NULL, 0 }
 243 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 244
 245 #define Eb { OP_E, b_mode }
 246 #define Ebnd { OP_E, bnd_mode }
 247 #define EbS { OP_E, b_swap_mode }
 248 #define Ev { OP_E, v_mode }
 249 #define Ev_bnd { OP_E, v_bnd_mode }
 250 #define EvS { OP_E, v_swap_mode }
 251 #define Ed { OP_E, d_mode }
 252 #define Edq { OP_E, dq_mode }
 253 #define Edqw { OP_E, dqw_mode }
 254 #define EdqwS { OP_E, dqw_swap_mode }
 255 #define Edqb { OP_E, dqb_mode }
 256 #define Edb { OP_E, db_mode }
 257 #define Edw { OP_E, dw_mode }
 258 #define Edqd { OP_E, dqd_mode }
 259 #define Eq { OP_E, q_mode }
 260 #define indirEv { OP_indirE, stack_v_mode }
 261 #define indirEp { OP_indirE, f_mode }
 262 #define stackEv { OP_E, stack_v_mode }
 263 #define Em { OP_E, m_mode }
 264 #define Ew { OP_E, w_mode }
 265 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 266 #define Ma { OP_M, a_mode }
 267 #define Mb { OP_M, b_mode }
 268 #define Md { OP_M, d_mode }
 269 #define Mo { OP_M, o_mode }
 270 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 271 #define Mq { OP_M, q_mode }
 272 #define Mx { OP_M, x_mode }
 273 #define Mxmm { OP_M, xmm_mode }
 274 #define Gb { OP_G, b_mode }
 275 #define Gbnd { OP_G, bnd_mode }
 276 #define Gv { OP_G, v_mode }
 277 #define Gd { OP_G, d_mode }
 278 #define Gdq { OP_G, dq_mode }
 279 #define Gm { OP_G, m_mode }
 280 #define Gw { OP_G, w_mode }
 281 #define Rd { OP_R, d_mode }
 282 #define Rdq { OP_R, dq_mode }
 283 #define Rm { OP_R, m_mode }
 284 #define Ib { OP_I, b_mode }
 285 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 286 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 287 #define Iv { OP_I, v_mode }
 288 #define sIv { OP_sI, v_mode }
 289 #define Iq { OP_I, q_mode }
 290 #define Iv64 { OP_I64, v_mode }
 291 #define Iw { OP_I, w_mode }
 292 #define I1 { OP_I, const_1_mode }
 293 #define Jb { OP_J, b_mode }
 294 #define Jv { OP_J, v_mode }
 295 #define Cm { OP_C, m_mode }
 296 #define Dm { OP_D, m_mode }
 297 #define Td { OP_T, d_mode }
 298 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 299
 300 #define RMeAX { OP_REG, eAX_reg }
 301 #define RMeBX { OP_REG, eBX_reg }
 302 #define RMeCX { OP_REG, eCX_reg }
 303 #define RMeDX { OP_REG, eDX_reg }
 304 #define RMeSP { OP_REG, eSP_reg }
 305 #define RMeBP { OP_REG, eBP_reg }
 306 #define RMeSI { OP_REG, eSI_reg }
 307 #define RMeDI { OP_REG, eDI_reg }
 308 #define RMrAX { OP_REG, rAX_reg }
 309 #define RMrBX { OP_REG, rBX_reg }
 310 #define RMrCX { OP_REG, rCX_reg }
 311 #define RMrDX { OP_REG, rDX_reg }
 312 #define RMrSP { OP_REG, rSP_reg }
 313 #define RMrBP { OP_REG, rBP_reg }
 314 #define RMrSI { OP_REG, rSI_reg }
 315 #define RMrDI { OP_REG, rDI_reg }
 316 #define RMAL { OP_REG, al_reg }
 317 #define RMCL { OP_REG, cl_reg }
 318 #define RMDL { OP_REG, dl_reg }
 319 #define RMBL { OP_REG, bl_reg }
 320 #define RMAH { OP_REG, ah_reg }
 321 #define RMCH { OP_REG, ch_reg }
 322 #define RMDH { OP_REG, dh_reg }
 323 #define RMBH { OP_REG, bh_reg }
 324 #define RMAX { OP_REG, ax_reg }
 325 #define RMDX { OP_REG, dx_reg }
 326
 327 #define eAX { OP_IMREG, eAX_reg }
 328 #define eBX { OP_IMREG, eBX_reg }
 329 #define eCX { OP_IMREG, eCX_reg }
 330 #define eDX { OP_IMREG, eDX_reg }
 331 #define eSP { OP_IMREG, eSP_reg }
 332 #define eBP { OP_IMREG, eBP_reg }
 333 #define eSI { OP_IMREG, eSI_reg }
 334 #define eDI { OP_IMREG, eDI_reg }
 335 #define AL { OP_IMREG, al_reg }
 336 #define CL { OP_IMREG, cl_reg }
 337 #define DL { OP_IMREG, dl_reg }
 338 #define BL { OP_IMREG, bl_reg }
 339 #define AH { OP_IMREG, ah_reg }
 340 #define CH { OP_IMREG, ch_reg }
 341 #define DH { OP_IMREG, dh_reg }
 342 #define BH { OP_IMREG, bh_reg }
 343 #define AX { OP_IMREG, ax_reg }
 344 #define DX { OP_IMREG, dx_reg }
 345 #define zAX { OP_IMREG, z_mode_ax_reg }
 346 #define indirDX { OP_IMREG, indir_dx_reg }
 347
 348 #define Sw { OP_SEG, w_mode }
 349 #define Sv { OP_SEG, v_mode }
 350 #define Ap { OP_DIR, 0 }
 351 #define Ob { OP_OFF64, b_mode }
 352 #define Ov { OP_OFF64, v_mode }
 353 #define Xb { OP_DSreg, eSI_reg }
 354 #define Xv { OP_DSreg, eSI_reg }
 355 #define Xz { OP_DSreg, eSI_reg }
 356 #define Yb { OP_ESreg, eDI_reg }
 357 #define Yv { OP_ESreg, eDI_reg }
 358 #define DSBX { OP_DSreg, eBX_reg }
 359
 360 #define es { OP_REG, es_reg }
 361 #define ss { OP_REG, ss_reg }
 362 #define cs { OP_REG, cs_reg }
 363 #define ds { OP_REG, ds_reg }
 364 #define fs { OP_REG, fs_reg }
 365 #define gs { OP_REG, gs_reg }
 366
 367 #define MX { OP_MMX, 0 }
 368 #define XM { OP_XMM, 0 }
 369 #define XMScalar { OP_XMM, scalar_mode }
 370 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 371 #define XMM { OP_XMM, xmm_mode }
 372 #define XMxmmq { OP_XMM, xmmq_mode }
 373 #define EM { OP_EM, v_mode }
 374 #define EMS { OP_EM, v_swap_mode }
 375 #define EMd { OP_EM, d_mode }
 376 #define EMx { OP_EM, x_mode }
 377 #define EXw { OP_EX, w_mode }
 378 #define EXd { OP_EX, d_mode }
 379 #define EXdScalar { OP_EX, d_scalar_mode }
 380 #define EXdS { OP_EX, d_swap_mode }
 381 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 382 #define EXq { OP_EX, q_mode }
 383 #define EXqScalar { OP_EX, q_scalar_mode }
 384 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 385 #define EXqS { OP_EX, q_swap_mode }
 386 #define EXx { OP_EX, x_mode }
 387 #define EXxS { OP_EX, x_swap_mode }
 388 #define EXxmm { OP_EX, xmm_mode }
 389 #define EXymm { OP_EX, ymm_mode }
 390 #define EXxmmq { OP_EX, xmmq_mode }
 391 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 392 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 393 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 394 #define EXxmm_md { OP_EX, xmm_md_mode }
 395 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 396 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 397 #define EXxmmdw { OP_EX, xmmdw_mode }
 398 #define EXxmmqd { OP_EX, xmmqd_mode }
 399 #define EXymmq { OP_EX, ymmq_mode }
 400 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 401 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 402 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 403 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 404 #define MS { OP_MS, v_mode }
 405 #define XS { OP_XS, v_mode }
 406 #define EMCq { OP_EMC, q_mode }
 407 #define MXC { OP_MXC, 0 }
 408 #define OPSUF { OP_3DNowSuffix, 0 }
 409 #define CMP { CMP_Fixup, 0 }
 410 #define XMM0 { XMM_Fixup, 0 }
 411 #define FXSAVE { FXSAVE_Fixup, 0 }
 412 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 413 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 414
 415 #define Vex { OP_VEX, vex_mode }
 416 #define VexScalar { OP_VEX, vex_scalar_mode }
 417 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 418 #define Vex128 { OP_VEX, vex128_mode }
 419 #define Vex256 { OP_VEX, vex256_mode }
 420 #define VexGdq { OP_VEX, dq_mode }
 421 #define VexI4 { VEXI4_Fixup, 0}
 422 #define EXdVex { OP_EX_Vex, d_mode }
 423 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 425 #define EXqVex { OP_EX_Vex, q_mode }
 426 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 427 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 428 #define EXVexW { OP_EX_VexW, x_mode }
 429 #define EXdVexW { OP_EX_VexW, d_mode }
 430 #define EXqVexW { OP_EX_VexW, q_mode }
 431 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 432 #define XMVex { OP_XMM_Vex, 0 }
 433 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 434 #define XMVexW { OP_XMM_VexW, 0 }
 435 #define XMVexI4 { OP_REG_VexI4, x_mode }
 436 #define PCLMUL { PCLMUL_Fixup, 0 }
 437 #define VZERO { VZERO_Fixup, 0 }
 438 #define VCMP { VCMP_Fixup, 0 }
 439 #define VPCMP { VPCMP_Fixup, 0 }
 440
 441 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 442 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 443
 444 #define XMask { OP_Mask, mask_mode }
 445 #define MaskG { OP_G, mask_mode }
 446 #define MaskE { OP_E, mask_mode }
 447 #define MaskBDE { OP_E, mask_bd_mode }
 448 #define MaskR { OP_R, mask_mode }
 449 #define MaskVex { OP_VEX, mask_mode }
 450
 451 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 452 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 453 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 454 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 455
 456 /* Used handle "rep" prefix for string instructions.  */
 457 #define Xbr { REP_Fixup, eSI_reg }
 458 #define Xvr { REP_Fixup, eSI_reg }
 459 #define Ybr { REP_Fixup, eDI_reg }
 460 #define Yvr { REP_Fixup, eDI_reg }
 461 #define Yzr { REP_Fixup, eDI_reg }
 462 #define indirDXr { REP_Fixup, indir_dx_reg }
 463 #define ALr { REP_Fixup, al_reg }
 464 #define eAXr { REP_Fixup, eAX_reg }
 465
 466 /* Used handle HLE prefix for lockable instructions.  */
 467 #define Ebh1 { HLE_Fixup1, b_mode }
 468 #define Evh1 { HLE_Fixup1, v_mode }
 469 #define Ebh2 { HLE_Fixup2, b_mode }
 470 #define Evh2 { HLE_Fixup2, v_mode }
 471 #define Ebh3 { HLE_Fixup3, b_mode }
 472 #define Evh3 { HLE_Fixup3, v_mode }
 473
 474 #define BND { BND_Fixup, 0 }
 475
 476 #define cond_jump_flag { NULL, cond_jump_mode }
 477 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 478
 479 /* bits in sizeflag */
 480 #define SUFFIX_ALWAYS 4
 481 #define AFLAG 2
 482 #define DFLAG 1
 483
 484 enum
 485 {
 486   /* byte operand */
 487   b_mode = 1,
 488   /* byte operand with operand swapped */
 489   b_swap_mode,
 490   /* byte operand, sign extend like 'T' suffix */
 491   b_T_mode,
 492   /* operand size depends on prefixes */
 493   v_mode,
 494   /* operand size depends on prefixes with operand swapped */
 495   v_swap_mode,
 496   /* word operand */
 497   w_mode,
 498   /* double word operand  */
 499   d_mode,
 500   /* double word operand with operand swapped */
 501   d_swap_mode,
 502   /* quad word operand */
 503   q_mode,
 504   /* quad word operand with operand swapped */
 505   q_swap_mode,
 506   /* ten-byte operand */
 507   t_mode,
 508   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 509      broadcast enabled.  */
 510   x_mode,
 511   /* Similar to x_mode, but with different EVEX mem shifts.  */
 512   evex_x_gscat_mode,
 513   /* Similar to x_mode, but with disabled broadcast.  */
 514   evex_x_nobcst_mode,
 515   /* Similar to x_mode, but with operands swapped and disabled broadcast
 516      in EVEX.  */
 517   x_swap_mode,
 518   /* 16-byte XMM operand */
 519   xmm_mode,
 520   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 521      memory operand (depending on vector length).  Broadcast isn't
 522      allowed.  */
 523   xmmq_mode,
 524   /* Same as xmmq_mode, but broadcast is allowed.  */
 525   evex_half_bcst_xmmq_mode,
 526   /* XMM register or byte memory operand */
 527   xmm_mb_mode,
 528   /* XMM register or word memory operand */
 529   xmm_mw_mode,
 530   /* XMM register or double word memory operand */
 531   xmm_md_mode,
 532   /* XMM register or quad word memory operand */
 533   xmm_mq_mode,
 534   /* XMM register or double/quad word memory operand, depending on
 535      VEX.W.  */
 536   xmm_mdq_mode,
 537   /* 16-byte XMM, word, double word or quad word operand.  */
 538   xmmdw_mode,
 539   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 540   xmmqd_mode,
 541   /* 32-byte YMM operand */
 542   ymm_mode,
 543   /* quad word, ymmword or zmmword memory operand.  */
 544   ymmq_mode,
 545   /* 32-byte YMM or 16-byte word operand */
 546   ymmxmm_mode,
 547   /* d_mode in 32bit, q_mode in 64bit mode.  */
 548   m_mode,
 549   /* pair of v_mode operands */
 550   a_mode,
 551   cond_jump_mode,
 552   loop_jcxz_mode,
 553   v_bnd_mode,
 554   /* operand size depends on REX prefixes.  */
 555   dq_mode,
 556   /* registers like dq_mode, memory like w_mode.  */
 557   dqw_mode,
 558   dqw_swap_mode,
 559   bnd_mode,
 560   /* 4- or 6-byte pointer operand */
 561   f_mode,
 562   const_1_mode,
 563   /* v_mode for stack-related opcodes.  */
 564   stack_v_mode,
 565   /* non-quad operand size depends on prefixes */
 566   z_mode,
 567   /* 16-byte operand */
 568   o_mode,
 569   /* registers like dq_mode, memory like b_mode.  */
 570   dqb_mode,
 571   /* registers like d_mode, memory like b_mode.  */
 572   db_mode,
 573   /* registers like d_mode, memory like w_mode.  */
 574   dw_mode,
 575   /* registers like dq_mode, memory like d_mode.  */
 576   dqd_mode,
 577   /* normal vex mode */
 578   vex_mode,
 579   /* 128bit vex mode */
 580   vex128_mode,
 581   /* 256bit vex mode */
 582   vex256_mode,
 583   /* operand size depends on the VEX.W bit.  */
 584   vex_w_dq_mode,
 585
 586   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 587   vex_vsib_d_w_dq_mode,
 588   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 589   vex_vsib_d_w_d_mode,
 590   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 591   vex_vsib_q_w_dq_mode,
 592   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 593   vex_vsib_q_w_d_mode,
 594
 595   /* scalar, ignore vector length.  */
 596   scalar_mode,
 597   /* like d_mode, ignore vector length.  */
 598   d_scalar_mode,
 599   /* like d_swap_mode, ignore vector length.  */
 600   d_scalar_swap_mode,
 601   /* like q_mode, ignore vector length.  */
 602   q_scalar_mode,
 603   /* like q_swap_mode, ignore vector length.  */
 604   q_scalar_swap_mode,
 605   /* like vex_mode, ignore vector length.  */
 606   vex_scalar_mode,
 607   /* like vex_w_dq_mode, ignore vector length.  */
 608   vex_scalar_w_dq_mode,
 609
 610   /* Static rounding.  */
 611   evex_rounding_mode,
 612   /* Supress all exceptions.  */
 613   evex_sae_mode,
 614
 615   /* Mask register operand.  */
 616   mask_mode,
 617   /* Mask register operand.  */
 618   mask_bd_mode,
 619
 620   es_reg,
 621   cs_reg,
 622   ss_reg,
 623   ds_reg,
 624   fs_reg,
 625   gs_reg,
 626
 627   eAX_reg,
 628   eCX_reg,
 629   eDX_reg,
 630   eBX_reg,
 631   eSP_reg,
 632   eBP_reg,
 633   eSI_reg,
 634   eDI_reg,
 635
 636   al_reg,
 637   cl_reg,
 638   dl_reg,
 639   bl_reg,
 640   ah_reg,
 641   ch_reg,
 642   dh_reg,
 643   bh_reg,
 644
 645   ax_reg,
 646   cx_reg,
 647   dx_reg,
 648   bx_reg,
 649   sp_reg,
 650   bp_reg,
 651   si_reg,
 652   di_reg,
 653
 654   rAX_reg,
 655   rCX_reg,
 656   rDX_reg,
 657   rBX_reg,
 658   rSP_reg,
 659   rBP_reg,
 660   rSI_reg,
 661   rDI_reg,
 662
 663   z_mode_ax_reg,
 664   indir_dx_reg
 665 };
 666
 667 enum
 668 {
 669   FLOATCODE = 1,
 670   USE_REG_TABLE,
 671   USE_MOD_TABLE,
 672   USE_RM_TABLE,
 673   USE_PREFIX_TABLE,
 674   USE_X86_64_TABLE,
 675   USE_3BYTE_TABLE,
 676   USE_XOP_8F_TABLE,
 677   USE_VEX_C4_TABLE,
 678   USE_VEX_C5_TABLE,
 679   USE_VEX_LEN_TABLE,
 680   USE_VEX_W_TABLE,
 681   USE_EVEX_TABLE
 682 };
 683
 684 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 685
 686 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 687 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 688 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 689 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 690 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 691 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 692 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 693 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 694 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 695 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 696 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 697 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 698 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 699 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 700 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 701
 702 enum
 703 {
 704   REG_80 = 0,
 705   REG_81,
 706   REG_82,
 707   REG_8F,
 708   REG_C0,
 709   REG_C1,
 710   REG_C6,
 711   REG_C7,
 712   REG_D0,
 713   REG_D1,
 714   REG_D2,
 715   REG_D3,
 716   REG_F6,
 717   REG_F7,
 718   REG_FE,
 719   REG_FF,
 720   REG_0F00,
 721   REG_0F01,
 722   REG_0F0D,
 723   REG_0F18,
 724   REG_0F71,
 725   REG_0F72,
 726   REG_0F73,
 727   REG_0FA6,
 728   REG_0FA7,
 729   REG_0FAE,
 730   REG_0FBA,
 731   REG_0FC7,
 732   REG_VEX_0F71,
 733   REG_VEX_0F72,
 734   REG_VEX_0F73,
 735   REG_VEX_0FAE,
 736   REG_VEX_0F38F3,
 737   REG_XOP_LWPCB,
 738   REG_XOP_LWP,
 739   REG_XOP_TBM_01,
 740   REG_XOP_TBM_02,
 741
 742   REG_EVEX_0F71,
 743   REG_EVEX_0F72,
 744   REG_EVEX_0F73,
 745   REG_EVEX_0F38C6,
 746   REG_EVEX_0F38C7
 747 };
 748
 749 enum
 750 {
 751   MOD_8D = 0,
 752   MOD_C6_REG_7,
 753   MOD_C7_REG_7,
 754   MOD_FF_REG_3,
 755   MOD_FF_REG_5,
 756   MOD_0F01_REG_0,
 757   MOD_0F01_REG_1,
 758   MOD_0F01_REG_2,
 759   MOD_0F01_REG_3,
 760   MOD_0F01_REG_7,
 761   MOD_0F12_PREFIX_0,
 762   MOD_0F13,
 763   MOD_0F16_PREFIX_0,
 764   MOD_0F17,
 765   MOD_0F18_REG_0,
 766   MOD_0F18_REG_1,
 767   MOD_0F18_REG_2,
 768   MOD_0F18_REG_3,
 769   MOD_0F18_REG_4,
 770   MOD_0F18_REG_5,
 771   MOD_0F18_REG_6,
 772   MOD_0F18_REG_7,
 773   MOD_0F1A_PREFIX_0,
 774   MOD_0F1B_PREFIX_0,
 775   MOD_0F1B_PREFIX_1,
 776   MOD_0F24,
 777   MOD_0F26,
 778   MOD_0F2B_PREFIX_0,
 779   MOD_0F2B_PREFIX_1,
 780   MOD_0F2B_PREFIX_2,
 781   MOD_0F2B_PREFIX_3,
 782   MOD_0F51,
 783   MOD_0F71_REG_2,
 784   MOD_0F71_REG_4,
 785   MOD_0F71_REG_6,
 786   MOD_0F72_REG_2,
 787   MOD_0F72_REG_4,
 788   MOD_0F72_REG_6,
 789   MOD_0F73_REG_2,
 790   MOD_0F73_REG_3,
 791   MOD_0F73_REG_6,
 792   MOD_0F73_REG_7,
 793   MOD_0FAE_REG_0,
 794   MOD_0FAE_REG_1,
 795   MOD_0FAE_REG_2,
 796   MOD_0FAE_REG_3,
 797   MOD_0FAE_REG_4,
 798   MOD_0FAE_REG_5,
 799   MOD_0FAE_REG_6,
 800   MOD_0FAE_REG_7,
 801   MOD_0FB2,
 802   MOD_0FB4,
 803   MOD_0FB5,
 804   MOD_0FC7_REG_3,
 805   MOD_0FC7_REG_4,
 806   MOD_0FC7_REG_5,
 807   MOD_0FC7_REG_6,
 808   MOD_0FC7_REG_7,
 809   MOD_0FD7,
 810   MOD_0FE7_PREFIX_2,
 811   MOD_0FF0_PREFIX_3,
 812   MOD_0F382A_PREFIX_2,
 813   MOD_62_32BIT,
 814   MOD_C4_32BIT,
 815   MOD_C5_32BIT,
 816   MOD_VEX_0F12_PREFIX_0,
 817   MOD_VEX_0F13,
 818   MOD_VEX_0F16_PREFIX_0,
 819   MOD_VEX_0F17,
 820   MOD_VEX_0F2B,
 821   MOD_VEX_0F50,
 822   MOD_VEX_0F71_REG_2,
 823   MOD_VEX_0F71_REG_4,
 824   MOD_VEX_0F71_REG_6,
 825   MOD_VEX_0F72_REG_2,
 826   MOD_VEX_0F72_REG_4,
 827   MOD_VEX_0F72_REG_6,
 828   MOD_VEX_0F73_REG_2,
 829   MOD_VEX_0F73_REG_3,
 830   MOD_VEX_0F73_REG_6,
 831   MOD_VEX_0F73_REG_7,
 832   MOD_VEX_0FAE_REG_2,
 833   MOD_VEX_0FAE_REG_3,
 834   MOD_VEX_0FD7_PREFIX_2,
 835   MOD_VEX_0FE7_PREFIX_2,
 836   MOD_VEX_0FF0_PREFIX_3,
 837   MOD_VEX_0F381A_PREFIX_2,
 838   MOD_VEX_0F382A_PREFIX_2,
 839   MOD_VEX_0F382C_PREFIX_2,
 840   MOD_VEX_0F382D_PREFIX_2,
 841   MOD_VEX_0F382E_PREFIX_2,
 842   MOD_VEX_0F382F_PREFIX_2,
 843   MOD_VEX_0F385A_PREFIX_2,
 844   MOD_VEX_0F388C_PREFIX_2,
 845   MOD_VEX_0F388E_PREFIX_2,
 846
 847   MOD_EVEX_0F10_PREFIX_1,
 848   MOD_EVEX_0F10_PREFIX_3,
 849   MOD_EVEX_0F11_PREFIX_1,
 850   MOD_EVEX_0F11_PREFIX_3,
 851   MOD_EVEX_0F12_PREFIX_0,
 852   MOD_EVEX_0F16_PREFIX_0,
 853   MOD_EVEX_0F38C6_REG_1,
 854   MOD_EVEX_0F38C6_REG_2,
 855   MOD_EVEX_0F38C6_REG_5,
 856   MOD_EVEX_0F38C6_REG_6,
 857   MOD_EVEX_0F38C7_REG_1,
 858   MOD_EVEX_0F38C7_REG_2,
 859   MOD_EVEX_0F38C7_REG_5,
 860   MOD_EVEX_0F38C7_REG_6
 861 };
 862
 863 enum
 864 {
 865   RM_C6_REG_7 = 0,
 866   RM_C7_REG_7,
 867   RM_0F01_REG_0,
 868   RM_0F01_REG_1,
 869   RM_0F01_REG_2,
 870   RM_0F01_REG_3,
 871   RM_0F01_REG_7,
 872   RM_0FAE_REG_5,
 873   RM_0FAE_REG_6,
 874   RM_0FAE_REG_7
 875 };
 876
 877 enum
 878 {
 879   PREFIX_90 = 0,
 880   PREFIX_0F10,
 881   PREFIX_0F11,
 882   PREFIX_0F12,
 883   PREFIX_0F16,
 884   PREFIX_0F1A,
 885   PREFIX_0F1B,
 886   PREFIX_0F2A,
 887   PREFIX_0F2B,
 888   PREFIX_0F2C,
 889   PREFIX_0F2D,
 890   PREFIX_0F2E,
 891   PREFIX_0F2F,
 892   PREFIX_0F51,
 893   PREFIX_0F52,
 894   PREFIX_0F53,
 895   PREFIX_0F58,
 896   PREFIX_0F59,
 897   PREFIX_0F5A,
 898   PREFIX_0F5B,
 899   PREFIX_0F5C,
 900   PREFIX_0F5D,
 901   PREFIX_0F5E,
 902   PREFIX_0F5F,
 903   PREFIX_0F60,
 904   PREFIX_0F61,
 905   PREFIX_0F62,
 906   PREFIX_0F6C,
 907   PREFIX_0F6D,
 908   PREFIX_0F6F,
 909   PREFIX_0F70,
 910   PREFIX_0F73_REG_3,
 911   PREFIX_0F73_REG_7,
 912   PREFIX_0F78,
 913   PREFIX_0F79,
 914   PREFIX_0F7C,
 915   PREFIX_0F7D,
 916   PREFIX_0F7E,
 917   PREFIX_0F7F,
 918   PREFIX_0FAE_REG_0,
 919   PREFIX_0FAE_REG_1,
 920   PREFIX_0FAE_REG_2,
 921   PREFIX_0FAE_REG_3,
 922   PREFIX_0FAE_REG_6,
 923   PREFIX_0FAE_REG_7,
 924   PREFIX_RM_0_0FAE_REG_7,
 925   PREFIX_0FB8,
 926   PREFIX_0FBC,
 927   PREFIX_0FBD,
 928   PREFIX_0FC2,
 929   PREFIX_0FC3,
 930   PREFIX_MOD_0_0FC7_REG_6,
 931   PREFIX_MOD_3_0FC7_REG_6,
 932   PREFIX_MOD_3_0FC7_REG_7,
 933   PREFIX_0FD0,
 934   PREFIX_0FD6,
 935   PREFIX_0FE6,
 936   PREFIX_0FE7,
 937   PREFIX_0FF0,
 938   PREFIX_0FF7,
 939   PREFIX_0F3810,
 940   PREFIX_0F3814,
 941   PREFIX_0F3815,
 942   PREFIX_0F3817,
 943   PREFIX_0F3820,
 944   PREFIX_0F3821,
 945   PREFIX_0F3822,
 946   PREFIX_0F3823,
 947   PREFIX_0F3824,
 948   PREFIX_0F3825,
 949   PREFIX_0F3828,
 950   PREFIX_0F3829,
 951   PREFIX_0F382A,
 952   PREFIX_0F382B,
 953   PREFIX_0F3830,
 954   PREFIX_0F3831,
 955   PREFIX_0F3832,
 956   PREFIX_0F3833,
 957   PREFIX_0F3834,
 958   PREFIX_0F3835,
 959   PREFIX_0F3837,
 960   PREFIX_0F3838,
 961   PREFIX_0F3839,
 962   PREFIX_0F383A,
 963   PREFIX_0F383B,
 964   PREFIX_0F383C,
 965   PREFIX_0F383D,
 966   PREFIX_0F383E,
 967   PREFIX_0F383F,
 968   PREFIX_0F3840,
 969   PREFIX_0F3841,
 970   PREFIX_0F3880,
 971   PREFIX_0F3881,
 972   PREFIX_0F3882,
 973   PREFIX_0F38C8,
 974   PREFIX_0F38C9,
 975   PREFIX_0F38CA,
 976   PREFIX_0F38CB,
 977   PREFIX_0F38CC,
 978   PREFIX_0F38CD,
 979   PREFIX_0F38DB,
 980   PREFIX_0F38DC,
 981   PREFIX_0F38DD,
 982   PREFIX_0F38DE,
 983   PREFIX_0F38DF,
 984   PREFIX_0F38F0,
 985   PREFIX_0F38F1,
 986   PREFIX_0F38F6,
 987   PREFIX_0F3A08,
 988   PREFIX_0F3A09,
 989   PREFIX_0F3A0A,
 990   PREFIX_0F3A0B,
 991   PREFIX_0F3A0C,
 992   PREFIX_0F3A0D,
 993   PREFIX_0F3A0E,
 994   PREFIX_0F3A14,
 995   PREFIX_0F3A15,
 996   PREFIX_0F3A16,
 997   PREFIX_0F3A17,
 998   PREFIX_0F3A20,
 999   PREFIX_0F3A21,
1000   PREFIX_0F3A22,
1001   PREFIX_0F3A40,
1002   PREFIX_0F3A41,
1003   PREFIX_0F3A42,
1004   PREFIX_0F3A44,
1005   PREFIX_0F3A60,
1006   PREFIX_0F3A61,
1007   PREFIX_0F3A62,
1008   PREFIX_0F3A63,
1009   PREFIX_0F3ACC,
1010   PREFIX_0F3ADF,
1011   PREFIX_VEX_0F10,
1012   PREFIX_VEX_0F11,
1013   PREFIX_VEX_0F12,
1014   PREFIX_VEX_0F16,
1015   PREFIX_VEX_0F2A,
1016   PREFIX_VEX_0F2C,
1017   PREFIX_VEX_0F2D,
1018   PREFIX_VEX_0F2E,
1019   PREFIX_VEX_0F2F,
1020   PREFIX_VEX_0F41,
1021   PREFIX_VEX_0F42,
1022   PREFIX_VEX_0F44,
1023   PREFIX_VEX_0F45,
1024   PREFIX_VEX_0F46,
1025   PREFIX_VEX_0F47,
1026   PREFIX_VEX_0F4A,
1027   PREFIX_VEX_0F4B,
1028   PREFIX_VEX_0F51,
1029   PREFIX_VEX_0F52,
1030   PREFIX_VEX_0F53,
1031   PREFIX_VEX_0F58,
1032   PREFIX_VEX_0F59,
1033   PREFIX_VEX_0F5A,
1034   PREFIX_VEX_0F5B,
1035   PREFIX_VEX_0F5C,
1036   PREFIX_VEX_0F5D,
1037   PREFIX_VEX_0F5E,
1038   PREFIX_VEX_0F5F,
1039   PREFIX_VEX_0F60,
1040   PREFIX_VEX_0F61,
1041   PREFIX_VEX_0F62,
1042   PREFIX_VEX_0F63,
1043   PREFIX_VEX_0F64,
1044   PREFIX_VEX_0F65,
1045   PREFIX_VEX_0F66,
1046   PREFIX_VEX_0F67,
1047   PREFIX_VEX_0F68,
1048   PREFIX_VEX_0F69,
1049   PREFIX_VEX_0F6A,
1050   PREFIX_VEX_0F6B,
1051   PREFIX_VEX_0F6C,
1052   PREFIX_VEX_0F6D,
1053   PREFIX_VEX_0F6E,
1054   PREFIX_VEX_0F6F,
1055   PREFIX_VEX_0F70,
1056   PREFIX_VEX_0F71_REG_2,
1057   PREFIX_VEX_0F71_REG_4,
1058   PREFIX_VEX_0F71_REG_6,
1059   PREFIX_VEX_0F72_REG_2,
1060   PREFIX_VEX_0F72_REG_4,
1061   PREFIX_VEX_0F72_REG_6,
1062   PREFIX_VEX_0F73_REG_2,
1063   PREFIX_VEX_0F73_REG_3,
1064   PREFIX_VEX_0F73_REG_6,
1065   PREFIX_VEX_0F73_REG_7,
1066   PREFIX_VEX_0F74,
1067   PREFIX_VEX_0F75,
1068   PREFIX_VEX_0F76,
1069   PREFIX_VEX_0F77,
1070   PREFIX_VEX_0F7C,
1071   PREFIX_VEX_0F7D,
1072   PREFIX_VEX_0F7E,
1073   PREFIX_VEX_0F7F,
1074   PREFIX_VEX_0F90,
1075   PREFIX_VEX_0F91,
1076   PREFIX_VEX_0F92,
1077   PREFIX_VEX_0F93,
1078   PREFIX_VEX_0F98,
1079   PREFIX_VEX_0F99,
1080   PREFIX_VEX_0FC2,
1081   PREFIX_VEX_0FC4,
1082   PREFIX_VEX_0FC5,
1083   PREFIX_VEX_0FD0,
1084   PREFIX_VEX_0FD1,
1085   PREFIX_VEX_0FD2,
1086   PREFIX_VEX_0FD3,
1087   PREFIX_VEX_0FD4,
1088   PREFIX_VEX_0FD5,
1089   PREFIX_VEX_0FD6,
1090   PREFIX_VEX_0FD7,
1091   PREFIX_VEX_0FD8,
1092   PREFIX_VEX_0FD9,
1093   PREFIX_VEX_0FDA,
1094   PREFIX_VEX_0FDB,
1095   PREFIX_VEX_0FDC,
1096   PREFIX_VEX_0FDD,
1097   PREFIX_VEX_0FDE,
1098   PREFIX_VEX_0FDF,
1099   PREFIX_VEX_0FE0,
1100   PREFIX_VEX_0FE1,
1101   PREFIX_VEX_0FE2,
1102   PREFIX_VEX_0FE3,
1103   PREFIX_VEX_0FE4,
1104   PREFIX_VEX_0FE5,
1105   PREFIX_VEX_0FE6,
1106   PREFIX_VEX_0FE7,
1107   PREFIX_VEX_0FE8,
1108   PREFIX_VEX_0FE9,
1109   PREFIX_VEX_0FEA,
1110   PREFIX_VEX_0FEB,
1111   PREFIX_VEX_0FEC,
1112   PREFIX_VEX_0FED,
1113   PREFIX_VEX_0FEE,
1114   PREFIX_VEX_0FEF,
1115   PREFIX_VEX_0FF0,
1116   PREFIX_VEX_0FF1,
1117   PREFIX_VEX_0FF2,
1118   PREFIX_VEX_0FF3,
1119   PREFIX_VEX_0FF4,
1120   PREFIX_VEX_0FF5,
1121   PREFIX_VEX_0FF6,
1122   PREFIX_VEX_0FF7,
1123   PREFIX_VEX_0FF8,
1124   PREFIX_VEX_0FF9,
1125   PREFIX_VEX_0FFA,
1126   PREFIX_VEX_0FFB,
1127   PREFIX_VEX_0FFC,
1128   PREFIX_VEX_0FFD,
1129   PREFIX_VEX_0FFE,
1130   PREFIX_VEX_0F3800,
1131   PREFIX_VEX_0F3801,
1132   PREFIX_VEX_0F3802,
1133   PREFIX_VEX_0F3803,
1134   PREFIX_VEX_0F3804,
1135   PREFIX_VEX_0F3805,
1136   PREFIX_VEX_0F3806,
1137   PREFIX_VEX_0F3807,
1138   PREFIX_VEX_0F3808,
1139   PREFIX_VEX_0F3809,
1140   PREFIX_VEX_0F380A,
1141   PREFIX_VEX_0F380B,
1142   PREFIX_VEX_0F380C,
1143   PREFIX_VEX_0F380D,
1144   PREFIX_VEX_0F380E,
1145   PREFIX_VEX_0F380F,
1146   PREFIX_VEX_0F3813,
1147   PREFIX_VEX_0F3816,
1148   PREFIX_VEX_0F3817,
1149   PREFIX_VEX_0F3818,
1150   PREFIX_VEX_0F3819,
1151   PREFIX_VEX_0F381A,
1152   PREFIX_VEX_0F381C,
1153   PREFIX_VEX_0F381D,
1154   PREFIX_VEX_0F381E,
1155   PREFIX_VEX_0F3820,
1156   PREFIX_VEX_0F3821,
1157   PREFIX_VEX_0F3822,
1158   PREFIX_VEX_0F3823,
1159   PREFIX_VEX_0F3824,
1160   PREFIX_VEX_0F3825,
1161   PREFIX_VEX_0F3828,
1162   PREFIX_VEX_0F3829,
1163   PREFIX_VEX_0F382A,
1164   PREFIX_VEX_0F382B,
1165   PREFIX_VEX_0F382C,
1166   PREFIX_VEX_0F382D,
1167   PREFIX_VEX_0F382E,
1168   PREFIX_VEX_0F382F,
1169   PREFIX_VEX_0F3830,
1170   PREFIX_VEX_0F3831,
1171   PREFIX_VEX_0F3832,
1172   PREFIX_VEX_0F3833,
1173   PREFIX_VEX_0F3834,
1174   PREFIX_VEX_0F3835,
1175   PREFIX_VEX_0F3836,
1176   PREFIX_VEX_0F3837,
1177   PREFIX_VEX_0F3838,
1178   PREFIX_VEX_0F3839,
1179   PREFIX_VEX_0F383A,
1180   PREFIX_VEX_0F383B,
1181   PREFIX_VEX_0F383C,
1182   PREFIX_VEX_0F383D,
1183   PREFIX_VEX_0F383E,
1184   PREFIX_VEX_0F383F,
1185   PREFIX_VEX_0F3840,
1186   PREFIX_VEX_0F3841,
1187   PREFIX_VEX_0F3845,
1188   PREFIX_VEX_0F3846,
1189   PREFIX_VEX_0F3847,
1190   PREFIX_VEX_0F3858,
1191   PREFIX_VEX_0F3859,
1192   PREFIX_VEX_0F385A,
1193   PREFIX_VEX_0F3878,
1194   PREFIX_VEX_0F3879,
1195   PREFIX_VEX_0F388C,
1196   PREFIX_VEX_0F388E,
1197   PREFIX_VEX_0F3890,
1198   PREFIX_VEX_0F3891,
1199   PREFIX_VEX_0F3892,
1200   PREFIX_VEX_0F3893,
1201   PREFIX_VEX_0F3896,
1202   PREFIX_VEX_0F3897,
1203   PREFIX_VEX_0F3898,
1204   PREFIX_VEX_0F3899,
1205   PREFIX_VEX_0F389A,
1206   PREFIX_VEX_0F389B,
1207   PREFIX_VEX_0F389C,
1208   PREFIX_VEX_0F389D,
1209   PREFIX_VEX_0F389E,
1210   PREFIX_VEX_0F389F,
1211   PREFIX_VEX_0F38A6,
1212   PREFIX_VEX_0F38A7,
1213   PREFIX_VEX_0F38A8,
1214   PREFIX_VEX_0F38A9,
1215   PREFIX_VEX_0F38AA,
1216   PREFIX_VEX_0F38AB,
1217   PREFIX_VEX_0F38AC,
1218   PREFIX_VEX_0F38AD,
1219   PREFIX_VEX_0F38AE,
1220   PREFIX_VEX_0F38AF,
1221   PREFIX_VEX_0F38B6,
1222   PREFIX_VEX_0F38B7,
1223   PREFIX_VEX_0F38B8,
1224   PREFIX_VEX_0F38B9,
1225   PREFIX_VEX_0F38BA,
1226   PREFIX_VEX_0F38BB,
1227   PREFIX_VEX_0F38BC,
1228   PREFIX_VEX_0F38BD,
1229   PREFIX_VEX_0F38BE,
1230   PREFIX_VEX_0F38BF,
1231   PREFIX_VEX_0F38DB,
1232   PREFIX_VEX_0F38DC,
1233   PREFIX_VEX_0F38DD,
1234   PREFIX_VEX_0F38DE,
1235   PREFIX_VEX_0F38DF,
1236   PREFIX_VEX_0F38F2,
1237   PREFIX_VEX_0F38F3_REG_1,
1238   PREFIX_VEX_0F38F3_REG_2,
1239   PREFIX_VEX_0F38F3_REG_3,
1240   PREFIX_VEX_0F38F5,
1241   PREFIX_VEX_0F38F6,
1242   PREFIX_VEX_0F38F7,
1243   PREFIX_VEX_0F3A00,
1244   PREFIX_VEX_0F3A01,
1245   PREFIX_VEX_0F3A02,
1246   PREFIX_VEX_0F3A04,
1247   PREFIX_VEX_0F3A05,
1248   PREFIX_VEX_0F3A06,
1249   PREFIX_VEX_0F3A08,
1250   PREFIX_VEX_0F3A09,
1251   PREFIX_VEX_0F3A0A,
1252   PREFIX_VEX_0F3A0B,
1253   PREFIX_VEX_0F3A0C,
1254   PREFIX_VEX_0F3A0D,
1255   PREFIX_VEX_0F3A0E,
1256   PREFIX_VEX_0F3A0F,
1257   PREFIX_VEX_0F3A14,
1258   PREFIX_VEX_0F3A15,
1259   PREFIX_VEX_0F3A16,
1260   PREFIX_VEX_0F3A17,
1261   PREFIX_VEX_0F3A18,
1262   PREFIX_VEX_0F3A19,
1263   PREFIX_VEX_0F3A1D,
1264   PREFIX_VEX_0F3A20,
1265   PREFIX_VEX_0F3A21,
1266   PREFIX_VEX_0F3A22,
1267   PREFIX_VEX_0F3A30,
1268   PREFIX_VEX_0F3A31,
1269   PREFIX_VEX_0F3A32,
1270   PREFIX_VEX_0F3A33,
1271   PREFIX_VEX_0F3A38,
1272   PREFIX_VEX_0F3A39,
1273   PREFIX_VEX_0F3A40,
1274   PREFIX_VEX_0F3A41,
1275   PREFIX_VEX_0F3A42,
1276   PREFIX_VEX_0F3A44,
1277   PREFIX_VEX_0F3A46,
1278   PREFIX_VEX_0F3A48,
1279   PREFIX_VEX_0F3A49,
1280   PREFIX_VEX_0F3A4A,
1281   PREFIX_VEX_0F3A4B,
1282   PREFIX_VEX_0F3A4C,
1283   PREFIX_VEX_0F3A5C,
1284   PREFIX_VEX_0F3A5D,
1285   PREFIX_VEX_0F3A5E,
1286   PREFIX_VEX_0F3A5F,
1287   PREFIX_VEX_0F3A60,
1288   PREFIX_VEX_0F3A61,
1289   PREFIX_VEX_0F3A62,
1290   PREFIX_VEX_0F3A63,
1291   PREFIX_VEX_0F3A68,
1292   PREFIX_VEX_0F3A69,
1293   PREFIX_VEX_0F3A6A,
1294   PREFIX_VEX_0F3A6B,
1295   PREFIX_VEX_0F3A6C,
1296   PREFIX_VEX_0F3A6D,
1297   PREFIX_VEX_0F3A6E,
1298   PREFIX_VEX_0F3A6F,
1299   PREFIX_VEX_0F3A78,
1300   PREFIX_VEX_0F3A79,
1301   PREFIX_VEX_0F3A7A,
1302   PREFIX_VEX_0F3A7B,
1303   PREFIX_VEX_0F3A7C,
1304   PREFIX_VEX_0F3A7D,
1305   PREFIX_VEX_0F3A7E,
1306   PREFIX_VEX_0F3A7F,
1307   PREFIX_VEX_0F3ADF,
1308   PREFIX_VEX_0F3AF0,
1309
1310   PREFIX_EVEX_0F10,
1311   PREFIX_EVEX_0F11,
1312   PREFIX_EVEX_0F12,
1313   PREFIX_EVEX_0F13,
1314   PREFIX_EVEX_0F14,
1315   PREFIX_EVEX_0F15,
1316   PREFIX_EVEX_0F16,
1317   PREFIX_EVEX_0F17,
1318   PREFIX_EVEX_0F28,
1319   PREFIX_EVEX_0F29,
1320   PREFIX_EVEX_0F2A,
1321   PREFIX_EVEX_0F2B,
1322   PREFIX_EVEX_0F2C,
1323   PREFIX_EVEX_0F2D,
1324   PREFIX_EVEX_0F2E,
1325   PREFIX_EVEX_0F2F,
1326   PREFIX_EVEX_0F51,
1327   PREFIX_EVEX_0F54,
1328   PREFIX_EVEX_0F55,
1329   PREFIX_EVEX_0F56,
1330   PREFIX_EVEX_0F57,
1331   PREFIX_EVEX_0F58,
1332   PREFIX_EVEX_0F59,
1333   PREFIX_EVEX_0F5A,
1334   PREFIX_EVEX_0F5B,
1335   PREFIX_EVEX_0F5C,
1336   PREFIX_EVEX_0F5D,
1337   PREFIX_EVEX_0F5E,
1338   PREFIX_EVEX_0F5F,
1339   PREFIX_EVEX_0F60,
1340   PREFIX_EVEX_0F61,
1341   PREFIX_EVEX_0F62,
1342   PREFIX_EVEX_0F63,
1343   PREFIX_EVEX_0F64,
1344   PREFIX_EVEX_0F65,
1345   PREFIX_EVEX_0F66,
1346   PREFIX_EVEX_0F67,
1347   PREFIX_EVEX_0F68,
1348   PREFIX_EVEX_0F69,
1349   PREFIX_EVEX_0F6A,
1350   PREFIX_EVEX_0F6B,
1351   PREFIX_EVEX_0F6C,
1352   PREFIX_EVEX_0F6D,
1353   PREFIX_EVEX_0F6E,
1354   PREFIX_EVEX_0F6F,
1355   PREFIX_EVEX_0F70,
1356   PREFIX_EVEX_0F71_REG_2,
1357   PREFIX_EVEX_0F71_REG_4,
1358   PREFIX_EVEX_0F71_REG_6,
1359   PREFIX_EVEX_0F72_REG_0,
1360   PREFIX_EVEX_0F72_REG_1,
1361   PREFIX_EVEX_0F72_REG_2,
1362   PREFIX_EVEX_0F72_REG_4,
1363   PREFIX_EVEX_0F72_REG_6,
1364   PREFIX_EVEX_0F73_REG_2,
1365   PREFIX_EVEX_0F73_REG_3,
1366   PREFIX_EVEX_0F73_REG_6,
1367   PREFIX_EVEX_0F73_REG_7,
1368   PREFIX_EVEX_0F74,
1369   PREFIX_EVEX_0F75,
1370   PREFIX_EVEX_0F76,
1371   PREFIX_EVEX_0F78,
1372   PREFIX_EVEX_0F79,
1373   PREFIX_EVEX_0F7A,
1374   PREFIX_EVEX_0F7B,
1375   PREFIX_EVEX_0F7E,
1376   PREFIX_EVEX_0F7F,
1377   PREFIX_EVEX_0FC2,
1378   PREFIX_EVEX_0FC4,
1379   PREFIX_EVEX_0FC5,
1380   PREFIX_EVEX_0FC6,
1381   PREFIX_EVEX_0FD1,
1382   PREFIX_EVEX_0FD2,
1383   PREFIX_EVEX_0FD3,
1384   PREFIX_EVEX_0FD4,
1385   PREFIX_EVEX_0FD5,
1386   PREFIX_EVEX_0FD6,
1387   PREFIX_EVEX_0FD8,
1388   PREFIX_EVEX_0FD9,
1389   PREFIX_EVEX_0FDA,
1390   PREFIX_EVEX_0FDB,
1391   PREFIX_EVEX_0FDC,
1392   PREFIX_EVEX_0FDD,
1393   PREFIX_EVEX_0FDE,
1394   PREFIX_EVEX_0FDF,
1395   PREFIX_EVEX_0FE0,
1396   PREFIX_EVEX_0FE1,
1397   PREFIX_EVEX_0FE2,
1398   PREFIX_EVEX_0FE3,
1399   PREFIX_EVEX_0FE4,
1400   PREFIX_EVEX_0FE5,
1401   PREFIX_EVEX_0FE6,
1402   PREFIX_EVEX_0FE7,
1403   PREFIX_EVEX_0FE8,
1404   PREFIX_EVEX_0FE9,
1405   PREFIX_EVEX_0FEA,
1406   PREFIX_EVEX_0FEB,
1407   PREFIX_EVEX_0FEC,
1408   PREFIX_EVEX_0FED,
1409   PREFIX_EVEX_0FEE,
1410   PREFIX_EVEX_0FEF,
1411   PREFIX_EVEX_0FF1,
1412   PREFIX_EVEX_0FF2,
1413   PREFIX_EVEX_0FF3,
1414   PREFIX_EVEX_0FF4,
1415   PREFIX_EVEX_0FF5,
1416   PREFIX_EVEX_0FF6,
1417   PREFIX_EVEX_0FF8,
1418   PREFIX_EVEX_0FF9,
1419   PREFIX_EVEX_0FFA,
1420   PREFIX_EVEX_0FFB,
1421   PREFIX_EVEX_0FFC,
1422   PREFIX_EVEX_0FFD,
1423   PREFIX_EVEX_0FFE,
1424   PREFIX_EVEX_0F3800,
1425   PREFIX_EVEX_0F3804,
1426   PREFIX_EVEX_0F380B,
1427   PREFIX_EVEX_0F380C,
1428   PREFIX_EVEX_0F380D,
1429   PREFIX_EVEX_0F3810,
1430   PREFIX_EVEX_0F3811,
1431   PREFIX_EVEX_0F3812,
1432   PREFIX_EVEX_0F3813,
1433   PREFIX_EVEX_0F3814,
1434   PREFIX_EVEX_0F3815,
1435   PREFIX_EVEX_0F3816,
1436   PREFIX_EVEX_0F3818,
1437   PREFIX_EVEX_0F3819,
1438   PREFIX_EVEX_0F381A,
1439   PREFIX_EVEX_0F381B,
1440   PREFIX_EVEX_0F381C,
1441   PREFIX_EVEX_0F381D,
1442   PREFIX_EVEX_0F381E,
1443   PREFIX_EVEX_0F381F,
1444   PREFIX_EVEX_0F3820,
1445   PREFIX_EVEX_0F3821,
1446   PREFIX_EVEX_0F3822,
1447   PREFIX_EVEX_0F3823,
1448   PREFIX_EVEX_0F3824,
1449   PREFIX_EVEX_0F3825,
1450   PREFIX_EVEX_0F3826,
1451   PREFIX_EVEX_0F3827,
1452   PREFIX_EVEX_0F3828,
1453   PREFIX_EVEX_0F3829,
1454   PREFIX_EVEX_0F382A,
1455   PREFIX_EVEX_0F382B,
1456   PREFIX_EVEX_0F382C,
1457   PREFIX_EVEX_0F382D,
1458   PREFIX_EVEX_0F3830,
1459   PREFIX_EVEX_0F3831,
1460   PREFIX_EVEX_0F3832,
1461   PREFIX_EVEX_0F3833,
1462   PREFIX_EVEX_0F3834,
1463   PREFIX_EVEX_0F3835,
1464   PREFIX_EVEX_0F3836,
1465   PREFIX_EVEX_0F3837,
1466   PREFIX_EVEX_0F3838,
1467   PREFIX_EVEX_0F3839,
1468   PREFIX_EVEX_0F383A,
1469   PREFIX_EVEX_0F383B,
1470   PREFIX_EVEX_0F383C,
1471   PREFIX_EVEX_0F383D,
1472   PREFIX_EVEX_0F383E,
1473   PREFIX_EVEX_0F383F,
1474   PREFIX_EVEX_0F3840,
1475   PREFIX_EVEX_0F3842,
1476   PREFIX_EVEX_0F3843,
1477   PREFIX_EVEX_0F3844,
1478   PREFIX_EVEX_0F3845,
1479   PREFIX_EVEX_0F3846,
1480   PREFIX_EVEX_0F3847,
1481   PREFIX_EVEX_0F384C,
1482   PREFIX_EVEX_0F384D,
1483   PREFIX_EVEX_0F384E,
1484   PREFIX_EVEX_0F384F,
1485   PREFIX_EVEX_0F3858,
1486   PREFIX_EVEX_0F3859,
1487   PREFIX_EVEX_0F385A,
1488   PREFIX_EVEX_0F385B,
1489   PREFIX_EVEX_0F3864,
1490   PREFIX_EVEX_0F3865,
1491   PREFIX_EVEX_0F3866,
1492   PREFIX_EVEX_0F3875,
1493   PREFIX_EVEX_0F3876,
1494   PREFIX_EVEX_0F3877,
1495   PREFIX_EVEX_0F3878,
1496   PREFIX_EVEX_0F3879,
1497   PREFIX_EVEX_0F387A,
1498   PREFIX_EVEX_0F387B,
1499   PREFIX_EVEX_0F387C,
1500   PREFIX_EVEX_0F387D,
1501   PREFIX_EVEX_0F387E,
1502   PREFIX_EVEX_0F387F,
1503   PREFIX_EVEX_0F3883,
1504   PREFIX_EVEX_0F3888,
1505   PREFIX_EVEX_0F3889,
1506   PREFIX_EVEX_0F388A,
1507   PREFIX_EVEX_0F388B,
1508   PREFIX_EVEX_0F388D,
1509   PREFIX_EVEX_0F3890,
1510   PREFIX_EVEX_0F3891,
1511   PREFIX_EVEX_0F3892,
1512   PREFIX_EVEX_0F3893,
1513   PREFIX_EVEX_0F3896,
1514   PREFIX_EVEX_0F3897,
1515   PREFIX_EVEX_0F3898,
1516   PREFIX_EVEX_0F3899,
1517   PREFIX_EVEX_0F389A,
1518   PREFIX_EVEX_0F389B,
1519   PREFIX_EVEX_0F389C,
1520   PREFIX_EVEX_0F389D,
1521   PREFIX_EVEX_0F389E,
1522   PREFIX_EVEX_0F389F,
1523   PREFIX_EVEX_0F38A0,
1524   PREFIX_EVEX_0F38A1,
1525   PREFIX_EVEX_0F38A2,
1526   PREFIX_EVEX_0F38A3,
1527   PREFIX_EVEX_0F38A6,
1528   PREFIX_EVEX_0F38A7,
1529   PREFIX_EVEX_0F38A8,
1530   PREFIX_EVEX_0F38A9,
1531   PREFIX_EVEX_0F38AA,
1532   PREFIX_EVEX_0F38AB,
1533   PREFIX_EVEX_0F38AC,
1534   PREFIX_EVEX_0F38AD,
1535   PREFIX_EVEX_0F38AE,
1536   PREFIX_EVEX_0F38AF,
1537   PREFIX_EVEX_0F38B4,
1538   PREFIX_EVEX_0F38B5,
1539   PREFIX_EVEX_0F38B6,
1540   PREFIX_EVEX_0F38B7,
1541   PREFIX_EVEX_0F38B8,
1542   PREFIX_EVEX_0F38B9,
1543   PREFIX_EVEX_0F38BA,
1544   PREFIX_EVEX_0F38BB,
1545   PREFIX_EVEX_0F38BC,
1546   PREFIX_EVEX_0F38BD,
1547   PREFIX_EVEX_0F38BE,
1548   PREFIX_EVEX_0F38BF,
1549   PREFIX_EVEX_0F38C4,
1550   PREFIX_EVEX_0F38C6_REG_1,
1551   PREFIX_EVEX_0F38C6_REG_2,
1552   PREFIX_EVEX_0F38C6_REG_5,
1553   PREFIX_EVEX_0F38C6_REG_6,
1554   PREFIX_EVEX_0F38C7_REG_1,
1555   PREFIX_EVEX_0F38C7_REG_2,
1556   PREFIX_EVEX_0F38C7_REG_5,
1557   PREFIX_EVEX_0F38C7_REG_6,
1558   PREFIX_EVEX_0F38C8,
1559   PREFIX_EVEX_0F38CA,
1560   PREFIX_EVEX_0F38CB,
1561   PREFIX_EVEX_0F38CC,
1562   PREFIX_EVEX_0F38CD,
1563
1564   PREFIX_EVEX_0F3A00,
1565   PREFIX_EVEX_0F3A01,
1566   PREFIX_EVEX_0F3A03,
1567   PREFIX_EVEX_0F3A04,
1568   PREFIX_EVEX_0F3A05,
1569   PREFIX_EVEX_0F3A08,
1570   PREFIX_EVEX_0F3A09,
1571   PREFIX_EVEX_0F3A0A,
1572   PREFIX_EVEX_0F3A0B,
1573   PREFIX_EVEX_0F3A0F,
1574   PREFIX_EVEX_0F3A14,
1575   PREFIX_EVEX_0F3A15,
1576   PREFIX_EVEX_0F3A16,
1577   PREFIX_EVEX_0F3A17,
1578   PREFIX_EVEX_0F3A18,
1579   PREFIX_EVEX_0F3A19,
1580   PREFIX_EVEX_0F3A1A,
1581   PREFIX_EVEX_0F3A1B,
1582   PREFIX_EVEX_0F3A1D,
1583   PREFIX_EVEX_0F3A1E,
1584   PREFIX_EVEX_0F3A1F,
1585   PREFIX_EVEX_0F3A20,
1586   PREFIX_EVEX_0F3A21,
1587   PREFIX_EVEX_0F3A22,
1588   PREFIX_EVEX_0F3A23,
1589   PREFIX_EVEX_0F3A25,
1590   PREFIX_EVEX_0F3A26,
1591   PREFIX_EVEX_0F3A27,
1592   PREFIX_EVEX_0F3A38,
1593   PREFIX_EVEX_0F3A39,
1594   PREFIX_EVEX_0F3A3A,
1595   PREFIX_EVEX_0F3A3B,
1596   PREFIX_EVEX_0F3A3E,
1597   PREFIX_EVEX_0F3A3F,
1598   PREFIX_EVEX_0F3A42,
1599   PREFIX_EVEX_0F3A43,
1600   PREFIX_EVEX_0F3A50,
1601   PREFIX_EVEX_0F3A51,
1602   PREFIX_EVEX_0F3A54,
1603   PREFIX_EVEX_0F3A55,
1604   PREFIX_EVEX_0F3A56,
1605   PREFIX_EVEX_0F3A57,
1606   PREFIX_EVEX_0F3A66,
1607   PREFIX_EVEX_0F3A67
1608 };
1609
1610 enum
1611 {
1612   X86_64_06 = 0,
1613   X86_64_07,
1614   X86_64_0D,
1615   X86_64_16,
1616   X86_64_17,
1617   X86_64_1E,
1618   X86_64_1F,
1619   X86_64_27,
1620   X86_64_2F,
1621   X86_64_37,
1622   X86_64_3F,
1623   X86_64_60,
1624   X86_64_61,
1625   X86_64_62,
1626   X86_64_63,
1627   X86_64_6D,
1628   X86_64_6F,
1629   X86_64_9A,
1630   X86_64_C4,
1631   X86_64_C5,
1632   X86_64_CE,
1633   X86_64_D4,
1634   X86_64_D5,
1635   X86_64_E8,
1636   X86_64_E9,
1637   X86_64_EA,
1638   X86_64_0F01_REG_0,
1639   X86_64_0F01_REG_1,
1640   X86_64_0F01_REG_2,
1641   X86_64_0F01_REG_3
1642 };
1643
1644 enum
1645 {
1646   THREE_BYTE_0F38 = 0,
1647   THREE_BYTE_0F3A,
1648   THREE_BYTE_0F7A
1649 };
1650
1651 enum
1652 {
1653   XOP_08 = 0,
1654   XOP_09,
1655   XOP_0A
1656 };
1657
1658 enum
1659 {
1660   VEX_0F = 0,
1661   VEX_0F38,
1662   VEX_0F3A
1663 };
1664
1665 enum
1666 {
1667   EVEX_0F = 0,
1668   EVEX_0F38,
1669   EVEX_0F3A
1670 };
1671
1672 enum
1673 {
1674   VEX_LEN_0F10_P_1 = 0,
1675   VEX_LEN_0F10_P_3,
1676   VEX_LEN_0F11_P_1,
1677   VEX_LEN_0F11_P_3,
1678   VEX_LEN_0F12_P_0_M_0,
1679   VEX_LEN_0F12_P_0_M_1,
1680   VEX_LEN_0F12_P_2,
1681   VEX_LEN_0F13_M_0,
1682   VEX_LEN_0F16_P_0_M_0,
1683   VEX_LEN_0F16_P_0_M_1,
1684   VEX_LEN_0F16_P_2,
1685   VEX_LEN_0F17_M_0,
1686   VEX_LEN_0F2A_P_1,
1687   VEX_LEN_0F2A_P_3,
1688   VEX_LEN_0F2C_P_1,
1689   VEX_LEN_0F2C_P_3,
1690   VEX_LEN_0F2D_P_1,
1691   VEX_LEN_0F2D_P_3,
1692   VEX_LEN_0F2E_P_0,
1693   VEX_LEN_0F2E_P_2,
1694   VEX_LEN_0F2F_P_0,
1695   VEX_LEN_0F2F_P_2,
1696   VEX_LEN_0F41_P_0,
1697   VEX_LEN_0F41_P_2,
1698   VEX_LEN_0F42_P_0,
1699   VEX_LEN_0F42_P_2,
1700   VEX_LEN_0F44_P_0,
1701   VEX_LEN_0F44_P_2,
1702   VEX_LEN_0F45_P_0,
1703   VEX_LEN_0F45_P_2,
1704   VEX_LEN_0F46_P_0,
1705   VEX_LEN_0F46_P_2,
1706   VEX_LEN_0F47_P_0,
1707   VEX_LEN_0F47_P_2,
1708   VEX_LEN_0F4A_P_0,
1709   VEX_LEN_0F4A_P_2,
1710   VEX_LEN_0F4B_P_0,
1711   VEX_LEN_0F4B_P_2,
1712   VEX_LEN_0F51_P_1,
1713   VEX_LEN_0F51_P_3,
1714   VEX_LEN_0F52_P_1,
1715   VEX_LEN_0F53_P_1,
1716   VEX_LEN_0F58_P_1,
1717   VEX_LEN_0F58_P_3,
1718   VEX_LEN_0F59_P_1,
1719   VEX_LEN_0F59_P_3,
1720   VEX_LEN_0F5A_P_1,
1721   VEX_LEN_0F5A_P_3,
1722   VEX_LEN_0F5C_P_1,
1723   VEX_LEN_0F5C_P_3,
1724   VEX_LEN_0F5D_P_1,
1725   VEX_LEN_0F5D_P_3,
1726   VEX_LEN_0F5E_P_1,
1727   VEX_LEN_0F5E_P_3,
1728   VEX_LEN_0F5F_P_1,
1729   VEX_LEN_0F5F_P_3,
1730   VEX_LEN_0F6E_P_2,
1731   VEX_LEN_0F7E_P_1,
1732   VEX_LEN_0F7E_P_2,
1733   VEX_LEN_0F90_P_0,
1734   VEX_LEN_0F90_P_2,
1735   VEX_LEN_0F91_P_0,
1736   VEX_LEN_0F91_P_2,
1737   VEX_LEN_0F92_P_0,
1738   VEX_LEN_0F92_P_2,
1739   VEX_LEN_0F92_P_3,
1740   VEX_LEN_0F93_P_0,
1741   VEX_LEN_0F93_P_2,
1742   VEX_LEN_0F93_P_3,
1743   VEX_LEN_0F98_P_0,
1744   VEX_LEN_0F98_P_2,
1745   VEX_LEN_0F99_P_0,
1746   VEX_LEN_0F99_P_2,
1747   VEX_LEN_0FAE_R_2_M_0,
1748   VEX_LEN_0FAE_R_3_M_0,
1749   VEX_LEN_0FC2_P_1,
1750   VEX_LEN_0FC2_P_3,
1751   VEX_LEN_0FC4_P_2,
1752   VEX_LEN_0FC5_P_2,
1753   VEX_LEN_0FD6_P_2,
1754   VEX_LEN_0FF7_P_2,
1755   VEX_LEN_0F3816_P_2,
1756   VEX_LEN_0F3819_P_2,
1757   VEX_LEN_0F381A_P_2_M_0,
1758   VEX_LEN_0F3836_P_2,
1759   VEX_LEN_0F3841_P_2,
1760   VEX_LEN_0F385A_P_2_M_0,
1761   VEX_LEN_0F38DB_P_2,
1762   VEX_LEN_0F38DC_P_2,
1763   VEX_LEN_0F38DD_P_2,
1764   VEX_LEN_0F38DE_P_2,
1765   VEX_LEN_0F38DF_P_2,
1766   VEX_LEN_0F38F2_P_0,
1767   VEX_LEN_0F38F3_R_1_P_0,
1768   VEX_LEN_0F38F3_R_2_P_0,
1769   VEX_LEN_0F38F3_R_3_P_0,
1770   VEX_LEN_0F38F5_P_0,
1771   VEX_LEN_0F38F5_P_1,
1772   VEX_LEN_0F38F5_P_3,
1773   VEX_LEN_0F38F6_P_3,
1774   VEX_LEN_0F38F7_P_0,
1775   VEX_LEN_0F38F7_P_1,
1776   VEX_LEN_0F38F7_P_2,
1777   VEX_LEN_0F38F7_P_3,
1778   VEX_LEN_0F3A00_P_2,
1779   VEX_LEN_0F3A01_P_2,
1780   VEX_LEN_0F3A06_P_2,
1781   VEX_LEN_0F3A0A_P_2,
1782   VEX_LEN_0F3A0B_P_2,
1783   VEX_LEN_0F3A14_P_2,
1784   VEX_LEN_0F3A15_P_2,
1785   VEX_LEN_0F3A16_P_2,
1786   VEX_LEN_0F3A17_P_2,
1787   VEX_LEN_0F3A18_P_2,
1788   VEX_LEN_0F3A19_P_2,
1789   VEX_LEN_0F3A20_P_2,
1790   VEX_LEN_0F3A21_P_2,
1791   VEX_LEN_0F3A22_P_2,
1792   VEX_LEN_0F3A30_P_2,
1793   VEX_LEN_0F3A31_P_2,
1794   VEX_LEN_0F3A32_P_2,
1795   VEX_LEN_0F3A33_P_2,
1796   VEX_LEN_0F3A38_P_2,
1797   VEX_LEN_0F3A39_P_2,
1798   VEX_LEN_0F3A41_P_2,
1799   VEX_LEN_0F3A44_P_2,
1800   VEX_LEN_0F3A46_P_2,
1801   VEX_LEN_0F3A60_P_2,
1802   VEX_LEN_0F3A61_P_2,
1803   VEX_LEN_0F3A62_P_2,
1804   VEX_LEN_0F3A63_P_2,
1805   VEX_LEN_0F3A6A_P_2,
1806   VEX_LEN_0F3A6B_P_2,
1807   VEX_LEN_0F3A6E_P_2,
1808   VEX_LEN_0F3A6F_P_2,
1809   VEX_LEN_0F3A7A_P_2,
1810   VEX_LEN_0F3A7B_P_2,
1811   VEX_LEN_0F3A7E_P_2,
1812   VEX_LEN_0F3A7F_P_2,
1813   VEX_LEN_0F3ADF_P_2,
1814   VEX_LEN_0F3AF0_P_3,
1815   VEX_LEN_0FXOP_08_CC,
1816   VEX_LEN_0FXOP_08_CD,
1817   VEX_LEN_0FXOP_08_CE,
1818   VEX_LEN_0FXOP_08_CF,
1819   VEX_LEN_0FXOP_08_EC,
1820   VEX_LEN_0FXOP_08_ED,
1821   VEX_LEN_0FXOP_08_EE,
1822   VEX_LEN_0FXOP_08_EF,
1823   VEX_LEN_0FXOP_09_80,
1824   VEX_LEN_0FXOP_09_81
1825 };
1826
1827 enum
1828 {
1829   VEX_W_0F10_P_0 = 0,
1830   VEX_W_0F10_P_1,
1831   VEX_W_0F10_P_2,
1832   VEX_W_0F10_P_3,
1833   VEX_W_0F11_P_0,
1834   VEX_W_0F11_P_1,
1835   VEX_W_0F11_P_2,
1836   VEX_W_0F11_P_3,
1837   VEX_W_0F12_P_0_M_0,
1838   VEX_W_0F12_P_0_M_1,
1839   VEX_W_0F12_P_1,
1840   VEX_W_0F12_P_2,
1841   VEX_W_0F12_P_3,
1842   VEX_W_0F13_M_0,
1843   VEX_W_0F14,
1844   VEX_W_0F15,
1845   VEX_W_0F16_P_0_M_0,
1846   VEX_W_0F16_P_0_M_1,
1847   VEX_W_0F16_P_1,
1848   VEX_W_0F16_P_2,
1849   VEX_W_0F17_M_0,
1850   VEX_W_0F28,
1851   VEX_W_0F29,
1852   VEX_W_0F2B_M_0,
1853   VEX_W_0F2E_P_0,
1854   VEX_W_0F2E_P_2,
1855   VEX_W_0F2F_P_0,
1856   VEX_W_0F2F_P_2,
1857   VEX_W_0F41_P_0_LEN_1,
1858   VEX_W_0F41_P_2_LEN_1,
1859   VEX_W_0F42_P_0_LEN_1,
1860   VEX_W_0F42_P_2_LEN_1,
1861   VEX_W_0F44_P_0_LEN_0,
1862   VEX_W_0F44_P_2_LEN_0,
1863   VEX_W_0F45_P_0_LEN_1,
1864   VEX_W_0F45_P_2_LEN_1,
1865   VEX_W_0F46_P_0_LEN_1,
1866   VEX_W_0F46_P_2_LEN_1,
1867   VEX_W_0F47_P_0_LEN_1,
1868   VEX_W_0F47_P_2_LEN_1,
1869   VEX_W_0F4A_P_0_LEN_1,
1870   VEX_W_0F4A_P_2_LEN_1,
1871   VEX_W_0F4B_P_0_LEN_1,
1872   VEX_W_0F4B_P_2_LEN_1,
1873   VEX_W_0F50_M_0,
1874   VEX_W_0F51_P_0,
1875   VEX_W_0F51_P_1,
1876   VEX_W_0F51_P_2,
1877   VEX_W_0F51_P_3,
1878   VEX_W_0F52_P_0,
1879   VEX_W_0F52_P_1,
1880   VEX_W_0F53_P_0,
1881   VEX_W_0F53_P_1,
1882   VEX_W_0F58_P_0,
1883   VEX_W_0F58_P_1,
1884   VEX_W_0F58_P_2,
1885   VEX_W_0F58_P_3,
1886   VEX_W_0F59_P_0,
1887   VEX_W_0F59_P_1,
1888   VEX_W_0F59_P_2,
1889   VEX_W_0F59_P_3,
1890   VEX_W_0F5A_P_0,
1891   VEX_W_0F5A_P_1,
1892   VEX_W_0F5A_P_3,
1893   VEX_W_0F5B_P_0,
1894   VEX_W_0F5B_P_1,
1895   VEX_W_0F5B_P_2,
1896   VEX_W_0F5C_P_0,
1897   VEX_W_0F5C_P_1,
1898   VEX_W_0F5C_P_2,
1899   VEX_W_0F5C_P_3,
1900   VEX_W_0F5D_P_0,
1901   VEX_W_0F5D_P_1,
1902   VEX_W_0F5D_P_2,
1903   VEX_W_0F5D_P_3,
1904   VEX_W_0F5E_P_0,
1905   VEX_W_0F5E_P_1,
1906   VEX_W_0F5E_P_2,
1907   VEX_W_0F5E_P_3,
1908   VEX_W_0F5F_P_0,
1909   VEX_W_0F5F_P_1,
1910   VEX_W_0F5F_P_2,
1911   VEX_W_0F5F_P_3,
1912   VEX_W_0F60_P_2,
1913   VEX_W_0F61_P_2,
1914   VEX_W_0F62_P_2,
1915   VEX_W_0F63_P_2,
1916   VEX_W_0F64_P_2,
1917   VEX_W_0F65_P_2,
1918   VEX_W_0F66_P_2,
1919   VEX_W_0F67_P_2,
1920   VEX_W_0F68_P_2,
1921   VEX_W_0F69_P_2,
1922   VEX_W_0F6A_P_2,
1923   VEX_W_0F6B_P_2,
1924   VEX_W_0F6C_P_2,
1925   VEX_W_0F6D_P_2,
1926   VEX_W_0F6F_P_1,
1927   VEX_W_0F6F_P_2,
1928   VEX_W_0F70_P_1,
1929   VEX_W_0F70_P_2,
1930   VEX_W_0F70_P_3,
1931   VEX_W_0F71_R_2_P_2,
1932   VEX_W_0F71_R_4_P_2,
1933   VEX_W_0F71_R_6_P_2,
1934   VEX_W_0F72_R_2_P_2,
1935   VEX_W_0F72_R_4_P_2,
1936   VEX_W_0F72_R_6_P_2,
1937   VEX_W_0F73_R_2_P_2,
1938   VEX_W_0F73_R_3_P_2,
1939   VEX_W_0F73_R_6_P_2,
1940   VEX_W_0F73_R_7_P_2,
1941   VEX_W_0F74_P_2,
1942   VEX_W_0F75_P_2,
1943   VEX_W_0F76_P_2,
1944   VEX_W_0F77_P_0,
1945   VEX_W_0F7C_P_2,
1946   VEX_W_0F7C_P_3,
1947   VEX_W_0F7D_P_2,
1948   VEX_W_0F7D_P_3,
1949   VEX_W_0F7E_P_1,
1950   VEX_W_0F7F_P_1,
1951   VEX_W_0F7F_P_2,
1952   VEX_W_0F90_P_0_LEN_0,
1953   VEX_W_0F90_P_2_LEN_0,
1954   VEX_W_0F91_P_0_LEN_0,
1955   VEX_W_0F91_P_2_LEN_0,
1956   VEX_W_0F92_P_0_LEN_0,
1957   VEX_W_0F92_P_2_LEN_0,
1958   VEX_W_0F92_P_3_LEN_0,
1959   VEX_W_0F93_P_0_LEN_0,
1960   VEX_W_0F93_P_2_LEN_0,
1961   VEX_W_0F93_P_3_LEN_0,
1962   VEX_W_0F98_P_0_LEN_0,
1963   VEX_W_0F98_P_2_LEN_0,
1964   VEX_W_0F99_P_0_LEN_0,
1965   VEX_W_0F99_P_2_LEN_0,
1966   VEX_W_0FAE_R_2_M_0,
1967   VEX_W_0FAE_R_3_M_0,
1968   VEX_W_0FC2_P_0,
1969   VEX_W_0FC2_P_1,
1970   VEX_W_0FC2_P_2,
1971   VEX_W_0FC2_P_3,
1972   VEX_W_0FC4_P_2,
1973   VEX_W_0FC5_P_2,
1974   VEX_W_0FD0_P_2,
1975   VEX_W_0FD0_P_3,
1976   VEX_W_0FD1_P_2,
1977   VEX_W_0FD2_P_2,
1978   VEX_W_0FD3_P_2,
1979   VEX_W_0FD4_P_2,
1980   VEX_W_0FD5_P_2,
1981   VEX_W_0FD6_P_2,
1982   VEX_W_0FD7_P_2_M_1,
1983   VEX_W_0FD8_P_2,
1984   VEX_W_0FD9_P_2,
1985   VEX_W_0FDA_P_2,
1986   VEX_W_0FDB_P_2,
1987   VEX_W_0FDC_P_2,
1988   VEX_W_0FDD_P_2,
1989   VEX_W_0FDE_P_2,
1990   VEX_W_0FDF_P_2,
1991   VEX_W_0FE0_P_2,
1992   VEX_W_0FE1_P_2,
1993   VEX_W_0FE2_P_2,
1994   VEX_W_0FE3_P_2,
1995   VEX_W_0FE4_P_2,
1996   VEX_W_0FE5_P_2,
1997   VEX_W_0FE6_P_1,
1998   VEX_W_0FE6_P_2,
1999   VEX_W_0FE6_P_3,
2000   VEX_W_0FE7_P_2_M_0,
2001   VEX_W_0FE8_P_2,
2002   VEX_W_0FE9_P_2,
2003   VEX_W_0FEA_P_2,
2004   VEX_W_0FEB_P_2,
2005   VEX_W_0FEC_P_2,
2006   VEX_W_0FED_P_2,
2007   VEX_W_0FEE_P_2,
2008   VEX_W_0FEF_P_2,
2009   VEX_W_0FF0_P_3_M_0,
2010   VEX_W_0FF1_P_2,
2011   VEX_W_0FF2_P_2,
2012   VEX_W_0FF3_P_2,
2013   VEX_W_0FF4_P_2,
2014   VEX_W_0FF5_P_2,
2015   VEX_W_0FF6_P_2,
2016   VEX_W_0FF7_P_2,
2017   VEX_W_0FF8_P_2,
2018   VEX_W_0FF9_P_2,
2019   VEX_W_0FFA_P_2,
2020   VEX_W_0FFB_P_2,
2021   VEX_W_0FFC_P_2,
2022   VEX_W_0FFD_P_2,
2023   VEX_W_0FFE_P_2,
2024   VEX_W_0F3800_P_2,
2025   VEX_W_0F3801_P_2,
2026   VEX_W_0F3802_P_2,
2027   VEX_W_0F3803_P_2,
2028   VEX_W_0F3804_P_2,
2029   VEX_W_0F3805_P_2,
2030   VEX_W_0F3806_P_2,
2031   VEX_W_0F3807_P_2,
2032   VEX_W_0F3808_P_2,
2033   VEX_W_0F3809_P_2,
2034   VEX_W_0F380A_P_2,
2035   VEX_W_0F380B_P_2,
2036   VEX_W_0F380C_P_2,
2037   VEX_W_0F380D_P_2,
2038   VEX_W_0F380E_P_2,
2039   VEX_W_0F380F_P_2,
2040   VEX_W_0F3816_P_2,
2041   VEX_W_0F3817_P_2,
2042   VEX_W_0F3818_P_2,
2043   VEX_W_0F3819_P_2,
2044   VEX_W_0F381A_P_2_M_0,
2045   VEX_W_0F381C_P_2,
2046   VEX_W_0F381D_P_2,
2047   VEX_W_0F381E_P_2,
2048   VEX_W_0F3820_P_2,
2049   VEX_W_0F3821_P_2,
2050   VEX_W_0F3822_P_2,
2051   VEX_W_0F3823_P_2,
2052   VEX_W_0F3824_P_2,
2053   VEX_W_0F3825_P_2,
2054   VEX_W_0F3828_P_2,
2055   VEX_W_0F3829_P_2,
2056   VEX_W_0F382A_P_2_M_0,
2057   VEX_W_0F382B_P_2,
2058   VEX_W_0F382C_P_2_M_0,
2059   VEX_W_0F382D_P_2_M_0,
2060   VEX_W_0F382E_P_2_M_0,
2061   VEX_W_0F382F_P_2_M_0,
2062   VEX_W_0F3830_P_2,
2063   VEX_W_0F3831_P_2,
2064   VEX_W_0F3832_P_2,
2065   VEX_W_0F3833_P_2,
2066   VEX_W_0F3834_P_2,
2067   VEX_W_0F3835_P_2,
2068   VEX_W_0F3836_P_2,
2069   VEX_W_0F3837_P_2,
2070   VEX_W_0F3838_P_2,
2071   VEX_W_0F3839_P_2,
2072   VEX_W_0F383A_P_2,
2073   VEX_W_0F383B_P_2,
2074   VEX_W_0F383C_P_2,
2075   VEX_W_0F383D_P_2,
2076   VEX_W_0F383E_P_2,
2077   VEX_W_0F383F_P_2,
2078   VEX_W_0F3840_P_2,
2079   VEX_W_0F3841_P_2,
2080   VEX_W_0F3846_P_2,
2081   VEX_W_0F3858_P_2,
2082   VEX_W_0F3859_P_2,
2083   VEX_W_0F385A_P_2_M_0,
2084   VEX_W_0F3878_P_2,
2085   VEX_W_0F3879_P_2,
2086   VEX_W_0F38DB_P_2,
2087   VEX_W_0F38DC_P_2,
2088   VEX_W_0F38DD_P_2,
2089   VEX_W_0F38DE_P_2,
2090   VEX_W_0F38DF_P_2,
2091   VEX_W_0F3A00_P_2,
2092   VEX_W_0F3A01_P_2,
2093   VEX_W_0F3A02_P_2,
2094   VEX_W_0F3A04_P_2,
2095   VEX_W_0F3A05_P_2,
2096   VEX_W_0F3A06_P_2,
2097   VEX_W_0F3A08_P_2,
2098   VEX_W_0F3A09_P_2,
2099   VEX_W_0F3A0A_P_2,
2100   VEX_W_0F3A0B_P_2,
2101   VEX_W_0F3A0C_P_2,
2102   VEX_W_0F3A0D_P_2,
2103   VEX_W_0F3A0E_P_2,
2104   VEX_W_0F3A0F_P_2,
2105   VEX_W_0F3A14_P_2,
2106   VEX_W_0F3A15_P_2,
2107   VEX_W_0F3A18_P_2,
2108   VEX_W_0F3A19_P_2,
2109   VEX_W_0F3A20_P_2,
2110   VEX_W_0F3A21_P_2,
2111   VEX_W_0F3A30_P_2_LEN_0,
2112   VEX_W_0F3A31_P_2_LEN_0,
2113   VEX_W_0F3A32_P_2_LEN_0,
2114   VEX_W_0F3A33_P_2_LEN_0,
2115   VEX_W_0F3A38_P_2,
2116   VEX_W_0F3A39_P_2,
2117   VEX_W_0F3A40_P_2,
2118   VEX_W_0F3A41_P_2,
2119   VEX_W_0F3A42_P_2,
2120   VEX_W_0F3A44_P_2,
2121   VEX_W_0F3A46_P_2,
2122   VEX_W_0F3A48_P_2,
2123   VEX_W_0F3A49_P_2,
2124   VEX_W_0F3A4A_P_2,
2125   VEX_W_0F3A4B_P_2,
2126   VEX_W_0F3A4C_P_2,
2127   VEX_W_0F3A60_P_2,
2128   VEX_W_0F3A61_P_2,
2129   VEX_W_0F3A62_P_2,
2130   VEX_W_0F3A63_P_2,
2131   VEX_W_0F3ADF_P_2,
2132
2133   EVEX_W_0F10_P_0,
2134   EVEX_W_0F10_P_1_M_0,
2135   EVEX_W_0F10_P_1_M_1,
2136   EVEX_W_0F10_P_2,
2137   EVEX_W_0F10_P_3_M_0,
2138   EVEX_W_0F10_P_3_M_1,
2139   EVEX_W_0F11_P_0,
2140   EVEX_W_0F11_P_1_M_0,
2141   EVEX_W_0F11_P_1_M_1,
2142   EVEX_W_0F11_P_2,
2143   EVEX_W_0F11_P_3_M_0,
2144   EVEX_W_0F11_P_3_M_1,
2145   EVEX_W_0F12_P_0_M_0,
2146   EVEX_W_0F12_P_0_M_1,
2147   EVEX_W_0F12_P_1,
2148   EVEX_W_0F12_P_2,
2149   EVEX_W_0F12_P_3,
2150   EVEX_W_0F13_P_0,
2151   EVEX_W_0F13_P_2,
2152   EVEX_W_0F14_P_0,
2153   EVEX_W_0F14_P_2,
2154   EVEX_W_0F15_P_0,
2155   EVEX_W_0F15_P_2,
2156   EVEX_W_0F16_P_0_M_0,
2157   EVEX_W_0F16_P_0_M_1,
2158   EVEX_W_0F16_P_1,
2159   EVEX_W_0F16_P_2,
2160   EVEX_W_0F17_P_0,
2161   EVEX_W_0F17_P_2,
2162   EVEX_W_0F28_P_0,
2163   EVEX_W_0F28_P_2,
2164   EVEX_W_0F29_P_0,
2165   EVEX_W_0F29_P_2,
2166   EVEX_W_0F2A_P_1,
2167   EVEX_W_0F2A_P_3,
2168   EVEX_W_0F2B_P_0,
2169   EVEX_W_0F2B_P_2,
2170   EVEX_W_0F2E_P_0,
2171   EVEX_W_0F2E_P_2,
2172   EVEX_W_0F2F_P_0,
2173   EVEX_W_0F2F_P_2,
2174   EVEX_W_0F51_P_0,
2175   EVEX_W_0F51_P_1,
2176   EVEX_W_0F51_P_2,
2177   EVEX_W_0F51_P_3,
2178   EVEX_W_0F54_P_0,
2179   EVEX_W_0F54_P_2,
2180   EVEX_W_0F55_P_0,
2181   EVEX_W_0F55_P_2,
2182   EVEX_W_0F56_P_0,
2183   EVEX_W_0F56_P_2,
2184   EVEX_W_0F57_P_0,
2185   EVEX_W_0F57_P_2,
2186   EVEX_W_0F58_P_0,
2187   EVEX_W_0F58_P_1,
2188   EVEX_W_0F58_P_2,
2189   EVEX_W_0F58_P_3,
2190   EVEX_W_0F59_P_0,
2191   EVEX_W_0F59_P_1,
2192   EVEX_W_0F59_P_2,
2193   EVEX_W_0F59_P_3,
2194   EVEX_W_0F5A_P_0,
2195   EVEX_W_0F5A_P_1,
2196   EVEX_W_0F5A_P_2,
2197   EVEX_W_0F5A_P_3,
2198   EVEX_W_0F5B_P_0,
2199   EVEX_W_0F5B_P_1,
2200   EVEX_W_0F5B_P_2,
2201   EVEX_W_0F5C_P_0,
2202   EVEX_W_0F5C_P_1,
2203   EVEX_W_0F5C_P_2,
2204   EVEX_W_0F5C_P_3,
2205   EVEX_W_0F5D_P_0,
2206   EVEX_W_0F5D_P_1,
2207   EVEX_W_0F5D_P_2,
2208   EVEX_W_0F5D_P_3,
2209   EVEX_W_0F5E_P_0,
2210   EVEX_W_0F5E_P_1,
2211   EVEX_W_0F5E_P_2,
2212   EVEX_W_0F5E_P_3,
2213   EVEX_W_0F5F_P_0,
2214   EVEX_W_0F5F_P_1,
2215   EVEX_W_0F5F_P_2,
2216   EVEX_W_0F5F_P_3,
2217   EVEX_W_0F62_P_2,
2218   EVEX_W_0F66_P_2,
2219   EVEX_W_0F6A_P_2,
2220   EVEX_W_0F6B_P_2,
2221   EVEX_W_0F6C_P_2,
2222   EVEX_W_0F6D_P_2,
2223   EVEX_W_0F6E_P_2,
2224   EVEX_W_0F6F_P_1,
2225   EVEX_W_0F6F_P_2,
2226   EVEX_W_0F6F_P_3,
2227   EVEX_W_0F70_P_2,
2228   EVEX_W_0F72_R_2_P_2,
2229   EVEX_W_0F72_R_6_P_2,
2230   EVEX_W_0F73_R_2_P_2,
2231   EVEX_W_0F73_R_6_P_2,
2232   EVEX_W_0F76_P_2,
2233   EVEX_W_0F78_P_0,
2234   EVEX_W_0F78_P_2,
2235   EVEX_W_0F79_P_0,
2236   EVEX_W_0F79_P_2,
2237   EVEX_W_0F7A_P_1,
2238   EVEX_W_0F7A_P_2,
2239   EVEX_W_0F7A_P_3,
2240   EVEX_W_0F7B_P_1,
2241   EVEX_W_0F7B_P_2,
2242   EVEX_W_0F7B_P_3,
2243   EVEX_W_0F7E_P_1,
2244   EVEX_W_0F7E_P_2,
2245   EVEX_W_0F7F_P_1,
2246   EVEX_W_0F7F_P_2,
2247   EVEX_W_0F7F_P_3,
2248   EVEX_W_0FC2_P_0,
2249   EVEX_W_0FC2_P_1,
2250   EVEX_W_0FC2_P_2,
2251   EVEX_W_0FC2_P_3,
2252   EVEX_W_0FC6_P_0,
2253   EVEX_W_0FC6_P_2,
2254   EVEX_W_0FD2_P_2,
2255   EVEX_W_0FD3_P_2,
2256   EVEX_W_0FD4_P_2,
2257   EVEX_W_0FD6_P_2,
2258   EVEX_W_0FE6_P_1,
2259   EVEX_W_0FE6_P_2,
2260   EVEX_W_0FE6_P_3,
2261   EVEX_W_0FE7_P_2,
2262   EVEX_W_0FF2_P_2,
2263   EVEX_W_0FF3_P_2,
2264   EVEX_W_0FF4_P_2,
2265   EVEX_W_0FFA_P_2,
2266   EVEX_W_0FFB_P_2,
2267   EVEX_W_0FFE_P_2,
2268   EVEX_W_0F380C_P_2,
2269   EVEX_W_0F380D_P_2,
2270   EVEX_W_0F3810_P_1,
2271   EVEX_W_0F3810_P_2,
2272   EVEX_W_0F3811_P_1,
2273   EVEX_W_0F3811_P_2,
2274   EVEX_W_0F3812_P_1,
2275   EVEX_W_0F3812_P_2,
2276   EVEX_W_0F3813_P_1,
2277   EVEX_W_0F3813_P_2,
2278   EVEX_W_0F3814_P_1,
2279   EVEX_W_0F3815_P_1,
2280   EVEX_W_0F3818_P_2,
2281   EVEX_W_0F3819_P_2,
2282   EVEX_W_0F381A_P_2,
2283   EVEX_W_0F381B_P_2,
2284   EVEX_W_0F381E_P_2,
2285   EVEX_W_0F381F_P_2,
2286   EVEX_W_0F3820_P_1,
2287   EVEX_W_0F3821_P_1,
2288   EVEX_W_0F3822_P_1,
2289   EVEX_W_0F3823_P_1,
2290   EVEX_W_0F3824_P_1,
2291   EVEX_W_0F3825_P_1,
2292   EVEX_W_0F3825_P_2,
2293   EVEX_W_0F3826_P_1,
2294   EVEX_W_0F3826_P_2,
2295   EVEX_W_0F3828_P_1,
2296   EVEX_W_0F3828_P_2,
2297   EVEX_W_0F3829_P_1,
2298   EVEX_W_0F3829_P_2,
2299   EVEX_W_0F382A_P_1,
2300   EVEX_W_0F382A_P_2,
2301   EVEX_W_0F382B_P_2,
2302   EVEX_W_0F3830_P_1,
2303   EVEX_W_0F3831_P_1,
2304   EVEX_W_0F3832_P_1,
2305   EVEX_W_0F3833_P_1,
2306   EVEX_W_0F3834_P_1,
2307   EVEX_W_0F3835_P_1,
2308   EVEX_W_0F3835_P_2,
2309   EVEX_W_0F3837_P_2,
2310   EVEX_W_0F3838_P_1,
2311   EVEX_W_0F3839_P_1,
2312   EVEX_W_0F383A_P_1,
2313   EVEX_W_0F3840_P_2,
2314   EVEX_W_0F3858_P_2,
2315   EVEX_W_0F3859_P_2,
2316   EVEX_W_0F385A_P_2,
2317   EVEX_W_0F385B_P_2,
2318   EVEX_W_0F3866_P_2,
2319   EVEX_W_0F3875_P_2,
2320   EVEX_W_0F3878_P_2,
2321   EVEX_W_0F3879_P_2,
2322   EVEX_W_0F387A_P_2,
2323   EVEX_W_0F387B_P_2,
2324   EVEX_W_0F387D_P_2,
2325   EVEX_W_0F3883_P_2,
2326   EVEX_W_0F388D_P_2,
2327   EVEX_W_0F3891_P_2,
2328   EVEX_W_0F3893_P_2,
2329   EVEX_W_0F38A1_P_2,
2330   EVEX_W_0F38A3_P_2,
2331   EVEX_W_0F38C7_R_1_P_2,
2332   EVEX_W_0F38C7_R_2_P_2,
2333   EVEX_W_0F38C7_R_5_P_2,
2334   EVEX_W_0F38C7_R_6_P_2,
2335
2336   EVEX_W_0F3A00_P_2,
2337   EVEX_W_0F3A01_P_2,
2338   EVEX_W_0F3A04_P_2,
2339   EVEX_W_0F3A05_P_2,
2340   EVEX_W_0F3A08_P_2,
2341   EVEX_W_0F3A09_P_2,
2342   EVEX_W_0F3A0A_P_2,
2343   EVEX_W_0F3A0B_P_2,
2344   EVEX_W_0F3A16_P_2,
2345   EVEX_W_0F3A18_P_2,
2346   EVEX_W_0F3A19_P_2,
2347   EVEX_W_0F3A1A_P_2,
2348   EVEX_W_0F3A1B_P_2,
2349   EVEX_W_0F3A1D_P_2,
2350   EVEX_W_0F3A21_P_2,
2351   EVEX_W_0F3A22_P_2,
2352   EVEX_W_0F3A23_P_2,
2353   EVEX_W_0F3A38_P_2,
2354   EVEX_W_0F3A39_P_2,
2355   EVEX_W_0F3A3A_P_2,
2356   EVEX_W_0F3A3B_P_2,
2357   EVEX_W_0F3A3E_P_2,
2358   EVEX_W_0F3A3F_P_2,
2359   EVEX_W_0F3A42_P_2,
2360   EVEX_W_0F3A43_P_2,
2361   EVEX_W_0F3A50_P_2,
2362   EVEX_W_0F3A51_P_2,
2363   EVEX_W_0F3A56_P_2,
2364   EVEX_W_0F3A57_P_2,
2365   EVEX_W_0F3A66_P_2,
2366   EVEX_W_0F3A67_P_2
2367 };
2368
2369 typedef void (*op_rtn) (int bytemode, int sizeflag);
2370
2371 struct dis386 {
2372   const char *name;
2373   struct
2374     {
2375       op_rtn rtn;
2376       int bytemode;
2377     } op[MAX_OPERANDS];
2378   unsigned int prefix_requirement;
2379 };
2380
2381 /* Upper case letters in the instruction names here are macros.
2382    'A' => print 'b' if no register operands or suffix_always is true
2383    'B' => print 'b' if suffix_always is true
2384    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2385           size prefix
2386    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2387           suffix_always is true
2388    'E' => print 'e' if 32-bit form of jcxz
2389    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2390    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2391    'H' => print ",pt" or ",pn" branch hint
2392    'I' => honor following macro letter even in Intel mode (implemented only
2393           for some of the macro letters)
2394    'J' => print 'l'
2395    'K' => print 'd' or 'q' if rex prefix is present.
2396    'L' => print 'l' if suffix_always is true
2397    'M' => print 'r' if intel_mnemonic is false.
2398    'N' => print 'n' if instruction has no wait "prefix"
2399    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2400    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2401           or suffix_always is true.  print 'q' if rex prefix is present.
2402    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2403           is true
2404    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2405    'S' => print 'w', 'l' or 'q' if suffix_always is true
2406    'T' => print 'q' in 64bit mode if instruction has no operand size
2407           prefix and behave as 'P' otherwise
2408    'U' => print 'q' in 64bit mode if instruction has no operand size
2409           prefix and behave as 'Q' otherwise
2410    'V' => print 'q' in 64bit mode if instruction has no operand size
2411           prefix and behave as 'S' otherwise
2412    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2413    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2414    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2415           suffix_always is true.
2416    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2417    '!' => change condition from true to false or from false to true.
2418    '%' => add 1 upper case letter to the macro.
2419    '^' => print 'w' or 'l' depending on operand size prefix or
2420           suffix_always is true (lcall/ljmp).
2421    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2422           on operand size prefix.
2423
2424    2 upper case letter macros:
2425    "XY" => print 'x' or 'y' if suffix_always is true or no register
2426            operands and no broadcast.
2427    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2428            register operands and no broadcast.
2429    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2430    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2431            or suffix_always is true
2432    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2433    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2434    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2435    "LW" => print 'd', 'q' depending on the VEX.W bit
2436    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2437            an operand size prefix, or suffix_always is true.  print
2438            'q' if rex prefix is present.
2439
2440    Many of the above letters print nothing in Intel mode.  See "putop"
2441    for the details.
2442
2443    Braces '{' and '}', and vertical bars '|', indicate alternative
2444    mnemonic strings for AT&T and Intel.  */
2445
2446 static const struct dis386 dis386[] = {
2447   /* 00 */
2448   { "addB",             { Ebh1, Gb }, 0 },
2449   { "addS",             { Evh1, Gv }, 0 },
2450   { "addB",             { Gb, EbS }, 0 },
2451   { "addS",             { Gv, EvS }, 0 },
2452   { "addB",             { AL, Ib }, 0 },
2453   { "addS",             { eAX, Iv }, 0 },
2454   { X86_64_TABLE (X86_64_06) },
2455   { X86_64_TABLE (X86_64_07) },
2456   /* 08 */
2457   { "orB",              { Ebh1, Gb }, 0 },
2458   { "orS",              { Evh1, Gv }, 0 },
2459   { "orB",              { Gb, EbS }, 0 },
2460   { "orS",              { Gv, EvS }, 0 },
2461   { "orB",              { AL, Ib }, 0 },
2462   { "orS",              { eAX, Iv }, 0 },
2463   { X86_64_TABLE (X86_64_0D) },
2464   { Bad_Opcode },       /* 0x0f extended opcode escape */
2465   /* 10 */
2466   { "adcB",             { Ebh1, Gb }, 0 },
2467   { "adcS",             { Evh1, Gv }, 0 },
2468   { "adcB",             { Gb, EbS }, 0 },
2469   { "adcS",             { Gv, EvS }, 0 },
2470   { "adcB",             { AL, Ib }, 0 },
2471   { "adcS",             { eAX, Iv }, 0 },
2472   { X86_64_TABLE (X86_64_16) },
2473   { X86_64_TABLE (X86_64_17) },
2474   /* 18 */
2475   { "sbbB",             { Ebh1, Gb }, 0 },
2476   { "sbbS",             { Evh1, Gv }, 0 },
2477   { "sbbB",             { Gb, EbS }, 0 },
2478   { "sbbS",             { Gv, EvS }, 0 },
2479   { "sbbB",             { AL, Ib }, 0 },
2480   { "sbbS",             { eAX, Iv }, 0 },
2481   { X86_64_TABLE (X86_64_1E) },
2482   { X86_64_TABLE (X86_64_1F) },
2483   /* 20 */
2484   { "andB",             { Ebh1, Gb }, 0 },
2485   { "andS",             { Evh1, Gv }, 0 },
2486   { "andB",             { Gb, EbS }, 0 },
2487   { "andS",             { Gv, EvS }, 0 },
2488   { "andB",             { AL, Ib }, 0 },
2489   { "andS",             { eAX, Iv }, 0 },
2490   { Bad_Opcode },       /* SEG ES prefix */
2491   { X86_64_TABLE (X86_64_27) },
2492   /* 28 */
2493   { "subB",             { Ebh1, Gb }, 0 },
2494   { "subS",             { Evh1, Gv }, 0 },
2495   { "subB",             { Gb, EbS }, 0 },
2496   { "subS",             { Gv, EvS }, 0 },
2497   { "subB",             { AL, Ib }, 0 },
2498   { "subS",             { eAX, Iv }, 0 },
2499   { Bad_Opcode },       /* SEG CS prefix */
2500   { X86_64_TABLE (X86_64_2F) },
2501   /* 30 */
2502   { "xorB",             { Ebh1, Gb }, 0 },
2503   { "xorS",             { Evh1, Gv }, 0 },
2504   { "xorB",             { Gb, EbS }, 0 },
2505   { "xorS",             { Gv, EvS }, 0 },
2506   { "xorB",             { AL, Ib }, 0 },
2507   { "xorS",             { eAX, Iv }, 0 },
2508   { Bad_Opcode },       /* SEG SS prefix */
2509   { X86_64_TABLE (X86_64_37) },
2510   /* 38 */
2511   { "cmpB",             { Eb, Gb }, 0 },
2512   { "cmpS",             { Ev, Gv }, 0 },
2513   { "cmpB",             { Gb, EbS }, 0 },
2514   { "cmpS",             { Gv, EvS }, 0 },
2515   { "cmpB",             { AL, Ib }, 0 },
2516   { "cmpS",             { eAX, Iv }, 0 },
2517   { Bad_Opcode },       /* SEG DS prefix */
2518   { X86_64_TABLE (X86_64_3F) },
2519   /* 40 */
2520   { "inc{S|}",          { RMeAX }, 0 },
2521   { "inc{S|}",          { RMeCX }, 0 },
2522   { "inc{S|}",          { RMeDX }, 0 },
2523   { "inc{S|}",          { RMeBX }, 0 },
2524   { "inc{S|}",          { RMeSP }, 0 },
2525   { "inc{S|}",          { RMeBP }, 0 },
2526   { "inc{S|}",          { RMeSI }, 0 },
2527   { "inc{S|}",          { RMeDI }, 0 },
2528   /* 48 */
2529   { "dec{S|}",          { RMeAX }, 0 },
2530   { "dec{S|}",          { RMeCX }, 0 },
2531   { "dec{S|}",          { RMeDX }, 0 },
2532   { "dec{S|}",          { RMeBX }, 0 },
2533   { "dec{S|}",          { RMeSP }, 0 },
2534   { "dec{S|}",          { RMeBP }, 0 },
2535   { "dec{S|}",          { RMeSI }, 0 },
2536   { "dec{S|}",          { RMeDI }, 0 },
2537   /* 50 */
2538   { "pushV",            { RMrAX }, 0 },
2539   { "pushV",            { RMrCX }, 0 },
2540   { "pushV",            { RMrDX }, 0 },
2541   { "pushV",            { RMrBX }, 0 },
2542   { "pushV",            { RMrSP }, 0 },
2543   { "pushV",            { RMrBP }, 0 },
2544   { "pushV",            { RMrSI }, 0 },
2545   { "pushV",            { RMrDI }, 0 },
2546   /* 58 */
2547   { "popV",             { RMrAX }, 0 },
2548   { "popV",             { RMrCX }, 0 },
2549   { "popV",             { RMrDX }, 0 },
2550   { "popV",             { RMrBX }, 0 },
2551   { "popV",             { RMrSP }, 0 },
2552   { "popV",             { RMrBP }, 0 },
2553   { "popV",             { RMrSI }, 0 },
2554   { "popV",             { RMrDI }, 0 },
2555   /* 60 */
2556   { X86_64_TABLE (X86_64_60) },
2557   { X86_64_TABLE (X86_64_61) },
2558   { X86_64_TABLE (X86_64_62) },
2559   { X86_64_TABLE (X86_64_63) },
2560   { Bad_Opcode },       /* seg fs */
2561   { Bad_Opcode },       /* seg gs */
2562   { Bad_Opcode },       /* op size prefix */
2563   { Bad_Opcode },       /* adr size prefix */
2564   /* 68 */
2565   { "pushT",            { sIv }, 0 },
2566   { "imulS",            { Gv, Ev, Iv }, 0 },
2567   { "pushT",            { sIbT }, 0 },
2568   { "imulS",            { Gv, Ev, sIb }, 0 },
2569   { "ins{b|}",          { Ybr, indirDX }, 0 },
2570   { X86_64_TABLE (X86_64_6D) },
2571   { "outs{b|}",         { indirDXr, Xb }, 0 },
2572   { X86_64_TABLE (X86_64_6F) },
2573   /* 70 */
2574   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2575   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2576   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2577   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2578   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2579   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2580   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2581   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2582   /* 78 */
2583   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2584   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2585   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2586   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2587   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2588   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2589   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2590   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2591   /* 80 */
2592   { REG_TABLE (REG_80) },
2593   { REG_TABLE (REG_81) },
2594   { Bad_Opcode },
2595   { REG_TABLE (REG_82) },
2596   { "testB",            { Eb, Gb }, 0 },
2597   { "testS",            { Ev, Gv }, 0 },
2598   { "xchgB",            { Ebh2, Gb }, 0 },
2599   { "xchgS",            { Evh2, Gv }, 0 },
2600   /* 88 */
2601   { "movB",             { Ebh3, Gb }, 0 },
2602   { "movS",             { Evh3, Gv }, 0 },
2603   { "movB",             { Gb, EbS }, 0 },
2604   { "movS",             { Gv, EvS }, 0 },
2605   { "movD",             { Sv, Sw }, 0 },
2606   { MOD_TABLE (MOD_8D) },
2607   { "movD",             { Sw, Sv }, 0 },
2608   { REG_TABLE (REG_8F) },
2609   /* 90 */
2610   { PREFIX_TABLE (PREFIX_90) },
2611   { "xchgS",            { RMeCX, eAX }, 0 },
2612   { "xchgS",            { RMeDX, eAX }, 0 },
2613   { "xchgS",            { RMeBX, eAX }, 0 },
2614   { "xchgS",            { RMeSP, eAX }, 0 },
2615   { "xchgS",            { RMeBP, eAX }, 0 },
2616   { "xchgS",            { RMeSI, eAX }, 0 },
2617   { "xchgS",            { RMeDI, eAX }, 0 },
2618   /* 98 */
2619   { "cW{t|}R",          { XX }, 0 },
2620   { "cR{t|}O",          { XX }, 0 },
2621   { X86_64_TABLE (X86_64_9A) },
2622   { Bad_Opcode },       /* fwait */
2623   { "pushfT",           { XX }, 0 },
2624   { "popfT",            { XX }, 0 },
2625   { "sahf",             { XX }, 0 },
2626   { "lahf",             { XX }, 0 },
2627   /* a0 */
2628   { "mov%LB",           { AL, Ob }, 0 },
2629   { "mov%LS",           { eAX, Ov }, 0 },
2630   { "mov%LB",           { Ob, AL }, 0 },
2631   { "mov%LS",           { Ov, eAX }, 0 },
2632   { "movs{b|}",         { Ybr, Xb }, 0 },
2633   { "movs{R|}",         { Yvr, Xv }, 0 },
2634   { "cmps{b|}",         { Xb, Yb }, 0 },
2635   { "cmps{R|}",         { Xv, Yv }, 0 },
2636   /* a8 */
2637   { "testB",            { AL, Ib }, 0 },
2638   { "testS",            { eAX, Iv }, 0 },
2639   { "stosB",            { Ybr, AL }, 0 },
2640   { "stosS",            { Yvr, eAX }, 0 },
2641   { "lodsB",            { ALr, Xb }, 0 },
2642   { "lodsS",            { eAXr, Xv }, 0 },
2643   { "scasB",            { AL, Yb }, 0 },
2644   { "scasS",            { eAX, Yv }, 0 },
2645   /* b0 */
2646   { "movB",             { RMAL, Ib }, 0 },
2647   { "movB",             { RMCL, Ib }, 0 },
2648   { "movB",             { RMDL, Ib }, 0 },
2649   { "movB",             { RMBL, Ib }, 0 },
2650   { "movB",             { RMAH, Ib }, 0 },
2651   { "movB",             { RMCH, Ib }, 0 },
2652   { "movB",             { RMDH, Ib }, 0 },
2653   { "movB",             { RMBH, Ib }, 0 },
2654   /* b8 */
2655   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2656   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2657   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2658   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2659   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2660   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2661   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2662   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2663   /* c0 */
2664   { REG_TABLE (REG_C0) },
2665   { REG_TABLE (REG_C1) },
2666   { "retT",             { Iw, BND }, 0 },
2667   { "retT",             { BND }, 0 },
2668   { X86_64_TABLE (X86_64_C4) },
2669   { X86_64_TABLE (X86_64_C5) },
2670   { REG_TABLE (REG_C6) },
2671   { REG_TABLE (REG_C7) },
2672   /* c8 */
2673   { "enterT",           { Iw, Ib }, 0 },
2674   { "leaveT",           { XX }, 0 },
2675   { "Jret{|f}P",        { Iw }, 0 },
2676   { "Jret{|f}P",        { XX }, 0 },
2677   { "int3",             { XX }, 0 },
2678   { "int",              { Ib }, 0 },
2679   { X86_64_TABLE (X86_64_CE) },
2680   { "iret%LP",          { XX }, 0 },
2681   /* d0 */
2682   { REG_TABLE (REG_D0) },
2683   { REG_TABLE (REG_D1) },
2684   { REG_TABLE (REG_D2) },
2685   { REG_TABLE (REG_D3) },
2686   { X86_64_TABLE (X86_64_D4) },
2687   { X86_64_TABLE (X86_64_D5) },
2688   { Bad_Opcode },
2689   { "xlat",             { DSBX }, 0 },
2690   /* d8 */
2691   { FLOAT },
2692   { FLOAT },
2693   { FLOAT },
2694   { FLOAT },
2695   { FLOAT },
2696   { FLOAT },
2697   { FLOAT },
2698   { FLOAT },
2699   /* e0 */
2700   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2701   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2702   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2703   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2704   { "inB",              { AL, Ib }, 0 },
2705   { "inG",              { zAX, Ib }, 0 },
2706   { "outB",             { Ib, AL }, 0 },
2707   { "outG",             { Ib, zAX }, 0 },
2708   /* e8 */
2709   { X86_64_TABLE (X86_64_E8) },
2710   { X86_64_TABLE (X86_64_E9) },
2711   { X86_64_TABLE (X86_64_EA) },
2712   { "jmp",              { Jb, BND }, 0 },
2713   { "inB",              { AL, indirDX }, 0 },
2714   { "inG",              { zAX, indirDX }, 0 },
2715   { "outB",             { indirDX, AL }, 0 },
2716   { "outG",             { indirDX, zAX }, 0 },
2717   /* f0 */
2718   { Bad_Opcode },       /* lock prefix */
2719   { "icebp",            { XX }, 0 },
2720   { Bad_Opcode },       /* repne */
2721   { Bad_Opcode },       /* repz */
2722   { "hlt",              { XX }, 0 },
2723   { "cmc",              { XX }, 0 },
2724   { REG_TABLE (REG_F6) },
2725   { REG_TABLE (REG_F7) },
2726   /* f8 */
2727   { "clc",              { XX }, 0 },
2728   { "stc",              { XX }, 0 },
2729   { "cli",              { XX }, 0 },
2730   { "sti",              { XX }, 0 },
2731   { "cld",              { XX }, 0 },
2732   { "std",              { XX }, 0 },
2733   { REG_TABLE (REG_FE) },
2734   { REG_TABLE (REG_FF) },
2735 };
2736
2737 static const struct dis386 dis386_twobyte[] = {
2738   /* 00 */
2739   { REG_TABLE (REG_0F00 ) },
2740   { REG_TABLE (REG_0F01 ) },
2741   { "larS",             { Gv, Ew }, 0 },
2742   { "lslS",             { Gv, Ew }, 0 },
2743   { Bad_Opcode },
2744   { "syscall",          { XX }, 0 },
2745   { "clts",             { XX }, 0 },
2746   { "sysret%LP",                { XX }, 0 },
2747   /* 08 */
2748   { "invd",             { XX }, 0 },
2749   { "wbinvd",           { XX }, 0 },
2750   { Bad_Opcode },
2751   { "ud2",              { XX }, 0 },
2752   { Bad_Opcode },
2753   { REG_TABLE (REG_0F0D) },
2754   { "femms",            { XX }, 0 },
2755   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2756   /* 10 */
2757   { PREFIX_TABLE (PREFIX_0F10) },
2758   { PREFIX_TABLE (PREFIX_0F11) },
2759   { PREFIX_TABLE (PREFIX_0F12) },
2760   { MOD_TABLE (MOD_0F13) },
2761   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2762   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2763   { PREFIX_TABLE (PREFIX_0F16) },
2764   { MOD_TABLE (MOD_0F17) },
2765   /* 18 */
2766   { REG_TABLE (REG_0F18) },
2767   { "nopQ",             { Ev }, 0 },
2768   { PREFIX_TABLE (PREFIX_0F1A) },
2769   { PREFIX_TABLE (PREFIX_0F1B) },
2770   { "nopQ",             { Ev }, 0 },
2771   { "nopQ",             { Ev }, 0 },
2772   { "nopQ",             { Ev }, 0 },
2773   { "nopQ",             { Ev }, 0 },
2774   /* 20 */
2775   { "movZ",             { Rm, Cm }, 0 },
2776   { "movZ",             { Rm, Dm }, 0 },
2777   { "movZ",             { Cm, Rm }, 0 },
2778   { "movZ",             { Dm, Rm }, 0 },
2779   { MOD_TABLE (MOD_0F24) },
2780   { Bad_Opcode },
2781   { MOD_TABLE (MOD_0F26) },
2782   { Bad_Opcode },
2783   /* 28 */
2784   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2785   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2786   { PREFIX_TABLE (PREFIX_0F2A) },
2787   { PREFIX_TABLE (PREFIX_0F2B) },
2788   { PREFIX_TABLE (PREFIX_0F2C) },
2789   { PREFIX_TABLE (PREFIX_0F2D) },
2790   { PREFIX_TABLE (PREFIX_0F2E) },
2791   { PREFIX_TABLE (PREFIX_0F2F) },
2792   /* 30 */
2793   { "wrmsr",            { XX }, 0 },
2794   { "rdtsc",            { XX }, 0 },
2795   { "rdmsr",            { XX }, 0 },
2796   { "rdpmc",            { XX }, 0 },
2797   { "sysenter",         { XX }, 0 },
2798   { "sysexit",          { XX }, 0 },
2799   { Bad_Opcode },
2800   { "getsec",           { XX }, 0 },
2801   /* 38 */
2802   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2803   { Bad_Opcode },
2804   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2805   { Bad_Opcode },
2806   { Bad_Opcode },
2807   { Bad_Opcode },
2808   { Bad_Opcode },
2809   { Bad_Opcode },
2810   /* 40 */
2811   { "cmovoS",           { Gv, Ev }, 0 },
2812   { "cmovnoS",          { Gv, Ev }, 0 },
2813   { "cmovbS",           { Gv, Ev }, 0 },
2814   { "cmovaeS",          { Gv, Ev }, 0 },
2815   { "cmoveS",           { Gv, Ev }, 0 },
2816   { "cmovneS",          { Gv, Ev }, 0 },
2817   { "cmovbeS",          { Gv, Ev }, 0 },
2818   { "cmovaS",           { Gv, Ev }, 0 },
2819   /* 48 */
2820   { "cmovsS",           { Gv, Ev }, 0 },
2821   { "cmovnsS",          { Gv, Ev }, 0 },
2822   { "cmovpS",           { Gv, Ev }, 0 },
2823   { "cmovnpS",          { Gv, Ev }, 0 },
2824   { "cmovlS",           { Gv, Ev }, 0 },
2825   { "cmovgeS",          { Gv, Ev }, 0 },
2826   { "cmovleS",          { Gv, Ev }, 0 },
2827   { "cmovgS",           { Gv, Ev }, 0 },
2828   /* 50 */
2829   { MOD_TABLE (MOD_0F51) },
2830   { PREFIX_TABLE (PREFIX_0F51) },
2831   { PREFIX_TABLE (PREFIX_0F52) },
2832   { PREFIX_TABLE (PREFIX_0F53) },
2833   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2834   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2835   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2836   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2837   /* 58 */
2838   { PREFIX_TABLE (PREFIX_0F58) },
2839   { PREFIX_TABLE (PREFIX_0F59) },
2840   { PREFIX_TABLE (PREFIX_0F5A) },
2841   { PREFIX_TABLE (PREFIX_0F5B) },
2842   { PREFIX_TABLE (PREFIX_0F5C) },
2843   { PREFIX_TABLE (PREFIX_0F5D) },
2844   { PREFIX_TABLE (PREFIX_0F5E) },
2845   { PREFIX_TABLE (PREFIX_0F5F) },
2846   /* 60 */
2847   { PREFIX_TABLE (PREFIX_0F60) },
2848   { PREFIX_TABLE (PREFIX_0F61) },
2849   { PREFIX_TABLE (PREFIX_0F62) },
2850   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2851   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2852   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2853   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2854   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2855   /* 68 */
2856   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2857   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2858   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2859   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2860   { PREFIX_TABLE (PREFIX_0F6C) },
2861   { PREFIX_TABLE (PREFIX_0F6D) },
2862   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2863   { PREFIX_TABLE (PREFIX_0F6F) },
2864   /* 70 */
2865   { PREFIX_TABLE (PREFIX_0F70) },
2866   { REG_TABLE (REG_0F71) },
2867   { REG_TABLE (REG_0F72) },
2868   { REG_TABLE (REG_0F73) },
2869   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2870   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2871   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2872   { "emms",             { XX }, PREFIX_OPCODE },
2873   /* 78 */
2874   { PREFIX_TABLE (PREFIX_0F78) },
2875   { PREFIX_TABLE (PREFIX_0F79) },
2876   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2877   { Bad_Opcode },
2878   { PREFIX_TABLE (PREFIX_0F7C) },
2879   { PREFIX_TABLE (PREFIX_0F7D) },
2880   { PREFIX_TABLE (PREFIX_0F7E) },
2881   { PREFIX_TABLE (PREFIX_0F7F) },
2882   /* 80 */
2883   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2884   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2885   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2886   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2887   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2888   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2889   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2890   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2891   /* 88 */
2892   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2893   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2894   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2895   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2896   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2897   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2898   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2899   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2900   /* 90 */
2901   { "seto",             { Eb }, 0 },
2902   { "setno",            { Eb }, 0 },
2903   { "setb",             { Eb }, 0 },
2904   { "setae",            { Eb }, 0 },
2905   { "sete",             { Eb }, 0 },
2906   { "setne",            { Eb }, 0 },
2907   { "setbe",            { Eb }, 0 },
2908   { "seta",             { Eb }, 0 },
2909   /* 98 */
2910   { "sets",             { Eb }, 0 },
2911   { "setns",            { Eb }, 0 },
2912   { "setp",             { Eb }, 0 },
2913   { "setnp",            { Eb }, 0 },
2914   { "setl",             { Eb }, 0 },
2915   { "setge",            { Eb }, 0 },
2916   { "setle",            { Eb }, 0 },
2917   { "setg",             { Eb }, 0 },
2918   /* a0 */
2919   { "pushT",            { fs }, 0 },
2920   { "popT",             { fs }, 0 },
2921   { "cpuid",            { XX }, 0 },
2922   { "btS",              { Ev, Gv }, 0 },
2923   { "shldS",            { Ev, Gv, Ib }, 0 },
2924   { "shldS",            { Ev, Gv, CL }, 0 },
2925   { REG_TABLE (REG_0FA6) },
2926   { REG_TABLE (REG_0FA7) },
2927   /* a8 */
2928   { "pushT",            { gs }, 0 },
2929   { "popT",             { gs }, 0 },
2930   { "rsm",              { XX }, 0 },
2931   { "btsS",             { Evh1, Gv }, 0 },
2932   { "shrdS",            { Ev, Gv, Ib }, 0 },
2933   { "shrdS",            { Ev, Gv, CL }, 0 },
2934   { REG_TABLE (REG_0FAE) },
2935   { "imulS",            { Gv, Ev }, 0 },
2936   /* b0 */
2937   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2938   { "cmpxchgS",         { Evh1, Gv }, 0 },
2939   { MOD_TABLE (MOD_0FB2) },
2940   { "btrS",             { Evh1, Gv }, 0 },
2941   { MOD_TABLE (MOD_0FB4) },
2942   { MOD_TABLE (MOD_0FB5) },
2943   { "movz{bR|x}",       { Gv, Eb }, 0 },
2944   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2945   /* b8 */
2946   { PREFIX_TABLE (PREFIX_0FB8) },
2947   { "ud1",              { XX }, 0 },
2948   { REG_TABLE (REG_0FBA) },
2949   { "btcS",             { Evh1, Gv }, 0 },
2950   { PREFIX_TABLE (PREFIX_0FBC) },
2951   { PREFIX_TABLE (PREFIX_0FBD) },
2952   { "movs{bR|x}",       { Gv, Eb }, 0 },
2953   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2954   /* c0 */
2955   { "xaddB",            { Ebh1, Gb }, 0 },
2956   { "xaddS",            { Evh1, Gv }, 0 },
2957   { PREFIX_TABLE (PREFIX_0FC2) },
2958   { PREFIX_TABLE (PREFIX_0FC3) },
2959   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2960   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2961   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2962   { REG_TABLE (REG_0FC7) },
2963   /* c8 */
2964   { "bswap",            { RMeAX }, 0 },
2965   { "bswap",            { RMeCX }, 0 },
2966   { "bswap",            { RMeDX }, 0 },
2967   { "bswap",            { RMeBX }, 0 },
2968   { "bswap",            { RMeSP }, 0 },
2969   { "bswap",            { RMeBP }, 0 },
2970   { "bswap",            { RMeSI }, 0 },
2971   { "bswap",            { RMeDI }, 0 },
2972   /* d0 */
2973   { PREFIX_TABLE (PREFIX_0FD0) },
2974   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2975   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2976   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2977   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2978   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2979   { PREFIX_TABLE (PREFIX_0FD6) },
2980   { MOD_TABLE (MOD_0FD7) },
2981   /* d8 */
2982   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2983   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2984   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2985   { "pand",             { MX, EM }, PREFIX_OPCODE },
2986   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2987   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2988   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2989   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2990   /* e0 */
2991   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2992   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2993   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2994   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2995   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2996   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2997   { PREFIX_TABLE (PREFIX_0FE6) },
2998   { PREFIX_TABLE (PREFIX_0FE7) },
2999   /* e8 */
3000   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3001   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3002   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3003   { "por",              { MX, EM }, PREFIX_OPCODE },
3004   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3005   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3006   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3007   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3008   /* f0 */
3009   { PREFIX_TABLE (PREFIX_0FF0) },
3010   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3011   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3012   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3013   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3014   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3015   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3016   { PREFIX_TABLE (PREFIX_0FF7) },
3017   /* f8 */
3018   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3019   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3020   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3021   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3022   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3023   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3024   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3025   { Bad_Opcode },
3026 };
3027
3028 static const unsigned char onebyte_has_modrm[256] = {
3029   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3030   /*       -------------------------------        */
3031   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3032   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3033   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3034   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3035   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3036   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3037   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3038   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3039   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3040   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3041   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3042   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3043   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3044   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3045   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3046   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3047   /*       -------------------------------        */
3048   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3049 };
3050
3051 static const unsigned char twobyte_has_modrm[256] = {
3052   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3053   /*       -------------------------------        */
3054   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3055   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3056   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3057   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3058   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3059   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3060   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3061   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3062   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3063   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3064   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3065   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3066   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3067   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3068   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3069   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3070   /*       -------------------------------        */
3071   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3072 };
3073
3074 static char obuf[100];
3075 static char *obufp;
3076 static char *mnemonicendp;
3077 static char scratchbuf[100];
3078 static unsigned char *start_codep;
3079 static unsigned char *insn_codep;
3080 static unsigned char *codep;
3081 static unsigned char *end_codep;
3082 static int last_lock_prefix;
3083 static int last_repz_prefix;
3084 static int last_repnz_prefix;
3085 static int last_data_prefix;
3086 static int last_addr_prefix;
3087 static int last_rex_prefix;
3088 static int last_seg_prefix;
3089 static int fwait_prefix;
3090 /* The active segment register prefix.  */
3091 static int active_seg_prefix;
3092 #define MAX_CODE_LENGTH 15
3093 /* We can up to 14 prefixes since the maximum instruction length is
3094    15bytes.  */
3095 static int all_prefixes[MAX_CODE_LENGTH - 1];
3096 static disassemble_info *the_info;
3097 static struct
3098   {
3099     int mod;
3100     int reg;
3101     int rm;
3102   }
3103 modrm;
3104 static unsigned char need_modrm;
3105 static struct
3106   {
3107     int scale;
3108     int index;
3109     int base;
3110   }
3111 sib;
3112 static struct
3113   {
3114     int register_specifier;
3115     int length;
3116     int prefix;
3117     int w;
3118     int evex;
3119     int r;
3120     int v;
3121     int mask_register_specifier;
3122     int zeroing;
3123     int ll;
3124     int b;
3125   }
3126 vex;
3127 static unsigned char need_vex;
3128 static unsigned char need_vex_reg;
3129 static unsigned char vex_w_done;
3130
3131 struct op
3132   {
3133     const char *name;
3134     unsigned int len;
3135   };
3136
3137 /* If we are accessing mod/rm/reg without need_modrm set, then the
3138    values are stale.  Hitting this abort likely indicates that you
3139    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3140 #define MODRM_CHECK  if (!need_modrm) abort ()
3141
3142 static const char **names64;
3143 static const char **names32;
3144 static const char **names16;
3145 static const char **names8;
3146 static const char **names8rex;
3147 static const char **names_seg;
3148 static const char *index64;
3149 static const char *index32;
3150 static const char **index16;
3151 static const char **names_bnd;
3152
3153 static const char *intel_names64[] = {
3154   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3155   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3156 };
3157 static const char *intel_names32[] = {
3158   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3159   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3160 };
3161 static const char *intel_names16[] = {
3162   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3163   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3164 };
3165 static const char *intel_names8[] = {
3166   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3167 };
3168 static const char *intel_names8rex[] = {
3169   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3170   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3171 };
3172 static const char *intel_names_seg[] = {
3173   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3174 };
3175 static const char *intel_index64 = "riz";
3176 static const char *intel_index32 = "eiz";
3177 static const char *intel_index16[] = {
3178   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3179 };
3180
3181 static const char *att_names64[] = {
3182   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3183   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3184 };
3185 static const char *att_names32[] = {
3186   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3187   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3188 };
3189 static const char *att_names16[] = {
3190   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3191   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3192 };
3193 static const char *att_names8[] = {
3194   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3195 };
3196 static const char *att_names8rex[] = {
3197   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3198   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3199 };
3200 static const char *att_names_seg[] = {
3201   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3202 };
3203 static const char *att_index64 = "%riz";
3204 static const char *att_index32 = "%eiz";
3205 static const char *att_index16[] = {
3206   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3207 };
3208
3209 static const char **names_mm;
3210 static const char *intel_names_mm[] = {
3211   "mm0", "mm1", "mm2", "mm3",
3212   "mm4", "mm5", "mm6", "mm7"
3213 };
3214 static const char *att_names_mm[] = {
3215   "%mm0", "%mm1", "%mm2", "%mm3",
3216   "%mm4", "%mm5", "%mm6", "%mm7"
3217 };
3218
3219 static const char *intel_names_bnd[] = {
3220   "bnd0", "bnd1", "bnd2", "bnd3"
3221 };
3222
3223 static const char *att_names_bnd[] = {
3224   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3225 };
3226
3227 static const char **names_xmm;
3228 static const char *intel_names_xmm[] = {
3229   "xmm0", "xmm1", "xmm2", "xmm3",
3230   "xmm4", "xmm5", "xmm6", "xmm7",
3231   "xmm8", "xmm9", "xmm10", "xmm11",
3232   "xmm12", "xmm13", "xmm14", "xmm15",
3233   "xmm16", "xmm17", "xmm18", "xmm19",
3234   "xmm20", "xmm21", "xmm22", "xmm23",
3235   "xmm24", "xmm25", "xmm26", "xmm27",
3236   "xmm28", "xmm29", "xmm30", "xmm31"
3237 };
3238 static const char *att_names_xmm[] = {
3239   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3240   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3241   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3242   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3243   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3244   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3245   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3246   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3247 };
3248
3249 static const char **names_ymm;
3250 static const char *intel_names_ymm[] = {
3251   "ymm0", "ymm1", "ymm2", "ymm3",
3252   "ymm4", "ymm5", "ymm6", "ymm7",
3253   "ymm8", "ymm9", "ymm10", "ymm11",
3254   "ymm12", "ymm13", "ymm14", "ymm15",
3255   "ymm16", "ymm17", "ymm18", "ymm19",
3256   "ymm20", "ymm21", "ymm22", "ymm23",
3257   "ymm24", "ymm25", "ymm26", "ymm27",
3258   "ymm28", "ymm29", "ymm30", "ymm31"
3259 };
3260 static const char *att_names_ymm[] = {
3261   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3262   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3263   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3264   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3265   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3266   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3267   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3268   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3269 };
3270
3271 static const char **names_zmm;
3272 static const char *intel_names_zmm[] = {
3273   "zmm0", "zmm1", "zmm2", "zmm3",
3274   "zmm4", "zmm5", "zmm6", "zmm7",
3275   "zmm8", "zmm9", "zmm10", "zmm11",
3276   "zmm12", "zmm13", "zmm14", "zmm15",
3277   "zmm16", "zmm17", "zmm18", "zmm19",
3278   "zmm20", "zmm21", "zmm22", "zmm23",
3279   "zmm24", "zmm25", "zmm26", "zmm27",
3280   "zmm28", "zmm29", "zmm30", "zmm31"
3281 };
3282 static const char *att_names_zmm[] = {
3283   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3284   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3285   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3286   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3287   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3288   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3289   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3290   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3291 };
3292
3293 static const char **names_mask;
3294 static const char *intel_names_mask[] = {
3295   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3296 };
3297 static const char *att_names_mask[] = {
3298   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3299 };
3300
3301 static const char *names_rounding[] =
3302 {
3303   "{rn-sae}",
3304   "{rd-sae}",
3305   "{ru-sae}",
3306   "{rz-sae}"
3307 };
3308
3309 static const struct dis386 reg_table[][8] = {
3310   /* REG_80 */
3311   {
3312     { "addA",   { Ebh1, Ib }, 0 },
3313     { "orA",    { Ebh1, Ib }, 0 },
3314     { "adcA",   { Ebh1, Ib }, 0 },
3315     { "sbbA",   { Ebh1, Ib }, 0 },
3316     { "andA",   { Ebh1, Ib }, 0 },
3317     { "subA",   { Ebh1, Ib }, 0 },
3318     { "xorA",   { Ebh1, Ib }, 0 },
3319     { "cmpA",   { Eb, Ib }, 0 },
3320   },
3321   /* REG_81 */
3322   {
3323     { "addQ",   { Evh1, Iv }, 0 },
3324     { "orQ",    { Evh1, Iv }, 0 },
3325     { "adcQ",   { Evh1, Iv }, 0 },
3326     { "sbbQ",   { Evh1, Iv }, 0 },
3327     { "andQ",   { Evh1, Iv }, 0 },
3328     { "subQ",   { Evh1, Iv }, 0 },
3329     { "xorQ",   { Evh1, Iv }, 0 },
3330     { "cmpQ",   { Ev, Iv }, 0 },
3331   },
3332   /* REG_82 */
3333   {
3334     { "addQ",   { Evh1, sIb }, 0 },
3335     { "orQ",    { Evh1, sIb }, 0 },
3336     { "adcQ",   { Evh1, sIb }, 0 },
3337     { "sbbQ",   { Evh1, sIb }, 0 },
3338     { "andQ",   { Evh1, sIb }, 0 },
3339     { "subQ",   { Evh1, sIb }, 0 },
3340     { "xorQ",   { Evh1, sIb }, 0 },
3341     { "cmpQ",   { Ev, sIb }, 0 },
3342   },
3343   /* REG_8F */
3344   {
3345     { "popU",   { stackEv }, 0 },
3346     { XOP_8F_TABLE (XOP_09) },
3347     { Bad_Opcode },
3348     { Bad_Opcode },
3349     { Bad_Opcode },
3350     { XOP_8F_TABLE (XOP_09) },
3351   },
3352   /* REG_C0 */
3353   {
3354     { "rolA",   { Eb, Ib }, 0 },
3355     { "rorA",   { Eb, Ib }, 0 },
3356     { "rclA",   { Eb, Ib }, 0 },
3357     { "rcrA",   { Eb, Ib }, 0 },
3358     { "shlA",   { Eb, Ib }, 0 },
3359     { "shrA",   { Eb, Ib }, 0 },
3360     { Bad_Opcode },
3361     { "sarA",   { Eb, Ib }, 0 },
3362   },
3363   /* REG_C1 */
3364   {
3365     { "rolQ",   { Ev, Ib }, 0 },
3366     { "rorQ",   { Ev, Ib }, 0 },
3367     { "rclQ",   { Ev, Ib }, 0 },
3368     { "rcrQ",   { Ev, Ib }, 0 },
3369     { "shlQ",   { Ev, Ib }, 0 },
3370     { "shrQ",   { Ev, Ib }, 0 },
3371     { Bad_Opcode },
3372     { "sarQ",   { Ev, Ib }, 0 },
3373   },
3374   /* REG_C6 */
3375   {
3376     { "movA",   { Ebh3, Ib }, 0 },
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380     { Bad_Opcode },
3381     { Bad_Opcode },
3382     { Bad_Opcode },
3383     { MOD_TABLE (MOD_C6_REG_7) },
3384   },
3385   /* REG_C7 */
3386   {
3387     { "movQ",   { Evh3, Iv }, 0 },
3388     { Bad_Opcode },
3389     { Bad_Opcode },
3390     { Bad_Opcode },
3391     { Bad_Opcode },
3392     { Bad_Opcode },
3393     { Bad_Opcode },
3394     { MOD_TABLE (MOD_C7_REG_7) },
3395   },
3396   /* REG_D0 */
3397   {
3398     { "rolA",   { Eb, I1 }, 0 },
3399     { "rorA",   { Eb, I1 }, 0 },
3400     { "rclA",   { Eb, I1 }, 0 },
3401     { "rcrA",   { Eb, I1 }, 0 },
3402     { "shlA",   { Eb, I1 }, 0 },
3403     { "shrA",   { Eb, I1 }, 0 },
3404     { Bad_Opcode },
3405     { "sarA",   { Eb, I1 }, 0 },
3406   },
3407   /* REG_D1 */
3408   {
3409     { "rolQ",   { Ev, I1 }, 0 },
3410     { "rorQ",   { Ev, I1 }, 0 },
3411     { "rclQ",   { Ev, I1 }, 0 },
3412     { "rcrQ",   { Ev, I1 }, 0 },
3413     { "shlQ",   { Ev, I1 }, 0 },
3414     { "shrQ",   { Ev, I1 }, 0 },
3415     { Bad_Opcode },
3416     { "sarQ",   { Ev, I1 }, 0 },
3417   },
3418   /* REG_D2 */
3419   {
3420     { "rolA",   { Eb, CL }, 0 },
3421     { "rorA",   { Eb, CL }, 0 },
3422     { "rclA",   { Eb, CL }, 0 },
3423     { "rcrA",   { Eb, CL }, 0 },
3424     { "shlA",   { Eb, CL }, 0 },
3425     { "shrA",   { Eb, CL }, 0 },
3426     { Bad_Opcode },
3427     { "sarA",   { Eb, CL }, 0 },
3428   },
3429   /* REG_D3 */
3430   {
3431     { "rolQ",   { Ev, CL }, 0 },
3432     { "rorQ",   { Ev, CL }, 0 },
3433     { "rclQ",   { Ev, CL }, 0 },
3434     { "rcrQ",   { Ev, CL }, 0 },
3435     { "shlQ",   { Ev, CL }, 0 },
3436     { "shrQ",   { Ev, CL }, 0 },
3437     { Bad_Opcode },
3438     { "sarQ",   { Ev, CL }, 0 },
3439   },
3440   /* REG_F6 */
3441   {
3442     { "testA",  { Eb, Ib }, 0 },
3443     { Bad_Opcode },
3444     { "notA",   { Ebh1 }, 0 },
3445     { "negA",   { Ebh1 }, 0 },
3446     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3447     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3448     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3449     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3450   },
3451   /* REG_F7 */
3452   {
3453     { "testQ",  { Ev, Iv }, 0 },
3454     { Bad_Opcode },
3455     { "notQ",   { Evh1 }, 0 },
3456     { "negQ",   { Evh1 }, 0 },
3457     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3458     { "imulQ",  { Ev }, 0 },
3459     { "divQ",   { Ev }, 0 },
3460     { "idivQ",  { Ev }, 0 },
3461   },
3462   /* REG_FE */
3463   {
3464     { "incA",   { Ebh1 }, 0 },
3465     { "decA",   { Ebh1 }, 0 },
3466   },
3467   /* REG_FF */
3468   {
3469     { "incQ",   { Evh1 }, 0 },
3470     { "decQ",   { Evh1 }, 0 },
3471     { "call{T|}", { indirEv, BND }, 0 },
3472     { MOD_TABLE (MOD_FF_REG_3) },
3473     { "jmp{T|}", { indirEv, BND }, 0 },
3474     { MOD_TABLE (MOD_FF_REG_5) },
3475     { "pushU",  { stackEv }, 0 },
3476     { Bad_Opcode },
3477   },
3478   /* REG_0F00 */
3479   {
3480     { "sldtD",  { Sv }, 0 },
3481     { "strD",   { Sv }, 0 },
3482     { "lldt",   { Ew }, 0 },
3483     { "ltr",    { Ew }, 0 },
3484     { "verr",   { Ew }, 0 },
3485     { "verw",   { Ew }, 0 },
3486     { Bad_Opcode },
3487     { Bad_Opcode },
3488   },
3489   /* REG_0F01 */
3490   {
3491     { MOD_TABLE (MOD_0F01_REG_0) },
3492     { MOD_TABLE (MOD_0F01_REG_1) },
3493     { MOD_TABLE (MOD_0F01_REG_2) },
3494     { MOD_TABLE (MOD_0F01_REG_3) },
3495     { "smswD",  { Sv }, 0 },
3496     { Bad_Opcode },
3497     { "lmsw",   { Ew }, 0 },
3498     { MOD_TABLE (MOD_0F01_REG_7) },
3499   },
3500   /* REG_0F0D */
3501   {
3502     { "prefetch",       { Mb }, 0 },
3503     { "prefetchw",      { Mb }, 0 },
3504     { "prefetchwt1",    { Mb }, 0 },
3505     { "prefetch",       { Mb }, 0 },
3506     { "prefetch",       { Mb }, 0 },
3507     { "prefetch",       { Mb }, 0 },
3508     { "prefetch",       { Mb }, 0 },
3509     { "prefetch",       { Mb }, 0 },
3510   },
3511   /* REG_0F18 */
3512   {
3513     { MOD_TABLE (MOD_0F18_REG_0) },
3514     { MOD_TABLE (MOD_0F18_REG_1) },
3515     { MOD_TABLE (MOD_0F18_REG_2) },
3516     { MOD_TABLE (MOD_0F18_REG_3) },
3517     { MOD_TABLE (MOD_0F18_REG_4) },
3518     { MOD_TABLE (MOD_0F18_REG_5) },
3519     { MOD_TABLE (MOD_0F18_REG_6) },
3520     { MOD_TABLE (MOD_0F18_REG_7) },
3521   },
3522   /* REG_0F71 */
3523   {
3524     { Bad_Opcode },
3525     { Bad_Opcode },
3526     { MOD_TABLE (MOD_0F71_REG_2) },
3527     { Bad_Opcode },
3528     { MOD_TABLE (MOD_0F71_REG_4) },
3529     { Bad_Opcode },
3530     { MOD_TABLE (MOD_0F71_REG_6) },
3531   },
3532   /* REG_0F72 */
3533   {
3534     { Bad_Opcode },
3535     { Bad_Opcode },
3536     { MOD_TABLE (MOD_0F72_REG_2) },
3537     { Bad_Opcode },
3538     { MOD_TABLE (MOD_0F72_REG_4) },
3539     { Bad_Opcode },
3540     { MOD_TABLE (MOD_0F72_REG_6) },
3541   },
3542   /* REG_0F73 */
3543   {
3544     { Bad_Opcode },
3545     { Bad_Opcode },
3546     { MOD_TABLE (MOD_0F73_REG_2) },
3547     { MOD_TABLE (MOD_0F73_REG_3) },
3548     { Bad_Opcode },
3549     { Bad_Opcode },
3550     { MOD_TABLE (MOD_0F73_REG_6) },
3551     { MOD_TABLE (MOD_0F73_REG_7) },
3552   },
3553   /* REG_0FA6 */
3554   {
3555     { "montmul",        { { OP_0f07, 0 } }, 0 },
3556     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3557     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3558   },
3559   /* REG_0FA7 */
3560   {
3561     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3562     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3563     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3564     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3565     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3566     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3567   },
3568   /* REG_0FAE */
3569   {
3570     { MOD_TABLE (MOD_0FAE_REG_0) },
3571     { MOD_TABLE (MOD_0FAE_REG_1) },
3572     { MOD_TABLE (MOD_0FAE_REG_2) },
3573     { MOD_TABLE (MOD_0FAE_REG_3) },
3574     { MOD_TABLE (MOD_0FAE_REG_4) },
3575     { MOD_TABLE (MOD_0FAE_REG_5) },
3576     { MOD_TABLE (MOD_0FAE_REG_6) },
3577     { MOD_TABLE (MOD_0FAE_REG_7) },
3578   },
3579   /* REG_0FBA */
3580   {
3581     { Bad_Opcode },
3582     { Bad_Opcode },
3583     { Bad_Opcode },
3584     { Bad_Opcode },
3585     { "btQ",    { Ev, Ib }, 0 },
3586     { "btsQ",   { Evh1, Ib }, 0 },
3587     { "btrQ",   { Evh1, Ib }, 0 },
3588     { "btcQ",   { Evh1, Ib }, 0 },
3589   },
3590   /* REG_0FC7 */
3591   {
3592     { Bad_Opcode },
3593     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3594     { Bad_Opcode },
3595     { MOD_TABLE (MOD_0FC7_REG_3) },
3596     { MOD_TABLE (MOD_0FC7_REG_4) },
3597     { MOD_TABLE (MOD_0FC7_REG_5) },
3598     { MOD_TABLE (MOD_0FC7_REG_6) },
3599     { MOD_TABLE (MOD_0FC7_REG_7) },
3600   },
3601   /* REG_VEX_0F71 */
3602   {
3603     { Bad_Opcode },
3604     { Bad_Opcode },
3605     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3606     { Bad_Opcode },
3607     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3608     { Bad_Opcode },
3609     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3610   },
3611   /* REG_VEX_0F72 */
3612   {
3613     { Bad_Opcode },
3614     { Bad_Opcode },
3615     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3616     { Bad_Opcode },
3617     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3618     { Bad_Opcode },
3619     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3620   },
3621   /* REG_VEX_0F73 */
3622   {
3623     { Bad_Opcode },
3624     { Bad_Opcode },
3625     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3626     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3627     { Bad_Opcode },
3628     { Bad_Opcode },
3629     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3630     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3631   },
3632   /* REG_VEX_0FAE */
3633   {
3634     { Bad_Opcode },
3635     { Bad_Opcode },
3636     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3637     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3638   },
3639   /* REG_VEX_0F38F3 */
3640   {
3641     { Bad_Opcode },
3642     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3643     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3644     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3645   },
3646   /* REG_XOP_LWPCB */
3647   {
3648     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3649     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3650   },
3651   /* REG_XOP_LWP */
3652   {
3653     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3654     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3655   },
3656   /* REG_XOP_TBM_01 */
3657   {
3658     { Bad_Opcode },
3659     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3660     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3661     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3662     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3663     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3664     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3665     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3666   },
3667   /* REG_XOP_TBM_02 */
3668   {
3669     { Bad_Opcode },
3670     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3671     { Bad_Opcode },
3672     { Bad_Opcode },
3673     { Bad_Opcode },
3674     { Bad_Opcode },
3675     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3676   },
3677 #define NEED_REG_TABLE
3678 #include "i386-dis-evex.h"
3679 #undef NEED_REG_TABLE
3680 };
3681
3682 static const struct dis386 prefix_table[][4] = {
3683   /* PREFIX_90 */
3684   {
3685     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3686     { "pause", { XX }, 0 },
3687     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3688     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3689   },
3690
3691   /* PREFIX_0F10 */
3692   {
3693     { "movups", { XM, EXx }, PREFIX_OPCODE },
3694     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3695     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3696     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3697   },
3698
3699   /* PREFIX_0F11 */
3700   {
3701     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3702     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3703     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3704     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3705   },
3706
3707   /* PREFIX_0F12 */
3708   {
3709     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3710     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3711     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3712     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3713   },
3714
3715   /* PREFIX_0F16 */
3716   {
3717     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3718     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3719     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3720   },
3721
3722   /* PREFIX_0F1A */
3723   {
3724     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3725     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3726     { "bndmov", { Gbnd, Ebnd }, 0 },
3727     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3728   },
3729
3730   /* PREFIX_0F1B */
3731   {
3732     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3733     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3734     { "bndmov", { Ebnd, Gbnd }, 0 },
3735     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3736   },
3737
3738   /* PREFIX_0F2A */
3739   {
3740     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3741     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3742     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3743     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3744   },
3745
3746   /* PREFIX_0F2B */
3747   {
3748     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3749     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3750     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3751     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3752   },
3753
3754   /* PREFIX_0F2C */
3755   {
3756     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3757     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3758     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3759     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3760   },
3761
3762   /* PREFIX_0F2D */
3763   {
3764     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3765     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3766     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3767     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3768   },
3769
3770   /* PREFIX_0F2E */
3771   {
3772     { "ucomiss",{ XM, EXd }, 0 },
3773     { Bad_Opcode },
3774     { "ucomisd",{ XM, EXq }, 0 },
3775   },
3776
3777   /* PREFIX_0F2F */
3778   {
3779     { "comiss", { XM, EXd }, 0 },
3780     { Bad_Opcode },
3781     { "comisd", { XM, EXq }, 0 },
3782   },
3783
3784   /* PREFIX_0F51 */
3785   {
3786     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3787     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3788     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3789     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3790   },
3791
3792   /* PREFIX_0F52 */
3793   {
3794     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3795     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3796   },
3797
3798   /* PREFIX_0F53 */
3799   {
3800     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3801     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3802   },
3803
3804   /* PREFIX_0F58 */
3805   {
3806     { "addps", { XM, EXx }, PREFIX_OPCODE },
3807     { "addss", { XM, EXd }, PREFIX_OPCODE },
3808     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3809     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3810   },
3811
3812   /* PREFIX_0F59 */
3813   {
3814     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3815     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3816     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3817     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3818   },
3819
3820   /* PREFIX_0F5A */
3821   {
3822     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3823     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3824     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3825     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3826   },
3827
3828   /* PREFIX_0F5B */
3829   {
3830     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3831     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3832     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3833   },
3834
3835   /* PREFIX_0F5C */
3836   {
3837     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3838     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3839     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3840     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3841   },
3842
3843   /* PREFIX_0F5D */
3844   {
3845     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3846     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3847     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3848     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3849   },
3850
3851   /* PREFIX_0F5E */
3852   {
3853     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3854     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3855     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3856     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3857   },
3858
3859   /* PREFIX_0F5F */
3860   {
3861     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3862     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3863     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3864     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3865   },
3866
3867   /* PREFIX_0F60 */
3868   {
3869     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3870     { Bad_Opcode },
3871     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3872   },
3873
3874   /* PREFIX_0F61 */
3875   {
3876     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3877     { Bad_Opcode },
3878     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3879   },
3880
3881   /* PREFIX_0F62 */
3882   {
3883     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3884     { Bad_Opcode },
3885     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3886   },
3887
3888   /* PREFIX_0F6C */
3889   {
3890     { Bad_Opcode },
3891     { Bad_Opcode },
3892     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3893   },
3894
3895   /* PREFIX_0F6D */
3896   {
3897     { Bad_Opcode },
3898     { Bad_Opcode },
3899     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3900   },
3901
3902   /* PREFIX_0F6F */
3903   {
3904     { "movq",   { MX, EM }, PREFIX_OPCODE },
3905     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3906     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3907   },
3908
3909   /* PREFIX_0F70 */
3910   {
3911     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3912     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3913     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3914     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3915   },
3916
3917   /* PREFIX_0F73_REG_3 */
3918   {
3919     { Bad_Opcode },
3920     { Bad_Opcode },
3921     { "psrldq", { XS, Ib }, 0 },
3922   },
3923
3924   /* PREFIX_0F73_REG_7 */
3925   {
3926     { Bad_Opcode },
3927     { Bad_Opcode },
3928     { "pslldq", { XS, Ib }, 0 },
3929   },
3930
3931   /* PREFIX_0F78 */
3932   {
3933     {"vmread",  { Em, Gm }, 0 },
3934     { Bad_Opcode },
3935     {"extrq",   { XS, Ib, Ib }, 0 },
3936     {"insertq", { XM, XS, Ib, Ib }, 0 },
3937   },
3938
3939   /* PREFIX_0F79 */
3940   {
3941     {"vmwrite", { Gm, Em }, 0 },
3942     { Bad_Opcode },
3943     {"extrq",   { XM, XS }, 0 },
3944     {"insertq", { XM, XS }, 0 },
3945   },
3946
3947   /* PREFIX_0F7C */
3948   {
3949     { Bad_Opcode },
3950     { Bad_Opcode },
3951     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3952     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3953   },
3954
3955   /* PREFIX_0F7D */
3956   {
3957     { Bad_Opcode },
3958     { Bad_Opcode },
3959     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3960     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3961   },
3962
3963   /* PREFIX_0F7E */
3964   {
3965     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3966     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3967     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3968   },
3969
3970   /* PREFIX_0F7F */
3971   {
3972     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3973     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3974     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3975   },
3976
3977   /* PREFIX_0FAE_REG_0 */
3978   {
3979     { Bad_Opcode },
3980     { "rdfsbase", { Ev }, 0 },
3981   },
3982
3983   /* PREFIX_0FAE_REG_1 */
3984   {
3985     { Bad_Opcode },
3986     { "rdgsbase", { Ev }, 0 },
3987   },
3988
3989   /* PREFIX_0FAE_REG_2 */
3990   {
3991     { Bad_Opcode },
3992     { "wrfsbase", { Ev }, 0 },
3993   },
3994
3995   /* PREFIX_0FAE_REG_3 */
3996   {
3997     { Bad_Opcode },
3998     { "wrgsbase", { Ev }, 0 },
3999   },
4000
4001   /* PREFIX_0FAE_REG_6 */
4002   {
4003     { "xsaveopt",      { FXSAVE }, 0 },
4004     { Bad_Opcode },
4005     { "clwb",   { Mb }, 0 },
4006   },
4007
4008   /* PREFIX_0FAE_REG_7 */
4009   {
4010     { "clflush",        { Mb }, 0 },
4011     { Bad_Opcode },
4012     { "clflushopt",     { Mb }, 0 },
4013   },
4014
4015   /* PREFIX_RM_0_0FAE_REG_7 */
4016   {
4017     { "sfence",         { Skip_MODRM }, 0 },
4018     { Bad_Opcode },
4019     { "pcommit",                { Skip_MODRM }, 0 },
4020   },
4021
4022   /* PREFIX_0FB8 */
4023   {
4024     { Bad_Opcode },
4025     { "popcntS", { Gv, Ev }, 0 },
4026   },
4027
4028   /* PREFIX_0FBC */
4029   {
4030     { "bsfS",   { Gv, Ev }, 0 },
4031     { "tzcntS", { Gv, Ev }, 0 },
4032     { "bsfS",   { Gv, Ev }, 0 },
4033   },
4034
4035   /* PREFIX_0FBD */
4036   {
4037     { "bsrS",   { Gv, Ev }, 0 },
4038     { "lzcntS", { Gv, Ev }, 0 },
4039     { "bsrS",   { Gv, Ev }, 0 },
4040   },
4041
4042   /* PREFIX_0FC2 */
4043   {
4044     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4045     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4046     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4047     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4048   },
4049
4050   /* PREFIX_0FC3 */
4051   {
4052     { "movntiS", { Ma, Gv }, PREFIX_OPCODE },
4053   },
4054
4055   /* PREFIX_MOD_0_0FC7_REG_6 */
4056   {
4057     { "vmptrld",{ Mq }, 0 },
4058     { "vmxon",  { Mq }, 0 },
4059     { "vmclear",{ Mq }, 0 },
4060   },
4061
4062   /* PREFIX_MOD_3_0FC7_REG_6 */
4063   {
4064     { "rdrand", { Ev }, 0 },
4065     { Bad_Opcode },
4066     { "rdrand", { Ev }, 0 }
4067   },
4068
4069   /* PREFIX_MOD_3_0FC7_REG_7 */
4070   {
4071     { "rdseed", { Ev }, 0 },
4072     { Bad_Opcode },
4073     { "rdseed", { Ev }, 0 },
4074   },
4075
4076   /* PREFIX_0FD0 */
4077   {
4078     { Bad_Opcode },
4079     { Bad_Opcode },
4080     { "addsubpd", { XM, EXx }, 0 },
4081     { "addsubps", { XM, EXx }, 0 },
4082   },
4083
4084   /* PREFIX_0FD6 */
4085   {
4086     { Bad_Opcode },
4087     { "movq2dq",{ XM, MS }, 0 },
4088     { "movq",   { EXqS, XM }, 0 },
4089     { "movdq2q",{ MX, XS }, 0 },
4090   },
4091
4092   /* PREFIX_0FE6 */
4093   {
4094     { Bad_Opcode },
4095     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4096     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4097     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4098   },
4099
4100   /* PREFIX_0FE7 */
4101   {
4102     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4103     { Bad_Opcode },
4104     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4105   },
4106
4107   /* PREFIX_0FF0 */
4108   {
4109     { Bad_Opcode },
4110     { Bad_Opcode },
4111     { Bad_Opcode },
4112     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4113   },
4114
4115   /* PREFIX_0FF7 */
4116   {
4117     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4118     { Bad_Opcode },
4119     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4120   },
4121
4122   /* PREFIX_0F3810 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4127   },
4128
4129   /* PREFIX_0F3814 */
4130   {
4131     { Bad_Opcode },
4132     { Bad_Opcode },
4133     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4134   },
4135
4136   /* PREFIX_0F3815 */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4141   },
4142
4143   /* PREFIX_0F3817 */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4148   },
4149
4150   /* PREFIX_0F3820 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4155   },
4156
4157   /* PREFIX_0F3821 */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4162   },
4163
4164   /* PREFIX_0F3822 */
4165   {
4166     { Bad_Opcode },
4167     { Bad_Opcode },
4168     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4169   },
4170
4171   /* PREFIX_0F3823 */
4172   {
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4176   },
4177
4178   /* PREFIX_0F3824 */
4179   {
4180     { Bad_Opcode },
4181     { Bad_Opcode },
4182     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4183   },
4184
4185   /* PREFIX_0F3825 */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4190   },
4191
4192   /* PREFIX_0F3828 */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4197   },
4198
4199   /* PREFIX_0F3829 */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4204   },
4205
4206   /* PREFIX_0F382A */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4211   },
4212
4213   /* PREFIX_0F382B */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4218   },
4219
4220   /* PREFIX_0F3830 */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4225   },
4226
4227   /* PREFIX_0F3831 */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4232   },
4233
4234   /* PREFIX_0F3832 */
4235   {
4236     { Bad_Opcode },
4237     { Bad_Opcode },
4238     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4239   },
4240
4241   /* PREFIX_0F3833 */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4246   },
4247
4248   /* PREFIX_0F3834 */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4253   },
4254
4255   /* PREFIX_0F3835 */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4260   },
4261
4262   /* PREFIX_0F3837 */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4267   },
4268
4269   /* PREFIX_0F3838 */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4274   },
4275
4276   /* PREFIX_0F3839 */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0F383A */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4288   },
4289
4290   /* PREFIX_0F383B */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4295   },
4296
4297   /* PREFIX_0F383C */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4302   },
4303
4304   /* PREFIX_0F383D */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4309   },
4310
4311   /* PREFIX_0F383E */
4312   {
4313     { Bad_Opcode },
4314     { Bad_Opcode },
4315     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4316   },
4317
4318   /* PREFIX_0F383F */
4319   {
4320     { Bad_Opcode },
4321     { Bad_Opcode },
4322     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4323   },
4324
4325   /* PREFIX_0F3840 */
4326   {
4327     { Bad_Opcode },
4328     { Bad_Opcode },
4329     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4330   },
4331
4332   /* PREFIX_0F3841 */
4333   {
4334     { Bad_Opcode },
4335     { Bad_Opcode },
4336     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4337   },
4338
4339   /* PREFIX_0F3880 */
4340   {
4341     { Bad_Opcode },
4342     { Bad_Opcode },
4343     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4344   },
4345
4346   /* PREFIX_0F3881 */
4347   {
4348     { Bad_Opcode },
4349     { Bad_Opcode },
4350     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4351   },
4352
4353   /* PREFIX_0F3882 */
4354   {
4355     { Bad_Opcode },
4356     { Bad_Opcode },
4357     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4358   },
4359
4360   /* PREFIX_0F38C8 */
4361   {
4362     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4363   },
4364
4365   /* PREFIX_0F38C9 */
4366   {
4367     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4368   },
4369
4370   /* PREFIX_0F38CA */
4371   {
4372     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4373   },
4374
4375   /* PREFIX_0F38CB */
4376   {
4377     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4378   },
4379
4380   /* PREFIX_0F38CC */
4381   {
4382     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4383   },
4384
4385   /* PREFIX_0F38CD */
4386   {
4387     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4388   },
4389
4390   /* PREFIX_0F38DB */
4391   {
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4395   },
4396
4397   /* PREFIX_0F38DC */
4398   {
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4402   },
4403
4404   /* PREFIX_0F38DD */
4405   {
4406     { Bad_Opcode },
4407     { Bad_Opcode },
4408     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4409   },
4410
4411   /* PREFIX_0F38DE */
4412   {
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4416   },
4417
4418   /* PREFIX_0F38DF */
4419   {
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4423   },
4424
4425   /* PREFIX_0F38F0 */
4426   {
4427     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4428     { Bad_Opcode },
4429     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4430     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4431   },
4432
4433   /* PREFIX_0F38F1 */
4434   {
4435     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4436     { Bad_Opcode },
4437     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4438     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4439   },
4440
4441   /* PREFIX_0F38F6 */
4442   {
4443     { Bad_Opcode },
4444     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4445     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4446     { Bad_Opcode },
4447   },
4448
4449   /* PREFIX_0F3A08 */
4450   {
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4454   },
4455
4456   /* PREFIX_0F3A09 */
4457   {
4458     { Bad_Opcode },
4459     { Bad_Opcode },
4460     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4461   },
4462
4463   /* PREFIX_0F3A0A */
4464   {
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4468   },
4469
4470   /* PREFIX_0F3A0B */
4471   {
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4475   },
4476
4477   /* PREFIX_0F3A0C */
4478   {
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4482   },
4483
4484   /* PREFIX_0F3A0D */
4485   {
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4489   },
4490
4491   /* PREFIX_0F3A0E */
4492   {
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4496   },
4497
4498   /* PREFIX_0F3A14 */
4499   {
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4503   },
4504
4505   /* PREFIX_0F3A15 */
4506   {
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4510   },
4511
4512   /* PREFIX_0F3A16 */
4513   {
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4517   },
4518
4519   /* PREFIX_0F3A17 */
4520   {
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4524   },
4525
4526   /* PREFIX_0F3A20 */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4531   },
4532
4533   /* PREFIX_0F3A21 */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4538   },
4539
4540   /* PREFIX_0F3A22 */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4545   },
4546
4547   /* PREFIX_0F3A40 */
4548   {
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4552   },
4553
4554   /* PREFIX_0F3A41 */
4555   {
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4559   },
4560
4561   /* PREFIX_0F3A42 */
4562   {
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4566   },
4567
4568   /* PREFIX_0F3A44 */
4569   {
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4573   },
4574
4575   /* PREFIX_0F3A60 */
4576   {
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4580   },
4581
4582   /* PREFIX_0F3A61 */
4583   {
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4587   },
4588
4589   /* PREFIX_0F3A62 */
4590   {
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4594   },
4595
4596   /* PREFIX_0F3A63 */
4597   {
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4601   },
4602
4603   /* PREFIX_0F3ACC */
4604   {
4605     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F3ADF */
4609   {
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4613   },
4614
4615   /* PREFIX_VEX_0F10 */
4616   {
4617     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4618     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4619     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4620     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4621   },
4622
4623   /* PREFIX_VEX_0F11 */
4624   {
4625     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4626     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4627     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4628     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4629   },
4630
4631   /* PREFIX_VEX_0F12 */
4632   {
4633     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4634     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4635     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4636     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4637   },
4638
4639   /* PREFIX_VEX_0F16 */
4640   {
4641     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4642     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4643     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4644   },
4645
4646   /* PREFIX_VEX_0F2A */
4647   {
4648     { Bad_Opcode },
4649     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4650     { Bad_Opcode },
4651     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4652   },
4653
4654   /* PREFIX_VEX_0F2C */
4655   {
4656     { Bad_Opcode },
4657     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4658     { Bad_Opcode },
4659     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4660   },
4661
4662   /* PREFIX_VEX_0F2D */
4663   {
4664     { Bad_Opcode },
4665     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4666     { Bad_Opcode },
4667     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4668   },
4669
4670   /* PREFIX_VEX_0F2E */
4671   {
4672     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4673     { Bad_Opcode },
4674     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4675   },
4676
4677   /* PREFIX_VEX_0F2F */
4678   {
4679     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4680     { Bad_Opcode },
4681     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4682   },
4683
4684   /* PREFIX_VEX_0F41 */
4685   {
4686     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4687     { Bad_Opcode },
4688     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4689   },
4690
4691   /* PREFIX_VEX_0F42 */
4692   {
4693     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4694     { Bad_Opcode },
4695     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4696   },
4697
4698   /* PREFIX_VEX_0F44 */
4699   {
4700     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4701     { Bad_Opcode },
4702     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4703   },
4704
4705   /* PREFIX_VEX_0F45 */
4706   {
4707     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4708     { Bad_Opcode },
4709     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4710   },
4711
4712   /* PREFIX_VEX_0F46 */
4713   {
4714     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4715     { Bad_Opcode },
4716     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4717   },
4718
4719   /* PREFIX_VEX_0F47 */
4720   {
4721     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4722     { Bad_Opcode },
4723     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4724   },
4725
4726   /* PREFIX_VEX_0F4A */
4727   {
4728     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4729     { Bad_Opcode },
4730     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4731   },
4732
4733   /* PREFIX_VEX_0F4B */
4734   {
4735     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4736     { Bad_Opcode },
4737     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4738   },
4739
4740   /* PREFIX_VEX_0F51 */
4741   {
4742     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4743     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4744     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4745     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4746   },
4747
4748   /* PREFIX_VEX_0F52 */
4749   {
4750     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4751     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4752   },
4753
4754   /* PREFIX_VEX_0F53 */
4755   {
4756     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4757     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4758   },
4759
4760   /* PREFIX_VEX_0F58 */
4761   {
4762     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4763     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4764     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4765     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4766   },
4767
4768   /* PREFIX_VEX_0F59 */
4769   {
4770     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4771     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4772     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4773     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4774   },
4775
4776   /* PREFIX_VEX_0F5A */
4777   {
4778     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4779     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4780     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4781     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4782   },
4783
4784   /* PREFIX_VEX_0F5B */
4785   {
4786     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4787     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4788     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4789   },
4790
4791   /* PREFIX_VEX_0F5C */
4792   {
4793     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4794     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4795     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4796     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4797   },
4798
4799   /* PREFIX_VEX_0F5D */
4800   {
4801     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4802     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4803     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4804     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4805   },
4806
4807   /* PREFIX_VEX_0F5E */
4808   {
4809     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4810     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4811     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4812     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4813   },
4814
4815   /* PREFIX_VEX_0F5F */
4816   {
4817     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4818     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4819     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4820     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4821   },
4822
4823   /* PREFIX_VEX_0F60 */
4824   {
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4828   },
4829
4830   /* PREFIX_VEX_0F61 */
4831   {
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4835   },
4836
4837   /* PREFIX_VEX_0F62 */
4838   {
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4842   },
4843
4844   /* PREFIX_VEX_0F63 */
4845   {
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4849   },
4850
4851   /* PREFIX_VEX_0F64 */
4852   {
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4856   },
4857
4858   /* PREFIX_VEX_0F65 */
4859   {
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4863   },
4864
4865   /* PREFIX_VEX_0F66 */
4866   {
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4870   },
4871
4872   /* PREFIX_VEX_0F67 */
4873   {
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4877   },
4878
4879   /* PREFIX_VEX_0F68 */
4880   {
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4884   },
4885
4886   /* PREFIX_VEX_0F69 */
4887   {
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4891   },
4892
4893   /* PREFIX_VEX_0F6A */
4894   {
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4898   },
4899
4900   /* PREFIX_VEX_0F6B */
4901   {
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4905   },
4906
4907   /* PREFIX_VEX_0F6C */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4912   },
4913
4914   /* PREFIX_VEX_0F6D */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4919   },
4920
4921   /* PREFIX_VEX_0F6E */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4926   },
4927
4928   /* PREFIX_VEX_0F6F */
4929   {
4930     { Bad_Opcode },
4931     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4932     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4933   },
4934
4935   /* PREFIX_VEX_0F70 */
4936   {
4937     { Bad_Opcode },
4938     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4939     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4940     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4941   },
4942
4943   /* PREFIX_VEX_0F71_REG_2 */
4944   {
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4948   },
4949
4950   /* PREFIX_VEX_0F71_REG_4 */
4951   {
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4955   },
4956
4957   /* PREFIX_VEX_0F71_REG_6 */
4958   {
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4962   },
4963
4964   /* PREFIX_VEX_0F72_REG_2 */
4965   {
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4969   },
4970
4971   /* PREFIX_VEX_0F72_REG_4 */
4972   {
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4976   },
4977
4978   /* PREFIX_VEX_0F72_REG_6 */
4979   {
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4983   },
4984
4985   /* PREFIX_VEX_0F73_REG_2 */
4986   {
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4990   },
4991
4992   /* PREFIX_VEX_0F73_REG_3 */
4993   {
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4997   },
4998
4999   /* PREFIX_VEX_0F73_REG_6 */
5000   {
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5004   },
5005
5006   /* PREFIX_VEX_0F73_REG_7 */
5007   {
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5011   },
5012
5013   /* PREFIX_VEX_0F74 */
5014   {
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5018   },
5019
5020   /* PREFIX_VEX_0F75 */
5021   {
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5025   },
5026
5027   /* PREFIX_VEX_0F76 */
5028   {
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5032   },
5033
5034   /* PREFIX_VEX_0F77 */
5035   {
5036     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5037   },
5038
5039   /* PREFIX_VEX_0F7C */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5044     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5045   },
5046
5047   /* PREFIX_VEX_0F7D */
5048   {
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5052     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5053   },
5054
5055   /* PREFIX_VEX_0F7E */
5056   {
5057     { Bad_Opcode },
5058     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5059     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5060   },
5061
5062   /* PREFIX_VEX_0F7F */
5063   {
5064     { Bad_Opcode },
5065     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5066     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5067   },
5068
5069   /* PREFIX_VEX_0F90 */
5070   {
5071     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5072     { Bad_Opcode },
5073     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5074   },
5075
5076   /* PREFIX_VEX_0F91 */
5077   {
5078     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5079     { Bad_Opcode },
5080     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5081   },
5082
5083   /* PREFIX_VEX_0F92 */
5084   {
5085     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5086     { Bad_Opcode },
5087     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5088     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5089   },
5090
5091   /* PREFIX_VEX_0F93 */
5092   {
5093     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5094     { Bad_Opcode },
5095     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5096     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5097   },
5098
5099   /* PREFIX_VEX_0F98 */
5100   {
5101     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5102     { Bad_Opcode },
5103     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5104   },
5105
5106   /* PREFIX_VEX_0F99 */
5107   {
5108     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5109     { Bad_Opcode },
5110     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5111   },
5112
5113   /* PREFIX_VEX_0FC2 */
5114   {
5115     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5116     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5117     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5118     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5119   },
5120
5121   /* PREFIX_VEX_0FC4 */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5126   },
5127
5128   /* PREFIX_VEX_0FC5 */
5129   {
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5133   },
5134
5135   /* PREFIX_VEX_0FD0 */
5136   {
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5140     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5141   },
5142
5143   /* PREFIX_VEX_0FD1 */
5144   {
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5148   },
5149
5150   /* PREFIX_VEX_0FD2 */
5151   {
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5155   },
5156
5157   /* PREFIX_VEX_0FD3 */
5158   {
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5162   },
5163
5164   /* PREFIX_VEX_0FD4 */
5165   {
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5169   },
5170
5171   /* PREFIX_VEX_0FD5 */
5172   {
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5176   },
5177
5178   /* PREFIX_VEX_0FD6 */
5179   {
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5183   },
5184
5185   /* PREFIX_VEX_0FD7 */
5186   {
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5190   },
5191
5192   /* PREFIX_VEX_0FD8 */
5193   {
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5197   },
5198
5199   /* PREFIX_VEX_0FD9 */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5204   },
5205
5206   /* PREFIX_VEX_0FDA */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5211   },
5212
5213   /* PREFIX_VEX_0FDB */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5218   },
5219
5220   /* PREFIX_VEX_0FDC */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5225   },
5226
5227   /* PREFIX_VEX_0FDD */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5232   },
5233
5234   /* PREFIX_VEX_0FDE */
5235   {
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5239   },
5240
5241   /* PREFIX_VEX_0FDF */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5246   },
5247
5248   /* PREFIX_VEX_0FE0 */
5249   {
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5253   },
5254
5255   /* PREFIX_VEX_0FE1 */
5256   {
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5260   },
5261
5262   /* PREFIX_VEX_0FE2 */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5267   },
5268
5269   /* PREFIX_VEX_0FE3 */
5270   {
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5274   },
5275
5276   /* PREFIX_VEX_0FE4 */
5277   {
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5281   },
5282
5283   /* PREFIX_VEX_0FE5 */
5284   {
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5288   },
5289
5290   /* PREFIX_VEX_0FE6 */
5291   {
5292     { Bad_Opcode },
5293     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5294     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5295     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5296   },
5297
5298   /* PREFIX_VEX_0FE7 */
5299   {
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5303   },
5304
5305   /* PREFIX_VEX_0FE8 */
5306   {
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5310   },
5311
5312   /* PREFIX_VEX_0FE9 */
5313   {
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5317   },
5318
5319   /* PREFIX_VEX_0FEA */
5320   {
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5324   },
5325
5326   /* PREFIX_VEX_0FEB */
5327   {
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5331   },
5332
5333   /* PREFIX_VEX_0FEC */
5334   {
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5338   },
5339
5340   /* PREFIX_VEX_0FED */
5341   {
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5345   },
5346
5347   /* PREFIX_VEX_0FEE */
5348   {
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5352   },
5353
5354   /* PREFIX_VEX_0FEF */
5355   {
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5359   },
5360
5361   /* PREFIX_VEX_0FF0 */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5367   },
5368
5369   /* PREFIX_VEX_0FF1 */
5370   {
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5374   },
5375
5376   /* PREFIX_VEX_0FF2 */
5377   {
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5381   },
5382
5383   /* PREFIX_VEX_0FF3 */
5384   {
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5388   },
5389
5390   /* PREFIX_VEX_0FF4 */
5391   {
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5395   },
5396
5397   /* PREFIX_VEX_0FF5 */
5398   {
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5402   },
5403
5404   /* PREFIX_VEX_0FF6 */
5405   {
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5409   },
5410
5411   /* PREFIX_VEX_0FF7 */
5412   {
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5416   },
5417
5418   /* PREFIX_VEX_0FF8 */
5419   {
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5423   },
5424
5425   /* PREFIX_VEX_0FF9 */
5426   {
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5430   },
5431
5432   /* PREFIX_VEX_0FFA */
5433   {
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5437   },
5438
5439   /* PREFIX_VEX_0FFB */
5440   {
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5444   },
5445
5446   /* PREFIX_VEX_0FFC */
5447   {
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5451   },
5452
5453   /* PREFIX_VEX_0FFD */
5454   {
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5458   },
5459
5460   /* PREFIX_VEX_0FFE */
5461   {
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5465   },
5466
5467   /* PREFIX_VEX_0F3800 */
5468   {
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5472   },
5473
5474   /* PREFIX_VEX_0F3801 */
5475   {
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5479   },
5480
5481   /* PREFIX_VEX_0F3802 */
5482   {
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5486   },
5487
5488   /* PREFIX_VEX_0F3803 */
5489   {
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5493   },
5494
5495   /* PREFIX_VEX_0F3804 */
5496   {
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5500   },
5501
5502   /* PREFIX_VEX_0F3805 */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5507   },
5508
5509   /* PREFIX_VEX_0F3806 */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5514   },
5515
5516   /* PREFIX_VEX_0F3807 */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5521   },
5522
5523   /* PREFIX_VEX_0F3808 */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5528   },
5529
5530   /* PREFIX_VEX_0F3809 */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5535   },
5536
5537   /* PREFIX_VEX_0F380A */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5542   },
5543
5544   /* PREFIX_VEX_0F380B */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5549   },
5550
5551   /* PREFIX_VEX_0F380C */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5556   },
5557
5558   /* PREFIX_VEX_0F380D */
5559   {
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5563   },
5564
5565   /* PREFIX_VEX_0F380E */
5566   {
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5570   },
5571
5572   /* PREFIX_VEX_0F380F */
5573   {
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5577   },
5578
5579   /* PREFIX_VEX_0F3813 */
5580   {
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5584   },
5585
5586   /* PREFIX_VEX_0F3816 */
5587   {
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5591   },
5592
5593   /* PREFIX_VEX_0F3817 */
5594   {
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5598   },
5599
5600   /* PREFIX_VEX_0F3818 */
5601   {
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5605   },
5606
5607   /* PREFIX_VEX_0F3819 */
5608   {
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5612   },
5613
5614   /* PREFIX_VEX_0F381A */
5615   {
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5619   },
5620
5621   /* PREFIX_VEX_0F381C */
5622   {
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5626   },
5627
5628   /* PREFIX_VEX_0F381D */
5629   {
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5633   },
5634
5635   /* PREFIX_VEX_0F381E */
5636   {
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5640   },
5641
5642   /* PREFIX_VEX_0F3820 */
5643   {
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5647   },
5648
5649   /* PREFIX_VEX_0F3821 */
5650   {
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5654   },
5655
5656   /* PREFIX_VEX_0F3822 */
5657   {
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5661   },
5662
5663   /* PREFIX_VEX_0F3823 */
5664   {
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5668   },
5669
5670   /* PREFIX_VEX_0F3824 */
5671   {
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5675   },
5676
5677   /* PREFIX_VEX_0F3825 */
5678   {
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5682   },
5683
5684   /* PREFIX_VEX_0F3828 */
5685   {
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5689   },
5690
5691   /* PREFIX_VEX_0F3829 */
5692   {
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5696   },
5697
5698   /* PREFIX_VEX_0F382A */
5699   {
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5703   },
5704
5705   /* PREFIX_VEX_0F382B */
5706   {
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5710   },
5711
5712   /* PREFIX_VEX_0F382C */
5713   {
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5717   },
5718
5719   /* PREFIX_VEX_0F382D */
5720   {
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5724   },
5725
5726   /* PREFIX_VEX_0F382E */
5727   {
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5731   },
5732
5733   /* PREFIX_VEX_0F382F */
5734   {
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5738   },
5739
5740   /* PREFIX_VEX_0F3830 */
5741   {
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5745   },
5746
5747   /* PREFIX_VEX_0F3831 */
5748   {
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5752   },
5753
5754   /* PREFIX_VEX_0F3832 */
5755   {
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5759   },
5760
5761   /* PREFIX_VEX_0F3833 */
5762   {
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5766   },
5767
5768   /* PREFIX_VEX_0F3834 */
5769   {
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5773   },
5774
5775   /* PREFIX_VEX_0F3835 */
5776   {
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5780   },
5781
5782   /* PREFIX_VEX_0F3836 */
5783   {
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5787   },
5788
5789   /* PREFIX_VEX_0F3837 */
5790   {
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5794   },
5795
5796   /* PREFIX_VEX_0F3838 */
5797   {
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5801   },
5802
5803   /* PREFIX_VEX_0F3839 */
5804   {
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5808   },
5809
5810   /* PREFIX_VEX_0F383A */
5811   {
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5815   },
5816
5817   /* PREFIX_VEX_0F383B */
5818   {
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5822   },
5823
5824   /* PREFIX_VEX_0F383C */
5825   {
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5829   },
5830
5831   /* PREFIX_VEX_0F383D */
5832   {
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5836   },
5837
5838   /* PREFIX_VEX_0F383E */
5839   {
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5843   },
5844
5845   /* PREFIX_VEX_0F383F */
5846   {
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5850   },
5851
5852   /* PREFIX_VEX_0F3840 */
5853   {
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5857   },
5858
5859   /* PREFIX_VEX_0F3841 */
5860   {
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5864   },
5865
5866   /* PREFIX_VEX_0F3845 */
5867   {
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5871   },
5872
5873   /* PREFIX_VEX_0F3846 */
5874   {
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5878   },
5879
5880   /* PREFIX_VEX_0F3847 */
5881   {
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5885   },
5886
5887   /* PREFIX_VEX_0F3858 */
5888   {
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5892   },
5893
5894   /* PREFIX_VEX_0F3859 */
5895   {
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5899   },
5900
5901   /* PREFIX_VEX_0F385A */
5902   {
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5906   },
5907
5908   /* PREFIX_VEX_0F3878 */
5909   {
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5913   },
5914
5915   /* PREFIX_VEX_0F3879 */
5916   {
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5920   },
5921
5922   /* PREFIX_VEX_0F388C */
5923   {
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5927   },
5928
5929   /* PREFIX_VEX_0F388E */
5930   {
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5934   },
5935
5936   /* PREFIX_VEX_0F3890 */
5937   {
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5941   },
5942
5943   /* PREFIX_VEX_0F3891 */
5944   {
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5948   },
5949
5950   /* PREFIX_VEX_0F3892 */
5951   {
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5955   },
5956
5957   /* PREFIX_VEX_0F3893 */
5958   {
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5962   },
5963
5964   /* PREFIX_VEX_0F3896 */
5965   {
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5969   },
5970
5971   /* PREFIX_VEX_0F3897 */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5976   },
5977
5978   /* PREFIX_VEX_0F3898 */
5979   {
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
5983   },
5984
5985   /* PREFIX_VEX_0F3899 */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5990   },
5991
5992   /* PREFIX_VEX_0F389A */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5997   },
5998
5999   /* PREFIX_VEX_0F389B */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6004   },
6005
6006   /* PREFIX_VEX_0F389C */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6011   },
6012
6013   /* PREFIX_VEX_0F389D */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6018   },
6019
6020   /* PREFIX_VEX_0F389E */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6025   },
6026
6027   /* PREFIX_VEX_0F389F */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6032   },
6033
6034   /* PREFIX_VEX_0F38A6 */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6039     { Bad_Opcode },
6040   },
6041
6042   /* PREFIX_VEX_0F38A7 */
6043   {
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6047   },
6048
6049   /* PREFIX_VEX_0F38A8 */
6050   {
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6054   },
6055
6056   /* PREFIX_VEX_0F38A9 */
6057   {
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6061   },
6062
6063   /* PREFIX_VEX_0F38AA */
6064   {
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6068   },
6069
6070   /* PREFIX_VEX_0F38AB */
6071   {
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6075   },
6076
6077   /* PREFIX_VEX_0F38AC */
6078   {
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6082   },
6083
6084   /* PREFIX_VEX_0F38AD */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6089   },
6090
6091   /* PREFIX_VEX_0F38AE */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6096   },
6097
6098   /* PREFIX_VEX_0F38AF */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6103   },
6104
6105   /* PREFIX_VEX_0F38B6 */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6110   },
6111
6112   /* PREFIX_VEX_0F38B7 */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6117   },
6118
6119   /* PREFIX_VEX_0F38B8 */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6124   },
6125
6126   /* PREFIX_VEX_0F38B9 */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6131   },
6132
6133   /* PREFIX_VEX_0F38BA */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6138   },
6139
6140   /* PREFIX_VEX_0F38BB */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6145   },
6146
6147   /* PREFIX_VEX_0F38BC */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F38BD */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F38BE */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6166   },
6167
6168   /* PREFIX_VEX_0F38BF */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6173   },
6174
6175   /* PREFIX_VEX_0F38DB */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6180   },
6181
6182   /* PREFIX_VEX_0F38DC */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6187   },
6188
6189   /* PREFIX_VEX_0F38DD */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6194   },
6195
6196   /* PREFIX_VEX_0F38DE */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6201   },
6202
6203   /* PREFIX_VEX_0F38DF */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6208   },
6209
6210   /* PREFIX_VEX_0F38F2 */
6211   {
6212     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6213   },
6214
6215   /* PREFIX_VEX_0F38F3_REG_1 */
6216   {
6217     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6218   },
6219
6220   /* PREFIX_VEX_0F38F3_REG_2 */
6221   {
6222     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6223   },
6224
6225   /* PREFIX_VEX_0F38F3_REG_3 */
6226   {
6227     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6228   },
6229
6230   /* PREFIX_VEX_0F38F5 */
6231   {
6232     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6233     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6234     { Bad_Opcode },
6235     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6236   },
6237
6238   /* PREFIX_VEX_0F38F6 */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6244   },
6245
6246   /* PREFIX_VEX_0F38F7 */
6247   {
6248     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6249     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6250     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6251     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6252   },
6253
6254   /* PREFIX_VEX_0F3A00 */
6255   {
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6259   },
6260
6261   /* PREFIX_VEX_0F3A01 */
6262   {
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6266   },
6267
6268   /* PREFIX_VEX_0F3A02 */
6269   {
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6273   },
6274
6275   /* PREFIX_VEX_0F3A04 */
6276   {
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6280   },
6281
6282   /* PREFIX_VEX_0F3A05 */
6283   {
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6287   },
6288
6289   /* PREFIX_VEX_0F3A06 */
6290   {
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6294   },
6295
6296   /* PREFIX_VEX_0F3A08 */
6297   {
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6301   },
6302
6303   /* PREFIX_VEX_0F3A09 */
6304   {
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6308   },
6309
6310   /* PREFIX_VEX_0F3A0A */
6311   {
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6315   },
6316
6317   /* PREFIX_VEX_0F3A0B */
6318   {
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6322   },
6323
6324   /* PREFIX_VEX_0F3A0C */
6325   {
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6329   },
6330
6331   /* PREFIX_VEX_0F3A0D */
6332   {
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6336   },
6337
6338   /* PREFIX_VEX_0F3A0E */
6339   {
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6343   },
6344
6345   /* PREFIX_VEX_0F3A0F */
6346   {
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6350   },
6351
6352   /* PREFIX_VEX_0F3A14 */
6353   {
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6357   },
6358
6359   /* PREFIX_VEX_0F3A15 */
6360   {
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6364   },
6365
6366   /* PREFIX_VEX_0F3A16 */
6367   {
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6371   },
6372
6373   /* PREFIX_VEX_0F3A17 */
6374   {
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6378   },
6379
6380   /* PREFIX_VEX_0F3A18 */
6381   {
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6385   },
6386
6387   /* PREFIX_VEX_0F3A19 */
6388   {
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6392   },
6393
6394   /* PREFIX_VEX_0F3A1D */
6395   {
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6399   },
6400
6401   /* PREFIX_VEX_0F3A20 */
6402   {
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6406   },
6407
6408   /* PREFIX_VEX_0F3A21 */
6409   {
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6413   },
6414
6415   /* PREFIX_VEX_0F3A22 */
6416   {
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6420   },
6421
6422   /* PREFIX_VEX_0F3A30 */
6423   {
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6427   },
6428
6429   /* PREFIX_VEX_0F3A31 */
6430   {
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6434   },
6435
6436   /* PREFIX_VEX_0F3A32 */
6437   {
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6441   },
6442
6443   /* PREFIX_VEX_0F3A33 */
6444   {
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6448   },
6449
6450   /* PREFIX_VEX_0F3A38 */
6451   {
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6455   },
6456
6457   /* PREFIX_VEX_0F3A39 */
6458   {
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6462   },
6463
6464   /* PREFIX_VEX_0F3A40 */
6465   {
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6469   },
6470
6471   /* PREFIX_VEX_0F3A41 */
6472   {
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6476   },
6477
6478   /* PREFIX_VEX_0F3A42 */
6479   {
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6483   },
6484
6485   /* PREFIX_VEX_0F3A44 */
6486   {
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6490   },
6491
6492   /* PREFIX_VEX_0F3A46 */
6493   {
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6497   },
6498
6499   /* PREFIX_VEX_0F3A48 */
6500   {
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6504   },
6505
6506   /* PREFIX_VEX_0F3A49 */
6507   {
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6511   },
6512
6513   /* PREFIX_VEX_0F3A4A */
6514   {
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6518   },
6519
6520   /* PREFIX_VEX_0F3A4B */
6521   {
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6525   },
6526
6527   /* PREFIX_VEX_0F3A4C */
6528   {
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6532   },
6533
6534   /* PREFIX_VEX_0F3A5C */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6539   },
6540
6541   /* PREFIX_VEX_0F3A5D */
6542   {
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6546   },
6547
6548   /* PREFIX_VEX_0F3A5E */
6549   {
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6553   },
6554
6555   /* PREFIX_VEX_0F3A5F */
6556   {
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6560   },
6561
6562   /* PREFIX_VEX_0F3A60 */
6563   {
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6567     { Bad_Opcode },
6568   },
6569
6570   /* PREFIX_VEX_0F3A61 */
6571   {
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6575   },
6576
6577   /* PREFIX_VEX_0F3A62 */
6578   {
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6582   },
6583
6584   /* PREFIX_VEX_0F3A63 */
6585   {
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6589   },
6590
6591   /* PREFIX_VEX_0F3A68 */
6592   {
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6596   },
6597
6598   /* PREFIX_VEX_0F3A69 */
6599   {
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6603   },
6604
6605   /* PREFIX_VEX_0F3A6A */
6606   {
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6610   },
6611
6612   /* PREFIX_VEX_0F3A6B */
6613   {
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6617   },
6618
6619   /* PREFIX_VEX_0F3A6C */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6624   },
6625
6626   /* PREFIX_VEX_0F3A6D */
6627   {
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6631   },
6632
6633   /* PREFIX_VEX_0F3A6E */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3A6F */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3A78 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6652   },
6653
6654   /* PREFIX_VEX_0F3A79 */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6659   },
6660
6661   /* PREFIX_VEX_0F3A7A */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6666   },
6667
6668   /* PREFIX_VEX_0F3A7B */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6673   },
6674
6675   /* PREFIX_VEX_0F3A7C */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6680     { Bad_Opcode },
6681   },
6682
6683   /* PREFIX_VEX_0F3A7D */
6684   {
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6688   },
6689
6690   /* PREFIX_VEX_0F3A7E */
6691   {
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6695   },
6696
6697   /* PREFIX_VEX_0F3A7F */
6698   {
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6702   },
6703
6704   /* PREFIX_VEX_0F3ADF */
6705   {
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6709   },
6710
6711   /* PREFIX_VEX_0F3AF0 */
6712   {
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6717   },
6718
6719 #define NEED_PREFIX_TABLE
6720 #include "i386-dis-evex.h"
6721 #undef NEED_PREFIX_TABLE
6722 };
6723
6724 static const struct dis386 x86_64_table[][2] = {
6725   /* X86_64_06 */
6726   {
6727     { "pushP", { es }, 0 },
6728   },
6729
6730   /* X86_64_07 */
6731   {
6732     { "popP", { es }, 0 },
6733   },
6734
6735   /* X86_64_0D */
6736   {
6737     { "pushP", { cs }, 0 },
6738   },
6739
6740   /* X86_64_16 */
6741   {
6742     { "pushP", { ss }, 0 },
6743   },
6744
6745   /* X86_64_17 */
6746   {
6747     { "popP", { ss }, 0 },
6748   },
6749
6750   /* X86_64_1E */
6751   {
6752     { "pushP", { ds }, 0 },
6753   },
6754
6755   /* X86_64_1F */
6756   {
6757     { "popP", { ds }, 0 },
6758   },
6759
6760   /* X86_64_27 */
6761   {
6762     { "daa", { XX }, 0 },
6763   },
6764
6765   /* X86_64_2F */
6766   {
6767     { "das", { XX }, 0 },
6768   },
6769
6770   /* X86_64_37 */
6771   {
6772     { "aaa", { XX }, 0 },
6773   },
6774
6775   /* X86_64_3F */
6776   {
6777     { "aas", { XX }, 0 },
6778   },
6779
6780   /* X86_64_60 */
6781   {
6782     { "pushaP", { XX }, 0 },
6783   },
6784
6785   /* X86_64_61 */
6786   {
6787     { "popaP", { XX }, 0 },
6788   },
6789
6790   /* X86_64_62 */
6791   {
6792     { MOD_TABLE (MOD_62_32BIT) },
6793     { EVEX_TABLE (EVEX_0F) },
6794   },
6795
6796   /* X86_64_63 */
6797   {
6798     { "arpl", { Ew, Gw }, 0 },
6799     { "movs{lq|xd}", { Gv, Ed }, 0 },
6800   },
6801
6802   /* X86_64_6D */
6803   {
6804     { "ins{R|}", { Yzr, indirDX }, 0 },
6805     { "ins{G|}", { Yzr, indirDX }, 0 },
6806   },
6807
6808   /* X86_64_6F */
6809   {
6810     { "outs{R|}", { indirDXr, Xz }, 0 },
6811     { "outs{G|}", { indirDXr, Xz }, 0 },
6812   },
6813
6814   /* X86_64_9A */
6815   {
6816     { "Jcall{T|}", { Ap }, 0 },
6817   },
6818
6819   /* X86_64_C4 */
6820   {
6821     { MOD_TABLE (MOD_C4_32BIT) },
6822     { VEX_C4_TABLE (VEX_0F) },
6823   },
6824
6825   /* X86_64_C5 */
6826   {
6827     { MOD_TABLE (MOD_C5_32BIT) },
6828     { VEX_C5_TABLE (VEX_0F) },
6829   },
6830
6831   /* X86_64_CE */
6832   {
6833     { "into", { XX }, 0 },
6834   },
6835
6836   /* X86_64_D4 */
6837   {
6838     { "aam", { Ib }, 0 },
6839   },
6840
6841   /* X86_64_D5 */
6842   {
6843     { "aad", { Ib }, 0 },
6844   },
6845
6846   /* X86_64_E8 */
6847   {
6848     { "callP",          { Jv, BND }, 0 },
6849     { "call@",          { Jv, BND }, 0 }
6850   },
6851
6852   /* X86_64_E9 */
6853   {
6854     { "jmpP",           { Jv, BND }, 0 },
6855     { "jmp@",           { Jv, BND }, 0 }
6856   },
6857
6858   /* X86_64_EA */
6859   {
6860     { "Jjmp{T|}", { Ap }, 0 },
6861   },
6862
6863   /* X86_64_0F01_REG_0 */
6864   {
6865     { "sgdt{Q|IQ}", { M }, 0 },
6866     { "sgdt", { M }, 0 },
6867   },
6868
6869   /* X86_64_0F01_REG_1 */
6870   {
6871     { "sidt{Q|IQ}", { M }, 0 },
6872     { "sidt", { M }, 0 },
6873   },
6874
6875   /* X86_64_0F01_REG_2 */
6876   {
6877     { "lgdt{Q|Q}", { M }, 0 },
6878     { "lgdt", { M }, 0 },
6879   },
6880
6881   /* X86_64_0F01_REG_3 */
6882   {
6883     { "lidt{Q|Q}", { M }, 0 },
6884     { "lidt", { M }, 0 },
6885   },
6886 };
6887
6888 static const struct dis386 three_byte_table[][256] = {
6889
6890   /* THREE_BYTE_0F38 */
6891   {
6892     /* 00 */
6893     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6894     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6895     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6896     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6897     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6898     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6899     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6900     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6901     /* 08 */
6902     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6903     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6904     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6905     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     /* 10 */
6911     { PREFIX_TABLE (PREFIX_0F3810) },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { PREFIX_TABLE (PREFIX_0F3814) },
6916     { PREFIX_TABLE (PREFIX_0F3815) },
6917     { Bad_Opcode },
6918     { PREFIX_TABLE (PREFIX_0F3817) },
6919     /* 18 */
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6925     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6926     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6927     { Bad_Opcode },
6928     /* 20 */
6929     { PREFIX_TABLE (PREFIX_0F3820) },
6930     { PREFIX_TABLE (PREFIX_0F3821) },
6931     { PREFIX_TABLE (PREFIX_0F3822) },
6932     { PREFIX_TABLE (PREFIX_0F3823) },
6933     { PREFIX_TABLE (PREFIX_0F3824) },
6934     { PREFIX_TABLE (PREFIX_0F3825) },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     /* 28 */
6938     { PREFIX_TABLE (PREFIX_0F3828) },
6939     { PREFIX_TABLE (PREFIX_0F3829) },
6940     { PREFIX_TABLE (PREFIX_0F382A) },
6941     { PREFIX_TABLE (PREFIX_0F382B) },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     /* 30 */
6947     { PREFIX_TABLE (PREFIX_0F3830) },
6948     { PREFIX_TABLE (PREFIX_0F3831) },
6949     { PREFIX_TABLE (PREFIX_0F3832) },
6950     { PREFIX_TABLE (PREFIX_0F3833) },
6951     { PREFIX_TABLE (PREFIX_0F3834) },
6952     { PREFIX_TABLE (PREFIX_0F3835) },
6953     { Bad_Opcode },
6954     { PREFIX_TABLE (PREFIX_0F3837) },
6955     /* 38 */
6956     { PREFIX_TABLE (PREFIX_0F3838) },
6957     { PREFIX_TABLE (PREFIX_0F3839) },
6958     { PREFIX_TABLE (PREFIX_0F383A) },
6959     { PREFIX_TABLE (PREFIX_0F383B) },
6960     { PREFIX_TABLE (PREFIX_0F383C) },
6961     { PREFIX_TABLE (PREFIX_0F383D) },
6962     { PREFIX_TABLE (PREFIX_0F383E) },
6963     { PREFIX_TABLE (PREFIX_0F383F) },
6964     /* 40 */
6965     { PREFIX_TABLE (PREFIX_0F3840) },
6966     { PREFIX_TABLE (PREFIX_0F3841) },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     /* 48 */
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     /* 50 */
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     /* 58 */
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     /* 60 */
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     /* 68 */
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     /* 70 */
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     /* 78 */
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     /* 80 */
7037     { PREFIX_TABLE (PREFIX_0F3880) },
7038     { PREFIX_TABLE (PREFIX_0F3881) },
7039     { PREFIX_TABLE (PREFIX_0F3882) },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     /* 88 */
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     /* 90 */
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     /* 98 */
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     /* a0 */
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     /* a8 */
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     /* b0 */
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     /* b8 */
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     /* c0 */
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     /* c8 */
7118     { PREFIX_TABLE (PREFIX_0F38C8) },
7119     { PREFIX_TABLE (PREFIX_0F38C9) },
7120     { PREFIX_TABLE (PREFIX_0F38CA) },
7121     { PREFIX_TABLE (PREFIX_0F38CB) },
7122     { PREFIX_TABLE (PREFIX_0F38CC) },
7123     { PREFIX_TABLE (PREFIX_0F38CD) },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     /* d0 */
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     /* d8 */
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { PREFIX_TABLE (PREFIX_0F38DB) },
7140     { PREFIX_TABLE (PREFIX_0F38DC) },
7141     { PREFIX_TABLE (PREFIX_0F38DD) },
7142     { PREFIX_TABLE (PREFIX_0F38DE) },
7143     { PREFIX_TABLE (PREFIX_0F38DF) },
7144     /* e0 */
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     /* e8 */
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     /* f0 */
7163     { PREFIX_TABLE (PREFIX_0F38F0) },
7164     { PREFIX_TABLE (PREFIX_0F38F1) },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { PREFIX_TABLE (PREFIX_0F38F6) },
7170     { Bad_Opcode },
7171     /* f8 */
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180   },
7181   /* THREE_BYTE_0F3A */
7182   {
7183     /* 00 */
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     /* 08 */
7193     { PREFIX_TABLE (PREFIX_0F3A08) },
7194     { PREFIX_TABLE (PREFIX_0F3A09) },
7195     { PREFIX_TABLE (PREFIX_0F3A0A) },
7196     { PREFIX_TABLE (PREFIX_0F3A0B) },
7197     { PREFIX_TABLE (PREFIX_0F3A0C) },
7198     { PREFIX_TABLE (PREFIX_0F3A0D) },
7199     { PREFIX_TABLE (PREFIX_0F3A0E) },
7200     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7201     /* 10 */
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { PREFIX_TABLE (PREFIX_0F3A14) },
7207     { PREFIX_TABLE (PREFIX_0F3A15) },
7208     { PREFIX_TABLE (PREFIX_0F3A16) },
7209     { PREFIX_TABLE (PREFIX_0F3A17) },
7210     /* 18 */
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     /* 20 */
7220     { PREFIX_TABLE (PREFIX_0F3A20) },
7221     { PREFIX_TABLE (PREFIX_0F3A21) },
7222     { PREFIX_TABLE (PREFIX_0F3A22) },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     /* 28 */
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     /* 30 */
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     /* 38 */
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     /* 40 */
7256     { PREFIX_TABLE (PREFIX_0F3A40) },
7257     { PREFIX_TABLE (PREFIX_0F3A41) },
7258     { PREFIX_TABLE (PREFIX_0F3A42) },
7259     { Bad_Opcode },
7260     { PREFIX_TABLE (PREFIX_0F3A44) },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     /* 48 */
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     /* 50 */
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     /* 58 */
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     /* 60 */
7292     { PREFIX_TABLE (PREFIX_0F3A60) },
7293     { PREFIX_TABLE (PREFIX_0F3A61) },
7294     { PREFIX_TABLE (PREFIX_0F3A62) },
7295     { PREFIX_TABLE (PREFIX_0F3A63) },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     /* 68 */
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     /* 70 */
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     /* 78 */
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     /* 80 */
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     /* 88 */
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     /* 90 */
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     /* 98 */
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     /* a0 */
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     /* a8 */
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     /* b0 */
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     /* b8 */
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     /* c0 */
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     /* c8 */
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { PREFIX_TABLE (PREFIX_0F3ACC) },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     /* d0 */
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     /* d8 */
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { PREFIX_TABLE (PREFIX_0F3ADF) },
7435     /* e0 */
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     /* e8 */
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     /* f0 */
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     /* f8 */
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471   },
7472
7473   /* THREE_BYTE_0F7A */
7474   {
7475     /* 00 */
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     /* 08 */
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     /* 10 */
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     /* 18 */
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     /* 20 */
7512     { "ptest",          { XX }, PREFIX_OPCODE },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     /* 28 */
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     /* 30 */
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     /* 38 */
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     /* 40 */
7548     { Bad_Opcode },
7549     { "phaddbw",        { XM, EXq }, PREFIX_OPCODE },
7550     { "phaddbd",        { XM, EXq }, PREFIX_OPCODE },
7551     { "phaddbq",        { XM, EXq }, PREFIX_OPCODE },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { "phaddwd",        { XM, EXq }, PREFIX_OPCODE },
7555     { "phaddwq",        { XM, EXq }, PREFIX_OPCODE },
7556     /* 48 */
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { "phadddq",        { XM, EXq }, PREFIX_OPCODE },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     /* 50 */
7566     { Bad_Opcode },
7567     { "phaddubw",       { XM, EXq }, PREFIX_OPCODE },
7568     { "phaddubd",       { XM, EXq }, PREFIX_OPCODE },
7569     { "phaddubq",       { XM, EXq }, PREFIX_OPCODE },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { "phadduwd",       { XM, EXq }, PREFIX_OPCODE },
7573     { "phadduwq",       { XM, EXq }, PREFIX_OPCODE },
7574     /* 58 */
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { "phaddudq",       { XM, EXq }, PREFIX_OPCODE },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     /* 60 */
7584     { Bad_Opcode },
7585     { "phsubbw",        { XM, EXq }, PREFIX_OPCODE },
7586     { "phsubbd",        { XM, EXq }, PREFIX_OPCODE },
7587     { "phsubbq",        { XM, EXq }, PREFIX_OPCODE },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     /* 68 */
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     /* 70 */
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     /* 78 */
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     /* 80 */
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     /* 88 */
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     /* 90 */
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     /* 98 */
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     /* a0 */
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     /* a8 */
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     /* b0 */
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     /* b8 */
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     /* c0 */
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     /* c8 */
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     /* d0 */
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     /* d8 */
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     /* e0 */
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     /* e8 */
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     /* f0 */
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     /* f8 */
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763   },
7764 };
7765
7766 static const struct dis386 xop_table[][256] = {
7767   /* XOP_08 */
7768   {
7769     /* 00 */
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     /* 08 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* 10 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     /* 18 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     /* 20 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     /* 28 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     /* 30 */
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     /* 38 */
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     /* 40 */
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     /* 48 */
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     /* 50 */
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     /* 58 */
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     /* 60 */
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     /* 68 */
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     /* 70 */
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     /* 78 */
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     /* 80 */
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7920     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7921     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7922     /* 88 */
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7930     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7931     /* 90 */
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7938     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7939     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7940     /* 98 */
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7948     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7949     /* a0 */
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7953     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7957     { Bad_Opcode },
7958     /* a8 */
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     /* b0 */
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7975     { Bad_Opcode },
7976     /* b8 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     /* c0 */
7986     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7987     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7988     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7989     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     /* c8 */
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8000     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8001     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8002     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8003     /* d0 */
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     /* d8 */
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     /* e0 */
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     /* e8 */
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8036     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8037     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8038     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8039     /* f0 */
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     /* f8 */
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057   },
8058   /* XOP_09 */
8059   {
8060     /* 00 */
8061     { Bad_Opcode },
8062     { REG_TABLE (REG_XOP_TBM_01) },
8063     { REG_TABLE (REG_XOP_TBM_02) },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     /* 08 */
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* 10 */
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { REG_TABLE (REG_XOP_LWPCB) },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     /* 18 */
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* 20 */
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     /* 28 */
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     /* 30 */
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     /* 38 */
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     /* 40 */
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     /* 48 */
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     /* 50 */
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     /* 58 */
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     /* 60 */
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     /* 68 */
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     /* 70 */
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     /* 78 */
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     /* 80 */
8205     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8206     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8207     { "vfrczss",        { XM, EXd }, 0 },
8208     { "vfrczsd",        { XM, EXq }, 0 },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     /* 88 */
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     /* 90 */
8223     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8224     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8225     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8226     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8227     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8228     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8229     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8230     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8231     /* 98 */
8232     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8233     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8234     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8235     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     /* a0 */
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     /* a8 */
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     /* b0 */
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     /* b8 */
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     /* c0 */
8277     { Bad_Opcode },
8278     { "vphaddbw",       { XM, EXxmm }, 0 },
8279     { "vphaddbd",       { XM, EXxmm }, 0 },
8280     { "vphaddbq",       { XM, EXxmm }, 0 },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { "vphaddwd",       { XM, EXxmm }, 0 },
8284     { "vphaddwq",       { XM, EXxmm }, 0 },
8285     /* c8 */
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { "vphadddq",       { XM, EXxmm }, 0 },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     /* d0 */
8295     { Bad_Opcode },
8296     { "vphaddubw",      { XM, EXxmm }, 0 },
8297     { "vphaddubd",      { XM, EXxmm }, 0 },
8298     { "vphaddubq",      { XM, EXxmm }, 0 },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { "vphadduwd",      { XM, EXxmm }, 0 },
8302     { "vphadduwq",      { XM, EXxmm }, 0 },
8303     /* d8 */
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { "vphaddudq",      { XM, EXxmm }, 0 },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     /* e0 */
8313     { Bad_Opcode },
8314     { "vphsubbw",       { XM, EXxmm }, 0 },
8315     { "vphsubwd",       { XM, EXxmm }, 0 },
8316     { "vphsubdq",       { XM, EXxmm }, 0 },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     /* e8 */
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     /* f0 */
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     /* f8 */
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348   },
8349   /* XOP_0A */
8350   {
8351     /* 00 */
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     /* 08 */
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     /* 10 */
8370     { "bextr",  { Gv, Ev, Iq }, 0 },
8371     { Bad_Opcode },
8372     { REG_TABLE (REG_XOP_LWP) },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     /* 18 */
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     /* 20 */
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     /* 28 */
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     /* 30 */
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     /* 38 */
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     /* 40 */
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     /* 48 */
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     /* 50 */
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     /* 58 */
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     /* 60 */
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     /* 68 */
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     /* 70 */
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     /* 78 */
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     /* 80 */
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     /* 88 */
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     /* 90 */
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     /* 98 */
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     /* a0 */
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     /* a8 */
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     /* b0 */
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     /* b8 */
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     /* c0 */
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     /* c8 */
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     /* d0 */
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     /* d8 */
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     /* e0 */
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     /* e8 */
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     /* f0 */
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     /* f8 */
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639   },
8640 };
8641
8642 static const struct dis386 vex_table[][256] = {
8643   /* VEX_0F */
8644   {
8645     /* 00 */
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     /* 08 */
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     /* 10 */
8664     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8667     { MOD_TABLE (MOD_VEX_0F13) },
8668     { VEX_W_TABLE (VEX_W_0F14) },
8669     { VEX_W_TABLE (VEX_W_0F15) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8671     { MOD_TABLE (MOD_VEX_0F17) },
8672     /* 18 */
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     /* 20 */
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     /* 28 */
8691     { VEX_W_TABLE (VEX_W_0F28) },
8692     { VEX_W_TABLE (VEX_W_0F29) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8694     { MOD_TABLE (MOD_VEX_0F2B) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8699     /* 30 */
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     /* 38 */
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     /* 40 */
8718     { Bad_Opcode },
8719     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8721     { Bad_Opcode },
8722     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8726     /* 48 */
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     /* 50 */
8736     { MOD_TABLE (MOD_VEX_0F50) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8740     { "vandpX",         { XM, Vex, EXx }, 0 },
8741     { "vandnpX",        { XM, Vex, EXx }, 0 },
8742     { "vorpX",          { XM, Vex, EXx }, 0 },
8743     { "vxorpX",         { XM, Vex, EXx }, 0 },
8744     /* 58 */
8745     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8753     /* 60 */
8754     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8762     /* 68 */
8763     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8771     /* 70 */
8772     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8773     { REG_TABLE (REG_VEX_0F71) },
8774     { REG_TABLE (REG_VEX_0F72) },
8775     { REG_TABLE (REG_VEX_0F73) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8780     /* 78 */
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8789     /* 80 */
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     /* 88 */
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     /* 90 */
8808     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     /* 98 */
8817     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8818     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     /* a0 */
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     /* a8 */
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { REG_TABLE (REG_VEX_0FAE) },
8842     { Bad_Opcode },
8843     /* b0 */
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     /* b8 */
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     /* c0 */
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8865     { Bad_Opcode },
8866     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8867     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8868     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8869     { Bad_Opcode },
8870     /* c8 */
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     /* d0 */
8880     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8881     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8882     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8883     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8884     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8885     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8886     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8887     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8888     /* d8 */
8889     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8890     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8891     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8892     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8893     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8894     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8895     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8896     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8897     /* e0 */
8898     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8899     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8900     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8901     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8902     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8903     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8904     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8905     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8906     /* e8 */
8907     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8908     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8909     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8910     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8911     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8912     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8913     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8914     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8915     /* f0 */
8916     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8917     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8918     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8919     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8920     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8921     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8922     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8923     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8924     /* f8 */
8925     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8926     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8927     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8928     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8929     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8930     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8931     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8932     { Bad_Opcode },
8933   },
8934   /* VEX_0F38 */
8935   {
8936     /* 00 */
8937     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8945     /* 08 */
8946     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8954     /* 10 */
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8963     /* 18 */
8964     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8967     { Bad_Opcode },
8968     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8971     { Bad_Opcode },
8972     /* 20 */
8973     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     /* 28 */
8982     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8990     /* 30 */
8991     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8999     /* 38 */
9000     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9008     /* 40 */
9009     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9017     /* 48 */
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     /* 50 */
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     /* 58 */
9036     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     /* 60 */
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     /* 68 */
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     /* 70 */
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     /* 78 */
9072     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     /* 80 */
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     /* 88 */
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9095     { Bad_Opcode },
9096     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9097     { Bad_Opcode },
9098     /* 90 */
9099     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9107     /* 98 */
9108     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9114     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9116     /* a0 */
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9125     /* a8 */
9126     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9134     /* b0 */
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9143     /* b8 */
9144     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9145     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9146     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9147     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9149     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9150     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9152     /* c0 */
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     /* c8 */
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     /* d0 */
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     /* d8 */
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9186     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9188     /* e0 */
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     /* e8 */
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     /* f0 */
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9210     { REG_TABLE (REG_VEX_0F38F3) },
9211     { Bad_Opcode },
9212     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9213     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9214     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9215     /* f8 */
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224   },
9225   /* VEX_0F3A */
9226   {
9227     /* 00 */
9228     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9229     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9230     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9231     { Bad_Opcode },
9232     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9233     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9234     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9235     { Bad_Opcode },
9236     /* 08 */
9237     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9238     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9239     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9240     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9241     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9242     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9244     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9245     /* 10 */
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9251     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9252     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9253     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9254     /* 18 */
9255     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9256     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     /* 20 */
9264     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9265     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9266     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     /* 28 */
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     /* 30 */
9282     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9283     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9284     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9285     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     /* 38 */
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9292     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     /* 40 */
9300     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9301     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9302     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9303     { Bad_Opcode },
9304     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9305     { Bad_Opcode },
9306     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9307     { Bad_Opcode },
9308     /* 48 */
9309     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     /* 50 */
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     /* 58 */
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9332     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9333     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9334     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9335     /* 60 */
9336     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9337     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9338     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9339     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     /* 68 */
9345     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9346     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9347     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9348     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9349     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9350     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9351     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9352     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9353     /* 70 */
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     /* 78 */
9363     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9364     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9365     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9366     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9367     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9368     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9369     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9370     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9371     /* 80 */
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     /* 88 */
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     /* 90 */
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     /* 98 */
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     /* a0 */
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     /* a8 */
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     /* b0 */
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     /* b8 */
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     /* c0 */
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     /* c8 */
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     /* d0 */
9462     { Bad_Opcode },
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     /* d8 */
9471     { Bad_Opcode },
9472     { Bad_Opcode },
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     { Bad_Opcode },
9477     { Bad_Opcode },
9478     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9479     /* e0 */
9480     { Bad_Opcode },
9481     { Bad_Opcode },
9482     { Bad_Opcode },
9483     { Bad_Opcode },
9484     { Bad_Opcode },
9485     { Bad_Opcode },
9486     { Bad_Opcode },
9487     { Bad_Opcode },
9488     /* e8 */
9489     { Bad_Opcode },
9490     { Bad_Opcode },
9491     { Bad_Opcode },
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     { Bad_Opcode },
9495     { Bad_Opcode },
9496     { Bad_Opcode },
9497     /* f0 */
9498     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9499     { Bad_Opcode },
9500     { Bad_Opcode },
9501     { Bad_Opcode },
9502     { Bad_Opcode },
9503     { Bad_Opcode },
9504     { Bad_Opcode },
9505     { Bad_Opcode },
9506     /* f8 */
9507     { Bad_Opcode },
9508     { Bad_Opcode },
9509     { Bad_Opcode },
9510     { Bad_Opcode },
9511     { Bad_Opcode },
9512     { Bad_Opcode },
9513     { Bad_Opcode },
9514     { Bad_Opcode },
9515   },
9516 };
9517
9518 #define NEED_OPCODE_TABLE
9519 #include "i386-dis-evex.h"
9520 #undef NEED_OPCODE_TABLE
9521 static const struct dis386 vex_len_table[][2] = {
9522   /* VEX_LEN_0F10_P_1 */
9523   {
9524     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9525     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9526   },
9527
9528   /* VEX_LEN_0F10_P_3 */
9529   {
9530     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9531     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9532   },
9533
9534   /* VEX_LEN_0F11_P_1 */
9535   {
9536     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9537     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9538   },
9539
9540   /* VEX_LEN_0F11_P_3 */
9541   {
9542     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9543     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9544   },
9545
9546   /* VEX_LEN_0F12_P_0_M_0 */
9547   {
9548     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9549   },
9550
9551   /* VEX_LEN_0F12_P_0_M_1 */
9552   {
9553     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9554   },
9555
9556   /* VEX_LEN_0F12_P_2 */
9557   {
9558     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9559   },
9560
9561   /* VEX_LEN_0F13_M_0 */
9562   {
9563     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9564   },
9565
9566   /* VEX_LEN_0F16_P_0_M_0 */
9567   {
9568     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9569   },
9570
9571   /* VEX_LEN_0F16_P_0_M_1 */
9572   {
9573     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9574   },
9575
9576   /* VEX_LEN_0F16_P_2 */
9577   {
9578     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9579   },
9580
9581   /* VEX_LEN_0F17_M_0 */
9582   {
9583     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9584   },
9585
9586   /* VEX_LEN_0F2A_P_1 */
9587   {
9588     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9589     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9590   },
9591
9592   /* VEX_LEN_0F2A_P_3 */
9593   {
9594     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9595     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9596   },
9597
9598   /* VEX_LEN_0F2C_P_1 */
9599   {
9600     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9601     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9602   },
9603
9604   /* VEX_LEN_0F2C_P_3 */
9605   {
9606     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9607     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9608   },
9609
9610   /* VEX_LEN_0F2D_P_1 */
9611   {
9612     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9613     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9614   },
9615
9616   /* VEX_LEN_0F2D_P_3 */
9617   {
9618     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9619     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9620   },
9621
9622   /* VEX_LEN_0F2E_P_0 */
9623   {
9624     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9625     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9626   },
9627
9628   /* VEX_LEN_0F2E_P_2 */
9629   {
9630     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9631     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9632   },
9633
9634   /* VEX_LEN_0F2F_P_0 */
9635   {
9636     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9637     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9638   },
9639
9640   /* VEX_LEN_0F2F_P_2 */
9641   {
9642     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9643     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9644   },
9645
9646   /* VEX_LEN_0F41_P_0 */
9647   {
9648     { Bad_Opcode },
9649     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9650   },
9651   /* VEX_LEN_0F41_P_2 */
9652   {
9653     { Bad_Opcode },
9654     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9655   },
9656   /* VEX_LEN_0F42_P_0 */
9657   {
9658     { Bad_Opcode },
9659     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9660   },
9661   /* VEX_LEN_0F42_P_2 */
9662   {
9663     { Bad_Opcode },
9664     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9665   },
9666   /* VEX_LEN_0F44_P_0 */
9667   {
9668     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9669   },
9670   /* VEX_LEN_0F44_P_2 */
9671   {
9672     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9673   },
9674   /* VEX_LEN_0F45_P_0 */
9675   {
9676     { Bad_Opcode },
9677     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9678   },
9679   /* VEX_LEN_0F45_P_2 */
9680   {
9681     { Bad_Opcode },
9682     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9683   },
9684   /* VEX_LEN_0F46_P_0 */
9685   {
9686     { Bad_Opcode },
9687     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9688   },
9689   /* VEX_LEN_0F46_P_2 */
9690   {
9691     { Bad_Opcode },
9692     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9693   },
9694   /* VEX_LEN_0F47_P_0 */
9695   {
9696     { Bad_Opcode },
9697     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9698   },
9699   /* VEX_LEN_0F47_P_2 */
9700   {
9701     { Bad_Opcode },
9702     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9703   },
9704   /* VEX_LEN_0F4A_P_0 */
9705   {
9706     { Bad_Opcode },
9707     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9708   },
9709   /* VEX_LEN_0F4A_P_2 */
9710   {
9711     { Bad_Opcode },
9712     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9713   },
9714   /* VEX_LEN_0F4B_P_0 */
9715   {
9716     { Bad_Opcode },
9717     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9718   },
9719   /* VEX_LEN_0F4B_P_2 */
9720   {
9721     { Bad_Opcode },
9722     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9723   },
9724
9725   /* VEX_LEN_0F51_P_1 */
9726   {
9727     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9728     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9729   },
9730
9731   /* VEX_LEN_0F51_P_3 */
9732   {
9733     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9734     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9735   },
9736
9737   /* VEX_LEN_0F52_P_1 */
9738   {
9739     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9740     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9741   },
9742
9743   /* VEX_LEN_0F53_P_1 */
9744   {
9745     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9746     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9747   },
9748
9749   /* VEX_LEN_0F58_P_1 */
9750   {
9751     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9752     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9753   },
9754
9755   /* VEX_LEN_0F58_P_3 */
9756   {
9757     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9758     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9759   },
9760
9761   /* VEX_LEN_0F59_P_1 */
9762   {
9763     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9764     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9765   },
9766
9767   /* VEX_LEN_0F59_P_3 */
9768   {
9769     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9770     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9771   },
9772
9773   /* VEX_LEN_0F5A_P_1 */
9774   {
9775     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9776     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9777   },
9778
9779   /* VEX_LEN_0F5A_P_3 */
9780   {
9781     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9782     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9783   },
9784
9785   /* VEX_LEN_0F5C_P_1 */
9786   {
9787     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9788     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9789   },
9790
9791   /* VEX_LEN_0F5C_P_3 */
9792   {
9793     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9794     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9795   },
9796
9797   /* VEX_LEN_0F5D_P_1 */
9798   {
9799     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9800     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9801   },
9802
9803   /* VEX_LEN_0F5D_P_3 */
9804   {
9805     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9806     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9807   },
9808
9809   /* VEX_LEN_0F5E_P_1 */
9810   {
9811     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9812     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9813   },
9814
9815   /* VEX_LEN_0F5E_P_3 */
9816   {
9817     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9818     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9819   },
9820
9821   /* VEX_LEN_0F5F_P_1 */
9822   {
9823     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9824     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9825   },
9826
9827   /* VEX_LEN_0F5F_P_3 */
9828   {
9829     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9830     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9831   },
9832
9833   /* VEX_LEN_0F6E_P_2 */
9834   {
9835     { "vmovK",          { XMScalar, Edq }, 0 },
9836     { "vmovK",          { XMScalar, Edq }, 0 },
9837   },
9838
9839   /* VEX_LEN_0F7E_P_1 */
9840   {
9841     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9842     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9843   },
9844
9845   /* VEX_LEN_0F7E_P_2 */
9846   {
9847     { "vmovK",          { Edq, XMScalar }, 0 },
9848     { "vmovK",          { Edq, XMScalar }, 0 },
9849   },
9850
9851   /* VEX_LEN_0F90_P_0 */
9852   {
9853     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9854   },
9855
9856   /* VEX_LEN_0F90_P_2 */
9857   {
9858     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9859   },
9860
9861   /* VEX_LEN_0F91_P_0 */
9862   {
9863     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9864   },
9865
9866   /* VEX_LEN_0F91_P_2 */
9867   {
9868     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9869   },
9870
9871   /* VEX_LEN_0F92_P_0 */
9872   {
9873     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9874   },
9875
9876   /* VEX_LEN_0F92_P_2 */
9877   {
9878     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9879   },
9880
9881   /* VEX_LEN_0F92_P_3 */
9882   {
9883     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9884   },
9885
9886   /* VEX_LEN_0F93_P_0 */
9887   {
9888     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9889   },
9890
9891   /* VEX_LEN_0F93_P_2 */
9892   {
9893     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9894   },
9895
9896   /* VEX_LEN_0F93_P_3 */
9897   {
9898     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9899   },
9900
9901   /* VEX_LEN_0F98_P_0 */
9902   {
9903     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9904   },
9905
9906   /* VEX_LEN_0F98_P_2 */
9907   {
9908     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9909   },
9910
9911   /* VEX_LEN_0F99_P_0 */
9912   {
9913     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9914   },
9915
9916   /* VEX_LEN_0F99_P_2 */
9917   {
9918     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9919   },
9920
9921   /* VEX_LEN_0FAE_R_2_M_0 */
9922   {
9923     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9924   },
9925
9926   /* VEX_LEN_0FAE_R_3_M_0 */
9927   {
9928     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9929   },
9930
9931   /* VEX_LEN_0FC2_P_1 */
9932   {
9933     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9934     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9935   },
9936
9937   /* VEX_LEN_0FC2_P_3 */
9938   {
9939     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9940     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9941   },
9942
9943   /* VEX_LEN_0FC4_P_2 */
9944   {
9945     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9946   },
9947
9948   /* VEX_LEN_0FC5_P_2 */
9949   {
9950     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9951   },
9952
9953   /* VEX_LEN_0FD6_P_2 */
9954   {
9955     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9956     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9957   },
9958
9959   /* VEX_LEN_0FF7_P_2 */
9960   {
9961     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9962   },
9963
9964   /* VEX_LEN_0F3816_P_2 */
9965   {
9966     { Bad_Opcode },
9967     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9968   },
9969
9970   /* VEX_LEN_0F3819_P_2 */
9971   {
9972     { Bad_Opcode },
9973     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9974   },
9975
9976   /* VEX_LEN_0F381A_P_2_M_0 */
9977   {
9978     { Bad_Opcode },
9979     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9980   },
9981
9982   /* VEX_LEN_0F3836_P_2 */
9983   {
9984     { Bad_Opcode },
9985     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9986   },
9987
9988   /* VEX_LEN_0F3841_P_2 */
9989   {
9990     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9991   },
9992
9993   /* VEX_LEN_0F385A_P_2_M_0 */
9994   {
9995     { Bad_Opcode },
9996     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9997   },
9998
9999   /* VEX_LEN_0F38DB_P_2 */
10000   {
10001     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10002   },
10003
10004   /* VEX_LEN_0F38DC_P_2 */
10005   {
10006     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
10007   },
10008
10009   /* VEX_LEN_0F38DD_P_2 */
10010   {
10011     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
10012   },
10013
10014   /* VEX_LEN_0F38DE_P_2 */
10015   {
10016     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
10017   },
10018
10019   /* VEX_LEN_0F38DF_P_2 */
10020   {
10021     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10022   },
10023
10024   /* VEX_LEN_0F38F2_P_0 */
10025   {
10026     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10027   },
10028
10029   /* VEX_LEN_0F38F3_R_1_P_0 */
10030   {
10031     { "blsrS",          { VexGdq, Edq }, 0 },
10032   },
10033
10034   /* VEX_LEN_0F38F3_R_2_P_0 */
10035   {
10036     { "blsmskS",        { VexGdq, Edq }, 0 },
10037   },
10038
10039   /* VEX_LEN_0F38F3_R_3_P_0 */
10040   {
10041     { "blsiS",          { VexGdq, Edq }, 0 },
10042   },
10043
10044   /* VEX_LEN_0F38F5_P_0 */
10045   {
10046     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10047   },
10048
10049   /* VEX_LEN_0F38F5_P_1 */
10050   {
10051     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10052   },
10053
10054   /* VEX_LEN_0F38F5_P_3 */
10055   {
10056     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10057   },
10058
10059   /* VEX_LEN_0F38F6_P_3 */
10060   {
10061     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10062   },
10063
10064   /* VEX_LEN_0F38F7_P_0 */
10065   {
10066     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10067   },
10068
10069   /* VEX_LEN_0F38F7_P_1 */
10070   {
10071     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10072   },
10073
10074   /* VEX_LEN_0F38F7_P_2 */
10075   {
10076     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10077   },
10078
10079   /* VEX_LEN_0F38F7_P_3 */
10080   {
10081     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10082   },
10083
10084   /* VEX_LEN_0F3A00_P_2 */
10085   {
10086     { Bad_Opcode },
10087     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10088   },
10089
10090   /* VEX_LEN_0F3A01_P_2 */
10091   {
10092     { Bad_Opcode },
10093     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10094   },
10095
10096   /* VEX_LEN_0F3A06_P_2 */
10097   {
10098     { Bad_Opcode },
10099     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10100   },
10101
10102   /* VEX_LEN_0F3A0A_P_2 */
10103   {
10104     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10105     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10106   },
10107
10108   /* VEX_LEN_0F3A0B_P_2 */
10109   {
10110     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10111     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10112   },
10113
10114   /* VEX_LEN_0F3A14_P_2 */
10115   {
10116     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10117   },
10118
10119   /* VEX_LEN_0F3A15_P_2 */
10120   {
10121     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10122   },
10123
10124   /* VEX_LEN_0F3A16_P_2  */
10125   {
10126     { "vpextrK",        { Edq, XM, Ib }, 0 },
10127   },
10128
10129   /* VEX_LEN_0F3A17_P_2 */
10130   {
10131     { "vextractps",     { Edqd, XM, Ib }, 0 },
10132   },
10133
10134   /* VEX_LEN_0F3A18_P_2 */
10135   {
10136     { Bad_Opcode },
10137     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10138   },
10139
10140   /* VEX_LEN_0F3A19_P_2 */
10141   {
10142     { Bad_Opcode },
10143     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10144   },
10145
10146   /* VEX_LEN_0F3A20_P_2 */
10147   {
10148     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10149   },
10150
10151   /* VEX_LEN_0F3A21_P_2 */
10152   {
10153     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10154   },
10155
10156   /* VEX_LEN_0F3A22_P_2 */
10157   {
10158     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10159   },
10160
10161   /* VEX_LEN_0F3A30_P_2 */
10162   {
10163     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10164   },
10165
10166   /* VEX_LEN_0F3A31_P_2 */
10167   {
10168     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10169   },
10170
10171   /* VEX_LEN_0F3A32_P_2 */
10172   {
10173     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10174   },
10175
10176   /* VEX_LEN_0F3A33_P_2 */
10177   {
10178     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10179   },
10180
10181   /* VEX_LEN_0F3A38_P_2 */
10182   {
10183     { Bad_Opcode },
10184     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10185   },
10186
10187   /* VEX_LEN_0F3A39_P_2 */
10188   {
10189     { Bad_Opcode },
10190     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10191   },
10192
10193   /* VEX_LEN_0F3A41_P_2 */
10194   {
10195     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10196   },
10197
10198   /* VEX_LEN_0F3A44_P_2 */
10199   {
10200     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10201   },
10202
10203   /* VEX_LEN_0F3A46_P_2 */
10204   {
10205     { Bad_Opcode },
10206     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10207   },
10208
10209   /* VEX_LEN_0F3A60_P_2 */
10210   {
10211     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10212   },
10213
10214   /* VEX_LEN_0F3A61_P_2 */
10215   {
10216     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10217   },
10218
10219   /* VEX_LEN_0F3A62_P_2 */
10220   {
10221     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10222   },
10223
10224   /* VEX_LEN_0F3A63_P_2 */
10225   {
10226     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10227   },
10228
10229   /* VEX_LEN_0F3A6A_P_2 */
10230   {
10231     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10232   },
10233
10234   /* VEX_LEN_0F3A6B_P_2 */
10235   {
10236     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10237   },
10238
10239   /* VEX_LEN_0F3A6E_P_2 */
10240   {
10241     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10242   },
10243
10244   /* VEX_LEN_0F3A6F_P_2 */
10245   {
10246     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10247   },
10248
10249   /* VEX_LEN_0F3A7A_P_2 */
10250   {
10251     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10252   },
10253
10254   /* VEX_LEN_0F3A7B_P_2 */
10255   {
10256     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10257   },
10258
10259   /* VEX_LEN_0F3A7E_P_2 */
10260   {
10261     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10262   },
10263
10264   /* VEX_LEN_0F3A7F_P_2 */
10265   {
10266     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10267   },
10268
10269   /* VEX_LEN_0F3ADF_P_2 */
10270   {
10271     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10272   },
10273
10274   /* VEX_LEN_0F3AF0_P_3 */
10275   {
10276     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10277   },
10278
10279   /* VEX_LEN_0FXOP_08_CC */
10280   {
10281      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10282   },
10283
10284   /* VEX_LEN_0FXOP_08_CD */
10285   {
10286      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10287   },
10288
10289   /* VEX_LEN_0FXOP_08_CE */
10290   {
10291      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10292   },
10293
10294   /* VEX_LEN_0FXOP_08_CF */
10295   {
10296      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10297   },
10298
10299   /* VEX_LEN_0FXOP_08_EC */
10300   {
10301      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10302   },
10303
10304   /* VEX_LEN_0FXOP_08_ED */
10305   {
10306      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10307   },
10308
10309   /* VEX_LEN_0FXOP_08_EE */
10310   {
10311      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10312   },
10313
10314   /* VEX_LEN_0FXOP_08_EF */
10315   {
10316      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10317   },
10318
10319   /* VEX_LEN_0FXOP_09_80 */
10320   {
10321     { "vfrczps",        { XM, EXxmm }, 0 },
10322     { "vfrczps",        { XM, EXymmq }, 0 },
10323   },
10324
10325   /* VEX_LEN_0FXOP_09_81 */
10326   {
10327     { "vfrczpd",        { XM, EXxmm }, 0 },
10328     { "vfrczpd",        { XM, EXymmq }, 0 },
10329   },
10330 };
10331
10332 static const struct dis386 vex_w_table[][2] = {
10333   {
10334     /* VEX_W_0F10_P_0 */
10335     { "vmovups",        { XM, EXx }, 0 },
10336   },
10337   {
10338     /* VEX_W_0F10_P_1 */
10339     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10340   },
10341   {
10342     /* VEX_W_0F10_P_2 */
10343     { "vmovupd",        { XM, EXx }, 0 },
10344   },
10345   {
10346     /* VEX_W_0F10_P_3 */
10347     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10348   },
10349   {
10350     /* VEX_W_0F11_P_0 */
10351     { "vmovups",        { EXxS, XM }, 0 },
10352   },
10353   {
10354     /* VEX_W_0F11_P_1 */
10355     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10356   },
10357   {
10358     /* VEX_W_0F11_P_2 */
10359     { "vmovupd",        { EXxS, XM }, 0 },
10360   },
10361   {
10362     /* VEX_W_0F11_P_3 */
10363     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10364   },
10365   {
10366     /* VEX_W_0F12_P_0_M_0 */
10367     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10368   },
10369   {
10370     /* VEX_W_0F12_P_0_M_1 */
10371     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10372   },
10373   {
10374     /* VEX_W_0F12_P_1 */
10375     { "vmovsldup",      { XM, EXx }, 0 },
10376   },
10377   {
10378     /* VEX_W_0F12_P_2 */
10379     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10380   },
10381   {
10382     /* VEX_W_0F12_P_3 */
10383     { "vmovddup",       { XM, EXymmq }, 0 },
10384   },
10385   {
10386     /* VEX_W_0F13_M_0 */
10387     { "vmovlpX",        { EXq, XM }, 0 },
10388   },
10389   {
10390     /* VEX_W_0F14 */
10391     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10392   },
10393   {
10394     /* VEX_W_0F15 */
10395     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10396   },
10397   {
10398     /* VEX_W_0F16_P_0_M_0 */
10399     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10400   },
10401   {
10402     /* VEX_W_0F16_P_0_M_1 */
10403     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10404   },
10405   {
10406     /* VEX_W_0F16_P_1 */
10407     { "vmovshdup",      { XM, EXx }, 0 },
10408   },
10409   {
10410     /* VEX_W_0F16_P_2 */
10411     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10412   },
10413   {
10414     /* VEX_W_0F17_M_0 */
10415     { "vmovhpX",        { EXq, XM }, 0 },
10416   },
10417   {
10418     /* VEX_W_0F28 */
10419     { "vmovapX",        { XM, EXx }, 0 },
10420   },
10421   {
10422     /* VEX_W_0F29 */
10423     { "vmovapX",        { EXxS, XM }, 0 },
10424   },
10425   {
10426     /* VEX_W_0F2B_M_0 */
10427     { "vmovntpX",       { Mx, XM }, 0 },
10428   },
10429   {
10430     /* VEX_W_0F2E_P_0 */
10431     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10432   },
10433   {
10434     /* VEX_W_0F2E_P_2 */
10435     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10436   },
10437   {
10438     /* VEX_W_0F2F_P_0 */
10439     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10440   },
10441   {
10442     /* VEX_W_0F2F_P_2 */
10443     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10444   },
10445   {
10446     /* VEX_W_0F41_P_0_LEN_1 */
10447     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10448     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10449   },
10450   {
10451     /* VEX_W_0F41_P_2_LEN_1 */
10452     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10453     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10454   },
10455   {
10456     /* VEX_W_0F42_P_0_LEN_1 */
10457     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10458     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10459   },
10460   {
10461     /* VEX_W_0F42_P_2_LEN_1 */
10462     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10463     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10464   },
10465   {
10466     /* VEX_W_0F44_P_0_LEN_0 */
10467     { "knotw",          { MaskG, MaskR }, 0 },
10468     { "knotq",          { MaskG, MaskR }, 0 },
10469   },
10470   {
10471     /* VEX_W_0F44_P_2_LEN_0 */
10472     { "knotb",          { MaskG, MaskR }, 0 },
10473     { "knotd",          { MaskG, MaskR }, 0 },
10474   },
10475   {
10476     /* VEX_W_0F45_P_0_LEN_1 */
10477     { "korw",           { MaskG, MaskVex, MaskR }, 0 },
10478     { "korq",           { MaskG, MaskVex, MaskR }, 0 },
10479   },
10480   {
10481     /* VEX_W_0F45_P_2_LEN_1 */
10482     { "korb",           { MaskG, MaskVex, MaskR }, 0 },
10483     { "kord",           { MaskG, MaskVex, MaskR }, 0 },
10484   },
10485   {
10486     /* VEX_W_0F46_P_0_LEN_1 */
10487     { "kxnorw",         { MaskG, MaskVex, MaskR }, 0 },
10488     { "kxnorq",         { MaskG, MaskVex, MaskR }, 0 },
10489   },
10490   {
10491     /* VEX_W_0F46_P_2_LEN_1 */
10492     { "kxnorb",         { MaskG, MaskVex, MaskR }, 0 },
10493     { "kxnord",         { MaskG, MaskVex, MaskR }, 0 },
10494   },
10495   {
10496     /* VEX_W_0F47_P_0_LEN_1 */
10497     { "kxorw",          { MaskG, MaskVex, MaskR }, 0 },
10498     { "kxorq",          { MaskG, MaskVex, MaskR }, 0 },
10499   },
10500   {
10501     /* VEX_W_0F47_P_2_LEN_1 */
10502     { "kxorb",          { MaskG, MaskVex, MaskR }, 0 },
10503     { "kxord",          { MaskG, MaskVex, MaskR }, 0 },
10504   },
10505   {
10506     /* VEX_W_0F4A_P_0_LEN_1 */
10507     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10508     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10509   },
10510   {
10511     /* VEX_W_0F4A_P_2_LEN_1 */
10512     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10513     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10514   },
10515   {
10516     /* VEX_W_0F4B_P_0_LEN_1 */
10517     { "kunpckwd",       { MaskG, MaskVex, MaskR }, 0 },
10518     { "kunpckdq",       { MaskG, MaskVex, MaskR }, 0 },
10519   },
10520   {
10521     /* VEX_W_0F4B_P_2_LEN_1 */
10522     { "kunpckbw",       { MaskG, MaskVex, MaskR }, 0 },
10523   },
10524   {
10525     /* VEX_W_0F50_M_0 */
10526     { "vmovmskpX",      { Gdq, XS }, 0 },
10527   },
10528   {
10529     /* VEX_W_0F51_P_0 */
10530     { "vsqrtps",        { XM, EXx }, 0 },
10531   },
10532   {
10533     /* VEX_W_0F51_P_1 */
10534     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10535   },
10536   {
10537     /* VEX_W_0F51_P_2  */
10538     { "vsqrtpd",        { XM, EXx }, 0 },
10539   },
10540   {
10541     /* VEX_W_0F51_P_3 */
10542     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10543   },
10544   {
10545     /* VEX_W_0F52_P_0 */
10546     { "vrsqrtps",       { XM, EXx }, 0 },
10547   },
10548   {
10549     /* VEX_W_0F52_P_1 */
10550     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10551   },
10552   {
10553     /* VEX_W_0F53_P_0  */
10554     { "vrcpps",         { XM, EXx }, 0 },
10555   },
10556   {
10557     /* VEX_W_0F53_P_1  */
10558     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10559   },
10560   {
10561     /* VEX_W_0F58_P_0  */
10562     { "vaddps",         { XM, Vex, EXx }, 0 },
10563   },
10564   {
10565     /* VEX_W_0F58_P_1  */
10566     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10567   },
10568   {
10569     /* VEX_W_0F58_P_2  */
10570     { "vaddpd",         { XM, Vex, EXx }, 0 },
10571   },
10572   {
10573     /* VEX_W_0F58_P_3  */
10574     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10575   },
10576   {
10577     /* VEX_W_0F59_P_0  */
10578     { "vmulps",         { XM, Vex, EXx }, 0 },
10579   },
10580   {
10581     /* VEX_W_0F59_P_1  */
10582     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10583   },
10584   {
10585     /* VEX_W_0F59_P_2  */
10586     { "vmulpd",         { XM, Vex, EXx }, 0 },
10587   },
10588   {
10589     /* VEX_W_0F59_P_3  */
10590     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10591   },
10592   {
10593     /* VEX_W_0F5A_P_0  */
10594     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10595   },
10596   {
10597     /* VEX_W_0F5A_P_1  */
10598     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10599   },
10600   {
10601     /* VEX_W_0F5A_P_3  */
10602     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10603   },
10604   {
10605     /* VEX_W_0F5B_P_0  */
10606     { "vcvtdq2ps",      { XM, EXx }, 0 },
10607   },
10608   {
10609     /* VEX_W_0F5B_P_1  */
10610     { "vcvttps2dq",     { XM, EXx }, 0 },
10611   },
10612   {
10613     /* VEX_W_0F5B_P_2  */
10614     { "vcvtps2dq",      { XM, EXx }, 0 },
10615   },
10616   {
10617     /* VEX_W_0F5C_P_0  */
10618     { "vsubps",         { XM, Vex, EXx }, 0 },
10619   },
10620   {
10621     /* VEX_W_0F5C_P_1  */
10622     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10623   },
10624   {
10625     /* VEX_W_0F5C_P_2  */
10626     { "vsubpd",         { XM, Vex, EXx }, 0 },
10627   },
10628   {
10629     /* VEX_W_0F5C_P_3  */
10630     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10631   },
10632   {
10633     /* VEX_W_0F5D_P_0  */
10634     { "vminps",         { XM, Vex, EXx }, 0 },
10635   },
10636   {
10637     /* VEX_W_0F5D_P_1  */
10638     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10639   },
10640   {
10641     /* VEX_W_0F5D_P_2  */
10642     { "vminpd",         { XM, Vex, EXx }, 0 },
10643   },
10644   {
10645     /* VEX_W_0F5D_P_3  */
10646     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10647   },
10648   {
10649     /* VEX_W_0F5E_P_0  */
10650     { "vdivps",         { XM, Vex, EXx }, 0 },
10651   },
10652   {
10653     /* VEX_W_0F5E_P_1  */
10654     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10655   },
10656   {
10657     /* VEX_W_0F5E_P_2  */
10658     { "vdivpd",         { XM, Vex, EXx }, 0 },
10659   },
10660   {
10661     /* VEX_W_0F5E_P_3  */
10662     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10663   },
10664   {
10665     /* VEX_W_0F5F_P_0  */
10666     { "vmaxps",         { XM, Vex, EXx }, 0 },
10667   },
10668   {
10669     /* VEX_W_0F5F_P_1  */
10670     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10671   },
10672   {
10673     /* VEX_W_0F5F_P_2  */
10674     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10675   },
10676   {
10677     /* VEX_W_0F5F_P_3  */
10678     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10679   },
10680   {
10681     /* VEX_W_0F60_P_2  */
10682     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10683   },
10684   {
10685     /* VEX_W_0F61_P_2  */
10686     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10687   },
10688   {
10689     /* VEX_W_0F62_P_2  */
10690     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10691   },
10692   {
10693     /* VEX_W_0F63_P_2  */
10694     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10695   },
10696   {
10697     /* VEX_W_0F64_P_2  */
10698     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10699   },
10700   {
10701     /* VEX_W_0F65_P_2  */
10702     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10703   },
10704   {
10705     /* VEX_W_0F66_P_2  */
10706     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10707   },
10708   {
10709     /* VEX_W_0F67_P_2  */
10710     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10711   },
10712   {
10713     /* VEX_W_0F68_P_2  */
10714     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10715   },
10716   {
10717     /* VEX_W_0F69_P_2  */
10718     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10719   },
10720   {
10721     /* VEX_W_0F6A_P_2  */
10722     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10723   },
10724   {
10725     /* VEX_W_0F6B_P_2  */
10726     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10727   },
10728   {
10729     /* VEX_W_0F6C_P_2  */
10730     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10731   },
10732   {
10733     /* VEX_W_0F6D_P_2  */
10734     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10735   },
10736   {
10737     /* VEX_W_0F6F_P_1  */
10738     { "vmovdqu",        { XM, EXx }, 0 },
10739   },
10740   {
10741     /* VEX_W_0F6F_P_2  */
10742     { "vmovdqa",        { XM, EXx }, 0 },
10743   },
10744   {
10745     /* VEX_W_0F70_P_1 */
10746     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10747   },
10748   {
10749     /* VEX_W_0F70_P_2 */
10750     { "vpshufd",        { XM, EXx, Ib }, 0 },
10751   },
10752   {
10753     /* VEX_W_0F70_P_3 */
10754     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10755   },
10756   {
10757     /* VEX_W_0F71_R_2_P_2  */
10758     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10759   },
10760   {
10761     /* VEX_W_0F71_R_4_P_2  */
10762     { "vpsraw",         { Vex, XS, Ib }, 0 },
10763   },
10764   {
10765     /* VEX_W_0F71_R_6_P_2  */
10766     { "vpsllw",         { Vex, XS, Ib }, 0 },
10767   },
10768   {
10769     /* VEX_W_0F72_R_2_P_2  */
10770     { "vpsrld",         { Vex, XS, Ib }, 0 },
10771   },
10772   {
10773     /* VEX_W_0F72_R_4_P_2  */
10774     { "vpsrad",         { Vex, XS, Ib }, 0 },
10775   },
10776   {
10777     /* VEX_W_0F72_R_6_P_2  */
10778     { "vpslld",         { Vex, XS, Ib }, 0 },
10779   },
10780   {
10781     /* VEX_W_0F73_R_2_P_2  */
10782     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10783   },
10784   {
10785     /* VEX_W_0F73_R_3_P_2  */
10786     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10787   },
10788   {
10789     /* VEX_W_0F73_R_6_P_2  */
10790     { "vpsllq",         { Vex, XS, Ib }, 0 },
10791   },
10792   {
10793     /* VEX_W_0F73_R_7_P_2  */
10794     { "vpslldq",        { Vex, XS, Ib }, 0 },
10795   },
10796   {
10797     /* VEX_W_0F74_P_2 */
10798     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10799   },
10800   {
10801     /* VEX_W_0F75_P_2 */
10802     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10803   },
10804   {
10805     /* VEX_W_0F76_P_2 */
10806     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10807   },
10808   {
10809     /* VEX_W_0F77_P_0 */
10810     { "",               { VZERO }, 0 },
10811   },
10812   {
10813     /* VEX_W_0F7C_P_2 */
10814     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10815   },
10816   {
10817     /* VEX_W_0F7C_P_3 */
10818     { "vhaddps",        { XM, Vex, EXx }, 0 },
10819   },
10820   {
10821     /* VEX_W_0F7D_P_2 */
10822     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10823   },
10824   {
10825     /* VEX_W_0F7D_P_3 */
10826     { "vhsubps",        { XM, Vex, EXx }, 0 },
10827   },
10828   {
10829     /* VEX_W_0F7E_P_1 */
10830     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10831   },
10832   {
10833     /* VEX_W_0F7F_P_1 */
10834     { "vmovdqu",        { EXxS, XM }, 0 },
10835   },
10836   {
10837     /* VEX_W_0F7F_P_2 */
10838     { "vmovdqa",        { EXxS, XM }, 0 },
10839   },
10840   {
10841     /* VEX_W_0F90_P_0_LEN_0 */
10842     { "kmovw",          { MaskG, MaskE }, 0 },
10843     { "kmovq",          { MaskG, MaskE }, 0 },
10844   },
10845   {
10846     /* VEX_W_0F90_P_2_LEN_0 */
10847     { "kmovb",          { MaskG, MaskBDE }, 0 },
10848     { "kmovd",          { MaskG, MaskBDE }, 0 },
10849   },
10850   {
10851     /* VEX_W_0F91_P_0_LEN_0 */
10852     { "kmovw",          { Ew, MaskG }, 0 },
10853     { "kmovq",          { Eq, MaskG }, 0 },
10854   },
10855   {
10856     /* VEX_W_0F91_P_2_LEN_0 */
10857     { "kmovb",          { Eb, MaskG }, 0 },
10858     { "kmovd",          { Ed, MaskG }, 0 },
10859   },
10860   {
10861     /* VEX_W_0F92_P_0_LEN_0 */
10862     { "kmovw",          { MaskG, Rdq }, 0 },
10863   },
10864   {
10865     /* VEX_W_0F92_P_2_LEN_0 */
10866     { "kmovb",          { MaskG, Rdq }, 0 },
10867   },
10868   {
10869     /* VEX_W_0F92_P_3_LEN_0 */
10870     { "kmovd",          { MaskG, Rdq }, 0 },
10871     { "kmovq",          { MaskG, Rdq }, 0 },
10872   },
10873   {
10874     /* VEX_W_0F93_P_0_LEN_0 */
10875     { "kmovw",          { Gdq, MaskR }, 0 },
10876   },
10877   {
10878     /* VEX_W_0F93_P_2_LEN_0 */
10879     { "kmovb",          { Gdq, MaskR }, 0 },
10880   },
10881   {
10882     /* VEX_W_0F93_P_3_LEN_0 */
10883     { "kmovd",          { Gdq, MaskR }, 0 },
10884     { "kmovq",          { Gdq, MaskR }, 0 },
10885   },
10886   {
10887     /* VEX_W_0F98_P_0_LEN_0 */
10888     { "kortestw",       { MaskG, MaskR }, 0 },
10889     { "kortestq",       { MaskG, MaskR }, 0 },
10890   },
10891   {
10892     /* VEX_W_0F98_P_2_LEN_0 */
10893     { "kortestb",       { MaskG, MaskR }, 0 },
10894     { "kortestd",       { MaskG, MaskR }, 0 },
10895   },
10896   {
10897     /* VEX_W_0F99_P_0_LEN_0 */
10898     { "ktestw", { MaskG, MaskR }, 0 },
10899     { "ktestq", { MaskG, MaskR }, 0 },
10900   },
10901   {
10902     /* VEX_W_0F99_P_2_LEN_0 */
10903     { "ktestb", { MaskG, MaskR }, 0 },
10904     { "ktestd", { MaskG, MaskR }, 0 },
10905   },
10906   {
10907     /* VEX_W_0FAE_R_2_M_0 */
10908     { "vldmxcsr",       { Md }, 0 },
10909   },
10910   {
10911     /* VEX_W_0FAE_R_3_M_0 */
10912     { "vstmxcsr",       { Md }, 0 },
10913   },
10914   {
10915     /* VEX_W_0FC2_P_0 */
10916     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10917   },
10918   {
10919     /* VEX_W_0FC2_P_1 */
10920     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10921   },
10922   {
10923     /* VEX_W_0FC2_P_2 */
10924     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10925   },
10926   {
10927     /* VEX_W_0FC2_P_3 */
10928     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10929   },
10930   {
10931     /* VEX_W_0FC4_P_2 */
10932     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10933   },
10934   {
10935     /* VEX_W_0FC5_P_2 */
10936     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10937   },
10938   {
10939     /* VEX_W_0FD0_P_2 */
10940     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10941   },
10942   {
10943     /* VEX_W_0FD0_P_3 */
10944     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10945   },
10946   {
10947     /* VEX_W_0FD1_P_2 */
10948     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10949   },
10950   {
10951     /* VEX_W_0FD2_P_2 */
10952     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10953   },
10954   {
10955     /* VEX_W_0FD3_P_2 */
10956     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10957   },
10958   {
10959     /* VEX_W_0FD4_P_2 */
10960     { "vpaddq",         { XM, Vex, EXx }, 0 },
10961   },
10962   {
10963     /* VEX_W_0FD5_P_2 */
10964     { "vpmullw",        { XM, Vex, EXx }, 0 },
10965   },
10966   {
10967     /* VEX_W_0FD6_P_2 */
10968     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10969   },
10970   {
10971     /* VEX_W_0FD7_P_2_M_1 */
10972     { "vpmovmskb",      { Gdq, XS }, 0 },
10973   },
10974   {
10975     /* VEX_W_0FD8_P_2 */
10976     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10977   },
10978   {
10979     /* VEX_W_0FD9_P_2 */
10980     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10981   },
10982   {
10983     /* VEX_W_0FDA_P_2 */
10984     { "vpminub",        { XM, Vex, EXx }, 0 },
10985   },
10986   {
10987     /* VEX_W_0FDB_P_2 */
10988     { "vpand",          { XM, Vex, EXx }, 0 },
10989   },
10990   {
10991     /* VEX_W_0FDC_P_2 */
10992     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10993   },
10994   {
10995     /* VEX_W_0FDD_P_2 */
10996     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10997   },
10998   {
10999     /* VEX_W_0FDE_P_2 */
11000     { "vpmaxub",        { XM, Vex, EXx }, 0 },
11001   },
11002   {
11003     /* VEX_W_0FDF_P_2 */
11004     { "vpandn",         { XM, Vex, EXx }, 0 },
11005   },
11006   {
11007     /* VEX_W_0FE0_P_2  */
11008     { "vpavgb",         { XM, Vex, EXx }, 0 },
11009   },
11010   {
11011     /* VEX_W_0FE1_P_2  */
11012     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
11013   },
11014   {
11015     /* VEX_W_0FE2_P_2  */
11016     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
11017   },
11018   {
11019     /* VEX_W_0FE3_P_2  */
11020     { "vpavgw",         { XM, Vex, EXx }, 0 },
11021   },
11022   {
11023     /* VEX_W_0FE4_P_2  */
11024     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11025   },
11026   {
11027     /* VEX_W_0FE5_P_2  */
11028     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11029   },
11030   {
11031     /* VEX_W_0FE6_P_1  */
11032     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11033   },
11034   {
11035     /* VEX_W_0FE6_P_2  */
11036     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11037   },
11038   {
11039     /* VEX_W_0FE6_P_3  */
11040     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11041   },
11042   {
11043     /* VEX_W_0FE7_P_2_M_0 */
11044     { "vmovntdq",       { Mx, XM }, 0 },
11045   },
11046   {
11047     /* VEX_W_0FE8_P_2  */
11048     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11049   },
11050   {
11051     /* VEX_W_0FE9_P_2  */
11052     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11053   },
11054   {
11055     /* VEX_W_0FEA_P_2  */
11056     { "vpminsw",        { XM, Vex, EXx }, 0 },
11057   },
11058   {
11059     /* VEX_W_0FEB_P_2  */
11060     { "vpor",           { XM, Vex, EXx }, 0 },
11061   },
11062   {
11063     /* VEX_W_0FEC_P_2  */
11064     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11065   },
11066   {
11067     /* VEX_W_0FED_P_2  */
11068     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11069   },
11070   {
11071     /* VEX_W_0FEE_P_2  */
11072     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11073   },
11074   {
11075     /* VEX_W_0FEF_P_2  */
11076     { "vpxor",          { XM, Vex, EXx }, 0 },
11077   },
11078   {
11079     /* VEX_W_0FF0_P_3_M_0 */
11080     { "vlddqu",         { XM, M }, 0 },
11081   },
11082   {
11083     /* VEX_W_0FF1_P_2 */
11084     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11085   },
11086   {
11087     /* VEX_W_0FF2_P_2 */
11088     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11089   },
11090   {
11091     /* VEX_W_0FF3_P_2 */
11092     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11093   },
11094   {
11095     /* VEX_W_0FF4_P_2 */
11096     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11097   },
11098   {
11099     /* VEX_W_0FF5_P_2 */
11100     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11101   },
11102   {
11103     /* VEX_W_0FF6_P_2 */
11104     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11105   },
11106   {
11107     /* VEX_W_0FF7_P_2 */
11108     { "vmaskmovdqu",    { XM, XS }, 0 },
11109   },
11110   {
11111     /* VEX_W_0FF8_P_2 */
11112     { "vpsubb",         { XM, Vex, EXx }, 0 },
11113   },
11114   {
11115     /* VEX_W_0FF9_P_2 */
11116     { "vpsubw",         { XM, Vex, EXx }, 0 },
11117   },
11118   {
11119     /* VEX_W_0FFA_P_2 */
11120     { "vpsubd",         { XM, Vex, EXx }, 0 },
11121   },
11122   {
11123     /* VEX_W_0FFB_P_2 */
11124     { "vpsubq",         { XM, Vex, EXx }, 0 },
11125   },
11126   {
11127     /* VEX_W_0FFC_P_2 */
11128     { "vpaddb",         { XM, Vex, EXx }, 0 },
11129   },
11130   {
11131     /* VEX_W_0FFD_P_2 */
11132     { "vpaddw",         { XM, Vex, EXx }, 0 },
11133   },
11134   {
11135     /* VEX_W_0FFE_P_2 */
11136     { "vpaddd",         { XM, Vex, EXx }, 0 },
11137   },
11138   {
11139     /* VEX_W_0F3800_P_2  */
11140     { "vpshufb",        { XM, Vex, EXx }, 0 },
11141   },
11142   {
11143     /* VEX_W_0F3801_P_2  */
11144     { "vphaddw",        { XM, Vex, EXx }, 0 },
11145   },
11146   {
11147     /* VEX_W_0F3802_P_2  */
11148     { "vphaddd",        { XM, Vex, EXx }, 0 },
11149   },
11150   {
11151     /* VEX_W_0F3803_P_2  */
11152     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11153   },
11154   {
11155     /* VEX_W_0F3804_P_2  */
11156     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11157   },
11158   {
11159     /* VEX_W_0F3805_P_2  */
11160     { "vphsubw",        { XM, Vex, EXx }, 0 },
11161   },
11162   {
11163     /* VEX_W_0F3806_P_2  */
11164     { "vphsubd",        { XM, Vex, EXx }, 0 },
11165   },
11166   {
11167     /* VEX_W_0F3807_P_2  */
11168     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11169   },
11170   {
11171     /* VEX_W_0F3808_P_2  */
11172     { "vpsignb",        { XM, Vex, EXx }, 0 },
11173   },
11174   {
11175     /* VEX_W_0F3809_P_2  */
11176     { "vpsignw",        { XM, Vex, EXx }, 0 },
11177   },
11178   {
11179     /* VEX_W_0F380A_P_2  */
11180     { "vpsignd",        { XM, Vex, EXx }, 0 },
11181   },
11182   {
11183     /* VEX_W_0F380B_P_2  */
11184     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11185   },
11186   {
11187     /* VEX_W_0F380C_P_2  */
11188     { "vpermilps",      { XM, Vex, EXx }, 0 },
11189   },
11190   {
11191     /* VEX_W_0F380D_P_2  */
11192     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11193   },
11194   {
11195     /* VEX_W_0F380E_P_2  */
11196     { "vtestps",        { XM, EXx }, 0 },
11197   },
11198   {
11199     /* VEX_W_0F380F_P_2  */
11200     { "vtestpd",        { XM, EXx }, 0 },
11201   },
11202   {
11203     /* VEX_W_0F3816_P_2  */
11204     { "vpermps",        { XM, Vex, EXx }, 0 },
11205   },
11206   {
11207     /* VEX_W_0F3817_P_2 */
11208     { "vptest",         { XM, EXx }, 0 },
11209   },
11210   {
11211     /* VEX_W_0F3818_P_2 */
11212     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11213   },
11214   {
11215     /* VEX_W_0F3819_P_2 */
11216     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11217   },
11218   {
11219     /* VEX_W_0F381A_P_2_M_0 */
11220     { "vbroadcastf128", { XM, Mxmm }, 0 },
11221   },
11222   {
11223     /* VEX_W_0F381C_P_2 */
11224     { "vpabsb",         { XM, EXx }, 0 },
11225   },
11226   {
11227     /* VEX_W_0F381D_P_2 */
11228     { "vpabsw",         { XM, EXx }, 0 },
11229   },
11230   {
11231     /* VEX_W_0F381E_P_2 */
11232     { "vpabsd",         { XM, EXx }, 0 },
11233   },
11234   {
11235     /* VEX_W_0F3820_P_2 */
11236     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11237   },
11238   {
11239     /* VEX_W_0F3821_P_2 */
11240     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11241   },
11242   {
11243     /* VEX_W_0F3822_P_2 */
11244     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11245   },
11246   {
11247     /* VEX_W_0F3823_P_2 */
11248     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11249   },
11250   {
11251     /* VEX_W_0F3824_P_2 */
11252     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11253   },
11254   {
11255     /* VEX_W_0F3825_P_2 */
11256     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11257   },
11258   {
11259     /* VEX_W_0F3828_P_2 */
11260     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11261   },
11262   {
11263     /* VEX_W_0F3829_P_2 */
11264     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11265   },
11266   {
11267     /* VEX_W_0F382A_P_2_M_0 */
11268     { "vmovntdqa",      { XM, Mx }, 0 },
11269   },
11270   {
11271     /* VEX_W_0F382B_P_2 */
11272     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11273   },
11274   {
11275     /* VEX_W_0F382C_P_2_M_0 */
11276     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11277   },
11278   {
11279     /* VEX_W_0F382D_P_2_M_0 */
11280     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11281   },
11282   {
11283     /* VEX_W_0F382E_P_2_M_0 */
11284     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11285   },
11286   {
11287     /* VEX_W_0F382F_P_2_M_0 */
11288     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11289   },
11290   {
11291     /* VEX_W_0F3830_P_2 */
11292     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11293   },
11294   {
11295     /* VEX_W_0F3831_P_2 */
11296     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11297   },
11298   {
11299     /* VEX_W_0F3832_P_2 */
11300     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11301   },
11302   {
11303     /* VEX_W_0F3833_P_2 */
11304     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11305   },
11306   {
11307     /* VEX_W_0F3834_P_2 */
11308     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11309   },
11310   {
11311     /* VEX_W_0F3835_P_2 */
11312     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11313   },
11314   {
11315     /* VEX_W_0F3836_P_2  */
11316     { "vpermd",         { XM, Vex, EXx }, 0 },
11317   },
11318   {
11319     /* VEX_W_0F3837_P_2 */
11320     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11321   },
11322   {
11323     /* VEX_W_0F3838_P_2 */
11324     { "vpminsb",        { XM, Vex, EXx }, 0 },
11325   },
11326   {
11327     /* VEX_W_0F3839_P_2 */
11328     { "vpminsd",        { XM, Vex, EXx }, 0 },
11329   },
11330   {
11331     /* VEX_W_0F383A_P_2 */
11332     { "vpminuw",        { XM, Vex, EXx }, 0 },
11333   },
11334   {
11335     /* VEX_W_0F383B_P_2 */
11336     { "vpminud",        { XM, Vex, EXx }, 0 },
11337   },
11338   {
11339     /* VEX_W_0F383C_P_2 */
11340     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11341   },
11342   {
11343     /* VEX_W_0F383D_P_2 */
11344     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11345   },
11346   {
11347     /* VEX_W_0F383E_P_2 */
11348     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11349   },
11350   {
11351     /* VEX_W_0F383F_P_2 */
11352     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11353   },
11354   {
11355     /* VEX_W_0F3840_P_2 */
11356     { "vpmulld",        { XM, Vex, EXx }, 0 },
11357   },
11358   {
11359     /* VEX_W_0F3841_P_2 */
11360     { "vphminposuw",    { XM, EXx }, 0 },
11361   },
11362   {
11363     /* VEX_W_0F3846_P_2 */
11364     { "vpsravd",        { XM, Vex, EXx }, 0 },
11365   },
11366   {
11367     /* VEX_W_0F3858_P_2 */
11368     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11369   },
11370   {
11371     /* VEX_W_0F3859_P_2 */
11372     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11373   },
11374   {
11375     /* VEX_W_0F385A_P_2_M_0 */
11376     { "vbroadcasti128", { XM, Mxmm }, 0 },
11377   },
11378   {
11379     /* VEX_W_0F3878_P_2 */
11380     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11381   },
11382   {
11383     /* VEX_W_0F3879_P_2 */
11384     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11385   },
11386   {
11387     /* VEX_W_0F38DB_P_2 */
11388     { "vaesimc",        { XM, EXx }, 0 },
11389   },
11390   {
11391     /* VEX_W_0F38DC_P_2 */
11392     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11393   },
11394   {
11395     /* VEX_W_0F38DD_P_2 */
11396     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11397   },
11398   {
11399     /* VEX_W_0F38DE_P_2 */
11400     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11401   },
11402   {
11403     /* VEX_W_0F38DF_P_2 */
11404     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11405   },
11406   {
11407     /* VEX_W_0F3A00_P_2 */
11408     { Bad_Opcode },
11409     { "vpermq",         { XM, EXx, Ib }, 0 },
11410   },
11411   {
11412     /* VEX_W_0F3A01_P_2 */
11413     { Bad_Opcode },
11414     { "vpermpd",        { XM, EXx, Ib }, 0 },
11415   },
11416   {
11417     /* VEX_W_0F3A02_P_2 */
11418     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11419   },
11420   {
11421     /* VEX_W_0F3A04_P_2 */
11422     { "vpermilps",      { XM, EXx, Ib }, 0 },
11423   },
11424   {
11425     /* VEX_W_0F3A05_P_2 */
11426     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11427   },
11428   {
11429     /* VEX_W_0F3A06_P_2 */
11430     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11431   },
11432   {
11433     /* VEX_W_0F3A08_P_2 */
11434     { "vroundps",       { XM, EXx, Ib }, 0 },
11435   },
11436   {
11437     /* VEX_W_0F3A09_P_2 */
11438     { "vroundpd",       { XM, EXx, Ib }, 0 },
11439   },
11440   {
11441     /* VEX_W_0F3A0A_P_2 */
11442     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11443   },
11444   {
11445     /* VEX_W_0F3A0B_P_2 */
11446     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11447   },
11448   {
11449     /* VEX_W_0F3A0C_P_2 */
11450     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11451   },
11452   {
11453     /* VEX_W_0F3A0D_P_2 */
11454     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11455   },
11456   {
11457     /* VEX_W_0F3A0E_P_2 */
11458     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11459   },
11460   {
11461     /* VEX_W_0F3A0F_P_2 */
11462     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11463   },
11464   {
11465     /* VEX_W_0F3A14_P_2 */
11466     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11467   },
11468   {
11469     /* VEX_W_0F3A15_P_2 */
11470     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11471   },
11472   {
11473     /* VEX_W_0F3A18_P_2 */
11474     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11475   },
11476   {
11477     /* VEX_W_0F3A19_P_2 */
11478     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11479   },
11480   {
11481     /* VEX_W_0F3A20_P_2 */
11482     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11483   },
11484   {
11485     /* VEX_W_0F3A21_P_2 */
11486     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11487   },
11488   {
11489     /* VEX_W_0F3A30_P_2_LEN_0 */
11490     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11491     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11492   },
11493   {
11494     /* VEX_W_0F3A31_P_2_LEN_0 */
11495     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11496     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11497   },
11498   {
11499     /* VEX_W_0F3A32_P_2_LEN_0 */
11500     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11501     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11502   },
11503   {
11504     /* VEX_W_0F3A33_P_2_LEN_0 */
11505     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11506     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11507   },
11508   {
11509     /* VEX_W_0F3A38_P_2 */
11510     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11511   },
11512   {
11513     /* VEX_W_0F3A39_P_2 */
11514     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11515   },
11516   {
11517     /* VEX_W_0F3A40_P_2 */
11518     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11519   },
11520   {
11521     /* VEX_W_0F3A41_P_2 */
11522     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11523   },
11524   {
11525     /* VEX_W_0F3A42_P_2 */
11526     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11527   },
11528   {
11529     /* VEX_W_0F3A44_P_2 */
11530     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11531   },
11532   {
11533     /* VEX_W_0F3A46_P_2 */
11534     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11535   },
11536   {
11537     /* VEX_W_0F3A48_P_2 */
11538     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11539     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11540   },
11541   {
11542     /* VEX_W_0F3A49_P_2 */
11543     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11544     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11545   },
11546   {
11547     /* VEX_W_0F3A4A_P_2 */
11548     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11549   },
11550   {
11551     /* VEX_W_0F3A4B_P_2 */
11552     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11553   },
11554   {
11555     /* VEX_W_0F3A4C_P_2 */
11556     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11557   },
11558   {
11559     /* VEX_W_0F3A60_P_2 */
11560     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11561   },
11562   {
11563     /* VEX_W_0F3A61_P_2 */
11564     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11565   },
11566   {
11567     /* VEX_W_0F3A62_P_2 */
11568     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11569   },
11570   {
11571     /* VEX_W_0F3A63_P_2 */
11572     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11573   },
11574   {
11575     /* VEX_W_0F3ADF_P_2 */
11576     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11577   },
11578 #define NEED_VEX_W_TABLE
11579 #include "i386-dis-evex.h"
11580 #undef NEED_VEX_W_TABLE
11581 };
11582
11583 static const struct dis386 mod_table[][2] = {
11584   {
11585     /* MOD_8D */
11586     { "leaS",           { Gv, M }, 0 },
11587   },
11588   {
11589     /* MOD_C6_REG_7 */
11590     { Bad_Opcode },
11591     { RM_TABLE (RM_C6_REG_7) },
11592   },
11593   {
11594     /* MOD_C7_REG_7 */
11595     { Bad_Opcode },
11596     { RM_TABLE (RM_C7_REG_7) },
11597   },
11598   {
11599     /* MOD_FF_REG_3 */
11600     { "Jcall^", { indirEp }, 0 },
11601   },
11602   {
11603     /* MOD_FF_REG_5 */
11604     { "Jjmp^", { indirEp }, 0 },
11605   },
11606   {
11607     /* MOD_0F01_REG_0 */
11608     { X86_64_TABLE (X86_64_0F01_REG_0) },
11609     { RM_TABLE (RM_0F01_REG_0) },
11610   },
11611   {
11612     /* MOD_0F01_REG_1 */
11613     { X86_64_TABLE (X86_64_0F01_REG_1) },
11614     { RM_TABLE (RM_0F01_REG_1) },
11615   },
11616   {
11617     /* MOD_0F01_REG_2 */
11618     { X86_64_TABLE (X86_64_0F01_REG_2) },
11619     { RM_TABLE (RM_0F01_REG_2) },
11620   },
11621   {
11622     /* MOD_0F01_REG_3 */
11623     { X86_64_TABLE (X86_64_0F01_REG_3) },
11624     { RM_TABLE (RM_0F01_REG_3) },
11625   },
11626   {
11627     /* MOD_0F01_REG_7 */
11628     { "invlpg",         { Mb }, 0 },
11629     { RM_TABLE (RM_0F01_REG_7) },
11630   },
11631   {
11632     /* MOD_0F12_PREFIX_0 */
11633     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11634     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11635   },
11636   {
11637     /* MOD_0F13 */
11638     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11639   },
11640   {
11641     /* MOD_0F16_PREFIX_0 */
11642     { "movhps",         { XM, EXq }, 0 },
11643     { "movlhps",        { XM, EXq }, 0 },
11644   },
11645   {
11646     /* MOD_0F17 */
11647     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11648   },
11649   {
11650     /* MOD_0F18_REG_0 */
11651     { "prefetchnta",    { Mb }, 0 },
11652   },
11653   {
11654     /* MOD_0F18_REG_1 */
11655     { "prefetcht0",     { Mb }, 0 },
11656   },
11657   {
11658     /* MOD_0F18_REG_2 */
11659     { "prefetcht1",     { Mb }, 0 },
11660   },
11661   {
11662     /* MOD_0F18_REG_3 */
11663     { "prefetcht2",     { Mb }, 0 },
11664   },
11665   {
11666     /* MOD_0F18_REG_4 */
11667     { "nop/reserved",   { Mb }, 0 },
11668   },
11669   {
11670     /* MOD_0F18_REG_5 */
11671     { "nop/reserved",   { Mb }, 0 },
11672   },
11673   {
11674     /* MOD_0F18_REG_6 */
11675     { "nop/reserved",   { Mb }, 0 },
11676   },
11677   {
11678     /* MOD_0F18_REG_7 */
11679     { "nop/reserved",   { Mb }, 0 },
11680   },
11681   {
11682     /* MOD_0F1A_PREFIX_0 */
11683     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11684     { "nopQ",           { Ev }, 0 },
11685   },
11686   {
11687     /* MOD_0F1B_PREFIX_0 */
11688     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11689     { "nopQ",           { Ev }, 0 },
11690   },
11691   {
11692     /* MOD_0F1B_PREFIX_1 */
11693     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11694     { "nopQ",           { Ev }, 0 },
11695   },
11696   {
11697     /* MOD_0F24 */
11698     { Bad_Opcode },
11699     { "movL",           { Rd, Td }, 0 },
11700   },
11701   {
11702     /* MOD_0F26 */
11703     { Bad_Opcode },
11704     { "movL",           { Td, Rd }, 0 },
11705   },
11706   {
11707     /* MOD_0F2B_PREFIX_0 */
11708     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11709   },
11710   {
11711     /* MOD_0F2B_PREFIX_1 */
11712     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11713   },
11714   {
11715     /* MOD_0F2B_PREFIX_2 */
11716     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11717   },
11718   {
11719     /* MOD_0F2B_PREFIX_3 */
11720     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11721   },
11722   {
11723     /* MOD_0F51 */
11724     { Bad_Opcode },
11725     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11726   },
11727   {
11728     /* MOD_0F71_REG_2 */
11729     { Bad_Opcode },
11730     { "psrlw",          { MS, Ib }, 0 },
11731   },
11732   {
11733     /* MOD_0F71_REG_4 */
11734     { Bad_Opcode },
11735     { "psraw",          { MS, Ib }, 0 },
11736   },
11737   {
11738     /* MOD_0F71_REG_6 */
11739     { Bad_Opcode },
11740     { "psllw",          { MS, Ib }, 0 },
11741   },
11742   {
11743     /* MOD_0F72_REG_2 */
11744     { Bad_Opcode },
11745     { "psrld",          { MS, Ib }, 0 },
11746   },
11747   {
11748     /* MOD_0F72_REG_4 */
11749     { Bad_Opcode },
11750     { "psrad",          { MS, Ib }, 0 },
11751   },
11752   {
11753     /* MOD_0F72_REG_6 */
11754     { Bad_Opcode },
11755     { "pslld",          { MS, Ib }, 0 },
11756   },
11757   {
11758     /* MOD_0F73_REG_2 */
11759     { Bad_Opcode },
11760     { "psrlq",          { MS, Ib }, 0 },
11761   },
11762   {
11763     /* MOD_0F73_REG_3 */
11764     { Bad_Opcode },
11765     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11766   },
11767   {
11768     /* MOD_0F73_REG_6 */
11769     { Bad_Opcode },
11770     { "psllq",          { MS, Ib }, 0 },
11771   },
11772   {
11773     /* MOD_0F73_REG_7 */
11774     { Bad_Opcode },
11775     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11776   },
11777   {
11778     /* MOD_0FAE_REG_0 */
11779     { "fxsave",         { FXSAVE }, 0 },
11780     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11781   },
11782   {
11783     /* MOD_0FAE_REG_1 */
11784     { "fxrstor",        { FXSAVE }, 0 },
11785     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11786   },
11787   {
11788     /* MOD_0FAE_REG_2 */
11789     { "ldmxcsr",        { Md }, 0 },
11790     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11791   },
11792   {
11793     /* MOD_0FAE_REG_3 */
11794     { "stmxcsr",        { Md }, 0 },
11795     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11796   },
11797   {
11798     /* MOD_0FAE_REG_4 */
11799     { "xsave",          { FXSAVE }, 0 },
11800   },
11801   {
11802     /* MOD_0FAE_REG_5 */
11803     { "xrstor",         { FXSAVE }, 0 },
11804     { RM_TABLE (RM_0FAE_REG_5) },
11805   },
11806   {
11807     /* MOD_0FAE_REG_6 */
11808     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11809     { RM_TABLE (RM_0FAE_REG_6) },
11810   },
11811   {
11812     /* MOD_0FAE_REG_7 */
11813     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11814     { RM_TABLE (RM_0FAE_REG_7) },
11815   },
11816   {
11817     /* MOD_0FB2 */
11818     { "lssS",           { Gv, Mp }, 0 },
11819   },
11820   {
11821     /* MOD_0FB4 */
11822     { "lfsS",           { Gv, Mp }, 0 },
11823   },
11824   {
11825     /* MOD_0FB5 */
11826     { "lgsS",           { Gv, Mp }, 0 },
11827   },
11828   {
11829     /* MOD_0FC7_REG_3 */
11830     { "xrstors",                { FXSAVE }, 0 },
11831   },
11832   {
11833     /* MOD_0FC7_REG_4 */
11834     { "xsavec",         { FXSAVE }, 0 },
11835   },
11836   {
11837     /* MOD_0FC7_REG_5 */
11838     { "xsaves",         { FXSAVE }, 0 },
11839   },
11840   {
11841     /* MOD_0FC7_REG_6 */
11842     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11843     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11844   },
11845   {
11846     /* MOD_0FC7_REG_7 */
11847     { "vmptrst",        { Mq }, 0 },
11848     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11849   },
11850   {
11851     /* MOD_0FD7 */
11852     { Bad_Opcode },
11853     { "pmovmskb",       { Gdq, MS }, 0 },
11854   },
11855   {
11856     /* MOD_0FE7_PREFIX_2 */
11857     { "movntdq",        { Mx, XM }, 0 },
11858   },
11859   {
11860     /* MOD_0FF0_PREFIX_3 */
11861     { "lddqu",          { XM, M }, 0 },
11862   },
11863   {
11864     /* MOD_0F382A_PREFIX_2 */
11865     { "movntdqa",       { XM, Mx }, 0 },
11866   },
11867   {
11868     /* MOD_62_32BIT */
11869     { "bound{S|}",      { Gv, Ma }, 0 },
11870     { EVEX_TABLE (EVEX_0F) },
11871   },
11872   {
11873     /* MOD_C4_32BIT */
11874     { "lesS",           { Gv, Mp }, 0 },
11875     { VEX_C4_TABLE (VEX_0F) },
11876   },
11877   {
11878     /* MOD_C5_32BIT */
11879     { "ldsS",           { Gv, Mp }, 0 },
11880     { VEX_C5_TABLE (VEX_0F) },
11881   },
11882   {
11883     /* MOD_VEX_0F12_PREFIX_0 */
11884     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11885     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11886   },
11887   {
11888     /* MOD_VEX_0F13 */
11889     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11890   },
11891   {
11892     /* MOD_VEX_0F16_PREFIX_0 */
11893     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11894     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11895   },
11896   {
11897     /* MOD_VEX_0F17 */
11898     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11899   },
11900   {
11901     /* MOD_VEX_0F2B */
11902     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11903   },
11904   {
11905     /* MOD_VEX_0F50 */
11906     { Bad_Opcode },
11907     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11908   },
11909   {
11910     /* MOD_VEX_0F71_REG_2 */
11911     { Bad_Opcode },
11912     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11913   },
11914   {
11915     /* MOD_VEX_0F71_REG_4 */
11916     { Bad_Opcode },
11917     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11918   },
11919   {
11920     /* MOD_VEX_0F71_REG_6 */
11921     { Bad_Opcode },
11922     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11923   },
11924   {
11925     /* MOD_VEX_0F72_REG_2 */
11926     { Bad_Opcode },
11927     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11928   },
11929   {
11930     /* MOD_VEX_0F72_REG_4 */
11931     { Bad_Opcode },
11932     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11933   },
11934   {
11935     /* MOD_VEX_0F72_REG_6 */
11936     { Bad_Opcode },
11937     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11938   },
11939   {
11940     /* MOD_VEX_0F73_REG_2 */
11941     { Bad_Opcode },
11942     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11943   },
11944   {
11945     /* MOD_VEX_0F73_REG_3 */
11946     { Bad_Opcode },
11947     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11948   },
11949   {
11950     /* MOD_VEX_0F73_REG_6 */
11951     { Bad_Opcode },
11952     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11953   },
11954   {
11955     /* MOD_VEX_0F73_REG_7 */
11956     { Bad_Opcode },
11957     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11958   },
11959   {
11960     /* MOD_VEX_0FAE_REG_2 */
11961     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11962   },
11963   {
11964     /* MOD_VEX_0FAE_REG_3 */
11965     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11966   },
11967   {
11968     /* MOD_VEX_0FD7_PREFIX_2 */
11969     { Bad_Opcode },
11970     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11971   },
11972   {
11973     /* MOD_VEX_0FE7_PREFIX_2 */
11974     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11975   },
11976   {
11977     /* MOD_VEX_0FF0_PREFIX_3 */
11978     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11979   },
11980   {
11981     /* MOD_VEX_0F381A_PREFIX_2 */
11982     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11983   },
11984   {
11985     /* MOD_VEX_0F382A_PREFIX_2 */
11986     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11987   },
11988   {
11989     /* MOD_VEX_0F382C_PREFIX_2 */
11990     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11991   },
11992   {
11993     /* MOD_VEX_0F382D_PREFIX_2 */
11994     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11995   },
11996   {
11997     /* MOD_VEX_0F382E_PREFIX_2 */
11998     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11999   },
12000   {
12001     /* MOD_VEX_0F382F_PREFIX_2 */
12002     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12003   },
12004   {
12005     /* MOD_VEX_0F385A_PREFIX_2 */
12006     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12007   },
12008   {
12009     /* MOD_VEX_0F388C_PREFIX_2 */
12010     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12011   },
12012   {
12013     /* MOD_VEX_0F388E_PREFIX_2 */
12014     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12015   },
12016 #define NEED_MOD_TABLE
12017 #include "i386-dis-evex.h"
12018 #undef NEED_MOD_TABLE
12019 };
12020
12021 static const struct dis386 rm_table[][8] = {
12022   {
12023     /* RM_C6_REG_7 */
12024     { "xabort",         { Skip_MODRM, Ib }, 0 },
12025   },
12026   {
12027     /* RM_C7_REG_7 */
12028     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12029   },
12030   {
12031     /* RM_0F01_REG_0 */
12032     { Bad_Opcode },
12033     { "vmcall",         { Skip_MODRM }, 0 },
12034     { "vmlaunch",       { Skip_MODRM }, 0 },
12035     { "vmresume",       { Skip_MODRM }, 0 },
12036     { "vmxoff",         { Skip_MODRM }, 0 },
12037   },
12038   {
12039     /* RM_0F01_REG_1 */
12040     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12041     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12042     { "clac",           { Skip_MODRM }, 0 },
12043     { "stac",           { Skip_MODRM }, 0 },
12044     { Bad_Opcode },
12045     { Bad_Opcode },
12046     { Bad_Opcode },
12047     { "encls",          { Skip_MODRM }, 0 },
12048   },
12049   {
12050     /* RM_0F01_REG_2 */
12051     { "xgetbv",         { Skip_MODRM }, 0 },
12052     { "xsetbv",         { Skip_MODRM }, 0 },
12053     { Bad_Opcode },
12054     { Bad_Opcode },
12055     { "vmfunc",         { Skip_MODRM }, 0 },
12056     { "xend",           { Skip_MODRM }, 0 },
12057     { "xtest",          { Skip_MODRM }, 0 },
12058     { "enclu",          { Skip_MODRM }, 0 },
12059   },
12060   {
12061     /* RM_0F01_REG_3 */
12062     { "vmrun",          { Skip_MODRM }, 0 },
12063     { "vmmcall",        { Skip_MODRM }, 0 },
12064     { "vmload",         { Skip_MODRM }, 0 },
12065     { "vmsave",         { Skip_MODRM }, 0 },
12066     { "stgi",           { Skip_MODRM }, 0 },
12067     { "clgi",           { Skip_MODRM }, 0 },
12068     { "skinit",         { Skip_MODRM }, 0 },
12069     { "invlpga",        { Skip_MODRM }, 0 },
12070   },
12071   {
12072     /* RM_0F01_REG_7 */
12073     { "swapgs",         { Skip_MODRM }, 0  },
12074     { "rdtscp",         { Skip_MODRM }, 0  },
12075     { Bad_Opcode },
12076     { Bad_Opcode },
12077     { "clzero",         { Skip_MODRM }, 0  },
12078   },
12079   {
12080     /* RM_0FAE_REG_5 */
12081     { "lfence",         { Skip_MODRM }, 0 },
12082   },
12083   {
12084     /* RM_0FAE_REG_6 */
12085     { "mfence",         { Skip_MODRM }, 0 },
12086   },
12087   {
12088     /* RM_0FAE_REG_7 */
12089     { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12090   },
12091 };
12092
12093 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12094
12095 /* We use the high bit to indicate different name for the same
12096    prefix.  */
12097 #define REP_PREFIX      (0xf3 | 0x100)
12098 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12099 #define XRELEASE_PREFIX (0xf3 | 0x400)
12100 #define BND_PREFIX      (0xf2 | 0x400)
12101
12102 static int
12103 ckprefix (void)
12104 {
12105   int newrex, i, length;
12106   rex = 0;
12107   rex_ignored = 0;
12108   prefixes = 0;
12109   used_prefixes = 0;
12110   rex_used = 0;
12111   last_lock_prefix = -1;
12112   last_repz_prefix = -1;
12113   last_repnz_prefix = -1;
12114   last_data_prefix = -1;
12115   last_addr_prefix = -1;
12116   last_rex_prefix = -1;
12117   last_seg_prefix = -1;
12118   fwait_prefix = -1;
12119   active_seg_prefix = 0;
12120   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12121     all_prefixes[i] = 0;
12122   i = 0;
12123   length = 0;
12124   /* The maximum instruction length is 15bytes.  */
12125   while (length < MAX_CODE_LENGTH - 1)
12126     {
12127       FETCH_DATA (the_info, codep + 1);
12128       newrex = 0;
12129       switch (*codep)
12130         {
12131         /* REX prefixes family.  */
12132         case 0x40:
12133         case 0x41:
12134         case 0x42:
12135         case 0x43:
12136         case 0x44:
12137         case 0x45:
12138         case 0x46:
12139         case 0x47:
12140         case 0x48:
12141         case 0x49:
12142         case 0x4a:
12143         case 0x4b:
12144         case 0x4c:
12145         case 0x4d:
12146         case 0x4e:
12147         case 0x4f:
12148           if (address_mode == mode_64bit)
12149             newrex = *codep;
12150           else
12151             return 1;
12152           last_rex_prefix = i;
12153           break;
12154         case 0xf3:
12155           prefixes |= PREFIX_REPZ;
12156           last_repz_prefix = i;
12157           break;
12158         case 0xf2:
12159           prefixes |= PREFIX_REPNZ;
12160           last_repnz_prefix = i;
12161           break;
12162         case 0xf0:
12163           prefixes |= PREFIX_LOCK;
12164           last_lock_prefix = i;
12165           break;
12166         case 0x2e:
12167           prefixes |= PREFIX_CS;
12168           last_seg_prefix = i;
12169           active_seg_prefix = PREFIX_CS;
12170           break;
12171         case 0x36:
12172           prefixes |= PREFIX_SS;
12173           last_seg_prefix = i;
12174           active_seg_prefix = PREFIX_SS;
12175           break;
12176         case 0x3e:
12177           prefixes |= PREFIX_DS;
12178           last_seg_prefix = i;
12179           active_seg_prefix = PREFIX_DS;
12180           break;
12181         case 0x26:
12182           prefixes |= PREFIX_ES;
12183           last_seg_prefix = i;
12184           active_seg_prefix = PREFIX_ES;
12185           break;
12186         case 0x64:
12187           prefixes |= PREFIX_FS;
12188           last_seg_prefix = i;
12189           active_seg_prefix = PREFIX_FS;
12190           break;
12191         case 0x65:
12192           prefixes |= PREFIX_GS;
12193           last_seg_prefix = i;
12194           active_seg_prefix = PREFIX_GS;
12195           break;
12196         case 0x66:
12197           prefixes |= PREFIX_DATA;
12198           last_data_prefix = i;
12199           break;
12200         case 0x67:
12201           prefixes |= PREFIX_ADDR;
12202           last_addr_prefix = i;
12203           break;
12204         case FWAIT_OPCODE:
12205           /* fwait is really an instruction.  If there are prefixes
12206              before the fwait, they belong to the fwait, *not* to the
12207              following instruction.  */
12208           fwait_prefix = i;
12209           if (prefixes || rex)
12210             {
12211               prefixes |= PREFIX_FWAIT;
12212               codep++;
12213               /* This ensures that the previous REX prefixes are noticed
12214                  as unused prefixes, as in the return case below.  */
12215               rex_used = rex;
12216               return 1;
12217             }
12218           prefixes = PREFIX_FWAIT;
12219           break;
12220         default:
12221           return 1;
12222         }
12223       /* Rex is ignored when followed by another prefix.  */
12224       if (rex)
12225         {
12226           rex_used = rex;
12227           return 1;
12228         }
12229       if (*codep != FWAIT_OPCODE)
12230         all_prefixes[i++] = *codep;
12231       rex = newrex;
12232       codep++;
12233       length++;
12234     }
12235   return 0;
12236 }
12237
12238 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12239    prefix byte.  */
12240
12241 static const char *
12242 prefix_name (int pref, int sizeflag)
12243 {
12244   static const char *rexes [16] =
12245     {
12246       "rex",            /* 0x40 */
12247       "rex.B",          /* 0x41 */
12248       "rex.X",          /* 0x42 */
12249       "rex.XB",         /* 0x43 */
12250       "rex.R",          /* 0x44 */
12251       "rex.RB",         /* 0x45 */
12252       "rex.RX",         /* 0x46 */
12253       "rex.RXB",        /* 0x47 */
12254       "rex.W",          /* 0x48 */
12255       "rex.WB",         /* 0x49 */
12256       "rex.WX",         /* 0x4a */
12257       "rex.WXB",        /* 0x4b */
12258       "rex.WR",         /* 0x4c */
12259       "rex.WRB",        /* 0x4d */
12260       "rex.WRX",        /* 0x4e */
12261       "rex.WRXB",       /* 0x4f */
12262     };
12263
12264   switch (pref)
12265     {
12266     /* REX prefixes family.  */
12267     case 0x40:
12268     case 0x41:
12269     case 0x42:
12270     case 0x43:
12271     case 0x44:
12272     case 0x45:
12273     case 0x46:
12274     case 0x47:
12275     case 0x48:
12276     case 0x49:
12277     case 0x4a:
12278     case 0x4b:
12279     case 0x4c:
12280     case 0x4d:
12281     case 0x4e:
12282     case 0x4f:
12283       return rexes [pref - 0x40];
12284     case 0xf3:
12285       return "repz";
12286     case 0xf2:
12287       return "repnz";
12288     case 0xf0:
12289       return "lock";
12290     case 0x2e:
12291       return "cs";
12292     case 0x36:
12293       return "ss";
12294     case 0x3e:
12295       return "ds";
12296     case 0x26:
12297       return "es";
12298     case 0x64:
12299       return "fs";
12300     case 0x65:
12301       return "gs";
12302     case 0x66:
12303       return (sizeflag & DFLAG) ? "data16" : "data32";
12304     case 0x67:
12305       if (address_mode == mode_64bit)
12306         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12307       else
12308         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12309     case FWAIT_OPCODE:
12310       return "fwait";
12311     case REP_PREFIX:
12312       return "rep";
12313     case XACQUIRE_PREFIX:
12314       return "xacquire";
12315     case XRELEASE_PREFIX:
12316       return "xrelease";
12317     case BND_PREFIX:
12318       return "bnd";
12319     default:
12320       return NULL;
12321     }
12322 }
12323
12324 static char op_out[MAX_OPERANDS][100];
12325 static int op_ad, op_index[MAX_OPERANDS];
12326 static int two_source_ops;
12327 static bfd_vma op_address[MAX_OPERANDS];
12328 static bfd_vma op_riprel[MAX_OPERANDS];
12329 static bfd_vma start_pc;
12330
12331 /*
12332  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12333  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12334  *   section of the "Virtual 8086 Mode" chapter.)
12335  * 'pc' should be the address of this instruction, it will
12336  *   be used to print the target address if this is a relative jump or call
12337  * The function returns the length of this instruction in bytes.
12338  */
12339
12340 static char intel_syntax;
12341 static char intel_mnemonic = !SYSV386_COMPAT;
12342 static char open_char;
12343 static char close_char;
12344 static char separator_char;
12345 static char scale_char;
12346
12347 enum x86_64_isa
12348 {
12349   amd64 = 0,
12350   intel64
12351 };
12352
12353 static enum x86_64_isa isa64;
12354
12355 /* Here for backwards compatibility.  When gdb stops using
12356    print_insn_i386_att and print_insn_i386_intel these functions can
12357    disappear, and print_insn_i386 be merged into print_insn.  */
12358 int
12359 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12360 {
12361   intel_syntax = 0;
12362
12363   return print_insn (pc, info);
12364 }
12365
12366 int
12367 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12368 {
12369   intel_syntax = 1;
12370
12371   return print_insn (pc, info);
12372 }
12373
12374 int
12375 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12376 {
12377   intel_syntax = -1;
12378
12379   return print_insn (pc, info);
12380 }
12381
12382 void
12383 print_i386_disassembler_options (FILE *stream)
12384 {
12385   fprintf (stream, _("\n\
12386 The following i386/x86-64 specific disassembler options are supported for use\n\
12387 with the -M switch (multiple options should be separated by commas):\n"));
12388
12389   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12390   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12391   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12392   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12393   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12394   fprintf (stream, _("  att-mnemonic\n"
12395                      "              Display instruction in AT&T mnemonic\n"));
12396   fprintf (stream, _("  intel-mnemonic\n"
12397                      "              Display instruction in Intel mnemonic\n"));
12398   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12399   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12400   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12401   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12402   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12403   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12404   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12405   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12406 }
12407
12408 /* Bad opcode.  */
12409 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12410
12411 /* Get a pointer to struct dis386 with a valid name.  */
12412
12413 static const struct dis386 *
12414 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12415 {
12416   int vindex, vex_table_index;
12417
12418   if (dp->name != NULL)
12419     return dp;
12420
12421   switch (dp->op[0].bytemode)
12422     {
12423     case USE_REG_TABLE:
12424       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12425       break;
12426
12427     case USE_MOD_TABLE:
12428       vindex = modrm.mod == 0x3 ? 1 : 0;
12429       dp = &mod_table[dp->op[1].bytemode][vindex];
12430       break;
12431
12432     case USE_RM_TABLE:
12433       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12434       break;
12435
12436     case USE_PREFIX_TABLE:
12437       if (need_vex)
12438         {
12439           /* The prefix in VEX is implicit.  */
12440           switch (vex.prefix)
12441             {
12442             case 0:
12443               vindex = 0;
12444               break;
12445             case REPE_PREFIX_OPCODE:
12446               vindex = 1;
12447               break;
12448             case DATA_PREFIX_OPCODE:
12449               vindex = 2;
12450               break;
12451             case REPNE_PREFIX_OPCODE:
12452               vindex = 3;
12453               break;
12454             default:
12455               abort ();
12456               break;
12457             }
12458         }
12459       else
12460         {
12461           int last_prefix = -1;
12462           int prefix = 0;
12463           vindex = 0;
12464           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12465              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12466              last one wins.  */
12467           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12468             {
12469               if (last_repz_prefix > last_repnz_prefix)
12470                 {
12471                   vindex = 1;
12472                   prefix = PREFIX_REPZ;
12473                   last_prefix = last_repz_prefix;
12474                 }
12475               else
12476                 {
12477                   vindex = 3;
12478                   prefix = PREFIX_REPNZ;
12479                   last_prefix = last_repnz_prefix;
12480                 }
12481
12482               /* Check if prefix should be ignored.  */
12483               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12484                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12485                    & prefix) != 0)
12486                 vindex = 0;
12487             }
12488
12489           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12490             {
12491               vindex = 2;
12492               prefix = PREFIX_DATA;
12493               last_prefix = last_data_prefix;
12494             }
12495
12496           if (vindex != 0)
12497             {
12498               used_prefixes |= prefix;
12499               all_prefixes[last_prefix] = 0;
12500             }
12501         }
12502       dp = &prefix_table[dp->op[1].bytemode][vindex];
12503       break;
12504
12505     case USE_X86_64_TABLE:
12506       vindex = address_mode == mode_64bit ? 1 : 0;
12507       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12508       break;
12509
12510     case USE_3BYTE_TABLE:
12511       FETCH_DATA (info, codep + 2);
12512       vindex = *codep++;
12513       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12514       end_codep = codep;
12515       modrm.mod = (*codep >> 6) & 3;
12516       modrm.reg = (*codep >> 3) & 7;
12517       modrm.rm = *codep & 7;
12518       break;
12519
12520     case USE_VEX_LEN_TABLE:
12521       if (!need_vex)
12522         abort ();
12523
12524       switch (vex.length)
12525         {
12526         case 128:
12527           vindex = 0;
12528           break;
12529         case 256:
12530           vindex = 1;
12531           break;
12532         default:
12533           abort ();
12534           break;
12535         }
12536
12537       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12538       break;
12539
12540     case USE_XOP_8F_TABLE:
12541       FETCH_DATA (info, codep + 3);
12542       /* All bits in the REX prefix are ignored.  */
12543       rex_ignored = rex;
12544       rex = ~(*codep >> 5) & 0x7;
12545
12546       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12547       switch ((*codep & 0x1f))
12548         {
12549         default:
12550           dp = &bad_opcode;
12551           return dp;
12552         case 0x8:
12553           vex_table_index = XOP_08;
12554           break;
12555         case 0x9:
12556           vex_table_index = XOP_09;
12557           break;
12558         case 0xa:
12559           vex_table_index = XOP_0A;
12560           break;
12561         }
12562       codep++;
12563       vex.w = *codep & 0x80;
12564       if (vex.w && address_mode == mode_64bit)
12565         rex |= REX_W;
12566
12567       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12568       if (address_mode != mode_64bit
12569           && vex.register_specifier > 0x7)
12570         {
12571           dp = &bad_opcode;
12572           return dp;
12573         }
12574
12575       vex.length = (*codep & 0x4) ? 256 : 128;
12576       switch ((*codep & 0x3))
12577         {
12578         case 0:
12579           vex.prefix = 0;
12580           break;
12581         case 1:
12582           vex.prefix = DATA_PREFIX_OPCODE;
12583           break;
12584         case 2:
12585           vex.prefix = REPE_PREFIX_OPCODE;
12586           break;
12587         case 3:
12588           vex.prefix = REPNE_PREFIX_OPCODE;
12589           break;
12590         }
12591       need_vex = 1;
12592       need_vex_reg = 1;
12593       codep++;
12594       vindex = *codep++;
12595       dp = &xop_table[vex_table_index][vindex];
12596
12597       end_codep = codep;
12598       FETCH_DATA (info, codep + 1);
12599       modrm.mod = (*codep >> 6) & 3;
12600       modrm.reg = (*codep >> 3) & 7;
12601       modrm.rm = *codep & 7;
12602       break;
12603
12604     case USE_VEX_C4_TABLE:
12605       /* VEX prefix.  */
12606       FETCH_DATA (info, codep + 3);
12607       /* All bits in the REX prefix are ignored.  */
12608       rex_ignored = rex;
12609       rex = ~(*codep >> 5) & 0x7;
12610       switch ((*codep & 0x1f))
12611         {
12612         default:
12613           dp = &bad_opcode;
12614           return dp;
12615         case 0x1:
12616           vex_table_index = VEX_0F;
12617           break;
12618         case 0x2:
12619           vex_table_index = VEX_0F38;
12620           break;
12621         case 0x3:
12622           vex_table_index = VEX_0F3A;
12623           break;
12624         }
12625       codep++;
12626       vex.w = *codep & 0x80;
12627       if (vex.w && address_mode == mode_64bit)
12628         rex |= REX_W;
12629
12630       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12631       if (address_mode != mode_64bit
12632           && vex.register_specifier > 0x7)
12633         {
12634           dp = &bad_opcode;
12635           return dp;
12636         }
12637
12638       vex.length = (*codep & 0x4) ? 256 : 128;
12639       switch ((*codep & 0x3))
12640         {
12641         case 0:
12642           vex.prefix = 0;
12643           break;
12644         case 1:
12645           vex.prefix = DATA_PREFIX_OPCODE;
12646           break;
12647         case 2:
12648           vex.prefix = REPE_PREFIX_OPCODE;
12649           break;
12650         case 3:
12651           vex.prefix = REPNE_PREFIX_OPCODE;
12652           break;
12653         }
12654       need_vex = 1;
12655       need_vex_reg = 1;
12656       codep++;
12657       vindex = *codep++;
12658       dp = &vex_table[vex_table_index][vindex];
12659       end_codep = codep;
12660       /* There is no MODRM byte for VEX [82|77].  */
12661       if (vindex != 0x77 && vindex != 0x82)
12662         {
12663           FETCH_DATA (info, codep + 1);
12664           modrm.mod = (*codep >> 6) & 3;
12665           modrm.reg = (*codep >> 3) & 7;
12666           modrm.rm = *codep & 7;
12667         }
12668       break;
12669
12670     case USE_VEX_C5_TABLE:
12671       /* VEX prefix.  */
12672       FETCH_DATA (info, codep + 2);
12673       /* All bits in the REX prefix are ignored.  */
12674       rex_ignored = rex;
12675       rex = (*codep & 0x80) ? 0 : REX_R;
12676
12677       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12678       if (address_mode != mode_64bit
12679           && vex.register_specifier > 0x7)
12680         {
12681           dp = &bad_opcode;
12682           return dp;
12683         }
12684
12685       vex.w = 0;
12686
12687       vex.length = (*codep & 0x4) ? 256 : 128;
12688       switch ((*codep & 0x3))
12689         {
12690         case 0:
12691           vex.prefix = 0;
12692           break;
12693         case 1:
12694           vex.prefix = DATA_PREFIX_OPCODE;
12695           break;
12696         case 2:
12697           vex.prefix = REPE_PREFIX_OPCODE;
12698           break;
12699         case 3:
12700           vex.prefix = REPNE_PREFIX_OPCODE;
12701           break;
12702         }
12703       need_vex = 1;
12704       need_vex_reg = 1;
12705       codep++;
12706       vindex = *codep++;
12707       dp = &vex_table[dp->op[1].bytemode][vindex];
12708       end_codep = codep;
12709       /* There is no MODRM byte for VEX [82|77].  */
12710       if (vindex != 0x77 && vindex != 0x82)
12711         {
12712           FETCH_DATA (info, codep + 1);
12713           modrm.mod = (*codep >> 6) & 3;
12714           modrm.reg = (*codep >> 3) & 7;
12715           modrm.rm = *codep & 7;
12716         }
12717       break;
12718
12719     case USE_VEX_W_TABLE:
12720       if (!need_vex)
12721         abort ();
12722
12723       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12724       break;
12725
12726     case USE_EVEX_TABLE:
12727       two_source_ops = 0;
12728       /* EVEX prefix.  */
12729       vex.evex = 1;
12730       FETCH_DATA (info, codep + 4);
12731       /* All bits in the REX prefix are ignored.  */
12732       rex_ignored = rex;
12733       /* The first byte after 0x62.  */
12734       rex = ~(*codep >> 5) & 0x7;
12735       vex.r = *codep & 0x10;
12736       switch ((*codep & 0xf))
12737         {
12738         default:
12739           return &bad_opcode;
12740         case 0x1:
12741           vex_table_index = EVEX_0F;
12742           break;
12743         case 0x2:
12744           vex_table_index = EVEX_0F38;
12745           break;
12746         case 0x3:
12747           vex_table_index = EVEX_0F3A;
12748           break;
12749         }
12750
12751       /* The second byte after 0x62.  */
12752       codep++;
12753       vex.w = *codep & 0x80;
12754       if (vex.w && address_mode == mode_64bit)
12755         rex |= REX_W;
12756
12757       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12758       if (address_mode != mode_64bit)
12759         {
12760           /* In 16/32-bit mode silently ignore following bits.  */
12761           rex &= ~REX_B;
12762           vex.r = 1;
12763           vex.v = 1;
12764           vex.register_specifier &= 0x7;
12765         }
12766
12767       /* The U bit.  */
12768       if (!(*codep & 0x4))
12769         return &bad_opcode;
12770
12771       switch ((*codep & 0x3))
12772         {
12773         case 0:
12774           vex.prefix = 0;
12775           break;
12776         case 1:
12777           vex.prefix = DATA_PREFIX_OPCODE;
12778           break;
12779         case 2:
12780           vex.prefix = REPE_PREFIX_OPCODE;
12781           break;
12782         case 3:
12783           vex.prefix = REPNE_PREFIX_OPCODE;
12784           break;
12785         }
12786
12787       /* The third byte after 0x62.  */
12788       codep++;
12789
12790       /* Remember the static rounding bits.  */
12791       vex.ll = (*codep >> 5) & 3;
12792       vex.b = (*codep & 0x10) != 0;
12793
12794       vex.v = *codep & 0x8;
12795       vex.mask_register_specifier = *codep & 0x7;
12796       vex.zeroing = *codep & 0x80;
12797
12798       need_vex = 1;
12799       need_vex_reg = 1;
12800       codep++;
12801       vindex = *codep++;
12802       dp = &evex_table[vex_table_index][vindex];
12803       end_codep = codep;
12804       FETCH_DATA (info, codep + 1);
12805       modrm.mod = (*codep >> 6) & 3;
12806       modrm.reg = (*codep >> 3) & 7;
12807       modrm.rm = *codep & 7;
12808
12809       /* Set vector length.  */
12810       if (modrm.mod == 3 && vex.b)
12811         vex.length = 512;
12812       else
12813         {
12814           switch (vex.ll)
12815             {
12816             case 0x0:
12817               vex.length = 128;
12818               break;
12819             case 0x1:
12820               vex.length = 256;
12821               break;
12822             case 0x2:
12823               vex.length = 512;
12824               break;
12825             default:
12826               return &bad_opcode;
12827             }
12828         }
12829       break;
12830
12831     case 0:
12832       dp = &bad_opcode;
12833       break;
12834
12835     default:
12836       abort ();
12837     }
12838
12839   if (dp->name != NULL)
12840     return dp;
12841   else
12842     return get_valid_dis386 (dp, info);
12843 }
12844
12845 static void
12846 get_sib (disassemble_info *info, int sizeflag)
12847 {
12848   /* If modrm.mod == 3, operand must be register.  */
12849   if (need_modrm
12850       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12851       && modrm.mod != 3
12852       && modrm.rm == 4)
12853     {
12854       FETCH_DATA (info, codep + 2);
12855       sib.index = (codep [1] >> 3) & 7;
12856       sib.scale = (codep [1] >> 6) & 3;
12857       sib.base = codep [1] & 7;
12858     }
12859 }
12860
12861 static int
12862 print_insn (bfd_vma pc, disassemble_info *info)
12863 {
12864   const struct dis386 *dp;
12865   int i;
12866   char *op_txt[MAX_OPERANDS];
12867   int needcomma;
12868   int sizeflag, orig_sizeflag;
12869   const char *p;
12870   struct dis_private priv;
12871   int prefix_length;
12872
12873   priv.orig_sizeflag = AFLAG | DFLAG;
12874   if ((info->mach & bfd_mach_i386_i386) != 0)
12875     address_mode = mode_32bit;
12876   else if (info->mach == bfd_mach_i386_i8086)
12877     {
12878       address_mode = mode_16bit;
12879       priv.orig_sizeflag = 0;
12880     }
12881   else
12882     address_mode = mode_64bit;
12883
12884   if (intel_syntax == (char) -1)
12885     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12886
12887   for (p = info->disassembler_options; p != NULL; )
12888     {
12889       if (CONST_STRNEQ (p, "amd64"))
12890         isa64 = amd64;
12891       else if (CONST_STRNEQ (p, "intel64"))
12892         isa64 = intel64;
12893       else if (CONST_STRNEQ (p, "x86-64"))
12894         {
12895           address_mode = mode_64bit;
12896           priv.orig_sizeflag = AFLAG | DFLAG;
12897         }
12898       else if (CONST_STRNEQ (p, "i386"))
12899         {
12900           address_mode = mode_32bit;
12901           priv.orig_sizeflag = AFLAG | DFLAG;
12902         }
12903       else if (CONST_STRNEQ (p, "i8086"))
12904         {
12905           address_mode = mode_16bit;
12906           priv.orig_sizeflag = 0;
12907         }
12908       else if (CONST_STRNEQ (p, "intel"))
12909         {
12910           intel_syntax = 1;
12911           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12912             intel_mnemonic = 1;
12913         }
12914       else if (CONST_STRNEQ (p, "att"))
12915         {
12916           intel_syntax = 0;
12917           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12918             intel_mnemonic = 0;
12919         }
12920       else if (CONST_STRNEQ (p, "addr"))
12921         {
12922           if (address_mode == mode_64bit)
12923             {
12924               if (p[4] == '3' && p[5] == '2')
12925                 priv.orig_sizeflag &= ~AFLAG;
12926               else if (p[4] == '6' && p[5] == '4')
12927                 priv.orig_sizeflag |= AFLAG;
12928             }
12929           else
12930             {
12931               if (p[4] == '1' && p[5] == '6')
12932                 priv.orig_sizeflag &= ~AFLAG;
12933               else if (p[4] == '3' && p[5] == '2')
12934                 priv.orig_sizeflag |= AFLAG;
12935             }
12936         }
12937       else if (CONST_STRNEQ (p, "data"))
12938         {
12939           if (p[4] == '1' && p[5] == '6')
12940             priv.orig_sizeflag &= ~DFLAG;
12941           else if (p[4] == '3' && p[5] == '2')
12942             priv.orig_sizeflag |= DFLAG;
12943         }
12944       else if (CONST_STRNEQ (p, "suffix"))
12945         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12946
12947       p = strchr (p, ',');
12948       if (p != NULL)
12949         p++;
12950     }
12951
12952   if (intel_syntax)
12953     {
12954       names64 = intel_names64;
12955       names32 = intel_names32;
12956       names16 = intel_names16;
12957       names8 = intel_names8;
12958       names8rex = intel_names8rex;
12959       names_seg = intel_names_seg;
12960       names_mm = intel_names_mm;
12961       names_bnd = intel_names_bnd;
12962       names_xmm = intel_names_xmm;
12963       names_ymm = intel_names_ymm;
12964       names_zmm = intel_names_zmm;
12965       index64 = intel_index64;
12966       index32 = intel_index32;
12967       names_mask = intel_names_mask;
12968       index16 = intel_index16;
12969       open_char = '[';
12970       close_char = ']';
12971       separator_char = '+';
12972       scale_char = '*';
12973     }
12974   else
12975     {
12976       names64 = att_names64;
12977       names32 = att_names32;
12978       names16 = att_names16;
12979       names8 = att_names8;
12980       names8rex = att_names8rex;
12981       names_seg = att_names_seg;
12982       names_mm = att_names_mm;
12983       names_bnd = att_names_bnd;
12984       names_xmm = att_names_xmm;
12985       names_ymm = att_names_ymm;
12986       names_zmm = att_names_zmm;
12987       index64 = att_index64;
12988       index32 = att_index32;
12989       names_mask = att_names_mask;
12990       index16 = att_index16;
12991       open_char = '(';
12992       close_char =  ')';
12993       separator_char = ',';
12994       scale_char = ',';
12995     }
12996
12997   /* The output looks better if we put 7 bytes on a line, since that
12998      puts most long word instructions on a single line.  Use 8 bytes
12999      for Intel L1OM.  */
13000   if ((info->mach & bfd_mach_l1om) != 0)
13001     info->bytes_per_line = 8;
13002   else
13003     info->bytes_per_line = 7;
13004
13005   info->private_data = &priv;
13006   priv.max_fetched = priv.the_buffer;
13007   priv.insn_start = pc;
13008
13009   obuf[0] = 0;
13010   for (i = 0; i < MAX_OPERANDS; ++i)
13011     {
13012       op_out[i][0] = 0;
13013       op_index[i] = -1;
13014     }
13015
13016   the_info = info;
13017   start_pc = pc;
13018   start_codep = priv.the_buffer;
13019   codep = priv.the_buffer;
13020
13021   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13022     {
13023       const char *name;
13024
13025       /* Getting here means we tried for data but didn't get it.  That
13026          means we have an incomplete instruction of some sort.  Just
13027          print the first byte as a prefix or a .byte pseudo-op.  */
13028       if (codep > priv.the_buffer)
13029         {
13030           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13031           if (name != NULL)
13032             (*info->fprintf_func) (info->stream, "%s", name);
13033           else
13034             {
13035               /* Just print the first byte as a .byte instruction.  */
13036               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13037                                      (unsigned int) priv.the_buffer[0]);
13038             }
13039
13040           return 1;
13041         }
13042
13043       return -1;
13044     }
13045
13046   obufp = obuf;
13047   sizeflag = priv.orig_sizeflag;
13048
13049   if (!ckprefix () || rex_used)
13050     {
13051       /* Too many prefixes or unused REX prefixes.  */
13052       for (i = 0;
13053            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13054            i++)
13055         (*info->fprintf_func) (info->stream, "%s%s",
13056                                i == 0 ? "" : " ",
13057                                prefix_name (all_prefixes[i], sizeflag));
13058       return i;
13059     }
13060
13061   insn_codep = codep;
13062
13063   FETCH_DATA (info, codep + 1);
13064   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13065
13066   if (((prefixes & PREFIX_FWAIT)
13067        && ((*codep < 0xd8) || (*codep > 0xdf))))
13068     {
13069       /* Handle prefixes before fwait.  */
13070       for (i = 0; i < fwait_prefix && all_prefixes[i];
13071            i++)
13072         (*info->fprintf_func) (info->stream, "%s ",
13073                                prefix_name (all_prefixes[i], sizeflag));
13074       (*info->fprintf_func) (info->stream, "fwait");
13075       return i + 1;
13076     }
13077
13078   if (*codep == 0x0f)
13079     {
13080       unsigned char threebyte;
13081       FETCH_DATA (info, codep + 2);
13082       threebyte = *++codep;
13083       dp = &dis386_twobyte[threebyte];
13084       need_modrm = twobyte_has_modrm[*codep];
13085       codep++;
13086     }
13087   else
13088     {
13089       dp = &dis386[*codep];
13090       need_modrm = onebyte_has_modrm[*codep];
13091       codep++;
13092     }
13093
13094   /* Save sizeflag for printing the extra prefixes later before updating
13095      it for mnemonic and operand processing.  The prefix names depend
13096      only on the address mode.  */
13097   orig_sizeflag = sizeflag;
13098   if (prefixes & PREFIX_ADDR)
13099     sizeflag ^= AFLAG;
13100   if ((prefixes & PREFIX_DATA))
13101     sizeflag ^= DFLAG;
13102
13103   end_codep = codep;
13104   if (need_modrm)
13105     {
13106       FETCH_DATA (info, codep + 1);
13107       modrm.mod = (*codep >> 6) & 3;
13108       modrm.reg = (*codep >> 3) & 7;
13109       modrm.rm = *codep & 7;
13110     }
13111
13112   need_vex = 0;
13113   need_vex_reg = 0;
13114   vex_w_done = 0;
13115   vex.evex = 0;
13116
13117   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13118     {
13119       get_sib (info, sizeflag);
13120       dofloat (sizeflag);
13121     }
13122   else
13123     {
13124       dp = get_valid_dis386 (dp, info);
13125       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13126         {
13127           get_sib (info, sizeflag);
13128           for (i = 0; i < MAX_OPERANDS; ++i)
13129             {
13130               obufp = op_out[i];
13131               op_ad = MAX_OPERANDS - 1 - i;
13132               if (dp->op[i].rtn)
13133                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13134               /* For EVEX instruction after the last operand masking
13135                  should be printed.  */
13136               if (i == 0 && vex.evex)
13137                 {
13138                   /* Don't print {%k0}.  */
13139                   if (vex.mask_register_specifier)
13140                     {
13141                       oappend ("{");
13142                       oappend (names_mask[vex.mask_register_specifier]);
13143                       oappend ("}");
13144                     }
13145                   if (vex.zeroing)
13146                     oappend ("{z}");
13147                 }
13148             }
13149         }
13150     }
13151
13152   /* Check if the REX prefix is used.  */
13153   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13154     all_prefixes[last_rex_prefix] = 0;
13155
13156   /* Check if the SEG prefix is used.  */
13157   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13158                    | PREFIX_FS | PREFIX_GS)) != 0
13159       && (used_prefixes & active_seg_prefix) != 0)
13160     all_prefixes[last_seg_prefix] = 0;
13161
13162   /* Check if the ADDR prefix is used.  */
13163   if ((prefixes & PREFIX_ADDR) != 0
13164       && (used_prefixes & PREFIX_ADDR) != 0)
13165     all_prefixes[last_addr_prefix] = 0;
13166
13167   /* Check if the DATA prefix is used.  */
13168   if ((prefixes & PREFIX_DATA) != 0
13169       && (used_prefixes & PREFIX_DATA) != 0)
13170     all_prefixes[last_data_prefix] = 0;
13171
13172   /* Print the extra prefixes.  */
13173   prefix_length = 0;
13174   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13175     if (all_prefixes[i])
13176       {
13177         const char *name;
13178         name = prefix_name (all_prefixes[i], orig_sizeflag);
13179         if (name == NULL)
13180           abort ();
13181         prefix_length += strlen (name) + 1;
13182         (*info->fprintf_func) (info->stream, "%s ", name);
13183       }
13184
13185   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13186      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13187      used by putop and MMX/SSE operand and may be overriden by the
13188      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13189      separately.  */
13190   if (dp->prefix_requirement == PREFIX_OPCODE
13191       && dp != &bad_opcode
13192       && (((prefixes
13193             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13194            && (used_prefixes
13195                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13196           || ((((prefixes
13197                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13198                 == PREFIX_DATA)
13199                && (used_prefixes & PREFIX_DATA) == 0))))
13200     {
13201       (*info->fprintf_func) (info->stream, "(bad)");
13202       return end_codep - priv.the_buffer;
13203     }
13204
13205   /* Check maximum code length.  */
13206   if ((codep - start_codep) > MAX_CODE_LENGTH)
13207     {
13208       (*info->fprintf_func) (info->stream, "(bad)");
13209       return MAX_CODE_LENGTH;
13210     }
13211
13212   obufp = mnemonicendp;
13213   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13214     oappend (" ");
13215   oappend (" ");
13216   (*info->fprintf_func) (info->stream, "%s", obuf);
13217
13218   /* The enter and bound instructions are printed with operands in the same
13219      order as the intel book; everything else is printed in reverse order.  */
13220   if (intel_syntax || two_source_ops)
13221     {
13222       bfd_vma riprel;
13223
13224       for (i = 0; i < MAX_OPERANDS; ++i)
13225         op_txt[i] = op_out[i];
13226
13227       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13228         {
13229           op_ad = op_index[i];
13230           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13231           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13232           riprel = op_riprel[i];
13233           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13234           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13235         }
13236     }
13237   else
13238     {
13239       for (i = 0; i < MAX_OPERANDS; ++i)
13240         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13241     }
13242
13243   needcomma = 0;
13244   for (i = 0; i < MAX_OPERANDS; ++i)
13245     if (*op_txt[i])
13246       {
13247         if (needcomma)
13248           (*info->fprintf_func) (info->stream, ",");
13249         if (op_index[i] != -1 && !op_riprel[i])
13250           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13251         else
13252           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13253         needcomma = 1;
13254       }
13255
13256   for (i = 0; i < MAX_OPERANDS; i++)
13257     if (op_index[i] != -1 && op_riprel[i])
13258       {
13259         (*info->fprintf_func) (info->stream, "        # ");
13260         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13261                                                 + op_address[op_index[i]]), info);
13262         break;
13263       }
13264   return codep - priv.the_buffer;
13265 }
13266
13267 static const char *float_mem[] = {
13268   /* d8 */
13269   "fadd{s|}",
13270   "fmul{s|}",
13271   "fcom{s|}",
13272   "fcomp{s|}",
13273   "fsub{s|}",
13274   "fsubr{s|}",
13275   "fdiv{s|}",
13276   "fdivr{s|}",
13277   /* d9 */
13278   "fld{s|}",
13279   "(bad)",
13280   "fst{s|}",
13281   "fstp{s|}",
13282   "fldenvIC",
13283   "fldcw",
13284   "fNstenvIC",
13285   "fNstcw",
13286   /* da */
13287   "fiadd{l|}",
13288   "fimul{l|}",
13289   "ficom{l|}",
13290   "ficomp{l|}",
13291   "fisub{l|}",
13292   "fisubr{l|}",
13293   "fidiv{l|}",
13294   "fidivr{l|}",
13295   /* db */
13296   "fild{l|}",
13297   "fisttp{l|}",
13298   "fist{l|}",
13299   "fistp{l|}",
13300   "(bad)",
13301   "fld{t||t|}",
13302   "(bad)",
13303   "fstp{t||t|}",
13304   /* dc */
13305   "fadd{l|}",
13306   "fmul{l|}",
13307   "fcom{l|}",
13308   "fcomp{l|}",
13309   "fsub{l|}",
13310   "fsubr{l|}",
13311   "fdiv{l|}",
13312   "fdivr{l|}",
13313   /* dd */
13314   "fld{l|}",
13315   "fisttp{ll|}",
13316   "fst{l||}",
13317   "fstp{l|}",
13318   "frstorIC",
13319   "(bad)",
13320   "fNsaveIC",
13321   "fNstsw",
13322   /* de */
13323   "fiadd",
13324   "fimul",
13325   "ficom",
13326   "ficomp",
13327   "fisub",
13328   "fisubr",
13329   "fidiv",
13330   "fidivr",
13331   /* df */
13332   "fild",
13333   "fisttp",
13334   "fist",
13335   "fistp",
13336   "fbld",
13337   "fild{ll|}",
13338   "fbstp",
13339   "fistp{ll|}",
13340 };
13341
13342 static const unsigned char float_mem_mode[] = {
13343   /* d8 */
13344   d_mode,
13345   d_mode,
13346   d_mode,
13347   d_mode,
13348   d_mode,
13349   d_mode,
13350   d_mode,
13351   d_mode,
13352   /* d9 */
13353   d_mode,
13354   0,
13355   d_mode,
13356   d_mode,
13357   0,
13358   w_mode,
13359   0,
13360   w_mode,
13361   /* da */
13362   d_mode,
13363   d_mode,
13364   d_mode,
13365   d_mode,
13366   d_mode,
13367   d_mode,
13368   d_mode,
13369   d_mode,
13370   /* db */
13371   d_mode,
13372   d_mode,
13373   d_mode,
13374   d_mode,
13375   0,
13376   t_mode,
13377   0,
13378   t_mode,
13379   /* dc */
13380   q_mode,
13381   q_mode,
13382   q_mode,
13383   q_mode,
13384   q_mode,
13385   q_mode,
13386   q_mode,
13387   q_mode,
13388   /* dd */
13389   q_mode,
13390   q_mode,
13391   q_mode,
13392   q_mode,
13393   0,
13394   0,
13395   0,
13396   w_mode,
13397   /* de */
13398   w_mode,
13399   w_mode,
13400   w_mode,
13401   w_mode,
13402   w_mode,
13403   w_mode,
13404   w_mode,
13405   w_mode,
13406   /* df */
13407   w_mode,
13408   w_mode,
13409   w_mode,
13410   w_mode,
13411   t_mode,
13412   q_mode,
13413   t_mode,
13414   q_mode
13415 };
13416
13417 #define ST { OP_ST, 0 }
13418 #define STi { OP_STi, 0 }
13419
13420 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13421 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13422 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13423 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13424 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13425 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13426 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13427 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13428 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13429
13430 static const struct dis386 float_reg[][8] = {
13431   /* d8 */
13432   {
13433     { "fadd",   { ST, STi }, 0 },
13434     { "fmul",   { ST, STi }, 0 },
13435     { "fcom",   { STi }, 0 },
13436     { "fcomp",  { STi }, 0 },
13437     { "fsub",   { ST, STi }, 0 },
13438     { "fsubr",  { ST, STi }, 0 },
13439     { "fdiv",   { ST, STi }, 0 },
13440     { "fdivr",  { ST, STi }, 0 },
13441   },
13442   /* d9 */
13443   {
13444     { "fld",    { STi }, 0 },
13445     { "fxch",   { STi }, 0 },
13446     { FGRPd9_2 },
13447     { Bad_Opcode },
13448     { FGRPd9_4 },
13449     { FGRPd9_5 },
13450     { FGRPd9_6 },
13451     { FGRPd9_7 },
13452   },
13453   /* da */
13454   {
13455     { "fcmovb", { ST, STi }, 0 },
13456     { "fcmove", { ST, STi }, 0 },
13457     { "fcmovbe",{ ST, STi }, 0 },
13458     { "fcmovu", { ST, STi }, 0 },
13459     { Bad_Opcode },
13460     { FGRPda_5 },
13461     { Bad_Opcode },
13462     { Bad_Opcode },
13463   },
13464   /* db */
13465   {
13466     { "fcmovnb",{ ST, STi }, 0 },
13467     { "fcmovne",{ ST, STi }, 0 },
13468     { "fcmovnbe",{ ST, STi }, 0 },
13469     { "fcmovnu",{ ST, STi }, 0 },
13470     { FGRPdb_4 },
13471     { "fucomi", { ST, STi }, 0 },
13472     { "fcomi",  { ST, STi }, 0 },
13473     { Bad_Opcode },
13474   },
13475   /* dc */
13476   {
13477     { "fadd",   { STi, ST }, 0 },
13478     { "fmul",   { STi, ST }, 0 },
13479     { Bad_Opcode },
13480     { Bad_Opcode },
13481     { "fsub!M", { STi, ST }, 0 },
13482     { "fsubM",  { STi, ST }, 0 },
13483     { "fdiv!M", { STi, ST }, 0 },
13484     { "fdivM",  { STi, ST }, 0 },
13485   },
13486   /* dd */
13487   {
13488     { "ffree",  { STi }, 0 },
13489     { Bad_Opcode },
13490     { "fst",    { STi }, 0 },
13491     { "fstp",   { STi }, 0 },
13492     { "fucom",  { STi }, 0 },
13493     { "fucomp", { STi }, 0 },
13494     { Bad_Opcode },
13495     { Bad_Opcode },
13496   },
13497   /* de */
13498   {
13499     { "faddp",  { STi, ST }, 0 },
13500     { "fmulp",  { STi, ST }, 0 },
13501     { Bad_Opcode },
13502     { FGRPde_3 },
13503     { "fsub!Mp", { STi, ST }, 0 },
13504     { "fsubMp", { STi, ST }, 0 },
13505     { "fdiv!Mp", { STi, ST }, 0 },
13506     { "fdivMp", { STi, ST }, 0 },
13507   },
13508   /* df */
13509   {
13510     { "ffreep", { STi }, 0 },
13511     { Bad_Opcode },
13512     { Bad_Opcode },
13513     { Bad_Opcode },
13514     { FGRPdf_4 },
13515     { "fucomip", { ST, STi }, 0 },
13516     { "fcomip", { ST, STi }, 0 },
13517     { Bad_Opcode },
13518   },
13519 };
13520
13521 static char *fgrps[][8] = {
13522   /* d9_2  0 */
13523   {
13524     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13525   },
13526
13527   /* d9_4  1 */
13528   {
13529     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13530   },
13531
13532   /* d9_5  2 */
13533   {
13534     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13535   },
13536
13537   /* d9_6  3 */
13538   {
13539     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13540   },
13541
13542   /* d9_7  4 */
13543   {
13544     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13545   },
13546
13547   /* da_5  5 */
13548   {
13549     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13550   },
13551
13552   /* db_4  6 */
13553   {
13554     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13555     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13556   },
13557
13558   /* de_3  7 */
13559   {
13560     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13561   },
13562
13563   /* df_4  8 */
13564   {
13565     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13566   },
13567 };
13568
13569 static void
13570 swap_operand (void)
13571 {
13572   mnemonicendp[0] = '.';
13573   mnemonicendp[1] = 's';
13574   mnemonicendp += 2;
13575 }
13576
13577 static void
13578 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13579                int sizeflag ATTRIBUTE_UNUSED)
13580 {
13581   /* Skip mod/rm byte.  */
13582   MODRM_CHECK;
13583   codep++;
13584 }
13585
13586 static void
13587 dofloat (int sizeflag)
13588 {
13589   const struct dis386 *dp;
13590   unsigned char floatop;
13591
13592   floatop = codep[-1];
13593
13594   if (modrm.mod != 3)
13595     {
13596       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13597
13598       putop (float_mem[fp_indx], sizeflag);
13599       obufp = op_out[0];
13600       op_ad = 2;
13601       OP_E (float_mem_mode[fp_indx], sizeflag);
13602       return;
13603     }
13604   /* Skip mod/rm byte.  */
13605   MODRM_CHECK;
13606   codep++;
13607
13608   dp = &float_reg[floatop - 0xd8][modrm.reg];
13609   if (dp->name == NULL)
13610     {
13611       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13612
13613       /* Instruction fnstsw is only one with strange arg.  */
13614       if (floatop == 0xdf && codep[-1] == 0xe0)
13615         strcpy (op_out[0], names16[0]);
13616     }
13617   else
13618     {
13619       putop (dp->name, sizeflag);
13620
13621       obufp = op_out[0];
13622       op_ad = 2;
13623       if (dp->op[0].rtn)
13624         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13625
13626       obufp = op_out[1];
13627       op_ad = 1;
13628       if (dp->op[1].rtn)
13629         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13630     }
13631 }
13632
13633 /* Like oappend (below), but S is a string starting with '%'.
13634    In Intel syntax, the '%' is elided.  */
13635 static void
13636 oappend_maybe_intel (const char *s)
13637 {
13638   oappend (s + intel_syntax);
13639 }
13640
13641 static void
13642 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13643 {
13644   oappend_maybe_intel ("%st");
13645 }
13646
13647 static void
13648 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13649 {
13650   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13651   oappend_maybe_intel (scratchbuf);
13652 }
13653
13654 /* Capital letters in template are macros.  */
13655 static int
13656 putop (const char *in_template, int sizeflag)
13657 {
13658   const char *p;
13659   int alt = 0;
13660   int cond = 1;
13661   unsigned int l = 0, len = 1;
13662   char last[4];
13663
13664 #define SAVE_LAST(c)                    \
13665   if (l < len && l < sizeof (last))     \
13666     last[l++] = c;                      \
13667   else                                  \
13668     abort ();
13669
13670   for (p = in_template; *p; p++)
13671     {
13672       switch (*p)
13673         {
13674         default:
13675           *obufp++ = *p;
13676           break;
13677         case '%':
13678           len++;
13679           break;
13680         case '!':
13681           cond = 0;
13682           break;
13683         case '{':
13684           alt = 0;
13685           if (intel_syntax)
13686             {
13687               while (*++p != '|')
13688                 if (*p == '}' || *p == '\0')
13689                   abort ();
13690             }
13691           /* Fall through.  */
13692         case 'I':
13693           alt = 1;
13694           continue;
13695         case '|':
13696           while (*++p != '}')
13697             {
13698               if (*p == '\0')
13699                 abort ();
13700             }
13701           break;
13702         case '}':
13703           break;
13704         case 'A':
13705           if (intel_syntax)
13706             break;
13707           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13708             *obufp++ = 'b';
13709           break;
13710         case 'B':
13711           if (l == 0 && len == 1)
13712             {
13713 case_B:
13714               if (intel_syntax)
13715                 break;
13716               if (sizeflag & SUFFIX_ALWAYS)
13717                 *obufp++ = 'b';
13718             }
13719           else
13720             {
13721               if (l != 1
13722                   || len != 2
13723                   || last[0] != 'L')
13724                 {
13725                   SAVE_LAST (*p);
13726                   break;
13727                 }
13728
13729               if (address_mode == mode_64bit
13730                   && !(prefixes & PREFIX_ADDR))
13731                 {
13732                   *obufp++ = 'a';
13733                   *obufp++ = 'b';
13734                   *obufp++ = 's';
13735                 }
13736
13737               goto case_B;
13738             }
13739           break;
13740         case 'C':
13741           if (intel_syntax && !alt)
13742             break;
13743           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13744             {
13745               if (sizeflag & DFLAG)
13746                 *obufp++ = intel_syntax ? 'd' : 'l';
13747               else
13748                 *obufp++ = intel_syntax ? 'w' : 's';
13749               used_prefixes |= (prefixes & PREFIX_DATA);
13750             }
13751           break;
13752         case 'D':
13753           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13754             break;
13755           USED_REX (REX_W);
13756           if (modrm.mod == 3)
13757             {
13758               if (rex & REX_W)
13759                 *obufp++ = 'q';
13760               else
13761                 {
13762                   if (sizeflag & DFLAG)
13763                     *obufp++ = intel_syntax ? 'd' : 'l';
13764                   else
13765                     *obufp++ = 'w';
13766                   used_prefixes |= (prefixes & PREFIX_DATA);
13767                 }
13768             }
13769           else
13770             *obufp++ = 'w';
13771           break;
13772         case 'E':               /* For jcxz/jecxz */
13773           if (address_mode == mode_64bit)
13774             {
13775               if (sizeflag & AFLAG)
13776                 *obufp++ = 'r';
13777               else
13778                 *obufp++ = 'e';
13779             }
13780           else
13781             if (sizeflag & AFLAG)
13782               *obufp++ = 'e';
13783           used_prefixes |= (prefixes & PREFIX_ADDR);
13784           break;
13785         case 'F':
13786           if (intel_syntax)
13787             break;
13788           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13789             {
13790               if (sizeflag & AFLAG)
13791                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13792               else
13793                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13794               used_prefixes |= (prefixes & PREFIX_ADDR);
13795             }
13796           break;
13797         case 'G':
13798           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13799             break;
13800           if ((rex & REX_W) || (sizeflag & DFLAG))
13801             *obufp++ = 'l';
13802           else
13803             *obufp++ = 'w';
13804           if (!(rex & REX_W))
13805             used_prefixes |= (prefixes & PREFIX_DATA);
13806           break;
13807         case 'H':
13808           if (intel_syntax)
13809             break;
13810           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13811               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13812             {
13813               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13814               *obufp++ = ',';
13815               *obufp++ = 'p';
13816               if (prefixes & PREFIX_DS)
13817                 *obufp++ = 't';
13818               else
13819                 *obufp++ = 'n';
13820             }
13821           break;
13822         case 'J':
13823           if (intel_syntax)
13824             break;
13825           *obufp++ = 'l';
13826           break;
13827         case 'K':
13828           USED_REX (REX_W);
13829           if (rex & REX_W)
13830             *obufp++ = 'q';
13831           else
13832             *obufp++ = 'd';
13833           break;
13834         case 'Z':
13835           if (l != 0 || len != 1)
13836             {
13837               if (l != 1 || len != 2 || last[0] != 'X')
13838                 {
13839                   SAVE_LAST (*p);
13840                   break;
13841                 }
13842               if (!need_vex || !vex.evex)
13843                 abort ();
13844               if (intel_syntax
13845                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13846                 break;
13847               switch (vex.length)
13848                 {
13849                 case 128:
13850                   *obufp++ = 'x';
13851                   break;
13852                 case 256:
13853                   *obufp++ = 'y';
13854                   break;
13855                 case 512:
13856                   *obufp++ = 'z';
13857                   break;
13858                 default:
13859                   abort ();
13860                 }
13861               break;
13862             }
13863           if (intel_syntax)
13864             break;
13865           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13866             {
13867               *obufp++ = 'q';
13868               break;
13869             }
13870           /* Fall through.  */
13871           goto case_L;
13872         case 'L':
13873           if (l != 0 || len != 1)
13874             {
13875               SAVE_LAST (*p);
13876               break;
13877             }
13878 case_L:
13879           if (intel_syntax)
13880             break;
13881           if (sizeflag & SUFFIX_ALWAYS)
13882             *obufp++ = 'l';
13883           break;
13884         case 'M':
13885           if (intel_mnemonic != cond)
13886             *obufp++ = 'r';
13887           break;
13888         case 'N':
13889           if ((prefixes & PREFIX_FWAIT) == 0)
13890             *obufp++ = 'n';
13891           else
13892             used_prefixes |= PREFIX_FWAIT;
13893           break;
13894         case 'O':
13895           USED_REX (REX_W);
13896           if (rex & REX_W)
13897             *obufp++ = 'o';
13898           else if (intel_syntax && (sizeflag & DFLAG))
13899             *obufp++ = 'q';
13900           else
13901             *obufp++ = 'd';
13902           if (!(rex & REX_W))
13903             used_prefixes |= (prefixes & PREFIX_DATA);
13904           break;
13905         case 'T':
13906           if (!intel_syntax
13907               && address_mode == mode_64bit
13908               && ((sizeflag & DFLAG) || (rex & REX_W)))
13909             {
13910               *obufp++ = 'q';
13911               break;
13912             }
13913           /* Fall through.  */
13914           goto case_P;
13915         case 'P':
13916           if (l == 0 && len == 1)
13917             {
13918 case_P:
13919               if (intel_syntax)
13920                 {
13921                   if ((rex & REX_W) == 0
13922                       && (prefixes & PREFIX_DATA))
13923                     {
13924                       if ((sizeflag & DFLAG) == 0)
13925                         *obufp++ = 'w';
13926                       used_prefixes |= (prefixes & PREFIX_DATA);
13927                     }
13928                   break;
13929                 }
13930               if ((prefixes & PREFIX_DATA)
13931                   || (rex & REX_W)
13932                   || (sizeflag & SUFFIX_ALWAYS))
13933                 {
13934                   USED_REX (REX_W);
13935                   if (rex & REX_W)
13936                     *obufp++ = 'q';
13937                   else
13938                     {
13939                       if (sizeflag & DFLAG)
13940                         *obufp++ = 'l';
13941                       else
13942                         *obufp++ = 'w';
13943                       used_prefixes |= (prefixes & PREFIX_DATA);
13944                     }
13945                 }
13946             }
13947           else
13948             {
13949               if (l != 1 || len != 2 || last[0] != 'L')
13950                 {
13951                   SAVE_LAST (*p);
13952                   break;
13953                 }
13954
13955               if ((prefixes & PREFIX_DATA)
13956                   || (rex & REX_W)
13957                   || (sizeflag & SUFFIX_ALWAYS))
13958                 {
13959                   USED_REX (REX_W);
13960                   if (rex & REX_W)
13961                     *obufp++ = 'q';
13962                   else
13963                     {
13964                       if (sizeflag & DFLAG)
13965                         *obufp++ = intel_syntax ? 'd' : 'l';
13966                       else
13967                         *obufp++ = 'w';
13968                       used_prefixes |= (prefixes & PREFIX_DATA);
13969                     }
13970                 }
13971             }
13972           break;
13973         case 'U':
13974           if (intel_syntax)
13975             break;
13976           if (address_mode == mode_64bit
13977               && ((sizeflag & DFLAG) || (rex & REX_W)))
13978             {
13979               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13980                 *obufp++ = 'q';
13981               break;
13982             }
13983           /* Fall through.  */
13984           goto case_Q;
13985         case 'Q':
13986           if (l == 0 && len == 1)
13987             {
13988 case_Q:
13989               if (intel_syntax && !alt)
13990                 break;
13991               USED_REX (REX_W);
13992               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13993                 {
13994                   if (rex & REX_W)
13995                     *obufp++ = 'q';
13996                   else
13997                     {
13998                       if (sizeflag & DFLAG)
13999                         *obufp++ = intel_syntax ? 'd' : 'l';
14000                       else
14001                         *obufp++ = 'w';
14002                       used_prefixes |= (prefixes & PREFIX_DATA);
14003                     }
14004                 }
14005             }
14006           else
14007             {
14008               if (l != 1 || len != 2 || last[0] != 'L')
14009                 {
14010                   SAVE_LAST (*p);
14011                   break;
14012                 }
14013               if (intel_syntax
14014                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14015                 break;
14016               if ((rex & REX_W))
14017                 {
14018                   USED_REX (REX_W);
14019                   *obufp++ = 'q';
14020                 }
14021               else
14022                 *obufp++ = 'l';
14023             }
14024           break;
14025         case 'R':
14026           USED_REX (REX_W);
14027           if (rex & REX_W)
14028             *obufp++ = 'q';
14029           else if (sizeflag & DFLAG)
14030             {
14031               if (intel_syntax)
14032                   *obufp++ = 'd';
14033               else
14034                   *obufp++ = 'l';
14035             }
14036           else
14037             *obufp++ = 'w';
14038           if (intel_syntax && !p[1]
14039               && ((rex & REX_W) || (sizeflag & DFLAG)))
14040             *obufp++ = 'e';
14041           if (!(rex & REX_W))
14042             used_prefixes |= (prefixes & PREFIX_DATA);
14043           break;
14044         case 'V':
14045           if (l == 0 && len == 1)
14046             {
14047               if (intel_syntax)
14048                 break;
14049               if (address_mode == mode_64bit
14050                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14051                 {
14052                   if (sizeflag & SUFFIX_ALWAYS)
14053                     *obufp++ = 'q';
14054                   break;
14055                 }
14056             }
14057           else
14058             {
14059               if (l != 1
14060                   || len != 2
14061                   || last[0] != 'L')
14062                 {
14063                   SAVE_LAST (*p);
14064                   break;
14065                 }
14066
14067               if (rex & REX_W)
14068                 {
14069                   *obufp++ = 'a';
14070                   *obufp++ = 'b';
14071                   *obufp++ = 's';
14072                 }
14073             }
14074           /* Fall through.  */
14075           goto case_S;
14076         case 'S':
14077           if (l == 0 && len == 1)
14078             {
14079 case_S:
14080               if (intel_syntax)
14081                 break;
14082               if (sizeflag & SUFFIX_ALWAYS)
14083                 {
14084                   if (rex & REX_W)
14085                     *obufp++ = 'q';
14086                   else
14087                     {
14088                       if (sizeflag & DFLAG)
14089                         *obufp++ = 'l';
14090                       else
14091                         *obufp++ = 'w';
14092                       used_prefixes |= (prefixes & PREFIX_DATA);
14093                     }
14094                 }
14095             }
14096           else
14097             {
14098               if (l != 1
14099                   || len != 2
14100                   || last[0] != 'L')
14101                 {
14102                   SAVE_LAST (*p);
14103                   break;
14104                 }
14105
14106               if (address_mode == mode_64bit
14107                   && !(prefixes & PREFIX_ADDR))
14108                 {
14109                   *obufp++ = 'a';
14110                   *obufp++ = 'b';
14111                   *obufp++ = 's';
14112                 }
14113
14114               goto case_S;
14115             }
14116           break;
14117         case 'X':
14118           if (l != 0 || len != 1)
14119             {
14120               SAVE_LAST (*p);
14121               break;
14122             }
14123           if (need_vex && vex.prefix)
14124             {
14125               if (vex.prefix == DATA_PREFIX_OPCODE)
14126                 *obufp++ = 'd';
14127               else
14128                 *obufp++ = 's';
14129             }
14130           else
14131             {
14132               if (prefixes & PREFIX_DATA)
14133                 *obufp++ = 'd';
14134               else
14135                 *obufp++ = 's';
14136               used_prefixes |= (prefixes & PREFIX_DATA);
14137             }
14138           break;
14139         case 'Y':
14140           if (l == 0 && len == 1)
14141             {
14142               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14143                 break;
14144               if (rex & REX_W)
14145                 {
14146                   USED_REX (REX_W);
14147                   *obufp++ = 'q';
14148                 }
14149               break;
14150             }
14151           else
14152             {
14153               if (l != 1 || len != 2 || last[0] != 'X')
14154                 {
14155                   SAVE_LAST (*p);
14156                   break;
14157                 }
14158               if (!need_vex)
14159                 abort ();
14160               if (intel_syntax
14161                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14162                 break;
14163               switch (vex.length)
14164                 {
14165                 case 128:
14166                   *obufp++ = 'x';
14167                   break;
14168                 case 256:
14169                   *obufp++ = 'y';
14170                   break;
14171                 case 512:
14172                   if (!vex.evex)
14173                 default:
14174                     abort ();
14175                 }
14176             }
14177           break;
14178         case 'W':
14179           if (l == 0 && len == 1)
14180             {
14181               /* operand size flag for cwtl, cbtw */
14182               USED_REX (REX_W);
14183               if (rex & REX_W)
14184                 {
14185                   if (intel_syntax)
14186                     *obufp++ = 'd';
14187                   else
14188                     *obufp++ = 'l';
14189                 }
14190               else if (sizeflag & DFLAG)
14191                 *obufp++ = 'w';
14192               else
14193                 *obufp++ = 'b';
14194               if (!(rex & REX_W))
14195                 used_prefixes |= (prefixes & PREFIX_DATA);
14196             }
14197           else
14198             {
14199               if (l != 1
14200                   || len != 2
14201                   || (last[0] != 'X'
14202                       && last[0] != 'L'))
14203                 {
14204                   SAVE_LAST (*p);
14205                   break;
14206                 }
14207               if (!need_vex)
14208                 abort ();
14209               if (last[0] == 'X')
14210                 *obufp++ = vex.w ? 'd': 's';
14211               else
14212                 *obufp++ = vex.w ? 'q': 'd';
14213             }
14214           break;
14215         case '^':
14216           if (intel_syntax)
14217             break;
14218           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14219             {
14220               if (sizeflag & DFLAG)
14221                 *obufp++ = 'l';
14222               else
14223                 *obufp++ = 'w';
14224               used_prefixes |= (prefixes & PREFIX_DATA);
14225             }
14226           break;
14227         case '@':
14228           if (intel_syntax)
14229             break;
14230           if (address_mode == mode_64bit
14231               && (isa64 == intel64
14232                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14233               *obufp++ = 'q';
14234           else if ((prefixes & PREFIX_DATA))
14235             {
14236               if (!(sizeflag & DFLAG))
14237                 *obufp++ = 'w';
14238               used_prefixes |= (prefixes & PREFIX_DATA);
14239             }
14240           break;
14241         }
14242       alt = 0;
14243     }
14244   *obufp = 0;
14245   mnemonicendp = obufp;
14246   return 0;
14247 }
14248
14249 static void
14250 oappend (const char *s)
14251 {
14252   obufp = stpcpy (obufp, s);
14253 }
14254
14255 static void
14256 append_seg (void)
14257 {
14258   /* Only print the active segment register.  */
14259   if (!active_seg_prefix)
14260     return;
14261
14262   used_prefixes |= active_seg_prefix;
14263   switch (active_seg_prefix)
14264     {
14265     case PREFIX_CS:
14266       oappend_maybe_intel ("%cs:");
14267       break;
14268     case PREFIX_DS:
14269       oappend_maybe_intel ("%ds:");
14270       break;
14271     case PREFIX_SS:
14272       oappend_maybe_intel ("%ss:");
14273       break;
14274     case PREFIX_ES:
14275       oappend_maybe_intel ("%es:");
14276       break;
14277     case PREFIX_FS:
14278       oappend_maybe_intel ("%fs:");
14279       break;
14280     case PREFIX_GS:
14281       oappend_maybe_intel ("%gs:");
14282       break;
14283     default:
14284       break;
14285     }
14286 }
14287
14288 static void
14289 OP_indirE (int bytemode, int sizeflag)
14290 {
14291   if (!intel_syntax)
14292     oappend ("*");
14293   OP_E (bytemode, sizeflag);
14294 }
14295
14296 static void
14297 print_operand_value (char *buf, int hex, bfd_vma disp)
14298 {
14299   if (address_mode == mode_64bit)
14300     {
14301       if (hex)
14302         {
14303           char tmp[30];
14304           int i;
14305           buf[0] = '0';
14306           buf[1] = 'x';
14307           sprintf_vma (tmp, disp);
14308           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14309           strcpy (buf + 2, tmp + i);
14310         }
14311       else
14312         {
14313           bfd_signed_vma v = disp;
14314           char tmp[30];
14315           int i;
14316           if (v < 0)
14317             {
14318               *(buf++) = '-';
14319               v = -disp;
14320               /* Check for possible overflow on 0x8000000000000000.  */
14321               if (v < 0)
14322                 {
14323                   strcpy (buf, "9223372036854775808");
14324                   return;
14325                 }
14326             }
14327           if (!v)
14328             {
14329               strcpy (buf, "0");
14330               return;
14331             }
14332
14333           i = 0;
14334           tmp[29] = 0;
14335           while (v)
14336             {
14337               tmp[28 - i] = (v % 10) + '0';
14338               v /= 10;
14339               i++;
14340             }
14341           strcpy (buf, tmp + 29 - i);
14342         }
14343     }
14344   else
14345     {
14346       if (hex)
14347         sprintf (buf, "0x%x", (unsigned int) disp);
14348       else
14349         sprintf (buf, "%d", (int) disp);
14350     }
14351 }
14352
14353 /* Put DISP in BUF as signed hex number.  */
14354
14355 static void
14356 print_displacement (char *buf, bfd_vma disp)
14357 {
14358   bfd_signed_vma val = disp;
14359   char tmp[30];
14360   int i, j = 0;
14361
14362   if (val < 0)
14363     {
14364       buf[j++] = '-';
14365       val = -disp;
14366
14367       /* Check for possible overflow.  */
14368       if (val < 0)
14369         {
14370           switch (address_mode)
14371             {
14372             case mode_64bit:
14373               strcpy (buf + j, "0x8000000000000000");
14374               break;
14375             case mode_32bit:
14376               strcpy (buf + j, "0x80000000");
14377               break;
14378             case mode_16bit:
14379               strcpy (buf + j, "0x8000");
14380               break;
14381             }
14382           return;
14383         }
14384     }
14385
14386   buf[j++] = '0';
14387   buf[j++] = 'x';
14388
14389   sprintf_vma (tmp, (bfd_vma) val);
14390   for (i = 0; tmp[i] == '0'; i++)
14391     continue;
14392   if (tmp[i] == '\0')
14393     i--;
14394   strcpy (buf + j, tmp + i);
14395 }
14396
14397 static void
14398 intel_operand_size (int bytemode, int sizeflag)
14399 {
14400   if (vex.evex
14401       && vex.b
14402       && (bytemode == x_mode
14403           || bytemode == evex_half_bcst_xmmq_mode))
14404     {
14405       if (vex.w)
14406         oappend ("QWORD PTR ");
14407       else
14408         oappend ("DWORD PTR ");
14409       return;
14410     }
14411   switch (bytemode)
14412     {
14413     case b_mode:
14414     case b_swap_mode:
14415     case dqb_mode:
14416     case db_mode:
14417       oappend ("BYTE PTR ");
14418       break;
14419     case w_mode:
14420     case dw_mode:
14421     case dqw_mode:
14422     case dqw_swap_mode:
14423       oappend ("WORD PTR ");
14424       break;
14425     case stack_v_mode:
14426       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14427         {
14428           oappend ("QWORD PTR ");
14429           break;
14430         }
14431       /* FALLTHRU */
14432     case v_mode:
14433     case v_swap_mode:
14434     case dq_mode:
14435       USED_REX (REX_W);
14436       if (rex & REX_W)
14437         oappend ("QWORD PTR ");
14438       else
14439         {
14440           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14441             oappend ("DWORD PTR ");
14442           else
14443             oappend ("WORD PTR ");
14444           used_prefixes |= (prefixes & PREFIX_DATA);
14445         }
14446       break;
14447     case z_mode:
14448       if ((rex & REX_W) || (sizeflag & DFLAG))
14449         *obufp++ = 'D';
14450       oappend ("WORD PTR ");
14451       if (!(rex & REX_W))
14452         used_prefixes |= (prefixes & PREFIX_DATA);
14453       break;
14454     case a_mode:
14455       if (sizeflag & DFLAG)
14456         oappend ("QWORD PTR ");
14457       else
14458         oappend ("DWORD PTR ");
14459       used_prefixes |= (prefixes & PREFIX_DATA);
14460       break;
14461     case d_mode:
14462     case d_scalar_mode:
14463     case d_scalar_swap_mode:
14464     case d_swap_mode:
14465     case dqd_mode:
14466       oappend ("DWORD PTR ");
14467       break;
14468     case q_mode:
14469     case q_scalar_mode:
14470     case q_scalar_swap_mode:
14471     case q_swap_mode:
14472       oappend ("QWORD PTR ");
14473       break;
14474     case m_mode:
14475       if (address_mode == mode_64bit)
14476         oappend ("QWORD PTR ");
14477       else
14478         oappend ("DWORD PTR ");
14479       break;
14480     case f_mode:
14481       if (sizeflag & DFLAG)
14482         oappend ("FWORD PTR ");
14483       else
14484         oappend ("DWORD PTR ");
14485       used_prefixes |= (prefixes & PREFIX_DATA);
14486       break;
14487     case t_mode:
14488       oappend ("TBYTE PTR ");
14489       break;
14490     case x_mode:
14491     case x_swap_mode:
14492     case evex_x_gscat_mode:
14493     case evex_x_nobcst_mode:
14494       if (need_vex)
14495         {
14496           switch (vex.length)
14497             {
14498             case 128:
14499               oappend ("XMMWORD PTR ");
14500               break;
14501             case 256:
14502               oappend ("YMMWORD PTR ");
14503               break;
14504             case 512:
14505               oappend ("ZMMWORD PTR ");
14506               break;
14507             default:
14508               abort ();
14509             }
14510         }
14511       else
14512         oappend ("XMMWORD PTR ");
14513       break;
14514     case xmm_mode:
14515       oappend ("XMMWORD PTR ");
14516       break;
14517     case ymm_mode:
14518       oappend ("YMMWORD PTR ");
14519       break;
14520     case xmmq_mode:
14521     case evex_half_bcst_xmmq_mode:
14522       if (!need_vex)
14523         abort ();
14524
14525       switch (vex.length)
14526         {
14527         case 128:
14528           oappend ("QWORD PTR ");
14529           break;
14530         case 256:
14531           oappend ("XMMWORD PTR ");
14532           break;
14533         case 512:
14534           oappend ("YMMWORD PTR ");
14535           break;
14536         default:
14537           abort ();
14538         }
14539       break;
14540     case xmm_mb_mode:
14541       if (!need_vex)
14542         abort ();
14543
14544       switch (vex.length)
14545         {
14546         case 128:
14547         case 256:
14548         case 512:
14549           oappend ("BYTE PTR ");
14550           break;
14551         default:
14552           abort ();
14553         }
14554       break;
14555     case xmm_mw_mode:
14556       if (!need_vex)
14557         abort ();
14558
14559       switch (vex.length)
14560         {
14561         case 128:
14562         case 256:
14563         case 512:
14564           oappend ("WORD PTR ");
14565           break;
14566         default:
14567           abort ();
14568         }
14569       break;
14570     case xmm_md_mode:
14571       if (!need_vex)
14572         abort ();
14573
14574       switch (vex.length)
14575         {
14576         case 128:
14577         case 256:
14578         case 512:
14579           oappend ("DWORD PTR ");
14580           break;
14581         default:
14582           abort ();
14583         }
14584       break;
14585     case xmm_mq_mode:
14586       if (!need_vex)
14587         abort ();
14588
14589       switch (vex.length)
14590         {
14591         case 128:
14592         case 256:
14593         case 512:
14594           oappend ("QWORD PTR ");
14595           break;
14596         default:
14597           abort ();
14598         }
14599       break;
14600     case xmmdw_mode:
14601       if (!need_vex)
14602         abort ();
14603
14604       switch (vex.length)
14605         {
14606         case 128:
14607           oappend ("WORD PTR ");
14608           break;
14609         case 256:
14610           oappend ("DWORD PTR ");
14611           break;
14612         case 512:
14613           oappend ("QWORD PTR ");
14614           break;
14615         default:
14616           abort ();
14617         }
14618       break;
14619     case xmmqd_mode:
14620       if (!need_vex)
14621         abort ();
14622
14623       switch (vex.length)
14624         {
14625         case 128:
14626           oappend ("DWORD PTR ");
14627           break;
14628         case 256:
14629           oappend ("QWORD PTR ");
14630           break;
14631         case 512:
14632           oappend ("XMMWORD PTR ");
14633           break;
14634         default:
14635           abort ();
14636         }
14637       break;
14638     case ymmq_mode:
14639       if (!need_vex)
14640         abort ();
14641
14642       switch (vex.length)
14643         {
14644         case 128:
14645           oappend ("QWORD PTR ");
14646           break;
14647         case 256:
14648           oappend ("YMMWORD PTR ");
14649           break;
14650         case 512:
14651           oappend ("ZMMWORD PTR ");
14652           break;
14653         default:
14654           abort ();
14655         }
14656       break;
14657     case ymmxmm_mode:
14658       if (!need_vex)
14659         abort ();
14660
14661       switch (vex.length)
14662         {
14663         case 128:
14664         case 256:
14665           oappend ("XMMWORD PTR ");
14666           break;
14667         default:
14668           abort ();
14669         }
14670       break;
14671     case o_mode:
14672       oappend ("OWORD PTR ");
14673       break;
14674     case xmm_mdq_mode:
14675     case vex_w_dq_mode:
14676     case vex_scalar_w_dq_mode:
14677       if (!need_vex)
14678         abort ();
14679
14680       if (vex.w)
14681         oappend ("QWORD PTR ");
14682       else
14683         oappend ("DWORD PTR ");
14684       break;
14685     case vex_vsib_d_w_dq_mode:
14686     case vex_vsib_q_w_dq_mode:
14687       if (!need_vex)
14688         abort ();
14689
14690       if (!vex.evex)
14691         {
14692           if (vex.w)
14693             oappend ("QWORD PTR ");
14694           else
14695             oappend ("DWORD PTR ");
14696         }
14697       else
14698         {
14699           switch (vex.length)
14700             {
14701             case 128:
14702               oappend ("XMMWORD PTR ");
14703               break;
14704             case 256:
14705               oappend ("YMMWORD PTR ");
14706               break;
14707             case 512:
14708               oappend ("ZMMWORD PTR ");
14709               break;
14710             default:
14711               abort ();
14712             }
14713         }
14714       break;
14715     case vex_vsib_q_w_d_mode:
14716     case vex_vsib_d_w_d_mode:
14717       if (!need_vex || !vex.evex)
14718         abort ();
14719
14720       switch (vex.length)
14721         {
14722         case 128:
14723           oappend ("QWORD PTR ");
14724           break;
14725         case 256:
14726           oappend ("XMMWORD PTR ");
14727           break;
14728         case 512:
14729           oappend ("YMMWORD PTR ");
14730           break;
14731         default:
14732           abort ();
14733         }
14734
14735       break;
14736     case mask_bd_mode:
14737       if (!need_vex || vex.length != 128)
14738         abort ();
14739       if (vex.w)
14740         oappend ("DWORD PTR ");
14741       else
14742         oappend ("BYTE PTR ");
14743       break;
14744     case mask_mode:
14745       if (!need_vex)
14746         abort ();
14747       if (vex.w)
14748         oappend ("QWORD PTR ");
14749       else
14750         oappend ("WORD PTR ");
14751       break;
14752     case v_bnd_mode:
14753     default:
14754       break;
14755     }
14756 }
14757
14758 static void
14759 OP_E_register (int bytemode, int sizeflag)
14760 {
14761   int reg = modrm.rm;
14762   const char **names;
14763
14764   USED_REX (REX_B);
14765   if ((rex & REX_B))
14766     reg += 8;
14767
14768   if ((sizeflag & SUFFIX_ALWAYS)
14769       && (bytemode == b_swap_mode
14770           || bytemode == v_swap_mode
14771           || bytemode == dqw_swap_mode))
14772     swap_operand ();
14773
14774   switch (bytemode)
14775     {
14776     case b_mode:
14777     case b_swap_mode:
14778       USED_REX (0);
14779       if (rex)
14780         names = names8rex;
14781       else
14782         names = names8;
14783       break;
14784     case w_mode:
14785       names = names16;
14786       break;
14787     case d_mode:
14788     case dw_mode:
14789     case db_mode:
14790       names = names32;
14791       break;
14792     case q_mode:
14793       names = names64;
14794       break;
14795     case m_mode:
14796     case v_bnd_mode:
14797       names = address_mode == mode_64bit ? names64 : names32;
14798       break;
14799     case bnd_mode:
14800       names = names_bnd;
14801       break;
14802     case stack_v_mode:
14803       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14804         {
14805           names = names64;
14806           break;
14807         }
14808       bytemode = v_mode;
14809       /* FALLTHRU */
14810     case v_mode:
14811     case v_swap_mode:
14812     case dq_mode:
14813     case dqb_mode:
14814     case dqd_mode:
14815     case dqw_mode:
14816     case dqw_swap_mode:
14817       USED_REX (REX_W);
14818       if (rex & REX_W)
14819         names = names64;
14820       else
14821         {
14822           if ((sizeflag & DFLAG)
14823               || (bytemode != v_mode
14824                   && bytemode != v_swap_mode))
14825             names = names32;
14826           else
14827             names = names16;
14828           used_prefixes |= (prefixes & PREFIX_DATA);
14829         }
14830       break;
14831     case mask_bd_mode:
14832     case mask_mode:
14833       names = names_mask;
14834       break;
14835     case 0:
14836       return;
14837     default:
14838       oappend (INTERNAL_DISASSEMBLER_ERROR);
14839       return;
14840     }
14841   oappend (names[reg]);
14842 }
14843
14844 static void
14845 OP_E_memory (int bytemode, int sizeflag)
14846 {
14847   bfd_vma disp = 0;
14848   int add = (rex & REX_B) ? 8 : 0;
14849   int riprel = 0;
14850   int shift;
14851
14852   if (vex.evex)
14853     {
14854       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14855       if (vex.b
14856           && bytemode != x_mode
14857           && bytemode != xmmq_mode
14858           && bytemode != evex_half_bcst_xmmq_mode)
14859         {
14860           BadOp ();
14861           return;
14862         }
14863       switch (bytemode)
14864         {
14865         case dqw_mode:
14866         case dw_mode:
14867         case dqw_swap_mode:
14868           shift = 1;
14869           break;
14870         case dqb_mode:
14871         case db_mode:
14872           shift = 0;
14873           break;
14874         case vex_vsib_d_w_dq_mode:
14875         case vex_vsib_d_w_d_mode:
14876         case vex_vsib_q_w_dq_mode:
14877         case vex_vsib_q_w_d_mode:
14878         case evex_x_gscat_mode:
14879         case xmm_mdq_mode:
14880           shift = vex.w ? 3 : 2;
14881           break;
14882         case x_mode:
14883         case evex_half_bcst_xmmq_mode:
14884         case xmmq_mode:
14885           if (vex.b)
14886             {
14887               shift = vex.w ? 3 : 2;
14888               break;
14889             }
14890           /* Fall through if vex.b == 0.  */
14891         case xmmqd_mode:
14892         case xmmdw_mode:
14893         case ymmq_mode:
14894         case evex_x_nobcst_mode:
14895         case x_swap_mode:
14896           switch (vex.length)
14897             {
14898             case 128:
14899               shift = 4;
14900               break;
14901             case 256:
14902               shift = 5;
14903               break;
14904             case 512:
14905               shift = 6;
14906               break;
14907             default:
14908               abort ();
14909             }
14910           break;
14911         case ymm_mode:
14912           shift = 5;
14913           break;
14914         case xmm_mode:
14915           shift = 4;
14916           break;
14917         case xmm_mq_mode:
14918         case q_mode:
14919         case q_scalar_mode:
14920         case q_swap_mode:
14921         case q_scalar_swap_mode:
14922           shift = 3;
14923           break;
14924         case dqd_mode:
14925         case xmm_md_mode:
14926         case d_mode:
14927         case d_scalar_mode:
14928         case d_swap_mode:
14929         case d_scalar_swap_mode:
14930           shift = 2;
14931           break;
14932         case xmm_mw_mode:
14933           shift = 1;
14934           break;
14935         case xmm_mb_mode:
14936           shift = 0;
14937           break;
14938         default:
14939           abort ();
14940         }
14941       /* Make necessary corrections to shift for modes that need it.
14942          For these modes we currently have shift 4, 5 or 6 depending on
14943          vex.length (it corresponds to xmmword, ymmword or zmmword
14944          operand).  We might want to make it 3, 4 or 5 (e.g. for
14945          xmmq_mode).  In case of broadcast enabled the corrections
14946          aren't needed, as element size is always 32 or 64 bits.  */
14947       if (!vex.b
14948           && (bytemode == xmmq_mode
14949               || bytemode == evex_half_bcst_xmmq_mode))
14950         shift -= 1;
14951       else if (bytemode == xmmqd_mode)
14952         shift -= 2;
14953       else if (bytemode == xmmdw_mode)
14954         shift -= 3;
14955       else if (bytemode == ymmq_mode && vex.length == 128)
14956         shift -= 1;
14957     }
14958   else
14959     shift = 0;
14960
14961   USED_REX (REX_B);
14962   if (intel_syntax)
14963     intel_operand_size (bytemode, sizeflag);
14964   append_seg ();
14965
14966   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14967     {
14968       /* 32/64 bit address mode */
14969       int havedisp;
14970       int havesib;
14971       int havebase;
14972       int haveindex;
14973       int needindex;
14974       int base, rbase;
14975       int vindex = 0;
14976       int scale = 0;
14977       int addr32flag = !((sizeflag & AFLAG)
14978                          || bytemode == v_bnd_mode
14979                          || bytemode == bnd_mode);
14980       const char **indexes64 = names64;
14981       const char **indexes32 = names32;
14982
14983       havesib = 0;
14984       havebase = 1;
14985       haveindex = 0;
14986       base = modrm.rm;
14987
14988       if (base == 4)
14989         {
14990           havesib = 1;
14991           vindex = sib.index;
14992           USED_REX (REX_X);
14993           if (rex & REX_X)
14994             vindex += 8;
14995           switch (bytemode)
14996             {
14997             case vex_vsib_d_w_dq_mode:
14998             case vex_vsib_d_w_d_mode:
14999             case vex_vsib_q_w_dq_mode:
15000             case vex_vsib_q_w_d_mode:
15001               if (!need_vex)
15002                 abort ();
15003               if (vex.evex)
15004                 {
15005                   if (!vex.v)
15006                     vindex += 16;
15007                 }
15008
15009               haveindex = 1;
15010               switch (vex.length)
15011                 {
15012                 case 128:
15013                   indexes64 = indexes32 = names_xmm;
15014                   break;
15015                 case 256:
15016                   if (!vex.w
15017                       || bytemode == vex_vsib_q_w_dq_mode
15018                       || bytemode == vex_vsib_q_w_d_mode)
15019                     indexes64 = indexes32 = names_ymm;
15020                   else
15021                     indexes64 = indexes32 = names_xmm;
15022                   break;
15023                 case 512:
15024                   if (!vex.w
15025                       || bytemode == vex_vsib_q_w_dq_mode
15026                       || bytemode == vex_vsib_q_w_d_mode)
15027                     indexes64 = indexes32 = names_zmm;
15028                   else
15029                     indexes64 = indexes32 = names_ymm;
15030                   break;
15031                 default:
15032                   abort ();
15033                 }
15034               break;
15035             default:
15036               haveindex = vindex != 4;
15037               break;
15038             }
15039           scale = sib.scale;
15040           base = sib.base;
15041           codep++;
15042         }
15043       rbase = base + add;
15044
15045       switch (modrm.mod)
15046         {
15047         case 0:
15048           if (base == 5)
15049             {
15050               havebase = 0;
15051               if (address_mode == mode_64bit && !havesib)
15052                 riprel = 1;
15053               disp = get32s ();
15054             }
15055           break;
15056         case 1:
15057           FETCH_DATA (the_info, codep + 1);
15058           disp = *codep++;
15059           if ((disp & 0x80) != 0)
15060             disp -= 0x100;
15061           if (vex.evex && shift > 0)
15062             disp <<= shift;
15063           break;
15064         case 2:
15065           disp = get32s ();
15066           break;
15067         }
15068
15069       /* In 32bit mode, we need index register to tell [offset] from
15070          [eiz*1 + offset].  */
15071       needindex = (havesib
15072                    && !havebase
15073                    && !haveindex
15074                    && address_mode == mode_32bit);
15075       havedisp = (havebase
15076                   || needindex
15077                   || (havesib && (haveindex || scale != 0)));
15078
15079       if (!intel_syntax)
15080         if (modrm.mod != 0 || base == 5)
15081           {
15082             if (havedisp || riprel)
15083               print_displacement (scratchbuf, disp);
15084             else
15085               print_operand_value (scratchbuf, 1, disp);
15086             oappend (scratchbuf);
15087             if (riprel)
15088               {
15089                 set_op (disp, 1);
15090                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
15091               }
15092           }
15093
15094       if ((havebase || haveindex || riprel)
15095           && (bytemode != v_bnd_mode)
15096           && (bytemode != bnd_mode))
15097         used_prefixes |= PREFIX_ADDR;
15098
15099       if (havedisp || (intel_syntax && riprel))
15100         {
15101           *obufp++ = open_char;
15102           if (intel_syntax && riprel)
15103             {
15104               set_op (disp, 1);
15105               oappend (sizeflag & AFLAG ? "rip" : "eip");
15106             }
15107           *obufp = '\0';
15108           if (havebase)
15109             oappend (address_mode == mode_64bit && !addr32flag
15110                      ? names64[rbase] : names32[rbase]);
15111           if (havesib)
15112             {
15113               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15114                  print index to tell base + index from base.  */
15115               if (scale != 0
15116                   || needindex
15117                   || haveindex
15118                   || (havebase && base != ESP_REG_NUM))
15119                 {
15120                   if (!intel_syntax || havebase)
15121                     {
15122                       *obufp++ = separator_char;
15123                       *obufp = '\0';
15124                     }
15125                   if (haveindex)
15126                     oappend (address_mode == mode_64bit && !addr32flag
15127                              ? indexes64[vindex] : indexes32[vindex]);
15128                   else
15129                     oappend (address_mode == mode_64bit && !addr32flag
15130                              ? index64 : index32);
15131
15132                   *obufp++ = scale_char;
15133                   *obufp = '\0';
15134                   sprintf (scratchbuf, "%d", 1 << scale);
15135                   oappend (scratchbuf);
15136                 }
15137             }
15138           if (intel_syntax
15139               && (disp || modrm.mod != 0 || base == 5))
15140             {
15141               if (!havedisp || (bfd_signed_vma) disp >= 0)
15142                 {
15143                   *obufp++ = '+';
15144                   *obufp = '\0';
15145                 }
15146               else if (modrm.mod != 1 && disp != -disp)
15147                 {
15148                   *obufp++ = '-';
15149                   *obufp = '\0';
15150                   disp = - (bfd_signed_vma) disp;
15151                 }
15152
15153               if (havedisp)
15154                 print_displacement (scratchbuf, disp);
15155               else
15156                 print_operand_value (scratchbuf, 1, disp);
15157               oappend (scratchbuf);
15158             }
15159
15160           *obufp++ = close_char;
15161           *obufp = '\0';
15162         }
15163       else if (intel_syntax)
15164         {
15165           if (modrm.mod != 0 || base == 5)
15166             {
15167               if (!active_seg_prefix)
15168                 {
15169                   oappend (names_seg[ds_reg - es_reg]);
15170                   oappend (":");
15171                 }
15172               print_operand_value (scratchbuf, 1, disp);
15173               oappend (scratchbuf);
15174             }
15175         }
15176     }
15177   else
15178     {
15179       /* 16 bit address mode */
15180       used_prefixes |= prefixes & PREFIX_ADDR;
15181       switch (modrm.mod)
15182         {
15183         case 0:
15184           if (modrm.rm == 6)
15185             {
15186               disp = get16 ();
15187               if ((disp & 0x8000) != 0)
15188                 disp -= 0x10000;
15189             }
15190           break;
15191         case 1:
15192           FETCH_DATA (the_info, codep + 1);
15193           disp = *codep++;
15194           if ((disp & 0x80) != 0)
15195             disp -= 0x100;
15196           break;
15197         case 2:
15198           disp = get16 ();
15199           if ((disp & 0x8000) != 0)
15200             disp -= 0x10000;
15201           break;
15202         }
15203
15204       if (!intel_syntax)
15205         if (modrm.mod != 0 || modrm.rm == 6)
15206           {
15207             print_displacement (scratchbuf, disp);
15208             oappend (scratchbuf);
15209           }
15210
15211       if (modrm.mod != 0 || modrm.rm != 6)
15212         {
15213           *obufp++ = open_char;
15214           *obufp = '\0';
15215           oappend (index16[modrm.rm]);
15216           if (intel_syntax
15217               && (disp || modrm.mod != 0 || modrm.rm == 6))
15218             {
15219               if ((bfd_signed_vma) disp >= 0)
15220                 {
15221                   *obufp++ = '+';
15222                   *obufp = '\0';
15223                 }
15224               else if (modrm.mod != 1)
15225                 {
15226                   *obufp++ = '-';
15227                   *obufp = '\0';
15228                   disp = - (bfd_signed_vma) disp;
15229                 }
15230
15231               print_displacement (scratchbuf, disp);
15232               oappend (scratchbuf);
15233             }
15234
15235           *obufp++ = close_char;
15236           *obufp = '\0';
15237         }
15238       else if (intel_syntax)
15239         {
15240           if (!active_seg_prefix)
15241             {
15242               oappend (names_seg[ds_reg - es_reg]);
15243               oappend (":");
15244             }
15245           print_operand_value (scratchbuf, 1, disp & 0xffff);
15246           oappend (scratchbuf);
15247         }
15248     }
15249   if (vex.evex && vex.b
15250       && (bytemode == x_mode
15251           || bytemode == xmmq_mode
15252           || bytemode == evex_half_bcst_xmmq_mode))
15253     {
15254       if (vex.w
15255           || bytemode == xmmq_mode
15256           || bytemode == evex_half_bcst_xmmq_mode)
15257         {
15258           switch (vex.length)
15259             {
15260             case 128:
15261               oappend ("{1to2}");
15262               break;
15263             case 256:
15264               oappend ("{1to4}");
15265               break;
15266             case 512:
15267               oappend ("{1to8}");
15268               break;
15269             default:
15270               abort ();
15271             }
15272         }
15273       else
15274         {
15275           switch (vex.length)
15276             {
15277             case 128:
15278               oappend ("{1to4}");
15279               break;
15280             case 256:
15281               oappend ("{1to8}");
15282               break;
15283             case 512:
15284               oappend ("{1to16}");
15285               break;
15286             default:
15287               abort ();
15288             }
15289         }
15290     }
15291 }
15292
15293 static void
15294 OP_E (int bytemode, int sizeflag)
15295 {
15296   /* Skip mod/rm byte.  */
15297   MODRM_CHECK;
15298   codep++;
15299
15300   if (modrm.mod == 3)
15301     OP_E_register (bytemode, sizeflag);
15302   else
15303     OP_E_memory (bytemode, sizeflag);
15304 }
15305
15306 static void
15307 OP_G (int bytemode, int sizeflag)
15308 {
15309   int add = 0;
15310   USED_REX (REX_R);
15311   if (rex & REX_R)
15312     add += 8;
15313   switch (bytemode)
15314     {
15315     case b_mode:
15316       USED_REX (0);
15317       if (rex)
15318         oappend (names8rex[modrm.reg + add]);
15319       else
15320         oappend (names8[modrm.reg + add]);
15321       break;
15322     case w_mode:
15323       oappend (names16[modrm.reg + add]);
15324       break;
15325     case d_mode:
15326     case db_mode:
15327     case dw_mode:
15328       oappend (names32[modrm.reg + add]);
15329       break;
15330     case q_mode:
15331       oappend (names64[modrm.reg + add]);
15332       break;
15333     case bnd_mode:
15334       oappend (names_bnd[modrm.reg]);
15335       break;
15336     case v_mode:
15337     case dq_mode:
15338     case dqb_mode:
15339     case dqd_mode:
15340     case dqw_mode:
15341     case dqw_swap_mode:
15342       USED_REX (REX_W);
15343       if (rex & REX_W)
15344         oappend (names64[modrm.reg + add]);
15345       else
15346         {
15347           if ((sizeflag & DFLAG) || bytemode != v_mode)
15348             oappend (names32[modrm.reg + add]);
15349           else
15350             oappend (names16[modrm.reg + add]);
15351           used_prefixes |= (prefixes & PREFIX_DATA);
15352         }
15353       break;
15354     case m_mode:
15355       if (address_mode == mode_64bit)
15356         oappend (names64[modrm.reg + add]);
15357       else
15358         oappend (names32[modrm.reg + add]);
15359       break;
15360     case mask_bd_mode:
15361     case mask_mode:
15362       oappend (names_mask[modrm.reg + add]);
15363       break;
15364     default:
15365       oappend (INTERNAL_DISASSEMBLER_ERROR);
15366       break;
15367     }
15368 }
15369
15370 static bfd_vma
15371 get64 (void)
15372 {
15373   bfd_vma x;
15374 #ifdef BFD64
15375   unsigned int a;
15376   unsigned int b;
15377
15378   FETCH_DATA (the_info, codep + 8);
15379   a = *codep++ & 0xff;
15380   a |= (*codep++ & 0xff) << 8;
15381   a |= (*codep++ & 0xff) << 16;
15382   a |= (*codep++ & 0xff) << 24;
15383   b = *codep++ & 0xff;
15384   b |= (*codep++ & 0xff) << 8;
15385   b |= (*codep++ & 0xff) << 16;
15386   b |= (*codep++ & 0xff) << 24;
15387   x = a + ((bfd_vma) b << 32);
15388 #else
15389   abort ();
15390   x = 0;
15391 #endif
15392   return x;
15393 }
15394
15395 static bfd_signed_vma
15396 get32 (void)
15397 {
15398   bfd_signed_vma x = 0;
15399
15400   FETCH_DATA (the_info, codep + 4);
15401   x = *codep++ & (bfd_signed_vma) 0xff;
15402   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15403   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15404   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15405   return x;
15406 }
15407
15408 static bfd_signed_vma
15409 get32s (void)
15410 {
15411   bfd_signed_vma x = 0;
15412
15413   FETCH_DATA (the_info, codep + 4);
15414   x = *codep++ & (bfd_signed_vma) 0xff;
15415   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15416   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15417   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15418
15419   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15420
15421   return x;
15422 }
15423
15424 static int
15425 get16 (void)
15426 {
15427   int x = 0;
15428
15429   FETCH_DATA (the_info, codep + 2);
15430   x = *codep++ & 0xff;
15431   x |= (*codep++ & 0xff) << 8;
15432   return x;
15433 }
15434
15435 static void
15436 set_op (bfd_vma op, int riprel)
15437 {
15438   op_index[op_ad] = op_ad;
15439   if (address_mode == mode_64bit)
15440     {
15441       op_address[op_ad] = op;
15442       op_riprel[op_ad] = riprel;
15443     }
15444   else
15445     {
15446       /* Mask to get a 32-bit address.  */
15447       op_address[op_ad] = op & 0xffffffff;
15448       op_riprel[op_ad] = riprel & 0xffffffff;
15449     }
15450 }
15451
15452 static void
15453 OP_REG (int code, int sizeflag)
15454 {
15455   const char *s;
15456   int add;
15457
15458   switch (code)
15459     {
15460     case es_reg: case ss_reg: case cs_reg:
15461     case ds_reg: case fs_reg: case gs_reg:
15462       oappend (names_seg[code - es_reg]);
15463       return;
15464     }
15465
15466   USED_REX (REX_B);
15467   if (rex & REX_B)
15468     add = 8;
15469   else
15470     add = 0;
15471
15472   switch (code)
15473     {
15474     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15475     case sp_reg: case bp_reg: case si_reg: case di_reg:
15476       s = names16[code - ax_reg + add];
15477       break;
15478     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15479     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15480       USED_REX (0);
15481       if (rex)
15482         s = names8rex[code - al_reg + add];
15483       else
15484         s = names8[code - al_reg];
15485       break;
15486     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15487     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15488       if (address_mode == mode_64bit
15489           && ((sizeflag & DFLAG) || (rex & REX_W)))
15490         {
15491           s = names64[code - rAX_reg + add];
15492           break;
15493         }
15494       code += eAX_reg - rAX_reg;
15495       /* Fall through.  */
15496     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15497     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15498       USED_REX (REX_W);
15499       if (rex & REX_W)
15500         s = names64[code - eAX_reg + add];
15501       else
15502         {
15503           if (sizeflag & DFLAG)
15504             s = names32[code - eAX_reg + add];
15505           else
15506             s = names16[code - eAX_reg + add];
15507           used_prefixes |= (prefixes & PREFIX_DATA);
15508         }
15509       break;
15510     default:
15511       s = INTERNAL_DISASSEMBLER_ERROR;
15512       break;
15513     }
15514   oappend (s);
15515 }
15516
15517 static void
15518 OP_IMREG (int code, int sizeflag)
15519 {
15520   const char *s;
15521
15522   switch (code)
15523     {
15524     case indir_dx_reg:
15525       if (intel_syntax)
15526         s = "dx";
15527       else
15528         s = "(%dx)";
15529       break;
15530     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15531     case sp_reg: case bp_reg: case si_reg: case di_reg:
15532       s = names16[code - ax_reg];
15533       break;
15534     case es_reg: case ss_reg: case cs_reg:
15535     case ds_reg: case fs_reg: case gs_reg:
15536       s = names_seg[code - es_reg];
15537       break;
15538     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15539     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15540       USED_REX (0);
15541       if (rex)
15542         s = names8rex[code - al_reg];
15543       else
15544         s = names8[code - al_reg];
15545       break;
15546     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15547     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15548       USED_REX (REX_W);
15549       if (rex & REX_W)
15550         s = names64[code - eAX_reg];
15551       else
15552         {
15553           if (sizeflag & DFLAG)
15554             s = names32[code - eAX_reg];
15555           else
15556             s = names16[code - eAX_reg];
15557           used_prefixes |= (prefixes & PREFIX_DATA);
15558         }
15559       break;
15560     case z_mode_ax_reg:
15561       if ((rex & REX_W) || (sizeflag & DFLAG))
15562         s = *names32;
15563       else
15564         s = *names16;
15565       if (!(rex & REX_W))
15566         used_prefixes |= (prefixes & PREFIX_DATA);
15567       break;
15568     default:
15569       s = INTERNAL_DISASSEMBLER_ERROR;
15570       break;
15571     }
15572   oappend (s);
15573 }
15574
15575 static void
15576 OP_I (int bytemode, int sizeflag)
15577 {
15578   bfd_signed_vma op;
15579   bfd_signed_vma mask = -1;
15580
15581   switch (bytemode)
15582     {
15583     case b_mode:
15584       FETCH_DATA (the_info, codep + 1);
15585       op = *codep++;
15586       mask = 0xff;
15587       break;
15588     case q_mode:
15589       if (address_mode == mode_64bit)
15590         {
15591           op = get32s ();
15592           break;
15593         }
15594       /* Fall through.  */
15595     case v_mode:
15596       USED_REX (REX_W);
15597       if (rex & REX_W)
15598         op = get32s ();
15599       else
15600         {
15601           if (sizeflag & DFLAG)
15602             {
15603               op = get32 ();
15604               mask = 0xffffffff;
15605             }
15606           else
15607             {
15608               op = get16 ();
15609               mask = 0xfffff;
15610             }
15611           used_prefixes |= (prefixes & PREFIX_DATA);
15612         }
15613       break;
15614     case w_mode:
15615       mask = 0xfffff;
15616       op = get16 ();
15617       break;
15618     case const_1_mode:
15619       if (intel_syntax)
15620         oappend ("1");
15621       return;
15622     default:
15623       oappend (INTERNAL_DISASSEMBLER_ERROR);
15624       return;
15625     }
15626
15627   op &= mask;
15628   scratchbuf[0] = '$';
15629   print_operand_value (scratchbuf + 1, 1, op);
15630   oappend_maybe_intel (scratchbuf);
15631   scratchbuf[0] = '\0';
15632 }
15633
15634 static void
15635 OP_I64 (int bytemode, int sizeflag)
15636 {
15637   bfd_signed_vma op;
15638   bfd_signed_vma mask = -1;
15639
15640   if (address_mode != mode_64bit)
15641     {
15642       OP_I (bytemode, sizeflag);
15643       return;
15644     }
15645
15646   switch (bytemode)
15647     {
15648     case b_mode:
15649       FETCH_DATA (the_info, codep + 1);
15650       op = *codep++;
15651       mask = 0xff;
15652       break;
15653     case v_mode:
15654       USED_REX (REX_W);
15655       if (rex & REX_W)
15656         op = get64 ();
15657       else
15658         {
15659           if (sizeflag & DFLAG)
15660             {
15661               op = get32 ();
15662               mask = 0xffffffff;
15663             }
15664           else
15665             {
15666               op = get16 ();
15667               mask = 0xfffff;
15668             }
15669           used_prefixes |= (prefixes & PREFIX_DATA);
15670         }
15671       break;
15672     case w_mode:
15673       mask = 0xfffff;
15674       op = get16 ();
15675       break;
15676     default:
15677       oappend (INTERNAL_DISASSEMBLER_ERROR);
15678       return;
15679     }
15680
15681   op &= mask;
15682   scratchbuf[0] = '$';
15683   print_operand_value (scratchbuf + 1, 1, op);
15684   oappend_maybe_intel (scratchbuf);
15685   scratchbuf[0] = '\0';
15686 }
15687
15688 static void
15689 OP_sI (int bytemode, int sizeflag)
15690 {
15691   bfd_signed_vma op;
15692
15693   switch (bytemode)
15694     {
15695     case b_mode:
15696     case b_T_mode:
15697       FETCH_DATA (the_info, codep + 1);
15698       op = *codep++;
15699       if ((op & 0x80) != 0)
15700         op -= 0x100;
15701       if (bytemode == b_T_mode)
15702         {
15703           if (address_mode != mode_64bit
15704               || !((sizeflag & DFLAG) || (rex & REX_W)))
15705             {
15706               /* The operand-size prefix is overridden by a REX prefix.  */
15707               if ((sizeflag & DFLAG) || (rex & REX_W))
15708                 op &= 0xffffffff;
15709               else
15710                 op &= 0xffff;
15711           }
15712         }
15713       else
15714         {
15715           if (!(rex & REX_W))
15716             {
15717               if (sizeflag & DFLAG)
15718                 op &= 0xffffffff;
15719               else
15720                 op &= 0xffff;
15721             }
15722         }
15723       break;
15724     case v_mode:
15725       /* The operand-size prefix is overridden by a REX prefix.  */
15726       if ((sizeflag & DFLAG) || (rex & REX_W))
15727         op = get32s ();
15728       else
15729         op = get16 ();
15730       break;
15731     default:
15732       oappend (INTERNAL_DISASSEMBLER_ERROR);
15733       return;
15734     }
15735
15736   scratchbuf[0] = '$';
15737   print_operand_value (scratchbuf + 1, 1, op);
15738   oappend_maybe_intel (scratchbuf);
15739 }
15740
15741 static void
15742 OP_J (int bytemode, int sizeflag)
15743 {
15744   bfd_vma disp;
15745   bfd_vma mask = -1;
15746   bfd_vma segment = 0;
15747
15748   switch (bytemode)
15749     {
15750     case b_mode:
15751       FETCH_DATA (the_info, codep + 1);
15752       disp = *codep++;
15753       if ((disp & 0x80) != 0)
15754         disp -= 0x100;
15755       break;
15756     case v_mode:
15757       if (isa64 == amd64)
15758         USED_REX (REX_W);
15759       if ((sizeflag & DFLAG)
15760           || (address_mode == mode_64bit
15761               && (isa64 != amd64 || (rex & REX_W))))
15762         disp = get32s ();
15763       else
15764         {
15765           disp = get16 ();
15766           if ((disp & 0x8000) != 0)
15767             disp -= 0x10000;
15768           /* In 16bit mode, address is wrapped around at 64k within
15769              the same segment.  Otherwise, a data16 prefix on a jump
15770              instruction means that the pc is masked to 16 bits after
15771              the displacement is added!  */
15772           mask = 0xffff;
15773           if ((prefixes & PREFIX_DATA) == 0)
15774             segment = ((start_pc + codep - start_codep)
15775                        & ~((bfd_vma) 0xffff));
15776         }
15777       if (address_mode != mode_64bit
15778           || (isa64 == amd64 && !(rex & REX_W)))
15779         used_prefixes |= (prefixes & PREFIX_DATA);
15780       break;
15781     default:
15782       oappend (INTERNAL_DISASSEMBLER_ERROR);
15783       return;
15784     }
15785   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15786   set_op (disp, 0);
15787   print_operand_value (scratchbuf, 1, disp);
15788   oappend (scratchbuf);
15789 }
15790
15791 static void
15792 OP_SEG (int bytemode, int sizeflag)
15793 {
15794   if (bytemode == w_mode)
15795     oappend (names_seg[modrm.reg]);
15796   else
15797     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15798 }
15799
15800 static void
15801 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15802 {
15803   int seg, offset;
15804
15805   if (sizeflag & DFLAG)
15806     {
15807       offset = get32 ();
15808       seg = get16 ();
15809     }
15810   else
15811     {
15812       offset = get16 ();
15813       seg = get16 ();
15814     }
15815   used_prefixes |= (prefixes & PREFIX_DATA);
15816   if (intel_syntax)
15817     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15818   else
15819     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15820   oappend (scratchbuf);
15821 }
15822
15823 static void
15824 OP_OFF (int bytemode, int sizeflag)
15825 {
15826   bfd_vma off;
15827
15828   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15829     intel_operand_size (bytemode, sizeflag);
15830   append_seg ();
15831
15832   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15833     off = get32 ();
15834   else
15835     off = get16 ();
15836
15837   if (intel_syntax)
15838     {
15839       if (!active_seg_prefix)
15840         {
15841           oappend (names_seg[ds_reg - es_reg]);
15842           oappend (":");
15843         }
15844     }
15845   print_operand_value (scratchbuf, 1, off);
15846   oappend (scratchbuf);
15847 }
15848
15849 static void
15850 OP_OFF64 (int bytemode, int sizeflag)
15851 {
15852   bfd_vma off;
15853
15854   if (address_mode != mode_64bit
15855       || (prefixes & PREFIX_ADDR))
15856     {
15857       OP_OFF (bytemode, sizeflag);
15858       return;
15859     }
15860
15861   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15862     intel_operand_size (bytemode, sizeflag);
15863   append_seg ();
15864
15865   off = get64 ();
15866
15867   if (intel_syntax)
15868     {
15869       if (!active_seg_prefix)
15870         {
15871           oappend (names_seg[ds_reg - es_reg]);
15872           oappend (":");
15873         }
15874     }
15875   print_operand_value (scratchbuf, 1, off);
15876   oappend (scratchbuf);
15877 }
15878
15879 static void
15880 ptr_reg (int code, int sizeflag)
15881 {
15882   const char *s;
15883
15884   *obufp++ = open_char;
15885   used_prefixes |= (prefixes & PREFIX_ADDR);
15886   if (address_mode == mode_64bit)
15887     {
15888       if (!(sizeflag & AFLAG))
15889         s = names32[code - eAX_reg];
15890       else
15891         s = names64[code - eAX_reg];
15892     }
15893   else if (sizeflag & AFLAG)
15894     s = names32[code - eAX_reg];
15895   else
15896     s = names16[code - eAX_reg];
15897   oappend (s);
15898   *obufp++ = close_char;
15899   *obufp = 0;
15900 }
15901
15902 static void
15903 OP_ESreg (int code, int sizeflag)
15904 {
15905   if (intel_syntax)
15906     {
15907       switch (codep[-1])
15908         {
15909         case 0x6d:      /* insw/insl */
15910           intel_operand_size (z_mode, sizeflag);
15911           break;
15912         case 0xa5:      /* movsw/movsl/movsq */
15913         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15914         case 0xab:      /* stosw/stosl */
15915         case 0xaf:      /* scasw/scasl */
15916           intel_operand_size (v_mode, sizeflag);
15917           break;
15918         default:
15919           intel_operand_size (b_mode, sizeflag);
15920         }
15921     }
15922   oappend_maybe_intel ("%es:");
15923   ptr_reg (code, sizeflag);
15924 }
15925
15926 static void
15927 OP_DSreg (int code, int sizeflag)
15928 {
15929   if (intel_syntax)
15930     {
15931       switch (codep[-1])
15932         {
15933         case 0x6f:      /* outsw/outsl */
15934           intel_operand_size (z_mode, sizeflag);
15935           break;
15936         case 0xa5:      /* movsw/movsl/movsq */
15937         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15938         case 0xad:      /* lodsw/lodsl/lodsq */
15939           intel_operand_size (v_mode, sizeflag);
15940           break;
15941         default:
15942           intel_operand_size (b_mode, sizeflag);
15943         }
15944     }
15945   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15946      default segment register DS is printed.  */
15947   if (!active_seg_prefix)
15948     active_seg_prefix = PREFIX_DS;
15949   append_seg ();
15950   ptr_reg (code, sizeflag);
15951 }
15952
15953 static void
15954 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15955 {
15956   int add;
15957   if (rex & REX_R)
15958     {
15959       USED_REX (REX_R);
15960       add = 8;
15961     }
15962   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15963     {
15964       all_prefixes[last_lock_prefix] = 0;
15965       used_prefixes |= PREFIX_LOCK;
15966       add = 8;
15967     }
15968   else
15969     add = 0;
15970   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15971   oappend_maybe_intel (scratchbuf);
15972 }
15973
15974 static void
15975 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15976 {
15977   int add;
15978   USED_REX (REX_R);
15979   if (rex & REX_R)
15980     add = 8;
15981   else
15982     add = 0;
15983   if (intel_syntax)
15984     sprintf (scratchbuf, "db%d", modrm.reg + add);
15985   else
15986     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15987   oappend (scratchbuf);
15988 }
15989
15990 static void
15991 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15992 {
15993   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15994   oappend_maybe_intel (scratchbuf);
15995 }
15996
15997 static void
15998 OP_R (int bytemode, int sizeflag)
15999 {
16000   /* Skip mod/rm byte.  */
16001   MODRM_CHECK;
16002   codep++;
16003   OP_E_register (bytemode, sizeflag);
16004 }
16005
16006 static void
16007 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16008 {
16009   int reg = modrm.reg;
16010   const char **names;
16011
16012   used_prefixes |= (prefixes & PREFIX_DATA);
16013   if (prefixes & PREFIX_DATA)
16014     {
16015       names = names_xmm;
16016       USED_REX (REX_R);
16017       if (rex & REX_R)
16018         reg += 8;
16019     }
16020   else
16021     names = names_mm;
16022   oappend (names[reg]);
16023 }
16024
16025 static void
16026 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16027 {
16028   int reg = modrm.reg;
16029   const char **names;
16030
16031   USED_REX (REX_R);
16032   if (rex & REX_R)
16033     reg += 8;
16034   if (vex.evex)
16035     {
16036       if (!vex.r)
16037         reg += 16;
16038     }
16039
16040   if (need_vex
16041       && bytemode != xmm_mode
16042       && bytemode != xmmq_mode
16043       && bytemode != evex_half_bcst_xmmq_mode
16044       && bytemode != ymm_mode
16045       && bytemode != scalar_mode)
16046     {
16047       switch (vex.length)
16048         {
16049         case 128:
16050           names = names_xmm;
16051           break;
16052         case 256:
16053           if (vex.w
16054               || (bytemode != vex_vsib_q_w_dq_mode
16055                   && bytemode != vex_vsib_q_w_d_mode))
16056             names = names_ymm;
16057           else
16058             names = names_xmm;
16059           break;
16060         case 512:
16061           names = names_zmm;
16062           break;
16063         default:
16064           abort ();
16065         }
16066     }
16067   else if (bytemode == xmmq_mode
16068            || bytemode == evex_half_bcst_xmmq_mode)
16069     {
16070       switch (vex.length)
16071         {
16072         case 128:
16073         case 256:
16074           names = names_xmm;
16075           break;
16076         case 512:
16077           names = names_ymm;
16078           break;
16079         default:
16080           abort ();
16081         }
16082     }
16083   else if (bytemode == ymm_mode)
16084     names = names_ymm;
16085   else
16086     names = names_xmm;
16087   oappend (names[reg]);
16088 }
16089
16090 static void
16091 OP_EM (int bytemode, int sizeflag)
16092 {
16093   int reg;
16094   const char **names;
16095
16096   if (modrm.mod != 3)
16097     {
16098       if (intel_syntax
16099           && (bytemode == v_mode || bytemode == v_swap_mode))
16100         {
16101           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16102           used_prefixes |= (prefixes & PREFIX_DATA);
16103         }
16104       OP_E (bytemode, sizeflag);
16105       return;
16106     }
16107
16108   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16109     swap_operand ();
16110
16111   /* Skip mod/rm byte.  */
16112   MODRM_CHECK;
16113   codep++;
16114   used_prefixes |= (prefixes & PREFIX_DATA);
16115   reg = modrm.rm;
16116   if (prefixes & PREFIX_DATA)
16117     {
16118       names = names_xmm;
16119       USED_REX (REX_B);
16120       if (rex & REX_B)
16121         reg += 8;
16122     }
16123   else
16124     names = names_mm;
16125   oappend (names[reg]);
16126 }
16127
16128 /* cvt* are the only instructions in sse2 which have
16129    both SSE and MMX operands and also have 0x66 prefix
16130    in their opcode. 0x66 was originally used to differentiate
16131    between SSE and MMX instruction(operands). So we have to handle the
16132    cvt* separately using OP_EMC and OP_MXC */
16133 static void
16134 OP_EMC (int bytemode, int sizeflag)
16135 {
16136   if (modrm.mod != 3)
16137     {
16138       if (intel_syntax && bytemode == v_mode)
16139         {
16140           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16141           used_prefixes |= (prefixes & PREFIX_DATA);
16142         }
16143       OP_E (bytemode, sizeflag);
16144       return;
16145     }
16146
16147   /* Skip mod/rm byte.  */
16148   MODRM_CHECK;
16149   codep++;
16150   used_prefixes |= (prefixes & PREFIX_DATA);
16151   oappend (names_mm[modrm.rm]);
16152 }
16153
16154 static void
16155 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16156 {
16157   used_prefixes |= (prefixes & PREFIX_DATA);
16158   oappend (names_mm[modrm.reg]);
16159 }
16160
16161 static void
16162 OP_EX (int bytemode, int sizeflag)
16163 {
16164   int reg;
16165   const char **names;
16166
16167   /* Skip mod/rm byte.  */
16168   MODRM_CHECK;
16169   codep++;
16170
16171   if (modrm.mod != 3)
16172     {
16173       OP_E_memory (bytemode, sizeflag);
16174       return;
16175     }
16176
16177   reg = modrm.rm;
16178   USED_REX (REX_B);
16179   if (rex & REX_B)
16180     reg += 8;
16181   if (vex.evex)
16182     {
16183       USED_REX (REX_X);
16184       if ((rex & REX_X))
16185         reg += 16;
16186     }
16187
16188   if ((sizeflag & SUFFIX_ALWAYS)
16189       && (bytemode == x_swap_mode
16190           || bytemode == d_swap_mode
16191           || bytemode == dqw_swap_mode
16192           || bytemode == d_scalar_swap_mode
16193           || bytemode == q_swap_mode
16194           || bytemode == q_scalar_swap_mode))
16195     swap_operand ();
16196
16197   if (need_vex
16198       && bytemode != xmm_mode
16199       && bytemode != xmmdw_mode
16200       && bytemode != xmmqd_mode
16201       && bytemode != xmm_mb_mode
16202       && bytemode != xmm_mw_mode
16203       && bytemode != xmm_md_mode
16204       && bytemode != xmm_mq_mode
16205       && bytemode != xmm_mdq_mode
16206       && bytemode != xmmq_mode
16207       && bytemode != evex_half_bcst_xmmq_mode
16208       && bytemode != ymm_mode
16209       && bytemode != d_scalar_mode
16210       && bytemode != d_scalar_swap_mode
16211       && bytemode != q_scalar_mode
16212       && bytemode != q_scalar_swap_mode
16213       && bytemode != vex_scalar_w_dq_mode)
16214     {
16215       switch (vex.length)
16216         {
16217         case 128:
16218           names = names_xmm;
16219           break;
16220         case 256:
16221           names = names_ymm;
16222           break;
16223         case 512:
16224           names = names_zmm;
16225           break;
16226         default:
16227           abort ();
16228         }
16229     }
16230   else if (bytemode == xmmq_mode
16231            || bytemode == evex_half_bcst_xmmq_mode)
16232     {
16233       switch (vex.length)
16234         {
16235         case 128:
16236         case 256:
16237           names = names_xmm;
16238           break;
16239         case 512:
16240           names = names_ymm;
16241           break;
16242         default:
16243           abort ();
16244         }
16245     }
16246   else if (bytemode == ymm_mode)
16247     names = names_ymm;
16248   else
16249     names = names_xmm;
16250   oappend (names[reg]);
16251 }
16252
16253 static void
16254 OP_MS (int bytemode, int sizeflag)
16255 {
16256   if (modrm.mod == 3)
16257     OP_EM (bytemode, sizeflag);
16258   else
16259     BadOp ();
16260 }
16261
16262 static void
16263 OP_XS (int bytemode, int sizeflag)
16264 {
16265   if (modrm.mod == 3)
16266     OP_EX (bytemode, sizeflag);
16267   else
16268     BadOp ();
16269 }
16270
16271 static void
16272 OP_M (int bytemode, int sizeflag)
16273 {
16274   if (modrm.mod == 3)
16275     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16276     BadOp ();
16277   else
16278     OP_E (bytemode, sizeflag);
16279 }
16280
16281 static void
16282 OP_0f07 (int bytemode, int sizeflag)
16283 {
16284   if (modrm.mod != 3 || modrm.rm != 0)
16285     BadOp ();
16286   else
16287     OP_E (bytemode, sizeflag);
16288 }
16289
16290 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16291    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16292
16293 static void
16294 NOP_Fixup1 (int bytemode, int sizeflag)
16295 {
16296   if ((prefixes & PREFIX_DATA) != 0
16297       || (rex != 0
16298           && rex != 0x48
16299           && address_mode == mode_64bit))
16300     OP_REG (bytemode, sizeflag);
16301   else
16302     strcpy (obuf, "nop");
16303 }
16304
16305 static void
16306 NOP_Fixup2 (int bytemode, int sizeflag)
16307 {
16308   if ((prefixes & PREFIX_DATA) != 0
16309       || (rex != 0
16310           && rex != 0x48
16311           && address_mode == mode_64bit))
16312     OP_IMREG (bytemode, sizeflag);
16313 }
16314
16315 static const char *const Suffix3DNow[] = {
16316 /* 00 */        NULL,           NULL,           NULL,           NULL,
16317 /* 04 */        NULL,           NULL,           NULL,           NULL,
16318 /* 08 */        NULL,           NULL,           NULL,           NULL,
16319 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16320 /* 10 */        NULL,           NULL,           NULL,           NULL,
16321 /* 14 */        NULL,           NULL,           NULL,           NULL,
16322 /* 18 */        NULL,           NULL,           NULL,           NULL,
16323 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16324 /* 20 */        NULL,           NULL,           NULL,           NULL,
16325 /* 24 */        NULL,           NULL,           NULL,           NULL,
16326 /* 28 */        NULL,           NULL,           NULL,           NULL,
16327 /* 2C */        NULL,           NULL,           NULL,           NULL,
16328 /* 30 */        NULL,           NULL,           NULL,           NULL,
16329 /* 34 */        NULL,           NULL,           NULL,           NULL,
16330 /* 38 */        NULL,           NULL,           NULL,           NULL,
16331 /* 3C */        NULL,           NULL,           NULL,           NULL,
16332 /* 40 */        NULL,           NULL,           NULL,           NULL,
16333 /* 44 */        NULL,           NULL,           NULL,           NULL,
16334 /* 48 */        NULL,           NULL,           NULL,           NULL,
16335 /* 4C */        NULL,           NULL,           NULL,           NULL,
16336 /* 50 */        NULL,           NULL,           NULL,           NULL,
16337 /* 54 */        NULL,           NULL,           NULL,           NULL,
16338 /* 58 */        NULL,           NULL,           NULL,           NULL,
16339 /* 5C */        NULL,           NULL,           NULL,           NULL,
16340 /* 60 */        NULL,           NULL,           NULL,           NULL,
16341 /* 64 */        NULL,           NULL,           NULL,           NULL,
16342 /* 68 */        NULL,           NULL,           NULL,           NULL,
16343 /* 6C */        NULL,           NULL,           NULL,           NULL,
16344 /* 70 */        NULL,           NULL,           NULL,           NULL,
16345 /* 74 */        NULL,           NULL,           NULL,           NULL,
16346 /* 78 */        NULL,           NULL,           NULL,           NULL,
16347 /* 7C */        NULL,           NULL,           NULL,           NULL,
16348 /* 80 */        NULL,           NULL,           NULL,           NULL,
16349 /* 84 */        NULL,           NULL,           NULL,           NULL,
16350 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16351 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16352 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16353 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16354 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16355 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16356 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16357 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16358 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16359 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16360 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16361 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16362 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16363 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16364 /* C0 */        NULL,           NULL,           NULL,           NULL,
16365 /* C4 */        NULL,           NULL,           NULL,           NULL,
16366 /* C8 */        NULL,           NULL,           NULL,           NULL,
16367 /* CC */        NULL,           NULL,           NULL,           NULL,
16368 /* D0 */        NULL,           NULL,           NULL,           NULL,
16369 /* D4 */        NULL,           NULL,           NULL,           NULL,
16370 /* D8 */        NULL,           NULL,           NULL,           NULL,
16371 /* DC */        NULL,           NULL,           NULL,           NULL,
16372 /* E0 */        NULL,           NULL,           NULL,           NULL,
16373 /* E4 */        NULL,           NULL,           NULL,           NULL,
16374 /* E8 */        NULL,           NULL,           NULL,           NULL,
16375 /* EC */        NULL,           NULL,           NULL,           NULL,
16376 /* F0 */        NULL,           NULL,           NULL,           NULL,
16377 /* F4 */        NULL,           NULL,           NULL,           NULL,
16378 /* F8 */        NULL,           NULL,           NULL,           NULL,
16379 /* FC */        NULL,           NULL,           NULL,           NULL,
16380 };
16381
16382 static void
16383 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16384 {
16385   const char *mnemonic;
16386
16387   FETCH_DATA (the_info, codep + 1);
16388   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16389      place where an 8-bit immediate would normally go.  ie. the last
16390      byte of the instruction.  */
16391   obufp = mnemonicendp;
16392   mnemonic = Suffix3DNow[*codep++ & 0xff];
16393   if (mnemonic)
16394     oappend (mnemonic);
16395   else
16396     {
16397       /* Since a variable sized modrm/sib chunk is between the start
16398          of the opcode (0x0f0f) and the opcode suffix, we need to do
16399          all the modrm processing first, and don't know until now that
16400          we have a bad opcode.  This necessitates some cleaning up.  */
16401       op_out[0][0] = '\0';
16402       op_out[1][0] = '\0';
16403       BadOp ();
16404     }
16405   mnemonicendp = obufp;
16406 }
16407
16408 static struct op simd_cmp_op[] =
16409 {
16410   { STRING_COMMA_LEN ("eq") },
16411   { STRING_COMMA_LEN ("lt") },
16412   { STRING_COMMA_LEN ("le") },
16413   { STRING_COMMA_LEN ("unord") },
16414   { STRING_COMMA_LEN ("neq") },
16415   { STRING_COMMA_LEN ("nlt") },
16416   { STRING_COMMA_LEN ("nle") },
16417   { STRING_COMMA_LEN ("ord") }
16418 };
16419
16420 static void
16421 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16422 {
16423   unsigned int cmp_type;
16424
16425   FETCH_DATA (the_info, codep + 1);
16426   cmp_type = *codep++ & 0xff;
16427   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16428     {
16429       char suffix [3];
16430       char *p = mnemonicendp - 2;
16431       suffix[0] = p[0];
16432       suffix[1] = p[1];
16433       suffix[2] = '\0';
16434       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16435       mnemonicendp += simd_cmp_op[cmp_type].len;
16436     }
16437   else
16438     {
16439       /* We have a reserved extension byte.  Output it directly.  */
16440       scratchbuf[0] = '$';
16441       print_operand_value (scratchbuf + 1, 1, cmp_type);
16442       oappend_maybe_intel (scratchbuf);
16443       scratchbuf[0] = '\0';
16444     }
16445 }
16446
16447 static void
16448 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16449           int sizeflag ATTRIBUTE_UNUSED)
16450 {
16451   /* mwait %eax,%ecx  */
16452   if (!intel_syntax)
16453     {
16454       const char **names = (address_mode == mode_64bit
16455                             ? names64 : names32);
16456       strcpy (op_out[0], names[0]);
16457       strcpy (op_out[1], names[1]);
16458       two_source_ops = 1;
16459     }
16460   /* Skip mod/rm byte.  */
16461   MODRM_CHECK;
16462   codep++;
16463 }
16464
16465 static void
16466 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16467             int sizeflag ATTRIBUTE_UNUSED)
16468 {
16469   /* monitor %eax,%ecx,%edx"  */
16470   if (!intel_syntax)
16471     {
16472       const char **op1_names;
16473       const char **names = (address_mode == mode_64bit
16474                             ? names64 : names32);
16475
16476       if (!(prefixes & PREFIX_ADDR))
16477         op1_names = (address_mode == mode_16bit
16478                      ? names16 : names);
16479       else
16480         {
16481           /* Remove "addr16/addr32".  */
16482           all_prefixes[last_addr_prefix] = 0;
16483           op1_names = (address_mode != mode_32bit
16484                        ? names32 : names16);
16485           used_prefixes |= PREFIX_ADDR;
16486         }
16487       strcpy (op_out[0], op1_names[0]);
16488       strcpy (op_out[1], names[1]);
16489       strcpy (op_out[2], names[2]);
16490       two_source_ops = 1;
16491     }
16492   /* Skip mod/rm byte.  */
16493   MODRM_CHECK;
16494   codep++;
16495 }
16496
16497 static void
16498 BadOp (void)
16499 {
16500   /* Throw away prefixes and 1st. opcode byte.  */
16501   codep = insn_codep + 1;
16502   oappend ("(bad)");
16503 }
16504
16505 static void
16506 REP_Fixup (int bytemode, int sizeflag)
16507 {
16508   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16509      lods and stos.  */
16510   if (prefixes & PREFIX_REPZ)
16511     all_prefixes[last_repz_prefix] = REP_PREFIX;
16512
16513   switch (bytemode)
16514     {
16515     case al_reg:
16516     case eAX_reg:
16517     case indir_dx_reg:
16518       OP_IMREG (bytemode, sizeflag);
16519       break;
16520     case eDI_reg:
16521       OP_ESreg (bytemode, sizeflag);
16522       break;
16523     case eSI_reg:
16524       OP_DSreg (bytemode, sizeflag);
16525       break;
16526     default:
16527       abort ();
16528       break;
16529     }
16530 }
16531
16532 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16533    "bnd".  */
16534
16535 static void
16536 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16537 {
16538   if (prefixes & PREFIX_REPNZ)
16539     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16540 }
16541
16542 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16543    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16544  */
16545
16546 static void
16547 HLE_Fixup1 (int bytemode, int sizeflag)
16548 {
16549   if (modrm.mod != 3
16550       && (prefixes & PREFIX_LOCK) != 0)
16551     {
16552       if (prefixes & PREFIX_REPZ)
16553         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16554       if (prefixes & PREFIX_REPNZ)
16555         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16556     }
16557
16558   OP_E (bytemode, sizeflag);
16559 }
16560
16561 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16562    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16563  */
16564
16565 static void
16566 HLE_Fixup2 (int bytemode, int sizeflag)
16567 {
16568   if (modrm.mod != 3)
16569     {
16570       if (prefixes & PREFIX_REPZ)
16571         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16572       if (prefixes & PREFIX_REPNZ)
16573         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16574     }
16575
16576   OP_E (bytemode, sizeflag);
16577 }
16578
16579 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16580    "xrelease" for memory operand.  No check for LOCK prefix.   */
16581
16582 static void
16583 HLE_Fixup3 (int bytemode, int sizeflag)
16584 {
16585   if (modrm.mod != 3
16586       && last_repz_prefix > last_repnz_prefix
16587       && (prefixes & PREFIX_REPZ) != 0)
16588     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16589
16590   OP_E (bytemode, sizeflag);
16591 }
16592
16593 static void
16594 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16595 {
16596   USED_REX (REX_W);
16597   if (rex & REX_W)
16598     {
16599       /* Change cmpxchg8b to cmpxchg16b.  */
16600       char *p = mnemonicendp - 2;
16601       mnemonicendp = stpcpy (p, "16b");
16602       bytemode = o_mode;
16603     }
16604   else if ((prefixes & PREFIX_LOCK) != 0)
16605     {
16606       if (prefixes & PREFIX_REPZ)
16607         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16608       if (prefixes & PREFIX_REPNZ)
16609         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16610     }
16611
16612   OP_M (bytemode, sizeflag);
16613 }
16614
16615 static void
16616 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16617 {
16618   const char **names;
16619
16620   if (need_vex)
16621     {
16622       switch (vex.length)
16623         {
16624         case 128:
16625           names = names_xmm;
16626           break;
16627         case 256:
16628           names = names_ymm;
16629           break;
16630         default:
16631           abort ();
16632         }
16633     }
16634   else
16635     names = names_xmm;
16636   oappend (names[reg]);
16637 }
16638
16639 static void
16640 CRC32_Fixup (int bytemode, int sizeflag)
16641 {
16642   /* Add proper suffix to "crc32".  */
16643   char *p = mnemonicendp;
16644
16645   switch (bytemode)
16646     {
16647     case b_mode:
16648       if (intel_syntax)
16649         goto skip;
16650
16651       *p++ = 'b';
16652       break;
16653     case v_mode:
16654       if (intel_syntax)
16655         goto skip;
16656
16657       USED_REX (REX_W);
16658       if (rex & REX_W)
16659         *p++ = 'q';
16660       else
16661         {
16662           if (sizeflag & DFLAG)
16663             *p++ = 'l';
16664           else
16665             *p++ = 'w';
16666           used_prefixes |= (prefixes & PREFIX_DATA);
16667         }
16668       break;
16669     default:
16670       oappend (INTERNAL_DISASSEMBLER_ERROR);
16671       break;
16672     }
16673   mnemonicendp = p;
16674   *p = '\0';
16675
16676 skip:
16677   if (modrm.mod == 3)
16678     {
16679       int add;
16680
16681       /* Skip mod/rm byte.  */
16682       MODRM_CHECK;
16683       codep++;
16684
16685       USED_REX (REX_B);
16686       add = (rex & REX_B) ? 8 : 0;
16687       if (bytemode == b_mode)
16688         {
16689           USED_REX (0);
16690           if (rex)
16691             oappend (names8rex[modrm.rm + add]);
16692           else
16693             oappend (names8[modrm.rm + add]);
16694         }
16695       else
16696         {
16697           USED_REX (REX_W);
16698           if (rex & REX_W)
16699             oappend (names64[modrm.rm + add]);
16700           else if ((prefixes & PREFIX_DATA))
16701             oappend (names16[modrm.rm + add]);
16702           else
16703             oappend (names32[modrm.rm + add]);
16704         }
16705     }
16706   else
16707     OP_E (bytemode, sizeflag);
16708 }
16709
16710 static void
16711 FXSAVE_Fixup (int bytemode, int sizeflag)
16712 {
16713   /* Add proper suffix to "fxsave" and "fxrstor".  */
16714   USED_REX (REX_W);
16715   if (rex & REX_W)
16716     {
16717       char *p = mnemonicendp;
16718       *p++ = '6';
16719       *p++ = '4';
16720       *p = '\0';
16721       mnemonicendp = p;
16722     }
16723   OP_M (bytemode, sizeflag);
16724 }
16725
16726 /* Display the destination register operand for instructions with
16727    VEX. */
16728
16729 static void
16730 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16731 {
16732   int reg;
16733   const char **names;
16734
16735   if (!need_vex)
16736     abort ();
16737
16738   if (!need_vex_reg)
16739     return;
16740
16741   reg = vex.register_specifier;
16742   if (vex.evex)
16743     {
16744       if (!vex.v)
16745         reg += 16;
16746     }
16747
16748   if (bytemode == vex_scalar_mode)
16749     {
16750       oappend (names_xmm[reg]);
16751       return;
16752     }
16753
16754   switch (vex.length)
16755     {
16756     case 128:
16757       switch (bytemode)
16758         {
16759         case vex_mode:
16760         case vex128_mode:
16761         case vex_vsib_q_w_dq_mode:
16762         case vex_vsib_q_w_d_mode:
16763           names = names_xmm;
16764           break;
16765         case dq_mode:
16766           if (vex.w)
16767             names = names64;
16768           else
16769             names = names32;
16770           break;
16771         case mask_bd_mode:
16772         case mask_mode:
16773           names = names_mask;
16774           break;
16775         default:
16776           abort ();
16777           return;
16778         }
16779       break;
16780     case 256:
16781       switch (bytemode)
16782         {
16783         case vex_mode:
16784         case vex256_mode:
16785           names = names_ymm;
16786           break;
16787         case vex_vsib_q_w_dq_mode:
16788         case vex_vsib_q_w_d_mode:
16789           names = vex.w ? names_ymm : names_xmm;
16790           break;
16791         case mask_bd_mode:
16792         case mask_mode:
16793           names = names_mask;
16794           break;
16795         default:
16796           abort ();
16797           return;
16798         }
16799       break;
16800     case 512:
16801       names = names_zmm;
16802       break;
16803     default:
16804       abort ();
16805       break;
16806     }
16807   oappend (names[reg]);
16808 }
16809
16810 /* Get the VEX immediate byte without moving codep.  */
16811
16812 static unsigned char
16813 get_vex_imm8 (int sizeflag, int opnum)
16814 {
16815   int bytes_before_imm = 0;
16816
16817   if (modrm.mod != 3)
16818     {
16819       /* There are SIB/displacement bytes.  */
16820       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16821         {
16822           /* 32/64 bit address mode */
16823           int base = modrm.rm;
16824
16825           /* Check SIB byte.  */
16826           if (base == 4)
16827             {
16828               FETCH_DATA (the_info, codep + 1);
16829               base = *codep & 7;
16830               /* When decoding the third source, don't increase
16831                  bytes_before_imm as this has already been incremented
16832                  by one in OP_E_memory while decoding the second
16833                  source operand.  */
16834               if (opnum == 0)
16835                 bytes_before_imm++;
16836             }
16837
16838           /* Don't increase bytes_before_imm when decoding the third source,
16839              it has already been incremented by OP_E_memory while decoding
16840              the second source operand.  */
16841           if (opnum == 0)
16842             {
16843               switch (modrm.mod)
16844                 {
16845                   case 0:
16846                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16847                        SIB == 5, there is a 4 byte displacement.  */
16848                     if (base != 5)
16849                       /* No displacement. */
16850                       break;
16851                   case 2:
16852                     /* 4 byte displacement.  */
16853                     bytes_before_imm += 4;
16854                     break;
16855                   case 1:
16856                     /* 1 byte displacement.  */
16857                     bytes_before_imm++;
16858                     break;
16859                 }
16860             }
16861         }
16862       else
16863         {
16864           /* 16 bit address mode */
16865           /* Don't increase bytes_before_imm when decoding the third source,
16866              it has already been incremented by OP_E_memory while decoding
16867              the second source operand.  */
16868           if (opnum == 0)
16869             {
16870               switch (modrm.mod)
16871                 {
16872                 case 0:
16873                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16874                   if (modrm.rm != 6)
16875                     /* No displacement. */
16876                     break;
16877                 case 2:
16878                   /* 2 byte displacement.  */
16879                   bytes_before_imm += 2;
16880                   break;
16881                 case 1:
16882                   /* 1 byte displacement: when decoding the third source,
16883                      don't increase bytes_before_imm as this has already
16884                      been incremented by one in OP_E_memory while decoding
16885                      the second source operand.  */
16886                   if (opnum == 0)
16887                     bytes_before_imm++;
16888
16889                   break;
16890                 }
16891             }
16892         }
16893     }
16894
16895   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16896   return codep [bytes_before_imm];
16897 }
16898
16899 static void
16900 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16901 {
16902   const char **names;
16903
16904   if (reg == -1 && modrm.mod != 3)
16905     {
16906       OP_E_memory (bytemode, sizeflag);
16907       return;
16908     }
16909   else
16910     {
16911       if (reg == -1)
16912         {
16913           reg = modrm.rm;
16914           USED_REX (REX_B);
16915           if (rex & REX_B)
16916             reg += 8;
16917         }
16918       else if (reg > 7 && address_mode != mode_64bit)
16919         BadOp ();
16920     }
16921
16922   switch (vex.length)
16923     {
16924     case 128:
16925       names = names_xmm;
16926       break;
16927     case 256:
16928       names = names_ymm;
16929       break;
16930     default:
16931       abort ();
16932     }
16933   oappend (names[reg]);
16934 }
16935
16936 static void
16937 OP_EX_VexImmW (int bytemode, int sizeflag)
16938 {
16939   int reg = -1;
16940   static unsigned char vex_imm8;
16941
16942   if (vex_w_done == 0)
16943     {
16944       vex_w_done = 1;
16945
16946       /* Skip mod/rm byte.  */
16947       MODRM_CHECK;
16948       codep++;
16949
16950       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16951
16952       if (vex.w)
16953           reg = vex_imm8 >> 4;
16954
16955       OP_EX_VexReg (bytemode, sizeflag, reg);
16956     }
16957   else if (vex_w_done == 1)
16958     {
16959       vex_w_done = 2;
16960
16961       if (!vex.w)
16962           reg = vex_imm8 >> 4;
16963
16964       OP_EX_VexReg (bytemode, sizeflag, reg);
16965     }
16966   else
16967     {
16968       /* Output the imm8 directly.  */
16969       scratchbuf[0] = '$';
16970       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16971       oappend_maybe_intel (scratchbuf);
16972       scratchbuf[0] = '\0';
16973       codep++;
16974     }
16975 }
16976
16977 static void
16978 OP_Vex_2src (int bytemode, int sizeflag)
16979 {
16980   if (modrm.mod == 3)
16981     {
16982       int reg = modrm.rm;
16983       USED_REX (REX_B);
16984       if (rex & REX_B)
16985         reg += 8;
16986       oappend (names_xmm[reg]);
16987     }
16988   else
16989     {
16990       if (intel_syntax
16991           && (bytemode == v_mode || bytemode == v_swap_mode))
16992         {
16993           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16994           used_prefixes |= (prefixes & PREFIX_DATA);
16995         }
16996       OP_E (bytemode, sizeflag);
16997     }
16998 }
16999
17000 static void
17001 OP_Vex_2src_1 (int bytemode, int sizeflag)
17002 {
17003   if (modrm.mod == 3)
17004     {
17005       /* Skip mod/rm byte.   */
17006       MODRM_CHECK;
17007       codep++;
17008     }
17009
17010   if (vex.w)
17011     oappend (names_xmm[vex.register_specifier]);
17012   else
17013     OP_Vex_2src (bytemode, sizeflag);
17014 }
17015
17016 static void
17017 OP_Vex_2src_2 (int bytemode, int sizeflag)
17018 {
17019   if (vex.w)
17020     OP_Vex_2src (bytemode, sizeflag);
17021   else
17022     oappend (names_xmm[vex.register_specifier]);
17023 }
17024
17025 static void
17026 OP_EX_VexW (int bytemode, int sizeflag)
17027 {
17028   int reg = -1;
17029
17030   if (!vex_w_done)
17031     {
17032       vex_w_done = 1;
17033
17034       /* Skip mod/rm byte.  */
17035       MODRM_CHECK;
17036       codep++;
17037
17038       if (vex.w)
17039         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17040     }
17041   else
17042     {
17043       if (!vex.w)
17044         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17045     }
17046
17047   OP_EX_VexReg (bytemode, sizeflag, reg);
17048 }
17049
17050 static void
17051 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17052              int sizeflag ATTRIBUTE_UNUSED)
17053 {
17054   /* Skip the immediate byte and check for invalid bits.  */
17055   FETCH_DATA (the_info, codep + 1);
17056   if (*codep++ & 0xf)
17057     BadOp ();
17058 }
17059
17060 static void
17061 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17062 {
17063   int reg;
17064   const char **names;
17065
17066   FETCH_DATA (the_info, codep + 1);
17067   reg = *codep++;
17068
17069   if (bytemode != x_mode)
17070     abort ();
17071
17072   if (reg & 0xf)
17073       BadOp ();
17074
17075   reg >>= 4;
17076   if (reg > 7 && address_mode != mode_64bit)
17077     BadOp ();
17078
17079   switch (vex.length)
17080     {
17081     case 128:
17082       names = names_xmm;
17083       break;
17084     case 256:
17085       names = names_ymm;
17086       break;
17087     default:
17088       abort ();
17089     }
17090   oappend (names[reg]);
17091 }
17092
17093 static void
17094 OP_XMM_VexW (int bytemode, int sizeflag)
17095 {
17096   /* Turn off the REX.W bit since it is used for swapping operands
17097      now.  */
17098   rex &= ~REX_W;
17099   OP_XMM (bytemode, sizeflag);
17100 }
17101
17102 static void
17103 OP_EX_Vex (int bytemode, int sizeflag)
17104 {
17105   if (modrm.mod != 3)
17106     {
17107       if (vex.register_specifier != 0)
17108         BadOp ();
17109       need_vex_reg = 0;
17110     }
17111   OP_EX (bytemode, sizeflag);
17112 }
17113
17114 static void
17115 OP_XMM_Vex (int bytemode, int sizeflag)
17116 {
17117   if (modrm.mod != 3)
17118     {
17119       if (vex.register_specifier != 0)
17120         BadOp ();
17121       need_vex_reg = 0;
17122     }
17123   OP_XMM (bytemode, sizeflag);
17124 }
17125
17126 static void
17127 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17128 {
17129   switch (vex.length)
17130     {
17131     case 128:
17132       mnemonicendp = stpcpy (obuf, "vzeroupper");
17133       break;
17134     case 256:
17135       mnemonicendp = stpcpy (obuf, "vzeroall");
17136       break;
17137     default:
17138       abort ();
17139     }
17140 }
17141
17142 static struct op vex_cmp_op[] =
17143 {
17144   { STRING_COMMA_LEN ("eq") },
17145   { STRING_COMMA_LEN ("lt") },
17146   { STRING_COMMA_LEN ("le") },
17147   { STRING_COMMA_LEN ("unord") },
17148   { STRING_COMMA_LEN ("neq") },
17149   { STRING_COMMA_LEN ("nlt") },
17150   { STRING_COMMA_LEN ("nle") },
17151   { STRING_COMMA_LEN ("ord") },
17152   { STRING_COMMA_LEN ("eq_uq") },
17153   { STRING_COMMA_LEN ("nge") },
17154   { STRING_COMMA_LEN ("ngt") },
17155   { STRING_COMMA_LEN ("false") },
17156   { STRING_COMMA_LEN ("neq_oq") },
17157   { STRING_COMMA_LEN ("ge") },
17158   { STRING_COMMA_LEN ("gt") },
17159   { STRING_COMMA_LEN ("true") },
17160   { STRING_COMMA_LEN ("eq_os") },
17161   { STRING_COMMA_LEN ("lt_oq") },
17162   { STRING_COMMA_LEN ("le_oq") },
17163   { STRING_COMMA_LEN ("unord_s") },
17164   { STRING_COMMA_LEN ("neq_us") },
17165   { STRING_COMMA_LEN ("nlt_uq") },
17166   { STRING_COMMA_LEN ("nle_uq") },
17167   { STRING_COMMA_LEN ("ord_s") },
17168   { STRING_COMMA_LEN ("eq_us") },
17169   { STRING_COMMA_LEN ("nge_uq") },
17170   { STRING_COMMA_LEN ("ngt_uq") },
17171   { STRING_COMMA_LEN ("false_os") },
17172   { STRING_COMMA_LEN ("neq_os") },
17173   { STRING_COMMA_LEN ("ge_oq") },
17174   { STRING_COMMA_LEN ("gt_oq") },
17175   { STRING_COMMA_LEN ("true_us") },
17176 };
17177
17178 static void
17179 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17180 {
17181   unsigned int cmp_type;
17182
17183   FETCH_DATA (the_info, codep + 1);
17184   cmp_type = *codep++ & 0xff;
17185   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17186     {
17187       char suffix [3];
17188       char *p = mnemonicendp - 2;
17189       suffix[0] = p[0];
17190       suffix[1] = p[1];
17191       suffix[2] = '\0';
17192       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17193       mnemonicendp += vex_cmp_op[cmp_type].len;
17194     }
17195   else
17196     {
17197       /* We have a reserved extension byte.  Output it directly.  */
17198       scratchbuf[0] = '$';
17199       print_operand_value (scratchbuf + 1, 1, cmp_type);
17200       oappend_maybe_intel (scratchbuf);
17201       scratchbuf[0] = '\0';
17202     }
17203 }
17204
17205 static void
17206 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17207              int sizeflag ATTRIBUTE_UNUSED)
17208 {
17209   unsigned int cmp_type;
17210
17211   if (!vex.evex)
17212     abort ();
17213
17214   FETCH_DATA (the_info, codep + 1);
17215   cmp_type = *codep++ & 0xff;
17216   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17217      If it's the case, print suffix, otherwise - print the immediate.  */
17218   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17219       && cmp_type != 3
17220       && cmp_type != 7)
17221     {
17222       char suffix [3];
17223       char *p = mnemonicendp - 2;
17224
17225       /* vpcmp* can have both one- and two-lettered suffix.  */
17226       if (p[0] == 'p')
17227         {
17228           p++;
17229           suffix[0] = p[0];
17230           suffix[1] = '\0';
17231         }
17232       else
17233         {
17234           suffix[0] = p[0];
17235           suffix[1] = p[1];
17236           suffix[2] = '\0';
17237         }
17238
17239       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17240       mnemonicendp += simd_cmp_op[cmp_type].len;
17241     }
17242   else
17243     {
17244       /* We have a reserved extension byte.  Output it directly.  */
17245       scratchbuf[0] = '$';
17246       print_operand_value (scratchbuf + 1, 1, cmp_type);
17247       oappend_maybe_intel (scratchbuf);
17248       scratchbuf[0] = '\0';
17249     }
17250 }
17251
17252 static const struct op pclmul_op[] =
17253 {
17254   { STRING_COMMA_LEN ("lql") },
17255   { STRING_COMMA_LEN ("hql") },
17256   { STRING_COMMA_LEN ("lqh") },
17257   { STRING_COMMA_LEN ("hqh") }
17258 };
17259
17260 static void
17261 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17262               int sizeflag ATTRIBUTE_UNUSED)
17263 {
17264   unsigned int pclmul_type;
17265
17266   FETCH_DATA (the_info, codep + 1);
17267   pclmul_type = *codep++ & 0xff;
17268   switch (pclmul_type)
17269     {
17270     case 0x10:
17271       pclmul_type = 2;
17272       break;
17273     case 0x11:
17274       pclmul_type = 3;
17275       break;
17276     default:
17277       break;
17278     }
17279   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17280     {
17281       char suffix [4];
17282       char *p = mnemonicendp - 3;
17283       suffix[0] = p[0];
17284       suffix[1] = p[1];
17285       suffix[2] = p[2];
17286       suffix[3] = '\0';
17287       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17288       mnemonicendp += pclmul_op[pclmul_type].len;
17289     }
17290   else
17291     {
17292       /* We have a reserved extension byte.  Output it directly.  */
17293       scratchbuf[0] = '$';
17294       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17295       oappend_maybe_intel (scratchbuf);
17296       scratchbuf[0] = '\0';
17297     }
17298 }
17299
17300 static void
17301 MOVBE_Fixup (int bytemode, int sizeflag)
17302 {
17303   /* Add proper suffix to "movbe".  */
17304   char *p = mnemonicendp;
17305
17306   switch (bytemode)
17307     {
17308     case v_mode:
17309       if (intel_syntax)
17310         goto skip;
17311
17312       USED_REX (REX_W);
17313       if (sizeflag & SUFFIX_ALWAYS)
17314         {
17315           if (rex & REX_W)
17316             *p++ = 'q';
17317           else
17318             {
17319               if (sizeflag & DFLAG)
17320                 *p++ = 'l';
17321               else
17322                 *p++ = 'w';
17323               used_prefixes |= (prefixes & PREFIX_DATA);
17324             }
17325         }
17326       break;
17327     default:
17328       oappend (INTERNAL_DISASSEMBLER_ERROR);
17329       break;
17330     }
17331   mnemonicendp = p;
17332   *p = '\0';
17333
17334 skip:
17335   OP_M (bytemode, sizeflag);
17336 }
17337
17338 static void
17339 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17340 {
17341   int reg;
17342   const char **names;
17343
17344   /* Skip mod/rm byte.  */
17345   MODRM_CHECK;
17346   codep++;
17347
17348   if (vex.w)
17349     names = names64;
17350   else
17351     names = names32;
17352
17353   reg = modrm.rm;
17354   USED_REX (REX_B);
17355   if (rex & REX_B)
17356     reg += 8;
17357
17358   oappend (names[reg]);
17359 }
17360
17361 static void
17362 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17363 {
17364   const char **names;
17365
17366   if (vex.w)
17367     names = names64;
17368   else
17369     names = names32;
17370
17371   oappend (names[vex.register_specifier]);
17372 }
17373
17374 static void
17375 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17376 {
17377   if (!vex.evex
17378       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17379     abort ();
17380
17381   USED_REX (REX_R);
17382   if ((rex & REX_R) != 0 || !vex.r)
17383     {
17384       BadOp ();
17385       return;
17386     }
17387
17388   oappend (names_mask [modrm.reg]);
17389 }
17390
17391 static void
17392 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17393 {
17394   if (!vex.evex
17395       || (bytemode != evex_rounding_mode
17396           && bytemode != evex_sae_mode))
17397     abort ();
17398   if (modrm.mod == 3 && vex.b)
17399     switch (bytemode)
17400       {
17401       case evex_rounding_mode:
17402         oappend (names_rounding[vex.ll]);
17403         break;
17404       case evex_sae_mode:
17405         oappend ("{sae}");
17406         break;
17407       default:
17408         break;
17409       }
17410 }