opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int fetch_data (struct disassemble_info *, bfd_byte *);
  46 static void ckprefix (void);
  47 static const char *prefix_name (int, int);
  48 static int print_insn (bfd_vma, disassemble_info *);
  49 static void dofloat (int);
  50 static void OP_ST (int, int);
  51 static void OP_STi (int, int);
  52 static int putop (const char *, int);
  53 static void oappend (const char *);
  54 static void append_seg (void);
  55 static void OP_indirE (int, int);
  56 static void print_operand_value (char *, int, bfd_vma);
  57 static void OP_E_register (int, int);
  58 static void OP_E_memory (int, int);
  59 static void OP_E_extended (int, int);
  60 static void print_displacement (char *, bfd_vma);
  61 static void OP_E (int, int);
  62 static void OP_G (int, int);
  63 static bfd_vma get64 (void);
  64 static bfd_signed_vma get32 (void);
  65 static bfd_signed_vma get32s (void);
  66 static int get16 (void);
  67 static void set_op (bfd_vma, int);
  68 static void OP_Skip_MODRM (int, int);
  69 static void OP_REG (int, int);
  70 static void OP_IMREG (int, int);
  71 static void OP_I (int, int);
  72 static void OP_I64 (int, int);
  73 static void OP_sI (int, int);
  74 static void OP_J (int, int);
  75 static void OP_SEG (int, int);
  76 static void OP_DIR (int, int);
  77 static void OP_OFF (int, int);
  78 static void OP_OFF64 (int, int);
  79 static void ptr_reg (int, int);
  80 static void OP_ESreg (int, int);
  81 static void OP_DSreg (int, int);
  82 static void OP_C (int, int);
  83 static void OP_D (int, int);
  84 static void OP_T (int, int);
  85 static void OP_R (int, int);
  86 static void OP_MMX (int, int);
  87 static void OP_XMM (int, int);
  88 static void OP_EM (int, int);
  89 static void OP_EX (int, int);
  90 static void OP_EMC (int,int);
  91 static void OP_MXC (int,int);
  92 static void OP_MS (int, int);
  93 static void OP_XS (int, int);
  94 static void OP_M (int, int);
  95 static void OP_VEX (int, int);
  96 static void OP_VEX_FMA (int, int);
  97 static void OP_EX_Vex (int, int);
  98 static void OP_EX_VexW (int, int);
  99 static void OP_XMM_Vex (int, int);
 100 static void OP_XMM_VexW (int, int);
 101 static void OP_REG_VexI4 (int, int);
 102 static void PCLMUL_Fixup (int, int);
 103 static void VEXI4_Fixup (int, int);
 104 static void VZERO_Fixup (int, int);
 105 static void VCMP_Fixup (int, int);
 106 static void OP_0f07 (int, int);
 107 static void OP_Monitor (int, int);
 108 static void OP_Mwait (int, int);
 109 static void NOP_Fixup1 (int, int);
 110 static void NOP_Fixup2 (int, int);
 111 static void OP_3DNowSuffix (int, int);
 112 static void CMP_Fixup (int, int);
 113 static void BadOp (void);
 114 static void REP_Fixup (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118
 119 static void MOVBE_Fixup (int, int);
 120
 121 struct dis_private {
 122   /* Points to first byte not fetched.  */
 123   bfd_byte *max_fetched;
 124   bfd_byte the_buffer[MAX_MNEM_SIZE];
 125   bfd_vma insn_start;
 126   int orig_sizeflag;
 127   jmp_buf bailout;
 128 };
 129
 130 enum address_mode
 131 {
 132   mode_16bit,
 133   mode_32bit,
 134   mode_64bit
 135 };
 136
 137 enum address_mode address_mode;
 138
 139 /* Flags for the prefixes for the current instruction.  See below.  */
 140 static int prefixes;
 141
 142 /* REX prefix the current instruction.  See below.  */
 143 static int rex;
 144 /* Bits of REX we've already used.  */
 145 static int rex_used;
 146 /* Original REX prefix.  */
 147 static int rex_original;
 148 /* REX bits in original REX prefix ignored.  It may not be the same
 149    as rex_original since some bits may not be ignored.  */
 150 static int rex_ignored;
 151 /* Mark parts used in the REX prefix.  When we are testing for
 152    empty prefix (for 8bit register REX extension), just mask it
 153    out.  Otherwise test for REX bit is excuse for existence of REX
 154    only in case value is nonzero.  */
 155 #define USED_REX(value)                                 \
 156   {                                                     \
 157     if (value)                                          \
 158       {                                                 \
 159         if ((rex & value))                              \
 160           rex_used |= (value) | REX_OPCODE;             \
 161       }                                                 \
 162     else                                                \
 163       rex_used |= REX_OPCODE;                           \
 164   }
 165
 166 /* Flags for prefixes which we somehow handled when printing the
 167    current instruction.  */
 168 static int used_prefixes;
 169
 170 /* Flags stored in PREFIXES.  */
 171 #define PREFIX_REPZ 1
 172 #define PREFIX_REPNZ 2
 173 #define PREFIX_LOCK 4
 174 #define PREFIX_CS 8
 175 #define PREFIX_SS 0x10
 176 #define PREFIX_DS 0x20
 177 #define PREFIX_ES 0x40
 178 #define PREFIX_FS 0x80
 179 #define PREFIX_GS 0x100
 180 #define PREFIX_DATA 0x200
 181 #define PREFIX_ADDR 0x400
 182 #define PREFIX_FWAIT 0x800
 183
 184 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 185    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 186    on error.  */
 187 #define FETCH_DATA(info, addr) \
 188   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 189    ? 1 : fetch_data ((info), (addr)))
 190
 191 static int
 192 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 193 {
 194   int status;
 195   struct dis_private *priv = (struct dis_private *) info->private_data;
 196   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 197
 198   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 199     status = (*info->read_memory_func) (start,
 200                                         priv->max_fetched,
 201                                         addr - priv->max_fetched,
 202                                         info);
 203   else
 204     status = -1;
 205   if (status != 0)
 206     {
 207       /* If we did manage to read at least one byte, then
 208          print_insn_i386 will do something sensible.  Otherwise, print
 209          an error.  We do that here because this is where we know
 210          STATUS.  */
 211       if (priv->max_fetched == priv->the_buffer)
 212         (*info->memory_error_func) (status, start, info);
 213       longjmp (priv->bailout, 1);
 214     }
 215   else
 216     priv->max_fetched = addr;
 217   return 1;
 218 }
 219
 220 #define XX { NULL, 0 }
 221
 222 #define Eb { OP_E, b_mode }
 223 #define EbS { OP_E, b_swap_mode }
 224 #define Ev { OP_E, v_mode }
 225 #define EvS { OP_E, v_swap_mode }
 226 #define Ed { OP_E, d_mode }
 227 #define Edq { OP_E, dq_mode }
 228 #define Edqw { OP_E, dqw_mode }
 229 #define Edqb { OP_E, dqb_mode }
 230 #define Edqd { OP_E, dqd_mode }
 231 #define Eq { OP_E, q_mode }
 232 #define indirEv { OP_indirE, stack_v_mode }
 233 #define indirEp { OP_indirE, f_mode }
 234 #define stackEv { OP_E, stack_v_mode }
 235 #define Em { OP_E, m_mode }
 236 #define Ew { OP_E, w_mode }
 237 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 238 #define Ma { OP_M, a_mode }
 239 #define Mb { OP_M, b_mode }
 240 #define Md { OP_M, d_mode }
 241 #define Mo { OP_M, o_mode }
 242 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 243 #define Mq { OP_M, q_mode }
 244 #define Mx { OP_M, x_mode }
 245 #define Mxmm { OP_M, xmm_mode }
 246 #define Gb { OP_G, b_mode }
 247 #define Gv { OP_G, v_mode }
 248 #define Gd { OP_G, d_mode }
 249 #define Gdq { OP_G, dq_mode }
 250 #define Gm { OP_G, m_mode }
 251 #define Gw { OP_G, w_mode }
 252 #define Rd { OP_R, d_mode }
 253 #define Rm { OP_R, m_mode }
 254 #define Ib { OP_I, b_mode }
 255 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 256 #define Iv { OP_I, v_mode }
 257 #define Iq { OP_I, q_mode }
 258 #define Iv64 { OP_I64, v_mode }
 259 #define Iw { OP_I, w_mode }
 260 #define I1 { OP_I, const_1_mode }
 261 #define Jb { OP_J, b_mode }
 262 #define Jv { OP_J, v_mode }
 263 #define Cm { OP_C, m_mode }
 264 #define Dm { OP_D, m_mode }
 265 #define Td { OP_T, d_mode }
 266 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 267
 268 #define RMeAX { OP_REG, eAX_reg }
 269 #define RMeBX { OP_REG, eBX_reg }
 270 #define RMeCX { OP_REG, eCX_reg }
 271 #define RMeDX { OP_REG, eDX_reg }
 272 #define RMeSP { OP_REG, eSP_reg }
 273 #define RMeBP { OP_REG, eBP_reg }
 274 #define RMeSI { OP_REG, eSI_reg }
 275 #define RMeDI { OP_REG, eDI_reg }
 276 #define RMrAX { OP_REG, rAX_reg }
 277 #define RMrBX { OP_REG, rBX_reg }
 278 #define RMrCX { OP_REG, rCX_reg }
 279 #define RMrDX { OP_REG, rDX_reg }
 280 #define RMrSP { OP_REG, rSP_reg }
 281 #define RMrBP { OP_REG, rBP_reg }
 282 #define RMrSI { OP_REG, rSI_reg }
 283 #define RMrDI { OP_REG, rDI_reg }
 284 #define RMAL { OP_REG, al_reg }
 285 #define RMAL { OP_REG, al_reg }
 286 #define RMCL { OP_REG, cl_reg }
 287 #define RMDL { OP_REG, dl_reg }
 288 #define RMBL { OP_REG, bl_reg }
 289 #define RMAH { OP_REG, ah_reg }
 290 #define RMCH { OP_REG, ch_reg }
 291 #define RMDH { OP_REG, dh_reg }
 292 #define RMBH { OP_REG, bh_reg }
 293 #define RMAX { OP_REG, ax_reg }
 294 #define RMDX { OP_REG, dx_reg }
 295
 296 #define eAX { OP_IMREG, eAX_reg }
 297 #define eBX { OP_IMREG, eBX_reg }
 298 #define eCX { OP_IMREG, eCX_reg }
 299 #define eDX { OP_IMREG, eDX_reg }
 300 #define eSP { OP_IMREG, eSP_reg }
 301 #define eBP { OP_IMREG, eBP_reg }
 302 #define eSI { OP_IMREG, eSI_reg }
 303 #define eDI { OP_IMREG, eDI_reg }
 304 #define AL { OP_IMREG, al_reg }
 305 #define CL { OP_IMREG, cl_reg }
 306 #define DL { OP_IMREG, dl_reg }
 307 #define BL { OP_IMREG, bl_reg }
 308 #define AH { OP_IMREG, ah_reg }
 309 #define CH { OP_IMREG, ch_reg }
 310 #define DH { OP_IMREG, dh_reg }
 311 #define BH { OP_IMREG, bh_reg }
 312 #define AX { OP_IMREG, ax_reg }
 313 #define DX { OP_IMREG, dx_reg }
 314 #define zAX { OP_IMREG, z_mode_ax_reg }
 315 #define indirDX { OP_IMREG, indir_dx_reg }
 316
 317 #define Sw { OP_SEG, w_mode }
 318 #define Sv { OP_SEG, v_mode }
 319 #define Ap { OP_DIR, 0 }
 320 #define Ob { OP_OFF64, b_mode }
 321 #define Ov { OP_OFF64, v_mode }
 322 #define Xb { OP_DSreg, eSI_reg }
 323 #define Xv { OP_DSreg, eSI_reg }
 324 #define Xz { OP_DSreg, eSI_reg }
 325 #define Yb { OP_ESreg, eDI_reg }
 326 #define Yv { OP_ESreg, eDI_reg }
 327 #define DSBX { OP_DSreg, eBX_reg }
 328
 329 #define es { OP_REG, es_reg }
 330 #define ss { OP_REG, ss_reg }
 331 #define cs { OP_REG, cs_reg }
 332 #define ds { OP_REG, ds_reg }
 333 #define fs { OP_REG, fs_reg }
 334 #define gs { OP_REG, gs_reg }
 335
 336 #define MX { OP_MMX, 0 }
 337 #define XM { OP_XMM, 0 }
 338 #define XMM { OP_XMM, xmm_mode }
 339 #define EM { OP_EM, v_mode }
 340 #define EMS { OP_EM, v_swap_mode }
 341 #define EMd { OP_EM, d_mode }
 342 #define EMx { OP_EM, x_mode }
 343 #define EXw { OP_EX, w_mode }
 344 #define EXd { OP_EX, d_mode }
 345 #define EXdS { OP_EX, d_swap_mode }
 346 #define EXq { OP_EX, q_mode }
 347 #define EXqS { OP_EX, q_swap_mode }
 348 #define EXx { OP_EX, x_mode }
 349 #define EXxS { OP_EX, x_swap_mode }
 350 #define EXxmm { OP_EX, xmm_mode }
 351 #define EXxmmq { OP_EX, xmmq_mode }
 352 #define EXymmq { OP_EX, ymmq_mode }
 353 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 354 #define MS { OP_MS, v_mode }
 355 #define XS { OP_XS, v_mode }
 356 #define EMCq { OP_EMC, q_mode }
 357 #define MXC { OP_MXC, 0 }
 358 #define OPSUF { OP_3DNowSuffix, 0 }
 359 #define CMP { CMP_Fixup, 0 }
 360 #define XMM0 { XMM_Fixup, 0 }
 361
 362 #define Vex { OP_VEX, vex_mode }
 363 #define Vex128 { OP_VEX, vex128_mode }
 364 #define Vex256 { OP_VEX, vex256_mode }
 365 #define VexI4 { VEXI4_Fixup, 0}
 366 #define VexFMA { OP_VEX_FMA, vex_mode }
 367 #define Vex128FMA { OP_VEX_FMA, vex128_mode }
 368 #define EXdVex { OP_EX_Vex, d_mode }
 369 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 370 #define EXqVex { OP_EX_Vex, q_mode }
 371 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 372 #define EXVexW { OP_EX_VexW, x_mode }
 373 #define EXdVexW { OP_EX_VexW, d_mode }
 374 #define EXqVexW { OP_EX_VexW, q_mode }
 375 #define XMVex { OP_XMM_Vex, 0 }
 376 #define XMVexW { OP_XMM_VexW, 0 }
 377 #define XMVexI4 { OP_REG_VexI4, x_mode }
 378 #define PCLMUL { PCLMUL_Fixup, 0 }
 379 #define VZERO { VZERO_Fixup, 0 }
 380 #define VCMP { VCMP_Fixup, 0 }
 381
 382 /* Used handle "rep" prefix for string instructions.  */
 383 #define Xbr { REP_Fixup, eSI_reg }
 384 #define Xvr { REP_Fixup, eSI_reg }
 385 #define Ybr { REP_Fixup, eDI_reg }
 386 #define Yvr { REP_Fixup, eDI_reg }
 387 #define Yzr { REP_Fixup, eDI_reg }
 388 #define indirDXr { REP_Fixup, indir_dx_reg }
 389 #define ALr { REP_Fixup, al_reg }
 390 #define eAXr { REP_Fixup, eAX_reg }
 391
 392 #define cond_jump_flag { NULL, cond_jump_mode }
 393 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 394
 395 /* bits in sizeflag */
 396 #define SUFFIX_ALWAYS 4
 397 #define AFLAG 2
 398 #define DFLAG 1
 399
 400 enum
 401 {
 402   /* byte operand */
 403   b_mode = 1,
 404   /* byte operand with operand swapped */
 405   b_swap_mode,
 406   /* operand size depends on prefixes */
 407   v_mode,
 408   /* operand size depends on prefixes with operand swapped */
 409   v_swap_mode,
 410   /* word operand */
 411   w_mode,
 412   /* double word operand  */
 413   d_mode,
 414   /* double word operand with operand swapped */
 415   d_swap_mode,
 416   /* quad word operand */
 417   q_mode,
 418   /* quad word operand with operand swapped */
 419   q_swap_mode,
 420   /* ten-byte operand */
 421   t_mode,
 422   /* 16-byte XMM or 32-byte YMM operand */
 423   x_mode,
 424   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 425   x_swap_mode,
 426   /* 16-byte XMM operand */
 427   xmm_mode,
 428   /* 16-byte XMM or quad word operand */
 429   xmmq_mode,
 430   /* 32-byte YMM or quad word operand */
 431   ymmq_mode,
 432   /* d_mode in 32bit, q_mode in 64bit mode.  */
 433   m_mode,
 434   /* pair of v_mode operands */
 435   a_mode,
 436   cond_jump_mode,
 437   loop_jcxz_mode,
 438   /* operand size depends on REX prefixes.  */
 439   dq_mode,
 440   /* registers like dq_mode, memory like w_mode.  */
 441   dqw_mode,
 442   /* 4- or 6-byte pointer operand */
 443   f_mode,
 444   const_1_mode,
 445   /* v_mode for stack-related opcodes.  */
 446   stack_v_mode,
 447   /* non-quad operand size depends on prefixes */
 448   z_mode,
 449   /* 16-byte operand */
 450   o_mode,
 451   /* registers like dq_mode, memory like b_mode.  */
 452   dqb_mode,
 453   /* registers like dq_mode, memory like d_mode.  */
 454   dqd_mode,
 455   /* normal vex mode */
 456   vex_mode,
 457   /* 128bit vex mode */
 458   vex128_mode,
 459   /* 256bit vex mode */
 460   vex256_mode,
 461   /* operand size depends on the VEX.W bit.  */
 462   vex_w_dq_mode,
 463
 464   es_reg,
 465   cs_reg,
 466   ss_reg,
 467   ds_reg,
 468   fs_reg,
 469   gs_reg,
 470
 471   eAX_reg,
 472   eCX_reg,
 473   eDX_reg,
 474   eBX_reg,
 475   eSP_reg,
 476   eBP_reg,
 477   eSI_reg,
 478   eDI_reg,
 479
 480   al_reg,
 481   cl_reg,
 482   dl_reg,
 483   bl_reg,
 484   ah_reg,
 485   ch_reg,
 486   dh_reg,
 487   bh_reg,
 488
 489   ax_reg,
 490   cx_reg,
 491   dx_reg,
 492   bx_reg,
 493   sp_reg,
 494   bp_reg,
 495   si_reg,
 496   di_reg,
 497
 498   rAX_reg,
 499   rCX_reg,
 500   rDX_reg,
 501   rBX_reg,
 502   rSP_reg,
 503   rBP_reg,
 504   rSI_reg,
 505   rDI_reg,
 506
 507   z_mode_ax_reg,
 508   indir_dx_reg
 509 };
 510
 511 enum
 512 {
 513   FLOATCODE = 1,
 514   USE_REG_TABLE,
 515   USE_MOD_TABLE,
 516   USE_RM_TABLE,
 517   USE_PREFIX_TABLE,
 518   USE_X86_64_TABLE,
 519   USE_3BYTE_TABLE,
 520   USE_VEX_C4_TABLE,
 521   USE_VEX_C5_TABLE,
 522   USE_VEX_LEN_TABLE
 523 };
 524
 525 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 526
 527 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 528 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 529 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 530 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 531 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 532 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 533 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 534 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 535 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 536 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 537
 538 enum
 539 {
 540   REG_80 = 0,
 541   REG_81,
 542   REG_82,
 543   REG_8F,
 544   REG_C0,
 545   REG_C1,
 546   REG_C6,
 547   REG_C7,
 548   REG_D0,
 549   REG_D1,
 550   REG_D2,
 551   REG_D3,
 552   REG_F6,
 553   REG_F7,
 554   REG_FE,
 555   REG_FF,
 556   REG_0F00,
 557   REG_0F01,
 558   REG_0F0D,
 559   REG_0F18,
 560   REG_0F71,
 561   REG_0F72,
 562   REG_0F73,
 563   REG_0FA6,
 564   REG_0FA7,
 565   REG_0FAE,
 566   REG_0FBA,
 567   REG_0FC7,
 568   REG_VEX_71,
 569   REG_VEX_72,
 570   REG_VEX_73,
 571   REG_VEX_AE
 572 };
 573
 574 enum
 575 {
 576   MOD_8D = 0,
 577   MOD_0F01_REG_0,
 578   MOD_0F01_REG_1,
 579   MOD_0F01_REG_2,
 580   MOD_0F01_REG_3,
 581   MOD_0F01_REG_7,
 582   MOD_0F12_PREFIX_0,
 583   MOD_0F13,
 584   MOD_0F16_PREFIX_0,
 585   MOD_0F17,
 586   MOD_0F18_REG_0,
 587   MOD_0F18_REG_1,
 588   MOD_0F18_REG_2,
 589   MOD_0F18_REG_3,
 590   MOD_0F20,
 591   MOD_0F21,
 592   MOD_0F22,
 593   MOD_0F23,
 594   MOD_0F24,
 595   MOD_0F26,
 596   MOD_0F2B_PREFIX_0,
 597   MOD_0F2B_PREFIX_1,
 598   MOD_0F2B_PREFIX_2,
 599   MOD_0F2B_PREFIX_3,
 600   MOD_0F51,
 601   MOD_0F71_REG_2,
 602   MOD_0F71_REG_4,
 603   MOD_0F71_REG_6,
 604   MOD_0F72_REG_2,
 605   MOD_0F72_REG_4,
 606   MOD_0F72_REG_6,
 607   MOD_0F73_REG_2,
 608   MOD_0F73_REG_3,
 609   MOD_0F73_REG_6,
 610   MOD_0F73_REG_7,
 611   MOD_0FAE_REG_0,
 612   MOD_0FAE_REG_1,
 613   MOD_0FAE_REG_2,
 614   MOD_0FAE_REG_3,
 615   MOD_0FAE_REG_4,
 616   MOD_0FAE_REG_5,
 617   MOD_0FAE_REG_6,
 618   MOD_0FAE_REG_7,
 619   MOD_0FB2,
 620   MOD_0FB4,
 621   MOD_0FB5,
 622   MOD_0FC7_REG_6,
 623   MOD_0FC7_REG_7,
 624   MOD_0FD7,
 625   MOD_0FE7_PREFIX_2,
 626   MOD_0FF0_PREFIX_3,
 627   MOD_0F382A_PREFIX_2,
 628   MOD_62_32BIT,
 629   MOD_C4_32BIT,
 630   MOD_C5_32BIT,
 631   MOD_VEX_12_PREFIX_0,
 632   MOD_VEX_13,
 633   MOD_VEX_16_PREFIX_0,
 634   MOD_VEX_17,
 635   MOD_VEX_2B,
 636   MOD_VEX_51,
 637   MOD_VEX_71_REG_2,
 638   MOD_VEX_71_REG_4,
 639   MOD_VEX_71_REG_6,
 640   MOD_VEX_72_REG_2,
 641   MOD_VEX_72_REG_4,
 642   MOD_VEX_72_REG_6,
 643   MOD_VEX_73_REG_2,
 644   MOD_VEX_73_REG_3,
 645   MOD_VEX_73_REG_6,
 646   MOD_VEX_73_REG_7,
 647   MOD_VEX_AE_REG_2,
 648   MOD_VEX_AE_REG_3,
 649   MOD_VEX_D7_PREFIX_2,
 650   MOD_VEX_E7_PREFIX_2,
 651   MOD_VEX_F0_PREFIX_3,
 652   MOD_VEX_3818_PREFIX_2,
 653   MOD_VEX_3819_PREFIX_2,
 654   MOD_VEX_381A_PREFIX_2,
 655   MOD_VEX_382A_PREFIX_2,
 656   MOD_VEX_382C_PREFIX_2,
 657   MOD_VEX_382D_PREFIX_2,
 658   MOD_VEX_382E_PREFIX_2,
 659   MOD_VEX_382F_PREFIX_2
 660 };
 661
 662 enum
 663 {
 664   RM_0F01_REG_0 = 0,
 665   RM_0F01_REG_1,
 666   RM_0F01_REG_2,
 667   RM_0F01_REG_3,
 668   RM_0F01_REG_7,
 669   RM_0FAE_REG_5,
 670   RM_0FAE_REG_6,
 671   RM_0FAE_REG_7
 672 };
 673
 674 enum
 675 {
 676   PREFIX_90 = 0,
 677   PREFIX_0F10,
 678   PREFIX_0F11,
 679   PREFIX_0F12,
 680   PREFIX_0F16,
 681   PREFIX_0F2A,
 682   PREFIX_0F2B,
 683   PREFIX_0F2C,
 684   PREFIX_0F2D,
 685   PREFIX_0F2E,
 686   PREFIX_0F2F,
 687   PREFIX_0F51,
 688   PREFIX_0F52,
 689   PREFIX_0F53,
 690   PREFIX_0F58,
 691   PREFIX_0F59,
 692   PREFIX_0F5A,
 693   PREFIX_0F5B,
 694   PREFIX_0F5C,
 695   PREFIX_0F5D,
 696   PREFIX_0F5E,
 697   PREFIX_0F5F,
 698   PREFIX_0F60,
 699   PREFIX_0F61,
 700   PREFIX_0F62,
 701   PREFIX_0F6C,
 702   PREFIX_0F6D,
 703   PREFIX_0F6F,
 704   PREFIX_0F70,
 705   PREFIX_0F73_REG_3,
 706   PREFIX_0F73_REG_7,
 707   PREFIX_0F78,
 708   PREFIX_0F79,
 709   PREFIX_0F7C,
 710   PREFIX_0F7D,
 711   PREFIX_0F7E,
 712   PREFIX_0F7F,
 713   PREFIX_0FB8,
 714   PREFIX_0FBD,
 715   PREFIX_0FC2,
 716   PREFIX_0FC3,
 717   PREFIX_0FC7_REG_6,
 718   PREFIX_0FD0,
 719   PREFIX_0FD6,
 720   PREFIX_0FE6,
 721   PREFIX_0FE7,
 722   PREFIX_0FF0,
 723   PREFIX_0FF7,
 724   PREFIX_0F3810,
 725   PREFIX_0F3814,
 726   PREFIX_0F3815,
 727   PREFIX_0F3817,
 728   PREFIX_0F3820,
 729   PREFIX_0F3821,
 730   PREFIX_0F3822,
 731   PREFIX_0F3823,
 732   PREFIX_0F3824,
 733   PREFIX_0F3825,
 734   PREFIX_0F3828,
 735   PREFIX_0F3829,
 736   PREFIX_0F382A,
 737   PREFIX_0F382B,
 738   PREFIX_0F3830,
 739   PREFIX_0F3831,
 740   PREFIX_0F3832,
 741   PREFIX_0F3833,
 742   PREFIX_0F3834,
 743   PREFIX_0F3835,
 744   PREFIX_0F3837,
 745   PREFIX_0F3838,
 746   PREFIX_0F3839,
 747   PREFIX_0F383A,
 748   PREFIX_0F383B,
 749   PREFIX_0F383C,
 750   PREFIX_0F383D,
 751   PREFIX_0F383E,
 752   PREFIX_0F383F,
 753   PREFIX_0F3840,
 754   PREFIX_0F3841,
 755   PREFIX_0F3880,
 756   PREFIX_0F3881,
 757   PREFIX_0F38DB,
 758   PREFIX_0F38DC,
 759   PREFIX_0F38DD,
 760   PREFIX_0F38DE,
 761   PREFIX_0F38DF,
 762   PREFIX_0F38F0,
 763   PREFIX_0F38F1,
 764   PREFIX_0F3A08,
 765   PREFIX_0F3A09,
 766   PREFIX_0F3A0A,
 767   PREFIX_0F3A0B,
 768   PREFIX_0F3A0C,
 769   PREFIX_0F3A0D,
 770   PREFIX_0F3A0E,
 771   PREFIX_0F3A14,
 772   PREFIX_0F3A15,
 773   PREFIX_0F3A16,
 774   PREFIX_0F3A17,
 775   PREFIX_0F3A20,
 776   PREFIX_0F3A21,
 777   PREFIX_0F3A22,
 778   PREFIX_0F3A40,
 779   PREFIX_0F3A41,
 780   PREFIX_0F3A42,
 781   PREFIX_0F3A44,
 782   PREFIX_0F3A60,
 783   PREFIX_0F3A61,
 784   PREFIX_0F3A62,
 785   PREFIX_0F3A63,
 786   PREFIX_0F3ADF,
 787   PREFIX_VEX_10,
 788   PREFIX_VEX_11,
 789   PREFIX_VEX_12,
 790   PREFIX_VEX_16,
 791   PREFIX_VEX_2A,
 792   PREFIX_VEX_2C,
 793   PREFIX_VEX_2D,
 794   PREFIX_VEX_2E,
 795   PREFIX_VEX_2F,
 796   PREFIX_VEX_51,
 797   PREFIX_VEX_52,
 798   PREFIX_VEX_53,
 799   PREFIX_VEX_58,
 800   PREFIX_VEX_59,
 801   PREFIX_VEX_5A,
 802   PREFIX_VEX_5B,
 803   PREFIX_VEX_5C,
 804   PREFIX_VEX_5D,
 805   PREFIX_VEX_5E,
 806   PREFIX_VEX_5F,
 807   PREFIX_VEX_60,
 808   PREFIX_VEX_61,
 809   PREFIX_VEX_62,
 810   PREFIX_VEX_63,
 811   PREFIX_VEX_64,
 812   PREFIX_VEX_65,
 813   PREFIX_VEX_66,
 814   PREFIX_VEX_67,
 815   PREFIX_VEX_68,
 816   PREFIX_VEX_69,
 817   PREFIX_VEX_6A,
 818   PREFIX_VEX_6B,
 819   PREFIX_VEX_6C,
 820   PREFIX_VEX_6D,
 821   PREFIX_VEX_6E,
 822   PREFIX_VEX_6F,
 823   PREFIX_VEX_70,
 824   PREFIX_VEX_71_REG_2,
 825   PREFIX_VEX_71_REG_4,
 826   PREFIX_VEX_71_REG_6,
 827   PREFIX_VEX_72_REG_2,
 828   PREFIX_VEX_72_REG_4,
 829   PREFIX_VEX_72_REG_6,
 830   PREFIX_VEX_73_REG_2,
 831   PREFIX_VEX_73_REG_3,
 832   PREFIX_VEX_73_REG_6,
 833   PREFIX_VEX_73_REG_7,
 834   PREFIX_VEX_74,
 835   PREFIX_VEX_75,
 836   PREFIX_VEX_76,
 837   PREFIX_VEX_77,
 838   PREFIX_VEX_7C,
 839   PREFIX_VEX_7D,
 840   PREFIX_VEX_7E,
 841   PREFIX_VEX_7F,
 842   PREFIX_VEX_C2,
 843   PREFIX_VEX_C4,
 844   PREFIX_VEX_C5,
 845   PREFIX_VEX_D0,
 846   PREFIX_VEX_D1,
 847   PREFIX_VEX_D2,
 848   PREFIX_VEX_D3,
 849   PREFIX_VEX_D4,
 850   PREFIX_VEX_D5,
 851   PREFIX_VEX_D6,
 852   PREFIX_VEX_D7,
 853   PREFIX_VEX_D8,
 854   PREFIX_VEX_D9,
 855   PREFIX_VEX_DA,
 856   PREFIX_VEX_DB,
 857   PREFIX_VEX_DC,
 858   PREFIX_VEX_DD,
 859   PREFIX_VEX_DE,
 860   PREFIX_VEX_DF,
 861   PREFIX_VEX_E0,
 862   PREFIX_VEX_E1,
 863   PREFIX_VEX_E2,
 864   PREFIX_VEX_E3,
 865   PREFIX_VEX_E4,
 866   PREFIX_VEX_E5,
 867   PREFIX_VEX_E6,
 868   PREFIX_VEX_E7,
 869   PREFIX_VEX_E8,
 870   PREFIX_VEX_E9,
 871   PREFIX_VEX_EA,
 872   PREFIX_VEX_EB,
 873   PREFIX_VEX_EC,
 874   PREFIX_VEX_ED,
 875   PREFIX_VEX_EE,
 876   PREFIX_VEX_EF,
 877   PREFIX_VEX_F0,
 878   PREFIX_VEX_F1,
 879   PREFIX_VEX_F2,
 880   PREFIX_VEX_F3,
 881   PREFIX_VEX_F4,
 882   PREFIX_VEX_F5,
 883   PREFIX_VEX_F6,
 884   PREFIX_VEX_F7,
 885   PREFIX_VEX_F8,
 886   PREFIX_VEX_F9,
 887   PREFIX_VEX_FA,
 888   PREFIX_VEX_FB,
 889   PREFIX_VEX_FC,
 890   PREFIX_VEX_FD,
 891   PREFIX_VEX_FE,
 892   PREFIX_VEX_3800,
 893   PREFIX_VEX_3801,
 894   PREFIX_VEX_3802,
 895   PREFIX_VEX_3803,
 896   PREFIX_VEX_3804,
 897   PREFIX_VEX_3805,
 898   PREFIX_VEX_3806,
 899   PREFIX_VEX_3807,
 900   PREFIX_VEX_3808,
 901   PREFIX_VEX_3809,
 902   PREFIX_VEX_380A,
 903   PREFIX_VEX_380B,
 904   PREFIX_VEX_380C,
 905   PREFIX_VEX_380D,
 906   PREFIX_VEX_380E,
 907   PREFIX_VEX_380F,
 908   PREFIX_VEX_3817,
 909   PREFIX_VEX_3818,
 910   PREFIX_VEX_3819,
 911   PREFIX_VEX_381A,
 912   PREFIX_VEX_381C,
 913   PREFIX_VEX_381D,
 914   PREFIX_VEX_381E,
 915   PREFIX_VEX_3820,
 916   PREFIX_VEX_3821,
 917   PREFIX_VEX_3822,
 918   PREFIX_VEX_3823,
 919   PREFIX_VEX_3824,
 920   PREFIX_VEX_3825,
 921   PREFIX_VEX_3828,
 922   PREFIX_VEX_3829,
 923   PREFIX_VEX_382A,
 924   PREFIX_VEX_382B,
 925   PREFIX_VEX_382C,
 926   PREFIX_VEX_382D,
 927   PREFIX_VEX_382E,
 928   PREFIX_VEX_382F,
 929   PREFIX_VEX_3830,
 930   PREFIX_VEX_3831,
 931   PREFIX_VEX_3832,
 932   PREFIX_VEX_3833,
 933   PREFIX_VEX_3834,
 934   PREFIX_VEX_3835,
 935   PREFIX_VEX_3837,
 936   PREFIX_VEX_3838,
 937   PREFIX_VEX_3839,
 938   PREFIX_VEX_383A,
 939   PREFIX_VEX_383B,
 940   PREFIX_VEX_383C,
 941   PREFIX_VEX_383D,
 942   PREFIX_VEX_383E,
 943   PREFIX_VEX_383F,
 944   PREFIX_VEX_3840,
 945   PREFIX_VEX_3841,
 946   PREFIX_VEX_3896,
 947   PREFIX_VEX_3897,
 948   PREFIX_VEX_3898,
 949   PREFIX_VEX_3899,
 950   PREFIX_VEX_389A,
 951   PREFIX_VEX_389B,
 952   PREFIX_VEX_389C,
 953   PREFIX_VEX_389D,
 954   PREFIX_VEX_389E,
 955   PREFIX_VEX_389F,
 956   PREFIX_VEX_38A6,
 957   PREFIX_VEX_38A7,
 958   PREFIX_VEX_38A8,
 959   PREFIX_VEX_38A9,
 960   PREFIX_VEX_38AA,
 961   PREFIX_VEX_38AB,
 962   PREFIX_VEX_38AC,
 963   PREFIX_VEX_38AD,
 964   PREFIX_VEX_38AE,
 965   PREFIX_VEX_38AF,
 966   PREFIX_VEX_38B6,
 967   PREFIX_VEX_38B7,
 968   PREFIX_VEX_38B8,
 969   PREFIX_VEX_38B9,
 970   PREFIX_VEX_38BA,
 971   PREFIX_VEX_38BB,
 972   PREFIX_VEX_38BC,
 973   PREFIX_VEX_38BD,
 974   PREFIX_VEX_38BE,
 975   PREFIX_VEX_38BF,
 976   PREFIX_VEX_38DB,
 977   PREFIX_VEX_38DC,
 978   PREFIX_VEX_38DD,
 979   PREFIX_VEX_38DE,
 980   PREFIX_VEX_38DF,
 981   PREFIX_VEX_3A04,
 982   PREFIX_VEX_3A05,
 983   PREFIX_VEX_3A06,
 984   PREFIX_VEX_3A08,
 985   PREFIX_VEX_3A09,
 986   PREFIX_VEX_3A0A,
 987   PREFIX_VEX_3A0B,
 988   PREFIX_VEX_3A0C,
 989   PREFIX_VEX_3A0D,
 990   PREFIX_VEX_3A0E,
 991   PREFIX_VEX_3A0F,
 992   PREFIX_VEX_3A14,
 993   PREFIX_VEX_3A15,
 994   PREFIX_VEX_3A16,
 995   PREFIX_VEX_3A17,
 996   PREFIX_VEX_3A18,
 997   PREFIX_VEX_3A19,
 998   PREFIX_VEX_3A20,
 999   PREFIX_VEX_3A21,
1000   PREFIX_VEX_3A22,
1001   PREFIX_VEX_3A40,
1002   PREFIX_VEX_3A41,
1003   PREFIX_VEX_3A42,
1004   PREFIX_VEX_3A44,
1005   PREFIX_VEX_3A4A,
1006   PREFIX_VEX_3A4B,
1007   PREFIX_VEX_3A4C,
1008   PREFIX_VEX_3A5C,
1009   PREFIX_VEX_3A5D,
1010   PREFIX_VEX_3A5E,
1011   PREFIX_VEX_3A5F,
1012   PREFIX_VEX_3A60,
1013   PREFIX_VEX_3A61,
1014   PREFIX_VEX_3A62,
1015   PREFIX_VEX_3A63,
1016   PREFIX_VEX_3A68,
1017   PREFIX_VEX_3A69,
1018   PREFIX_VEX_3A6A,
1019   PREFIX_VEX_3A6B,
1020   PREFIX_VEX_3A6C,
1021   PREFIX_VEX_3A6D,
1022   PREFIX_VEX_3A6E,
1023   PREFIX_VEX_3A6F,
1024   PREFIX_VEX_3A78,
1025   PREFIX_VEX_3A79,
1026   PREFIX_VEX_3A7A,
1027   PREFIX_VEX_3A7B,
1028   PREFIX_VEX_3A7C,
1029   PREFIX_VEX_3A7D,
1030   PREFIX_VEX_3A7E,
1031   PREFIX_VEX_3A7F,
1032   PREFIX_VEX_3ADF
1033 };
1034
1035 enum
1036 {
1037   X86_64_06 = 0,
1038   X86_64_07,
1039   X86_64_0D,
1040   X86_64_16,
1041   X86_64_17,
1042   X86_64_1E,
1043   X86_64_1F,
1044   X86_64_27,
1045   X86_64_2F,
1046   X86_64_37,
1047   X86_64_3F,
1048   X86_64_60,
1049   X86_64_61,
1050   X86_64_62,
1051   X86_64_63,
1052   X86_64_6D,
1053   X86_64_6F,
1054   X86_64_9A,
1055   X86_64_C4,
1056   X86_64_C5,
1057   X86_64_CE,
1058   X86_64_D4,
1059   X86_64_D5,
1060   X86_64_EA,
1061   X86_64_0F01_REG_0,
1062   X86_64_0F01_REG_1,
1063   X86_64_0F01_REG_2,
1064   X86_64_0F01_REG_3
1065 };
1066
1067 enum
1068 {
1069   THREE_BYTE_0F38 = 0,
1070   THREE_BYTE_0F3A,
1071   THREE_BYTE_0F7A
1072 };
1073
1074 enum
1075 {
1076   VEX_0F = 0,
1077   VEX_0F38,
1078   VEX_0F3A
1079 };
1080
1081 enum
1082 {
1083   VEX_LEN_10_P_1 = 0,
1084   VEX_LEN_10_P_3,
1085   VEX_LEN_11_P_1,
1086   VEX_LEN_11_P_3,
1087   VEX_LEN_12_P_0_M_0,
1088   VEX_LEN_12_P_0_M_1,
1089   VEX_LEN_12_P_2,
1090   VEX_LEN_13_M_0,
1091   VEX_LEN_16_P_0_M_0,
1092   VEX_LEN_16_P_0_M_1,
1093   VEX_LEN_16_P_2,
1094   VEX_LEN_17_M_0,
1095   VEX_LEN_2A_P_1,
1096   VEX_LEN_2A_P_3,
1097   VEX_LEN_2C_P_1,
1098   VEX_LEN_2C_P_3,
1099   VEX_LEN_2D_P_1,
1100   VEX_LEN_2D_P_3,
1101   VEX_LEN_2E_P_0,
1102   VEX_LEN_2E_P_2,
1103   VEX_LEN_2F_P_0,
1104   VEX_LEN_2F_P_2,
1105   VEX_LEN_51_P_1,
1106   VEX_LEN_51_P_3,
1107   VEX_LEN_52_P_1,
1108   VEX_LEN_53_P_1,
1109   VEX_LEN_58_P_1,
1110   VEX_LEN_58_P_3,
1111   VEX_LEN_59_P_1,
1112   VEX_LEN_59_P_3,
1113   VEX_LEN_5A_P_1,
1114   VEX_LEN_5A_P_3,
1115   VEX_LEN_5C_P_1,
1116   VEX_LEN_5C_P_3,
1117   VEX_LEN_5D_P_1,
1118   VEX_LEN_5D_P_3,
1119   VEX_LEN_5E_P_1,
1120   VEX_LEN_5E_P_3,
1121   VEX_LEN_5F_P_1,
1122   VEX_LEN_5F_P_3,
1123   VEX_LEN_60_P_2,
1124   VEX_LEN_61_P_2,
1125   VEX_LEN_62_P_2,
1126   VEX_LEN_63_P_2,
1127   VEX_LEN_64_P_2,
1128   VEX_LEN_65_P_2,
1129   VEX_LEN_66_P_2,
1130   VEX_LEN_67_P_2,
1131   VEX_LEN_68_P_2,
1132   VEX_LEN_69_P_2,
1133   VEX_LEN_6A_P_2,
1134   VEX_LEN_6B_P_2,
1135   VEX_LEN_6C_P_2,
1136   VEX_LEN_6D_P_2,
1137   VEX_LEN_6E_P_2,
1138   VEX_LEN_70_P_1,
1139   VEX_LEN_70_P_2,
1140   VEX_LEN_70_P_3,
1141   VEX_LEN_71_R_2_P_2,
1142   VEX_LEN_71_R_4_P_2,
1143   VEX_LEN_71_R_6_P_2,
1144   VEX_LEN_72_R_2_P_2,
1145   VEX_LEN_72_R_4_P_2,
1146   VEX_LEN_72_R_6_P_2,
1147   VEX_LEN_73_R_2_P_2,
1148   VEX_LEN_73_R_3_P_2,
1149   VEX_LEN_73_R_6_P_2,
1150   VEX_LEN_73_R_7_P_2,
1151   VEX_LEN_74_P_2,
1152   VEX_LEN_75_P_2,
1153   VEX_LEN_76_P_2,
1154   VEX_LEN_7E_P_1,
1155   VEX_LEN_7E_P_2,
1156   VEX_LEN_AE_R_2_M_0,
1157   VEX_LEN_AE_R_3_M_0,
1158   VEX_LEN_C2_P_1,
1159   VEX_LEN_C2_P_3,
1160   VEX_LEN_C4_P_2,
1161   VEX_LEN_C5_P_2,
1162   VEX_LEN_D1_P_2,
1163   VEX_LEN_D2_P_2,
1164   VEX_LEN_D3_P_2,
1165   VEX_LEN_D4_P_2,
1166   VEX_LEN_D5_P_2,
1167   VEX_LEN_D6_P_2,
1168   VEX_LEN_D7_P_2_M_1,
1169   VEX_LEN_D8_P_2,
1170   VEX_LEN_D9_P_2,
1171   VEX_LEN_DA_P_2,
1172   VEX_LEN_DB_P_2,
1173   VEX_LEN_DC_P_2,
1174   VEX_LEN_DD_P_2,
1175   VEX_LEN_DE_P_2,
1176   VEX_LEN_DF_P_2,
1177   VEX_LEN_E0_P_2,
1178   VEX_LEN_E1_P_2,
1179   VEX_LEN_E2_P_2,
1180   VEX_LEN_E3_P_2,
1181   VEX_LEN_E4_P_2,
1182   VEX_LEN_E5_P_2,
1183   VEX_LEN_E8_P_2,
1184   VEX_LEN_E9_P_2,
1185   VEX_LEN_EA_P_2,
1186   VEX_LEN_EB_P_2,
1187   VEX_LEN_EC_P_2,
1188   VEX_LEN_ED_P_2,
1189   VEX_LEN_EE_P_2,
1190   VEX_LEN_EF_P_2,
1191   VEX_LEN_F1_P_2,
1192   VEX_LEN_F2_P_2,
1193   VEX_LEN_F3_P_2,
1194   VEX_LEN_F4_P_2,
1195   VEX_LEN_F5_P_2,
1196   VEX_LEN_F6_P_2,
1197   VEX_LEN_F7_P_2,
1198   VEX_LEN_F8_P_2,
1199   VEX_LEN_F9_P_2,
1200   VEX_LEN_FA_P_2,
1201   VEX_LEN_FB_P_2,
1202   VEX_LEN_FC_P_2,
1203   VEX_LEN_FD_P_2,
1204   VEX_LEN_FE_P_2,
1205   VEX_LEN_3800_P_2,
1206   VEX_LEN_3801_P_2,
1207   VEX_LEN_3802_P_2,
1208   VEX_LEN_3803_P_2,
1209   VEX_LEN_3804_P_2,
1210   VEX_LEN_3805_P_2,
1211   VEX_LEN_3806_P_2,
1212   VEX_LEN_3807_P_2,
1213   VEX_LEN_3808_P_2,
1214   VEX_LEN_3809_P_2,
1215   VEX_LEN_380A_P_2,
1216   VEX_LEN_380B_P_2,
1217   VEX_LEN_3819_P_2_M_0,
1218   VEX_LEN_381A_P_2_M_0,
1219   VEX_LEN_381C_P_2,
1220   VEX_LEN_381D_P_2,
1221   VEX_LEN_381E_P_2,
1222   VEX_LEN_3820_P_2,
1223   VEX_LEN_3821_P_2,
1224   VEX_LEN_3822_P_2,
1225   VEX_LEN_3823_P_2,
1226   VEX_LEN_3824_P_2,
1227   VEX_LEN_3825_P_2,
1228   VEX_LEN_3828_P_2,
1229   VEX_LEN_3829_P_2,
1230   VEX_LEN_382A_P_2_M_0,
1231   VEX_LEN_382B_P_2,
1232   VEX_LEN_3830_P_2,
1233   VEX_LEN_3831_P_2,
1234   VEX_LEN_3832_P_2,
1235   VEX_LEN_3833_P_2,
1236   VEX_LEN_3834_P_2,
1237   VEX_LEN_3835_P_2,
1238   VEX_LEN_3837_P_2,
1239   VEX_LEN_3838_P_2,
1240   VEX_LEN_3839_P_2,
1241   VEX_LEN_383A_P_2,
1242   VEX_LEN_383B_P_2,
1243   VEX_LEN_383C_P_2,
1244   VEX_LEN_383D_P_2,
1245   VEX_LEN_383E_P_2,
1246   VEX_LEN_383F_P_2,
1247   VEX_LEN_3840_P_2,
1248   VEX_LEN_3841_P_2,
1249   VEX_LEN_38DB_P_2,
1250   VEX_LEN_38DC_P_2,
1251   VEX_LEN_38DD_P_2,
1252   VEX_LEN_38DE_P_2,
1253   VEX_LEN_38DF_P_2,
1254   VEX_LEN_3A06_P_2,
1255   VEX_LEN_3A0A_P_2,
1256   VEX_LEN_3A0B_P_2,
1257   VEX_LEN_3A0E_P_2,
1258   VEX_LEN_3A0F_P_2,
1259   VEX_LEN_3A14_P_2,
1260   VEX_LEN_3A15_P_2,
1261   VEX_LEN_3A16_P_2,
1262   VEX_LEN_3A17_P_2,
1263   VEX_LEN_3A18_P_2,
1264   VEX_LEN_3A19_P_2,
1265   VEX_LEN_3A20_P_2,
1266   VEX_LEN_3A21_P_2,
1267   VEX_LEN_3A22_P_2,
1268   VEX_LEN_3A41_P_2,
1269   VEX_LEN_3A42_P_2,
1270   VEX_LEN_3A44_P_2,
1271   VEX_LEN_3A4C_P_2,
1272   VEX_LEN_3A60_P_2,
1273   VEX_LEN_3A61_P_2,
1274   VEX_LEN_3A62_P_2,
1275   VEX_LEN_3A63_P_2,
1276   VEX_LEN_3A6A_P_2,
1277   VEX_LEN_3A6B_P_2,
1278   VEX_LEN_3A6E_P_2,
1279   VEX_LEN_3A6F_P_2,
1280   VEX_LEN_3A7A_P_2,
1281   VEX_LEN_3A7B_P_2,
1282   VEX_LEN_3A7E_P_2,
1283   VEX_LEN_3A7F_P_2,
1284   VEX_LEN_3ADF_P_2
1285 };
1286
1287 typedef void (*op_rtn) (int bytemode, int sizeflag);
1288
1289 struct dis386 {
1290   const char *name;
1291   struct
1292     {
1293       op_rtn rtn;
1294       int bytemode;
1295     } op[MAX_OPERANDS];
1296 };
1297
1298 /* Upper case letters in the instruction names here are macros.
1299    'A' => print 'b' if no register operands or suffix_always is true
1300    'B' => print 'b' if suffix_always is true
1301    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1302           size prefix
1303    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1304           suffix_always is true
1305    'E' => print 'e' if 32-bit form of jcxz
1306    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1307    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1308    'H' => print ",pt" or ",pn" branch hint
1309    'I' => honor following macro letter even in Intel mode (implemented only
1310           for some of the macro letters)
1311    'J' => print 'l'
1312    'K' => print 'd' or 'q' if rex prefix is present.
1313    'L' => print 'l' if suffix_always is true
1314    'M' => print 'r' if intel_mnemonic is false.
1315    'N' => print 'n' if instruction has no wait "prefix"
1316    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1317    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1318           or suffix_always is true.  print 'q' if rex prefix is present.
1319    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1320           is true
1321    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1322    'S' => print 'w', 'l' or 'q' if suffix_always is true
1323    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1324    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1325    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1326    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1327    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1328    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1329           suffix_always is true.
1330    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1331    '!' => change condition from true to false or from false to true.
1332    '%' => add 1 upper case letter to the macro.
1333
1334    2 upper case letter macros:
1335    "XY" => print 'x' or 'y' if no register operands or suffix_always
1336            is true.
1337    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1338    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1339            or suffix_always is true
1340    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1341    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1342    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1343
1344    Many of the above letters print nothing in Intel mode.  See "putop"
1345    for the details.
1346
1347    Braces '{' and '}', and vertical bars '|', indicate alternative
1348    mnemonic strings for AT&T and Intel.  */
1349
1350 static const struct dis386 dis386[] = {
1351   /* 00 */
1352   { "addB",             { Eb, Gb } },
1353   { "addS",             { Ev, Gv } },
1354   { "addB",             { Gb, EbS } },
1355   { "addS",             { Gv, EvS } },
1356   { "addB",             { AL, Ib } },
1357   { "addS",             { eAX, Iv } },
1358   { X86_64_TABLE (X86_64_06) },
1359   { X86_64_TABLE (X86_64_07) },
1360   /* 08 */
1361   { "orB",              { Eb, Gb } },
1362   { "orS",              { Ev, Gv } },
1363   { "orB",              { Gb, EbS } },
1364   { "orS",              { Gv, EvS } },
1365   { "orB",              { AL, Ib } },
1366   { "orS",              { eAX, Iv } },
1367   { X86_64_TABLE (X86_64_0D) },
1368   { "(bad)",            { XX } },       /* 0x0f extended opcode escape */
1369   /* 10 */
1370   { "adcB",             { Eb, Gb } },
1371   { "adcS",             { Ev, Gv } },
1372   { "adcB",             { Gb, EbS } },
1373   { "adcS",             { Gv, EvS } },
1374   { "adcB",             { AL, Ib } },
1375   { "adcS",             { eAX, Iv } },
1376   { X86_64_TABLE (X86_64_16) },
1377   { X86_64_TABLE (X86_64_17) },
1378   /* 18 */
1379   { "sbbB",             { Eb, Gb } },
1380   { "sbbS",             { Ev, Gv } },
1381   { "sbbB",             { Gb, EbS } },
1382   { "sbbS",             { Gv, EvS } },
1383   { "sbbB",             { AL, Ib } },
1384   { "sbbS",             { eAX, Iv } },
1385   { X86_64_TABLE (X86_64_1E) },
1386   { X86_64_TABLE (X86_64_1F) },
1387   /* 20 */
1388   { "andB",             { Eb, Gb } },
1389   { "andS",             { Ev, Gv } },
1390   { "andB",             { Gb, EbS } },
1391   { "andS",             { Gv, EvS } },
1392   { "andB",             { AL, Ib } },
1393   { "andS",             { eAX, Iv } },
1394   { "(bad)",            { XX } },       /* SEG ES prefix */
1395   { X86_64_TABLE (X86_64_27) },
1396   /* 28 */
1397   { "subB",             { Eb, Gb } },
1398   { "subS",             { Ev, Gv } },
1399   { "subB",             { Gb, EbS } },
1400   { "subS",             { Gv, EvS } },
1401   { "subB",             { AL, Ib } },
1402   { "subS",             { eAX, Iv } },
1403   { "(bad)",            { XX } },       /* SEG CS prefix */
1404   { X86_64_TABLE (X86_64_2F) },
1405   /* 30 */
1406   { "xorB",             { Eb, Gb } },
1407   { "xorS",             { Ev, Gv } },
1408   { "xorB",             { Gb, EbS } },
1409   { "xorS",             { Gv, EvS } },
1410   { "xorB",             { AL, Ib } },
1411   { "xorS",             { eAX, Iv } },
1412   { "(bad)",            { XX } },       /* SEG SS prefix */
1413   { X86_64_TABLE (X86_64_37) },
1414   /* 38 */
1415   { "cmpB",             { Eb, Gb } },
1416   { "cmpS",             { Ev, Gv } },
1417   { "cmpB",             { Gb, EbS } },
1418   { "cmpS",             { Gv, EvS } },
1419   { "cmpB",             { AL, Ib } },
1420   { "cmpS",             { eAX, Iv } },
1421   { "(bad)",            { XX } },       /* SEG DS prefix */
1422   { X86_64_TABLE (X86_64_3F) },
1423   /* 40 */
1424   { "inc{S|}",          { RMeAX } },
1425   { "inc{S|}",          { RMeCX } },
1426   { "inc{S|}",          { RMeDX } },
1427   { "inc{S|}",          { RMeBX } },
1428   { "inc{S|}",          { RMeSP } },
1429   { "inc{S|}",          { RMeBP } },
1430   { "inc{S|}",          { RMeSI } },
1431   { "inc{S|}",          { RMeDI } },
1432   /* 48 */
1433   { "dec{S|}",          { RMeAX } },
1434   { "dec{S|}",          { RMeCX } },
1435   { "dec{S|}",          { RMeDX } },
1436   { "dec{S|}",          { RMeBX } },
1437   { "dec{S|}",          { RMeSP } },
1438   { "dec{S|}",          { RMeBP } },
1439   { "dec{S|}",          { RMeSI } },
1440   { "dec{S|}",          { RMeDI } },
1441   /* 50 */
1442   { "pushV",            { RMrAX } },
1443   { "pushV",            { RMrCX } },
1444   { "pushV",            { RMrDX } },
1445   { "pushV",            { RMrBX } },
1446   { "pushV",            { RMrSP } },
1447   { "pushV",            { RMrBP } },
1448   { "pushV",            { RMrSI } },
1449   { "pushV",            { RMrDI } },
1450   /* 58 */
1451   { "popV",             { RMrAX } },
1452   { "popV",             { RMrCX } },
1453   { "popV",             { RMrDX } },
1454   { "popV",             { RMrBX } },
1455   { "popV",             { RMrSP } },
1456   { "popV",             { RMrBP } },
1457   { "popV",             { RMrSI } },
1458   { "popV",             { RMrDI } },
1459   /* 60 */
1460   { X86_64_TABLE (X86_64_60) },
1461   { X86_64_TABLE (X86_64_61) },
1462   { X86_64_TABLE (X86_64_62) },
1463   { X86_64_TABLE (X86_64_63) },
1464   { "(bad)",            { XX } },       /* seg fs */
1465   { "(bad)",            { XX } },       /* seg gs */
1466   { "(bad)",            { XX } },       /* op size prefix */
1467   { "(bad)",            { XX } },       /* adr size prefix */
1468   /* 68 */
1469   { "pushT",            { Iq } },
1470   { "imulS",            { Gv, Ev, Iv } },
1471   { "pushT",            { sIb } },
1472   { "imulS",            { Gv, Ev, sIb } },
1473   { "ins{b|}",          { Ybr, indirDX } },
1474   { X86_64_TABLE (X86_64_6D) },
1475   { "outs{b|}",         { indirDXr, Xb } },
1476   { X86_64_TABLE (X86_64_6F) },
1477   /* 70 */
1478   { "joH",              { Jb, XX, cond_jump_flag } },
1479   { "jnoH",             { Jb, XX, cond_jump_flag } },
1480   { "jbH",              { Jb, XX, cond_jump_flag } },
1481   { "jaeH",             { Jb, XX, cond_jump_flag } },
1482   { "jeH",              { Jb, XX, cond_jump_flag } },
1483   { "jneH",             { Jb, XX, cond_jump_flag } },
1484   { "jbeH",             { Jb, XX, cond_jump_flag } },
1485   { "jaH",              { Jb, XX, cond_jump_flag } },
1486   /* 78 */
1487   { "jsH",              { Jb, XX, cond_jump_flag } },
1488   { "jnsH",             { Jb, XX, cond_jump_flag } },
1489   { "jpH",              { Jb, XX, cond_jump_flag } },
1490   { "jnpH",             { Jb, XX, cond_jump_flag } },
1491   { "jlH",              { Jb, XX, cond_jump_flag } },
1492   { "jgeH",             { Jb, XX, cond_jump_flag } },
1493   { "jleH",             { Jb, XX, cond_jump_flag } },
1494   { "jgH",              { Jb, XX, cond_jump_flag } },
1495   /* 80 */
1496   { REG_TABLE (REG_80) },
1497   { REG_TABLE (REG_81) },
1498   { "(bad)",            { XX } },
1499   { REG_TABLE (REG_82) },
1500   { "testB",            { Eb, Gb } },
1501   { "testS",            { Ev, Gv } },
1502   { "xchgB",            { Eb, Gb } },
1503   { "xchgS",            { Ev, Gv } },
1504   /* 88 */
1505   { "movB",             { Eb, Gb } },
1506   { "movS",             { Ev, Gv } },
1507   { "movB",             { Gb, EbS } },
1508   { "movS",             { Gv, EvS } },
1509   { "movD",             { Sv, Sw } },
1510   { MOD_TABLE (MOD_8D) },
1511   { "movD",             { Sw, Sv } },
1512   { REG_TABLE (REG_8F) },
1513   /* 90 */
1514   { PREFIX_TABLE (PREFIX_90) },
1515   { "xchgS",            { RMeCX, eAX } },
1516   { "xchgS",            { RMeDX, eAX } },
1517   { "xchgS",            { RMeBX, eAX } },
1518   { "xchgS",            { RMeSP, eAX } },
1519   { "xchgS",            { RMeBP, eAX } },
1520   { "xchgS",            { RMeSI, eAX } },
1521   { "xchgS",            { RMeDI, eAX } },
1522   /* 98 */
1523   { "cW{t|}R",          { XX } },
1524   { "cR{t|}O",          { XX } },
1525   { X86_64_TABLE (X86_64_9A) },
1526   { "(bad)",            { XX } },       /* fwait */
1527   { "pushfT",           { XX } },
1528   { "popfT",            { XX } },
1529   { "sahf",             { XX } },
1530   { "lahf",             { XX } },
1531   /* a0 */
1532   { "mov%LB",           { AL, Ob } },
1533   { "mov%LS",           { eAX, Ov } },
1534   { "mov%LB",           { Ob, AL } },
1535   { "mov%LS",           { Ov, eAX } },
1536   { "movs{b|}",         { Ybr, Xb } },
1537   { "movs{R|}",         { Yvr, Xv } },
1538   { "cmps{b|}",         { Xb, Yb } },
1539   { "cmps{R|}",         { Xv, Yv } },
1540   /* a8 */
1541   { "testB",            { AL, Ib } },
1542   { "testS",            { eAX, Iv } },
1543   { "stosB",            { Ybr, AL } },
1544   { "stosS",            { Yvr, eAX } },
1545   { "lodsB",            { ALr, Xb } },
1546   { "lodsS",            { eAXr, Xv } },
1547   { "scasB",            { AL, Yb } },
1548   { "scasS",            { eAX, Yv } },
1549   /* b0 */
1550   { "movB",             { RMAL, Ib } },
1551   { "movB",             { RMCL, Ib } },
1552   { "movB",             { RMDL, Ib } },
1553   { "movB",             { RMBL, Ib } },
1554   { "movB",             { RMAH, Ib } },
1555   { "movB",             { RMCH, Ib } },
1556   { "movB",             { RMDH, Ib } },
1557   { "movB",             { RMBH, Ib } },
1558   /* b8 */
1559   { "mov%LV",           { RMeAX, Iv64 } },
1560   { "mov%LV",           { RMeCX, Iv64 } },
1561   { "mov%LV",           { RMeDX, Iv64 } },
1562   { "mov%LV",           { RMeBX, Iv64 } },
1563   { "mov%LV",           { RMeSP, Iv64 } },
1564   { "mov%LV",           { RMeBP, Iv64 } },
1565   { "mov%LV",           { RMeSI, Iv64 } },
1566   { "mov%LV",           { RMeDI, Iv64 } },
1567   /* c0 */
1568   { REG_TABLE (REG_C0) },
1569   { REG_TABLE (REG_C1) },
1570   { "retT",             { Iw } },
1571   { "retT",             { XX } },
1572   { X86_64_TABLE (X86_64_C4) },
1573   { X86_64_TABLE (X86_64_C5) },
1574   { REG_TABLE (REG_C6) },
1575   { REG_TABLE (REG_C7) },
1576   /* c8 */
1577   { "enterT",           { Iw, Ib } },
1578   { "leaveT",           { XX } },
1579   { "Jret{|f}P",        { Iw } },
1580   { "Jret{|f}P",        { XX } },
1581   { "int3",             { XX } },
1582   { "int",              { Ib } },
1583   { X86_64_TABLE (X86_64_CE) },
1584   { "iretP",            { XX } },
1585   /* d0 */
1586   { REG_TABLE (REG_D0) },
1587   { REG_TABLE (REG_D1) },
1588   { REG_TABLE (REG_D2) },
1589   { REG_TABLE (REG_D3) },
1590   { X86_64_TABLE (X86_64_D4) },
1591   { X86_64_TABLE (X86_64_D5) },
1592   { "(bad)",            { XX } },
1593   { "xlat",             { DSBX } },
1594   /* d8 */
1595   { FLOAT },
1596   { FLOAT },
1597   { FLOAT },
1598   { FLOAT },
1599   { FLOAT },
1600   { FLOAT },
1601   { FLOAT },
1602   { FLOAT },
1603   /* e0 */
1604   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1605   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1606   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1607   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1608   { "inB",              { AL, Ib } },
1609   { "inG",              { zAX, Ib } },
1610   { "outB",             { Ib, AL } },
1611   { "outG",             { Ib, zAX } },
1612   /* e8 */
1613   { "callT",            { Jv } },
1614   { "jmpT",             { Jv } },
1615   { X86_64_TABLE (X86_64_EA) },
1616   { "jmp",              { Jb } },
1617   { "inB",              { AL, indirDX } },
1618   { "inG",              { zAX, indirDX } },
1619   { "outB",             { indirDX, AL } },
1620   { "outG",             { indirDX, zAX } },
1621   /* f0 */
1622   { "(bad)",            { XX } },       /* lock prefix */
1623   { "icebp",            { XX } },
1624   { "(bad)",            { XX } },       /* repne */
1625   { "(bad)",            { XX } },       /* repz */
1626   { "hlt",              { XX } },
1627   { "cmc",              { XX } },
1628   { REG_TABLE (REG_F6) },
1629   { REG_TABLE (REG_F7) },
1630   /* f8 */
1631   { "clc",              { XX } },
1632   { "stc",              { XX } },
1633   { "cli",              { XX } },
1634   { "sti",              { XX } },
1635   { "cld",              { XX } },
1636   { "std",              { XX } },
1637   { REG_TABLE (REG_FE) },
1638   { REG_TABLE (REG_FF) },
1639 };
1640
1641 static const struct dis386 dis386_twobyte[] = {
1642   /* 00 */
1643   { REG_TABLE (REG_0F00 ) },
1644   { REG_TABLE (REG_0F01 ) },
1645   { "larS",             { Gv, Ew } },
1646   { "lslS",             { Gv, Ew } },
1647   { "(bad)",            { XX } },
1648   { "syscall",          { XX } },
1649   { "clts",             { XX } },
1650   { "sysretP",          { XX } },
1651   /* 08 */
1652   { "invd",             { XX } },
1653   { "wbinvd",           { XX } },
1654   { "(bad)",            { XX } },
1655   { "ud2a",             { XX } },
1656   { "(bad)",            { XX } },
1657   { REG_TABLE (REG_0F0D) },
1658   { "femms",            { XX } },
1659   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1660   /* 10 */
1661   { PREFIX_TABLE (PREFIX_0F10) },
1662   { PREFIX_TABLE (PREFIX_0F11) },
1663   { PREFIX_TABLE (PREFIX_0F12) },
1664   { MOD_TABLE (MOD_0F13) },
1665   { "unpcklpX",         { XM, EXx } },
1666   { "unpckhpX",         { XM, EXx } },
1667   { PREFIX_TABLE (PREFIX_0F16) },
1668   { MOD_TABLE (MOD_0F17) },
1669   /* 18 */
1670   { REG_TABLE (REG_0F18) },
1671   { "nopQ",             { Ev } },
1672   { "nopQ",             { Ev } },
1673   { "nopQ",             { Ev } },
1674   { "nopQ",             { Ev } },
1675   { "nopQ",             { Ev } },
1676   { "nopQ",             { Ev } },
1677   { "nopQ",             { Ev } },
1678   /* 20 */
1679   { MOD_TABLE (MOD_0F20) },
1680   { MOD_TABLE (MOD_0F21) },
1681   { MOD_TABLE (MOD_0F22) },
1682   { MOD_TABLE (MOD_0F23) },
1683   { MOD_TABLE (MOD_0F24) },
1684   { "(bad)",            { XX } },
1685   { MOD_TABLE (MOD_0F26) },
1686   { "(bad)",            { XX } },
1687   /* 28 */
1688   { "movapX",           { XM, EXx } },
1689   { "movapX",           { EXxS, XM } },
1690   { PREFIX_TABLE (PREFIX_0F2A) },
1691   { PREFIX_TABLE (PREFIX_0F2B) },
1692   { PREFIX_TABLE (PREFIX_0F2C) },
1693   { PREFIX_TABLE (PREFIX_0F2D) },
1694   { PREFIX_TABLE (PREFIX_0F2E) },
1695   { PREFIX_TABLE (PREFIX_0F2F) },
1696   /* 30 */
1697   { "wrmsr",            { XX } },
1698   { "rdtsc",            { XX } },
1699   { "rdmsr",            { XX } },
1700   { "rdpmc",            { XX } },
1701   { "sysenter",         { XX } },
1702   { "sysexit",          { XX } },
1703   { "(bad)",            { XX } },
1704   { "getsec",           { XX } },
1705   /* 38 */
1706   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1707   { "(bad)",            { XX } },
1708   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1709   { "(bad)",            { XX } },
1710   { "(bad)",            { XX } },
1711   { "(bad)",            { XX } },
1712   { "(bad)",            { XX } },
1713   { "(bad)",            { XX } },
1714   /* 40 */
1715   { "cmovoS",           { Gv, Ev } },
1716   { "cmovnoS",          { Gv, Ev } },
1717   { "cmovbS",           { Gv, Ev } },
1718   { "cmovaeS",          { Gv, Ev } },
1719   { "cmoveS",           { Gv, Ev } },
1720   { "cmovneS",          { Gv, Ev } },
1721   { "cmovbeS",          { Gv, Ev } },
1722   { "cmovaS",           { Gv, Ev } },
1723   /* 48 */
1724   { "cmovsS",           { Gv, Ev } },
1725   { "cmovnsS",          { Gv, Ev } },
1726   { "cmovpS",           { Gv, Ev } },
1727   { "cmovnpS",          { Gv, Ev } },
1728   { "cmovlS",           { Gv, Ev } },
1729   { "cmovgeS",          { Gv, Ev } },
1730   { "cmovleS",          { Gv, Ev } },
1731   { "cmovgS",           { Gv, Ev } },
1732   /* 50 */
1733   { MOD_TABLE (MOD_0F51) },
1734   { PREFIX_TABLE (PREFIX_0F51) },
1735   { PREFIX_TABLE (PREFIX_0F52) },
1736   { PREFIX_TABLE (PREFIX_0F53) },
1737   { "andpX",            { XM, EXx } },
1738   { "andnpX",           { XM, EXx } },
1739   { "orpX",             { XM, EXx } },
1740   { "xorpX",            { XM, EXx } },
1741   /* 58 */
1742   { PREFIX_TABLE (PREFIX_0F58) },
1743   { PREFIX_TABLE (PREFIX_0F59) },
1744   { PREFIX_TABLE (PREFIX_0F5A) },
1745   { PREFIX_TABLE (PREFIX_0F5B) },
1746   { PREFIX_TABLE (PREFIX_0F5C) },
1747   { PREFIX_TABLE (PREFIX_0F5D) },
1748   { PREFIX_TABLE (PREFIX_0F5E) },
1749   { PREFIX_TABLE (PREFIX_0F5F) },
1750   /* 60 */
1751   { PREFIX_TABLE (PREFIX_0F60) },
1752   { PREFIX_TABLE (PREFIX_0F61) },
1753   { PREFIX_TABLE (PREFIX_0F62) },
1754   { "packsswb",         { MX, EM } },
1755   { "pcmpgtb",          { MX, EM } },
1756   { "pcmpgtw",          { MX, EM } },
1757   { "pcmpgtd",          { MX, EM } },
1758   { "packuswb",         { MX, EM } },
1759   /* 68 */
1760   { "punpckhbw",        { MX, EM } },
1761   { "punpckhwd",        { MX, EM } },
1762   { "punpckhdq",        { MX, EM } },
1763   { "packssdw",         { MX, EM } },
1764   { PREFIX_TABLE (PREFIX_0F6C) },
1765   { PREFIX_TABLE (PREFIX_0F6D) },
1766   { "movK",             { MX, Edq } },
1767   { PREFIX_TABLE (PREFIX_0F6F) },
1768   /* 70 */
1769   { PREFIX_TABLE (PREFIX_0F70) },
1770   { REG_TABLE (REG_0F71) },
1771   { REG_TABLE (REG_0F72) },
1772   { REG_TABLE (REG_0F73) },
1773   { "pcmpeqb",          { MX, EM } },
1774   { "pcmpeqw",          { MX, EM } },
1775   { "pcmpeqd",          { MX, EM } },
1776   { "emms",             { XX } },
1777   /* 78 */
1778   { PREFIX_TABLE (PREFIX_0F78) },
1779   { PREFIX_TABLE (PREFIX_0F79) },
1780   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1781   { "(bad)",            { XX } },
1782   { PREFIX_TABLE (PREFIX_0F7C) },
1783   { PREFIX_TABLE (PREFIX_0F7D) },
1784   { PREFIX_TABLE (PREFIX_0F7E) },
1785   { PREFIX_TABLE (PREFIX_0F7F) },
1786   /* 80 */
1787   { "joH",              { Jv, XX, cond_jump_flag } },
1788   { "jnoH",             { Jv, XX, cond_jump_flag } },
1789   { "jbH",              { Jv, XX, cond_jump_flag } },
1790   { "jaeH",             { Jv, XX, cond_jump_flag } },
1791   { "jeH",              { Jv, XX, cond_jump_flag } },
1792   { "jneH",             { Jv, XX, cond_jump_flag } },
1793   { "jbeH",             { Jv, XX, cond_jump_flag } },
1794   { "jaH",              { Jv, XX, cond_jump_flag } },
1795   /* 88 */
1796   { "jsH",              { Jv, XX, cond_jump_flag } },
1797   { "jnsH",             { Jv, XX, cond_jump_flag } },
1798   { "jpH",              { Jv, XX, cond_jump_flag } },
1799   { "jnpH",             { Jv, XX, cond_jump_flag } },
1800   { "jlH",              { Jv, XX, cond_jump_flag } },
1801   { "jgeH",             { Jv, XX, cond_jump_flag } },
1802   { "jleH",             { Jv, XX, cond_jump_flag } },
1803   { "jgH",              { Jv, XX, cond_jump_flag } },
1804   /* 90 */
1805   { "seto",             { Eb } },
1806   { "setno",            { Eb } },
1807   { "setb",             { Eb } },
1808   { "setae",            { Eb } },
1809   { "sete",             { Eb } },
1810   { "setne",            { Eb } },
1811   { "setbe",            { Eb } },
1812   { "seta",             { Eb } },
1813   /* 98 */
1814   { "sets",             { Eb } },
1815   { "setns",            { Eb } },
1816   { "setp",             { Eb } },
1817   { "setnp",            { Eb } },
1818   { "setl",             { Eb } },
1819   { "setge",            { Eb } },
1820   { "setle",            { Eb } },
1821   { "setg",             { Eb } },
1822   /* a0 */
1823   { "pushT",            { fs } },
1824   { "popT",             { fs } },
1825   { "cpuid",            { XX } },
1826   { "btS",              { Ev, Gv } },
1827   { "shldS",            { Ev, Gv, Ib } },
1828   { "shldS",            { Ev, Gv, CL } },
1829   { REG_TABLE (REG_0FA6) },
1830   { REG_TABLE (REG_0FA7) },
1831   /* a8 */
1832   { "pushT",            { gs } },
1833   { "popT",             { gs } },
1834   { "rsm",              { XX } },
1835   { "btsS",             { Ev, Gv } },
1836   { "shrdS",            { Ev, Gv, Ib } },
1837   { "shrdS",            { Ev, Gv, CL } },
1838   { REG_TABLE (REG_0FAE) },
1839   { "imulS",            { Gv, Ev } },
1840   /* b0 */
1841   { "cmpxchgB",         { Eb, Gb } },
1842   { "cmpxchgS",         { Ev, Gv } },
1843   { MOD_TABLE (MOD_0FB2) },
1844   { "btrS",             { Ev, Gv } },
1845   { MOD_TABLE (MOD_0FB4) },
1846   { MOD_TABLE (MOD_0FB5) },
1847   { "movz{bR|x}",       { Gv, Eb } },
1848   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
1849   /* b8 */
1850   { PREFIX_TABLE (PREFIX_0FB8) },
1851   { "ud2b",             { XX } },
1852   { REG_TABLE (REG_0FBA) },
1853   { "btcS",             { Ev, Gv } },
1854   { "bsfS",             { Gv, Ev } },
1855   { PREFIX_TABLE (PREFIX_0FBD) },
1856   { "movs{bR|x}",       { Gv, Eb } },
1857   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
1858   /* c0 */
1859   { "xaddB",            { Eb, Gb } },
1860   { "xaddS",            { Ev, Gv } },
1861   { PREFIX_TABLE (PREFIX_0FC2) },
1862   { PREFIX_TABLE (PREFIX_0FC3) },
1863   { "pinsrw",           { MX, Edqw, Ib } },
1864   { "pextrw",           { Gdq, MS, Ib } },
1865   { "shufpX",           { XM, EXx, Ib } },
1866   { REG_TABLE (REG_0FC7) },
1867   /* c8 */
1868   { "bswap",            { RMeAX } },
1869   { "bswap",            { RMeCX } },
1870   { "bswap",            { RMeDX } },
1871   { "bswap",            { RMeBX } },
1872   { "bswap",            { RMeSP } },
1873   { "bswap",            { RMeBP } },
1874   { "bswap",            { RMeSI } },
1875   { "bswap",            { RMeDI } },
1876   /* d0 */
1877   { PREFIX_TABLE (PREFIX_0FD0) },
1878   { "psrlw",            { MX, EM } },
1879   { "psrld",            { MX, EM } },
1880   { "psrlq",            { MX, EM } },
1881   { "paddq",            { MX, EM } },
1882   { "pmullw",           { MX, EM } },
1883   { PREFIX_TABLE (PREFIX_0FD6) },
1884   { MOD_TABLE (MOD_0FD7) },
1885   /* d8 */
1886   { "psubusb",          { MX, EM } },
1887   { "psubusw",          { MX, EM } },
1888   { "pminub",           { MX, EM } },
1889   { "pand",             { MX, EM } },
1890   { "paddusb",          { MX, EM } },
1891   { "paddusw",          { MX, EM } },
1892   { "pmaxub",           { MX, EM } },
1893   { "pandn",            { MX, EM } },
1894   /* e0 */
1895   { "pavgb",            { MX, EM } },
1896   { "psraw",            { MX, EM } },
1897   { "psrad",            { MX, EM } },
1898   { "pavgw",            { MX, EM } },
1899   { "pmulhuw",          { MX, EM } },
1900   { "pmulhw",           { MX, EM } },
1901   { PREFIX_TABLE (PREFIX_0FE6) },
1902   { PREFIX_TABLE (PREFIX_0FE7) },
1903   /* e8 */
1904   { "psubsb",           { MX, EM } },
1905   { "psubsw",           { MX, EM } },
1906   { "pminsw",           { MX, EM } },
1907   { "por",              { MX, EM } },
1908   { "paddsb",           { MX, EM } },
1909   { "paddsw",           { MX, EM } },
1910   { "pmaxsw",           { MX, EM } },
1911   { "pxor",             { MX, EM } },
1912   /* f0 */
1913   { PREFIX_TABLE (PREFIX_0FF0) },
1914   { "psllw",            { MX, EM } },
1915   { "pslld",            { MX, EM } },
1916   { "psllq",            { MX, EM } },
1917   { "pmuludq",          { MX, EM } },
1918   { "pmaddwd",          { MX, EM } },
1919   { "psadbw",           { MX, EM } },
1920   { PREFIX_TABLE (PREFIX_0FF7) },
1921   /* f8 */
1922   { "psubb",            { MX, EM } },
1923   { "psubw",            { MX, EM } },
1924   { "psubd",            { MX, EM } },
1925   { "psubq",            { MX, EM } },
1926   { "paddb",            { MX, EM } },
1927   { "paddw",            { MX, EM } },
1928   { "paddd",            { MX, EM } },
1929   { "(bad)",            { XX } },
1930 };
1931
1932 static const unsigned char onebyte_has_modrm[256] = {
1933   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1934   /*       -------------------------------        */
1935   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1936   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1937   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1938   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1939   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1940   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1941   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1942   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1943   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1944   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1945   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1946   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1947   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1948   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1949   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1950   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
1951   /*       -------------------------------        */
1952   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1953 };
1954
1955 static const unsigned char twobyte_has_modrm[256] = {
1956   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1957   /*       -------------------------------        */
1958   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1959   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1960   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1961   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1962   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1963   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1964   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1965   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1966   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1967   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1968   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1969   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1970   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1971   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1972   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1973   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
1974   /*       -------------------------------        */
1975   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1976 };
1977
1978 static char obuf[100];
1979 static char *obufp;
1980 static char *mnemonicendp;
1981 static char scratchbuf[100];
1982 static unsigned char *start_codep;
1983 static unsigned char *insn_codep;
1984 static unsigned char *codep;
1985 static const char *lock_prefix;
1986 static const char *data_prefix;
1987 static const char *addr_prefix;
1988 static const char *repz_prefix;
1989 static const char *repnz_prefix;
1990 static disassemble_info *the_info;
1991 static struct
1992   {
1993     int mod;
1994     int reg;
1995     int rm;
1996   }
1997 modrm;
1998 static unsigned char need_modrm;
1999 static struct
2000   {
2001     int register_specifier;
2002     int length;
2003     int prefix;
2004     int w;
2005   }
2006 vex;
2007 static unsigned char need_vex;
2008 static unsigned char need_vex_reg;
2009 static unsigned char vex_w_done;
2010
2011 struct op
2012   {
2013     const char *name;
2014     unsigned int len;
2015   };
2016
2017 /* If we are accessing mod/rm/reg without need_modrm set, then the
2018    values are stale.  Hitting this abort likely indicates that you
2019    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2020 #define MODRM_CHECK  if (!need_modrm) abort ()
2021
2022 static const char **names64;
2023 static const char **names32;
2024 static const char **names16;
2025 static const char **names8;
2026 static const char **names8rex;
2027 static const char **names_seg;
2028 static const char *index64;
2029 static const char *index32;
2030 static const char **index16;
2031
2032 static const char *intel_names64[] = {
2033   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2034   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2035 };
2036 static const char *intel_names32[] = {
2037   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2038   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2039 };
2040 static const char *intel_names16[] = {
2041   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2042   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2043 };
2044 static const char *intel_names8[] = {
2045   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2046 };
2047 static const char *intel_names8rex[] = {
2048   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2049   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2050 };
2051 static const char *intel_names_seg[] = {
2052   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2053 };
2054 static const char *intel_index64 = "riz";
2055 static const char *intel_index32 = "eiz";
2056 static const char *intel_index16[] = {
2057   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2058 };
2059
2060 static const char *att_names64[] = {
2061   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2062   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2063 };
2064 static const char *att_names32[] = {
2065   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2066   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2067 };
2068 static const char *att_names16[] = {
2069   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2070   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2071 };
2072 static const char *att_names8[] = {
2073   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2074 };
2075 static const char *att_names8rex[] = {
2076   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2077   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2078 };
2079 static const char *att_names_seg[] = {
2080   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2081 };
2082 static const char *att_index64 = "%riz";
2083 static const char *att_index32 = "%eiz";
2084 static const char *att_index16[] = {
2085   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2086 };
2087
2088 static const struct dis386 reg_table[][8] = {
2089   /* REG_80 */
2090   {
2091     { "addA",   { Eb, Ib } },
2092     { "orA",    { Eb, Ib } },
2093     { "adcA",   { Eb, Ib } },
2094     { "sbbA",   { Eb, Ib } },
2095     { "andA",   { Eb, Ib } },
2096     { "subA",   { Eb, Ib } },
2097     { "xorA",   { Eb, Ib } },
2098     { "cmpA",   { Eb, Ib } },
2099   },
2100   /* REG_81 */
2101   {
2102     { "addQ",   { Ev, Iv } },
2103     { "orQ",    { Ev, Iv } },
2104     { "adcQ",   { Ev, Iv } },
2105     { "sbbQ",   { Ev, Iv } },
2106     { "andQ",   { Ev, Iv } },
2107     { "subQ",   { Ev, Iv } },
2108     { "xorQ",   { Ev, Iv } },
2109     { "cmpQ",   { Ev, Iv } },
2110   },
2111   /* REG_82 */
2112   {
2113     { "addQ",   { Ev, sIb } },
2114     { "orQ",    { Ev, sIb } },
2115     { "adcQ",   { Ev, sIb } },
2116     { "sbbQ",   { Ev, sIb } },
2117     { "andQ",   { Ev, sIb } },
2118     { "subQ",   { Ev, sIb } },
2119     { "xorQ",   { Ev, sIb } },
2120     { "cmpQ",   { Ev, sIb } },
2121   },
2122   /* REG_8F */
2123   {
2124     { "popU",   { stackEv } },
2125     { "(bad)",  { XX } },
2126     { "(bad)",  { XX } },
2127     { "(bad)",  { XX } },
2128     { "(bad)",  { XX } },
2129     { "(bad)",  { XX } },
2130     { "(bad)",  { XX } },
2131     { "(bad)",  { XX } },
2132   },
2133   /* REG_C0 */
2134   {
2135     { "rolA",   { Eb, Ib } },
2136     { "rorA",   { Eb, Ib } },
2137     { "rclA",   { Eb, Ib } },
2138     { "rcrA",   { Eb, Ib } },
2139     { "shlA",   { Eb, Ib } },
2140     { "shrA",   { Eb, Ib } },
2141     { "(bad)",  { XX } },
2142     { "sarA",   { Eb, Ib } },
2143   },
2144   /* REG_C1 */
2145   {
2146     { "rolQ",   { Ev, Ib } },
2147     { "rorQ",   { Ev, Ib } },
2148     { "rclQ",   { Ev, Ib } },
2149     { "rcrQ",   { Ev, Ib } },
2150     { "shlQ",   { Ev, Ib } },
2151     { "shrQ",   { Ev, Ib } },
2152     { "(bad)",  { XX } },
2153     { "sarQ",   { Ev, Ib } },
2154   },
2155   /* REG_C6 */
2156   {
2157     { "movA",   { Eb, Ib } },
2158     { "(bad)",  { XX } },
2159     { "(bad)",  { XX } },
2160     { "(bad)",  { XX } },
2161     { "(bad)",  { XX } },
2162     { "(bad)",  { XX } },
2163     { "(bad)",  { XX } },
2164     { "(bad)",  { XX } },
2165   },
2166   /* REG_C7 */
2167   {
2168     { "movQ",   { Ev, Iv } },
2169     { "(bad)",  { XX } },
2170     { "(bad)",  { XX } },
2171     { "(bad)",  { XX } },
2172     { "(bad)",  { XX } },
2173     { "(bad)",  { XX } },
2174     { "(bad)",  { XX } },
2175     { "(bad)",  { XX } },
2176   },
2177   /* REG_D0 */
2178   {
2179     { "rolA",   { Eb, I1 } },
2180     { "rorA",   { Eb, I1 } },
2181     { "rclA",   { Eb, I1 } },
2182     { "rcrA",   { Eb, I1 } },
2183     { "shlA",   { Eb, I1 } },
2184     { "shrA",   { Eb, I1 } },
2185     { "(bad)",  { XX } },
2186     { "sarA",   { Eb, I1 } },
2187   },
2188   /* REG_D1 */
2189   {
2190     { "rolQ",   { Ev, I1 } },
2191     { "rorQ",   { Ev, I1 } },
2192     { "rclQ",   { Ev, I1 } },
2193     { "rcrQ",   { Ev, I1 } },
2194     { "shlQ",   { Ev, I1 } },
2195     { "shrQ",   { Ev, I1 } },
2196     { "(bad)",  { XX } },
2197     { "sarQ",   { Ev, I1 } },
2198   },
2199   /* REG_D2 */
2200   {
2201     { "rolA",   { Eb, CL } },
2202     { "rorA",   { Eb, CL } },
2203     { "rclA",   { Eb, CL } },
2204     { "rcrA",   { Eb, CL } },
2205     { "shlA",   { Eb, CL } },
2206     { "shrA",   { Eb, CL } },
2207     { "(bad)",  { XX } },
2208     { "sarA",   { Eb, CL } },
2209   },
2210   /* REG_D3 */
2211   {
2212     { "rolQ",   { Ev, CL } },
2213     { "rorQ",   { Ev, CL } },
2214     { "rclQ",   { Ev, CL } },
2215     { "rcrQ",   { Ev, CL } },
2216     { "shlQ",   { Ev, CL } },
2217     { "shrQ",   { Ev, CL } },
2218     { "(bad)",  { XX } },
2219     { "sarQ",   { Ev, CL } },
2220   },
2221   /* REG_F6 */
2222   {
2223     { "testA",  { Eb, Ib } },
2224     { "(bad)",  { XX } },
2225     { "notA",   { Eb } },
2226     { "negA",   { Eb } },
2227     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2228     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2229     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2230     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2231   },
2232   /* REG_F7 */
2233   {
2234     { "testQ",  { Ev, Iv } },
2235     { "(bad)",  { XX } },
2236     { "notQ",   { Ev } },
2237     { "negQ",   { Ev } },
2238     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2239     { "imulQ",  { Ev } },
2240     { "divQ",   { Ev } },
2241     { "idivQ",  { Ev } },
2242   },
2243   /* REG_FE */
2244   {
2245     { "incA",   { Eb } },
2246     { "decA",   { Eb } },
2247     { "(bad)",  { XX } },
2248     { "(bad)",  { XX } },
2249     { "(bad)",  { XX } },
2250     { "(bad)",  { XX } },
2251     { "(bad)",  { XX } },
2252     { "(bad)",  { XX } },
2253   },
2254   /* REG_FF */
2255   {
2256     { "incQ",   { Ev } },
2257     { "decQ",   { Ev } },
2258     { "callT",  { indirEv } },
2259     { "JcallT", { indirEp } },
2260     { "jmpT",   { indirEv } },
2261     { "JjmpT",  { indirEp } },
2262     { "pushU",  { stackEv } },
2263     { "(bad)",  { XX } },
2264   },
2265   /* REG_0F00 */
2266   {
2267     { "sldtD",  { Sv } },
2268     { "strD",   { Sv } },
2269     { "lldt",   { Ew } },
2270     { "ltr",    { Ew } },
2271     { "verr",   { Ew } },
2272     { "verw",   { Ew } },
2273     { "(bad)",  { XX } },
2274     { "(bad)",  { XX } },
2275   },
2276   /* REG_0F01 */
2277   {
2278     { MOD_TABLE (MOD_0F01_REG_0) },
2279     { MOD_TABLE (MOD_0F01_REG_1) },
2280     { MOD_TABLE (MOD_0F01_REG_2) },
2281     { MOD_TABLE (MOD_0F01_REG_3) },
2282     { "smswD",  { Sv } },
2283     { "(bad)",  { XX } },
2284     { "lmsw",   { Ew } },
2285     { MOD_TABLE (MOD_0F01_REG_7) },
2286   },
2287   /* REG_0F0D */
2288   {
2289     { "prefetch",       { Eb } },
2290     { "prefetchw",      { Eb } },
2291     { "(bad)",          { XX } },
2292     { "(bad)",          { XX } },
2293     { "(bad)",          { XX } },
2294     { "(bad)",          { XX } },
2295     { "(bad)",          { XX } },
2296     { "(bad)",          { XX } },
2297   },
2298   /* REG_0F18 */
2299   {
2300     { MOD_TABLE (MOD_0F18_REG_0) },
2301     { MOD_TABLE (MOD_0F18_REG_1) },
2302     { MOD_TABLE (MOD_0F18_REG_2) },
2303     { MOD_TABLE (MOD_0F18_REG_3) },
2304     { "(bad)",  { XX } },
2305     { "(bad)",  { XX } },
2306     { "(bad)",  { XX } },
2307     { "(bad)",  { XX } },
2308   },
2309   /* REG_0F71 */
2310   {
2311     { "(bad)",  { XX } },
2312     { "(bad)",  { XX } },
2313     { MOD_TABLE (MOD_0F71_REG_2) },
2314     { "(bad)",  { XX } },
2315     { MOD_TABLE (MOD_0F71_REG_4) },
2316     { "(bad)",  { XX } },
2317     { MOD_TABLE (MOD_0F71_REG_6) },
2318     { "(bad)",  { XX } },
2319   },
2320   /* REG_0F72 */
2321   {
2322     { "(bad)",  { XX } },
2323     { "(bad)",  { XX } },
2324     { MOD_TABLE (MOD_0F72_REG_2) },
2325     { "(bad)",  { XX } },
2326     { MOD_TABLE (MOD_0F72_REG_4) },
2327     { "(bad)",  { XX } },
2328     { MOD_TABLE (MOD_0F72_REG_6) },
2329     { "(bad)",  { XX } },
2330   },
2331   /* REG_0F73 */
2332   {
2333     { "(bad)",  { XX } },
2334     { "(bad)",  { XX } },
2335     { MOD_TABLE (MOD_0F73_REG_2) },
2336     { MOD_TABLE (MOD_0F73_REG_3) },
2337     { "(bad)",  { XX } },
2338     { "(bad)",  { XX } },
2339     { MOD_TABLE (MOD_0F73_REG_6) },
2340     { MOD_TABLE (MOD_0F73_REG_7) },
2341   },
2342   /* REG_0FA6 */
2343   {
2344     { "montmul",        { { OP_0f07, 0 } } },
2345     { "xsha1",          { { OP_0f07, 0 } } },
2346     { "xsha256",        { { OP_0f07, 0 } } },
2347     { "(bad)",          { { OP_0f07, 0 } } },
2348     { "(bad)",          { { OP_0f07, 0 } } },
2349     { "(bad)",          { { OP_0f07, 0 } } },
2350     { "(bad)",          { { OP_0f07, 0 } } },
2351     { "(bad)",          { { OP_0f07, 0 } } },
2352   },
2353   /* REG_0FA7 */
2354   {
2355     { "xstore-rng",     { { OP_0f07, 0 } } },
2356     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2357     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2358     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2359     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2360     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2361     { "(bad)",          { { OP_0f07, 0 } } },
2362     { "(bad)",          { { OP_0f07, 0 } } },
2363   },
2364   /* REG_0FAE */
2365   {
2366     { MOD_TABLE (MOD_0FAE_REG_0) },
2367     { MOD_TABLE (MOD_0FAE_REG_1) },
2368     { MOD_TABLE (MOD_0FAE_REG_2) },
2369     { MOD_TABLE (MOD_0FAE_REG_3) },
2370     { MOD_TABLE (MOD_0FAE_REG_4) },
2371     { MOD_TABLE (MOD_0FAE_REG_5) },
2372     { MOD_TABLE (MOD_0FAE_REG_6) },
2373     { MOD_TABLE (MOD_0FAE_REG_7) },
2374   },
2375   /* REG_0FBA */
2376   {
2377     { "(bad)",  { XX } },
2378     { "(bad)",  { XX } },
2379     { "(bad)",  { XX } },
2380     { "(bad)",  { XX } },
2381     { "btQ",    { Ev, Ib } },
2382     { "btsQ",   { Ev, Ib } },
2383     { "btrQ",   { Ev, Ib } },
2384     { "btcQ",   { Ev, Ib } },
2385   },
2386   /* REG_0FC7 */
2387   {
2388     { "(bad)",  { XX } },
2389     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2390     { "(bad)",  { XX } },
2391     { "(bad)",  { XX } },
2392     { "(bad)",  { XX } },
2393     { "(bad)",  { XX } },
2394     { MOD_TABLE (MOD_0FC7_REG_6) },
2395     { MOD_TABLE (MOD_0FC7_REG_7) },
2396   },
2397   /* REG_VEX_71 */
2398   {
2399     { "(bad)",  { XX } },
2400     { "(bad)",  { XX } },
2401     { MOD_TABLE (MOD_VEX_71_REG_2) },
2402     { "(bad)",  { XX } },
2403     { MOD_TABLE (MOD_VEX_71_REG_4) },
2404     { "(bad)",  { XX } },
2405     { MOD_TABLE (MOD_VEX_71_REG_6) },
2406     { "(bad)",  { XX } },
2407   },
2408   /* REG_VEX_72 */
2409   {
2410     { "(bad)",  { XX } },
2411     { "(bad)",  { XX } },
2412     { MOD_TABLE (MOD_VEX_72_REG_2) },
2413     { "(bad)",  { XX } },
2414     { MOD_TABLE (MOD_VEX_72_REG_4) },
2415     { "(bad)",  { XX } },
2416     { MOD_TABLE (MOD_VEX_72_REG_6) },
2417     { "(bad)",  { XX } },
2418   },
2419   /* REG_VEX_73 */
2420   {
2421     { "(bad)",  { XX } },
2422     { "(bad)",  { XX } },
2423     { MOD_TABLE (MOD_VEX_73_REG_2) },
2424     { MOD_TABLE (MOD_VEX_73_REG_3) },
2425     { "(bad)",  { XX } },
2426     { "(bad)",  { XX } },
2427     { MOD_TABLE (MOD_VEX_73_REG_6) },
2428     { MOD_TABLE (MOD_VEX_73_REG_7) },
2429   },
2430   /* REG_VEX_AE */
2431   {
2432     { "(bad)",  { XX } },
2433     { "(bad)",  { XX } },
2434     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2435     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2436     { "(bad)",  { XX } },
2437     { "(bad)",  { XX } },
2438     { "(bad)",  { XX } },
2439     { "(bad)",  { XX } },
2440   },
2441 };
2442
2443 static const struct dis386 prefix_table[][4] = {
2444   /* PREFIX_90 */
2445   {
2446     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2447     { "pause", { XX } },
2448     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2449     { "(bad)", { XX } },
2450   },
2451
2452   /* PREFIX_0F10 */
2453   {
2454     { "movups", { XM, EXx } },
2455     { "movss",  { XM, EXd } },
2456     { "movupd", { XM, EXx } },
2457     { "movsd",  { XM, EXq } },
2458   },
2459
2460   /* PREFIX_0F11 */
2461   {
2462     { "movups", { EXxS, XM } },
2463     { "movss",  { EXdS, XM } },
2464     { "movupd", { EXxS, XM } },
2465     { "movsd",  { EXqS, XM } },
2466   },
2467
2468   /* PREFIX_0F12 */
2469   {
2470     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2471     { "movsldup", { XM, EXx } },
2472     { "movlpd", { XM, EXq } },
2473     { "movddup", { XM, EXq } },
2474   },
2475
2476   /* PREFIX_0F16 */
2477   {
2478     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2479     { "movshdup", { XM, EXx } },
2480     { "movhpd", { XM, EXq } },
2481     { "(bad)",  { XX } },
2482   },
2483
2484   /* PREFIX_0F2A */
2485   {
2486     { "cvtpi2ps", { XM, EMCq } },
2487     { "cvtsi2ss%LQ", { XM, Ev } },
2488     { "cvtpi2pd", { XM, EMCq } },
2489     { "cvtsi2sd%LQ", { XM, Ev } },
2490   },
2491
2492   /* PREFIX_0F2B */
2493   {
2494     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2495     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2496     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2497     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2498   },
2499
2500   /* PREFIX_0F2C */
2501   {
2502     { "cvttps2pi", { MXC, EXq } },
2503     { "cvttss2siY", { Gv, EXd } },
2504     { "cvttpd2pi", { MXC, EXx } },
2505     { "cvttsd2siY", { Gv, EXq } },
2506   },
2507
2508   /* PREFIX_0F2D */
2509   {
2510     { "cvtps2pi", { MXC, EXq } },
2511     { "cvtss2siY", { Gv, EXd } },
2512     { "cvtpd2pi", { MXC, EXx } },
2513     { "cvtsd2siY", { Gv, EXq } },
2514   },
2515
2516   /* PREFIX_0F2E */
2517   {
2518     { "ucomiss",{ XM, EXd } },
2519     { "(bad)",  { XX } },
2520     { "ucomisd",{ XM, EXq } },
2521     { "(bad)",  { XX } },
2522   },
2523
2524   /* PREFIX_0F2F */
2525   {
2526     { "comiss", { XM, EXd } },
2527     { "(bad)",  { XX } },
2528     { "comisd", { XM, EXq } },
2529     { "(bad)",  { XX } },
2530   },
2531
2532   /* PREFIX_0F51 */
2533   {
2534     { "sqrtps", { XM, EXx } },
2535     { "sqrtss", { XM, EXd } },
2536     { "sqrtpd", { XM, EXx } },
2537     { "sqrtsd", { XM, EXq } },
2538   },
2539
2540   /* PREFIX_0F52 */
2541   {
2542     { "rsqrtps",{ XM, EXx } },
2543     { "rsqrtss",{ XM, EXd } },
2544     { "(bad)",  { XX } },
2545     { "(bad)",  { XX } },
2546   },
2547
2548   /* PREFIX_0F53 */
2549   {
2550     { "rcpps",  { XM, EXx } },
2551     { "rcpss",  { XM, EXd } },
2552     { "(bad)",  { XX } },
2553     { "(bad)",  { XX } },
2554   },
2555
2556   /* PREFIX_0F58 */
2557   {
2558     { "addps", { XM, EXx } },
2559     { "addss", { XM, EXd } },
2560     { "addpd", { XM, EXx } },
2561     { "addsd", { XM, EXq } },
2562   },
2563
2564   /* PREFIX_0F59 */
2565   {
2566     { "mulps",  { XM, EXx } },
2567     { "mulss",  { XM, EXd } },
2568     { "mulpd",  { XM, EXx } },
2569     { "mulsd",  { XM, EXq } },
2570   },
2571
2572   /* PREFIX_0F5A */
2573   {
2574     { "cvtps2pd", { XM, EXq } },
2575     { "cvtss2sd", { XM, EXd } },
2576     { "cvtpd2ps", { XM, EXx } },
2577     { "cvtsd2ss", { XM, EXq } },
2578   },
2579
2580   /* PREFIX_0F5B */
2581   {
2582     { "cvtdq2ps", { XM, EXx } },
2583     { "cvttps2dq", { XM, EXx } },
2584     { "cvtps2dq", { XM, EXx } },
2585     { "(bad)",  { XX } },
2586   },
2587
2588   /* PREFIX_0F5C */
2589   {
2590     { "subps",  { XM, EXx } },
2591     { "subss",  { XM, EXd } },
2592     { "subpd",  { XM, EXx } },
2593     { "subsd",  { XM, EXq } },
2594   },
2595
2596   /* PREFIX_0F5D */
2597   {
2598     { "minps",  { XM, EXx } },
2599     { "minss",  { XM, EXd } },
2600     { "minpd",  { XM, EXx } },
2601     { "minsd",  { XM, EXq } },
2602   },
2603
2604   /* PREFIX_0F5E */
2605   {
2606     { "divps",  { XM, EXx } },
2607     { "divss",  { XM, EXd } },
2608     { "divpd",  { XM, EXx } },
2609     { "divsd",  { XM, EXq } },
2610   },
2611
2612   /* PREFIX_0F5F */
2613   {
2614     { "maxps",  { XM, EXx } },
2615     { "maxss",  { XM, EXd } },
2616     { "maxpd",  { XM, EXx } },
2617     { "maxsd",  { XM, EXq } },
2618   },
2619
2620   /* PREFIX_0F60 */
2621   {
2622     { "punpcklbw",{ MX, EMd } },
2623     { "(bad)",  { XX } },
2624     { "punpcklbw",{ MX, EMx } },
2625     { "(bad)",  { XX } },
2626   },
2627
2628   /* PREFIX_0F61 */
2629   {
2630     { "punpcklwd",{ MX, EMd } },
2631     { "(bad)",  { XX } },
2632     { "punpcklwd",{ MX, EMx } },
2633     { "(bad)",  { XX } },
2634   },
2635
2636   /* PREFIX_0F62 */
2637   {
2638     { "punpckldq",{ MX, EMd } },
2639     { "(bad)",  { XX } },
2640     { "punpckldq",{ MX, EMx } },
2641     { "(bad)",  { XX } },
2642   },
2643
2644   /* PREFIX_0F6C */
2645   {
2646     { "(bad)",  { XX } },
2647     { "(bad)",  { XX } },
2648     { "punpcklqdq", { XM, EXx } },
2649     { "(bad)",  { XX } },
2650   },
2651
2652   /* PREFIX_0F6D */
2653   {
2654     { "(bad)",  { XX } },
2655     { "(bad)",  { XX } },
2656     { "punpckhqdq", { XM, EXx } },
2657     { "(bad)",  { XX } },
2658   },
2659
2660   /* PREFIX_0F6F */
2661   {
2662     { "movq",   { MX, EM } },
2663     { "movdqu", { XM, EXx } },
2664     { "movdqa", { XM, EXx } },
2665     { "(bad)",  { XX } },
2666   },
2667
2668   /* PREFIX_0F70 */
2669   {
2670     { "pshufw", { MX, EM, Ib } },
2671     { "pshufhw",{ XM, EXx, Ib } },
2672     { "pshufd", { XM, EXx, Ib } },
2673     { "pshuflw",{ XM, EXx, Ib } },
2674   },
2675
2676   /* PREFIX_0F73_REG_3 */
2677   {
2678     { "(bad)",  { XX } },
2679     { "(bad)",  { XX } },
2680     { "psrldq", { XS, Ib } },
2681     { "(bad)",  { XX } },
2682   },
2683
2684   /* PREFIX_0F73_REG_7 */
2685   {
2686     { "(bad)",  { XX } },
2687     { "(bad)",  { XX } },
2688     { "pslldq", { XS, Ib } },
2689     { "(bad)",  { XX } },
2690   },
2691
2692   /* PREFIX_0F78 */
2693   {
2694     {"vmread",  { Em, Gm } },
2695     {"(bad)",   { XX } },
2696     {"extrq",   { XS, Ib, Ib } },
2697     {"insertq", { XM, XS, Ib, Ib } },
2698   },
2699
2700   /* PREFIX_0F79 */
2701   {
2702     {"vmwrite", { Gm, Em } },
2703     {"(bad)",   { XX } },
2704     {"extrq",   { XM, XS } },
2705     {"insertq", { XM, XS } },
2706   },
2707
2708   /* PREFIX_0F7C */
2709   {
2710     { "(bad)",  { XX } },
2711     { "(bad)",  { XX } },
2712     { "haddpd", { XM, EXx } },
2713     { "haddps", { XM, EXx } },
2714   },
2715
2716   /* PREFIX_0F7D */
2717   {
2718     { "(bad)",  { XX } },
2719     { "(bad)",  { XX } },
2720     { "hsubpd", { XM, EXx } },
2721     { "hsubps", { XM, EXx } },
2722   },
2723
2724   /* PREFIX_0F7E */
2725   {
2726     { "movK",   { Edq, MX } },
2727     { "movq",   { XM, EXq } },
2728     { "movK",   { Edq, XM } },
2729     { "(bad)",  { XX } },
2730   },
2731
2732   /* PREFIX_0F7F */
2733   {
2734     { "movq",   { EMS, MX } },
2735     { "movdqu", { EXxS, XM } },
2736     { "movdqa", { EXxS, XM } },
2737     { "(bad)",  { XX } },
2738   },
2739
2740   /* PREFIX_0FB8 */
2741   {
2742     { "(bad)", { XX } },
2743     { "popcntS", { Gv, Ev } },
2744     { "(bad)", { XX } },
2745     { "(bad)", { XX } },
2746   },
2747
2748   /* PREFIX_0FBD */
2749   {
2750     { "bsrS",   { Gv, Ev } },
2751     { "lzcntS", { Gv, Ev } },
2752     { "bsrS",   { Gv, Ev } },
2753     { "(bad)",  { XX } },
2754   },
2755
2756   /* PREFIX_0FC2 */
2757   {
2758     { "cmpps",  { XM, EXx, CMP } },
2759     { "cmpss",  { XM, EXd, CMP } },
2760     { "cmppd",  { XM, EXx, CMP } },
2761     { "cmpsd",  { XM, EXq, CMP } },
2762   },
2763
2764   /* PREFIX_0FC3 */
2765   {
2766     { "movntiS", { Ma, Gv } },
2767     { "(bad)",  { XX } },
2768     { "(bad)",  { XX } },
2769     { "(bad)",  { XX } },
2770   },
2771
2772   /* PREFIX_0FC7_REG_6 */
2773   {
2774     { "vmptrld",{ Mq } },
2775     { "vmxon",  { Mq } },
2776     { "vmclear",{ Mq } },
2777     { "(bad)",  { XX } },
2778   },
2779
2780   /* PREFIX_0FD0 */
2781   {
2782     { "(bad)",  { XX } },
2783     { "(bad)",  { XX } },
2784     { "addsubpd", { XM, EXx } },
2785     { "addsubps", { XM, EXx } },
2786   },
2787
2788   /* PREFIX_0FD6 */
2789   {
2790     { "(bad)",  { XX } },
2791     { "movq2dq",{ XM, MS } },
2792     { "movq",   { EXqS, XM } },
2793     { "movdq2q",{ MX, XS } },
2794   },
2795
2796   /* PREFIX_0FE6 */
2797   {
2798     { "(bad)",  { XX } },
2799     { "cvtdq2pd", { XM, EXq } },
2800     { "cvttpd2dq", { XM, EXx } },
2801     { "cvtpd2dq", { XM, EXx } },
2802   },
2803
2804   /* PREFIX_0FE7 */
2805   {
2806     { "movntq", { Mq, MX } },
2807     { "(bad)",  { XX } },
2808     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2809     { "(bad)",  { XX } },
2810   },
2811
2812   /* PREFIX_0FF0 */
2813   {
2814     { "(bad)",  { XX } },
2815     { "(bad)",  { XX } },
2816     { "(bad)",  { XX } },
2817     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2818   },
2819
2820   /* PREFIX_0FF7 */
2821   {
2822     { "maskmovq", { MX, MS } },
2823     { "(bad)",  { XX } },
2824     { "maskmovdqu", { XM, XS } },
2825     { "(bad)",  { XX } },
2826   },
2827
2828   /* PREFIX_0F3810 */
2829   {
2830     { "(bad)",  { XX } },
2831     { "(bad)",  { XX } },
2832     { "pblendvb", { XM, EXx, XMM0 } },
2833     { "(bad)",  { XX } },
2834   },
2835
2836   /* PREFIX_0F3814 */
2837   {
2838     { "(bad)",  { XX } },
2839     { "(bad)",  { XX } },
2840     { "blendvps", { XM, EXx, XMM0 } },
2841     { "(bad)",  { XX } },
2842   },
2843
2844   /* PREFIX_0F3815 */
2845   {
2846     { "(bad)",  { XX } },
2847     { "(bad)",  { XX } },
2848     { "blendvpd", { XM, EXx, XMM0 } },
2849     { "(bad)",  { XX } },
2850   },
2851
2852   /* PREFIX_0F3817 */
2853   {
2854     { "(bad)",  { XX } },
2855     { "(bad)",  { XX } },
2856     { "ptest",  { XM, EXx } },
2857     { "(bad)",  { XX } },
2858   },
2859
2860   /* PREFIX_0F3820 */
2861   {
2862     { "(bad)",  { XX } },
2863     { "(bad)",  { XX } },
2864     { "pmovsxbw", { XM, EXq } },
2865     { "(bad)",  { XX } },
2866   },
2867
2868   /* PREFIX_0F3821 */
2869   {
2870     { "(bad)",  { XX } },
2871     { "(bad)",  { XX } },
2872     { "pmovsxbd", { XM, EXd } },
2873     { "(bad)",  { XX } },
2874   },
2875
2876   /* PREFIX_0F3822 */
2877   {
2878     { "(bad)",  { XX } },
2879     { "(bad)",  { XX } },
2880     { "pmovsxbq", { XM, EXw } },
2881     { "(bad)",  { XX } },
2882   },
2883
2884   /* PREFIX_0F3823 */
2885   {
2886     { "(bad)",  { XX } },
2887     { "(bad)",  { XX } },
2888     { "pmovsxwd", { XM, EXq } },
2889     { "(bad)",  { XX } },
2890   },
2891
2892   /* PREFIX_0F3824 */
2893   {
2894     { "(bad)",  { XX } },
2895     { "(bad)",  { XX } },
2896     { "pmovsxwq", { XM, EXd } },
2897     { "(bad)",  { XX } },
2898   },
2899
2900   /* PREFIX_0F3825 */
2901   {
2902     { "(bad)",  { XX } },
2903     { "(bad)",  { XX } },
2904     { "pmovsxdq", { XM, EXq } },
2905     { "(bad)",  { XX } },
2906   },
2907
2908   /* PREFIX_0F3828 */
2909   {
2910     { "(bad)",  { XX } },
2911     { "(bad)",  { XX } },
2912     { "pmuldq", { XM, EXx } },
2913     { "(bad)",  { XX } },
2914   },
2915
2916   /* PREFIX_0F3829 */
2917   {
2918     { "(bad)",  { XX } },
2919     { "(bad)",  { XX } },
2920     { "pcmpeqq", { XM, EXx } },
2921     { "(bad)",  { XX } },
2922   },
2923
2924   /* PREFIX_0F382A */
2925   {
2926     { "(bad)",  { XX } },
2927     { "(bad)",  { XX } },
2928     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2929     { "(bad)",  { XX } },
2930   },
2931
2932   /* PREFIX_0F382B */
2933   {
2934     { "(bad)",  { XX } },
2935     { "(bad)",  { XX } },
2936     { "packusdw", { XM, EXx } },
2937     { "(bad)",  { XX } },
2938   },
2939
2940   /* PREFIX_0F3830 */
2941   {
2942     { "(bad)",  { XX } },
2943     { "(bad)",  { XX } },
2944     { "pmovzxbw", { XM, EXq } },
2945     { "(bad)",  { XX } },
2946   },
2947
2948   /* PREFIX_0F3831 */
2949   {
2950     { "(bad)",  { XX } },
2951     { "(bad)",  { XX } },
2952     { "pmovzxbd", { XM, EXd } },
2953     { "(bad)",  { XX } },
2954   },
2955
2956   /* PREFIX_0F3832 */
2957   {
2958     { "(bad)",  { XX } },
2959     { "(bad)",  { XX } },
2960     { "pmovzxbq", { XM, EXw } },
2961     { "(bad)",  { XX } },
2962   },
2963
2964   /* PREFIX_0F3833 */
2965   {
2966     { "(bad)",  { XX } },
2967     { "(bad)",  { XX } },
2968     { "pmovzxwd", { XM, EXq } },
2969     { "(bad)",  { XX } },
2970   },
2971
2972   /* PREFIX_0F3834 */
2973   {
2974     { "(bad)",  { XX } },
2975     { "(bad)",  { XX } },
2976     { "pmovzxwq", { XM, EXd } },
2977     { "(bad)",  { XX } },
2978   },
2979
2980   /* PREFIX_0F3835 */
2981   {
2982     { "(bad)",  { XX } },
2983     { "(bad)",  { XX } },
2984     { "pmovzxdq", { XM, EXq } },
2985     { "(bad)",  { XX } },
2986   },
2987
2988   /* PREFIX_0F3837 */
2989   {
2990     { "(bad)",  { XX } },
2991     { "(bad)",  { XX } },
2992     { "pcmpgtq", { XM, EXx } },
2993     { "(bad)",  { XX } },
2994   },
2995
2996   /* PREFIX_0F3838 */
2997   {
2998     { "(bad)",  { XX } },
2999     { "(bad)",  { XX } },
3000     { "pminsb", { XM, EXx } },
3001     { "(bad)",  { XX } },
3002   },
3003
3004   /* PREFIX_0F3839 */
3005   {
3006     { "(bad)",  { XX } },
3007     { "(bad)",  { XX } },
3008     { "pminsd", { XM, EXx } },
3009     { "(bad)",  { XX } },
3010   },
3011
3012   /* PREFIX_0F383A */
3013   {
3014     { "(bad)",  { XX } },
3015     { "(bad)",  { XX } },
3016     { "pminuw", { XM, EXx } },
3017     { "(bad)",  { XX } },
3018   },
3019
3020   /* PREFIX_0F383B */
3021   {
3022     { "(bad)",  { XX } },
3023     { "(bad)",  { XX } },
3024     { "pminud", { XM, EXx } },
3025     { "(bad)",  { XX } },
3026   },
3027
3028   /* PREFIX_0F383C */
3029   {
3030     { "(bad)",  { XX } },
3031     { "(bad)",  { XX } },
3032     { "pmaxsb", { XM, EXx } },
3033     { "(bad)",  { XX } },
3034   },
3035
3036   /* PREFIX_0F383D */
3037   {
3038     { "(bad)",  { XX } },
3039     { "(bad)",  { XX } },
3040     { "pmaxsd", { XM, EXx } },
3041     { "(bad)",  { XX } },
3042   },
3043
3044   /* PREFIX_0F383E */
3045   {
3046     { "(bad)",  { XX } },
3047     { "(bad)",  { XX } },
3048     { "pmaxuw", { XM, EXx } },
3049     { "(bad)",  { XX } },
3050   },
3051
3052   /* PREFIX_0F383F */
3053   {
3054     { "(bad)",  { XX } },
3055     { "(bad)",  { XX } },
3056     { "pmaxud", { XM, EXx } },
3057     { "(bad)",  { XX } },
3058   },
3059
3060   /* PREFIX_0F3840 */
3061   {
3062     { "(bad)",  { XX } },
3063     { "(bad)",  { XX } },
3064     { "pmulld", { XM, EXx } },
3065     { "(bad)",  { XX } },
3066   },
3067
3068   /* PREFIX_0F3841 */
3069   {
3070     { "(bad)",  { XX } },
3071     { "(bad)",  { XX } },
3072     { "phminposuw", { XM, EXx } },
3073     { "(bad)",  { XX } },
3074   },
3075
3076   /* PREFIX_0F3880 */
3077   {
3078     { "(bad)",  { XX } },
3079     { "(bad)",  { XX } },
3080     { "invept", { Gm, Mo } },
3081     { "(bad)",  { XX } },
3082   },
3083
3084   /* PREFIX_0F3881 */
3085   {
3086     { "(bad)",  { XX } },
3087     { "(bad)",  { XX } },
3088     { "invvpid", { Gm, Mo } },
3089     { "(bad)",  { XX } },
3090   },
3091
3092   /* PREFIX_0F38DB */
3093   {
3094     { "(bad)",  { XX } },
3095     { "(bad)",  { XX } },
3096     { "aesimc", { XM, EXx } },
3097     { "(bad)",  { XX } },
3098   },
3099
3100   /* PREFIX_0F38DC */
3101   {
3102     { "(bad)",  { XX } },
3103     { "(bad)",  { XX } },
3104     { "aesenc", { XM, EXx } },
3105     { "(bad)",  { XX } },
3106   },
3107
3108   /* PREFIX_0F38DD */
3109   {
3110     { "(bad)",  { XX } },
3111     { "(bad)",  { XX } },
3112     { "aesenclast", { XM, EXx } },
3113     { "(bad)",  { XX } },
3114   },
3115
3116   /* PREFIX_0F38DE */
3117   {
3118     { "(bad)",  { XX } },
3119     { "(bad)",  { XX } },
3120     { "aesdec", { XM, EXx } },
3121     { "(bad)",  { XX } },
3122   },
3123
3124   /* PREFIX_0F38DF */
3125   {
3126     { "(bad)",  { XX } },
3127     { "(bad)",  { XX } },
3128     { "aesdeclast", { XM, EXx } },
3129     { "(bad)",  { XX } },
3130   },
3131
3132   /* PREFIX_0F38F0 */
3133   {
3134     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3135     { "(bad)",  { XX } },
3136     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3137     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3138   },
3139
3140   /* PREFIX_0F38F1 */
3141   {
3142     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3143     { "(bad)",  { XX } },
3144     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3145     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3146   },
3147
3148   /* PREFIX_0F3A08 */
3149   {
3150     { "(bad)",  { XX } },
3151     { "(bad)",  { XX } },
3152     { "roundps", { XM, EXx, Ib } },
3153     { "(bad)",  { XX } },
3154   },
3155
3156   /* PREFIX_0F3A09 */
3157   {
3158     { "(bad)",  { XX } },
3159     { "(bad)",  { XX } },
3160     { "roundpd", { XM, EXx, Ib } },
3161     { "(bad)",  { XX } },
3162   },
3163
3164   /* PREFIX_0F3A0A */
3165   {
3166     { "(bad)",  { XX } },
3167     { "(bad)",  { XX } },
3168     { "roundss", { XM, EXd, Ib } },
3169     { "(bad)",  { XX } },
3170   },
3171
3172   /* PREFIX_0F3A0B */
3173   {
3174     { "(bad)",  { XX } },
3175     { "(bad)",  { XX } },
3176     { "roundsd", { XM, EXq, Ib } },
3177     { "(bad)",  { XX } },
3178   },
3179
3180   /* PREFIX_0F3A0C */
3181   {
3182     { "(bad)",  { XX } },
3183     { "(bad)",  { XX } },
3184     { "blendps", { XM, EXx, Ib } },
3185     { "(bad)",  { XX } },
3186   },
3187
3188   /* PREFIX_0F3A0D */
3189   {
3190     { "(bad)",  { XX } },
3191     { "(bad)",  { XX } },
3192     { "blendpd", { XM, EXx, Ib } },
3193     { "(bad)",  { XX } },
3194   },
3195
3196   /* PREFIX_0F3A0E */
3197   {
3198     { "(bad)",  { XX } },
3199     { "(bad)",  { XX } },
3200     { "pblendw", { XM, EXx, Ib } },
3201     { "(bad)",  { XX } },
3202   },
3203
3204   /* PREFIX_0F3A14 */
3205   {
3206     { "(bad)",  { XX } },
3207     { "(bad)",  { XX } },
3208     { "pextrb", { Edqb, XM, Ib } },
3209     { "(bad)",  { XX } },
3210   },
3211
3212   /* PREFIX_0F3A15 */
3213   {
3214     { "(bad)",  { XX } },
3215     { "(bad)",  { XX } },
3216     { "pextrw", { Edqw, XM, Ib } },
3217     { "(bad)",  { XX } },
3218   },
3219
3220   /* PREFIX_0F3A16 */
3221   {
3222     { "(bad)",  { XX } },
3223     { "(bad)",  { XX } },
3224     { "pextrK", { Edq, XM, Ib } },
3225     { "(bad)",  { XX } },
3226   },
3227
3228   /* PREFIX_0F3A17 */
3229   {
3230     { "(bad)",  { XX } },
3231     { "(bad)",  { XX } },
3232     { "extractps", { Edqd, XM, Ib } },
3233     { "(bad)",  { XX } },
3234   },
3235
3236   /* PREFIX_0F3A20 */
3237   {
3238     { "(bad)",  { XX } },
3239     { "(bad)",  { XX } },
3240     { "pinsrb", { XM, Edqb, Ib } },
3241     { "(bad)",  { XX } },
3242   },
3243
3244   /* PREFIX_0F3A21 */
3245   {
3246     { "(bad)",  { XX } },
3247     { "(bad)",  { XX } },
3248     { "insertps", { XM, EXd, Ib } },
3249     { "(bad)",  { XX } },
3250   },
3251
3252   /* PREFIX_0F3A22 */
3253   {
3254     { "(bad)",  { XX } },
3255     { "(bad)",  { XX } },
3256     { "pinsrK", { XM, Edq, Ib } },
3257     { "(bad)",  { XX } },
3258   },
3259
3260   /* PREFIX_0F3A40 */
3261   {
3262     { "(bad)",  { XX } },
3263     { "(bad)",  { XX } },
3264     { "dpps",   { XM, EXx, Ib } },
3265     { "(bad)",  { XX } },
3266   },
3267
3268   /* PREFIX_0F3A41 */
3269   {
3270     { "(bad)",  { XX } },
3271     { "(bad)",  { XX } },
3272     { "dppd",   { XM, EXx, Ib } },
3273     { "(bad)",  { XX } },
3274   },
3275
3276   /* PREFIX_0F3A42 */
3277   {
3278     { "(bad)",  { XX } },
3279     { "(bad)",  { XX } },
3280     { "mpsadbw", { XM, EXx, Ib } },
3281     { "(bad)",  { XX } },
3282   },
3283
3284   /* PREFIX_0F3A44 */
3285   {
3286     { "(bad)",  { XX } },
3287     { "(bad)",  { XX } },
3288     { "pclmulqdq", { XM, EXx, PCLMUL } },
3289     { "(bad)",  { XX } },
3290   },
3291
3292   /* PREFIX_0F3A60 */
3293   {
3294     { "(bad)",  { XX } },
3295     { "(bad)",  { XX } },
3296     { "pcmpestrm", { XM, EXx, Ib } },
3297     { "(bad)",  { XX } },
3298   },
3299
3300   /* PREFIX_0F3A61 */
3301   {
3302     { "(bad)",  { XX } },
3303     { "(bad)",  { XX } },
3304     { "pcmpestri", { XM, EXx, Ib } },
3305     { "(bad)",  { XX } },
3306   },
3307
3308   /* PREFIX_0F3A62 */
3309   {
3310     { "(bad)",  { XX } },
3311     { "(bad)",  { XX } },
3312     { "pcmpistrm", { XM, EXx, Ib } },
3313     { "(bad)",  { XX } },
3314   },
3315
3316   /* PREFIX_0F3A63 */
3317   {
3318     { "(bad)",  { XX } },
3319     { "(bad)",  { XX } },
3320     { "pcmpistri", { XM, EXx, Ib } },
3321     { "(bad)",  { XX } },
3322   },
3323
3324   /* PREFIX_0F3ADF */
3325   {
3326     { "(bad)",  { XX } },
3327     { "(bad)",  { XX } },
3328     { "aeskeygenassist", { XM, EXx, Ib } },
3329     { "(bad)",  { XX } },
3330   },
3331
3332   /* PREFIX_VEX_10 */
3333   {
3334     { "vmovups", { XM, EXx } },
3335     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3336     { "vmovupd", { XM, EXx } },
3337     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3338   },
3339
3340   /* PREFIX_VEX_11 */
3341   {
3342     { "vmovups", { EXxS, XM } },
3343     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3344     { "vmovupd", { EXxS, XM } },
3345     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3346   },
3347
3348   /* PREFIX_VEX_12 */
3349   {
3350     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3351     { "vmovsldup", { XM, EXx } },
3352     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3353     { "vmovddup", { XM, EXymmq } },
3354   },
3355
3356   /* PREFIX_VEX_16 */
3357   {
3358     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3359     { "vmovshdup", { XM, EXx } },
3360     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3361     { "(bad)",  { XX } },
3362   },
3363
3364   /* PREFIX_VEX_2A */
3365   {
3366     { "(bad)",  { XX } },
3367     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3368     { "(bad)",  { XX } },
3369     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3370   },
3371
3372   /* PREFIX_VEX_2C */
3373   {
3374     { "(bad)",  { XX } },
3375     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3376     { "(bad)",  { XX } },
3377     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3378   },
3379
3380   /* PREFIX_VEX_2D */
3381   {
3382     { "(bad)",  { XX } },
3383     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3384     { "(bad)",  { XX } },
3385     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3386   },
3387
3388   /* PREFIX_VEX_2E */
3389   {
3390     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3391     { "(bad)",  { XX } },
3392     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3393     { "(bad)",  { XX } },
3394   },
3395
3396   /* PREFIX_VEX_2F */
3397   {
3398     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3399     { "(bad)",  { XX } },
3400     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3401     { "(bad)",  { XX } },
3402   },
3403
3404   /* PREFIX_VEX_51 */
3405   {
3406     { "vsqrtps", { XM, EXx } },
3407     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3408     { "vsqrtpd", { XM, EXx } },
3409     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3410   },
3411
3412   /* PREFIX_VEX_52 */
3413   {
3414     { "vrsqrtps", { XM, EXx } },
3415     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3416     { "(bad)",  { XX } },
3417     { "(bad)",  { XX } },
3418   },
3419
3420   /* PREFIX_VEX_53 */
3421   {
3422     { "vrcpps", { XM, EXx } },
3423     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3424     { "(bad)",  { XX } },
3425     { "(bad)",  { XX } },
3426   },
3427
3428   /* PREFIX_VEX_58 */
3429   {
3430     { "vaddps", { XM, Vex, EXx } },
3431     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3432     { "vaddpd", { XM, Vex, EXx } },
3433     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3434   },
3435
3436   /* PREFIX_VEX_59 */
3437   {
3438     { "vmulps", { XM, Vex, EXx } },
3439     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3440     { "vmulpd", { XM, Vex, EXx } },
3441     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3442   },
3443
3444   /* PREFIX_VEX_5A */
3445   {
3446     { "vcvtps2pd", { XM, EXxmmq } },
3447     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3448     { "vcvtpd2ps%XY", { XMM, EXx } },
3449     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3450   },
3451
3452   /* PREFIX_VEX_5B */
3453   {
3454     { "vcvtdq2ps", { XM, EXx } },
3455     { "vcvttps2dq", { XM, EXx } },
3456     { "vcvtps2dq", { XM, EXx } },
3457     { "(bad)",  { XX } },
3458   },
3459
3460   /* PREFIX_VEX_5C */
3461   {
3462     { "vsubps", { XM, Vex, EXx } },
3463     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3464     { "vsubpd", { XM, Vex, EXx } },
3465     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3466   },
3467
3468   /* PREFIX_VEX_5D */
3469   {
3470     { "vminps", { XM, Vex, EXx } },
3471     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3472     { "vminpd", { XM, Vex, EXx } },
3473     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3474   },
3475
3476   /* PREFIX_VEX_5E */
3477   {
3478     { "vdivps", { XM, Vex, EXx } },
3479     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3480     { "vdivpd", { XM, Vex, EXx } },
3481     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3482   },
3483
3484   /* PREFIX_VEX_5F */
3485   {
3486     { "vmaxps", { XM, Vex, EXx } },
3487     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3488     { "vmaxpd", { XM, Vex, EXx } },
3489     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3490   },
3491
3492   /* PREFIX_VEX_60 */
3493   {
3494     { "(bad)",  { XX } },
3495     { "(bad)",  { XX } },
3496     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3497     { "(bad)",  { XX } },
3498   },
3499
3500   /* PREFIX_VEX_61 */
3501   {
3502     { "(bad)",  { XX } },
3503     { "(bad)",  { XX } },
3504     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3505     { "(bad)",  { XX } },
3506   },
3507
3508   /* PREFIX_VEX_62 */
3509   {
3510     { "(bad)",  { XX } },
3511     { "(bad)",  { XX } },
3512     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3513     { "(bad)",  { XX } },
3514   },
3515
3516   /* PREFIX_VEX_63 */
3517   {
3518     { "(bad)",  { XX } },
3519     { "(bad)",  { XX } },
3520     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3521     { "(bad)",  { XX } },
3522   },
3523
3524   /* PREFIX_VEX_64 */
3525   {
3526     { "(bad)",  { XX } },
3527     { "(bad)",  { XX } },
3528     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3529     { "(bad)",  { XX } },
3530   },
3531
3532   /* PREFIX_VEX_65 */
3533   {
3534     { "(bad)",  { XX } },
3535     { "(bad)",  { XX } },
3536     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3537     { "(bad)",  { XX } },
3538   },
3539
3540   /* PREFIX_VEX_66 */
3541   {
3542     { "(bad)",  { XX } },
3543     { "(bad)",  { XX } },
3544     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3545     { "(bad)",  { XX } },
3546   },
3547
3548   /* PREFIX_VEX_67 */
3549   {
3550     { "(bad)",  { XX } },
3551     { "(bad)",  { XX } },
3552     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3553     { "(bad)",  { XX } },
3554   },
3555
3556   /* PREFIX_VEX_68 */
3557   {
3558     { "(bad)",  { XX } },
3559     { "(bad)",  { XX } },
3560     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3561     { "(bad)",  { XX } },
3562   },
3563
3564   /* PREFIX_VEX_69 */
3565   {
3566     { "(bad)",  { XX } },
3567     { "(bad)",  { XX } },
3568     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3569     { "(bad)",  { XX } },
3570   },
3571
3572   /* PREFIX_VEX_6A */
3573   {
3574     { "(bad)",  { XX } },
3575     { "(bad)",  { XX } },
3576     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3577     { "(bad)",  { XX } },
3578   },
3579
3580   /* PREFIX_VEX_6B */
3581   {
3582     { "(bad)",  { XX } },
3583     { "(bad)",  { XX } },
3584     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3585     { "(bad)",  { XX } },
3586   },
3587
3588   /* PREFIX_VEX_6C */
3589   {
3590     { "(bad)",  { XX } },
3591     { "(bad)",  { XX } },
3592     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3593     { "(bad)",  { XX } },
3594   },
3595
3596   /* PREFIX_VEX_6D */
3597   {
3598     { "(bad)",  { XX } },
3599     { "(bad)",  { XX } },
3600     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3601     { "(bad)",  { XX } },
3602   },
3603
3604   /* PREFIX_VEX_6E */
3605   {
3606     { "(bad)",  { XX } },
3607     { "(bad)",  { XX } },
3608     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3609     { "(bad)",  { XX } },
3610   },
3611
3612   /* PREFIX_VEX_6F */
3613   {
3614     { "(bad)",  { XX } },
3615     { "vmovdqu", { XM, EXx } },
3616     { "vmovdqa", { XM, EXx } },
3617     { "(bad)",  { XX } },
3618   },
3619
3620   /* PREFIX_VEX_70 */
3621   {
3622     { "(bad)",  { XX } },
3623     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3624     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3625     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3626   },
3627
3628   /* PREFIX_VEX_71_REG_2 */
3629   {
3630     { "(bad)",  { XX } },
3631     { "(bad)",  { XX } },
3632     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3633     { "(bad)",  { XX } },
3634   },
3635
3636   /* PREFIX_VEX_71_REG_4 */
3637   {
3638     { "(bad)",  { XX } },
3639     { "(bad)",  { XX } },
3640     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3641     { "(bad)",  { XX } },
3642   },
3643
3644   /* PREFIX_VEX_71_REG_6 */
3645   {
3646     { "(bad)",  { XX } },
3647     { "(bad)",  { XX } },
3648     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3649     { "(bad)",  { XX } },
3650   },
3651
3652   /* PREFIX_VEX_72_REG_2 */
3653   {
3654     { "(bad)",  { XX } },
3655     { "(bad)",  { XX } },
3656     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3657     { "(bad)",  { XX } },
3658   },
3659
3660   /* PREFIX_VEX_72_REG_4 */
3661   {
3662     { "(bad)",  { XX } },
3663     { "(bad)",  { XX } },
3664     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3665     { "(bad)",  { XX } },
3666   },
3667
3668   /* PREFIX_VEX_72_REG_6 */
3669   {
3670     { "(bad)",  { XX } },
3671     { "(bad)",  { XX } },
3672     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3673     { "(bad)",  { XX } },
3674   },
3675
3676   /* PREFIX_VEX_73_REG_2 */
3677   {
3678     { "(bad)",  { XX } },
3679     { "(bad)",  { XX } },
3680     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3681     { "(bad)",  { XX } },
3682   },
3683
3684   /* PREFIX_VEX_73_REG_3 */
3685   {
3686     { "(bad)",  { XX } },
3687     { "(bad)",  { XX } },
3688     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3689     { "(bad)",  { XX } },
3690   },
3691
3692   /* PREFIX_VEX_73_REG_6 */
3693   {
3694     { "(bad)",  { XX } },
3695     { "(bad)",  { XX } },
3696     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3697     { "(bad)",  { XX } },
3698   },
3699
3700   /* PREFIX_VEX_73_REG_7 */
3701   {
3702     { "(bad)",  { XX } },
3703     { "(bad)",  { XX } },
3704     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3705     { "(bad)",  { XX } },
3706   },
3707
3708   /* PREFIX_VEX_74 */
3709   {
3710     { "(bad)",  { XX } },
3711     { "(bad)",  { XX } },
3712     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3713     { "(bad)",  { XX } },
3714   },
3715
3716   /* PREFIX_VEX_75 */
3717   {
3718     { "(bad)",  { XX } },
3719     { "(bad)",  { XX } },
3720     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3721     { "(bad)",  { XX } },
3722   },
3723
3724   /* PREFIX_VEX_76 */
3725   {
3726     { "(bad)",  { XX } },
3727     { "(bad)",  { XX } },
3728     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3729     { "(bad)",  { XX } },
3730   },
3731
3732   /* PREFIX_VEX_77 */
3733   {
3734     { "",       { VZERO } },
3735     { "(bad)",  { XX } },
3736     { "(bad)",  { XX } },
3737     { "(bad)",  { XX } },
3738   },
3739
3740   /* PREFIX_VEX_7C */
3741   {
3742     { "(bad)",  { XX } },
3743     { "(bad)",  { XX } },
3744     { "vhaddpd", { XM, Vex, EXx } },
3745     { "vhaddps", { XM, Vex, EXx } },
3746   },
3747
3748   /* PREFIX_VEX_7D */
3749   {
3750     { "(bad)",  { XX } },
3751     { "(bad)",  { XX } },
3752     { "vhsubpd", { XM, Vex, EXx } },
3753     { "vhsubps", { XM, Vex, EXx } },
3754   },
3755
3756   /* PREFIX_VEX_7E */
3757   {
3758     { "(bad)",  { XX } },
3759     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3760     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3761     { "(bad)",  { XX } },
3762   },
3763
3764   /* PREFIX_VEX_7F */
3765   {
3766     { "(bad)",  { XX } },
3767     { "vmovdqu", { EXxS, XM } },
3768     { "vmovdqa", { EXxS, XM } },
3769     { "(bad)",  { XX } },
3770   },
3771
3772   /* PREFIX_VEX_C2 */
3773   {
3774     { "vcmpps", { XM, Vex, EXx, VCMP } },
3775     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3776     { "vcmppd", { XM, Vex, EXx, VCMP } },
3777     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3778   },
3779
3780   /* PREFIX_VEX_C4 */
3781   {
3782     { "(bad)",  { XX } },
3783     { "(bad)",  { XX } },
3784     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3785     { "(bad)",  { XX } },
3786   },
3787
3788   /* PREFIX_VEX_C5 */
3789   {
3790     { "(bad)",  { XX } },
3791     { "(bad)",  { XX } },
3792     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3793     { "(bad)",  { XX } },
3794   },
3795
3796   /* PREFIX_VEX_D0 */
3797   {
3798     { "(bad)",  { XX } },
3799     { "(bad)",  { XX } },
3800     { "vaddsubpd", { XM, Vex, EXx } },
3801     { "vaddsubps", { XM, Vex, EXx } },
3802   },
3803
3804   /* PREFIX_VEX_D1 */
3805   {
3806     { "(bad)",  { XX } },
3807     { "(bad)",  { XX } },
3808     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3809     { "(bad)",  { XX } },
3810   },
3811
3812   /* PREFIX_VEX_D2 */
3813   {
3814     { "(bad)",  { XX } },
3815     { "(bad)",  { XX } },
3816     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3817     { "(bad)",  { XX } },
3818   },
3819
3820   /* PREFIX_VEX_D3 */
3821   {
3822     { "(bad)",  { XX } },
3823     { "(bad)",  { XX } },
3824     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3825     { "(bad)",  { XX } },
3826   },
3827
3828   /* PREFIX_VEX_D4 */
3829   {
3830     { "(bad)",  { XX } },
3831     { "(bad)",  { XX } },
3832     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3833     { "(bad)",  { XX } },
3834   },
3835
3836   /* PREFIX_VEX_D5 */
3837   {
3838     { "(bad)",  { XX } },
3839     { "(bad)",  { XX } },
3840     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3841     { "(bad)",  { XX } },
3842   },
3843
3844   /* PREFIX_VEX_D6 */
3845   {
3846     { "(bad)",  { XX } },
3847     { "(bad)",  { XX } },
3848     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3849     { "(bad)",  { XX } },
3850   },
3851
3852   /* PREFIX_VEX_D7 */
3853   {
3854     { "(bad)",  { XX } },
3855     { "(bad)",  { XX } },
3856     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3857     { "(bad)",  { XX } },
3858   },
3859
3860   /* PREFIX_VEX_D8 */
3861   {
3862     { "(bad)",  { XX } },
3863     { "(bad)",  { XX } },
3864     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3865     { "(bad)",  { XX } },
3866   },
3867
3868   /* PREFIX_VEX_D9 */
3869   {
3870     { "(bad)",  { XX } },
3871     { "(bad)",  { XX } },
3872     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3873     { "(bad)",  { XX } },
3874   },
3875
3876   /* PREFIX_VEX_DA */
3877   {
3878     { "(bad)",  { XX } },
3879     { "(bad)",  { XX } },
3880     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3881     { "(bad)",  { XX } },
3882   },
3883
3884   /* PREFIX_VEX_DB */
3885   {
3886     { "(bad)",  { XX } },
3887     { "(bad)",  { XX } },
3888     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3889     { "(bad)",  { XX } },
3890   },
3891
3892   /* PREFIX_VEX_DC */
3893   {
3894     { "(bad)",  { XX } },
3895     { "(bad)",  { XX } },
3896     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3897     { "(bad)",  { XX } },
3898   },
3899
3900   /* PREFIX_VEX_DD */
3901   {
3902     { "(bad)",  { XX } },
3903     { "(bad)",  { XX } },
3904     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3905     { "(bad)",  { XX } },
3906   },
3907
3908   /* PREFIX_VEX_DE */
3909   {
3910     { "(bad)",  { XX } },
3911     { "(bad)",  { XX } },
3912     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3913     { "(bad)",  { XX } },
3914   },
3915
3916   /* PREFIX_VEX_DF */
3917   {
3918     { "(bad)",  { XX } },
3919     { "(bad)",  { XX } },
3920     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3921     { "(bad)",  { XX } },
3922   },
3923
3924   /* PREFIX_VEX_E0 */
3925   {
3926     { "(bad)",  { XX } },
3927     { "(bad)",  { XX } },
3928     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3929     { "(bad)",  { XX } },
3930   },
3931
3932   /* PREFIX_VEX_E1 */
3933   {
3934     { "(bad)",  { XX } },
3935     { "(bad)",  { XX } },
3936     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3937     { "(bad)",  { XX } },
3938   },
3939
3940   /* PREFIX_VEX_E2 */
3941   {
3942     { "(bad)",  { XX } },
3943     { "(bad)",  { XX } },
3944     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3945     { "(bad)",  { XX } },
3946   },
3947
3948   /* PREFIX_VEX_E3 */
3949   {
3950     { "(bad)",  { XX } },
3951     { "(bad)",  { XX } },
3952     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3953     { "(bad)",  { XX } },
3954   },
3955
3956   /* PREFIX_VEX_E4 */
3957   {
3958     { "(bad)",  { XX } },
3959     { "(bad)",  { XX } },
3960     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3961     { "(bad)",  { XX } },
3962   },
3963
3964   /* PREFIX_VEX_E5 */
3965   {
3966     { "(bad)",  { XX } },
3967     { "(bad)",  { XX } },
3968     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3969     { "(bad)",  { XX } },
3970   },
3971
3972   /* PREFIX_VEX_E6 */
3973   {
3974     { "(bad)",  { XX } },
3975     { "vcvtdq2pd", { XM, EXxmmq } },
3976     { "vcvttpd2dq%XY", { XMM, EXx } },
3977     { "vcvtpd2dq%XY", { XMM, EXx } },
3978   },
3979
3980   /* PREFIX_VEX_E7 */
3981   {
3982     { "(bad)",  { XX } },
3983     { "(bad)",  { XX } },
3984     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3985     { "(bad)",  { XX } },
3986   },
3987
3988   /* PREFIX_VEX_E8 */
3989   {
3990     { "(bad)",  { XX } },
3991     { "(bad)",  { XX } },
3992     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3993     { "(bad)",  { XX } },
3994   },
3995
3996   /* PREFIX_VEX_E9 */
3997   {
3998     { "(bad)",  { XX } },
3999     { "(bad)",  { XX } },
4000     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4001     { "(bad)",  { XX } },
4002   },
4003
4004   /* PREFIX_VEX_EA */
4005   {
4006     { "(bad)",  { XX } },
4007     { "(bad)",  { XX } },
4008     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4009     { "(bad)",  { XX } },
4010   },
4011
4012   /* PREFIX_VEX_EB */
4013   {
4014     { "(bad)",  { XX } },
4015     { "(bad)",  { XX } },
4016     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4017     { "(bad)",  { XX } },
4018   },
4019
4020   /* PREFIX_VEX_EC */
4021   {
4022     { "(bad)",  { XX } },
4023     { "(bad)",  { XX } },
4024     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4025     { "(bad)",  { XX } },
4026   },
4027
4028   /* PREFIX_VEX_ED */
4029   {
4030     { "(bad)",  { XX } },
4031     { "(bad)",  { XX } },
4032     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4033     { "(bad)",  { XX } },
4034   },
4035
4036   /* PREFIX_VEX_EE */
4037   {
4038     { "(bad)",  { XX } },
4039     { "(bad)",  { XX } },
4040     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4041     { "(bad)",  { XX } },
4042   },
4043
4044   /* PREFIX_VEX_EF */
4045   {
4046     { "(bad)",  { XX } },
4047     { "(bad)",  { XX } },
4048     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4049     { "(bad)",  { XX } },
4050   },
4051
4052   /* PREFIX_VEX_F0 */
4053   {
4054     { "(bad)",  { XX } },
4055     { "(bad)",  { XX } },
4056     { "(bad)",  { XX } },
4057     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4058   },
4059
4060   /* PREFIX_VEX_F1 */
4061   {
4062     { "(bad)",  { XX } },
4063     { "(bad)",  { XX } },
4064     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4065     { "(bad)",  { XX } },
4066   },
4067
4068   /* PREFIX_VEX_F2 */
4069   {
4070     { "(bad)",  { XX } },
4071     { "(bad)",  { XX } },
4072     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4073     { "(bad)",  { XX } },
4074   },
4075
4076   /* PREFIX_VEX_F3 */
4077   {
4078     { "(bad)",  { XX } },
4079     { "(bad)",  { XX } },
4080     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4081     { "(bad)",  { XX } },
4082   },
4083
4084   /* PREFIX_VEX_F4 */
4085   {
4086     { "(bad)",  { XX } },
4087     { "(bad)",  { XX } },
4088     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4089     { "(bad)",  { XX } },
4090   },
4091
4092   /* PREFIX_VEX_F5 */
4093   {
4094     { "(bad)",  { XX } },
4095     { "(bad)",  { XX } },
4096     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4097     { "(bad)",  { XX } },
4098   },
4099
4100   /* PREFIX_VEX_F6 */
4101   {
4102     { "(bad)",  { XX } },
4103     { "(bad)",  { XX } },
4104     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4105     { "(bad)",  { XX } },
4106   },
4107
4108   /* PREFIX_VEX_F7 */
4109   {
4110     { "(bad)",  { XX } },
4111     { "(bad)",  { XX } },
4112     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4113     { "(bad)",  { XX } },
4114   },
4115
4116   /* PREFIX_VEX_F8 */
4117   {
4118     { "(bad)",  { XX } },
4119     { "(bad)",  { XX } },
4120     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4121     { "(bad)",  { XX } },
4122   },
4123
4124   /* PREFIX_VEX_F9 */
4125   {
4126     { "(bad)",  { XX } },
4127     { "(bad)",  { XX } },
4128     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4129     { "(bad)",  { XX } },
4130   },
4131
4132   /* PREFIX_VEX_FA */
4133   {
4134     { "(bad)",  { XX } },
4135     { "(bad)",  { XX } },
4136     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4137     { "(bad)",  { XX } },
4138   },
4139
4140   /* PREFIX_VEX_FB */
4141   {
4142     { "(bad)",  { XX } },
4143     { "(bad)",  { XX } },
4144     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4145     { "(bad)",  { XX } },
4146   },
4147
4148   /* PREFIX_VEX_FC */
4149   {
4150     { "(bad)",  { XX } },
4151     { "(bad)",  { XX } },
4152     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4153     { "(bad)",  { XX } },
4154   },
4155
4156   /* PREFIX_VEX_FD */
4157   {
4158     { "(bad)",  { XX } },
4159     { "(bad)",  { XX } },
4160     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4161     { "(bad)",  { XX } },
4162   },
4163
4164   /* PREFIX_VEX_FE */
4165   {
4166     { "(bad)",  { XX } },
4167     { "(bad)",  { XX } },
4168     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4169     { "(bad)",  { XX } },
4170   },
4171
4172   /* PREFIX_VEX_3800 */
4173   {
4174     { "(bad)",  { XX } },
4175     { "(bad)",  { XX } },
4176     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4177     { "(bad)",  { XX } },
4178   },
4179
4180   /* PREFIX_VEX_3801 */
4181   {
4182     { "(bad)",  { XX } },
4183     { "(bad)",  { XX } },
4184     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4185     { "(bad)",  { XX } },
4186   },
4187
4188   /* PREFIX_VEX_3802 */
4189   {
4190     { "(bad)",  { XX } },
4191     { "(bad)",  { XX } },
4192     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4193     { "(bad)",  { XX } },
4194   },
4195
4196   /* PREFIX_VEX_3803 */
4197   {
4198     { "(bad)",  { XX } },
4199     { "(bad)",  { XX } },
4200     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4201     { "(bad)",  { XX } },
4202   },
4203
4204   /* PREFIX_VEX_3804 */
4205   {
4206     { "(bad)",  { XX } },
4207     { "(bad)",  { XX } },
4208     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4209     { "(bad)",  { XX } },
4210   },
4211
4212   /* PREFIX_VEX_3805 */
4213   {
4214     { "(bad)",  { XX } },
4215     { "(bad)",  { XX } },
4216     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4217     { "(bad)",  { XX } },
4218   },
4219
4220   /* PREFIX_VEX_3806 */
4221   {
4222     { "(bad)",  { XX } },
4223     { "(bad)",  { XX } },
4224     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4225     { "(bad)",  { XX } },
4226   },
4227
4228   /* PREFIX_VEX_3807 */
4229   {
4230     { "(bad)",  { XX } },
4231     { "(bad)",  { XX } },
4232     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4233     { "(bad)",  { XX } },
4234   },
4235
4236   /* PREFIX_VEX_3808 */
4237   {
4238     { "(bad)",  { XX } },
4239     { "(bad)",  { XX } },
4240     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4241     { "(bad)",  { XX } },
4242   },
4243
4244   /* PREFIX_VEX_3809 */
4245   {
4246     { "(bad)",  { XX } },
4247     { "(bad)",  { XX } },
4248     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4249     { "(bad)",  { XX } },
4250   },
4251
4252   /* PREFIX_VEX_380A */
4253   {
4254     { "(bad)",  { XX } },
4255     { "(bad)",  { XX } },
4256     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4257     { "(bad)",  { XX } },
4258   },
4259
4260   /* PREFIX_VEX_380B */
4261   {
4262     { "(bad)",  { XX } },
4263     { "(bad)",  { XX } },
4264     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4265     { "(bad)",  { XX } },
4266   },
4267
4268   /* PREFIX_VEX_380C */
4269   {
4270     { "(bad)",  { XX } },
4271     { "(bad)",  { XX } },
4272     { "vpermilps", { XM, Vex, EXx } },
4273     { "(bad)",  { XX } },
4274   },
4275
4276   /* PREFIX_VEX_380D */
4277   {
4278     { "(bad)",  { XX } },
4279     { "(bad)",  { XX } },
4280     { "vpermilpd", { XM, Vex, EXx } },
4281     { "(bad)",  { XX } },
4282   },
4283
4284   /* PREFIX_VEX_380E */
4285   {
4286     { "(bad)",  { XX } },
4287     { "(bad)",  { XX } },
4288     { "vtestps", { XM, EXx } },
4289     { "(bad)",  { XX } },
4290   },
4291
4292   /* PREFIX_VEX_380F */
4293   {
4294     { "(bad)",  { XX } },
4295     { "(bad)",  { XX } },
4296     { "vtestpd", { XM, EXx } },
4297     { "(bad)",  { XX } },
4298   },
4299
4300   /* PREFIX_VEX_3817 */
4301   {
4302     { "(bad)",  { XX } },
4303     { "(bad)",  { XX } },
4304     { "vptest", { XM, EXx } },
4305     { "(bad)",  { XX } },
4306   },
4307
4308   /* PREFIX_VEX_3818 */
4309   {
4310     { "(bad)",  { XX } },
4311     { "(bad)",  { XX } },
4312     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4313     { "(bad)",  { XX } },
4314   },
4315
4316   /* PREFIX_VEX_3819 */
4317   {
4318     { "(bad)",  { XX } },
4319     { "(bad)",  { XX } },
4320     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4321     { "(bad)",  { XX } },
4322   },
4323
4324   /* PREFIX_VEX_381A */
4325   {
4326     { "(bad)",  { XX } },
4327     { "(bad)",  { XX } },
4328     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4329     { "(bad)",  { XX } },
4330   },
4331
4332   /* PREFIX_VEX_381C */
4333   {
4334     { "(bad)",  { XX } },
4335     { "(bad)",  { XX } },
4336     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4337     { "(bad)",  { XX } },
4338   },
4339
4340   /* PREFIX_VEX_381D */
4341   {
4342     { "(bad)",  { XX } },
4343     { "(bad)",  { XX } },
4344     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4345     { "(bad)",  { XX } },
4346   },
4347
4348   /* PREFIX_VEX_381E */
4349   {
4350     { "(bad)",  { XX } },
4351     { "(bad)",  { XX } },
4352     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4353     { "(bad)",  { XX } },
4354   },
4355
4356   /* PREFIX_VEX_3820 */
4357   {
4358     { "(bad)",  { XX } },
4359     { "(bad)",  { XX } },
4360     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4361     { "(bad)",  { XX } },
4362   },
4363
4364   /* PREFIX_VEX_3821 */
4365   {
4366     { "(bad)",  { XX } },
4367     { "(bad)",  { XX } },
4368     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4369     { "(bad)",  { XX } },
4370   },
4371
4372   /* PREFIX_VEX_3822 */
4373   {
4374     { "(bad)",  { XX } },
4375     { "(bad)",  { XX } },
4376     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4377     { "(bad)",  { XX } },
4378   },
4379
4380   /* PREFIX_VEX_3823 */
4381   {
4382     { "(bad)",  { XX } },
4383     { "(bad)",  { XX } },
4384     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4385     { "(bad)",  { XX } },
4386   },
4387
4388   /* PREFIX_VEX_3824 */
4389   {
4390     { "(bad)",  { XX } },
4391     { "(bad)",  { XX } },
4392     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4393     { "(bad)",  { XX } },
4394   },
4395
4396   /* PREFIX_VEX_3825 */
4397   {
4398     { "(bad)",  { XX } },
4399     { "(bad)",  { XX } },
4400     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4401     { "(bad)",  { XX } },
4402   },
4403
4404   /* PREFIX_VEX_3828 */
4405   {
4406     { "(bad)",  { XX } },
4407     { "(bad)",  { XX } },
4408     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4409     { "(bad)",  { XX } },
4410   },
4411
4412   /* PREFIX_VEX_3829 */
4413   {
4414     { "(bad)",  { XX } },
4415     { "(bad)",  { XX } },
4416     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4417     { "(bad)",  { XX } },
4418   },
4419
4420   /* PREFIX_VEX_382A */
4421   {
4422     { "(bad)",  { XX } },
4423     { "(bad)",  { XX } },
4424     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4425     { "(bad)",  { XX } },
4426   },
4427
4428   /* PREFIX_VEX_382B */
4429   {
4430     { "(bad)",  { XX } },
4431     { "(bad)",  { XX } },
4432     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4433     { "(bad)",  { XX } },
4434   },
4435
4436   /* PREFIX_VEX_382C */
4437   {
4438     { "(bad)",  { XX } },
4439     { "(bad)",  { XX } },
4440      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4441     { "(bad)",  { XX } },
4442   },
4443
4444   /* PREFIX_VEX_382D */
4445   {
4446     { "(bad)",  { XX } },
4447     { "(bad)",  { XX } },
4448      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4449     { "(bad)",  { XX } },
4450   },
4451
4452   /* PREFIX_VEX_382E */
4453   {
4454     { "(bad)",  { XX } },
4455     { "(bad)",  { XX } },
4456      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4457     { "(bad)",  { XX } },
4458   },
4459
4460   /* PREFIX_VEX_382F */
4461   {
4462     { "(bad)",  { XX } },
4463     { "(bad)",  { XX } },
4464      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4465     { "(bad)",  { XX } },
4466   },
4467
4468   /* PREFIX_VEX_3830 */
4469   {
4470     { "(bad)",  { XX } },
4471     { "(bad)",  { XX } },
4472     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4473     { "(bad)",  { XX } },
4474   },
4475
4476   /* PREFIX_VEX_3831 */
4477   {
4478     { "(bad)",  { XX } },
4479     { "(bad)",  { XX } },
4480     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4481     { "(bad)",  { XX } },
4482   },
4483
4484   /* PREFIX_VEX_3832 */
4485   {
4486     { "(bad)",  { XX } },
4487     { "(bad)",  { XX } },
4488     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4489     { "(bad)",  { XX } },
4490   },
4491
4492   /* PREFIX_VEX_3833 */
4493   {
4494     { "(bad)",  { XX } },
4495     { "(bad)",  { XX } },
4496     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4497     { "(bad)",  { XX } },
4498   },
4499
4500   /* PREFIX_VEX_3834 */
4501   {
4502     { "(bad)",  { XX } },
4503     { "(bad)",  { XX } },
4504     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4505     { "(bad)",  { XX } },
4506   },
4507
4508   /* PREFIX_VEX_3835 */
4509   {
4510     { "(bad)",  { XX } },
4511     { "(bad)",  { XX } },
4512     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4513     { "(bad)",  { XX } },
4514   },
4515
4516   /* PREFIX_VEX_3837 */
4517   {
4518     { "(bad)",  { XX } },
4519     { "(bad)",  { XX } },
4520     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4521     { "(bad)",  { XX } },
4522   },
4523
4524   /* PREFIX_VEX_3838 */
4525   {
4526     { "(bad)",  { XX } },
4527     { "(bad)",  { XX } },
4528     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4529     { "(bad)",  { XX } },
4530   },
4531
4532   /* PREFIX_VEX_3839 */
4533   {
4534     { "(bad)",  { XX } },
4535     { "(bad)",  { XX } },
4536     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4537     { "(bad)",  { XX } },
4538   },
4539
4540   /* PREFIX_VEX_383A */
4541   {
4542     { "(bad)",  { XX } },
4543     { "(bad)",  { XX } },
4544     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4545     { "(bad)",  { XX } },
4546   },
4547
4548   /* PREFIX_VEX_383B */
4549   {
4550     { "(bad)",  { XX } },
4551     { "(bad)",  { XX } },
4552     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4553     { "(bad)",  { XX } },
4554   },
4555
4556   /* PREFIX_VEX_383C */
4557   {
4558     { "(bad)",  { XX } },
4559     { "(bad)",  { XX } },
4560     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4561     { "(bad)",  { XX } },
4562   },
4563
4564   /* PREFIX_VEX_383D */
4565   {
4566     { "(bad)",  { XX } },
4567     { "(bad)",  { XX } },
4568     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4569     { "(bad)",  { XX } },
4570   },
4571
4572   /* PREFIX_VEX_383E */
4573   {
4574     { "(bad)",  { XX } },
4575     { "(bad)",  { XX } },
4576     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4577     { "(bad)",  { XX } },
4578   },
4579
4580   /* PREFIX_VEX_383F */
4581   {
4582     { "(bad)",  { XX } },
4583     { "(bad)",  { XX } },
4584     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4585     { "(bad)",  { XX } },
4586   },
4587
4588   /* PREFIX_VEX_3840 */
4589   {
4590     { "(bad)",  { XX } },
4591     { "(bad)",  { XX } },
4592     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4593     { "(bad)",  { XX } },
4594   },
4595
4596   /* PREFIX_VEX_3841 */
4597   {
4598     { "(bad)",  { XX } },
4599     { "(bad)",  { XX } },
4600     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4601     { "(bad)",  { XX } },
4602   },
4603
4604   /* PREFIX_VEX_3896 */
4605   {
4606     { "(bad)",  { XX } },
4607     { "(bad)",  { XX } },
4608     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4609     { "(bad)",  { XX } },
4610   },
4611
4612   /* PREFIX_VEX_3897 */
4613   {
4614     { "(bad)",  { XX } },
4615     { "(bad)",  { XX } },
4616     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4617     { "(bad)",  { XX } },
4618   },
4619
4620   /* PREFIX_VEX_3898 */
4621   {
4622     { "(bad)",  { XX } },
4623     { "(bad)",  { XX } },
4624     { "vfmadd132p%XW", { XM, Vex, EXx } },
4625     { "(bad)",  { XX } },
4626   },
4627
4628   /* PREFIX_VEX_3899 */
4629   {
4630     { "(bad)",  { XX } },
4631     { "(bad)",  { XX } },
4632     { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4633     { "(bad)",  { XX } },
4634   },
4635
4636   /* PREFIX_VEX_389A */
4637   {
4638     { "(bad)",  { XX } },
4639     { "(bad)",  { XX } },
4640     { "vfmsub132p%XW", { XM, Vex, EXx } },
4641     { "(bad)",  { XX } },
4642   },
4643
4644   /* PREFIX_VEX_389B */
4645   {
4646     { "(bad)",  { XX } },
4647     { "(bad)",  { XX } },
4648     { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4649     { "(bad)",  { XX } },
4650   },
4651
4652   /* PREFIX_VEX_389C */
4653   {
4654     { "(bad)",  { XX } },
4655     { "(bad)",  { XX } },
4656     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4657     { "(bad)",  { XX } },
4658   },
4659
4660   /* PREFIX_VEX_389D */
4661   {
4662     { "(bad)",  { XX } },
4663     { "(bad)",  { XX } },
4664     { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4665     { "(bad)",  { XX } },
4666   },
4667
4668   /* PREFIX_VEX_389E */
4669   {
4670     { "(bad)",  { XX } },
4671     { "(bad)",  { XX } },
4672     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4673     { "(bad)",  { XX } },
4674   },
4675
4676   /* PREFIX_VEX_389F */
4677   {
4678     { "(bad)",  { XX } },
4679     { "(bad)",  { XX } },
4680     { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4681     { "(bad)",  { XX } },
4682   },
4683
4684   /* PREFIX_VEX_38A6 */
4685   {
4686     { "(bad)",  { XX } },
4687     { "(bad)",  { XX } },
4688     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4689     { "(bad)",  { XX } },
4690   },
4691
4692   /* PREFIX_VEX_38A7 */
4693   {
4694     { "(bad)",  { XX } },
4695     { "(bad)",  { XX } },
4696     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4697     { "(bad)",  { XX } },
4698   },
4699
4700   /* PREFIX_VEX_38A8 */
4701   {
4702     { "(bad)",  { XX } },
4703     { "(bad)",  { XX } },
4704     { "vfmadd213p%XW", { XM, Vex, EXx } },
4705     { "(bad)",  { XX } },
4706   },
4707
4708   /* PREFIX_VEX_38A9 */
4709   {
4710     { "(bad)",  { XX } },
4711     { "(bad)",  { XX } },
4712     { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4713     { "(bad)",  { XX } },
4714   },
4715
4716   /* PREFIX_VEX_38AA */
4717   {
4718     { "(bad)",  { XX } },
4719     { "(bad)",  { XX } },
4720     { "vfmsub213p%XW", { XM, Vex, EXx } },
4721     { "(bad)",  { XX } },
4722   },
4723
4724   /* PREFIX_VEX_38AB */
4725   {
4726     { "(bad)",  { XX } },
4727     { "(bad)",  { XX } },
4728     { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4729     { "(bad)",  { XX } },
4730   },
4731
4732   /* PREFIX_VEX_38AC */
4733   {
4734     { "(bad)",  { XX } },
4735     { "(bad)",  { XX } },
4736     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4737     { "(bad)",  { XX } },
4738   },
4739
4740   /* PREFIX_VEX_38AD */
4741   {
4742     { "(bad)",  { XX } },
4743     { "(bad)",  { XX } },
4744     { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4745     { "(bad)",  { XX } },
4746   },
4747
4748   /* PREFIX_VEX_38AE */
4749   {
4750     { "(bad)",  { XX } },
4751     { "(bad)",  { XX } },
4752     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4753     { "(bad)",  { XX } },
4754   },
4755
4756   /* PREFIX_VEX_38AF */
4757   {
4758     { "(bad)",  { XX } },
4759     { "(bad)",  { XX } },
4760     { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4761     { "(bad)",  { XX } },
4762   },
4763
4764   /* PREFIX_VEX_38B6 */
4765   {
4766     { "(bad)",  { XX } },
4767     { "(bad)",  { XX } },
4768     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4769     { "(bad)",  { XX } },
4770   },
4771
4772   /* PREFIX_VEX_38B7 */
4773   {
4774     { "(bad)",  { XX } },
4775     { "(bad)",  { XX } },
4776     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4777     { "(bad)",  { XX } },
4778   },
4779
4780   /* PREFIX_VEX_38B8 */
4781   {
4782     { "(bad)",  { XX } },
4783     { "(bad)",  { XX } },
4784     { "vfmadd231p%XW", { XM, Vex, EXx } },
4785     { "(bad)",  { XX } },
4786   },
4787
4788   /* PREFIX_VEX_38B9 */
4789   {
4790     { "(bad)",  { XX } },
4791     { "(bad)",  { XX } },
4792     { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4793     { "(bad)",  { XX } },
4794   },
4795
4796   /* PREFIX_VEX_38BA */
4797   {
4798     { "(bad)",  { XX } },
4799     { "(bad)",  { XX } },
4800     { "vfmsub231p%XW", { XM, Vex, EXx } },
4801     { "(bad)",  { XX } },
4802   },
4803
4804   /* PREFIX_VEX_38BB */
4805   {
4806     { "(bad)",  { XX } },
4807     { "(bad)",  { XX } },
4808     { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4809     { "(bad)",  { XX } },
4810   },
4811
4812   /* PREFIX_VEX_38BC */
4813   {
4814     { "(bad)",  { XX } },
4815     { "(bad)",  { XX } },
4816     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4817     { "(bad)",  { XX } },
4818   },
4819
4820   /* PREFIX_VEX_38BD */
4821   {
4822     { "(bad)",  { XX } },
4823     { "(bad)",  { XX } },
4824     { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4825     { "(bad)",  { XX } },
4826   },
4827
4828   /* PREFIX_VEX_38BE */
4829   {
4830     { "(bad)",  { XX } },
4831     { "(bad)",  { XX } },
4832     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4833     { "(bad)",  { XX } },
4834   },
4835
4836   /* PREFIX_VEX_38BF */
4837   {
4838     { "(bad)",  { XX } },
4839     { "(bad)",  { XX } },
4840     { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4841     { "(bad)",  { XX } },
4842   },
4843
4844   /* PREFIX_VEX_38DB */
4845   {
4846     { "(bad)",  { XX } },
4847     { "(bad)",  { XX } },
4848     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4849     { "(bad)",  { XX } },
4850   },
4851
4852   /* PREFIX_VEX_38DC */
4853   {
4854     { "(bad)",  { XX } },
4855     { "(bad)",  { XX } },
4856     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4857     { "(bad)",  { XX } },
4858   },
4859
4860   /* PREFIX_VEX_38DD */
4861   {
4862     { "(bad)",  { XX } },
4863     { "(bad)",  { XX } },
4864     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4865     { "(bad)",  { XX } },
4866   },
4867
4868   /* PREFIX_VEX_38DE */
4869   {
4870     { "(bad)",  { XX } },
4871     { "(bad)",  { XX } },
4872     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4873     { "(bad)",  { XX } },
4874   },
4875
4876   /* PREFIX_VEX_38DF */
4877   {
4878     { "(bad)",  { XX } },
4879     { "(bad)",  { XX } },
4880     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4881     { "(bad)",  { XX } },
4882   },
4883
4884   /* PREFIX_VEX_3A04 */
4885   {
4886     { "(bad)",  { XX } },
4887     { "(bad)",  { XX } },
4888     { "vpermilps", { XM, EXx, Ib } },
4889     { "(bad)",  { XX } },
4890   },
4891
4892   /* PREFIX_VEX_3A05 */
4893   {
4894     { "(bad)",  { XX } },
4895     { "(bad)",  { XX } },
4896     { "vpermilpd", { XM, EXx, Ib } },
4897     { "(bad)",  { XX } },
4898   },
4899
4900   /* PREFIX_VEX_3A06 */
4901   {
4902     { "(bad)",  { XX } },
4903     { "(bad)",  { XX } },
4904     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4905     { "(bad)",  { XX } },
4906   },
4907
4908   /* PREFIX_VEX_3A08 */
4909   {
4910     { "(bad)",  { XX } },
4911     { "(bad)",  { XX } },
4912     { "vroundps", { XM, EXx, Ib } },
4913     { "(bad)",  { XX } },
4914   },
4915
4916   /* PREFIX_VEX_3A09 */
4917   {
4918     { "(bad)",  { XX } },
4919     { "(bad)",  { XX } },
4920     { "vroundpd", { XM, EXx, Ib } },
4921     { "(bad)",  { XX } },
4922   },
4923
4924   /* PREFIX_VEX_3A0A */
4925   {
4926     { "(bad)",  { XX } },
4927     { "(bad)",  { XX } },
4928     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4929     { "(bad)",  { XX } },
4930   },
4931
4932   /* PREFIX_VEX_3A0B */
4933   {
4934     { "(bad)",  { XX } },
4935     { "(bad)",  { XX } },
4936     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4937     { "(bad)",  { XX } },
4938   },
4939
4940   /* PREFIX_VEX_3A0C */
4941   {
4942     { "(bad)",  { XX } },
4943     { "(bad)",  { XX } },
4944     { "vblendps", { XM, Vex, EXx, Ib } },
4945     { "(bad)",  { XX } },
4946   },
4947
4948   /* PREFIX_VEX_3A0D */
4949   {
4950     { "(bad)",  { XX } },
4951     { "(bad)",  { XX } },
4952     { "vblendpd", { XM, Vex, EXx, Ib } },
4953     { "(bad)",  { XX } },
4954   },
4955
4956   /* PREFIX_VEX_3A0E */
4957   {
4958     { "(bad)",  { XX } },
4959     { "(bad)",  { XX } },
4960     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4961     { "(bad)",  { XX } },
4962   },
4963
4964   /* PREFIX_VEX_3A0F */
4965   {
4966     { "(bad)",  { XX } },
4967     { "(bad)",  { XX } },
4968     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4969     { "(bad)",  { XX } },
4970   },
4971
4972   /* PREFIX_VEX_3A14 */
4973   {
4974     { "(bad)",  { XX } },
4975     { "(bad)",  { XX } },
4976     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4977     { "(bad)",  { XX } },
4978   },
4979
4980   /* PREFIX_VEX_3A15 */
4981   {
4982     { "(bad)",  { XX } },
4983     { "(bad)",  { XX } },
4984     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4985     { "(bad)",  { XX } },
4986   },
4987
4988   /* PREFIX_VEX_3A16 */
4989   {
4990     { "(bad)",  { XX } },
4991     { "(bad)",  { XX } },
4992     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4993     { "(bad)",  { XX } },
4994   },
4995
4996   /* PREFIX_VEX_3A17 */
4997   {
4998     { "(bad)",  { XX } },
4999     { "(bad)",  { XX } },
5000     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5001     { "(bad)",  { XX } },
5002   },
5003
5004   /* PREFIX_VEX_3A18 */
5005   {
5006     { "(bad)",  { XX } },
5007     { "(bad)",  { XX } },
5008     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5009     { "(bad)",  { XX } },
5010   },
5011
5012   /* PREFIX_VEX_3A19 */
5013   {
5014     { "(bad)",  { XX } },
5015     { "(bad)",  { XX } },
5016     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5017     { "(bad)",  { XX } },
5018   },
5019
5020   /* PREFIX_VEX_3A20 */
5021   {
5022     { "(bad)",  { XX } },
5023     { "(bad)",  { XX } },
5024     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5025     { "(bad)",  { XX } },
5026   },
5027
5028   /* PREFIX_VEX_3A21 */
5029   {
5030     { "(bad)",  { XX } },
5031     { "(bad)",  { XX } },
5032     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5033     { "(bad)",  { XX } },
5034   },
5035
5036   /* PREFIX_VEX_3A22 */
5037   {
5038     { "(bad)",  { XX } },
5039     { "(bad)",  { XX } },
5040     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5041     { "(bad)",  { XX } },
5042   },
5043
5044   /* PREFIX_VEX_3A40 */
5045   {
5046     { "(bad)",  { XX } },
5047     { "(bad)",  { XX } },
5048     { "vdpps",  { XM, Vex, EXx, Ib } },
5049     { "(bad)",  { XX } },
5050   },
5051
5052   /* PREFIX_VEX_3A41 */
5053   {
5054     { "(bad)",  { XX } },
5055     { "(bad)",  { XX } },
5056     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5057     { "(bad)",  { XX } },
5058   },
5059
5060   /* PREFIX_VEX_3A42 */
5061   {
5062     { "(bad)",  { XX } },
5063     { "(bad)",  { XX } },
5064     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5065     { "(bad)",  { XX } },
5066   },
5067
5068   /* PREFIX_VEX_3A44 */
5069   {
5070     { "(bad)",  { XX } },
5071     { "(bad)",  { XX } },
5072     { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5073     { "(bad)",  { XX } },
5074   },
5075
5076   /* PREFIX_VEX_3A4A */
5077   {
5078     { "(bad)",  { XX } },
5079     { "(bad)",  { XX } },
5080     { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
5081     { "(bad)",  { XX } },
5082   },
5083
5084   /* PREFIX_VEX_3A4B */
5085   {
5086     { "(bad)",  { XX } },
5087     { "(bad)",  { XX } },
5088     { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
5089     { "(bad)",  { XX } },
5090   },
5091
5092   /* PREFIX_VEX_3A4C */
5093   {
5094     { "(bad)",  { XX } },
5095     { "(bad)",  { XX } },
5096     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5097     { "(bad)",  { XX } },
5098   },
5099
5100   /* PREFIX_VEX_3A5C */
5101   {
5102     { "(bad)",  { XX } },
5103     { "(bad)",  { XX } },
5104     { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5105     { "(bad)",  { XX } },
5106   },
5107
5108   /* PREFIX_VEX_3A5D */
5109   {
5110     { "(bad)",  { XX } },
5111     { "(bad)",  { XX } },
5112     { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5113     { "(bad)",  { XX } },
5114   },
5115
5116   /* PREFIX_VEX_3A5E */
5117   {
5118     { "(bad)",  { XX } },
5119     { "(bad)",  { XX } },
5120     { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5121     { "(bad)",  { XX } },
5122   },
5123
5124   /* PREFIX_VEX_3A5F */
5125   {
5126     { "(bad)",  { XX } },
5127     { "(bad)",  { XX } },
5128     { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5129     { "(bad)",  { XX } },
5130   },
5131
5132   /* PREFIX_VEX_3A60 */
5133   {
5134     { "(bad)",  { XX } },
5135     { "(bad)",  { XX } },
5136     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5137     { "(bad)",  { XX } },
5138   },
5139
5140   /* PREFIX_VEX_3A61 */
5141   {
5142     { "(bad)",  { XX } },
5143     { "(bad)",  { XX } },
5144     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5145     { "(bad)",  { XX } },
5146   },
5147
5148   /* PREFIX_VEX_3A62 */
5149   {
5150     { "(bad)",  { XX } },
5151     { "(bad)",  { XX } },
5152     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5153     { "(bad)",  { XX } },
5154   },
5155
5156   /* PREFIX_VEX_3A63 */
5157   {
5158     { "(bad)",  { XX } },
5159     { "(bad)",  { XX } },
5160     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5161     { "(bad)",  { XX } },
5162   },
5163
5164   /* PREFIX_VEX_3A68 */
5165   {
5166     { "(bad)",  { XX } },
5167     { "(bad)",  { XX } },
5168     { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5169     { "(bad)",  { XX } },
5170   },
5171
5172   /* PREFIX_VEX_3A69 */
5173   {
5174     { "(bad)",  { XX } },
5175     { "(bad)",  { XX } },
5176     { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5177     { "(bad)",  { XX } },
5178   },
5179
5180   /* PREFIX_VEX_3A6A */
5181   {
5182     { "(bad)",  { XX } },
5183     { "(bad)",  { XX } },
5184     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5185     { "(bad)",  { XX } },
5186   },
5187
5188   /* PREFIX_VEX_3A6B */
5189   {
5190     { "(bad)",  { XX } },
5191     { "(bad)",  { XX } },
5192     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5193     { "(bad)",  { XX } },
5194   },
5195
5196   /* PREFIX_VEX_3A6C */
5197   {
5198     { "(bad)",  { XX } },
5199     { "(bad)",  { XX } },
5200     { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5201     { "(bad)",  { XX } },
5202   },
5203
5204   /* PREFIX_VEX_3A6D */
5205   {
5206     { "(bad)",  { XX } },
5207     { "(bad)",  { XX } },
5208     { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5209     { "(bad)",  { XX } },
5210   },
5211
5212   /* PREFIX_VEX_3A6E */
5213   {
5214     { "(bad)",  { XX } },
5215     { "(bad)",  { XX } },
5216     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5217     { "(bad)",  { XX } },
5218   },
5219
5220   /* PREFIX_VEX_3A6F */
5221   {
5222     { "(bad)",  { XX } },
5223     { "(bad)",  { XX } },
5224     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5225     { "(bad)",  { XX } },
5226   },
5227
5228   /* PREFIX_VEX_3A78 */
5229   {
5230     { "(bad)",  { XX } },
5231     { "(bad)",  { XX } },
5232     { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5233     { "(bad)",  { XX } },
5234   },
5235
5236   /* PREFIX_VEX_3A79 */
5237   {
5238     { "(bad)",  { XX } },
5239     { "(bad)",  { XX } },
5240     { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5241     { "(bad)",  { XX } },
5242   },
5243
5244   /* PREFIX_VEX_3A7A */
5245   {
5246     { "(bad)",  { XX } },
5247     { "(bad)",  { XX } },
5248     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5249     { "(bad)",  { XX } },
5250   },
5251
5252   /* PREFIX_VEX_3A7B */
5253   {
5254     { "(bad)",  { XX } },
5255     { "(bad)",  { XX } },
5256     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5257     { "(bad)",  { XX } },
5258   },
5259
5260   /* PREFIX_VEX_3A7C */
5261   {
5262     { "(bad)",  { XX } },
5263     { "(bad)",  { XX } },
5264     { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5265     { "(bad)",  { XX } },
5266   },
5267
5268   /* PREFIX_VEX_3A7D */
5269   {
5270     { "(bad)",  { XX } },
5271     { "(bad)",  { XX } },
5272     { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5273     { "(bad)",  { XX } },
5274   },
5275
5276   /* PREFIX_VEX_3A7E */
5277   {
5278     { "(bad)",  { XX } },
5279     { "(bad)",  { XX } },
5280     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5281     { "(bad)",  { XX } },
5282   },
5283
5284   /* PREFIX_VEX_3A7F */
5285   {
5286     { "(bad)",  { XX } },
5287     { "(bad)",  { XX } },
5288     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5289     { "(bad)",  { XX } },
5290   },
5291
5292   /* PREFIX_VEX_3ADF */
5293   {
5294     { "(bad)",  { XX } },
5295     { "(bad)",  { XX } },
5296     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5297     { "(bad)",  { XX } },
5298   },
5299 };
5300
5301 static const struct dis386 x86_64_table[][2] = {
5302   /* X86_64_06 */
5303   {
5304     { "push{T|}", { es } },
5305     { "(bad)", { XX } },
5306   },
5307
5308   /* X86_64_07 */
5309   {
5310     { "pop{T|}", { es } },
5311     { "(bad)", { XX } },
5312   },
5313
5314   /* X86_64_0D */
5315   {
5316     { "push{T|}", { cs } },
5317     { "(bad)", { XX } },
5318   },
5319
5320   /* X86_64_16 */
5321   {
5322     { "push{T|}", { ss } },
5323     { "(bad)", { XX } },
5324   },
5325
5326   /* X86_64_17 */
5327   {
5328     { "pop{T|}", { ss } },
5329     { "(bad)", { XX } },
5330   },
5331
5332   /* X86_64_1E */
5333   {
5334     { "push{T|}", { ds } },
5335     { "(bad)", { XX } },
5336   },
5337
5338   /* X86_64_1F */
5339   {
5340     { "pop{T|}", { ds } },
5341     { "(bad)", { XX } },
5342   },
5343
5344   /* X86_64_27 */
5345   {
5346     { "daa", { XX } },
5347     { "(bad)", { XX } },
5348   },
5349
5350   /* X86_64_2F */
5351   {
5352     { "das", { XX } },
5353     { "(bad)", { XX } },
5354   },
5355
5356   /* X86_64_37 */
5357   {
5358     { "aaa", { XX } },
5359     { "(bad)", { XX } },
5360   },
5361
5362   /* X86_64_3F */
5363   {
5364     { "aas", { XX } },
5365     { "(bad)", { XX } },
5366   },
5367
5368   /* X86_64_60 */
5369   {
5370     { "pusha{P|}", { XX } },
5371     { "(bad)", { XX } },
5372   },
5373
5374   /* X86_64_61 */
5375   {
5376     { "popa{P|}", { XX } },
5377     { "(bad)", { XX } },
5378   },
5379
5380   /* X86_64_62 */
5381   {
5382     { MOD_TABLE (MOD_62_32BIT) },
5383     { "(bad)", { XX } },
5384   },
5385
5386   /* X86_64_63 */
5387   {
5388     { "arpl", { Ew, Gw } },
5389     { "movs{lq|xd}", { Gv, Ed } },
5390   },
5391
5392   /* X86_64_6D */
5393   {
5394     { "ins{R|}", { Yzr, indirDX } },
5395     { "ins{G|}", { Yzr, indirDX } },
5396   },
5397
5398   /* X86_64_6F */
5399   {
5400     { "outs{R|}", { indirDXr, Xz } },
5401     { "outs{G|}", { indirDXr, Xz } },
5402   },
5403
5404   /* X86_64_9A */
5405   {
5406     { "Jcall{T|}", { Ap } },
5407     { "(bad)", { XX } },
5408   },
5409
5410   /* X86_64_C4 */
5411   {
5412     { MOD_TABLE (MOD_C4_32BIT) },
5413     { VEX_C4_TABLE (VEX_0F) },
5414   },
5415
5416   /* X86_64_C5 */
5417   {
5418     { MOD_TABLE (MOD_C5_32BIT) },
5419     { VEX_C5_TABLE (VEX_0F) },
5420   },
5421
5422   /* X86_64_CE */
5423   {
5424     { "into", { XX } },
5425     { "(bad)", { XX } },
5426   },
5427
5428   /* X86_64_D4 */
5429   {
5430     { "aam", { sIb } },
5431     { "(bad)", { XX } },
5432   },
5433
5434   /* X86_64_D5 */
5435   {
5436     { "aad", { sIb } },
5437     { "(bad)", { XX } },
5438   },
5439
5440   /* X86_64_EA */
5441   {
5442     { "Jjmp{T|}", { Ap } },
5443     { "(bad)", { XX } },
5444   },
5445
5446   /* X86_64_0F01_REG_0 */
5447   {
5448     { "sgdt{Q|IQ}", { M } },
5449     { "sgdt", { M } },
5450   },
5451
5452   /* X86_64_0F01_REG_1 */
5453   {
5454     { "sidt{Q|IQ}", { M } },
5455     { "sidt", { M } },
5456   },
5457
5458   /* X86_64_0F01_REG_2 */
5459   {
5460     { "lgdt{Q|Q}", { M } },
5461     { "lgdt", { M } },
5462   },
5463
5464   /* X86_64_0F01_REG_3 */
5465   {
5466     { "lidt{Q|Q}", { M } },
5467     { "lidt", { M } },
5468   },
5469 };
5470
5471 static const struct dis386 three_byte_table[][256] = {
5472
5473   /* THREE_BYTE_0F38 */
5474   {
5475     /* 00 */
5476     { "pshufb",         { MX, EM } },
5477     { "phaddw",         { MX, EM } },
5478     { "phaddd",         { MX, EM } },
5479     { "phaddsw",        { MX, EM } },
5480     { "pmaddubsw",      { MX, EM } },
5481     { "phsubw",         { MX, EM } },
5482     { "phsubd",         { MX, EM } },
5483     { "phsubsw",        { MX, EM } },
5484     /* 08 */
5485     { "psignb",         { MX, EM } },
5486     { "psignw",         { MX, EM } },
5487     { "psignd",         { MX, EM } },
5488     { "pmulhrsw",       { MX, EM } },
5489     { "(bad)",          { XX } },
5490     { "(bad)",          { XX } },
5491     { "(bad)",          { XX } },
5492     { "(bad)",          { XX } },
5493     /* 10 */
5494     { PREFIX_TABLE (PREFIX_0F3810) },
5495     { "(bad)",          { XX } },
5496     { "(bad)",          { XX } },
5497     { "(bad)",          { XX } },
5498     { PREFIX_TABLE (PREFIX_0F3814) },
5499     { PREFIX_TABLE (PREFIX_0F3815) },
5500     { "(bad)",          { XX } },
5501     { PREFIX_TABLE (PREFIX_0F3817) },
5502     /* 18 */
5503     { "(bad)",          { XX } },
5504     { "(bad)",          { XX } },
5505     { "(bad)",          { XX } },
5506     { "(bad)",          { XX } },
5507     { "pabsb",          { MX, EM } },
5508     { "pabsw",          { MX, EM } },
5509     { "pabsd",          { MX, EM } },
5510     { "(bad)",          { XX } },
5511     /* 20 */
5512     { PREFIX_TABLE (PREFIX_0F3820) },
5513     { PREFIX_TABLE (PREFIX_0F3821) },
5514     { PREFIX_TABLE (PREFIX_0F3822) },
5515     { PREFIX_TABLE (PREFIX_0F3823) },
5516     { PREFIX_TABLE (PREFIX_0F3824) },
5517     { PREFIX_TABLE (PREFIX_0F3825) },
5518     { "(bad)",          { XX } },
5519     { "(bad)",          { XX } },
5520     /* 28 */
5521     { PREFIX_TABLE (PREFIX_0F3828) },
5522     { PREFIX_TABLE (PREFIX_0F3829) },
5523     { PREFIX_TABLE (PREFIX_0F382A) },
5524     { PREFIX_TABLE (PREFIX_0F382B) },
5525     { "(bad)",          { XX } },
5526     { "(bad)",          { XX } },
5527     { "(bad)",          { XX } },
5528     { "(bad)",          { XX } },
5529     /* 30 */
5530     { PREFIX_TABLE (PREFIX_0F3830) },
5531     { PREFIX_TABLE (PREFIX_0F3831) },
5532     { PREFIX_TABLE (PREFIX_0F3832) },
5533     { PREFIX_TABLE (PREFIX_0F3833) },
5534     { PREFIX_TABLE (PREFIX_0F3834) },
5535     { PREFIX_TABLE (PREFIX_0F3835) },
5536     { "(bad)",          { XX } },
5537     { PREFIX_TABLE (PREFIX_0F3837) },
5538     /* 38 */
5539     { PREFIX_TABLE (PREFIX_0F3838) },
5540     { PREFIX_TABLE (PREFIX_0F3839) },
5541     { PREFIX_TABLE (PREFIX_0F383A) },
5542     { PREFIX_TABLE (PREFIX_0F383B) },
5543     { PREFIX_TABLE (PREFIX_0F383C) },
5544     { PREFIX_TABLE (PREFIX_0F383D) },
5545     { PREFIX_TABLE (PREFIX_0F383E) },
5546     { PREFIX_TABLE (PREFIX_0F383F) },
5547     /* 40 */
5548     { PREFIX_TABLE (PREFIX_0F3840) },
5549     { PREFIX_TABLE (PREFIX_0F3841) },
5550     { "(bad)",          { XX } },
5551     { "(bad)",          { XX } },
5552     { "(bad)",          { XX } },
5553     { "(bad)",          { XX } },
5554     { "(bad)",          { XX } },
5555     { "(bad)",          { XX } },
5556     /* 48 */
5557     { "(bad)",          { XX } },
5558     { "(bad)",          { XX } },
5559     { "(bad)",          { XX } },
5560     { "(bad)",          { XX } },
5561     { "(bad)",          { XX } },
5562     { "(bad)",          { XX } },
5563     { "(bad)",          { XX } },
5564     { "(bad)",          { XX } },
5565     /* 50 */
5566     { "(bad)",          { XX } },
5567     { "(bad)",          { XX } },
5568     { "(bad)",          { XX } },
5569     { "(bad)",          { XX } },
5570     { "(bad)",          { XX } },
5571     { "(bad)",          { XX } },
5572     { "(bad)",          { XX } },
5573     { "(bad)",          { XX } },
5574     /* 58 */
5575     { "(bad)",          { XX } },
5576     { "(bad)",          { XX } },
5577     { "(bad)",          { XX } },
5578     { "(bad)",          { XX } },
5579     { "(bad)",          { XX } },
5580     { "(bad)",          { XX } },
5581     { "(bad)",          { XX } },
5582     { "(bad)",          { XX } },
5583     /* 60 */
5584     { "(bad)",          { XX } },
5585     { "(bad)",          { XX } },
5586     { "(bad)",          { XX } },
5587     { "(bad)",          { XX } },
5588     { "(bad)",          { XX } },
5589     { "(bad)",          { XX } },
5590     { "(bad)",          { XX } },
5591     { "(bad)",          { XX } },
5592     /* 68 */
5593     { "(bad)",          { XX } },
5594     { "(bad)",          { XX } },
5595     { "(bad)",          { XX } },
5596     { "(bad)",          { XX } },
5597     { "(bad)",          { XX } },
5598     { "(bad)",          { XX } },
5599     { "(bad)",          { XX } },
5600     { "(bad)",          { XX } },
5601     /* 70 */
5602     { "(bad)",          { XX } },
5603     { "(bad)",          { XX } },
5604     { "(bad)",          { XX } },
5605     { "(bad)",          { XX } },
5606     { "(bad)",          { XX } },
5607     { "(bad)",          { XX } },
5608     { "(bad)",          { XX } },
5609     { "(bad)",          { XX } },
5610     /* 78 */
5611     { "(bad)",          { XX } },
5612     { "(bad)",          { XX } },
5613     { "(bad)",          { XX } },
5614     { "(bad)",          { XX } },
5615     { "(bad)",          { XX } },
5616     { "(bad)",          { XX } },
5617     { "(bad)",          { XX } },
5618     { "(bad)",          { XX } },
5619     /* 80 */
5620     { PREFIX_TABLE (PREFIX_0F3880) },
5621     { PREFIX_TABLE (PREFIX_0F3881) },
5622     { "(bad)",          { XX } },
5623     { "(bad)",          { XX } },
5624     { "(bad)",          { XX } },
5625     { "(bad)",          { XX } },
5626     { "(bad)",          { XX } },
5627     { "(bad)",          { XX } },
5628     /* 88 */
5629     { "(bad)",          { XX } },
5630     { "(bad)",          { XX } },
5631     { "(bad)",          { XX } },
5632     { "(bad)",          { XX } },
5633     { "(bad)",          { XX } },
5634     { "(bad)",          { XX } },
5635     { "(bad)",          { XX } },
5636     { "(bad)",          { XX } },
5637     /* 90 */
5638     { "(bad)",          { XX } },
5639     { "(bad)",          { XX } },
5640     { "(bad)",          { XX } },
5641     { "(bad)",          { XX } },
5642     { "(bad)",          { XX } },
5643     { "(bad)",          { XX } },
5644     { "(bad)",          { XX } },
5645     { "(bad)",          { XX } },
5646     /* 98 */
5647     { "(bad)",          { XX } },
5648     { "(bad)",          { XX } },
5649     { "(bad)",          { XX } },
5650     { "(bad)",          { XX } },
5651     { "(bad)",          { XX } },
5652     { "(bad)",          { XX } },
5653     { "(bad)",          { XX } },
5654     { "(bad)",          { XX } },
5655     /* a0 */
5656     { "(bad)",          { XX } },
5657     { "(bad)",          { XX } },
5658     { "(bad)",          { XX } },
5659     { "(bad)",          { XX } },
5660     { "(bad)",          { XX } },
5661     { "(bad)",          { XX } },
5662     { "(bad)",          { XX } },
5663     { "(bad)",          { XX } },
5664     /* a8 */
5665     { "(bad)",          { XX } },
5666     { "(bad)",          { XX } },
5667     { "(bad)",          { XX } },
5668     { "(bad)",          { XX } },
5669     { "(bad)",          { XX } },
5670     { "(bad)",          { XX } },
5671     { "(bad)",          { XX } },
5672     { "(bad)",          { XX } },
5673     /* b0 */
5674     { "(bad)",          { XX } },
5675     { "(bad)",          { XX } },
5676     { "(bad)",          { XX } },
5677     { "(bad)",          { XX } },
5678     { "(bad)",          { XX } },
5679     { "(bad)",          { XX } },
5680     { "(bad)",          { XX } },
5681     { "(bad)",          { XX } },
5682     /* b8 */
5683     { "(bad)",          { XX } },
5684     { "(bad)",          { XX } },
5685     { "(bad)",          { XX } },
5686     { "(bad)",          { XX } },
5687     { "(bad)",          { XX } },
5688     { "(bad)",          { XX } },
5689     { "(bad)",          { XX } },
5690     { "(bad)",          { XX } },
5691     /* c0 */
5692     { "(bad)",          { XX } },
5693     { "(bad)",          { XX } },
5694     { "(bad)",          { XX } },
5695     { "(bad)",          { XX } },
5696     { "(bad)",          { XX } },
5697     { "(bad)",          { XX } },
5698     { "(bad)",          { XX } },
5699     { "(bad)",          { XX } },
5700     /* c8 */
5701     { "(bad)",          { XX } },
5702     { "(bad)",          { XX } },
5703     { "(bad)",          { XX } },
5704     { "(bad)",          { XX } },
5705     { "(bad)",          { XX } },
5706     { "(bad)",          { XX } },
5707     { "(bad)",          { XX } },
5708     { "(bad)",          { XX } },
5709     /* d0 */
5710     { "(bad)",          { XX } },
5711     { "(bad)",          { XX } },
5712     { "(bad)",          { XX } },
5713     { "(bad)",          { XX } },
5714     { "(bad)",          { XX } },
5715     { "(bad)",          { XX } },
5716     { "(bad)",          { XX } },
5717     { "(bad)",          { XX } },
5718     /* d8 */
5719     { "(bad)",          { XX } },
5720     { "(bad)",          { XX } },
5721     { "(bad)",          { XX } },
5722     { PREFIX_TABLE (PREFIX_0F38DB) },
5723     { PREFIX_TABLE (PREFIX_0F38DC) },
5724     { PREFIX_TABLE (PREFIX_0F38DD) },
5725     { PREFIX_TABLE (PREFIX_0F38DE) },
5726     { PREFIX_TABLE (PREFIX_0F38DF) },
5727     /* e0 */
5728     { "(bad)",          { XX } },
5729     { "(bad)",          { XX } },
5730     { "(bad)",          { XX } },
5731     { "(bad)",          { XX } },
5732     { "(bad)",          { XX } },
5733     { "(bad)",          { XX } },
5734     { "(bad)",          { XX } },
5735     { "(bad)",          { XX } },
5736     /* e8 */
5737     { "(bad)",          { XX } },
5738     { "(bad)",          { XX } },
5739     { "(bad)",          { XX } },
5740     { "(bad)",          { XX } },
5741     { "(bad)",          { XX } },
5742     { "(bad)",          { XX } },
5743     { "(bad)",          { XX } },
5744     { "(bad)",          { XX } },
5745     /* f0 */
5746     { PREFIX_TABLE (PREFIX_0F38F0) },
5747     { PREFIX_TABLE (PREFIX_0F38F1) },
5748     { "(bad)",          { XX } },
5749     { "(bad)",          { XX } },
5750     { "(bad)",          { XX } },
5751     { "(bad)",          { XX } },
5752     { "(bad)",          { XX } },
5753     { "(bad)",          { XX } },
5754     /* f8 */
5755     { "(bad)",          { XX } },
5756     { "(bad)",          { XX } },
5757     { "(bad)",          { XX } },
5758     { "(bad)",          { XX } },
5759     { "(bad)",          { XX } },
5760     { "(bad)",          { XX } },
5761     { "(bad)",          { XX } },
5762     { "(bad)",          { XX } },
5763   },
5764   /* THREE_BYTE_0F3A */
5765   {
5766     /* 00 */
5767     { "(bad)",          { XX } },
5768     { "(bad)",          { XX } },
5769     { "(bad)",          { XX } },
5770     { "(bad)",          { XX } },
5771     { "(bad)",          { XX } },
5772     { "(bad)",          { XX } },
5773     { "(bad)",          { XX } },
5774     { "(bad)",          { XX } },
5775     /* 08 */
5776     { PREFIX_TABLE (PREFIX_0F3A08) },
5777     { PREFIX_TABLE (PREFIX_0F3A09) },
5778     { PREFIX_TABLE (PREFIX_0F3A0A) },
5779     { PREFIX_TABLE (PREFIX_0F3A0B) },
5780     { PREFIX_TABLE (PREFIX_0F3A0C) },
5781     { PREFIX_TABLE (PREFIX_0F3A0D) },
5782     { PREFIX_TABLE (PREFIX_0F3A0E) },
5783     { "palignr",        { MX, EM, Ib } },
5784     /* 10 */
5785     { "(bad)",          { XX } },
5786     { "(bad)",          { XX } },
5787     { "(bad)",          { XX } },
5788     { "(bad)",          { XX } },
5789     { PREFIX_TABLE (PREFIX_0F3A14) },
5790     { PREFIX_TABLE (PREFIX_0F3A15) },
5791     { PREFIX_TABLE (PREFIX_0F3A16) },
5792     { PREFIX_TABLE (PREFIX_0F3A17) },
5793     /* 18 */
5794     { "(bad)",          { XX } },
5795     { "(bad)",          { XX } },
5796     { "(bad)",          { XX } },
5797     { "(bad)",          { XX } },
5798     { "(bad)",          { XX } },
5799     { "(bad)",          { XX } },
5800     { "(bad)",          { XX } },
5801     { "(bad)",          { XX } },
5802     /* 20 */
5803     { PREFIX_TABLE (PREFIX_0F3A20) },
5804     { PREFIX_TABLE (PREFIX_0F3A21) },
5805     { PREFIX_TABLE (PREFIX_0F3A22) },
5806     { "(bad)",          { XX } },
5807     { "(bad)",          { XX } },
5808     { "(bad)",          { XX } },
5809     { "(bad)",          { XX } },
5810     { "(bad)",          { XX } },
5811     /* 28 */
5812     { "(bad)",          { XX } },
5813     { "(bad)",          { XX } },
5814     { "(bad)",          { XX } },
5815     { "(bad)",          { XX } },
5816     { "(bad)",          { XX } },
5817     { "(bad)",          { XX } },
5818     { "(bad)",          { XX } },
5819     { "(bad)",          { XX } },
5820     /* 30 */
5821     { "(bad)",          { XX } },
5822     { "(bad)",          { XX } },
5823     { "(bad)",          { XX } },
5824     { "(bad)",          { XX } },
5825     { "(bad)",          { XX } },
5826     { "(bad)",          { XX } },
5827     { "(bad)",          { XX } },
5828     { "(bad)",          { XX } },
5829     /* 38 */
5830     { "(bad)",          { XX } },
5831     { "(bad)",          { XX } },
5832     { "(bad)",          { XX } },
5833     { "(bad)",          { XX } },
5834     { "(bad)",          { XX } },
5835     { "(bad)",          { XX } },
5836     { "(bad)",          { XX } },
5837     { "(bad)",          { XX } },
5838     /* 40 */
5839     { PREFIX_TABLE (PREFIX_0F3A40) },
5840     { PREFIX_TABLE (PREFIX_0F3A41) },
5841     { PREFIX_TABLE (PREFIX_0F3A42) },
5842     { "(bad)",          { XX } },
5843     { PREFIX_TABLE (PREFIX_0F3A44) },
5844     { "(bad)",          { XX } },
5845     { "(bad)",          { XX } },
5846     { "(bad)",          { XX } },
5847     /* 48 */
5848     { "(bad)",          { XX } },
5849     { "(bad)",          { XX } },
5850     { "(bad)",          { XX } },
5851     { "(bad)",          { XX } },
5852     { "(bad)",          { XX } },
5853     { "(bad)",          { XX } },
5854     { "(bad)",          { XX } },
5855     { "(bad)",          { XX } },
5856     /* 50 */
5857     { "(bad)",          { XX } },
5858     { "(bad)",          { XX } },
5859     { "(bad)",          { XX } },
5860     { "(bad)",          { XX } },
5861     { "(bad)",          { XX } },
5862     { "(bad)",          { XX } },
5863     { "(bad)",          { XX } },
5864     { "(bad)",          { XX } },
5865     /* 58 */
5866     { "(bad)",          { XX } },
5867     { "(bad)",          { XX } },
5868     { "(bad)",          { XX } },
5869     { "(bad)",          { XX } },
5870     { "(bad)",          { XX } },
5871     { "(bad)",          { XX } },
5872     { "(bad)",          { XX } },
5873     { "(bad)",          { XX } },
5874     /* 60 */
5875     { PREFIX_TABLE (PREFIX_0F3A60) },
5876     { PREFIX_TABLE (PREFIX_0F3A61) },
5877     { PREFIX_TABLE (PREFIX_0F3A62) },
5878     { PREFIX_TABLE (PREFIX_0F3A63) },
5879     { "(bad)",          { XX } },
5880     { "(bad)",          { XX } },
5881     { "(bad)",          { XX } },
5882     { "(bad)",          { XX } },
5883     /* 68 */
5884     { "(bad)",          { XX } },
5885     { "(bad)",          { XX } },
5886     { "(bad)",          { XX } },
5887     { "(bad)",          { XX } },
5888     { "(bad)",          { XX } },
5889     { "(bad)",          { XX } },
5890     { "(bad)",          { XX } },
5891     { "(bad)",          { XX } },
5892     /* 70 */
5893     { "(bad)",          { XX } },
5894     { "(bad)",          { XX } },
5895     { "(bad)",          { XX } },
5896     { "(bad)",          { XX } },
5897     { "(bad)",          { XX } },
5898     { "(bad)",          { XX } },
5899     { "(bad)",          { XX } },
5900     { "(bad)",          { XX } },
5901     /* 78 */
5902     { "(bad)",          { XX } },
5903     { "(bad)",          { XX } },
5904     { "(bad)",          { XX } },
5905     { "(bad)",          { XX } },
5906     { "(bad)",          { XX } },
5907     { "(bad)",          { XX } },
5908     { "(bad)",          { XX } },
5909     { "(bad)",          { XX } },
5910     /* 80 */
5911     { "(bad)",          { XX } },
5912     { "(bad)",          { XX } },
5913     { "(bad)",          { XX } },
5914     { "(bad)",          { XX } },
5915     { "(bad)",          { XX } },
5916     { "(bad)",          { XX } },
5917     { "(bad)",          { XX } },
5918     { "(bad)",          { XX } },
5919     /* 88 */
5920     { "(bad)",          { XX } },
5921     { "(bad)",          { XX } },
5922     { "(bad)",          { XX } },
5923     { "(bad)",          { XX } },
5924     { "(bad)",          { XX } },
5925     { "(bad)",          { XX } },
5926     { "(bad)",          { XX } },
5927     { "(bad)",          { XX } },
5928     /* 90 */
5929     { "(bad)",          { XX } },
5930     { "(bad)",          { XX } },
5931     { "(bad)",          { XX } },
5932     { "(bad)",          { XX } },
5933     { "(bad)",          { XX } },
5934     { "(bad)",          { XX } },
5935     { "(bad)",          { XX } },
5936     { "(bad)",          { XX } },
5937     /* 98 */
5938     { "(bad)",          { XX } },
5939     { "(bad)",          { XX } },
5940     { "(bad)",          { XX } },
5941     { "(bad)",          { XX } },
5942     { "(bad)",          { XX } },
5943     { "(bad)",          { XX } },
5944     { "(bad)",          { XX } },
5945     { "(bad)",          { XX } },
5946     /* a0 */
5947     { "(bad)",          { XX } },
5948     { "(bad)",          { XX } },
5949     { "(bad)",          { XX } },
5950     { "(bad)",          { XX } },
5951     { "(bad)",          { XX } },
5952     { "(bad)",          { XX } },
5953     { "(bad)",          { XX } },
5954     { "(bad)",          { XX } },
5955     /* a8 */
5956     { "(bad)",          { XX } },
5957     { "(bad)",          { XX } },
5958     { "(bad)",          { XX } },
5959     { "(bad)",          { XX } },
5960     { "(bad)",          { XX } },
5961     { "(bad)",          { XX } },
5962     { "(bad)",          { XX } },
5963     { "(bad)",          { XX } },
5964     /* b0 */
5965     { "(bad)",          { XX } },
5966     { "(bad)",          { XX } },
5967     { "(bad)",          { XX } },
5968     { "(bad)",          { XX } },
5969     { "(bad)",          { XX } },
5970     { "(bad)",          { XX } },
5971     { "(bad)",          { XX } },
5972     { "(bad)",          { XX } },
5973     /* b8 */
5974     { "(bad)",          { XX } },
5975     { "(bad)",          { XX } },
5976     { "(bad)",          { XX } },
5977     { "(bad)",          { XX } },
5978     { "(bad)",          { XX } },
5979     { "(bad)",          { XX } },
5980     { "(bad)",          { XX } },
5981     { "(bad)",          { XX } },
5982     /* c0 */
5983     { "(bad)",          { XX } },
5984     { "(bad)",          { XX } },
5985     { "(bad)",          { XX } },
5986     { "(bad)",          { XX } },
5987     { "(bad)",          { XX } },
5988     { "(bad)",          { XX } },
5989     { "(bad)",          { XX } },
5990     { "(bad)",          { XX } },
5991     /* c8 */
5992     { "(bad)",          { XX } },
5993     { "(bad)",          { XX } },
5994     { "(bad)",          { XX } },
5995     { "(bad)",          { XX } },
5996     { "(bad)",          { XX } },
5997     { "(bad)",          { XX } },
5998     { "(bad)",          { XX } },
5999     { "(bad)",          { XX } },
6000     /* d0 */
6001     { "(bad)",          { XX } },
6002     { "(bad)",          { XX } },
6003     { "(bad)",          { XX } },
6004     { "(bad)",          { XX } },
6005     { "(bad)",          { XX } },
6006     { "(bad)",          { XX } },
6007     { "(bad)",          { XX } },
6008     { "(bad)",          { XX } },
6009     /* d8 */
6010     { "(bad)",          { XX } },
6011     { "(bad)",          { XX } },
6012     { "(bad)",          { XX } },
6013     { "(bad)",          { XX } },
6014     { "(bad)",          { XX } },
6015     { "(bad)",          { XX } },
6016     { "(bad)",          { XX } },
6017     { PREFIX_TABLE (PREFIX_0F3ADF) },
6018     /* e0 */
6019     { "(bad)",          { XX } },
6020     { "(bad)",          { XX } },
6021     { "(bad)",          { XX } },
6022     { "(bad)",          { XX } },
6023     { "(bad)",          { XX } },
6024     { "(bad)",          { XX } },
6025     { "(bad)",          { XX } },
6026     { "(bad)",          { XX } },
6027     /* e8 */
6028     { "(bad)",          { XX } },
6029     { "(bad)",          { XX } },
6030     { "(bad)",          { XX } },
6031     { "(bad)",          { XX } },
6032     { "(bad)",          { XX } },
6033     { "(bad)",          { XX } },
6034     { "(bad)",          { XX } },
6035     { "(bad)",          { XX } },
6036     /* f0 */
6037     { "(bad)",          { XX } },
6038     { "(bad)",          { XX } },
6039     { "(bad)",          { XX } },
6040     { "(bad)",          { XX } },
6041     { "(bad)",          { XX } },
6042     { "(bad)",          { XX } },
6043     { "(bad)",          { XX } },
6044     { "(bad)",          { XX } },
6045     /* f8 */
6046     { "(bad)",          { XX } },
6047     { "(bad)",          { XX } },
6048     { "(bad)",          { XX } },
6049     { "(bad)",          { XX } },
6050     { "(bad)",          { XX } },
6051     { "(bad)",          { XX } },
6052     { "(bad)",          { XX } },
6053     { "(bad)",          { XX } },
6054   },
6055
6056   /* THREE_BYTE_0F7A */
6057   {
6058     /* 00 */
6059     { "(bad)",          { XX } },
6060     { "(bad)",          { XX } },
6061     { "(bad)",          { XX } },
6062     { "(bad)",          { XX } },
6063     { "(bad)",          { XX } },
6064     { "(bad)",          { XX } },
6065     { "(bad)",          { XX } },
6066     { "(bad)",          { XX } },
6067     /* 08 */
6068     { "(bad)",          { XX } },
6069     { "(bad)",          { XX } },
6070     { "(bad)",          { XX } },
6071     { "(bad)",          { XX } },
6072     { "(bad)",          { XX } },
6073     { "(bad)",          { XX } },
6074     { "(bad)",          { XX } },
6075     { "(bad)",          { XX } },
6076     /* 10 */
6077     { "(bad)",          { XX } },
6078     { "(bad)",          { XX } },
6079     { "(bad)",          { XX } },
6080     { "(bad)",          { XX } },
6081     { "(bad)",          { XX } },
6082     { "(bad)",          { XX } },
6083     { "(bad)",          { XX } },
6084     { "(bad)",          { XX } },
6085     /* 18 */
6086     { "(bad)",          { XX } },
6087     { "(bad)",          { XX } },
6088     { "(bad)",          { XX } },
6089     { "(bad)",          { XX } },
6090     { "(bad)",          { XX } },
6091     { "(bad)",          { XX } },
6092     { "(bad)",          { XX } },
6093     { "(bad)",          { XX } },
6094     /* 20 */
6095     { "ptest",          { XX } },
6096     { "(bad)",          { XX } },
6097     { "(bad)",          { XX } },
6098     { "(bad)",          { XX } },
6099     { "(bad)",          { XX } },
6100     { "(bad)",          { XX } },
6101     { "(bad)",          { XX } },
6102     { "(bad)",          { XX } },
6103     /* 28 */
6104     { "(bad)",          { XX } },
6105     { "(bad)",          { XX } },
6106     { "(bad)",          { XX } },
6107     { "(bad)",          { XX } },
6108     { "(bad)",          { XX } },
6109     { "(bad)",          { XX } },
6110     { "(bad)",          { XX } },
6111     { "(bad)",          { XX } },
6112     /* 30 */
6113     { "(bad)",          { XX } },
6114     { "(bad)",          { XX } },
6115     { "(bad)",          { XX } },
6116     { "(bad)",          { XX } },
6117     { "(bad)",          { XX } },
6118     { "(bad)",          { XX } },
6119     { "(bad)",          { XX } },
6120     { "(bad)",          { XX } },
6121     /* 38 */
6122     { "(bad)",          { XX } },
6123     { "(bad)",          { XX } },
6124     { "(bad)",          { XX } },
6125     { "(bad)",          { XX } },
6126     { "(bad)",          { XX } },
6127     { "(bad)",          { XX } },
6128     { "(bad)",          { XX } },
6129     { "(bad)",          { XX } },
6130     /* 40 */
6131     { "(bad)",          { XX } },
6132     { "phaddbw",        { XM, EXq } },
6133     { "phaddbd",        { XM, EXq } },
6134     { "phaddbq",        { XM, EXq } },
6135     { "(bad)",          { XX } },
6136     { "(bad)",          { XX } },
6137     { "phaddwd",        { XM, EXq } },
6138     { "phaddwq",        { XM, EXq } },
6139     /* 48 */
6140     { "(bad)",          { XX } },
6141     { "(bad)",          { XX } },
6142     { "(bad)",          { XX } },
6143     { "phadddq",        { XM, EXq } },
6144     { "(bad)",          { XX } },
6145     { "(bad)",          { XX } },
6146     { "(bad)",          { XX } },
6147     { "(bad)",          { XX } },
6148     /* 50 */
6149     { "(bad)",          { XX } },
6150     { "phaddubw",       { XM, EXq } },
6151     { "phaddubd",       { XM, EXq } },
6152     { "phaddubq",       { XM, EXq } },
6153     { "(bad)",          { XX } },
6154     { "(bad)",          { XX } },
6155     { "phadduwd",       { XM, EXq } },
6156     { "phadduwq",       { XM, EXq } },
6157     /* 58 */
6158     { "(bad)",          { XX } },
6159     { "(bad)",          { XX } },
6160     { "(bad)",          { XX } },
6161     { "phaddudq",       { XM, EXq } },
6162     { "(bad)",          { XX } },
6163     { "(bad)",          { XX } },
6164     { "(bad)",          { XX } },
6165     { "(bad)",          { XX } },
6166     /* 60 */
6167     { "(bad)",          { XX } },
6168     { "phsubbw",        { XM, EXq } },
6169     { "phsubbd",        { XM, EXq } },
6170     { "phsubbq",        { XM, EXq } },
6171     { "(bad)",          { XX } },
6172     { "(bad)",          { XX } },
6173     { "(bad)",          { XX } },
6174     { "(bad)",          { XX } },
6175     /* 68 */
6176     { "(bad)",          { XX } },
6177     { "(bad)",          { XX } },
6178     { "(bad)",          { XX } },
6179     { "(bad)",          { XX } },
6180     { "(bad)",          { XX } },
6181     { "(bad)",          { XX } },
6182     { "(bad)",          { XX } },
6183     { "(bad)",          { XX } },
6184     /* 70 */
6185     { "(bad)",          { XX } },
6186     { "(bad)",          { XX } },
6187     { "(bad)",          { XX } },
6188     { "(bad)",          { XX } },
6189     { "(bad)",          { XX } },
6190     { "(bad)",          { XX } },
6191     { "(bad)",          { XX } },
6192     { "(bad)",          { XX } },
6193     /* 78 */
6194     { "(bad)",          { XX } },
6195     { "(bad)",          { XX } },
6196     { "(bad)",          { XX } },
6197     { "(bad)",          { XX } },
6198     { "(bad)",          { XX } },
6199     { "(bad)",          { XX } },
6200     { "(bad)",          { XX } },
6201     { "(bad)",          { XX } },
6202     /* 80 */
6203     { "(bad)",          { XX } },
6204     { "(bad)",          { XX } },
6205     { "(bad)",          { XX } },
6206     { "(bad)",          { XX } },
6207     { "(bad)",          { XX } },
6208     { "(bad)",          { XX } },
6209     { "(bad)",          { XX } },
6210     { "(bad)",          { XX } },
6211     /* 88 */
6212     { "(bad)",          { XX } },
6213     { "(bad)",          { XX } },
6214     { "(bad)",          { XX } },
6215     { "(bad)",          { XX } },
6216     { "(bad)",          { XX } },
6217     { "(bad)",          { XX } },
6218     { "(bad)",          { XX } },
6219     { "(bad)",          { XX } },
6220     /* 90 */
6221     { "(bad)",          { XX } },
6222     { "(bad)",          { XX } },
6223     { "(bad)",          { XX } },
6224     { "(bad)",          { XX } },
6225     { "(bad)",          { XX } },
6226     { "(bad)",          { XX } },
6227     { "(bad)",          { XX } },
6228     { "(bad)",          { XX } },
6229     /* 98 */
6230     { "(bad)",          { XX } },
6231     { "(bad)",          { XX } },
6232     { "(bad)",          { XX } },
6233     { "(bad)",          { XX } },
6234     { "(bad)",          { XX } },
6235     { "(bad)",          { XX } },
6236     { "(bad)",          { XX } },
6237     { "(bad)",          { XX } },
6238     /* a0 */
6239     { "(bad)",          { XX } },
6240     { "(bad)",          { XX } },
6241     { "(bad)",          { XX } },
6242     { "(bad)",          { XX } },
6243     { "(bad)",          { XX } },
6244     { "(bad)",          { XX } },
6245     { "(bad)",          { XX } },
6246     { "(bad)",          { XX } },
6247     /* a8 */
6248     { "(bad)",          { XX } },
6249     { "(bad)",          { XX } },
6250     { "(bad)",          { XX } },
6251     { "(bad)",          { XX } },
6252     { "(bad)",          { XX } },
6253     { "(bad)",          { XX } },
6254     { "(bad)",          { XX } },
6255     { "(bad)",          { XX } },
6256     /* b0 */
6257     { "(bad)",          { XX } },
6258     { "(bad)",          { XX } },
6259     { "(bad)",          { XX } },
6260     { "(bad)",          { XX } },
6261     { "(bad)",          { XX } },
6262     { "(bad)",          { XX } },
6263     { "(bad)",          { XX } },
6264     { "(bad)",          { XX } },
6265     /* b8 */
6266     { "(bad)",          { XX } },
6267     { "(bad)",          { XX } },
6268     { "(bad)",          { XX } },
6269     { "(bad)",          { XX } },
6270     { "(bad)",          { XX } },
6271     { "(bad)",          { XX } },
6272     { "(bad)",          { XX } },
6273     { "(bad)",          { XX } },
6274     /* c0 */
6275     { "(bad)",          { XX } },
6276     { "(bad)",          { XX } },
6277     { "(bad)",          { XX } },
6278     { "(bad)",          { XX } },
6279     { "(bad)",          { XX } },
6280     { "(bad)",          { XX } },
6281     { "(bad)",          { XX } },
6282     { "(bad)",          { XX } },
6283     /* c8 */
6284     { "(bad)",          { XX } },
6285     { "(bad)",          { XX } },
6286     { "(bad)",          { XX } },
6287     { "(bad)",          { XX } },
6288     { "(bad)",          { XX } },
6289     { "(bad)",          { XX } },
6290     { "(bad)",          { XX } },
6291     { "(bad)",          { XX } },
6292     /* d0 */
6293     { "(bad)",          { XX } },
6294     { "(bad)",          { XX } },
6295     { "(bad)",          { XX } },
6296     { "(bad)",          { XX } },
6297     { "(bad)",          { XX } },
6298     { "(bad)",          { XX } },
6299     { "(bad)",          { XX } },
6300     { "(bad)",          { XX } },
6301     /* d8 */
6302     { "(bad)",          { XX } },
6303     { "(bad)",          { XX } },
6304     { "(bad)",          { XX } },
6305     { "(bad)",          { XX } },
6306     { "(bad)",          { XX } },
6307     { "(bad)",          { XX } },
6308     { "(bad)",          { XX } },
6309     { "(bad)",          { XX } },
6310     /* e0 */
6311     { "(bad)",          { XX } },
6312     { "(bad)",          { XX } },
6313     { "(bad)",          { XX } },
6314     { "(bad)",          { XX } },
6315     { "(bad)",          { XX } },
6316     { "(bad)",          { XX } },
6317     { "(bad)",          { XX } },
6318     { "(bad)",          { XX } },
6319     /* e8 */
6320     { "(bad)",          { XX } },
6321     { "(bad)",          { XX } },
6322     { "(bad)",          { XX } },
6323     { "(bad)",          { XX } },
6324     { "(bad)",          { XX } },
6325     { "(bad)",          { XX } },
6326     { "(bad)",          { XX } },
6327     { "(bad)",          { XX } },
6328     /* f0 */
6329     { "(bad)",          { XX } },
6330     { "(bad)",          { XX } },
6331     { "(bad)",          { XX } },
6332     { "(bad)",          { XX } },
6333     { "(bad)",          { XX } },
6334     { "(bad)",          { XX } },
6335     { "(bad)",          { XX } },
6336     { "(bad)",          { XX } },
6337     /* f8 */
6338     { "(bad)",          { XX } },
6339     { "(bad)",          { XX } },
6340     { "(bad)",          { XX } },
6341     { "(bad)",          { XX } },
6342     { "(bad)",          { XX } },
6343     { "(bad)",          { XX } },
6344     { "(bad)",          { XX } },
6345     { "(bad)",          { XX } },
6346   },
6347 };
6348
6349
6350 static const struct dis386 vex_table[][256] = {
6351   /* VEX_0F */
6352   {
6353     /* 00 */
6354     { "(bad)",          { XX } },
6355     { "(bad)",          { XX } },
6356     { "(bad)",          { XX } },
6357     { "(bad)",          { XX } },
6358     { "(bad)",          { XX } },
6359     { "(bad)",          { XX } },
6360     { "(bad)",          { XX } },
6361     { "(bad)",          { XX } },
6362     /* 08 */
6363     { "(bad)",          { XX } },
6364     { "(bad)",          { XX } },
6365     { "(bad)",          { XX } },
6366     { "(bad)",          { XX } },
6367     { "(bad)",          { XX } },
6368     { "(bad)",          { XX } },
6369     { "(bad)",          { XX } },
6370     { "(bad)",          { XX } },
6371     /* 10 */
6372     { PREFIX_TABLE (PREFIX_VEX_10) },
6373     { PREFIX_TABLE (PREFIX_VEX_11) },
6374     { PREFIX_TABLE (PREFIX_VEX_12) },
6375     { MOD_TABLE (MOD_VEX_13) },
6376     { "vunpcklpX",      { XM, Vex, EXx } },
6377     { "vunpckhpX",      { XM, Vex, EXx } },
6378     { PREFIX_TABLE (PREFIX_VEX_16) },
6379     { MOD_TABLE (MOD_VEX_17) },
6380     /* 18 */
6381     { "(bad)",          { XX } },
6382     { "(bad)",          { XX } },
6383     { "(bad)",          { XX } },
6384     { "(bad)",          { XX } },
6385     { "(bad)",          { XX } },
6386     { "(bad)",          { XX } },
6387     { "(bad)",          { XX } },
6388     { "(bad)",          { XX } },
6389     /* 20 */
6390     { "(bad)",          { XX } },
6391     { "(bad)",          { XX } },
6392     { "(bad)",          { XX } },
6393     { "(bad)",          { XX } },
6394     { "(bad)",          { XX } },
6395     { "(bad)",          { XX } },
6396     { "(bad)",          { XX } },
6397     { "(bad)",          { XX } },
6398     /* 28 */
6399     { "vmovapX",        { XM, EXx } },
6400     { "vmovapX",        { EXxS, XM } },
6401     { PREFIX_TABLE (PREFIX_VEX_2A) },
6402     { MOD_TABLE (MOD_VEX_2B) },
6403     { PREFIX_TABLE (PREFIX_VEX_2C) },
6404     { PREFIX_TABLE (PREFIX_VEX_2D) },
6405     { PREFIX_TABLE (PREFIX_VEX_2E) },
6406     { PREFIX_TABLE (PREFIX_VEX_2F) },
6407     /* 30 */
6408     { "(bad)",          { XX } },
6409     { "(bad)",          { XX } },
6410     { "(bad)",          { XX } },
6411     { "(bad)",          { XX } },
6412     { "(bad)",          { XX } },
6413     { "(bad)",          { XX } },
6414     { "(bad)",          { XX } },
6415     { "(bad)",          { XX } },
6416     /* 38 */
6417     { "(bad)",          { XX } },
6418     { "(bad)",          { XX } },
6419     { "(bad)",          { XX } },
6420     { "(bad)",          { XX } },
6421     { "(bad)",          { XX } },
6422     { "(bad)",          { XX } },
6423     { "(bad)",          { XX } },
6424     { "(bad)",          { XX } },
6425     /* 40 */
6426     { "(bad)",          { XX } },
6427     { "(bad)",          { XX } },
6428     { "(bad)",          { XX } },
6429     { "(bad)",          { XX } },
6430     { "(bad)",          { XX } },
6431     { "(bad)",          { XX } },
6432     { "(bad)",          { XX } },
6433     { "(bad)",          { XX } },
6434     /* 48 */
6435     { "(bad)",          { XX } },
6436     { "(bad)",          { XX } },
6437     { "(bad)",          { XX } },
6438     { "(bad)",          { XX } },
6439     { "(bad)",          { XX } },
6440     { "(bad)",          { XX } },
6441     { "(bad)",          { XX } },
6442     { "(bad)",          { XX } },
6443     /* 50 */
6444     { MOD_TABLE (MOD_VEX_51) },
6445     { PREFIX_TABLE (PREFIX_VEX_51) },
6446     { PREFIX_TABLE (PREFIX_VEX_52) },
6447     { PREFIX_TABLE (PREFIX_VEX_53) },
6448     { "vandpX",         { XM, Vex, EXx } },
6449     { "vandnpX",        { XM, Vex, EXx } },
6450     { "vorpX",          { XM, Vex, EXx } },
6451     { "vxorpX",         { XM, Vex, EXx } },
6452     /* 58 */
6453     { PREFIX_TABLE (PREFIX_VEX_58) },
6454     { PREFIX_TABLE (PREFIX_VEX_59) },
6455     { PREFIX_TABLE (PREFIX_VEX_5A) },
6456     { PREFIX_TABLE (PREFIX_VEX_5B) },
6457     { PREFIX_TABLE (PREFIX_VEX_5C) },
6458     { PREFIX_TABLE (PREFIX_VEX_5D) },
6459     { PREFIX_TABLE (PREFIX_VEX_5E) },
6460     { PREFIX_TABLE (PREFIX_VEX_5F) },
6461     /* 60 */
6462     { PREFIX_TABLE (PREFIX_VEX_60) },
6463     { PREFIX_TABLE (PREFIX_VEX_61) },
6464     { PREFIX_TABLE (PREFIX_VEX_62) },
6465     { PREFIX_TABLE (PREFIX_VEX_63) },
6466     { PREFIX_TABLE (PREFIX_VEX_64) },
6467     { PREFIX_TABLE (PREFIX_VEX_65) },
6468     { PREFIX_TABLE (PREFIX_VEX_66) },
6469     { PREFIX_TABLE (PREFIX_VEX_67) },
6470     /* 68 */
6471     { PREFIX_TABLE (PREFIX_VEX_68) },
6472     { PREFIX_TABLE (PREFIX_VEX_69) },
6473     { PREFIX_TABLE (PREFIX_VEX_6A) },
6474     { PREFIX_TABLE (PREFIX_VEX_6B) },
6475     { PREFIX_TABLE (PREFIX_VEX_6C) },
6476     { PREFIX_TABLE (PREFIX_VEX_6D) },
6477     { PREFIX_TABLE (PREFIX_VEX_6E) },
6478     { PREFIX_TABLE (PREFIX_VEX_6F) },
6479     /* 70 */
6480     { PREFIX_TABLE (PREFIX_VEX_70) },
6481     { REG_TABLE (REG_VEX_71) },
6482     { REG_TABLE (REG_VEX_72) },
6483     { REG_TABLE (REG_VEX_73) },
6484     { PREFIX_TABLE (PREFIX_VEX_74) },
6485     { PREFIX_TABLE (PREFIX_VEX_75) },
6486     { PREFIX_TABLE (PREFIX_VEX_76) },
6487     { PREFIX_TABLE (PREFIX_VEX_77) },
6488     /* 78 */
6489     { "(bad)",          { XX } },
6490     { "(bad)",          { XX } },
6491     { "(bad)",          { XX } },
6492     { "(bad)",          { XX } },
6493     { PREFIX_TABLE (PREFIX_VEX_7C) },
6494     { PREFIX_TABLE (PREFIX_VEX_7D) },
6495     { PREFIX_TABLE (PREFIX_VEX_7E) },
6496     { PREFIX_TABLE (PREFIX_VEX_7F) },
6497     /* 80 */
6498     { "(bad)",          { XX } },
6499     { "(bad)",          { XX } },
6500     { "(bad)",          { XX } },
6501     { "(bad)",          { XX } },
6502     { "(bad)",          { XX } },
6503     { "(bad)",          { XX } },
6504     { "(bad)",          { XX } },
6505     { "(bad)",          { XX } },
6506     /* 88 */
6507     { "(bad)",          { XX } },
6508     { "(bad)",          { XX } },
6509     { "(bad)",          { XX } },
6510     { "(bad)",          { XX } },
6511     { "(bad)",          { XX } },
6512     { "(bad)",          { XX } },
6513     { "(bad)",          { XX } },
6514     { "(bad)",          { XX } },
6515     /* 90 */
6516     { "(bad)",          { XX } },
6517     { "(bad)",          { XX } },
6518     { "(bad)",          { XX } },
6519     { "(bad)",          { XX } },
6520     { "(bad)",          { XX } },
6521     { "(bad)",          { XX } },
6522     { "(bad)",          { XX } },
6523     { "(bad)",          { XX } },
6524     /* 98 */
6525     { "(bad)",          { XX } },
6526     { "(bad)",          { XX } },
6527     { "(bad)",          { XX } },
6528     { "(bad)",          { XX } },
6529     { "(bad)",          { XX } },
6530     { "(bad)",          { XX } },
6531     { "(bad)",          { XX } },
6532     { "(bad)",          { XX } },
6533     /* a0 */
6534     { "(bad)",          { XX } },
6535     { "(bad)",          { XX } },
6536     { "(bad)",          { XX } },
6537     { "(bad)",          { XX } },
6538     { "(bad)",          { XX } },
6539     { "(bad)",          { XX } },
6540     { "(bad)",          { XX } },
6541     { "(bad)",          { XX } },
6542     /* a8 */
6543     { "(bad)",          { XX } },
6544     { "(bad)",          { XX } },
6545     { "(bad)",          { XX } },
6546     { "(bad)",          { XX } },
6547     { "(bad)",          { XX } },
6548     { "(bad)",          { XX } },
6549     { REG_TABLE (REG_VEX_AE) },
6550     { "(bad)",          { XX } },
6551     /* b0 */
6552     { "(bad)",          { XX } },
6553     { "(bad)",          { XX } },
6554     { "(bad)",          { XX } },
6555     { "(bad)",          { XX } },
6556     { "(bad)",          { XX } },
6557     { "(bad)",          { XX } },
6558     { "(bad)",          { XX } },
6559     { "(bad)",          { XX } },
6560     /* b8 */
6561     { "(bad)",          { XX } },
6562     { "(bad)",          { XX } },
6563     { "(bad)",          { XX } },
6564     { "(bad)",          { XX } },
6565     { "(bad)",          { XX } },
6566     { "(bad)",          { XX } },
6567     { "(bad)",          { XX } },
6568     { "(bad)",          { XX } },
6569     /* c0 */
6570     { "(bad)",          { XX } },
6571     { "(bad)",          { XX } },
6572     { PREFIX_TABLE (PREFIX_VEX_C2) },
6573     { "(bad)",          { XX } },
6574     { PREFIX_TABLE (PREFIX_VEX_C4) },
6575     { PREFIX_TABLE (PREFIX_VEX_C5) },
6576     { "vshufpX",        { XM, Vex, EXx, Ib } },
6577     { "(bad)",          { XX } },
6578     /* c8 */
6579     { "(bad)",          { XX } },
6580     { "(bad)",          { XX } },
6581     { "(bad)",          { XX } },
6582     { "(bad)",          { XX } },
6583     { "(bad)",          { XX } },
6584     { "(bad)",          { XX } },
6585     { "(bad)",          { XX } },
6586     { "(bad)",          { XX } },
6587     /* d0 */
6588     { PREFIX_TABLE (PREFIX_VEX_D0) },
6589     { PREFIX_TABLE (PREFIX_VEX_D1) },
6590     { PREFIX_TABLE (PREFIX_VEX_D2) },
6591     { PREFIX_TABLE (PREFIX_VEX_D3) },
6592     { PREFIX_TABLE (PREFIX_VEX_D4) },
6593     { PREFIX_TABLE (PREFIX_VEX_D5) },
6594     { PREFIX_TABLE (PREFIX_VEX_D6) },
6595     { PREFIX_TABLE (PREFIX_VEX_D7) },
6596     /* d8 */
6597     { PREFIX_TABLE (PREFIX_VEX_D8) },
6598     { PREFIX_TABLE (PREFIX_VEX_D9) },
6599     { PREFIX_TABLE (PREFIX_VEX_DA) },
6600     { PREFIX_TABLE (PREFIX_VEX_DB) },
6601     { PREFIX_TABLE (PREFIX_VEX_DC) },
6602     { PREFIX_TABLE (PREFIX_VEX_DD) },
6603     { PREFIX_TABLE (PREFIX_VEX_DE) },
6604     { PREFIX_TABLE (PREFIX_VEX_DF) },
6605     /* e0 */
6606     { PREFIX_TABLE (PREFIX_VEX_E0) },
6607     { PREFIX_TABLE (PREFIX_VEX_E1) },
6608     { PREFIX_TABLE (PREFIX_VEX_E2) },
6609     { PREFIX_TABLE (PREFIX_VEX_E3) },
6610     { PREFIX_TABLE (PREFIX_VEX_E4) },
6611     { PREFIX_TABLE (PREFIX_VEX_E5) },
6612     { PREFIX_TABLE (PREFIX_VEX_E6) },
6613     { PREFIX_TABLE (PREFIX_VEX_E7) },
6614     /* e8 */
6615     { PREFIX_TABLE (PREFIX_VEX_E8) },
6616     { PREFIX_TABLE (PREFIX_VEX_E9) },
6617     { PREFIX_TABLE (PREFIX_VEX_EA) },
6618     { PREFIX_TABLE (PREFIX_VEX_EB) },
6619     { PREFIX_TABLE (PREFIX_VEX_EC) },
6620     { PREFIX_TABLE (PREFIX_VEX_ED) },
6621     { PREFIX_TABLE (PREFIX_VEX_EE) },
6622     { PREFIX_TABLE (PREFIX_VEX_EF) },
6623     /* f0 */
6624     { PREFIX_TABLE (PREFIX_VEX_F0) },
6625     { PREFIX_TABLE (PREFIX_VEX_F1) },
6626     { PREFIX_TABLE (PREFIX_VEX_F2) },
6627     { PREFIX_TABLE (PREFIX_VEX_F3) },
6628     { PREFIX_TABLE (PREFIX_VEX_F4) },
6629     { PREFIX_TABLE (PREFIX_VEX_F5) },
6630     { PREFIX_TABLE (PREFIX_VEX_F6) },
6631     { PREFIX_TABLE (PREFIX_VEX_F7) },
6632     /* f8 */
6633     { PREFIX_TABLE (PREFIX_VEX_F8) },
6634     { PREFIX_TABLE (PREFIX_VEX_F9) },
6635     { PREFIX_TABLE (PREFIX_VEX_FA) },
6636     { PREFIX_TABLE (PREFIX_VEX_FB) },
6637     { PREFIX_TABLE (PREFIX_VEX_FC) },
6638     { PREFIX_TABLE (PREFIX_VEX_FD) },
6639     { PREFIX_TABLE (PREFIX_VEX_FE) },
6640     { "(bad)",          { XX } },
6641   },
6642   /* VEX_0F38 */
6643   {
6644     /* 00 */
6645     { PREFIX_TABLE (PREFIX_VEX_3800) },
6646     { PREFIX_TABLE (PREFIX_VEX_3801) },
6647     { PREFIX_TABLE (PREFIX_VEX_3802) },
6648     { PREFIX_TABLE (PREFIX_VEX_3803) },
6649     { PREFIX_TABLE (PREFIX_VEX_3804) },
6650     { PREFIX_TABLE (PREFIX_VEX_3805) },
6651     { PREFIX_TABLE (PREFIX_VEX_3806) },
6652     { PREFIX_TABLE (PREFIX_VEX_3807) },
6653     /* 08 */
6654     { PREFIX_TABLE (PREFIX_VEX_3808) },
6655     { PREFIX_TABLE (PREFIX_VEX_3809) },
6656     { PREFIX_TABLE (PREFIX_VEX_380A) },
6657     { PREFIX_TABLE (PREFIX_VEX_380B) },
6658     { PREFIX_TABLE (PREFIX_VEX_380C) },
6659     { PREFIX_TABLE (PREFIX_VEX_380D) },
6660     { PREFIX_TABLE (PREFIX_VEX_380E) },
6661     { PREFIX_TABLE (PREFIX_VEX_380F) },
6662     /* 10 */
6663     { "(bad)",          { XX } },
6664     { "(bad)",          { XX } },
6665     { "(bad)",          { XX } },
6666     { "(bad)",          { XX } },
6667     { "(bad)",          { XX } },
6668     { "(bad)",          { XX } },
6669     { "(bad)",          { XX } },
6670     { PREFIX_TABLE (PREFIX_VEX_3817) },
6671     /* 18 */
6672     { PREFIX_TABLE (PREFIX_VEX_3818) },
6673     { PREFIX_TABLE (PREFIX_VEX_3819) },
6674     { PREFIX_TABLE (PREFIX_VEX_381A) },
6675     { "(bad)",          { XX } },
6676     { PREFIX_TABLE (PREFIX_VEX_381C) },
6677     { PREFIX_TABLE (PREFIX_VEX_381D) },
6678     { PREFIX_TABLE (PREFIX_VEX_381E) },
6679     { "(bad)",          { XX } },
6680     /* 20 */
6681     { PREFIX_TABLE (PREFIX_VEX_3820) },
6682     { PREFIX_TABLE (PREFIX_VEX_3821) },
6683     { PREFIX_TABLE (PREFIX_VEX_3822) },
6684     { PREFIX_TABLE (PREFIX_VEX_3823) },
6685     { PREFIX_TABLE (PREFIX_VEX_3824) },
6686     { PREFIX_TABLE (PREFIX_VEX_3825) },
6687     { "(bad)",          { XX } },
6688     { "(bad)",          { XX } },
6689     /* 28 */
6690     { PREFIX_TABLE (PREFIX_VEX_3828) },
6691     { PREFIX_TABLE (PREFIX_VEX_3829) },
6692     { PREFIX_TABLE (PREFIX_VEX_382A) },
6693     { PREFIX_TABLE (PREFIX_VEX_382B) },
6694     { PREFIX_TABLE (PREFIX_VEX_382C) },
6695     { PREFIX_TABLE (PREFIX_VEX_382D) },
6696     { PREFIX_TABLE (PREFIX_VEX_382E) },
6697     { PREFIX_TABLE (PREFIX_VEX_382F) },
6698     /* 30 */
6699     { PREFIX_TABLE (PREFIX_VEX_3830) },
6700     { PREFIX_TABLE (PREFIX_VEX_3831) },
6701     { PREFIX_TABLE (PREFIX_VEX_3832) },
6702     { PREFIX_TABLE (PREFIX_VEX_3833) },
6703     { PREFIX_TABLE (PREFIX_VEX_3834) },
6704     { PREFIX_TABLE (PREFIX_VEX_3835) },
6705     { "(bad)",          { XX } },
6706     { PREFIX_TABLE (PREFIX_VEX_3837) },
6707     /* 38 */
6708     { PREFIX_TABLE (PREFIX_VEX_3838) },
6709     { PREFIX_TABLE (PREFIX_VEX_3839) },
6710     { PREFIX_TABLE (PREFIX_VEX_383A) },
6711     { PREFIX_TABLE (PREFIX_VEX_383B) },
6712     { PREFIX_TABLE (PREFIX_VEX_383C) },
6713     { PREFIX_TABLE (PREFIX_VEX_383D) },
6714     { PREFIX_TABLE (PREFIX_VEX_383E) },
6715     { PREFIX_TABLE (PREFIX_VEX_383F) },
6716     /* 40 */
6717     { PREFIX_TABLE (PREFIX_VEX_3840) },
6718     { PREFIX_TABLE (PREFIX_VEX_3841) },
6719     { "(bad)",          { XX } },
6720     { "(bad)",          { XX } },
6721     { "(bad)",          { XX } },
6722     { "(bad)",          { XX } },
6723     { "(bad)",          { XX } },
6724     { "(bad)",          { XX } },
6725     /* 48 */
6726     { "(bad)",          { XX } },
6727     { "(bad)",          { XX } },
6728     { "(bad)",          { XX } },
6729     { "(bad)",          { XX } },
6730     { "(bad)",          { XX } },
6731     { "(bad)",          { XX } },
6732     { "(bad)",          { XX } },
6733     { "(bad)",          { XX } },
6734     /* 50 */
6735     { "(bad)",          { XX } },
6736     { "(bad)",          { XX } },
6737     { "(bad)",          { XX } },
6738     { "(bad)",          { XX } },
6739     { "(bad)",          { XX } },
6740     { "(bad)",          { XX } },
6741     { "(bad)",          { XX } },
6742     { "(bad)",          { XX } },
6743     /* 58 */
6744     { "(bad)",          { XX } },
6745     { "(bad)",          { XX } },
6746     { "(bad)",          { XX } },
6747     { "(bad)",          { XX } },
6748     { "(bad)",          { XX } },
6749     { "(bad)",          { XX } },
6750     { "(bad)",          { XX } },
6751     { "(bad)",          { XX } },
6752     /* 60 */
6753     { "(bad)",          { XX } },
6754     { "(bad)",          { XX } },
6755     { "(bad)",          { XX } },
6756     { "(bad)",          { XX } },
6757     { "(bad)",          { XX } },
6758     { "(bad)",          { XX } },
6759     { "(bad)",          { XX } },
6760     { "(bad)",          { XX } },
6761     /* 68 */
6762     { "(bad)",          { XX } },
6763     { "(bad)",          { XX } },
6764     { "(bad)",          { XX } },
6765     { "(bad)",          { XX } },
6766     { "(bad)",          { XX } },
6767     { "(bad)",          { XX } },
6768     { "(bad)",          { XX } },
6769     { "(bad)",          { XX } },
6770     /* 70 */
6771     { "(bad)",          { XX } },
6772     { "(bad)",          { XX } },
6773     { "(bad)",          { XX } },
6774     { "(bad)",          { XX } },
6775     { "(bad)",          { XX } },
6776     { "(bad)",          { XX } },
6777     { "(bad)",          { XX } },
6778     { "(bad)",          { XX } },
6779     /* 78 */
6780     { "(bad)",          { XX } },
6781     { "(bad)",          { XX } },
6782     { "(bad)",          { XX } },
6783     { "(bad)",          { XX } },
6784     { "(bad)",          { XX } },
6785     { "(bad)",          { XX } },
6786     { "(bad)",          { XX } },
6787     { "(bad)",          { XX } },
6788     /* 80 */
6789     { "(bad)",          { XX } },
6790     { "(bad)",          { XX } },
6791     { "(bad)",          { XX } },
6792     { "(bad)",          { XX } },
6793     { "(bad)",          { XX } },
6794     { "(bad)",          { XX } },
6795     { "(bad)",          { XX } },
6796     { "(bad)",          { XX } },
6797     /* 88 */
6798     { "(bad)",          { XX } },
6799     { "(bad)",          { XX } },
6800     { "(bad)",          { XX } },
6801     { "(bad)",          { XX } },
6802     { "(bad)",          { XX } },
6803     { "(bad)",          { XX } },
6804     { "(bad)",          { XX } },
6805     { "(bad)",          { XX } },
6806     /* 90 */
6807     { "(bad)",          { XX } },
6808     { "(bad)",          { XX } },
6809     { "(bad)",          { XX } },
6810     { "(bad)",          { XX } },
6811     { "(bad)",          { XX } },
6812     { "(bad)",          { XX } },
6813     { PREFIX_TABLE (PREFIX_VEX_3896) },
6814     { PREFIX_TABLE (PREFIX_VEX_3897) },
6815     /* 98 */
6816     { PREFIX_TABLE (PREFIX_VEX_3898) },
6817     { PREFIX_TABLE (PREFIX_VEX_3899) },
6818     { PREFIX_TABLE (PREFIX_VEX_389A) },
6819     { PREFIX_TABLE (PREFIX_VEX_389B) },
6820     { PREFIX_TABLE (PREFIX_VEX_389C) },
6821     { PREFIX_TABLE (PREFIX_VEX_389D) },
6822     { PREFIX_TABLE (PREFIX_VEX_389E) },
6823     { PREFIX_TABLE (PREFIX_VEX_389F) },
6824     /* a0 */
6825     { "(bad)",          { XX } },
6826     { "(bad)",          { XX } },
6827     { "(bad)",          { XX } },
6828     { "(bad)",          { XX } },
6829     { "(bad)",          { XX } },
6830     { "(bad)",          { XX } },
6831     { PREFIX_TABLE (PREFIX_VEX_38A6) },
6832     { PREFIX_TABLE (PREFIX_VEX_38A7) },
6833     /* a8 */
6834     { PREFIX_TABLE (PREFIX_VEX_38A8) },
6835     { PREFIX_TABLE (PREFIX_VEX_38A9) },
6836     { PREFIX_TABLE (PREFIX_VEX_38AA) },
6837     { PREFIX_TABLE (PREFIX_VEX_38AB) },
6838     { PREFIX_TABLE (PREFIX_VEX_38AC) },
6839     { PREFIX_TABLE (PREFIX_VEX_38AD) },
6840     { PREFIX_TABLE (PREFIX_VEX_38AE) },
6841     { PREFIX_TABLE (PREFIX_VEX_38AF) },
6842     /* b0 */
6843     { "(bad)",          { XX } },
6844     { "(bad)",          { XX } },
6845     { "(bad)",          { XX } },
6846     { "(bad)",          { XX } },
6847     { "(bad)",          { XX } },
6848     { "(bad)",          { XX } },
6849     { PREFIX_TABLE (PREFIX_VEX_38B6) },
6850     { PREFIX_TABLE (PREFIX_VEX_38B7) },
6851     /* b8 */
6852     { PREFIX_TABLE (PREFIX_VEX_38B8) },
6853     { PREFIX_TABLE (PREFIX_VEX_38B9) },
6854     { PREFIX_TABLE (PREFIX_VEX_38BA) },
6855     { PREFIX_TABLE (PREFIX_VEX_38BB) },
6856     { PREFIX_TABLE (PREFIX_VEX_38BC) },
6857     { PREFIX_TABLE (PREFIX_VEX_38BD) },
6858     { PREFIX_TABLE (PREFIX_VEX_38BE) },
6859     { PREFIX_TABLE (PREFIX_VEX_38BF) },
6860     /* c0 */
6861     { "(bad)",          { XX } },
6862     { "(bad)",          { XX } },
6863     { "(bad)",          { XX } },
6864     { "(bad)",          { XX } },
6865     { "(bad)",          { XX } },
6866     { "(bad)",          { XX } },
6867     { "(bad)",          { XX } },
6868     { "(bad)",          { XX } },
6869     /* c8 */
6870     { "(bad)",          { XX } },
6871     { "(bad)",          { XX } },
6872     { "(bad)",          { XX } },
6873     { "(bad)",          { XX } },
6874     { "(bad)",          { XX } },
6875     { "(bad)",          { XX } },
6876     { "(bad)",          { XX } },
6877     { "(bad)",          { XX } },
6878     /* d0 */
6879     { "(bad)",          { XX } },
6880     { "(bad)",          { XX } },
6881     { "(bad)",          { XX } },
6882     { "(bad)",          { XX } },
6883     { "(bad)",          { XX } },
6884     { "(bad)",          { XX } },
6885     { "(bad)",          { XX } },
6886     { "(bad)",          { XX } },
6887     /* d8 */
6888     { "(bad)",          { XX } },
6889     { "(bad)",          { XX } },
6890     { "(bad)",          { XX } },
6891     { PREFIX_TABLE (PREFIX_VEX_38DB) },
6892     { PREFIX_TABLE (PREFIX_VEX_38DC) },
6893     { PREFIX_TABLE (PREFIX_VEX_38DD) },
6894     { PREFIX_TABLE (PREFIX_VEX_38DE) },
6895     { PREFIX_TABLE (PREFIX_VEX_38DF) },
6896     /* e0 */
6897     { "(bad)",          { XX } },
6898     { "(bad)",          { XX } },
6899     { "(bad)",          { XX } },
6900     { "(bad)",          { XX } },
6901     { "(bad)",          { XX } },
6902     { "(bad)",          { XX } },
6903     { "(bad)",          { XX } },
6904     { "(bad)",          { XX } },
6905     /* e8 */
6906     { "(bad)",          { XX } },
6907     { "(bad)",          { XX } },
6908     { "(bad)",          { XX } },
6909     { "(bad)",          { XX } },
6910     { "(bad)",          { XX } },
6911     { "(bad)",          { XX } },
6912     { "(bad)",          { XX } },
6913     { "(bad)",          { XX } },
6914     /* f0 */
6915     { "(bad)",          { XX } },
6916     { "(bad)",          { XX } },
6917     { "(bad)",          { XX } },
6918     { "(bad)",          { XX } },
6919     { "(bad)",          { XX } },
6920     { "(bad)",          { XX } },
6921     { "(bad)",          { XX } },
6922     { "(bad)",          { XX } },
6923     /* f8 */
6924     { "(bad)",          { XX } },
6925     { "(bad)",          { XX } },
6926     { "(bad)",          { XX } },
6927     { "(bad)",          { XX } },
6928     { "(bad)",          { XX } },
6929     { "(bad)",          { XX } },
6930     { "(bad)",          { XX } },
6931     { "(bad)",          { XX } },
6932   },
6933   /* VEX_0F3A */
6934   {
6935     /* 00 */
6936     { "(bad)",          { XX } },
6937     { "(bad)",          { XX } },
6938     { "(bad)",          { XX } },
6939     { "(bad)",          { XX } },
6940     { PREFIX_TABLE (PREFIX_VEX_3A04) },
6941     { PREFIX_TABLE (PREFIX_VEX_3A05) },
6942     { PREFIX_TABLE (PREFIX_VEX_3A06) },
6943     { "(bad)",          { XX } },
6944     /* 08 */
6945     { PREFIX_TABLE (PREFIX_VEX_3A08) },
6946     { PREFIX_TABLE (PREFIX_VEX_3A09) },
6947     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
6948     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
6949     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
6950     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
6951     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
6952     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
6953     /* 10 */
6954     { "(bad)",          { XX } },
6955     { "(bad)",          { XX } },
6956     { "(bad)",          { XX } },
6957     { "(bad)",          { XX } },
6958     { PREFIX_TABLE (PREFIX_VEX_3A14) },
6959     { PREFIX_TABLE (PREFIX_VEX_3A15) },
6960     { PREFIX_TABLE (PREFIX_VEX_3A16) },
6961     { PREFIX_TABLE (PREFIX_VEX_3A17) },
6962     /* 18 */
6963     { PREFIX_TABLE (PREFIX_VEX_3A18) },
6964     { PREFIX_TABLE (PREFIX_VEX_3A19) },
6965     { "(bad)",          { XX } },
6966     { "(bad)",          { XX } },
6967     { "(bad)",          { XX } },
6968     { "(bad)",          { XX } },
6969     { "(bad)",          { XX } },
6970     { "(bad)",          { XX } },
6971     /* 20 */
6972     { PREFIX_TABLE (PREFIX_VEX_3A20) },
6973     { PREFIX_TABLE (PREFIX_VEX_3A21) },
6974     { PREFIX_TABLE (PREFIX_VEX_3A22) },
6975     { "(bad)",          { XX } },
6976     { "(bad)",          { XX } },
6977     { "(bad)",          { XX } },
6978     { "(bad)",          { XX } },
6979     { "(bad)",          { XX } },
6980     /* 28 */
6981     { "(bad)",          { XX } },
6982     { "(bad)",          { XX } },
6983     { "(bad)",          { XX } },
6984     { "(bad)",          { XX } },
6985     { "(bad)",          { XX } },
6986     { "(bad)",          { XX } },
6987     { "(bad)",          { XX } },
6988     { "(bad)",          { XX } },
6989     /* 30 */
6990     { "(bad)",          { XX } },
6991     { "(bad)",          { XX } },
6992     { "(bad)",          { XX } },
6993     { "(bad)",          { XX } },
6994     { "(bad)",          { XX } },
6995     { "(bad)",          { XX } },
6996     { "(bad)",          { XX } },
6997     { "(bad)",          { XX } },
6998     /* 38 */
6999     { "(bad)",          { XX } },
7000     { "(bad)",          { XX } },
7001     { "(bad)",          { XX } },
7002     { "(bad)",          { XX } },
7003     { "(bad)",          { XX } },
7004     { "(bad)",          { XX } },
7005     { "(bad)",          { XX } },
7006     { "(bad)",          { XX } },
7007     /* 40 */
7008     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7009     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7010     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7011     { "(bad)",          { XX } },
7012     { PREFIX_TABLE (PREFIX_VEX_3A44) },
7013     { "(bad)",          { XX } },
7014     { "(bad)",          { XX } },
7015     { "(bad)",          { XX } },
7016     /* 48 */
7017     { "(bad)",          { XX } },
7018     { "(bad)",          { XX } },
7019     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7020     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7021     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7022     { "(bad)",          { XX } },
7023     { "(bad)",          { XX } },
7024     { "(bad)",          { XX } },
7025     /* 50 */
7026     { "(bad)",          { XX } },
7027     { "(bad)",          { XX } },
7028     { "(bad)",          { XX } },
7029     { "(bad)",          { XX } },
7030     { "(bad)",          { XX } },
7031     { "(bad)",          { XX } },
7032     { "(bad)",          { XX } },
7033     { "(bad)",          { XX } },
7034     /* 58 */
7035     { "(bad)",          { XX } },
7036     { "(bad)",          { XX } },
7037     { "(bad)",          { XX } },
7038     { "(bad)",          { XX } },
7039     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7040     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7041     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7042     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7043     /* 60 */
7044     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7045     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7046     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7047     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7048     { "(bad)",          { XX } },
7049     { "(bad)",          { XX } },
7050     { "(bad)",          { XX } },
7051     { "(bad)",          { XX } },
7052     /* 68 */
7053     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7054     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7055     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7056     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7057     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7058     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7059     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7060     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7061     /* 70 */
7062     { "(bad)",          { XX } },
7063     { "(bad)",          { XX } },
7064     { "(bad)",          { XX } },
7065     { "(bad)",          { XX } },
7066     { "(bad)",          { XX } },
7067     { "(bad)",          { XX } },
7068     { "(bad)",          { XX } },
7069     { "(bad)",          { XX } },
7070     /* 78 */
7071     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7072     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7073     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7074     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7075     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7076     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7077     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7078     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7079     /* 80 */
7080     { "(bad)",          { XX } },
7081     { "(bad)",          { XX } },
7082     { "(bad)",          { XX } },
7083     { "(bad)",          { XX } },
7084     { "(bad)",          { XX } },
7085     { "(bad)",          { XX } },
7086     { "(bad)",          { XX } },
7087     { "(bad)",          { XX } },
7088     /* 88 */
7089     { "(bad)",          { XX } },
7090     { "(bad)",          { XX } },
7091     { "(bad)",          { XX } },
7092     { "(bad)",          { XX } },
7093     { "(bad)",          { XX } },
7094     { "(bad)",          { XX } },
7095     { "(bad)",          { XX } },
7096     { "(bad)",          { XX } },
7097     /* 90 */
7098     { "(bad)",          { XX } },
7099     { "(bad)",          { XX } },
7100     { "(bad)",          { XX } },
7101     { "(bad)",          { XX } },
7102     { "(bad)",          { XX } },
7103     { "(bad)",          { XX } },
7104     { "(bad)",          { XX } },
7105     { "(bad)",          { XX } },
7106     /* 98 */
7107     { "(bad)",          { XX } },
7108     { "(bad)",          { XX } },
7109     { "(bad)",          { XX } },
7110     { "(bad)",          { XX } },
7111     { "(bad)",          { XX } },
7112     { "(bad)",          { XX } },
7113     { "(bad)",          { XX } },
7114     { "(bad)",          { XX } },
7115     /* a0 */
7116     { "(bad)",          { XX } },
7117     { "(bad)",          { XX } },
7118     { "(bad)",          { XX } },
7119     { "(bad)",          { XX } },
7120     { "(bad)",          { XX } },
7121     { "(bad)",          { XX } },
7122     { "(bad)",          { XX } },
7123     { "(bad)",          { XX } },
7124     /* a8 */
7125     { "(bad)",          { XX } },
7126     { "(bad)",          { XX } },
7127     { "(bad)",          { XX } },
7128     { "(bad)",          { XX } },
7129     { "(bad)",          { XX } },
7130     { "(bad)",          { XX } },
7131     { "(bad)",          { XX } },
7132     { "(bad)",          { XX } },
7133     /* b0 */
7134     { "(bad)",          { XX } },
7135     { "(bad)",          { XX } },
7136     { "(bad)",          { XX } },
7137     { "(bad)",          { XX } },
7138     { "(bad)",          { XX } },
7139     { "(bad)",          { XX } },
7140     { "(bad)",          { XX } },
7141     { "(bad)",          { XX } },
7142     /* b8 */
7143     { "(bad)",          { XX } },
7144     { "(bad)",          { XX } },
7145     { "(bad)",          { XX } },
7146     { "(bad)",          { XX } },
7147     { "(bad)",          { XX } },
7148     { "(bad)",          { XX } },
7149     { "(bad)",          { XX } },
7150     { "(bad)",          { XX } },
7151     /* c0 */
7152     { "(bad)",          { XX } },
7153     { "(bad)",          { XX } },
7154     { "(bad)",          { XX } },
7155     { "(bad)",          { XX } },
7156     { "(bad)",          { XX } },
7157     { "(bad)",          { XX } },
7158     { "(bad)",          { XX } },
7159     { "(bad)",          { XX } },
7160     /* c8 */
7161     { "(bad)",          { XX } },
7162     { "(bad)",          { XX } },
7163     { "(bad)",          { XX } },
7164     { "(bad)",          { XX } },
7165     { "(bad)",          { XX } },
7166     { "(bad)",          { XX } },
7167     { "(bad)",          { XX } },
7168     { "(bad)",          { XX } },
7169     /* d0 */
7170     { "(bad)",          { XX } },
7171     { "(bad)",          { XX } },
7172     { "(bad)",          { XX } },
7173     { "(bad)",          { XX } },
7174     { "(bad)",          { XX } },
7175     { "(bad)",          { XX } },
7176     { "(bad)",          { XX } },
7177     { "(bad)",          { XX } },
7178     /* d8 */
7179     { "(bad)",          { XX } },
7180     { "(bad)",          { XX } },
7181     { "(bad)",          { XX } },
7182     { "(bad)",          { XX } },
7183     { "(bad)",          { XX } },
7184     { "(bad)",          { XX } },
7185     { "(bad)",          { XX } },
7186     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
7187     /* e0 */
7188     { "(bad)",          { XX } },
7189     { "(bad)",          { XX } },
7190     { "(bad)",          { XX } },
7191     { "(bad)",          { XX } },
7192     { "(bad)",          { XX } },
7193     { "(bad)",          { XX } },
7194     { "(bad)",          { XX } },
7195     { "(bad)",          { XX } },
7196     /* e8 */
7197     { "(bad)",          { XX } },
7198     { "(bad)",          { XX } },
7199     { "(bad)",          { XX } },
7200     { "(bad)",          { XX } },
7201     { "(bad)",          { XX } },
7202     { "(bad)",          { XX } },
7203     { "(bad)",          { XX } },
7204     { "(bad)",          { XX } },
7205     /* f0 */
7206     { "(bad)",          { XX } },
7207     { "(bad)",          { XX } },
7208     { "(bad)",          { XX } },
7209     { "(bad)",          { XX } },
7210     { "(bad)",          { XX } },
7211     { "(bad)",          { XX } },
7212     { "(bad)",          { XX } },
7213     { "(bad)",          { XX } },
7214     /* f8 */
7215     { "(bad)",          { XX } },
7216     { "(bad)",          { XX } },
7217     { "(bad)",          { XX } },
7218     { "(bad)",          { XX } },
7219     { "(bad)",          { XX } },
7220     { "(bad)",          { XX } },
7221     { "(bad)",          { XX } },
7222     { "(bad)",          { XX } },
7223   },
7224 };
7225
7226 static const struct dis386 vex_len_table[][2] = {
7227   /* VEX_LEN_10_P_1 */
7228   {
7229     { "vmovss",         { XMVex, Vex128, EXd } },
7230     { "(bad)",          { XX } },
7231   },
7232
7233   /* VEX_LEN_10_P_3 */
7234   {
7235     { "vmovsd",         { XMVex, Vex128, EXq } },
7236     { "(bad)",          { XX } },
7237   },
7238
7239   /* VEX_LEN_11_P_1 */
7240   {
7241     { "vmovss",         { EXdVexS, Vex128, XM } },
7242     { "(bad)",          { XX } },
7243   },
7244
7245   /* VEX_LEN_11_P_3 */
7246   {
7247     { "vmovsd",         { EXqVexS, Vex128, XM } },
7248     { "(bad)",          { XX } },
7249   },
7250
7251   /* VEX_LEN_12_P_0_M_0 */
7252   {
7253     { "vmovlps",        { XM, Vex128, EXq } },
7254     { "(bad)",          { XX } },
7255   },
7256
7257   /* VEX_LEN_12_P_0_M_1 */
7258   {
7259     { "vmovhlps",       { XM, Vex128, EXq } },
7260     { "(bad)",          { XX } },
7261   },
7262
7263   /* VEX_LEN_12_P_2 */
7264   {
7265     { "vmovlpd",        { XM, Vex128, EXq } },
7266     { "(bad)",          { XX } },
7267   },
7268
7269   /* VEX_LEN_13_M_0 */
7270   {
7271     { "vmovlpX",        { EXq, XM } },
7272     { "(bad)",          { XX } },
7273   },
7274
7275   /* VEX_LEN_16_P_0_M_0 */
7276   {
7277     { "vmovhps",        { XM, Vex128, EXq } },
7278     { "(bad)",          { XX } },
7279   },
7280
7281   /* VEX_LEN_16_P_0_M_1 */
7282   {
7283     { "vmovlhps",       { XM, Vex128, EXq } },
7284     { "(bad)",          { XX } },
7285   },
7286
7287   /* VEX_LEN_16_P_2 */
7288   {
7289     { "vmovhpd",        { XM, Vex128, EXq } },
7290     { "(bad)",          { XX } },
7291   },
7292
7293   /* VEX_LEN_17_M_0 */
7294   {
7295     { "vmovhpX",        { EXq, XM } },
7296     { "(bad)",          { XX } },
7297   },
7298
7299   /* VEX_LEN_2A_P_1 */
7300   {
7301     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
7302     { "(bad)",          { XX } },
7303   },
7304
7305   /* VEX_LEN_2A_P_3 */
7306   {
7307     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
7308     { "(bad)",          { XX } },
7309   },
7310
7311   /* VEX_LEN_2C_P_1 */
7312   {
7313     { "vcvttss2siY",    { Gv, EXd } },
7314     { "(bad)",          { XX } },
7315   },
7316
7317   /* VEX_LEN_2C_P_3 */
7318   {
7319     { "vcvttsd2siY",    { Gv, EXq } },
7320     { "(bad)",          { XX } },
7321   },
7322
7323   /* VEX_LEN_2D_P_1 */
7324   {
7325     { "vcvtss2siY",     { Gv, EXd } },
7326     { "(bad)",          { XX } },
7327   },
7328
7329   /* VEX_LEN_2D_P_3 */
7330   {
7331     { "vcvtsd2siY",     { Gv, EXq } },
7332     { "(bad)",          { XX } },
7333   },
7334
7335   /* VEX_LEN_2E_P_0 */
7336   {
7337     { "vucomiss",       { XM, EXd } },
7338     { "(bad)",          { XX } },
7339   },
7340
7341   /* VEX_LEN_2E_P_2 */
7342   {
7343     { "vucomisd",       { XM, EXq } },
7344     { "(bad)",          { XX } },
7345   },
7346
7347   /* VEX_LEN_2F_P_0 */
7348   {
7349     { "vcomiss",        { XM, EXd } },
7350     { "(bad)",          { XX } },
7351   },
7352
7353   /* VEX_LEN_2F_P_2 */
7354   {
7355     { "vcomisd",        { XM, EXq } },
7356     { "(bad)",          { XX } },
7357   },
7358
7359   /* VEX_LEN_51_P_1 */
7360   {
7361     { "vsqrtss",        { XM, Vex128, EXd } },
7362     { "(bad)",          { XX } },
7363   },
7364
7365   /* VEX_LEN_51_P_3 */
7366   {
7367     { "vsqrtsd",        { XM, Vex128, EXq } },
7368     { "(bad)",          { XX } },
7369   },
7370
7371   /* VEX_LEN_52_P_1 */
7372   {
7373     { "vrsqrtss",       { XM, Vex128, EXd } },
7374     { "(bad)",          { XX } },
7375   },
7376
7377   /* VEX_LEN_53_P_1 */
7378   {
7379     { "vrcpss",         { XM, Vex128, EXd } },
7380     { "(bad)",          { XX } },
7381   },
7382
7383   /* VEX_LEN_58_P_1 */
7384   {
7385     { "vaddss",         { XM, Vex128, EXd } },
7386     { "(bad)",          { XX } },
7387   },
7388
7389   /* VEX_LEN_58_P_3 */
7390   {
7391     { "vaddsd",         { XM, Vex128, EXq } },
7392     { "(bad)",          { XX } },
7393   },
7394
7395   /* VEX_LEN_59_P_1 */
7396   {
7397     { "vmulss",         { XM, Vex128, EXd } },
7398     { "(bad)",          { XX } },
7399   },
7400
7401   /* VEX_LEN_59_P_3 */
7402   {
7403     { "vmulsd",         { XM, Vex128, EXq } },
7404     { "(bad)",          { XX } },
7405   },
7406
7407   /* VEX_LEN_5A_P_1 */
7408   {
7409     { "vcvtss2sd",      { XM, Vex128, EXd } },
7410     { "(bad)",          { XX } },
7411   },
7412
7413   /* VEX_LEN_5A_P_3 */
7414   {
7415     { "vcvtsd2ss",      { XM, Vex128, EXq } },
7416     { "(bad)",          { XX } },
7417   },
7418
7419   /* VEX_LEN_5C_P_1 */
7420   {
7421     { "vsubss",         { XM, Vex128, EXd } },
7422     { "(bad)",          { XX } },
7423   },
7424
7425   /* VEX_LEN_5C_P_3 */
7426   {
7427     { "vsubsd",         { XM, Vex128, EXq } },
7428     { "(bad)",          { XX } },
7429   },
7430
7431   /* VEX_LEN_5D_P_1 */
7432   {
7433     { "vminss",         { XM, Vex128, EXd } },
7434     { "(bad)",          { XX } },
7435   },
7436
7437   /* VEX_LEN_5D_P_3 */
7438   {
7439     { "vminsd",         { XM, Vex128, EXq } },
7440     { "(bad)",          { XX } },
7441   },
7442
7443   /* VEX_LEN_5E_P_1 */
7444   {
7445     { "vdivss",         { XM, Vex128, EXd } },
7446     { "(bad)",          { XX } },
7447   },
7448
7449   /* VEX_LEN_5E_P_3 */
7450   {
7451     { "vdivsd",         { XM, Vex128, EXq } },
7452     { "(bad)",          { XX } },
7453   },
7454
7455   /* VEX_LEN_5F_P_1 */
7456   {
7457     { "vmaxss",         { XM, Vex128, EXd } },
7458     { "(bad)",          { XX } },
7459   },
7460
7461   /* VEX_LEN_5F_P_3 */
7462   {
7463     { "vmaxsd",         { XM, Vex128, EXq } },
7464     { "(bad)",          { XX } },
7465   },
7466
7467   /* VEX_LEN_60_P_2 */
7468   {
7469     { "vpunpcklbw",     { XM, Vex128, EXx } },
7470     { "(bad)",          { XX } },
7471   },
7472
7473   /* VEX_LEN_61_P_2 */
7474   {
7475     { "vpunpcklwd",     { XM, Vex128, EXx } },
7476     { "(bad)",          { XX } },
7477   },
7478
7479   /* VEX_LEN_62_P_2 */
7480   {
7481     { "vpunpckldq",     { XM, Vex128, EXx } },
7482     { "(bad)",          { XX } },
7483   },
7484
7485   /* VEX_LEN_63_P_2 */
7486   {
7487     { "vpacksswb",      { XM, Vex128, EXx } },
7488     { "(bad)",          { XX } },
7489   },
7490
7491   /* VEX_LEN_64_P_2 */
7492   {
7493     { "vpcmpgtb",       { XM, Vex128, EXx } },
7494     { "(bad)",          { XX } },
7495   },
7496
7497   /* VEX_LEN_65_P_2 */
7498   {
7499     { "vpcmpgtw",       { XM, Vex128, EXx } },
7500     { "(bad)",          { XX } },
7501   },
7502
7503   /* VEX_LEN_66_P_2 */
7504   {
7505     { "vpcmpgtd",       { XM, Vex128, EXx } },
7506     { "(bad)",          { XX } },
7507   },
7508
7509   /* VEX_LEN_67_P_2 */
7510   {
7511     { "vpackuswb",      { XM, Vex128, EXx } },
7512     { "(bad)",          { XX } },
7513   },
7514
7515   /* VEX_LEN_68_P_2 */
7516   {
7517     { "vpunpckhbw",     { XM, Vex128, EXx } },
7518     { "(bad)",          { XX } },
7519   },
7520
7521   /* VEX_LEN_69_P_2 */
7522   {
7523     { "vpunpckhwd",     { XM, Vex128, EXx } },
7524     { "(bad)",          { XX } },
7525   },
7526
7527   /* VEX_LEN_6A_P_2 */
7528   {
7529     { "vpunpckhdq",     { XM, Vex128, EXx } },
7530     { "(bad)",          { XX } },
7531   },
7532
7533   /* VEX_LEN_6B_P_2 */
7534   {
7535     { "vpackssdw",      { XM, Vex128, EXx } },
7536     { "(bad)",          { XX } },
7537   },
7538
7539   /* VEX_LEN_6C_P_2 */
7540   {
7541     { "vpunpcklqdq",    { XM, Vex128, EXx } },
7542     { "(bad)",          { XX } },
7543   },
7544
7545   /* VEX_LEN_6D_P_2 */
7546   {
7547     { "vpunpckhqdq",    { XM, Vex128, EXx } },
7548     { "(bad)",          { XX } },
7549   },
7550
7551   /* VEX_LEN_6E_P_2 */
7552   {
7553     { "vmovK",          { XM, Edq } },
7554     { "(bad)",          { XX } },
7555   },
7556
7557   /* VEX_LEN_70_P_1 */
7558   {
7559     { "vpshufhw",       { XM, EXx, Ib } },
7560     { "(bad)",          { XX } },
7561   },
7562
7563   /* VEX_LEN_70_P_2 */
7564   {
7565     { "vpshufd",        { XM, EXx, Ib } },
7566     { "(bad)",          { XX } },
7567   },
7568
7569   /* VEX_LEN_70_P_3 */
7570   {
7571     { "vpshuflw",       { XM, EXx, Ib } },
7572     { "(bad)",          { XX } },
7573   },
7574
7575   /* VEX_LEN_71_R_2_P_2 */
7576   {
7577     { "vpsrlw",         { Vex128, XS, Ib } },
7578     { "(bad)",          { XX } },
7579   },
7580
7581   /* VEX_LEN_71_R_4_P_2 */
7582   {
7583     { "vpsraw",         { Vex128, XS, Ib } },
7584     { "(bad)",          { XX } },
7585   },
7586
7587   /* VEX_LEN_71_R_6_P_2 */
7588   {
7589     { "vpsllw",         { Vex128, XS, Ib } },
7590     { "(bad)",          { XX } },
7591   },
7592
7593   /* VEX_LEN_72_R_2_P_2 */
7594   {
7595     { "vpsrld",         { Vex128, XS, Ib } },
7596     { "(bad)",          { XX } },
7597   },
7598
7599   /* VEX_LEN_72_R_4_P_2 */
7600   {
7601     { "vpsrad",         { Vex128, XS, Ib } },
7602     { "(bad)",          { XX } },
7603   },
7604
7605   /* VEX_LEN_72_R_6_P_2 */
7606   {
7607     { "vpslld",         { Vex128, XS, Ib } },
7608     { "(bad)",          { XX } },
7609   },
7610
7611   /* VEX_LEN_73_R_2_P_2 */
7612   {
7613     { "vpsrlq",         { Vex128, XS, Ib } },
7614     { "(bad)",          { XX } },
7615   },
7616
7617   /* VEX_LEN_73_R_3_P_2 */
7618   {
7619     { "vpsrldq",        { Vex128, XS, Ib } },
7620     { "(bad)",          { XX } },
7621   },
7622
7623   /* VEX_LEN_73_R_6_P_2 */
7624   {
7625     { "vpsllq",         { Vex128, XS, Ib } },
7626     { "(bad)",          { XX } },
7627   },
7628
7629   /* VEX_LEN_73_R_7_P_2 */
7630   {
7631     { "vpslldq",        { Vex128, XS, Ib } },
7632     { "(bad)",          { XX } },
7633   },
7634
7635   /* VEX_LEN_74_P_2 */
7636   {
7637     { "vpcmpeqb",       { XM, Vex128, EXx } },
7638     { "(bad)",          { XX } },
7639   },
7640
7641   /* VEX_LEN_75_P_2 */
7642   {
7643     { "vpcmpeqw",       { XM, Vex128, EXx } },
7644     { "(bad)",          { XX } },
7645   },
7646
7647   /* VEX_LEN_76_P_2 */
7648   {
7649     { "vpcmpeqd",       { XM, Vex128, EXx } },
7650     { "(bad)",          { XX } },
7651   },
7652
7653   /* VEX_LEN_7E_P_1 */
7654   {
7655     { "vmovq",          { XM, EXq } },
7656     { "(bad)",          { XX } },
7657   },
7658
7659   /* VEX_LEN_7E_P_2 */
7660   {
7661     { "vmovK",          { Edq, XM } },
7662     { "(bad)",          { XX } },
7663   },
7664
7665   /* VEX_LEN_AE_R_2_M_0 */
7666   {
7667     { "vldmxcsr",       { Md } },
7668     { "(bad)",          { XX } },
7669   },
7670
7671   /* VEX_LEN_AE_R_3_M_0 */
7672   {
7673     { "vstmxcsr",       { Md } },
7674     { "(bad)",          { XX } },
7675   },
7676
7677   /* VEX_LEN_C2_P_1 */
7678   {
7679     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
7680     { "(bad)",          { XX } },
7681   },
7682
7683   /* VEX_LEN_C2_P_3 */
7684   {
7685     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
7686     { "(bad)",          { XX } },
7687   },
7688
7689   /* VEX_LEN_C4_P_2 */
7690   {
7691     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
7692     { "(bad)",          { XX } },
7693   },
7694
7695   /* VEX_LEN_C5_P_2 */
7696   {
7697     { "vpextrw",        { Gdq, XS, Ib } },
7698     { "(bad)",          { XX } },
7699   },
7700
7701   /* VEX_LEN_D1_P_2 */
7702   {
7703     { "vpsrlw",         { XM, Vex128, EXx } },
7704     { "(bad)",          { XX } },
7705   },
7706
7707   /* VEX_LEN_D2_P_2 */
7708   {
7709     { "vpsrld",         { XM, Vex128, EXx } },
7710     { "(bad)",          { XX } },
7711   },
7712
7713   /* VEX_LEN_D3_P_2 */
7714   {
7715     { "vpsrlq",         { XM, Vex128, EXx } },
7716     { "(bad)",          { XX } },
7717   },
7718
7719   /* VEX_LEN_D4_P_2 */
7720   {
7721     { "vpaddq",         { XM, Vex128, EXx } },
7722     { "(bad)",          { XX } },
7723   },
7724
7725   /* VEX_LEN_D5_P_2 */
7726   {
7727     { "vpmullw",        { XM, Vex128, EXx } },
7728     { "(bad)",          { XX } },
7729   },
7730
7731   /* VEX_LEN_D6_P_2 */
7732   {
7733     { "vmovq",          { EXqS, XM } },
7734     { "(bad)",          { XX } },
7735   },
7736
7737   /* VEX_LEN_D7_P_2_M_1 */
7738   {
7739     { "vpmovmskb",      { Gdq, XS } },
7740     { "(bad)",          { XX } },
7741   },
7742
7743   /* VEX_LEN_D8_P_2 */
7744   {
7745     { "vpsubusb",       { XM, Vex128, EXx } },
7746     { "(bad)",          { XX } },
7747   },
7748
7749   /* VEX_LEN_D9_P_2 */
7750   {
7751     { "vpsubusw",       { XM, Vex128, EXx } },
7752     { "(bad)",          { XX } },
7753   },
7754
7755   /* VEX_LEN_DA_P_2 */
7756   {
7757     { "vpminub",        { XM, Vex128, EXx } },
7758     { "(bad)",          { XX } },
7759   },
7760
7761   /* VEX_LEN_DB_P_2 */
7762   {
7763     { "vpand",          { XM, Vex128, EXx } },
7764     { "(bad)",          { XX } },
7765   },
7766
7767   /* VEX_LEN_DC_P_2 */
7768   {
7769     { "vpaddusb",       { XM, Vex128, EXx } },
7770     { "(bad)",          { XX } },
7771   },
7772
7773   /* VEX_LEN_DD_P_2 */
7774   {
7775     { "vpaddusw",       { XM, Vex128, EXx } },
7776     { "(bad)",          { XX } },
7777   },
7778
7779   /* VEX_LEN_DE_P_2 */
7780   {
7781     { "vpmaxub",        { XM, Vex128, EXx } },
7782     { "(bad)",          { XX } },
7783   },
7784
7785   /* VEX_LEN_DF_P_2 */
7786   {
7787     { "vpandn",         { XM, Vex128, EXx } },
7788     { "(bad)",          { XX } },
7789   },
7790
7791   /* VEX_LEN_E0_P_2 */
7792   {
7793     { "vpavgb",         { XM, Vex128, EXx } },
7794     { "(bad)",          { XX } },
7795   },
7796
7797   /* VEX_LEN_E1_P_2 */
7798   {
7799     { "vpsraw",         { XM, Vex128, EXx } },
7800     { "(bad)",          { XX } },
7801   },
7802
7803   /* VEX_LEN_E2_P_2 */
7804   {
7805     { "vpsrad",         { XM, Vex128, EXx } },
7806     { "(bad)",          { XX } },
7807   },
7808
7809   /* VEX_LEN_E3_P_2 */
7810   {
7811     { "vpavgw",         { XM, Vex128, EXx } },
7812     { "(bad)",          { XX } },
7813   },
7814
7815   /* VEX_LEN_E4_P_2 */
7816   {
7817     { "vpmulhuw",       { XM, Vex128, EXx } },
7818     { "(bad)",          { XX } },
7819   },
7820
7821   /* VEX_LEN_E5_P_2 */
7822   {
7823     { "vpmulhw",        { XM, Vex128, EXx } },
7824     { "(bad)",          { XX } },
7825   },
7826
7827   /* VEX_LEN_E8_P_2 */
7828   {
7829     { "vpsubsb",        { XM, Vex128, EXx } },
7830     { "(bad)",          { XX } },
7831   },
7832
7833   /* VEX_LEN_E9_P_2 */
7834   {
7835     { "vpsubsw",        { XM, Vex128, EXx } },
7836     { "(bad)",          { XX } },
7837   },
7838
7839   /* VEX_LEN_EA_P_2 */
7840   {
7841     { "vpminsw",        { XM, Vex128, EXx } },
7842     { "(bad)",          { XX } },
7843   },
7844
7845   /* VEX_LEN_EB_P_2 */
7846   {
7847     { "vpor",           { XM, Vex128, EXx } },
7848     { "(bad)",          { XX } },
7849   },
7850
7851   /* VEX_LEN_EC_P_2 */
7852   {
7853     { "vpaddsb",        { XM, Vex128, EXx } },
7854     { "(bad)",          { XX } },
7855   },
7856
7857   /* VEX_LEN_ED_P_2 */
7858   {
7859     { "vpaddsw",        { XM, Vex128, EXx } },
7860     { "(bad)",          { XX } },
7861   },
7862
7863   /* VEX_LEN_EE_P_2 */
7864   {
7865     { "vpmaxsw",        { XM, Vex128, EXx } },
7866     { "(bad)",          { XX } },
7867   },
7868
7869   /* VEX_LEN_EF_P_2 */
7870   {
7871     { "vpxor",          { XM, Vex128, EXx } },
7872     { "(bad)",          { XX } },
7873   },
7874
7875   /* VEX_LEN_F1_P_2 */
7876   {
7877     { "vpsllw",         { XM, Vex128, EXx } },
7878     { "(bad)",          { XX } },
7879   },
7880
7881   /* VEX_LEN_F2_P_2 */
7882   {
7883     { "vpslld",         { XM, Vex128, EXx } },
7884     { "(bad)",          { XX } },
7885   },
7886
7887   /* VEX_LEN_F3_P_2 */
7888   {
7889     { "vpsllq",         { XM, Vex128, EXx } },
7890     { "(bad)",          { XX } },
7891   },
7892
7893   /* VEX_LEN_F4_P_2 */
7894   {
7895     { "vpmuludq",       { XM, Vex128, EXx } },
7896     { "(bad)",          { XX } },
7897   },
7898
7899   /* VEX_LEN_F5_P_2 */
7900   {
7901     { "vpmaddwd",       { XM, Vex128, EXx } },
7902     { "(bad)",          { XX } },
7903   },
7904
7905   /* VEX_LEN_F6_P_2 */
7906   {
7907     { "vpsadbw",        { XM, Vex128, EXx } },
7908     { "(bad)",          { XX } },
7909   },
7910
7911   /* VEX_LEN_F7_P_2 */
7912   {
7913     { "vmaskmovdqu",    { XM, XS } },
7914     { "(bad)",          { XX } },
7915   },
7916
7917   /* VEX_LEN_F8_P_2 */
7918   {
7919     { "vpsubb",         { XM, Vex128, EXx } },
7920     { "(bad)",          { XX } },
7921   },
7922
7923   /* VEX_LEN_F9_P_2 */
7924   {
7925     { "vpsubw",         { XM, Vex128, EXx } },
7926     { "(bad)",          { XX } },
7927   },
7928
7929   /* VEX_LEN_FA_P_2 */
7930   {
7931     { "vpsubd",         { XM, Vex128, EXx } },
7932     { "(bad)",          { XX } },
7933   },
7934
7935   /* VEX_LEN_FB_P_2 */
7936   {
7937     { "vpsubq",         { XM, Vex128, EXx } },
7938     { "(bad)",          { XX } },
7939   },
7940
7941   /* VEX_LEN_FC_P_2 */
7942   {
7943     { "vpaddb",         { XM, Vex128, EXx } },
7944     { "(bad)",          { XX } },
7945   },
7946
7947   /* VEX_LEN_FD_P_2 */
7948   {
7949     { "vpaddw",         { XM, Vex128, EXx } },
7950     { "(bad)",          { XX } },
7951   },
7952
7953   /* VEX_LEN_FE_P_2 */
7954   {
7955     { "vpaddd",         { XM, Vex128, EXx } },
7956     { "(bad)",          { XX } },
7957   },
7958
7959   /* VEX_LEN_3800_P_2 */
7960   {
7961     { "vpshufb",        { XM, Vex128, EXx } },
7962     { "(bad)",          { XX } },
7963   },
7964
7965   /* VEX_LEN_3801_P_2 */
7966   {
7967     { "vphaddw",        { XM, Vex128, EXx } },
7968     { "(bad)",          { XX } },
7969   },
7970
7971   /* VEX_LEN_3802_P_2 */
7972   {
7973     { "vphaddd",        { XM, Vex128, EXx } },
7974     { "(bad)",          { XX } },
7975   },
7976
7977   /* VEX_LEN_3803_P_2 */
7978   {
7979     { "vphaddsw",       { XM, Vex128, EXx } },
7980     { "(bad)",          { XX } },
7981   },
7982
7983   /* VEX_LEN_3804_P_2 */
7984   {
7985     { "vpmaddubsw",     { XM, Vex128, EXx } },
7986     { "(bad)",          { XX } },
7987   },
7988
7989   /* VEX_LEN_3805_P_2 */
7990   {
7991     { "vphsubw",        { XM, Vex128, EXx } },
7992     { "(bad)",          { XX } },
7993   },
7994
7995   /* VEX_LEN_3806_P_2 */
7996   {
7997     { "vphsubd",        { XM, Vex128, EXx } },
7998     { "(bad)",          { XX } },
7999   },
8000
8001   /* VEX_LEN_3807_P_2 */
8002   {
8003     { "vphsubsw",       { XM, Vex128, EXx } },
8004     { "(bad)",          { XX } },
8005   },
8006
8007   /* VEX_LEN_3808_P_2 */
8008   {
8009     { "vpsignb",        { XM, Vex128, EXx } },
8010     { "(bad)",          { XX } },
8011   },
8012
8013   /* VEX_LEN_3809_P_2 */
8014   {
8015     { "vpsignw",        { XM, Vex128, EXx } },
8016     { "(bad)",          { XX } },
8017   },
8018
8019   /* VEX_LEN_380A_P_2 */
8020   {
8021     { "vpsignd",        { XM, Vex128, EXx } },
8022     { "(bad)",          { XX } },
8023   },
8024
8025   /* VEX_LEN_380B_P_2 */
8026   {
8027     { "vpmulhrsw",      { XM, Vex128, EXx } },
8028     { "(bad)",          { XX } },
8029   },
8030
8031   /* VEX_LEN_3819_P_2_M_0 */
8032   {
8033     { "(bad)",          { XX } },
8034     { "vbroadcastsd",   { XM, Mq } },
8035   },
8036
8037   /* VEX_LEN_381A_P_2_M_0 */
8038   {
8039     { "(bad)",          { XX } },
8040     { "vbroadcastf128", { XM, Mxmm } },
8041   },
8042
8043   /* VEX_LEN_381C_P_2 */
8044   {
8045     { "vpabsb",         { XM, EXx } },
8046     { "(bad)",          { XX } },
8047   },
8048
8049   /* VEX_LEN_381D_P_2 */
8050   {
8051     { "vpabsw",         { XM, EXx } },
8052     { "(bad)",          { XX } },
8053   },
8054
8055   /* VEX_LEN_381E_P_2 */
8056   {
8057     { "vpabsd",         { XM, EXx } },
8058     { "(bad)",          { XX } },
8059   },
8060
8061   /* VEX_LEN_3820_P_2 */
8062   {
8063     { "vpmovsxbw",      { XM, EXq } },
8064     { "(bad)",          { XX } },
8065   },
8066
8067   /* VEX_LEN_3821_P_2 */
8068   {
8069     { "vpmovsxbd",      { XM, EXd } },
8070     { "(bad)",          { XX } },
8071   },
8072
8073   /* VEX_LEN_3822_P_2 */
8074   {
8075     { "vpmovsxbq",      { XM, EXw } },
8076     { "(bad)",          { XX } },
8077   },
8078
8079   /* VEX_LEN_3823_P_2 */
8080   {
8081     { "vpmovsxwd",      { XM, EXq } },
8082     { "(bad)",          { XX } },
8083   },
8084
8085   /* VEX_LEN_3824_P_2 */
8086   {
8087     { "vpmovsxwq",      { XM, EXd } },
8088     { "(bad)",          { XX } },
8089   },
8090
8091   /* VEX_LEN_3825_P_2 */
8092   {
8093     { "vpmovsxdq",      { XM, EXq } },
8094     { "(bad)",          { XX } },
8095   },
8096
8097   /* VEX_LEN_3828_P_2 */
8098   {
8099     { "vpmuldq",        { XM, Vex128, EXx } },
8100     { "(bad)",          { XX } },
8101   },
8102
8103   /* VEX_LEN_3829_P_2 */
8104   {
8105     { "vpcmpeqq",       { XM, Vex128, EXx } },
8106     { "(bad)",          { XX } },
8107   },
8108
8109   /* VEX_LEN_382A_P_2_M_0 */
8110   {
8111     { "vmovntdqa",      { XM, Mx } },
8112     { "(bad)",          { XX } },
8113   },
8114
8115   /* VEX_LEN_382B_P_2 */
8116   {
8117     { "vpackusdw",      { XM, Vex128, EXx } },
8118     { "(bad)",          { XX } },
8119   },
8120
8121   /* VEX_LEN_3830_P_2 */
8122   {
8123     { "vpmovzxbw",      { XM, EXq } },
8124     { "(bad)",          { XX } },
8125   },
8126
8127   /* VEX_LEN_3831_P_2 */
8128   {
8129     { "vpmovzxbd",      { XM, EXd } },
8130     { "(bad)",          { XX } },
8131   },
8132
8133   /* VEX_LEN_3832_P_2 */
8134   {
8135     { "vpmovzxbq",      { XM, EXw } },
8136     { "(bad)",          { XX } },
8137   },
8138
8139   /* VEX_LEN_3833_P_2 */
8140   {
8141     { "vpmovzxwd",      { XM, EXq } },
8142     { "(bad)",          { XX } },
8143   },
8144
8145   /* VEX_LEN_3834_P_2 */
8146   {
8147     { "vpmovzxwq",      { XM, EXd } },
8148     { "(bad)",          { XX } },
8149   },
8150
8151   /* VEX_LEN_3835_P_2 */
8152   {
8153     { "vpmovzxdq",      { XM, EXq } },
8154     { "(bad)",          { XX } },
8155   },
8156
8157   /* VEX_LEN_3837_P_2 */
8158   {
8159     { "vpcmpgtq",       { XM, Vex128, EXx } },
8160     { "(bad)",          { XX } },
8161   },
8162
8163   /* VEX_LEN_3838_P_2 */
8164   {
8165     { "vpminsb",        { XM, Vex128, EXx } },
8166     { "(bad)",          { XX } },
8167   },
8168
8169   /* VEX_LEN_3839_P_2 */
8170   {
8171     { "vpminsd",        { XM, Vex128, EXx } },
8172     { "(bad)",          { XX } },
8173   },
8174
8175   /* VEX_LEN_383A_P_2 */
8176   {
8177     { "vpminuw",        { XM, Vex128, EXx } },
8178     { "(bad)",          { XX } },
8179   },
8180
8181   /* VEX_LEN_383B_P_2 */
8182   {
8183     { "vpminud",        { XM, Vex128, EXx } },
8184     { "(bad)",          { XX } },
8185   },
8186
8187   /* VEX_LEN_383C_P_2 */
8188   {
8189     { "vpmaxsb",        { XM, Vex128, EXx } },
8190     { "(bad)",          { XX } },
8191   },
8192
8193   /* VEX_LEN_383D_P_2 */
8194   {
8195     { "vpmaxsd",        { XM, Vex128, EXx } },
8196     { "(bad)",          { XX } },
8197   },
8198
8199   /* VEX_LEN_383E_P_2 */
8200   {
8201     { "vpmaxuw",        { XM, Vex128, EXx } },
8202     { "(bad)",          { XX } },
8203   },
8204
8205   /* VEX_LEN_383F_P_2 */
8206   {
8207     { "vpmaxud",        { XM, Vex128, EXx } },
8208     { "(bad)",          { XX } },
8209   },
8210
8211   /* VEX_LEN_3840_P_2 */
8212   {
8213     { "vpmulld",        { XM, Vex128, EXx } },
8214     { "(bad)",          { XX } },
8215   },
8216
8217   /* VEX_LEN_3841_P_2 */
8218   {
8219     { "vphminposuw",    { XM, EXx } },
8220     { "(bad)",          { XX } },
8221   },
8222
8223   /* VEX_LEN_38DB_P_2 */
8224   {
8225     { "vaesimc",        { XM, EXx } },
8226     { "(bad)",          { XX } },
8227   },
8228
8229   /* VEX_LEN_38DC_P_2 */
8230   {
8231     { "vaesenc",        { XM, Vex128, EXx } },
8232     { "(bad)",          { XX } },
8233   },
8234
8235   /* VEX_LEN_38DD_P_2 */
8236   {
8237     { "vaesenclast",    { XM, Vex128, EXx } },
8238     { "(bad)",          { XX } },
8239   },
8240
8241   /* VEX_LEN_38DE_P_2 */
8242   {
8243     { "vaesdec",        { XM, Vex128, EXx } },
8244     { "(bad)",          { XX } },
8245   },
8246
8247   /* VEX_LEN_38DF_P_2 */
8248   {
8249     { "vaesdeclast",    { XM, Vex128, EXx } },
8250     { "(bad)",          { XX } },
8251   },
8252
8253   /* VEX_LEN_3A06_P_2 */
8254   {
8255     { "(bad)",          { XX } },
8256     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
8257   },
8258
8259   /* VEX_LEN_3A0A_P_2 */
8260   {
8261     { "vroundss",       { XM, Vex128, EXd, Ib } },
8262     { "(bad)",          { XX } },
8263   },
8264
8265   /* VEX_LEN_3A0B_P_2 */
8266   {
8267     { "vroundsd",       { XM, Vex128, EXq, Ib } },
8268     { "(bad)",          { XX } },
8269   },
8270
8271   /* VEX_LEN_3A0E_P_2 */
8272   {
8273     { "vpblendw",       { XM, Vex128, EXx, Ib } },
8274     { "(bad)",          { XX } },
8275   },
8276
8277   /* VEX_LEN_3A0F_P_2 */
8278   {
8279     { "vpalignr",       { XM, Vex128, EXx, Ib } },
8280     { "(bad)",          { XX } },
8281   },
8282
8283   /* VEX_LEN_3A14_P_2 */
8284   {
8285     { "vpextrb",        { Edqb, XM, Ib } },
8286     { "(bad)",          { XX } },
8287   },
8288
8289   /* VEX_LEN_3A15_P_2 */
8290   {
8291     { "vpextrw",        { Edqw, XM, Ib } },
8292     { "(bad)",          { XX } },
8293   },
8294
8295   /* VEX_LEN_3A16_P_2  */
8296   {
8297     { "vpextrK",        { Edq, XM, Ib } },
8298     { "(bad)",          { XX } },
8299   },
8300
8301   /* VEX_LEN_3A17_P_2 */
8302   {
8303     { "vextractps",     { Edqd, XM, Ib } },
8304     { "(bad)",          { XX } },
8305   },
8306
8307   /* VEX_LEN_3A18_P_2 */
8308   {
8309     { "(bad)",          { XX } },
8310     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
8311   },
8312
8313   /* VEX_LEN_3A19_P_2 */
8314   {
8315     { "(bad)",          { XX } },
8316     { "vextractf128",   { EXxmm, XM, Ib } },
8317   },
8318
8319   /* VEX_LEN_3A20_P_2 */
8320   {
8321     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
8322     { "(bad)",          { XX } },
8323   },
8324
8325   /* VEX_LEN_3A21_P_2 */
8326   {
8327     { "vinsertps",      { XM, Vex128, EXd, Ib } },
8328     { "(bad)",          { XX } },
8329   },
8330
8331   /* VEX_LEN_3A22_P_2 */
8332   {
8333     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8334     { "(bad)",          { XX } },
8335   },
8336
8337   /* VEX_LEN_3A41_P_2 */
8338   {
8339     { "vdppd",          { XM, Vex128, EXx, Ib } },
8340     { "(bad)",          { XX } },
8341   },
8342
8343   /* VEX_LEN_3A42_P_2 */
8344   {
8345     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
8346     { "(bad)",          { XX } },
8347   },
8348
8349   /* VEX_LEN_3A44_P_2 */
8350   {
8351     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
8352     { "(bad)",          { XX } },
8353   },
8354
8355   /* VEX_LEN_3A4C_P_2 */
8356   {
8357     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
8358     { "(bad)",          { XX } },
8359   },
8360
8361   /* VEX_LEN_3A60_P_2 */
8362   {
8363     { "vpcmpestrm",     { XM, EXx, Ib } },
8364     { "(bad)",          { XX } },
8365   },
8366
8367   /* VEX_LEN_3A61_P_2 */
8368   {
8369     { "vpcmpestri",     { XM, EXx, Ib } },
8370     { "(bad)",          { XX } },
8371   },
8372
8373   /* VEX_LEN_3A62_P_2 */
8374   {
8375     { "vpcmpistrm",     { XM, EXx, Ib } },
8376     { "(bad)",          { XX } },
8377   },
8378
8379   /* VEX_LEN_3A63_P_2 */
8380   {
8381     { "vpcmpistri",     { XM, EXx, Ib } },
8382     { "(bad)",          { XX } },
8383   },
8384
8385   /* VEX_LEN_3A6A_P_2 */
8386   {
8387     { "vfmaddss",       { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8388     { "(bad)",          { XX } },
8389   },
8390
8391   /* VEX_LEN_3A6B_P_2 */
8392   {
8393     { "vfmaddsd",       { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8394     { "(bad)",          { XX } },
8395   },
8396
8397   /* VEX_LEN_3A6E_P_2 */
8398   {
8399     { "vfmsubss",       { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8400     { "(bad)",          { XX } },
8401   },
8402
8403   /* VEX_LEN_3A6F_P_2 */
8404   {
8405     { "vfmsubsd",       { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8406     { "(bad)",          { XX } },
8407   },
8408
8409   /* VEX_LEN_3A7A_P_2 */
8410   {
8411     { "vfnmaddss",      { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8412     { "(bad)",          { XX } },
8413   },
8414
8415   /* VEX_LEN_3A7B_P_2 */
8416   {
8417     { "vfnmaddsd",      { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8418     { "(bad)",          { XX } },
8419   },
8420
8421   /* VEX_LEN_3A7E_P_2 */
8422   {
8423     { "vfnmsubss",      { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8424     { "(bad)",          { XX } },
8425   },
8426
8427   /* VEX_LEN_3A7F_P_2 */
8428   {
8429     { "vfnmsubsd",      { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8430     { "(bad)",          { XX } },
8431   },
8432
8433   /* VEX_LEN_3ADF_P_2 */
8434   {
8435     { "vaeskeygenassist", { XM, EXx, Ib } },
8436     { "(bad)",          { XX } },
8437   },
8438 };
8439
8440 static const struct dis386 mod_table[][2] = {
8441   {
8442     /* MOD_8D */
8443     { "leaS",           { Gv, M } },
8444     { "(bad)",          { XX } },
8445   },
8446   {
8447     /* MOD_0F01_REG_0 */
8448     { X86_64_TABLE (X86_64_0F01_REG_0) },
8449     { RM_TABLE (RM_0F01_REG_0) },
8450   },
8451   {
8452     /* MOD_0F01_REG_1 */
8453     { X86_64_TABLE (X86_64_0F01_REG_1) },
8454     { RM_TABLE (RM_0F01_REG_1) },
8455   },
8456   {
8457     /* MOD_0F01_REG_2 */
8458     { X86_64_TABLE (X86_64_0F01_REG_2) },
8459     { RM_TABLE (RM_0F01_REG_2) },
8460   },
8461   {
8462     /* MOD_0F01_REG_3 */
8463     { X86_64_TABLE (X86_64_0F01_REG_3) },
8464     { RM_TABLE (RM_0F01_REG_3) },
8465   },
8466   {
8467     /* MOD_0F01_REG_7 */
8468     { "invlpg",         { Mb } },
8469     { RM_TABLE (RM_0F01_REG_7) },
8470   },
8471   {
8472     /* MOD_0F12_PREFIX_0 */
8473     { "movlps",         { XM, EXq } },
8474     { "movhlps",        { XM, EXq } },
8475   },
8476   {
8477     /* MOD_0F13 */
8478     { "movlpX",         { EXq, XM } },
8479     { "(bad)",          { XX } },
8480   },
8481   {
8482     /* MOD_0F16_PREFIX_0 */
8483     { "movhps",         { XM, EXq } },
8484     { "movlhps",        { XM, EXq } },
8485   },
8486   {
8487     /* MOD_0F17 */
8488     { "movhpX",         { EXq, XM } },
8489     { "(bad)",          { XX } },
8490   },
8491   {
8492     /* MOD_0F18_REG_0 */
8493     { "prefetchnta",    { Mb } },
8494     { "(bad)",          { XX } },
8495   },
8496   {
8497     /* MOD_0F18_REG_1 */
8498     { "prefetcht0",     { Mb } },
8499     { "(bad)",          { XX } },
8500   },
8501   {
8502     /* MOD_0F18_REG_2 */
8503     { "prefetcht1",     { Mb } },
8504     { "(bad)",          { XX } },
8505   },
8506   {
8507     /* MOD_0F18_REG_3 */
8508     { "prefetcht2",     { Mb } },
8509     { "(bad)",          { XX } },
8510   },
8511   {
8512     /* MOD_0F20 */
8513     { "(bad)",          { XX } },
8514     { "movZ",           { Rm, Cm } },
8515   },
8516   {
8517     /* MOD_0F21 */
8518     { "(bad)",          { XX } },
8519     { "movZ",           { Rm, Dm } },
8520   },
8521   {
8522     /* MOD_0F22 */
8523     { "(bad)",          { XX } },
8524     { "movZ",           { Cm, Rm } },
8525   },
8526   {
8527     /* MOD_0F23 */
8528     { "(bad)",          { XX } },
8529     { "movZ",           { Dm, Rm } },
8530   },
8531   {
8532     /* MOD_0F24 */
8533     { "(bad)",          { XX } },
8534     { "movL",           { Rd, Td } },
8535   },
8536   {
8537     /* MOD_0F26 */
8538     { "(bad)",          { XX } },
8539     { "movL",           { Td, Rd } },
8540   },
8541   {
8542     /* MOD_0F2B_PREFIX_0 */
8543     {"movntps",         { Mx, XM } },
8544     { "(bad)",          { XX } },
8545   },
8546   {
8547     /* MOD_0F2B_PREFIX_1 */
8548     {"movntss",         { Md, XM } },
8549     { "(bad)",          { XX } },
8550   },
8551   {
8552     /* MOD_0F2B_PREFIX_2 */
8553     {"movntpd",         { Mx, XM } },
8554     { "(bad)",          { XX } },
8555   },
8556   {
8557     /* MOD_0F2B_PREFIX_3 */
8558     {"movntsd",         { Mq, XM } },
8559     { "(bad)",          { XX } },
8560   },
8561   {
8562     /* MOD_0F51 */
8563     { "(bad)",          { XX } },
8564     { "movmskpX",       { Gdq, XS } },
8565   },
8566   {
8567     /* MOD_0F71_REG_2 */
8568     { "(bad)",          { XX } },
8569     { "psrlw",          { MS, Ib } },
8570   },
8571   {
8572     /* MOD_0F71_REG_4 */
8573     { "(bad)",          { XX } },
8574     { "psraw",          { MS, Ib } },
8575   },
8576   {
8577     /* MOD_0F71_REG_6 */
8578     { "(bad)",          { XX } },
8579     { "psllw",          { MS, Ib } },
8580   },
8581   {
8582     /* MOD_0F72_REG_2 */
8583     { "(bad)",          { XX } },
8584     { "psrld",          { MS, Ib } },
8585   },
8586   {
8587     /* MOD_0F72_REG_4 */
8588     { "(bad)",          { XX } },
8589     { "psrad",          { MS, Ib } },
8590   },
8591   {
8592     /* MOD_0F72_REG_6 */
8593     { "(bad)",          { XX } },
8594     { "pslld",          { MS, Ib } },
8595   },
8596   {
8597     /* MOD_0F73_REG_2 */
8598     { "(bad)",          { XX } },
8599     { "psrlq",          { MS, Ib } },
8600   },
8601   {
8602     /* MOD_0F73_REG_3 */
8603     { "(bad)",          { XX } },
8604     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
8605   },
8606   {
8607     /* MOD_0F73_REG_6 */
8608     { "(bad)",          { XX } },
8609     { "psllq",          { MS, Ib } },
8610   },
8611   {
8612     /* MOD_0F73_REG_7 */
8613     { "(bad)",          { XX } },
8614     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
8615   },
8616   {
8617     /* MOD_0FAE_REG_0 */
8618     { "fxsave",         { M } },
8619     { "(bad)",          { XX } },
8620   },
8621   {
8622     /* MOD_0FAE_REG_1 */
8623     { "fxrstor",        { M } },
8624     { "(bad)",          { XX } },
8625   },
8626   {
8627     /* MOD_0FAE_REG_2 */
8628     { "ldmxcsr",        { Md } },
8629     { "(bad)",          { XX } },
8630   },
8631   {
8632     /* MOD_0FAE_REG_3 */
8633     { "stmxcsr",        { Md } },
8634     { "(bad)",          { XX } },
8635   },
8636   {
8637     /* MOD_0FAE_REG_4 */
8638     { "xsave",          { M } },
8639     { "(bad)",          { XX } },
8640   },
8641   {
8642     /* MOD_0FAE_REG_5 */
8643     { "xrstor",         { M } },
8644     { RM_TABLE (RM_0FAE_REG_5) },
8645   },
8646   {
8647     /* MOD_0FAE_REG_6 */
8648     { "xsaveopt",       { M } },
8649     { RM_TABLE (RM_0FAE_REG_6) },
8650   },
8651   {
8652     /* MOD_0FAE_REG_7 */
8653     { "clflush",        { Mb } },
8654     { RM_TABLE (RM_0FAE_REG_7) },
8655   },
8656   {
8657     /* MOD_0FB2 */
8658     { "lssS",           { Gv, Mp } },
8659     { "(bad)",          { XX } },
8660   },
8661   {
8662     /* MOD_0FB4 */
8663     { "lfsS",           { Gv, Mp } },
8664     { "(bad)",          { XX } },
8665   },
8666   {
8667     /* MOD_0FB5 */
8668     { "lgsS",           { Gv, Mp } },
8669     { "(bad)",          { XX } },
8670   },
8671   {
8672     /* MOD_0FC7_REG_6 */
8673     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
8674     { "(bad)",          { XX } },
8675   },
8676   {
8677     /* MOD_0FC7_REG_7 */
8678     { "vmptrst",        { Mq } },
8679     { "(bad)",          { XX } },
8680   },
8681   {
8682     /* MOD_0FD7 */
8683     { "(bad)",          { XX } },
8684     { "pmovmskb",       { Gdq, MS } },
8685   },
8686   {
8687     /* MOD_0FE7_PREFIX_2 */
8688     { "movntdq",        { Mx, XM } },
8689     { "(bad)",          { XX } },
8690   },
8691   {
8692     /* MOD_0FF0_PREFIX_3 */
8693     { "lddqu",          { XM, M } },
8694     { "(bad)",          { XX } },
8695   },
8696   {
8697     /* MOD_0F382A_PREFIX_2 */
8698     { "movntdqa",       { XM, Mx } },
8699     { "(bad)",          { XX } },
8700   },
8701   {
8702     /* MOD_62_32BIT */
8703     { "bound{S|}",      { Gv, Ma } },
8704     { "(bad)",          { XX } },
8705   },
8706   {
8707     /* MOD_C4_32BIT */
8708     { "lesS",           { Gv, Mp } },
8709     { VEX_C4_TABLE (VEX_0F) },
8710   },
8711   {
8712     /* MOD_C5_32BIT */
8713     { "ldsS",           { Gv, Mp } },
8714     { VEX_C5_TABLE (VEX_0F) },
8715   },
8716   {
8717     /* MOD_VEX_12_PREFIX_0 */
8718     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
8719     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
8720   },
8721   {
8722     /* MOD_VEX_13 */
8723     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
8724     { "(bad)",          { XX } },
8725   },
8726   {
8727     /* MOD_VEX_16_PREFIX_0 */
8728     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
8729     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
8730   },
8731   {
8732     /* MOD_VEX_17 */
8733     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
8734     { "(bad)",          { XX } },
8735   },
8736   {
8737     /* MOD_VEX_2B */
8738     { "vmovntpX",       { Mx, XM } },
8739     { "(bad)",          { XX } },
8740   },
8741   {
8742     /* MOD_VEX_51 */
8743     { "(bad)",          { XX } },
8744     { "vmovmskpX",      { Gdq, XS } },
8745   },
8746   {
8747     /* MOD_VEX_71_REG_2 */
8748     { "(bad)",          { XX } },
8749     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
8750   },
8751   {
8752     /* MOD_VEX_71_REG_4 */
8753     { "(bad)",          { XX } },
8754     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
8755   },
8756   {
8757     /* MOD_VEX_71_REG_6 */
8758     { "(bad)",          { XX } },
8759     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
8760   },
8761   {
8762     /* MOD_VEX_72_REG_2 */
8763     { "(bad)",          { XX } },
8764     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
8765   },
8766   {
8767     /* MOD_VEX_72_REG_4 */
8768     { "(bad)",          { XX } },
8769     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
8770   },
8771   {
8772     /* MOD_VEX_72_REG_6 */
8773     { "(bad)",          { XX } },
8774     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
8775   },
8776   {
8777     /* MOD_VEX_73_REG_2 */
8778     { "(bad)",          { XX } },
8779     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
8780   },
8781   {
8782     /* MOD_VEX_73_REG_3 */
8783     { "(bad)",          { XX } },
8784     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
8785   },
8786   {
8787     /* MOD_VEX_73_REG_6 */
8788     { "(bad)",          { XX } },
8789     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
8790   },
8791   {
8792     /* MOD_VEX_73_REG_7 */
8793     { "(bad)",          { XX } },
8794     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
8795   },
8796   {
8797     /* MOD_VEX_AE_REG_2 */
8798     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
8799     { "(bad)",          { XX } },
8800   },
8801   {
8802     /* MOD_VEX_AE_REG_3 */
8803     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
8804     { "(bad)",          { XX } },
8805   },
8806   {
8807     /* MOD_VEX_D7_PREFIX_2 */
8808     { "(bad)",          { XX } },
8809     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
8810   },
8811   {
8812     /* MOD_VEX_E7_PREFIX_2 */
8813     { "vmovntdq",       { Mx, XM } },
8814     { "(bad)",          { XX } },
8815   },
8816   {
8817     /* MOD_VEX_F0_PREFIX_3 */
8818     { "vlddqu",         { XM, M } },
8819     { "(bad)",          { XX } },
8820   },
8821   {
8822     /* MOD_VEX_3818_PREFIX_2 */
8823     { "vbroadcastss",   { XM, Md } },
8824     { "(bad)",          { XX } },
8825   },
8826   {
8827     /* MOD_VEX_3819_PREFIX_2 */
8828     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
8829     { "(bad)",          { XX } },
8830   },
8831   {
8832     /* MOD_VEX_381A_PREFIX_2 */
8833     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
8834     { "(bad)",          { XX } },
8835   },
8836   {
8837     /* MOD_VEX_382A_PREFIX_2 */
8838     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
8839     { "(bad)",          { XX } },
8840   },
8841   {
8842     /* MOD_VEX_382C_PREFIX_2 */
8843     { "vmaskmovps",     { XM, Vex, Mx } },
8844     { "(bad)",          { XX } },
8845   },
8846   {
8847     /* MOD_VEX_382D_PREFIX_2 */
8848     { "vmaskmovpd",     { XM, Vex, Mx } },
8849     { "(bad)",          { XX } },
8850   },
8851   {
8852     /* MOD_VEX_382E_PREFIX_2 */
8853     { "vmaskmovps",     { Mx, Vex, XM } },
8854     { "(bad)",          { XX } },
8855   },
8856   {
8857     /* MOD_VEX_382F_PREFIX_2 */
8858     { "vmaskmovpd",     { Mx, Vex, XM } },
8859     { "(bad)",          { XX } },
8860   },
8861 };
8862
8863 static const struct dis386 rm_table[][8] = {
8864   {
8865     /* RM_0F01_REG_0 */
8866     { "(bad)",          { XX } },
8867     { "vmcall",         { Skip_MODRM } },
8868     { "vmlaunch",       { Skip_MODRM } },
8869     { "vmresume",       { Skip_MODRM } },
8870     { "vmxoff",         { Skip_MODRM } },
8871     { "(bad)",          { XX } },
8872     { "(bad)",          { XX } },
8873     { "(bad)",          { XX } },
8874   },
8875   {
8876     /* RM_0F01_REG_1 */
8877     { "monitor",        { { OP_Monitor, 0 } } },
8878     { "mwait",          { { OP_Mwait, 0 } } },
8879     { "(bad)",          { XX } },
8880     { "(bad)",          { XX } },
8881     { "(bad)",          { XX } },
8882     { "(bad)",          { XX } },
8883     { "(bad)",          { XX } },
8884     { "(bad)",          { XX } },
8885   },
8886   {
8887     /* RM_0F01_REG_2 */
8888     { "xgetbv",         { Skip_MODRM } },
8889     { "xsetbv",         { Skip_MODRM } },
8890     { "(bad)",          { XX } },
8891     { "(bad)",          { XX } },
8892     { "(bad)",          { XX } },
8893     { "(bad)",          { XX } },
8894     { "(bad)",          { XX } },
8895     { "(bad)",          { XX } },
8896   },
8897   {
8898     /* RM_0F01_REG_3 */
8899     { "vmrun",          { Skip_MODRM } },
8900     { "vmmcall",        { Skip_MODRM } },
8901     { "vmload",         { Skip_MODRM } },
8902     { "vmsave",         { Skip_MODRM } },
8903     { "stgi",           { Skip_MODRM } },
8904     { "clgi",           { Skip_MODRM } },
8905     { "skinit",         { Skip_MODRM } },
8906     { "invlpga",        { Skip_MODRM } },
8907   },
8908   {
8909     /* RM_0F01_REG_7 */
8910     { "swapgs",         { Skip_MODRM } },
8911     { "rdtscp",         { Skip_MODRM } },
8912     { "(bad)",          { XX } },
8913     { "(bad)",          { XX } },
8914     { "(bad)",          { XX } },
8915     { "(bad)",          { XX } },
8916     { "(bad)",          { XX } },
8917     { "(bad)",          { XX } },
8918   },
8919   {
8920     /* RM_0FAE_REG_5 */
8921     { "lfence",         { Skip_MODRM } },
8922     { "(bad)",          { XX } },
8923     { "(bad)",          { XX } },
8924     { "(bad)",          { XX } },
8925     { "(bad)",          { XX } },
8926     { "(bad)",          { XX } },
8927     { "(bad)",          { XX } },
8928     { "(bad)",          { XX } },
8929   },
8930   {
8931     /* RM_0FAE_REG_6 */
8932     { "mfence",         { Skip_MODRM } },
8933     { "(bad)",          { XX } },
8934     { "(bad)",          { XX } },
8935     { "(bad)",          { XX } },
8936     { "(bad)",          { XX } },
8937     { "(bad)",          { XX } },
8938     { "(bad)",          { XX } },
8939     { "(bad)",          { XX } },
8940   },
8941   {
8942     /* RM_0FAE_REG_7 */
8943     { "sfence",         { Skip_MODRM } },
8944     { "(bad)",          { XX } },
8945     { "(bad)",          { XX } },
8946     { "(bad)",          { XX } },
8947     { "(bad)",          { XX } },
8948     { "(bad)",          { XX } },
8949     { "(bad)",          { XX } },
8950     { "(bad)",          { XX } },
8951   },
8952 };
8953
8954 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8955
8956 static void
8957 ckprefix (void)
8958 {
8959   int newrex;
8960   rex = 0;
8961   rex_original = 0;
8962   rex_ignored = 0;
8963   prefixes = 0;
8964   used_prefixes = 0;
8965   rex_used = 0;
8966   while (1)
8967     {
8968       FETCH_DATA (the_info, codep + 1);
8969       newrex = 0;
8970       switch (*codep)
8971         {
8972         /* REX prefixes family.  */
8973         case 0x40:
8974         case 0x41:
8975         case 0x42:
8976         case 0x43:
8977         case 0x44:
8978         case 0x45:
8979         case 0x46:
8980         case 0x47:
8981         case 0x48:
8982         case 0x49:
8983         case 0x4a:
8984         case 0x4b:
8985         case 0x4c:
8986         case 0x4d:
8987         case 0x4e:
8988         case 0x4f:
8989             if (address_mode == mode_64bit)
8990               newrex = *codep;
8991             else
8992               return;
8993           break;
8994         case 0xf3:
8995           prefixes |= PREFIX_REPZ;
8996           break;
8997         case 0xf2:
8998           prefixes |= PREFIX_REPNZ;
8999           break;
9000         case 0xf0:
9001           prefixes |= PREFIX_LOCK;
9002           break;
9003         case 0x2e:
9004           prefixes |= PREFIX_CS;
9005           break;
9006         case 0x36:
9007           prefixes |= PREFIX_SS;
9008           break;
9009         case 0x3e:
9010           prefixes |= PREFIX_DS;
9011           break;
9012         case 0x26:
9013           prefixes |= PREFIX_ES;
9014           break;
9015         case 0x64:
9016           prefixes |= PREFIX_FS;
9017           break;
9018         case 0x65:
9019           prefixes |= PREFIX_GS;
9020           break;
9021         case 0x66:
9022           prefixes |= PREFIX_DATA;
9023           break;
9024         case 0x67:
9025           prefixes |= PREFIX_ADDR;
9026           break;
9027         case FWAIT_OPCODE:
9028           /* fwait is really an instruction.  If there are prefixes
9029              before the fwait, they belong to the fwait, *not* to the
9030              following instruction.  */
9031           if (prefixes || rex)
9032             {
9033               prefixes |= PREFIX_FWAIT;
9034               codep++;
9035               return;
9036             }
9037           prefixes = PREFIX_FWAIT;
9038           break;
9039         default:
9040           return;
9041         }
9042       /* Rex is ignored when followed by another prefix.  */
9043       if (rex)
9044         {
9045           rex_used = rex;
9046           return;
9047         }
9048       rex = newrex;
9049       rex_original = rex;
9050       codep++;
9051     }
9052 }
9053
9054 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9055    prefix byte.  */
9056
9057 static const char *
9058 prefix_name (int pref, int sizeflag)
9059 {
9060   static const char *rexes [16] =
9061     {
9062       "rex",            /* 0x40 */
9063       "rex.B",          /* 0x41 */
9064       "rex.X",          /* 0x42 */
9065       "rex.XB",         /* 0x43 */
9066       "rex.R",          /* 0x44 */
9067       "rex.RB",         /* 0x45 */
9068       "rex.RX",         /* 0x46 */
9069       "rex.RXB",        /* 0x47 */
9070       "rex.W",          /* 0x48 */
9071       "rex.WB",         /* 0x49 */
9072       "rex.WX",         /* 0x4a */
9073       "rex.WXB",        /* 0x4b */
9074       "rex.WR",         /* 0x4c */
9075       "rex.WRB",        /* 0x4d */
9076       "rex.WRX",        /* 0x4e */
9077       "rex.WRXB",       /* 0x4f */
9078     };
9079
9080   switch (pref)
9081     {
9082     /* REX prefixes family.  */
9083     case 0x40:
9084     case 0x41:
9085     case 0x42:
9086     case 0x43:
9087     case 0x44:
9088     case 0x45:
9089     case 0x46:
9090     case 0x47:
9091     case 0x48:
9092     case 0x49:
9093     case 0x4a:
9094     case 0x4b:
9095     case 0x4c:
9096     case 0x4d:
9097     case 0x4e:
9098     case 0x4f:
9099       return rexes [pref - 0x40];
9100     case 0xf3:
9101       return "repz";
9102     case 0xf2:
9103       return "repnz";
9104     case 0xf0:
9105       return "lock";
9106     case 0x2e:
9107       return "cs";
9108     case 0x36:
9109       return "ss";
9110     case 0x3e:
9111       return "ds";
9112     case 0x26:
9113       return "es";
9114     case 0x64:
9115       return "fs";
9116     case 0x65:
9117       return "gs";
9118     case 0x66:
9119       return (sizeflag & DFLAG) ? "data16" : "data32";
9120     case 0x67:
9121       if (address_mode == mode_64bit)
9122         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9123       else
9124         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9125     case FWAIT_OPCODE:
9126       return "fwait";
9127     default:
9128       return NULL;
9129     }
9130 }
9131
9132 static char op_out[MAX_OPERANDS][100];
9133 static int op_ad, op_index[MAX_OPERANDS];
9134 static int two_source_ops;
9135 static bfd_vma op_address[MAX_OPERANDS];
9136 static bfd_vma op_riprel[MAX_OPERANDS];
9137 static bfd_vma start_pc;
9138
9139 /*
9140  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9141  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9142  *   section of the "Virtual 8086 Mode" chapter.)
9143  * 'pc' should be the address of this instruction, it will
9144  *   be used to print the target address if this is a relative jump or call
9145  * The function returns the length of this instruction in bytes.
9146  */
9147
9148 static char intel_syntax;
9149 static char intel_mnemonic = !SYSV386_COMPAT;
9150 static char open_char;
9151 static char close_char;
9152 static char separator_char;
9153 static char scale_char;
9154
9155 /* Here for backwards compatibility.  When gdb stops using
9156    print_insn_i386_att and print_insn_i386_intel these functions can
9157    disappear, and print_insn_i386 be merged into print_insn.  */
9158 int
9159 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9160 {
9161   intel_syntax = 0;
9162
9163   return print_insn (pc, info);
9164 }
9165
9166 int
9167 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9168 {
9169   intel_syntax = 1;
9170
9171   return print_insn (pc, info);
9172 }
9173
9174 int
9175 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9176 {
9177   intel_syntax = -1;
9178
9179   return print_insn (pc, info);
9180 }
9181
9182 void
9183 print_i386_disassembler_options (FILE *stream)
9184 {
9185   fprintf (stream, _("\n\
9186 The following i386/x86-64 specific disassembler options are supported for use\n\
9187 with the -M switch (multiple options should be separated by commas):\n"));
9188
9189   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9190   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9191   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9192   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9193   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9194   fprintf (stream, _("  att-mnemonic\n"
9195                      "              Display instruction in AT&T mnemonic\n"));
9196   fprintf (stream, _("  intel-mnemonic\n"
9197                      "              Display instruction in Intel mnemonic\n"));
9198   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9199   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9200   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9201   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9202   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9203   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9204 }
9205
9206 /* Get a pointer to struct dis386 with a valid name.  */
9207
9208 static const struct dis386 *
9209 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9210 {
9211   int index, vex_table_index;
9212
9213   if (dp->name != NULL)
9214     return dp;
9215
9216   switch (dp->op[0].bytemode)
9217     {
9218     case USE_REG_TABLE:
9219       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9220       break;
9221
9222     case USE_MOD_TABLE:
9223       index = modrm.mod == 0x3 ? 1 : 0;
9224       dp = &mod_table[dp->op[1].bytemode][index];
9225       break;
9226
9227     case USE_RM_TABLE:
9228       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9229       break;
9230
9231     case USE_PREFIX_TABLE:
9232       if (need_vex)
9233         {
9234           /* The prefix in VEX is implicit.  */
9235           switch (vex.prefix)
9236             {
9237             case 0:
9238               index = 0;
9239               break;
9240             case REPE_PREFIX_OPCODE:
9241               index = 1;
9242               break;
9243             case DATA_PREFIX_OPCODE:
9244               index = 2;
9245               break;
9246             case REPNE_PREFIX_OPCODE:
9247               index = 3;
9248               break;
9249             default:
9250               abort ();
9251               break;
9252             }
9253         }
9254       else
9255         {
9256           index = 0;
9257           used_prefixes |= (prefixes & PREFIX_REPZ);
9258           if (prefixes & PREFIX_REPZ)
9259             {
9260               index = 1;
9261               repz_prefix = NULL;
9262             }
9263           else
9264             {
9265               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9266                  PREFIX_DATA.  */
9267               used_prefixes |= (prefixes & PREFIX_REPNZ);
9268               if (prefixes & PREFIX_REPNZ)
9269                 {
9270                   index = 3;
9271                   repnz_prefix = NULL;
9272                 }
9273               else
9274                 {
9275                   used_prefixes |= (prefixes & PREFIX_DATA);
9276                   if (prefixes & PREFIX_DATA)
9277                     {
9278                       index = 2;
9279                       data_prefix = NULL;
9280                     }
9281                 }
9282             }
9283         }
9284       dp = &prefix_table[dp->op[1].bytemode][index];
9285       break;
9286
9287     case USE_X86_64_TABLE:
9288       index = address_mode == mode_64bit ? 1 : 0;
9289       dp = &x86_64_table[dp->op[1].bytemode][index];
9290       break;
9291
9292     case USE_3BYTE_TABLE:
9293       FETCH_DATA (info, codep + 2);
9294       index = *codep++;
9295       dp = &three_byte_table[dp->op[1].bytemode][index];
9296       modrm.mod = (*codep >> 6) & 3;
9297       modrm.reg = (*codep >> 3) & 7;
9298       modrm.rm = *codep & 7;
9299       break;
9300
9301     case USE_VEX_LEN_TABLE:
9302       if (!need_vex)
9303         abort ();
9304
9305       switch (vex.length)
9306         {
9307         case 128:
9308           index = 0;
9309           break;
9310         case 256:
9311           index = 1;
9312           break;
9313         default:
9314           abort ();
9315           break;
9316         }
9317
9318       dp = &vex_len_table[dp->op[1].bytemode][index];
9319       break;
9320
9321     case USE_VEX_C4_TABLE:
9322       FETCH_DATA (info, codep + 3);
9323       /* All bits in the REX prefix are ignored.  */
9324       rex_ignored = rex;
9325       rex = ~(*codep >> 5) & 0x7;
9326       switch ((*codep & 0x1f))
9327         {
9328         default:
9329           BadOp ();
9330         case 0x1:
9331           vex_table_index = 0;
9332           break;
9333         case 0x2:
9334           vex_table_index = 1;
9335           break;
9336         case 0x3:
9337           vex_table_index = 2;
9338           break;
9339         }
9340       codep++;
9341       vex.w = *codep & 0x80;
9342       if (vex.w && address_mode == mode_64bit)
9343         rex |= REX_W;
9344
9345       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9346       if (address_mode != mode_64bit
9347           && vex.register_specifier > 0x7)
9348         BadOp ();
9349
9350       vex.length = (*codep & 0x4) ? 256 : 128;
9351       switch ((*codep & 0x3))
9352         {
9353         case 0:
9354           vex.prefix = 0;
9355           break;
9356         case 1:
9357           vex.prefix = DATA_PREFIX_OPCODE;
9358           break;
9359         case 2:
9360           vex.prefix = REPE_PREFIX_OPCODE;
9361           break;
9362         case 3:
9363           vex.prefix = REPNE_PREFIX_OPCODE;
9364           break;
9365         }
9366       need_vex = 1;
9367       need_vex_reg = 1;
9368       codep++;
9369       index = *codep++;
9370       dp = &vex_table[vex_table_index][index];
9371       /* There is no MODRM byte for VEX [82|77].  */
9372       if (index != 0x77 && index != 0x82)
9373         {
9374           FETCH_DATA (info, codep + 1);
9375           modrm.mod = (*codep >> 6) & 3;
9376           modrm.reg = (*codep >> 3) & 7;
9377           modrm.rm = *codep & 7;
9378         }
9379       break;
9380
9381     case USE_VEX_C5_TABLE:
9382       FETCH_DATA (info, codep + 2);
9383       /* All bits in the REX prefix are ignored.  */
9384       rex_ignored = rex;
9385       rex = (*codep & 0x80) ? 0 : REX_R;
9386
9387       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9388       if (address_mode != mode_64bit
9389           && vex.register_specifier > 0x7)
9390         BadOp ();
9391
9392       vex.length = (*codep & 0x4) ? 256 : 128;
9393       switch ((*codep & 0x3))
9394         {
9395         case 0:
9396           vex.prefix = 0;
9397           break;
9398         case 1:
9399           vex.prefix = DATA_PREFIX_OPCODE;
9400           break;
9401         case 2:
9402           vex.prefix = REPE_PREFIX_OPCODE;
9403           break;
9404         case 3:
9405           vex.prefix = REPNE_PREFIX_OPCODE;
9406           break;
9407         }
9408       need_vex = 1;
9409       need_vex_reg = 1;
9410       codep++;
9411       index = *codep++;
9412       dp = &vex_table[dp->op[1].bytemode][index];
9413       /* There is no MODRM byte for VEX [82|77].  */
9414       if (index != 0x77 && index != 0x82)
9415         {
9416           FETCH_DATA (info, codep + 1);
9417           modrm.mod = (*codep >> 6) & 3;
9418           modrm.reg = (*codep >> 3) & 7;
9419           modrm.rm = *codep & 7;
9420         }
9421       break;
9422
9423     default:
9424       abort ();
9425     }
9426
9427   if (dp->name != NULL)
9428     return dp;
9429   else
9430     return get_valid_dis386 (dp, info);
9431 }
9432
9433 static int
9434 print_insn (bfd_vma pc, disassemble_info *info)
9435 {
9436   const struct dis386 *dp;
9437   int i;
9438   char *op_txt[MAX_OPERANDS];
9439   int needcomma;
9440   int sizeflag;
9441   const char *p;
9442   struct dis_private priv;
9443   unsigned char op;
9444   char prefix_obuf[32];
9445   char *prefix_obufp;
9446
9447   if (info->mach == bfd_mach_x86_64_intel_syntax
9448       || info->mach == bfd_mach_x86_64
9449       || info->mach == bfd_mach_l1om
9450       || info->mach == bfd_mach_l1om_intel_syntax)
9451     address_mode = mode_64bit;
9452   else
9453     address_mode = mode_32bit;
9454
9455   if (intel_syntax == (char) -1)
9456     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
9457                     || info->mach == bfd_mach_x86_64_intel_syntax
9458                     || info->mach == bfd_mach_l1om_intel_syntax);
9459
9460   if (info->mach == bfd_mach_i386_i386
9461       || info->mach == bfd_mach_x86_64
9462       || info->mach == bfd_mach_l1om
9463       || info->mach == bfd_mach_i386_i386_intel_syntax
9464       || info->mach == bfd_mach_x86_64_intel_syntax
9465       || info->mach == bfd_mach_l1om_intel_syntax)
9466     priv.orig_sizeflag = AFLAG | DFLAG;
9467   else if (info->mach == bfd_mach_i386_i8086)
9468     priv.orig_sizeflag = 0;
9469   else
9470     abort ();
9471
9472   for (p = info->disassembler_options; p != NULL; )
9473     {
9474       if (CONST_STRNEQ (p, "x86-64"))
9475         {
9476           address_mode = mode_64bit;
9477           priv.orig_sizeflag = AFLAG | DFLAG;
9478         }
9479       else if (CONST_STRNEQ (p, "i386"))
9480         {
9481           address_mode = mode_32bit;
9482           priv.orig_sizeflag = AFLAG | DFLAG;
9483         }
9484       else if (CONST_STRNEQ (p, "i8086"))
9485         {
9486           address_mode = mode_16bit;
9487           priv.orig_sizeflag = 0;
9488         }
9489       else if (CONST_STRNEQ (p, "intel"))
9490         {
9491           intel_syntax = 1;
9492           if (CONST_STRNEQ (p + 5, "-mnemonic"))
9493             intel_mnemonic = 1;
9494         }
9495       else if (CONST_STRNEQ (p, "att"))
9496         {
9497           intel_syntax = 0;
9498           if (CONST_STRNEQ (p + 3, "-mnemonic"))
9499             intel_mnemonic = 0;
9500         }
9501       else if (CONST_STRNEQ (p, "addr"))
9502         {
9503           if (address_mode == mode_64bit)
9504             {
9505               if (p[4] == '3' && p[5] == '2')
9506                 priv.orig_sizeflag &= ~AFLAG;
9507               else if (p[4] == '6' && p[5] == '4')
9508                 priv.orig_sizeflag |= AFLAG;
9509             }
9510           else
9511             {
9512               if (p[4] == '1' && p[5] == '6')
9513                 priv.orig_sizeflag &= ~AFLAG;
9514               else if (p[4] == '3' && p[5] == '2')
9515                 priv.orig_sizeflag |= AFLAG;
9516             }
9517         }
9518       else if (CONST_STRNEQ (p, "data"))
9519         {
9520           if (p[4] == '1' && p[5] == '6')
9521             priv.orig_sizeflag &= ~DFLAG;
9522           else if (p[4] == '3' && p[5] == '2')
9523             priv.orig_sizeflag |= DFLAG;
9524         }
9525       else if (CONST_STRNEQ (p, "suffix"))
9526         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9527
9528       p = strchr (p, ',');
9529       if (p != NULL)
9530         p++;
9531     }
9532
9533   if (intel_syntax)
9534     {
9535       names64 = intel_names64;
9536       names32 = intel_names32;
9537       names16 = intel_names16;
9538       names8 = intel_names8;
9539       names8rex = intel_names8rex;
9540       names_seg = intel_names_seg;
9541       index64 = intel_index64;
9542       index32 = intel_index32;
9543       index16 = intel_index16;
9544       open_char = '[';
9545       close_char = ']';
9546       separator_char = '+';
9547       scale_char = '*';
9548     }
9549   else
9550     {
9551       names64 = att_names64;
9552       names32 = att_names32;
9553       names16 = att_names16;
9554       names8 = att_names8;
9555       names8rex = att_names8rex;
9556       names_seg = att_names_seg;
9557       index64 = att_index64;
9558       index32 = att_index32;
9559       index16 = att_index16;
9560       open_char = '(';
9561       close_char =  ')';
9562       separator_char = ',';
9563       scale_char = ',';
9564     }
9565
9566   /* The output looks better if we put 7 bytes on a line, since that
9567      puts most long word instructions on a single line.  Use 8 bytes
9568      for Intel L1OM.  */
9569   if (info->mach == bfd_mach_l1om
9570       || info->mach == bfd_mach_l1om_intel_syntax)
9571     info->bytes_per_line = 8;
9572   else
9573     info->bytes_per_line = 7;
9574
9575   info->private_data = &priv;
9576   priv.max_fetched = priv.the_buffer;
9577   priv.insn_start = pc;
9578
9579   obuf[0] = 0;
9580   for (i = 0; i < MAX_OPERANDS; ++i)
9581     {
9582       op_out[i][0] = 0;
9583       op_index[i] = -1;
9584     }
9585
9586   the_info = info;
9587   start_pc = pc;
9588   start_codep = priv.the_buffer;
9589   codep = priv.the_buffer;
9590
9591   if (setjmp (priv.bailout) != 0)
9592     {
9593       const char *name;
9594
9595       /* Getting here means we tried for data but didn't get it.  That
9596          means we have an incomplete instruction of some sort.  Just
9597          print the first byte as a prefix or a .byte pseudo-op.  */
9598       if (codep > priv.the_buffer)
9599         {
9600           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9601           if (name != NULL)
9602             (*info->fprintf_func) (info->stream, "%s", name);
9603           else
9604             {
9605               /* Just print the first byte as a .byte instruction.  */
9606               (*info->fprintf_func) (info->stream, ".byte 0x%x",
9607                                      (unsigned int) priv.the_buffer[0]);
9608             }
9609
9610           return 1;
9611         }
9612
9613       return -1;
9614     }
9615
9616   obufp = obuf;
9617   ckprefix ();
9618
9619   insn_codep = codep;
9620   sizeflag = priv.orig_sizeflag;
9621
9622   FETCH_DATA (info, codep + 1);
9623   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9624
9625   if (((prefixes & PREFIX_FWAIT)
9626        && ((*codep < 0xd8) || (*codep > 0xdf)))
9627       || (rex && rex_used))
9628     {
9629       const char *name;
9630
9631       /* fwait not followed by floating point instruction, or rex followed
9632          by other prefixes.  Print the first prefix.  */
9633       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9634       if (name == NULL)
9635         name = INTERNAL_DISASSEMBLER_ERROR;
9636       (*info->fprintf_func) (info->stream, "%s", name);
9637       return 1;
9638     }
9639
9640   op = 0;
9641
9642   if (*codep == 0x0f)
9643     {
9644       unsigned char threebyte;
9645       FETCH_DATA (info, codep + 2);
9646       threebyte = *++codep;
9647       dp = &dis386_twobyte[threebyte];
9648       need_modrm = twobyte_has_modrm[*codep];
9649       codep++;
9650     }
9651   else
9652     {
9653       dp = &dis386[*codep];
9654       need_modrm = onebyte_has_modrm[*codep];
9655       codep++;
9656     }
9657
9658   if ((prefixes & PREFIX_REPZ))
9659     {
9660       repz_prefix = "repz ";
9661       used_prefixes |= PREFIX_REPZ;
9662     }
9663   else
9664     repz_prefix = NULL;
9665
9666   if ((prefixes & PREFIX_REPNZ))
9667     {
9668       repnz_prefix = "repnz ";
9669       used_prefixes |= PREFIX_REPNZ;
9670     }
9671   else
9672     repnz_prefix = NULL;
9673
9674   if ((prefixes & PREFIX_LOCK))
9675     {
9676       lock_prefix = "lock ";
9677       used_prefixes |= PREFIX_LOCK;
9678     }
9679   else
9680     lock_prefix = NULL;
9681
9682   addr_prefix = NULL;
9683   if (prefixes & PREFIX_ADDR)
9684     {
9685       sizeflag ^= AFLAG;
9686       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
9687         {
9688           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
9689             addr_prefix = "addr32 ";
9690           else
9691             addr_prefix = "addr16 ";
9692           used_prefixes |= PREFIX_ADDR;
9693         }
9694     }
9695
9696   data_prefix = NULL;
9697   if ((prefixes & PREFIX_DATA))
9698     {
9699       sizeflag ^= DFLAG;
9700       if (dp->op[2].bytemode == cond_jump_mode
9701           && dp->op[0].bytemode == v_mode
9702           && !intel_syntax)
9703         {
9704           if (sizeflag & DFLAG)
9705             data_prefix = "data32 ";
9706           else
9707             data_prefix = "data16 ";
9708           used_prefixes |= PREFIX_DATA;
9709         }
9710     }
9711
9712   if (need_modrm)
9713     {
9714       FETCH_DATA (info, codep + 1);
9715       modrm.mod = (*codep >> 6) & 3;
9716       modrm.reg = (*codep >> 3) & 7;
9717       modrm.rm = *codep & 7;
9718     }
9719
9720    need_vex = 0;
9721    need_vex_reg = 0;
9722    vex_w_done = 0;
9723
9724   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9725     {
9726       dofloat (sizeflag);
9727     }
9728   else
9729     {
9730       dp = get_valid_dis386 (dp, info);
9731       if (dp != NULL && putop (dp->name, sizeflag) == 0)
9732         {
9733           for (i = 0; i < MAX_OPERANDS; ++i)
9734             {
9735               obufp = op_out[i];
9736               op_ad = MAX_OPERANDS - 1 - i;
9737               if (dp->op[i].rtn)
9738                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9739             }
9740         }
9741     }
9742
9743   /* See if any prefixes were not used.  If so, print the first one
9744      separately.  If we don't do this, we'll wind up printing an
9745      instruction stream which does not precisely correspond to the
9746      bytes we are disassembling.  */
9747   if ((prefixes & ~used_prefixes) != 0)
9748     {
9749       const char *name;
9750
9751       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9752       if (name == NULL)
9753         name = INTERNAL_DISASSEMBLER_ERROR;
9754       (*info->fprintf_func) (info->stream, "%s", name);
9755       return 1;
9756     }
9757   if ((rex_original & ~rex_used) || rex_ignored)
9758     {
9759       const char *name;
9760       name = prefix_name (rex_original, priv.orig_sizeflag);
9761       if (name == NULL)
9762         name = INTERNAL_DISASSEMBLER_ERROR;
9763       (*info->fprintf_func) (info->stream, "%s ", name);
9764     }
9765
9766   prefix_obuf[0] = 0;
9767   prefix_obufp = prefix_obuf;
9768   if (lock_prefix)
9769     prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
9770   if (repz_prefix)
9771     prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
9772   if (repnz_prefix)
9773     prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
9774   if (addr_prefix)
9775     prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
9776   if (data_prefix)
9777     prefix_obufp = stpcpy (prefix_obufp, data_prefix);
9778
9779   if (prefix_obuf[0] != 0)
9780     (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
9781
9782   obufp = mnemonicendp;
9783   for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
9784     oappend (" ");
9785   oappend (" ");
9786   (*info->fprintf_func) (info->stream, "%s", obuf);
9787
9788   /* The enter and bound instructions are printed with operands in the same
9789      order as the intel book; everything else is printed in reverse order.  */
9790   if (intel_syntax || two_source_ops)
9791     {
9792       bfd_vma riprel;
9793
9794       for (i = 0; i < MAX_OPERANDS; ++i)
9795         op_txt[i] = op_out[i];
9796
9797       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9798         {
9799           op_ad = op_index[i];
9800           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
9801           op_index[MAX_OPERANDS - 1 - i] = op_ad;
9802           riprel = op_riprel[i];
9803           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
9804           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9805         }
9806     }
9807   else
9808     {
9809       for (i = 0; i < MAX_OPERANDS; ++i)
9810         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
9811     }
9812
9813   needcomma = 0;
9814   for (i = 0; i < MAX_OPERANDS; ++i)
9815     if (*op_txt[i])
9816       {
9817         if (needcomma)
9818           (*info->fprintf_func) (info->stream, ",");
9819         if (op_index[i] != -1 && !op_riprel[i])
9820           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
9821         else
9822           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
9823         needcomma = 1;
9824       }
9825
9826   for (i = 0; i < MAX_OPERANDS; i++)
9827     if (op_index[i] != -1 && op_riprel[i])
9828       {
9829         (*info->fprintf_func) (info->stream, "        # ");
9830         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
9831                                                 + op_address[op_index[i]]), info);
9832         break;
9833       }
9834   return codep - priv.the_buffer;
9835 }
9836
9837 static const char *float_mem[] = {
9838   /* d8 */
9839   "fadd{s|}",
9840   "fmul{s|}",
9841   "fcom{s|}",
9842   "fcomp{s|}",
9843   "fsub{s|}",
9844   "fsubr{s|}",
9845   "fdiv{s|}",
9846   "fdivr{s|}",
9847   /* d9 */
9848   "fld{s|}",
9849   "(bad)",
9850   "fst{s|}",
9851   "fstp{s|}",
9852   "fldenvIC",
9853   "fldcw",
9854   "fNstenvIC",
9855   "fNstcw",
9856   /* da */
9857   "fiadd{l|}",
9858   "fimul{l|}",
9859   "ficom{l|}",
9860   "ficomp{l|}",
9861   "fisub{l|}",
9862   "fisubr{l|}",
9863   "fidiv{l|}",
9864   "fidivr{l|}",
9865   /* db */
9866   "fild{l|}",
9867   "fisttp{l|}",
9868   "fist{l|}",
9869   "fistp{l|}",
9870   "(bad)",
9871   "fld{t||t|}",
9872   "(bad)",
9873   "fstp{t||t|}",
9874   /* dc */
9875   "fadd{l|}",
9876   "fmul{l|}",
9877   "fcom{l|}",
9878   "fcomp{l|}",
9879   "fsub{l|}",
9880   "fsubr{l|}",
9881   "fdiv{l|}",
9882   "fdivr{l|}",
9883   /* dd */
9884   "fld{l|}",
9885   "fisttp{ll|}",
9886   "fst{l||}",
9887   "fstp{l|}",
9888   "frstorIC",
9889   "(bad)",
9890   "fNsaveIC",
9891   "fNstsw",
9892   /* de */
9893   "fiadd",
9894   "fimul",
9895   "ficom",
9896   "ficomp",
9897   "fisub",
9898   "fisubr",
9899   "fidiv",
9900   "fidivr",
9901   /* df */
9902   "fild",
9903   "fisttp",
9904   "fist",
9905   "fistp",
9906   "fbld",
9907   "fild{ll|}",
9908   "fbstp",
9909   "fistp{ll|}",
9910 };
9911
9912 static const unsigned char float_mem_mode[] = {
9913   /* d8 */
9914   d_mode,
9915   d_mode,
9916   d_mode,
9917   d_mode,
9918   d_mode,
9919   d_mode,
9920   d_mode,
9921   d_mode,
9922   /* d9 */
9923   d_mode,
9924   0,
9925   d_mode,
9926   d_mode,
9927   0,
9928   w_mode,
9929   0,
9930   w_mode,
9931   /* da */
9932   d_mode,
9933   d_mode,
9934   d_mode,
9935   d_mode,
9936   d_mode,
9937   d_mode,
9938   d_mode,
9939   d_mode,
9940   /* db */
9941   d_mode,
9942   d_mode,
9943   d_mode,
9944   d_mode,
9945   0,
9946   t_mode,
9947   0,
9948   t_mode,
9949   /* dc */
9950   q_mode,
9951   q_mode,
9952   q_mode,
9953   q_mode,
9954   q_mode,
9955   q_mode,
9956   q_mode,
9957   q_mode,
9958   /* dd */
9959   q_mode,
9960   q_mode,
9961   q_mode,
9962   q_mode,
9963   0,
9964   0,
9965   0,
9966   w_mode,
9967   /* de */
9968   w_mode,
9969   w_mode,
9970   w_mode,
9971   w_mode,
9972   w_mode,
9973   w_mode,
9974   w_mode,
9975   w_mode,
9976   /* df */
9977   w_mode,
9978   w_mode,
9979   w_mode,
9980   w_mode,
9981   t_mode,
9982   q_mode,
9983   t_mode,
9984   q_mode
9985 };
9986
9987 #define ST { OP_ST, 0 }
9988 #define STi { OP_STi, 0 }
9989
9990 #define FGRPd9_2 NULL, { { NULL, 0 } }
9991 #define FGRPd9_4 NULL, { { NULL, 1 } }
9992 #define FGRPd9_5 NULL, { { NULL, 2 } }
9993 #define FGRPd9_6 NULL, { { NULL, 3 } }
9994 #define FGRPd9_7 NULL, { { NULL, 4 } }
9995 #define FGRPda_5 NULL, { { NULL, 5 } }
9996 #define FGRPdb_4 NULL, { { NULL, 6 } }
9997 #define FGRPde_3 NULL, { { NULL, 7 } }
9998 #define FGRPdf_4 NULL, { { NULL, 8 } }
9999
10000 static const struct dis386 float_reg[][8] = {
10001   /* d8 */
10002   {
10003     { "fadd",   { ST, STi } },
10004     { "fmul",   { ST, STi } },
10005     { "fcom",   { STi } },
10006     { "fcomp",  { STi } },
10007     { "fsub",   { ST, STi } },
10008     { "fsubr",  { ST, STi } },
10009     { "fdiv",   { ST, STi } },
10010     { "fdivr",  { ST, STi } },
10011   },
10012   /* d9 */
10013   {
10014     { "fld",    { STi } },
10015     { "fxch",   { STi } },
10016     { FGRPd9_2 },
10017     { "(bad)",  { XX } },
10018     { FGRPd9_4 },
10019     { FGRPd9_5 },
10020     { FGRPd9_6 },
10021     { FGRPd9_7 },
10022   },
10023   /* da */
10024   {
10025     { "fcmovb", { ST, STi } },
10026     { "fcmove", { ST, STi } },
10027     { "fcmovbe",{ ST, STi } },
10028     { "fcmovu", { ST, STi } },
10029     { "(bad)",  { XX } },
10030     { FGRPda_5 },
10031     { "(bad)",  { XX } },
10032     { "(bad)",  { XX } },
10033   },
10034   /* db */
10035   {
10036     { "fcmovnb",{ ST, STi } },
10037     { "fcmovne",{ ST, STi } },
10038     { "fcmovnbe",{ ST, STi } },
10039     { "fcmovnu",{ ST, STi } },
10040     { FGRPdb_4 },
10041     { "fucomi", { ST, STi } },
10042     { "fcomi",  { ST, STi } },
10043     { "(bad)",  { XX } },
10044   },
10045   /* dc */
10046   {
10047     { "fadd",   { STi, ST } },
10048     { "fmul",   { STi, ST } },
10049     { "(bad)",  { XX } },
10050     { "(bad)",  { XX } },
10051     { "fsub!M", { STi, ST } },
10052     { "fsubM",  { STi, ST } },
10053     { "fdiv!M", { STi, ST } },
10054     { "fdivM",  { STi, ST } },
10055   },
10056   /* dd */
10057   {
10058     { "ffree",  { STi } },
10059     { "(bad)",  { XX } },
10060     { "fst",    { STi } },
10061     { "fstp",   { STi } },
10062     { "fucom",  { STi } },
10063     { "fucomp", { STi } },
10064     { "(bad)",  { XX } },
10065     { "(bad)",  { XX } },
10066   },
10067   /* de */
10068   {
10069     { "faddp",  { STi, ST } },
10070     { "fmulp",  { STi, ST } },
10071     { "(bad)",  { XX } },
10072     { FGRPde_3 },
10073     { "fsub!Mp", { STi, ST } },
10074     { "fsubMp", { STi, ST } },
10075     { "fdiv!Mp", { STi, ST } },
10076     { "fdivMp", { STi, ST } },
10077   },
10078   /* df */
10079   {
10080     { "ffreep", { STi } },
10081     { "(bad)",  { XX } },
10082     { "(bad)",  { XX } },
10083     { "(bad)",  { XX } },
10084     { FGRPdf_4 },
10085     { "fucomip", { ST, STi } },
10086     { "fcomip", { ST, STi } },
10087     { "(bad)",  { XX } },
10088   },
10089 };
10090
10091 static char *fgrps[][8] = {
10092   /* d9_2  0 */
10093   {
10094     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10095   },
10096
10097   /* d9_4  1 */
10098   {
10099     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10100   },
10101
10102   /* d9_5  2 */
10103   {
10104     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10105   },
10106
10107   /* d9_6  3 */
10108   {
10109     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10110   },
10111
10112   /* d9_7  4 */
10113   {
10114     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10115   },
10116
10117   /* da_5  5 */
10118   {
10119     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10120   },
10121
10122   /* db_4  6 */
10123   {
10124     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10125     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10126   },
10127
10128   /* de_3  7 */
10129   {
10130     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10131   },
10132
10133   /* df_4  8 */
10134   {
10135     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10136   },
10137 };
10138
10139 static void
10140 swap_operand (void)
10141 {
10142   mnemonicendp[0] = '.';
10143   mnemonicendp[1] = 's';
10144   mnemonicendp += 2;
10145 }
10146
10147 static void
10148 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10149                int sizeflag ATTRIBUTE_UNUSED)
10150 {
10151   /* Skip mod/rm byte.  */
10152   MODRM_CHECK;
10153   codep++;
10154 }
10155
10156 static void
10157 dofloat (int sizeflag)
10158 {
10159   const struct dis386 *dp;
10160   unsigned char floatop;
10161
10162   floatop = codep[-1];
10163
10164   if (modrm.mod != 3)
10165     {
10166       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10167
10168       putop (float_mem[fp_indx], sizeflag);
10169       obufp = op_out[0];
10170       op_ad = 2;
10171       OP_E (float_mem_mode[fp_indx], sizeflag);
10172       return;
10173     }
10174   /* Skip mod/rm byte.  */
10175   MODRM_CHECK;
10176   codep++;
10177
10178   dp = &float_reg[floatop - 0xd8][modrm.reg];
10179   if (dp->name == NULL)
10180     {
10181       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10182
10183       /* Instruction fnstsw is only one with strange arg.  */
10184       if (floatop == 0xdf && codep[-1] == 0xe0)
10185         strcpy (op_out[0], names16[0]);
10186     }
10187   else
10188     {
10189       putop (dp->name, sizeflag);
10190
10191       obufp = op_out[0];
10192       op_ad = 2;
10193       if (dp->op[0].rtn)
10194         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10195
10196       obufp = op_out[1];
10197       op_ad = 1;
10198       if (dp->op[1].rtn)
10199         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10200     }
10201 }
10202
10203 static void
10204 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10205 {
10206   oappend ("%st" + intel_syntax);
10207 }
10208
10209 static void
10210 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10211 {
10212   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10213   oappend (scratchbuf + intel_syntax);
10214 }
10215
10216 /* Capital letters in template are macros.  */
10217 static int
10218 putop (const char *in_template, int sizeflag)
10219 {
10220   const char *p;
10221   int alt = 0;
10222   int cond = 1;
10223   unsigned int l = 0, len = 1;
10224   char last[4];
10225
10226 #define SAVE_LAST(c)                    \
10227   if (l < len && l < sizeof (last))     \
10228     last[l++] = c;                      \
10229   else                                  \
10230     abort ();
10231
10232   for (p = in_template; *p; p++)
10233     {
10234       switch (*p)
10235         {
10236         default:
10237           *obufp++ = *p;
10238           break;
10239         case '%':
10240           len++;
10241           break;
10242         case '!':
10243           cond = 0;
10244           break;
10245         case '{':
10246           alt = 0;
10247           if (intel_syntax)
10248             {
10249               while (*++p != '|')
10250                 if (*p == '}' || *p == '\0')
10251                   abort ();
10252             }
10253           /* Fall through.  */
10254         case 'I':
10255           alt = 1;
10256           continue;
10257         case '|':
10258           while (*++p != '}')
10259             {
10260               if (*p == '\0')
10261                 abort ();
10262             }
10263           break;
10264         case '}':
10265           break;
10266         case 'A':
10267           if (intel_syntax)
10268             break;
10269           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10270             *obufp++ = 'b';
10271           break;
10272         case 'B':
10273           if (l == 0 && len == 1)
10274             {
10275 case_B:
10276               if (intel_syntax)
10277                 break;
10278               if (sizeflag & SUFFIX_ALWAYS)
10279                 *obufp++ = 'b';
10280             }
10281           else
10282             {
10283               if (l != 1
10284                   || len != 2
10285                   || last[0] != 'L')
10286                 {
10287                   SAVE_LAST (*p);
10288                   break;
10289                 }
10290
10291               if (address_mode == mode_64bit
10292                   && !(prefixes & PREFIX_ADDR))
10293                 {
10294                   *obufp++ = 'a';
10295                   *obufp++ = 'b';
10296                   *obufp++ = 's';
10297                 }
10298
10299               goto case_B;
10300             }
10301           break;
10302         case 'C':
10303           if (intel_syntax && !alt)
10304             break;
10305           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10306             {
10307               if (sizeflag & DFLAG)
10308                 *obufp++ = intel_syntax ? 'd' : 'l';
10309               else
10310                 *obufp++ = intel_syntax ? 'w' : 's';
10311               used_prefixes |= (prefixes & PREFIX_DATA);
10312             }
10313           break;
10314         case 'D':
10315           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10316             break;
10317           USED_REX (REX_W);
10318           if (modrm.mod == 3)
10319             {
10320               if (rex & REX_W)
10321                 *obufp++ = 'q';
10322               else if (sizeflag & DFLAG)
10323                 *obufp++ = intel_syntax ? 'd' : 'l';
10324               else
10325                 *obufp++ = 'w';
10326               used_prefixes |= (prefixes & PREFIX_DATA);
10327             }
10328           else
10329             *obufp++ = 'w';
10330           break;
10331         case 'E':               /* For jcxz/jecxz */
10332           if (address_mode == mode_64bit)
10333             {
10334               if (sizeflag & AFLAG)
10335                 *obufp++ = 'r';
10336               else
10337                 *obufp++ = 'e';
10338             }
10339           else
10340             if (sizeflag & AFLAG)
10341               *obufp++ = 'e';
10342           used_prefixes |= (prefixes & PREFIX_ADDR);
10343           break;
10344         case 'F':
10345           if (intel_syntax)
10346             break;
10347           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10348             {
10349               if (sizeflag & AFLAG)
10350                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10351               else
10352                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10353               used_prefixes |= (prefixes & PREFIX_ADDR);
10354             }
10355           break;
10356         case 'G':
10357           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10358             break;
10359           if ((rex & REX_W) || (sizeflag & DFLAG))
10360             *obufp++ = 'l';
10361           else
10362             *obufp++ = 'w';
10363           if (!(rex & REX_W))
10364             used_prefixes |= (prefixes & PREFIX_DATA);
10365           break;
10366         case 'H':
10367           if (intel_syntax)
10368             break;
10369           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10370               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10371             {
10372               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10373               *obufp++ = ',';
10374               *obufp++ = 'p';
10375               if (prefixes & PREFIX_DS)
10376                 *obufp++ = 't';
10377               else
10378                 *obufp++ = 'n';
10379             }
10380           break;
10381         case 'J':
10382           if (intel_syntax)
10383             break;
10384           *obufp++ = 'l';
10385           break;
10386         case 'K':
10387           USED_REX (REX_W);
10388           if (rex & REX_W)
10389             *obufp++ = 'q';
10390           else
10391             *obufp++ = 'd';
10392           break;
10393         case 'Z':
10394           if (intel_syntax)
10395             break;
10396           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10397             {
10398               *obufp++ = 'q';
10399               break;
10400             }
10401           /* Fall through.  */
10402           goto case_L;
10403         case 'L':
10404           if (l != 0 || len != 1)
10405             {
10406               SAVE_LAST (*p);
10407               break;
10408             }
10409 case_L:
10410           if (intel_syntax)
10411             break;
10412           if (sizeflag & SUFFIX_ALWAYS)
10413             *obufp++ = 'l';
10414           break;
10415         case 'M':
10416           if (intel_mnemonic != cond)
10417             *obufp++ = 'r';
10418           break;
10419         case 'N':
10420           if ((prefixes & PREFIX_FWAIT) == 0)
10421             *obufp++ = 'n';
10422           else
10423             used_prefixes |= PREFIX_FWAIT;
10424           break;
10425         case 'O':
10426           USED_REX (REX_W);
10427           if (rex & REX_W)
10428             *obufp++ = 'o';
10429           else if (intel_syntax && (sizeflag & DFLAG))
10430             *obufp++ = 'q';
10431           else
10432             *obufp++ = 'd';
10433           if (!(rex & REX_W))
10434             used_prefixes |= (prefixes & PREFIX_DATA);
10435           break;
10436         case 'T':
10437           if (intel_syntax)
10438             break;
10439           if (address_mode == mode_64bit && (sizeflag & DFLAG))
10440             {
10441               *obufp++ = 'q';
10442               break;
10443             }
10444           /* Fall through.  */
10445         case 'P':
10446           if (intel_syntax)
10447             break;
10448           if ((prefixes & PREFIX_DATA)
10449               || (rex & REX_W)
10450               || (sizeflag & SUFFIX_ALWAYS))
10451             {
10452               USED_REX (REX_W);
10453               if (rex & REX_W)
10454                 *obufp++ = 'q';
10455               else
10456                 {
10457                    if (sizeflag & DFLAG)
10458                       *obufp++ = 'l';
10459                    else
10460                      *obufp++ = 'w';
10461                 }
10462               used_prefixes |= (prefixes & PREFIX_DATA);
10463             }
10464           break;
10465         case 'U':
10466           if (intel_syntax)
10467             break;
10468           if (address_mode == mode_64bit && (sizeflag & DFLAG))
10469             {
10470               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10471                 *obufp++ = 'q';
10472               break;
10473             }
10474           /* Fall through.  */
10475           goto case_Q;
10476         case 'Q':
10477           if (l == 0 && len == 1)
10478             {
10479 case_Q:
10480               if (intel_syntax && !alt)
10481                 break;
10482               USED_REX (REX_W);
10483               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10484                 {
10485                   if (rex & REX_W)
10486                     *obufp++ = 'q';
10487                   else
10488                     {
10489                       if (sizeflag & DFLAG)
10490                         *obufp++ = intel_syntax ? 'd' : 'l';
10491                       else
10492                         *obufp++ = 'w';
10493                     }
10494                   used_prefixes |= (prefixes & PREFIX_DATA);
10495                 }
10496             }
10497           else
10498             {
10499               if (l != 1 || len != 2 || last[0] != 'L')
10500                 {
10501                   SAVE_LAST (*p);
10502                   break;
10503                 }
10504               if (intel_syntax
10505                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
10506                 break;
10507               if ((rex & REX_W))
10508                 {
10509                   USED_REX (REX_W);
10510                   *obufp++ = 'q';
10511                 }
10512               else
10513                 *obufp++ = 'l';
10514             }
10515           break;
10516         case 'R':
10517           USED_REX (REX_W);
10518           if (rex & REX_W)
10519             *obufp++ = 'q';
10520           else if (sizeflag & DFLAG)
10521             {
10522               if (intel_syntax)
10523                   *obufp++ = 'd';
10524               else
10525                   *obufp++ = 'l';
10526             }
10527           else
10528             *obufp++ = 'w';
10529           if (intel_syntax && !p[1]
10530               && ((rex & REX_W) || (sizeflag & DFLAG)))
10531             *obufp++ = 'e';
10532           if (!(rex & REX_W))
10533             used_prefixes |= (prefixes & PREFIX_DATA);
10534           break;
10535         case 'V':
10536           if (l == 0 && len == 1)
10537             {
10538               if (intel_syntax)
10539                 break;
10540               if (address_mode == mode_64bit && (sizeflag & DFLAG))
10541                 {
10542                   if (sizeflag & SUFFIX_ALWAYS)
10543                     *obufp++ = 'q';
10544                   break;
10545                 }
10546             }
10547           else
10548             {
10549               if (l != 1
10550                   || len != 2
10551                   || last[0] != 'L')
10552                 {
10553                   SAVE_LAST (*p);
10554                   break;
10555                 }
10556
10557               if (rex & REX_W)
10558                 {
10559                   *obufp++ = 'a';
10560                   *obufp++ = 'b';
10561                   *obufp++ = 's';
10562                 }
10563             }
10564           /* Fall through.  */
10565           goto case_S;
10566         case 'S':
10567           if (l == 0 && len == 1)
10568             {
10569 case_S:
10570               if (intel_syntax)
10571                 break;
10572               if (sizeflag & SUFFIX_ALWAYS)
10573                 {
10574                   if (rex & REX_W)
10575                     *obufp++ = 'q';
10576                   else
10577                     {
10578                       if (sizeflag & DFLAG)
10579                         *obufp++ = 'l';
10580                       else
10581                         *obufp++ = 'w';
10582                       used_prefixes |= (prefixes & PREFIX_DATA);
10583                     }
10584                 }
10585             }
10586           else
10587             {
10588               if (l != 1
10589                   || len != 2
10590                   || last[0] != 'L')
10591                 {
10592                   SAVE_LAST (*p);
10593                   break;
10594                 }
10595
10596               if (address_mode == mode_64bit
10597                   && !(prefixes & PREFIX_ADDR))
10598                 {
10599                   *obufp++ = 'a';
10600                   *obufp++ = 'b';
10601                   *obufp++ = 's';
10602                 }
10603
10604               goto case_S;
10605             }
10606           break;
10607         case 'X':
10608           if (l != 0 || len != 1)
10609             {
10610               SAVE_LAST (*p);
10611               break;
10612             }
10613           if (need_vex && vex.prefix)
10614             {
10615               if (vex.prefix == DATA_PREFIX_OPCODE)
10616                 *obufp++ = 'd';
10617               else
10618                 *obufp++ = 's';
10619             }
10620           else if (prefixes & PREFIX_DATA)
10621             *obufp++ = 'd';
10622           else
10623             *obufp++ = 's';
10624           used_prefixes |= (prefixes & PREFIX_DATA);
10625           break;
10626         case 'Y':
10627           if (l == 0 && len == 1)
10628             {
10629               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10630                 break;
10631               if (rex & REX_W)
10632                 {
10633                   USED_REX (REX_W);
10634                   *obufp++ = 'q';
10635                 }
10636               break;
10637             }
10638           else
10639             {
10640               if (l != 1 || len != 2 || last[0] != 'X')
10641                 {
10642                   SAVE_LAST (*p);
10643                   break;
10644                 }
10645               if (!need_vex)
10646                 abort ();
10647               if (intel_syntax
10648                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
10649                 break;
10650               switch (vex.length)
10651                 {
10652                 case 128:
10653                   *obufp++ = 'x';
10654                   break;
10655                 case 256:
10656                   *obufp++ = 'y';
10657                   break;
10658                 default:
10659                   abort ();
10660                 }
10661             }
10662           break;
10663         case 'W':
10664           if (l == 0 && len == 1)
10665             {
10666               /* operand size flag for cwtl, cbtw */
10667               USED_REX (REX_W);
10668               if (rex & REX_W)
10669                 {
10670                   if (intel_syntax)
10671                     *obufp++ = 'd';
10672                   else
10673                     *obufp++ = 'l';
10674                 }
10675               else if (sizeflag & DFLAG)
10676                 *obufp++ = 'w';
10677               else
10678                 *obufp++ = 'b';
10679               if (!(rex & REX_W))
10680                 used_prefixes |= (prefixes & PREFIX_DATA);
10681             }
10682           else
10683             {
10684               if (l != 1 || len != 2 || last[0] != 'X')
10685                 {
10686                   SAVE_LAST (*p);
10687                   break;
10688                 }
10689               if (!need_vex)
10690                 abort ();
10691               *obufp++ = vex.w ? 'd': 's';
10692             }
10693           break;
10694         }
10695       alt = 0;
10696     }
10697   *obufp = 0;
10698   mnemonicendp = obufp;
10699   return 0;
10700 }
10701
10702 static void
10703 oappend (const char *s)
10704 {
10705   obufp = stpcpy (obufp, s);
10706 }
10707
10708 static void
10709 append_seg (void)
10710 {
10711   if (prefixes & PREFIX_CS)
10712     {
10713       used_prefixes |= PREFIX_CS;
10714       oappend ("%cs:" + intel_syntax);
10715     }
10716   if (prefixes & PREFIX_DS)
10717     {
10718       used_prefixes |= PREFIX_DS;
10719       oappend ("%ds:" + intel_syntax);
10720     }
10721   if (prefixes & PREFIX_SS)
10722     {
10723       used_prefixes |= PREFIX_SS;
10724       oappend ("%ss:" + intel_syntax);
10725     }
10726   if (prefixes & PREFIX_ES)
10727     {
10728       used_prefixes |= PREFIX_ES;
10729       oappend ("%es:" + intel_syntax);
10730     }
10731   if (prefixes & PREFIX_FS)
10732     {
10733       used_prefixes |= PREFIX_FS;
10734       oappend ("%fs:" + intel_syntax);
10735     }
10736   if (prefixes & PREFIX_GS)
10737     {
10738       used_prefixes |= PREFIX_GS;
10739       oappend ("%gs:" + intel_syntax);
10740     }
10741 }
10742
10743 static void
10744 OP_indirE (int bytemode, int sizeflag)
10745 {
10746   if (!intel_syntax)
10747     oappend ("*");
10748   OP_E (bytemode, sizeflag);
10749 }
10750
10751 static void
10752 print_operand_value (char *buf, int hex, bfd_vma disp)
10753 {
10754   if (address_mode == mode_64bit)
10755     {
10756       if (hex)
10757         {
10758           char tmp[30];
10759           int i;
10760           buf[0] = '0';
10761           buf[1] = 'x';
10762           sprintf_vma (tmp, disp);
10763           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10764           strcpy (buf + 2, tmp + i);
10765         }
10766       else
10767         {
10768           bfd_signed_vma v = disp;
10769           char tmp[30];
10770           int i;
10771           if (v < 0)
10772             {
10773               *(buf++) = '-';
10774               v = -disp;
10775               /* Check for possible overflow on 0x8000000000000000.  */
10776               if (v < 0)
10777                 {
10778                   strcpy (buf, "9223372036854775808");
10779                   return;
10780                 }
10781             }
10782           if (!v)
10783             {
10784               strcpy (buf, "0");
10785               return;
10786             }
10787
10788           i = 0;
10789           tmp[29] = 0;
10790           while (v)
10791             {
10792               tmp[28 - i] = (v % 10) + '0';
10793               v /= 10;
10794               i++;
10795             }
10796           strcpy (buf, tmp + 29 - i);
10797         }
10798     }
10799   else
10800     {
10801       if (hex)
10802         sprintf (buf, "0x%x", (unsigned int) disp);
10803       else
10804         sprintf (buf, "%d", (int) disp);
10805     }
10806 }
10807
10808 /* Put DISP in BUF as signed hex number.  */
10809
10810 static void
10811 print_displacement (char *buf, bfd_vma disp)
10812 {
10813   bfd_signed_vma val = disp;
10814   char tmp[30];
10815   int i, j = 0;
10816
10817   if (val < 0)
10818     {
10819       buf[j++] = '-';
10820       val = -disp;
10821
10822       /* Check for possible overflow.  */
10823       if (val < 0)
10824         {
10825           switch (address_mode)
10826             {
10827             case mode_64bit:
10828               strcpy (buf + j, "0x8000000000000000");
10829               break;
10830             case mode_32bit:
10831               strcpy (buf + j, "0x80000000");
10832               break;
10833             case mode_16bit:
10834               strcpy (buf + j, "0x8000");
10835               break;
10836             }
10837           return;
10838         }
10839     }
10840
10841   buf[j++] = '0';
10842   buf[j++] = 'x';
10843
10844   sprintf_vma (tmp, (bfd_vma) val);
10845   for (i = 0; tmp[i] == '0'; i++)
10846     continue;
10847   if (tmp[i] == '\0')
10848     i--;
10849   strcpy (buf + j, tmp + i);
10850 }
10851
10852 static void
10853 intel_operand_size (int bytemode, int sizeflag)
10854 {
10855   switch (bytemode)
10856     {
10857     case b_mode:
10858     case b_swap_mode:
10859     case dqb_mode:
10860       oappend ("BYTE PTR ");
10861       break;
10862     case w_mode:
10863     case dqw_mode:
10864       oappend ("WORD PTR ");
10865       break;
10866     case stack_v_mode:
10867       if (address_mode == mode_64bit && (sizeflag & DFLAG))
10868         {
10869           oappend ("QWORD PTR ");
10870           used_prefixes |= (prefixes & PREFIX_DATA);
10871           break;
10872         }
10873       /* FALLTHRU */
10874     case v_mode:
10875     case v_swap_mode:
10876     case dq_mode:
10877       USED_REX (REX_W);
10878       if (rex & REX_W)
10879         oappend ("QWORD PTR ");
10880       else if ((sizeflag & DFLAG) || bytemode == dq_mode)
10881         oappend ("DWORD PTR ");
10882       else
10883         oappend ("WORD PTR ");
10884       used_prefixes |= (prefixes & PREFIX_DATA);
10885       break;
10886     case z_mode:
10887       if ((rex & REX_W) || (sizeflag & DFLAG))
10888         *obufp++ = 'D';
10889       oappend ("WORD PTR ");
10890       if (!(rex & REX_W))
10891         used_prefixes |= (prefixes & PREFIX_DATA);
10892       break;
10893     case a_mode:
10894       if (sizeflag & DFLAG)
10895         oappend ("QWORD PTR ");
10896       else
10897         oappend ("DWORD PTR ");
10898       used_prefixes |= (prefixes & PREFIX_DATA);
10899       break;
10900     case d_mode:
10901     case d_swap_mode:
10902     case dqd_mode:
10903       oappend ("DWORD PTR ");
10904       break;
10905     case q_mode:
10906     case q_swap_mode:
10907       oappend ("QWORD PTR ");
10908       break;
10909     case m_mode:
10910       if (address_mode == mode_64bit)
10911         oappend ("QWORD PTR ");
10912       else
10913         oappend ("DWORD PTR ");
10914       break;
10915     case f_mode:
10916       if (sizeflag & DFLAG)
10917         oappend ("FWORD PTR ");
10918       else
10919         oappend ("DWORD PTR ");
10920       used_prefixes |= (prefixes & PREFIX_DATA);
10921       break;
10922     case t_mode:
10923       oappend ("TBYTE PTR ");
10924       break;
10925     case x_mode:
10926     case x_swap_mode:
10927       if (need_vex)
10928         {
10929           switch (vex.length)
10930             {
10931             case 128:
10932               oappend ("XMMWORD PTR ");
10933               break;
10934             case 256:
10935               oappend ("YMMWORD PTR ");
10936               break;
10937             default:
10938               abort ();
10939             }
10940         }
10941       else
10942         oappend ("XMMWORD PTR ");
10943       break;
10944     case xmm_mode:
10945       oappend ("XMMWORD PTR ");
10946       break;
10947     case xmmq_mode:
10948       if (!need_vex)
10949         abort ();
10950
10951       switch (vex.length)
10952         {
10953         case 128:
10954           oappend ("QWORD PTR ");
10955           break;
10956         case 256:
10957           oappend ("XMMWORD PTR ");
10958           break;
10959         default:
10960           abort ();
10961         }
10962       break;
10963     case ymmq_mode:
10964       if (!need_vex)
10965         abort ();
10966
10967       switch (vex.length)
10968         {
10969         case 128:
10970           oappend ("QWORD PTR ");
10971           break;
10972         case 256:
10973           oappend ("YMMWORD PTR ");
10974           break;
10975         default:
10976           abort ();
10977         }
10978       break;
10979     case o_mode:
10980       oappend ("OWORD PTR ");
10981       break;
10982     case vex_w_dq_mode:
10983       if (!need_vex)
10984         abort ();
10985
10986       if (vex.w)
10987         oappend ("QWORD PTR ");
10988       else
10989         oappend ("DWORD PTR ");
10990       break;
10991     default:
10992       break;
10993     }
10994 }
10995
10996 static void
10997 OP_E_register (int bytemode, int sizeflag)
10998 {
10999   int reg = modrm.rm;
11000   const char **names;
11001
11002   USED_REX (REX_B);
11003   if ((rex & REX_B))
11004     reg += 8;
11005
11006   if ((sizeflag & SUFFIX_ALWAYS)
11007       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
11008     swap_operand ();
11009
11010   switch (bytemode)
11011     {
11012     case b_mode:
11013     case b_swap_mode:
11014       USED_REX (0);
11015       if (rex)
11016         names = names8rex;
11017       else
11018         names = names8;
11019       break;
11020     case w_mode:
11021       names = names16;
11022       break;
11023     case d_mode:
11024       names = names32;
11025       break;
11026     case q_mode:
11027       names = names64;
11028       break;
11029     case m_mode:
11030       names = address_mode == mode_64bit ? names64 : names32;
11031       break;
11032     case stack_v_mode:
11033       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11034         {
11035           names = names64;
11036           used_prefixes |= (prefixes & PREFIX_DATA);
11037           break;
11038         }
11039       bytemode = v_mode;
11040       /* FALLTHRU */
11041     case v_mode:
11042     case v_swap_mode:
11043     case dq_mode:
11044     case dqb_mode:
11045     case dqd_mode:
11046     case dqw_mode:
11047       USED_REX (REX_W);
11048       if (rex & REX_W)
11049         names = names64;
11050       else if ((sizeflag & DFLAG)
11051                || (bytemode != v_mode
11052                    && bytemode != v_swap_mode))
11053         names = names32;
11054       else
11055         names = names16;
11056       used_prefixes |= (prefixes & PREFIX_DATA);
11057       break;
11058     case 0:
11059       return;
11060     default:
11061       oappend (INTERNAL_DISASSEMBLER_ERROR);
11062       return;
11063     }
11064   oappend (names[reg]);
11065 }
11066
11067 static void
11068 OP_E_memory (int bytemode, int sizeflag)
11069 {
11070   bfd_vma disp = 0;
11071   int add = (rex & REX_B) ? 8 : 0;
11072   int riprel = 0;
11073
11074   USED_REX (REX_B);
11075   if (intel_syntax)
11076     intel_operand_size (bytemode, sizeflag);
11077   append_seg ();
11078
11079   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11080     {
11081       /* 32/64 bit address mode */
11082       int havedisp;
11083       int havesib;
11084       int havebase;
11085       int haveindex;
11086       int needindex;
11087       int base, rbase;
11088       int index = 0;
11089       int scale = 0;
11090
11091       havesib = 0;
11092       havebase = 1;
11093       haveindex = 0;
11094       base = modrm.rm;
11095
11096       if (base == 4)
11097         {
11098           havesib = 1;
11099           FETCH_DATA (the_info, codep + 1);
11100           index = (*codep >> 3) & 7;
11101           scale = (*codep >> 6) & 3;
11102           base = *codep & 7;
11103           USED_REX (REX_X);
11104           if (rex & REX_X)
11105             index += 8;
11106           haveindex = index != 4;
11107           codep++;
11108         }
11109       rbase = base + add;
11110
11111       switch (modrm.mod)
11112         {
11113         case 0:
11114           if (base == 5)
11115             {
11116               havebase = 0;
11117               if (address_mode == mode_64bit && !havesib)
11118                 riprel = 1;
11119               disp = get32s ();
11120             }
11121           break;
11122         case 1:
11123           FETCH_DATA (the_info, codep + 1);
11124           disp = *codep++;
11125           if ((disp & 0x80) != 0)
11126             disp -= 0x100;
11127           break;
11128         case 2:
11129           disp = get32s ();
11130           break;
11131         }
11132
11133       /* In 32bit mode, we need index register to tell [offset] from
11134          [eiz*1 + offset].  */
11135       needindex = (havesib
11136                    && !havebase
11137                    && !haveindex
11138                    && address_mode == mode_32bit);
11139       havedisp = (havebase
11140                   || needindex
11141                   || (havesib && (haveindex || scale != 0)));
11142
11143       if (!intel_syntax)
11144         if (modrm.mod != 0 || base == 5)
11145           {
11146             if (havedisp || riprel)
11147               print_displacement (scratchbuf, disp);
11148             else
11149               print_operand_value (scratchbuf, 1, disp);
11150             oappend (scratchbuf);
11151             if (riprel)
11152               {
11153                 set_op (disp, 1);
11154                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11155               }
11156           }
11157
11158       if (havebase || haveindex || riprel)
11159         used_prefixes |= PREFIX_ADDR;
11160
11161       if (havedisp || (intel_syntax && riprel))
11162         {
11163           *obufp++ = open_char;
11164           if (intel_syntax && riprel)
11165             {
11166               set_op (disp, 1);
11167               oappend (sizeflag & AFLAG ? "rip" : "eip");
11168             }
11169           *obufp = '\0';
11170           if (havebase)
11171             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11172                      ? names64[rbase] : names32[rbase]);
11173           if (havesib)
11174             {
11175               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11176                  print index to tell base + index from base.  */
11177               if (scale != 0
11178                   || needindex
11179                   || haveindex
11180                   || (havebase && base != ESP_REG_NUM))
11181                 {
11182                   if (!intel_syntax || havebase)
11183                     {
11184                       *obufp++ = separator_char;
11185                       *obufp = '\0';
11186                     }
11187                   if (haveindex)
11188                     oappend (address_mode == mode_64bit
11189                              && (sizeflag & AFLAG)
11190                              ? names64[index] : names32[index]);
11191                   else
11192                     oappend (address_mode == mode_64bit
11193                              && (sizeflag & AFLAG)
11194                              ? index64 : index32);
11195
11196                   *obufp++ = scale_char;
11197                   *obufp = '\0';
11198                   sprintf (scratchbuf, "%d", 1 << scale);
11199                   oappend (scratchbuf);
11200                 }
11201             }
11202           if (intel_syntax
11203               && (disp || modrm.mod != 0 || base == 5))
11204             {
11205               if (!havedisp || (bfd_signed_vma) disp >= 0)
11206                 {
11207                   *obufp++ = '+';
11208                   *obufp = '\0';
11209                 }
11210               else if (modrm.mod != 1 && disp != -disp)
11211                 {
11212                   *obufp++ = '-';
11213                   *obufp = '\0';
11214                   disp = - (bfd_signed_vma) disp;
11215                 }
11216
11217               if (havedisp)
11218                 print_displacement (scratchbuf, disp);
11219               else
11220                 print_operand_value (scratchbuf, 1, disp);
11221               oappend (scratchbuf);
11222             }
11223
11224           *obufp++ = close_char;
11225           *obufp = '\0';
11226         }
11227       else if (intel_syntax)
11228         {
11229           if (modrm.mod != 0 || base == 5)
11230             {
11231               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11232                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11233                 ;
11234               else
11235                 {
11236                   oappend (names_seg[ds_reg - es_reg]);
11237                   oappend (":");
11238                 }
11239               print_operand_value (scratchbuf, 1, disp);
11240               oappend (scratchbuf);
11241             }
11242         }
11243     }
11244   else
11245     { /* 16 bit address mode */
11246       switch (modrm.mod)
11247         {
11248         case 0:
11249           if (modrm.rm == 6)
11250             {
11251               disp = get16 ();
11252               if ((disp & 0x8000) != 0)
11253                 disp -= 0x10000;
11254             }
11255           break;
11256         case 1:
11257           FETCH_DATA (the_info, codep + 1);
11258           disp = *codep++;
11259           if ((disp & 0x80) != 0)
11260             disp -= 0x100;
11261           break;
11262         case 2:
11263           disp = get16 ();
11264           if ((disp & 0x8000) != 0)
11265             disp -= 0x10000;
11266           break;
11267         }
11268
11269       if (!intel_syntax)
11270         if (modrm.mod != 0 || modrm.rm == 6)
11271           {
11272             print_displacement (scratchbuf, disp);
11273             oappend (scratchbuf);
11274           }
11275
11276       if (modrm.mod != 0 || modrm.rm != 6)
11277         {
11278           *obufp++ = open_char;
11279           *obufp = '\0';
11280           oappend (index16[modrm.rm]);
11281           if (intel_syntax
11282               && (disp || modrm.mod != 0 || modrm.rm == 6))
11283             {
11284               if ((bfd_signed_vma) disp >= 0)
11285                 {
11286                   *obufp++ = '+';
11287                   *obufp = '\0';
11288                 }
11289               else if (modrm.mod != 1)
11290                 {
11291                   *obufp++ = '-';
11292                   *obufp = '\0';
11293                   disp = - (bfd_signed_vma) disp;
11294                 }
11295
11296               print_displacement (scratchbuf, disp);
11297               oappend (scratchbuf);
11298             }
11299
11300           *obufp++ = close_char;
11301           *obufp = '\0';
11302         }
11303       else if (intel_syntax)
11304         {
11305           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11306                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11307             ;
11308           else
11309             {
11310               oappend (names_seg[ds_reg - es_reg]);
11311               oappend (":");
11312             }
11313           print_operand_value (scratchbuf, 1, disp & 0xffff);
11314           oappend (scratchbuf);
11315         }
11316     }
11317 }
11318
11319 static void
11320 OP_E_extended (int bytemode, int sizeflag)
11321 {
11322   /* Skip mod/rm byte.  */
11323   MODRM_CHECK;
11324   codep++;
11325
11326   if (modrm.mod == 3)
11327     OP_E_register (bytemode, sizeflag);
11328   else
11329     OP_E_memory (bytemode, sizeflag);
11330 }
11331
11332 static void
11333 OP_E (int bytemode, int sizeflag)
11334 {
11335   OP_E_extended (bytemode, sizeflag);
11336 }
11337
11338
11339 static void
11340 OP_G (int bytemode, int sizeflag)
11341 {
11342   int add = 0;
11343   USED_REX (REX_R);
11344   if (rex & REX_R)
11345     add += 8;
11346   switch (bytemode)
11347     {
11348     case b_mode:
11349       USED_REX (0);
11350       if (rex)
11351         oappend (names8rex[modrm.reg + add]);
11352       else
11353         oappend (names8[modrm.reg + add]);
11354       break;
11355     case w_mode:
11356       oappend (names16[modrm.reg + add]);
11357       break;
11358     case d_mode:
11359       oappend (names32[modrm.reg + add]);
11360       break;
11361     case q_mode:
11362       oappend (names64[modrm.reg + add]);
11363       break;
11364     case v_mode:
11365     case dq_mode:
11366     case dqb_mode:
11367     case dqd_mode:
11368     case dqw_mode:
11369       USED_REX (REX_W);
11370       if (rex & REX_W)
11371         oappend (names64[modrm.reg + add]);
11372       else if ((sizeflag & DFLAG) || bytemode != v_mode)
11373         oappend (names32[modrm.reg + add]);
11374       else
11375         oappend (names16[modrm.reg + add]);
11376       used_prefixes |= (prefixes & PREFIX_DATA);
11377       break;
11378     case m_mode:
11379       if (address_mode == mode_64bit)
11380         oappend (names64[modrm.reg + add]);
11381       else
11382         oappend (names32[modrm.reg + add]);
11383       break;
11384     default:
11385       oappend (INTERNAL_DISASSEMBLER_ERROR);
11386       break;
11387     }
11388 }
11389
11390 static bfd_vma
11391 get64 (void)
11392 {
11393   bfd_vma x;
11394 #ifdef BFD64
11395   unsigned int a;
11396   unsigned int b;
11397
11398   FETCH_DATA (the_info, codep + 8);
11399   a = *codep++ & 0xff;
11400   a |= (*codep++ & 0xff) << 8;
11401   a |= (*codep++ & 0xff) << 16;
11402   a |= (*codep++ & 0xff) << 24;
11403   b = *codep++ & 0xff;
11404   b |= (*codep++ & 0xff) << 8;
11405   b |= (*codep++ & 0xff) << 16;
11406   b |= (*codep++ & 0xff) << 24;
11407   x = a + ((bfd_vma) b << 32);
11408 #else
11409   abort ();
11410   x = 0;
11411 #endif
11412   return x;
11413 }
11414
11415 static bfd_signed_vma
11416 get32 (void)
11417 {
11418   bfd_signed_vma x = 0;
11419
11420   FETCH_DATA (the_info, codep + 4);
11421   x = *codep++ & (bfd_signed_vma) 0xff;
11422   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11423   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11424   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11425   return x;
11426 }
11427
11428 static bfd_signed_vma
11429 get32s (void)
11430 {
11431   bfd_signed_vma x = 0;
11432
11433   FETCH_DATA (the_info, codep + 4);
11434   x = *codep++ & (bfd_signed_vma) 0xff;
11435   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11436   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11437   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11438
11439   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11440
11441   return x;
11442 }
11443
11444 static int
11445 get16 (void)
11446 {
11447   int x = 0;
11448
11449   FETCH_DATA (the_info, codep + 2);
11450   x = *codep++ & 0xff;
11451   x |= (*codep++ & 0xff) << 8;
11452   return x;
11453 }
11454
11455 static void
11456 set_op (bfd_vma op, int riprel)
11457 {
11458   op_index[op_ad] = op_ad;
11459   if (address_mode == mode_64bit)
11460     {
11461       op_address[op_ad] = op;
11462       op_riprel[op_ad] = riprel;
11463     }
11464   else
11465     {
11466       /* Mask to get a 32-bit address.  */
11467       op_address[op_ad] = op & 0xffffffff;
11468       op_riprel[op_ad] = riprel & 0xffffffff;
11469     }
11470 }
11471
11472 static void
11473 OP_REG (int code, int sizeflag)
11474 {
11475   const char *s;
11476   int add;
11477   USED_REX (REX_B);
11478   if (rex & REX_B)
11479     add = 8;
11480   else
11481     add = 0;
11482
11483   switch (code)
11484     {
11485     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11486     case sp_reg: case bp_reg: case si_reg: case di_reg:
11487       s = names16[code - ax_reg + add];
11488       break;
11489     case es_reg: case ss_reg: case cs_reg:
11490     case ds_reg: case fs_reg: case gs_reg:
11491       s = names_seg[code - es_reg + add];
11492       break;
11493     case al_reg: case ah_reg: case cl_reg: case ch_reg:
11494     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11495       USED_REX (0);
11496       if (rex)
11497         s = names8rex[code - al_reg + add];
11498       else
11499         s = names8[code - al_reg];
11500       break;
11501     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
11502     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
11503       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11504         {
11505           s = names64[code - rAX_reg + add];
11506           break;
11507         }
11508       code += eAX_reg - rAX_reg;
11509       /* Fall through.  */
11510     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11511     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11512       USED_REX (REX_W);
11513       if (rex & REX_W)
11514         s = names64[code - eAX_reg + add];
11515       else if (sizeflag & DFLAG)
11516         s = names32[code - eAX_reg + add];
11517       else
11518         s = names16[code - eAX_reg + add];
11519       used_prefixes |= (prefixes & PREFIX_DATA);
11520       break;
11521     default:
11522       s = INTERNAL_DISASSEMBLER_ERROR;
11523       break;
11524     }
11525   oappend (s);
11526 }
11527
11528 static void
11529 OP_IMREG (int code, int sizeflag)
11530 {
11531   const char *s;
11532
11533   switch (code)
11534     {
11535     case indir_dx_reg:
11536       if (intel_syntax)
11537         s = "dx";
11538       else
11539         s = "(%dx)";
11540       break;
11541     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11542     case sp_reg: case bp_reg: case si_reg: case di_reg:
11543       s = names16[code - ax_reg];
11544       break;
11545     case es_reg: case ss_reg: case cs_reg:
11546     case ds_reg: case fs_reg: case gs_reg:
11547       s = names_seg[code - es_reg];
11548       break;
11549     case al_reg: case ah_reg: case cl_reg: case ch_reg:
11550     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11551       USED_REX (0);
11552       if (rex)
11553         s = names8rex[code - al_reg];
11554       else
11555         s = names8[code - al_reg];
11556       break;
11557     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11558     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11559       USED_REX (REX_W);
11560       if (rex & REX_W)
11561         s = names64[code - eAX_reg];
11562       else if (sizeflag & DFLAG)
11563         s = names32[code - eAX_reg];
11564       else
11565         s = names16[code - eAX_reg];
11566       used_prefixes |= (prefixes & PREFIX_DATA);
11567       break;
11568     case z_mode_ax_reg:
11569       if ((rex & REX_W) || (sizeflag & DFLAG))
11570         s = *names32;
11571       else
11572         s = *names16;
11573       if (!(rex & REX_W))
11574         used_prefixes |= (prefixes & PREFIX_DATA);
11575       break;
11576     default:
11577       s = INTERNAL_DISASSEMBLER_ERROR;
11578       break;
11579     }
11580   oappend (s);
11581 }
11582
11583 static void
11584 OP_I (int bytemode, int sizeflag)
11585 {
11586   bfd_signed_vma op;
11587   bfd_signed_vma mask = -1;
11588
11589   switch (bytemode)
11590     {
11591     case b_mode:
11592       FETCH_DATA (the_info, codep + 1);
11593       op = *codep++;
11594       mask = 0xff;
11595       break;
11596     case q_mode:
11597       if (address_mode == mode_64bit)
11598         {
11599           op = get32s ();
11600           break;
11601         }
11602       /* Fall through.  */
11603     case v_mode:
11604       USED_REX (REX_W);
11605       if (rex & REX_W)
11606         op = get32s ();
11607       else if (sizeflag & DFLAG)
11608         {
11609           op = get32 ();
11610           mask = 0xffffffff;
11611         }
11612       else
11613         {
11614           op = get16 ();
11615           mask = 0xfffff;
11616         }
11617       used_prefixes |= (prefixes & PREFIX_DATA);
11618       break;
11619     case w_mode:
11620       mask = 0xfffff;
11621       op = get16 ();
11622       break;
11623     case const_1_mode:
11624       if (intel_syntax)
11625         oappend ("1");
11626       return;
11627     default:
11628       oappend (INTERNAL_DISASSEMBLER_ERROR);
11629       return;
11630     }
11631
11632   op &= mask;
11633   scratchbuf[0] = '$';
11634   print_operand_value (scratchbuf + 1, 1, op);
11635   oappend (scratchbuf + intel_syntax);
11636   scratchbuf[0] = '\0';
11637 }
11638
11639 static void
11640 OP_I64 (int bytemode, int sizeflag)
11641 {
11642   bfd_signed_vma op;
11643   bfd_signed_vma mask = -1;
11644
11645   if (address_mode != mode_64bit)
11646     {
11647       OP_I (bytemode, sizeflag);
11648       return;
11649     }
11650
11651   switch (bytemode)
11652     {
11653     case b_mode:
11654       FETCH_DATA (the_info, codep + 1);
11655       op = *codep++;
11656       mask = 0xff;
11657       break;
11658     case v_mode:
11659       USED_REX (REX_W);
11660       if (rex & REX_W)
11661         op = get64 ();
11662       else if (sizeflag & DFLAG)
11663         {
11664           op = get32 ();
11665           mask = 0xffffffff;
11666         }
11667       else
11668         {
11669           op = get16 ();
11670           mask = 0xfffff;
11671         }
11672       used_prefixes |= (prefixes & PREFIX_DATA);
11673       break;
11674     case w_mode:
11675       mask = 0xfffff;
11676       op = get16 ();
11677       break;
11678     default:
11679       oappend (INTERNAL_DISASSEMBLER_ERROR);
11680       return;
11681     }
11682
11683   op &= mask;
11684   scratchbuf[0] = '$';
11685   print_operand_value (scratchbuf + 1, 1, op);
11686   oappend (scratchbuf + intel_syntax);
11687   scratchbuf[0] = '\0';
11688 }
11689
11690 static void
11691 OP_sI (int bytemode, int sizeflag)
11692 {
11693   bfd_signed_vma op;
11694   bfd_signed_vma mask = -1;
11695
11696   switch (bytemode)
11697     {
11698     case b_mode:
11699       FETCH_DATA (the_info, codep + 1);
11700       op = *codep++;
11701       if ((op & 0x80) != 0)
11702         op -= 0x100;
11703       mask = 0xffffffff;
11704       break;
11705     case v_mode:
11706       USED_REX (REX_W);
11707       if (rex & REX_W)
11708         op = get32s ();
11709       else if (sizeflag & DFLAG)
11710         {
11711           op = get32s ();
11712           mask = 0xffffffff;
11713         }
11714       else
11715         {
11716           mask = 0xffffffff;
11717           op = get16 ();
11718           if ((op & 0x8000) != 0)
11719             op -= 0x10000;
11720         }
11721       used_prefixes |= (prefixes & PREFIX_DATA);
11722       break;
11723     case w_mode:
11724       op = get16 ();
11725       mask = 0xffffffff;
11726       if ((op & 0x8000) != 0)
11727         op -= 0x10000;
11728       break;
11729     default:
11730       oappend (INTERNAL_DISASSEMBLER_ERROR);
11731       return;
11732     }
11733
11734   scratchbuf[0] = '$';
11735   print_operand_value (scratchbuf + 1, 1, op);
11736   oappend (scratchbuf + intel_syntax);
11737 }
11738
11739 static void
11740 OP_J (int bytemode, int sizeflag)
11741 {
11742   bfd_vma disp;
11743   bfd_vma mask = -1;
11744   bfd_vma segment = 0;
11745
11746   switch (bytemode)
11747     {
11748     case b_mode:
11749       FETCH_DATA (the_info, codep + 1);
11750       disp = *codep++;
11751       if ((disp & 0x80) != 0)
11752         disp -= 0x100;
11753       break;
11754     case v_mode:
11755       if ((sizeflag & DFLAG) || (rex & REX_W))
11756         disp = get32s ();
11757       else
11758         {
11759           disp = get16 ();
11760           if ((disp & 0x8000) != 0)
11761             disp -= 0x10000;
11762           /* In 16bit mode, address is wrapped around at 64k within
11763              the same segment.  Otherwise, a data16 prefix on a jump
11764              instruction means that the pc is masked to 16 bits after
11765              the displacement is added!  */
11766           mask = 0xffff;
11767           if ((prefixes & PREFIX_DATA) == 0)
11768             segment = ((start_pc + codep - start_codep)
11769                        & ~((bfd_vma) 0xffff));
11770         }
11771       used_prefixes |= (prefixes & PREFIX_DATA);
11772       break;
11773     default:
11774       oappend (INTERNAL_DISASSEMBLER_ERROR);
11775       return;
11776     }
11777   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
11778   set_op (disp, 0);
11779   print_operand_value (scratchbuf, 1, disp);
11780   oappend (scratchbuf);
11781 }
11782
11783 static void
11784 OP_SEG (int bytemode, int sizeflag)
11785 {
11786   if (bytemode == w_mode)
11787     oappend (names_seg[modrm.reg]);
11788   else
11789     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
11790 }
11791
11792 static void
11793 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
11794 {
11795   int seg, offset;
11796
11797   if (sizeflag & DFLAG)
11798     {
11799       offset = get32 ();
11800       seg = get16 ();
11801     }
11802   else
11803     {
11804       offset = get16 ();
11805       seg = get16 ();
11806     }
11807   used_prefixes |= (prefixes & PREFIX_DATA);
11808   if (intel_syntax)
11809     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
11810   else
11811     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
11812   oappend (scratchbuf);
11813 }
11814
11815 static void
11816 OP_OFF (int bytemode, int sizeflag)
11817 {
11818   bfd_vma off;
11819
11820   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11821     intel_operand_size (bytemode, sizeflag);
11822   append_seg ();
11823
11824   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11825     off = get32 ();
11826   else
11827     off = get16 ();
11828
11829   if (intel_syntax)
11830     {
11831       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11832                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
11833         {
11834           oappend (names_seg[ds_reg - es_reg]);
11835           oappend (":");
11836         }
11837     }
11838   print_operand_value (scratchbuf, 1, off);
11839   oappend (scratchbuf);
11840 }
11841
11842 static void
11843 OP_OFF64 (int bytemode, int sizeflag)
11844 {
11845   bfd_vma off;
11846
11847   if (address_mode != mode_64bit
11848       || (prefixes & PREFIX_ADDR))
11849     {
11850       OP_OFF (bytemode, sizeflag);
11851       return;
11852     }
11853
11854   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11855     intel_operand_size (bytemode, sizeflag);
11856   append_seg ();
11857
11858   off = get64 ();
11859
11860   if (intel_syntax)
11861     {
11862       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11863                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
11864         {
11865           oappend (names_seg[ds_reg - es_reg]);
11866           oappend (":");
11867         }
11868     }
11869   print_operand_value (scratchbuf, 1, off);
11870   oappend (scratchbuf);
11871 }
11872
11873 static void
11874 ptr_reg (int code, int sizeflag)
11875 {
11876   const char *s;
11877
11878   *obufp++ = open_char;
11879   used_prefixes |= (prefixes & PREFIX_ADDR);
11880   if (address_mode == mode_64bit)
11881     {
11882       if (!(sizeflag & AFLAG))
11883         s = names32[code - eAX_reg];
11884       else
11885         s = names64[code - eAX_reg];
11886     }
11887   else if (sizeflag & AFLAG)
11888     s = names32[code - eAX_reg];
11889   else
11890     s = names16[code - eAX_reg];
11891   oappend (s);
11892   *obufp++ = close_char;
11893   *obufp = 0;
11894 }
11895
11896 static void
11897 OP_ESreg (int code, int sizeflag)
11898 {
11899   if (intel_syntax)
11900     {
11901       switch (codep[-1])
11902         {
11903         case 0x6d:      /* insw/insl */
11904           intel_operand_size (z_mode, sizeflag);
11905           break;
11906         case 0xa5:      /* movsw/movsl/movsq */
11907         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
11908         case 0xab:      /* stosw/stosl */
11909         case 0xaf:      /* scasw/scasl */
11910           intel_operand_size (v_mode, sizeflag);
11911           break;
11912         default:
11913           intel_operand_size (b_mode, sizeflag);
11914         }
11915     }
11916   oappend ("%es:" + intel_syntax);
11917   ptr_reg (code, sizeflag);
11918 }
11919
11920 static void
11921 OP_DSreg (int code, int sizeflag)
11922 {
11923   if (intel_syntax)
11924     {
11925       switch (codep[-1])
11926         {
11927         case 0x6f:      /* outsw/outsl */
11928           intel_operand_size (z_mode, sizeflag);
11929           break;
11930         case 0xa5:      /* movsw/movsl/movsq */
11931         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
11932         case 0xad:      /* lodsw/lodsl/lodsq */
11933           intel_operand_size (v_mode, sizeflag);
11934           break;
11935         default:
11936           intel_operand_size (b_mode, sizeflag);
11937         }
11938     }
11939   if ((prefixes
11940        & (PREFIX_CS
11941           | PREFIX_DS
11942           | PREFIX_SS
11943           | PREFIX_ES
11944           | PREFIX_FS
11945           | PREFIX_GS)) == 0)
11946     prefixes |= PREFIX_DS;
11947   append_seg ();
11948   ptr_reg (code, sizeflag);
11949 }
11950
11951 static void
11952 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11953 {
11954   int add;
11955   if (rex & REX_R)
11956     {
11957       USED_REX (REX_R);
11958       add = 8;
11959     }
11960   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
11961     {
11962       lock_prefix = NULL;
11963       used_prefixes |= PREFIX_LOCK;
11964       add = 8;
11965     }
11966   else
11967     add = 0;
11968   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
11969   oappend (scratchbuf + intel_syntax);
11970 }
11971
11972 static void
11973 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11974 {
11975   int add;
11976   USED_REX (REX_R);
11977   if (rex & REX_R)
11978     add = 8;
11979   else
11980     add = 0;
11981   if (intel_syntax)
11982     sprintf (scratchbuf, "db%d", modrm.reg + add);
11983   else
11984     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
11985   oappend (scratchbuf);
11986 }
11987
11988 static void
11989 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11990 {
11991   sprintf (scratchbuf, "%%tr%d", modrm.reg);
11992   oappend (scratchbuf + intel_syntax);
11993 }
11994
11995 static void
11996 OP_R (int bytemode, int sizeflag)
11997 {
11998   if (modrm.mod == 3)
11999     OP_E (bytemode, sizeflag);
12000   else
12001     BadOp ();
12002 }
12003
12004 static void
12005 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12006 {
12007   used_prefixes |= (prefixes & PREFIX_DATA);
12008   if (prefixes & PREFIX_DATA)
12009     {
12010       int add;
12011       USED_REX (REX_R);
12012       if (rex & REX_R)
12013         add = 8;
12014       else
12015         add = 0;
12016       sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12017     }
12018   else
12019     sprintf (scratchbuf, "%%mm%d", modrm.reg);
12020   oappend (scratchbuf + intel_syntax);
12021 }
12022
12023 static void
12024 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12025 {
12026   int add;
12027   USED_REX (REX_R);
12028   if (rex & REX_R)
12029     add = 8;
12030   else
12031     add = 0;
12032   if (need_vex && bytemode != xmm_mode)
12033     {
12034       switch (vex.length)
12035         {
12036         case 128:
12037           sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12038           break;
12039         case 256:
12040           sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12041           break;
12042         default:
12043           abort ();
12044         }
12045     }
12046   else
12047     sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12048   oappend (scratchbuf + intel_syntax);
12049 }
12050
12051 static void
12052 OP_EM (int bytemode, int sizeflag)
12053 {
12054   if (modrm.mod != 3)
12055     {
12056       if (intel_syntax
12057           && (bytemode == v_mode || bytemode == v_swap_mode))
12058         {
12059           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12060           used_prefixes |= (prefixes & PREFIX_DATA);
12061         }
12062       OP_E (bytemode, sizeflag);
12063       return;
12064     }
12065
12066   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12067     swap_operand ();
12068
12069   /* Skip mod/rm byte.  */
12070   MODRM_CHECK;
12071   codep++;
12072   used_prefixes |= (prefixes & PREFIX_DATA);
12073   if (prefixes & PREFIX_DATA)
12074     {
12075       int add;
12076
12077       USED_REX (REX_B);
12078       if (rex & REX_B)
12079         add = 8;
12080       else
12081         add = 0;
12082       sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12083     }
12084   else
12085     sprintf (scratchbuf, "%%mm%d", modrm.rm);
12086   oappend (scratchbuf + intel_syntax);
12087 }
12088
12089 /* cvt* are the only instructions in sse2 which have
12090    both SSE and MMX operands and also have 0x66 prefix
12091    in their opcode. 0x66 was originally used to differentiate
12092    between SSE and MMX instruction(operands). So we have to handle the
12093    cvt* separately using OP_EMC and OP_MXC */
12094 static void
12095 OP_EMC (int bytemode, int sizeflag)
12096 {
12097   if (modrm.mod != 3)
12098     {
12099       if (intel_syntax && bytemode == v_mode)
12100         {
12101           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12102           used_prefixes |= (prefixes & PREFIX_DATA);
12103         }
12104       OP_E (bytemode, sizeflag);
12105       return;
12106     }
12107
12108   /* Skip mod/rm byte.  */
12109   MODRM_CHECK;
12110   codep++;
12111   used_prefixes |= (prefixes & PREFIX_DATA);
12112   sprintf (scratchbuf, "%%mm%d", modrm.rm);
12113   oappend (scratchbuf + intel_syntax);
12114 }
12115
12116 static void
12117 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12118 {
12119   used_prefixes |= (prefixes & PREFIX_DATA);
12120   sprintf (scratchbuf, "%%mm%d", modrm.reg);
12121   oappend (scratchbuf + intel_syntax);
12122 }
12123
12124 static void
12125 OP_EX (int bytemode, int sizeflag)
12126 {
12127   int add;
12128
12129   /* Skip mod/rm byte.  */
12130   MODRM_CHECK;
12131   codep++;
12132
12133   if (modrm.mod != 3)
12134     {
12135       OP_E_memory (bytemode, sizeflag);
12136       return;
12137     }
12138
12139   USED_REX (REX_B);
12140   if (rex & REX_B)
12141     add = 8;
12142   else
12143     add = 0;
12144
12145   if ((sizeflag & SUFFIX_ALWAYS)
12146       && (bytemode == x_swap_mode
12147           || bytemode == d_swap_mode
12148           || bytemode == q_swap_mode))
12149     swap_operand ();
12150
12151   if (need_vex
12152       && bytemode != xmm_mode
12153       && bytemode != xmmq_mode)
12154     {
12155       switch (vex.length)
12156         {
12157         case 128:
12158           sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12159           break;
12160         case 256:
12161           sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12162           break;
12163         default:
12164           abort ();
12165         }
12166     }
12167   else
12168     sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12169   oappend (scratchbuf + intel_syntax);
12170 }
12171
12172 static void
12173 OP_MS (int bytemode, int sizeflag)
12174 {
12175   if (modrm.mod == 3)
12176     OP_EM (bytemode, sizeflag);
12177   else
12178     BadOp ();
12179 }
12180
12181 static void
12182 OP_XS (int bytemode, int sizeflag)
12183 {
12184   if (modrm.mod == 3)
12185     OP_EX (bytemode, sizeflag);
12186   else
12187     BadOp ();
12188 }
12189
12190 static void
12191 OP_M (int bytemode, int sizeflag)
12192 {
12193   if (modrm.mod == 3)
12194     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12195     BadOp ();
12196   else
12197     OP_E (bytemode, sizeflag);
12198 }
12199
12200 static void
12201 OP_0f07 (int bytemode, int sizeflag)
12202 {
12203   if (modrm.mod != 3 || modrm.rm != 0)
12204     BadOp ();
12205   else
12206     OP_E (bytemode, sizeflag);
12207 }
12208
12209 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12210    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12211
12212 static void
12213 NOP_Fixup1 (int bytemode, int sizeflag)
12214 {
12215   if ((prefixes & PREFIX_DATA) != 0
12216       || (rex != 0
12217           && rex != 0x48
12218           && address_mode == mode_64bit))
12219     OP_REG (bytemode, sizeflag);
12220   else
12221     strcpy (obuf, "nop");
12222 }
12223
12224 static void
12225 NOP_Fixup2 (int bytemode, int sizeflag)
12226 {
12227   if ((prefixes & PREFIX_DATA) != 0
12228       || (rex != 0
12229           && rex != 0x48
12230           && address_mode == mode_64bit))
12231     OP_IMREG (bytemode, sizeflag);
12232 }
12233
12234 static const char *const Suffix3DNow[] = {
12235 /* 00 */        NULL,           NULL,           NULL,           NULL,
12236 /* 04 */        NULL,           NULL,           NULL,           NULL,
12237 /* 08 */        NULL,           NULL,           NULL,           NULL,
12238 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12239 /* 10 */        NULL,           NULL,           NULL,           NULL,
12240 /* 14 */        NULL,           NULL,           NULL,           NULL,
12241 /* 18 */        NULL,           NULL,           NULL,           NULL,
12242 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12243 /* 20 */        NULL,           NULL,           NULL,           NULL,
12244 /* 24 */        NULL,           NULL,           NULL,           NULL,
12245 /* 28 */        NULL,           NULL,           NULL,           NULL,
12246 /* 2C */        NULL,           NULL,           NULL,           NULL,
12247 /* 30 */        NULL,           NULL,           NULL,           NULL,
12248 /* 34 */        NULL,           NULL,           NULL,           NULL,
12249 /* 38 */        NULL,           NULL,           NULL,           NULL,
12250 /* 3C */        NULL,           NULL,           NULL,           NULL,
12251 /* 40 */        NULL,           NULL,           NULL,           NULL,
12252 /* 44 */        NULL,           NULL,           NULL,           NULL,
12253 /* 48 */        NULL,           NULL,           NULL,           NULL,
12254 /* 4C */        NULL,           NULL,           NULL,           NULL,
12255 /* 50 */        NULL,           NULL,           NULL,           NULL,
12256 /* 54 */        NULL,           NULL,           NULL,           NULL,
12257 /* 58 */        NULL,           NULL,           NULL,           NULL,
12258 /* 5C */        NULL,           NULL,           NULL,           NULL,
12259 /* 60 */        NULL,           NULL,           NULL,           NULL,
12260 /* 64 */        NULL,           NULL,           NULL,           NULL,
12261 /* 68 */        NULL,           NULL,           NULL,           NULL,
12262 /* 6C */        NULL,           NULL,           NULL,           NULL,
12263 /* 70 */        NULL,           NULL,           NULL,           NULL,
12264 /* 74 */        NULL,           NULL,           NULL,           NULL,
12265 /* 78 */        NULL,           NULL,           NULL,           NULL,
12266 /* 7C */        NULL,           NULL,           NULL,           NULL,
12267 /* 80 */        NULL,           NULL,           NULL,           NULL,
12268 /* 84 */        NULL,           NULL,           NULL,           NULL,
12269 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12270 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12271 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12272 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12273 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12274 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12275 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12276 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12277 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12278 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12279 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12280 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12281 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12282 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12283 /* C0 */        NULL,           NULL,           NULL,           NULL,
12284 /* C4 */        NULL,           NULL,           NULL,           NULL,
12285 /* C8 */        NULL,           NULL,           NULL,           NULL,
12286 /* CC */        NULL,           NULL,           NULL,           NULL,
12287 /* D0 */        NULL,           NULL,           NULL,           NULL,
12288 /* D4 */        NULL,           NULL,           NULL,           NULL,
12289 /* D8 */        NULL,           NULL,           NULL,           NULL,
12290 /* DC */        NULL,           NULL,           NULL,           NULL,
12291 /* E0 */        NULL,           NULL,           NULL,           NULL,
12292 /* E4 */        NULL,           NULL,           NULL,           NULL,
12293 /* E8 */        NULL,           NULL,           NULL,           NULL,
12294 /* EC */        NULL,           NULL,           NULL,           NULL,
12295 /* F0 */        NULL,           NULL,           NULL,           NULL,
12296 /* F4 */        NULL,           NULL,           NULL,           NULL,
12297 /* F8 */        NULL,           NULL,           NULL,           NULL,
12298 /* FC */        NULL,           NULL,           NULL,           NULL,
12299 };
12300
12301 static void
12302 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12303 {
12304   const char *mnemonic;
12305
12306   FETCH_DATA (the_info, codep + 1);
12307   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12308      place where an 8-bit immediate would normally go.  ie. the last
12309      byte of the instruction.  */
12310   obufp = mnemonicendp;
12311   mnemonic = Suffix3DNow[*codep++ & 0xff];
12312   if (mnemonic)
12313     oappend (mnemonic);
12314   else
12315     {
12316       /* Since a variable sized modrm/sib chunk is between the start
12317          of the opcode (0x0f0f) and the opcode suffix, we need to do
12318          all the modrm processing first, and don't know until now that
12319          we have a bad opcode.  This necessitates some cleaning up.  */
12320       op_out[0][0] = '\0';
12321       op_out[1][0] = '\0';
12322       BadOp ();
12323     }
12324   mnemonicendp = obufp;
12325 }
12326
12327 static struct op simd_cmp_op[] =
12328 {
12329   { STRING_COMMA_LEN ("eq") },
12330   { STRING_COMMA_LEN ("lt") },
12331   { STRING_COMMA_LEN ("le") },
12332   { STRING_COMMA_LEN ("unord") },
12333   { STRING_COMMA_LEN ("neq") },
12334   { STRING_COMMA_LEN ("nlt") },
12335   { STRING_COMMA_LEN ("nle") },
12336   { STRING_COMMA_LEN ("ord") }
12337 };
12338
12339 static void
12340 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12341 {
12342   unsigned int cmp_type;
12343
12344   FETCH_DATA (the_info, codep + 1);
12345   cmp_type = *codep++ & 0xff;
12346   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12347     {
12348       char suffix [3];
12349       char *p = mnemonicendp - 2;
12350       suffix[0] = p[0];
12351       suffix[1] = p[1];
12352       suffix[2] = '\0';
12353       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12354       mnemonicendp += simd_cmp_op[cmp_type].len;
12355     }
12356   else
12357     {
12358       /* We have a reserved extension byte.  Output it directly.  */
12359       scratchbuf[0] = '$';
12360       print_operand_value (scratchbuf + 1, 1, cmp_type);
12361       oappend (scratchbuf + intel_syntax);
12362       scratchbuf[0] = '\0';
12363     }
12364 }
12365
12366 static void
12367 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12368           int sizeflag ATTRIBUTE_UNUSED)
12369 {
12370   /* mwait %eax,%ecx  */
12371   if (!intel_syntax)
12372     {
12373       const char **names = (address_mode == mode_64bit
12374                             ? names64 : names32);
12375       strcpy (op_out[0], names[0]);
12376       strcpy (op_out[1], names[1]);
12377       two_source_ops = 1;
12378     }
12379   /* Skip mod/rm byte.  */
12380   MODRM_CHECK;
12381   codep++;
12382 }
12383
12384 static void
12385 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12386             int sizeflag ATTRIBUTE_UNUSED)
12387 {
12388   /* monitor %eax,%ecx,%edx"  */
12389   if (!intel_syntax)
12390     {
12391       const char **op1_names;
12392       const char **names = (address_mode == mode_64bit
12393                             ? names64 : names32);
12394
12395       if (!(prefixes & PREFIX_ADDR))
12396         op1_names = (address_mode == mode_16bit
12397                      ? names16 : names);
12398       else
12399         {
12400           /* Remove "addr16/addr32".  */
12401           addr_prefix = NULL;
12402           op1_names = (address_mode != mode_32bit
12403                        ? names32 : names16);
12404           used_prefixes |= PREFIX_ADDR;
12405         }
12406       strcpy (op_out[0], op1_names[0]);
12407       strcpy (op_out[1], names[1]);
12408       strcpy (op_out[2], names[2]);
12409       two_source_ops = 1;
12410     }
12411   /* Skip mod/rm byte.  */
12412   MODRM_CHECK;
12413   codep++;
12414 }
12415
12416 static void
12417 BadOp (void)
12418 {
12419   /* Throw away prefixes and 1st. opcode byte.  */
12420   codep = insn_codep + 1;
12421   oappend ("(bad)");
12422 }
12423
12424 static void
12425 REP_Fixup (int bytemode, int sizeflag)
12426 {
12427   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12428      lods and stos.  */
12429   if (prefixes & PREFIX_REPZ)
12430     repz_prefix = "rep ";
12431
12432   switch (bytemode)
12433     {
12434     case al_reg:
12435     case eAX_reg:
12436     case indir_dx_reg:
12437       OP_IMREG (bytemode, sizeflag);
12438       break;
12439     case eDI_reg:
12440       OP_ESreg (bytemode, sizeflag);
12441       break;
12442     case eSI_reg:
12443       OP_DSreg (bytemode, sizeflag);
12444       break;
12445     default:
12446       abort ();
12447       break;
12448     }
12449 }
12450
12451 static void
12452 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12453 {
12454   USED_REX (REX_W);
12455   if (rex & REX_W)
12456     {
12457       /* Change cmpxchg8b to cmpxchg16b.  */
12458       char *p = mnemonicendp - 2;
12459       mnemonicendp = stpcpy (p, "16b");
12460       bytemode = o_mode;
12461     }
12462   OP_M (bytemode, sizeflag);
12463 }
12464
12465 static void
12466 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
12467 {
12468   if (need_vex)
12469     {
12470       switch (vex.length)
12471         {
12472         case 128:
12473           sprintf (scratchbuf, "%%xmm%d", reg);
12474           break;
12475         case 256:
12476           sprintf (scratchbuf, "%%ymm%d", reg);
12477           break;
12478         default:
12479           abort ();
12480         }
12481     }
12482   else
12483     sprintf (scratchbuf, "%%xmm%d", reg);
12484   oappend (scratchbuf + intel_syntax);
12485 }
12486
12487 static void
12488 CRC32_Fixup (int bytemode, int sizeflag)
12489 {
12490   /* Add proper suffix to "crc32".  */
12491   char *p = mnemonicendp;
12492
12493   switch (bytemode)
12494     {
12495     case b_mode:
12496       if (intel_syntax)
12497         goto skip;
12498
12499       *p++ = 'b';
12500       break;
12501     case v_mode:
12502       if (intel_syntax)
12503         goto skip;
12504
12505       USED_REX (REX_W);
12506       if (rex & REX_W)
12507         *p++ = 'q';
12508       else if (sizeflag & DFLAG)
12509         *p++ = 'l';
12510       else
12511         *p++ = 'w';
12512       used_prefixes |= (prefixes & PREFIX_DATA);
12513       break;
12514     default:
12515       oappend (INTERNAL_DISASSEMBLER_ERROR);
12516       break;
12517     }
12518   mnemonicendp = p;
12519   *p = '\0';
12520
12521 skip:
12522   if (modrm.mod == 3)
12523     {
12524       int add;
12525
12526       /* Skip mod/rm byte.  */
12527       MODRM_CHECK;
12528       codep++;
12529
12530       USED_REX (REX_B);
12531       add = (rex & REX_B) ? 8 : 0;
12532       if (bytemode == b_mode)
12533         {
12534           USED_REX (0);
12535           if (rex)
12536             oappend (names8rex[modrm.rm + add]);
12537           else
12538             oappend (names8[modrm.rm + add]);
12539         }
12540       else
12541         {
12542           USED_REX (REX_W);
12543           if (rex & REX_W)
12544             oappend (names64[modrm.rm + add]);
12545           else if ((prefixes & PREFIX_DATA))
12546             oappend (names16[modrm.rm + add]);
12547           else
12548             oappend (names32[modrm.rm + add]);
12549         }
12550     }
12551   else
12552     OP_E (bytemode, sizeflag);
12553 }
12554
12555 /* Display the destination register operand for instructions with
12556    VEX. */
12557
12558 static void
12559 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12560 {
12561   if (!need_vex)
12562     abort ();
12563
12564   if (!need_vex_reg)
12565     return;
12566
12567   switch (vex.length)
12568     {
12569     case 128:
12570       switch (bytemode)
12571         {
12572         case vex_mode:
12573         case vex128_mode:
12574           break;
12575         default:
12576           abort ();
12577           return;
12578         }
12579
12580       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
12581       break;
12582     case 256:
12583       switch (bytemode)
12584         {
12585         case vex_mode:
12586         case vex256_mode:
12587           break;
12588         default:
12589           abort ();
12590           return;
12591         }
12592
12593       sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
12594       break;
12595     default:
12596       abort ();
12597       break;
12598     }
12599   oappend (scratchbuf + intel_syntax);
12600 }
12601
12602 /* Get the VEX immediate byte without moving codep.  */
12603
12604 static unsigned char
12605 get_vex_imm8 (int sizeflag)
12606 {
12607   int bytes_before_imm = 0;
12608
12609   /* Skip mod/rm byte.   */
12610   MODRM_CHECK;
12611   codep++;
12612
12613   if (modrm.mod != 3)
12614     {
12615       /* There are SIB/displacement bytes.  */
12616       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12617         {
12618           /* 32/64 bit address mode */
12619           int base = modrm.rm;
12620
12621           /* Check SIB byte.  */
12622           if (base == 4)
12623             {
12624               FETCH_DATA (the_info, codep + 1);
12625               base = *codep & 7;
12626               bytes_before_imm++;
12627             }
12628
12629           switch (modrm.mod)
12630             {
12631             case 0:
12632               /* When modrm.rm == 5 or modrm.rm == 4 and base in
12633                  SIB == 5, there is a 4 byte displacement.  */
12634               if (base != 5)
12635                 /* No displacement. */
12636                 break;
12637             case 2:
12638               /* 4 byte displacement.  */
12639               bytes_before_imm += 4;
12640               break;
12641             case 1:
12642               /* 1 byte displacement.  */
12643               bytes_before_imm++;
12644               break;
12645             }
12646         }
12647       else
12648         { /* 16 bit address mode */
12649           switch (modrm.mod)
12650             {
12651             case 0:
12652               /* When modrm.rm == 6, there is a 2 byte displacement.  */
12653               if (modrm.rm != 6)
12654                 /* No displacement. */
12655                 break;
12656             case 2:
12657               /* 2 byte displacement.  */
12658               bytes_before_imm += 2;
12659               break;
12660             case 1:
12661               /* 1 byte displacement.  */
12662               bytes_before_imm++;
12663               break;
12664             }
12665         }
12666     }
12667
12668   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
12669   return codep [bytes_before_imm];
12670 }
12671
12672 static void
12673 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
12674 {
12675   if (reg == -1 && modrm.mod != 3)
12676     {
12677       OP_E_memory (bytemode, sizeflag);
12678       return;
12679     }
12680   else
12681     {
12682       if (reg == -1)
12683         {
12684           reg = modrm.rm;
12685           USED_REX (REX_B);
12686           if (rex & REX_B)
12687             reg += 8;
12688         }
12689       else if (reg > 7 && address_mode != mode_64bit)
12690         BadOp ();
12691     }
12692
12693   switch (vex.length)
12694     {
12695     case 128:
12696       sprintf (scratchbuf, "%%xmm%d", reg);
12697       break;
12698     case 256:
12699       sprintf (scratchbuf, "%%ymm%d", reg);
12700       break;
12701     default:
12702       abort ();
12703     }
12704   oappend (scratchbuf + intel_syntax);
12705 }
12706
12707 static void
12708 OP_EX_VexW (int bytemode, int sizeflag)
12709 {
12710   int reg = -1;
12711
12712   if (!vex_w_done)
12713     {
12714       vex_w_done = 1;
12715       if (vex.w)
12716         reg = vex.register_specifier;
12717     }
12718   else
12719     {
12720       if (!vex.w)
12721         reg = vex.register_specifier;
12722     }
12723
12724   OP_EX_VexReg (bytemode, sizeflag, reg);
12725 }
12726
12727 static void
12728 OP_VEX_FMA (int bytemode, int sizeflag)
12729 {
12730   int reg = get_vex_imm8 (sizeflag) >> 4;
12731
12732   if (reg > 7 && address_mode != mode_64bit)
12733     BadOp ();
12734
12735   switch (vex.length)
12736     {
12737     case 128:
12738       switch (bytemode)
12739         {
12740         case vex_mode:
12741         case vex128_mode:
12742           break;
12743         default:
12744           abort ();
12745           return;
12746         }
12747
12748       sprintf (scratchbuf, "%%xmm%d", reg);
12749       break;
12750     case 256:
12751       switch (bytemode)
12752         {
12753         case vex_mode:
12754           break;
12755         default:
12756           abort ();
12757           return;
12758         }
12759
12760       sprintf (scratchbuf, "%%ymm%d", reg);
12761       break;
12762     default:
12763       abort ();
12764     }
12765   oappend (scratchbuf + intel_syntax);
12766 }
12767
12768 static void
12769 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
12770              int sizeflag ATTRIBUTE_UNUSED)
12771 {
12772   /* Skip the immediate byte and check for invalid bits.  */
12773   FETCH_DATA (the_info, codep + 1);
12774   if (*codep++ & 0xf)
12775     BadOp ();
12776 }
12777
12778 static void
12779 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12780 {
12781   int reg;
12782   FETCH_DATA (the_info, codep + 1);
12783   reg = *codep++;
12784
12785   if (bytemode != x_mode)
12786     abort ();
12787
12788   if (reg & 0xf)
12789       BadOp ();
12790
12791   reg >>= 4;
12792   if (reg > 7 && address_mode != mode_64bit)
12793     BadOp ();
12794
12795   switch (vex.length)
12796     {
12797     case 128:
12798       sprintf (scratchbuf, "%%xmm%d", reg);
12799       break;
12800     case 256:
12801       sprintf (scratchbuf, "%%ymm%d", reg);
12802       break;
12803     default:
12804       abort ();
12805     }
12806   oappend (scratchbuf + intel_syntax);
12807 }
12808
12809 static void
12810 OP_XMM_VexW (int bytemode, int sizeflag)
12811 {
12812   /* Turn off the REX.W bit since it is used for swapping operands
12813      now.  */
12814   rex &= ~REX_W;
12815   OP_XMM (bytemode, sizeflag);
12816 }
12817
12818 static void
12819 OP_EX_Vex (int bytemode, int sizeflag)
12820 {
12821   if (modrm.mod != 3)
12822     {
12823       if (vex.register_specifier != 0)
12824         BadOp ();
12825       need_vex_reg = 0;
12826     }
12827   OP_EX (bytemode, sizeflag);
12828 }
12829
12830 static void
12831 OP_XMM_Vex (int bytemode, int sizeflag)
12832 {
12833   if (modrm.mod != 3)
12834     {
12835       if (vex.register_specifier != 0)
12836         BadOp ();
12837       need_vex_reg = 0;
12838     }
12839   OP_XMM (bytemode, sizeflag);
12840 }
12841
12842 static void
12843 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12844 {
12845   switch (vex.length)
12846     {
12847     case 128:
12848       mnemonicendp = stpcpy (obuf, "vzeroupper");
12849       break;
12850     case 256:
12851       mnemonicendp = stpcpy (obuf, "vzeroall");
12852       break;
12853     default:
12854       abort ();
12855     }
12856 }
12857
12858 static struct op vex_cmp_op[] =
12859 {
12860   { STRING_COMMA_LEN ("eq") },
12861   { STRING_COMMA_LEN ("lt") },
12862   { STRING_COMMA_LEN ("le") },
12863   { STRING_COMMA_LEN ("unord") },
12864   { STRING_COMMA_LEN ("neq") },
12865   { STRING_COMMA_LEN ("nlt") },
12866   { STRING_COMMA_LEN ("nle") },
12867   { STRING_COMMA_LEN ("ord") },
12868   { STRING_COMMA_LEN ("eq_uq") },
12869   { STRING_COMMA_LEN ("nge") },
12870   { STRING_COMMA_LEN ("ngt") },
12871   { STRING_COMMA_LEN ("false") },
12872   { STRING_COMMA_LEN ("neq_oq") },
12873   { STRING_COMMA_LEN ("ge") },
12874   { STRING_COMMA_LEN ("gt") },
12875   { STRING_COMMA_LEN ("true") },
12876   { STRING_COMMA_LEN ("eq_os") },
12877   { STRING_COMMA_LEN ("lt_oq") },
12878   { STRING_COMMA_LEN ("le_oq") },
12879   { STRING_COMMA_LEN ("unord_s") },
12880   { STRING_COMMA_LEN ("neq_us") },
12881   { STRING_COMMA_LEN ("nlt_uq") },
12882   { STRING_COMMA_LEN ("nle_uq") },
12883   { STRING_COMMA_LEN ("ord_s") },
12884   { STRING_COMMA_LEN ("eq_us") },
12885   { STRING_COMMA_LEN ("nge_uq") },
12886   { STRING_COMMA_LEN ("ngt_uq") },
12887   { STRING_COMMA_LEN ("false_os") },
12888   { STRING_COMMA_LEN ("neq_os") },
12889   { STRING_COMMA_LEN ("ge_oq") },
12890   { STRING_COMMA_LEN ("gt_oq") },
12891   { STRING_COMMA_LEN ("true_us") },
12892 };
12893
12894 static void
12895 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12896 {
12897   unsigned int cmp_type;
12898
12899   FETCH_DATA (the_info, codep + 1);
12900   cmp_type = *codep++ & 0xff;
12901   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
12902     {
12903       char suffix [3];
12904       char *p = mnemonicendp - 2;
12905       suffix[0] = p[0];
12906       suffix[1] = p[1];
12907       suffix[2] = '\0';
12908       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
12909       mnemonicendp += vex_cmp_op[cmp_type].len;
12910     }
12911   else
12912     {
12913       /* We have a reserved extension byte.  Output it directly.  */
12914       scratchbuf[0] = '$';
12915       print_operand_value (scratchbuf + 1, 1, cmp_type);
12916       oappend (scratchbuf + intel_syntax);
12917       scratchbuf[0] = '\0';
12918     }
12919 }
12920
12921 static const struct op pclmul_op[] =
12922 {
12923   { STRING_COMMA_LEN ("lql") },
12924   { STRING_COMMA_LEN ("hql") },
12925   { STRING_COMMA_LEN ("lqh") },
12926   { STRING_COMMA_LEN ("hqh") }
12927 };
12928
12929 static void
12930 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
12931               int sizeflag ATTRIBUTE_UNUSED)
12932 {
12933   unsigned int pclmul_type;
12934
12935   FETCH_DATA (the_info, codep + 1);
12936   pclmul_type = *codep++ & 0xff;
12937   switch (pclmul_type)
12938     {
12939     case 0x10:
12940       pclmul_type = 2;
12941       break;
12942     case 0x11:
12943       pclmul_type = 3;
12944       break;
12945     default:
12946       break;
12947     }
12948   if (pclmul_type < ARRAY_SIZE (pclmul_op))
12949     {
12950       char suffix [4];
12951       char *p = mnemonicendp - 3;
12952       suffix[0] = p[0];
12953       suffix[1] = p[1];
12954       suffix[2] = p[2];
12955       suffix[3] = '\0';
12956       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
12957       mnemonicendp += pclmul_op[pclmul_type].len;
12958     }
12959   else
12960     {
12961       /* We have a reserved extension byte.  Output it directly.  */
12962       scratchbuf[0] = '$';
12963       print_operand_value (scratchbuf + 1, 1, pclmul_type);
12964       oappend (scratchbuf + intel_syntax);
12965       scratchbuf[0] = '\0';
12966     }
12967 }
12968
12969 static void
12970 MOVBE_Fixup (int bytemode, int sizeflag)
12971 {
12972   /* Add proper suffix to "movbe".  */
12973   char *p = mnemonicendp;
12974
12975   switch (bytemode)
12976     {
12977     case v_mode:
12978       if (intel_syntax)
12979         goto skip;
12980
12981       USED_REX (REX_W);
12982       if (sizeflag & SUFFIX_ALWAYS)
12983         {
12984           if (rex & REX_W)
12985             *p++ = 'q';
12986           else if (sizeflag & DFLAG)
12987             *p++ = 'l';
12988           else
12989             *p++ = 'w';
12990         }
12991       used_prefixes |= (prefixes & PREFIX_DATA);
12992       break;
12993     default:
12994       oappend (INTERNAL_DISASSEMBLER_ERROR);
12995       break;
12996     }
12997   mnemonicendp = p;
12998   *p = '\0';
12999
13000 skip:
13001   OP_M (bytemode, sizeflag);
13002 }