opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2015 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 /* Possible values for prefix requirement.  */
 225 #define PREFIX_IGNORED_SHIFT    16
 226 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 227 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 231
 232 /* Opcode prefixes.  */
 233 #define PREFIX_OPCODE           (PREFIX_REPZ \
 234                                  | PREFIX_REPNZ \
 235                                  | PREFIX_DATA)
 236
 237 /* Prefixes ignored.  */
 238 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 239                                  | PREFIX_IGNORED_REPNZ \
 240                                  | PREFIX_IGNORED_DATA)
 241
 242 #define XX { NULL, 0 }
 243 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 244
 245 #define Eb { OP_E, b_mode }
 246 #define Ebnd { OP_E, bnd_mode }
 247 #define EbS { OP_E, b_swap_mode }
 248 #define Ev { OP_E, v_mode }
 249 #define Ev_bnd { OP_E, v_bnd_mode }
 250 #define EvS { OP_E, v_swap_mode }
 251 #define Ed { OP_E, d_mode }
 252 #define Edq { OP_E, dq_mode }
 253 #define Edqw { OP_E, dqw_mode }
 254 #define EdqwS { OP_E, dqw_swap_mode }
 255 #define Edqb { OP_E, dqb_mode }
 256 #define Edb { OP_E, db_mode }
 257 #define Edw { OP_E, dw_mode }
 258 #define Edqd { OP_E, dqd_mode }
 259 #define Eq { OP_E, q_mode }
 260 #define indirEv { OP_indirE, stack_v_mode }
 261 #define indirEp { OP_indirE, f_mode }
 262 #define stackEv { OP_E, stack_v_mode }
 263 #define Em { OP_E, m_mode }
 264 #define Ew { OP_E, w_mode }
 265 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 266 #define Ma { OP_M, a_mode }
 267 #define Mb { OP_M, b_mode }
 268 #define Md { OP_M, d_mode }
 269 #define Mo { OP_M, o_mode }
 270 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 271 #define Mq { OP_M, q_mode }
 272 #define Mx { OP_M, x_mode }
 273 #define Mxmm { OP_M, xmm_mode }
 274 #define Gb { OP_G, b_mode }
 275 #define Gbnd { OP_G, bnd_mode }
 276 #define Gv { OP_G, v_mode }
 277 #define Gd { OP_G, d_mode }
 278 #define Gdq { OP_G, dq_mode }
 279 #define Gm { OP_G, m_mode }
 280 #define Gw { OP_G, w_mode }
 281 #define Rd { OP_R, d_mode }
 282 #define Rdq { OP_R, dq_mode }
 283 #define Rm { OP_R, m_mode }
 284 #define Ib { OP_I, b_mode }
 285 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 286 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 287 #define Iv { OP_I, v_mode }
 288 #define sIv { OP_sI, v_mode }
 289 #define Iq { OP_I, q_mode }
 290 #define Iv64 { OP_I64, v_mode }
 291 #define Iw { OP_I, w_mode }
 292 #define I1 { OP_I, const_1_mode }
 293 #define Jb { OP_J, b_mode }
 294 #define Jv { OP_J, v_mode }
 295 #define Cm { OP_C, m_mode }
 296 #define Dm { OP_D, m_mode }
 297 #define Td { OP_T, d_mode }
 298 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 299
 300 #define RMeAX { OP_REG, eAX_reg }
 301 #define RMeBX { OP_REG, eBX_reg }
 302 #define RMeCX { OP_REG, eCX_reg }
 303 #define RMeDX { OP_REG, eDX_reg }
 304 #define RMeSP { OP_REG, eSP_reg }
 305 #define RMeBP { OP_REG, eBP_reg }
 306 #define RMeSI { OP_REG, eSI_reg }
 307 #define RMeDI { OP_REG, eDI_reg }
 308 #define RMrAX { OP_REG, rAX_reg }
 309 #define RMrBX { OP_REG, rBX_reg }
 310 #define RMrCX { OP_REG, rCX_reg }
 311 #define RMrDX { OP_REG, rDX_reg }
 312 #define RMrSP { OP_REG, rSP_reg }
 313 #define RMrBP { OP_REG, rBP_reg }
 314 #define RMrSI { OP_REG, rSI_reg }
 315 #define RMrDI { OP_REG, rDI_reg }
 316 #define RMAL { OP_REG, al_reg }
 317 #define RMCL { OP_REG, cl_reg }
 318 #define RMDL { OP_REG, dl_reg }
 319 #define RMBL { OP_REG, bl_reg }
 320 #define RMAH { OP_REG, ah_reg }
 321 #define RMCH { OP_REG, ch_reg }
 322 #define RMDH { OP_REG, dh_reg }
 323 #define RMBH { OP_REG, bh_reg }
 324 #define RMAX { OP_REG, ax_reg }
 325 #define RMDX { OP_REG, dx_reg }
 326
 327 #define eAX { OP_IMREG, eAX_reg }
 328 #define eBX { OP_IMREG, eBX_reg }
 329 #define eCX { OP_IMREG, eCX_reg }
 330 #define eDX { OP_IMREG, eDX_reg }
 331 #define eSP { OP_IMREG, eSP_reg }
 332 #define eBP { OP_IMREG, eBP_reg }
 333 #define eSI { OP_IMREG, eSI_reg }
 334 #define eDI { OP_IMREG, eDI_reg }
 335 #define AL { OP_IMREG, al_reg }
 336 #define CL { OP_IMREG, cl_reg }
 337 #define DL { OP_IMREG, dl_reg }
 338 #define BL { OP_IMREG, bl_reg }
 339 #define AH { OP_IMREG, ah_reg }
 340 #define CH { OP_IMREG, ch_reg }
 341 #define DH { OP_IMREG, dh_reg }
 342 #define BH { OP_IMREG, bh_reg }
 343 #define AX { OP_IMREG, ax_reg }
 344 #define DX { OP_IMREG, dx_reg }
 345 #define zAX { OP_IMREG, z_mode_ax_reg }
 346 #define indirDX { OP_IMREG, indir_dx_reg }
 347
 348 #define Sw { OP_SEG, w_mode }
 349 #define Sv { OP_SEG, v_mode }
 350 #define Ap { OP_DIR, 0 }
 351 #define Ob { OP_OFF64, b_mode }
 352 #define Ov { OP_OFF64, v_mode }
 353 #define Xb { OP_DSreg, eSI_reg }
 354 #define Xv { OP_DSreg, eSI_reg }
 355 #define Xz { OP_DSreg, eSI_reg }
 356 #define Yb { OP_ESreg, eDI_reg }
 357 #define Yv { OP_ESreg, eDI_reg }
 358 #define DSBX { OP_DSreg, eBX_reg }
 359
 360 #define es { OP_REG, es_reg }
 361 #define ss { OP_REG, ss_reg }
 362 #define cs { OP_REG, cs_reg }
 363 #define ds { OP_REG, ds_reg }
 364 #define fs { OP_REG, fs_reg }
 365 #define gs { OP_REG, gs_reg }
 366
 367 #define MX { OP_MMX, 0 }
 368 #define XM { OP_XMM, 0 }
 369 #define XMScalar { OP_XMM, scalar_mode }
 370 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 371 #define XMM { OP_XMM, xmm_mode }
 372 #define XMxmmq { OP_XMM, xmmq_mode }
 373 #define EM { OP_EM, v_mode }
 374 #define EMS { OP_EM, v_swap_mode }
 375 #define EMd { OP_EM, d_mode }
 376 #define EMx { OP_EM, x_mode }
 377 #define EXw { OP_EX, w_mode }
 378 #define EXd { OP_EX, d_mode }
 379 #define EXdScalar { OP_EX, d_scalar_mode }
 380 #define EXdS { OP_EX, d_swap_mode }
 381 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 382 #define EXq { OP_EX, q_mode }
 383 #define EXqScalar { OP_EX, q_scalar_mode }
 384 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 385 #define EXqS { OP_EX, q_swap_mode }
 386 #define EXx { OP_EX, x_mode }
 387 #define EXxS { OP_EX, x_swap_mode }
 388 #define EXxmm { OP_EX, xmm_mode }
 389 #define EXymm { OP_EX, ymm_mode }
 390 #define EXxmmq { OP_EX, xmmq_mode }
 391 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 392 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 393 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 394 #define EXxmm_md { OP_EX, xmm_md_mode }
 395 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 396 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 397 #define EXxmmdw { OP_EX, xmmdw_mode }
 398 #define EXxmmqd { OP_EX, xmmqd_mode }
 399 #define EXymmq { OP_EX, ymmq_mode }
 400 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 401 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 402 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 403 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 404 #define MS { OP_MS, v_mode }
 405 #define XS { OP_XS, v_mode }
 406 #define EMCq { OP_EMC, q_mode }
 407 #define MXC { OP_MXC, 0 }
 408 #define OPSUF { OP_3DNowSuffix, 0 }
 409 #define CMP { CMP_Fixup, 0 }
 410 #define XMM0 { XMM_Fixup, 0 }
 411 #define FXSAVE { FXSAVE_Fixup, 0 }
 412 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 413 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 414
 415 #define Vex { OP_VEX, vex_mode }
 416 #define VexScalar { OP_VEX, vex_scalar_mode }
 417 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 418 #define Vex128 { OP_VEX, vex128_mode }
 419 #define Vex256 { OP_VEX, vex256_mode }
 420 #define VexGdq { OP_VEX, dq_mode }
 421 #define VexI4 { VEXI4_Fixup, 0}
 422 #define EXdVex { OP_EX_Vex, d_mode }
 423 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 425 #define EXqVex { OP_EX_Vex, q_mode }
 426 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 427 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 428 #define EXVexW { OP_EX_VexW, x_mode }
 429 #define EXdVexW { OP_EX_VexW, d_mode }
 430 #define EXqVexW { OP_EX_VexW, q_mode }
 431 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 432 #define XMVex { OP_XMM_Vex, 0 }
 433 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 434 #define XMVexW { OP_XMM_VexW, 0 }
 435 #define XMVexI4 { OP_REG_VexI4, x_mode }
 436 #define PCLMUL { PCLMUL_Fixup, 0 }
 437 #define VZERO { VZERO_Fixup, 0 }
 438 #define VCMP { VCMP_Fixup, 0 }
 439 #define VPCMP { VPCMP_Fixup, 0 }
 440
 441 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 442 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 443
 444 #define XMask { OP_Mask, mask_mode }
 445 #define MaskG { OP_G, mask_mode }
 446 #define MaskE { OP_E, mask_mode }
 447 #define MaskBDE { OP_E, mask_bd_mode }
 448 #define MaskR { OP_R, mask_mode }
 449 #define MaskVex { OP_VEX, mask_mode }
 450
 451 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 452 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 453 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 454 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 455
 456 /* Used handle "rep" prefix for string instructions.  */
 457 #define Xbr { REP_Fixup, eSI_reg }
 458 #define Xvr { REP_Fixup, eSI_reg }
 459 #define Ybr { REP_Fixup, eDI_reg }
 460 #define Yvr { REP_Fixup, eDI_reg }
 461 #define Yzr { REP_Fixup, eDI_reg }
 462 #define indirDXr { REP_Fixup, indir_dx_reg }
 463 #define ALr { REP_Fixup, al_reg }
 464 #define eAXr { REP_Fixup, eAX_reg }
 465
 466 /* Used handle HLE prefix for lockable instructions.  */
 467 #define Ebh1 { HLE_Fixup1, b_mode }
 468 #define Evh1 { HLE_Fixup1, v_mode }
 469 #define Ebh2 { HLE_Fixup2, b_mode }
 470 #define Evh2 { HLE_Fixup2, v_mode }
 471 #define Ebh3 { HLE_Fixup3, b_mode }
 472 #define Evh3 { HLE_Fixup3, v_mode }
 473
 474 #define BND { BND_Fixup, 0 }
 475
 476 #define cond_jump_flag { NULL, cond_jump_mode }
 477 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 478
 479 /* bits in sizeflag */
 480 #define SUFFIX_ALWAYS 4
 481 #define AFLAG 2
 482 #define DFLAG 1
 483
 484 enum
 485 {
 486   /* byte operand */
 487   b_mode = 1,
 488   /* byte operand with operand swapped */
 489   b_swap_mode,
 490   /* byte operand, sign extend like 'T' suffix */
 491   b_T_mode,
 492   /* operand size depends on prefixes */
 493   v_mode,
 494   /* operand size depends on prefixes with operand swapped */
 495   v_swap_mode,
 496   /* word operand */
 497   w_mode,
 498   /* double word operand  */
 499   d_mode,
 500   /* double word operand with operand swapped */
 501   d_swap_mode,
 502   /* quad word operand */
 503   q_mode,
 504   /* quad word operand with operand swapped */
 505   q_swap_mode,
 506   /* ten-byte operand */
 507   t_mode,
 508   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 509      broadcast enabled.  */
 510   x_mode,
 511   /* Similar to x_mode, but with different EVEX mem shifts.  */
 512   evex_x_gscat_mode,
 513   /* Similar to x_mode, but with disabled broadcast.  */
 514   evex_x_nobcst_mode,
 515   /* Similar to x_mode, but with operands swapped and disabled broadcast
 516      in EVEX.  */
 517   x_swap_mode,
 518   /* 16-byte XMM operand */
 519   xmm_mode,
 520   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 521      memory operand (depending on vector length).  Broadcast isn't
 522      allowed.  */
 523   xmmq_mode,
 524   /* Same as xmmq_mode, but broadcast is allowed.  */
 525   evex_half_bcst_xmmq_mode,
 526   /* XMM register or byte memory operand */
 527   xmm_mb_mode,
 528   /* XMM register or word memory operand */
 529   xmm_mw_mode,
 530   /* XMM register or double word memory operand */
 531   xmm_md_mode,
 532   /* XMM register or quad word memory operand */
 533   xmm_mq_mode,
 534   /* XMM register or double/quad word memory operand, depending on
 535      VEX.W.  */
 536   xmm_mdq_mode,
 537   /* 16-byte XMM, word, double word or quad word operand.  */
 538   xmmdw_mode,
 539   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 540   xmmqd_mode,
 541   /* 32-byte YMM operand */
 542   ymm_mode,
 543   /* quad word, ymmword or zmmword memory operand.  */
 544   ymmq_mode,
 545   /* 32-byte YMM or 16-byte word operand */
 546   ymmxmm_mode,
 547   /* d_mode in 32bit, q_mode in 64bit mode.  */
 548   m_mode,
 549   /* pair of v_mode operands */
 550   a_mode,
 551   cond_jump_mode,
 552   loop_jcxz_mode,
 553   v_bnd_mode,
 554   /* operand size depends on REX prefixes.  */
 555   dq_mode,
 556   /* registers like dq_mode, memory like w_mode.  */
 557   dqw_mode,
 558   dqw_swap_mode,
 559   bnd_mode,
 560   /* 4- or 6-byte pointer operand */
 561   f_mode,
 562   const_1_mode,
 563   /* v_mode for stack-related opcodes.  */
 564   stack_v_mode,
 565   /* non-quad operand size depends on prefixes */
 566   z_mode,
 567   /* 16-byte operand */
 568   o_mode,
 569   /* registers like dq_mode, memory like b_mode.  */
 570   dqb_mode,
 571   /* registers like d_mode, memory like b_mode.  */
 572   db_mode,
 573   /* registers like d_mode, memory like w_mode.  */
 574   dw_mode,
 575   /* registers like dq_mode, memory like d_mode.  */
 576   dqd_mode,
 577   /* normal vex mode */
 578   vex_mode,
 579   /* 128bit vex mode */
 580   vex128_mode,
 581   /* 256bit vex mode */
 582   vex256_mode,
 583   /* operand size depends on the VEX.W bit.  */
 584   vex_w_dq_mode,
 585
 586   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 587   vex_vsib_d_w_dq_mode,
 588   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 589   vex_vsib_d_w_d_mode,
 590   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 591   vex_vsib_q_w_dq_mode,
 592   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 593   vex_vsib_q_w_d_mode,
 594
 595   /* scalar, ignore vector length.  */
 596   scalar_mode,
 597   /* like d_mode, ignore vector length.  */
 598   d_scalar_mode,
 599   /* like d_swap_mode, ignore vector length.  */
 600   d_scalar_swap_mode,
 601   /* like q_mode, ignore vector length.  */
 602   q_scalar_mode,
 603   /* like q_swap_mode, ignore vector length.  */
 604   q_scalar_swap_mode,
 605   /* like vex_mode, ignore vector length.  */
 606   vex_scalar_mode,
 607   /* like vex_w_dq_mode, ignore vector length.  */
 608   vex_scalar_w_dq_mode,
 609
 610   /* Static rounding.  */
 611   evex_rounding_mode,
 612   /* Supress all exceptions.  */
 613   evex_sae_mode,
 614
 615   /* Mask register operand.  */
 616   mask_mode,
 617   /* Mask register operand.  */
 618   mask_bd_mode,
 619
 620   es_reg,
 621   cs_reg,
 622   ss_reg,
 623   ds_reg,
 624   fs_reg,
 625   gs_reg,
 626
 627   eAX_reg,
 628   eCX_reg,
 629   eDX_reg,
 630   eBX_reg,
 631   eSP_reg,
 632   eBP_reg,
 633   eSI_reg,
 634   eDI_reg,
 635
 636   al_reg,
 637   cl_reg,
 638   dl_reg,
 639   bl_reg,
 640   ah_reg,
 641   ch_reg,
 642   dh_reg,
 643   bh_reg,
 644
 645   ax_reg,
 646   cx_reg,
 647   dx_reg,
 648   bx_reg,
 649   sp_reg,
 650   bp_reg,
 651   si_reg,
 652   di_reg,
 653
 654   rAX_reg,
 655   rCX_reg,
 656   rDX_reg,
 657   rBX_reg,
 658   rSP_reg,
 659   rBP_reg,
 660   rSI_reg,
 661   rDI_reg,
 662
 663   z_mode_ax_reg,
 664   indir_dx_reg
 665 };
 666
 667 enum
 668 {
 669   FLOATCODE = 1,
 670   USE_REG_TABLE,
 671   USE_MOD_TABLE,
 672   USE_RM_TABLE,
 673   USE_PREFIX_TABLE,
 674   USE_X86_64_TABLE,
 675   USE_3BYTE_TABLE,
 676   USE_XOP_8F_TABLE,
 677   USE_VEX_C4_TABLE,
 678   USE_VEX_C5_TABLE,
 679   USE_VEX_LEN_TABLE,
 680   USE_VEX_W_TABLE,
 681   USE_EVEX_TABLE
 682 };
 683
 684 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 685
 686 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 687 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 688 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 689 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 690 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 691 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 692 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 693 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 694 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 695 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 696 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 697 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 698 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 699 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 700 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 701
 702 enum
 703 {
 704   REG_80 = 0,
 705   REG_81,
 706   REG_82,
 707   REG_8F,
 708   REG_C0,
 709   REG_C1,
 710   REG_C6,
 711   REG_C7,
 712   REG_D0,
 713   REG_D1,
 714   REG_D2,
 715   REG_D3,
 716   REG_F6,
 717   REG_F7,
 718   REG_FE,
 719   REG_FF,
 720   REG_0F00,
 721   REG_0F01,
 722   REG_0F0D,
 723   REG_0F18,
 724   REG_0F71,
 725   REG_0F72,
 726   REG_0F73,
 727   REG_0FA6,
 728   REG_0FA7,
 729   REG_0FAE,
 730   REG_0FBA,
 731   REG_0FC7,
 732   REG_VEX_0F71,
 733   REG_VEX_0F72,
 734   REG_VEX_0F73,
 735   REG_VEX_0FAE,
 736   REG_VEX_0F38F3,
 737   REG_XOP_LWPCB,
 738   REG_XOP_LWP,
 739   REG_XOP_TBM_01,
 740   REG_XOP_TBM_02,
 741
 742   REG_EVEX_0F71,
 743   REG_EVEX_0F72,
 744   REG_EVEX_0F73,
 745   REG_EVEX_0F38C6,
 746   REG_EVEX_0F38C7
 747 };
 748
 749 enum
 750 {
 751   MOD_8D = 0,
 752   MOD_C6_REG_7,
 753   MOD_C7_REG_7,
 754   MOD_FF_REG_3,
 755   MOD_FF_REG_5,
 756   MOD_0F01_REG_0,
 757   MOD_0F01_REG_1,
 758   MOD_0F01_REG_2,
 759   MOD_0F01_REG_3,
 760   MOD_0F01_REG_7,
 761   MOD_0F12_PREFIX_0,
 762   MOD_0F13,
 763   MOD_0F16_PREFIX_0,
 764   MOD_0F17,
 765   MOD_0F18_REG_0,
 766   MOD_0F18_REG_1,
 767   MOD_0F18_REG_2,
 768   MOD_0F18_REG_3,
 769   MOD_0F18_REG_4,
 770   MOD_0F18_REG_5,
 771   MOD_0F18_REG_6,
 772   MOD_0F18_REG_7,
 773   MOD_0F1A_PREFIX_0,
 774   MOD_0F1B_PREFIX_0,
 775   MOD_0F1B_PREFIX_1,
 776   MOD_0F24,
 777   MOD_0F26,
 778   MOD_0F2B_PREFIX_0,
 779   MOD_0F2B_PREFIX_1,
 780   MOD_0F2B_PREFIX_2,
 781   MOD_0F2B_PREFIX_3,
 782   MOD_0F51,
 783   MOD_0F71_REG_2,
 784   MOD_0F71_REG_4,
 785   MOD_0F71_REG_6,
 786   MOD_0F72_REG_2,
 787   MOD_0F72_REG_4,
 788   MOD_0F72_REG_6,
 789   MOD_0F73_REG_2,
 790   MOD_0F73_REG_3,
 791   MOD_0F73_REG_6,
 792   MOD_0F73_REG_7,
 793   MOD_0FAE_REG_0,
 794   MOD_0FAE_REG_1,
 795   MOD_0FAE_REG_2,
 796   MOD_0FAE_REG_3,
 797   MOD_0FAE_REG_4,
 798   MOD_0FAE_REG_5,
 799   MOD_0FAE_REG_6,
 800   MOD_0FAE_REG_7,
 801   MOD_0FB2,
 802   MOD_0FB4,
 803   MOD_0FB5,
 804   MOD_0FC7_REG_3,
 805   MOD_0FC7_REG_4,
 806   MOD_0FC7_REG_5,
 807   MOD_0FC7_REG_6,
 808   MOD_0FC7_REG_7,
 809   MOD_0FD7,
 810   MOD_0FE7_PREFIX_2,
 811   MOD_0FF0_PREFIX_3,
 812   MOD_0F382A_PREFIX_2,
 813   MOD_62_32BIT,
 814   MOD_C4_32BIT,
 815   MOD_C5_32BIT,
 816   MOD_VEX_0F12_PREFIX_0,
 817   MOD_VEX_0F13,
 818   MOD_VEX_0F16_PREFIX_0,
 819   MOD_VEX_0F17,
 820   MOD_VEX_0F2B,
 821   MOD_VEX_0F50,
 822   MOD_VEX_0F71_REG_2,
 823   MOD_VEX_0F71_REG_4,
 824   MOD_VEX_0F71_REG_6,
 825   MOD_VEX_0F72_REG_2,
 826   MOD_VEX_0F72_REG_4,
 827   MOD_VEX_0F72_REG_6,
 828   MOD_VEX_0F73_REG_2,
 829   MOD_VEX_0F73_REG_3,
 830   MOD_VEX_0F73_REG_6,
 831   MOD_VEX_0F73_REG_7,
 832   MOD_VEX_0FAE_REG_2,
 833   MOD_VEX_0FAE_REG_3,
 834   MOD_VEX_0FD7_PREFIX_2,
 835   MOD_VEX_0FE7_PREFIX_2,
 836   MOD_VEX_0FF0_PREFIX_3,
 837   MOD_VEX_0F381A_PREFIX_2,
 838   MOD_VEX_0F382A_PREFIX_2,
 839   MOD_VEX_0F382C_PREFIX_2,
 840   MOD_VEX_0F382D_PREFIX_2,
 841   MOD_VEX_0F382E_PREFIX_2,
 842   MOD_VEX_0F382F_PREFIX_2,
 843   MOD_VEX_0F385A_PREFIX_2,
 844   MOD_VEX_0F388C_PREFIX_2,
 845   MOD_VEX_0F388E_PREFIX_2,
 846
 847   MOD_EVEX_0F10_PREFIX_1,
 848   MOD_EVEX_0F10_PREFIX_3,
 849   MOD_EVEX_0F11_PREFIX_1,
 850   MOD_EVEX_0F11_PREFIX_3,
 851   MOD_EVEX_0F12_PREFIX_0,
 852   MOD_EVEX_0F16_PREFIX_0,
 853   MOD_EVEX_0F38C6_REG_1,
 854   MOD_EVEX_0F38C6_REG_2,
 855   MOD_EVEX_0F38C6_REG_5,
 856   MOD_EVEX_0F38C6_REG_6,
 857   MOD_EVEX_0F38C7_REG_1,
 858   MOD_EVEX_0F38C7_REG_2,
 859   MOD_EVEX_0F38C7_REG_5,
 860   MOD_EVEX_0F38C7_REG_6
 861 };
 862
 863 enum
 864 {
 865   RM_C6_REG_7 = 0,
 866   RM_C7_REG_7,
 867   RM_0F01_REG_0,
 868   RM_0F01_REG_1,
 869   RM_0F01_REG_2,
 870   RM_0F01_REG_3,
 871   RM_0F01_REG_7,
 872   RM_0FAE_REG_5,
 873   RM_0FAE_REG_6,
 874   RM_0FAE_REG_7
 875 };
 876
 877 enum
 878 {
 879   PREFIX_90 = 0,
 880   PREFIX_0F10,
 881   PREFIX_0F11,
 882   PREFIX_0F12,
 883   PREFIX_0F16,
 884   PREFIX_0F1A,
 885   PREFIX_0F1B,
 886   PREFIX_0F2A,
 887   PREFIX_0F2B,
 888   PREFIX_0F2C,
 889   PREFIX_0F2D,
 890   PREFIX_0F2E,
 891   PREFIX_0F2F,
 892   PREFIX_0F51,
 893   PREFIX_0F52,
 894   PREFIX_0F53,
 895   PREFIX_0F58,
 896   PREFIX_0F59,
 897   PREFIX_0F5A,
 898   PREFIX_0F5B,
 899   PREFIX_0F5C,
 900   PREFIX_0F5D,
 901   PREFIX_0F5E,
 902   PREFIX_0F5F,
 903   PREFIX_0F60,
 904   PREFIX_0F61,
 905   PREFIX_0F62,
 906   PREFIX_0F6C,
 907   PREFIX_0F6D,
 908   PREFIX_0F6F,
 909   PREFIX_0F70,
 910   PREFIX_0F73_REG_3,
 911   PREFIX_0F73_REG_7,
 912   PREFIX_0F78,
 913   PREFIX_0F79,
 914   PREFIX_0F7C,
 915   PREFIX_0F7D,
 916   PREFIX_0F7E,
 917   PREFIX_0F7F,
 918   PREFIX_0FAE_REG_0,
 919   PREFIX_0FAE_REG_1,
 920   PREFIX_0FAE_REG_2,
 921   PREFIX_0FAE_REG_3,
 922   PREFIX_0FAE_REG_6,
 923   PREFIX_0FAE_REG_7,
 924   PREFIX_RM_0_0FAE_REG_7,
 925   PREFIX_0FB8,
 926   PREFIX_0FBC,
 927   PREFIX_0FBD,
 928   PREFIX_0FC2,
 929   PREFIX_0FC3,
 930   PREFIX_MOD_0_0FC7_REG_6,
 931   PREFIX_MOD_3_0FC7_REG_6,
 932   PREFIX_MOD_3_0FC7_REG_7,
 933   PREFIX_0FD0,
 934   PREFIX_0FD6,
 935   PREFIX_0FE6,
 936   PREFIX_0FE7,
 937   PREFIX_0FF0,
 938   PREFIX_0FF7,
 939   PREFIX_0F3810,
 940   PREFIX_0F3814,
 941   PREFIX_0F3815,
 942   PREFIX_0F3817,
 943   PREFIX_0F3820,
 944   PREFIX_0F3821,
 945   PREFIX_0F3822,
 946   PREFIX_0F3823,
 947   PREFIX_0F3824,
 948   PREFIX_0F3825,
 949   PREFIX_0F3828,
 950   PREFIX_0F3829,
 951   PREFIX_0F382A,
 952   PREFIX_0F382B,
 953   PREFIX_0F3830,
 954   PREFIX_0F3831,
 955   PREFIX_0F3832,
 956   PREFIX_0F3833,
 957   PREFIX_0F3834,
 958   PREFIX_0F3835,
 959   PREFIX_0F3837,
 960   PREFIX_0F3838,
 961   PREFIX_0F3839,
 962   PREFIX_0F383A,
 963   PREFIX_0F383B,
 964   PREFIX_0F383C,
 965   PREFIX_0F383D,
 966   PREFIX_0F383E,
 967   PREFIX_0F383F,
 968   PREFIX_0F3840,
 969   PREFIX_0F3841,
 970   PREFIX_0F3880,
 971   PREFIX_0F3881,
 972   PREFIX_0F3882,
 973   PREFIX_0F38C8,
 974   PREFIX_0F38C9,
 975   PREFIX_0F38CA,
 976   PREFIX_0F38CB,
 977   PREFIX_0F38CC,
 978   PREFIX_0F38CD,
 979   PREFIX_0F38DB,
 980   PREFIX_0F38DC,
 981   PREFIX_0F38DD,
 982   PREFIX_0F38DE,
 983   PREFIX_0F38DF,
 984   PREFIX_0F38F0,
 985   PREFIX_0F38F1,
 986   PREFIX_0F38F6,
 987   PREFIX_0F3A08,
 988   PREFIX_0F3A09,
 989   PREFIX_0F3A0A,
 990   PREFIX_0F3A0B,
 991   PREFIX_0F3A0C,
 992   PREFIX_0F3A0D,
 993   PREFIX_0F3A0E,
 994   PREFIX_0F3A14,
 995   PREFIX_0F3A15,
 996   PREFIX_0F3A16,
 997   PREFIX_0F3A17,
 998   PREFIX_0F3A20,
 999   PREFIX_0F3A21,
1000   PREFIX_0F3A22,
1001   PREFIX_0F3A40,
1002   PREFIX_0F3A41,
1003   PREFIX_0F3A42,
1004   PREFIX_0F3A44,
1005   PREFIX_0F3A60,
1006   PREFIX_0F3A61,
1007   PREFIX_0F3A62,
1008   PREFIX_0F3A63,
1009   PREFIX_0F3ACC,
1010   PREFIX_0F3ADF,
1011   PREFIX_VEX_0F10,
1012   PREFIX_VEX_0F11,
1013   PREFIX_VEX_0F12,
1014   PREFIX_VEX_0F16,
1015   PREFIX_VEX_0F2A,
1016   PREFIX_VEX_0F2C,
1017   PREFIX_VEX_0F2D,
1018   PREFIX_VEX_0F2E,
1019   PREFIX_VEX_0F2F,
1020   PREFIX_VEX_0F41,
1021   PREFIX_VEX_0F42,
1022   PREFIX_VEX_0F44,
1023   PREFIX_VEX_0F45,
1024   PREFIX_VEX_0F46,
1025   PREFIX_VEX_0F47,
1026   PREFIX_VEX_0F4A,
1027   PREFIX_VEX_0F4B,
1028   PREFIX_VEX_0F51,
1029   PREFIX_VEX_0F52,
1030   PREFIX_VEX_0F53,
1031   PREFIX_VEX_0F58,
1032   PREFIX_VEX_0F59,
1033   PREFIX_VEX_0F5A,
1034   PREFIX_VEX_0F5B,
1035   PREFIX_VEX_0F5C,
1036   PREFIX_VEX_0F5D,
1037   PREFIX_VEX_0F5E,
1038   PREFIX_VEX_0F5F,
1039   PREFIX_VEX_0F60,
1040   PREFIX_VEX_0F61,
1041   PREFIX_VEX_0F62,
1042   PREFIX_VEX_0F63,
1043   PREFIX_VEX_0F64,
1044   PREFIX_VEX_0F65,
1045   PREFIX_VEX_0F66,
1046   PREFIX_VEX_0F67,
1047   PREFIX_VEX_0F68,
1048   PREFIX_VEX_0F69,
1049   PREFIX_VEX_0F6A,
1050   PREFIX_VEX_0F6B,
1051   PREFIX_VEX_0F6C,
1052   PREFIX_VEX_0F6D,
1053   PREFIX_VEX_0F6E,
1054   PREFIX_VEX_0F6F,
1055   PREFIX_VEX_0F70,
1056   PREFIX_VEX_0F71_REG_2,
1057   PREFIX_VEX_0F71_REG_4,
1058   PREFIX_VEX_0F71_REG_6,
1059   PREFIX_VEX_0F72_REG_2,
1060   PREFIX_VEX_0F72_REG_4,
1061   PREFIX_VEX_0F72_REG_6,
1062   PREFIX_VEX_0F73_REG_2,
1063   PREFIX_VEX_0F73_REG_3,
1064   PREFIX_VEX_0F73_REG_6,
1065   PREFIX_VEX_0F73_REG_7,
1066   PREFIX_VEX_0F74,
1067   PREFIX_VEX_0F75,
1068   PREFIX_VEX_0F76,
1069   PREFIX_VEX_0F77,
1070   PREFIX_VEX_0F7C,
1071   PREFIX_VEX_0F7D,
1072   PREFIX_VEX_0F7E,
1073   PREFIX_VEX_0F7F,
1074   PREFIX_VEX_0F90,
1075   PREFIX_VEX_0F91,
1076   PREFIX_VEX_0F92,
1077   PREFIX_VEX_0F93,
1078   PREFIX_VEX_0F98,
1079   PREFIX_VEX_0F99,
1080   PREFIX_VEX_0FC2,
1081   PREFIX_VEX_0FC4,
1082   PREFIX_VEX_0FC5,
1083   PREFIX_VEX_0FD0,
1084   PREFIX_VEX_0FD1,
1085   PREFIX_VEX_0FD2,
1086   PREFIX_VEX_0FD3,
1087   PREFIX_VEX_0FD4,
1088   PREFIX_VEX_0FD5,
1089   PREFIX_VEX_0FD6,
1090   PREFIX_VEX_0FD7,
1091   PREFIX_VEX_0FD8,
1092   PREFIX_VEX_0FD9,
1093   PREFIX_VEX_0FDA,
1094   PREFIX_VEX_0FDB,
1095   PREFIX_VEX_0FDC,
1096   PREFIX_VEX_0FDD,
1097   PREFIX_VEX_0FDE,
1098   PREFIX_VEX_0FDF,
1099   PREFIX_VEX_0FE0,
1100   PREFIX_VEX_0FE1,
1101   PREFIX_VEX_0FE2,
1102   PREFIX_VEX_0FE3,
1103   PREFIX_VEX_0FE4,
1104   PREFIX_VEX_0FE5,
1105   PREFIX_VEX_0FE6,
1106   PREFIX_VEX_0FE7,
1107   PREFIX_VEX_0FE8,
1108   PREFIX_VEX_0FE9,
1109   PREFIX_VEX_0FEA,
1110   PREFIX_VEX_0FEB,
1111   PREFIX_VEX_0FEC,
1112   PREFIX_VEX_0FED,
1113   PREFIX_VEX_0FEE,
1114   PREFIX_VEX_0FEF,
1115   PREFIX_VEX_0FF0,
1116   PREFIX_VEX_0FF1,
1117   PREFIX_VEX_0FF2,
1118   PREFIX_VEX_0FF3,
1119   PREFIX_VEX_0FF4,
1120   PREFIX_VEX_0FF5,
1121   PREFIX_VEX_0FF6,
1122   PREFIX_VEX_0FF7,
1123   PREFIX_VEX_0FF8,
1124   PREFIX_VEX_0FF9,
1125   PREFIX_VEX_0FFA,
1126   PREFIX_VEX_0FFB,
1127   PREFIX_VEX_0FFC,
1128   PREFIX_VEX_0FFD,
1129   PREFIX_VEX_0FFE,
1130   PREFIX_VEX_0F3800,
1131   PREFIX_VEX_0F3801,
1132   PREFIX_VEX_0F3802,
1133   PREFIX_VEX_0F3803,
1134   PREFIX_VEX_0F3804,
1135   PREFIX_VEX_0F3805,
1136   PREFIX_VEX_0F3806,
1137   PREFIX_VEX_0F3807,
1138   PREFIX_VEX_0F3808,
1139   PREFIX_VEX_0F3809,
1140   PREFIX_VEX_0F380A,
1141   PREFIX_VEX_0F380B,
1142   PREFIX_VEX_0F380C,
1143   PREFIX_VEX_0F380D,
1144   PREFIX_VEX_0F380E,
1145   PREFIX_VEX_0F380F,
1146   PREFIX_VEX_0F3813,
1147   PREFIX_VEX_0F3816,
1148   PREFIX_VEX_0F3817,
1149   PREFIX_VEX_0F3818,
1150   PREFIX_VEX_0F3819,
1151   PREFIX_VEX_0F381A,
1152   PREFIX_VEX_0F381C,
1153   PREFIX_VEX_0F381D,
1154   PREFIX_VEX_0F381E,
1155   PREFIX_VEX_0F3820,
1156   PREFIX_VEX_0F3821,
1157   PREFIX_VEX_0F3822,
1158   PREFIX_VEX_0F3823,
1159   PREFIX_VEX_0F3824,
1160   PREFIX_VEX_0F3825,
1161   PREFIX_VEX_0F3828,
1162   PREFIX_VEX_0F3829,
1163   PREFIX_VEX_0F382A,
1164   PREFIX_VEX_0F382B,
1165   PREFIX_VEX_0F382C,
1166   PREFIX_VEX_0F382D,
1167   PREFIX_VEX_0F382E,
1168   PREFIX_VEX_0F382F,
1169   PREFIX_VEX_0F3830,
1170   PREFIX_VEX_0F3831,
1171   PREFIX_VEX_0F3832,
1172   PREFIX_VEX_0F3833,
1173   PREFIX_VEX_0F3834,
1174   PREFIX_VEX_0F3835,
1175   PREFIX_VEX_0F3836,
1176   PREFIX_VEX_0F3837,
1177   PREFIX_VEX_0F3838,
1178   PREFIX_VEX_0F3839,
1179   PREFIX_VEX_0F383A,
1180   PREFIX_VEX_0F383B,
1181   PREFIX_VEX_0F383C,
1182   PREFIX_VEX_0F383D,
1183   PREFIX_VEX_0F383E,
1184   PREFIX_VEX_0F383F,
1185   PREFIX_VEX_0F3840,
1186   PREFIX_VEX_0F3841,
1187   PREFIX_VEX_0F3845,
1188   PREFIX_VEX_0F3846,
1189   PREFIX_VEX_0F3847,
1190   PREFIX_VEX_0F3858,
1191   PREFIX_VEX_0F3859,
1192   PREFIX_VEX_0F385A,
1193   PREFIX_VEX_0F3878,
1194   PREFIX_VEX_0F3879,
1195   PREFIX_VEX_0F388C,
1196   PREFIX_VEX_0F388E,
1197   PREFIX_VEX_0F3890,
1198   PREFIX_VEX_0F3891,
1199   PREFIX_VEX_0F3892,
1200   PREFIX_VEX_0F3893,
1201   PREFIX_VEX_0F3896,
1202   PREFIX_VEX_0F3897,
1203   PREFIX_VEX_0F3898,
1204   PREFIX_VEX_0F3899,
1205   PREFIX_VEX_0F389A,
1206   PREFIX_VEX_0F389B,
1207   PREFIX_VEX_0F389C,
1208   PREFIX_VEX_0F389D,
1209   PREFIX_VEX_0F389E,
1210   PREFIX_VEX_0F389F,
1211   PREFIX_VEX_0F38A6,
1212   PREFIX_VEX_0F38A7,
1213   PREFIX_VEX_0F38A8,
1214   PREFIX_VEX_0F38A9,
1215   PREFIX_VEX_0F38AA,
1216   PREFIX_VEX_0F38AB,
1217   PREFIX_VEX_0F38AC,
1218   PREFIX_VEX_0F38AD,
1219   PREFIX_VEX_0F38AE,
1220   PREFIX_VEX_0F38AF,
1221   PREFIX_VEX_0F38B6,
1222   PREFIX_VEX_0F38B7,
1223   PREFIX_VEX_0F38B8,
1224   PREFIX_VEX_0F38B9,
1225   PREFIX_VEX_0F38BA,
1226   PREFIX_VEX_0F38BB,
1227   PREFIX_VEX_0F38BC,
1228   PREFIX_VEX_0F38BD,
1229   PREFIX_VEX_0F38BE,
1230   PREFIX_VEX_0F38BF,
1231   PREFIX_VEX_0F38DB,
1232   PREFIX_VEX_0F38DC,
1233   PREFIX_VEX_0F38DD,
1234   PREFIX_VEX_0F38DE,
1235   PREFIX_VEX_0F38DF,
1236   PREFIX_VEX_0F38F2,
1237   PREFIX_VEX_0F38F3_REG_1,
1238   PREFIX_VEX_0F38F3_REG_2,
1239   PREFIX_VEX_0F38F3_REG_3,
1240   PREFIX_VEX_0F38F5,
1241   PREFIX_VEX_0F38F6,
1242   PREFIX_VEX_0F38F7,
1243   PREFIX_VEX_0F3A00,
1244   PREFIX_VEX_0F3A01,
1245   PREFIX_VEX_0F3A02,
1246   PREFIX_VEX_0F3A04,
1247   PREFIX_VEX_0F3A05,
1248   PREFIX_VEX_0F3A06,
1249   PREFIX_VEX_0F3A08,
1250   PREFIX_VEX_0F3A09,
1251   PREFIX_VEX_0F3A0A,
1252   PREFIX_VEX_0F3A0B,
1253   PREFIX_VEX_0F3A0C,
1254   PREFIX_VEX_0F3A0D,
1255   PREFIX_VEX_0F3A0E,
1256   PREFIX_VEX_0F3A0F,
1257   PREFIX_VEX_0F3A14,
1258   PREFIX_VEX_0F3A15,
1259   PREFIX_VEX_0F3A16,
1260   PREFIX_VEX_0F3A17,
1261   PREFIX_VEX_0F3A18,
1262   PREFIX_VEX_0F3A19,
1263   PREFIX_VEX_0F3A1D,
1264   PREFIX_VEX_0F3A20,
1265   PREFIX_VEX_0F3A21,
1266   PREFIX_VEX_0F3A22,
1267   PREFIX_VEX_0F3A30,
1268   PREFIX_VEX_0F3A31,
1269   PREFIX_VEX_0F3A32,
1270   PREFIX_VEX_0F3A33,
1271   PREFIX_VEX_0F3A38,
1272   PREFIX_VEX_0F3A39,
1273   PREFIX_VEX_0F3A40,
1274   PREFIX_VEX_0F3A41,
1275   PREFIX_VEX_0F3A42,
1276   PREFIX_VEX_0F3A44,
1277   PREFIX_VEX_0F3A46,
1278   PREFIX_VEX_0F3A48,
1279   PREFIX_VEX_0F3A49,
1280   PREFIX_VEX_0F3A4A,
1281   PREFIX_VEX_0F3A4B,
1282   PREFIX_VEX_0F3A4C,
1283   PREFIX_VEX_0F3A5C,
1284   PREFIX_VEX_0F3A5D,
1285   PREFIX_VEX_0F3A5E,
1286   PREFIX_VEX_0F3A5F,
1287   PREFIX_VEX_0F3A60,
1288   PREFIX_VEX_0F3A61,
1289   PREFIX_VEX_0F3A62,
1290   PREFIX_VEX_0F3A63,
1291   PREFIX_VEX_0F3A68,
1292   PREFIX_VEX_0F3A69,
1293   PREFIX_VEX_0F3A6A,
1294   PREFIX_VEX_0F3A6B,
1295   PREFIX_VEX_0F3A6C,
1296   PREFIX_VEX_0F3A6D,
1297   PREFIX_VEX_0F3A6E,
1298   PREFIX_VEX_0F3A6F,
1299   PREFIX_VEX_0F3A78,
1300   PREFIX_VEX_0F3A79,
1301   PREFIX_VEX_0F3A7A,
1302   PREFIX_VEX_0F3A7B,
1303   PREFIX_VEX_0F3A7C,
1304   PREFIX_VEX_0F3A7D,
1305   PREFIX_VEX_0F3A7E,
1306   PREFIX_VEX_0F3A7F,
1307   PREFIX_VEX_0F3ADF,
1308   PREFIX_VEX_0F3AF0,
1309
1310   PREFIX_EVEX_0F10,
1311   PREFIX_EVEX_0F11,
1312   PREFIX_EVEX_0F12,
1313   PREFIX_EVEX_0F13,
1314   PREFIX_EVEX_0F14,
1315   PREFIX_EVEX_0F15,
1316   PREFIX_EVEX_0F16,
1317   PREFIX_EVEX_0F17,
1318   PREFIX_EVEX_0F28,
1319   PREFIX_EVEX_0F29,
1320   PREFIX_EVEX_0F2A,
1321   PREFIX_EVEX_0F2B,
1322   PREFIX_EVEX_0F2C,
1323   PREFIX_EVEX_0F2D,
1324   PREFIX_EVEX_0F2E,
1325   PREFIX_EVEX_0F2F,
1326   PREFIX_EVEX_0F51,
1327   PREFIX_EVEX_0F54,
1328   PREFIX_EVEX_0F55,
1329   PREFIX_EVEX_0F56,
1330   PREFIX_EVEX_0F57,
1331   PREFIX_EVEX_0F58,
1332   PREFIX_EVEX_0F59,
1333   PREFIX_EVEX_0F5A,
1334   PREFIX_EVEX_0F5B,
1335   PREFIX_EVEX_0F5C,
1336   PREFIX_EVEX_0F5D,
1337   PREFIX_EVEX_0F5E,
1338   PREFIX_EVEX_0F5F,
1339   PREFIX_EVEX_0F60,
1340   PREFIX_EVEX_0F61,
1341   PREFIX_EVEX_0F62,
1342   PREFIX_EVEX_0F63,
1343   PREFIX_EVEX_0F64,
1344   PREFIX_EVEX_0F65,
1345   PREFIX_EVEX_0F66,
1346   PREFIX_EVEX_0F67,
1347   PREFIX_EVEX_0F68,
1348   PREFIX_EVEX_0F69,
1349   PREFIX_EVEX_0F6A,
1350   PREFIX_EVEX_0F6B,
1351   PREFIX_EVEX_0F6C,
1352   PREFIX_EVEX_0F6D,
1353   PREFIX_EVEX_0F6E,
1354   PREFIX_EVEX_0F6F,
1355   PREFIX_EVEX_0F70,
1356   PREFIX_EVEX_0F71_REG_2,
1357   PREFIX_EVEX_0F71_REG_4,
1358   PREFIX_EVEX_0F71_REG_6,
1359   PREFIX_EVEX_0F72_REG_0,
1360   PREFIX_EVEX_0F72_REG_1,
1361   PREFIX_EVEX_0F72_REG_2,
1362   PREFIX_EVEX_0F72_REG_4,
1363   PREFIX_EVEX_0F72_REG_6,
1364   PREFIX_EVEX_0F73_REG_2,
1365   PREFIX_EVEX_0F73_REG_3,
1366   PREFIX_EVEX_0F73_REG_6,
1367   PREFIX_EVEX_0F73_REG_7,
1368   PREFIX_EVEX_0F74,
1369   PREFIX_EVEX_0F75,
1370   PREFIX_EVEX_0F76,
1371   PREFIX_EVEX_0F78,
1372   PREFIX_EVEX_0F79,
1373   PREFIX_EVEX_0F7A,
1374   PREFIX_EVEX_0F7B,
1375   PREFIX_EVEX_0F7E,
1376   PREFIX_EVEX_0F7F,
1377   PREFIX_EVEX_0FC2,
1378   PREFIX_EVEX_0FC4,
1379   PREFIX_EVEX_0FC5,
1380   PREFIX_EVEX_0FC6,
1381   PREFIX_EVEX_0FD1,
1382   PREFIX_EVEX_0FD2,
1383   PREFIX_EVEX_0FD3,
1384   PREFIX_EVEX_0FD4,
1385   PREFIX_EVEX_0FD5,
1386   PREFIX_EVEX_0FD6,
1387   PREFIX_EVEX_0FD8,
1388   PREFIX_EVEX_0FD9,
1389   PREFIX_EVEX_0FDA,
1390   PREFIX_EVEX_0FDB,
1391   PREFIX_EVEX_0FDC,
1392   PREFIX_EVEX_0FDD,
1393   PREFIX_EVEX_0FDE,
1394   PREFIX_EVEX_0FDF,
1395   PREFIX_EVEX_0FE0,
1396   PREFIX_EVEX_0FE1,
1397   PREFIX_EVEX_0FE2,
1398   PREFIX_EVEX_0FE3,
1399   PREFIX_EVEX_0FE4,
1400   PREFIX_EVEX_0FE5,
1401   PREFIX_EVEX_0FE6,
1402   PREFIX_EVEX_0FE7,
1403   PREFIX_EVEX_0FE8,
1404   PREFIX_EVEX_0FE9,
1405   PREFIX_EVEX_0FEA,
1406   PREFIX_EVEX_0FEB,
1407   PREFIX_EVEX_0FEC,
1408   PREFIX_EVEX_0FED,
1409   PREFIX_EVEX_0FEE,
1410   PREFIX_EVEX_0FEF,
1411   PREFIX_EVEX_0FF1,
1412   PREFIX_EVEX_0FF2,
1413   PREFIX_EVEX_0FF3,
1414   PREFIX_EVEX_0FF4,
1415   PREFIX_EVEX_0FF5,
1416   PREFIX_EVEX_0FF6,
1417   PREFIX_EVEX_0FF8,
1418   PREFIX_EVEX_0FF9,
1419   PREFIX_EVEX_0FFA,
1420   PREFIX_EVEX_0FFB,
1421   PREFIX_EVEX_0FFC,
1422   PREFIX_EVEX_0FFD,
1423   PREFIX_EVEX_0FFE,
1424   PREFIX_EVEX_0F3800,
1425   PREFIX_EVEX_0F3804,
1426   PREFIX_EVEX_0F380B,
1427   PREFIX_EVEX_0F380C,
1428   PREFIX_EVEX_0F380D,
1429   PREFIX_EVEX_0F3810,
1430   PREFIX_EVEX_0F3811,
1431   PREFIX_EVEX_0F3812,
1432   PREFIX_EVEX_0F3813,
1433   PREFIX_EVEX_0F3814,
1434   PREFIX_EVEX_0F3815,
1435   PREFIX_EVEX_0F3816,
1436   PREFIX_EVEX_0F3818,
1437   PREFIX_EVEX_0F3819,
1438   PREFIX_EVEX_0F381A,
1439   PREFIX_EVEX_0F381B,
1440   PREFIX_EVEX_0F381C,
1441   PREFIX_EVEX_0F381D,
1442   PREFIX_EVEX_0F381E,
1443   PREFIX_EVEX_0F381F,
1444   PREFIX_EVEX_0F3820,
1445   PREFIX_EVEX_0F3821,
1446   PREFIX_EVEX_0F3822,
1447   PREFIX_EVEX_0F3823,
1448   PREFIX_EVEX_0F3824,
1449   PREFIX_EVEX_0F3825,
1450   PREFIX_EVEX_0F3826,
1451   PREFIX_EVEX_0F3827,
1452   PREFIX_EVEX_0F3828,
1453   PREFIX_EVEX_0F3829,
1454   PREFIX_EVEX_0F382A,
1455   PREFIX_EVEX_0F382B,
1456   PREFIX_EVEX_0F382C,
1457   PREFIX_EVEX_0F382D,
1458   PREFIX_EVEX_0F3830,
1459   PREFIX_EVEX_0F3831,
1460   PREFIX_EVEX_0F3832,
1461   PREFIX_EVEX_0F3833,
1462   PREFIX_EVEX_0F3834,
1463   PREFIX_EVEX_0F3835,
1464   PREFIX_EVEX_0F3836,
1465   PREFIX_EVEX_0F3837,
1466   PREFIX_EVEX_0F3838,
1467   PREFIX_EVEX_0F3839,
1468   PREFIX_EVEX_0F383A,
1469   PREFIX_EVEX_0F383B,
1470   PREFIX_EVEX_0F383C,
1471   PREFIX_EVEX_0F383D,
1472   PREFIX_EVEX_0F383E,
1473   PREFIX_EVEX_0F383F,
1474   PREFIX_EVEX_0F3840,
1475   PREFIX_EVEX_0F3842,
1476   PREFIX_EVEX_0F3843,
1477   PREFIX_EVEX_0F3844,
1478   PREFIX_EVEX_0F3845,
1479   PREFIX_EVEX_0F3846,
1480   PREFIX_EVEX_0F3847,
1481   PREFIX_EVEX_0F384C,
1482   PREFIX_EVEX_0F384D,
1483   PREFIX_EVEX_0F384E,
1484   PREFIX_EVEX_0F384F,
1485   PREFIX_EVEX_0F3858,
1486   PREFIX_EVEX_0F3859,
1487   PREFIX_EVEX_0F385A,
1488   PREFIX_EVEX_0F385B,
1489   PREFIX_EVEX_0F3864,
1490   PREFIX_EVEX_0F3865,
1491   PREFIX_EVEX_0F3866,
1492   PREFIX_EVEX_0F3875,
1493   PREFIX_EVEX_0F3876,
1494   PREFIX_EVEX_0F3877,
1495   PREFIX_EVEX_0F3878,
1496   PREFIX_EVEX_0F3879,
1497   PREFIX_EVEX_0F387A,
1498   PREFIX_EVEX_0F387B,
1499   PREFIX_EVEX_0F387C,
1500   PREFIX_EVEX_0F387D,
1501   PREFIX_EVEX_0F387E,
1502   PREFIX_EVEX_0F387F,
1503   PREFIX_EVEX_0F3883,
1504   PREFIX_EVEX_0F3888,
1505   PREFIX_EVEX_0F3889,
1506   PREFIX_EVEX_0F388A,
1507   PREFIX_EVEX_0F388B,
1508   PREFIX_EVEX_0F388D,
1509   PREFIX_EVEX_0F3890,
1510   PREFIX_EVEX_0F3891,
1511   PREFIX_EVEX_0F3892,
1512   PREFIX_EVEX_0F3893,
1513   PREFIX_EVEX_0F3896,
1514   PREFIX_EVEX_0F3897,
1515   PREFIX_EVEX_0F3898,
1516   PREFIX_EVEX_0F3899,
1517   PREFIX_EVEX_0F389A,
1518   PREFIX_EVEX_0F389B,
1519   PREFIX_EVEX_0F389C,
1520   PREFIX_EVEX_0F389D,
1521   PREFIX_EVEX_0F389E,
1522   PREFIX_EVEX_0F389F,
1523   PREFIX_EVEX_0F38A0,
1524   PREFIX_EVEX_0F38A1,
1525   PREFIX_EVEX_0F38A2,
1526   PREFIX_EVEX_0F38A3,
1527   PREFIX_EVEX_0F38A6,
1528   PREFIX_EVEX_0F38A7,
1529   PREFIX_EVEX_0F38A8,
1530   PREFIX_EVEX_0F38A9,
1531   PREFIX_EVEX_0F38AA,
1532   PREFIX_EVEX_0F38AB,
1533   PREFIX_EVEX_0F38AC,
1534   PREFIX_EVEX_0F38AD,
1535   PREFIX_EVEX_0F38AE,
1536   PREFIX_EVEX_0F38AF,
1537   PREFIX_EVEX_0F38B4,
1538   PREFIX_EVEX_0F38B5,
1539   PREFIX_EVEX_0F38B6,
1540   PREFIX_EVEX_0F38B7,
1541   PREFIX_EVEX_0F38B8,
1542   PREFIX_EVEX_0F38B9,
1543   PREFIX_EVEX_0F38BA,
1544   PREFIX_EVEX_0F38BB,
1545   PREFIX_EVEX_0F38BC,
1546   PREFIX_EVEX_0F38BD,
1547   PREFIX_EVEX_0F38BE,
1548   PREFIX_EVEX_0F38BF,
1549   PREFIX_EVEX_0F38C4,
1550   PREFIX_EVEX_0F38C6_REG_1,
1551   PREFIX_EVEX_0F38C6_REG_2,
1552   PREFIX_EVEX_0F38C6_REG_5,
1553   PREFIX_EVEX_0F38C6_REG_6,
1554   PREFIX_EVEX_0F38C7_REG_1,
1555   PREFIX_EVEX_0F38C7_REG_2,
1556   PREFIX_EVEX_0F38C7_REG_5,
1557   PREFIX_EVEX_0F38C7_REG_6,
1558   PREFIX_EVEX_0F38C8,
1559   PREFIX_EVEX_0F38CA,
1560   PREFIX_EVEX_0F38CB,
1561   PREFIX_EVEX_0F38CC,
1562   PREFIX_EVEX_0F38CD,
1563
1564   PREFIX_EVEX_0F3A00,
1565   PREFIX_EVEX_0F3A01,
1566   PREFIX_EVEX_0F3A03,
1567   PREFIX_EVEX_0F3A04,
1568   PREFIX_EVEX_0F3A05,
1569   PREFIX_EVEX_0F3A08,
1570   PREFIX_EVEX_0F3A09,
1571   PREFIX_EVEX_0F3A0A,
1572   PREFIX_EVEX_0F3A0B,
1573   PREFIX_EVEX_0F3A0F,
1574   PREFIX_EVEX_0F3A14,
1575   PREFIX_EVEX_0F3A15,
1576   PREFIX_EVEX_0F3A16,
1577   PREFIX_EVEX_0F3A17,
1578   PREFIX_EVEX_0F3A18,
1579   PREFIX_EVEX_0F3A19,
1580   PREFIX_EVEX_0F3A1A,
1581   PREFIX_EVEX_0F3A1B,
1582   PREFIX_EVEX_0F3A1D,
1583   PREFIX_EVEX_0F3A1E,
1584   PREFIX_EVEX_0F3A1F,
1585   PREFIX_EVEX_0F3A20,
1586   PREFIX_EVEX_0F3A21,
1587   PREFIX_EVEX_0F3A22,
1588   PREFIX_EVEX_0F3A23,
1589   PREFIX_EVEX_0F3A25,
1590   PREFIX_EVEX_0F3A26,
1591   PREFIX_EVEX_0F3A27,
1592   PREFIX_EVEX_0F3A38,
1593   PREFIX_EVEX_0F3A39,
1594   PREFIX_EVEX_0F3A3A,
1595   PREFIX_EVEX_0F3A3B,
1596   PREFIX_EVEX_0F3A3E,
1597   PREFIX_EVEX_0F3A3F,
1598   PREFIX_EVEX_0F3A42,
1599   PREFIX_EVEX_0F3A43,
1600   PREFIX_EVEX_0F3A50,
1601   PREFIX_EVEX_0F3A51,
1602   PREFIX_EVEX_0F3A54,
1603   PREFIX_EVEX_0F3A55,
1604   PREFIX_EVEX_0F3A56,
1605   PREFIX_EVEX_0F3A57,
1606   PREFIX_EVEX_0F3A66,
1607   PREFIX_EVEX_0F3A67
1608 };
1609
1610 enum
1611 {
1612   X86_64_06 = 0,
1613   X86_64_07,
1614   X86_64_0D,
1615   X86_64_16,
1616   X86_64_17,
1617   X86_64_1E,
1618   X86_64_1F,
1619   X86_64_27,
1620   X86_64_2F,
1621   X86_64_37,
1622   X86_64_3F,
1623   X86_64_60,
1624   X86_64_61,
1625   X86_64_62,
1626   X86_64_63,
1627   X86_64_6D,
1628   X86_64_6F,
1629   X86_64_9A,
1630   X86_64_C4,
1631   X86_64_C5,
1632   X86_64_CE,
1633   X86_64_D4,
1634   X86_64_D5,
1635   X86_64_E8,
1636   X86_64_E9,
1637   X86_64_EA,
1638   X86_64_0F01_REG_0,
1639   X86_64_0F01_REG_1,
1640   X86_64_0F01_REG_2,
1641   X86_64_0F01_REG_3
1642 };
1643
1644 enum
1645 {
1646   THREE_BYTE_0F38 = 0,
1647   THREE_BYTE_0F3A,
1648   THREE_BYTE_0F7A
1649 };
1650
1651 enum
1652 {
1653   XOP_08 = 0,
1654   XOP_09,
1655   XOP_0A
1656 };
1657
1658 enum
1659 {
1660   VEX_0F = 0,
1661   VEX_0F38,
1662   VEX_0F3A
1663 };
1664
1665 enum
1666 {
1667   EVEX_0F = 0,
1668   EVEX_0F38,
1669   EVEX_0F3A
1670 };
1671
1672 enum
1673 {
1674   VEX_LEN_0F10_P_1 = 0,
1675   VEX_LEN_0F10_P_3,
1676   VEX_LEN_0F11_P_1,
1677   VEX_LEN_0F11_P_3,
1678   VEX_LEN_0F12_P_0_M_0,
1679   VEX_LEN_0F12_P_0_M_1,
1680   VEX_LEN_0F12_P_2,
1681   VEX_LEN_0F13_M_0,
1682   VEX_LEN_0F16_P_0_M_0,
1683   VEX_LEN_0F16_P_0_M_1,
1684   VEX_LEN_0F16_P_2,
1685   VEX_LEN_0F17_M_0,
1686   VEX_LEN_0F2A_P_1,
1687   VEX_LEN_0F2A_P_3,
1688   VEX_LEN_0F2C_P_1,
1689   VEX_LEN_0F2C_P_3,
1690   VEX_LEN_0F2D_P_1,
1691   VEX_LEN_0F2D_P_3,
1692   VEX_LEN_0F2E_P_0,
1693   VEX_LEN_0F2E_P_2,
1694   VEX_LEN_0F2F_P_0,
1695   VEX_LEN_0F2F_P_2,
1696   VEX_LEN_0F41_P_0,
1697   VEX_LEN_0F41_P_2,
1698   VEX_LEN_0F42_P_0,
1699   VEX_LEN_0F42_P_2,
1700   VEX_LEN_0F44_P_0,
1701   VEX_LEN_0F44_P_2,
1702   VEX_LEN_0F45_P_0,
1703   VEX_LEN_0F45_P_2,
1704   VEX_LEN_0F46_P_0,
1705   VEX_LEN_0F46_P_2,
1706   VEX_LEN_0F47_P_0,
1707   VEX_LEN_0F47_P_2,
1708   VEX_LEN_0F4A_P_0,
1709   VEX_LEN_0F4A_P_2,
1710   VEX_LEN_0F4B_P_0,
1711   VEX_LEN_0F4B_P_2,
1712   VEX_LEN_0F51_P_1,
1713   VEX_LEN_0F51_P_3,
1714   VEX_LEN_0F52_P_1,
1715   VEX_LEN_0F53_P_1,
1716   VEX_LEN_0F58_P_1,
1717   VEX_LEN_0F58_P_3,
1718   VEX_LEN_0F59_P_1,
1719   VEX_LEN_0F59_P_3,
1720   VEX_LEN_0F5A_P_1,
1721   VEX_LEN_0F5A_P_3,
1722   VEX_LEN_0F5C_P_1,
1723   VEX_LEN_0F5C_P_3,
1724   VEX_LEN_0F5D_P_1,
1725   VEX_LEN_0F5D_P_3,
1726   VEX_LEN_0F5E_P_1,
1727   VEX_LEN_0F5E_P_3,
1728   VEX_LEN_0F5F_P_1,
1729   VEX_LEN_0F5F_P_3,
1730   VEX_LEN_0F6E_P_2,
1731   VEX_LEN_0F7E_P_1,
1732   VEX_LEN_0F7E_P_2,
1733   VEX_LEN_0F90_P_0,
1734   VEX_LEN_0F90_P_2,
1735   VEX_LEN_0F91_P_0,
1736   VEX_LEN_0F91_P_2,
1737   VEX_LEN_0F92_P_0,
1738   VEX_LEN_0F92_P_2,
1739   VEX_LEN_0F92_P_3,
1740   VEX_LEN_0F93_P_0,
1741   VEX_LEN_0F93_P_2,
1742   VEX_LEN_0F93_P_3,
1743   VEX_LEN_0F98_P_0,
1744   VEX_LEN_0F98_P_2,
1745   VEX_LEN_0F99_P_0,
1746   VEX_LEN_0F99_P_2,
1747   VEX_LEN_0FAE_R_2_M_0,
1748   VEX_LEN_0FAE_R_3_M_0,
1749   VEX_LEN_0FC2_P_1,
1750   VEX_LEN_0FC2_P_3,
1751   VEX_LEN_0FC4_P_2,
1752   VEX_LEN_0FC5_P_2,
1753   VEX_LEN_0FD6_P_2,
1754   VEX_LEN_0FF7_P_2,
1755   VEX_LEN_0F3816_P_2,
1756   VEX_LEN_0F3819_P_2,
1757   VEX_LEN_0F381A_P_2_M_0,
1758   VEX_LEN_0F3836_P_2,
1759   VEX_LEN_0F3841_P_2,
1760   VEX_LEN_0F385A_P_2_M_0,
1761   VEX_LEN_0F38DB_P_2,
1762   VEX_LEN_0F38DC_P_2,
1763   VEX_LEN_0F38DD_P_2,
1764   VEX_LEN_0F38DE_P_2,
1765   VEX_LEN_0F38DF_P_2,
1766   VEX_LEN_0F38F2_P_0,
1767   VEX_LEN_0F38F3_R_1_P_0,
1768   VEX_LEN_0F38F3_R_2_P_0,
1769   VEX_LEN_0F38F3_R_3_P_0,
1770   VEX_LEN_0F38F5_P_0,
1771   VEX_LEN_0F38F5_P_1,
1772   VEX_LEN_0F38F5_P_3,
1773   VEX_LEN_0F38F6_P_3,
1774   VEX_LEN_0F38F7_P_0,
1775   VEX_LEN_0F38F7_P_1,
1776   VEX_LEN_0F38F7_P_2,
1777   VEX_LEN_0F38F7_P_3,
1778   VEX_LEN_0F3A00_P_2,
1779   VEX_LEN_0F3A01_P_2,
1780   VEX_LEN_0F3A06_P_2,
1781   VEX_LEN_0F3A0A_P_2,
1782   VEX_LEN_0F3A0B_P_2,
1783   VEX_LEN_0F3A14_P_2,
1784   VEX_LEN_0F3A15_P_2,
1785   VEX_LEN_0F3A16_P_2,
1786   VEX_LEN_0F3A17_P_2,
1787   VEX_LEN_0F3A18_P_2,
1788   VEX_LEN_0F3A19_P_2,
1789   VEX_LEN_0F3A20_P_2,
1790   VEX_LEN_0F3A21_P_2,
1791   VEX_LEN_0F3A22_P_2,
1792   VEX_LEN_0F3A30_P_2,
1793   VEX_LEN_0F3A31_P_2,
1794   VEX_LEN_0F3A32_P_2,
1795   VEX_LEN_0F3A33_P_2,
1796   VEX_LEN_0F3A38_P_2,
1797   VEX_LEN_0F3A39_P_2,
1798   VEX_LEN_0F3A41_P_2,
1799   VEX_LEN_0F3A44_P_2,
1800   VEX_LEN_0F3A46_P_2,
1801   VEX_LEN_0F3A60_P_2,
1802   VEX_LEN_0F3A61_P_2,
1803   VEX_LEN_0F3A62_P_2,
1804   VEX_LEN_0F3A63_P_2,
1805   VEX_LEN_0F3A6A_P_2,
1806   VEX_LEN_0F3A6B_P_2,
1807   VEX_LEN_0F3A6E_P_2,
1808   VEX_LEN_0F3A6F_P_2,
1809   VEX_LEN_0F3A7A_P_2,
1810   VEX_LEN_0F3A7B_P_2,
1811   VEX_LEN_0F3A7E_P_2,
1812   VEX_LEN_0F3A7F_P_2,
1813   VEX_LEN_0F3ADF_P_2,
1814   VEX_LEN_0F3AF0_P_3,
1815   VEX_LEN_0FXOP_08_CC,
1816   VEX_LEN_0FXOP_08_CD,
1817   VEX_LEN_0FXOP_08_CE,
1818   VEX_LEN_0FXOP_08_CF,
1819   VEX_LEN_0FXOP_08_EC,
1820   VEX_LEN_0FXOP_08_ED,
1821   VEX_LEN_0FXOP_08_EE,
1822   VEX_LEN_0FXOP_08_EF,
1823   VEX_LEN_0FXOP_09_80,
1824   VEX_LEN_0FXOP_09_81
1825 };
1826
1827 enum
1828 {
1829   VEX_W_0F10_P_0 = 0,
1830   VEX_W_0F10_P_1,
1831   VEX_W_0F10_P_2,
1832   VEX_W_0F10_P_3,
1833   VEX_W_0F11_P_0,
1834   VEX_W_0F11_P_1,
1835   VEX_W_0F11_P_2,
1836   VEX_W_0F11_P_3,
1837   VEX_W_0F12_P_0_M_0,
1838   VEX_W_0F12_P_0_M_1,
1839   VEX_W_0F12_P_1,
1840   VEX_W_0F12_P_2,
1841   VEX_W_0F12_P_3,
1842   VEX_W_0F13_M_0,
1843   VEX_W_0F14,
1844   VEX_W_0F15,
1845   VEX_W_0F16_P_0_M_0,
1846   VEX_W_0F16_P_0_M_1,
1847   VEX_W_0F16_P_1,
1848   VEX_W_0F16_P_2,
1849   VEX_W_0F17_M_0,
1850   VEX_W_0F28,
1851   VEX_W_0F29,
1852   VEX_W_0F2B_M_0,
1853   VEX_W_0F2E_P_0,
1854   VEX_W_0F2E_P_2,
1855   VEX_W_0F2F_P_0,
1856   VEX_W_0F2F_P_2,
1857   VEX_W_0F41_P_0_LEN_1,
1858   VEX_W_0F41_P_2_LEN_1,
1859   VEX_W_0F42_P_0_LEN_1,
1860   VEX_W_0F42_P_2_LEN_1,
1861   VEX_W_0F44_P_0_LEN_0,
1862   VEX_W_0F44_P_2_LEN_0,
1863   VEX_W_0F45_P_0_LEN_1,
1864   VEX_W_0F45_P_2_LEN_1,
1865   VEX_W_0F46_P_0_LEN_1,
1866   VEX_W_0F46_P_2_LEN_1,
1867   VEX_W_0F47_P_0_LEN_1,
1868   VEX_W_0F47_P_2_LEN_1,
1869   VEX_W_0F4A_P_0_LEN_1,
1870   VEX_W_0F4A_P_2_LEN_1,
1871   VEX_W_0F4B_P_0_LEN_1,
1872   VEX_W_0F4B_P_2_LEN_1,
1873   VEX_W_0F50_M_0,
1874   VEX_W_0F51_P_0,
1875   VEX_W_0F51_P_1,
1876   VEX_W_0F51_P_2,
1877   VEX_W_0F51_P_3,
1878   VEX_W_0F52_P_0,
1879   VEX_W_0F52_P_1,
1880   VEX_W_0F53_P_0,
1881   VEX_W_0F53_P_1,
1882   VEX_W_0F58_P_0,
1883   VEX_W_0F58_P_1,
1884   VEX_W_0F58_P_2,
1885   VEX_W_0F58_P_3,
1886   VEX_W_0F59_P_0,
1887   VEX_W_0F59_P_1,
1888   VEX_W_0F59_P_2,
1889   VEX_W_0F59_P_3,
1890   VEX_W_0F5A_P_0,
1891   VEX_W_0F5A_P_1,
1892   VEX_W_0F5A_P_3,
1893   VEX_W_0F5B_P_0,
1894   VEX_W_0F5B_P_1,
1895   VEX_W_0F5B_P_2,
1896   VEX_W_0F5C_P_0,
1897   VEX_W_0F5C_P_1,
1898   VEX_W_0F5C_P_2,
1899   VEX_W_0F5C_P_3,
1900   VEX_W_0F5D_P_0,
1901   VEX_W_0F5D_P_1,
1902   VEX_W_0F5D_P_2,
1903   VEX_W_0F5D_P_3,
1904   VEX_W_0F5E_P_0,
1905   VEX_W_0F5E_P_1,
1906   VEX_W_0F5E_P_2,
1907   VEX_W_0F5E_P_3,
1908   VEX_W_0F5F_P_0,
1909   VEX_W_0F5F_P_1,
1910   VEX_W_0F5F_P_2,
1911   VEX_W_0F5F_P_3,
1912   VEX_W_0F60_P_2,
1913   VEX_W_0F61_P_2,
1914   VEX_W_0F62_P_2,
1915   VEX_W_0F63_P_2,
1916   VEX_W_0F64_P_2,
1917   VEX_W_0F65_P_2,
1918   VEX_W_0F66_P_2,
1919   VEX_W_0F67_P_2,
1920   VEX_W_0F68_P_2,
1921   VEX_W_0F69_P_2,
1922   VEX_W_0F6A_P_2,
1923   VEX_W_0F6B_P_2,
1924   VEX_W_0F6C_P_2,
1925   VEX_W_0F6D_P_2,
1926   VEX_W_0F6F_P_1,
1927   VEX_W_0F6F_P_2,
1928   VEX_W_0F70_P_1,
1929   VEX_W_0F70_P_2,
1930   VEX_W_0F70_P_3,
1931   VEX_W_0F71_R_2_P_2,
1932   VEX_W_0F71_R_4_P_2,
1933   VEX_W_0F71_R_6_P_2,
1934   VEX_W_0F72_R_2_P_2,
1935   VEX_W_0F72_R_4_P_2,
1936   VEX_W_0F72_R_6_P_2,
1937   VEX_W_0F73_R_2_P_2,
1938   VEX_W_0F73_R_3_P_2,
1939   VEX_W_0F73_R_6_P_2,
1940   VEX_W_0F73_R_7_P_2,
1941   VEX_W_0F74_P_2,
1942   VEX_W_0F75_P_2,
1943   VEX_W_0F76_P_2,
1944   VEX_W_0F77_P_0,
1945   VEX_W_0F7C_P_2,
1946   VEX_W_0F7C_P_3,
1947   VEX_W_0F7D_P_2,
1948   VEX_W_0F7D_P_3,
1949   VEX_W_0F7E_P_1,
1950   VEX_W_0F7F_P_1,
1951   VEX_W_0F7F_P_2,
1952   VEX_W_0F90_P_0_LEN_0,
1953   VEX_W_0F90_P_2_LEN_0,
1954   VEX_W_0F91_P_0_LEN_0,
1955   VEX_W_0F91_P_2_LEN_0,
1956   VEX_W_0F92_P_0_LEN_0,
1957   VEX_W_0F92_P_2_LEN_0,
1958   VEX_W_0F92_P_3_LEN_0,
1959   VEX_W_0F93_P_0_LEN_0,
1960   VEX_W_0F93_P_2_LEN_0,
1961   VEX_W_0F93_P_3_LEN_0,
1962   VEX_W_0F98_P_0_LEN_0,
1963   VEX_W_0F98_P_2_LEN_0,
1964   VEX_W_0F99_P_0_LEN_0,
1965   VEX_W_0F99_P_2_LEN_0,
1966   VEX_W_0FAE_R_2_M_0,
1967   VEX_W_0FAE_R_3_M_0,
1968   VEX_W_0FC2_P_0,
1969   VEX_W_0FC2_P_1,
1970   VEX_W_0FC2_P_2,
1971   VEX_W_0FC2_P_3,
1972   VEX_W_0FC4_P_2,
1973   VEX_W_0FC5_P_2,
1974   VEX_W_0FD0_P_2,
1975   VEX_W_0FD0_P_3,
1976   VEX_W_0FD1_P_2,
1977   VEX_W_0FD2_P_2,
1978   VEX_W_0FD3_P_2,
1979   VEX_W_0FD4_P_2,
1980   VEX_W_0FD5_P_2,
1981   VEX_W_0FD6_P_2,
1982   VEX_W_0FD7_P_2_M_1,
1983   VEX_W_0FD8_P_2,
1984   VEX_W_0FD9_P_2,
1985   VEX_W_0FDA_P_2,
1986   VEX_W_0FDB_P_2,
1987   VEX_W_0FDC_P_2,
1988   VEX_W_0FDD_P_2,
1989   VEX_W_0FDE_P_2,
1990   VEX_W_0FDF_P_2,
1991   VEX_W_0FE0_P_2,
1992   VEX_W_0FE1_P_2,
1993   VEX_W_0FE2_P_2,
1994   VEX_W_0FE3_P_2,
1995   VEX_W_0FE4_P_2,
1996   VEX_W_0FE5_P_2,
1997   VEX_W_0FE6_P_1,
1998   VEX_W_0FE6_P_2,
1999   VEX_W_0FE6_P_3,
2000   VEX_W_0FE7_P_2_M_0,
2001   VEX_W_0FE8_P_2,
2002   VEX_W_0FE9_P_2,
2003   VEX_W_0FEA_P_2,
2004   VEX_W_0FEB_P_2,
2005   VEX_W_0FEC_P_2,
2006   VEX_W_0FED_P_2,
2007   VEX_W_0FEE_P_2,
2008   VEX_W_0FEF_P_2,
2009   VEX_W_0FF0_P_3_M_0,
2010   VEX_W_0FF1_P_2,
2011   VEX_W_0FF2_P_2,
2012   VEX_W_0FF3_P_2,
2013   VEX_W_0FF4_P_2,
2014   VEX_W_0FF5_P_2,
2015   VEX_W_0FF6_P_2,
2016   VEX_W_0FF7_P_2,
2017   VEX_W_0FF8_P_2,
2018   VEX_W_0FF9_P_2,
2019   VEX_W_0FFA_P_2,
2020   VEX_W_0FFB_P_2,
2021   VEX_W_0FFC_P_2,
2022   VEX_W_0FFD_P_2,
2023   VEX_W_0FFE_P_2,
2024   VEX_W_0F3800_P_2,
2025   VEX_W_0F3801_P_2,
2026   VEX_W_0F3802_P_2,
2027   VEX_W_0F3803_P_2,
2028   VEX_W_0F3804_P_2,
2029   VEX_W_0F3805_P_2,
2030   VEX_W_0F3806_P_2,
2031   VEX_W_0F3807_P_2,
2032   VEX_W_0F3808_P_2,
2033   VEX_W_0F3809_P_2,
2034   VEX_W_0F380A_P_2,
2035   VEX_W_0F380B_P_2,
2036   VEX_W_0F380C_P_2,
2037   VEX_W_0F380D_P_2,
2038   VEX_W_0F380E_P_2,
2039   VEX_W_0F380F_P_2,
2040   VEX_W_0F3816_P_2,
2041   VEX_W_0F3817_P_2,
2042   VEX_W_0F3818_P_2,
2043   VEX_W_0F3819_P_2,
2044   VEX_W_0F381A_P_2_M_0,
2045   VEX_W_0F381C_P_2,
2046   VEX_W_0F381D_P_2,
2047   VEX_W_0F381E_P_2,
2048   VEX_W_0F3820_P_2,
2049   VEX_W_0F3821_P_2,
2050   VEX_W_0F3822_P_2,
2051   VEX_W_0F3823_P_2,
2052   VEX_W_0F3824_P_2,
2053   VEX_W_0F3825_P_2,
2054   VEX_W_0F3828_P_2,
2055   VEX_W_0F3829_P_2,
2056   VEX_W_0F382A_P_2_M_0,
2057   VEX_W_0F382B_P_2,
2058   VEX_W_0F382C_P_2_M_0,
2059   VEX_W_0F382D_P_2_M_0,
2060   VEX_W_0F382E_P_2_M_0,
2061   VEX_W_0F382F_P_2_M_0,
2062   VEX_W_0F3830_P_2,
2063   VEX_W_0F3831_P_2,
2064   VEX_W_0F3832_P_2,
2065   VEX_W_0F3833_P_2,
2066   VEX_W_0F3834_P_2,
2067   VEX_W_0F3835_P_2,
2068   VEX_W_0F3836_P_2,
2069   VEX_W_0F3837_P_2,
2070   VEX_W_0F3838_P_2,
2071   VEX_W_0F3839_P_2,
2072   VEX_W_0F383A_P_2,
2073   VEX_W_0F383B_P_2,
2074   VEX_W_0F383C_P_2,
2075   VEX_W_0F383D_P_2,
2076   VEX_W_0F383E_P_2,
2077   VEX_W_0F383F_P_2,
2078   VEX_W_0F3840_P_2,
2079   VEX_W_0F3841_P_2,
2080   VEX_W_0F3846_P_2,
2081   VEX_W_0F3858_P_2,
2082   VEX_W_0F3859_P_2,
2083   VEX_W_0F385A_P_2_M_0,
2084   VEX_W_0F3878_P_2,
2085   VEX_W_0F3879_P_2,
2086   VEX_W_0F38DB_P_2,
2087   VEX_W_0F38DC_P_2,
2088   VEX_W_0F38DD_P_2,
2089   VEX_W_0F38DE_P_2,
2090   VEX_W_0F38DF_P_2,
2091   VEX_W_0F3A00_P_2,
2092   VEX_W_0F3A01_P_2,
2093   VEX_W_0F3A02_P_2,
2094   VEX_W_0F3A04_P_2,
2095   VEX_W_0F3A05_P_2,
2096   VEX_W_0F3A06_P_2,
2097   VEX_W_0F3A08_P_2,
2098   VEX_W_0F3A09_P_2,
2099   VEX_W_0F3A0A_P_2,
2100   VEX_W_0F3A0B_P_2,
2101   VEX_W_0F3A0C_P_2,
2102   VEX_W_0F3A0D_P_2,
2103   VEX_W_0F3A0E_P_2,
2104   VEX_W_0F3A0F_P_2,
2105   VEX_W_0F3A14_P_2,
2106   VEX_W_0F3A15_P_2,
2107   VEX_W_0F3A18_P_2,
2108   VEX_W_0F3A19_P_2,
2109   VEX_W_0F3A20_P_2,
2110   VEX_W_0F3A21_P_2,
2111   VEX_W_0F3A30_P_2_LEN_0,
2112   VEX_W_0F3A31_P_2_LEN_0,
2113   VEX_W_0F3A32_P_2_LEN_0,
2114   VEX_W_0F3A33_P_2_LEN_0,
2115   VEX_W_0F3A38_P_2,
2116   VEX_W_0F3A39_P_2,
2117   VEX_W_0F3A40_P_2,
2118   VEX_W_0F3A41_P_2,
2119   VEX_W_0F3A42_P_2,
2120   VEX_W_0F3A44_P_2,
2121   VEX_W_0F3A46_P_2,
2122   VEX_W_0F3A48_P_2,
2123   VEX_W_0F3A49_P_2,
2124   VEX_W_0F3A4A_P_2,
2125   VEX_W_0F3A4B_P_2,
2126   VEX_W_0F3A4C_P_2,
2127   VEX_W_0F3A60_P_2,
2128   VEX_W_0F3A61_P_2,
2129   VEX_W_0F3A62_P_2,
2130   VEX_W_0F3A63_P_2,
2131   VEX_W_0F3ADF_P_2,
2132
2133   EVEX_W_0F10_P_0,
2134   EVEX_W_0F10_P_1_M_0,
2135   EVEX_W_0F10_P_1_M_1,
2136   EVEX_W_0F10_P_2,
2137   EVEX_W_0F10_P_3_M_0,
2138   EVEX_W_0F10_P_3_M_1,
2139   EVEX_W_0F11_P_0,
2140   EVEX_W_0F11_P_1_M_0,
2141   EVEX_W_0F11_P_1_M_1,
2142   EVEX_W_0F11_P_2,
2143   EVEX_W_0F11_P_3_M_0,
2144   EVEX_W_0F11_P_3_M_1,
2145   EVEX_W_0F12_P_0_M_0,
2146   EVEX_W_0F12_P_0_M_1,
2147   EVEX_W_0F12_P_1,
2148   EVEX_W_0F12_P_2,
2149   EVEX_W_0F12_P_3,
2150   EVEX_W_0F13_P_0,
2151   EVEX_W_0F13_P_2,
2152   EVEX_W_0F14_P_0,
2153   EVEX_W_0F14_P_2,
2154   EVEX_W_0F15_P_0,
2155   EVEX_W_0F15_P_2,
2156   EVEX_W_0F16_P_0_M_0,
2157   EVEX_W_0F16_P_0_M_1,
2158   EVEX_W_0F16_P_1,
2159   EVEX_W_0F16_P_2,
2160   EVEX_W_0F17_P_0,
2161   EVEX_W_0F17_P_2,
2162   EVEX_W_0F28_P_0,
2163   EVEX_W_0F28_P_2,
2164   EVEX_W_0F29_P_0,
2165   EVEX_W_0F29_P_2,
2166   EVEX_W_0F2A_P_1,
2167   EVEX_W_0F2A_P_3,
2168   EVEX_W_0F2B_P_0,
2169   EVEX_W_0F2B_P_2,
2170   EVEX_W_0F2E_P_0,
2171   EVEX_W_0F2E_P_2,
2172   EVEX_W_0F2F_P_0,
2173   EVEX_W_0F2F_P_2,
2174   EVEX_W_0F51_P_0,
2175   EVEX_W_0F51_P_1,
2176   EVEX_W_0F51_P_2,
2177   EVEX_W_0F51_P_3,
2178   EVEX_W_0F54_P_0,
2179   EVEX_W_0F54_P_2,
2180   EVEX_W_0F55_P_0,
2181   EVEX_W_0F55_P_2,
2182   EVEX_W_0F56_P_0,
2183   EVEX_W_0F56_P_2,
2184   EVEX_W_0F57_P_0,
2185   EVEX_W_0F57_P_2,
2186   EVEX_W_0F58_P_0,
2187   EVEX_W_0F58_P_1,
2188   EVEX_W_0F58_P_2,
2189   EVEX_W_0F58_P_3,
2190   EVEX_W_0F59_P_0,
2191   EVEX_W_0F59_P_1,
2192   EVEX_W_0F59_P_2,
2193   EVEX_W_0F59_P_3,
2194   EVEX_W_0F5A_P_0,
2195   EVEX_W_0F5A_P_1,
2196   EVEX_W_0F5A_P_2,
2197   EVEX_W_0F5A_P_3,
2198   EVEX_W_0F5B_P_0,
2199   EVEX_W_0F5B_P_1,
2200   EVEX_W_0F5B_P_2,
2201   EVEX_W_0F5C_P_0,
2202   EVEX_W_0F5C_P_1,
2203   EVEX_W_0F5C_P_2,
2204   EVEX_W_0F5C_P_3,
2205   EVEX_W_0F5D_P_0,
2206   EVEX_W_0F5D_P_1,
2207   EVEX_W_0F5D_P_2,
2208   EVEX_W_0F5D_P_3,
2209   EVEX_W_0F5E_P_0,
2210   EVEX_W_0F5E_P_1,
2211   EVEX_W_0F5E_P_2,
2212   EVEX_W_0F5E_P_3,
2213   EVEX_W_0F5F_P_0,
2214   EVEX_W_0F5F_P_1,
2215   EVEX_W_0F5F_P_2,
2216   EVEX_W_0F5F_P_3,
2217   EVEX_W_0F62_P_2,
2218   EVEX_W_0F66_P_2,
2219   EVEX_W_0F6A_P_2,
2220   EVEX_W_0F6B_P_2,
2221   EVEX_W_0F6C_P_2,
2222   EVEX_W_0F6D_P_2,
2223   EVEX_W_0F6E_P_2,
2224   EVEX_W_0F6F_P_1,
2225   EVEX_W_0F6F_P_2,
2226   EVEX_W_0F6F_P_3,
2227   EVEX_W_0F70_P_2,
2228   EVEX_W_0F72_R_2_P_2,
2229   EVEX_W_0F72_R_6_P_2,
2230   EVEX_W_0F73_R_2_P_2,
2231   EVEX_W_0F73_R_6_P_2,
2232   EVEX_W_0F76_P_2,
2233   EVEX_W_0F78_P_0,
2234   EVEX_W_0F78_P_2,
2235   EVEX_W_0F79_P_0,
2236   EVEX_W_0F79_P_2,
2237   EVEX_W_0F7A_P_1,
2238   EVEX_W_0F7A_P_2,
2239   EVEX_W_0F7A_P_3,
2240   EVEX_W_0F7B_P_1,
2241   EVEX_W_0F7B_P_2,
2242   EVEX_W_0F7B_P_3,
2243   EVEX_W_0F7E_P_1,
2244   EVEX_W_0F7E_P_2,
2245   EVEX_W_0F7F_P_1,
2246   EVEX_W_0F7F_P_2,
2247   EVEX_W_0F7F_P_3,
2248   EVEX_W_0FC2_P_0,
2249   EVEX_W_0FC2_P_1,
2250   EVEX_W_0FC2_P_2,
2251   EVEX_W_0FC2_P_3,
2252   EVEX_W_0FC6_P_0,
2253   EVEX_W_0FC6_P_2,
2254   EVEX_W_0FD2_P_2,
2255   EVEX_W_0FD3_P_2,
2256   EVEX_W_0FD4_P_2,
2257   EVEX_W_0FD6_P_2,
2258   EVEX_W_0FE6_P_1,
2259   EVEX_W_0FE6_P_2,
2260   EVEX_W_0FE6_P_3,
2261   EVEX_W_0FE7_P_2,
2262   EVEX_W_0FF2_P_2,
2263   EVEX_W_0FF3_P_2,
2264   EVEX_W_0FF4_P_2,
2265   EVEX_W_0FFA_P_2,
2266   EVEX_W_0FFB_P_2,
2267   EVEX_W_0FFE_P_2,
2268   EVEX_W_0F380C_P_2,
2269   EVEX_W_0F380D_P_2,
2270   EVEX_W_0F3810_P_1,
2271   EVEX_W_0F3810_P_2,
2272   EVEX_W_0F3811_P_1,
2273   EVEX_W_0F3811_P_2,
2274   EVEX_W_0F3812_P_1,
2275   EVEX_W_0F3812_P_2,
2276   EVEX_W_0F3813_P_1,
2277   EVEX_W_0F3813_P_2,
2278   EVEX_W_0F3814_P_1,
2279   EVEX_W_0F3815_P_1,
2280   EVEX_W_0F3818_P_2,
2281   EVEX_W_0F3819_P_2,
2282   EVEX_W_0F381A_P_2,
2283   EVEX_W_0F381B_P_2,
2284   EVEX_W_0F381E_P_2,
2285   EVEX_W_0F381F_P_2,
2286   EVEX_W_0F3820_P_1,
2287   EVEX_W_0F3821_P_1,
2288   EVEX_W_0F3822_P_1,
2289   EVEX_W_0F3823_P_1,
2290   EVEX_W_0F3824_P_1,
2291   EVEX_W_0F3825_P_1,
2292   EVEX_W_0F3825_P_2,
2293   EVEX_W_0F3826_P_1,
2294   EVEX_W_0F3826_P_2,
2295   EVEX_W_0F3828_P_1,
2296   EVEX_W_0F3828_P_2,
2297   EVEX_W_0F3829_P_1,
2298   EVEX_W_0F3829_P_2,
2299   EVEX_W_0F382A_P_1,
2300   EVEX_W_0F382A_P_2,
2301   EVEX_W_0F382B_P_2,
2302   EVEX_W_0F3830_P_1,
2303   EVEX_W_0F3831_P_1,
2304   EVEX_W_0F3832_P_1,
2305   EVEX_W_0F3833_P_1,
2306   EVEX_W_0F3834_P_1,
2307   EVEX_W_0F3835_P_1,
2308   EVEX_W_0F3835_P_2,
2309   EVEX_W_0F3837_P_2,
2310   EVEX_W_0F3838_P_1,
2311   EVEX_W_0F3839_P_1,
2312   EVEX_W_0F383A_P_1,
2313   EVEX_W_0F3840_P_2,
2314   EVEX_W_0F3858_P_2,
2315   EVEX_W_0F3859_P_2,
2316   EVEX_W_0F385A_P_2,
2317   EVEX_W_0F385B_P_2,
2318   EVEX_W_0F3866_P_2,
2319   EVEX_W_0F3875_P_2,
2320   EVEX_W_0F3878_P_2,
2321   EVEX_W_0F3879_P_2,
2322   EVEX_W_0F387A_P_2,
2323   EVEX_W_0F387B_P_2,
2324   EVEX_W_0F387D_P_2,
2325   EVEX_W_0F3883_P_2,
2326   EVEX_W_0F388D_P_2,
2327   EVEX_W_0F3891_P_2,
2328   EVEX_W_0F3893_P_2,
2329   EVEX_W_0F38A1_P_2,
2330   EVEX_W_0F38A3_P_2,
2331   EVEX_W_0F38C7_R_1_P_2,
2332   EVEX_W_0F38C7_R_2_P_2,
2333   EVEX_W_0F38C7_R_5_P_2,
2334   EVEX_W_0F38C7_R_6_P_2,
2335
2336   EVEX_W_0F3A00_P_2,
2337   EVEX_W_0F3A01_P_2,
2338   EVEX_W_0F3A04_P_2,
2339   EVEX_W_0F3A05_P_2,
2340   EVEX_W_0F3A08_P_2,
2341   EVEX_W_0F3A09_P_2,
2342   EVEX_W_0F3A0A_P_2,
2343   EVEX_W_0F3A0B_P_2,
2344   EVEX_W_0F3A16_P_2,
2345   EVEX_W_0F3A18_P_2,
2346   EVEX_W_0F3A19_P_2,
2347   EVEX_W_0F3A1A_P_2,
2348   EVEX_W_0F3A1B_P_2,
2349   EVEX_W_0F3A1D_P_2,
2350   EVEX_W_0F3A21_P_2,
2351   EVEX_W_0F3A22_P_2,
2352   EVEX_W_0F3A23_P_2,
2353   EVEX_W_0F3A38_P_2,
2354   EVEX_W_0F3A39_P_2,
2355   EVEX_W_0F3A3A_P_2,
2356   EVEX_W_0F3A3B_P_2,
2357   EVEX_W_0F3A3E_P_2,
2358   EVEX_W_0F3A3F_P_2,
2359   EVEX_W_0F3A42_P_2,
2360   EVEX_W_0F3A43_P_2,
2361   EVEX_W_0F3A50_P_2,
2362   EVEX_W_0F3A51_P_2,
2363   EVEX_W_0F3A56_P_2,
2364   EVEX_W_0F3A57_P_2,
2365   EVEX_W_0F3A66_P_2,
2366   EVEX_W_0F3A67_P_2
2367 };
2368
2369 typedef void (*op_rtn) (int bytemode, int sizeflag);
2370
2371 struct dis386 {
2372   const char *name;
2373   struct
2374     {
2375       op_rtn rtn;
2376       int bytemode;
2377     } op[MAX_OPERANDS];
2378   unsigned int prefix_requirement;
2379 };
2380
2381 /* Upper case letters in the instruction names here are macros.
2382    'A' => print 'b' if no register operands or suffix_always is true
2383    'B' => print 'b' if suffix_always is true
2384    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2385           size prefix
2386    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2387           suffix_always is true
2388    'E' => print 'e' if 32-bit form of jcxz
2389    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2390    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2391    'H' => print ",pt" or ",pn" branch hint
2392    'I' => honor following macro letter even in Intel mode (implemented only
2393           for some of the macro letters)
2394    'J' => print 'l'
2395    'K' => print 'd' or 'q' if rex prefix is present.
2396    'L' => print 'l' if suffix_always is true
2397    'M' => print 'r' if intel_mnemonic is false.
2398    'N' => print 'n' if instruction has no wait "prefix"
2399    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2400    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2401           or suffix_always is true.  print 'q' if rex prefix is present.
2402    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2403           is true
2404    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2405    'S' => print 'w', 'l' or 'q' if suffix_always is true
2406    'T' => print 'q' in 64bit mode if instruction has no operand size
2407           prefix and behave as 'P' otherwise
2408    'U' => print 'q' in 64bit mode if instruction has no operand size
2409           prefix and behave as 'Q' otherwise
2410    'V' => print 'q' in 64bit mode if instruction has no operand size
2411           prefix and behave as 'S' otherwise
2412    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2413    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2414    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2415           suffix_always is true.
2416    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2417    '!' => change condition from true to false or from false to true.
2418    '%' => add 1 upper case letter to the macro.
2419    '^' => print 'w' or 'l' depending on operand size prefix or
2420           suffix_always is true (lcall/ljmp).
2421
2422    2 upper case letter macros:
2423    "XY" => print 'x' or 'y' if suffix_always is true or no register
2424            operands and no broadcast.
2425    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2426            register operands and no broadcast.
2427    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2428    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2429            or suffix_always is true
2430    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2431    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2432    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2433    "LW" => print 'd', 'q' depending on the VEX.W bit
2434    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2435            an operand size prefix, or suffix_always is true.  print
2436            'q' if rex prefix is present.
2437
2438    Many of the above letters print nothing in Intel mode.  See "putop"
2439    for the details.
2440
2441    Braces '{' and '}', and vertical bars '|', indicate alternative
2442    mnemonic strings for AT&T and Intel.  */
2443
2444 static const struct dis386 dis386[] = {
2445   /* 00 */
2446   { "addB",             { Ebh1, Gb }, 0 },
2447   { "addS",             { Evh1, Gv }, 0 },
2448   { "addB",             { Gb, EbS }, 0 },
2449   { "addS",             { Gv, EvS }, 0 },
2450   { "addB",             { AL, Ib }, 0 },
2451   { "addS",             { eAX, Iv }, 0 },
2452   { X86_64_TABLE (X86_64_06) },
2453   { X86_64_TABLE (X86_64_07) },
2454   /* 08 */
2455   { "orB",              { Ebh1, Gb }, 0 },
2456   { "orS",              { Evh1, Gv }, 0 },
2457   { "orB",              { Gb, EbS }, 0 },
2458   { "orS",              { Gv, EvS }, 0 },
2459   { "orB",              { AL, Ib }, 0 },
2460   { "orS",              { eAX, Iv }, 0 },
2461   { X86_64_TABLE (X86_64_0D) },
2462   { Bad_Opcode },       /* 0x0f extended opcode escape */
2463   /* 10 */
2464   { "adcB",             { Ebh1, Gb }, 0 },
2465   { "adcS",             { Evh1, Gv }, 0 },
2466   { "adcB",             { Gb, EbS }, 0 },
2467   { "adcS",             { Gv, EvS }, 0 },
2468   { "adcB",             { AL, Ib }, 0 },
2469   { "adcS",             { eAX, Iv }, 0 },
2470   { X86_64_TABLE (X86_64_16) },
2471   { X86_64_TABLE (X86_64_17) },
2472   /* 18 */
2473   { "sbbB",             { Ebh1, Gb }, 0 },
2474   { "sbbS",             { Evh1, Gv }, 0 },
2475   { "sbbB",             { Gb, EbS }, 0 },
2476   { "sbbS",             { Gv, EvS }, 0 },
2477   { "sbbB",             { AL, Ib }, 0 },
2478   { "sbbS",             { eAX, Iv }, 0 },
2479   { X86_64_TABLE (X86_64_1E) },
2480   { X86_64_TABLE (X86_64_1F) },
2481   /* 20 */
2482   { "andB",             { Ebh1, Gb }, 0 },
2483   { "andS",             { Evh1, Gv }, 0 },
2484   { "andB",             { Gb, EbS }, 0 },
2485   { "andS",             { Gv, EvS }, 0 },
2486   { "andB",             { AL, Ib }, 0 },
2487   { "andS",             { eAX, Iv }, 0 },
2488   { Bad_Opcode },       /* SEG ES prefix */
2489   { X86_64_TABLE (X86_64_27) },
2490   /* 28 */
2491   { "subB",             { Ebh1, Gb }, 0 },
2492   { "subS",             { Evh1, Gv }, 0 },
2493   { "subB",             { Gb, EbS }, 0 },
2494   { "subS",             { Gv, EvS }, 0 },
2495   { "subB",             { AL, Ib }, 0 },
2496   { "subS",             { eAX, Iv }, 0 },
2497   { Bad_Opcode },       /* SEG CS prefix */
2498   { X86_64_TABLE (X86_64_2F) },
2499   /* 30 */
2500   { "xorB",             { Ebh1, Gb }, 0 },
2501   { "xorS",             { Evh1, Gv }, 0 },
2502   { "xorB",             { Gb, EbS }, 0 },
2503   { "xorS",             { Gv, EvS }, 0 },
2504   { "xorB",             { AL, Ib }, 0 },
2505   { "xorS",             { eAX, Iv }, 0 },
2506   { Bad_Opcode },       /* SEG SS prefix */
2507   { X86_64_TABLE (X86_64_37) },
2508   /* 38 */
2509   { "cmpB",             { Eb, Gb }, 0 },
2510   { "cmpS",             { Ev, Gv }, 0 },
2511   { "cmpB",             { Gb, EbS }, 0 },
2512   { "cmpS",             { Gv, EvS }, 0 },
2513   { "cmpB",             { AL, Ib }, 0 },
2514   { "cmpS",             { eAX, Iv }, 0 },
2515   { Bad_Opcode },       /* SEG DS prefix */
2516   { X86_64_TABLE (X86_64_3F) },
2517   /* 40 */
2518   { "inc{S|}",          { RMeAX }, 0 },
2519   { "inc{S|}",          { RMeCX }, 0 },
2520   { "inc{S|}",          { RMeDX }, 0 },
2521   { "inc{S|}",          { RMeBX }, 0 },
2522   { "inc{S|}",          { RMeSP }, 0 },
2523   { "inc{S|}",          { RMeBP }, 0 },
2524   { "inc{S|}",          { RMeSI }, 0 },
2525   { "inc{S|}",          { RMeDI }, 0 },
2526   /* 48 */
2527   { "dec{S|}",          { RMeAX }, 0 },
2528   { "dec{S|}",          { RMeCX }, 0 },
2529   { "dec{S|}",          { RMeDX }, 0 },
2530   { "dec{S|}",          { RMeBX }, 0 },
2531   { "dec{S|}",          { RMeSP }, 0 },
2532   { "dec{S|}",          { RMeBP }, 0 },
2533   { "dec{S|}",          { RMeSI }, 0 },
2534   { "dec{S|}",          { RMeDI }, 0 },
2535   /* 50 */
2536   { "pushV",            { RMrAX }, 0 },
2537   { "pushV",            { RMrCX }, 0 },
2538   { "pushV",            { RMrDX }, 0 },
2539   { "pushV",            { RMrBX }, 0 },
2540   { "pushV",            { RMrSP }, 0 },
2541   { "pushV",            { RMrBP }, 0 },
2542   { "pushV",            { RMrSI }, 0 },
2543   { "pushV",            { RMrDI }, 0 },
2544   /* 58 */
2545   { "popV",             { RMrAX }, 0 },
2546   { "popV",             { RMrCX }, 0 },
2547   { "popV",             { RMrDX }, 0 },
2548   { "popV",             { RMrBX }, 0 },
2549   { "popV",             { RMrSP }, 0 },
2550   { "popV",             { RMrBP }, 0 },
2551   { "popV",             { RMrSI }, 0 },
2552   { "popV",             { RMrDI }, 0 },
2553   /* 60 */
2554   { X86_64_TABLE (X86_64_60) },
2555   { X86_64_TABLE (X86_64_61) },
2556   { X86_64_TABLE (X86_64_62) },
2557   { X86_64_TABLE (X86_64_63) },
2558   { Bad_Opcode },       /* seg fs */
2559   { Bad_Opcode },       /* seg gs */
2560   { Bad_Opcode },       /* op size prefix */
2561   { Bad_Opcode },       /* adr size prefix */
2562   /* 68 */
2563   { "pushT",            { sIv }, 0 },
2564   { "imulS",            { Gv, Ev, Iv }, 0 },
2565   { "pushT",            { sIbT }, 0 },
2566   { "imulS",            { Gv, Ev, sIb }, 0 },
2567   { "ins{b|}",          { Ybr, indirDX }, 0 },
2568   { X86_64_TABLE (X86_64_6D) },
2569   { "outs{b|}",         { indirDXr, Xb }, 0 },
2570   { X86_64_TABLE (X86_64_6F) },
2571   /* 70 */
2572   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2573   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2574   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2575   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2576   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2577   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2578   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2579   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2580   /* 78 */
2581   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2582   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2583   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2584   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2585   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2586   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2587   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2588   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2589   /* 80 */
2590   { REG_TABLE (REG_80) },
2591   { REG_TABLE (REG_81) },
2592   { Bad_Opcode },
2593   { REG_TABLE (REG_82) },
2594   { "testB",            { Eb, Gb }, 0 },
2595   { "testS",            { Ev, Gv }, 0 },
2596   { "xchgB",            { Ebh2, Gb }, 0 },
2597   { "xchgS",            { Evh2, Gv }, 0 },
2598   /* 88 */
2599   { "movB",             { Ebh3, Gb }, 0 },
2600   { "movS",             { Evh3, Gv }, 0 },
2601   { "movB",             { Gb, EbS }, 0 },
2602   { "movS",             { Gv, EvS }, 0 },
2603   { "movD",             { Sv, Sw }, 0 },
2604   { MOD_TABLE (MOD_8D) },
2605   { "movD",             { Sw, Sv }, 0 },
2606   { REG_TABLE (REG_8F) },
2607   /* 90 */
2608   { PREFIX_TABLE (PREFIX_90) },
2609   { "xchgS",            { RMeCX, eAX }, 0 },
2610   { "xchgS",            { RMeDX, eAX }, 0 },
2611   { "xchgS",            { RMeBX, eAX }, 0 },
2612   { "xchgS",            { RMeSP, eAX }, 0 },
2613   { "xchgS",            { RMeBP, eAX }, 0 },
2614   { "xchgS",            { RMeSI, eAX }, 0 },
2615   { "xchgS",            { RMeDI, eAX }, 0 },
2616   /* 98 */
2617   { "cW{t|}R",          { XX }, 0 },
2618   { "cR{t|}O",          { XX }, 0 },
2619   { X86_64_TABLE (X86_64_9A) },
2620   { Bad_Opcode },       /* fwait */
2621   { "pushfT",           { XX }, 0 },
2622   { "popfT",            { XX }, 0 },
2623   { "sahf",             { XX }, 0 },
2624   { "lahf",             { XX }, 0 },
2625   /* a0 */
2626   { "mov%LB",           { AL, Ob }, 0 },
2627   { "mov%LS",           { eAX, Ov }, 0 },
2628   { "mov%LB",           { Ob, AL }, 0 },
2629   { "mov%LS",           { Ov, eAX }, 0 },
2630   { "movs{b|}",         { Ybr, Xb }, 0 },
2631   { "movs{R|}",         { Yvr, Xv }, 0 },
2632   { "cmps{b|}",         { Xb, Yb }, 0 },
2633   { "cmps{R|}",         { Xv, Yv }, 0 },
2634   /* a8 */
2635   { "testB",            { AL, Ib }, 0 },
2636   { "testS",            { eAX, Iv }, 0 },
2637   { "stosB",            { Ybr, AL }, 0 },
2638   { "stosS",            { Yvr, eAX }, 0 },
2639   { "lodsB",            { ALr, Xb }, 0 },
2640   { "lodsS",            { eAXr, Xv }, 0 },
2641   { "scasB",            { AL, Yb }, 0 },
2642   { "scasS",            { eAX, Yv }, 0 },
2643   /* b0 */
2644   { "movB",             { RMAL, Ib }, 0 },
2645   { "movB",             { RMCL, Ib }, 0 },
2646   { "movB",             { RMDL, Ib }, 0 },
2647   { "movB",             { RMBL, Ib }, 0 },
2648   { "movB",             { RMAH, Ib }, 0 },
2649   { "movB",             { RMCH, Ib }, 0 },
2650   { "movB",             { RMDH, Ib }, 0 },
2651   { "movB",             { RMBH, Ib }, 0 },
2652   /* b8 */
2653   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2654   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2655   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2656   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2657   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2658   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2659   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2660   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2661   /* c0 */
2662   { REG_TABLE (REG_C0) },
2663   { REG_TABLE (REG_C1) },
2664   { "retT",             { Iw, BND }, 0 },
2665   { "retT",             { BND }, 0 },
2666   { X86_64_TABLE (X86_64_C4) },
2667   { X86_64_TABLE (X86_64_C5) },
2668   { REG_TABLE (REG_C6) },
2669   { REG_TABLE (REG_C7) },
2670   /* c8 */
2671   { "enterT",           { Iw, Ib }, 0 },
2672   { "leaveT",           { XX }, 0 },
2673   { "Jret{|f}P",        { Iw }, 0 },
2674   { "Jret{|f}P",        { XX }, 0 },
2675   { "int3",             { XX }, 0 },
2676   { "int",              { Ib }, 0 },
2677   { X86_64_TABLE (X86_64_CE) },
2678   { "iret%LP",          { XX }, 0 },
2679   /* d0 */
2680   { REG_TABLE (REG_D0) },
2681   { REG_TABLE (REG_D1) },
2682   { REG_TABLE (REG_D2) },
2683   { REG_TABLE (REG_D3) },
2684   { X86_64_TABLE (X86_64_D4) },
2685   { X86_64_TABLE (X86_64_D5) },
2686   { Bad_Opcode },
2687   { "xlat",             { DSBX }, 0 },
2688   /* d8 */
2689   { FLOAT },
2690   { FLOAT },
2691   { FLOAT },
2692   { FLOAT },
2693   { FLOAT },
2694   { FLOAT },
2695   { FLOAT },
2696   { FLOAT },
2697   /* e0 */
2698   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2699   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2700   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2701   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2702   { "inB",              { AL, Ib }, 0 },
2703   { "inG",              { zAX, Ib }, 0 },
2704   { "outB",             { Ib, AL }, 0 },
2705   { "outG",             { Ib, zAX }, 0 },
2706   /* e8 */
2707   { X86_64_TABLE (X86_64_E8) },
2708   { X86_64_TABLE (X86_64_E9) },
2709   { X86_64_TABLE (X86_64_EA) },
2710   { "jmp",              { Jb, BND }, 0 },
2711   { "inB",              { AL, indirDX }, 0 },
2712   { "inG",              { zAX, indirDX }, 0 },
2713   { "outB",             { indirDX, AL }, 0 },
2714   { "outG",             { indirDX, zAX }, 0 },
2715   /* f0 */
2716   { Bad_Opcode },       /* lock prefix */
2717   { "icebp",            { XX }, 0 },
2718   { Bad_Opcode },       /* repne */
2719   { Bad_Opcode },       /* repz */
2720   { "hlt",              { XX }, 0 },
2721   { "cmc",              { XX }, 0 },
2722   { REG_TABLE (REG_F6) },
2723   { REG_TABLE (REG_F7) },
2724   /* f8 */
2725   { "clc",              { XX }, 0 },
2726   { "stc",              { XX }, 0 },
2727   { "cli",              { XX }, 0 },
2728   { "sti",              { XX }, 0 },
2729   { "cld",              { XX }, 0 },
2730   { "std",              { XX }, 0 },
2731   { REG_TABLE (REG_FE) },
2732   { REG_TABLE (REG_FF) },
2733 };
2734
2735 static const struct dis386 dis386_twobyte[] = {
2736   /* 00 */
2737   { REG_TABLE (REG_0F00 ) },
2738   { REG_TABLE (REG_0F01 ) },
2739   { "larS",             { Gv, Ew }, 0 },
2740   { "lslS",             { Gv, Ew }, 0 },
2741   { Bad_Opcode },
2742   { "syscall",          { XX }, 0 },
2743   { "clts",             { XX }, 0 },
2744   { "sysret%LP",                { XX }, 0 },
2745   /* 08 */
2746   { "invd",             { XX }, 0 },
2747   { "wbinvd",           { XX }, 0 },
2748   { Bad_Opcode },
2749   { "ud2",              { XX }, 0 },
2750   { Bad_Opcode },
2751   { REG_TABLE (REG_0F0D) },
2752   { "femms",            { XX }, 0 },
2753   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2754   /* 10 */
2755   { PREFIX_TABLE (PREFIX_0F10) },
2756   { PREFIX_TABLE (PREFIX_0F11) },
2757   { PREFIX_TABLE (PREFIX_0F12) },
2758   { MOD_TABLE (MOD_0F13) },
2759   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2760   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2761   { PREFIX_TABLE (PREFIX_0F16) },
2762   { MOD_TABLE (MOD_0F17) },
2763   /* 18 */
2764   { REG_TABLE (REG_0F18) },
2765   { "nopQ",             { Ev }, 0 },
2766   { PREFIX_TABLE (PREFIX_0F1A) },
2767   { PREFIX_TABLE (PREFIX_0F1B) },
2768   { "nopQ",             { Ev }, 0 },
2769   { "nopQ",             { Ev }, 0 },
2770   { "nopQ",             { Ev }, 0 },
2771   { "nopQ",             { Ev }, 0 },
2772   /* 20 */
2773   { "movZ",             { Rm, Cm }, 0 },
2774   { "movZ",             { Rm, Dm }, 0 },
2775   { "movZ",             { Cm, Rm }, 0 },
2776   { "movZ",             { Dm, Rm }, 0 },
2777   { MOD_TABLE (MOD_0F24) },
2778   { Bad_Opcode },
2779   { MOD_TABLE (MOD_0F26) },
2780   { Bad_Opcode },
2781   /* 28 */
2782   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2783   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2784   { PREFIX_TABLE (PREFIX_0F2A) },
2785   { PREFIX_TABLE (PREFIX_0F2B) },
2786   { PREFIX_TABLE (PREFIX_0F2C) },
2787   { PREFIX_TABLE (PREFIX_0F2D) },
2788   { PREFIX_TABLE (PREFIX_0F2E) },
2789   { PREFIX_TABLE (PREFIX_0F2F) },
2790   /* 30 */
2791   { "wrmsr",            { XX }, 0 },
2792   { "rdtsc",            { XX }, 0 },
2793   { "rdmsr",            { XX }, 0 },
2794   { "rdpmc",            { XX }, 0 },
2795   { "sysenter",         { XX }, 0 },
2796   { "sysexit",          { XX }, 0 },
2797   { Bad_Opcode },
2798   { "getsec",           { XX }, 0 },
2799   /* 38 */
2800   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2801   { Bad_Opcode },
2802   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2803   { Bad_Opcode },
2804   { Bad_Opcode },
2805   { Bad_Opcode },
2806   { Bad_Opcode },
2807   { Bad_Opcode },
2808   /* 40 */
2809   { "cmovoS",           { Gv, Ev }, 0 },
2810   { "cmovnoS",          { Gv, Ev }, 0 },
2811   { "cmovbS",           { Gv, Ev }, 0 },
2812   { "cmovaeS",          { Gv, Ev }, 0 },
2813   { "cmoveS",           { Gv, Ev }, 0 },
2814   { "cmovneS",          { Gv, Ev }, 0 },
2815   { "cmovbeS",          { Gv, Ev }, 0 },
2816   { "cmovaS",           { Gv, Ev }, 0 },
2817   /* 48 */
2818   { "cmovsS",           { Gv, Ev }, 0 },
2819   { "cmovnsS",          { Gv, Ev }, 0 },
2820   { "cmovpS",           { Gv, Ev }, 0 },
2821   { "cmovnpS",          { Gv, Ev }, 0 },
2822   { "cmovlS",           { Gv, Ev }, 0 },
2823   { "cmovgeS",          { Gv, Ev }, 0 },
2824   { "cmovleS",          { Gv, Ev }, 0 },
2825   { "cmovgS",           { Gv, Ev }, 0 },
2826   /* 50 */
2827   { MOD_TABLE (MOD_0F51) },
2828   { PREFIX_TABLE (PREFIX_0F51) },
2829   { PREFIX_TABLE (PREFIX_0F52) },
2830   { PREFIX_TABLE (PREFIX_0F53) },
2831   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2832   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2833   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2834   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2835   /* 58 */
2836   { PREFIX_TABLE (PREFIX_0F58) },
2837   { PREFIX_TABLE (PREFIX_0F59) },
2838   { PREFIX_TABLE (PREFIX_0F5A) },
2839   { PREFIX_TABLE (PREFIX_0F5B) },
2840   { PREFIX_TABLE (PREFIX_0F5C) },
2841   { PREFIX_TABLE (PREFIX_0F5D) },
2842   { PREFIX_TABLE (PREFIX_0F5E) },
2843   { PREFIX_TABLE (PREFIX_0F5F) },
2844   /* 60 */
2845   { PREFIX_TABLE (PREFIX_0F60) },
2846   { PREFIX_TABLE (PREFIX_0F61) },
2847   { PREFIX_TABLE (PREFIX_0F62) },
2848   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2849   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2850   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2851   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2852   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2853   /* 68 */
2854   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2855   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2856   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2857   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2858   { PREFIX_TABLE (PREFIX_0F6C) },
2859   { PREFIX_TABLE (PREFIX_0F6D) },
2860   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2861   { PREFIX_TABLE (PREFIX_0F6F) },
2862   /* 70 */
2863   { PREFIX_TABLE (PREFIX_0F70) },
2864   { REG_TABLE (REG_0F71) },
2865   { REG_TABLE (REG_0F72) },
2866   { REG_TABLE (REG_0F73) },
2867   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2868   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2869   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2870   { "emms",             { XX }, PREFIX_OPCODE },
2871   /* 78 */
2872   { PREFIX_TABLE (PREFIX_0F78) },
2873   { PREFIX_TABLE (PREFIX_0F79) },
2874   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2875   { Bad_Opcode },
2876   { PREFIX_TABLE (PREFIX_0F7C) },
2877   { PREFIX_TABLE (PREFIX_0F7D) },
2878   { PREFIX_TABLE (PREFIX_0F7E) },
2879   { PREFIX_TABLE (PREFIX_0F7F) },
2880   /* 80 */
2881   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2882   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2883   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2884   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2885   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2886   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2887   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2888   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2889   /* 88 */
2890   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2891   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2892   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2893   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2894   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2895   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2896   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2897   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2898   /* 90 */
2899   { "seto",             { Eb }, 0 },
2900   { "setno",            { Eb }, 0 },
2901   { "setb",             { Eb }, 0 },
2902   { "setae",            { Eb }, 0 },
2903   { "sete",             { Eb }, 0 },
2904   { "setne",            { Eb }, 0 },
2905   { "setbe",            { Eb }, 0 },
2906   { "seta",             { Eb }, 0 },
2907   /* 98 */
2908   { "sets",             { Eb }, 0 },
2909   { "setns",            { Eb }, 0 },
2910   { "setp",             { Eb }, 0 },
2911   { "setnp",            { Eb }, 0 },
2912   { "setl",             { Eb }, 0 },
2913   { "setge",            { Eb }, 0 },
2914   { "setle",            { Eb }, 0 },
2915   { "setg",             { Eb }, 0 },
2916   /* a0 */
2917   { "pushT",            { fs }, 0 },
2918   { "popT",             { fs }, 0 },
2919   { "cpuid",            { XX }, 0 },
2920   { "btS",              { Ev, Gv }, 0 },
2921   { "shldS",            { Ev, Gv, Ib }, 0 },
2922   { "shldS",            { Ev, Gv, CL }, 0 },
2923   { REG_TABLE (REG_0FA6) },
2924   { REG_TABLE (REG_0FA7) },
2925   /* a8 */
2926   { "pushT",            { gs }, 0 },
2927   { "popT",             { gs }, 0 },
2928   { "rsm",              { XX }, 0 },
2929   { "btsS",             { Evh1, Gv }, 0 },
2930   { "shrdS",            { Ev, Gv, Ib }, 0 },
2931   { "shrdS",            { Ev, Gv, CL }, 0 },
2932   { REG_TABLE (REG_0FAE) },
2933   { "imulS",            { Gv, Ev }, 0 },
2934   /* b0 */
2935   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2936   { "cmpxchgS",         { Evh1, Gv }, 0 },
2937   { MOD_TABLE (MOD_0FB2) },
2938   { "btrS",             { Evh1, Gv }, 0 },
2939   { MOD_TABLE (MOD_0FB4) },
2940   { MOD_TABLE (MOD_0FB5) },
2941   { "movz{bR|x}",       { Gv, Eb }, 0 },
2942   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2943   /* b8 */
2944   { PREFIX_TABLE (PREFIX_0FB8) },
2945   { "ud1",              { XX }, 0 },
2946   { REG_TABLE (REG_0FBA) },
2947   { "btcS",             { Evh1, Gv }, 0 },
2948   { PREFIX_TABLE (PREFIX_0FBC) },
2949   { PREFIX_TABLE (PREFIX_0FBD) },
2950   { "movs{bR|x}",       { Gv, Eb }, 0 },
2951   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2952   /* c0 */
2953   { "xaddB",            { Ebh1, Gb }, 0 },
2954   { "xaddS",            { Evh1, Gv }, 0 },
2955   { PREFIX_TABLE (PREFIX_0FC2) },
2956   { PREFIX_TABLE (PREFIX_0FC3) },
2957   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2958   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2959   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2960   { REG_TABLE (REG_0FC7) },
2961   /* c8 */
2962   { "bswap",            { RMeAX }, 0 },
2963   { "bswap",            { RMeCX }, 0 },
2964   { "bswap",            { RMeDX }, 0 },
2965   { "bswap",            { RMeBX }, 0 },
2966   { "bswap",            { RMeSP }, 0 },
2967   { "bswap",            { RMeBP }, 0 },
2968   { "bswap",            { RMeSI }, 0 },
2969   { "bswap",            { RMeDI }, 0 },
2970   /* d0 */
2971   { PREFIX_TABLE (PREFIX_0FD0) },
2972   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2973   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2974   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2975   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2976   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2977   { PREFIX_TABLE (PREFIX_0FD6) },
2978   { MOD_TABLE (MOD_0FD7) },
2979   /* d8 */
2980   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2981   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2982   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2983   { "pand",             { MX, EM }, PREFIX_OPCODE },
2984   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2985   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2986   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2987   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2988   /* e0 */
2989   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2990   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2991   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2992   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2993   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2994   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2995   { PREFIX_TABLE (PREFIX_0FE6) },
2996   { PREFIX_TABLE (PREFIX_0FE7) },
2997   /* e8 */
2998   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2999   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3000   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3001   { "por",              { MX, EM }, PREFIX_OPCODE },
3002   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3003   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3004   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3005   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3006   /* f0 */
3007   { PREFIX_TABLE (PREFIX_0FF0) },
3008   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3009   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3010   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3011   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3012   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3013   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3014   { PREFIX_TABLE (PREFIX_0FF7) },
3015   /* f8 */
3016   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3017   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3018   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3019   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3020   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3021   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3022   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3023   { Bad_Opcode },
3024 };
3025
3026 static const unsigned char onebyte_has_modrm[256] = {
3027   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3028   /*       -------------------------------        */
3029   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3030   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3031   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3032   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3033   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3034   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3035   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3036   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3037   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3038   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3039   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3040   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3041   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3042   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3043   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3044   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3045   /*       -------------------------------        */
3046   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3047 };
3048
3049 static const unsigned char twobyte_has_modrm[256] = {
3050   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3051   /*       -------------------------------        */
3052   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3053   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3054   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3055   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3056   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3057   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3058   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3059   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3060   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3061   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3062   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3063   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3064   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3065   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3066   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3067   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3068   /*       -------------------------------        */
3069   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3070 };
3071
3072 static char obuf[100];
3073 static char *obufp;
3074 static char *mnemonicendp;
3075 static char scratchbuf[100];
3076 static unsigned char *start_codep;
3077 static unsigned char *insn_codep;
3078 static unsigned char *codep;
3079 static unsigned char *end_codep;
3080 static int last_lock_prefix;
3081 static int last_repz_prefix;
3082 static int last_repnz_prefix;
3083 static int last_data_prefix;
3084 static int last_addr_prefix;
3085 static int last_rex_prefix;
3086 static int last_seg_prefix;
3087 static int fwait_prefix;
3088 /* The active segment register prefix.  */
3089 static int active_seg_prefix;
3090 #define MAX_CODE_LENGTH 15
3091 /* We can up to 14 prefixes since the maximum instruction length is
3092    15bytes.  */
3093 static int all_prefixes[MAX_CODE_LENGTH - 1];
3094 static disassemble_info *the_info;
3095 static struct
3096   {
3097     int mod;
3098     int reg;
3099     int rm;
3100   }
3101 modrm;
3102 static unsigned char need_modrm;
3103 static struct
3104   {
3105     int scale;
3106     int index;
3107     int base;
3108   }
3109 sib;
3110 static struct
3111   {
3112     int register_specifier;
3113     int length;
3114     int prefix;
3115     int w;
3116     int evex;
3117     int r;
3118     int v;
3119     int mask_register_specifier;
3120     int zeroing;
3121     int ll;
3122     int b;
3123   }
3124 vex;
3125 static unsigned char need_vex;
3126 static unsigned char need_vex_reg;
3127 static unsigned char vex_w_done;
3128
3129 struct op
3130   {
3131     const char *name;
3132     unsigned int len;
3133   };
3134
3135 /* If we are accessing mod/rm/reg without need_modrm set, then the
3136    values are stale.  Hitting this abort likely indicates that you
3137    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3138 #define MODRM_CHECK  if (!need_modrm) abort ()
3139
3140 static const char **names64;
3141 static const char **names32;
3142 static const char **names16;
3143 static const char **names8;
3144 static const char **names8rex;
3145 static const char **names_seg;
3146 static const char *index64;
3147 static const char *index32;
3148 static const char **index16;
3149 static const char **names_bnd;
3150
3151 static const char *intel_names64[] = {
3152   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3153   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3154 };
3155 static const char *intel_names32[] = {
3156   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3157   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3158 };
3159 static const char *intel_names16[] = {
3160   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3161   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3162 };
3163 static const char *intel_names8[] = {
3164   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3165 };
3166 static const char *intel_names8rex[] = {
3167   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3168   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3169 };
3170 static const char *intel_names_seg[] = {
3171   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3172 };
3173 static const char *intel_index64 = "riz";
3174 static const char *intel_index32 = "eiz";
3175 static const char *intel_index16[] = {
3176   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3177 };
3178
3179 static const char *att_names64[] = {
3180   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3181   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3182 };
3183 static const char *att_names32[] = {
3184   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3185   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3186 };
3187 static const char *att_names16[] = {
3188   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3189   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3190 };
3191 static const char *att_names8[] = {
3192   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3193 };
3194 static const char *att_names8rex[] = {
3195   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3196   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3197 };
3198 static const char *att_names_seg[] = {
3199   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3200 };
3201 static const char *att_index64 = "%riz";
3202 static const char *att_index32 = "%eiz";
3203 static const char *att_index16[] = {
3204   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3205 };
3206
3207 static const char **names_mm;
3208 static const char *intel_names_mm[] = {
3209   "mm0", "mm1", "mm2", "mm3",
3210   "mm4", "mm5", "mm6", "mm7"
3211 };
3212 static const char *att_names_mm[] = {
3213   "%mm0", "%mm1", "%mm2", "%mm3",
3214   "%mm4", "%mm5", "%mm6", "%mm7"
3215 };
3216
3217 static const char *intel_names_bnd[] = {
3218   "bnd0", "bnd1", "bnd2", "bnd3"
3219 };
3220
3221 static const char *att_names_bnd[] = {
3222   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3223 };
3224
3225 static const char **names_xmm;
3226 static const char *intel_names_xmm[] = {
3227   "xmm0", "xmm1", "xmm2", "xmm3",
3228   "xmm4", "xmm5", "xmm6", "xmm7",
3229   "xmm8", "xmm9", "xmm10", "xmm11",
3230   "xmm12", "xmm13", "xmm14", "xmm15",
3231   "xmm16", "xmm17", "xmm18", "xmm19",
3232   "xmm20", "xmm21", "xmm22", "xmm23",
3233   "xmm24", "xmm25", "xmm26", "xmm27",
3234   "xmm28", "xmm29", "xmm30", "xmm31"
3235 };
3236 static const char *att_names_xmm[] = {
3237   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3238   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3239   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3240   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3241   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3242   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3243   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3244   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3245 };
3246
3247 static const char **names_ymm;
3248 static const char *intel_names_ymm[] = {
3249   "ymm0", "ymm1", "ymm2", "ymm3",
3250   "ymm4", "ymm5", "ymm6", "ymm7",
3251   "ymm8", "ymm9", "ymm10", "ymm11",
3252   "ymm12", "ymm13", "ymm14", "ymm15",
3253   "ymm16", "ymm17", "ymm18", "ymm19",
3254   "ymm20", "ymm21", "ymm22", "ymm23",
3255   "ymm24", "ymm25", "ymm26", "ymm27",
3256   "ymm28", "ymm29", "ymm30", "ymm31"
3257 };
3258 static const char *att_names_ymm[] = {
3259   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3260   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3261   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3262   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3263   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3264   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3265   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3266   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3267 };
3268
3269 static const char **names_zmm;
3270 static const char *intel_names_zmm[] = {
3271   "zmm0", "zmm1", "zmm2", "zmm3",
3272   "zmm4", "zmm5", "zmm6", "zmm7",
3273   "zmm8", "zmm9", "zmm10", "zmm11",
3274   "zmm12", "zmm13", "zmm14", "zmm15",
3275   "zmm16", "zmm17", "zmm18", "zmm19",
3276   "zmm20", "zmm21", "zmm22", "zmm23",
3277   "zmm24", "zmm25", "zmm26", "zmm27",
3278   "zmm28", "zmm29", "zmm30", "zmm31"
3279 };
3280 static const char *att_names_zmm[] = {
3281   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3282   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3283   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3284   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3285   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3286   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3287   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3288   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3289 };
3290
3291 static const char **names_mask;
3292 static const char *intel_names_mask[] = {
3293   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3294 };
3295 static const char *att_names_mask[] = {
3296   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3297 };
3298
3299 static const char *names_rounding[] =
3300 {
3301   "{rn-sae}",
3302   "{rd-sae}",
3303   "{ru-sae}",
3304   "{rz-sae}"
3305 };
3306
3307 static const struct dis386 reg_table[][8] = {
3308   /* REG_80 */
3309   {
3310     { "addA",   { Ebh1, Ib }, 0 },
3311     { "orA",    { Ebh1, Ib }, 0 },
3312     { "adcA",   { Ebh1, Ib }, 0 },
3313     { "sbbA",   { Ebh1, Ib }, 0 },
3314     { "andA",   { Ebh1, Ib }, 0 },
3315     { "subA",   { Ebh1, Ib }, 0 },
3316     { "xorA",   { Ebh1, Ib }, 0 },
3317     { "cmpA",   { Eb, Ib }, 0 },
3318   },
3319   /* REG_81 */
3320   {
3321     { "addQ",   { Evh1, Iv }, 0 },
3322     { "orQ",    { Evh1, Iv }, 0 },
3323     { "adcQ",   { Evh1, Iv }, 0 },
3324     { "sbbQ",   { Evh1, Iv }, 0 },
3325     { "andQ",   { Evh1, Iv }, 0 },
3326     { "subQ",   { Evh1, Iv }, 0 },
3327     { "xorQ",   { Evh1, Iv }, 0 },
3328     { "cmpQ",   { Ev, Iv }, 0 },
3329   },
3330   /* REG_82 */
3331   {
3332     { "addQ",   { Evh1, sIb }, 0 },
3333     { "orQ",    { Evh1, sIb }, 0 },
3334     { "adcQ",   { Evh1, sIb }, 0 },
3335     { "sbbQ",   { Evh1, sIb }, 0 },
3336     { "andQ",   { Evh1, sIb }, 0 },
3337     { "subQ",   { Evh1, sIb }, 0 },
3338     { "xorQ",   { Evh1, sIb }, 0 },
3339     { "cmpQ",   { Ev, sIb }, 0 },
3340   },
3341   /* REG_8F */
3342   {
3343     { "popU",   { stackEv }, 0 },
3344     { XOP_8F_TABLE (XOP_09) },
3345     { Bad_Opcode },
3346     { Bad_Opcode },
3347     { Bad_Opcode },
3348     { XOP_8F_TABLE (XOP_09) },
3349   },
3350   /* REG_C0 */
3351   {
3352     { "rolA",   { Eb, Ib }, 0 },
3353     { "rorA",   { Eb, Ib }, 0 },
3354     { "rclA",   { Eb, Ib }, 0 },
3355     { "rcrA",   { Eb, Ib }, 0 },
3356     { "shlA",   { Eb, Ib }, 0 },
3357     { "shrA",   { Eb, Ib }, 0 },
3358     { Bad_Opcode },
3359     { "sarA",   { Eb, Ib }, 0 },
3360   },
3361   /* REG_C1 */
3362   {
3363     { "rolQ",   { Ev, Ib }, 0 },
3364     { "rorQ",   { Ev, Ib }, 0 },
3365     { "rclQ",   { Ev, Ib }, 0 },
3366     { "rcrQ",   { Ev, Ib }, 0 },
3367     { "shlQ",   { Ev, Ib }, 0 },
3368     { "shrQ",   { Ev, Ib }, 0 },
3369     { Bad_Opcode },
3370     { "sarQ",   { Ev, Ib }, 0 },
3371   },
3372   /* REG_C6 */
3373   {
3374     { "movA",   { Ebh3, Ib }, 0 },
3375     { Bad_Opcode },
3376     { Bad_Opcode },
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380     { Bad_Opcode },
3381     { MOD_TABLE (MOD_C6_REG_7) },
3382   },
3383   /* REG_C7 */
3384   {
3385     { "movQ",   { Evh3, Iv }, 0 },
3386     { Bad_Opcode },
3387     { Bad_Opcode },
3388     { Bad_Opcode },
3389     { Bad_Opcode },
3390     { Bad_Opcode },
3391     { Bad_Opcode },
3392     { MOD_TABLE (MOD_C7_REG_7) },
3393   },
3394   /* REG_D0 */
3395   {
3396     { "rolA",   { Eb, I1 }, 0 },
3397     { "rorA",   { Eb, I1 }, 0 },
3398     { "rclA",   { Eb, I1 }, 0 },
3399     { "rcrA",   { Eb, I1 }, 0 },
3400     { "shlA",   { Eb, I1 }, 0 },
3401     { "shrA",   { Eb, I1 }, 0 },
3402     { Bad_Opcode },
3403     { "sarA",   { Eb, I1 }, 0 },
3404   },
3405   /* REG_D1 */
3406   {
3407     { "rolQ",   { Ev, I1 }, 0 },
3408     { "rorQ",   { Ev, I1 }, 0 },
3409     { "rclQ",   { Ev, I1 }, 0 },
3410     { "rcrQ",   { Ev, I1 }, 0 },
3411     { "shlQ",   { Ev, I1 }, 0 },
3412     { "shrQ",   { Ev, I1 }, 0 },
3413     { Bad_Opcode },
3414     { "sarQ",   { Ev, I1 }, 0 },
3415   },
3416   /* REG_D2 */
3417   {
3418     { "rolA",   { Eb, CL }, 0 },
3419     { "rorA",   { Eb, CL }, 0 },
3420     { "rclA",   { Eb, CL }, 0 },
3421     { "rcrA",   { Eb, CL }, 0 },
3422     { "shlA",   { Eb, CL }, 0 },
3423     { "shrA",   { Eb, CL }, 0 },
3424     { Bad_Opcode },
3425     { "sarA",   { Eb, CL }, 0 },
3426   },
3427   /* REG_D3 */
3428   {
3429     { "rolQ",   { Ev, CL }, 0 },
3430     { "rorQ",   { Ev, CL }, 0 },
3431     { "rclQ",   { Ev, CL }, 0 },
3432     { "rcrQ",   { Ev, CL }, 0 },
3433     { "shlQ",   { Ev, CL }, 0 },
3434     { "shrQ",   { Ev, CL }, 0 },
3435     { Bad_Opcode },
3436     { "sarQ",   { Ev, CL }, 0 },
3437   },
3438   /* REG_F6 */
3439   {
3440     { "testA",  { Eb, Ib }, 0 },
3441     { Bad_Opcode },
3442     { "notA",   { Ebh1 }, 0 },
3443     { "negA",   { Ebh1 }, 0 },
3444     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3445     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3446     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3447     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3448   },
3449   /* REG_F7 */
3450   {
3451     { "testQ",  { Ev, Iv }, 0 },
3452     { Bad_Opcode },
3453     { "notQ",   { Evh1 }, 0 },
3454     { "negQ",   { Evh1 }, 0 },
3455     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3456     { "imulQ",  { Ev }, 0 },
3457     { "divQ",   { Ev }, 0 },
3458     { "idivQ",  { Ev }, 0 },
3459   },
3460   /* REG_FE */
3461   {
3462     { "incA",   { Ebh1 }, 0 },
3463     { "decA",   { Ebh1 }, 0 },
3464   },
3465   /* REG_FF */
3466   {
3467     { "incQ",   { Evh1 }, 0 },
3468     { "decQ",   { Evh1 }, 0 },
3469     { "call{T|}", { indirEv, BND }, 0 },
3470     { MOD_TABLE (MOD_FF_REG_3) },
3471     { "jmp{T|}", { indirEv, BND }, 0 },
3472     { MOD_TABLE (MOD_FF_REG_5) },
3473     { "pushU",  { stackEv }, 0 },
3474     { Bad_Opcode },
3475   },
3476   /* REG_0F00 */
3477   {
3478     { "sldtD",  { Sv }, 0 },
3479     { "strD",   { Sv }, 0 },
3480     { "lldt",   { Ew }, 0 },
3481     { "ltr",    { Ew }, 0 },
3482     { "verr",   { Ew }, 0 },
3483     { "verw",   { Ew }, 0 },
3484     { Bad_Opcode },
3485     { Bad_Opcode },
3486   },
3487   /* REG_0F01 */
3488   {
3489     { MOD_TABLE (MOD_0F01_REG_0) },
3490     { MOD_TABLE (MOD_0F01_REG_1) },
3491     { MOD_TABLE (MOD_0F01_REG_2) },
3492     { MOD_TABLE (MOD_0F01_REG_3) },
3493     { "smswD",  { Sv }, 0 },
3494     { Bad_Opcode },
3495     { "lmsw",   { Ew }, 0 },
3496     { MOD_TABLE (MOD_0F01_REG_7) },
3497   },
3498   /* REG_0F0D */
3499   {
3500     { "prefetch",       { Mb }, 0 },
3501     { "prefetchw",      { Mb }, 0 },
3502     { "prefetchwt1",    { Mb }, 0 },
3503     { "prefetch",       { Mb }, 0 },
3504     { "prefetch",       { Mb }, 0 },
3505     { "prefetch",       { Mb }, 0 },
3506     { "prefetch",       { Mb }, 0 },
3507     { "prefetch",       { Mb }, 0 },
3508   },
3509   /* REG_0F18 */
3510   {
3511     { MOD_TABLE (MOD_0F18_REG_0) },
3512     { MOD_TABLE (MOD_0F18_REG_1) },
3513     { MOD_TABLE (MOD_0F18_REG_2) },
3514     { MOD_TABLE (MOD_0F18_REG_3) },
3515     { MOD_TABLE (MOD_0F18_REG_4) },
3516     { MOD_TABLE (MOD_0F18_REG_5) },
3517     { MOD_TABLE (MOD_0F18_REG_6) },
3518     { MOD_TABLE (MOD_0F18_REG_7) },
3519   },
3520   /* REG_0F71 */
3521   {
3522     { Bad_Opcode },
3523     { Bad_Opcode },
3524     { MOD_TABLE (MOD_0F71_REG_2) },
3525     { Bad_Opcode },
3526     { MOD_TABLE (MOD_0F71_REG_4) },
3527     { Bad_Opcode },
3528     { MOD_TABLE (MOD_0F71_REG_6) },
3529   },
3530   /* REG_0F72 */
3531   {
3532     { Bad_Opcode },
3533     { Bad_Opcode },
3534     { MOD_TABLE (MOD_0F72_REG_2) },
3535     { Bad_Opcode },
3536     { MOD_TABLE (MOD_0F72_REG_4) },
3537     { Bad_Opcode },
3538     { MOD_TABLE (MOD_0F72_REG_6) },
3539   },
3540   /* REG_0F73 */
3541   {
3542     { Bad_Opcode },
3543     { Bad_Opcode },
3544     { MOD_TABLE (MOD_0F73_REG_2) },
3545     { MOD_TABLE (MOD_0F73_REG_3) },
3546     { Bad_Opcode },
3547     { Bad_Opcode },
3548     { MOD_TABLE (MOD_0F73_REG_6) },
3549     { MOD_TABLE (MOD_0F73_REG_7) },
3550   },
3551   /* REG_0FA6 */
3552   {
3553     { "montmul",        { { OP_0f07, 0 } }, 0 },
3554     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3555     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3556   },
3557   /* REG_0FA7 */
3558   {
3559     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3560     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3561     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3562     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3563     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3564     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3565   },
3566   /* REG_0FAE */
3567   {
3568     { MOD_TABLE (MOD_0FAE_REG_0) },
3569     { MOD_TABLE (MOD_0FAE_REG_1) },
3570     { MOD_TABLE (MOD_0FAE_REG_2) },
3571     { MOD_TABLE (MOD_0FAE_REG_3) },
3572     { MOD_TABLE (MOD_0FAE_REG_4) },
3573     { MOD_TABLE (MOD_0FAE_REG_5) },
3574     { MOD_TABLE (MOD_0FAE_REG_6) },
3575     { MOD_TABLE (MOD_0FAE_REG_7) },
3576   },
3577   /* REG_0FBA */
3578   {
3579     { Bad_Opcode },
3580     { Bad_Opcode },
3581     { Bad_Opcode },
3582     { Bad_Opcode },
3583     { "btQ",    { Ev, Ib }, 0 },
3584     { "btsQ",   { Evh1, Ib }, 0 },
3585     { "btrQ",   { Evh1, Ib }, 0 },
3586     { "btcQ",   { Evh1, Ib }, 0 },
3587   },
3588   /* REG_0FC7 */
3589   {
3590     { Bad_Opcode },
3591     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3592     { Bad_Opcode },
3593     { MOD_TABLE (MOD_0FC7_REG_3) },
3594     { MOD_TABLE (MOD_0FC7_REG_4) },
3595     { MOD_TABLE (MOD_0FC7_REG_5) },
3596     { MOD_TABLE (MOD_0FC7_REG_6) },
3597     { MOD_TABLE (MOD_0FC7_REG_7) },
3598   },
3599   /* REG_VEX_0F71 */
3600   {
3601     { Bad_Opcode },
3602     { Bad_Opcode },
3603     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3604     { Bad_Opcode },
3605     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3606     { Bad_Opcode },
3607     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3608   },
3609   /* REG_VEX_0F72 */
3610   {
3611     { Bad_Opcode },
3612     { Bad_Opcode },
3613     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3614     { Bad_Opcode },
3615     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3616     { Bad_Opcode },
3617     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3618   },
3619   /* REG_VEX_0F73 */
3620   {
3621     { Bad_Opcode },
3622     { Bad_Opcode },
3623     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3624     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3625     { Bad_Opcode },
3626     { Bad_Opcode },
3627     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3628     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3629   },
3630   /* REG_VEX_0FAE */
3631   {
3632     { Bad_Opcode },
3633     { Bad_Opcode },
3634     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3635     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3636   },
3637   /* REG_VEX_0F38F3 */
3638   {
3639     { Bad_Opcode },
3640     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3641     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3642     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3643   },
3644   /* REG_XOP_LWPCB */
3645   {
3646     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3647     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3648   },
3649   /* REG_XOP_LWP */
3650   {
3651     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3652     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3653   },
3654   /* REG_XOP_TBM_01 */
3655   {
3656     { Bad_Opcode },
3657     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3658     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3659     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3660     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3661     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3662     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3663     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3664   },
3665   /* REG_XOP_TBM_02 */
3666   {
3667     { Bad_Opcode },
3668     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3669     { Bad_Opcode },
3670     { Bad_Opcode },
3671     { Bad_Opcode },
3672     { Bad_Opcode },
3673     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3674   },
3675 #define NEED_REG_TABLE
3676 #include "i386-dis-evex.h"
3677 #undef NEED_REG_TABLE
3678 };
3679
3680 static const struct dis386 prefix_table[][4] = {
3681   /* PREFIX_90 */
3682   {
3683     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3684     { "pause", { XX }, 0 },
3685     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3686     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3687   },
3688
3689   /* PREFIX_0F10 */
3690   {
3691     { "movups", { XM, EXx }, PREFIX_OPCODE },
3692     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3693     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3694     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3695   },
3696
3697   /* PREFIX_0F11 */
3698   {
3699     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3700     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3701     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3702     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3703   },
3704
3705   /* PREFIX_0F12 */
3706   {
3707     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3708     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3709     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3710     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3711   },
3712
3713   /* PREFIX_0F16 */
3714   {
3715     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3716     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3717     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3718   },
3719
3720   /* PREFIX_0F1A */
3721   {
3722     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3723     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3724     { "bndmov", { Gbnd, Ebnd }, 0 },
3725     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3726   },
3727
3728   /* PREFIX_0F1B */
3729   {
3730     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3731     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3732     { "bndmov", { Ebnd, Gbnd }, 0 },
3733     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3734   },
3735
3736   /* PREFIX_0F2A */
3737   {
3738     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3739     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3740     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3741     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3742   },
3743
3744   /* PREFIX_0F2B */
3745   {
3746     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3747     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3748     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3749     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3750   },
3751
3752   /* PREFIX_0F2C */
3753   {
3754     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3755     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3756     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3757     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3758   },
3759
3760   /* PREFIX_0F2D */
3761   {
3762     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3763     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3764     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3765     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3766   },
3767
3768   /* PREFIX_0F2E */
3769   {
3770     { "ucomiss",{ XM, EXd }, 0 },
3771     { Bad_Opcode },
3772     { "ucomisd",{ XM, EXq }, 0 },
3773   },
3774
3775   /* PREFIX_0F2F */
3776   {
3777     { "comiss", { XM, EXd }, 0 },
3778     { Bad_Opcode },
3779     { "comisd", { XM, EXq }, 0 },
3780   },
3781
3782   /* PREFIX_0F51 */
3783   {
3784     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3785     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3786     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3787     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3788   },
3789
3790   /* PREFIX_0F52 */
3791   {
3792     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3793     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3794   },
3795
3796   /* PREFIX_0F53 */
3797   {
3798     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3799     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3800   },
3801
3802   /* PREFIX_0F58 */
3803   {
3804     { "addps", { XM, EXx }, PREFIX_OPCODE },
3805     { "addss", { XM, EXd }, PREFIX_OPCODE },
3806     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3807     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3808   },
3809
3810   /* PREFIX_0F59 */
3811   {
3812     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3813     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3814     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3815     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3816   },
3817
3818   /* PREFIX_0F5A */
3819   {
3820     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3821     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3822     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3823     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3824   },
3825
3826   /* PREFIX_0F5B */
3827   {
3828     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3829     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3830     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3831   },
3832
3833   /* PREFIX_0F5C */
3834   {
3835     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3836     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3837     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3838     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3839   },
3840
3841   /* PREFIX_0F5D */
3842   {
3843     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3844     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3845     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3846     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3847   },
3848
3849   /* PREFIX_0F5E */
3850   {
3851     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3852     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3853     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3854     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3855   },
3856
3857   /* PREFIX_0F5F */
3858   {
3859     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3860     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3861     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3862     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3863   },
3864
3865   /* PREFIX_0F60 */
3866   {
3867     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3868     { Bad_Opcode },
3869     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3870   },
3871
3872   /* PREFIX_0F61 */
3873   {
3874     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3875     { Bad_Opcode },
3876     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3877   },
3878
3879   /* PREFIX_0F62 */
3880   {
3881     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3882     { Bad_Opcode },
3883     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3884   },
3885
3886   /* PREFIX_0F6C */
3887   {
3888     { Bad_Opcode },
3889     { Bad_Opcode },
3890     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3891   },
3892
3893   /* PREFIX_0F6D */
3894   {
3895     { Bad_Opcode },
3896     { Bad_Opcode },
3897     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3898   },
3899
3900   /* PREFIX_0F6F */
3901   {
3902     { "movq",   { MX, EM }, PREFIX_OPCODE },
3903     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3904     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3905   },
3906
3907   /* PREFIX_0F70 */
3908   {
3909     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3910     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3911     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3912     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3913   },
3914
3915   /* PREFIX_0F73_REG_3 */
3916   {
3917     { Bad_Opcode },
3918     { Bad_Opcode },
3919     { "psrldq", { XS, Ib }, 0 },
3920   },
3921
3922   /* PREFIX_0F73_REG_7 */
3923   {
3924     { Bad_Opcode },
3925     { Bad_Opcode },
3926     { "pslldq", { XS, Ib }, 0 },
3927   },
3928
3929   /* PREFIX_0F78 */
3930   {
3931     {"vmread",  { Em, Gm }, 0 },
3932     { Bad_Opcode },
3933     {"extrq",   { XS, Ib, Ib }, 0 },
3934     {"insertq", { XM, XS, Ib, Ib }, 0 },
3935   },
3936
3937   /* PREFIX_0F79 */
3938   {
3939     {"vmwrite", { Gm, Em }, 0 },
3940     { Bad_Opcode },
3941     {"extrq",   { XM, XS }, 0 },
3942     {"insertq", { XM, XS }, 0 },
3943   },
3944
3945   /* PREFIX_0F7C */
3946   {
3947     { Bad_Opcode },
3948     { Bad_Opcode },
3949     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3950     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3951   },
3952
3953   /* PREFIX_0F7D */
3954   {
3955     { Bad_Opcode },
3956     { Bad_Opcode },
3957     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3958     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3959   },
3960
3961   /* PREFIX_0F7E */
3962   {
3963     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3964     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3965     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3966   },
3967
3968   /* PREFIX_0F7F */
3969   {
3970     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3971     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3972     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3973   },
3974
3975   /* PREFIX_0FAE_REG_0 */
3976   {
3977     { Bad_Opcode },
3978     { "rdfsbase", { Ev }, 0 },
3979   },
3980
3981   /* PREFIX_0FAE_REG_1 */
3982   {
3983     { Bad_Opcode },
3984     { "rdgsbase", { Ev }, 0 },
3985   },
3986
3987   /* PREFIX_0FAE_REG_2 */
3988   {
3989     { Bad_Opcode },
3990     { "wrfsbase", { Ev }, 0 },
3991   },
3992
3993   /* PREFIX_0FAE_REG_3 */
3994   {
3995     { Bad_Opcode },
3996     { "wrgsbase", { Ev }, 0 },
3997   },
3998
3999   /* PREFIX_0FAE_REG_6 */
4000   {
4001     { "xsaveopt",      { FXSAVE }, 0 },
4002     { Bad_Opcode },
4003     { "clwb",   { Mb }, 0 },
4004   },
4005
4006   /* PREFIX_0FAE_REG_7 */
4007   {
4008     { "clflush",        { Mb }, 0 },
4009     { Bad_Opcode },
4010     { "clflushopt",     { Mb }, 0 },
4011   },
4012
4013   /* PREFIX_RM_0_0FAE_REG_7 */
4014   {
4015     { "sfence",         { Skip_MODRM }, 0 },
4016     { Bad_Opcode },
4017     { "pcommit",                { Skip_MODRM }, 0 },
4018   },
4019
4020   /* PREFIX_0FB8 */
4021   {
4022     { Bad_Opcode },
4023     { "popcntS", { Gv, Ev }, 0 },
4024   },
4025
4026   /* PREFIX_0FBC */
4027   {
4028     { "bsfS",   { Gv, Ev }, 0 },
4029     { "tzcntS", { Gv, Ev }, 0 },
4030     { "bsfS",   { Gv, Ev }, 0 },
4031   },
4032
4033   /* PREFIX_0FBD */
4034   {
4035     { "bsrS",   { Gv, Ev }, 0 },
4036     { "lzcntS", { Gv, Ev }, 0 },
4037     { "bsrS",   { Gv, Ev }, 0 },
4038   },
4039
4040   /* PREFIX_0FC2 */
4041   {
4042     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4043     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4044     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4045     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4046   },
4047
4048   /* PREFIX_0FC3 */
4049   {
4050     { "movntiS", { Ma, Gv }, PREFIX_OPCODE },
4051   },
4052
4053   /* PREFIX_MOD_0_0FC7_REG_6 */
4054   {
4055     { "vmptrld",{ Mq }, 0 },
4056     { "vmxon",  { Mq }, 0 },
4057     { "vmclear",{ Mq }, 0 },
4058   },
4059
4060   /* PREFIX_MOD_3_0FC7_REG_6 */
4061   {
4062     { "rdrand", { Ev }, 0 },
4063     { Bad_Opcode },
4064     { "rdrand", { Ev }, 0 }
4065   },
4066
4067   /* PREFIX_MOD_3_0FC7_REG_7 */
4068   {
4069     { "rdseed", { Ev }, 0 },
4070     { Bad_Opcode },
4071     { "rdseed", { Ev }, 0 },
4072   },
4073
4074   /* PREFIX_0FD0 */
4075   {
4076     { Bad_Opcode },
4077     { Bad_Opcode },
4078     { "addsubpd", { XM, EXx }, 0 },
4079     { "addsubps", { XM, EXx }, 0 },
4080   },
4081
4082   /* PREFIX_0FD6 */
4083   {
4084     { Bad_Opcode },
4085     { "movq2dq",{ XM, MS }, 0 },
4086     { "movq",   { EXqS, XM }, 0 },
4087     { "movdq2q",{ MX, XS }, 0 },
4088   },
4089
4090   /* PREFIX_0FE6 */
4091   {
4092     { Bad_Opcode },
4093     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4094     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4095     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4096   },
4097
4098   /* PREFIX_0FE7 */
4099   {
4100     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4101     { Bad_Opcode },
4102     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4103   },
4104
4105   /* PREFIX_0FF0 */
4106   {
4107     { Bad_Opcode },
4108     { Bad_Opcode },
4109     { Bad_Opcode },
4110     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4111   },
4112
4113   /* PREFIX_0FF7 */
4114   {
4115     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4116     { Bad_Opcode },
4117     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4118   },
4119
4120   /* PREFIX_0F3810 */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4125   },
4126
4127   /* PREFIX_0F3814 */
4128   {
4129     { Bad_Opcode },
4130     { Bad_Opcode },
4131     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4132   },
4133
4134   /* PREFIX_0F3815 */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4139   },
4140
4141   /* PREFIX_0F3817 */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4146   },
4147
4148   /* PREFIX_0F3820 */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4153   },
4154
4155   /* PREFIX_0F3821 */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4160   },
4161
4162   /* PREFIX_0F3822 */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4167   },
4168
4169   /* PREFIX_0F3823 */
4170   {
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4174   },
4175
4176   /* PREFIX_0F3824 */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4181   },
4182
4183   /* PREFIX_0F3825 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4188   },
4189
4190   /* PREFIX_0F3828 */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4195   },
4196
4197   /* PREFIX_0F3829 */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4202   },
4203
4204   /* PREFIX_0F382A */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4209   },
4210
4211   /* PREFIX_0F382B */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4216   },
4217
4218   /* PREFIX_0F3830 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4223   },
4224
4225   /* PREFIX_0F3831 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4230   },
4231
4232   /* PREFIX_0F3832 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4237   },
4238
4239   /* PREFIX_0F3833 */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4244   },
4245
4246   /* PREFIX_0F3834 */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4251   },
4252
4253   /* PREFIX_0F3835 */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4258   },
4259
4260   /* PREFIX_0F3837 */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4265   },
4266
4267   /* PREFIX_0F3838 */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4272   },
4273
4274   /* PREFIX_0F3839 */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4279   },
4280
4281   /* PREFIX_0F383A */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4286   },
4287
4288   /* PREFIX_0F383B */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4293   },
4294
4295   /* PREFIX_0F383C */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4300   },
4301
4302   /* PREFIX_0F383D */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4307   },
4308
4309   /* PREFIX_0F383E */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4314   },
4315
4316   /* PREFIX_0F383F */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4321   },
4322
4323   /* PREFIX_0F3840 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4328   },
4329
4330   /* PREFIX_0F3841 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4335   },
4336
4337   /* PREFIX_0F3880 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F3881 */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4349   },
4350
4351   /* PREFIX_0F3882 */
4352   {
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4356   },
4357
4358   /* PREFIX_0F38C8 */
4359   {
4360     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4361   },
4362
4363   /* PREFIX_0F38C9 */
4364   {
4365     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4366   },
4367
4368   /* PREFIX_0F38CA */
4369   {
4370     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4371   },
4372
4373   /* PREFIX_0F38CB */
4374   {
4375     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F38CC */
4379   {
4380     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4381   },
4382
4383   /* PREFIX_0F38CD */
4384   {
4385     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F38DB */
4389   {
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4393   },
4394
4395   /* PREFIX_0F38DC */
4396   {
4397     { Bad_Opcode },
4398     { Bad_Opcode },
4399     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4400   },
4401
4402   /* PREFIX_0F38DD */
4403   {
4404     { Bad_Opcode },
4405     { Bad_Opcode },
4406     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4407   },
4408
4409   /* PREFIX_0F38DE */
4410   {
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4414   },
4415
4416   /* PREFIX_0F38DF */
4417   {
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4421   },
4422
4423   /* PREFIX_0F38F0 */
4424   {
4425     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4426     { Bad_Opcode },
4427     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4428     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4429   },
4430
4431   /* PREFIX_0F38F1 */
4432   {
4433     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4434     { Bad_Opcode },
4435     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4436     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4437   },
4438
4439   /* PREFIX_0F38F6 */
4440   {
4441     { Bad_Opcode },
4442     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4443     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4444     { Bad_Opcode },
4445   },
4446
4447   /* PREFIX_0F3A08 */
4448   {
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4452   },
4453
4454   /* PREFIX_0F3A09 */
4455   {
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4459   },
4460
4461   /* PREFIX_0F3A0A */
4462   {
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4466   },
4467
4468   /* PREFIX_0F3A0B */
4469   {
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4473   },
4474
4475   /* PREFIX_0F3A0C */
4476   {
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4480   },
4481
4482   /* PREFIX_0F3A0D */
4483   {
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4487   },
4488
4489   /* PREFIX_0F3A0E */
4490   {
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4494   },
4495
4496   /* PREFIX_0F3A14 */
4497   {
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4501   },
4502
4503   /* PREFIX_0F3A15 */
4504   {
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4508   },
4509
4510   /* PREFIX_0F3A16 */
4511   {
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F3A17 */
4518   {
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4522   },
4523
4524   /* PREFIX_0F3A20 */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F3A21 */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F3A22 */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F3A40 */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F3A41 */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3A42 */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3A44 */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3A60 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F3A61 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F3A62 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F3A63 */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F3ACC */
4602   {
4603     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4604   },
4605
4606   /* PREFIX_0F3ADF */
4607   {
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4611   },
4612
4613   /* PREFIX_VEX_0F10 */
4614   {
4615     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4616     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4617     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4618     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4619   },
4620
4621   /* PREFIX_VEX_0F11 */
4622   {
4623     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4624     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4625     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4626     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4627   },
4628
4629   /* PREFIX_VEX_0F12 */
4630   {
4631     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4632     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4633     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4634     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4635   },
4636
4637   /* PREFIX_VEX_0F16 */
4638   {
4639     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4640     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4641     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4642   },
4643
4644   /* PREFIX_VEX_0F2A */
4645   {
4646     { Bad_Opcode },
4647     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4648     { Bad_Opcode },
4649     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4650   },
4651
4652   /* PREFIX_VEX_0F2C */
4653   {
4654     { Bad_Opcode },
4655     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4656     { Bad_Opcode },
4657     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4658   },
4659
4660   /* PREFIX_VEX_0F2D */
4661   {
4662     { Bad_Opcode },
4663     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4664     { Bad_Opcode },
4665     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4666   },
4667
4668   /* PREFIX_VEX_0F2E */
4669   {
4670     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4671     { Bad_Opcode },
4672     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4673   },
4674
4675   /* PREFIX_VEX_0F2F */
4676   {
4677     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4678     { Bad_Opcode },
4679     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4680   },
4681
4682   /* PREFIX_VEX_0F41 */
4683   {
4684     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4685     { Bad_Opcode },
4686     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4687   },
4688
4689   /* PREFIX_VEX_0F42 */
4690   {
4691     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4692     { Bad_Opcode },
4693     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4694   },
4695
4696   /* PREFIX_VEX_0F44 */
4697   {
4698     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4699     { Bad_Opcode },
4700     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4701   },
4702
4703   /* PREFIX_VEX_0F45 */
4704   {
4705     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4706     { Bad_Opcode },
4707     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4708   },
4709
4710   /* PREFIX_VEX_0F46 */
4711   {
4712     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4713     { Bad_Opcode },
4714     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4715   },
4716
4717   /* PREFIX_VEX_0F47 */
4718   {
4719     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4720     { Bad_Opcode },
4721     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4722   },
4723
4724   /* PREFIX_VEX_0F4A */
4725   {
4726     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4727     { Bad_Opcode },
4728     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4729   },
4730
4731   /* PREFIX_VEX_0F4B */
4732   {
4733     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4734     { Bad_Opcode },
4735     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4736   },
4737
4738   /* PREFIX_VEX_0F51 */
4739   {
4740     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4741     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4742     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4743     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4744   },
4745
4746   /* PREFIX_VEX_0F52 */
4747   {
4748     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4749     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4750   },
4751
4752   /* PREFIX_VEX_0F53 */
4753   {
4754     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4755     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4756   },
4757
4758   /* PREFIX_VEX_0F58 */
4759   {
4760     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4761     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4762     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4763     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4764   },
4765
4766   /* PREFIX_VEX_0F59 */
4767   {
4768     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4769     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4770     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4771     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4772   },
4773
4774   /* PREFIX_VEX_0F5A */
4775   {
4776     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4777     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4778     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4779     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4780   },
4781
4782   /* PREFIX_VEX_0F5B */
4783   {
4784     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4785     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4786     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4787   },
4788
4789   /* PREFIX_VEX_0F5C */
4790   {
4791     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4792     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4793     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4794     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4795   },
4796
4797   /* PREFIX_VEX_0F5D */
4798   {
4799     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4800     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4801     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4802     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4803   },
4804
4805   /* PREFIX_VEX_0F5E */
4806   {
4807     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4808     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4809     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4810     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4811   },
4812
4813   /* PREFIX_VEX_0F5F */
4814   {
4815     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4816     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4817     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4818     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4819   },
4820
4821   /* PREFIX_VEX_0F60 */
4822   {
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4826   },
4827
4828   /* PREFIX_VEX_0F61 */
4829   {
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4833   },
4834
4835   /* PREFIX_VEX_0F62 */
4836   {
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4840   },
4841
4842   /* PREFIX_VEX_0F63 */
4843   {
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4847   },
4848
4849   /* PREFIX_VEX_0F64 */
4850   {
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4854   },
4855
4856   /* PREFIX_VEX_0F65 */
4857   {
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4861   },
4862
4863   /* PREFIX_VEX_0F66 */
4864   {
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4868   },
4869
4870   /* PREFIX_VEX_0F67 */
4871   {
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4875   },
4876
4877   /* PREFIX_VEX_0F68 */
4878   {
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4882   },
4883
4884   /* PREFIX_VEX_0F69 */
4885   {
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4889   },
4890
4891   /* PREFIX_VEX_0F6A */
4892   {
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4896   },
4897
4898   /* PREFIX_VEX_0F6B */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4903   },
4904
4905   /* PREFIX_VEX_0F6C */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4910   },
4911
4912   /* PREFIX_VEX_0F6D */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4917   },
4918
4919   /* PREFIX_VEX_0F6E */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4924   },
4925
4926   /* PREFIX_VEX_0F6F */
4927   {
4928     { Bad_Opcode },
4929     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4930     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4931   },
4932
4933   /* PREFIX_VEX_0F70 */
4934   {
4935     { Bad_Opcode },
4936     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4937     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4938     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4939   },
4940
4941   /* PREFIX_VEX_0F71_REG_2 */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4946   },
4947
4948   /* PREFIX_VEX_0F71_REG_4 */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4953   },
4954
4955   /* PREFIX_VEX_0F71_REG_6 */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4960   },
4961
4962   /* PREFIX_VEX_0F72_REG_2 */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4967   },
4968
4969   /* PREFIX_VEX_0F72_REG_4 */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4974   },
4975
4976   /* PREFIX_VEX_0F72_REG_6 */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4981   },
4982
4983   /* PREFIX_VEX_0F73_REG_2 */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4988   },
4989
4990   /* PREFIX_VEX_0F73_REG_3 */
4991   {
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4995   },
4996
4997   /* PREFIX_VEX_0F73_REG_6 */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5002   },
5003
5004   /* PREFIX_VEX_0F73_REG_7 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5009   },
5010
5011   /* PREFIX_VEX_0F74 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5016   },
5017
5018   /* PREFIX_VEX_0F75 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5023   },
5024
5025   /* PREFIX_VEX_0F76 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5030   },
5031
5032   /* PREFIX_VEX_0F77 */
5033   {
5034     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5035   },
5036
5037   /* PREFIX_VEX_0F7C */
5038   {
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5042     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5043   },
5044
5045   /* PREFIX_VEX_0F7D */
5046   {
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5050     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5051   },
5052
5053   /* PREFIX_VEX_0F7E */
5054   {
5055     { Bad_Opcode },
5056     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5057     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5058   },
5059
5060   /* PREFIX_VEX_0F7F */
5061   {
5062     { Bad_Opcode },
5063     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5064     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5065   },
5066
5067   /* PREFIX_VEX_0F90 */
5068   {
5069     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5070     { Bad_Opcode },
5071     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5072   },
5073
5074   /* PREFIX_VEX_0F91 */
5075   {
5076     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5077     { Bad_Opcode },
5078     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5079   },
5080
5081   /* PREFIX_VEX_0F92 */
5082   {
5083     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5084     { Bad_Opcode },
5085     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5086     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5087   },
5088
5089   /* PREFIX_VEX_0F93 */
5090   {
5091     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5092     { Bad_Opcode },
5093     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5094     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5095   },
5096
5097   /* PREFIX_VEX_0F98 */
5098   {
5099     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5100     { Bad_Opcode },
5101     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5102   },
5103
5104   /* PREFIX_VEX_0F99 */
5105   {
5106     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5107     { Bad_Opcode },
5108     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5109   },
5110
5111   /* PREFIX_VEX_0FC2 */
5112   {
5113     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5114     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5115     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5116     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5117   },
5118
5119   /* PREFIX_VEX_0FC4 */
5120   {
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5124   },
5125
5126   /* PREFIX_VEX_0FC5 */
5127   {
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5131   },
5132
5133   /* PREFIX_VEX_0FD0 */
5134   {
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5138     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5139   },
5140
5141   /* PREFIX_VEX_0FD1 */
5142   {
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5146   },
5147
5148   /* PREFIX_VEX_0FD2 */
5149   {
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5153   },
5154
5155   /* PREFIX_VEX_0FD3 */
5156   {
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5160   },
5161
5162   /* PREFIX_VEX_0FD4 */
5163   {
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5167   },
5168
5169   /* PREFIX_VEX_0FD5 */
5170   {
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5174   },
5175
5176   /* PREFIX_VEX_0FD6 */
5177   {
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5181   },
5182
5183   /* PREFIX_VEX_0FD7 */
5184   {
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5188   },
5189
5190   /* PREFIX_VEX_0FD8 */
5191   {
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5195   },
5196
5197   /* PREFIX_VEX_0FD9 */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5202   },
5203
5204   /* PREFIX_VEX_0FDA */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5209   },
5210
5211   /* PREFIX_VEX_0FDB */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5216   },
5217
5218   /* PREFIX_VEX_0FDC */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5223   },
5224
5225   /* PREFIX_VEX_0FDD */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5230   },
5231
5232   /* PREFIX_VEX_0FDE */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5237   },
5238
5239   /* PREFIX_VEX_0FDF */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5244   },
5245
5246   /* PREFIX_VEX_0FE0 */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5251   },
5252
5253   /* PREFIX_VEX_0FE1 */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5258   },
5259
5260   /* PREFIX_VEX_0FE2 */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5265   },
5266
5267   /* PREFIX_VEX_0FE3 */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5272   },
5273
5274   /* PREFIX_VEX_0FE4 */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5279   },
5280
5281   /* PREFIX_VEX_0FE5 */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5286   },
5287
5288   /* PREFIX_VEX_0FE6 */
5289   {
5290     { Bad_Opcode },
5291     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5292     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5293     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5294   },
5295
5296   /* PREFIX_VEX_0FE7 */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5301   },
5302
5303   /* PREFIX_VEX_0FE8 */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5308   },
5309
5310   /* PREFIX_VEX_0FE9 */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5315   },
5316
5317   /* PREFIX_VEX_0FEA */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5322   },
5323
5324   /* PREFIX_VEX_0FEB */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5329   },
5330
5331   /* PREFIX_VEX_0FEC */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5336   },
5337
5338   /* PREFIX_VEX_0FED */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5343   },
5344
5345   /* PREFIX_VEX_0FEE */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5350   },
5351
5352   /* PREFIX_VEX_0FEF */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5357   },
5358
5359   /* PREFIX_VEX_0FF0 */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5365   },
5366
5367   /* PREFIX_VEX_0FF1 */
5368   {
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5372   },
5373
5374   /* PREFIX_VEX_0FF2 */
5375   {
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5379   },
5380
5381   /* PREFIX_VEX_0FF3 */
5382   {
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5386   },
5387
5388   /* PREFIX_VEX_0FF4 */
5389   {
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5393   },
5394
5395   /* PREFIX_VEX_0FF5 */
5396   {
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5400   },
5401
5402   /* PREFIX_VEX_0FF6 */
5403   {
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5407   },
5408
5409   /* PREFIX_VEX_0FF7 */
5410   {
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5414   },
5415
5416   /* PREFIX_VEX_0FF8 */
5417   {
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5421   },
5422
5423   /* PREFIX_VEX_0FF9 */
5424   {
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5428   },
5429
5430   /* PREFIX_VEX_0FFA */
5431   {
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5435   },
5436
5437   /* PREFIX_VEX_0FFB */
5438   {
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5442   },
5443
5444   /* PREFIX_VEX_0FFC */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5449   },
5450
5451   /* PREFIX_VEX_0FFD */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5456   },
5457
5458   /* PREFIX_VEX_0FFE */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5463   },
5464
5465   /* PREFIX_VEX_0F3800 */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5470   },
5471
5472   /* PREFIX_VEX_0F3801 */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5477   },
5478
5479   /* PREFIX_VEX_0F3802 */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5484   },
5485
5486   /* PREFIX_VEX_0F3803 */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5491   },
5492
5493   /* PREFIX_VEX_0F3804 */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5498   },
5499
5500   /* PREFIX_VEX_0F3805 */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5505   },
5506
5507   /* PREFIX_VEX_0F3806 */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5512   },
5513
5514   /* PREFIX_VEX_0F3807 */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5519   },
5520
5521   /* PREFIX_VEX_0F3808 */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5526   },
5527
5528   /* PREFIX_VEX_0F3809 */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5533   },
5534
5535   /* PREFIX_VEX_0F380A */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5540   },
5541
5542   /* PREFIX_VEX_0F380B */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5547   },
5548
5549   /* PREFIX_VEX_0F380C */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5554   },
5555
5556   /* PREFIX_VEX_0F380D */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5561   },
5562
5563   /* PREFIX_VEX_0F380E */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5568   },
5569
5570   /* PREFIX_VEX_0F380F */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5575   },
5576
5577   /* PREFIX_VEX_0F3813 */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5582   },
5583
5584   /* PREFIX_VEX_0F3816 */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0F3817 */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5596   },
5597
5598   /* PREFIX_VEX_0F3818 */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5603   },
5604
5605   /* PREFIX_VEX_0F3819 */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F381A */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5617   },
5618
5619   /* PREFIX_VEX_0F381C */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F381D */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F381E */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5638   },
5639
5640   /* PREFIX_VEX_0F3820 */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5645   },
5646
5647   /* PREFIX_VEX_0F3821 */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5652   },
5653
5654   /* PREFIX_VEX_0F3822 */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5659   },
5660
5661   /* PREFIX_VEX_0F3823 */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5666   },
5667
5668   /* PREFIX_VEX_0F3824 */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5673   },
5674
5675   /* PREFIX_VEX_0F3825 */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5680   },
5681
5682   /* PREFIX_VEX_0F3828 */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5687   },
5688
5689   /* PREFIX_VEX_0F3829 */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5694   },
5695
5696   /* PREFIX_VEX_0F382A */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5701   },
5702
5703   /* PREFIX_VEX_0F382B */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5708   },
5709
5710   /* PREFIX_VEX_0F382C */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5715   },
5716
5717   /* PREFIX_VEX_0F382D */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5722   },
5723
5724   /* PREFIX_VEX_0F382E */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5729   },
5730
5731   /* PREFIX_VEX_0F382F */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5736   },
5737
5738   /* PREFIX_VEX_0F3830 */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5743   },
5744
5745   /* PREFIX_VEX_0F3831 */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5750   },
5751
5752   /* PREFIX_VEX_0F3832 */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5757   },
5758
5759   /* PREFIX_VEX_0F3833 */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5764   },
5765
5766   /* PREFIX_VEX_0F3834 */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5771   },
5772
5773   /* PREFIX_VEX_0F3835 */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5778   },
5779
5780   /* PREFIX_VEX_0F3836 */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5785   },
5786
5787   /* PREFIX_VEX_0F3837 */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5792   },
5793
5794   /* PREFIX_VEX_0F3838 */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5799   },
5800
5801   /* PREFIX_VEX_0F3839 */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5806   },
5807
5808   /* PREFIX_VEX_0F383A */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5813   },
5814
5815   /* PREFIX_VEX_0F383B */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5820   },
5821
5822   /* PREFIX_VEX_0F383C */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5827   },
5828
5829   /* PREFIX_VEX_0F383D */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5834   },
5835
5836   /* PREFIX_VEX_0F383E */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5841   },
5842
5843   /* PREFIX_VEX_0F383F */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5848   },
5849
5850   /* PREFIX_VEX_0F3840 */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5855   },
5856
5857   /* PREFIX_VEX_0F3841 */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5862   },
5863
5864   /* PREFIX_VEX_0F3845 */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5869   },
5870
5871   /* PREFIX_VEX_0F3846 */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5876   },
5877
5878   /* PREFIX_VEX_0F3847 */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5883   },
5884
5885   /* PREFIX_VEX_0F3858 */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5890   },
5891
5892   /* PREFIX_VEX_0F3859 */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5897   },
5898
5899   /* PREFIX_VEX_0F385A */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5904   },
5905
5906   /* PREFIX_VEX_0F3878 */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5911   },
5912
5913   /* PREFIX_VEX_0F3879 */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F388C */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5925   },
5926
5927   /* PREFIX_VEX_0F388E */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5932   },
5933
5934   /* PREFIX_VEX_0F3890 */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5939   },
5940
5941   /* PREFIX_VEX_0F3891 */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5946   },
5947
5948   /* PREFIX_VEX_0F3892 */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5953   },
5954
5955   /* PREFIX_VEX_0F3893 */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5960   },
5961
5962   /* PREFIX_VEX_0F3896 */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5967   },
5968
5969   /* PREFIX_VEX_0F3897 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5974   },
5975
5976   /* PREFIX_VEX_0F3898 */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
5981   },
5982
5983   /* PREFIX_VEX_0F3899 */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5988   },
5989
5990   /* PREFIX_VEX_0F389A */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5995   },
5996
5997   /* PREFIX_VEX_0F389B */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6002   },
6003
6004   /* PREFIX_VEX_0F389C */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6009   },
6010
6011   /* PREFIX_VEX_0F389D */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6016   },
6017
6018   /* PREFIX_VEX_0F389E */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6023   },
6024
6025   /* PREFIX_VEX_0F389F */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6030   },
6031
6032   /* PREFIX_VEX_0F38A6 */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6037     { Bad_Opcode },
6038   },
6039
6040   /* PREFIX_VEX_0F38A7 */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6045   },
6046
6047   /* PREFIX_VEX_0F38A8 */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6052   },
6053
6054   /* PREFIX_VEX_0F38A9 */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6059   },
6060
6061   /* PREFIX_VEX_0F38AA */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6066   },
6067
6068   /* PREFIX_VEX_0F38AB */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6073   },
6074
6075   /* PREFIX_VEX_0F38AC */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6080   },
6081
6082   /* PREFIX_VEX_0F38AD */
6083   {
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6087   },
6088
6089   /* PREFIX_VEX_0F38AE */
6090   {
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6094   },
6095
6096   /* PREFIX_VEX_0F38AF */
6097   {
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6101   },
6102
6103   /* PREFIX_VEX_0F38B6 */
6104   {
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6108   },
6109
6110   /* PREFIX_VEX_0F38B7 */
6111   {
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6115   },
6116
6117   /* PREFIX_VEX_0F38B8 */
6118   {
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6122   },
6123
6124   /* PREFIX_VEX_0F38B9 */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6129   },
6130
6131   /* PREFIX_VEX_0F38BA */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6136   },
6137
6138   /* PREFIX_VEX_0F38BB */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6143   },
6144
6145   /* PREFIX_VEX_0F38BC */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6150   },
6151
6152   /* PREFIX_VEX_0F38BD */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6157   },
6158
6159   /* PREFIX_VEX_0F38BE */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6164   },
6165
6166   /* PREFIX_VEX_0F38BF */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6171   },
6172
6173   /* PREFIX_VEX_0F38DB */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6178   },
6179
6180   /* PREFIX_VEX_0F38DC */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6185   },
6186
6187   /* PREFIX_VEX_0F38DD */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6192   },
6193
6194   /* PREFIX_VEX_0F38DE */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6199   },
6200
6201   /* PREFIX_VEX_0F38DF */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6206   },
6207
6208   /* PREFIX_VEX_0F38F2 */
6209   {
6210     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6211   },
6212
6213   /* PREFIX_VEX_0F38F3_REG_1 */
6214   {
6215     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6216   },
6217
6218   /* PREFIX_VEX_0F38F3_REG_2 */
6219   {
6220     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6221   },
6222
6223   /* PREFIX_VEX_0F38F3_REG_3 */
6224   {
6225     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6226   },
6227
6228   /* PREFIX_VEX_0F38F5 */
6229   {
6230     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6231     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6232     { Bad_Opcode },
6233     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6234   },
6235
6236   /* PREFIX_VEX_0F38F6 */
6237   {
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6242   },
6243
6244   /* PREFIX_VEX_0F38F7 */
6245   {
6246     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6247     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6248     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6249     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6250   },
6251
6252   /* PREFIX_VEX_0F3A00 */
6253   {
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6257   },
6258
6259   /* PREFIX_VEX_0F3A01 */
6260   {
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6264   },
6265
6266   /* PREFIX_VEX_0F3A02 */
6267   {
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6271   },
6272
6273   /* PREFIX_VEX_0F3A04 */
6274   {
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6278   },
6279
6280   /* PREFIX_VEX_0F3A05 */
6281   {
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6285   },
6286
6287   /* PREFIX_VEX_0F3A06 */
6288   {
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6292   },
6293
6294   /* PREFIX_VEX_0F3A08 */
6295   {
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6299   },
6300
6301   /* PREFIX_VEX_0F3A09 */
6302   {
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6306   },
6307
6308   /* PREFIX_VEX_0F3A0A */
6309   {
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6313   },
6314
6315   /* PREFIX_VEX_0F3A0B */
6316   {
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6320   },
6321
6322   /* PREFIX_VEX_0F3A0C */
6323   {
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6327   },
6328
6329   /* PREFIX_VEX_0F3A0D */
6330   {
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6334   },
6335
6336   /* PREFIX_VEX_0F3A0E */
6337   {
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6341   },
6342
6343   /* PREFIX_VEX_0F3A0F */
6344   {
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6348   },
6349
6350   /* PREFIX_VEX_0F3A14 */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6355   },
6356
6357   /* PREFIX_VEX_0F3A15 */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6362   },
6363
6364   /* PREFIX_VEX_0F3A16 */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6369   },
6370
6371   /* PREFIX_VEX_0F3A17 */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6376   },
6377
6378   /* PREFIX_VEX_0F3A18 */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6383   },
6384
6385   /* PREFIX_VEX_0F3A19 */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6390   },
6391
6392   /* PREFIX_VEX_0F3A1D */
6393   {
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6397   },
6398
6399   /* PREFIX_VEX_0F3A20 */
6400   {
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6404   },
6405
6406   /* PREFIX_VEX_0F3A21 */
6407   {
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6411   },
6412
6413   /* PREFIX_VEX_0F3A22 */
6414   {
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6418   },
6419
6420   /* PREFIX_VEX_0F3A30 */
6421   {
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6425   },
6426
6427   /* PREFIX_VEX_0F3A31 */
6428   {
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6432   },
6433
6434   /* PREFIX_VEX_0F3A32 */
6435   {
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6439   },
6440
6441   /* PREFIX_VEX_0F3A33 */
6442   {
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6446   },
6447
6448   /* PREFIX_VEX_0F3A38 */
6449   {
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6453   },
6454
6455   /* PREFIX_VEX_0F3A39 */
6456   {
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6460   },
6461
6462   /* PREFIX_VEX_0F3A40 */
6463   {
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6467   },
6468
6469   /* PREFIX_VEX_0F3A41 */
6470   {
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6474   },
6475
6476   /* PREFIX_VEX_0F3A42 */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6481   },
6482
6483   /* PREFIX_VEX_0F3A44 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A46 */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6495   },
6496
6497   /* PREFIX_VEX_0F3A48 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6502   },
6503
6504   /* PREFIX_VEX_0F3A49 */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6509   },
6510
6511   /* PREFIX_VEX_0F3A4A */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6516   },
6517
6518   /* PREFIX_VEX_0F3A4B */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6523   },
6524
6525   /* PREFIX_VEX_0F3A4C */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6530   },
6531
6532   /* PREFIX_VEX_0F3A5C */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6537   },
6538
6539   /* PREFIX_VEX_0F3A5D */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6544   },
6545
6546   /* PREFIX_VEX_0F3A5E */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6551   },
6552
6553   /* PREFIX_VEX_0F3A5F */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6558   },
6559
6560   /* PREFIX_VEX_0F3A60 */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6565     { Bad_Opcode },
6566   },
6567
6568   /* PREFIX_VEX_0F3A61 */
6569   {
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6573   },
6574
6575   /* PREFIX_VEX_0F3A62 */
6576   {
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6580   },
6581
6582   /* PREFIX_VEX_0F3A63 */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6587   },
6588
6589   /* PREFIX_VEX_0F3A68 */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6594   },
6595
6596   /* PREFIX_VEX_0F3A69 */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6601   },
6602
6603   /* PREFIX_VEX_0F3A6A */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6608   },
6609
6610   /* PREFIX_VEX_0F3A6B */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6615   },
6616
6617   /* PREFIX_VEX_0F3A6C */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6622   },
6623
6624   /* PREFIX_VEX_0F3A6D */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6629   },
6630
6631   /* PREFIX_VEX_0F3A6E */
6632   {
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6636   },
6637
6638   /* PREFIX_VEX_0F3A6F */
6639   {
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6643   },
6644
6645   /* PREFIX_VEX_0F3A78 */
6646   {
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6650   },
6651
6652   /* PREFIX_VEX_0F3A79 */
6653   {
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6657   },
6658
6659   /* PREFIX_VEX_0F3A7A */
6660   {
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6664   },
6665
6666   /* PREFIX_VEX_0F3A7B */
6667   {
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6671   },
6672
6673   /* PREFIX_VEX_0F3A7C */
6674   {
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6678     { Bad_Opcode },
6679   },
6680
6681   /* PREFIX_VEX_0F3A7D */
6682   {
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6686   },
6687
6688   /* PREFIX_VEX_0F3A7E */
6689   {
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6693   },
6694
6695   /* PREFIX_VEX_0F3A7F */
6696   {
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6700   },
6701
6702   /* PREFIX_VEX_0F3ADF */
6703   {
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6707   },
6708
6709   /* PREFIX_VEX_0F3AF0 */
6710   {
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6715   },
6716
6717 #define NEED_PREFIX_TABLE
6718 #include "i386-dis-evex.h"
6719 #undef NEED_PREFIX_TABLE
6720 };
6721
6722 static const struct dis386 x86_64_table[][2] = {
6723   /* X86_64_06 */
6724   {
6725     { "pushP", { es }, 0 },
6726   },
6727
6728   /* X86_64_07 */
6729   {
6730     { "popP", { es }, 0 },
6731   },
6732
6733   /* X86_64_0D */
6734   {
6735     { "pushP", { cs }, 0 },
6736   },
6737
6738   /* X86_64_16 */
6739   {
6740     { "pushP", { ss }, 0 },
6741   },
6742
6743   /* X86_64_17 */
6744   {
6745     { "popP", { ss }, 0 },
6746   },
6747
6748   /* X86_64_1E */
6749   {
6750     { "pushP", { ds }, 0 },
6751   },
6752
6753   /* X86_64_1F */
6754   {
6755     { "popP", { ds }, 0 },
6756   },
6757
6758   /* X86_64_27 */
6759   {
6760     { "daa", { XX }, 0 },
6761   },
6762
6763   /* X86_64_2F */
6764   {
6765     { "das", { XX }, 0 },
6766   },
6767
6768   /* X86_64_37 */
6769   {
6770     { "aaa", { XX }, 0 },
6771   },
6772
6773   /* X86_64_3F */
6774   {
6775     { "aas", { XX }, 0 },
6776   },
6777
6778   /* X86_64_60 */
6779   {
6780     { "pushaP", { XX }, 0 },
6781   },
6782
6783   /* X86_64_61 */
6784   {
6785     { "popaP", { XX }, 0 },
6786   },
6787
6788   /* X86_64_62 */
6789   {
6790     { MOD_TABLE (MOD_62_32BIT) },
6791     { EVEX_TABLE (EVEX_0F) },
6792   },
6793
6794   /* X86_64_63 */
6795   {
6796     { "arpl", { Ew, Gw }, 0 },
6797     { "movs{lq|xd}", { Gv, Ed }, 0 },
6798   },
6799
6800   /* X86_64_6D */
6801   {
6802     { "ins{R|}", { Yzr, indirDX }, 0 },
6803     { "ins{G|}", { Yzr, indirDX }, 0 },
6804   },
6805
6806   /* X86_64_6F */
6807   {
6808     { "outs{R|}", { indirDXr, Xz }, 0 },
6809     { "outs{G|}", { indirDXr, Xz }, 0 },
6810   },
6811
6812   /* X86_64_9A */
6813   {
6814     { "Jcall{T|}", { Ap }, 0 },
6815   },
6816
6817   /* X86_64_C4 */
6818   {
6819     { MOD_TABLE (MOD_C4_32BIT) },
6820     { VEX_C4_TABLE (VEX_0F) },
6821   },
6822
6823   /* X86_64_C5 */
6824   {
6825     { MOD_TABLE (MOD_C5_32BIT) },
6826     { VEX_C5_TABLE (VEX_0F) },
6827   },
6828
6829   /* X86_64_CE */
6830   {
6831     { "into", { XX }, 0 },
6832   },
6833
6834   /* X86_64_D4 */
6835   {
6836     { "aam", { Ib }, 0 },
6837   },
6838
6839   /* X86_64_D5 */
6840   {
6841     { "aad", { Ib }, 0 },
6842   },
6843
6844   /* X86_64_E8 */
6845   {
6846     { "callP",          { Jv, BND }, 0 },
6847     { "callq",          { Jv, BND }, 0 }
6848   },
6849
6850   /* X86_64_E9 */
6851   {
6852     { "jmpP",           { Jv, BND }, 0 },
6853     { "jmpq",           { Jv, BND }, 0 }
6854   },
6855
6856   /* X86_64_EA */
6857   {
6858     { "Jjmp{T|}", { Ap }, 0 },
6859   },
6860
6861   /* X86_64_0F01_REG_0 */
6862   {
6863     { "sgdt{Q|IQ}", { M }, 0 },
6864     { "sgdt", { M }, 0 },
6865   },
6866
6867   /* X86_64_0F01_REG_1 */
6868   {
6869     { "sidt{Q|IQ}", { M }, 0 },
6870     { "sidt", { M }, 0 },
6871   },
6872
6873   /* X86_64_0F01_REG_2 */
6874   {
6875     { "lgdt{Q|Q}", { M }, 0 },
6876     { "lgdt", { M }, 0 },
6877   },
6878
6879   /* X86_64_0F01_REG_3 */
6880   {
6881     { "lidt{Q|Q}", { M }, 0 },
6882     { "lidt", { M }, 0 },
6883   },
6884 };
6885
6886 static const struct dis386 three_byte_table[][256] = {
6887
6888   /* THREE_BYTE_0F38 */
6889   {
6890     /* 00 */
6891     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6892     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6893     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6894     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6895     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6896     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6897     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6898     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6899     /* 08 */
6900     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6901     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6902     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6903     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     /* 10 */
6909     { PREFIX_TABLE (PREFIX_0F3810) },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { PREFIX_TABLE (PREFIX_0F3814) },
6914     { PREFIX_TABLE (PREFIX_0F3815) },
6915     { Bad_Opcode },
6916     { PREFIX_TABLE (PREFIX_0F3817) },
6917     /* 18 */
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6923     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6924     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6925     { Bad_Opcode },
6926     /* 20 */
6927     { PREFIX_TABLE (PREFIX_0F3820) },
6928     { PREFIX_TABLE (PREFIX_0F3821) },
6929     { PREFIX_TABLE (PREFIX_0F3822) },
6930     { PREFIX_TABLE (PREFIX_0F3823) },
6931     { PREFIX_TABLE (PREFIX_0F3824) },
6932     { PREFIX_TABLE (PREFIX_0F3825) },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     /* 28 */
6936     { PREFIX_TABLE (PREFIX_0F3828) },
6937     { PREFIX_TABLE (PREFIX_0F3829) },
6938     { PREFIX_TABLE (PREFIX_0F382A) },
6939     { PREFIX_TABLE (PREFIX_0F382B) },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     /* 30 */
6945     { PREFIX_TABLE (PREFIX_0F3830) },
6946     { PREFIX_TABLE (PREFIX_0F3831) },
6947     { PREFIX_TABLE (PREFIX_0F3832) },
6948     { PREFIX_TABLE (PREFIX_0F3833) },
6949     { PREFIX_TABLE (PREFIX_0F3834) },
6950     { PREFIX_TABLE (PREFIX_0F3835) },
6951     { Bad_Opcode },
6952     { PREFIX_TABLE (PREFIX_0F3837) },
6953     /* 38 */
6954     { PREFIX_TABLE (PREFIX_0F3838) },
6955     { PREFIX_TABLE (PREFIX_0F3839) },
6956     { PREFIX_TABLE (PREFIX_0F383A) },
6957     { PREFIX_TABLE (PREFIX_0F383B) },
6958     { PREFIX_TABLE (PREFIX_0F383C) },
6959     { PREFIX_TABLE (PREFIX_0F383D) },
6960     { PREFIX_TABLE (PREFIX_0F383E) },
6961     { PREFIX_TABLE (PREFIX_0F383F) },
6962     /* 40 */
6963     { PREFIX_TABLE (PREFIX_0F3840) },
6964     { PREFIX_TABLE (PREFIX_0F3841) },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     /* 48 */
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     /* 50 */
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     /* 58 */
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     /* 60 */
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     /* 68 */
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     /* 70 */
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     /* 78 */
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     /* 80 */
7035     { PREFIX_TABLE (PREFIX_0F3880) },
7036     { PREFIX_TABLE (PREFIX_0F3881) },
7037     { PREFIX_TABLE (PREFIX_0F3882) },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     /* 88 */
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     /* 90 */
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     /* 98 */
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     /* a0 */
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     /* a8 */
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     /* b0 */
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     /* b8 */
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     /* c0 */
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     /* c8 */
7116     { PREFIX_TABLE (PREFIX_0F38C8) },
7117     { PREFIX_TABLE (PREFIX_0F38C9) },
7118     { PREFIX_TABLE (PREFIX_0F38CA) },
7119     { PREFIX_TABLE (PREFIX_0F38CB) },
7120     { PREFIX_TABLE (PREFIX_0F38CC) },
7121     { PREFIX_TABLE (PREFIX_0F38CD) },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     /* d0 */
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     /* d8 */
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { PREFIX_TABLE (PREFIX_0F38DB) },
7138     { PREFIX_TABLE (PREFIX_0F38DC) },
7139     { PREFIX_TABLE (PREFIX_0F38DD) },
7140     { PREFIX_TABLE (PREFIX_0F38DE) },
7141     { PREFIX_TABLE (PREFIX_0F38DF) },
7142     /* e0 */
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     /* e8 */
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     /* f0 */
7161     { PREFIX_TABLE (PREFIX_0F38F0) },
7162     { PREFIX_TABLE (PREFIX_0F38F1) },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { PREFIX_TABLE (PREFIX_0F38F6) },
7168     { Bad_Opcode },
7169     /* f8 */
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178   },
7179   /* THREE_BYTE_0F3A */
7180   {
7181     /* 00 */
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     /* 08 */
7191     { PREFIX_TABLE (PREFIX_0F3A08) },
7192     { PREFIX_TABLE (PREFIX_0F3A09) },
7193     { PREFIX_TABLE (PREFIX_0F3A0A) },
7194     { PREFIX_TABLE (PREFIX_0F3A0B) },
7195     { PREFIX_TABLE (PREFIX_0F3A0C) },
7196     { PREFIX_TABLE (PREFIX_0F3A0D) },
7197     { PREFIX_TABLE (PREFIX_0F3A0E) },
7198     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7199     /* 10 */
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { PREFIX_TABLE (PREFIX_0F3A14) },
7205     { PREFIX_TABLE (PREFIX_0F3A15) },
7206     { PREFIX_TABLE (PREFIX_0F3A16) },
7207     { PREFIX_TABLE (PREFIX_0F3A17) },
7208     /* 18 */
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     /* 20 */
7218     { PREFIX_TABLE (PREFIX_0F3A20) },
7219     { PREFIX_TABLE (PREFIX_0F3A21) },
7220     { PREFIX_TABLE (PREFIX_0F3A22) },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     /* 28 */
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     /* 30 */
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     /* 38 */
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     /* 40 */
7254     { PREFIX_TABLE (PREFIX_0F3A40) },
7255     { PREFIX_TABLE (PREFIX_0F3A41) },
7256     { PREFIX_TABLE (PREFIX_0F3A42) },
7257     { Bad_Opcode },
7258     { PREFIX_TABLE (PREFIX_0F3A44) },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     /* 48 */
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     /* 50 */
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     /* 58 */
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     /* 60 */
7290     { PREFIX_TABLE (PREFIX_0F3A60) },
7291     { PREFIX_TABLE (PREFIX_0F3A61) },
7292     { PREFIX_TABLE (PREFIX_0F3A62) },
7293     { PREFIX_TABLE (PREFIX_0F3A63) },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     /* 68 */
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     /* 70 */
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     /* 78 */
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     /* 80 */
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     /* 88 */
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     /* 90 */
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     /* 98 */
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     /* a0 */
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     /* a8 */
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     /* b0 */
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     /* b8 */
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     /* c0 */
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     /* c8 */
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { PREFIX_TABLE (PREFIX_0F3ACC) },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     /* d0 */
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     /* d8 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { PREFIX_TABLE (PREFIX_0F3ADF) },
7433     /* e0 */
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     /* e8 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* f0 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* f8 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469   },
7470
7471   /* THREE_BYTE_0F7A */
7472   {
7473     /* 00 */
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     /* 08 */
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     /* 10 */
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     /* 18 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     /* 20 */
7510     { "ptest",          { XX }, PREFIX_OPCODE },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     /* 28 */
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     /* 30 */
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     /* 38 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     /* 40 */
7546     { Bad_Opcode },
7547     { "phaddbw",        { XM, EXq }, PREFIX_OPCODE },
7548     { "phaddbd",        { XM, EXq }, PREFIX_OPCODE },
7549     { "phaddbq",        { XM, EXq }, PREFIX_OPCODE },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { "phaddwd",        { XM, EXq }, PREFIX_OPCODE },
7553     { "phaddwq",        { XM, EXq }, PREFIX_OPCODE },
7554     /* 48 */
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { "phadddq",        { XM, EXq }, PREFIX_OPCODE },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     /* 50 */
7564     { Bad_Opcode },
7565     { "phaddubw",       { XM, EXq }, PREFIX_OPCODE },
7566     { "phaddubd",       { XM, EXq }, PREFIX_OPCODE },
7567     { "phaddubq",       { XM, EXq }, PREFIX_OPCODE },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { "phadduwd",       { XM, EXq }, PREFIX_OPCODE },
7571     { "phadduwq",       { XM, EXq }, PREFIX_OPCODE },
7572     /* 58 */
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { "phaddudq",       { XM, EXq }, PREFIX_OPCODE },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     /* 60 */
7582     { Bad_Opcode },
7583     { "phsubbw",        { XM, EXq }, PREFIX_OPCODE },
7584     { "phsubbd",        { XM, EXq }, PREFIX_OPCODE },
7585     { "phsubbq",        { XM, EXq }, PREFIX_OPCODE },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     /* 68 */
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     /* 70 */
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     /* 78 */
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     /* 80 */
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     /* 88 */
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     /* 90 */
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     /* 98 */
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     /* a0 */
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     /* a8 */
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     /* b0 */
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     /* b8 */
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     /* c0 */
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     /* c8 */
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     /* d0 */
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     /* d8 */
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     /* e0 */
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     /* e8 */
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     /* f0 */
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     /* f8 */
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761   },
7762 };
7763
7764 static const struct dis386 xop_table[][256] = {
7765   /* XOP_08 */
7766   {
7767     /* 00 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     /* 08 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* 10 */
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     /* 18 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     /* 20 */
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     /* 28 */
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     /* 30 */
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     /* 38 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* 40 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     /* 48 */
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     /* 50 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     /* 58 */
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     /* 60 */
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     /* 68 */
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     /* 70 */
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     /* 78 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     /* 80 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7918     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7919     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7920     /* 88 */
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7928     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7929     /* 90 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7936     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7937     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7938     /* 98 */
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7946     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7947     /* a0 */
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7951     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7955     { Bad_Opcode },
7956     /* a8 */
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     /* b0 */
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7973     { Bad_Opcode },
7974     /* b8 */
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     /* c0 */
7984     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7985     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7986     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7987     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     /* c8 */
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7998     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7999     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8000     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8001     /* d0 */
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     /* d8 */
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     /* e0 */
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     /* e8 */
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8034     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8035     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8036     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8037     /* f0 */
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     /* f8 */
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055   },
8056   /* XOP_09 */
8057   {
8058     /* 00 */
8059     { Bad_Opcode },
8060     { REG_TABLE (REG_XOP_TBM_01) },
8061     { REG_TABLE (REG_XOP_TBM_02) },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* 08 */
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* 10 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { REG_TABLE (REG_XOP_LWPCB) },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* 18 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     /* 20 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* 28 */
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     /* 30 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     /* 38 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* 40 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     /* 48 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* 50 */
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     /* 58 */
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     /* 60 */
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     /* 68 */
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* 70 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     /* 78 */
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* 80 */
8203     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8204     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8205     { "vfrczss",        { XM, EXd }, 0 },
8206     { "vfrczsd",        { XM, EXq }, 0 },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* 88 */
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     /* 90 */
8221     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8222     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8223     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8224     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8225     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8226     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8227     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8228     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8229     /* 98 */
8230     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8231     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8232     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8233     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     /* a0 */
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     /* a8 */
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* b0 */
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     /* b8 */
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* c0 */
8275     { Bad_Opcode },
8276     { "vphaddbw",       { XM, EXxmm }, 0 },
8277     { "vphaddbd",       { XM, EXxmm }, 0 },
8278     { "vphaddbq",       { XM, EXxmm }, 0 },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { "vphaddwd",       { XM, EXxmm }, 0 },
8282     { "vphaddwq",       { XM, EXxmm }, 0 },
8283     /* c8 */
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { "vphadddq",       { XM, EXxmm }, 0 },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     /* d0 */
8293     { Bad_Opcode },
8294     { "vphaddubw",      { XM, EXxmm }, 0 },
8295     { "vphaddubd",      { XM, EXxmm }, 0 },
8296     { "vphaddubq",      { XM, EXxmm }, 0 },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { "vphadduwd",      { XM, EXxmm }, 0 },
8300     { "vphadduwq",      { XM, EXxmm }, 0 },
8301     /* d8 */
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { "vphaddudq",      { XM, EXxmm }, 0 },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     /* e0 */
8311     { Bad_Opcode },
8312     { "vphsubbw",       { XM, EXxmm }, 0 },
8313     { "vphsubwd",       { XM, EXxmm }, 0 },
8314     { "vphsubdq",       { XM, EXxmm }, 0 },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     /* e8 */
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     /* f0 */
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     /* f8 */
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346   },
8347   /* XOP_0A */
8348   {
8349     /* 00 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* 08 */
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     /* 10 */
8368     { "bextr",  { Gv, Ev, Iq }, 0 },
8369     { Bad_Opcode },
8370     { REG_TABLE (REG_XOP_LWP) },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     /* 18 */
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     /* 20 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     /* 28 */
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     /* 30 */
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     /* 38 */
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     /* 40 */
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     /* 48 */
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     /* 50 */
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     /* 58 */
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     /* 60 */
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     /* 68 */
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     /* 70 */
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     /* 78 */
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     /* 80 */
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     /* 88 */
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     /* 90 */
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     /* 98 */
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     /* a0 */
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     /* a8 */
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     /* b0 */
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     /* b8 */
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     /* c0 */
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     /* c8 */
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     /* d0 */
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     /* d8 */
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     /* e0 */
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     /* e8 */
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     /* f0 */
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     /* f8 */
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637   },
8638 };
8639
8640 static const struct dis386 vex_table[][256] = {
8641   /* VEX_0F */
8642   {
8643     /* 00 */
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     /* 08 */
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     /* 10 */
8662     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8663     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8665     { MOD_TABLE (MOD_VEX_0F13) },
8666     { VEX_W_TABLE (VEX_W_0F14) },
8667     { VEX_W_TABLE (VEX_W_0F15) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8669     { MOD_TABLE (MOD_VEX_0F17) },
8670     /* 18 */
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     /* 20 */
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     /* 28 */
8689     { VEX_W_TABLE (VEX_W_0F28) },
8690     { VEX_W_TABLE (VEX_W_0F29) },
8691     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8692     { MOD_TABLE (MOD_VEX_0F2B) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8697     /* 30 */
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     /* 38 */
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     /* 40 */
8716     { Bad_Opcode },
8717     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8719     { Bad_Opcode },
8720     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8724     /* 48 */
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     /* 50 */
8734     { MOD_TABLE (MOD_VEX_0F50) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8738     { "vandpX",         { XM, Vex, EXx }, 0 },
8739     { "vandnpX",        { XM, Vex, EXx }, 0 },
8740     { "vorpX",          { XM, Vex, EXx }, 0 },
8741     { "vxorpX",         { XM, Vex, EXx }, 0 },
8742     /* 58 */
8743     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8751     /* 60 */
8752     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8760     /* 68 */
8761     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8769     /* 70 */
8770     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8771     { REG_TABLE (REG_VEX_0F71) },
8772     { REG_TABLE (REG_VEX_0F72) },
8773     { REG_TABLE (REG_VEX_0F73) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8778     /* 78 */
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8787     /* 80 */
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     /* 88 */
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     /* 90 */
8806     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     /* 98 */
8815     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     /* a0 */
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     /* a8 */
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { REG_TABLE (REG_VEX_0FAE) },
8840     { Bad_Opcode },
8841     /* b0 */
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     /* b8 */
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     /* c0 */
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8863     { Bad_Opcode },
8864     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8865     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8866     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8867     { Bad_Opcode },
8868     /* c8 */
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     /* d0 */
8878     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8879     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8880     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8881     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8882     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8883     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8884     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8885     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8886     /* d8 */
8887     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8888     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8889     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8890     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8891     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8892     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8893     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8894     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8895     /* e0 */
8896     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8897     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8898     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8899     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8900     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8901     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8902     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8903     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8904     /* e8 */
8905     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8906     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8907     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8908     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8909     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8910     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8911     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8912     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8913     /* f0 */
8914     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8915     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8916     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8917     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8918     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8919     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8920     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8921     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8922     /* f8 */
8923     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8924     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8925     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8926     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8927     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8928     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8929     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8930     { Bad_Opcode },
8931   },
8932   /* VEX_0F38 */
8933   {
8934     /* 00 */
8935     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8943     /* 08 */
8944     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8952     /* 10 */
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8961     /* 18 */
8962     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8965     { Bad_Opcode },
8966     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8969     { Bad_Opcode },
8970     /* 20 */
8971     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     /* 28 */
8980     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8988     /* 30 */
8989     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8997     /* 38 */
8998     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9006     /* 40 */
9007     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9015     /* 48 */
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     /* 50 */
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     /* 58 */
9034     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     /* 60 */
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     /* 68 */
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     /* 70 */
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     /* 78 */
9070     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     /* 80 */
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     /* 88 */
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9093     { Bad_Opcode },
9094     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9095     { Bad_Opcode },
9096     /* 90 */
9097     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9105     /* 98 */
9106     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9114     /* a0 */
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9123     /* a8 */
9124     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9132     /* b0 */
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9141     /* b8 */
9142     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9143     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9144     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9145     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9146     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9147     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9149     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9150     /* c0 */
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     /* c8 */
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     /* d0 */
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     /* d8 */
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9182     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9183     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9186     /* e0 */
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     /* e8 */
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     /* f0 */
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9208     { REG_TABLE (REG_VEX_0F38F3) },
9209     { Bad_Opcode },
9210     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9211     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9212     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9213     /* f8 */
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222   },
9223   /* VEX_0F3A */
9224   {
9225     /* 00 */
9226     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9227     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9228     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9229     { Bad_Opcode },
9230     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9231     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9232     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9233     { Bad_Opcode },
9234     /* 08 */
9235     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9236     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9237     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9238     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9239     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9240     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9241     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9242     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9243     /* 10 */
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9249     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9250     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9251     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9252     /* 18 */
9253     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9254     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     /* 20 */
9262     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9263     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9264     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     /* 28 */
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     /* 30 */
9280     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9281     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9282     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9283     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     /* 38 */
9289     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9290     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     /* 40 */
9298     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9299     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9300     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9301     { Bad_Opcode },
9302     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9303     { Bad_Opcode },
9304     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9305     { Bad_Opcode },
9306     /* 48 */
9307     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9308     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9309     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     /* 50 */
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     /* 58 */
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9330     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9331     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9332     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9333     /* 60 */
9334     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9335     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9336     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9337     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     /* 68 */
9343     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9344     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9345     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9346     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9347     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9348     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9349     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9350     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9351     /* 70 */
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     /* 78 */
9361     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9362     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9363     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9364     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9365     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9366     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9367     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9368     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9369     /* 80 */
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     /* 88 */
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     /* 90 */
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     /* 98 */
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     /* a0 */
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     /* a8 */
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     /* b0 */
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     /* b8 */
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     /* c0 */
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     /* c8 */
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     /* d0 */
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     /* d8 */
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     { Bad_Opcode },
9472     { Bad_Opcode },
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9477     /* e0 */
9478     { Bad_Opcode },
9479     { Bad_Opcode },
9480     { Bad_Opcode },
9481     { Bad_Opcode },
9482     { Bad_Opcode },
9483     { Bad_Opcode },
9484     { Bad_Opcode },
9485     { Bad_Opcode },
9486     /* e8 */
9487     { Bad_Opcode },
9488     { Bad_Opcode },
9489     { Bad_Opcode },
9490     { Bad_Opcode },
9491     { Bad_Opcode },
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     { Bad_Opcode },
9495     /* f0 */
9496     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9497     { Bad_Opcode },
9498     { Bad_Opcode },
9499     { Bad_Opcode },
9500     { Bad_Opcode },
9501     { Bad_Opcode },
9502     { Bad_Opcode },
9503     { Bad_Opcode },
9504     /* f8 */
9505     { Bad_Opcode },
9506     { Bad_Opcode },
9507     { Bad_Opcode },
9508     { Bad_Opcode },
9509     { Bad_Opcode },
9510     { Bad_Opcode },
9511     { Bad_Opcode },
9512     { Bad_Opcode },
9513   },
9514 };
9515
9516 #define NEED_OPCODE_TABLE
9517 #include "i386-dis-evex.h"
9518 #undef NEED_OPCODE_TABLE
9519 static const struct dis386 vex_len_table[][2] = {
9520   /* VEX_LEN_0F10_P_1 */
9521   {
9522     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9523     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9524   },
9525
9526   /* VEX_LEN_0F10_P_3 */
9527   {
9528     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9529     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9530   },
9531
9532   /* VEX_LEN_0F11_P_1 */
9533   {
9534     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9535     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9536   },
9537
9538   /* VEX_LEN_0F11_P_3 */
9539   {
9540     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9541     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9542   },
9543
9544   /* VEX_LEN_0F12_P_0_M_0 */
9545   {
9546     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9547   },
9548
9549   /* VEX_LEN_0F12_P_0_M_1 */
9550   {
9551     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9552   },
9553
9554   /* VEX_LEN_0F12_P_2 */
9555   {
9556     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9557   },
9558
9559   /* VEX_LEN_0F13_M_0 */
9560   {
9561     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9562   },
9563
9564   /* VEX_LEN_0F16_P_0_M_0 */
9565   {
9566     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9567   },
9568
9569   /* VEX_LEN_0F16_P_0_M_1 */
9570   {
9571     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9572   },
9573
9574   /* VEX_LEN_0F16_P_2 */
9575   {
9576     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9577   },
9578
9579   /* VEX_LEN_0F17_M_0 */
9580   {
9581     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9582   },
9583
9584   /* VEX_LEN_0F2A_P_1 */
9585   {
9586     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9587     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9588   },
9589
9590   /* VEX_LEN_0F2A_P_3 */
9591   {
9592     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9593     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9594   },
9595
9596   /* VEX_LEN_0F2C_P_1 */
9597   {
9598     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9599     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9600   },
9601
9602   /* VEX_LEN_0F2C_P_3 */
9603   {
9604     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9605     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9606   },
9607
9608   /* VEX_LEN_0F2D_P_1 */
9609   {
9610     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9611     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9612   },
9613
9614   /* VEX_LEN_0F2D_P_3 */
9615   {
9616     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9617     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9618   },
9619
9620   /* VEX_LEN_0F2E_P_0 */
9621   {
9622     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9623     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9624   },
9625
9626   /* VEX_LEN_0F2E_P_2 */
9627   {
9628     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9629     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9630   },
9631
9632   /* VEX_LEN_0F2F_P_0 */
9633   {
9634     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9635     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9636   },
9637
9638   /* VEX_LEN_0F2F_P_2 */
9639   {
9640     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9641     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9642   },
9643
9644   /* VEX_LEN_0F41_P_0 */
9645   {
9646     { Bad_Opcode },
9647     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9648   },
9649   /* VEX_LEN_0F41_P_2 */
9650   {
9651     { Bad_Opcode },
9652     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9653   },
9654   /* VEX_LEN_0F42_P_0 */
9655   {
9656     { Bad_Opcode },
9657     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9658   },
9659   /* VEX_LEN_0F42_P_2 */
9660   {
9661     { Bad_Opcode },
9662     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9663   },
9664   /* VEX_LEN_0F44_P_0 */
9665   {
9666     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9667   },
9668   /* VEX_LEN_0F44_P_2 */
9669   {
9670     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9671   },
9672   /* VEX_LEN_0F45_P_0 */
9673   {
9674     { Bad_Opcode },
9675     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9676   },
9677   /* VEX_LEN_0F45_P_2 */
9678   {
9679     { Bad_Opcode },
9680     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9681   },
9682   /* VEX_LEN_0F46_P_0 */
9683   {
9684     { Bad_Opcode },
9685     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9686   },
9687   /* VEX_LEN_0F46_P_2 */
9688   {
9689     { Bad_Opcode },
9690     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9691   },
9692   /* VEX_LEN_0F47_P_0 */
9693   {
9694     { Bad_Opcode },
9695     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9696   },
9697   /* VEX_LEN_0F47_P_2 */
9698   {
9699     { Bad_Opcode },
9700     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9701   },
9702   /* VEX_LEN_0F4A_P_0 */
9703   {
9704     { Bad_Opcode },
9705     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9706   },
9707   /* VEX_LEN_0F4A_P_2 */
9708   {
9709     { Bad_Opcode },
9710     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9711   },
9712   /* VEX_LEN_0F4B_P_0 */
9713   {
9714     { Bad_Opcode },
9715     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9716   },
9717   /* VEX_LEN_0F4B_P_2 */
9718   {
9719     { Bad_Opcode },
9720     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9721   },
9722
9723   /* VEX_LEN_0F51_P_1 */
9724   {
9725     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9726     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9727   },
9728
9729   /* VEX_LEN_0F51_P_3 */
9730   {
9731     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9732     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9733   },
9734
9735   /* VEX_LEN_0F52_P_1 */
9736   {
9737     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9738     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9739   },
9740
9741   /* VEX_LEN_0F53_P_1 */
9742   {
9743     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9744     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9745   },
9746
9747   /* VEX_LEN_0F58_P_1 */
9748   {
9749     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9750     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9751   },
9752
9753   /* VEX_LEN_0F58_P_3 */
9754   {
9755     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9756     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9757   },
9758
9759   /* VEX_LEN_0F59_P_1 */
9760   {
9761     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9762     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9763   },
9764
9765   /* VEX_LEN_0F59_P_3 */
9766   {
9767     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9768     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9769   },
9770
9771   /* VEX_LEN_0F5A_P_1 */
9772   {
9773     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9774     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9775   },
9776
9777   /* VEX_LEN_0F5A_P_3 */
9778   {
9779     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9780     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9781   },
9782
9783   /* VEX_LEN_0F5C_P_1 */
9784   {
9785     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9786     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9787   },
9788
9789   /* VEX_LEN_0F5C_P_3 */
9790   {
9791     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9792     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9793   },
9794
9795   /* VEX_LEN_0F5D_P_1 */
9796   {
9797     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9798     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9799   },
9800
9801   /* VEX_LEN_0F5D_P_3 */
9802   {
9803     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9804     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9805   },
9806
9807   /* VEX_LEN_0F5E_P_1 */
9808   {
9809     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9810     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9811   },
9812
9813   /* VEX_LEN_0F5E_P_3 */
9814   {
9815     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9816     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9817   },
9818
9819   /* VEX_LEN_0F5F_P_1 */
9820   {
9821     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9822     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9823   },
9824
9825   /* VEX_LEN_0F5F_P_3 */
9826   {
9827     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9828     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9829   },
9830
9831   /* VEX_LEN_0F6E_P_2 */
9832   {
9833     { "vmovK",          { XMScalar, Edq }, 0 },
9834     { "vmovK",          { XMScalar, Edq }, 0 },
9835   },
9836
9837   /* VEX_LEN_0F7E_P_1 */
9838   {
9839     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9840     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9841   },
9842
9843   /* VEX_LEN_0F7E_P_2 */
9844   {
9845     { "vmovK",          { Edq, XMScalar }, 0 },
9846     { "vmovK",          { Edq, XMScalar }, 0 },
9847   },
9848
9849   /* VEX_LEN_0F90_P_0 */
9850   {
9851     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9852   },
9853
9854   /* VEX_LEN_0F90_P_2 */
9855   {
9856     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9857   },
9858
9859   /* VEX_LEN_0F91_P_0 */
9860   {
9861     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9862   },
9863
9864   /* VEX_LEN_0F91_P_2 */
9865   {
9866     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9867   },
9868
9869   /* VEX_LEN_0F92_P_0 */
9870   {
9871     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9872   },
9873
9874   /* VEX_LEN_0F92_P_2 */
9875   {
9876     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9877   },
9878
9879   /* VEX_LEN_0F92_P_3 */
9880   {
9881     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9882   },
9883
9884   /* VEX_LEN_0F93_P_0 */
9885   {
9886     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9887   },
9888
9889   /* VEX_LEN_0F93_P_2 */
9890   {
9891     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9892   },
9893
9894   /* VEX_LEN_0F93_P_3 */
9895   {
9896     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9897   },
9898
9899   /* VEX_LEN_0F98_P_0 */
9900   {
9901     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9902   },
9903
9904   /* VEX_LEN_0F98_P_2 */
9905   {
9906     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9907   },
9908
9909   /* VEX_LEN_0F99_P_0 */
9910   {
9911     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9912   },
9913
9914   /* VEX_LEN_0F99_P_2 */
9915   {
9916     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9917   },
9918
9919   /* VEX_LEN_0FAE_R_2_M_0 */
9920   {
9921     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9922   },
9923
9924   /* VEX_LEN_0FAE_R_3_M_0 */
9925   {
9926     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9927   },
9928
9929   /* VEX_LEN_0FC2_P_1 */
9930   {
9931     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9932     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9933   },
9934
9935   /* VEX_LEN_0FC2_P_3 */
9936   {
9937     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9938     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9939   },
9940
9941   /* VEX_LEN_0FC4_P_2 */
9942   {
9943     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9944   },
9945
9946   /* VEX_LEN_0FC5_P_2 */
9947   {
9948     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9949   },
9950
9951   /* VEX_LEN_0FD6_P_2 */
9952   {
9953     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9954     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9955   },
9956
9957   /* VEX_LEN_0FF7_P_2 */
9958   {
9959     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9960   },
9961
9962   /* VEX_LEN_0F3816_P_2 */
9963   {
9964     { Bad_Opcode },
9965     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9966   },
9967
9968   /* VEX_LEN_0F3819_P_2 */
9969   {
9970     { Bad_Opcode },
9971     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9972   },
9973
9974   /* VEX_LEN_0F381A_P_2_M_0 */
9975   {
9976     { Bad_Opcode },
9977     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9978   },
9979
9980   /* VEX_LEN_0F3836_P_2 */
9981   {
9982     { Bad_Opcode },
9983     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9984   },
9985
9986   /* VEX_LEN_0F3841_P_2 */
9987   {
9988     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9989   },
9990
9991   /* VEX_LEN_0F385A_P_2_M_0 */
9992   {
9993     { Bad_Opcode },
9994     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9995   },
9996
9997   /* VEX_LEN_0F38DB_P_2 */
9998   {
9999     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10000   },
10001
10002   /* VEX_LEN_0F38DC_P_2 */
10003   {
10004     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
10005   },
10006
10007   /* VEX_LEN_0F38DD_P_2 */
10008   {
10009     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
10010   },
10011
10012   /* VEX_LEN_0F38DE_P_2 */
10013   {
10014     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
10015   },
10016
10017   /* VEX_LEN_0F38DF_P_2 */
10018   {
10019     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10020   },
10021
10022   /* VEX_LEN_0F38F2_P_0 */
10023   {
10024     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10025   },
10026
10027   /* VEX_LEN_0F38F3_R_1_P_0 */
10028   {
10029     { "blsrS",          { VexGdq, Edq }, 0 },
10030   },
10031
10032   /* VEX_LEN_0F38F3_R_2_P_0 */
10033   {
10034     { "blsmskS",        { VexGdq, Edq }, 0 },
10035   },
10036
10037   /* VEX_LEN_0F38F3_R_3_P_0 */
10038   {
10039     { "blsiS",          { VexGdq, Edq }, 0 },
10040   },
10041
10042   /* VEX_LEN_0F38F5_P_0 */
10043   {
10044     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10045   },
10046
10047   /* VEX_LEN_0F38F5_P_1 */
10048   {
10049     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10050   },
10051
10052   /* VEX_LEN_0F38F5_P_3 */
10053   {
10054     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10055   },
10056
10057   /* VEX_LEN_0F38F6_P_3 */
10058   {
10059     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10060   },
10061
10062   /* VEX_LEN_0F38F7_P_0 */
10063   {
10064     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10065   },
10066
10067   /* VEX_LEN_0F38F7_P_1 */
10068   {
10069     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10070   },
10071
10072   /* VEX_LEN_0F38F7_P_2 */
10073   {
10074     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10075   },
10076
10077   /* VEX_LEN_0F38F7_P_3 */
10078   {
10079     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10080   },
10081
10082   /* VEX_LEN_0F3A00_P_2 */
10083   {
10084     { Bad_Opcode },
10085     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10086   },
10087
10088   /* VEX_LEN_0F3A01_P_2 */
10089   {
10090     { Bad_Opcode },
10091     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10092   },
10093
10094   /* VEX_LEN_0F3A06_P_2 */
10095   {
10096     { Bad_Opcode },
10097     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10098   },
10099
10100   /* VEX_LEN_0F3A0A_P_2 */
10101   {
10102     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10103     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10104   },
10105
10106   /* VEX_LEN_0F3A0B_P_2 */
10107   {
10108     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10109     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10110   },
10111
10112   /* VEX_LEN_0F3A14_P_2 */
10113   {
10114     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10115   },
10116
10117   /* VEX_LEN_0F3A15_P_2 */
10118   {
10119     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10120   },
10121
10122   /* VEX_LEN_0F3A16_P_2  */
10123   {
10124     { "vpextrK",        { Edq, XM, Ib }, 0 },
10125   },
10126
10127   /* VEX_LEN_0F3A17_P_2 */
10128   {
10129     { "vextractps",     { Edqd, XM, Ib }, 0 },
10130   },
10131
10132   /* VEX_LEN_0F3A18_P_2 */
10133   {
10134     { Bad_Opcode },
10135     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10136   },
10137
10138   /* VEX_LEN_0F3A19_P_2 */
10139   {
10140     { Bad_Opcode },
10141     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10142   },
10143
10144   /* VEX_LEN_0F3A20_P_2 */
10145   {
10146     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10147   },
10148
10149   /* VEX_LEN_0F3A21_P_2 */
10150   {
10151     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10152   },
10153
10154   /* VEX_LEN_0F3A22_P_2 */
10155   {
10156     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10157   },
10158
10159   /* VEX_LEN_0F3A30_P_2 */
10160   {
10161     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10162   },
10163
10164   /* VEX_LEN_0F3A31_P_2 */
10165   {
10166     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10167   },
10168
10169   /* VEX_LEN_0F3A32_P_2 */
10170   {
10171     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10172   },
10173
10174   /* VEX_LEN_0F3A33_P_2 */
10175   {
10176     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10177   },
10178
10179   /* VEX_LEN_0F3A38_P_2 */
10180   {
10181     { Bad_Opcode },
10182     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10183   },
10184
10185   /* VEX_LEN_0F3A39_P_2 */
10186   {
10187     { Bad_Opcode },
10188     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10189   },
10190
10191   /* VEX_LEN_0F3A41_P_2 */
10192   {
10193     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10194   },
10195
10196   /* VEX_LEN_0F3A44_P_2 */
10197   {
10198     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10199   },
10200
10201   /* VEX_LEN_0F3A46_P_2 */
10202   {
10203     { Bad_Opcode },
10204     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10205   },
10206
10207   /* VEX_LEN_0F3A60_P_2 */
10208   {
10209     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10210   },
10211
10212   /* VEX_LEN_0F3A61_P_2 */
10213   {
10214     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10215   },
10216
10217   /* VEX_LEN_0F3A62_P_2 */
10218   {
10219     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10220   },
10221
10222   /* VEX_LEN_0F3A63_P_2 */
10223   {
10224     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10225   },
10226
10227   /* VEX_LEN_0F3A6A_P_2 */
10228   {
10229     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10230   },
10231
10232   /* VEX_LEN_0F3A6B_P_2 */
10233   {
10234     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10235   },
10236
10237   /* VEX_LEN_0F3A6E_P_2 */
10238   {
10239     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10240   },
10241
10242   /* VEX_LEN_0F3A6F_P_2 */
10243   {
10244     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10245   },
10246
10247   /* VEX_LEN_0F3A7A_P_2 */
10248   {
10249     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10250   },
10251
10252   /* VEX_LEN_0F3A7B_P_2 */
10253   {
10254     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10255   },
10256
10257   /* VEX_LEN_0F3A7E_P_2 */
10258   {
10259     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10260   },
10261
10262   /* VEX_LEN_0F3A7F_P_2 */
10263   {
10264     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10265   },
10266
10267   /* VEX_LEN_0F3ADF_P_2 */
10268   {
10269     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10270   },
10271
10272   /* VEX_LEN_0F3AF0_P_3 */
10273   {
10274     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10275   },
10276
10277   /* VEX_LEN_0FXOP_08_CC */
10278   {
10279      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10280   },
10281
10282   /* VEX_LEN_0FXOP_08_CD */
10283   {
10284      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10285   },
10286
10287   /* VEX_LEN_0FXOP_08_CE */
10288   {
10289      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10290   },
10291
10292   /* VEX_LEN_0FXOP_08_CF */
10293   {
10294      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10295   },
10296
10297   /* VEX_LEN_0FXOP_08_EC */
10298   {
10299      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10300   },
10301
10302   /* VEX_LEN_0FXOP_08_ED */
10303   {
10304      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10305   },
10306
10307   /* VEX_LEN_0FXOP_08_EE */
10308   {
10309      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10310   },
10311
10312   /* VEX_LEN_0FXOP_08_EF */
10313   {
10314      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10315   },
10316
10317   /* VEX_LEN_0FXOP_09_80 */
10318   {
10319     { "vfrczps",        { XM, EXxmm }, 0 },
10320     { "vfrczps",        { XM, EXymmq }, 0 },
10321   },
10322
10323   /* VEX_LEN_0FXOP_09_81 */
10324   {
10325     { "vfrczpd",        { XM, EXxmm }, 0 },
10326     { "vfrczpd",        { XM, EXymmq }, 0 },
10327   },
10328 };
10329
10330 static const struct dis386 vex_w_table[][2] = {
10331   {
10332     /* VEX_W_0F10_P_0 */
10333     { "vmovups",        { XM, EXx }, 0 },
10334   },
10335   {
10336     /* VEX_W_0F10_P_1 */
10337     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10338   },
10339   {
10340     /* VEX_W_0F10_P_2 */
10341     { "vmovupd",        { XM, EXx }, 0 },
10342   },
10343   {
10344     /* VEX_W_0F10_P_3 */
10345     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10346   },
10347   {
10348     /* VEX_W_0F11_P_0 */
10349     { "vmovups",        { EXxS, XM }, 0 },
10350   },
10351   {
10352     /* VEX_W_0F11_P_1 */
10353     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10354   },
10355   {
10356     /* VEX_W_0F11_P_2 */
10357     { "vmovupd",        { EXxS, XM }, 0 },
10358   },
10359   {
10360     /* VEX_W_0F11_P_3 */
10361     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10362   },
10363   {
10364     /* VEX_W_0F12_P_0_M_0 */
10365     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10366   },
10367   {
10368     /* VEX_W_0F12_P_0_M_1 */
10369     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10370   },
10371   {
10372     /* VEX_W_0F12_P_1 */
10373     { "vmovsldup",      { XM, EXx }, 0 },
10374   },
10375   {
10376     /* VEX_W_0F12_P_2 */
10377     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10378   },
10379   {
10380     /* VEX_W_0F12_P_3 */
10381     { "vmovddup",       { XM, EXymmq }, 0 },
10382   },
10383   {
10384     /* VEX_W_0F13_M_0 */
10385     { "vmovlpX",        { EXq, XM }, 0 },
10386   },
10387   {
10388     /* VEX_W_0F14 */
10389     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10390   },
10391   {
10392     /* VEX_W_0F15 */
10393     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10394   },
10395   {
10396     /* VEX_W_0F16_P_0_M_0 */
10397     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10398   },
10399   {
10400     /* VEX_W_0F16_P_0_M_1 */
10401     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10402   },
10403   {
10404     /* VEX_W_0F16_P_1 */
10405     { "vmovshdup",      { XM, EXx }, 0 },
10406   },
10407   {
10408     /* VEX_W_0F16_P_2 */
10409     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10410   },
10411   {
10412     /* VEX_W_0F17_M_0 */
10413     { "vmovhpX",        { EXq, XM }, 0 },
10414   },
10415   {
10416     /* VEX_W_0F28 */
10417     { "vmovapX",        { XM, EXx }, 0 },
10418   },
10419   {
10420     /* VEX_W_0F29 */
10421     { "vmovapX",        { EXxS, XM }, 0 },
10422   },
10423   {
10424     /* VEX_W_0F2B_M_0 */
10425     { "vmovntpX",       { Mx, XM }, 0 },
10426   },
10427   {
10428     /* VEX_W_0F2E_P_0 */
10429     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10430   },
10431   {
10432     /* VEX_W_0F2E_P_2 */
10433     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10434   },
10435   {
10436     /* VEX_W_0F2F_P_0 */
10437     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10438   },
10439   {
10440     /* VEX_W_0F2F_P_2 */
10441     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10442   },
10443   {
10444     /* VEX_W_0F41_P_0_LEN_1 */
10445     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10446     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10447   },
10448   {
10449     /* VEX_W_0F41_P_2_LEN_1 */
10450     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10451     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10452   },
10453   {
10454     /* VEX_W_0F42_P_0_LEN_1 */
10455     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10456     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10457   },
10458   {
10459     /* VEX_W_0F42_P_2_LEN_1 */
10460     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10461     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10462   },
10463   {
10464     /* VEX_W_0F44_P_0_LEN_0 */
10465     { "knotw",          { MaskG, MaskR }, 0 },
10466     { "knotq",          { MaskG, MaskR }, 0 },
10467   },
10468   {
10469     /* VEX_W_0F44_P_2_LEN_0 */
10470     { "knotb",          { MaskG, MaskR }, 0 },
10471     { "knotd",          { MaskG, MaskR }, 0 },
10472   },
10473   {
10474     /* VEX_W_0F45_P_0_LEN_1 */
10475     { "korw",           { MaskG, MaskVex, MaskR }, 0 },
10476     { "korq",           { MaskG, MaskVex, MaskR }, 0 },
10477   },
10478   {
10479     /* VEX_W_0F45_P_2_LEN_1 */
10480     { "korb",           { MaskG, MaskVex, MaskR }, 0 },
10481     { "kord",           { MaskG, MaskVex, MaskR }, 0 },
10482   },
10483   {
10484     /* VEX_W_0F46_P_0_LEN_1 */
10485     { "kxnorw",         { MaskG, MaskVex, MaskR }, 0 },
10486     { "kxnorq",         { MaskG, MaskVex, MaskR }, 0 },
10487   },
10488   {
10489     /* VEX_W_0F46_P_2_LEN_1 */
10490     { "kxnorb",         { MaskG, MaskVex, MaskR }, 0 },
10491     { "kxnord",         { MaskG, MaskVex, MaskR }, 0 },
10492   },
10493   {
10494     /* VEX_W_0F47_P_0_LEN_1 */
10495     { "kxorw",          { MaskG, MaskVex, MaskR }, 0 },
10496     { "kxorq",          { MaskG, MaskVex, MaskR }, 0 },
10497   },
10498   {
10499     /* VEX_W_0F47_P_2_LEN_1 */
10500     { "kxorb",          { MaskG, MaskVex, MaskR }, 0 },
10501     { "kxord",          { MaskG, MaskVex, MaskR }, 0 },
10502   },
10503   {
10504     /* VEX_W_0F4A_P_0_LEN_1 */
10505     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10506     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10507   },
10508   {
10509     /* VEX_W_0F4A_P_2_LEN_1 */
10510     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10511     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10512   },
10513   {
10514     /* VEX_W_0F4B_P_0_LEN_1 */
10515     { "kunpckwd",       { MaskG, MaskVex, MaskR }, 0 },
10516     { "kunpckdq",       { MaskG, MaskVex, MaskR }, 0 },
10517   },
10518   {
10519     /* VEX_W_0F4B_P_2_LEN_1 */
10520     { "kunpckbw",       { MaskG, MaskVex, MaskR }, 0 },
10521   },
10522   {
10523     /* VEX_W_0F50_M_0 */
10524     { "vmovmskpX",      { Gdq, XS }, 0 },
10525   },
10526   {
10527     /* VEX_W_0F51_P_0 */
10528     { "vsqrtps",        { XM, EXx }, 0 },
10529   },
10530   {
10531     /* VEX_W_0F51_P_1 */
10532     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10533   },
10534   {
10535     /* VEX_W_0F51_P_2  */
10536     { "vsqrtpd",        { XM, EXx }, 0 },
10537   },
10538   {
10539     /* VEX_W_0F51_P_3 */
10540     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10541   },
10542   {
10543     /* VEX_W_0F52_P_0 */
10544     { "vrsqrtps",       { XM, EXx }, 0 },
10545   },
10546   {
10547     /* VEX_W_0F52_P_1 */
10548     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10549   },
10550   {
10551     /* VEX_W_0F53_P_0  */
10552     { "vrcpps",         { XM, EXx }, 0 },
10553   },
10554   {
10555     /* VEX_W_0F53_P_1  */
10556     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10557   },
10558   {
10559     /* VEX_W_0F58_P_0  */
10560     { "vaddps",         { XM, Vex, EXx }, 0 },
10561   },
10562   {
10563     /* VEX_W_0F58_P_1  */
10564     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10565   },
10566   {
10567     /* VEX_W_0F58_P_2  */
10568     { "vaddpd",         { XM, Vex, EXx }, 0 },
10569   },
10570   {
10571     /* VEX_W_0F58_P_3  */
10572     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10573   },
10574   {
10575     /* VEX_W_0F59_P_0  */
10576     { "vmulps",         { XM, Vex, EXx }, 0 },
10577   },
10578   {
10579     /* VEX_W_0F59_P_1  */
10580     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10581   },
10582   {
10583     /* VEX_W_0F59_P_2  */
10584     { "vmulpd",         { XM, Vex, EXx }, 0 },
10585   },
10586   {
10587     /* VEX_W_0F59_P_3  */
10588     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10589   },
10590   {
10591     /* VEX_W_0F5A_P_0  */
10592     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10593   },
10594   {
10595     /* VEX_W_0F5A_P_1  */
10596     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10597   },
10598   {
10599     /* VEX_W_0F5A_P_3  */
10600     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10601   },
10602   {
10603     /* VEX_W_0F5B_P_0  */
10604     { "vcvtdq2ps",      { XM, EXx }, 0 },
10605   },
10606   {
10607     /* VEX_W_0F5B_P_1  */
10608     { "vcvttps2dq",     { XM, EXx }, 0 },
10609   },
10610   {
10611     /* VEX_W_0F5B_P_2  */
10612     { "vcvtps2dq",      { XM, EXx }, 0 },
10613   },
10614   {
10615     /* VEX_W_0F5C_P_0  */
10616     { "vsubps",         { XM, Vex, EXx }, 0 },
10617   },
10618   {
10619     /* VEX_W_0F5C_P_1  */
10620     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10621   },
10622   {
10623     /* VEX_W_0F5C_P_2  */
10624     { "vsubpd",         { XM, Vex, EXx }, 0 },
10625   },
10626   {
10627     /* VEX_W_0F5C_P_3  */
10628     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10629   },
10630   {
10631     /* VEX_W_0F5D_P_0  */
10632     { "vminps",         { XM, Vex, EXx }, 0 },
10633   },
10634   {
10635     /* VEX_W_0F5D_P_1  */
10636     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10637   },
10638   {
10639     /* VEX_W_0F5D_P_2  */
10640     { "vminpd",         { XM, Vex, EXx }, 0 },
10641   },
10642   {
10643     /* VEX_W_0F5D_P_3  */
10644     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10645   },
10646   {
10647     /* VEX_W_0F5E_P_0  */
10648     { "vdivps",         { XM, Vex, EXx }, 0 },
10649   },
10650   {
10651     /* VEX_W_0F5E_P_1  */
10652     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10653   },
10654   {
10655     /* VEX_W_0F5E_P_2  */
10656     { "vdivpd",         { XM, Vex, EXx }, 0 },
10657   },
10658   {
10659     /* VEX_W_0F5E_P_3  */
10660     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10661   },
10662   {
10663     /* VEX_W_0F5F_P_0  */
10664     { "vmaxps",         { XM, Vex, EXx }, 0 },
10665   },
10666   {
10667     /* VEX_W_0F5F_P_1  */
10668     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10669   },
10670   {
10671     /* VEX_W_0F5F_P_2  */
10672     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10673   },
10674   {
10675     /* VEX_W_0F5F_P_3  */
10676     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10677   },
10678   {
10679     /* VEX_W_0F60_P_2  */
10680     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10681   },
10682   {
10683     /* VEX_W_0F61_P_2  */
10684     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10685   },
10686   {
10687     /* VEX_W_0F62_P_2  */
10688     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10689   },
10690   {
10691     /* VEX_W_0F63_P_2  */
10692     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10693   },
10694   {
10695     /* VEX_W_0F64_P_2  */
10696     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10697   },
10698   {
10699     /* VEX_W_0F65_P_2  */
10700     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10701   },
10702   {
10703     /* VEX_W_0F66_P_2  */
10704     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10705   },
10706   {
10707     /* VEX_W_0F67_P_2  */
10708     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10709   },
10710   {
10711     /* VEX_W_0F68_P_2  */
10712     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10713   },
10714   {
10715     /* VEX_W_0F69_P_2  */
10716     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10717   },
10718   {
10719     /* VEX_W_0F6A_P_2  */
10720     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10721   },
10722   {
10723     /* VEX_W_0F6B_P_2  */
10724     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10725   },
10726   {
10727     /* VEX_W_0F6C_P_2  */
10728     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10729   },
10730   {
10731     /* VEX_W_0F6D_P_2  */
10732     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10733   },
10734   {
10735     /* VEX_W_0F6F_P_1  */
10736     { "vmovdqu",        { XM, EXx }, 0 },
10737   },
10738   {
10739     /* VEX_W_0F6F_P_2  */
10740     { "vmovdqa",        { XM, EXx }, 0 },
10741   },
10742   {
10743     /* VEX_W_0F70_P_1 */
10744     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10745   },
10746   {
10747     /* VEX_W_0F70_P_2 */
10748     { "vpshufd",        { XM, EXx, Ib }, 0 },
10749   },
10750   {
10751     /* VEX_W_0F70_P_3 */
10752     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10753   },
10754   {
10755     /* VEX_W_0F71_R_2_P_2  */
10756     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10757   },
10758   {
10759     /* VEX_W_0F71_R_4_P_2  */
10760     { "vpsraw",         { Vex, XS, Ib }, 0 },
10761   },
10762   {
10763     /* VEX_W_0F71_R_6_P_2  */
10764     { "vpsllw",         { Vex, XS, Ib }, 0 },
10765   },
10766   {
10767     /* VEX_W_0F72_R_2_P_2  */
10768     { "vpsrld",         { Vex, XS, Ib }, 0 },
10769   },
10770   {
10771     /* VEX_W_0F72_R_4_P_2  */
10772     { "vpsrad",         { Vex, XS, Ib }, 0 },
10773   },
10774   {
10775     /* VEX_W_0F72_R_6_P_2  */
10776     { "vpslld",         { Vex, XS, Ib }, 0 },
10777   },
10778   {
10779     /* VEX_W_0F73_R_2_P_2  */
10780     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10781   },
10782   {
10783     /* VEX_W_0F73_R_3_P_2  */
10784     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10785   },
10786   {
10787     /* VEX_W_0F73_R_6_P_2  */
10788     { "vpsllq",         { Vex, XS, Ib }, 0 },
10789   },
10790   {
10791     /* VEX_W_0F73_R_7_P_2  */
10792     { "vpslldq",        { Vex, XS, Ib }, 0 },
10793   },
10794   {
10795     /* VEX_W_0F74_P_2 */
10796     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10797   },
10798   {
10799     /* VEX_W_0F75_P_2 */
10800     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10801   },
10802   {
10803     /* VEX_W_0F76_P_2 */
10804     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10805   },
10806   {
10807     /* VEX_W_0F77_P_0 */
10808     { "",               { VZERO }, 0 },
10809   },
10810   {
10811     /* VEX_W_0F7C_P_2 */
10812     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10813   },
10814   {
10815     /* VEX_W_0F7C_P_3 */
10816     { "vhaddps",        { XM, Vex, EXx }, 0 },
10817   },
10818   {
10819     /* VEX_W_0F7D_P_2 */
10820     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10821   },
10822   {
10823     /* VEX_W_0F7D_P_3 */
10824     { "vhsubps",        { XM, Vex, EXx }, 0 },
10825   },
10826   {
10827     /* VEX_W_0F7E_P_1 */
10828     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10829   },
10830   {
10831     /* VEX_W_0F7F_P_1 */
10832     { "vmovdqu",        { EXxS, XM }, 0 },
10833   },
10834   {
10835     /* VEX_W_0F7F_P_2 */
10836     { "vmovdqa",        { EXxS, XM }, 0 },
10837   },
10838   {
10839     /* VEX_W_0F90_P_0_LEN_0 */
10840     { "kmovw",          { MaskG, MaskE }, 0 },
10841     { "kmovq",          { MaskG, MaskE }, 0 },
10842   },
10843   {
10844     /* VEX_W_0F90_P_2_LEN_0 */
10845     { "kmovb",          { MaskG, MaskBDE }, 0 },
10846     { "kmovd",          { MaskG, MaskBDE }, 0 },
10847   },
10848   {
10849     /* VEX_W_0F91_P_0_LEN_0 */
10850     { "kmovw",          { Ew, MaskG }, 0 },
10851     { "kmovq",          { Eq, MaskG }, 0 },
10852   },
10853   {
10854     /* VEX_W_0F91_P_2_LEN_0 */
10855     { "kmovb",          { Eb, MaskG }, 0 },
10856     { "kmovd",          { Ed, MaskG }, 0 },
10857   },
10858   {
10859     /* VEX_W_0F92_P_0_LEN_0 */
10860     { "kmovw",          { MaskG, Rdq }, 0 },
10861   },
10862   {
10863     /* VEX_W_0F92_P_2_LEN_0 */
10864     { "kmovb",          { MaskG, Rdq }, 0 },
10865   },
10866   {
10867     /* VEX_W_0F92_P_3_LEN_0 */
10868     { "kmovd",          { MaskG, Rdq }, 0 },
10869     { "kmovq",          { MaskG, Rdq }, 0 },
10870   },
10871   {
10872     /* VEX_W_0F93_P_0_LEN_0 */
10873     { "kmovw",          { Gdq, MaskR }, 0 },
10874   },
10875   {
10876     /* VEX_W_0F93_P_2_LEN_0 */
10877     { "kmovb",          { Gdq, MaskR }, 0 },
10878   },
10879   {
10880     /* VEX_W_0F93_P_3_LEN_0 */
10881     { "kmovd",          { Gdq, MaskR }, 0 },
10882     { "kmovq",          { Gdq, MaskR }, 0 },
10883   },
10884   {
10885     /* VEX_W_0F98_P_0_LEN_0 */
10886     { "kortestw",       { MaskG, MaskR }, 0 },
10887     { "kortestq",       { MaskG, MaskR }, 0 },
10888   },
10889   {
10890     /* VEX_W_0F98_P_2_LEN_0 */
10891     { "kortestb",       { MaskG, MaskR }, 0 },
10892     { "kortestd",       { MaskG, MaskR }, 0 },
10893   },
10894   {
10895     /* VEX_W_0F99_P_0_LEN_0 */
10896     { "ktestw", { MaskG, MaskR }, 0 },
10897     { "ktestq", { MaskG, MaskR }, 0 },
10898   },
10899   {
10900     /* VEX_W_0F99_P_2_LEN_0 */
10901     { "ktestb", { MaskG, MaskR }, 0 },
10902     { "ktestd", { MaskG, MaskR }, 0 },
10903   },
10904   {
10905     /* VEX_W_0FAE_R_2_M_0 */
10906     { "vldmxcsr",       { Md }, 0 },
10907   },
10908   {
10909     /* VEX_W_0FAE_R_3_M_0 */
10910     { "vstmxcsr",       { Md }, 0 },
10911   },
10912   {
10913     /* VEX_W_0FC2_P_0 */
10914     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10915   },
10916   {
10917     /* VEX_W_0FC2_P_1 */
10918     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10919   },
10920   {
10921     /* VEX_W_0FC2_P_2 */
10922     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10923   },
10924   {
10925     /* VEX_W_0FC2_P_3 */
10926     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10927   },
10928   {
10929     /* VEX_W_0FC4_P_2 */
10930     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10931   },
10932   {
10933     /* VEX_W_0FC5_P_2 */
10934     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10935   },
10936   {
10937     /* VEX_W_0FD0_P_2 */
10938     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10939   },
10940   {
10941     /* VEX_W_0FD0_P_3 */
10942     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10943   },
10944   {
10945     /* VEX_W_0FD1_P_2 */
10946     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10947   },
10948   {
10949     /* VEX_W_0FD2_P_2 */
10950     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10951   },
10952   {
10953     /* VEX_W_0FD3_P_2 */
10954     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10955   },
10956   {
10957     /* VEX_W_0FD4_P_2 */
10958     { "vpaddq",         { XM, Vex, EXx }, 0 },
10959   },
10960   {
10961     /* VEX_W_0FD5_P_2 */
10962     { "vpmullw",        { XM, Vex, EXx }, 0 },
10963   },
10964   {
10965     /* VEX_W_0FD6_P_2 */
10966     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10967   },
10968   {
10969     /* VEX_W_0FD7_P_2_M_1 */
10970     { "vpmovmskb",      { Gdq, XS }, 0 },
10971   },
10972   {
10973     /* VEX_W_0FD8_P_2 */
10974     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10975   },
10976   {
10977     /* VEX_W_0FD9_P_2 */
10978     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10979   },
10980   {
10981     /* VEX_W_0FDA_P_2 */
10982     { "vpminub",        { XM, Vex, EXx }, 0 },
10983   },
10984   {
10985     /* VEX_W_0FDB_P_2 */
10986     { "vpand",          { XM, Vex, EXx }, 0 },
10987   },
10988   {
10989     /* VEX_W_0FDC_P_2 */
10990     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10991   },
10992   {
10993     /* VEX_W_0FDD_P_2 */
10994     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10995   },
10996   {
10997     /* VEX_W_0FDE_P_2 */
10998     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10999   },
11000   {
11001     /* VEX_W_0FDF_P_2 */
11002     { "vpandn",         { XM, Vex, EXx }, 0 },
11003   },
11004   {
11005     /* VEX_W_0FE0_P_2  */
11006     { "vpavgb",         { XM, Vex, EXx }, 0 },
11007   },
11008   {
11009     /* VEX_W_0FE1_P_2  */
11010     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
11011   },
11012   {
11013     /* VEX_W_0FE2_P_2  */
11014     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
11015   },
11016   {
11017     /* VEX_W_0FE3_P_2  */
11018     { "vpavgw",         { XM, Vex, EXx }, 0 },
11019   },
11020   {
11021     /* VEX_W_0FE4_P_2  */
11022     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11023   },
11024   {
11025     /* VEX_W_0FE5_P_2  */
11026     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11027   },
11028   {
11029     /* VEX_W_0FE6_P_1  */
11030     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11031   },
11032   {
11033     /* VEX_W_0FE6_P_2  */
11034     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11035   },
11036   {
11037     /* VEX_W_0FE6_P_3  */
11038     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11039   },
11040   {
11041     /* VEX_W_0FE7_P_2_M_0 */
11042     { "vmovntdq",       { Mx, XM }, 0 },
11043   },
11044   {
11045     /* VEX_W_0FE8_P_2  */
11046     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11047   },
11048   {
11049     /* VEX_W_0FE9_P_2  */
11050     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11051   },
11052   {
11053     /* VEX_W_0FEA_P_2  */
11054     { "vpminsw",        { XM, Vex, EXx }, 0 },
11055   },
11056   {
11057     /* VEX_W_0FEB_P_2  */
11058     { "vpor",           { XM, Vex, EXx }, 0 },
11059   },
11060   {
11061     /* VEX_W_0FEC_P_2  */
11062     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11063   },
11064   {
11065     /* VEX_W_0FED_P_2  */
11066     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11067   },
11068   {
11069     /* VEX_W_0FEE_P_2  */
11070     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11071   },
11072   {
11073     /* VEX_W_0FEF_P_2  */
11074     { "vpxor",          { XM, Vex, EXx }, 0 },
11075   },
11076   {
11077     /* VEX_W_0FF0_P_3_M_0 */
11078     { "vlddqu",         { XM, M }, 0 },
11079   },
11080   {
11081     /* VEX_W_0FF1_P_2 */
11082     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11083   },
11084   {
11085     /* VEX_W_0FF2_P_2 */
11086     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11087   },
11088   {
11089     /* VEX_W_0FF3_P_2 */
11090     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11091   },
11092   {
11093     /* VEX_W_0FF4_P_2 */
11094     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11095   },
11096   {
11097     /* VEX_W_0FF5_P_2 */
11098     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11099   },
11100   {
11101     /* VEX_W_0FF6_P_2 */
11102     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11103   },
11104   {
11105     /* VEX_W_0FF7_P_2 */
11106     { "vmaskmovdqu",    { XM, XS }, 0 },
11107   },
11108   {
11109     /* VEX_W_0FF8_P_2 */
11110     { "vpsubb",         { XM, Vex, EXx }, 0 },
11111   },
11112   {
11113     /* VEX_W_0FF9_P_2 */
11114     { "vpsubw",         { XM, Vex, EXx }, 0 },
11115   },
11116   {
11117     /* VEX_W_0FFA_P_2 */
11118     { "vpsubd",         { XM, Vex, EXx }, 0 },
11119   },
11120   {
11121     /* VEX_W_0FFB_P_2 */
11122     { "vpsubq",         { XM, Vex, EXx }, 0 },
11123   },
11124   {
11125     /* VEX_W_0FFC_P_2 */
11126     { "vpaddb",         { XM, Vex, EXx }, 0 },
11127   },
11128   {
11129     /* VEX_W_0FFD_P_2 */
11130     { "vpaddw",         { XM, Vex, EXx }, 0 },
11131   },
11132   {
11133     /* VEX_W_0FFE_P_2 */
11134     { "vpaddd",         { XM, Vex, EXx }, 0 },
11135   },
11136   {
11137     /* VEX_W_0F3800_P_2  */
11138     { "vpshufb",        { XM, Vex, EXx }, 0 },
11139   },
11140   {
11141     /* VEX_W_0F3801_P_2  */
11142     { "vphaddw",        { XM, Vex, EXx }, 0 },
11143   },
11144   {
11145     /* VEX_W_0F3802_P_2  */
11146     { "vphaddd",        { XM, Vex, EXx }, 0 },
11147   },
11148   {
11149     /* VEX_W_0F3803_P_2  */
11150     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11151   },
11152   {
11153     /* VEX_W_0F3804_P_2  */
11154     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11155   },
11156   {
11157     /* VEX_W_0F3805_P_2  */
11158     { "vphsubw",        { XM, Vex, EXx }, 0 },
11159   },
11160   {
11161     /* VEX_W_0F3806_P_2  */
11162     { "vphsubd",        { XM, Vex, EXx }, 0 },
11163   },
11164   {
11165     /* VEX_W_0F3807_P_2  */
11166     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11167   },
11168   {
11169     /* VEX_W_0F3808_P_2  */
11170     { "vpsignb",        { XM, Vex, EXx }, 0 },
11171   },
11172   {
11173     /* VEX_W_0F3809_P_2  */
11174     { "vpsignw",        { XM, Vex, EXx }, 0 },
11175   },
11176   {
11177     /* VEX_W_0F380A_P_2  */
11178     { "vpsignd",        { XM, Vex, EXx }, 0 },
11179   },
11180   {
11181     /* VEX_W_0F380B_P_2  */
11182     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11183   },
11184   {
11185     /* VEX_W_0F380C_P_2  */
11186     { "vpermilps",      { XM, Vex, EXx }, 0 },
11187   },
11188   {
11189     /* VEX_W_0F380D_P_2  */
11190     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11191   },
11192   {
11193     /* VEX_W_0F380E_P_2  */
11194     { "vtestps",        { XM, EXx }, 0 },
11195   },
11196   {
11197     /* VEX_W_0F380F_P_2  */
11198     { "vtestpd",        { XM, EXx }, 0 },
11199   },
11200   {
11201     /* VEX_W_0F3816_P_2  */
11202     { "vpermps",        { XM, Vex, EXx }, 0 },
11203   },
11204   {
11205     /* VEX_W_0F3817_P_2 */
11206     { "vptest",         { XM, EXx }, 0 },
11207   },
11208   {
11209     /* VEX_W_0F3818_P_2 */
11210     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11211   },
11212   {
11213     /* VEX_W_0F3819_P_2 */
11214     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11215   },
11216   {
11217     /* VEX_W_0F381A_P_2_M_0 */
11218     { "vbroadcastf128", { XM, Mxmm }, 0 },
11219   },
11220   {
11221     /* VEX_W_0F381C_P_2 */
11222     { "vpabsb",         { XM, EXx }, 0 },
11223   },
11224   {
11225     /* VEX_W_0F381D_P_2 */
11226     { "vpabsw",         { XM, EXx }, 0 },
11227   },
11228   {
11229     /* VEX_W_0F381E_P_2 */
11230     { "vpabsd",         { XM, EXx }, 0 },
11231   },
11232   {
11233     /* VEX_W_0F3820_P_2 */
11234     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11235   },
11236   {
11237     /* VEX_W_0F3821_P_2 */
11238     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11239   },
11240   {
11241     /* VEX_W_0F3822_P_2 */
11242     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11243   },
11244   {
11245     /* VEX_W_0F3823_P_2 */
11246     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11247   },
11248   {
11249     /* VEX_W_0F3824_P_2 */
11250     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11251   },
11252   {
11253     /* VEX_W_0F3825_P_2 */
11254     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11255   },
11256   {
11257     /* VEX_W_0F3828_P_2 */
11258     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11259   },
11260   {
11261     /* VEX_W_0F3829_P_2 */
11262     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11263   },
11264   {
11265     /* VEX_W_0F382A_P_2_M_0 */
11266     { "vmovntdqa",      { XM, Mx }, 0 },
11267   },
11268   {
11269     /* VEX_W_0F382B_P_2 */
11270     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11271   },
11272   {
11273     /* VEX_W_0F382C_P_2_M_0 */
11274     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11275   },
11276   {
11277     /* VEX_W_0F382D_P_2_M_0 */
11278     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11279   },
11280   {
11281     /* VEX_W_0F382E_P_2_M_0 */
11282     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11283   },
11284   {
11285     /* VEX_W_0F382F_P_2_M_0 */
11286     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11287   },
11288   {
11289     /* VEX_W_0F3830_P_2 */
11290     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11291   },
11292   {
11293     /* VEX_W_0F3831_P_2 */
11294     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11295   },
11296   {
11297     /* VEX_W_0F3832_P_2 */
11298     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11299   },
11300   {
11301     /* VEX_W_0F3833_P_2 */
11302     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11303   },
11304   {
11305     /* VEX_W_0F3834_P_2 */
11306     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11307   },
11308   {
11309     /* VEX_W_0F3835_P_2 */
11310     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11311   },
11312   {
11313     /* VEX_W_0F3836_P_2  */
11314     { "vpermd",         { XM, Vex, EXx }, 0 },
11315   },
11316   {
11317     /* VEX_W_0F3837_P_2 */
11318     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11319   },
11320   {
11321     /* VEX_W_0F3838_P_2 */
11322     { "vpminsb",        { XM, Vex, EXx }, 0 },
11323   },
11324   {
11325     /* VEX_W_0F3839_P_2 */
11326     { "vpminsd",        { XM, Vex, EXx }, 0 },
11327   },
11328   {
11329     /* VEX_W_0F383A_P_2 */
11330     { "vpminuw",        { XM, Vex, EXx }, 0 },
11331   },
11332   {
11333     /* VEX_W_0F383B_P_2 */
11334     { "vpminud",        { XM, Vex, EXx }, 0 },
11335   },
11336   {
11337     /* VEX_W_0F383C_P_2 */
11338     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11339   },
11340   {
11341     /* VEX_W_0F383D_P_2 */
11342     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11343   },
11344   {
11345     /* VEX_W_0F383E_P_2 */
11346     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11347   },
11348   {
11349     /* VEX_W_0F383F_P_2 */
11350     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11351   },
11352   {
11353     /* VEX_W_0F3840_P_2 */
11354     { "vpmulld",        { XM, Vex, EXx }, 0 },
11355   },
11356   {
11357     /* VEX_W_0F3841_P_2 */
11358     { "vphminposuw",    { XM, EXx }, 0 },
11359   },
11360   {
11361     /* VEX_W_0F3846_P_2 */
11362     { "vpsravd",        { XM, Vex, EXx }, 0 },
11363   },
11364   {
11365     /* VEX_W_0F3858_P_2 */
11366     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11367   },
11368   {
11369     /* VEX_W_0F3859_P_2 */
11370     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11371   },
11372   {
11373     /* VEX_W_0F385A_P_2_M_0 */
11374     { "vbroadcasti128", { XM, Mxmm }, 0 },
11375   },
11376   {
11377     /* VEX_W_0F3878_P_2 */
11378     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11379   },
11380   {
11381     /* VEX_W_0F3879_P_2 */
11382     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11383   },
11384   {
11385     /* VEX_W_0F38DB_P_2 */
11386     { "vaesimc",        { XM, EXx }, 0 },
11387   },
11388   {
11389     /* VEX_W_0F38DC_P_2 */
11390     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11391   },
11392   {
11393     /* VEX_W_0F38DD_P_2 */
11394     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11395   },
11396   {
11397     /* VEX_W_0F38DE_P_2 */
11398     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11399   },
11400   {
11401     /* VEX_W_0F38DF_P_2 */
11402     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11403   },
11404   {
11405     /* VEX_W_0F3A00_P_2 */
11406     { Bad_Opcode },
11407     { "vpermq",         { XM, EXx, Ib }, 0 },
11408   },
11409   {
11410     /* VEX_W_0F3A01_P_2 */
11411     { Bad_Opcode },
11412     { "vpermpd",        { XM, EXx, Ib }, 0 },
11413   },
11414   {
11415     /* VEX_W_0F3A02_P_2 */
11416     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11417   },
11418   {
11419     /* VEX_W_0F3A04_P_2 */
11420     { "vpermilps",      { XM, EXx, Ib }, 0 },
11421   },
11422   {
11423     /* VEX_W_0F3A05_P_2 */
11424     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11425   },
11426   {
11427     /* VEX_W_0F3A06_P_2 */
11428     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11429   },
11430   {
11431     /* VEX_W_0F3A08_P_2 */
11432     { "vroundps",       { XM, EXx, Ib }, 0 },
11433   },
11434   {
11435     /* VEX_W_0F3A09_P_2 */
11436     { "vroundpd",       { XM, EXx, Ib }, 0 },
11437   },
11438   {
11439     /* VEX_W_0F3A0A_P_2 */
11440     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11441   },
11442   {
11443     /* VEX_W_0F3A0B_P_2 */
11444     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11445   },
11446   {
11447     /* VEX_W_0F3A0C_P_2 */
11448     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11449   },
11450   {
11451     /* VEX_W_0F3A0D_P_2 */
11452     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11453   },
11454   {
11455     /* VEX_W_0F3A0E_P_2 */
11456     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11457   },
11458   {
11459     /* VEX_W_0F3A0F_P_2 */
11460     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11461   },
11462   {
11463     /* VEX_W_0F3A14_P_2 */
11464     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11465   },
11466   {
11467     /* VEX_W_0F3A15_P_2 */
11468     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11469   },
11470   {
11471     /* VEX_W_0F3A18_P_2 */
11472     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11473   },
11474   {
11475     /* VEX_W_0F3A19_P_2 */
11476     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11477   },
11478   {
11479     /* VEX_W_0F3A20_P_2 */
11480     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11481   },
11482   {
11483     /* VEX_W_0F3A21_P_2 */
11484     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11485   },
11486   {
11487     /* VEX_W_0F3A30_P_2_LEN_0 */
11488     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11489     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11490   },
11491   {
11492     /* VEX_W_0F3A31_P_2_LEN_0 */
11493     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11494     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11495   },
11496   {
11497     /* VEX_W_0F3A32_P_2_LEN_0 */
11498     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11499     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11500   },
11501   {
11502     /* VEX_W_0F3A33_P_2_LEN_0 */
11503     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11504     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11505   },
11506   {
11507     /* VEX_W_0F3A38_P_2 */
11508     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11509   },
11510   {
11511     /* VEX_W_0F3A39_P_2 */
11512     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11513   },
11514   {
11515     /* VEX_W_0F3A40_P_2 */
11516     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11517   },
11518   {
11519     /* VEX_W_0F3A41_P_2 */
11520     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11521   },
11522   {
11523     /* VEX_W_0F3A42_P_2 */
11524     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11525   },
11526   {
11527     /* VEX_W_0F3A44_P_2 */
11528     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11529   },
11530   {
11531     /* VEX_W_0F3A46_P_2 */
11532     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11533   },
11534   {
11535     /* VEX_W_0F3A48_P_2 */
11536     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11537     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11538   },
11539   {
11540     /* VEX_W_0F3A49_P_2 */
11541     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11542     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11543   },
11544   {
11545     /* VEX_W_0F3A4A_P_2 */
11546     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11547   },
11548   {
11549     /* VEX_W_0F3A4B_P_2 */
11550     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11551   },
11552   {
11553     /* VEX_W_0F3A4C_P_2 */
11554     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11555   },
11556   {
11557     /* VEX_W_0F3A60_P_2 */
11558     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11559   },
11560   {
11561     /* VEX_W_0F3A61_P_2 */
11562     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11563   },
11564   {
11565     /* VEX_W_0F3A62_P_2 */
11566     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11567   },
11568   {
11569     /* VEX_W_0F3A63_P_2 */
11570     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11571   },
11572   {
11573     /* VEX_W_0F3ADF_P_2 */
11574     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11575   },
11576 #define NEED_VEX_W_TABLE
11577 #include "i386-dis-evex.h"
11578 #undef NEED_VEX_W_TABLE
11579 };
11580
11581 static const struct dis386 mod_table[][2] = {
11582   {
11583     /* MOD_8D */
11584     { "leaS",           { Gv, M }, 0 },
11585   },
11586   {
11587     /* MOD_C6_REG_7 */
11588     { Bad_Opcode },
11589     { RM_TABLE (RM_C6_REG_7) },
11590   },
11591   {
11592     /* MOD_C7_REG_7 */
11593     { Bad_Opcode },
11594     { RM_TABLE (RM_C7_REG_7) },
11595   },
11596   {
11597     /* MOD_FF_REG_3 */
11598     { "Jcall^", { indirEp }, 0 },
11599   },
11600   {
11601     /* MOD_FF_REG_5 */
11602     { "Jjmp^", { indirEp }, 0 },
11603   },
11604   {
11605     /* MOD_0F01_REG_0 */
11606     { X86_64_TABLE (X86_64_0F01_REG_0) },
11607     { RM_TABLE (RM_0F01_REG_0) },
11608   },
11609   {
11610     /* MOD_0F01_REG_1 */
11611     { X86_64_TABLE (X86_64_0F01_REG_1) },
11612     { RM_TABLE (RM_0F01_REG_1) },
11613   },
11614   {
11615     /* MOD_0F01_REG_2 */
11616     { X86_64_TABLE (X86_64_0F01_REG_2) },
11617     { RM_TABLE (RM_0F01_REG_2) },
11618   },
11619   {
11620     /* MOD_0F01_REG_3 */
11621     { X86_64_TABLE (X86_64_0F01_REG_3) },
11622     { RM_TABLE (RM_0F01_REG_3) },
11623   },
11624   {
11625     /* MOD_0F01_REG_7 */
11626     { "invlpg",         { Mb }, 0 },
11627     { RM_TABLE (RM_0F01_REG_7) },
11628   },
11629   {
11630     /* MOD_0F12_PREFIX_0 */
11631     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11632     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11633   },
11634   {
11635     /* MOD_0F13 */
11636     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11637   },
11638   {
11639     /* MOD_0F16_PREFIX_0 */
11640     { "movhps",         { XM, EXq }, 0 },
11641     { "movlhps",        { XM, EXq }, 0 },
11642   },
11643   {
11644     /* MOD_0F17 */
11645     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11646   },
11647   {
11648     /* MOD_0F18_REG_0 */
11649     { "prefetchnta",    { Mb }, 0 },
11650   },
11651   {
11652     /* MOD_0F18_REG_1 */
11653     { "prefetcht0",     { Mb }, 0 },
11654   },
11655   {
11656     /* MOD_0F18_REG_2 */
11657     { "prefetcht1",     { Mb }, 0 },
11658   },
11659   {
11660     /* MOD_0F18_REG_3 */
11661     { "prefetcht2",     { Mb }, 0 },
11662   },
11663   {
11664     /* MOD_0F18_REG_4 */
11665     { "nop/reserved",   { Mb }, 0 },
11666   },
11667   {
11668     /* MOD_0F18_REG_5 */
11669     { "nop/reserved",   { Mb }, 0 },
11670   },
11671   {
11672     /* MOD_0F18_REG_6 */
11673     { "nop/reserved",   { Mb }, 0 },
11674   },
11675   {
11676     /* MOD_0F18_REG_7 */
11677     { "nop/reserved",   { Mb }, 0 },
11678   },
11679   {
11680     /* MOD_0F1A_PREFIX_0 */
11681     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11682     { "nopQ",           { Ev }, 0 },
11683   },
11684   {
11685     /* MOD_0F1B_PREFIX_0 */
11686     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11687     { "nopQ",           { Ev }, 0 },
11688   },
11689   {
11690     /* MOD_0F1B_PREFIX_1 */
11691     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11692     { "nopQ",           { Ev }, 0 },
11693   },
11694   {
11695     /* MOD_0F24 */
11696     { Bad_Opcode },
11697     { "movL",           { Rd, Td }, 0 },
11698   },
11699   {
11700     /* MOD_0F26 */
11701     { Bad_Opcode },
11702     { "movL",           { Td, Rd }, 0 },
11703   },
11704   {
11705     /* MOD_0F2B_PREFIX_0 */
11706     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11707   },
11708   {
11709     /* MOD_0F2B_PREFIX_1 */
11710     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11711   },
11712   {
11713     /* MOD_0F2B_PREFIX_2 */
11714     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11715   },
11716   {
11717     /* MOD_0F2B_PREFIX_3 */
11718     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11719   },
11720   {
11721     /* MOD_0F51 */
11722     { Bad_Opcode },
11723     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11724   },
11725   {
11726     /* MOD_0F71_REG_2 */
11727     { Bad_Opcode },
11728     { "psrlw",          { MS, Ib }, 0 },
11729   },
11730   {
11731     /* MOD_0F71_REG_4 */
11732     { Bad_Opcode },
11733     { "psraw",          { MS, Ib }, 0 },
11734   },
11735   {
11736     /* MOD_0F71_REG_6 */
11737     { Bad_Opcode },
11738     { "psllw",          { MS, Ib }, 0 },
11739   },
11740   {
11741     /* MOD_0F72_REG_2 */
11742     { Bad_Opcode },
11743     { "psrld",          { MS, Ib }, 0 },
11744   },
11745   {
11746     /* MOD_0F72_REG_4 */
11747     { Bad_Opcode },
11748     { "psrad",          { MS, Ib }, 0 },
11749   },
11750   {
11751     /* MOD_0F72_REG_6 */
11752     { Bad_Opcode },
11753     { "pslld",          { MS, Ib }, 0 },
11754   },
11755   {
11756     /* MOD_0F73_REG_2 */
11757     { Bad_Opcode },
11758     { "psrlq",          { MS, Ib }, 0 },
11759   },
11760   {
11761     /* MOD_0F73_REG_3 */
11762     { Bad_Opcode },
11763     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11764   },
11765   {
11766     /* MOD_0F73_REG_6 */
11767     { Bad_Opcode },
11768     { "psllq",          { MS, Ib }, 0 },
11769   },
11770   {
11771     /* MOD_0F73_REG_7 */
11772     { Bad_Opcode },
11773     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11774   },
11775   {
11776     /* MOD_0FAE_REG_0 */
11777     { "fxsave",         { FXSAVE }, 0 },
11778     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11779   },
11780   {
11781     /* MOD_0FAE_REG_1 */
11782     { "fxrstor",        { FXSAVE }, 0 },
11783     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11784   },
11785   {
11786     /* MOD_0FAE_REG_2 */
11787     { "ldmxcsr",        { Md }, 0 },
11788     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11789   },
11790   {
11791     /* MOD_0FAE_REG_3 */
11792     { "stmxcsr",        { Md }, 0 },
11793     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11794   },
11795   {
11796     /* MOD_0FAE_REG_4 */
11797     { "xsave",          { FXSAVE }, 0 },
11798   },
11799   {
11800     /* MOD_0FAE_REG_5 */
11801     { "xrstor",         { FXSAVE }, 0 },
11802     { RM_TABLE (RM_0FAE_REG_5) },
11803   },
11804   {
11805     /* MOD_0FAE_REG_6 */
11806     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11807     { RM_TABLE (RM_0FAE_REG_6) },
11808   },
11809   {
11810     /* MOD_0FAE_REG_7 */
11811     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11812     { RM_TABLE (RM_0FAE_REG_7) },
11813   },
11814   {
11815     /* MOD_0FB2 */
11816     { "lssS",           { Gv, Mp }, 0 },
11817   },
11818   {
11819     /* MOD_0FB4 */
11820     { "lfsS",           { Gv, Mp }, 0 },
11821   },
11822   {
11823     /* MOD_0FB5 */
11824     { "lgsS",           { Gv, Mp }, 0 },
11825   },
11826   {
11827     /* MOD_0FC7_REG_3 */
11828     { "xrstors",                { FXSAVE }, 0 },
11829   },
11830   {
11831     /* MOD_0FC7_REG_4 */
11832     { "xsavec",         { FXSAVE }, 0 },
11833   },
11834   {
11835     /* MOD_0FC7_REG_5 */
11836     { "xsaves",         { FXSAVE }, 0 },
11837   },
11838   {
11839     /* MOD_0FC7_REG_6 */
11840     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11841     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11842   },
11843   {
11844     /* MOD_0FC7_REG_7 */
11845     { "vmptrst",        { Mq }, 0 },
11846     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11847   },
11848   {
11849     /* MOD_0FD7 */
11850     { Bad_Opcode },
11851     { "pmovmskb",       { Gdq, MS }, 0 },
11852   },
11853   {
11854     /* MOD_0FE7_PREFIX_2 */
11855     { "movntdq",        { Mx, XM }, 0 },
11856   },
11857   {
11858     /* MOD_0FF0_PREFIX_3 */
11859     { "lddqu",          { XM, M }, 0 },
11860   },
11861   {
11862     /* MOD_0F382A_PREFIX_2 */
11863     { "movntdqa",       { XM, Mx }, 0 },
11864   },
11865   {
11866     /* MOD_62_32BIT */
11867     { "bound{S|}",      { Gv, Ma }, 0 },
11868     { EVEX_TABLE (EVEX_0F) },
11869   },
11870   {
11871     /* MOD_C4_32BIT */
11872     { "lesS",           { Gv, Mp }, 0 },
11873     { VEX_C4_TABLE (VEX_0F) },
11874   },
11875   {
11876     /* MOD_C5_32BIT */
11877     { "ldsS",           { Gv, Mp }, 0 },
11878     { VEX_C5_TABLE (VEX_0F) },
11879   },
11880   {
11881     /* MOD_VEX_0F12_PREFIX_0 */
11882     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11883     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11884   },
11885   {
11886     /* MOD_VEX_0F13 */
11887     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11888   },
11889   {
11890     /* MOD_VEX_0F16_PREFIX_0 */
11891     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11892     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11893   },
11894   {
11895     /* MOD_VEX_0F17 */
11896     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11897   },
11898   {
11899     /* MOD_VEX_0F2B */
11900     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11901   },
11902   {
11903     /* MOD_VEX_0F50 */
11904     { Bad_Opcode },
11905     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11906   },
11907   {
11908     /* MOD_VEX_0F71_REG_2 */
11909     { Bad_Opcode },
11910     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11911   },
11912   {
11913     /* MOD_VEX_0F71_REG_4 */
11914     { Bad_Opcode },
11915     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11916   },
11917   {
11918     /* MOD_VEX_0F71_REG_6 */
11919     { Bad_Opcode },
11920     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11921   },
11922   {
11923     /* MOD_VEX_0F72_REG_2 */
11924     { Bad_Opcode },
11925     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11926   },
11927   {
11928     /* MOD_VEX_0F72_REG_4 */
11929     { Bad_Opcode },
11930     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11931   },
11932   {
11933     /* MOD_VEX_0F72_REG_6 */
11934     { Bad_Opcode },
11935     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11936   },
11937   {
11938     /* MOD_VEX_0F73_REG_2 */
11939     { Bad_Opcode },
11940     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11941   },
11942   {
11943     /* MOD_VEX_0F73_REG_3 */
11944     { Bad_Opcode },
11945     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11946   },
11947   {
11948     /* MOD_VEX_0F73_REG_6 */
11949     { Bad_Opcode },
11950     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11951   },
11952   {
11953     /* MOD_VEX_0F73_REG_7 */
11954     { Bad_Opcode },
11955     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11956   },
11957   {
11958     /* MOD_VEX_0FAE_REG_2 */
11959     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11960   },
11961   {
11962     /* MOD_VEX_0FAE_REG_3 */
11963     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11964   },
11965   {
11966     /* MOD_VEX_0FD7_PREFIX_2 */
11967     { Bad_Opcode },
11968     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11969   },
11970   {
11971     /* MOD_VEX_0FE7_PREFIX_2 */
11972     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11973   },
11974   {
11975     /* MOD_VEX_0FF0_PREFIX_3 */
11976     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11977   },
11978   {
11979     /* MOD_VEX_0F381A_PREFIX_2 */
11980     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11981   },
11982   {
11983     /* MOD_VEX_0F382A_PREFIX_2 */
11984     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11985   },
11986   {
11987     /* MOD_VEX_0F382C_PREFIX_2 */
11988     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11989   },
11990   {
11991     /* MOD_VEX_0F382D_PREFIX_2 */
11992     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11993   },
11994   {
11995     /* MOD_VEX_0F382E_PREFIX_2 */
11996     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11997   },
11998   {
11999     /* MOD_VEX_0F382F_PREFIX_2 */
12000     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12001   },
12002   {
12003     /* MOD_VEX_0F385A_PREFIX_2 */
12004     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12005   },
12006   {
12007     /* MOD_VEX_0F388C_PREFIX_2 */
12008     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12009   },
12010   {
12011     /* MOD_VEX_0F388E_PREFIX_2 */
12012     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12013   },
12014 #define NEED_MOD_TABLE
12015 #include "i386-dis-evex.h"
12016 #undef NEED_MOD_TABLE
12017 };
12018
12019 static const struct dis386 rm_table[][8] = {
12020   {
12021     /* RM_C6_REG_7 */
12022     { "xabort",         { Skip_MODRM, Ib }, 0 },
12023   },
12024   {
12025     /* RM_C7_REG_7 */
12026     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12027   },
12028   {
12029     /* RM_0F01_REG_0 */
12030     { Bad_Opcode },
12031     { "vmcall",         { Skip_MODRM }, 0 },
12032     { "vmlaunch",       { Skip_MODRM }, 0 },
12033     { "vmresume",       { Skip_MODRM }, 0 },
12034     { "vmxoff",         { Skip_MODRM }, 0 },
12035   },
12036   {
12037     /* RM_0F01_REG_1 */
12038     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12039     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12040     { "clac",           { Skip_MODRM }, 0 },
12041     { "stac",           { Skip_MODRM }, 0 },
12042     { Bad_Opcode },
12043     { Bad_Opcode },
12044     { Bad_Opcode },
12045     { "encls",          { Skip_MODRM }, 0 },
12046   },
12047   {
12048     /* RM_0F01_REG_2 */
12049     { "xgetbv",         { Skip_MODRM }, 0 },
12050     { "xsetbv",         { Skip_MODRM }, 0 },
12051     { Bad_Opcode },
12052     { Bad_Opcode },
12053     { "vmfunc",         { Skip_MODRM }, 0 },
12054     { "xend",           { Skip_MODRM }, 0 },
12055     { "xtest",          { Skip_MODRM }, 0 },
12056     { "enclu",          { Skip_MODRM }, 0 },
12057   },
12058   {
12059     /* RM_0F01_REG_3 */
12060     { "vmrun",          { Skip_MODRM }, 0 },
12061     { "vmmcall",        { Skip_MODRM }, 0 },
12062     { "vmload",         { Skip_MODRM }, 0 },
12063     { "vmsave",         { Skip_MODRM }, 0 },
12064     { "stgi",           { Skip_MODRM }, 0 },
12065     { "clgi",           { Skip_MODRM }, 0 },
12066     { "skinit",         { Skip_MODRM }, 0 },
12067     { "invlpga",        { Skip_MODRM }, 0 },
12068   },
12069   {
12070     /* RM_0F01_REG_7 */
12071     { "swapgs",         { Skip_MODRM }, 0  },
12072     { "rdtscp",         { Skip_MODRM }, 0  },
12073     { Bad_Opcode },
12074     { Bad_Opcode },
12075     { "clzero",         { Skip_MODRM }, 0  },
12076   },
12077   {
12078     /* RM_0FAE_REG_5 */
12079     { "lfence",         { Skip_MODRM }, 0 },
12080   },
12081   {
12082     /* RM_0FAE_REG_6 */
12083     { "mfence",         { Skip_MODRM }, 0 },
12084   },
12085   {
12086     /* RM_0FAE_REG_7 */
12087     { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12088   },
12089 };
12090
12091 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12092
12093 /* We use the high bit to indicate different name for the same
12094    prefix.  */
12095 #define REP_PREFIX      (0xf3 | 0x100)
12096 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12097 #define XRELEASE_PREFIX (0xf3 | 0x400)
12098 #define BND_PREFIX      (0xf2 | 0x400)
12099
12100 static int
12101 ckprefix (void)
12102 {
12103   int newrex, i, length;
12104   rex = 0;
12105   rex_ignored = 0;
12106   prefixes = 0;
12107   used_prefixes = 0;
12108   rex_used = 0;
12109   last_lock_prefix = -1;
12110   last_repz_prefix = -1;
12111   last_repnz_prefix = -1;
12112   last_data_prefix = -1;
12113   last_addr_prefix = -1;
12114   last_rex_prefix = -1;
12115   last_seg_prefix = -1;
12116   fwait_prefix = -1;
12117   active_seg_prefix = 0;
12118   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12119     all_prefixes[i] = 0;
12120   i = 0;
12121   length = 0;
12122   /* The maximum instruction length is 15bytes.  */
12123   while (length < MAX_CODE_LENGTH - 1)
12124     {
12125       FETCH_DATA (the_info, codep + 1);
12126       newrex = 0;
12127       switch (*codep)
12128         {
12129         /* REX prefixes family.  */
12130         case 0x40:
12131         case 0x41:
12132         case 0x42:
12133         case 0x43:
12134         case 0x44:
12135         case 0x45:
12136         case 0x46:
12137         case 0x47:
12138         case 0x48:
12139         case 0x49:
12140         case 0x4a:
12141         case 0x4b:
12142         case 0x4c:
12143         case 0x4d:
12144         case 0x4e:
12145         case 0x4f:
12146           if (address_mode == mode_64bit)
12147             newrex = *codep;
12148           else
12149             return 1;
12150           last_rex_prefix = i;
12151           break;
12152         case 0xf3:
12153           prefixes |= PREFIX_REPZ;
12154           last_repz_prefix = i;
12155           break;
12156         case 0xf2:
12157           prefixes |= PREFIX_REPNZ;
12158           last_repnz_prefix = i;
12159           break;
12160         case 0xf0:
12161           prefixes |= PREFIX_LOCK;
12162           last_lock_prefix = i;
12163           break;
12164         case 0x2e:
12165           prefixes |= PREFIX_CS;
12166           last_seg_prefix = i;
12167           active_seg_prefix = PREFIX_CS;
12168           break;
12169         case 0x36:
12170           prefixes |= PREFIX_SS;
12171           last_seg_prefix = i;
12172           active_seg_prefix = PREFIX_SS;
12173           break;
12174         case 0x3e:
12175           prefixes |= PREFIX_DS;
12176           last_seg_prefix = i;
12177           active_seg_prefix = PREFIX_DS;
12178           break;
12179         case 0x26:
12180           prefixes |= PREFIX_ES;
12181           last_seg_prefix = i;
12182           active_seg_prefix = PREFIX_ES;
12183           break;
12184         case 0x64:
12185           prefixes |= PREFIX_FS;
12186           last_seg_prefix = i;
12187           active_seg_prefix = PREFIX_FS;
12188           break;
12189         case 0x65:
12190           prefixes |= PREFIX_GS;
12191           last_seg_prefix = i;
12192           active_seg_prefix = PREFIX_GS;
12193           break;
12194         case 0x66:
12195           prefixes |= PREFIX_DATA;
12196           last_data_prefix = i;
12197           break;
12198         case 0x67:
12199           prefixes |= PREFIX_ADDR;
12200           last_addr_prefix = i;
12201           break;
12202         case FWAIT_OPCODE:
12203           /* fwait is really an instruction.  If there are prefixes
12204              before the fwait, they belong to the fwait, *not* to the
12205              following instruction.  */
12206           fwait_prefix = i;
12207           if (prefixes || rex)
12208             {
12209               prefixes |= PREFIX_FWAIT;
12210               codep++;
12211               /* This ensures that the previous REX prefixes are noticed
12212                  as unused prefixes, as in the return case below.  */
12213               rex_used = rex;
12214               return 1;
12215             }
12216           prefixes = PREFIX_FWAIT;
12217           break;
12218         default:
12219           return 1;
12220         }
12221       /* Rex is ignored when followed by another prefix.  */
12222       if (rex)
12223         {
12224           rex_used = rex;
12225           return 1;
12226         }
12227       if (*codep != FWAIT_OPCODE)
12228         all_prefixes[i++] = *codep;
12229       rex = newrex;
12230       codep++;
12231       length++;
12232     }
12233   return 0;
12234 }
12235
12236 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12237    prefix byte.  */
12238
12239 static const char *
12240 prefix_name (int pref, int sizeflag)
12241 {
12242   static const char *rexes [16] =
12243     {
12244       "rex",            /* 0x40 */
12245       "rex.B",          /* 0x41 */
12246       "rex.X",          /* 0x42 */
12247       "rex.XB",         /* 0x43 */
12248       "rex.R",          /* 0x44 */
12249       "rex.RB",         /* 0x45 */
12250       "rex.RX",         /* 0x46 */
12251       "rex.RXB",        /* 0x47 */
12252       "rex.W",          /* 0x48 */
12253       "rex.WB",         /* 0x49 */
12254       "rex.WX",         /* 0x4a */
12255       "rex.WXB",        /* 0x4b */
12256       "rex.WR",         /* 0x4c */
12257       "rex.WRB",        /* 0x4d */
12258       "rex.WRX",        /* 0x4e */
12259       "rex.WRXB",       /* 0x4f */
12260     };
12261
12262   switch (pref)
12263     {
12264     /* REX prefixes family.  */
12265     case 0x40:
12266     case 0x41:
12267     case 0x42:
12268     case 0x43:
12269     case 0x44:
12270     case 0x45:
12271     case 0x46:
12272     case 0x47:
12273     case 0x48:
12274     case 0x49:
12275     case 0x4a:
12276     case 0x4b:
12277     case 0x4c:
12278     case 0x4d:
12279     case 0x4e:
12280     case 0x4f:
12281       return rexes [pref - 0x40];
12282     case 0xf3:
12283       return "repz";
12284     case 0xf2:
12285       return "repnz";
12286     case 0xf0:
12287       return "lock";
12288     case 0x2e:
12289       return "cs";
12290     case 0x36:
12291       return "ss";
12292     case 0x3e:
12293       return "ds";
12294     case 0x26:
12295       return "es";
12296     case 0x64:
12297       return "fs";
12298     case 0x65:
12299       return "gs";
12300     case 0x66:
12301       return (sizeflag & DFLAG) ? "data16" : "data32";
12302     case 0x67:
12303       if (address_mode == mode_64bit)
12304         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12305       else
12306         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12307     case FWAIT_OPCODE:
12308       return "fwait";
12309     case REP_PREFIX:
12310       return "rep";
12311     case XACQUIRE_PREFIX:
12312       return "xacquire";
12313     case XRELEASE_PREFIX:
12314       return "xrelease";
12315     case BND_PREFIX:
12316       return "bnd";
12317     default:
12318       return NULL;
12319     }
12320 }
12321
12322 static char op_out[MAX_OPERANDS][100];
12323 static int op_ad, op_index[MAX_OPERANDS];
12324 static int two_source_ops;
12325 static bfd_vma op_address[MAX_OPERANDS];
12326 static bfd_vma op_riprel[MAX_OPERANDS];
12327 static bfd_vma start_pc;
12328
12329 /*
12330  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12331  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12332  *   section of the "Virtual 8086 Mode" chapter.)
12333  * 'pc' should be the address of this instruction, it will
12334  *   be used to print the target address if this is a relative jump or call
12335  * The function returns the length of this instruction in bytes.
12336  */
12337
12338 static char intel_syntax;
12339 static char intel_mnemonic = !SYSV386_COMPAT;
12340 static char open_char;
12341 static char close_char;
12342 static char separator_char;
12343 static char scale_char;
12344
12345 /* Here for backwards compatibility.  When gdb stops using
12346    print_insn_i386_att and print_insn_i386_intel these functions can
12347    disappear, and print_insn_i386 be merged into print_insn.  */
12348 int
12349 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12350 {
12351   intel_syntax = 0;
12352
12353   return print_insn (pc, info);
12354 }
12355
12356 int
12357 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12358 {
12359   intel_syntax = 1;
12360
12361   return print_insn (pc, info);
12362 }
12363
12364 int
12365 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12366 {
12367   intel_syntax = -1;
12368
12369   return print_insn (pc, info);
12370 }
12371
12372 void
12373 print_i386_disassembler_options (FILE *stream)
12374 {
12375   fprintf (stream, _("\n\
12376 The following i386/x86-64 specific disassembler options are supported for use\n\
12377 with the -M switch (multiple options should be separated by commas):\n"));
12378
12379   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12380   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12381   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12382   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12383   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12384   fprintf (stream, _("  att-mnemonic\n"
12385                      "              Display instruction in AT&T mnemonic\n"));
12386   fprintf (stream, _("  intel-mnemonic\n"
12387                      "              Display instruction in Intel mnemonic\n"));
12388   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12389   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12390   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12391   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12392   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12393   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12394 }
12395
12396 /* Bad opcode.  */
12397 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12398
12399 /* Get a pointer to struct dis386 with a valid name.  */
12400
12401 static const struct dis386 *
12402 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12403 {
12404   int vindex, vex_table_index;
12405
12406   if (dp->name != NULL)
12407     return dp;
12408
12409   switch (dp->op[0].bytemode)
12410     {
12411     case USE_REG_TABLE:
12412       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12413       break;
12414
12415     case USE_MOD_TABLE:
12416       vindex = modrm.mod == 0x3 ? 1 : 0;
12417       dp = &mod_table[dp->op[1].bytemode][vindex];
12418       break;
12419
12420     case USE_RM_TABLE:
12421       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12422       break;
12423
12424     case USE_PREFIX_TABLE:
12425       if (need_vex)
12426         {
12427           /* The prefix in VEX is implicit.  */
12428           switch (vex.prefix)
12429             {
12430             case 0:
12431               vindex = 0;
12432               break;
12433             case REPE_PREFIX_OPCODE:
12434               vindex = 1;
12435               break;
12436             case DATA_PREFIX_OPCODE:
12437               vindex = 2;
12438               break;
12439             case REPNE_PREFIX_OPCODE:
12440               vindex = 3;
12441               break;
12442             default:
12443               abort ();
12444               break;
12445             }
12446         }
12447       else
12448         {
12449           int last_prefix = -1;
12450           int prefix = 0;
12451           vindex = 0;
12452           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12453              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12454              last one wins.  */
12455           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12456             {
12457               if (last_repz_prefix > last_repnz_prefix)
12458                 {
12459                   vindex = 1;
12460                   prefix = PREFIX_REPZ;
12461                   last_prefix = last_repz_prefix;
12462                 }
12463               else
12464                 {
12465                   vindex = 3;
12466                   prefix = PREFIX_REPNZ;
12467                   last_prefix = last_repnz_prefix;
12468                 }
12469
12470               /* Check if prefix should be ignored.  */
12471               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12472                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12473                    & prefix) != 0)
12474                 vindex = 0;
12475             }
12476
12477           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12478             {
12479               vindex = 2;
12480               prefix = PREFIX_DATA;
12481               last_prefix = last_data_prefix;
12482             }
12483
12484           if (vindex != 0)
12485             {
12486               used_prefixes |= prefix;
12487               all_prefixes[last_prefix] = 0;
12488             }
12489         }
12490       dp = &prefix_table[dp->op[1].bytemode][vindex];
12491       break;
12492
12493     case USE_X86_64_TABLE:
12494       vindex = address_mode == mode_64bit ? 1 : 0;
12495       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12496       break;
12497
12498     case USE_3BYTE_TABLE:
12499       FETCH_DATA (info, codep + 2);
12500       vindex = *codep++;
12501       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12502       end_codep = codep;
12503       modrm.mod = (*codep >> 6) & 3;
12504       modrm.reg = (*codep >> 3) & 7;
12505       modrm.rm = *codep & 7;
12506       break;
12507
12508     case USE_VEX_LEN_TABLE:
12509       if (!need_vex)
12510         abort ();
12511
12512       switch (vex.length)
12513         {
12514         case 128:
12515           vindex = 0;
12516           break;
12517         case 256:
12518           vindex = 1;
12519           break;
12520         default:
12521           abort ();
12522           break;
12523         }
12524
12525       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12526       break;
12527
12528     case USE_XOP_8F_TABLE:
12529       FETCH_DATA (info, codep + 3);
12530       /* All bits in the REX prefix are ignored.  */
12531       rex_ignored = rex;
12532       rex = ~(*codep >> 5) & 0x7;
12533
12534       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12535       switch ((*codep & 0x1f))
12536         {
12537         default:
12538           dp = &bad_opcode;
12539           return dp;
12540         case 0x8:
12541           vex_table_index = XOP_08;
12542           break;
12543         case 0x9:
12544           vex_table_index = XOP_09;
12545           break;
12546         case 0xa:
12547           vex_table_index = XOP_0A;
12548           break;
12549         }
12550       codep++;
12551       vex.w = *codep & 0x80;
12552       if (vex.w && address_mode == mode_64bit)
12553         rex |= REX_W;
12554
12555       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12556       if (address_mode != mode_64bit
12557           && vex.register_specifier > 0x7)
12558         {
12559           dp = &bad_opcode;
12560           return dp;
12561         }
12562
12563       vex.length = (*codep & 0x4) ? 256 : 128;
12564       switch ((*codep & 0x3))
12565         {
12566         case 0:
12567           vex.prefix = 0;
12568           break;
12569         case 1:
12570           vex.prefix = DATA_PREFIX_OPCODE;
12571           break;
12572         case 2:
12573           vex.prefix = REPE_PREFIX_OPCODE;
12574           break;
12575         case 3:
12576           vex.prefix = REPNE_PREFIX_OPCODE;
12577           break;
12578         }
12579       need_vex = 1;
12580       need_vex_reg = 1;
12581       codep++;
12582       vindex = *codep++;
12583       dp = &xop_table[vex_table_index][vindex];
12584
12585       end_codep = codep;
12586       FETCH_DATA (info, codep + 1);
12587       modrm.mod = (*codep >> 6) & 3;
12588       modrm.reg = (*codep >> 3) & 7;
12589       modrm.rm = *codep & 7;
12590       break;
12591
12592     case USE_VEX_C4_TABLE:
12593       /* VEX prefix.  */
12594       FETCH_DATA (info, codep + 3);
12595       /* All bits in the REX prefix are ignored.  */
12596       rex_ignored = rex;
12597       rex = ~(*codep >> 5) & 0x7;
12598       switch ((*codep & 0x1f))
12599         {
12600         default:
12601           dp = &bad_opcode;
12602           return dp;
12603         case 0x1:
12604           vex_table_index = VEX_0F;
12605           break;
12606         case 0x2:
12607           vex_table_index = VEX_0F38;
12608           break;
12609         case 0x3:
12610           vex_table_index = VEX_0F3A;
12611           break;
12612         }
12613       codep++;
12614       vex.w = *codep & 0x80;
12615       if (vex.w && address_mode == mode_64bit)
12616         rex |= REX_W;
12617
12618       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12619       if (address_mode != mode_64bit
12620           && vex.register_specifier > 0x7)
12621         {
12622           dp = &bad_opcode;
12623           return dp;
12624         }
12625
12626       vex.length = (*codep & 0x4) ? 256 : 128;
12627       switch ((*codep & 0x3))
12628         {
12629         case 0:
12630           vex.prefix = 0;
12631           break;
12632         case 1:
12633           vex.prefix = DATA_PREFIX_OPCODE;
12634           break;
12635         case 2:
12636           vex.prefix = REPE_PREFIX_OPCODE;
12637           break;
12638         case 3:
12639           vex.prefix = REPNE_PREFIX_OPCODE;
12640           break;
12641         }
12642       need_vex = 1;
12643       need_vex_reg = 1;
12644       codep++;
12645       vindex = *codep++;
12646       dp = &vex_table[vex_table_index][vindex];
12647       end_codep = codep;
12648       /* There is no MODRM byte for VEX [82|77].  */
12649       if (vindex != 0x77 && vindex != 0x82)
12650         {
12651           FETCH_DATA (info, codep + 1);
12652           modrm.mod = (*codep >> 6) & 3;
12653           modrm.reg = (*codep >> 3) & 7;
12654           modrm.rm = *codep & 7;
12655         }
12656       break;
12657
12658     case USE_VEX_C5_TABLE:
12659       /* VEX prefix.  */
12660       FETCH_DATA (info, codep + 2);
12661       /* All bits in the REX prefix are ignored.  */
12662       rex_ignored = rex;
12663       rex = (*codep & 0x80) ? 0 : REX_R;
12664
12665       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12666       if (address_mode != mode_64bit
12667           && vex.register_specifier > 0x7)
12668         {
12669           dp = &bad_opcode;
12670           return dp;
12671         }
12672
12673       vex.w = 0;
12674
12675       vex.length = (*codep & 0x4) ? 256 : 128;
12676       switch ((*codep & 0x3))
12677         {
12678         case 0:
12679           vex.prefix = 0;
12680           break;
12681         case 1:
12682           vex.prefix = DATA_PREFIX_OPCODE;
12683           break;
12684         case 2:
12685           vex.prefix = REPE_PREFIX_OPCODE;
12686           break;
12687         case 3:
12688           vex.prefix = REPNE_PREFIX_OPCODE;
12689           break;
12690         }
12691       need_vex = 1;
12692       need_vex_reg = 1;
12693       codep++;
12694       vindex = *codep++;
12695       dp = &vex_table[dp->op[1].bytemode][vindex];
12696       end_codep = codep;
12697       /* There is no MODRM byte for VEX [82|77].  */
12698       if (vindex != 0x77 && vindex != 0x82)
12699         {
12700           FETCH_DATA (info, codep + 1);
12701           modrm.mod = (*codep >> 6) & 3;
12702           modrm.reg = (*codep >> 3) & 7;
12703           modrm.rm = *codep & 7;
12704         }
12705       break;
12706
12707     case USE_VEX_W_TABLE:
12708       if (!need_vex)
12709         abort ();
12710
12711       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12712       break;
12713
12714     case USE_EVEX_TABLE:
12715       two_source_ops = 0;
12716       /* EVEX prefix.  */
12717       vex.evex = 1;
12718       FETCH_DATA (info, codep + 4);
12719       /* All bits in the REX prefix are ignored.  */
12720       rex_ignored = rex;
12721       /* The first byte after 0x62.  */
12722       rex = ~(*codep >> 5) & 0x7;
12723       vex.r = *codep & 0x10;
12724       switch ((*codep & 0xf))
12725         {
12726         default:
12727           return &bad_opcode;
12728         case 0x1:
12729           vex_table_index = EVEX_0F;
12730           break;
12731         case 0x2:
12732           vex_table_index = EVEX_0F38;
12733           break;
12734         case 0x3:
12735           vex_table_index = EVEX_0F3A;
12736           break;
12737         }
12738
12739       /* The second byte after 0x62.  */
12740       codep++;
12741       vex.w = *codep & 0x80;
12742       if (vex.w && address_mode == mode_64bit)
12743         rex |= REX_W;
12744
12745       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12746       if (address_mode != mode_64bit)
12747         {
12748           /* In 16/32-bit mode silently ignore following bits.  */
12749           rex &= ~REX_B;
12750           vex.r = 1;
12751           vex.v = 1;
12752           vex.register_specifier &= 0x7;
12753         }
12754
12755       /* The U bit.  */
12756       if (!(*codep & 0x4))
12757         return &bad_opcode;
12758
12759       switch ((*codep & 0x3))
12760         {
12761         case 0:
12762           vex.prefix = 0;
12763           break;
12764         case 1:
12765           vex.prefix = DATA_PREFIX_OPCODE;
12766           break;
12767         case 2:
12768           vex.prefix = REPE_PREFIX_OPCODE;
12769           break;
12770         case 3:
12771           vex.prefix = REPNE_PREFIX_OPCODE;
12772           break;
12773         }
12774
12775       /* The third byte after 0x62.  */
12776       codep++;
12777
12778       /* Remember the static rounding bits.  */
12779       vex.ll = (*codep >> 5) & 3;
12780       vex.b = (*codep & 0x10) != 0;
12781
12782       vex.v = *codep & 0x8;
12783       vex.mask_register_specifier = *codep & 0x7;
12784       vex.zeroing = *codep & 0x80;
12785
12786       need_vex = 1;
12787       need_vex_reg = 1;
12788       codep++;
12789       vindex = *codep++;
12790       dp = &evex_table[vex_table_index][vindex];
12791       end_codep = codep;
12792       FETCH_DATA (info, codep + 1);
12793       modrm.mod = (*codep >> 6) & 3;
12794       modrm.reg = (*codep >> 3) & 7;
12795       modrm.rm = *codep & 7;
12796
12797       /* Set vector length.  */
12798       if (modrm.mod == 3 && vex.b)
12799         vex.length = 512;
12800       else
12801         {
12802           switch (vex.ll)
12803             {
12804             case 0x0:
12805               vex.length = 128;
12806               break;
12807             case 0x1:
12808               vex.length = 256;
12809               break;
12810             case 0x2:
12811               vex.length = 512;
12812               break;
12813             default:
12814               return &bad_opcode;
12815             }
12816         }
12817       break;
12818
12819     case 0:
12820       dp = &bad_opcode;
12821       break;
12822
12823     default:
12824       abort ();
12825     }
12826
12827   if (dp->name != NULL)
12828     return dp;
12829   else
12830     return get_valid_dis386 (dp, info);
12831 }
12832
12833 static void
12834 get_sib (disassemble_info *info, int sizeflag)
12835 {
12836   /* If modrm.mod == 3, operand must be register.  */
12837   if (need_modrm
12838       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12839       && modrm.mod != 3
12840       && modrm.rm == 4)
12841     {
12842       FETCH_DATA (info, codep + 2);
12843       sib.index = (codep [1] >> 3) & 7;
12844       sib.scale = (codep [1] >> 6) & 3;
12845       sib.base = codep [1] & 7;
12846     }
12847 }
12848
12849 static int
12850 print_insn (bfd_vma pc, disassemble_info *info)
12851 {
12852   const struct dis386 *dp;
12853   int i;
12854   char *op_txt[MAX_OPERANDS];
12855   int needcomma;
12856   int sizeflag, orig_sizeflag;
12857   const char *p;
12858   struct dis_private priv;
12859   int prefix_length;
12860
12861   priv.orig_sizeflag = AFLAG | DFLAG;
12862   if ((info->mach & bfd_mach_i386_i386) != 0)
12863     address_mode = mode_32bit;
12864   else if (info->mach == bfd_mach_i386_i8086)
12865     {
12866       address_mode = mode_16bit;
12867       priv.orig_sizeflag = 0;
12868     }
12869   else
12870     address_mode = mode_64bit;
12871
12872   if (intel_syntax == (char) -1)
12873     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12874
12875   for (p = info->disassembler_options; p != NULL; )
12876     {
12877       if (CONST_STRNEQ (p, "x86-64"))
12878         {
12879           address_mode = mode_64bit;
12880           priv.orig_sizeflag = AFLAG | DFLAG;
12881         }
12882       else if (CONST_STRNEQ (p, "i386"))
12883         {
12884           address_mode = mode_32bit;
12885           priv.orig_sizeflag = AFLAG | DFLAG;
12886         }
12887       else if (CONST_STRNEQ (p, "i8086"))
12888         {
12889           address_mode = mode_16bit;
12890           priv.orig_sizeflag = 0;
12891         }
12892       else if (CONST_STRNEQ (p, "intel"))
12893         {
12894           intel_syntax = 1;
12895           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12896             intel_mnemonic = 1;
12897         }
12898       else if (CONST_STRNEQ (p, "att"))
12899         {
12900           intel_syntax = 0;
12901           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12902             intel_mnemonic = 0;
12903         }
12904       else if (CONST_STRNEQ (p, "addr"))
12905         {
12906           if (address_mode == mode_64bit)
12907             {
12908               if (p[4] == '3' && p[5] == '2')
12909                 priv.orig_sizeflag &= ~AFLAG;
12910               else if (p[4] == '6' && p[5] == '4')
12911                 priv.orig_sizeflag |= AFLAG;
12912             }
12913           else
12914             {
12915               if (p[4] == '1' && p[5] == '6')
12916                 priv.orig_sizeflag &= ~AFLAG;
12917               else if (p[4] == '3' && p[5] == '2')
12918                 priv.orig_sizeflag |= AFLAG;
12919             }
12920         }
12921       else if (CONST_STRNEQ (p, "data"))
12922         {
12923           if (p[4] == '1' && p[5] == '6')
12924             priv.orig_sizeflag &= ~DFLAG;
12925           else if (p[4] == '3' && p[5] == '2')
12926             priv.orig_sizeflag |= DFLAG;
12927         }
12928       else if (CONST_STRNEQ (p, "suffix"))
12929         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12930
12931       p = strchr (p, ',');
12932       if (p != NULL)
12933         p++;
12934     }
12935
12936   if (intel_syntax)
12937     {
12938       names64 = intel_names64;
12939       names32 = intel_names32;
12940       names16 = intel_names16;
12941       names8 = intel_names8;
12942       names8rex = intel_names8rex;
12943       names_seg = intel_names_seg;
12944       names_mm = intel_names_mm;
12945       names_bnd = intel_names_bnd;
12946       names_xmm = intel_names_xmm;
12947       names_ymm = intel_names_ymm;
12948       names_zmm = intel_names_zmm;
12949       index64 = intel_index64;
12950       index32 = intel_index32;
12951       names_mask = intel_names_mask;
12952       index16 = intel_index16;
12953       open_char = '[';
12954       close_char = ']';
12955       separator_char = '+';
12956       scale_char = '*';
12957     }
12958   else
12959     {
12960       names64 = att_names64;
12961       names32 = att_names32;
12962       names16 = att_names16;
12963       names8 = att_names8;
12964       names8rex = att_names8rex;
12965       names_seg = att_names_seg;
12966       names_mm = att_names_mm;
12967       names_bnd = att_names_bnd;
12968       names_xmm = att_names_xmm;
12969       names_ymm = att_names_ymm;
12970       names_zmm = att_names_zmm;
12971       index64 = att_index64;
12972       index32 = att_index32;
12973       names_mask = att_names_mask;
12974       index16 = att_index16;
12975       open_char = '(';
12976       close_char =  ')';
12977       separator_char = ',';
12978       scale_char = ',';
12979     }
12980
12981   /* The output looks better if we put 7 bytes on a line, since that
12982      puts most long word instructions on a single line.  Use 8 bytes
12983      for Intel L1OM.  */
12984   if ((info->mach & bfd_mach_l1om) != 0)
12985     info->bytes_per_line = 8;
12986   else
12987     info->bytes_per_line = 7;
12988
12989   info->private_data = &priv;
12990   priv.max_fetched = priv.the_buffer;
12991   priv.insn_start = pc;
12992
12993   obuf[0] = 0;
12994   for (i = 0; i < MAX_OPERANDS; ++i)
12995     {
12996       op_out[i][0] = 0;
12997       op_index[i] = -1;
12998     }
12999
13000   the_info = info;
13001   start_pc = pc;
13002   start_codep = priv.the_buffer;
13003   codep = priv.the_buffer;
13004
13005   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13006     {
13007       const char *name;
13008
13009       /* Getting here means we tried for data but didn't get it.  That
13010          means we have an incomplete instruction of some sort.  Just
13011          print the first byte as a prefix or a .byte pseudo-op.  */
13012       if (codep > priv.the_buffer)
13013         {
13014           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13015           if (name != NULL)
13016             (*info->fprintf_func) (info->stream, "%s", name);
13017           else
13018             {
13019               /* Just print the first byte as a .byte instruction.  */
13020               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13021                                      (unsigned int) priv.the_buffer[0]);
13022             }
13023
13024           return 1;
13025         }
13026
13027       return -1;
13028     }
13029
13030   obufp = obuf;
13031   sizeflag = priv.orig_sizeflag;
13032
13033   if (!ckprefix () || rex_used)
13034     {
13035       /* Too many prefixes or unused REX prefixes.  */
13036       for (i = 0;
13037            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13038            i++)
13039         (*info->fprintf_func) (info->stream, "%s%s",
13040                                i == 0 ? "" : " ",
13041                                prefix_name (all_prefixes[i], sizeflag));
13042       return i;
13043     }
13044
13045   insn_codep = codep;
13046
13047   FETCH_DATA (info, codep + 1);
13048   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13049
13050   if (((prefixes & PREFIX_FWAIT)
13051        && ((*codep < 0xd8) || (*codep > 0xdf))))
13052     {
13053       /* Handle prefixes before fwait.  */
13054       for (i = 0; i < fwait_prefix && all_prefixes[i];
13055            i++)
13056         (*info->fprintf_func) (info->stream, "%s ",
13057                                prefix_name (all_prefixes[i], sizeflag));
13058       (*info->fprintf_func) (info->stream, "fwait");
13059       return i + 1;
13060     }
13061
13062   if (*codep == 0x0f)
13063     {
13064       unsigned char threebyte;
13065       FETCH_DATA (info, codep + 2);
13066       threebyte = *++codep;
13067       dp = &dis386_twobyte[threebyte];
13068       need_modrm = twobyte_has_modrm[*codep];
13069       codep++;
13070     }
13071   else
13072     {
13073       dp = &dis386[*codep];
13074       need_modrm = onebyte_has_modrm[*codep];
13075       codep++;
13076     }
13077
13078   /* Save sizeflag for printing the extra prefixes later before updating
13079      it for mnemonic and operand processing.  The prefix names depend
13080      only on the address mode.  */
13081   orig_sizeflag = sizeflag;
13082   if (prefixes & PREFIX_ADDR)
13083     sizeflag ^= AFLAG;
13084   if ((prefixes & PREFIX_DATA))
13085     sizeflag ^= DFLAG;
13086
13087   end_codep = codep;
13088   if (need_modrm)
13089     {
13090       FETCH_DATA (info, codep + 1);
13091       modrm.mod = (*codep >> 6) & 3;
13092       modrm.reg = (*codep >> 3) & 7;
13093       modrm.rm = *codep & 7;
13094     }
13095
13096   need_vex = 0;
13097   need_vex_reg = 0;
13098   vex_w_done = 0;
13099   vex.evex = 0;
13100
13101   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13102     {
13103       get_sib (info, sizeflag);
13104       dofloat (sizeflag);
13105     }
13106   else
13107     {
13108       dp = get_valid_dis386 (dp, info);
13109       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13110         {
13111           get_sib (info, sizeflag);
13112           for (i = 0; i < MAX_OPERANDS; ++i)
13113             {
13114               obufp = op_out[i];
13115               op_ad = MAX_OPERANDS - 1 - i;
13116               if (dp->op[i].rtn)
13117                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13118               /* For EVEX instruction after the last operand masking
13119                  should be printed.  */
13120               if (i == 0 && vex.evex)
13121                 {
13122                   /* Don't print {%k0}.  */
13123                   if (vex.mask_register_specifier)
13124                     {
13125                       oappend ("{");
13126                       oappend (names_mask[vex.mask_register_specifier]);
13127                       oappend ("}");
13128                     }
13129                   if (vex.zeroing)
13130                     oappend ("{z}");
13131                 }
13132             }
13133         }
13134     }
13135
13136   /* Check if the REX prefix is used.  */
13137   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13138     all_prefixes[last_rex_prefix] = 0;
13139
13140   /* Check if the SEG prefix is used.  */
13141   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13142                    | PREFIX_FS | PREFIX_GS)) != 0
13143       && (used_prefixes & active_seg_prefix) != 0)
13144     all_prefixes[last_seg_prefix] = 0;
13145
13146   /* Check if the ADDR prefix is used.  */
13147   if ((prefixes & PREFIX_ADDR) != 0
13148       && (used_prefixes & PREFIX_ADDR) != 0)
13149     all_prefixes[last_addr_prefix] = 0;
13150
13151   /* Check if the DATA prefix is used.  */
13152   if ((prefixes & PREFIX_DATA) != 0
13153       && (used_prefixes & PREFIX_DATA) != 0)
13154     all_prefixes[last_data_prefix] = 0;
13155
13156   /* Print the extra prefixes.  */
13157   prefix_length = 0;
13158   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13159     if (all_prefixes[i])
13160       {
13161         const char *name;
13162         name = prefix_name (all_prefixes[i], orig_sizeflag);
13163         if (name == NULL)
13164           abort ();
13165         prefix_length += strlen (name) + 1;
13166         (*info->fprintf_func) (info->stream, "%s ", name);
13167       }
13168
13169   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13170      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13171      used by putop and MMX/SSE operand and may be overriden by the
13172      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13173      separately.  */
13174   if (dp->prefix_requirement == PREFIX_OPCODE
13175       && dp != &bad_opcode
13176       && (((prefixes
13177             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13178            && (used_prefixes
13179                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13180           || ((((prefixes
13181                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13182                 == PREFIX_DATA)
13183                && (used_prefixes & PREFIX_DATA) == 0))))
13184     {
13185       (*info->fprintf_func) (info->stream, "(bad)");
13186       return end_codep - priv.the_buffer;
13187     }
13188
13189   /* Check maximum code length.  */
13190   if ((codep - start_codep) > MAX_CODE_LENGTH)
13191     {
13192       (*info->fprintf_func) (info->stream, "(bad)");
13193       return MAX_CODE_LENGTH;
13194     }
13195
13196   obufp = mnemonicendp;
13197   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13198     oappend (" ");
13199   oappend (" ");
13200   (*info->fprintf_func) (info->stream, "%s", obuf);
13201
13202   /* The enter and bound instructions are printed with operands in the same
13203      order as the intel book; everything else is printed in reverse order.  */
13204   if (intel_syntax || two_source_ops)
13205     {
13206       bfd_vma riprel;
13207
13208       for (i = 0; i < MAX_OPERANDS; ++i)
13209         op_txt[i] = op_out[i];
13210
13211       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13212         {
13213           op_ad = op_index[i];
13214           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13215           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13216           riprel = op_riprel[i];
13217           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13218           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13219         }
13220     }
13221   else
13222     {
13223       for (i = 0; i < MAX_OPERANDS; ++i)
13224         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13225     }
13226
13227   needcomma = 0;
13228   for (i = 0; i < MAX_OPERANDS; ++i)
13229     if (*op_txt[i])
13230       {
13231         if (needcomma)
13232           (*info->fprintf_func) (info->stream, ",");
13233         if (op_index[i] != -1 && !op_riprel[i])
13234           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13235         else
13236           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13237         needcomma = 1;
13238       }
13239
13240   for (i = 0; i < MAX_OPERANDS; i++)
13241     if (op_index[i] != -1 && op_riprel[i])
13242       {
13243         (*info->fprintf_func) (info->stream, "        # ");
13244         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13245                                                 + op_address[op_index[i]]), info);
13246         break;
13247       }
13248   return codep - priv.the_buffer;
13249 }
13250
13251 static const char *float_mem[] = {
13252   /* d8 */
13253   "fadd{s|}",
13254   "fmul{s|}",
13255   "fcom{s|}",
13256   "fcomp{s|}",
13257   "fsub{s|}",
13258   "fsubr{s|}",
13259   "fdiv{s|}",
13260   "fdivr{s|}",
13261   /* d9 */
13262   "fld{s|}",
13263   "(bad)",
13264   "fst{s|}",
13265   "fstp{s|}",
13266   "fldenvIC",
13267   "fldcw",
13268   "fNstenvIC",
13269   "fNstcw",
13270   /* da */
13271   "fiadd{l|}",
13272   "fimul{l|}",
13273   "ficom{l|}",
13274   "ficomp{l|}",
13275   "fisub{l|}",
13276   "fisubr{l|}",
13277   "fidiv{l|}",
13278   "fidivr{l|}",
13279   /* db */
13280   "fild{l|}",
13281   "fisttp{l|}",
13282   "fist{l|}",
13283   "fistp{l|}",
13284   "(bad)",
13285   "fld{t||t|}",
13286   "(bad)",
13287   "fstp{t||t|}",
13288   /* dc */
13289   "fadd{l|}",
13290   "fmul{l|}",
13291   "fcom{l|}",
13292   "fcomp{l|}",
13293   "fsub{l|}",
13294   "fsubr{l|}",
13295   "fdiv{l|}",
13296   "fdivr{l|}",
13297   /* dd */
13298   "fld{l|}",
13299   "fisttp{ll|}",
13300   "fst{l||}",
13301   "fstp{l|}",
13302   "frstorIC",
13303   "(bad)",
13304   "fNsaveIC",
13305   "fNstsw",
13306   /* de */
13307   "fiadd",
13308   "fimul",
13309   "ficom",
13310   "ficomp",
13311   "fisub",
13312   "fisubr",
13313   "fidiv",
13314   "fidivr",
13315   /* df */
13316   "fild",
13317   "fisttp",
13318   "fist",
13319   "fistp",
13320   "fbld",
13321   "fild{ll|}",
13322   "fbstp",
13323   "fistp{ll|}",
13324 };
13325
13326 static const unsigned char float_mem_mode[] = {
13327   /* d8 */
13328   d_mode,
13329   d_mode,
13330   d_mode,
13331   d_mode,
13332   d_mode,
13333   d_mode,
13334   d_mode,
13335   d_mode,
13336   /* d9 */
13337   d_mode,
13338   0,
13339   d_mode,
13340   d_mode,
13341   0,
13342   w_mode,
13343   0,
13344   w_mode,
13345   /* da */
13346   d_mode,
13347   d_mode,
13348   d_mode,
13349   d_mode,
13350   d_mode,
13351   d_mode,
13352   d_mode,
13353   d_mode,
13354   /* db */
13355   d_mode,
13356   d_mode,
13357   d_mode,
13358   d_mode,
13359   0,
13360   t_mode,
13361   0,
13362   t_mode,
13363   /* dc */
13364   q_mode,
13365   q_mode,
13366   q_mode,
13367   q_mode,
13368   q_mode,
13369   q_mode,
13370   q_mode,
13371   q_mode,
13372   /* dd */
13373   q_mode,
13374   q_mode,
13375   q_mode,
13376   q_mode,
13377   0,
13378   0,
13379   0,
13380   w_mode,
13381   /* de */
13382   w_mode,
13383   w_mode,
13384   w_mode,
13385   w_mode,
13386   w_mode,
13387   w_mode,
13388   w_mode,
13389   w_mode,
13390   /* df */
13391   w_mode,
13392   w_mode,
13393   w_mode,
13394   w_mode,
13395   t_mode,
13396   q_mode,
13397   t_mode,
13398   q_mode
13399 };
13400
13401 #define ST { OP_ST, 0 }
13402 #define STi { OP_STi, 0 }
13403
13404 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13405 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13406 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13407 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13408 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13409 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13410 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13411 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13412 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13413
13414 static const struct dis386 float_reg[][8] = {
13415   /* d8 */
13416   {
13417     { "fadd",   { ST, STi }, 0 },
13418     { "fmul",   { ST, STi }, 0 },
13419     { "fcom",   { STi }, 0 },
13420     { "fcomp",  { STi }, 0 },
13421     { "fsub",   { ST, STi }, 0 },
13422     { "fsubr",  { ST, STi }, 0 },
13423     { "fdiv",   { ST, STi }, 0 },
13424     { "fdivr",  { ST, STi }, 0 },
13425   },
13426   /* d9 */
13427   {
13428     { "fld",    { STi }, 0 },
13429     { "fxch",   { STi }, 0 },
13430     { FGRPd9_2 },
13431     { Bad_Opcode },
13432     { FGRPd9_4 },
13433     { FGRPd9_5 },
13434     { FGRPd9_6 },
13435     { FGRPd9_7 },
13436   },
13437   /* da */
13438   {
13439     { "fcmovb", { ST, STi }, 0 },
13440     { "fcmove", { ST, STi }, 0 },
13441     { "fcmovbe",{ ST, STi }, 0 },
13442     { "fcmovu", { ST, STi }, 0 },
13443     { Bad_Opcode },
13444     { FGRPda_5 },
13445     { Bad_Opcode },
13446     { Bad_Opcode },
13447   },
13448   /* db */
13449   {
13450     { "fcmovnb",{ ST, STi }, 0 },
13451     { "fcmovne",{ ST, STi }, 0 },
13452     { "fcmovnbe",{ ST, STi }, 0 },
13453     { "fcmovnu",{ ST, STi }, 0 },
13454     { FGRPdb_4 },
13455     { "fucomi", { ST, STi }, 0 },
13456     { "fcomi",  { ST, STi }, 0 },
13457     { Bad_Opcode },
13458   },
13459   /* dc */
13460   {
13461     { "fadd",   { STi, ST }, 0 },
13462     { "fmul",   { STi, ST }, 0 },
13463     { Bad_Opcode },
13464     { Bad_Opcode },
13465     { "fsub!M", { STi, ST }, 0 },
13466     { "fsubM",  { STi, ST }, 0 },
13467     { "fdiv!M", { STi, ST }, 0 },
13468     { "fdivM",  { STi, ST }, 0 },
13469   },
13470   /* dd */
13471   {
13472     { "ffree",  { STi }, 0 },
13473     { Bad_Opcode },
13474     { "fst",    { STi }, 0 },
13475     { "fstp",   { STi }, 0 },
13476     { "fucom",  { STi }, 0 },
13477     { "fucomp", { STi }, 0 },
13478     { Bad_Opcode },
13479     { Bad_Opcode },
13480   },
13481   /* de */
13482   {
13483     { "faddp",  { STi, ST }, 0 },
13484     { "fmulp",  { STi, ST }, 0 },
13485     { Bad_Opcode },
13486     { FGRPde_3 },
13487     { "fsub!Mp", { STi, ST }, 0 },
13488     { "fsubMp", { STi, ST }, 0 },
13489     { "fdiv!Mp", { STi, ST }, 0 },
13490     { "fdivMp", { STi, ST }, 0 },
13491   },
13492   /* df */
13493   {
13494     { "ffreep", { STi }, 0 },
13495     { Bad_Opcode },
13496     { Bad_Opcode },
13497     { Bad_Opcode },
13498     { FGRPdf_4 },
13499     { "fucomip", { ST, STi }, 0 },
13500     { "fcomip", { ST, STi }, 0 },
13501     { Bad_Opcode },
13502   },
13503 };
13504
13505 static char *fgrps[][8] = {
13506   /* d9_2  0 */
13507   {
13508     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13509   },
13510
13511   /* d9_4  1 */
13512   {
13513     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13514   },
13515
13516   /* d9_5  2 */
13517   {
13518     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13519   },
13520
13521   /* d9_6  3 */
13522   {
13523     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13524   },
13525
13526   /* d9_7  4 */
13527   {
13528     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13529   },
13530
13531   /* da_5  5 */
13532   {
13533     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13534   },
13535
13536   /* db_4  6 */
13537   {
13538     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13539     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13540   },
13541
13542   /* de_3  7 */
13543   {
13544     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13545   },
13546
13547   /* df_4  8 */
13548   {
13549     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13550   },
13551 };
13552
13553 static void
13554 swap_operand (void)
13555 {
13556   mnemonicendp[0] = '.';
13557   mnemonicendp[1] = 's';
13558   mnemonicendp += 2;
13559 }
13560
13561 static void
13562 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13563                int sizeflag ATTRIBUTE_UNUSED)
13564 {
13565   /* Skip mod/rm byte.  */
13566   MODRM_CHECK;
13567   codep++;
13568 }
13569
13570 static void
13571 dofloat (int sizeflag)
13572 {
13573   const struct dis386 *dp;
13574   unsigned char floatop;
13575
13576   floatop = codep[-1];
13577
13578   if (modrm.mod != 3)
13579     {
13580       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13581
13582       putop (float_mem[fp_indx], sizeflag);
13583       obufp = op_out[0];
13584       op_ad = 2;
13585       OP_E (float_mem_mode[fp_indx], sizeflag);
13586       return;
13587     }
13588   /* Skip mod/rm byte.  */
13589   MODRM_CHECK;
13590   codep++;
13591
13592   dp = &float_reg[floatop - 0xd8][modrm.reg];
13593   if (dp->name == NULL)
13594     {
13595       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13596
13597       /* Instruction fnstsw is only one with strange arg.  */
13598       if (floatop == 0xdf && codep[-1] == 0xe0)
13599         strcpy (op_out[0], names16[0]);
13600     }
13601   else
13602     {
13603       putop (dp->name, sizeflag);
13604
13605       obufp = op_out[0];
13606       op_ad = 2;
13607       if (dp->op[0].rtn)
13608         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13609
13610       obufp = op_out[1];
13611       op_ad = 1;
13612       if (dp->op[1].rtn)
13613         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13614     }
13615 }
13616
13617 /* Like oappend (below), but S is a string starting with '%'.
13618    In Intel syntax, the '%' is elided.  */
13619 static void
13620 oappend_maybe_intel (const char *s)
13621 {
13622   oappend (s + intel_syntax);
13623 }
13624
13625 static void
13626 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13627 {
13628   oappend_maybe_intel ("%st");
13629 }
13630
13631 static void
13632 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13633 {
13634   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13635   oappend_maybe_intel (scratchbuf);
13636 }
13637
13638 /* Capital letters in template are macros.  */
13639 static int
13640 putop (const char *in_template, int sizeflag)
13641 {
13642   const char *p;
13643   int alt = 0;
13644   int cond = 1;
13645   unsigned int l = 0, len = 1;
13646   char last[4];
13647
13648 #define SAVE_LAST(c)                    \
13649   if (l < len && l < sizeof (last))     \
13650     last[l++] = c;                      \
13651   else                                  \
13652     abort ();
13653
13654   for (p = in_template; *p; p++)
13655     {
13656       switch (*p)
13657         {
13658         default:
13659           *obufp++ = *p;
13660           break;
13661         case '%':
13662           len++;
13663           break;
13664         case '!':
13665           cond = 0;
13666           break;
13667         case '{':
13668           alt = 0;
13669           if (intel_syntax)
13670             {
13671               while (*++p != '|')
13672                 if (*p == '}' || *p == '\0')
13673                   abort ();
13674             }
13675           /* Fall through.  */
13676         case 'I':
13677           alt = 1;
13678           continue;
13679         case '|':
13680           while (*++p != '}')
13681             {
13682               if (*p == '\0')
13683                 abort ();
13684             }
13685           break;
13686         case '}':
13687           break;
13688         case 'A':
13689           if (intel_syntax)
13690             break;
13691           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13692             *obufp++ = 'b';
13693           break;
13694         case 'B':
13695           if (l == 0 && len == 1)
13696             {
13697 case_B:
13698               if (intel_syntax)
13699                 break;
13700               if (sizeflag & SUFFIX_ALWAYS)
13701                 *obufp++ = 'b';
13702             }
13703           else
13704             {
13705               if (l != 1
13706                   || len != 2
13707                   || last[0] != 'L')
13708                 {
13709                   SAVE_LAST (*p);
13710                   break;
13711                 }
13712
13713               if (address_mode == mode_64bit
13714                   && !(prefixes & PREFIX_ADDR))
13715                 {
13716                   *obufp++ = 'a';
13717                   *obufp++ = 'b';
13718                   *obufp++ = 's';
13719                 }
13720
13721               goto case_B;
13722             }
13723           break;
13724         case 'C':
13725           if (intel_syntax && !alt)
13726             break;
13727           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13728             {
13729               if (sizeflag & DFLAG)
13730                 *obufp++ = intel_syntax ? 'd' : 'l';
13731               else
13732                 *obufp++ = intel_syntax ? 'w' : 's';
13733               used_prefixes |= (prefixes & PREFIX_DATA);
13734             }
13735           break;
13736         case 'D':
13737           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13738             break;
13739           USED_REX (REX_W);
13740           if (modrm.mod == 3)
13741             {
13742               if (rex & REX_W)
13743                 *obufp++ = 'q';
13744               else
13745                 {
13746                   if (sizeflag & DFLAG)
13747                     *obufp++ = intel_syntax ? 'd' : 'l';
13748                   else
13749                     *obufp++ = 'w';
13750                   used_prefixes |= (prefixes & PREFIX_DATA);
13751                 }
13752             }
13753           else
13754             *obufp++ = 'w';
13755           break;
13756         case 'E':               /* For jcxz/jecxz */
13757           if (address_mode == mode_64bit)
13758             {
13759               if (sizeflag & AFLAG)
13760                 *obufp++ = 'r';
13761               else
13762                 *obufp++ = 'e';
13763             }
13764           else
13765             if (sizeflag & AFLAG)
13766               *obufp++ = 'e';
13767           used_prefixes |= (prefixes & PREFIX_ADDR);
13768           break;
13769         case 'F':
13770           if (intel_syntax)
13771             break;
13772           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13773             {
13774               if (sizeflag & AFLAG)
13775                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13776               else
13777                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13778               used_prefixes |= (prefixes & PREFIX_ADDR);
13779             }
13780           break;
13781         case 'G':
13782           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13783             break;
13784           if ((rex & REX_W) || (sizeflag & DFLAG))
13785             *obufp++ = 'l';
13786           else
13787             *obufp++ = 'w';
13788           if (!(rex & REX_W))
13789             used_prefixes |= (prefixes & PREFIX_DATA);
13790           break;
13791         case 'H':
13792           if (intel_syntax)
13793             break;
13794           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13795               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13796             {
13797               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13798               *obufp++ = ',';
13799               *obufp++ = 'p';
13800               if (prefixes & PREFIX_DS)
13801                 *obufp++ = 't';
13802               else
13803                 *obufp++ = 'n';
13804             }
13805           break;
13806         case 'J':
13807           if (intel_syntax)
13808             break;
13809           *obufp++ = 'l';
13810           break;
13811         case 'K':
13812           USED_REX (REX_W);
13813           if (rex & REX_W)
13814             *obufp++ = 'q';
13815           else
13816             *obufp++ = 'd';
13817           break;
13818         case 'Z':
13819           if (l != 0 || len != 1)
13820             {
13821               if (l != 1 || len != 2 || last[0] != 'X')
13822                 {
13823                   SAVE_LAST (*p);
13824                   break;
13825                 }
13826               if (!need_vex || !vex.evex)
13827                 abort ();
13828               if (intel_syntax
13829                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13830                 break;
13831               switch (vex.length)
13832                 {
13833                 case 128:
13834                   *obufp++ = 'x';
13835                   break;
13836                 case 256:
13837                   *obufp++ = 'y';
13838                   break;
13839                 case 512:
13840                   *obufp++ = 'z';
13841                   break;
13842                 default:
13843                   abort ();
13844                 }
13845               break;
13846             }
13847           if (intel_syntax)
13848             break;
13849           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13850             {
13851               *obufp++ = 'q';
13852               break;
13853             }
13854           /* Fall through.  */
13855           goto case_L;
13856         case 'L':
13857           if (l != 0 || len != 1)
13858             {
13859               SAVE_LAST (*p);
13860               break;
13861             }
13862 case_L:
13863           if (intel_syntax)
13864             break;
13865           if (sizeflag & SUFFIX_ALWAYS)
13866             *obufp++ = 'l';
13867           break;
13868         case 'M':
13869           if (intel_mnemonic != cond)
13870             *obufp++ = 'r';
13871           break;
13872         case 'N':
13873           if ((prefixes & PREFIX_FWAIT) == 0)
13874             *obufp++ = 'n';
13875           else
13876             used_prefixes |= PREFIX_FWAIT;
13877           break;
13878         case 'O':
13879           USED_REX (REX_W);
13880           if (rex & REX_W)
13881             *obufp++ = 'o';
13882           else if (intel_syntax && (sizeflag & DFLAG))
13883             *obufp++ = 'q';
13884           else
13885             *obufp++ = 'd';
13886           if (!(rex & REX_W))
13887             used_prefixes |= (prefixes & PREFIX_DATA);
13888           break;
13889         case 'T':
13890           if (!intel_syntax
13891               && address_mode == mode_64bit
13892               && ((sizeflag & DFLAG) || (rex & REX_W)))
13893             {
13894               *obufp++ = 'q';
13895               break;
13896             }
13897           /* Fall through.  */
13898           goto case_P;
13899         case 'P':
13900           if (l == 0 && len == 1)
13901             {
13902 case_P:
13903               if (intel_syntax)
13904                 {
13905                   if ((rex & REX_W) == 0
13906                       && (prefixes & PREFIX_DATA))
13907                     {
13908                       if ((sizeflag & DFLAG) == 0)
13909                         *obufp++ = 'w';
13910                       used_prefixes |= (prefixes & PREFIX_DATA);
13911                     }
13912                   break;
13913                 }
13914               if ((prefixes & PREFIX_DATA)
13915                   || (rex & REX_W)
13916                   || (sizeflag & SUFFIX_ALWAYS))
13917                 {
13918                   USED_REX (REX_W);
13919                   if (rex & REX_W)
13920                     *obufp++ = 'q';
13921                   else
13922                     {
13923                       if (sizeflag & DFLAG)
13924                         *obufp++ = 'l';
13925                       else
13926                         *obufp++ = 'w';
13927                       used_prefixes |= (prefixes & PREFIX_DATA);
13928                     }
13929                 }
13930             }
13931           else
13932             {
13933               if (l != 1 || len != 2 || last[0] != 'L')
13934                 {
13935                   SAVE_LAST (*p);
13936                   break;
13937                 }
13938
13939               if ((prefixes & PREFIX_DATA)
13940                   || (rex & REX_W)
13941                   || (sizeflag & SUFFIX_ALWAYS))
13942                 {
13943                   USED_REX (REX_W);
13944                   if (rex & REX_W)
13945                     *obufp++ = 'q';
13946                   else
13947                     {
13948                       if (sizeflag & DFLAG)
13949                         *obufp++ = intel_syntax ? 'd' : 'l';
13950                       else
13951                         *obufp++ = 'w';
13952                       used_prefixes |= (prefixes & PREFIX_DATA);
13953                     }
13954                 }
13955             }
13956           break;
13957         case 'U':
13958           if (intel_syntax)
13959             break;
13960           if (address_mode == mode_64bit
13961               && ((sizeflag & DFLAG) || (rex & REX_W)))
13962             {
13963               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13964                 *obufp++ = 'q';
13965               break;
13966             }
13967           /* Fall through.  */
13968           goto case_Q;
13969         case 'Q':
13970           if (l == 0 && len == 1)
13971             {
13972 case_Q:
13973               if (intel_syntax && !alt)
13974                 break;
13975               USED_REX (REX_W);
13976               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13977                 {
13978                   if (rex & REX_W)
13979                     *obufp++ = 'q';
13980                   else
13981                     {
13982                       if (sizeflag & DFLAG)
13983                         *obufp++ = intel_syntax ? 'd' : 'l';
13984                       else
13985                         *obufp++ = 'w';
13986                       used_prefixes |= (prefixes & PREFIX_DATA);
13987                     }
13988                 }
13989             }
13990           else
13991             {
13992               if (l != 1 || len != 2 || last[0] != 'L')
13993                 {
13994                   SAVE_LAST (*p);
13995                   break;
13996                 }
13997               if (intel_syntax
13998                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13999                 break;
14000               if ((rex & REX_W))
14001                 {
14002                   USED_REX (REX_W);
14003                   *obufp++ = 'q';
14004                 }
14005               else
14006                 *obufp++ = 'l';
14007             }
14008           break;
14009         case 'R':
14010           USED_REX (REX_W);
14011           if (rex & REX_W)
14012             *obufp++ = 'q';
14013           else if (sizeflag & DFLAG)
14014             {
14015               if (intel_syntax)
14016                   *obufp++ = 'd';
14017               else
14018                   *obufp++ = 'l';
14019             }
14020           else
14021             *obufp++ = 'w';
14022           if (intel_syntax && !p[1]
14023               && ((rex & REX_W) || (sizeflag & DFLAG)))
14024             *obufp++ = 'e';
14025           if (!(rex & REX_W))
14026             used_prefixes |= (prefixes & PREFIX_DATA);
14027           break;
14028         case 'V':
14029           if (l == 0 && len == 1)
14030             {
14031               if (intel_syntax)
14032                 break;
14033               if (address_mode == mode_64bit
14034                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14035                 {
14036                   if (sizeflag & SUFFIX_ALWAYS)
14037                     *obufp++ = 'q';
14038                   break;
14039                 }
14040             }
14041           else
14042             {
14043               if (l != 1
14044                   || len != 2
14045                   || last[0] != 'L')
14046                 {
14047                   SAVE_LAST (*p);
14048                   break;
14049                 }
14050
14051               if (rex & REX_W)
14052                 {
14053                   *obufp++ = 'a';
14054                   *obufp++ = 'b';
14055                   *obufp++ = 's';
14056                 }
14057             }
14058           /* Fall through.  */
14059           goto case_S;
14060         case 'S':
14061           if (l == 0 && len == 1)
14062             {
14063 case_S:
14064               if (intel_syntax)
14065                 break;
14066               if (sizeflag & SUFFIX_ALWAYS)
14067                 {
14068                   if (rex & REX_W)
14069                     *obufp++ = 'q';
14070                   else
14071                     {
14072                       if (sizeflag & DFLAG)
14073                         *obufp++ = 'l';
14074                       else
14075                         *obufp++ = 'w';
14076                       used_prefixes |= (prefixes & PREFIX_DATA);
14077                     }
14078                 }
14079             }
14080           else
14081             {
14082               if (l != 1
14083                   || len != 2
14084                   || last[0] != 'L')
14085                 {
14086                   SAVE_LAST (*p);
14087                   break;
14088                 }
14089
14090               if (address_mode == mode_64bit
14091                   && !(prefixes & PREFIX_ADDR))
14092                 {
14093                   *obufp++ = 'a';
14094                   *obufp++ = 'b';
14095                   *obufp++ = 's';
14096                 }
14097
14098               goto case_S;
14099             }
14100           break;
14101         case 'X':
14102           if (l != 0 || len != 1)
14103             {
14104               SAVE_LAST (*p);
14105               break;
14106             }
14107           if (need_vex && vex.prefix)
14108             {
14109               if (vex.prefix == DATA_PREFIX_OPCODE)
14110                 *obufp++ = 'd';
14111               else
14112                 *obufp++ = 's';
14113             }
14114           else
14115             {
14116               if (prefixes & PREFIX_DATA)
14117                 *obufp++ = 'd';
14118               else
14119                 *obufp++ = 's';
14120               used_prefixes |= (prefixes & PREFIX_DATA);
14121             }
14122           break;
14123         case 'Y':
14124           if (l == 0 && len == 1)
14125             {
14126               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14127                 break;
14128               if (rex & REX_W)
14129                 {
14130                   USED_REX (REX_W);
14131                   *obufp++ = 'q';
14132                 }
14133               break;
14134             }
14135           else
14136             {
14137               if (l != 1 || len != 2 || last[0] != 'X')
14138                 {
14139                   SAVE_LAST (*p);
14140                   break;
14141                 }
14142               if (!need_vex)
14143                 abort ();
14144               if (intel_syntax
14145                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14146                 break;
14147               switch (vex.length)
14148                 {
14149                 case 128:
14150                   *obufp++ = 'x';
14151                   break;
14152                 case 256:
14153                   *obufp++ = 'y';
14154                   break;
14155                 case 512:
14156                   if (!vex.evex)
14157                 default:
14158                     abort ();
14159                 }
14160             }
14161           break;
14162         case 'W':
14163           if (l == 0 && len == 1)
14164             {
14165               /* operand size flag for cwtl, cbtw */
14166               USED_REX (REX_W);
14167               if (rex & REX_W)
14168                 {
14169                   if (intel_syntax)
14170                     *obufp++ = 'd';
14171                   else
14172                     *obufp++ = 'l';
14173                 }
14174               else if (sizeflag & DFLAG)
14175                 *obufp++ = 'w';
14176               else
14177                 *obufp++ = 'b';
14178               if (!(rex & REX_W))
14179                 used_prefixes |= (prefixes & PREFIX_DATA);
14180             }
14181           else
14182             {
14183               if (l != 1
14184                   || len != 2
14185                   || (last[0] != 'X'
14186                       && last[0] != 'L'))
14187                 {
14188                   SAVE_LAST (*p);
14189                   break;
14190                 }
14191               if (!need_vex)
14192                 abort ();
14193               if (last[0] == 'X')
14194                 *obufp++ = vex.w ? 'd': 's';
14195               else
14196                 *obufp++ = vex.w ? 'q': 'd';
14197             }
14198           break;
14199         case '^':
14200           if (intel_syntax)
14201             break;
14202           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14203             {
14204               if (sizeflag & DFLAG)
14205                 *obufp++ = 'l';
14206               else
14207                 *obufp++ = 'w';
14208               used_prefixes |= (prefixes & PREFIX_DATA);
14209             }
14210           break;
14211         }
14212       alt = 0;
14213     }
14214   *obufp = 0;
14215   mnemonicendp = obufp;
14216   return 0;
14217 }
14218
14219 static void
14220 oappend (const char *s)
14221 {
14222   obufp = stpcpy (obufp, s);
14223 }
14224
14225 static void
14226 append_seg (void)
14227 {
14228   /* Only print the active segment register.  */
14229   if (!active_seg_prefix)
14230     return;
14231
14232   used_prefixes |= active_seg_prefix;
14233   switch (active_seg_prefix)
14234     {
14235     case PREFIX_CS:
14236       oappend_maybe_intel ("%cs:");
14237       break;
14238     case PREFIX_DS:
14239       oappend_maybe_intel ("%ds:");
14240       break;
14241     case PREFIX_SS:
14242       oappend_maybe_intel ("%ss:");
14243       break;
14244     case PREFIX_ES:
14245       oappend_maybe_intel ("%es:");
14246       break;
14247     case PREFIX_FS:
14248       oappend_maybe_intel ("%fs:");
14249       break;
14250     case PREFIX_GS:
14251       oappend_maybe_intel ("%gs:");
14252       break;
14253     default:
14254       break;
14255     }
14256 }
14257
14258 static void
14259 OP_indirE (int bytemode, int sizeflag)
14260 {
14261   if (!intel_syntax)
14262     oappend ("*");
14263   OP_E (bytemode, sizeflag);
14264 }
14265
14266 static void
14267 print_operand_value (char *buf, int hex, bfd_vma disp)
14268 {
14269   if (address_mode == mode_64bit)
14270     {
14271       if (hex)
14272         {
14273           char tmp[30];
14274           int i;
14275           buf[0] = '0';
14276           buf[1] = 'x';
14277           sprintf_vma (tmp, disp);
14278           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14279           strcpy (buf + 2, tmp + i);
14280         }
14281       else
14282         {
14283           bfd_signed_vma v = disp;
14284           char tmp[30];
14285           int i;
14286           if (v < 0)
14287             {
14288               *(buf++) = '-';
14289               v = -disp;
14290               /* Check for possible overflow on 0x8000000000000000.  */
14291               if (v < 0)
14292                 {
14293                   strcpy (buf, "9223372036854775808");
14294                   return;
14295                 }
14296             }
14297           if (!v)
14298             {
14299               strcpy (buf, "0");
14300               return;
14301             }
14302
14303           i = 0;
14304           tmp[29] = 0;
14305           while (v)
14306             {
14307               tmp[28 - i] = (v % 10) + '0';
14308               v /= 10;
14309               i++;
14310             }
14311           strcpy (buf, tmp + 29 - i);
14312         }
14313     }
14314   else
14315     {
14316       if (hex)
14317         sprintf (buf, "0x%x", (unsigned int) disp);
14318       else
14319         sprintf (buf, "%d", (int) disp);
14320     }
14321 }
14322
14323 /* Put DISP in BUF as signed hex number.  */
14324
14325 static void
14326 print_displacement (char *buf, bfd_vma disp)
14327 {
14328   bfd_signed_vma val = disp;
14329   char tmp[30];
14330   int i, j = 0;
14331
14332   if (val < 0)
14333     {
14334       buf[j++] = '-';
14335       val = -disp;
14336
14337       /* Check for possible overflow.  */
14338       if (val < 0)
14339         {
14340           switch (address_mode)
14341             {
14342             case mode_64bit:
14343               strcpy (buf + j, "0x8000000000000000");
14344               break;
14345             case mode_32bit:
14346               strcpy (buf + j, "0x80000000");
14347               break;
14348             case mode_16bit:
14349               strcpy (buf + j, "0x8000");
14350               break;
14351             }
14352           return;
14353         }
14354     }
14355
14356   buf[j++] = '0';
14357   buf[j++] = 'x';
14358
14359   sprintf_vma (tmp, (bfd_vma) val);
14360   for (i = 0; tmp[i] == '0'; i++)
14361     continue;
14362   if (tmp[i] == '\0')
14363     i--;
14364   strcpy (buf + j, tmp + i);
14365 }
14366
14367 static void
14368 intel_operand_size (int bytemode, int sizeflag)
14369 {
14370   if (vex.evex
14371       && vex.b
14372       && (bytemode == x_mode
14373           || bytemode == evex_half_bcst_xmmq_mode))
14374     {
14375       if (vex.w)
14376         oappend ("QWORD PTR ");
14377       else
14378         oappend ("DWORD PTR ");
14379       return;
14380     }
14381   switch (bytemode)
14382     {
14383     case b_mode:
14384     case b_swap_mode:
14385     case dqb_mode:
14386     case db_mode:
14387       oappend ("BYTE PTR ");
14388       break;
14389     case w_mode:
14390     case dw_mode:
14391     case dqw_mode:
14392     case dqw_swap_mode:
14393       oappend ("WORD PTR ");
14394       break;
14395     case stack_v_mode:
14396       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14397         {
14398           oappend ("QWORD PTR ");
14399           break;
14400         }
14401       /* FALLTHRU */
14402     case v_mode:
14403     case v_swap_mode:
14404     case dq_mode:
14405       USED_REX (REX_W);
14406       if (rex & REX_W)
14407         oappend ("QWORD PTR ");
14408       else
14409         {
14410           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14411             oappend ("DWORD PTR ");
14412           else
14413             oappend ("WORD PTR ");
14414           used_prefixes |= (prefixes & PREFIX_DATA);
14415         }
14416       break;
14417     case z_mode:
14418       if ((rex & REX_W) || (sizeflag & DFLAG))
14419         *obufp++ = 'D';
14420       oappend ("WORD PTR ");
14421       if (!(rex & REX_W))
14422         used_prefixes |= (prefixes & PREFIX_DATA);
14423       break;
14424     case a_mode:
14425       if (sizeflag & DFLAG)
14426         oappend ("QWORD PTR ");
14427       else
14428         oappend ("DWORD PTR ");
14429       used_prefixes |= (prefixes & PREFIX_DATA);
14430       break;
14431     case d_mode:
14432     case d_scalar_mode:
14433     case d_scalar_swap_mode:
14434     case d_swap_mode:
14435     case dqd_mode:
14436       oappend ("DWORD PTR ");
14437       break;
14438     case q_mode:
14439     case q_scalar_mode:
14440     case q_scalar_swap_mode:
14441     case q_swap_mode:
14442       oappend ("QWORD PTR ");
14443       break;
14444     case m_mode:
14445       if (address_mode == mode_64bit)
14446         oappend ("QWORD PTR ");
14447       else
14448         oappend ("DWORD PTR ");
14449       break;
14450     case f_mode:
14451       if (sizeflag & DFLAG)
14452         oappend ("FWORD PTR ");
14453       else
14454         oappend ("DWORD PTR ");
14455       used_prefixes |= (prefixes & PREFIX_DATA);
14456       break;
14457     case t_mode:
14458       oappend ("TBYTE PTR ");
14459       break;
14460     case x_mode:
14461     case x_swap_mode:
14462     case evex_x_gscat_mode:
14463     case evex_x_nobcst_mode:
14464       if (need_vex)
14465         {
14466           switch (vex.length)
14467             {
14468             case 128:
14469               oappend ("XMMWORD PTR ");
14470               break;
14471             case 256:
14472               oappend ("YMMWORD PTR ");
14473               break;
14474             case 512:
14475               oappend ("ZMMWORD PTR ");
14476               break;
14477             default:
14478               abort ();
14479             }
14480         }
14481       else
14482         oappend ("XMMWORD PTR ");
14483       break;
14484     case xmm_mode:
14485       oappend ("XMMWORD PTR ");
14486       break;
14487     case ymm_mode:
14488       oappend ("YMMWORD PTR ");
14489       break;
14490     case xmmq_mode:
14491     case evex_half_bcst_xmmq_mode:
14492       if (!need_vex)
14493         abort ();
14494
14495       switch (vex.length)
14496         {
14497         case 128:
14498           oappend ("QWORD PTR ");
14499           break;
14500         case 256:
14501           oappend ("XMMWORD PTR ");
14502           break;
14503         case 512:
14504           oappend ("YMMWORD PTR ");
14505           break;
14506         default:
14507           abort ();
14508         }
14509       break;
14510     case xmm_mb_mode:
14511       if (!need_vex)
14512         abort ();
14513
14514       switch (vex.length)
14515         {
14516         case 128:
14517         case 256:
14518         case 512:
14519           oappend ("BYTE PTR ");
14520           break;
14521         default:
14522           abort ();
14523         }
14524       break;
14525     case xmm_mw_mode:
14526       if (!need_vex)
14527         abort ();
14528
14529       switch (vex.length)
14530         {
14531         case 128:
14532         case 256:
14533         case 512:
14534           oappend ("WORD PTR ");
14535           break;
14536         default:
14537           abort ();
14538         }
14539       break;
14540     case xmm_md_mode:
14541       if (!need_vex)
14542         abort ();
14543
14544       switch (vex.length)
14545         {
14546         case 128:
14547         case 256:
14548         case 512:
14549           oappend ("DWORD PTR ");
14550           break;
14551         default:
14552           abort ();
14553         }
14554       break;
14555     case xmm_mq_mode:
14556       if (!need_vex)
14557         abort ();
14558
14559       switch (vex.length)
14560         {
14561         case 128:
14562         case 256:
14563         case 512:
14564           oappend ("QWORD PTR ");
14565           break;
14566         default:
14567           abort ();
14568         }
14569       break;
14570     case xmmdw_mode:
14571       if (!need_vex)
14572         abort ();
14573
14574       switch (vex.length)
14575         {
14576         case 128:
14577           oappend ("WORD PTR ");
14578           break;
14579         case 256:
14580           oappend ("DWORD PTR ");
14581           break;
14582         case 512:
14583           oappend ("QWORD PTR ");
14584           break;
14585         default:
14586           abort ();
14587         }
14588       break;
14589     case xmmqd_mode:
14590       if (!need_vex)
14591         abort ();
14592
14593       switch (vex.length)
14594         {
14595         case 128:
14596           oappend ("DWORD PTR ");
14597           break;
14598         case 256:
14599           oappend ("QWORD PTR ");
14600           break;
14601         case 512:
14602           oappend ("XMMWORD PTR ");
14603           break;
14604         default:
14605           abort ();
14606         }
14607       break;
14608     case ymmq_mode:
14609       if (!need_vex)
14610         abort ();
14611
14612       switch (vex.length)
14613         {
14614         case 128:
14615           oappend ("QWORD PTR ");
14616           break;
14617         case 256:
14618           oappend ("YMMWORD PTR ");
14619           break;
14620         case 512:
14621           oappend ("ZMMWORD PTR ");
14622           break;
14623         default:
14624           abort ();
14625         }
14626       break;
14627     case ymmxmm_mode:
14628       if (!need_vex)
14629         abort ();
14630
14631       switch (vex.length)
14632         {
14633         case 128:
14634         case 256:
14635           oappend ("XMMWORD PTR ");
14636           break;
14637         default:
14638           abort ();
14639         }
14640       break;
14641     case o_mode:
14642       oappend ("OWORD PTR ");
14643       break;
14644     case xmm_mdq_mode:
14645     case vex_w_dq_mode:
14646     case vex_scalar_w_dq_mode:
14647       if (!need_vex)
14648         abort ();
14649
14650       if (vex.w)
14651         oappend ("QWORD PTR ");
14652       else
14653         oappend ("DWORD PTR ");
14654       break;
14655     case vex_vsib_d_w_dq_mode:
14656     case vex_vsib_q_w_dq_mode:
14657       if (!need_vex)
14658         abort ();
14659
14660       if (!vex.evex)
14661         {
14662           if (vex.w)
14663             oappend ("QWORD PTR ");
14664           else
14665             oappend ("DWORD PTR ");
14666         }
14667       else
14668         {
14669           switch (vex.length)
14670             {
14671             case 128:
14672               oappend ("XMMWORD PTR ");
14673               break;
14674             case 256:
14675               oappend ("YMMWORD PTR ");
14676               break;
14677             case 512:
14678               oappend ("ZMMWORD PTR ");
14679               break;
14680             default:
14681               abort ();
14682             }
14683         }
14684       break;
14685     case vex_vsib_q_w_d_mode:
14686     case vex_vsib_d_w_d_mode:
14687       if (!need_vex || !vex.evex)
14688         abort ();
14689
14690       switch (vex.length)
14691         {
14692         case 128:
14693           oappend ("QWORD PTR ");
14694           break;
14695         case 256:
14696           oappend ("XMMWORD PTR ");
14697           break;
14698         case 512:
14699           oappend ("YMMWORD PTR ");
14700           break;
14701         default:
14702           abort ();
14703         }
14704
14705       break;
14706     case mask_bd_mode:
14707       if (!need_vex || vex.length != 128)
14708         abort ();
14709       if (vex.w)
14710         oappend ("DWORD PTR ");
14711       else
14712         oappend ("BYTE PTR ");
14713       break;
14714     case mask_mode:
14715       if (!need_vex)
14716         abort ();
14717       if (vex.w)
14718         oappend ("QWORD PTR ");
14719       else
14720         oappend ("WORD PTR ");
14721       break;
14722     case v_bnd_mode:
14723     default:
14724       break;
14725     }
14726 }
14727
14728 static void
14729 OP_E_register (int bytemode, int sizeflag)
14730 {
14731   int reg = modrm.rm;
14732   const char **names;
14733
14734   USED_REX (REX_B);
14735   if ((rex & REX_B))
14736     reg += 8;
14737
14738   if ((sizeflag & SUFFIX_ALWAYS)
14739       && (bytemode == b_swap_mode
14740           || bytemode == v_swap_mode
14741           || bytemode == dqw_swap_mode))
14742     swap_operand ();
14743
14744   switch (bytemode)
14745     {
14746     case b_mode:
14747     case b_swap_mode:
14748       USED_REX (0);
14749       if (rex)
14750         names = names8rex;
14751       else
14752         names = names8;
14753       break;
14754     case w_mode:
14755       names = names16;
14756       break;
14757     case d_mode:
14758     case dw_mode:
14759     case db_mode:
14760       names = names32;
14761       break;
14762     case q_mode:
14763       names = names64;
14764       break;
14765     case m_mode:
14766     case v_bnd_mode:
14767       names = address_mode == mode_64bit ? names64 : names32;
14768       break;
14769     case bnd_mode:
14770       names = names_bnd;
14771       break;
14772     case stack_v_mode:
14773       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14774         {
14775           names = names64;
14776           break;
14777         }
14778       bytemode = v_mode;
14779       /* FALLTHRU */
14780     case v_mode:
14781     case v_swap_mode:
14782     case dq_mode:
14783     case dqb_mode:
14784     case dqd_mode:
14785     case dqw_mode:
14786     case dqw_swap_mode:
14787       USED_REX (REX_W);
14788       if (rex & REX_W)
14789         names = names64;
14790       else
14791         {
14792           if ((sizeflag & DFLAG)
14793               || (bytemode != v_mode
14794                   && bytemode != v_swap_mode))
14795             names = names32;
14796           else
14797             names = names16;
14798           used_prefixes |= (prefixes & PREFIX_DATA);
14799         }
14800       break;
14801     case mask_bd_mode:
14802     case mask_mode:
14803       names = names_mask;
14804       break;
14805     case 0:
14806       return;
14807     default:
14808       oappend (INTERNAL_DISASSEMBLER_ERROR);
14809       return;
14810     }
14811   oappend (names[reg]);
14812 }
14813
14814 static void
14815 OP_E_memory (int bytemode, int sizeflag)
14816 {
14817   bfd_vma disp = 0;
14818   int add = (rex & REX_B) ? 8 : 0;
14819   int riprel = 0;
14820   int shift;
14821
14822   if (vex.evex)
14823     {
14824       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14825       if (vex.b
14826           && bytemode != x_mode
14827           && bytemode != xmmq_mode
14828           && bytemode != evex_half_bcst_xmmq_mode)
14829         {
14830           BadOp ();
14831           return;
14832         }
14833       switch (bytemode)
14834         {
14835         case dqw_mode:
14836         case dw_mode:
14837         case dqw_swap_mode:
14838           shift = 1;
14839           break;
14840         case dqb_mode:
14841         case db_mode:
14842           shift = 0;
14843           break;
14844         case vex_vsib_d_w_dq_mode:
14845         case vex_vsib_d_w_d_mode:
14846         case vex_vsib_q_w_dq_mode:
14847         case vex_vsib_q_w_d_mode:
14848         case evex_x_gscat_mode:
14849         case xmm_mdq_mode:
14850           shift = vex.w ? 3 : 2;
14851           break;
14852         case x_mode:
14853         case evex_half_bcst_xmmq_mode:
14854         case xmmq_mode:
14855           if (vex.b)
14856             {
14857               shift = vex.w ? 3 : 2;
14858               break;
14859             }
14860           /* Fall through if vex.b == 0.  */
14861         case xmmqd_mode:
14862         case xmmdw_mode:
14863         case ymmq_mode:
14864         case evex_x_nobcst_mode:
14865         case x_swap_mode:
14866           switch (vex.length)
14867             {
14868             case 128:
14869               shift = 4;
14870               break;
14871             case 256:
14872               shift = 5;
14873               break;
14874             case 512:
14875               shift = 6;
14876               break;
14877             default:
14878               abort ();
14879             }
14880           break;
14881         case ymm_mode:
14882           shift = 5;
14883           break;
14884         case xmm_mode:
14885           shift = 4;
14886           break;
14887         case xmm_mq_mode:
14888         case q_mode:
14889         case q_scalar_mode:
14890         case q_swap_mode:
14891         case q_scalar_swap_mode:
14892           shift = 3;
14893           break;
14894         case dqd_mode:
14895         case xmm_md_mode:
14896         case d_mode:
14897         case d_scalar_mode:
14898         case d_swap_mode:
14899         case d_scalar_swap_mode:
14900           shift = 2;
14901           break;
14902         case xmm_mw_mode:
14903           shift = 1;
14904           break;
14905         case xmm_mb_mode:
14906           shift = 0;
14907           break;
14908         default:
14909           abort ();
14910         }
14911       /* Make necessary corrections to shift for modes that need it.
14912          For these modes we currently have shift 4, 5 or 6 depending on
14913          vex.length (it corresponds to xmmword, ymmword or zmmword
14914          operand).  We might want to make it 3, 4 or 5 (e.g. for
14915          xmmq_mode).  In case of broadcast enabled the corrections
14916          aren't needed, as element size is always 32 or 64 bits.  */
14917       if (!vex.b
14918           && (bytemode == xmmq_mode
14919               || bytemode == evex_half_bcst_xmmq_mode))
14920         shift -= 1;
14921       else if (bytemode == xmmqd_mode)
14922         shift -= 2;
14923       else if (bytemode == xmmdw_mode)
14924         shift -= 3;
14925       else if (bytemode == ymmq_mode && vex.length == 128)
14926         shift -= 1;
14927     }
14928   else
14929     shift = 0;
14930
14931   USED_REX (REX_B);
14932   if (intel_syntax)
14933     intel_operand_size (bytemode, sizeflag);
14934   append_seg ();
14935
14936   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14937     {
14938       /* 32/64 bit address mode */
14939       int havedisp;
14940       int havesib;
14941       int havebase;
14942       int haveindex;
14943       int needindex;
14944       int base, rbase;
14945       int vindex = 0;
14946       int scale = 0;
14947       int addr32flag = !((sizeflag & AFLAG)
14948                          || bytemode == v_bnd_mode
14949                          || bytemode == bnd_mode);
14950       const char **indexes64 = names64;
14951       const char **indexes32 = names32;
14952
14953       havesib = 0;
14954       havebase = 1;
14955       haveindex = 0;
14956       base = modrm.rm;
14957
14958       if (base == 4)
14959         {
14960           havesib = 1;
14961           vindex = sib.index;
14962           USED_REX (REX_X);
14963           if (rex & REX_X)
14964             vindex += 8;
14965           switch (bytemode)
14966             {
14967             case vex_vsib_d_w_dq_mode:
14968             case vex_vsib_d_w_d_mode:
14969             case vex_vsib_q_w_dq_mode:
14970             case vex_vsib_q_w_d_mode:
14971               if (!need_vex)
14972                 abort ();
14973               if (vex.evex)
14974                 {
14975                   if (!vex.v)
14976                     vindex += 16;
14977                 }
14978
14979               haveindex = 1;
14980               switch (vex.length)
14981                 {
14982                 case 128:
14983                   indexes64 = indexes32 = names_xmm;
14984                   break;
14985                 case 256:
14986                   if (!vex.w
14987                       || bytemode == vex_vsib_q_w_dq_mode
14988                       || bytemode == vex_vsib_q_w_d_mode)
14989                     indexes64 = indexes32 = names_ymm;
14990                   else
14991                     indexes64 = indexes32 = names_xmm;
14992                   break;
14993                 case 512:
14994                   if (!vex.w
14995                       || bytemode == vex_vsib_q_w_dq_mode
14996                       || bytemode == vex_vsib_q_w_d_mode)
14997                     indexes64 = indexes32 = names_zmm;
14998                   else
14999                     indexes64 = indexes32 = names_ymm;
15000                   break;
15001                 default:
15002                   abort ();
15003                 }
15004               break;
15005             default:
15006               haveindex = vindex != 4;
15007               break;
15008             }
15009           scale = sib.scale;
15010           base = sib.base;
15011           codep++;
15012         }
15013       rbase = base + add;
15014
15015       switch (modrm.mod)
15016         {
15017         case 0:
15018           if (base == 5)
15019             {
15020               havebase = 0;
15021               if (address_mode == mode_64bit && !havesib)
15022                 riprel = 1;
15023               disp = get32s ();
15024             }
15025           break;
15026         case 1:
15027           FETCH_DATA (the_info, codep + 1);
15028           disp = *codep++;
15029           if ((disp & 0x80) != 0)
15030             disp -= 0x100;
15031           if (vex.evex && shift > 0)
15032             disp <<= shift;
15033           break;
15034         case 2:
15035           disp = get32s ();
15036           break;
15037         }
15038
15039       /* In 32bit mode, we need index register to tell [offset] from
15040          [eiz*1 + offset].  */
15041       needindex = (havesib
15042                    && !havebase
15043                    && !haveindex
15044                    && address_mode == mode_32bit);
15045       havedisp = (havebase
15046                   || needindex
15047                   || (havesib && (haveindex || scale != 0)));
15048
15049       if (!intel_syntax)
15050         if (modrm.mod != 0 || base == 5)
15051           {
15052             if (havedisp || riprel)
15053               print_displacement (scratchbuf, disp);
15054             else
15055               print_operand_value (scratchbuf, 1, disp);
15056             oappend (scratchbuf);
15057             if (riprel)
15058               {
15059                 set_op (disp, 1);
15060                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
15061               }
15062           }
15063
15064       if ((havebase || haveindex || riprel)
15065           && (bytemode != v_bnd_mode)
15066           && (bytemode != bnd_mode))
15067         used_prefixes |= PREFIX_ADDR;
15068
15069       if (havedisp || (intel_syntax && riprel))
15070         {
15071           *obufp++ = open_char;
15072           if (intel_syntax && riprel)
15073             {
15074               set_op (disp, 1);
15075               oappend (sizeflag & AFLAG ? "rip" : "eip");
15076             }
15077           *obufp = '\0';
15078           if (havebase)
15079             oappend (address_mode == mode_64bit && !addr32flag
15080                      ? names64[rbase] : names32[rbase]);
15081           if (havesib)
15082             {
15083               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15084                  print index to tell base + index from base.  */
15085               if (scale != 0
15086                   || needindex
15087                   || haveindex
15088                   || (havebase && base != ESP_REG_NUM))
15089                 {
15090                   if (!intel_syntax || havebase)
15091                     {
15092                       *obufp++ = separator_char;
15093                       *obufp = '\0';
15094                     }
15095                   if (haveindex)
15096                     oappend (address_mode == mode_64bit && !addr32flag
15097                              ? indexes64[vindex] : indexes32[vindex]);
15098                   else
15099                     oappend (address_mode == mode_64bit && !addr32flag
15100                              ? index64 : index32);
15101
15102                   *obufp++ = scale_char;
15103                   *obufp = '\0';
15104                   sprintf (scratchbuf, "%d", 1 << scale);
15105                   oappend (scratchbuf);
15106                 }
15107             }
15108           if (intel_syntax
15109               && (disp || modrm.mod != 0 || base == 5))
15110             {
15111               if (!havedisp || (bfd_signed_vma) disp >= 0)
15112                 {
15113                   *obufp++ = '+';
15114                   *obufp = '\0';
15115                 }
15116               else if (modrm.mod != 1 && disp != -disp)
15117                 {
15118                   *obufp++ = '-';
15119                   *obufp = '\0';
15120                   disp = - (bfd_signed_vma) disp;
15121                 }
15122
15123               if (havedisp)
15124                 print_displacement (scratchbuf, disp);
15125               else
15126                 print_operand_value (scratchbuf, 1, disp);
15127               oappend (scratchbuf);
15128             }
15129
15130           *obufp++ = close_char;
15131           *obufp = '\0';
15132         }
15133       else if (intel_syntax)
15134         {
15135           if (modrm.mod != 0 || base == 5)
15136             {
15137               if (!active_seg_prefix)
15138                 {
15139                   oappend (names_seg[ds_reg - es_reg]);
15140                   oappend (":");
15141                 }
15142               print_operand_value (scratchbuf, 1, disp);
15143               oappend (scratchbuf);
15144             }
15145         }
15146     }
15147   else
15148     {
15149       /* 16 bit address mode */
15150       used_prefixes |= prefixes & PREFIX_ADDR;
15151       switch (modrm.mod)
15152         {
15153         case 0:
15154           if (modrm.rm == 6)
15155             {
15156               disp = get16 ();
15157               if ((disp & 0x8000) != 0)
15158                 disp -= 0x10000;
15159             }
15160           break;
15161         case 1:
15162           FETCH_DATA (the_info, codep + 1);
15163           disp = *codep++;
15164           if ((disp & 0x80) != 0)
15165             disp -= 0x100;
15166           break;
15167         case 2:
15168           disp = get16 ();
15169           if ((disp & 0x8000) != 0)
15170             disp -= 0x10000;
15171           break;
15172         }
15173
15174       if (!intel_syntax)
15175         if (modrm.mod != 0 || modrm.rm == 6)
15176           {
15177             print_displacement (scratchbuf, disp);
15178             oappend (scratchbuf);
15179           }
15180
15181       if (modrm.mod != 0 || modrm.rm != 6)
15182         {
15183           *obufp++ = open_char;
15184           *obufp = '\0';
15185           oappend (index16[modrm.rm]);
15186           if (intel_syntax
15187               && (disp || modrm.mod != 0 || modrm.rm == 6))
15188             {
15189               if ((bfd_signed_vma) disp >= 0)
15190                 {
15191                   *obufp++ = '+';
15192                   *obufp = '\0';
15193                 }
15194               else if (modrm.mod != 1)
15195                 {
15196                   *obufp++ = '-';
15197                   *obufp = '\0';
15198                   disp = - (bfd_signed_vma) disp;
15199                 }
15200
15201               print_displacement (scratchbuf, disp);
15202               oappend (scratchbuf);
15203             }
15204
15205           *obufp++ = close_char;
15206           *obufp = '\0';
15207         }
15208       else if (intel_syntax)
15209         {
15210           if (!active_seg_prefix)
15211             {
15212               oappend (names_seg[ds_reg - es_reg]);
15213               oappend (":");
15214             }
15215           print_operand_value (scratchbuf, 1, disp & 0xffff);
15216           oappend (scratchbuf);
15217         }
15218     }
15219   if (vex.evex && vex.b
15220       && (bytemode == x_mode
15221           || bytemode == xmmq_mode
15222           || bytemode == evex_half_bcst_xmmq_mode))
15223     {
15224       if (vex.w
15225           || bytemode == xmmq_mode
15226           || bytemode == evex_half_bcst_xmmq_mode)
15227         {
15228           switch (vex.length)
15229             {
15230             case 128:
15231               oappend ("{1to2}");
15232               break;
15233             case 256:
15234               oappend ("{1to4}");
15235               break;
15236             case 512:
15237               oappend ("{1to8}");
15238               break;
15239             default:
15240               abort ();
15241             }
15242         }
15243       else
15244         {
15245           switch (vex.length)
15246             {
15247             case 128:
15248               oappend ("{1to4}");
15249               break;
15250             case 256:
15251               oappend ("{1to8}");
15252               break;
15253             case 512:
15254               oappend ("{1to16}");
15255               break;
15256             default:
15257               abort ();
15258             }
15259         }
15260     }
15261 }
15262
15263 static void
15264 OP_E (int bytemode, int sizeflag)
15265 {
15266   /* Skip mod/rm byte.  */
15267   MODRM_CHECK;
15268   codep++;
15269
15270   if (modrm.mod == 3)
15271     OP_E_register (bytemode, sizeflag);
15272   else
15273     OP_E_memory (bytemode, sizeflag);
15274 }
15275
15276 static void
15277 OP_G (int bytemode, int sizeflag)
15278 {
15279   int add = 0;
15280   USED_REX (REX_R);
15281   if (rex & REX_R)
15282     add += 8;
15283   switch (bytemode)
15284     {
15285     case b_mode:
15286       USED_REX (0);
15287       if (rex)
15288         oappend (names8rex[modrm.reg + add]);
15289       else
15290         oappend (names8[modrm.reg + add]);
15291       break;
15292     case w_mode:
15293       oappend (names16[modrm.reg + add]);
15294       break;
15295     case d_mode:
15296     case db_mode:
15297     case dw_mode:
15298       oappend (names32[modrm.reg + add]);
15299       break;
15300     case q_mode:
15301       oappend (names64[modrm.reg + add]);
15302       break;
15303     case bnd_mode:
15304       oappend (names_bnd[modrm.reg]);
15305       break;
15306     case v_mode:
15307     case dq_mode:
15308     case dqb_mode:
15309     case dqd_mode:
15310     case dqw_mode:
15311     case dqw_swap_mode:
15312       USED_REX (REX_W);
15313       if (rex & REX_W)
15314         oappend (names64[modrm.reg + add]);
15315       else
15316         {
15317           if ((sizeflag & DFLAG) || bytemode != v_mode)
15318             oappend (names32[modrm.reg + add]);
15319           else
15320             oappend (names16[modrm.reg + add]);
15321           used_prefixes |= (prefixes & PREFIX_DATA);
15322         }
15323       break;
15324     case m_mode:
15325       if (address_mode == mode_64bit)
15326         oappend (names64[modrm.reg + add]);
15327       else
15328         oappend (names32[modrm.reg + add]);
15329       break;
15330     case mask_bd_mode:
15331     case mask_mode:
15332       oappend (names_mask[modrm.reg + add]);
15333       break;
15334     default:
15335       oappend (INTERNAL_DISASSEMBLER_ERROR);
15336       break;
15337     }
15338 }
15339
15340 static bfd_vma
15341 get64 (void)
15342 {
15343   bfd_vma x;
15344 #ifdef BFD64
15345   unsigned int a;
15346   unsigned int b;
15347
15348   FETCH_DATA (the_info, codep + 8);
15349   a = *codep++ & 0xff;
15350   a |= (*codep++ & 0xff) << 8;
15351   a |= (*codep++ & 0xff) << 16;
15352   a |= (*codep++ & 0xff) << 24;
15353   b = *codep++ & 0xff;
15354   b |= (*codep++ & 0xff) << 8;
15355   b |= (*codep++ & 0xff) << 16;
15356   b |= (*codep++ & 0xff) << 24;
15357   x = a + ((bfd_vma) b << 32);
15358 #else
15359   abort ();
15360   x = 0;
15361 #endif
15362   return x;
15363 }
15364
15365 static bfd_signed_vma
15366 get32 (void)
15367 {
15368   bfd_signed_vma x = 0;
15369
15370   FETCH_DATA (the_info, codep + 4);
15371   x = *codep++ & (bfd_signed_vma) 0xff;
15372   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15373   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15374   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15375   return x;
15376 }
15377
15378 static bfd_signed_vma
15379 get32s (void)
15380 {
15381   bfd_signed_vma x = 0;
15382
15383   FETCH_DATA (the_info, codep + 4);
15384   x = *codep++ & (bfd_signed_vma) 0xff;
15385   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15386   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15387   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15388
15389   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15390
15391   return x;
15392 }
15393
15394 static int
15395 get16 (void)
15396 {
15397   int x = 0;
15398
15399   FETCH_DATA (the_info, codep + 2);
15400   x = *codep++ & 0xff;
15401   x |= (*codep++ & 0xff) << 8;
15402   return x;
15403 }
15404
15405 static void
15406 set_op (bfd_vma op, int riprel)
15407 {
15408   op_index[op_ad] = op_ad;
15409   if (address_mode == mode_64bit)
15410     {
15411       op_address[op_ad] = op;
15412       op_riprel[op_ad] = riprel;
15413     }
15414   else
15415     {
15416       /* Mask to get a 32-bit address.  */
15417       op_address[op_ad] = op & 0xffffffff;
15418       op_riprel[op_ad] = riprel & 0xffffffff;
15419     }
15420 }
15421
15422 static void
15423 OP_REG (int code, int sizeflag)
15424 {
15425   const char *s;
15426   int add;
15427
15428   switch (code)
15429     {
15430     case es_reg: case ss_reg: case cs_reg:
15431     case ds_reg: case fs_reg: case gs_reg:
15432       oappend (names_seg[code - es_reg]);
15433       return;
15434     }
15435
15436   USED_REX (REX_B);
15437   if (rex & REX_B)
15438     add = 8;
15439   else
15440     add = 0;
15441
15442   switch (code)
15443     {
15444     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15445     case sp_reg: case bp_reg: case si_reg: case di_reg:
15446       s = names16[code - ax_reg + add];
15447       break;
15448     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15449     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15450       USED_REX (0);
15451       if (rex)
15452         s = names8rex[code - al_reg + add];
15453       else
15454         s = names8[code - al_reg];
15455       break;
15456     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15457     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15458       if (address_mode == mode_64bit
15459           && ((sizeflag & DFLAG) || (rex & REX_W)))
15460         {
15461           s = names64[code - rAX_reg + add];
15462           break;
15463         }
15464       code += eAX_reg - rAX_reg;
15465       /* Fall through.  */
15466     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15467     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15468       USED_REX (REX_W);
15469       if (rex & REX_W)
15470         s = names64[code - eAX_reg + add];
15471       else
15472         {
15473           if (sizeflag & DFLAG)
15474             s = names32[code - eAX_reg + add];
15475           else
15476             s = names16[code - eAX_reg + add];
15477           used_prefixes |= (prefixes & PREFIX_DATA);
15478         }
15479       break;
15480     default:
15481       s = INTERNAL_DISASSEMBLER_ERROR;
15482       break;
15483     }
15484   oappend (s);
15485 }
15486
15487 static void
15488 OP_IMREG (int code, int sizeflag)
15489 {
15490   const char *s;
15491
15492   switch (code)
15493     {
15494     case indir_dx_reg:
15495       if (intel_syntax)
15496         s = "dx";
15497       else
15498         s = "(%dx)";
15499       break;
15500     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15501     case sp_reg: case bp_reg: case si_reg: case di_reg:
15502       s = names16[code - ax_reg];
15503       break;
15504     case es_reg: case ss_reg: case cs_reg:
15505     case ds_reg: case fs_reg: case gs_reg:
15506       s = names_seg[code - es_reg];
15507       break;
15508     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15509     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15510       USED_REX (0);
15511       if (rex)
15512         s = names8rex[code - al_reg];
15513       else
15514         s = names8[code - al_reg];
15515       break;
15516     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15517     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15518       USED_REX (REX_W);
15519       if (rex & REX_W)
15520         s = names64[code - eAX_reg];
15521       else
15522         {
15523           if (sizeflag & DFLAG)
15524             s = names32[code - eAX_reg];
15525           else
15526             s = names16[code - eAX_reg];
15527           used_prefixes |= (prefixes & PREFIX_DATA);
15528         }
15529       break;
15530     case z_mode_ax_reg:
15531       if ((rex & REX_W) || (sizeflag & DFLAG))
15532         s = *names32;
15533       else
15534         s = *names16;
15535       if (!(rex & REX_W))
15536         used_prefixes |= (prefixes & PREFIX_DATA);
15537       break;
15538     default:
15539       s = INTERNAL_DISASSEMBLER_ERROR;
15540       break;
15541     }
15542   oappend (s);
15543 }
15544
15545 static void
15546 OP_I (int bytemode, int sizeflag)
15547 {
15548   bfd_signed_vma op;
15549   bfd_signed_vma mask = -1;
15550
15551   switch (bytemode)
15552     {
15553     case b_mode:
15554       FETCH_DATA (the_info, codep + 1);
15555       op = *codep++;
15556       mask = 0xff;
15557       break;
15558     case q_mode:
15559       if (address_mode == mode_64bit)
15560         {
15561           op = get32s ();
15562           break;
15563         }
15564       /* Fall through.  */
15565     case v_mode:
15566       USED_REX (REX_W);
15567       if (rex & REX_W)
15568         op = get32s ();
15569       else
15570         {
15571           if (sizeflag & DFLAG)
15572             {
15573               op = get32 ();
15574               mask = 0xffffffff;
15575             }
15576           else
15577             {
15578               op = get16 ();
15579               mask = 0xfffff;
15580             }
15581           used_prefixes |= (prefixes & PREFIX_DATA);
15582         }
15583       break;
15584     case w_mode:
15585       mask = 0xfffff;
15586       op = get16 ();
15587       break;
15588     case const_1_mode:
15589       if (intel_syntax)
15590         oappend ("1");
15591       return;
15592     default:
15593       oappend (INTERNAL_DISASSEMBLER_ERROR);
15594       return;
15595     }
15596
15597   op &= mask;
15598   scratchbuf[0] = '$';
15599   print_operand_value (scratchbuf + 1, 1, op);
15600   oappend_maybe_intel (scratchbuf);
15601   scratchbuf[0] = '\0';
15602 }
15603
15604 static void
15605 OP_I64 (int bytemode, int sizeflag)
15606 {
15607   bfd_signed_vma op;
15608   bfd_signed_vma mask = -1;
15609
15610   if (address_mode != mode_64bit)
15611     {
15612       OP_I (bytemode, sizeflag);
15613       return;
15614     }
15615
15616   switch (bytemode)
15617     {
15618     case b_mode:
15619       FETCH_DATA (the_info, codep + 1);
15620       op = *codep++;
15621       mask = 0xff;
15622       break;
15623     case v_mode:
15624       USED_REX (REX_W);
15625       if (rex & REX_W)
15626         op = get64 ();
15627       else
15628         {
15629           if (sizeflag & DFLAG)
15630             {
15631               op = get32 ();
15632               mask = 0xffffffff;
15633             }
15634           else
15635             {
15636               op = get16 ();
15637               mask = 0xfffff;
15638             }
15639           used_prefixes |= (prefixes & PREFIX_DATA);
15640         }
15641       break;
15642     case w_mode:
15643       mask = 0xfffff;
15644       op = get16 ();
15645       break;
15646     default:
15647       oappend (INTERNAL_DISASSEMBLER_ERROR);
15648       return;
15649     }
15650
15651   op &= mask;
15652   scratchbuf[0] = '$';
15653   print_operand_value (scratchbuf + 1, 1, op);
15654   oappend_maybe_intel (scratchbuf);
15655   scratchbuf[0] = '\0';
15656 }
15657
15658 static void
15659 OP_sI (int bytemode, int sizeflag)
15660 {
15661   bfd_signed_vma op;
15662
15663   switch (bytemode)
15664     {
15665     case b_mode:
15666     case b_T_mode:
15667       FETCH_DATA (the_info, codep + 1);
15668       op = *codep++;
15669       if ((op & 0x80) != 0)
15670         op -= 0x100;
15671       if (bytemode == b_T_mode)
15672         {
15673           if (address_mode != mode_64bit
15674               || !((sizeflag & DFLAG) || (rex & REX_W)))
15675             {
15676               /* The operand-size prefix is overridden by a REX prefix.  */
15677               if ((sizeflag & DFLAG) || (rex & REX_W))
15678                 op &= 0xffffffff;
15679               else
15680                 op &= 0xffff;
15681           }
15682         }
15683       else
15684         {
15685           if (!(rex & REX_W))
15686             {
15687               if (sizeflag & DFLAG)
15688                 op &= 0xffffffff;
15689               else
15690                 op &= 0xffff;
15691             }
15692         }
15693       break;
15694     case v_mode:
15695       /* The operand-size prefix is overridden by a REX prefix.  */
15696       if ((sizeflag & DFLAG) || (rex & REX_W))
15697         op = get32s ();
15698       else
15699         op = get16 ();
15700       break;
15701     default:
15702       oappend (INTERNAL_DISASSEMBLER_ERROR);
15703       return;
15704     }
15705
15706   scratchbuf[0] = '$';
15707   print_operand_value (scratchbuf + 1, 1, op);
15708   oappend_maybe_intel (scratchbuf);
15709 }
15710
15711 static void
15712 OP_J (int bytemode, int sizeflag)
15713 {
15714   bfd_vma disp;
15715   bfd_vma mask = -1;
15716   bfd_vma segment = 0;
15717
15718   switch (bytemode)
15719     {
15720     case b_mode:
15721       FETCH_DATA (the_info, codep + 1);
15722       disp = *codep++;
15723       if ((disp & 0x80) != 0)
15724         disp -= 0x100;
15725       break;
15726     case v_mode:
15727       if (address_mode == mode_64bit || (sizeflag & DFLAG))
15728         disp = get32s ();
15729       else
15730         {
15731           disp = get16 ();
15732           if ((disp & 0x8000) != 0)
15733             disp -= 0x10000;
15734           /* In 16bit mode, address is wrapped around at 64k within
15735              the same segment.  Otherwise, a data16 prefix on a jump
15736              instruction means that the pc is masked to 16 bits after
15737              the displacement is added!  */
15738           mask = 0xffff;
15739           if ((prefixes & PREFIX_DATA) == 0)
15740             segment = ((start_pc + codep - start_codep)
15741                        & ~((bfd_vma) 0xffff));
15742         }
15743       if (address_mode != mode_64bit)
15744         used_prefixes |= (prefixes & PREFIX_DATA);
15745       break;
15746     default:
15747       oappend (INTERNAL_DISASSEMBLER_ERROR);
15748       return;
15749     }
15750   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15751   set_op (disp, 0);
15752   print_operand_value (scratchbuf, 1, disp);
15753   oappend (scratchbuf);
15754 }
15755
15756 static void
15757 OP_SEG (int bytemode, int sizeflag)
15758 {
15759   if (bytemode == w_mode)
15760     oappend (names_seg[modrm.reg]);
15761   else
15762     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15763 }
15764
15765 static void
15766 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15767 {
15768   int seg, offset;
15769
15770   if (sizeflag & DFLAG)
15771     {
15772       offset = get32 ();
15773       seg = get16 ();
15774     }
15775   else
15776     {
15777       offset = get16 ();
15778       seg = get16 ();
15779     }
15780   used_prefixes |= (prefixes & PREFIX_DATA);
15781   if (intel_syntax)
15782     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15783   else
15784     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15785   oappend (scratchbuf);
15786 }
15787
15788 static void
15789 OP_OFF (int bytemode, int sizeflag)
15790 {
15791   bfd_vma off;
15792
15793   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15794     intel_operand_size (bytemode, sizeflag);
15795   append_seg ();
15796
15797   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15798     off = get32 ();
15799   else
15800     off = get16 ();
15801
15802   if (intel_syntax)
15803     {
15804       if (!active_seg_prefix)
15805         {
15806           oappend (names_seg[ds_reg - es_reg]);
15807           oappend (":");
15808         }
15809     }
15810   print_operand_value (scratchbuf, 1, off);
15811   oappend (scratchbuf);
15812 }
15813
15814 static void
15815 OP_OFF64 (int bytemode, int sizeflag)
15816 {
15817   bfd_vma off;
15818
15819   if (address_mode != mode_64bit
15820       || (prefixes & PREFIX_ADDR))
15821     {
15822       OP_OFF (bytemode, sizeflag);
15823       return;
15824     }
15825
15826   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15827     intel_operand_size (bytemode, sizeflag);
15828   append_seg ();
15829
15830   off = get64 ();
15831
15832   if (intel_syntax)
15833     {
15834       if (!active_seg_prefix)
15835         {
15836           oappend (names_seg[ds_reg - es_reg]);
15837           oappend (":");
15838         }
15839     }
15840   print_operand_value (scratchbuf, 1, off);
15841   oappend (scratchbuf);
15842 }
15843
15844 static void
15845 ptr_reg (int code, int sizeflag)
15846 {
15847   const char *s;
15848
15849   *obufp++ = open_char;
15850   used_prefixes |= (prefixes & PREFIX_ADDR);
15851   if (address_mode == mode_64bit)
15852     {
15853       if (!(sizeflag & AFLAG))
15854         s = names32[code - eAX_reg];
15855       else
15856         s = names64[code - eAX_reg];
15857     }
15858   else if (sizeflag & AFLAG)
15859     s = names32[code - eAX_reg];
15860   else
15861     s = names16[code - eAX_reg];
15862   oappend (s);
15863   *obufp++ = close_char;
15864   *obufp = 0;
15865 }
15866
15867 static void
15868 OP_ESreg (int code, int sizeflag)
15869 {
15870   if (intel_syntax)
15871     {
15872       switch (codep[-1])
15873         {
15874         case 0x6d:      /* insw/insl */
15875           intel_operand_size (z_mode, sizeflag);
15876           break;
15877         case 0xa5:      /* movsw/movsl/movsq */
15878         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15879         case 0xab:      /* stosw/stosl */
15880         case 0xaf:      /* scasw/scasl */
15881           intel_operand_size (v_mode, sizeflag);
15882           break;
15883         default:
15884           intel_operand_size (b_mode, sizeflag);
15885         }
15886     }
15887   oappend_maybe_intel ("%es:");
15888   ptr_reg (code, sizeflag);
15889 }
15890
15891 static void
15892 OP_DSreg (int code, int sizeflag)
15893 {
15894   if (intel_syntax)
15895     {
15896       switch (codep[-1])
15897         {
15898         case 0x6f:      /* outsw/outsl */
15899           intel_operand_size (z_mode, sizeflag);
15900           break;
15901         case 0xa5:      /* movsw/movsl/movsq */
15902         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15903         case 0xad:      /* lodsw/lodsl/lodsq */
15904           intel_operand_size (v_mode, sizeflag);
15905           break;
15906         default:
15907           intel_operand_size (b_mode, sizeflag);
15908         }
15909     }
15910   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15911      default segment register DS is printed.  */
15912   if (!active_seg_prefix)
15913     active_seg_prefix = PREFIX_DS;
15914   append_seg ();
15915   ptr_reg (code, sizeflag);
15916 }
15917
15918 static void
15919 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15920 {
15921   int add;
15922   if (rex & REX_R)
15923     {
15924       USED_REX (REX_R);
15925       add = 8;
15926     }
15927   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15928     {
15929       all_prefixes[last_lock_prefix] = 0;
15930       used_prefixes |= PREFIX_LOCK;
15931       add = 8;
15932     }
15933   else
15934     add = 0;
15935   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15936   oappend_maybe_intel (scratchbuf);
15937 }
15938
15939 static void
15940 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15941 {
15942   int add;
15943   USED_REX (REX_R);
15944   if (rex & REX_R)
15945     add = 8;
15946   else
15947     add = 0;
15948   if (intel_syntax)
15949     sprintf (scratchbuf, "db%d", modrm.reg + add);
15950   else
15951     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15952   oappend (scratchbuf);
15953 }
15954
15955 static void
15956 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15957 {
15958   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15959   oappend_maybe_intel (scratchbuf);
15960 }
15961
15962 static void
15963 OP_R (int bytemode, int sizeflag)
15964 {
15965   /* Skip mod/rm byte.  */
15966   MODRM_CHECK;
15967   codep++;
15968   OP_E_register (bytemode, sizeflag);
15969 }
15970
15971 static void
15972 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15973 {
15974   int reg = modrm.reg;
15975   const char **names;
15976
15977   used_prefixes |= (prefixes & PREFIX_DATA);
15978   if (prefixes & PREFIX_DATA)
15979     {
15980       names = names_xmm;
15981       USED_REX (REX_R);
15982       if (rex & REX_R)
15983         reg += 8;
15984     }
15985   else
15986     names = names_mm;
15987   oappend (names[reg]);
15988 }
15989
15990 static void
15991 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15992 {
15993   int reg = modrm.reg;
15994   const char **names;
15995
15996   USED_REX (REX_R);
15997   if (rex & REX_R)
15998     reg += 8;
15999   if (vex.evex)
16000     {
16001       if (!vex.r)
16002         reg += 16;
16003     }
16004
16005   if (need_vex
16006       && bytemode != xmm_mode
16007       && bytemode != xmmq_mode
16008       && bytemode != evex_half_bcst_xmmq_mode
16009       && bytemode != ymm_mode
16010       && bytemode != scalar_mode)
16011     {
16012       switch (vex.length)
16013         {
16014         case 128:
16015           names = names_xmm;
16016           break;
16017         case 256:
16018           if (vex.w
16019               || (bytemode != vex_vsib_q_w_dq_mode
16020                   && bytemode != vex_vsib_q_w_d_mode))
16021             names = names_ymm;
16022           else
16023             names = names_xmm;
16024           break;
16025         case 512:
16026           names = names_zmm;
16027           break;
16028         default:
16029           abort ();
16030         }
16031     }
16032   else if (bytemode == xmmq_mode
16033            || bytemode == evex_half_bcst_xmmq_mode)
16034     {
16035       switch (vex.length)
16036         {
16037         case 128:
16038         case 256:
16039           names = names_xmm;
16040           break;
16041         case 512:
16042           names = names_ymm;
16043           break;
16044         default:
16045           abort ();
16046         }
16047     }
16048   else if (bytemode == ymm_mode)
16049     names = names_ymm;
16050   else
16051     names = names_xmm;
16052   oappend (names[reg]);
16053 }
16054
16055 static void
16056 OP_EM (int bytemode, int sizeflag)
16057 {
16058   int reg;
16059   const char **names;
16060
16061   if (modrm.mod != 3)
16062     {
16063       if (intel_syntax
16064           && (bytemode == v_mode || bytemode == v_swap_mode))
16065         {
16066           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16067           used_prefixes |= (prefixes & PREFIX_DATA);
16068         }
16069       OP_E (bytemode, sizeflag);
16070       return;
16071     }
16072
16073   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16074     swap_operand ();
16075
16076   /* Skip mod/rm byte.  */
16077   MODRM_CHECK;
16078   codep++;
16079   used_prefixes |= (prefixes & PREFIX_DATA);
16080   reg = modrm.rm;
16081   if (prefixes & PREFIX_DATA)
16082     {
16083       names = names_xmm;
16084       USED_REX (REX_B);
16085       if (rex & REX_B)
16086         reg += 8;
16087     }
16088   else
16089     names = names_mm;
16090   oappend (names[reg]);
16091 }
16092
16093 /* cvt* are the only instructions in sse2 which have
16094    both SSE and MMX operands and also have 0x66 prefix
16095    in their opcode. 0x66 was originally used to differentiate
16096    between SSE and MMX instruction(operands). So we have to handle the
16097    cvt* separately using OP_EMC and OP_MXC */
16098 static void
16099 OP_EMC (int bytemode, int sizeflag)
16100 {
16101   if (modrm.mod != 3)
16102     {
16103       if (intel_syntax && bytemode == v_mode)
16104         {
16105           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16106           used_prefixes |= (prefixes & PREFIX_DATA);
16107         }
16108       OP_E (bytemode, sizeflag);
16109       return;
16110     }
16111
16112   /* Skip mod/rm byte.  */
16113   MODRM_CHECK;
16114   codep++;
16115   used_prefixes |= (prefixes & PREFIX_DATA);
16116   oappend (names_mm[modrm.rm]);
16117 }
16118
16119 static void
16120 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16121 {
16122   used_prefixes |= (prefixes & PREFIX_DATA);
16123   oappend (names_mm[modrm.reg]);
16124 }
16125
16126 static void
16127 OP_EX (int bytemode, int sizeflag)
16128 {
16129   int reg;
16130   const char **names;
16131
16132   /* Skip mod/rm byte.  */
16133   MODRM_CHECK;
16134   codep++;
16135
16136   if (modrm.mod != 3)
16137     {
16138       OP_E_memory (bytemode, sizeflag);
16139       return;
16140     }
16141
16142   reg = modrm.rm;
16143   USED_REX (REX_B);
16144   if (rex & REX_B)
16145     reg += 8;
16146   if (vex.evex)
16147     {
16148       USED_REX (REX_X);
16149       if ((rex & REX_X))
16150         reg += 16;
16151     }
16152
16153   if ((sizeflag & SUFFIX_ALWAYS)
16154       && (bytemode == x_swap_mode
16155           || bytemode == d_swap_mode
16156           || bytemode == dqw_swap_mode
16157           || bytemode == d_scalar_swap_mode
16158           || bytemode == q_swap_mode
16159           || bytemode == q_scalar_swap_mode))
16160     swap_operand ();
16161
16162   if (need_vex
16163       && bytemode != xmm_mode
16164       && bytemode != xmmdw_mode
16165       && bytemode != xmmqd_mode
16166       && bytemode != xmm_mb_mode
16167       && bytemode != xmm_mw_mode
16168       && bytemode != xmm_md_mode
16169       && bytemode != xmm_mq_mode
16170       && bytemode != xmm_mdq_mode
16171       && bytemode != xmmq_mode
16172       && bytemode != evex_half_bcst_xmmq_mode
16173       && bytemode != ymm_mode
16174       && bytemode != d_scalar_mode
16175       && bytemode != d_scalar_swap_mode
16176       && bytemode != q_scalar_mode
16177       && bytemode != q_scalar_swap_mode
16178       && bytemode != vex_scalar_w_dq_mode)
16179     {
16180       switch (vex.length)
16181         {
16182         case 128:
16183           names = names_xmm;
16184           break;
16185         case 256:
16186           names = names_ymm;
16187           break;
16188         case 512:
16189           names = names_zmm;
16190           break;
16191         default:
16192           abort ();
16193         }
16194     }
16195   else if (bytemode == xmmq_mode
16196            || bytemode == evex_half_bcst_xmmq_mode)
16197     {
16198       switch (vex.length)
16199         {
16200         case 128:
16201         case 256:
16202           names = names_xmm;
16203           break;
16204         case 512:
16205           names = names_ymm;
16206           break;
16207         default:
16208           abort ();
16209         }
16210     }
16211   else if (bytemode == ymm_mode)
16212     names = names_ymm;
16213   else
16214     names = names_xmm;
16215   oappend (names[reg]);
16216 }
16217
16218 static void
16219 OP_MS (int bytemode, int sizeflag)
16220 {
16221   if (modrm.mod == 3)
16222     OP_EM (bytemode, sizeflag);
16223   else
16224     BadOp ();
16225 }
16226
16227 static void
16228 OP_XS (int bytemode, int sizeflag)
16229 {
16230   if (modrm.mod == 3)
16231     OP_EX (bytemode, sizeflag);
16232   else
16233     BadOp ();
16234 }
16235
16236 static void
16237 OP_M (int bytemode, int sizeflag)
16238 {
16239   if (modrm.mod == 3)
16240     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16241     BadOp ();
16242   else
16243     OP_E (bytemode, sizeflag);
16244 }
16245
16246 static void
16247 OP_0f07 (int bytemode, int sizeflag)
16248 {
16249   if (modrm.mod != 3 || modrm.rm != 0)
16250     BadOp ();
16251   else
16252     OP_E (bytemode, sizeflag);
16253 }
16254
16255 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16256    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16257
16258 static void
16259 NOP_Fixup1 (int bytemode, int sizeflag)
16260 {
16261   if ((prefixes & PREFIX_DATA) != 0
16262       || (rex != 0
16263           && rex != 0x48
16264           && address_mode == mode_64bit))
16265     OP_REG (bytemode, sizeflag);
16266   else
16267     strcpy (obuf, "nop");
16268 }
16269
16270 static void
16271 NOP_Fixup2 (int bytemode, int sizeflag)
16272 {
16273   if ((prefixes & PREFIX_DATA) != 0
16274       || (rex != 0
16275           && rex != 0x48
16276           && address_mode == mode_64bit))
16277     OP_IMREG (bytemode, sizeflag);
16278 }
16279
16280 static const char *const Suffix3DNow[] = {
16281 /* 00 */        NULL,           NULL,           NULL,           NULL,
16282 /* 04 */        NULL,           NULL,           NULL,           NULL,
16283 /* 08 */        NULL,           NULL,           NULL,           NULL,
16284 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16285 /* 10 */        NULL,           NULL,           NULL,           NULL,
16286 /* 14 */        NULL,           NULL,           NULL,           NULL,
16287 /* 18 */        NULL,           NULL,           NULL,           NULL,
16288 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16289 /* 20 */        NULL,           NULL,           NULL,           NULL,
16290 /* 24 */        NULL,           NULL,           NULL,           NULL,
16291 /* 28 */        NULL,           NULL,           NULL,           NULL,
16292 /* 2C */        NULL,           NULL,           NULL,           NULL,
16293 /* 30 */        NULL,           NULL,           NULL,           NULL,
16294 /* 34 */        NULL,           NULL,           NULL,           NULL,
16295 /* 38 */        NULL,           NULL,           NULL,           NULL,
16296 /* 3C */        NULL,           NULL,           NULL,           NULL,
16297 /* 40 */        NULL,           NULL,           NULL,           NULL,
16298 /* 44 */        NULL,           NULL,           NULL,           NULL,
16299 /* 48 */        NULL,           NULL,           NULL,           NULL,
16300 /* 4C */        NULL,           NULL,           NULL,           NULL,
16301 /* 50 */        NULL,           NULL,           NULL,           NULL,
16302 /* 54 */        NULL,           NULL,           NULL,           NULL,
16303 /* 58 */        NULL,           NULL,           NULL,           NULL,
16304 /* 5C */        NULL,           NULL,           NULL,           NULL,
16305 /* 60 */        NULL,           NULL,           NULL,           NULL,
16306 /* 64 */        NULL,           NULL,           NULL,           NULL,
16307 /* 68 */        NULL,           NULL,           NULL,           NULL,
16308 /* 6C */        NULL,           NULL,           NULL,           NULL,
16309 /* 70 */        NULL,           NULL,           NULL,           NULL,
16310 /* 74 */        NULL,           NULL,           NULL,           NULL,
16311 /* 78 */        NULL,           NULL,           NULL,           NULL,
16312 /* 7C */        NULL,           NULL,           NULL,           NULL,
16313 /* 80 */        NULL,           NULL,           NULL,           NULL,
16314 /* 84 */        NULL,           NULL,           NULL,           NULL,
16315 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16316 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16317 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16318 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16319 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16320 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16321 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16322 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16323 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16324 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16325 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16326 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16327 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16328 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16329 /* C0 */        NULL,           NULL,           NULL,           NULL,
16330 /* C4 */        NULL,           NULL,           NULL,           NULL,
16331 /* C8 */        NULL,           NULL,           NULL,           NULL,
16332 /* CC */        NULL,           NULL,           NULL,           NULL,
16333 /* D0 */        NULL,           NULL,           NULL,           NULL,
16334 /* D4 */        NULL,           NULL,           NULL,           NULL,
16335 /* D8 */        NULL,           NULL,           NULL,           NULL,
16336 /* DC */        NULL,           NULL,           NULL,           NULL,
16337 /* E0 */        NULL,           NULL,           NULL,           NULL,
16338 /* E4 */        NULL,           NULL,           NULL,           NULL,
16339 /* E8 */        NULL,           NULL,           NULL,           NULL,
16340 /* EC */        NULL,           NULL,           NULL,           NULL,
16341 /* F0 */        NULL,           NULL,           NULL,           NULL,
16342 /* F4 */        NULL,           NULL,           NULL,           NULL,
16343 /* F8 */        NULL,           NULL,           NULL,           NULL,
16344 /* FC */        NULL,           NULL,           NULL,           NULL,
16345 };
16346
16347 static void
16348 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16349 {
16350   const char *mnemonic;
16351
16352   FETCH_DATA (the_info, codep + 1);
16353   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16354      place where an 8-bit immediate would normally go.  ie. the last
16355      byte of the instruction.  */
16356   obufp = mnemonicendp;
16357   mnemonic = Suffix3DNow[*codep++ & 0xff];
16358   if (mnemonic)
16359     oappend (mnemonic);
16360   else
16361     {
16362       /* Since a variable sized modrm/sib chunk is between the start
16363          of the opcode (0x0f0f) and the opcode suffix, we need to do
16364          all the modrm processing first, and don't know until now that
16365          we have a bad opcode.  This necessitates some cleaning up.  */
16366       op_out[0][0] = '\0';
16367       op_out[1][0] = '\0';
16368       BadOp ();
16369     }
16370   mnemonicendp = obufp;
16371 }
16372
16373 static struct op simd_cmp_op[] =
16374 {
16375   { STRING_COMMA_LEN ("eq") },
16376   { STRING_COMMA_LEN ("lt") },
16377   { STRING_COMMA_LEN ("le") },
16378   { STRING_COMMA_LEN ("unord") },
16379   { STRING_COMMA_LEN ("neq") },
16380   { STRING_COMMA_LEN ("nlt") },
16381   { STRING_COMMA_LEN ("nle") },
16382   { STRING_COMMA_LEN ("ord") }
16383 };
16384
16385 static void
16386 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16387 {
16388   unsigned int cmp_type;
16389
16390   FETCH_DATA (the_info, codep + 1);
16391   cmp_type = *codep++ & 0xff;
16392   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16393     {
16394       char suffix [3];
16395       char *p = mnemonicendp - 2;
16396       suffix[0] = p[0];
16397       suffix[1] = p[1];
16398       suffix[2] = '\0';
16399       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16400       mnemonicendp += simd_cmp_op[cmp_type].len;
16401     }
16402   else
16403     {
16404       /* We have a reserved extension byte.  Output it directly.  */
16405       scratchbuf[0] = '$';
16406       print_operand_value (scratchbuf + 1, 1, cmp_type);
16407       oappend_maybe_intel (scratchbuf);
16408       scratchbuf[0] = '\0';
16409     }
16410 }
16411
16412 static void
16413 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16414           int sizeflag ATTRIBUTE_UNUSED)
16415 {
16416   /* mwait %eax,%ecx  */
16417   if (!intel_syntax)
16418     {
16419       const char **names = (address_mode == mode_64bit
16420                             ? names64 : names32);
16421       strcpy (op_out[0], names[0]);
16422       strcpy (op_out[1], names[1]);
16423       two_source_ops = 1;
16424     }
16425   /* Skip mod/rm byte.  */
16426   MODRM_CHECK;
16427   codep++;
16428 }
16429
16430 static void
16431 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16432             int sizeflag ATTRIBUTE_UNUSED)
16433 {
16434   /* monitor %eax,%ecx,%edx"  */
16435   if (!intel_syntax)
16436     {
16437       const char **op1_names;
16438       const char **names = (address_mode == mode_64bit
16439                             ? names64 : names32);
16440
16441       if (!(prefixes & PREFIX_ADDR))
16442         op1_names = (address_mode == mode_16bit
16443                      ? names16 : names);
16444       else
16445         {
16446           /* Remove "addr16/addr32".  */
16447           all_prefixes[last_addr_prefix] = 0;
16448           op1_names = (address_mode != mode_32bit
16449                        ? names32 : names16);
16450           used_prefixes |= PREFIX_ADDR;
16451         }
16452       strcpy (op_out[0], op1_names[0]);
16453       strcpy (op_out[1], names[1]);
16454       strcpy (op_out[2], names[2]);
16455       two_source_ops = 1;
16456     }
16457   /* Skip mod/rm byte.  */
16458   MODRM_CHECK;
16459   codep++;
16460 }
16461
16462 static void
16463 BadOp (void)
16464 {
16465   /* Throw away prefixes and 1st. opcode byte.  */
16466   codep = insn_codep + 1;
16467   oappend ("(bad)");
16468 }
16469
16470 static void
16471 REP_Fixup (int bytemode, int sizeflag)
16472 {
16473   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16474      lods and stos.  */
16475   if (prefixes & PREFIX_REPZ)
16476     all_prefixes[last_repz_prefix] = REP_PREFIX;
16477
16478   switch (bytemode)
16479     {
16480     case al_reg:
16481     case eAX_reg:
16482     case indir_dx_reg:
16483       OP_IMREG (bytemode, sizeflag);
16484       break;
16485     case eDI_reg:
16486       OP_ESreg (bytemode, sizeflag);
16487       break;
16488     case eSI_reg:
16489       OP_DSreg (bytemode, sizeflag);
16490       break;
16491     default:
16492       abort ();
16493       break;
16494     }
16495 }
16496
16497 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16498    "bnd".  */
16499
16500 static void
16501 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16502 {
16503   if (prefixes & PREFIX_REPNZ)
16504     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16505 }
16506
16507 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16508    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16509  */
16510
16511 static void
16512 HLE_Fixup1 (int bytemode, int sizeflag)
16513 {
16514   if (modrm.mod != 3
16515       && (prefixes & PREFIX_LOCK) != 0)
16516     {
16517       if (prefixes & PREFIX_REPZ)
16518         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16519       if (prefixes & PREFIX_REPNZ)
16520         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16521     }
16522
16523   OP_E (bytemode, sizeflag);
16524 }
16525
16526 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16527    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16528  */
16529
16530 static void
16531 HLE_Fixup2 (int bytemode, int sizeflag)
16532 {
16533   if (modrm.mod != 3)
16534     {
16535       if (prefixes & PREFIX_REPZ)
16536         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16537       if (prefixes & PREFIX_REPNZ)
16538         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16539     }
16540
16541   OP_E (bytemode, sizeflag);
16542 }
16543
16544 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16545    "xrelease" for memory operand.  No check for LOCK prefix.   */
16546
16547 static void
16548 HLE_Fixup3 (int bytemode, int sizeflag)
16549 {
16550   if (modrm.mod != 3
16551       && last_repz_prefix > last_repnz_prefix
16552       && (prefixes & PREFIX_REPZ) != 0)
16553     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16554
16555   OP_E (bytemode, sizeflag);
16556 }
16557
16558 static void
16559 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16560 {
16561   USED_REX (REX_W);
16562   if (rex & REX_W)
16563     {
16564       /* Change cmpxchg8b to cmpxchg16b.  */
16565       char *p = mnemonicendp - 2;
16566       mnemonicendp = stpcpy (p, "16b");
16567       bytemode = o_mode;
16568     }
16569   else if ((prefixes & PREFIX_LOCK) != 0)
16570     {
16571       if (prefixes & PREFIX_REPZ)
16572         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16573       if (prefixes & PREFIX_REPNZ)
16574         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16575     }
16576
16577   OP_M (bytemode, sizeflag);
16578 }
16579
16580 static void
16581 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16582 {
16583   const char **names;
16584
16585   if (need_vex)
16586     {
16587       switch (vex.length)
16588         {
16589         case 128:
16590           names = names_xmm;
16591           break;
16592         case 256:
16593           names = names_ymm;
16594           break;
16595         default:
16596           abort ();
16597         }
16598     }
16599   else
16600     names = names_xmm;
16601   oappend (names[reg]);
16602 }
16603
16604 static void
16605 CRC32_Fixup (int bytemode, int sizeflag)
16606 {
16607   /* Add proper suffix to "crc32".  */
16608   char *p = mnemonicendp;
16609
16610   switch (bytemode)
16611     {
16612     case b_mode:
16613       if (intel_syntax)
16614         goto skip;
16615
16616       *p++ = 'b';
16617       break;
16618     case v_mode:
16619       if (intel_syntax)
16620         goto skip;
16621
16622       USED_REX (REX_W);
16623       if (rex & REX_W)
16624         *p++ = 'q';
16625       else
16626         {
16627           if (sizeflag & DFLAG)
16628             *p++ = 'l';
16629           else
16630             *p++ = 'w';
16631           used_prefixes |= (prefixes & PREFIX_DATA);
16632         }
16633       break;
16634     default:
16635       oappend (INTERNAL_DISASSEMBLER_ERROR);
16636       break;
16637     }
16638   mnemonicendp = p;
16639   *p = '\0';
16640
16641 skip:
16642   if (modrm.mod == 3)
16643     {
16644       int add;
16645
16646       /* Skip mod/rm byte.  */
16647       MODRM_CHECK;
16648       codep++;
16649
16650       USED_REX (REX_B);
16651       add = (rex & REX_B) ? 8 : 0;
16652       if (bytemode == b_mode)
16653         {
16654           USED_REX (0);
16655           if (rex)
16656             oappend (names8rex[modrm.rm + add]);
16657           else
16658             oappend (names8[modrm.rm + add]);
16659         }
16660       else
16661         {
16662           USED_REX (REX_W);
16663           if (rex & REX_W)
16664             oappend (names64[modrm.rm + add]);
16665           else if ((prefixes & PREFIX_DATA))
16666             oappend (names16[modrm.rm + add]);
16667           else
16668             oappend (names32[modrm.rm + add]);
16669         }
16670     }
16671   else
16672     OP_E (bytemode, sizeflag);
16673 }
16674
16675 static void
16676 FXSAVE_Fixup (int bytemode, int sizeflag)
16677 {
16678   /* Add proper suffix to "fxsave" and "fxrstor".  */
16679   USED_REX (REX_W);
16680   if (rex & REX_W)
16681     {
16682       char *p = mnemonicendp;
16683       *p++ = '6';
16684       *p++ = '4';
16685       *p = '\0';
16686       mnemonicendp = p;
16687     }
16688   OP_M (bytemode, sizeflag);
16689 }
16690
16691 /* Display the destination register operand for instructions with
16692    VEX. */
16693
16694 static void
16695 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16696 {
16697   int reg;
16698   const char **names;
16699
16700   if (!need_vex)
16701     abort ();
16702
16703   if (!need_vex_reg)
16704     return;
16705
16706   reg = vex.register_specifier;
16707   if (vex.evex)
16708     {
16709       if (!vex.v)
16710         reg += 16;
16711     }
16712
16713   if (bytemode == vex_scalar_mode)
16714     {
16715       oappend (names_xmm[reg]);
16716       return;
16717     }
16718
16719   switch (vex.length)
16720     {
16721     case 128:
16722       switch (bytemode)
16723         {
16724         case vex_mode:
16725         case vex128_mode:
16726         case vex_vsib_q_w_dq_mode:
16727         case vex_vsib_q_w_d_mode:
16728           names = names_xmm;
16729           break;
16730         case dq_mode:
16731           if (vex.w)
16732             names = names64;
16733           else
16734             names = names32;
16735           break;
16736         case mask_bd_mode:
16737         case mask_mode:
16738           names = names_mask;
16739           break;
16740         default:
16741           abort ();
16742           return;
16743         }
16744       break;
16745     case 256:
16746       switch (bytemode)
16747         {
16748         case vex_mode:
16749         case vex256_mode:
16750           names = names_ymm;
16751           break;
16752         case vex_vsib_q_w_dq_mode:
16753         case vex_vsib_q_w_d_mode:
16754           names = vex.w ? names_ymm : names_xmm;
16755           break;
16756         case mask_bd_mode:
16757         case mask_mode:
16758           names = names_mask;
16759           break;
16760         default:
16761           abort ();
16762           return;
16763         }
16764       break;
16765     case 512:
16766       names = names_zmm;
16767       break;
16768     default:
16769       abort ();
16770       break;
16771     }
16772   oappend (names[reg]);
16773 }
16774
16775 /* Get the VEX immediate byte without moving codep.  */
16776
16777 static unsigned char
16778 get_vex_imm8 (int sizeflag, int opnum)
16779 {
16780   int bytes_before_imm = 0;
16781
16782   if (modrm.mod != 3)
16783     {
16784       /* There are SIB/displacement bytes.  */
16785       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16786         {
16787           /* 32/64 bit address mode */
16788           int base = modrm.rm;
16789
16790           /* Check SIB byte.  */
16791           if (base == 4)
16792             {
16793               FETCH_DATA (the_info, codep + 1);
16794               base = *codep & 7;
16795               /* When decoding the third source, don't increase
16796                  bytes_before_imm as this has already been incremented
16797                  by one in OP_E_memory while decoding the second
16798                  source operand.  */
16799               if (opnum == 0)
16800                 bytes_before_imm++;
16801             }
16802
16803           /* Don't increase bytes_before_imm when decoding the third source,
16804              it has already been incremented by OP_E_memory while decoding
16805              the second source operand.  */
16806           if (opnum == 0)
16807             {
16808               switch (modrm.mod)
16809                 {
16810                   case 0:
16811                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16812                        SIB == 5, there is a 4 byte displacement.  */
16813                     if (base != 5)
16814                       /* No displacement. */
16815                       break;
16816                   case 2:
16817                     /* 4 byte displacement.  */
16818                     bytes_before_imm += 4;
16819                     break;
16820                   case 1:
16821                     /* 1 byte displacement.  */
16822                     bytes_before_imm++;
16823                     break;
16824                 }
16825             }
16826         }
16827       else
16828         {
16829           /* 16 bit address mode */
16830           /* Don't increase bytes_before_imm when decoding the third source,
16831              it has already been incremented by OP_E_memory while decoding
16832              the second source operand.  */
16833           if (opnum == 0)
16834             {
16835               switch (modrm.mod)
16836                 {
16837                 case 0:
16838                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16839                   if (modrm.rm != 6)
16840                     /* No displacement. */
16841                     break;
16842                 case 2:
16843                   /* 2 byte displacement.  */
16844                   bytes_before_imm += 2;
16845                   break;
16846                 case 1:
16847                   /* 1 byte displacement: when decoding the third source,
16848                      don't increase bytes_before_imm as this has already
16849                      been incremented by one in OP_E_memory while decoding
16850                      the second source operand.  */
16851                   if (opnum == 0)
16852                     bytes_before_imm++;
16853
16854                   break;
16855                 }
16856             }
16857         }
16858     }
16859
16860   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16861   return codep [bytes_before_imm];
16862 }
16863
16864 static void
16865 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16866 {
16867   const char **names;
16868
16869   if (reg == -1 && modrm.mod != 3)
16870     {
16871       OP_E_memory (bytemode, sizeflag);
16872       return;
16873     }
16874   else
16875     {
16876       if (reg == -1)
16877         {
16878           reg = modrm.rm;
16879           USED_REX (REX_B);
16880           if (rex & REX_B)
16881             reg += 8;
16882         }
16883       else if (reg > 7 && address_mode != mode_64bit)
16884         BadOp ();
16885     }
16886
16887   switch (vex.length)
16888     {
16889     case 128:
16890       names = names_xmm;
16891       break;
16892     case 256:
16893       names = names_ymm;
16894       break;
16895     default:
16896       abort ();
16897     }
16898   oappend (names[reg]);
16899 }
16900
16901 static void
16902 OP_EX_VexImmW (int bytemode, int sizeflag)
16903 {
16904   int reg = -1;
16905   static unsigned char vex_imm8;
16906
16907   if (vex_w_done == 0)
16908     {
16909       vex_w_done = 1;
16910
16911       /* Skip mod/rm byte.  */
16912       MODRM_CHECK;
16913       codep++;
16914
16915       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16916
16917       if (vex.w)
16918           reg = vex_imm8 >> 4;
16919
16920       OP_EX_VexReg (bytemode, sizeflag, reg);
16921     }
16922   else if (vex_w_done == 1)
16923     {
16924       vex_w_done = 2;
16925
16926       if (!vex.w)
16927           reg = vex_imm8 >> 4;
16928
16929       OP_EX_VexReg (bytemode, sizeflag, reg);
16930     }
16931   else
16932     {
16933       /* Output the imm8 directly.  */
16934       scratchbuf[0] = '$';
16935       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16936       oappend_maybe_intel (scratchbuf);
16937       scratchbuf[0] = '\0';
16938       codep++;
16939     }
16940 }
16941
16942 static void
16943 OP_Vex_2src (int bytemode, int sizeflag)
16944 {
16945   if (modrm.mod == 3)
16946     {
16947       int reg = modrm.rm;
16948       USED_REX (REX_B);
16949       if (rex & REX_B)
16950         reg += 8;
16951       oappend (names_xmm[reg]);
16952     }
16953   else
16954     {
16955       if (intel_syntax
16956           && (bytemode == v_mode || bytemode == v_swap_mode))
16957         {
16958           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16959           used_prefixes |= (prefixes & PREFIX_DATA);
16960         }
16961       OP_E (bytemode, sizeflag);
16962     }
16963 }
16964
16965 static void
16966 OP_Vex_2src_1 (int bytemode, int sizeflag)
16967 {
16968   if (modrm.mod == 3)
16969     {
16970       /* Skip mod/rm byte.   */
16971       MODRM_CHECK;
16972       codep++;
16973     }
16974
16975   if (vex.w)
16976     oappend (names_xmm[vex.register_specifier]);
16977   else
16978     OP_Vex_2src (bytemode, sizeflag);
16979 }
16980
16981 static void
16982 OP_Vex_2src_2 (int bytemode, int sizeflag)
16983 {
16984   if (vex.w)
16985     OP_Vex_2src (bytemode, sizeflag);
16986   else
16987     oappend (names_xmm[vex.register_specifier]);
16988 }
16989
16990 static void
16991 OP_EX_VexW (int bytemode, int sizeflag)
16992 {
16993   int reg = -1;
16994
16995   if (!vex_w_done)
16996     {
16997       vex_w_done = 1;
16998
16999       /* Skip mod/rm byte.  */
17000       MODRM_CHECK;
17001       codep++;
17002
17003       if (vex.w)
17004         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17005     }
17006   else
17007     {
17008       if (!vex.w)
17009         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17010     }
17011
17012   OP_EX_VexReg (bytemode, sizeflag, reg);
17013 }
17014
17015 static void
17016 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17017              int sizeflag ATTRIBUTE_UNUSED)
17018 {
17019   /* Skip the immediate byte and check for invalid bits.  */
17020   FETCH_DATA (the_info, codep + 1);
17021   if (*codep++ & 0xf)
17022     BadOp ();
17023 }
17024
17025 static void
17026 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17027 {
17028   int reg;
17029   const char **names;
17030
17031   FETCH_DATA (the_info, codep + 1);
17032   reg = *codep++;
17033
17034   if (bytemode != x_mode)
17035     abort ();
17036
17037   if (reg & 0xf)
17038       BadOp ();
17039
17040   reg >>= 4;
17041   if (reg > 7 && address_mode != mode_64bit)
17042     BadOp ();
17043
17044   switch (vex.length)
17045     {
17046     case 128:
17047       names = names_xmm;
17048       break;
17049     case 256:
17050       names = names_ymm;
17051       break;
17052     default:
17053       abort ();
17054     }
17055   oappend (names[reg]);
17056 }
17057
17058 static void
17059 OP_XMM_VexW (int bytemode, int sizeflag)
17060 {
17061   /* Turn off the REX.W bit since it is used for swapping operands
17062      now.  */
17063   rex &= ~REX_W;
17064   OP_XMM (bytemode, sizeflag);
17065 }
17066
17067 static void
17068 OP_EX_Vex (int bytemode, int sizeflag)
17069 {
17070   if (modrm.mod != 3)
17071     {
17072       if (vex.register_specifier != 0)
17073         BadOp ();
17074       need_vex_reg = 0;
17075     }
17076   OP_EX (bytemode, sizeflag);
17077 }
17078
17079 static void
17080 OP_XMM_Vex (int bytemode, int sizeflag)
17081 {
17082   if (modrm.mod != 3)
17083     {
17084       if (vex.register_specifier != 0)
17085         BadOp ();
17086       need_vex_reg = 0;
17087     }
17088   OP_XMM (bytemode, sizeflag);
17089 }
17090
17091 static void
17092 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17093 {
17094   switch (vex.length)
17095     {
17096     case 128:
17097       mnemonicendp = stpcpy (obuf, "vzeroupper");
17098       break;
17099     case 256:
17100       mnemonicendp = stpcpy (obuf, "vzeroall");
17101       break;
17102     default:
17103       abort ();
17104     }
17105 }
17106
17107 static struct op vex_cmp_op[] =
17108 {
17109   { STRING_COMMA_LEN ("eq") },
17110   { STRING_COMMA_LEN ("lt") },
17111   { STRING_COMMA_LEN ("le") },
17112   { STRING_COMMA_LEN ("unord") },
17113   { STRING_COMMA_LEN ("neq") },
17114   { STRING_COMMA_LEN ("nlt") },
17115   { STRING_COMMA_LEN ("nle") },
17116   { STRING_COMMA_LEN ("ord") },
17117   { STRING_COMMA_LEN ("eq_uq") },
17118   { STRING_COMMA_LEN ("nge") },
17119   { STRING_COMMA_LEN ("ngt") },
17120   { STRING_COMMA_LEN ("false") },
17121   { STRING_COMMA_LEN ("neq_oq") },
17122   { STRING_COMMA_LEN ("ge") },
17123   { STRING_COMMA_LEN ("gt") },
17124   { STRING_COMMA_LEN ("true") },
17125   { STRING_COMMA_LEN ("eq_os") },
17126   { STRING_COMMA_LEN ("lt_oq") },
17127   { STRING_COMMA_LEN ("le_oq") },
17128   { STRING_COMMA_LEN ("unord_s") },
17129   { STRING_COMMA_LEN ("neq_us") },
17130   { STRING_COMMA_LEN ("nlt_uq") },
17131   { STRING_COMMA_LEN ("nle_uq") },
17132   { STRING_COMMA_LEN ("ord_s") },
17133   { STRING_COMMA_LEN ("eq_us") },
17134   { STRING_COMMA_LEN ("nge_uq") },
17135   { STRING_COMMA_LEN ("ngt_uq") },
17136   { STRING_COMMA_LEN ("false_os") },
17137   { STRING_COMMA_LEN ("neq_os") },
17138   { STRING_COMMA_LEN ("ge_oq") },
17139   { STRING_COMMA_LEN ("gt_oq") },
17140   { STRING_COMMA_LEN ("true_us") },
17141 };
17142
17143 static void
17144 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17145 {
17146   unsigned int cmp_type;
17147
17148   FETCH_DATA (the_info, codep + 1);
17149   cmp_type = *codep++ & 0xff;
17150   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17151     {
17152       char suffix [3];
17153       char *p = mnemonicendp - 2;
17154       suffix[0] = p[0];
17155       suffix[1] = p[1];
17156       suffix[2] = '\0';
17157       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17158       mnemonicendp += vex_cmp_op[cmp_type].len;
17159     }
17160   else
17161     {
17162       /* We have a reserved extension byte.  Output it directly.  */
17163       scratchbuf[0] = '$';
17164       print_operand_value (scratchbuf + 1, 1, cmp_type);
17165       oappend_maybe_intel (scratchbuf);
17166       scratchbuf[0] = '\0';
17167     }
17168 }
17169
17170 static void
17171 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17172              int sizeflag ATTRIBUTE_UNUSED)
17173 {
17174   unsigned int cmp_type;
17175
17176   if (!vex.evex)
17177     abort ();
17178
17179   FETCH_DATA (the_info, codep + 1);
17180   cmp_type = *codep++ & 0xff;
17181   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17182      If it's the case, print suffix, otherwise - print the immediate.  */
17183   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17184       && cmp_type != 3
17185       && cmp_type != 7)
17186     {
17187       char suffix [3];
17188       char *p = mnemonicendp - 2;
17189
17190       /* vpcmp* can have both one- and two-lettered suffix.  */
17191       if (p[0] == 'p')
17192         {
17193           p++;
17194           suffix[0] = p[0];
17195           suffix[1] = '\0';
17196         }
17197       else
17198         {
17199           suffix[0] = p[0];
17200           suffix[1] = p[1];
17201           suffix[2] = '\0';
17202         }
17203
17204       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17205       mnemonicendp += simd_cmp_op[cmp_type].len;
17206     }
17207   else
17208     {
17209       /* We have a reserved extension byte.  Output it directly.  */
17210       scratchbuf[0] = '$';
17211       print_operand_value (scratchbuf + 1, 1, cmp_type);
17212       oappend_maybe_intel (scratchbuf);
17213       scratchbuf[0] = '\0';
17214     }
17215 }
17216
17217 static const struct op pclmul_op[] =
17218 {
17219   { STRING_COMMA_LEN ("lql") },
17220   { STRING_COMMA_LEN ("hql") },
17221   { STRING_COMMA_LEN ("lqh") },
17222   { STRING_COMMA_LEN ("hqh") }
17223 };
17224
17225 static void
17226 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17227               int sizeflag ATTRIBUTE_UNUSED)
17228 {
17229   unsigned int pclmul_type;
17230
17231   FETCH_DATA (the_info, codep + 1);
17232   pclmul_type = *codep++ & 0xff;
17233   switch (pclmul_type)
17234     {
17235     case 0x10:
17236       pclmul_type = 2;
17237       break;
17238     case 0x11:
17239       pclmul_type = 3;
17240       break;
17241     default:
17242       break;
17243     }
17244   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17245     {
17246       char suffix [4];
17247       char *p = mnemonicendp - 3;
17248       suffix[0] = p[0];
17249       suffix[1] = p[1];
17250       suffix[2] = p[2];
17251       suffix[3] = '\0';
17252       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17253       mnemonicendp += pclmul_op[pclmul_type].len;
17254     }
17255   else
17256     {
17257       /* We have a reserved extension byte.  Output it directly.  */
17258       scratchbuf[0] = '$';
17259       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17260       oappend_maybe_intel (scratchbuf);
17261       scratchbuf[0] = '\0';
17262     }
17263 }
17264
17265 static void
17266 MOVBE_Fixup (int bytemode, int sizeflag)
17267 {
17268   /* Add proper suffix to "movbe".  */
17269   char *p = mnemonicendp;
17270
17271   switch (bytemode)
17272     {
17273     case v_mode:
17274       if (intel_syntax)
17275         goto skip;
17276
17277       USED_REX (REX_W);
17278       if (sizeflag & SUFFIX_ALWAYS)
17279         {
17280           if (rex & REX_W)
17281             *p++ = 'q';
17282           else
17283             {
17284               if (sizeflag & DFLAG)
17285                 *p++ = 'l';
17286               else
17287                 *p++ = 'w';
17288               used_prefixes |= (prefixes & PREFIX_DATA);
17289             }
17290         }
17291       break;
17292     default:
17293       oappend (INTERNAL_DISASSEMBLER_ERROR);
17294       break;
17295     }
17296   mnemonicendp = p;
17297   *p = '\0';
17298
17299 skip:
17300   OP_M (bytemode, sizeflag);
17301 }
17302
17303 static void
17304 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17305 {
17306   int reg;
17307   const char **names;
17308
17309   /* Skip mod/rm byte.  */
17310   MODRM_CHECK;
17311   codep++;
17312
17313   if (vex.w)
17314     names = names64;
17315   else
17316     names = names32;
17317
17318   reg = modrm.rm;
17319   USED_REX (REX_B);
17320   if (rex & REX_B)
17321     reg += 8;
17322
17323   oappend (names[reg]);
17324 }
17325
17326 static void
17327 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17328 {
17329   const char **names;
17330
17331   if (vex.w)
17332     names = names64;
17333   else
17334     names = names32;
17335
17336   oappend (names[vex.register_specifier]);
17337 }
17338
17339 static void
17340 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17341 {
17342   if (!vex.evex
17343       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17344     abort ();
17345
17346   USED_REX (REX_R);
17347   if ((rex & REX_R) != 0 || !vex.r)
17348     {
17349       BadOp ();
17350       return;
17351     }
17352
17353   oappend (names_mask [modrm.reg]);
17354 }
17355
17356 static void
17357 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17358 {
17359   if (!vex.evex
17360       || (bytemode != evex_rounding_mode
17361           && bytemode != evex_sae_mode))
17362     abort ();
17363   if (modrm.mod == 3 && vex.b)
17364     switch (bytemode)
17365       {
17366       case evex_rounding_mode:
17367         oappend (names_rounding[vex.ll]);
17368         break;
17369       case evex_sae_mode:
17370         oappend ("{sae}");
17371         break;
17372       default:
17373         break;
17374       }
17375 }